| blob | 69f44aa60860804fd14308f0e8e48eebc907ab6f |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
70 #ifndef CHECK_STACK_LIMIT
71 #define CHECK_STACK_LIMIT (-1)
72 #endif
74 /* Return index of given mode in mult and division cost tables. */
75 #define MODE_INDEX(mode) \
76 ((mode) == QImode ? 0 \
77 : (mode) == HImode ? 1 \
78 : (mode) == SImode ? 2 \
79 : (mode) == DImode ? 3 \
80 : 4)
82 /* Processor costs (relative to an add) */
83 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
84 #define COSTS_N_BYTES(N) ((N) * 2)
86 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
88 const
111 in QImode, HImode and SImode.
112 Relative to reg-reg move (2). */
116 in SFmode, DFmode and XFmode */
118 in SFmode, DFmode and XFmode */
121 in SImode and DImode */
123 in SImode and DImode */
126 in SImode, DImode and TImode */
128 in SImode, DImode and TImode */
156 };
158 /* Processor costs (relative to an add) */
159 static const
182 in QImode, HImode and SImode.
183 Relative to reg-reg move (2). */
187 in SFmode, DFmode and XFmode */
189 in SFmode, DFmode and XFmode */
192 in SImode and DImode */
194 in SImode and DImode */
197 in SImode, DImode and TImode */
199 in SImode, DImode and TImode */
213 DUMMY_STRINGOP_ALGS},
215 DUMMY_STRINGOP_ALGS},
227 };
229 static const
252 in QImode, HImode and SImode.
253 Relative to reg-reg move (2). */
257 in SFmode, DFmode and XFmode */
259 in SFmode, DFmode and XFmode */
262 in SImode and DImode */
264 in SImode and DImode */
267 in SImode, DImode and TImode */
269 in SImode, DImode and TImode */
272 shared for code and data, so 4kB is
273 not really precise. */
285 DUMMY_STRINGOP_ALGS},
287 DUMMY_STRINGOP_ALGS},
299 };
301 static const
324 in QImode, HImode and SImode.
325 Relative to reg-reg move (2). */
329 in SFmode, DFmode and XFmode */
331 in SFmode, DFmode and XFmode */
334 in SImode and DImode */
336 in SImode and DImode */
339 in SImode, DImode and TImode */
341 in SImode, DImode and TImode */
355 DUMMY_STRINGOP_ALGS},
357 DUMMY_STRINGOP_ALGS},
369 };
371 static const
394 in QImode, HImode and SImode.
395 Relative to reg-reg move (2). */
399 in SFmode, DFmode and XFmode */
401 in SFmode, DFmode and XFmode */
404 in SImode and DImode */
406 in SImode and DImode */
409 in SImode, DImode and TImode */
411 in SImode, DImode and TImode */
424 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
425 (we ensure the alignment). For small blocks inline loop is still a
426 noticeable win, for bigger blocks either rep movsl or rep movsb is
427 way to go. Rep movsb has apparently more expensive startup time in CPU,
428 but after 4K the difference is down in the noise. */
432 DUMMY_STRINGOP_ALGS},
436 DUMMY_STRINGOP_ALGS},
448 };
450 static const
473 in QImode, HImode and SImode.
474 Relative to reg-reg move (2). */
478 in SFmode, DFmode and XFmode */
480 in SFmode, DFmode and XFmode */
484 in SImode and DImode */
486 in SImode and DImode */
489 in SImode, DImode and TImode */
491 in SImode, DImode and TImode */
505 DUMMY_STRINGOP_ALGS},
507 DUMMY_STRINGOP_ALGS},
519 };
521 static const
544 in QImode, HImode and SImode.
545 Relative to reg-reg move (2). */
549 in SFmode, DFmode and XFmode */
551 in SFmode, DFmode and XFmode */
554 in SImode and DImode */
556 in SImode and DImode */
559 in SImode, DImode and TImode */
561 in SImode, DImode and TImode */
565 have integrated l2 cache, but
566 optimizing for k6 is not important
567 enough to worry about that. */
578 DUMMY_STRINGOP_ALGS},
580 DUMMY_STRINGOP_ALGS},
592 };
594 static const
617 in QImode, HImode and SImode.
618 Relative to reg-reg move (2). */
622 in SFmode, DFmode and XFmode */
624 in SFmode, DFmode and XFmode */
627 in SImode and DImode */
629 in SImode and DImode */
632 in SImode, DImode and TImode */
634 in SImode, DImode and TImode */
647 /* For some reason, Athlon deals better with REP prefix (relative to loops)
648 compared to K8. Alignment becomes important after 8 bytes for memcpy and
649 128 bytes for memset. */
651 DUMMY_STRINGOP_ALGS},
653 DUMMY_STRINGOP_ALGS},
665 };
667 static const
690 in QImode, HImode and SImode.
691 Relative to reg-reg move (2). */
695 in SFmode, DFmode and XFmode */
697 in SFmode, DFmode and XFmode */
700 in SImode and DImode */
702 in SImode and DImode */
705 in SImode, DImode and TImode */
707 in SImode, DImode and TImode */
712 /* New AMD processors never drop prefetches; if they cannot be performed
713 immediately, they are queued. We set number of simultaneous prefetches
714 to a large constant to reflect this (it probably is not a good idea not
715 to limit number of prefetches at all, as their execution also takes some
716 time). */
725 /* K8 has optimized REP instruction for medium sized blocks, but for very
726 small blocks it is better to use loop. For large blocks, libcall can
727 do nontemporary accesses and beat inline considerably. */
747 };
771 in QImode, HImode and SImode.
772 Relative to reg-reg move (2). */
776 in SFmode, DFmode and XFmode */
778 in SFmode, DFmode and XFmode */
781 in SImode and DImode */
783 in SImode and DImode */
786 in SImode, DImode and TImode */
788 in SImode, DImode and TImode */
790 /* On K8:
791 MOVD reg64, xmmreg Double FSTORE 4
792 MOVD reg32, xmmreg Double FSTORE 4
793 On AMDFAM10:
794 MOVD reg64, xmmreg Double FADD 3
795 1/1 1/1
796 MOVD reg32, xmmreg Double FADD 3
797 1/1 1/1 */
801 /* New AMD processors never drop prefetches; if they cannot be performed
802 immediately, they are queued. We set number of simultaneous prefetches
803 to a large constant to reflect this (it probably is not a good idea not
804 to limit number of prefetches at all, as their execution also takes some
805 time). */
815 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
816 very small blocks it is better to use loop. For large blocks, libcall can
817 do nontemporary accesses and beat inline considerably. */
837 };
861 in QImode, HImode and SImode.
862 Relative to reg-reg move (2). */
866 in SFmode, DFmode and XFmode */
868 in SFmode, DFmode and XFmode */
871 in SImode and DImode */
873 in SImode and DImode */
876 in SImode, DImode and TImode */
878 in SImode, DImode and TImode */
880 /* On K8:
881 MOVD reg64, xmmreg Double FSTORE 4
882 MOVD reg32, xmmreg Double FSTORE 4
883 On AMDFAM10:
884 MOVD reg64, xmmreg Double FADD 3
885 1/1 1/1
886 MOVD reg32, xmmreg Double FADD 3
887 1/1 1/1 */
891 /* New AMD processors never drop prefetches; if they cannot be performed
892 immediately, they are queued. We set number of simultaneous prefetches
893 to a large constant to reflect this (it probably is not a good idea not
894 to limit number of prefetches at all, as their execution also takes some
895 time). */
905 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
906 very small blocks it is better to use loop. For large blocks, libcall
907 can do nontemporary accesses and beat inline considerably. */
927 };
951 in QImode, HImode and SImode.
952 Relative to reg-reg move (2). */
956 in SFmode, DFmode and XFmode */
958 in SFmode, DFmode and XFmode */
961 in SImode and DImode */
963 in SImode and DImode */
966 in SImode, DImode and TImode */
968 in SImode, DImode and TImode */
970 /* On K8:
971 MOVD reg64, xmmreg Double FSTORE 4
972 MOVD reg32, xmmreg Double FSTORE 4
973 On AMDFAM10:
974 MOVD reg64, xmmreg Double FADD 3
975 1/1 1/1
976 MOVD reg32, xmmreg Double FADD 3
977 1/1 1/1 */
981 /* New AMD processors never drop prefetches; if they cannot be performed
982 immediately, they are queued. We set number of simultaneous prefetches
983 to a large constant to reflect this (it probably is not a good idea not
984 to limit number of prefetches at all, as their execution also takes some
985 time). */
995 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
996 very small blocks it is better to use loop. For large blocks, libcall
997 can do nontemporary accesses and beat inline considerably. */
1017 };
1041 in QImode, HImode and SImode.
1042 Relative to reg-reg move (2). */
1046 in SFmode, DFmode and XFmode */
1048 in SFmode, DFmode and XFmode */
1051 in SImode and DImode */
1053 in SImode and DImode */
1056 in SImode, DImode and TImode */
1058 in SImode, DImode and TImode */
1063 /* New AMD processors never drop prefetches; if they cannot be performed
1064 immediately, they are queued. We set number of simultaneous prefetches
1065 to a large constant to reflect this (it probably is not a good idea not
1066 to limit number of prefetches at all, as their execution also takes some
1067 time). */
1077 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1078 very small blocks it is better to use loop. For large blocks, libcall
1079 can do nontemporary accesses and beat inline considerably. */
1099 };
1123 in QImode, HImode and SImode.
1124 Relative to reg-reg move (2). */
1128 in SFmode, DFmode and XFmode */
1130 in SFmode, DFmode and XFmode */
1133 in SImode and DImode */
1135 in SImode and DImode */
1138 in SImode, DImode and TImode */
1140 in SImode, DImode and TImode */
1142 /* On K8:
1143 MOVD reg64, xmmreg Double FSTORE 4
1144 MOVD reg32, xmmreg Double FSTORE 4
1145 On AMDFAM10:
1146 MOVD reg64, xmmreg Double FADD 3
1147 1/1 1/1
1148 MOVD reg32, xmmreg Double FADD 3
1149 1/1 1/1 */
1162 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1163 very small blocks it is better to use loop. For large blocks, libcall can
1164 do nontemporary accesses and beat inline considerably. */
1184 };
1208 in QImode, HImode and SImode.
1209 Relative to reg-reg move (2). */
1213 in SFmode, DFmode and XFmode */
1215 in SFmode, DFmode and XFmode */
1218 in SImode and DImode */
1220 in SImode and DImode */
1223 in SImode, DImode and TImode */
1225 in SImode, DImode and TImode */
1227 /* On K8:
1228 MOVD reg64, xmmreg Double FSTORE 4
1229 MOVD reg32, xmmreg Double FSTORE 4
1230 On AMDFAM10:
1231 MOVD reg64, xmmreg Double FADD 3
1232 1/1 1/1
1233 MOVD reg32, xmmreg Double FADD 3
1234 1/1 1/1 */
1266 };
1268 static const
1291 in QImode, HImode and SImode.
1292 Relative to reg-reg move (2). */
1296 in SFmode, DFmode and XFmode */
1298 in SFmode, DFmode and XFmode */
1301 in SImode and DImode */
1303 in SImode and DImode */
1306 in SImode, DImode and TImode */
1308 in SImode, DImode and TImode */
1322 DUMMY_STRINGOP_ALGS},
1325 DUMMY_STRINGOP_ALGS},
1337 };
1339 static const
1362 in QImode, HImode and SImode.
1363 Relative to reg-reg move (2). */
1367 in SFmode, DFmode and XFmode */
1369 in SFmode, DFmode and XFmode */
1372 in SImode and DImode */
1374 in SImode and DImode */
1377 in SImode, DImode and TImode */
1379 in SImode, DImode and TImode */
1410 };
1412 static const
1435 in QImode, HImode and SImode.
1436 Relative to reg-reg move (2). */
1440 in SFmode, DFmode and XFmode */
1442 in SFmode, DFmode and XFmode */
1445 in SImode and DImode */
1447 in SImode and DImode */
1450 in SImode, DImode and TImode */
1452 in SImode, DImode and TImode */
1483 };
1485 /* Generic64 should produce code tuned for Nocona and K8. */
1486 static const
1489 /* On all chips taken into consideration lea is 2 cycles and more. With
1490 this cost however our current implementation of synth_mult results in
1491 use of unnecessary temporary registers causing regression on several
1492 SPECfp benchmarks. */
1513 in QImode, HImode and SImode.
1514 Relative to reg-reg move (2). */
1518 in SFmode, DFmode and XFmode */
1520 in SFmode, DFmode and XFmode */
1523 in SImode and DImode */
1525 in SImode and DImode */
1528 in SImode, DImode and TImode */
1530 in SImode, DImode and TImode */
1536 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1537 value is increased to perhaps more appropriate value of 5. */
1562 };
1564 /* core_cost should produce code tuned for Core familly of CPUs. */
1565 static const
1568 /* On all chips taken into consideration lea is 2 cycles and more. With
1569 this cost however our current implementation of synth_mult results in
1570 use of unnecessary temporary registers causing regression on several
1571 SPECfp benchmarks. */
1592 in QImode, HImode and SImode.
1593 Relative to reg-reg move (2). */
1597 in SFmode, DFmode and XFmode */
1599 in SFmode, DFmode and XFmode */
1602 in SImode and DImode */
1604 in SImode and DImode */
1607 in SImode, DImode and TImode */
1609 in SImode, DImode and TImode */
1615 /* FIXME perhaps more appropriate value is 5. */
1643 };
1645 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1646 Athlon and K8. */
1647 static const
1670 in QImode, HImode and SImode.
1671 Relative to reg-reg move (2). */
1675 in SFmode, DFmode and XFmode */
1677 in SFmode, DFmode and XFmode */
1680 in SImode and DImode */
1682 in SImode and DImode */
1685 in SImode, DImode and TImode */
1687 in SImode, DImode and TImode */
1702 DUMMY_STRINGOP_ALGS},
1705 DUMMY_STRINGOP_ALGS},
1717 };
1719 /* Set by -mtune. */
1722 /* Set by -mtune or -Os. */
1725 /* Processor feature/optimization bitmasks. */
1726 #define m_386 (1<<PROCESSOR_I386)
1727 #define m_486 (1<<PROCESSOR_I486)
1728 #define m_PENT (1<<PROCESSOR_PENTIUM)
1729 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1730 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1731 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1732 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1733 #define m_CORE2 (1<<PROCESSOR_CORE2)
1734 #define m_COREI7 (1<<PROCESSOR_COREI7)
1735 #define m_CORE2I7 (m_CORE2 | m_COREI7)
1736 #define m_ATOM (1<<PROCESSOR_ATOM)
1738 #define m_GEODE (1<<PROCESSOR_GEODE)
1739 #define m_K6 (1<<PROCESSOR_K6)
1740 #define m_K6_GEODE (m_K6 | m_GEODE)
1741 #define m_K8 (1<<PROCESSOR_K8)
1742 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1743 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1744 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1745 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1746 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1747 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1748 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1749 #define m_BTVER (m_BTVER1 | m_BTVER2)
1750 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1751 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1752 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1754 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1755 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1757 /* Generic instruction choice should be common subset of supported CPUs
1758 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1759 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1761 /* Feature tests against the various tunings. */
1764 /* Feature tests against the various tunings used to create ix86_tune_features
1765 based on the processor mask. */
1767 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1768 negatively, so enabling for Generic64 seems like good code size
1769 tradeoff. We can't enable it for 32bit generic because it does not
1770 work well with PPro base chips. */
1773 /* X86_TUNE_PUSH_MEMORY */
1776 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1779 /* X86_TUNE_UNROLL_STRLEN */
1782 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1783 on simulation result. But after P4 was made, no performance benefit
1784 was observed with branch hints. It also increases the code size.
1785 As a result, icc never generates branch hints. */
1788 /* X86_TUNE_DOUBLE_WITH_ADD */
1791 /* X86_TUNE_USE_SAHF */
1792 m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC,
1794 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1795 partial dependencies. */
1798 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1799 register stalls on Generic32 compilation setting as well. However
1800 in current implementation the partial register stalls are not eliminated
1801 very well - they can be introduced via subregs synthesized by combine
1802 and can happen in caller/callee saving sequences. Because this option
1803 pays back little on PPro based chips and is in conflict with partial reg
1804 dependencies used by Athlon/P4 based chips, it is better to leave it off
1805 for generic32 for now. */
1806 m_PPRO,
1808 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1811 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
1812 * on 16-bit immediate moves into memory on Core2 and Corei7. */
1815 /* X86_TUNE_USE_HIMODE_FIOP */
1818 /* X86_TUNE_USE_SIMODE_FIOP */
1821 /* X86_TUNE_USE_MOV0 */
1822 m_K6,
1824 /* X86_TUNE_USE_CLTD */
1827 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1828 m_PENT4,
1830 /* X86_TUNE_SPLIT_LONG_MOVES */
1831 m_PPRO,
1833 /* X86_TUNE_READ_MODIFY_WRITE */
1836 /* X86_TUNE_READ_MODIFY */
1839 /* X86_TUNE_PROMOTE_QIMODE */
1842 /* X86_TUNE_FAST_PREFIX */
1845 /* X86_TUNE_SINGLE_STRINGOP */
1848 /* X86_TUNE_QIMODE_MATH */
1851 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1852 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1853 might be considered for Generic32 if our scheme for avoiding partial
1854 stalls was more effective. */
1857 /* X86_TUNE_PROMOTE_QI_REGS */
1860 /* X86_TUNE_PROMOTE_HI_REGS */
1861 m_PPRO,
1863 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1864 over esp addition. */
1867 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1868 over esp addition. */
1869 m_PENT,
1871 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1872 over esp subtraction. */
1875 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1876 over esp subtraction. */
1879 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1880 for DFmode copies */
1883 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1886 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1887 conflict here in between PPro/Pentium4 based chips that thread 128bit
1888 SSE registers as single units versus K8 based chips that divide SSE
1889 registers to two 64bit halves. This knob promotes all store destinations
1890 to be 128bit to allow register renaming on 128bit SSE units, but usually
1891 results in one extra microop on 64bit SSE units. Experimental results
1892 shows that disabling this option on P4 brings over 20% SPECfp regression,
1893 while enabling it on K8 brings roughly 2.4% regression that can be partly
1894 masked by careful scheduling of moves. */
1897 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1900 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1903 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1904 m_BDVER ,
1906 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1907 are resolved on SSE register parts instead of whole registers, so we may
1908 maintain just lower part of scalar values in proper format leaving the
1909 upper part undefined. */
1910 m_ATHLON_K8,
1912 /* X86_TUNE_SSE_TYPELESS_STORES */
1913 m_AMD_MULTIPLE,
1915 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1918 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1921 /* X86_TUNE_PROLOGUE_USING_MOVE */
1924 /* X86_TUNE_EPILOGUE_USING_MOVE */
1927 /* X86_TUNE_SHIFT1 */
1930 /* X86_TUNE_USE_FFREEP */
1931 m_AMD_MULTIPLE,
1933 /* X86_TUNE_INTER_UNIT_MOVES */
1936 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1939 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1940 than 4 branch instructions in the 16 byte window. */
1943 /* X86_TUNE_SCHEDULE */
1946 /* X86_TUNE_USE_BT */
1949 /* X86_TUNE_USE_INCDEC */
1952 /* X86_TUNE_PAD_RETURNS */
1955 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1956 m_ATOM,
1958 /* X86_TUNE_EXT_80387_CONSTANTS */
1961 /* X86_TUNE_AVOID_VECTOR_DECODE */
1964 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1965 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1968 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1969 vector path on AMD machines. */
1972 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1973 machines. */
1976 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1977 than a MOV. */
1978 m_PENT,
1980 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1981 but one byte longer. */
1982 m_PENT,
1984 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1985 operand that cannot be represented using a modRM byte. The XOR
1986 replacement is long decoded, so this split helps here as well. */
1987 m_K6,
1989 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1990 from FP to FP. */
1993 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1994 from integer to FP. */
1995 m_AMDFAM10,
1997 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1998 with a subsequent conditional jump instruction into a single
1999 compare-and-branch uop. */
2000 m_BDVER,
2002 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2003 will impact LEA instruction selection. */
2004 m_ATOM,
2006 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2007 instructions. */
2010 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2011 at -O3. For the moment, the prefetching seems badly tuned for Intel
2012 chips. */
2015 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
2016 the auto-vectorizer. */
2017 m_BDVER,
2019 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
2020 during reassociation of integer computation. */
2021 m_ATOM,
2023 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
2024 during reassociation of fp computation. */
2025 m_ATOM,
2027 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
2028 regs instead of memory. */
2029 m_COREI7 | m_CORE2I7
2030 };
2032 /* Feature tests against the various architecture variations. */
2035 /* Feature tests against the various architecture variations, used to create
2036 ix86_arch_features based on the processor mask. */
2038 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2041 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2044 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2047 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2050 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2052 };
2054 static const unsigned int x86_accumulate_outgoing_args
2057 static const unsigned int x86_arch_always_fancy_math_387
2060 static const unsigned int x86_avx256_split_unaligned_load
2063 static const unsigned int x86_avx256_split_unaligned_store
2066 /* In case the average insn count for single function invocation is
2067 lower than this constant, emit fast (but longer) prologue and
2068 epilogue code. */
2069 #define FAST_PROLOGUE_INSN_COUNT 20
2071 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2076 /* Array of the smallest class containing reg number REGNO, indexed by
2077 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2080 {
2081 /* ax, dx, cx, bx */
2083 /* si, di, bp, sp */
2085 /* FP registers */
2088 /* arg pointer */
2089 NON_Q_REGS,
2090 /* flags, fpsr, fpcr, frame */
2092 /* SSE registers */
2095 /* MMX registers */
2098 /* REX registers */
2101 /* SSE REX registers */
2104 };
2106 /* The "default" register map used in 32bit mode. */
2109 {
2117 };
2119 /* The "default" register map used in 64bit mode. */
2122 {
2130 };
2132 /* Define the register numbers to be used in Dwarf debugging information.
2133 The SVR4 reference port C compiler uses the following register numbers
2134 in its Dwarf output code:
2135 0 for %eax (gcc regno = 0)
2136 1 for %ecx (gcc regno = 2)
2137 2 for %edx (gcc regno = 1)
2138 3 for %ebx (gcc regno = 3)
2139 4 for %esp (gcc regno = 7)
2140 5 for %ebp (gcc regno = 6)
2141 6 for %esi (gcc regno = 4)
2142 7 for %edi (gcc regno = 5)
2143 The following three DWARF register numbers are never generated by
2144 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2145 believes these numbers have these meanings.
2146 8 for %eip (no gcc equivalent)
2147 9 for %eflags (gcc regno = 17)
2148 10 for %trapno (no gcc equivalent)
2149 It is not at all clear how we should number the FP stack registers
2150 for the x86 architecture. If the version of SDB on x86/svr4 were
2151 a bit less brain dead with respect to floating-point then we would
2152 have a precedent to follow with respect to DWARF register numbers
2153 for x86 FP registers, but the SDB on x86/svr4 is so completely
2154 broken with respect to FP registers that it is hardly worth thinking
2155 of it as something to strive for compatibility with.
2156 The version of x86/svr4 SDB I have at the moment does (partially)
2157 seem to believe that DWARF register number 11 is associated with
2158 the x86 register %st(0), but that's about all. Higher DWARF
2159 register numbers don't seem to be associated with anything in
2160 particular, and even for DWARF regno 11, SDB only seems to under-
2161 stand that it should say that a variable lives in %st(0) (when
2162 asked via an `=' command) if we said it was in DWARF regno 11,
2163 but SDB still prints garbage when asked for the value of the
2164 variable in question (via a `/' command).
2165 (Also note that the labels SDB prints for various FP stack regs
2166 when doing an `x' command are all wrong.)
2167 Note that these problems generally don't affect the native SVR4
2168 C compiler because it doesn't allow the use of -O with -g and
2169 because when it is *not* optimizing, it allocates a memory
2170 location for each floating-point variable, and the memory
2171 location is what gets described in the DWARF AT_location
2172 attribute for the variable in question.
2173 Regardless of the severe mental illness of the x86/svr4 SDB, we
2174 do something sensible here and we use the following DWARF
2175 register numbers. Note that these are all stack-top-relative
2176 numbers.
2177 11 for %st(0) (gcc regno = 8)
2178 12 for %st(1) (gcc regno = 9)
2179 13 for %st(2) (gcc regno = 10)
2180 14 for %st(3) (gcc regno = 11)
2181 15 for %st(4) (gcc regno = 12)
2182 16 for %st(5) (gcc regno = 13)
2183 17 for %st(6) (gcc regno = 14)
2184 18 for %st(7) (gcc regno = 15)
2185 */
2187 {
2195 };
2197 /* Define parameter passing and return registers. */
2200 {
2202 };
2205 {
2207 };
2210 {
2212 };
2214 /* Define the structure for the machine field in struct function. */
2219 rtx rtl;
2221 };
2223 /* Structure describing stack frame layout.
2224 Stack grows downward:
2226 [arguments]
2227 <- ARG_POINTER
2228 saved pc
2230 saved static chain if ix86_static_chain_on_stack
2232 saved frame pointer if frame_pointer_needed
2233 <- HARD_FRAME_POINTER
2234 [saved regs]
2235 <- regs_save_offset
2236 [padding0]
2238 [saved SSE regs]
2239 <- sse_regs_save_offset
2240 [padding1] |
2241 | <- FRAME_POINTER
2242 [va_arg registers] |
2243 |
2244 [frame] |
2245 |
2246 [padding2] | = to_allocate
2247 <- STACK_POINTER
2248 */
2249 struct ix86_frame
2250 {
2257 /* The offsets relative to ARG_POINTER. */
2258 HOST_WIDE_INT frame_pointer_offset;
2259 HOST_WIDE_INT hard_frame_pointer_offset;
2260 HOST_WIDE_INT stack_pointer_offset;
2261 HOST_WIDE_INT hfp_save_offset;
2262 HOST_WIDE_INT reg_save_offset;
2263 HOST_WIDE_INT sse_reg_save_offset;
2265 /* When save_regs_using_mov is set, emit prologue using
2266 move instead of push instructions. */
2268 };
2270 /* Which cpu are we scheduling for. */
2273 /* Which cpu are we optimizing for. */
2276 /* Which instruction set architecture to use. */
2279 /* True if processor has SSE prefetch instruction. */
2282 /* -mstackrealign option */
2299 /* Preferred alignment for stack boundary in bits. */
2302 /* Alignment for incoming stack boundary in bits specified at
2303 command line. */
2306 /* Default alignment for incoming stack boundary in bits. */
2309 /* Alignment for incoming stack boundary in bits. */
2312 /* Calling abi specific va_list type nodes. */
2316 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2320 /* Fence to use after loop using movnt. */
2321 tree x86_mfence;
2323 /* Register class used for passing given 64bit part of the argument.
2324 These represent classes as documented by the PS ABI, with the exception
2325 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2326 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2328 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2329 whenever possible (upper half does contain padding). */
2330 enum x86_64_reg_class
2331 {
2332 X86_64_NO_CLASS,
2333 X86_64_INTEGER_CLASS,
2334 X86_64_INTEGERSI_CLASS,
2335 X86_64_SSE_CLASS,
2336 X86_64_SSESF_CLASS,
2337 X86_64_SSEDF_CLASS,
2338 X86_64_SSEUP_CLASS,
2339 X86_64_X87_CLASS,
2340 X86_64_X87UP_CLASS,
2341 X86_64_COMPLEX_X87_CLASS,
2342 X86_64_MEMORY_CLASS
2343 };
2345 #define MAX_CLASSES 4
2347 /* Table of constants used by fldpi, fldln2, etc.... */
2351 \f
2356 const_tree);
2368 enum ix86_function_specific_strings
2369 {
2370 IX86_FUNCTION_SPECIFIC_ARCH,
2371 IX86_FUNCTION_SPECIFIC_TUNE,
2372 IX86_FUNCTION_SPECIFIC_MAX
2373 };
2391 \f
2392 #ifndef SUBTARGET32_DEFAULT_CPU
2394 #endif
2396 /* The svr4 ABI for the i386 says that records and unions are returned
2397 in memory. */
2398 #ifndef DEFAULT_PCC_STRUCT_RETURN
2399 #define DEFAULT_PCC_STRUCT_RETURN 1
2400 #endif
2402 /* Whether -mtune= or -march= were specified */
2406 /* Vectorization library interface and handlers. */
2412 /* Processor target table, indexed by processor number */
2413 struct ptt
2414 {
2421 };
2424 {
2435 /* Core 2 */
2437 /* Core i7 */
2448 };
2451 {
2479 "btver2"
2480 };
2481 \f
2482 static bool
2484 {
2486 }
2488 static unsigned int
2490 {
2493 /* vzeroupper instructions are inserted immediately after reload to
2494 account for possible spills from 256bit registers. The pass
2495 reuses mode switching infrastructure by re-running mode insertion
2496 pass, so disable entities that have already been processed. */
2502 /* Call optimize_mode_switching. */
2505 }
2508 {
2509 {
2510 RTL_PASS,
2525 }
2526 };
2528 /* Return true if a red-zone is in use. */
2532 {
2534 }
2535 \f
2536 /* Return a string that documents the current -m options. The caller is
2537 responsible for freeing the string. */
2543 {
2544 struct ix86_target_opts
2545 {
2548 };
2550 /* This table is ordered so that options like -msse4.2 that imply
2551 preceding options while match those first. */
2553 {
2589 };
2591 /* Flag options. */
2593 {
2621 };
2638 /* Add -march= option. */
2640 {
2643 }
2645 /* Add -mtune= option. */
2647 {
2650 }
2652 /* Add -m32/-m64/-mx32. */
2654 {
2657 else
2659 isa &= ~ (OPTION_MASK_ISA_64BIT
2660 | OPTION_MASK_ABI_64
2662 }
2663 else
2667 /* Pick out the options in isa options. */
2669 {
2671 {
2674 }
2675 }
2678 {
2681 isa);
2682 }
2684 /* Add flag options. */
2686 {
2688 {
2691 }
2692 }
2695 {
2698 }
2700 /* Add -fpmath= option. */
2702 {
2705 {
2720 }
2721 }
2723 /* Any options? */
2729 /* Size the string. */
2733 {
2738 }
2740 /* Build the string. */
2745 {
2752 {
2754 line_len++;
2757 {
2761 }
2762 }
2766 {
2770 }
2771 }
2777 }
2779 /* Return true, if profiling code should be emitted before
2780 prologue. Otherwise it returns false.
2781 Note: For x86 with "hotfix" it is sorried. */
2782 static bool
2784 {
2786 }
2788 /* Function that is callable from the debugger to print the current
2789 options. */
2790 void
2792 {
2798 {
2801 }
2802 else
2806 }
2807 \f
2808 /* Override various settings based on options. If MAIN_ARGS_P, the
2809 options are from the command line, otherwise they are from
2810 attributes. */
2812 static void
2814 {
2822 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2823 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2824 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2825 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2826 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2827 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2828 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2829 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2830 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2831 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2832 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2833 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2834 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2835 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2836 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2837 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2838 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2839 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2840 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2841 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2842 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2843 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2844 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2845 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2846 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2847 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2848 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2849 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2850 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2851 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2852 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2853 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2854 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2855 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2856 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2857 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2858 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2859 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2860 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2861 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2863 /* if this reaches 64, need to widen struct pta flags below */
2865 static struct pta
2866 {
2871 }
2873 {
3003 PTA_64BIT
3005 };
3007 /* -mrecip options. */
3008 static struct
3009 {
3012 }
3014 {
3021 };
3025 /* Set up prefix/suffix so the error messages refer to either the command
3026 line argument, or the attribute(target). */
3028 {
3032 }
3033 else
3034 {
3038 }
3040 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3041 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3044 #ifdef TARGET_BI_ARCH
3045 else
3046 {
3047 #if TARGET_BI_ARCH == 1
3048 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3049 is on and OPTION_MASK_ABI_X32 is off. We turn off
3050 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3051 -mx32. */
3054 #else
3055 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3056 on and OPTION_MASK_ABI_64 is off. We turn off
3057 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3058 -m64. */
3061 #endif
3062 }
3063 #endif
3066 {
3067 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3068 OPTION_MASK_ABI_64 for TARGET_X32. */
3071 }
3073 {
3074 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3075 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3078 }
3080 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3081 SUBTARGET_OVERRIDE_OPTIONS;
3082 #endif
3084 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3085 SUBSUBTARGET_OVERRIDE_OPTIONS;
3086 #endif
3088 /* -fPIC is the default for x86_64. */
3092 /* Need to check -mtune=generic first. */
3094 {
3097 /* As special support for cross compilers we read -mtune=native
3098 as -mtune=generic. With native compilers we won't see the
3099 -mtune=native, as it was changed by the driver. */
3101 {
3104 else
3106 }
3107 /* If this call is for setting the option attribute, allow the
3108 generic32/generic64 that was previously set. */
3112 ;
3120 }
3121 else
3122 {
3126 {
3129 }
3131 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3132 need to use a sensible tune option. */
3136 {
3139 else
3141 }
3142 }
3145 {
3146 /* rep; movq isn't available in 32-bit code. */
3149 }
3153 else
3157 {
3163 }
3164 else
3171 {
3173 {
3217 {
3220 }
3228 }
3229 }
3230 else
3231 {
3232 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3233 use of rip-relative addressing. This eliminates fixups that
3234 would otherwise be needed if this object is to be placed in a
3235 DLL, and is essentially just as efficient as direct addressing. */
3240 else
3242 }
3244 {
3247 }
3254 {
3257 /* Default cpu tuning to the architecture. */
3382 }
3397 {
3401 {
3403 {
3405 {
3413 }
3414 else
3417 }
3418 }
3419 else
3420 {
3421 /* Adjust tuning when compiling for 32-bit ABI. */
3423 {
3431 }
3432 }
3433 /* Intel CPUs have always interpreted SSE prefetch instructions as
3434 NOPs; so, we can enable SSE prefetch instructions even when
3435 -mtune (rather than -march) points us to a processor that has them.
3436 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3437 higher processors. */
3442 }
3452 #ifndef USE_IX86_FRAME_POINTER
3453 #define USE_IX86_FRAME_POINTER 0
3454 #endif
3456 #ifndef USE_X86_64_FRAME_POINTER
3457 #define USE_X86_64_FRAME_POINTER 0
3458 #endif
3460 /* Set the default values for switches whose default depends on TARGET_64BIT
3461 in case they weren't overwritten by command line options. */
3463 {
3470 }
3471 else
3472 {
3479 }
3484 else
3487 /* Arrange to set up i386_stack_locals for all functions. */
3490 /* Validate -mregparm= value. */
3492 {
3496 {
3500 }
3501 }
3505 /* Default align_* from the processor table. */
3507 {
3510 }
3512 {
3515 }
3517 {
3519 }
3521 /* Provide default for -mbranch-cost= value. */
3526 {
3529 /* Enable by default the SSE and MMX builtins. Do allow the user to
3530 explicitly disable any of these. In particular, disabling SSE and
3531 MMX for kernel code is extremely useful. */
3533 ix86_isa_flags
3539 }
3540 else
3541 {
3545 ix86_isa_flags
3548 /* i386 ABI does not specify red zone. It still makes sense to use it
3549 when programmer takes care to stack from being destroyed. */
3552 }
3554 /* Keep nonleaf frame pointers. */
3560 /* If we're doing fast math, we don't care about comparison order
3561 wrt NaNs. This lets us use a shorter comparison sequence. */
3565 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3566 since the insns won't need emulation. */
3570 /* Likewise, if the target doesn't have a 387, or we've specified
3571 software floating point, don't use 387 inline intrinsics. */
3575 /* Turn on MMX builtins for -msse. */
3579 /* Enable SSE prefetch. */
3583 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3587 /* Turn on lzcnt instruction for -mabm. */
3591 /* Validate -mpreferred-stack-boundary= value or default it to
3592 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3595 {
3601 {
3605 else
3608 }
3609 else
3610 ix86_preferred_stack_boundary
3612 }
3614 /* Set the default value for -mstackrealign. */
3620 /* Validate -mincoming-stack-boundary= value or default it to
3621 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3624 {
3629 else
3630 {
3631 ix86_user_incoming_stack_boundary
3633 ix86_incoming_stack_boundary
3635 }
3636 }
3638 /* Accept -msseregparm only if at least SSE support is enabled. */
3644 {
3646 {
3648 {
3651 }
3653 {
3656 }
3657 }
3658 }
3659 else
3662 /* If the i387 is disabled, then do not return values in it. */
3666 /* Use external vectorized library in vectorizing intrinsics. */
3669 {
3680 }
3688 /* ??? Unwind info is not correct around the CFG unless either a frame
3689 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3690 unwind info generation to be aware of the CFG and propagating states
3691 around edges. */
3694 && flag_omit_frame_pointer
3696 {
3702 }
3704 /* If stack probes are required, the space used for large function
3705 arguments on the stack must also be probed, so enable
3706 -maccumulate-outgoing-args so this happens in the prologue. */
3709 {
3714 }
3716 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3717 {
3723 }
3725 /* When scheduling description is not available, disable scheduler pass
3726 so it won't slow down the compilation and make x87 code slower. */
3747 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3749 && HAVE_prefetch
3754 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3755 can be optimized to ap = __builtin_next_arg (0). */
3760 {
3763 {
3766 ix86_gen_tls_local_dynamic_base_64
3768 }
3769 else
3770 {
3773 ix86_gen_tls_local_dynamic_base_64
3775 }
3776 }
3777 else
3778 {
3781 }
3784 {
3793 }
3794 else
3795 {
3804 }
3806 #ifdef USE_IX86_CLD
3807 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3810 #endif
3813 {
3818 }
3820 {
3824 }
3826 {
3827 #if defined(PROFILE_BEFORE_PROLOGUE)
3829 #else
3831 #endif
3832 }
3835 {
3836 /* When not optimize for size, enable vzeroupper optimization for
3837 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3838 AVX unaligned load/store. */
3840 {
3850 /* Enable 128-bit AVX instruction generation
3851 for the auto-vectorizer. */
3855 }
3856 }
3857 else
3858 {
3859 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3861 }
3864 {
3871 {
3874 {
3876 q++;
3877 }
3878 else
3883 else
3884 {
3887 {
3890 }
3893 {
3897 }
3898 }
3903 else
3905 }
3906 }
3913 /* Default long double to 64-bit for Bionic. */
3918 /* Save the initial options in case the user does function specific
3919 options. */
3921 target_option_default_node = target_option_current_node
3923 }
3925 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3927 static void
3929 {
3930 static struct register_pass_info insert_vzeroupper_info
3933 };
3938 /* This needs to be done at start up. It's convenient to do it here. */
3940 }
3942 /* Update register usage after having seen the compiler flags. */
3944 static void
3946 {
3950 /* The PIC register, if it exists, is fixed. */
3955 /* For 32-bit targets, squash the REX registers. */
3957 {
3962 }
3964 /* See the definition of CALL_USED_REGISTERS in i386.h. */
3972 {
3973 /* Set/reset conditionally defined registers from
3974 CALL_USED_REGISTERS initializer. */
3978 /* Calculate registers of CLOBBERED_REGS register set
3979 as call used registers from GENERAL_REGS register set. */
3983 }
3985 /* If MMX is disabled, squash the registers. */
3991 /* If SSE is disabled, squash the registers. */
3997 /* If the FPU is disabled, squash the registers. */
4002 }
4004 \f
4005 /* Save the current options */
4007 static void
4009 {
4020 /* The fields are char but the variables are not; make sure the
4021 values fit in the fields. */
4026 }
4028 /* Restore the current options */
4030 static void
4032 {
4048 /* Recreate the arch feature tests if the arch changed */
4050 {
4055 }
4057 /* Recreate the tune optimization tests */
4059 {
4064 }
4065 }
4067 /* Print the current options */
4069 static void
4072 {
4094 {
4097 }
4098 }
4100 \f
4101 /* Inner function to process the attribute((target(...))), take an argument and
4102 set the current options from the argument. If we have a list, recursively go
4103 over the list. */
4105 static bool
4108 {
4112 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4113 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4114 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4115 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4116 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4118 enum ix86_opt_type
4119 {
4120 ix86_opt_unknown,
4121 ix86_opt_yes,
4122 ix86_opt_no,
4123 ix86_opt_str,
4124 ix86_opt_enum,
4125 ix86_opt_isa
4126 };
4128 static const struct
4129 {
4136 /* isa options */
4173 /* enum options */
4176 /* string options */
4180 /* flag options */
4182 OPT_mcld,
4183 MASK_CLD),
4186 OPT_mfancy_math_387,
4187 MASK_NO_FANCY_MATH_387),
4190 OPT_mieee_fp,
4191 MASK_IEEE_FP),
4194 OPT_minline_all_stringops,
4195 MASK_INLINE_ALL_STRINGOPS),
4198 OPT_minline_stringops_dynamically,
4199 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4202 OPT_mno_align_stringops,
4203 MASK_NO_ALIGN_STRINGOPS),
4206 OPT_mrecip,
4207 MASK_RECIP),
4209 };
4211 /* If this is a list, recurse to get the options. */
4213 {
4223 }
4228 /* Handle multiple arguments separated by commas. */
4232 {
4246 {
4250 }
4251 else
4252 {
4255 }
4257 /* Recognize no-xxx. */
4259 {
4263 }
4264 else
4267 /* Find the option. */
4271 {
4279 {
4284 }
4285 }
4287 /* Process the option. */
4289 {
4292 }
4295 {
4301 }
4304 {
4310 else
4312 }
4315 {
4317 {
4320 }
4321 else
4323 }
4326 {
4334 global_dc);
4335 else
4336 {
4339 }
4340 }
4342 else
4344 }
4347 }
4349 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4351 tree
4353 {
4368 /* Process each of the options on the chain. */
4373 /* If the changed options are different from the default, rerun
4374 ix86_option_override_internal, and then save the options away.
4375 The string options are are attribute options, and will be undone
4376 when we copy the save structure. */
4382 {
4383 /* If we are using the default tune= or arch=, undo the string assigned,
4384 and use the default. */
4395 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4399 {
4402 }
4404 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4407 /* Add any builtin functions with the new isa if any. */
4410 /* Save the current options unless we are validating options for
4411 #pragma. */
4418 /* Free up memory allocated to hold the strings */
4421 }
4424 }
4426 /* Hook to validate attribute((target("string"))). */
4428 static bool
4431 tree args,
4433 {
4440 /* If the function changed the optimization levels as well as setting target
4441 options, start with the optimizations specified. */
4446 /* The target attributes may also change some optimization flags, so update
4447 the optimization options if necessary. */
4456 {
4461 }
4470 }
4472 \f
4473 /* Hook to determine if one function can safely inline another. */
4475 static bool
4477 {
4482 /* If callee has no option attributes, then it is ok to inline. */
4486 /* If caller has no option attributes, but callee does then it is not ok to
4487 inline. */
4491 else
4492 {
4496 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4497 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4498 function. */
4503 /* See if we have the same non-isa options. */
4507 /* See if arch, tune, etc. are the same. */
4520 else
4522 }
4525 }
4527 \f
4528 /* Remember the last target of ix86_set_current_function. */
4531 /* Establish appropriate back-end context for processing the function
4532 FNDECL. The argument might be NULL to indicate processing at top
4533 level, outside of any function scope. */
4534 static void
4536 {
4537 /* Only change the context if the function changes. This hook is called
4538 several times in the course of compiling a function, and we don't want to
4539 slow things down too much or call target_reinit when it isn't safe. */
4541 {
4542 tree old_tree = (ix86_previous_fndecl
4546 tree new_tree = (fndecl
4552 ;
4555 {
4559 }
4562 {
4568 }
4569 }
4570 }
4572 \f
4573 /* Return true if this goes in large data/bss. */
4575 static bool
4577 {
4581 /* Functions are never large data. */
4586 {
4592 }
4593 else
4594 {
4597 /* If this is an incomplete type with size 0, then we can't put it
4598 in data because it might be too big when completed. */
4601 }
4604 }
4606 /* Switch to the appropriate section for output of DECL.
4607 DECL is either a `VAR_DECL' node or a constant of some sort.
4608 RELOC indicates whether forming the initial value of DECL requires
4609 link-time relocations. */
4612 ATTRIBUTE_UNUSED;
4617 {
4620 {
4624 {
4658 /* We don't split these for medium model. Place them into
4659 default sections and hope for best. */
4661 }
4663 {
4664 /* We might get called with string constants, but get_named_section
4665 doesn't like them as they are not DECLs. Also, we need to set
4666 flags in that case. */
4670 }
4671 }
4673 }
4675 /* Build up a unique section name, expressed as a
4676 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4677 RELOC indicates whether the initial value of EXP requires
4678 link-time relocations. */
4680 static void ATTRIBUTE_UNUSED
4682 {
4685 {
4687 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4691 {
4715 /* We don't split these for medium model. Place them into
4716 default sections and hope for best. */
4718 }
4720 {
4727 /* If we're using one_only, then there needs to be a .gnu.linkonce
4728 prefix to the section name. */
4735 }
4736 }
4738 }
4740 #ifdef COMMON_ASM_OP
4741 /* This says how to output assembler code to declare an
4742 uninitialized external linkage data object.
4744 For medium model x86-64 we need to use .largecomm opcode for
4745 large objects. */
4746 void
4750 {
4754 else
4759 }
4760 #endif
4762 /* Utility function for targets to use in implementing
4763 ASM_OUTPUT_ALIGNED_BSS. */
4765 void
4769 {
4773 else
4776 #ifdef ASM_DECLARE_OBJECT_NAME
4779 #else
4780 /* Standard thing is just output label for the object. */
4784 }
4785 \f
4786 /* Decide whether we must probe the stack before any space allocation
4787 on this target. It's essentially TARGET_STACK_PROBE except when
4788 -fstack-check causes the stack to be already probed differently. */
4790 bool
4792 {
4793 /* Do not probe the stack twice if static stack checking is enabled. */
4798 }
4799 \f
4800 /* Decide whether we can make a sibling call to a function. DECL is the
4801 declaration of the function being targeted by the call and EXP is the
4802 CALL_EXPR representing the call. */
4804 static bool
4806 {
4810 /* If we are generating position-independent code, we cannot sibcall
4811 optimize any indirect call, or a direct call to a global function,
4812 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4814 && !TARGET_64BIT
4815 && flag_pic
4819 /* If we need to align the outgoing stack, then sibcalling would
4820 unalign the stack, which may break the called function. */
4826 {
4829 }
4830 else
4831 {
4832 /* We're looking at the CALL_EXPR, we need the type of the function. */
4837 }
4839 /* Check that the return value locations are the same. Like
4840 if we are returning floats on the 80387 register stack, we cannot
4841 make a sibcall from a function that doesn't return a float to a
4842 function that does or, conversely, from a function that does return
4843 a float to a function that doesn't; the necessary stack adjustment
4844 would not be executed. This is also the place we notice
4845 differences in the return value ABI. Note that it is ok for one
4846 of the functions to have void return type as long as the return
4847 value of the other is passed in a register. */
4852 {
4855 }
4857 ;
4862 {
4863 /* The SYSV ABI has more call-clobbered registers;
4864 disallow sibcalls from MS to SYSV. */
4868 }
4869 else
4870 {
4871 /* If this call is indirect, we'll need to be able to use a
4872 call-clobbered register for the address of the target function.
4873 Make sure that all such registers are not used for passing
4874 parameters. Note that DLLIMPORT functions are indirect. */
4877 {
4879 {
4880 /* ??? Need to count the actual number of registers to be used,
4881 not the possible number of registers. Fix later. */
4883 }
4884 }
4885 }
4887 /* Otherwise okay. That also includes certain types of indirect calls. */
4889 }
4891 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4892 and "sseregparm" calling convention attributes;
4893 arguments as in struct attribute_spec.handler. */
4895 static tree
4897 tree args,
4900 {
4905 {
4907 name);
4910 }
4912 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4914 {
4915 tree cst;
4918 {
4920 }
4923 {
4925 }
4929 {
4932 name);
4934 }
4936 {
4940 }
4943 }
4946 {
4947 /* Do not warn when emulating the MS ABI. */
4952 name);
4955 }
4957 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4959 {
4961 {
4963 }
4965 {
4967 }
4969 {
4971 }
4973 {
4975 }
4976 }
4978 /* Can combine stdcall with fastcall (redundant), regparm and
4979 sseregparm. */
4981 {
4983 {
4985 }
4987 {
4989 }
4991 {
4993 }
4994 }
4996 /* Can combine cdecl with regparm and sseregparm. */
4998 {
5000 {
5002 }
5004 {
5006 }
5008 {
5010 }
5011 }
5013 {
5016 name);
5018 {
5020 }
5022 {
5024 }
5026 {
5028 }
5029 }
5031 /* Can combine sseregparm with all attributes. */
5034 }
5036 /* The transactional memory builtins are implicitly regparm or fastcall
5037 depending on the ABI. Override the generic do-nothing attribute that
5038 these builtins were declared with, and replace it with one of the two
5039 attributes that we expect elsewhere. */
5041 static tree
5043 tree args ATTRIBUTE_UNUSED,
5046 {
5047 tree alt;
5049 /* In no case do we want to add the placeholder attribute. */
5052 /* The 64-bit ABI is unchanged for transactional memory. */
5056 /* ??? Is there a better way to validate 32-bit windows? We have
5057 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5060 else
5061 {
5064 }
5068 }
5070 /* This function determines from TYPE the calling-convention. */
5072 unsigned int
5074 {
5077 tree attrs;
5084 {
5094 /* Regparam isn't allowed for thiscall and fastcall. */
5096 {
5101 }
5105 }
5112 || is_stdarg
5118 }
5120 /* Return 0 if the attributes for two types are incompatible, 1 if they
5121 are compatible, and 2 if they are nearly compatible (which causes a
5122 warning to be generated). */
5124 static int
5126 {
5142 }
5143 \f
5144 /* Return the regparm value for a function with the indicated TYPE and DECL.
5145 DECL may be NULL when calling function indirectly
5146 or considering a libcall. */
5148 static int
5150 {
5151 tree attr;
5162 {
5165 {
5168 }
5169 }
5175 /* Use register calling convention for local functions when possible. */
5178 && optimize
5180 {
5181 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5184 {
5187 /* Make sure no regparm register is taken by a
5188 fixed register variable. */
5193 /* We don't want to use regparm(3) for nested functions as
5194 these use a static chain pointer in the third argument. */
5198 /* In 32-bit mode save a register for the split stack. */
5202 /* Each fixed register usage increases register pressure,
5203 so less registers should be used for argument passing.
5204 This functionality can be overriden by an explicit
5205 regparm value. */
5208 globals++;
5210 local_regparm
5215 }
5216 }
5219 }
5221 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5222 DFmode (2) arguments in SSE registers for a function with the
5223 indicated TYPE and DECL. DECL may be NULL when calling function
5224 indirectly or considering a libcall. Otherwise return 0. */
5226 static int
5228 {
5231 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5232 by the sseregparm attribute. */
5235 {
5237 {
5239 {
5243 else
5246 }
5248 }
5251 }
5253 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5254 (and DFmode for SSE2) arguments in SSE registers. */
5257 {
5258 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5262 }
5265 }
5267 /* Return true if EAX is live at the start of the function. Used by
5268 ix86_expand_prologue to determine if we need special help before
5269 calling allocate_stack_worker. */
5271 static bool
5273 {
5274 /* Cheat. Don't bother working forward from ix86_function_regparm
5275 to the function type to whether an actual argument is located in
5276 eax. Instead just look at cfg info, which is still close enough
5277 to correct at this point. This gives false positives for broken
5278 functions that might use uninitialized data that happens to be
5279 allocated in eax, but who cares? */
5281 }
5283 static bool
5285 {
5286 tree attr;
5289 {
5295 /* For 32-bit MS-ABI the default is to keep aggregate
5296 return pointer. */
5299 }
5301 }
5303 /* Value is the number of bytes of arguments automatically
5304 popped when returning from a subroutine call.
5305 FUNDECL is the declaration node of the function (as a tree),
5306 FUNTYPE is the data type of the function (as a tree),
5307 or for a library call it is an identifier node for the subroutine name.
5308 SIZE is the number of bytes of arguments passed on the stack.
5310 On the 80386, the RTD insn may be used to pop them if the number
5311 of args is fixed, but if the number is variable then the caller
5312 must pop them all. RTD can't be used for library calls now
5313 because the library is compiled with the Unix compiler.
5314 Use of RTD is a selectable option, since it is incompatible with
5315 standard Unix calling sequences. If the option is not selected,
5316 the caller must always pop the args.
5318 The attribute stdcall is equivalent to RTD on a per module basis. */
5320 static int
5322 {
5325 /* None of the 64-bit ABIs pop arguments. */
5336 /* Lose any fake structure return argument if it is passed on the stack. */
5339 {
5343 }
5346 }
5348 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5350 static bool
5352 {
5353 /* Check operand constraints in case hard registers were propagated
5354 into insn pattern. This check prevents combine pass from
5355 generating insn patterns with invalid hard register operands.
5356 These invalid insns can eventually confuse reload to error out
5357 with a spill failure. See also PRs 46829 and 46843. */
5359 {
5366 {
5374 /* A unary operator may be accepted by the predicate, but it
5375 is irrelevant for matching constraints. */
5380 {
5388 }
5395 /* Operand has no constraints, anything is OK. */
5399 {
5402 && operands_match_p
5406 {
5409 }
5410 }
5414 }
5415 }
5418 }
5419 \f
5420 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5422 static unsigned HOST_WIDE_INT
5424 {
5426 }
5427 \f
5428 /* Argument support functions. */
5430 /* Return true when register may be used to pass function parameters. */
5431 bool
5433 {
5438 {
5442 else
5448 }
5451 {
5454 }
5455 else
5456 {
5460 }
5462 /* TODO: The function should depend on current function ABI but
5463 builtins.c would need updating then. Therefore we use the
5464 default ABI. */
5466 /* RAX is used as hidden argument to va_arg functions. */
5472 else
5479 }
5481 /* Return if we do not know how to pass TYPE solely in registers. */
5483 static bool
5485 {
5489 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5490 The layout_type routine is crafty and tries to trick us into passing
5491 currently unsupported vector types on the stack by using TImode. */
5494 }
5496 /* It returns the size, in bytes, of the area reserved for arguments passed
5497 in registers for the function represented by fndecl dependent to the used
5498 abi format. */
5499 int
5501 {
5505 else
5510 }
5512 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5513 call abi used. */
5514 enum calling_abi
5516 {
5518 {
5521 {
5524 }
5528 }
5530 }
5532 static bool
5534 {
5536 {
5540 else
5542 }
5544 }
5546 static enum calling_abi
5548 {
5552 }
5554 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5555 call abi used. */
5556 enum calling_abi
5558 {
5562 }
5564 /* Write the extra assembler code needed to declare a function properly. */
5566 void
5568 tree decl)
5569 {
5573 {
5579 }
5581 #ifdef SUBTARGET_ASM_UNWIND_INIT
5583 #endif
5587 /* Output magic byte marker, if hot-patch attribute is set. */
5589 {
5591 {
5592 /* leaq [%rsp + 0], %rsp */
5595 }
5596 else
5597 {
5598 /* movl.s %edi, %edi
5599 push %ebp
5600 movl.s %esp, %ebp */
5603 }
5604 }
5605 }
5607 /* regclass.c */
5610 /* Implementation of call abi switching target hook. Specific to FNDECL
5611 the specific call register sets are set. See also
5612 ix86_conditional_register_usage for more details. */
5613 void
5615 {
5618 else
5620 }
5622 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5623 expensive re-initialization of init_regs each time we switch function context
5624 since this is needed only during RTL expansion. */
5625 static void
5627 {
5631 }
5633 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5634 for a call to a function whose data type is FNTYPE.
5635 For a library call, FNTYPE is 0. */
5637 void
5641 tree fndecl,
5643 {
5649 {
5652 }
5653 else
5654 {
5657 }
5661 /* Set up the number of registers to use for passing arguments. */
5668 {
5670 ? X86_64_REGPARM_MAX
5672 }
5674 {
5677 {
5679 ? X86_64_SSE_REGPARM_MAX
5681 }
5682 }
5689 /* Because type might mismatch in between caller and callee, we need to
5690 use actual type of function for local calls.
5691 FIXME: cgraph_analyze can be told to actually record if function uses
5692 va_start so for local functions maybe_vaarg can be made aggressive
5693 helping K&R code.
5694 FIXME: once typesytem is fixed, we won't need this code anymore. */
5702 {
5703 /* If there are variable arguments, then we won't pass anything
5704 in registers in 32-bit mode. */
5706 {
5714 }
5716 /* Use ecx and edx registers if function has fastcall attribute,
5717 else look for regparm information. */
5719 {
5722 {
5725 }
5727 {
5730 }
5731 else
5733 }
5735 /* Set up the number of SSE registers used for passing SFmode
5736 and DFmode arguments. Warn for mismatching ABI. */
5738 }
5739 }
5741 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5742 But in the case of vector types, it is some vector mode.
5744 When we have only some of our vector isa extensions enabled, then there
5745 are some modes for which vector_mode_supported_p is false. For these
5746 modes, the generic vector support in gcc will choose some non-vector mode
5747 in order to implement the type. By computing the natural mode, we'll
5748 select the proper ABI location for the operand and not depend on whatever
5749 the middle-end decides to do with these vector types.
5751 The midde-end can't deal with the vector types > 16 bytes. In this
5752 case, we return the original mode and warn ABI change if CUM isn't
5753 NULL. */
5755 static enum machine_mode
5757 {
5761 {
5764 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5766 {
5771 else
5774 /* Get the mode which has this inner mode and number of units. */
5778 {
5780 {
5784 && !warnedavx
5786 {
5790 }
5792 }
5794 {
5798 && !warnedsse
5800 {
5804 }
5806 }
5807 else
5809 }
5812 }
5813 }
5816 }
5818 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5819 this may not agree with the mode that the type system has chosen for the
5820 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5821 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5823 static rtx
5826 {
5827 rtx tmp;
5831 else
5832 {
5836 }
5839 }
5841 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5842 of this code is to classify each 8bytes of incoming argument by the register
5843 class and assign registers accordingly. */
5845 /* Return the union class of CLASS1 and CLASS2.
5846 See the x86-64 PS ABI for details. */
5848 static enum x86_64_reg_class
5850 {
5851 /* Rule #1: If both classes are equal, this is the resulting class. */
5855 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5856 the other class. */
5862 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5866 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5874 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5875 MEMORY is used. */
5884 /* Rule #6: Otherwise class SSE is used. */
5886 }
5888 /* Classify the argument of type TYPE and mode MODE.
5889 CLASSES will be filled by the register class used to pass each word
5890 of the operand. The number of words is returned. In case the parameter
5891 should be passed in memory, 0 is returned. As a special case for zero
5892 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5894 BIT_OFFSET is used internally for handling records and specifies offset
5895 of the offset in bits modulo 256 to avoid overflow cases.
5897 See the x86-64 PS ABI for details.
5898 */
5900 static int
5903 {
5904 HOST_WIDE_INT bytes =
5906 int words
5909 /* Variable sized entities are always passed/returned in memory. */
5918 {
5920 tree field;
5923 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5930 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5931 signalize memory class, so handle it as special case. */
5933 {
5936 }
5938 /* Classify each field of record and merge classes. */
5940 {
5942 /* And now merge the fields of structure. */
5944 {
5946 {
5952 /* Bitfields are always classified as integer. Handle them
5953 early, since later code would consider them to be
5954 misaligned integers. */
5956 {
5965 }
5966 else
5967 {
5972 /* Flexible array member is ignored. */
5979 {
5983 {
5986 "the ABI of passing struct with"
5987 " a flexible array member has"
5989 }
5991 }
5993 subclasses,
6003 }
6004 }
6005 }
6009 /* Arrays are handled as small records. */
6010 {
6017 /* The partial classes are now full classes. */
6028 }
6031 /* Unions are similar to RECORD_TYPE but offset is always 0.
6032 */
6034 {
6036 {
6044 bit_offset);
6049 }
6050 }
6055 }
6058 {
6059 /* When size > 16 bytes, if the first one isn't
6060 X86_64_SSE_CLASS or any other ones aren't
6061 X86_64_SSEUP_CLASS, everything should be passed in
6062 memory. */
6069 }
6071 /* Final merger cleanup. */
6073 {
6074 /* If one class is MEMORY, everything should be passed in
6075 memory. */
6079 /* The X86_64_SSEUP_CLASS should be always preceded by
6080 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6084 {
6085 /* The first one should never be X86_64_SSEUP_CLASS. */
6088 }
6090 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6091 everything should be passed in memory. */
6094 {
6097 /* The first one should never be X86_64_X87UP_CLASS. */
6100 {
6103 "the ABI of passing union with long double"
6105 }
6107 }
6108 }
6110 }
6112 /* Compute alignment needed. We align all types to natural boundaries with
6113 exception of XFmode that is aligned to 64bits. */
6115 {
6124 /* Misaligned fields are always returned in memory. */
6127 }
6129 /* for V1xx modes, just use the base mode */
6134 /* Classification of atomic types. */
6136 {
6152 {
6156 {
6159 }
6161 {
6164 }
6166 {
6170 }
6172 {
6175 }
6176 else
6178 }
6185 /* OImode shouldn't be used directly. */
6192 else
6210 else
6211 {
6215 {
6218 "the ABI of passing structure with complex float"
6220 }
6223 }
6232 /* This modes is larger than 16 bytes. */
6275 else
6279 }
6280 }
6282 /* Examine the argument and return set number of register required in each
6283 class. Return 0 iff parameter should be passed in memory. */
6284 static int
6287 {
6297 {
6319 }
6321 }
6323 /* Construct container for the argument used by GCC interface. See
6324 FUNCTION_ARG for the detailed description. */
6326 static rtx
6330 {
6331 /* The following variables hold the static issued_error state. */
6345 rtx ret;
6356 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6357 some less clueful developer tries to use floating-point anyway. */
6359 {
6361 {
6363 {
6366 }
6367 }
6369 {
6372 }
6374 }
6376 /* Likewise, error if the ABI requires us to return values in the
6377 x87 registers and the user specified -mno-80387. */
6383 {
6385 {
6388 }
6390 }
6392 /* First construct simple cases. Avoid SCmode, since we want to use
6393 single register to pass this type. */
6396 {
6411 /* Zero sized array, struct or class. */
6415 }
6442 /* Otherwise figure out the entries of the PARALLEL. */
6444 {
6448 {
6453 /* Merge TImodes on aligned occasions here too. */
6455 tmpmode
6459 else
6461 /* We've requested 24 bytes we
6462 don't have mode for. Use DImode. */
6469 intreg++;
6477 sse_regno++;
6485 sse_regno++;
6490 {
6496 {
6498 i++;
6499 }
6500 else
6513 }
6519 sse_regno++;
6523 }
6524 }
6526 /* Empty aligned struct, union or class. */
6534 }
6536 /* Update the data in CUM to advance over an argument of mode MODE
6537 and data type TYPE. (TYPE is null for libcalls where that information
6538 may not be available.) */
6540 static void
6543 HOST_WIDE_INT words)
6544 {
6546 {
6553 /* FALLTHRU */
6564 {
6567 }
6571 /* OImode shouldn't be used directly. */
6580 /* FALLTHRU */
6596 {
6601 {
6604 }
6605 }
6615 {
6620 {
6623 }
6624 }
6626 }
6627 }
6629 static void
6632 {
6635 /* Unnamed 256bit vector mode parameters are passed on stack. */
6641 {
6646 }
6647 else
6648 {
6652 }
6653 }
6655 static void
6657 HOST_WIDE_INT words)
6658 {
6659 /* Otherwise, this should be passed indirect. */
6664 {
6667 }
6668 }
6670 /* Update the data in CUM to advance over an argument of mode MODE and
6671 data type TYPE. (TYPE is null for libcalls where that information
6672 may not be available.) */
6674 static void
6677 {
6683 else
6694 else
6696 }
6698 /* Define where to put the arguments to a function.
6699 Value is zero to push the argument on the stack,
6700 or a hard register in which to store the argument.
6702 MODE is the argument's machine mode.
6703 TYPE is the data type of the argument (as a tree).
6704 This is null for libcalls where that information may
6705 not be available.
6706 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6707 the preceding args and about the function being called.
6708 NAMED is nonzero if this argument is a named parameter
6709 (otherwise it is an extra parameter matching an ellipsis). */
6711 static rtx
6715 {
6718 /* Avoid the AL settings for the Unix64 ABI. */
6723 {
6730 /* FALLTHRU */
6736 {
6739 /* Fastcall allocates the first two DWORD (SImode) or
6740 smaller arguments to ECX and EDX if it isn't an
6741 aggregate type . */
6743 {
6749 /* ECX not EAX is the first allocated register. */
6752 }
6754 }
6763 /* FALLTHRU */
6765 /* In 32bit, we pass TImode in xmm registers. */
6773 {
6775 {
6779 }
6783 }
6787 /* OImode shouldn't be used directly. */
6797 {
6801 }
6811 {
6813 {
6817 }
6821 }
6823 }
6826 }
6828 static rtx
6831 {
6832 /* Handle a hidden AL argument containing number of registers
6833 for varargs x86-64 functions. */
6837 ? X86_64_SSE_REGPARM_MAX
6842 {
6852 /* Unnamed 256bit vector mode parameters are passed on stack. */
6856 }
6862 }
6864 static rtx
6867 HOST_WIDE_INT bytes)
6868 {
6871 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6872 We use value of -2 to specify that current function call is MSABI. */
6876 /* If we've run out of registers, it goes on the stack. */
6882 /* Only floating point modes are passed in anything but integer regs. */
6884 {
6887 else
6888 {
6891 /* Unnamed floating parameters are passed in both the
6892 SSE and integer registers. */
6898 }
6899 }
6900 /* Handle aggregated types passed in register. */
6902 {
6907 }
6910 }
6912 /* Return where to put the arguments to a function.
6913 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6915 MODE is the argument's machine mode. TYPE is the data type of the
6916 argument. It is null for libcalls where that information may not be
6917 available. CUM gives information about the preceding args and about
6918 the function being called. NAMED is nonzero if this argument is a
6919 named parameter (otherwise it is an extra parameter matching an
6920 ellipsis). */
6922 static rtx
6925 {
6929 rtx arg;
6933 else
6937 /* To simplify the code below, represent vector types with a vector mode
6938 even if MMX/SSE are not active. */
6946 else
6950 }
6952 /* A C expression that indicates when an argument must be passed by
6953 reference. If nonzero for an argument, a copy of that argument is
6954 made in memory and a pointer to the argument is passed instead of
6955 the argument itself. The pointer is passed in whatever way is
6956 appropriate for passing a pointer to that type. */
6958 static bool
6962 {
6965 /* See Windows x64 Software Convention. */
6967 {
6970 {
6971 /* Arrays are passed by reference. */
6976 {
6977 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6978 are passed by reference. */
6980 }
6981 }
6983 /* __m128 is passed by reference. */
6989 }
6990 }
6995 }
6997 /* Return true when TYPE should be 128bit aligned for 32bit argument
6998 passing ABI. XXX: This function is obsolete and is only used for
6999 checking psABI compatibility with previous versions of GCC. */
7001 static bool
7003 {
7015 {
7016 /* Walk the aggregates recursively. */
7018 {
7022 {
7023 tree field;
7025 /* Walk all the structure fields. */
7027 {
7031 }
7033 }
7036 /* Just for use if some languages passes arrays by value. */
7043 }
7044 }
7046 }
7048 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7049 XXX: This function is obsolete and is only used for checking psABI
7050 compatibility with previous versions of GCC. */
7052 static unsigned int
7055 {
7056 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7057 natural boundaries. */
7059 {
7060 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7061 make an exception for SSE modes since these require 128bit
7062 alignment.
7064 The handling here differs from field_alignment. ICC aligns MMX
7065 arguments to 4 byte boundaries, while structure fields are aligned
7066 to 8 byte boundaries. */
7068 {
7071 }
7072 else
7073 {
7076 }
7077 }
7081 }
7083 /* Return true when TYPE should be 128bit aligned for 32bit argument
7084 passing ABI. */
7086 static bool
7088 {
7098 {
7099 /* Walk the aggregates recursively. */
7101 {
7105 {
7106 tree field;
7108 /* Walk all the structure fields. */
7110 field;
7112 {
7116 }
7118 }
7121 /* Just for use if some languages passes arrays by value. */
7128 }
7129 }
7130 else
7134 }
7136 /* Gives the alignment boundary, in bits, of an argument with the
7137 specified mode and type. */
7139 static unsigned int
7141 {
7144 {
7145 /* Since the main variant type is used for call, we convert it to
7146 the main variant type. */
7149 }
7150 else
7154 else
7155 {
7160 {
7161 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7163 {
7166 }
7172 }
7175 && !warned
7177 saved_align))
7178 {
7181 "The ABI for passing parameters with %d-byte"
7184 }
7185 }
7188 }
7190 /* Return true if N is a possible register number of function value. */
7192 static bool
7194 {
7196 {
7201 /* TODO: The function should depend on current function ABI but
7202 builtins.c would need updating then. Therefore we use the
7203 default ABI. */
7215 }
7218 }
7220 /* Define how to find the value returned by a function.
7221 VALTYPE is the data type of the value (as a tree).
7222 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7223 otherwise, FUNC is 0. */
7225 static rtx
7228 {
7231 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7232 we normally prevent this case when mmx is not available. However
7233 some ABIs may require the result to be returned like DImode. */
7237 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7238 we prevent this case when sse is not available. However some ABIs
7239 may require the result to be returned like integer TImode. */
7244 /* 32-byte vector modes in %ymm0. */
7248 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7251 else
7252 /* Most things go in %eax. */
7255 /* Override FP return register with %xmm0 for local functions when
7256 SSE math is enabled or for functions with sseregparm attribute. */
7258 {
7263 }
7265 /* OImode shouldn't be used directly. */
7269 }
7271 static rtx
7273 const_tree valtype)
7274 {
7275 rtx ret;
7277 /* Handle libcalls, which don't provide a type node. */
7279 {
7283 {
7302 }
7305 }
7307 {
7308 /* Pointers are always returned in word_mode. */
7310 }
7316 /* For zero sized structures, construct_container returns NULL, but we
7317 need to keep rest of compiler happy by returning meaningful value. */
7322 }
7324 static rtx
7326 {
7330 {
7332 {
7345 }
7346 }
7348 }
7350 static rtx
7353 {
7365 else
7367 }
7369 static rtx
7372 {
7378 }
7380 /* Pointer function arguments and return values are promoted to
7381 word_mode. */
7383 static enum machine_mode
7387 {
7389 {
7392 }
7394 for_return);
7395 }
7397 /* Return true if a structure, union or array with MODE containing FIELD
7398 should be accessed using BLKmode. */
7400 static bool
7402 {
7403 /* Union with XFmode must be in BLKmode. */
7407 }
7409 rtx
7411 {
7413 }
7415 /* Return true iff type is returned in memory. */
7417 static bool ATTRIBUTE_UNUSED
7419 {
7420 HOST_WIDE_INT size;
7431 {
7432 /* User-created vectors small enough to fit in EAX. */
7436 /* MMX/3dNow values are returned in MM0,
7437 except when it doesn't exits or the ABI prescribes otherwise. */
7441 /* SSE values are returned in XMM0, except when it doesn't exist. */
7445 /* AVX values are returned in YMM0, except when it doesn't exist. */
7448 }
7456 /* OImode shouldn't be used directly. */
7460 }
7462 static bool ATTRIBUTE_UNUSED
7464 {
7467 }
7469 static bool ATTRIBUTE_UNUSED
7471 {
7474 /* __m128 is returned in xmm0. */
7479 /* Otherwise, the size must be exactly in [1248]. */
7481 }
7483 static bool
7485 {
7486 #ifdef SUBTARGET_RETURN_IN_MEMORY
7488 #else
7492 {
7495 else
7497 }
7498 else
7500 #endif
7501 }
7503 /* When returning SSE vector types, we have a choice of either
7504 (1) being abi incompatible with a -march switch, or
7505 (2) generating an error.
7506 Given no good solution, I think the safest thing is one warning.
7507 The user won't be able to use -Werror, but....
7509 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7510 called in response to actually generating a caller or callee that
7511 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7512 via aggregate_value_p for general type probing from tree-ssa. */
7514 static rtx
7516 {
7520 {
7521 /* Look at the return type of the function, not the function type. */
7525 {
7528 {
7532 }
7533 }
7536 {
7538 {
7542 }
7543 }
7544 }
7547 }
7549 \f
7550 /* Create the va_list data type. */
7552 /* Returns the calling convention specific va_list date type.
7553 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7555 static tree
7557 {
7560 /* For i386 we use plain pointer to argument area. */
7570 unsigned_type_node);
7573 unsigned_type_node);
7576 ptr_type_node);
7579 ptr_type_node);
7598 /* The correct type is an array type of one element. */
7600 }
7602 /* Setup the builtin va_list data type and for 64-bit the additional
7603 calling convention specific va_list data types. */
7605 static tree
7607 {
7610 /* Initialize abi specific va_list builtin types. */
7612 {
7613 tree t;
7615 {
7620 }
7621 else
7622 {
7627 }
7629 {
7634 }
7635 else
7636 {
7641 }
7642 }
7645 }
7647 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7649 static void
7651 {
7653 alias_set_type set;
7656 /* GPR size of varargs save area. */
7659 else
7662 /* FPR size of varargs save area. We don't need it if we don't pass
7663 anything in SSE registers. */
7666 else
7680 {
7688 }
7691 {
7695 /* Now emit code to save SSE registers. The AX parameter contains number
7696 of SSE parameter registers used to call this function, though all we
7697 actually check here is the zero/non-zero status. */
7702 label));
7704 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7705 we used movdqa (i.e. TImode) instead? Perhaps even better would
7706 be if we could determine the real mode of the data, via a hook
7707 into pass_stdarg. Ignore all that for now. */
7717 {
7726 }
7729 }
7730 }
7732 static void
7734 {
7738 /* Reset to zero, as there might be a sysv vaarg used
7739 before. */
7744 {
7755 }
7756 }
7758 static void
7762 {
7764 CUMULATIVE_ARGS next_cum;
7765 tree fntype;
7767 /* This argument doesn't appear to be used anymore. Which is good,
7768 because the old code here didn't suppress rtl generation. */
7776 /* For varargs, we do not want to skip the dummy va_dcl argument.
7777 For stdargs, we do want to skip the last named argument. */
7785 else
7787 }
7789 /* Checks if TYPE is of kind va_list char *. */
7791 static bool
7793 {
7794 tree canonic;
7796 /* For 32-bit it is always true. */
7802 }
7804 /* Implement va_start. */
7806 static void
7808 {
7812 tree type;
7813 rtx ovf_rtx;
7817 {
7820 /* When we are splitting the stack, we can't refer to the stack
7821 arguments using internal_arg_pointer, because they may be on
7822 the old stack. The split stack prologue will arrange to
7823 leave a pointer to the old stack arguments in a scratch
7824 register, which we here copy to a pseudo-register. The split
7825 stack prologue can't set the pseudo-register directly because
7826 it (the prologue) runs before any registers have been saved. */
7830 {
7844 }
7845 }
7847 /* Only 64bit target needs something special. */
7849 {
7852 else
7853 {
7862 }
7864 }
7873 /* The following should be folded into the MEM_REF offset. */
7883 /* Count number of gp and fp argument registers used. */
7889 {
7895 }
7898 {
7904 }
7906 /* Find the overflow area. */
7910 else
7920 {
7921 /* Find the register save area.
7922 Prologue of the function save it right above stack frame. */
7930 }
7931 }
7933 /* Implement va_arg. */
7935 static tree
7938 {
7945 rtx container;
7947 tree ptrtype;
7951 /* Only 64bit target needs something special. */
7975 {
7982 /* Unnamed 256bit vector mode parameters are passed on stack. */
7984 {
7987 }
7995 }
7997 /* Pull the value out of the saved registers. */
8002 {
8016 /* In case we are passing structure, verify that it is consecutive block
8017 on the register save area. If not we need to do moves. */
8019 {
8020 /* Verify that all registers are strictly consecutive */
8022 {
8026 {
8031 }
8032 }
8033 else
8034 {
8038 {
8043 }
8044 }
8045 }
8047 {
8050 }
8051 else
8052 {
8055 }
8057 /* First ensure that we fit completely in registers. */
8059 {
8066 }
8068 {
8076 }
8078 /* Compute index to start of area used for integer regs. */
8080 {
8081 /* int_addr = gpr + sav; */
8084 }
8086 {
8087 /* sse_addr = fpr + sav; */
8090 }
8092 {
8096 /* addr = &temp; */
8101 {
8105 tree piece_type;
8106 tree addr_type;
8107 tree daddr_type;
8116 {
8121 }
8125 else
8132 {
8135 }
8136 else
8137 {
8140 }
8147 {
8152 }
8153 else
8154 {
8155 tree copy
8160 }
8162 }
8163 }
8166 {
8170 }
8173 {
8177 }
8182 }
8184 /* ... otherwise out of the overflow area. */
8186 /* When we align parameter on stack for caller, if the parameter
8187 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8188 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8189 here with caller. */
8194 /* Care for on-stack alignment if needed. */
8197 else
8198 {
8203 }
8220 }
8221 \f
8222 /* Return true if OPNUM's MEM should be matched
8223 in movabs* patterns. */
8225 bool
8227 {
8239 }
8240 \f
8241 /* Initialize the table of extra 80387 mathematical constants. */
8243 static void
8245 {
8247 {
8253 };
8257 {
8259 /* Ensure each constant is rounded to XFmode precision. */
8262 }
8265 }
8267 /* Return non-zero if the constant is something that
8268 can be loaded with a special instruction. */
8270 int
8272 {
8275 REAL_VALUE_TYPE r;
8287 /* For XFmode constants, try to find a special 80387 instruction when
8288 optimizing for size or on those CPUs that benefit from them. */
8291 {
8300 }
8302 /* Load of the constant -0.0 or -1.0 will be split as
8303 fldz;fchs or fld1;fchs sequence. */
8310 }
8312 /* Return the opcode of the special instruction to be used to load
8313 the constant X. */
8317 {
8319 {
8339 }
8340 }
8342 /* Return the CONST_DOUBLE representing the 80387 constant that is
8343 loaded by the specified special instruction. The argument IDX
8344 matches the return value from standard_80387_constant_p. */
8346 rtx
8348 {
8355 {
8366 }
8369 XFmode);
8370 }
8372 /* Return 1 if X is all 0s and 2 if x is all 1s
8373 in supported SSE/AVX vector mode. */
8375 int
8377 {
8384 {
8399 }
8402 }
8404 /* Return the opcode of the special instruction to be used to load
8405 the constant X. */
8409 {
8411 {
8414 {
8431 }
8436 else
8441 }
8443 }
8445 /* Returns true if OP contains a symbol reference */
8447 bool
8449 {
8458 {
8460 {
8466 }
8470 }
8473 }
8475 /* Return true if it is appropriate to emit `ret' instructions in the
8476 body of a function. Do this only if the epilogue is simple, needing a
8477 couple of insns. Prior to reloading, we can't tell how many registers
8478 must be saved, so return false then. Return false if there is no frame
8479 marker to de-allocate. */
8481 bool
8483 {
8489 /* Don't allow more than 32k pop, since that's all we can do
8490 with one instruction. */
8497 }
8498 \f
8499 /* Value should be nonzero if functions must have frame pointers.
8500 Zero means the frame pointer need not be set up (and parms may
8501 be accessed via the stack pointer) in functions that seem suitable. */
8503 static bool
8505 {
8506 /* If we accessed previous frames, then the generated code expects
8507 to be able to access the saved ebp value in our frame. */
8511 /* Several x86 os'es need a frame pointer for other reasons,
8512 usually pertaining to setjmp. */
8516 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8520 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8521 allocation is 4GB. */
8525 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8526 turns off the frame pointer by default. Turn it back on now if
8527 we've not got a leaf function. */
8537 }
8539 /* Record that the current function accesses previous call frames. */
8541 void
8543 {
8545 }
8546 \f
8547 #ifndef USE_HIDDEN_LINKONCE
8548 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8549 # define USE_HIDDEN_LINKONCE 1
8550 # else
8551 # define USE_HIDDEN_LINKONCE 0
8552 # endif
8553 #endif
8557 /* Fills in the label name that should be used for a pc thunk for
8558 the given register. */
8560 static void
8562 {
8567 else
8569 }
8572 /* This function generates code for -fpic that loads %ebx with
8573 the return address of the caller and then returns. */
8575 static void
8577 {
8582 {
8584 tree decl;
8600 #if TARGET_MACHO
8602 {
8611 }
8612 else
8613 #endif
8615 {
8626 }
8627 else
8628 {
8631 }
8637 /* Make sure unwind info is emitted for the thunk if needed. */
8640 /* Pad stack IP move with 4 instructions (two NOPs count
8641 as one instruction). */
8643 {
8648 }
8659 }
8663 }
8665 /* Emit code for the SET_GOT patterns. */
8669 {
8675 {
8676 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8681 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8682 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8683 an unadorned address. */
8688 }
8693 {
8698 #if TARGET_MACHO
8699 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8700 is what will be referenced by the Mach-O PIC subsystem. */
8703 #endif
8707 }
8708 else
8709 {
8717 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8718 is what will be referenced by the Mach-O PIC subsystem. */
8719 #if TARGET_MACHO
8722 else
8725 #endif
8726 }
8732 }
8734 /* Generate an "push" pattern for input ARG. */
8736 static rtx
8738 {
8751 stack_pointer_rtx)),
8752 arg);
8753 }
8755 /* Generate an "pop" pattern for input ARG. */
8757 static rtx
8759 {
8764 arg,
8767 stack_pointer_rtx)));
8768 }
8770 /* Return >= 0 if there is an unused call-clobbered register available
8771 for the entire function. */
8773 static unsigned int
8775 {
8779 {
8781 /* Can't use the same register for both PIC and DRAP. */
8784 else
8789 }
8792 }
8794 /* Return TRUE if we need to save REGNO. */
8796 static bool
8798 {
8808 {
8811 {
8817 }
8818 }
8827 }
8829 /* Return number of saved general prupose registers. */
8831 static int
8833 {
8839 nregs ++;
8841 }
8843 /* Return number of saved SSE registrers. */
8845 static int
8847 {
8855 nregs ++;
8857 }
8859 /* Given FROM and TO register numbers, say whether this elimination is
8860 allowed. If stack alignment is needed, we can only replace argument
8861 pointer with hard frame pointer, or replace frame pointer with stack
8862 pointer. Otherwise, frame pointer elimination is automatically
8863 handled and all other eliminations are valid. */
8865 static bool
8867 {
8873 else
8875 }
8877 /* Return the offset between two registers, one to be eliminated, and the other
8878 its replacement, at the start of a routine. */
8880 HOST_WIDE_INT
8882 {
8891 else
8892 {
8900 }
8901 }
8903 /* In a dynamically-aligned function, we can't know the offset from
8904 stack pointer to frame pointer, so we must ensure that setjmp
8905 eliminates fp against the hard fp (%ebp) rather than trying to
8906 index from %esp up to the top of the frame across a gap that is
8907 of unknown (at compile-time) size. */
8908 static rtx
8910 {
8912 }
8914 /* When using -fsplit-stack, the allocation routines set a field in
8915 the TCB to the bottom of the stack plus this much space, measured
8916 in bytes. */
8918 #define SPLIT_STACK_AVAILABLE 256
8920 /* Fill structure ix86_frame about frame of currently computed function. */
8922 static void
8924 {
8926 HOST_WIDE_INT offset;
8929 HOST_WIDE_INT to_allocate;
8937 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8938 function prologues and leaf. */
8942 {
8947 }
8953 /* For SEH we have to limit the amount of code movement into the prologue.
8954 At present we do this via a BLOCKAGE, at which point there's very little
8955 scheduling that can be done, which means that there's very little point
8956 in doing anything except PUSHs. */
8960 /* During reload iteration the amount of registers saved can change.
8961 Recompute the value as needed. Do not recompute when amount of registers
8962 didn't change as reload does multiple calls to the function and does not
8963 expect the decision to change within single iteration. */
8966 {
8972 /* The fast prologue uses move instead of push to save registers. This
8973 is significantly longer, but also executes faster as modern hardware
8974 can execute the moves in parallel, but can't do that for push/pop.
8976 Be careful about choosing what prologue to emit: When function takes
8977 many instructions to execute we may use slow version as well as in
8978 case function is known to be outside hot spot (this is known with
8979 feedback only). Weight the size of function by number of registers
8980 to save as it is cheap to use one or two push instructions but very
8981 slow to use many of them. */
8985 || (flag_branch_probabilities
8988 else
8991 }
8993 frame->save_regs_using_mov
8995 /* If static stack checking is enabled and done with probes,
8996 the registers need to be saved before allocating the frame. */
8999 /* Skip return address. */
9002 /* Skip pushed static chain. */
9006 /* Skip saved base pointer. */
9011 /* The traditional frame pointer location is at the top of the frame. */
9014 /* Register save area */
9018 /* On SEH target, registers are pushed just before the frame pointer
9019 location. */
9023 /* Align and set SSE register save area. */
9025 {
9026 /* The only ABI that has saved SSE registers (Win64) also has a
9027 16-byte aligned default stack, and thus we don't need to be
9028 within the re-aligned local stack frame to save them. */
9032 }
9035 /* The re-aligned stack starts here. Values before this point are not
9036 directly comparable with values below this point. In order to make
9037 sure that no value happens to be the same before and after, force
9038 the alignment computation below to add a non-zero value. */
9042 /* Va-arg area */
9046 /* Align start of frame for local function. */
9055 /* Frame pointer points here. */
9060 /* Add outgoing arguments area. Can be skipped if we eliminated
9061 all the function calls as dead code.
9062 Skipping is however impossible when function calls alloca. Alloca
9063 expander assumes that last crtl->outgoing_args_size
9064 of stack frame are unused. */
9068 {
9071 }
9072 else
9075 /* Align stack boundary. Only needed if we're calling another function
9076 or using alloca. */
9081 /* We've reached end of stack frame. */
9084 /* Size prologue needs to allocate. */
9095 {
9101 }
9102 else
9106 /* The SEH frame pointer location is near the bottom of the frame.
9107 This is enforced by the fact that the difference between the
9108 stack pointer and the frame pointer is limited to 240 bytes in
9109 the unwind data structure. */
9111 {
9112 HOST_WIDE_INT diff;
9114 /* If we can leave the frame pointer where it is, do so. Also, returns
9115 the establisher frame for __builtin_frame_address (0). */
9120 {
9121 /* Ideally we'd determine what portion of the local stack frame
9122 (within the constraint of the lowest 240) is most heavily used.
9123 But without that complication, simply bias the frame pointer
9124 by 128 bytes so as to maximize the amount of the local stack
9125 frame that is addressable with 8-bit offsets. */
9127 }
9128 }
9129 }
9131 /* This is semi-inlined memory_address_length, but simplified
9132 since we know that we're always dealing with reg+offset, and
9133 to avoid having to create and discard all that rtl. */
9137 {
9141 {
9142 /* EBP and R13 cannot be encoded without an offset. */
9144 }
9148 /* ESP and R12 must be encoded with a SIB byte. */
9150 len++;
9153 }
9155 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9156 The valid base registers are taken from CFUN->MACHINE->FS. */
9158 static rtx
9160 {
9166 {
9167 /* Choose the base register most likely to allow the most scheduling
9168 opportunities. Generally FP is valid throughout the function,
9169 while DRAP must be reloaded within the epilogue. But choose either
9170 over the SP due to increased encoding size. */
9173 {
9176 }
9178 {
9181 }
9183 {
9186 }
9187 }
9188 else
9189 {
9190 HOST_WIDE_INT toffset;
9193 /* Choose the base register with the smallest address encoding.
9194 With a tie, choose FP > DRAP > SP. */
9196 {
9200 }
9202 {
9206 {
9210 }
9211 }
9213 {
9217 {
9221 }
9222 }
9223 }
9227 }
9229 /* Emit code to save registers in the prologue. */
9231 static void
9233 {
9235 rtx insn;
9239 {
9242 }
9243 }
9245 /* Emit a single register save at CFA - CFA_OFFSET. */
9247 static void
9249 HOST_WIDE_INT cfa_offset)
9250 {
9258 /* For SSE saves, we need to indicate the 128-bit alignment. */
9269 /* When saving registers into a re-aligned local stack frame, avoid
9270 any tricky guessing by dwarf2out. */
9272 {
9276 {
9277 /* A bit of a hack. We force the DRAP register to be saved in
9278 the re-aligned stack frame, which provides us with a copy
9279 of the CFA that will last past the prologue. Install it. */
9285 }
9286 else
9287 {
9288 /* The frame pointer is a stable reference within the
9289 aligned frame. Use it. */
9296 }
9297 }
9299 /* The memory may not be relative to the current CFA register,
9300 which means that we may need to generate a new pattern for
9301 use by the unwind info. */
9303 {
9308 }
9309 }
9311 /* Emit code to save registers using MOV insns.
9312 First register is stored at CFA - CFA_OFFSET. */
9313 static void
9315 {
9320 {
9323 }
9324 }
9326 /* Emit code to save SSE registers using MOV insns.
9327 First register is stored at CFA - CFA_OFFSET. */
9328 static void
9330 {
9335 {
9338 }
9339 }
9343 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9344 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9345 Don't add the note if the previously saved value will be left untouched
9346 within stack red-zone till return, as unwinders can find the same value
9347 in the register and on the stack. */
9349 static void
9351 {
9357 {
9360 }
9361 else
9362 queued_cfa_restores
9364 }
9366 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9368 static void
9370 {
9371 rtx last;
9375 ;
9380 }
9382 /* Expand prologue or epilogue stack adjustment.
9383 The pattern exist to put a dependency on all ebp-based memory accesses.
9384 STYLE should be negative if instructions should be marked as frame related,
9385 zero if %r11 register is live and cannot be freely used and positive
9386 otherwise. */
9388 static void
9391 {
9393 rtx insn;
9400 else
9401 {
9402 rtx tmp;
9403 /* r11 is used by indirect sibcall return as well, set before the
9404 epilogue and used after the epilogue. */
9407 else
9408 {
9412 }
9418 }
9425 {
9426 rtx r;
9436 }
9438 {
9441 {
9445 }
9446 }
9449 {
9454 {
9457 }
9459 {
9462 }
9463 else
9464 {
9465 /* Else there are two possibilities: SP itself, which we set
9466 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9467 taken care of this by hand along the eh_return path. */
9470 }
9474 }
9475 }
9477 /* Find an available register to be used as dynamic realign argument
9478 pointer regsiter. Such a register will be written in prologue and
9479 used in begin of body, so it must not be
9480 1. parameter passing register.
9481 2. GOT pointer.
9482 We reuse static-chain register if it is available. Otherwise, we
9483 use DI for i386 and R13 for x86-64. We chose R13 since it has
9484 shorter encoding.
9486 Return: the regno of chosen register. */
9488 static unsigned int
9490 {
9494 {
9495 /* Use R13 for nested function or function need static chain.
9496 Since function with tail call may use any caller-saved
9497 registers in epilogue, DRAP must not use caller-saved
9498 register in such case. */
9503 }
9504 else
9505 {
9506 /* Use DI for nested function or function need static chain.
9507 Since function with tail call may use any caller-saved
9508 registers in epilogue, DRAP must not use caller-saved
9509 register in such case. */
9513 /* Reuse static chain register if it isn't used for parameter
9514 passing. */
9516 {
9520 }
9522 }
9523 }
9525 /* Return minimum incoming stack alignment. */
9527 static unsigned int
9529 {
9532 /* Prefer the one specified at command line. */
9535 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9536 if -mstackrealign is used, it isn't used for sibcall check and
9537 estimated stack alignment is 128bit. */
9539 && !TARGET_64BIT
9540 && ix86_force_align_arg_pointer
9543 else
9546 /* Incoming stack alignment can be changed on individual functions
9547 via force_align_arg_pointer attribute. We use the smallest
9548 incoming stack boundary. */
9554 /* The incoming stack frame has to be aligned at least at
9555 parm_stack_boundary. */
9559 /* Stack at entrance of main is aligned by runtime. We use the
9560 smallest incoming stack boundary. */
9568 }
9570 /* Update incoming stack boundary and estimated stack alignment. */
9572 static void
9574 {
9575 ix86_incoming_stack_boundary
9578 /* x86_64 vararg needs 16byte stack alignment for register save
9579 area. */
9584 }
9586 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9587 needed or an rtx for DRAP otherwise. */
9589 static rtx
9591 {
9596 {
9597 /* Assign DRAP to vDRAP and returns vDRAP */
9599 rtx drap_vreg;
9600 rtx arg_ptr;
9613 {
9616 }
9618 }
9619 else
9621 }
9623 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9625 static rtx
9627 {
9629 }
9632 rtx reg;
9634 };
9636 /* Return a short-lived scratch register for use on function entry.
9637 In 32-bit mode, it is valid only after the registers are saved
9638 in the prologue. This register must be released by means of
9639 release_scratch_register_on_entry once it is dead. */
9641 static void
9643 {
9649 {
9650 /* We always use R11 in 64-bit mode. */
9652 }
9653 else
9654 {
9656 bool fastcall_p
9658 bool thiscall_p
9662 int drap_regno
9665 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9666 for the static chain register. */
9670 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9671 for the static chain register. */
9676 /* ecx is the static chain register. */
9678 && !static_chain_p
9683 /* esi is the static chain register. */
9689 else
9690 {
9693 }
9694 }
9698 {
9701 }
9702 }
9704 /* Release a scratch register obtained from the preceding function. */
9706 static void
9708 {
9710 {
9714 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9720 }
9721 }
9723 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9725 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9727 static void
9729 {
9730 /* We skip the probe for the first interval + a small dope of 4 words and
9731 probe that many bytes past the specified size to maintain a protection
9732 area at the botton of the stack. */
9736 /* See if we have a constant small number of probes to generate. If so,
9737 that's the easy case. The run-time loop is made up of 11 insns in the
9738 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9739 for n # of intervals. */
9741 {
9745 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9746 values of N from 1 until it exceeds SIZE. If only one probe is
9747 needed, this will not generate any code. Then adjust and probe
9748 to PROBE_INTERVAL + SIZE. */
9750 {
9752 {
9755 }
9756 else
9763 }
9767 else
9775 /* Adjust back to account for the additional first interval. */
9779 }
9781 /* Otherwise, do the same as above, but in a loop. Note that we must be
9782 extra careful with variables wrapping around because we might be at
9783 the very top (or the very bottom) of the address space and we have
9784 to be able to handle this case properly; in particular, we use an
9785 equality test for the loop condition. */
9786 else
9787 {
9788 HOST_WIDE_INT rounded_size;
9794 /* Step 1: round SIZE to the previous multiple of the interval. */
9799 /* Step 2: compute initial and final value of the loop counter. */
9801 /* SP = SP_0 + PROBE_INTERVAL. */
9806 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9810 stack_pointer_rtx)));
9813 /* Step 3: the loop
9815 while (SP != LAST_ADDR)
9816 {
9817 SP = SP + PROBE_INTERVAL
9818 probe at SP
9819 }
9821 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9822 values of N from 1 until it is equal to ROUNDED_SIZE. */
9827 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9828 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9831 {
9836 }
9838 /* Adjust back to account for the additional first interval. */
9844 }
9848 /* Even if the stack pointer isn't the CFA register, we need to correctly
9849 describe the adjustments made to it, in particular differentiate the
9850 frame-related ones from the frame-unrelated ones. */
9852 {
9865 }
9867 /* Make sure nothing is scheduled before we are done. */
9869 }
9871 /* Adjust the stack pointer up to REG while probing it. */
9875 {
9885 /* Jump to END_LAB if SP == LAST_ADDR. */
9893 /* SP = SP + PROBE_INTERVAL. */
9897 /* Probe at SP. */
9908 }
9910 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9911 inclusive. These are offsets from the current stack pointer. */
9913 static void
9915 {
9916 /* See if we have a constant small number of probes to generate. If so,
9917 that's the easy case. The run-time loop is made up of 7 insns in the
9918 generic case while the compile-time loop is made up of n insns for n #
9919 of intervals. */
9921 {
9922 HOST_WIDE_INT i;
9924 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9925 it exceeds SIZE. If only one probe is needed, this will not
9926 generate any code. Then probe at FIRST + SIZE. */
9933 }
9935 /* Otherwise, do the same as above, but in a loop. Note that we must be
9936 extra careful with variables wrapping around because we might be at
9937 the very top (or the very bottom) of the address space and we have
9938 to be able to handle this case properly; in particular, we use an
9939 equality test for the loop condition. */
9940 else
9941 {
9948 /* Step 1: round SIZE to the previous multiple of the interval. */
9953 /* Step 2: compute initial and final value of the loop counter. */
9955 /* TEST_OFFSET = FIRST. */
9958 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
9962 /* Step 3: the loop
9964 while (TEST_ADDR != LAST_ADDR)
9965 {
9966 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
9967 probe at TEST_ADDR
9968 }
9970 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
9971 until it is equal to ROUNDED_SIZE. */
9976 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
9977 that SIZE is equal to ROUNDED_SIZE. */
9982 stack_pointer_rtx,
9987 }
9989 /* Make sure nothing is scheduled before we are done. */
9991 }
9993 /* Probe a range of stack addresses from REG to END, inclusive. These are
9994 offsets from the current stack pointer. */
9998 {
10008 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10016 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10020 /* Probe at TEST_ADDR. */
10033 }
10035 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10036 to be generated in correct form. */
10037 static void
10039 {
10040 /* Check if stack realign is really needed after reload, and
10041 stores result in cfun */
10042 unsigned int incoming_stack_boundary
10051 {
10052 /* After stack_realign_needed is finalized, we can't no longer
10053 change it. */
10056 }
10058 /* If the only reason for frame_pointer_needed is that we conservatively
10059 assumed stack realignment might be needed, but in the end nothing that
10060 needed the stack alignment had been spilled, clear frame_pointer_needed
10061 and say we don't need stack realignment. */
10064 && frame_pointer_needed
10066 && flag_omit_frame_pointer
10068 && !ix86_current_function_calls_tls_descriptor
10077 {
10079 basic_block bb;
10086 HARD_FRAME_POINTER_REGNUM);
10088 {
10089 rtx insn;
10093 set_up_by_prologue))
10094 {
10098 }
10099 }
10113 }
10117 }
10119 /* Expand the prologue into a bunch of separate insns. */
10121 void
10123 {
10128 HOST_WIDE_INT allocate;
10134 /* DRAP should not coexist with stack_realign_fp */
10139 /* Initialize CFA state for before the prologue. */
10143 /* Track SP offset to the CFA. We continue tracking this after we've
10144 swapped the CFA register away from SP. In the case of re-alignment
10145 this is fudged; we're interested to offsets within the local frame. */
10152 {
10153 /* We should have already generated an error for any use of
10154 ms_hook on a nested function. */
10157 /* Check if profiling is active and we shall use profiling before
10158 prologue variant. If so sorry. */
10163 /* In ix86_asm_output_function_label we emitted:
10164 8b ff movl.s %edi,%edi
10165 55 push %ebp
10166 8b ec movl.s %esp,%ebp
10168 This matches the hookable function prologue in Win32 API
10169 functions in Microsoft Windows XP Service Pack 2 and newer.
10170 Wine uses this to enable Windows apps to hook the Win32 API
10171 functions provided by Wine.
10173 What that means is that we've already set up the frame pointer. */
10177 {
10180 /* We've decided to use the frame pointer already set up.
10181 Describe this to the unwinder by pretending that both
10182 push and mov insns happen right here.
10184 Putting the unwind info here at the end of the ms_hook
10185 is done so that we can make absolutely certain we get
10186 the required byte sequence at the start of the function,
10187 rather than relying on an assembler that can produce
10188 the exact encoding required.
10190 However it does mean (in the unpatched case) that we have
10191 a 1 insn window where the asynchronous unwind info is
10192 incorrect. However, if we placed the unwind info at
10193 its correct location we would have incorrect unwind info
10194 in the patched case. Which is probably all moot since
10195 I don't expect Wine generates dwarf2 unwind info for the
10196 system libraries that use this feature. */
10202 stack_pointer_rtx);
10210 /* Note that gen_push incremented m->fs.cfa_offset, even
10211 though we didn't emit the push insn here. */
10215 }
10216 else
10217 {
10218 /* The frame pointer is not needed so pop %ebp again.
10219 This leaves us with a pristine state. */
10221 }
10222 }
10224 /* The first insn of a function that accepts its static chain on the
10225 stack is to push the register that would be filled in by a direct
10226 call. This insn will be skipped by the trampoline. */
10228 {
10232 /* We don't want to interpret this push insn as a register save,
10233 only as a stack adjustment. The real copy of the register as
10234 a save will be done later, if needed. */
10239 }
10241 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10242 of DRAP is needed and stack realignment is really needed after reload */
10244 {
10247 /* Only need to push parameter pointer reg if it is caller saved. */
10249 {
10250 /* Push arg pointer reg */
10253 }
10255 /* Grab the argument pointer. */
10262 /* Align the stack. */
10264 stack_pointer_rtx,
10268 /* Replicate the return address on the stack so that return
10269 address can be reached via (argp - 1) slot. This is needed
10270 to implement macro RETURN_ADDR_RTX and intrinsic function
10271 expand_builtin_return_addr etc. */
10277 /* For the purposes of frame and register save area addressing,
10278 we've started over with a new frame. */
10281 }
10287 {
10288 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10289 slower on all targets. Also sdb doesn't like it. */
10293 /* Push registers now, before setting the frame pointer
10294 on SEH target. */
10296 && TARGET_SEH
10298 {
10302 }
10305 {
10313 }
10314 }
10317 {
10318 /* If saving registers via PUSH, do so now. */
10320 {
10324 }
10326 /* When using red zone we may start register saving before allocating
10327 the stack frame saving one cycle of the prologue. However, avoid
10328 doing this if we have to probe the stack; at least on x86_64 the
10329 stack probe can turn into a call that clobbers a red zone location. */
10331 && (! TARGET_STACK_PROBE
10333 {
10336 }
10337 }
10340 {
10344 /* The computation of the size of the re-aligned stack frame means
10345 that we must allocate the size of the register save area before
10346 performing the actual alignment. Otherwise we cannot guarantee
10347 that there's enough storage above the realignment point. */
10354 /* Align the stack. */
10356 stack_pointer_rtx,
10359 /* For the purposes of register save area addressing, the stack
10360 pointer is no longer valid. As for the value of sp_offset,
10361 see ix86_compute_frame_layout, which we need to match in order
10362 to pass verification of stack_pointer_offset at the end. */
10365 }
10370 {
10371 /* We start to count from ARG_POINTER. */
10374 /* If it was realigned, take into account the fake frame. */
10376 {
10383 /* This over-estimates by 1 minimal-stack-alignment-unit but
10384 mitigates that by counting in the new return address slot. */
10385 current_function_dynamic_stack_size
10387 }
10390 }
10392 /* On SEH target with very large frame size, allocate an area to save
10393 SSE registers (as the very large allocation won't be described). */
10397 {
10398 HOST_WIDE_INT sse_size =
10403 /* No need to do stack checking as the area will be immediately
10404 written. */
10411 }
10413 /* The stack has already been decremented by the instruction calling us
10414 so probe if the size is non-negative to preserve the protection area. */
10416 {
10417 /* We expect the registers to be saved when probes are used. */
10421 {
10424 }
10425 else
10426 {
10434 else
10436 }
10437 }
10440 ;
10443 {
10447 }
10448 else
10449 {
10462 /* Note that SEH directives need to continue tracking the stack
10463 pointer even after the frame pointer has been set up. */
10465 {
10469 {
10473 }
10474 }
10477 {
10482 {
10486 }
10487 }
10492 /* Use the fact that AX still contains ALLOCATE. */
10494 ? gen_pro_epilogue_adjust_stack_di_sub
10501 {
10509 }
10513 {
10520 }
10522 {
10527 }
10528 }
10531 /* If we havn't already set up the frame pointer, do so now. */
10533 {
10545 }
10556 {
10563 }
10566 {
10568 {
10570 {
10580 label));
10584 }
10585 else
10587 }
10588 else
10589 {
10593 }
10594 }
10596 /* In the pic_reg_used case, make sure that the got load isn't deleted
10597 when mcount needs it. Blockage to avoid call movement across mcount
10598 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10599 note. */
10604 {
10605 /* vDRAP is setup but after reload it turns out stack realign
10606 isn't necessary, here we will emit prologue to setup DRAP
10607 without stack realign adjustment */
10610 }
10612 /* Prevent instructions from being scheduled into register save push
10613 sequence when access to the redzone area is done through frame pointer.
10614 The offset between the frame pointer and the stack pointer is calculated
10615 relative to the value of the stack pointer at the end of the function
10616 prologue, and moving instructions that access redzone area via frame
10617 pointer inside push sequence violates this assumption. */
10621 /* Emit cld instruction if stringops are used in the function. */
10625 /* SEH requires that the prologue end within 256 bytes of the start of
10626 the function. Prevent instruction schedules that would extend that.
10627 Further, prevent alloca modifications to the stack pointer from being
10628 combined with prologue modifications. */
10631 }
10633 /* Emit code to restore REG using a POP insn. */
10635 static void
10637 {
10646 {
10647 /* Previously we'd represented the CFA as an expression
10648 like *(%ebp - 8). We've just popped that value from
10649 the stack, which means we need to reset the CFA to
10650 the drap register. This will remain until we restore
10651 the stack pointer. */
10655 /* This means that the DRAP register is valid for addressing too. */
10658 }
10661 {
10668 }
10670 /* When the frame pointer is the CFA, and we pop it, we are
10671 swapping back to the stack pointer as the CFA. This happens
10672 for stack frames that don't allocate other data, so we assume
10673 the stack pointer is now pointing at the return address, i.e.
10674 the function entry state, which makes the offset be 1 word. */
10676 {
10679 {
10687 }
10688 }
10689 }
10691 /* Emit code to restore saved registers using POP insns. */
10693 static void
10695 {
10701 }
10703 /* Emit code and notes for the LEAVE instruction. */
10705 static void
10707 {
10719 {
10727 }
10730 }
10732 /* Emit code to restore saved registers using MOV insns.
10733 First register is restored from CFA - CFA_OFFSET. */
10734 static void
10737 {
10743 {
10752 {
10753 /* Previously we'd represented the CFA as an expression
10754 like *(%ebp - 8). We've just popped that value from
10755 the stack, which means we need to reset the CFA to
10756 the drap register. This will remain until we restore
10757 the stack pointer. */
10761 /* This means that the DRAP register is valid for addressing. */
10763 }
10764 else
10768 }
10769 }
10771 /* Emit code to restore saved registers using MOV insns.
10772 First register is restored from CFA - CFA_OFFSET. */
10773 static void
10776 {
10781 {
10783 rtx mem;
10793 }
10794 }
10796 /* Restore function stack, frame, and registers. */
10798 void
10800 {
10816 /* The FP must be valid if the frame pointer is present. */
10821 /* We must have *some* valid pointer to the stack frame. */
10824 /* The DRAP is never valid at this point. */
10827 /* See the comment about red zone and frame
10828 pointer usage in ix86_expand_prologue. */
10835 /* Determine the CFA offset of the end of the red-zone. */
10838 {
10839 /* The red-zone begins below the return address. */
10842 /* When the register save area is in the aligned portion of
10843 the stack, determine the maximum runtime displacement that
10844 matches up with the aligned frame. */
10848 }
10850 /* Special care must be taken for the normal return case of a function
10851 using eh_return: the eax and edx registers are marked as saved, but
10852 not restored along this path. Adjust the save location to match. */
10856 /* EH_RETURN requires the use of moves to function properly. */
10859 /* SEH requires the use of pops to identify the epilogue. */
10862 /* If we're only restoring one register and sp is not valid then
10863 using a move instruction to restore the register since it's
10864 less work than reloading sp and popping the register. */
10877 && TARGET_USE_LEAVE
10881 else
10885 {
10886 /* Ensure that the entire register save area is addressable via
10887 the stack pointer, if we will restore via sp. */
10892 {
10896 style,
10898 }
10899 }
10901 /* If there are any SSE registers to restore, then we have to do it
10902 via moves, since there's obviously no pop for SSE regs. */
10908 {
10909 rtx t;
10914 /* eh_return epilogues need %ecx added to the stack pointer. */
10916 {
10919 /* Stack align doesn't work with eh_return. */
10921 /* Neither does regparm nested functions. */
10925 {
10933 /* Note that we use SA as a temporary CFA, as the return
10934 address is at the proper place relative to it. We
10935 pretend this happens at the FP restore insn because
10936 prior to this insn the FP would be stored at the wrong
10937 offset relative to SA, and after this insn we have no
10938 other reasonable register to use for the CFA. We don't
10939 bother resetting the CFA to the SP for the duration of
10940 the return insn. */
10953 }
10954 else
10955 {
10963 {
10967 UNITS_PER_WORD));
10969 }
10970 }
10973 }
10974 }
10975 else
10976 {
10977 /* SEH requires that the function end with (1) a stack adjustment
10978 if necessary, (2) a sequence of pops, and (3) a return or
10979 jump instruction. Prevent insns from the function body from
10980 being scheduled into this sequence. */
10982 {
10983 /* Prevent a catch region from being adjacent to the standard
10984 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
10985 several other flags that would be interesting to test are
10986 not yet set up. */
10989 else
10991 }
10993 /* First step is to deallocate the stack frame so that we can
10994 pop the registers. Also do it on SEH target for very large
10995 frame as the emitted instructions aren't allowed by the ABI in
10996 epilogues. */
10998 || (TARGET_SEH
11001 {
11006 }
11008 {
11012 style,
11014 }
11017 }
11019 /* If we used a stack pointer and haven't already got rid of it,
11020 then do so now. */
11022 {
11023 /* If the stack pointer is valid and pointing at the frame
11024 pointer store address, then we only need a pop. */
11027 /* Leave results in shorter dependency chains on CPUs that are
11028 able to grok it fast. */
11033 else
11034 {
11036 hard_frame_pointer_rtx,
11039 }
11040 }
11043 {
11045 rtx insn;
11071 }
11073 /* At this point the stack pointer must be valid, and we must have
11074 restored all of the registers. We may not have deallocated the
11075 entire stack frame. We've delayed this until now because it may
11076 be possible to merge the local stack deallocation with the
11077 deallocation forced by ix86_static_chain_on_stack. */
11082 {
11086 }
11087 else
11090 /* Sibcall epilogues don't want a return instruction. */
11092 {
11095 }
11098 {
11101 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11102 address, do explicit add, and jump indirectly to the caller. */
11105 {
11107 rtx insn;
11109 /* There is no "pascal" calling convention in any 64bit ABI. */
11125 }
11126 else
11128 }
11129 else
11132 /* Restore the state back to the state from the prologue,
11133 so that it's correct for the next epilogue. */
11135 }
11137 /* Reset from the function's potential modifications. */
11139 static void
11141 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11142 {
11145 #if TARGET_MACHO
11146 /* Mach-O doesn't support labels at the end of objects, so if
11147 it looks like we might want one, insert a NOP. */
11148 {
11154 {
11155 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11156 notes only, instead set their CODE_LABEL_NUMBER to -1,
11157 otherwise there would be code generation differences
11158 in between -g and -g0. */
11162 }
11172 }
11173 #endif
11175 }
11177 /* Return a scratch register to use in the split stack prologue. The
11178 split stack prologue is used for -fsplit-stack. It is the first
11179 instructions in the function, even before the regular prologue.
11180 The scratch register can be any caller-saved register which is not
11181 used for parameters or for the static chain. */
11183 static unsigned int
11185 {
11188 else
11189 {
11202 {
11204 {
11208 }
11210 }
11212 {
11216 }
11218 {
11221 else
11222 {
11224 {
11228 }
11230 }
11231 }
11232 else
11233 {
11234 /* FIXME: We could make this work by pushing a register
11235 around the addition and comparison. */
11238 }
11239 }
11240 }
11242 /* A SYMBOL_REF for the function which allocates new stackspace for
11243 -fsplit-stack. */
11247 /* A SYMBOL_REF for the more stack function when using the large
11248 model. */
11252 /* Handle -fsplit-stack. These are the first instructions in the
11253 function, even before the regular prologue. */
11255 void
11257 {
11259 HOST_WIDE_INT allocate;
11264 rtx fn;
11272 /* This is the label we will branch to if we have enough stack
11273 space. We expect the basic block reordering pass to reverse this
11274 branch if optimizing, so that we branch in the unlikely case. */
11277 /* We need to compare the stack pointer minus the frame size with
11278 the stack boundary in the TCB. The stack boundary always gives
11279 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11280 can compare directly. Otherwise we need to do an addition. */
11283 UNSPEC_STACK_CHECK);
11288 else
11289 {
11291 rtx offset;
11293 /* We need a scratch register to hold the stack pointer minus
11294 the required frame size. Since this is the very start of the
11295 function, the scratch register can be any caller-saved
11296 register which is not used for parameters. */
11303 {
11304 /* We don't use ix86_gen_add3 in this case because it will
11305 want to split to lea, but when not optimizing the insn
11306 will not be split after this point. */
11309 offset)));
11310 }
11311 else
11312 {
11315 stack_pointer_rtx));
11316 }
11318 }
11324 /* Mark the jump as very likely to be taken. */
11332 /* Get more stack space. We pass in the desired stack space and the
11333 size of the arguments to copy to the new stack. In 32-bit mode
11334 we push the parameters; __morestack will return on a new stack
11335 anyhow. In 64-bit mode we pass the parameters in r10 and
11336 r11. */
11341 {
11347 /* If this function uses a static chain, it will be in %r10.
11348 Preserve it across the call to __morestack. */
11350 {
11351 rtx rax;
11356 }
11359 {
11360 HOST_WIDE_INT argval;
11363 /* When using the large model we need to load the address
11364 into a register, and we've run out of registers. So we
11365 switch to a different calling convention, and we call a
11366 different function: __morestack_large. We pass the
11367 argument size in the upper 32 bits of r10 and pass the
11368 frame size in the lower 32 bits. */
11373 split_stack_fn_large =
11377 {
11387 UNSPEC_GOT);
11393 }
11394 else
11401 }
11402 else
11403 {
11407 }
11410 }
11411 else
11412 {
11415 }
11421 /* In order to make call/return prediction work right, we now need
11422 to execute a return instruction. See
11423 libgcc/config/i386/morestack.S for the details on how this works.
11425 For flow purposes gcc must not see this as a return
11426 instruction--we need control flow to continue at the subsequent
11427 label. Therefore, we use an unspec. */
11431 /* If we are in 64-bit mode and this function uses a static chain,
11432 we saved %r10 in %rax before calling _morestack. */
11437 /* If this function calls va_start, we need to store a pointer to
11438 the arguments on the old stack, because they may not have been
11439 all copied to the new stack. At this point the old stack can be
11440 found at the frame pointer value used by __morestack, because
11441 __morestack has set that up before calling back to us. Here we
11442 store that pointer in a scratch register, and in
11443 ix86_expand_prologue we store the scratch register in a stack
11444 slot. */
11446 {
11448 rtx frame_reg;
11455 /* 64-bit:
11456 fp -> old fp value
11457 return address within this function
11458 return address of caller of this function
11459 stack arguments
11460 So we add three words to get to the stack arguments.
11462 32-bit:
11463 fp -> old fp value
11464 return address within this function
11465 first argument to __morestack
11466 second argument to __morestack
11467 return address of caller of this function
11468 stack arguments
11469 So we add five words to get to the stack arguments.
11470 */
11481 }
11486 /* If this function calls va_start, we now have to set the scratch
11487 register for the case where we do not call __morestack. In this
11488 case we need to set it based on the stack pointer. */
11490 {
11497 }
11498 }
11500 /* We may have to tell the dataflow pass that the split stack prologue
11501 is initializing a scratch register. */
11503 static void
11505 {
11507 {
11510 }
11511 }
11512 \f
11513 /* Determine if op is suitable SUBREG RTX for address. */
11515 static bool
11517 {
11528 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11529 failures when the register is one word out of a two word structure. */
11533 /* Allow only SUBREGs of non-eliminable hard registers. */
11535 }
11537 /* Extract the parts of an RTL expression that is a valid memory address
11538 for an instruction. Return 0 if the structure of the address is
11539 grossly off. Return -1 if the address contains ASHIFT, so it is not
11540 strictly valid, but still used for computing length of lea instruction. */
11542 int
11544 {
11549 rtx tmp;
11553 /* Allow zero-extended SImode addresses,
11554 they will be emitted with addr32 prefix. */
11556 {
11559 {
11563 }
11566 {
11573 }
11574 }
11576 /* Allow SImode subregs of DImode addresses,
11577 they will be emitted with addr32 prefix. */
11579 {
11582 {
11586 }
11587 }
11592 {
11595 else
11597 }
11599 {
11604 do
11605 {
11610 }
11617 {
11620 {
11645 /* FALLTHRU */
11649 && TARGET_TLS_DIRECT_SEG_REFS
11652 else
11659 /* FALLTHRU */
11666 else
11681 }
11682 }
11683 }
11685 {
11688 }
11690 {
11691 /* We're called for lea too, which implements ashift on occasion. */
11701 }
11703 {
11707 /* Constant addresses are sign extended to 64bit, we have to
11708 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11714 }
11715 else
11719 {
11721 ;
11724 ;
11725 else
11727 }
11729 /* Address override works only on the (%reg) part of %fs:(%reg). */
11735 /* Extract the integral value of scale. */
11737 {
11741 }
11746 /* Avoid useless 0 displacement. */
11750 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11755 {
11756 rtx tmp;
11759 }
11761 /* Special case: %ebp cannot be encoded as a base without a displacement.
11762 Similarly %r13. */
11764 && base_reg
11773 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11774 Avoid this by transforming to [%esi+0].
11775 Reload calls address legitimization without cfun defined, so we need
11776 to test cfun for being non-NULL. */
11782 /* Special case: encode reg+reg instead of reg*2. */
11786 /* Special case: scaling cannot be encoded without base or displacement. */
11797 }
11798 \f
11799 /* Return cost of the memory address x.
11800 For i386, it is better to use a complex address than let gcc copy
11801 the address into a reg and make a new pseudo. But not if the address
11802 requires to two regs - that would mean more pseudos with longer
11803 lifetimes. */
11804 static int
11806 addr_space_t as ATTRIBUTE_UNUSED,
11808 {
11820 /* Attempt to minimize number of registers in the address. */
11826 cost++;
11833 cost++;
11835 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11836 since it's predecode logic can't detect the length of instructions
11837 and it degenerates to vector decoded. Increase cost of such
11838 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11839 to split such addresses or even refuse such addresses at all.
11841 Following addressing modes are affected:
11842 [base+scale*index]
11843 [scale*index+disp]
11844 [base+index]
11846 The first and last case may be avoidable by explicitly coding the zero in
11847 memory address, but I don't have AMD-K6 machine handy to check this
11848 theory. */
11857 }
11858 \f
11859 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11860 this is used for to form addresses to local data when -fPIC is in
11861 use. */
11863 static bool
11865 {
11868 }
11870 /* Determine if a given RTX is a valid constant. We already know this
11871 satisfies CONSTANT_P. */
11873 static bool
11875 {
11877 {
11882 {
11886 }
11891 /* Only some unspecs are valid as "constants". */
11894 {
11910 }
11912 /* We must have drilled down to a symbol. */
11917 /* FALLTHRU */
11920 /* TLS symbols are never valid. */
11924 /* DLLIMPORT symbols are never valid. */
11929 #if TARGET_MACHO
11930 /* mdynamic-no-pic */
11933 #endif
11949 }
11951 /* Otherwise we handle everything else in the move patterns. */
11953 }
11955 /* Determine if it's legal to put X into the constant pool. This
11956 is not possible for the address of thread-local symbols, which
11957 is checked above. */
11959 static bool
11961 {
11962 /* We can always put integral constants and vectors in memory. */
11964 {
11972 }
11974 }
11977 /* Nonzero if the constant value X is a legitimate general operand
11978 when generating PIC code. It is given that flag_pic is on and
11979 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
11981 bool
11983 {
11984 rtx inner;
11987 {
11994 /* Only some unspecs are valid as "constants". */
11997 {
12010 }
12011 /* FALLTHRU */
12019 }
12020 }
12022 /* Determine if a given CONST RTX is a valid memory displacement
12023 in PIC mode. */
12025 bool
12027 {
12030 /* In 64bit mode we can allow direct addresses of symbols and labels
12031 when they are not dynamic symbols. */
12033 {
12037 {
12061 /* FALLTHRU */
12064 /* TLS references should always be enclosed in UNSPEC. */
12074 }
12075 }
12081 {
12082 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12083 of GOT tables. We should not need these anyway. */
12095 }
12099 {
12104 }
12113 {
12117 /* We need to check for both symbols and labels because VxWorks loads
12118 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12119 details. */
12123 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12124 While ABI specify also 32bit relocation but we don't produce it in
12125 small PIC model at all. */
12147 }
12150 }
12152 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12153 replace the input X, or the original X if no replacement is called for.
12154 The output parameter *WIN is 1 if the calling macro should goto WIN,
12155 0 if it should not. */
12157 bool
12162 {
12163 /* Reload can generate:
12165 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12166 (reg:DI 97))
12167 (reg:DI 2 cx))
12169 This RTX is rejected from ix86_legitimate_address_p due to
12170 non-strictness of base register 97. Following this rejection,
12171 reload pushes all three components into separate registers,
12172 creating invalid memory address RTX.
12174 Following code reloads only the invalid part of the
12175 memory address RTX. */
12181 {
12187 {
12192 }
12196 {
12201 }
12205 }
12208 }
12210 /* Recognizes RTL expressions that are valid memory addresses for an
12211 instruction. The MODE argument is the machine mode for the MEM
12212 expression that wants to use this address.
12214 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12215 convert common non-canonical forms to canonical form so that they will
12216 be recognized. */
12218 static bool
12221 {
12224 HOST_WIDE_INT scale;
12227 /* Decomposition failed. */
12235 /* Validate base register. */
12237 {
12238 rtx reg;
12244 else
12245 /* Base is not a register. */
12253 /* Base is not valid. */
12255 }
12257 /* Validate index register. */
12259 {
12260 rtx reg;
12266 else
12267 /* Index is not a register. */
12275 /* Index is not valid. */
12277 }
12279 /* Index and base should have the same mode. */
12284 /* Validate scale factor. */
12286 {
12288 /* Scale without index. */
12292 /* Scale is not a valid multiplier. */
12294 }
12296 /* Validate displacement. */
12298 {
12303 {
12304 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12305 used. While ABI specify also 32bit relocations, we don't produce
12306 them at all and use IP relative instead. */
12313 /* 64bit address unspec. */
12333 /* Invalid address unspec. */
12335 }
12338 && (flag_pic
12339 || (TARGET_MACHO
12340 #if TARGET_MACHO
12341 && MACHOPIC_INDIRECT
12343 #endif
12344 )))
12345 {
12347 is_legitimate_pic:
12349 {
12350 /* foo@dtpoff(%rX) is ok. */
12357 /* Non-constant pic memory reference. */
12359 }
12362 /* Displacement is an invalid pic construct. */
12364 #if TARGET_MACHO
12367 /* displacment must be referenced via non_lazy_pointer */
12369 #endif
12371 /* This code used to verify that a symbolic pic displacement
12372 includes the pic_offset_table_rtx register.
12374 While this is good idea, unfortunately these constructs may
12375 be created by "adds using lea" optimization for incorrect
12376 code like:
12378 int a;
12379 int foo(int i)
12380 {
12381 return *(&a+i);
12382 }
12384 This code is nonsensical, but results in addressing
12385 GOT table with pic_offset_table_rtx base. We can't
12386 just refuse it easily, since it gets matched by
12387 "addsi3" pattern, that later gets split to lea in the
12388 case output register differs from input. While this
12389 can be handled by separate addsi pattern for this case
12390 that never results in lea, this seems to be easier and
12391 correct fix for crash to disable this test. */
12392 }
12399 /* Displacement is not constant. */
12403 /* Displacement is out of range. */
12405 }
12407 /* Everything looks valid. */
12409 }
12411 /* Determine if a given RTX is a valid constant address. */
12413 bool
12415 {
12417 }
12418 \f
12419 /* Return a unique alias set for the GOT. */
12421 static alias_set_type
12423 {
12428 }
12430 /* Return a legitimate reference for ORIG (an address) using the
12431 register REG. If REG is 0, a new pseudo is generated.
12433 There are two types of references that must be handled:
12435 1. Global data references must load the address from the GOT, via
12436 the PIC reg. An insn is emitted to do this load, and the reg is
12437 returned.
12439 2. Static data references, constant pool addresses, and code labels
12440 compute the address as an offset from the GOT, whose base is in
12441 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12442 differentiate them from global data objects. The returned
12443 address is the PIC reg + an unspec constant.
12445 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12446 reg also appears in the address. */
12448 static rtx
12450 {
12454 #if TARGET_MACHO
12456 {
12459 /* Use the generic Mach-O PIC machinery. */
12461 }
12462 #endif
12469 {
12470 rtx tmpreg;
12471 /* This symbol may be referenced via a displacement from the PIC
12472 base address (@GOTOFF). */
12479 {
12481 UNSPEC_GOTOFF);
12483 }
12484 else
12489 else
12494 {
12498 }
12500 }
12502 {
12503 /* This symbol may be referenced via a displacement from the PIC
12504 base address (@GOTOFF). */
12511 {
12513 UNSPEC_GOTOFF);
12515 }
12516 else
12522 {
12525 }
12526 }
12528 /* We can't use @GOTOFF for text labels on VxWorks;
12529 see gotoff_operand. */
12531 {
12533 {
12539 {
12542 }
12543 }
12545 /* For x64 PE-COFF there is no GOT table. So we use address
12546 directly. */
12548 {
12556 }
12558 {
12566 /* Use directly gen_movsi, otherwise the address is loaded
12567 into register for CSE. We don't want to CSE this addresses,
12568 instead we CSE addresses from the GOT table, so skip this. */
12571 }
12572 else
12573 {
12574 /* This symbol must be referenced via a load from the
12575 Global Offset Table (@GOT). */
12591 }
12592 }
12593 else
12594 {
12597 {
12599 {
12602 }
12603 else
12605 }
12607 {
12610 /* We must match stuff we generate before. Assume the only
12611 unspecs that can get here are ours. Not that we could do
12612 anything with them anyway.... */
12618 }
12620 {
12623 /* Check first to see if this is a constant offset from a @GOTOFF
12624 symbol reference. */
12627 {
12629 {
12633 UNSPEC_GOTOFF);
12639 {
12642 }
12643 }
12644 else
12645 {
12648 {
12652 }
12653 }
12654 }
12655 else
12656 {
12659 new_rtx
12663 {
12666 {
12669 new_rtx
12671 }
12672 else
12674 }
12675 else
12676 {
12679 {
12682 }
12684 }
12685 }
12686 }
12687 }
12689 }
12690 \f
12691 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12693 static rtx
12695 {
12699 {
12704 }
12710 }
12712 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12716 static rtx
12718 {
12720 {
12726 }
12729 }
12731 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12735 rtx
12737 {
12739 {
12740 ix86_tls_module_base_symbol
12745 }
12748 }
12750 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12751 false if we expect this to be used for a memory address and true if
12752 we expect to load the address into a register. */
12754 static rtx
12756 {
12763 {
12768 {
12771 else
12772 {
12775 }
12776 }
12779 {
12782 else
12792 }
12793 else
12794 {
12798 {
12800 rtx insns;
12803 emit_call_insn
12813 }
12814 else
12816 }
12823 {
12826 else
12827 {
12830 }
12831 }
12834 {
12839 else
12845 }
12846 else
12847 {
12851 {
12856 emit_call_insn
12861 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12862 share the LD_BASE result with other LD model accesses. */
12864 UNSPEC_TLS_LD_BASE);
12868 }
12869 else
12871 }
12879 {
12886 }
12891 {
12893 {
12894 /* The Sun linker took the AMD64 TLS spec literally
12895 and can only handle %rax as destination of the
12896 initial executable code sequence. */
12901 }
12903 /* Generate DImode references to avoid %fs:(%reg32)
12904 problems and linker IE->LE relaxation bug. */
12908 }
12910 {
12915 }
12917 {
12921 }
12922 else
12923 {
12926 }
12936 {
12941 }
12942 else
12943 {
12947 }
12957 {
12961 }
12962 else
12963 {
12967 }
12972 }
12975 }
12977 /* Create or return the unique __imp_DECL dllimport symbol corresponding
12978 to symbol DECL. */
12981 htab_t dllimport_map;
12983 static tree
12985 {
12992 tree to;
12993 rtx rtl;
13037 }
13039 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13040 true if we require the result be a register. */
13042 static rtx
13044 {
13045 tree imp_decl;
13046 rtx x;
13055 }
13057 /* Try machine-dependent ways of modifying an illegitimate address
13058 to be legitimate. If we find one, return the new, valid address.
13059 This macro is used in only one place: `memory_address' in explow.c.
13061 OLDX is the address as it was before break_out_memory_refs was called.
13062 In some cases it is useful to look at this to decide what needs to be done.
13064 It is always safe for this macro to do nothing. It exists to recognize
13065 opportunities to optimize the output.
13067 For the 80386, we handle X+REG by loading X into a register R and
13068 using R+REG. R will go in a general reg and indexing will be used.
13069 However, if REG is a broken-out memory address or multiplication,
13070 nothing needs to be done because REG can certainly go in a general reg.
13072 When -fpic is used, special handling is needed for symbolic references.
13073 See comments by legitimize_pic_address in i386.c for details. */
13075 static rtx
13078 {
13089 {
13093 }
13096 {
13103 {
13106 }
13107 }
13112 #if TARGET_MACHO
13115 #endif
13117 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13121 {
13126 }
13129 {
13130 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13135 {
13141 }
13146 {
13152 }
13154 /* Put multiply first if it isn't already. */
13156 {
13161 }
13163 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13164 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13165 created by virtual register instantiation, register elimination, and
13166 similar optimizations. */
13168 {
13174 }
13176 /* Canonicalize
13177 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13178 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13183 {
13184 rtx constant;
13188 {
13191 }
13193 {
13196 }
13197 else
13201 {
13208 }
13209 }
13215 {
13218 }
13221 {
13224 }
13232 {
13235 }
13241 {
13245 {
13249 }
13253 }
13256 {
13260 {
13264 }
13268 }
13269 }
13272 }
13273 \f
13274 /* Print an integer constant expression in assembler syntax. Addition
13275 and subtraction are the only arithmetic that may appear in these
13276 expressions. FILE is the stdio stream to write to, X is the rtx, and
13277 CODE is the operand print code from the output string. */
13279 static void
13281 {
13285 {
13294 else
13295 {
13298 /* Mark the decl as referenced so that cgraph will
13299 output the function. */
13303 #if TARGET_MACHO
13307 #endif
13309 }
13317 /* FALLTHRU */
13328 /* This used to output parentheses around the expression,
13329 but that does not work on the 386 (either ATT or BSD assembler). */
13335 {
13336 /* We can use %d if the number is <32 bits and positive. */
13341 else
13343 }
13344 else
13345 /* We can't handle floating point constants;
13346 TARGET_PRINT_OPERAND must handle them. */
13351 /* Some assemblers need integer constants to appear first. */
13353 {
13357 }
13358 else
13359 {
13364 }
13379 {
13383 }
13388 {
13407 /* FIXME: This might be @TPOFF in Sun ld too. */
13416 else
13426 else
13432 #if TARGET_MACHO
13437 #endif
13441 }
13446 }
13447 }
13449 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13450 We need to emit DTP-relative relocations. */
13452 static void ATTRIBUTE_UNUSED
13454 {
13459 {
13467 }
13468 }
13470 /* Return true if X is a representation of the PIC register. This copes
13471 with calls from ix86_find_base_term, where the register might have
13472 been replaced by a cselib value. */
13474 static bool
13476 {
13480 else
13482 }
13484 /* Helper function for ix86_delegitimize_address.
13485 Attempt to delegitimize TLS local-exec accesses. */
13487 static rtx
13489 {
13514 {
13519 }
13525 }
13527 /* In the name of slightly smaller debug output, and to cater to
13528 general assembler lossage, recognize PIC+GOTOFF and turn it back
13529 into a direct symbol reference.
13531 On Darwin, this is necessary to avoid a crash, because Darwin
13532 has a different PIC label for each routine but the DWARF debugging
13533 information is not associated with any particular routine, so it's
13534 necessary to remove references to the PIC label from RTL stored by
13535 the DWARF output code. */
13537 static rtx
13539 {
13541 /* addend is NULL or some rtx if x is something+GOTOFF where
13542 something doesn't include the PIC register. */
13544 /* reg_addend is NULL or a multiple of some register. */
13546 /* const_addend is NULL or a const_int. */
13548 /* This is the result, or NULL. */
13557 {
13564 {
13570 }
13579 {
13584 }
13586 }
13593 /* %ebx + GOT/GOTOFF */
13594 ;
13596 {
13597 /* %ebx + %reg * scale + GOT/GOTOFF */
13603 else
13604 {
13607 }
13608 }
13609 else
13615 {
13618 }
13637 {
13638 /* If the rest of original X doesn't involve the PIC register, add
13639 addend and subtract pic_offset_table_rtx. This can happen e.g.
13640 for code like:
13641 leal (%ebx, %ecx, 4), %ecx
13642 ...
13643 movl foo@GOTOFF(%ecx), %edx
13644 in which case we return (%ecx - %ebx) + foo. */
13647 pic_offset_table_rtx),
13648 result);
13649 else
13651 }
13653 {
13657 }
13659 }
13661 /* If X is a machine specific address (i.e. a symbol or label being
13662 referenced as a displacement from the GOT implemented using an
13663 UNSPEC), then return the base term. Otherwise return X. */
13665 rtx
13667 {
13668 rtx term;
13671 {
13685 }
13688 }
13689 \f
13690 static void
13693 {
13697 {
13700 }
13705 {
13708 {
13727 }
13731 {
13750 }
13757 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13758 Those same assemblers have the same but opposite lossage on cmov. */
13763 else
13768 {
13781 }
13789 {
13802 }
13805 /* ??? As above. */
13814 /* ??? As above. */
13819 else
13830 }
13832 }
13834 /* Print the name of register X to FILE based on its machine mode and number.
13835 If CODE is 'w', pretend the mode is HImode.
13836 If CODE is 'b', pretend the mode is QImode.
13837 If CODE is 'k', pretend the mode is SImode.
13838 If CODE is 'q', pretend the mode is DImode.
13839 If CODE is 'x', pretend the mode is V4SFmode.
13840 If CODE is 't', pretend the mode is V8SFmode.
13841 If CODE is 'h', pretend the reg is the 'high' byte register.
13842 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13843 If CODE is 'd', duplicate the operand for AVX instruction.
13844 */
13846 void
13848 {
13857 {
13861 }
13886 else
13889 /* Irritatingly, AMD extended registers use different naming convention
13890 from the normal registers: "r%d[bwd]" */
13892 {
13897 {
13911 /* no suffix */
13916 }
13918 }
13922 {
13925 {
13928 }
13929 /* FALLTHRU */
13935 /* FALLTHRU */
13938 normal:
13953 {
13958 }
13962 }
13966 {
13969 else
13971 }
13972 }
13974 /* Locate some local-dynamic symbol still in use by this function
13975 so that we can print its name in some tls_local_dynamic_base
13976 pattern. */
13978 static int
13980 {
13985 {
13988 }
13991 }
13995 {
13996 rtx insn;
14007 }
14009 /* Meaning of CODE:
14010 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14011 C -- print opcode suffix for set/cmov insn.
14012 c -- like C, but print reversed condition
14013 F,f -- likewise, but for floating-point.
14014 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14015 otherwise nothing
14016 R -- print the prefix for register names.
14017 z -- print the opcode suffix for the size of the current operand.
14018 Z -- likewise, with special suffixes for x87 instructions.
14019 * -- print a star (in certain assembler syntax)
14020 A -- print an absolute memory reference.
14021 E -- print address with DImode register names if TARGET_64BIT.
14022 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14023 s -- print a shift double count, followed by the assemblers argument
14024 delimiter.
14025 b -- print the QImode name of the register for the indicated operand.
14026 %b0 would print %al if operands[0] is reg 0.
14027 w -- likewise, print the HImode name of the register.
14028 k -- likewise, print the SImode name of the register.
14029 q -- likewise, print the DImode name of the register.
14030 x -- likewise, print the V4SFmode name of the register.
14031 t -- likewise, print the V8SFmode name of the register.
14032 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14033 y -- print "st(0)" instead of "st" as a register.
14034 d -- print duplicated register operand for AVX instruction.
14035 D -- print condition for SSE cmp instruction.
14036 P -- if PIC, print an @PLT suffix.
14037 p -- print raw symbol name.
14038 X -- don't print any sort of PIC '@' suffix for a symbol.
14039 & -- print some in-use local-dynamic symbol name.
14040 H -- print a memory address offset by 8; used for sse high-parts
14041 Y -- print condition for XOP pcom* instruction.
14042 + -- print a branch hint as 'cs' or 'ds' prefix
14043 ; -- print a semicolon (after prefixes due to bug in older gas).
14044 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14045 @ -- print a segment register of thread base pointer load
14046 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14047 */
14049 void
14051 {
14053 {
14055 {
14058 {
14064 /* Intel syntax. For absolute addresses, registers should not
14065 be surrounded by braces. */
14067 {
14072 }
14077 }
14083 /* Wrap address in an UNSPEC to declare special handling. */
14121 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14126 {
14140 output_operand_lossage
14143 }
14146 #endif
14151 {
14152 /* Opcodes don't get size suffixes if using Intel opcodes. */
14157 {
14175 output_operand_lossage
14178 }
14179 }
14182 warning
14184 /* FALLTHRU */
14187 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14192 {
14194 {
14196 #ifdef HAVE_AS_IX86_FILDS
14198 #endif
14206 #ifdef HAVE_AS_IX86_FILDQ
14208 #else
14210 #endif
14215 }
14216 }
14218 {
14219 /* 387 opcodes don't get size suffixes
14220 if the operands are registers. */
14225 {
14241 }
14242 }
14243 else
14244 {
14245 output_operand_lossage
14248 }
14250 output_operand_lossage
14270 {
14273 }
14278 {
14329 }
14333 /* Little bit of braindamage here. The SSE compare instructions
14334 does use completely different names for the comparisons that the
14335 fp conditional moves. */
14337 {
14340 {
14343 }
14349 {
14352 }
14358 {
14361 }
14370 {
14373 }
14379 {
14382 }
14388 {
14391 }
14402 }
14407 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14410 #endif
14415 {
14419 }
14423 file);
14428 {
14432 }
14433 /* It doesn't actually matter what mode we use here, as we're
14434 only going to use this for printing. */
14442 #ifdef HAVE_AS_IX86_HLE
14444 #else
14446 #endif
14448 #ifdef HAVE_AS_IX86_HLE
14450 #else
14452 #endif
14453 /* We do not want to print value of the operand. */
14462 {
14467 else
14470 }
14473 {
14474 rtx x;
14483 {
14488 {
14490 bool cputaken
14493 /* Emit hints only in the case default branch prediction
14494 heuristics would fail. */
14496 {
14497 /* We use 3e (DS) prefix for taken branches and
14498 2e (CS) prefix for not taken branches. */
14501 else
14503 }
14504 }
14505 }
14507 }
14510 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14512 #endif
14519 /* The kernel uses a different segment register for performance
14520 reasons; a system call would not have to trash the userspace
14521 segment register, which would be expensive. */
14524 else
14539 }
14540 }
14546 {
14547 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14550 {
14553 {
14562 else
14568 }
14570 /* Check for explicit size override (codes 'b', 'w', 'k',
14571 'q' and 'x') */
14585 }
14588 /* Avoid (%rip) for call operands. */
14594 else
14596 }
14599 {
14600 REAL_VALUE_TYPE r;
14608 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14611 else
14613 }
14616 {
14617 REAL_VALUE_TYPE r;
14626 }
14628 /* These float cases don't actually occur as immediate operands. */
14630 {
14635 }
14637 else
14638 {
14639 /* We have patterns that allow zero sets of memory, for instance.
14640 In 64-bit mode, we should probably support all 8-byte vectors,
14641 since we can in fact encode that into an immediate. */
14643 {
14646 }
14649 {
14651 {
14654 }
14657 {
14660 else
14662 }
14663 }
14668 else
14670 }
14671 }
14673 static bool
14675 {
14678 }
14679 \f
14680 /* Print a memory operand whose address is ADDR. */
14682 static void
14684 {
14693 {
14700 }
14702 {
14706 }
14707 else
14718 {
14729 }
14731 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14733 {
14745 }
14747 {
14748 /* Displacement only requires special attention. */
14751 {
14755 }
14758 else
14760 }
14761 else
14762 {
14763 /* Print SImode register names to force addr32 prefix. */
14765 {
14766 #ifdef ENABLE_CHECKING
14769 {
14780 }
14781 #endif
14784 }
14786 && TARGET_X32
14787 && disp
14790 {
14791 /* X32 runs in 64-bit mode, where displacement, DISP, in
14792 address DISP(%r64), is encoded as 32-bit immediate sign-
14793 extended from 32-bit to 64-bit. For -0x40000300(%r64),
14794 address is %r64 + 0xffffffffbffffd00. When %r64 <
14795 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
14796 which is invalid for x32. The correct address is %r64
14797 - 0x40000300 == 0xf7ffdd64. To properly encode
14798 -0x40000300(%r64) for x32, we zero-extend negative
14799 displacement by forcing addr32 prefix which truncates
14800 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
14801 zero-extend all negative displacements, including -1(%rsp).
14802 However, for small negative displacements, sign-extension
14803 won't cause overflow. We only zero-extend negative
14804 displacements if they < -16*1024*1024, which is also used
14805 to check legitimate address displacements for PIC. */
14807 }
14810 {
14812 {
14817 else
14819 }
14825 {
14830 }
14832 }
14833 else
14834 {
14838 {
14839 /* Pull out the offset of a symbol; print any symbol itself. */
14843 {
14847 }
14855 else
14857 }
14861 {
14864 {
14868 }
14869 }
14872 else
14876 {
14881 }
14883 }
14884 }
14885 }
14887 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14889 static bool
14891 {
14892 rtx op;
14899 {
14902 /* FIXME: This might be @TPOFF in Sun ld. */
14913 else
14925 else
14932 #if TARGET_MACHO
14938 #endif
14941 {
14946 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14948 #else
14950 #endif
14953 }
14958 }
14961 }
14962 \f
14963 /* Split one or more double-mode RTL references into pairs of half-mode
14964 references. The RTL can be REG, offsettable MEM, integer constant, or
14965 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14966 split and "num" is its length. lo_half and hi_half are output arrays
14967 that parallel "operands". */
14969 void
14972 {
14977 {
14986 }
14991 {
14994 /* simplify_subreg refuse to split volatile memory addresses,
14995 but we still have to handle it. */
14997 {
15000 }
15001 else
15002 {
15009 }
15010 }
15011 }
15012 \f
15013 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15014 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15015 is the expression of the binary operation. The output may either be
15016 emitted here, or returned to the caller, like all output_* functions.
15018 There is no guarantee that the operands are the same mode, as they
15019 might be within FLOAT or FLOAT_EXTEND expressions. */
15021 #ifndef SYSV386_COMPAT
15022 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15023 wants to fix the assemblers because that causes incompatibility
15024 with gcc. No-one wants to fix gcc because that causes
15025 incompatibility with assemblers... You can use the option of
15026 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15027 #define SYSV386_COMPAT 1
15028 #endif
15032 {
15038 #ifdef ENABLE_CHECKING
15039 /* Even if we do not want to check the inputs, this documents input
15040 constraints. Which helps in understanding the following code. */
15050 else
15052 #endif
15055 {
15060 else
15069 else
15078 else
15087 else
15094 }
15097 {
15099 {
15103 else
15105 }
15106 else
15107 {
15111 else
15113 }
15115 }
15119 {
15123 {
15127 }
15129 /* know operands[0] == operands[1]. */
15132 {
15135 }
15138 {
15140 /* How is it that we are storing to a dead operand[2]?
15141 Well, presumably operands[1] is dead too. We can't
15142 store the result to st(0) as st(0) gets popped on this
15143 instruction. Instead store to operands[2] (which I
15144 think has to be st(1)). st(1) will be popped later.
15145 gcc <= 2.8.1 didn't have this check and generated
15146 assembly code that the Unixware assembler rejected. */
15148 else
15151 }
15155 else
15162 {
15165 }
15168 {
15171 }
15174 {
15175 #if SYSV386_COMPAT
15176 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15177 derived assemblers, confusingly reverse the direction of
15178 the operation for fsub{r} and fdiv{r} when the
15179 destination register is not st(0). The Intel assembler
15180 doesn't have this brain damage. Read !SYSV386_COMPAT to
15181 figure out what the hardware really does. */
15184 else
15186 #else
15188 /* As above for fmul/fadd, we can't store to st(0). */
15190 else
15192 #endif
15194 }
15197 {
15198 #if SYSV386_COMPAT
15201 else
15203 #else
15206 else
15208 #endif
15210 }
15213 {
15216 else
15219 }
15221 {
15222 #if SYSV386_COMPAT
15224 #else
15226 #endif
15227 }
15228 else
15229 {
15230 #if SYSV386_COMPAT
15232 #else
15234 #endif
15235 }
15240 }
15244 }
15246 /* Check if a 256bit AVX register is referenced inside of EXP. */
15248 static int
15250 {
15261 }
15263 /* Return needed mode for entity in optimize_mode_switching pass. */
15265 static int
15267 {
15269 {
15270 rtx link;
15272 /* Needed mode is set to AVX_U128_CLEAN if there are
15273 no 256bit modes used in function arguments. */
15275 link;
15277 {
15279 {
15284 }
15285 }
15288 }
15290 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15291 changes state only when a 256bit register is written to, but we need
15292 to prevent the compiler from moving optimal insertion point above
15293 eventual read from 256bit register. */
15298 }
15300 /* Return mode that i387 must be switched into
15301 prior to the execution of insn. */
15303 static int
15305 {
15308 /* The mode UNINITIALIZED is used to store control word after a
15309 function call or ASM pattern. The mode ANY specify that function
15310 has no requirements on the control word and make no changes in the
15311 bits we are interested in. */
15325 {
15348 }
15351 }
15353 /* Return mode that entity must be switched into
15354 prior to the execution of insn. */
15356 int
15358 {
15360 {
15370 }
15372 }
15374 /* Check if a 256bit AVX register is referenced in stores. */
15376 static void
15378 {
15380 {
15383 }
15384 }
15386 /* Calculate mode of upper 128bit AVX registers after the insn. */
15388 static int
15390 {
15397 /* We know that state is clean after CALL insn if there are no
15398 256bit registers used in the function return register. */
15400 {
15405 }
15407 /* Otherwise, return current mode. Remember that if insn
15408 references AVX 256bit registers, the mode was already changed
15409 to DIRTY from MODE_NEEDED. */
15411 }
15413 /* Return the mode that an insn results in. */
15415 int
15417 {
15419 {
15429 }
15430 }
15432 static int
15434 {
15435 tree arg;
15437 /* Entry mode is set to AVX_U128_DIRTY if there are
15438 256bit modes used in function arguments. */
15441 {
15446 }
15449 }
15451 /* Return a mode that ENTITY is assumed to be
15452 switched to at function entry. */
15454 int
15456 {
15458 {
15468 }
15469 }
15471 static int
15473 {
15476 /* Exit mode is set to AVX_U128_DIRTY if there are
15477 256bit modes used in the function return register. */
15482 }
15484 /* Return a mode that ENTITY is assumed to be
15485 switched to at function exit. */
15487 int
15489 {
15491 {
15501 }
15502 }
15504 /* Output code to initialize control word copies used by trunc?f?i and
15505 rounding patterns. CURRENT_MODE is set to current control word,
15506 while NEW_MODE is set to new control word. */
15508 static void
15510 {
15512 rtx new_mode;
15523 {
15525 {
15527 /* round toward zero (truncate) */
15533 /* round down toward -oo */
15540 /* round up toward +oo */
15547 /* mask precision exception for nearbyint() */
15554 }
15555 }
15556 else
15557 {
15559 {
15561 /* round toward zero (truncate) */
15567 /* round down toward -oo */
15573 /* round up toward +oo */
15579 /* mask precision exception for nearbyint() */
15586 }
15587 }
15593 }
15595 /* Emit vzeroupper. */
15597 void
15599 {
15602 /* Cancel automatic vzeroupper insertion if there are
15603 live call-saved SSE registers at the insertion point. */
15615 }
15617 /* Generate one or more insns to set ENTITY to MODE. */
15619 void
15621 {
15623 {
15638 }
15639 }
15641 /* Output code for INSN to convert a float to a signed int. OPERANDS
15642 are the insn operands. The output may be [HSD]Imode and the input
15643 operand may be [SDX]Fmode. */
15647 {
15652 /* Jump through a hoop or two for DImode, since the hardware has no
15653 non-popping instruction. We used to do this a different way, but
15654 that was somewhat fragile and broke with post-reload splitters. */
15664 else
15665 {
15670 else
15674 }
15677 }
15679 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15680 have the values zero or one, indicates the ffreep insn's operand
15681 from the OPERANDS array. */
15685 {
15687 #ifdef HAVE_AS_IX86_FFREEP
15689 #else
15690 {
15700 }
15701 #endif
15704 }
15707 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15708 should be used. UNORDERED_P is true when fucom should be used. */
15712 {
15718 {
15721 }
15722 else
15723 {
15726 }
15729 {
15733 else
15735 else
15738 else
15740 }
15747 {
15749 {
15752 }
15753 else
15755 }
15758 && stack_top_dies
15761 {
15762 /* If both the top of the 387 stack dies, and the other operand
15763 is also a stack register that dies, then this must be a
15764 `fcompp' float compare */
15767 {
15768 /* There is no double popping fcomi variant. Fortunately,
15769 eflags is immune from the fstp's cc clobbering. */
15772 else
15775 }
15776 else
15777 {
15780 else
15782 }
15783 }
15784 else
15785 {
15786 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15789 {
15797 NULL,
15798 NULL,
15805 NULL,
15806 NULL,
15807 NULL,
15808 NULL
15809 };
15824 }
15825 }
15827 void
15829 {
15832 #ifdef ASM_QUAD
15835 #else
15837 #endif
15840 }
15842 void
15844 {
15847 #ifdef ASM_QUAD
15850 #else
15852 #endif
15853 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15859 #if TARGET_MACHO
15861 {
15865 }
15866 #endif
15867 else
15870 }
15871 \f
15872 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15873 for the target. */
15875 void
15877 {
15878 rtx tmp;
15880 /* We play register width games, which are only valid after reload. */
15883 /* Avoid HImode and its attendant prefix byte. */
15888 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15890 {
15893 }
15896 }
15898 /* X is an unchanging MEM. If it is a constant pool reference, return
15899 the constant pool rtx, else NULL. */
15901 rtx
15903 {
15910 }
15912 void
15914 {
15922 {
15925 {
15932 }
15936 }
15940 {
15953 {
15961 }
15962 }
15966 {
15968 {
15969 #if TARGET_MACHO
15970 /* dynamic-no-pic */
15972 {
15973 rtx temp = ((reload_in_progress
15981 }
15983 {
15987 }
15990 else
15991 {
15999 }
16000 /* dynamic-no-pic */
16001 #endif
16002 }
16003 else
16004 {
16008 {
16015 }
16016 }
16017 }
16018 else
16019 {
16030 /* Force large constants in 64bit compilation into register
16031 to get them CSEed. */
16043 {
16044 /* If we are loading a floating point constant to a register,
16045 force the value to memory now, since we'll get better code
16046 out the back end. */
16050 {
16055 }
16056 }
16057 }
16060 }
16062 void
16064 {
16068 /* Force constants other than zero into memory. We do not know how
16069 the instructions used to build constants modify the upper 64 bits
16070 of the register, once we have that information we may be able
16071 to handle some of them more efficiently. */
16080 /* We need to check memory alignment for SSE mode since attribute
16081 can make operands unaligned. */
16086 {
16089 /* ix86_expand_vector_move_misalign() does not like constants ... */
16095 /* ... nor both arguments in memory. */
16103 }
16105 /* Make operand1 a register if it isn't already. */
16109 {
16112 }
16115 }
16117 /* Split 32-byte AVX unaligned load and store if needed. */
16119 static void
16121 {
16122 rtx m;
16129 {
16150 }
16153 {
16155 {
16162 }
16163 else
16165 }
16167 {
16169 {
16174 }
16175 else
16177 }
16178 else
16180 }
16182 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16183 straight to ix86_expand_vector_move. */
16184 /* Code generation for scalar reg-reg moves of single and double precision data:
16185 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16186 movaps reg, reg
16187 else
16188 movss reg, reg
16189 if (x86_sse_partial_reg_dependency == true)
16190 movapd reg, reg
16191 else
16192 movsd reg, reg
16194 Code generation for scalar loads of double precision data:
16195 if (x86_sse_split_regs == true)
16196 movlpd mem, reg (gas syntax)
16197 else
16198 movsd mem, reg
16200 Code generation for unaligned packed loads of single precision data
16201 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16202 if (x86_sse_unaligned_move_optimal)
16203 movups mem, reg
16205 if (x86_sse_partial_reg_dependency == true)
16206 {
16207 xorps reg, reg
16208 movlps mem, reg
16209 movhps mem+8, reg
16210 }
16211 else
16212 {
16213 movlps mem, reg
16214 movhps mem+8, reg
16215 }
16217 Code generation for unaligned packed loads of double precision data
16218 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16219 if (x86_sse_unaligned_move_optimal)
16220 movupd mem, reg
16222 if (x86_sse_split_regs == true)
16223 {
16224 movlpd mem, reg
16225 movhpd mem+8, reg
16226 }
16227 else
16228 {
16229 movsd mem, reg
16230 movhpd mem+8, reg
16231 }
16232 */
16234 void
16236 {
16244 {
16246 {
16251 /* FALLTHRU */
16259 }
16262 }
16265 {
16266 /* ??? If we have typed data, then it would appear that using
16267 movdqu is the only way to get unaligned data loaded with
16268 integer type. */
16270 {
16273 /* We will eventually emit movups based on insn attributes. */
16275 }
16277 {
16278 rtx zero;
16281 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16282 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16284 {
16285 /* We will eventually emit movups based on insn attributes. */
16288 }
16290 /* When SSE registers are split into halves, we can avoid
16291 writing to the top half twice. */
16293 {
16296 }
16297 else
16298 {
16299 /* ??? Not sure about the best option for the Intel chips.
16300 The following would seem to satisfy; the register is
16301 entirely cleared, breaking the dependency chain. We
16302 then store to the upper half, with a dependency depth
16303 of one. A rumor has it that Intel recommends two movsd
16304 followed by an unpacklpd, but this is unconfirmed. And
16305 given that the dependency depth of the unpacklpd would
16306 still be one, I'm not sure why this would be better. */
16308 }
16314 }
16315 else
16316 {
16318 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16319 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16321 {
16326 }
16330 else
16340 }
16341 }
16343 {
16345 {
16348 /* We will eventually emit movups based on insn attributes. */
16350 }
16352 {
16354 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16355 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16357 /* We will eventually emit movups based on insn attributes. */
16359 else
16360 {
16365 }
16366 }
16367 else
16368 {
16373 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16374 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16376 {
16379 }
16380 else
16381 {
16386 }
16387 }
16388 }
16389 else
16391 }
16393 /* Expand a push in MODE. This is some mode for which we do not support
16394 proper push instructions, at least from the registers that we expect
16395 the value to live in. */
16397 void
16399 {
16400 rtx tmp;
16410 /* When we push an operand onto stack, it has to be aligned at least
16411 at the function argument boundary. However since we don't have
16412 the argument type, we can't determine the actual argument
16413 boundary. */
16415 }
16417 /* Helper function of ix86_fixup_binary_operands to canonicalize
16418 operand order. Returns true if the operands should be swapped. */
16420 static bool
16422 rtx operands[])
16423 {
16428 /* If the operation is not commutative, we can't do anything. */
16432 /* Highest priority is that src1 should match dst. */
16438 /* Next highest priority is that immediate constants come second. */
16444 /* Lowest priority is that memory references should come second. */
16451 }
16454 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16455 destination to use for the operation. If different from the true
16456 destination in operands[0], a copy operation will be required. */
16458 rtx
16460 rtx operands[])
16461 {
16466 /* Canonicalize operand order. */
16468 {
16469 rtx temp;
16471 /* It is invalid to swap operands of different modes. */
16477 }
16479 /* Both source operands cannot be in memory. */
16481 {
16482 /* Optimization: Only read from memory once. */
16484 {
16487 }
16488 else
16490 }
16492 /* If the destination is memory, and we do not have matching source
16493 operands, do things in registers. */
16497 /* Source 1 cannot be a constant. */
16501 /* Source 1 cannot be a non-matching memory. */
16505 /* Improve address combine. */
16514 }
16516 /* Similarly, but assume that the destination has already been
16517 set up properly. */
16519 void
16522 {
16525 }
16527 /* Attempt to expand a binary operator. Make the expansion closer to the
16528 actual machine, then just general_operand, which will allow 3 separate
16529 memory references (one output, two input) in a single insn. */
16531 void
16533 rtx operands[])
16534 {
16541 /* Emit the instruction. */
16545 {
16546 /* Reload doesn't know about the flags register, and doesn't know that
16547 it doesn't want to clobber it. We can only do this with PLUS. */
16550 }
16554 {
16555 /* This is going to be an LEA; avoid splitting it later. */
16557 }
16558 else
16559 {
16562 }
16564 /* Fix up the destination if needed. */
16567 }
16569 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16570 the given OPERANDS. */
16572 void
16574 rtx operands[])
16575 {
16578 {
16581 }
16583 {
16586 }
16587 /* Optimize (__m128i) d | (__m128i) e and similar code
16588 when d and e are float vectors into float vector logical
16589 insn. In C/C++ without using intrinsics there is no other way
16590 to express vector logical operation on float vectors than
16591 to cast them temporarily to integer vectors. */
16593 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16602 {
16603 rtx dst;
16605 {
16612 {
16615 }
16616 else
16617 {
16622 }
16633 }
16634 }
16643 }
16645 /* Return TRUE or FALSE depending on whether the binary operator meets the
16646 appropriate constraints. */
16648 bool
16651 {
16656 /* Both source operands cannot be in memory. */
16660 /* Canonicalize operand order for commutative operators. */
16662 {
16666 }
16668 /* If the destination is memory, we must have a matching source operand. */
16672 /* Source 1 cannot be a constant. */
16676 /* Source 1 cannot be a non-matching memory. */
16678 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16686 }
16688 /* Attempt to expand a unary operator. Make the expansion closer to the
16689 actual machine, then just general_operand, which will allow 2 separate
16690 memory references (one output, one input) in a single insn. */
16692 void
16694 rtx operands[])
16695 {
16702 /* If the destination is memory, and we do not have matching source
16703 operands, do things in registers. */
16706 {
16709 else
16711 }
16713 /* When source operand is memory, destination must match. */
16717 /* Emit the instruction. */
16721 {
16722 /* Reload doesn't know about the flags register, and doesn't know that
16723 it doesn't want to clobber it. */
16726 }
16727 else
16728 {
16731 }
16733 /* Fix up the destination if needed. */
16736 }
16738 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16739 divisor are within the range [0-255]. */
16741 void
16744 {
16753 {
16766 }
16773 /* Use 8bit unsigned divimod if dividend and divisor are within
16774 the range [0-255]. */
16783 pc_rtx);
16788 /* Generate original signed/unsigned divimod. */
16793 /* Branch to the end. */
16797 /* Generate 8bit unsigned divide. */
16799 /* Don't use operands[0] for result of 8bit divide since not all
16800 registers support QImode ZERO_EXTRACT. */
16807 {
16810 }
16811 else
16812 {
16815 }
16817 /* Extract remainder from AH. */
16821 else
16822 {
16823 /* Need a new scratch register since the old one has result
16824 of 8bit divide. */
16828 }
16831 /* Zero extend quotient from AL. */
16837 }
16839 #define LEA_MAX_STALL (3)
16840 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16842 /* Increase given DISTANCE in half-cycles according to
16843 dependencies between PREV and NEXT instructions.
16844 Add 1 half-cycle if there is no dependency and
16845 go to next cycle if there is some dependecy. */
16847 static unsigned int
16849 {
16866 }
16868 /* Function checks if instruction INSN defines register number
16869 REGNO1 or REGNO2. */
16871 static bool
16873 rtx insn)
16874 {
16882 {
16884 }
16887 }
16889 /* Function checks if instruction INSN uses register number
16890 REGNO as a part of address expression. */
16892 static bool
16894 {
16902 }
16904 /* Search backward for non-agu definition of register number REGNO1
16905 or register number REGNO2 in basic block starting from instruction
16906 START up to head of basic block or instruction INSN.
16908 Function puts true value into *FOUND var if definition was found
16909 and false otherwise.
16911 Distance in half-cycles between START and found instruction or head
16912 of BB is added to DISTANCE and returned. */
16914 static int
16918 {
16928 {
16930 {
16933 {
16936 {
16939 }
16940 }
16943 }
16948 }
16951 }
16953 /* Search backward for non-agu definition of register number REGNO1
16954 or register number REGNO2 in INSN's basic block until
16955 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16956 2. Reach neighbour BBs boundary, or
16957 3. Reach agu definition.
16958 Returns the distance between the non-agu definition point and INSN.
16959 If no definition point, returns -1. */
16961 static int
16963 rtx insn)
16964 {
16975 {
16976 edge e;
16977 edge_iterator ei;
16982 {
16985 }
16991 else
16992 {
16997 {
16998 int bb_dist
17004 {
17011 }
17012 }
17015 }
17016 }
17018 /* get_attr_type may modify recog data. We want to make sure
17019 that recog data is valid for instruction INSN, on which
17020 distance_non_agu_define is called. INSN is unchanged here. */
17027 }
17029 /* Return the distance in half-cycles between INSN and the next
17030 insn that uses register number REGNO in memory address added
17031 to DISTANCE. Return -1 if REGNO0 is set.
17033 Put true value into *FOUND if register usage was found and
17034 false otherwise.
17035 Put true value into *REDEFINED if register redefinition was
17036 found and false otherwise. */
17038 static int
17042 {
17053 {
17055 {
17058 {
17059 /* Return DISTANCE if OP0 is used in memory
17060 address in NEXT. */
17063 }
17066 {
17067 /* Return -1 if OP0 is set in NEXT. */
17070 }
17073 }
17079 }
17082 }
17084 /* Return the distance between INSN and the next insn that uses
17085 register number REGNO0 in memory address. Return -1 if no such
17086 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17088 static int
17090 {
17102 {
17103 edge e;
17104 edge_iterator ei;
17109 {
17112 }
17118 else
17119 {
17125 {
17126 int bb_dist
17131 {
17138 }
17139 }
17142 }
17143 }
17149 }
17151 /* Define this macro to tune LEA priority vs ADD, it take effect when
17152 there is a dilemma of choicing LEA or ADD
17153 Negative value: ADD is more preferred than LEA
17154 Zero: Netrual
17155 Positive value: LEA is more preferred than ADD*/
17156 #define IX86_LEA_PRIORITY 0
17158 /* Return true if usage of lea INSN has performance advantage
17159 over a sequence of instructions. Instructions sequence has
17160 SPLIT_COST cycles higher latency than lea latency. */
17162 static bool
17165 {
17172 {
17173 /* If there is no non AGU operand definition, no AGU
17174 operand usage and split cost is 0 then both lea
17175 and non lea variants have same priority. Currently
17176 we prefer lea for 64 bit code and non lea on 32 bit
17177 code. */
17180 else
17182 }
17184 /* With longer definitions distance lea is more preferable.
17185 Here we change it to take into account splitting cost and
17186 lea priority. */
17189 /* If there is no use in memory addess then we just check
17190 that split cost exceeds AGU stall. */
17194 /* If this insn has both backward non-agu dependence and forward
17195 agu dependence, the one with short distance takes effect. */
17197 }
17199 /* Return true if it is legal to clobber flags by INSN and
17200 false otherwise. */
17202 static bool
17204 {
17207 bitmap live;
17210 {
17212 {
17219 }
17225 }
17229 }
17231 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17232 move and add to avoid AGU stalls. */
17234 bool
17236 {
17239 /* Check if we need to optimize. */
17243 /* Check it is correct to split here. */
17251 /* We need to split only adds with non destructive
17252 destination operand. */
17255 else
17257 }
17259 /* Return true if we should emit lea instruction instead of mov
17260 instruction. */
17262 bool
17264 {
17267 /* Check if we need to optimize. */
17271 /* Use lea for reg to reg moves only. */
17279 }
17281 /* Return true if we need to split lea into a sequence of
17282 instructions to avoid AGU stalls. */
17284 bool
17286 {
17292 /* Check we need to optimize. */
17296 /* Check it is correct to split here. */
17303 /* There should be at least two components in the address. */
17308 /* We should not split into add if non legitimate pic
17309 operand is used as displacement. */
17324 /* Compute how many cycles we will add to execution time
17325 if split lea into a sequence of instructions. */
17327 {
17328 /* Have to use mov instruction if non desctructive
17329 destination form is used. */
17333 /* Have to add index to base if both exist. */
17337 /* Have to use shift and adds if scale is 2 or greater. */
17339 {
17344 else
17346 }
17348 /* Have to use add instruction with immediate if
17349 disp is non zero. */
17353 /* Subtract the price of lea. */
17355 }
17358 }
17360 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17361 matches destination. RTX includes clobber of FLAGS_REG. */
17363 static void
17366 {
17373 }
17375 /* Return true if regno1 def is nearest to the insn. */
17377 static bool
17379 {
17386 {
17388 {
17391 }
17397 }
17399 /* None of the regs is defined in the bb. */
17401 }
17403 /* Split lea instructions into a sequence of instructions
17404 which are executed on ALU to avoid AGU stalls.
17405 It is assumed that it is allowed to clobber flags register
17406 at lea position. */
17408 void
17410 {
17426 {
17429 }
17432 {
17435 }
17441 {
17442 /* Case r1 = r1 + ... */
17444 {
17445 /* If we have a case r1 = r1 + C * r1 then we
17446 should use multiplication which is very
17447 expensive. Assume cost model is wrong if we
17448 have such case here. */
17453 }
17454 else
17455 {
17456 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17460 /* Use shift for scaling. */
17469 }
17470 }
17472 {
17475 }
17476 else
17477 {
17479 {
17482 }
17484 {
17487 }
17488 else
17489 {
17494 else
17495 {
17496 rtx tmp1;
17498 /* Find better operand for SET instruction, depending
17499 on which definition is farther from the insn. */
17502 else
17512 }
17515 }
17519 }
17520 }
17522 /* Return true if it is ok to optimize an ADD operation to LEA
17523 operation to avoid flag register consumation. For most processors,
17524 ADD is faster than LEA. For the processors like ATOM, if the
17525 destination register of LEA holds an actual address which will be
17526 used soon, LEA is better and otherwise ADD is better. */
17528 bool
17530 {
17535 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17543 }
17545 /* Return true if destination reg of SET_BODY is shift count of
17546 USE_BODY. */
17548 static bool
17550 {
17551 rtx set_dest;
17552 rtx shift_rtx;
17555 /* Retrieve destination of SET_BODY. */
17557 {
17566 use_body))
17571 }
17573 /* Retrieve shift count of USE_BODY. */
17575 {
17587 }
17595 {
17598 /* Return true if shift count is dest of SET_BODY. */
17600 {
17601 /* Add check since it can be invoked before register
17602 allocation in pre-reload schedule. */
17608 }
17609 }
17612 }
17614 /* Return true if destination reg of SET_INSN is shift count of
17615 USE_INSN. */
17617 bool
17619 {
17622 }
17624 /* Return TRUE or FALSE depending on whether the unary operator meets the
17625 appropriate constraints. */
17627 bool
17631 {
17632 /* If one of operands is memory, source and destination must match. */
17638 }
17640 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17641 are ok, keeping in mind the possible movddup alternative. */
17643 bool
17645 {
17651 }
17653 /* Post-reload splitter for converting an SF or DFmode value in an
17654 SSE register into an unsigned SImode. */
17656 void
17658 {
17669 /* Load up the value into the low element. We must ensure that the other
17670 elements are valid floats -- zero is the easiest such value. */
17672 {
17675 else
17677 }
17678 else
17679 {
17684 else
17686 }
17706 else
17711 }
17713 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17714 Expects the 64-bit DImode to be supplied in a pair of integral
17715 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17716 -mfpmath=sse, !optimize_size only. */
17718 void
17720 {
17724 rtx x;
17730 {
17733 }
17734 else
17735 {
17739 }
17747 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17750 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17751 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17752 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17753 (0x1.0p84 + double(fp_value_hi_xmm)).
17754 Note these exponents differ by 32. */
17758 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17759 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17768 /* Add the upper and lower DFmode values together. */
17771 else
17772 {
17776 }
17779 }
17781 /* Not used, but eases macroization of patterns. */
17782 void
17784 rtx input ATTRIBUTE_UNUSED)
17785 {
17787 }
17789 /* Convert an unsigned SImode value into a DFmode. Only currently used
17790 for SSE, but applicable anywhere. */
17792 void
17794 {
17795 REAL_VALUE_TYPE TWO31r;
17810 }
17812 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17813 32-bit mode; otherwise we have a direct convert instruction. */
17815 void
17817 {
17818 REAL_VALUE_TYPE TWO32r;
17836 }
17838 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17839 For x86_32, -mfpmath=sse, !optimize_size only. */
17840 void
17842 {
17843 REAL_VALUE_TYPE ONE16r;
17862 }
17864 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
17865 a vector of unsigned ints VAL to vector of floats TARGET. */
17867 void
17869 {
17871 REAL_VALUE_TYPE TWO16r;
17878 else
17883 OPTAB_DIRECT);
17894 OPTAB_DIRECT);
17896 OPTAB_DIRECT);
17899 }
17901 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
17902 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
17903 This is done by doing just signed conversion if < 0x1p31, and otherwise by
17904 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
17906 rtx
17908 {
17909 REAL_VALUE_TYPE TWO31r;
17924 {
17930 }
17939 OPTAB_DIRECT);
17940 else
17941 {
17947 OPTAB_DIRECT);
17948 }
17951 }
17953 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
17954 then replicate the value for all elements of the vector
17955 register. */
17957 rtx
17959 {
17961 rtvec v;
17965 {
17992 }
17993 }
17995 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
17996 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
17997 for an SSE register. If VECT is true, then replicate the mask for
17998 all elements of the vector register. If INVERT is true, then create
17999 a mask excluding the sign bit. */
18001 rtx
18003 {
18007 rtx v;
18008 rtx mask;
18010 /* Find the sign bit, sign extended to 2*HWI. */
18012 {
18032 else
18040 {
18043 }
18044 else
18045 {
18046 rtvec vec;
18052 {
18055 }
18056 else
18066 }
18071 }
18076 /* Force this value into the low part of a fp vector constant. */
18085 }
18087 /* Generate code for floating point ABS or NEG. */
18089 void
18091 rtx operands[])
18092 {
18103 {
18109 }
18111 /* NEG and ABS performed with SSE use bitwise mask operations.
18112 Create the appropriate mask now. */
18115 else
18125 {
18127 rtvec par;
18132 else
18133 {
18136 }
18138 }
18139 else
18141 }
18143 /* Expand a copysign operation. Special case operand 0 being a constant. */
18145 void
18147 {
18161 else
18165 {
18172 {
18175 else
18176 {
18180 }
18181 }
18191 else
18195 }
18196 else
18197 {
18207 else
18211 }
18212 }
18214 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18215 be a constant, and so has already been expanded into a vector constant. */
18217 void
18219 {
18235 {
18238 }
18239 }
18241 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18242 so we have to do two masks. */
18244 void
18246 {
18261 {
18262 /* Shouldn't happen often (it's useless, obviously), but when it does
18263 we'd generate incorrect code if we continue below. */
18266 }
18269 {
18280 }
18281 else
18282 {
18284 {
18286 }
18288 {
18292 }
18296 {
18299 }
18301 {
18306 }
18308 }
18312 }
18314 /* Return TRUE or FALSE depending on whether the first SET in INSN
18315 has source and destination with matching CC modes, and that the
18316 CC mode is at least as constrained as REQ_MODE. */
18318 bool
18320 {
18321 rtx set;
18332 {
18342 /* FALLTHRU */
18346 /* FALLTHRU */
18350 /* FALLTHRU */
18364 }
18367 }
18369 /* Generate insn patterns to do an integer compare of OPERANDS. */
18371 static rtx
18373 {
18380 /* This is very simple, but making the interface the same as in the
18381 FP case makes the rest of the code easier. */
18385 /* Return the test that should be put into the flags user, i.e.
18386 the bcc, scc, or cmov instruction. */
18388 }
18390 /* Figure out whether to use ordered or unordered fp comparisons.
18391 Return the appropriate mode to use. */
18393 enum machine_mode
18395 {
18396 /* ??? In order to make all comparisons reversible, we do all comparisons
18397 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18398 all forms trapping and nontrapping comparisons, we can make inequality
18399 comparisons trapping again, since it results in better code when using
18400 FCOM based compares. */
18402 }
18404 enum machine_mode
18406 {
18410 {
18413 }
18416 {
18417 /* Only zero flag is needed. */
18421 /* Codes needing carry flag. */
18424 /* Detect overflow checks. They need just the carry flag. */
18428 else
18432 /* Detect overflow checks. They need just the carry flag. */
18436 else
18438 /* Codes possibly doable only with sign flag when
18439 comparing against zero. */
18444 else
18445 /* For other cases Carry flag is not required. */
18447 /* Codes doable only with sign flag when comparing
18448 against zero, but we miss jump instruction for it
18449 so we need to use relational tests against overflow
18450 that thus needs to be zero. */
18455 else
18457 /* strcmp pattern do (use flags) and combine may ask us for proper
18458 mode. */
18463 }
18464 }
18466 /* Return the fixed registers used for condition codes. */
18468 static bool
18470 {
18474 }
18476 /* If two condition code modes are compatible, return a condition code
18477 mode which is compatible with both. Otherwise, return
18478 VOIDmode. */
18480 static enum machine_mode
18482 {
18499 {
18513 {
18527 }
18531 /* These are only compatible with themselves, which we already
18532 checked above. */
18534 }
18535 }
18538 /* Return a comparison we can do and that it is equivalent to
18539 swap_condition (code) apart possibly from orderedness.
18540 But, never change orderedness if TARGET_IEEE_FP, returning
18541 UNKNOWN in that case if necessary. */
18543 static enum rtx_code
18545 {
18547 {
18558 }
18559 }
18561 /* Return cost of comparison CODE using the best strategy for performance.
18562 All following functions do use number of instructions as a cost metrics.
18563 In future this should be tweaked to compute bytes for optimize_size and
18564 take into account performance of various instructions on various CPUs. */
18566 static int
18568 {
18571 /* The cost of code using bit-twiddling on %ah. */
18573 {
18596 }
18599 {
18606 }
18607 }
18609 /* Return strategy to use for floating-point. We assume that fcomi is always
18610 preferrable where available, since that is also true when looking at size
18611 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18613 enum ix86_fpcmp_strategy
18615 {
18616 /* Do fcomi/sahf based test when profitable. */
18625 }
18627 /* Swap, force into registers, or otherwise massage the two operands
18628 to a fp comparison. The operands are updated in place; the new
18629 comparison code is returned. */
18631 static enum rtx_code
18633 {
18639 /* All of the unordered compare instructions only work on registers.
18640 The same is true of the fcomi compare instructions. The XFmode
18641 compare instructions require registers except when comparing
18642 against zero or when converting operand 1 from fixed point to
18643 floating point. */
18652 {
18655 }
18656 else
18657 {
18658 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18659 things around if they appear profitable, otherwise force op0
18660 into a register. */
18666 {
18669 {
18670 rtx tmp;
18673 }
18674 }
18680 {
18685 {
18688 }
18689 else
18691 }
18692 }
18694 /* Try to rearrange the comparison to make it cheaper. */
18698 {
18699 rtx tmp;
18704 }
18709 }
18711 /* Convert comparison codes we use to represent FP comparison to integer
18712 code that will result in proper branch. Return UNKNOWN if no such code
18713 is available. */
18715 enum rtx_code
18717 {
18719 {
18742 }
18743 }
18745 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18747 static rtx
18749 {
18756 /* Do fcomi/sahf based test when profitable. */
18758 {
18763 tmp);
18771 tmp);
18780 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18787 /* In the unordered case, we have to check C2 for NaN's, which
18788 doesn't happen to work out to anything nice combination-wise.
18789 So do some bit twiddling on the value we've got in AH to come
18790 up with an appropriate set of condition codes. */
18794 {
18798 {
18801 }
18802 else
18803 {
18809 }
18814 {
18819 }
18820 else
18821 {
18824 }
18829 {
18832 }
18833 else
18834 {
18838 }
18843 {
18849 }
18850 else
18851 {
18854 }
18859 {
18864 }
18865 else
18866 {
18869 }
18874 {
18879 }
18880 else
18881 {
18884 }
18898 }
18903 }
18905 /* Return the test that should be put into the flags user, i.e.
18906 the bcc, scc, or cmov instruction. */
18909 const0_rtx);
18910 }
18912 static rtx
18914 {
18915 rtx ret;
18921 {
18924 }
18925 else
18929 }
18931 void
18933 {
18935 rtx tmp;
18938 {
18945 simple:
18949 pc_rtx);
18957 /* Expand DImode branch into multiple compare+branch. */
18958 {
18964 {
18967 }
18974 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
18975 avoid two branches. This costs one extra insn, so disable when
18976 optimizing for size. */
18981 {
18999 }
19001 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19002 op1 is a constant and the low word is zero, then we can just
19003 examine the high word. Similarly for low word -1 and
19004 less-or-equal-than or greater-than. */
19008 {
19011 {
19014 }
19018 {
19021 }
19025 }
19027 /* Otherwise, we need two or three jumps. */
19036 {
19050 }
19052 /*
19053 * a < b =>
19054 * if (hi(a) < hi(b)) goto true;
19055 * if (hi(a) > hi(b)) goto false;
19056 * if (lo(a) < lo(b)) goto true;
19057 * false:
19058 */
19070 }
19075 }
19076 }
19078 /* Split branch based on floating point condition. */
19079 void
19082 {
19083 rtx condition;
19084 rtx i;
19087 {
19092 }
19095 tmp);
19097 /* Remove pushed operand from stack. */
19107 }
19109 void
19111 {
19112 rtx ret;
19119 }
19121 /* Expand comparison setting or clearing carry flag. Return true when
19122 successful and set pop for the operation. */
19123 static bool
19125 {
19129 /* Do not handle double-mode compares that go through special path. */
19134 {
19139 /* Shortcut: following common codes never translate
19140 into carry flag compares. */
19145 /* These comparisons require zero flag; swap operands so they won't. */
19148 {
19153 }
19155 /* Try to expand the comparison and verify that we end up with
19156 carry flag based comparison. This fails to be true only when
19157 we decide to expand comparison using arithmetic that is not
19158 too common scenario. */
19167 else
19176 }
19182 {
19187 /* Convert a==0 into (unsigned)a<1. */
19196 /* Convert a>b into b<a or a>=b-1. */
19200 {
19202 /* Bail out on overflow. We still can swap operands but that
19203 would force loading of the constant into register. */
19208 }
19209 else
19210 {
19215 }
19218 /* Convert a>=0 into (unsigned)a<0x80000000. */
19236 }
19237 /* Swapping operands may cause constant to appear as first operand. */
19239 {
19243 }
19247 }
19249 bool
19251 {
19275 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19276 HImode insns, we'd be swallowed in word prefix ops. */
19282 {
19286 HOST_WIDE_INT diff;
19289 /* Sign bit compares are better done using shifts than we do by using
19290 sbb. */
19293 {
19294 /* Detect overlap between destination and compare sources. */
19298 {
19299 rtx flags;
19308 {
19310 compare_code
19312 }
19314 /* To simplify rest of code, restrict to the GEU case. */
19316 {
19322 }
19323 else
19324 {
19327 reverse_condition_maybe_unordered
19329 else
19332 }
19341 else
19344 }
19345 else
19346 {
19349 else
19350 {
19355 }
19357 }
19360 {
19361 /*
19362 * cmpl op0,op1
19363 * sbbl dest,dest
19364 * [addl dest, ct]
19365 *
19366 * Size 5 - 8.
19367 */
19372 }
19374 {
19375 /*
19376 * cmpl op0,op1
19377 * sbbl dest,dest
19378 * orl $ct, dest
19379 *
19380 * Size 8.
19381 */
19385 }
19387 {
19388 /*
19389 * cmpl op0,op1
19390 * sbbl dest,dest
19391 * notl dest
19392 * [addl dest, cf]
19393 *
19394 * Size 8 - 11.
19395 */
19401 }
19402 else
19403 {
19404 /*
19405 * cmpl op0,op1
19406 * sbbl dest,dest
19407 * [notl dest]
19408 * andl cf - ct, dest
19409 * [addl dest, ct]
19410 *
19411 * Size 8 - 11.
19412 */
19415 {
19419 }
19429 }
19435 }
19438 {
19441 HOST_WIDE_INT tmp;
19446 {
19449 /* We may be reversing unordered compare to normal compare, that
19450 is not valid in general (we may convert non-trapping condition
19451 to trapping one), however on i386 we currently emit all
19452 comparisons unordered. */
19455 }
19456 else
19457 {
19460 }
19461 }
19466 {
19471 {
19476 }
19477 }
19479 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19483 {
19484 /* If lea code below could be used, only optimize
19485 if it results in a 2 insn sequence. */
19491 {
19492 /*
19493 * notl op1 (if necessary)
19494 * sarl $31, op1
19495 * orl cf, op1
19496 */
19498 {
19502 }
19513 }
19514 }
19522 {
19523 /*
19524 * xorl dest,dest
19525 * cmpl op1,op2
19526 * setcc dest
19527 * lea cf(dest*(ct-cf)),dest
19528 *
19529 * Size 14.
19530 *
19531 * This also catches the degenerate setcc-only case.
19532 */
19534 rtx tmp;
19540 /* On x86_64 the lea instruction operates on Pmode, so we need
19541 to get arithmetics done in proper mode to match. */
19544 else
19545 {
19546 rtx out1;
19549 nops++;
19551 {
19553 nops++;
19554 }
19555 }
19557 {
19559 nops++;
19560 }
19562 {
19565 else
19567 }
19572 }
19574 /*
19575 * General case: Jumpful:
19576 * xorl dest,dest cmpl op1, op2
19577 * cmpl op1, op2 movl ct, dest
19578 * setcc dest jcc 1f
19579 * decl dest movl cf, dest
19580 * andl (cf-ct),dest 1:
19581 * addl ct,dest
19582 *
19583 * Size 20. Size 14.
19584 *
19585 * This is reasonably steep, but branch mispredict costs are
19586 * high on modern cpus, so consider failing only if optimizing
19587 * for space.
19588 */
19593 {
19595 {
19602 {
19605 /* We may be reversing unordered compare to normal compare,
19606 that is not valid in general (we may convert non-trapping
19607 condition to trapping one), however on i386 we currently
19608 emit all comparisons unordered. */
19610 }
19611 else
19612 {
19616 }
19617 }
19620 {
19621 /* notl op1 (if needed)
19622 sarl $31, op1
19623 andl (cf-ct), op1
19624 addl ct, op1
19626 For x < 0 (resp. x <= -1) there will be no notl,
19627 so if possible swap the constants to get rid of the
19628 complement.
19629 True/false will be -1/0 while code below (store flag
19630 followed by decrement) is 0/-1, so the constants need
19631 to be exchanged once more. */
19634 {
19637 }
19638 else
19639 {
19643 }
19646 }
19647 else
19648 {
19652 constm1_rtx,
19654 }
19666 }
19667 }
19670 {
19671 /* Try a few things more with specific constants and a variable. */
19673 optab op;
19679 /* If one of the two operands is an interesting constant, load a
19680 constant with the above and mask it in with a logical operation. */
19683 {
19689 else
19691 }
19693 {
19699 else
19701 }
19702 else
19709 /* Recurse to get the constant loaded. */
19713 /* Mask in the interesting variable. */
19715 OPTAB_WIDEN);
19720 }
19722 /*
19723 * For comparison with above,
19724 *
19725 * movl cf,dest
19726 * movl ct,tmp
19727 * cmpl op1,op2
19728 * cmovcc tmp,dest
19729 *
19730 * Size 15.
19731 */
19753 }
19755 /* Swap, force into registers, or otherwise massage the two operands
19756 to an sse comparison with a mask result. Thus we differ a bit from
19757 ix86_prepare_fp_compare_args which expects to produce a flags result.
19759 The DEST operand exists to help determine whether to commute commutative
19760 operators. The POP0/POP1 operands are updated in place. The new
19761 comparison code is returned, or UNKNOWN if not implementable. */
19763 static enum rtx_code
19766 {
19767 rtx tmp;
19770 {
19773 /* AVX supports all the needed comparisons. */
19776 /* We have no LTGT as an operator. We could implement it with
19777 NE & ORDERED, but this requires an extra temporary. It's
19778 not clear that it's worth it. */
19785 /* These are supported directly. */
19792 /* AVX has 3 operand comparisons, no need to swap anything. */
19795 /* For commutative operators, try to canonicalize the destination
19796 operand to be first in the comparison - this helps reload to
19797 avoid extra moves. */
19800 /* FALLTHRU */
19806 /* These are not supported directly before AVX, and furthermore
19807 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19808 comparison operands to transform into something that is
19809 supported. */
19818 }
19821 }
19823 /* Detect conditional moves that exactly match min/max operational
19824 semantics. Note that this is IEEE safe, as long as we don't
19825 interchange the operands.
19827 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19828 and TRUE if the operation is successful and instructions are emitted. */
19830 static bool
19833 {
19836 rtx tmp;
19839 ;
19841 {
19845 }
19846 else
19853 else
19858 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
19859 but MODE may be a vector mode and thus not appropriate. */
19861 {
19863 rtvec v;
19868 }
19869 else
19870 {
19873 }
19877 }
19879 /* Expand an sse vector comparison. Return the register with the result. */
19881 static rtx
19884 {
19887 rtx x;
19900 {
19903 }
19904 else
19908 }
19910 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
19911 operations. This is used for both scalar and vector conditional moves. */
19913 static void
19915 {
19921 {
19923 }
19925 {
19929 }
19931 {
19936 }
19938 {
19942 }
19944 {
19952 op_true,
19953 op_false)));
19954 }
19955 else
19956 {
19965 {
19979 {
19985 }
20000 {
20006 }
20010 }
20014 else
20015 {
20021 else
20033 }
20034 }
20035 }
20037 /* Expand a floating-point conditional move. Return true if successful. */
20039 bool
20041 {
20049 {
20052 /* Since we've no cmove for sse registers, don't force bad register
20053 allocation just to gain access to it. Deny movcc when the
20054 comparison mode doesn't match the move mode. */
20073 }
20080 /* The floating point conditional move instructions don't directly
20081 support conditions resulting from a signed integer comparison. */
20085 {
20090 }
20097 }
20099 /* Expand a floating-point vector conditional move; a vcond operation
20100 rather than a movcc operation. */
20102 bool
20104 {
20106 rtx cmp;
20111 {
20112 rtx temp;
20114 {
20131 }
20133 OPTAB_DIRECT);
20136 }
20146 }
20148 /* Expand a signed/unsigned integral vector conditional move. */
20150 bool
20152 {
20162 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20163 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20172 {
20176 {
20182 }
20185 {
20191 }
20192 }
20201 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20205 ;
20206 else
20207 {
20208 /* Canonicalize the comparison to EQ, GT, GTU. */
20210 {
20227 /* FALLTHRU */
20237 }
20239 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20241 {
20243 {
20245 /* SSE4.1 supports EQ. */
20252 /* SSE4.2 supports GT/GTU. */
20259 }
20260 }
20262 /* Unsigned parallel compare is not supported by the hardware.
20263 Play some tricks to turn this into a signed comparison
20264 against 0. */
20266 {
20270 {
20275 {
20280 {
20287 }
20288 /* Subtract (-(INT MAX) - 1) from both operands to make
20289 them signed. */
20300 }
20307 /* Perform a parallel unsigned saturating subtraction. */
20320 }
20321 }
20322 }
20324 /* Allow the comparison to be done in one mode, but the movcc to
20325 happen in another mode. */
20327 {
20330 }
20331 else
20332 {
20338 }
20343 }
20345 /* Expand a variable vector permutation. */
20347 void
20349 {
20360 /* Number of elements in the vector. */
20366 {
20368 {
20369 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20370 an constant shuffle operand. With a tiny bit of effort we can
20371 use VPERMD instead. A re-interpretation stall for V4DFmode is
20372 unfortunate but there's no avoiding it.
20373 Similarly for V16HImode we don't have instructions for variable
20374 shuffling, while for V32QImode we can use after preparing suitable
20375 masks vpshufb; vpshufb; vpermq; vpor. */
20378 {
20382 }
20383 else
20384 {
20388 }
20391 /* Replicate the low bits of the V4DImode mask into V8SImode:
20392 mask = { A B C D }
20393 t1 = { A A B B C C D D }. */
20401 else
20404 /* Multiply the shuffle indicies by two. */
20406 OPTAB_DIRECT);
20408 /* Add one to the odd shuffle indicies:
20409 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20411 {
20414 }
20418 OPTAB_DIRECT);
20420 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20425 }
20428 {
20430 /* The VPERMD and VPERMPS instructions already properly ignore
20431 the high bits of the shuffle elements. No need for us to
20432 perform an AND ourselves. */
20435 else
20436 {
20442 }
20449 else
20450 {
20456 }
20460 /* By combining the two 128-bit input vectors into one 256-bit
20461 input vector, we can use VPERMD and VPERMPS for the full
20462 two-operand shuffle. */
20494 /* From mask create two adjusted masks, which contain the same
20495 bits as mask in the low 7 bits of each vector element.
20496 The first mask will have the most significant bit clear
20497 if it requests element from the same 128-bit lane
20498 and MSB set if it requests element from the other 128-bit lane.
20499 The second mask will have the opposite values of the MSB,
20500 and additionally will have its 128-bit lanes swapped.
20501 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20502 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20503 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20504 stands for other 12 bytes. */
20505 /* The bit whether element is from the same lane or the other
20506 lane is bit 4, so shift it up by 3 to the MSB position. */
20510 /* Clear MSB bits from the mask just in case it had them set. */
20512 /* After this t1 will have MSB set for elements from other lane. */
20514 /* Clear bits other than MSB. */
20516 /* Or in the lower bits from mask into t3. */
20518 /* And invert MSB bits in t1, so MSB is set for elements from the same
20519 lane. */
20521 /* Swap 128-bit lanes in t3. */
20526 /* And or in the lower bits from mask into t1. */
20529 {
20530 /* Each of these shuffles will put 0s in places where
20531 element from the other 128-bit lane is needed, otherwise
20532 will shuffle in the requested value. */
20535 /* For t3 the 128-bit lanes are swapped again. */
20540 /* And oring both together leads to the result. */
20543 }
20546 /* Similarly to the above one_operand_shuffle code,
20547 just for repeated twice for each operand. merge_two:
20548 code will merge the two results together. */
20570 }
20571 }
20574 {
20575 /* The XOP VPPERM insn supports three inputs. By ignoring the
20576 one_operand_shuffle special case, we avoid creating another
20577 set of constant vectors in memory. */
20580 /* mask = mask & {2*w-1, ...} */
20582 }
20583 else
20584 {
20585 /* mask = mask & {w-1, ...} */
20587 }
20595 /* For non-QImode operations, convert the word permutation control
20596 into a byte permutation control. */
20598 {
20603 /* Convert mask to vector of chars. */
20606 /* Replicate each of the input bytes into byte positions:
20607 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20608 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20609 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20616 else
20619 /* Convert it into the byte positions by doing
20620 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20626 }
20628 /* The actual shuffle operations all operate on V16QImode. */
20634 {
20636 }
20638 {
20640 }
20641 else
20642 {
20646 /* Shuffle the two input vectors independently. */
20652 merge_two:
20653 /* Then merge them together. The key is whether any given control
20654 element contained a bit set that indicates the second word. */
20658 {
20659 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20660 more shuffle to convert the V2DI input mask into a V4SI
20661 input mask. At which point the masking that expand_int_vcond
20662 will work as desired. */
20670 }
20687 }
20688 }
20690 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20691 true if we should do zero extension, else sign extension. HIGH_P is
20692 true if we want the N/2 high elements, else the low elements. */
20694 void
20696 {
20698 rtx tmp;
20701 {
20707 {
20711 else
20714 extract
20720 else
20723 extract
20729 else
20732 extract
20738 else
20744 else
20750 else
20755 }
20758 {
20761 }
20763 {
20764 /* Shift higher 8 bytes to lower 8 bytes. */
20769 }
20770 else
20774 }
20775 else
20776 {
20780 {
20784 else
20790 else
20796 else
20801 }
20805 else
20810 }
20811 }
20813 /* Expand conditional increment or decrement using adb/sbb instructions.
20814 The default case using setcc followed by the conditional move can be
20815 done by generic code. */
20816 bool
20818 {
20820 rtx flags;
20822 rtx compare_op;
20840 {
20843 }
20846 {
20850 reverse_condition_maybe_unordered
20852 else
20854 }
20858 /* Construct either adc or sbb insn. */
20860 {
20862 {
20877 }
20878 }
20879 else
20880 {
20882 {
20897 }
20898 }
20902 }
20905 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
20906 but works for floating pointer parameters and nonoffsetable memories.
20907 For pushes, it returns just stack offsets; the values will be saved
20908 in the right order. Maximally three parts are generated. */
20910 static int
20912 {
20917 else
20923 /* Optimize constant pool reference to immediates. This is used by fp
20924 moves, that force all constants to memory to allow combining. */
20926 {
20930 }
20933 {
20934 /* The only non-offsetable memories we handle are pushes. */
20943 }
20946 {
20948 /* Caution: if we looked through a constant pool memory above,
20949 the operand may actually have a different mode now. That's
20950 ok, since we want to pun this all the way back to an integer. */
20954 }
20957 {
20960 else
20961 {
20965 {
20969 }
20971 {
20976 }
20978 {
20979 REAL_VALUE_TYPE r;
20984 {
20991 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
20992 long double may not be 80-bit. */
21001 }
21004 }
21005 else
21007 }
21008 }
21009 else
21010 {
21014 {
21017 {
21021 }
21023 {
21027 }
21029 {
21030 REAL_VALUE_TYPE r;
21036 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21039 = gen_int_mode
21042 DImode);
21043 else
21050 = gen_int_mode
21053 DImode);
21054 else
21056 }
21057 else
21059 }
21060 }
21063 }
21065 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21066 Return false when normal moves are needed; true when all required
21067 insns have been emitted. Operands 2-4 contain the input values
21068 int the correct order; operands 5-7 contain the output values. */
21070 void
21072 {
21080 /* The DFmode expanders may ask us to move double.
21081 For 64bit target this is single move. By hiding the fact
21082 here we simplify i386.md splitters. */
21084 {
21085 /* Optimize constant pool reference to immediates. This is used by
21086 fp moves, that force all constants to memory to allow combining. */
21093 {
21096 }
21097 else
21102 }
21104 /* The only non-offsettable memory we handle is push. */
21107 else
21114 /* When emitting push, take care for source operands on the stack. */
21117 {
21120 /* Compensate for the stack decrement by 4. */
21125 /* src_base refers to the stack pointer and is
21126 automatically decreased by emitted push. */
21130 }
21132 /* We need to do copy in the right order in case an address register
21133 of the source overlaps the destination. */
21135 {
21136 rtx tmp;
21139 {
21143 collisions++;
21144 }
21146 /* Collision in the middle part can be handled by reordering. */
21148 {
21151 }
21155 {
21157 {
21160 }
21161 else
21162 {
21165 }
21166 }
21168 /* If there are more collisions, we can't handle it by reordering.
21169 Do an lea to the last part and use only one colliding move. */
21171 {
21172 rtx base;
21178 /* Handle the case when the last part isn't valid for lea.
21179 Happens in 64-bit mode storing the 12-byte XFmode. */
21186 {
21189 }
21190 }
21191 }
21194 {
21196 {
21198 {
21203 }
21205 {
21208 }
21209 }
21210 else
21211 {
21212 /* In 64bit mode we don't have 32bit push available. In case this is
21213 register, it is OK - we will just use larger counterpart. We also
21214 retype memory - these comes from attempt to avoid REX prefix on
21215 moving of second half of TFmode value. */
21217 {
21219 {
21230 }
21234 }
21235 }
21239 }
21241 /* Choose correct order to not overwrite the source before it is copied. */
21251 {
21253 {
21256 }
21257 }
21258 else
21259 {
21261 {
21264 }
21265 }
21267 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21269 {
21278 }
21284 }
21286 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21287 left shift by a constant, either using a single shift or
21288 a sequence of add instructions. */
21290 static void
21292 {
21298 {
21302 }
21303 else
21304 {
21307 }
21308 }
21310 void
21312 {
21321 {
21326 {
21332 }
21333 else
21334 {
21342 }
21344 }
21351 {
21352 /* Assuming we've chosen a QImode capable registers, then 1 << N
21353 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21355 {
21371 }
21373 /* Otherwise, we can get the same results by manually performing
21374 a bit extract operation on bit 5/6, and then performing the two
21375 shifts. The two methods of getting 0/1 into low/high are exactly
21376 the same size. Avoiding the shift in the bit extract case helps
21377 pentium4 a bit; no one else seems to care much either way. */
21378 else
21379 {
21384 HOST_WIDE_INT bits;
21385 rtx x;
21388 {
21394 }
21395 else
21396 {
21402 }
21406 else
21414 }
21419 }
21422 {
21423 /* For -1 << N, we can avoid the shld instruction, because we
21424 know that we're shifting 0...31/63 ones into a -1. */
21428 else
21430 }
21431 else
21432 {
21440 }
21445 {
21451 }
21452 else
21453 {
21458 }
21459 }
21461 void
21463 {
21473 {
21478 {
21484 }
21486 {
21495 }
21496 else
21497 {
21505 }
21506 }
21507 else
21508 {
21520 {
21528 scratch));
21529 }
21530 else
21531 {
21536 }
21537 }
21538 }
21540 void
21542 {
21552 {
21557 {
21564 }
21565 else
21566 {
21574 }
21575 }
21576 else
21577 {
21589 {
21595 scratch));
21596 }
21597 else
21598 {
21603 }
21604 }
21605 }
21607 /* Predict just emitted jump instruction to be taken with probability PROB. */
21608 static void
21610 {
21614 }
21616 /* Helper function for the string operations below. Dest VARIABLE whether
21617 it is aligned to VALUE bytes. If true, jump to the label. */
21618 static rtx
21620 {
21625 else
21631 else
21634 }
21636 /* Adjust COUNTER by the VALUE. */
21637 static void
21639 {
21644 }
21646 /* Zero extend possibly SImode EXP to Pmode register. */
21647 rtx
21649 {
21653 }
21655 /* Divide COUNTREG by SCALE. */
21656 static rtx
21658 {
21659 rtx sc;
21671 }
21673 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21674 DImode for constant loop counts. */
21676 static enum machine_mode
21678 {
21686 }
21688 /* When SRCPTR is non-NULL, output simple loop to move memory
21689 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21690 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21691 equivalent loop to set memory by VALUE (supposed to be in MODE).
21693 The size is rounded down to whole number of chunk size moved at once.
21694 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21697 static void
21702 {
21707 rtx size;
21708 rtx x_addr;
21709 rtx y_addr;
21718 /* Those two should combine. */
21720 {
21724 }
21734 {
21738 /* When unrolling for chips that reorder memory reads and writes,
21739 we can save registers by using single temporary.
21740 Also using 4 temporaries is overkill in 32bit mode. */
21742 {
21744 {
21746 {
21747 destmem =
21749 srcmem =
21751 }
21753 }
21754 }
21755 else
21756 {
21760 {
21763 {
21764 srcmem =
21766 }
21768 }
21770 {
21772 {
21773 destmem =
21775 }
21777 }
21778 }
21779 }
21780 else
21782 {
21784 destmem =
21787 }
21797 {
21803 else
21805 }
21806 else
21814 {
21819 }
21821 }
21823 /* Output "rep; mov" instruction.
21824 Arguments have same meaning as for previous function */
21825 static void
21828 rtx count,
21830 {
21831 rtx destexp;
21832 rtx srcexp;
21833 rtx countreg;
21834 HOST_WIDE_INT rounded_count;
21836 /* If the size is known, it is shorter to use rep movs. */
21847 {
21854 }
21855 else
21856 {
21859 }
21861 {
21868 }
21869 else
21870 {
21875 }
21878 }
21880 /* Output "rep; stos" instruction.
21881 Arguments have same meaning as for previous function */
21882 static void
21885 rtx orig_value)
21886 {
21887 rtx destexp;
21888 rtx countreg;
21889 HOST_WIDE_INT rounded_count;
21896 {
21900 }
21901 else
21904 {
21909 }
21913 }
21915 static void
21918 {
21922 }
21924 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
21925 static void
21928 {
21931 {
21936 {
21938 {
21941 }
21942 else
21945 }
21947 {
21950 else
21951 {
21954 }
21956 }
21958 {
21961 }
21963 {
21966 }
21968 {
21971 }
21973 }
21975 {
21981 }
21983 /* When there are stringops, we can cheaply increase dest and src pointers.
21984 Otherwise we save code size by maintaining offset (zero is readily
21985 available from preceding rep operation) and using x86 addressing modes.
21986 */
21988 {
21990 {
21997 }
21999 {
22006 }
22008 {
22015 }
22016 }
22017 else
22018 {
22020 rtx tmp;
22023 {
22034 }
22036 {
22049 }
22051 {
22060 }
22061 }
22062 }
22064 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22065 static void
22068 {
22069 count =
22075 }
22077 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22078 static void
22080 {
22081 rtx dest;
22084 {
22089 {
22091 {
22096 }
22097 else
22100 }
22102 {
22104 {
22107 }
22108 else
22109 {
22114 }
22116 }
22118 {
22122 }
22124 {
22128 }
22130 {
22134 }
22136 }
22138 {
22141 }
22143 {
22146 {
22150 }
22151 else
22152 {
22158 }
22161 }
22163 {
22166 {
22169 }
22170 else
22171 {
22175 }
22178 }
22180 {
22186 }
22188 {
22194 }
22196 {
22202 }
22203 }
22205 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22206 DESIRED_ALIGNMENT. */
22207 static void
22211 {
22213 {
22221 }
22223 {
22231 }
22233 {
22241 }
22243 }
22245 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22246 ALIGN_BYTES is how many bytes need to be copied. */
22247 static rtx
22250 {
22259 {
22264 }
22266 {
22277 }
22279 {
22285 {
22293 }
22296 }
22302 {
22314 }
22321 }
22323 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22324 DESIRED_ALIGNMENT. */
22325 static void
22328 {
22330 {
22337 }
22339 {
22346 }
22348 {
22355 }
22357 }
22359 /* Set enough from DST to align DST known to by aligned by ALIGN to
22360 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22361 static rtx
22364 {
22368 {
22373 }
22375 {
22382 }
22384 {
22391 }
22398 }
22400 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22401 static enum stringop_alg
22404 {
22407 /* Algorithms using the rep prefix want at least edi and ecx;
22408 additionally, memset wants eax and memcpy wants esi. Don't
22409 consider such algorithms if the user has appropriated those
22410 registers for their own purposes. */
22412 || (memset
22416 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22417 || (alg != rep_prefix_1_byte \
22418 && alg != rep_prefix_4_byte \
22419 && alg != rep_prefix_8_byte))
22422 /* Even if the string operation call is cold, we still might spend a lot
22423 of time processing large blocks. */
22428 else
22436 else
22440 /* rep; movq or rep; movl is the smallest variant. */
22442 {
22445 else
22447 }
22448 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22449 */
22453 {
22457 {
22458 /* We get here if the algorithms that were not libcall-based
22459 were rep-prefix based and we are unable to use rep prefixes
22460 based on global register usage. Break out of the loop and
22461 use the heuristic below. */
22465 {
22470 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22471 last non-libcall inline algorithm. */
22473 {
22474 /* When the current size is best to be copied by a libcall,
22475 but we are still forced to inline, run the heuristic below
22476 that will pick code for medium sized blocks. */
22480 }
22482 {
22485 }
22486 }
22487 }
22489 }
22490 /* When asked to inline the call anyway, try to pick meaningful choice.
22491 We look for maximal size of block that is faster to copy by hand and
22492 take blocks of at most of that size guessing that average size will
22493 be roughly half of the block.
22495 If this turns out to be bad, we might simply specify the preferred
22496 choice in ix86_costs. */
22499 {
22506 {
22513 }
22514 /* If there aren't any usable algorithms, then recursing on
22515 smaller sizes isn't going to find anything. Just return the
22516 simple byte-at-a-time copy loop. */
22518 {
22519 /* Pick something reasonable. */
22523 }
22532 }
22534 #undef ALG_USABLE_P
22535 }
22537 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22538 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22539 static int
22543 {
22546 {
22557 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22558 copying whole cacheline at once. */
22561 else
22565 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22566 copying whole cacheline at once. */
22569 else
22577 }
22586 }
22588 /* Return the smallest power of 2 greater than VAL. */
22589 static int
22591 {
22596 }
22598 /* Expand string move (memcpy) operation. Use i386 string operations
22599 when profitable. expand_setmem contains similar code. The code
22600 depends upon architecture, block size and alignment, but always has
22601 the same overall structure:
22603 1) Prologue guard: Conditional that jumps up to epilogues for small
22604 blocks that can be handled by epilogue alone. This is faster
22605 but also needed for correctness, since prologue assume the block
22606 is larger than the desired alignment.
22608 Optional dynamic check for size and libcall for large
22609 blocks is emitted here too, with -minline-stringops-dynamically.
22611 2) Prologue: copy first few bytes in order to get destination
22612 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22613 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22614 copied. We emit either a jump tree on power of two sized
22615 blocks, or a byte loop.
22617 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22618 with specified algorithm.
22620 4) Epilogue: code copying tail of the block that is too small to be
22621 handled by main body (or up to size guarded by prologue guard). */
22623 bool
22626 {
22627 rtx destreg;
22628 rtx srcreg;
22630 rtx tmp;
22644 /* i386 can do misaligned access on reasonably increased cost. */
22648 /* ALIGN is the minimum of destination and source alignment, but we care here
22649 just about destination alignment. */
22658 /* Make sure we don't need to care about overflow later on. */
22662 /* Step 0: Decide on preferred algorithm, desired alignment and
22663 size of chunks to be copied by main loop. */
22679 {
22704 }
22708 /* Step 1: Prologue guard. */
22710 /* Alignment code needs count to be in register. */
22712 {
22715 {
22716 align_bytes
22720 else
22722 }
22725 }
22728 /* Ensure that alignment prologue won't copy past end of block. */
22730 {
22732 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22733 Make sure it is power of 2. */
22737 {
22739 {
22740 /* If main algorithm works on QImode, no epilogue is needed.
22741 For small sizes just don't align anything. */
22744 else
22746 }
22747 }
22748 else
22749 {
22756 else
22758 }
22759 }
22761 /* Emit code to decide on runtime whether library call or inline should be
22762 used. */
22764 {
22766 {
22768 {
22772 }
22773 }
22774 else
22775 {
22784 }
22785 }
22787 /* Step 2: Alignment prologue. */
22790 {
22792 {
22793 /* Except for the first move in epilogue, we no longer know
22794 constant offset in aliasing info. It don't seems to worth
22795 the pain to maintain it for the first move, so throw away
22796 the info early. */
22800 desired_align);
22801 }
22802 else
22803 {
22804 /* If we know how many bytes need to be stored before dst is
22805 sufficiently aligned, maintain aliasing info accurately. */
22811 }
22817 {
22818 /* It is possible that we copied enough so the main loop will not
22819 execute. */
22829 else
22831 }
22832 }
22834 {
22839 }
22843 /* Step 3: Main loop. */
22846 {
22859 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
22860 registers for 4 temporaries anyway. */
22863 expected_size);
22867 DImode);
22871 SImode);
22875 QImode);
22877 }
22878 /* Adjust properly the offset of src and dest memory for aliasing. */
22880 {
22885 }
22886 else
22887 {
22890 }
22892 /* Step 4: Epilogue to copy the remaining bytes. */
22893 epilogue:
22895 {
22896 /* When the main loop is done, COUNT_EXP might hold original count,
22897 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22898 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22899 bytes. Compensate if needed. */
22902 {
22903 tmp =
22906 OPTAB_DIRECT);
22909 }
22912 }
22916 epilogue_size_needed);
22920 }
22922 /* Helper function for memcpy. For QImode value 0xXY produce
22923 0xXYXYXYXY of wide specified by MODE. This is essentially
22924 a * 0x10101010, but we can do slightly better than
22925 synth_mult by unwinding the sequence by hand on CPUs with
22926 slow multiply. */
22927 static rtx
22929 {
22931 rtx tmp;
22938 {
22946 }
22955 nops--;
22960 {
22964 OPTAB_DIRECT);
22965 }
22966 else
22967 {
22973 else
22975 else
22976 {
22979 reg =
22981 }
22991 }
22992 }
22994 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
22995 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
22996 alignment from ALIGN to DESIRED_ALIGN. */
22997 static rtx
22999 {
23000 rtx promoted_val;
23009 else
23013 }
23015 /* Expand string clear operation (bzero). Use i386 string operations when
23016 profitable. See expand_movmem comment for explanation of individual
23017 steps performed. */
23018 bool
23021 {
23022 rtx destreg;
23024 rtx tmp;
23040 /* i386 can do misaligned access on reasonably increased cost. */
23049 /* Make sure we don't need to care about overflow later on. */
23053 /* Step 0: Decide on preferred algorithm, desired alignment and
23054 size of chunks to be copied by main loop. */
23069 {
23094 }
23097 /* Step 1: Prologue guard. */
23099 /* Alignment code needs count to be in register. */
23101 {
23104 {
23105 align_bytes
23109 else
23111 }
23113 {
23118 }
23119 }
23120 /* Do the cheap promotion to allow better CSE across the
23121 main loop and epilogue (ie one load of the big constant in the
23122 front of all code. */
23126 /* Ensure that alignment prologue won't copy past end of block. */
23128 {
23130 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23131 Make sure it is power of 2. */
23134 /* To improve performance of small blocks, we jump around the VAL
23135 promoting mode. This mean that if the promoted VAL is not constant,
23136 we might not use it in the epilogue and have to use byte
23137 loop variant. */
23141 {
23143 {
23144 /* If main algorithm works on QImode, no epilogue is needed.
23145 For small sizes just don't align anything. */
23148 else
23150 }
23151 }
23152 else
23153 {
23160 else
23162 }
23163 }
23165 {
23174 }
23176 /* Step 2: Alignment prologue. */
23178 /* Do the expensive promotion once we branched off the small blocks. */
23185 {
23187 {
23188 /* Except for the first move in epilogue, we no longer know
23189 constant offset in aliasing info. It don't seems to worth
23190 the pain to maintain it for the first move, so throw away
23191 the info early. */
23194 desired_align);
23195 }
23196 else
23197 {
23198 /* If we know how many bytes need to be stored before dst is
23199 sufficiently aligned, maintain aliasing info accurately. */
23205 }
23211 {
23212 /* It is possible that we copied enough so the main loop will not
23213 execute. */
23223 else
23225 }
23226 }
23228 {
23234 }
23238 /* Step 3: Main loop. */
23241 {
23269 }
23270 /* Adjust properly the offset of src and dest memory for aliasing. */
23274 else
23277 /* Step 4: Epilogue to copy the remaining bytes. */
23280 {
23281 /* When the main loop is done, COUNT_EXP might hold original count,
23282 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23283 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23284 bytes. Compensate if needed. */
23287 {
23288 tmp =
23291 OPTAB_DIRECT);
23294 }
23297 }
23298 epilogue:
23300 {
23303 epilogue_size_needed);
23304 else
23306 epilogue_size_needed);
23307 }
23311 }
23313 /* Expand the appropriate insns for doing strlen if not just doing
23314 repnz; scasb
23316 out = result, initialized with the start address
23317 align_rtx = alignment of the address.
23318 scratch = scratch register, initialized with the startaddress when
23319 not aligned, otherwise undefined
23321 This is just the body. It needs the initializations mentioned above and
23322 some address computing at the end. These things are done in i386.md. */
23324 static void
23326 {
23328 rtx tmp;
23333 rtx mem;
23336 rtx cmp;
23342 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23344 /* Is there a known alignment and is it less than 4? */
23346 {
23349 /* Is there a known alignment and is it not 2? */
23351 {
23355 /* Leave just the 3 lower bits. */
23365 }
23366 else
23367 {
23368 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23369 check if is aligned to 4 - byte. */
23376 }
23380 /* Now compare the bytes. */
23382 /* Compare the first n unaligned byte on a byte per byte basis. */
23386 /* Increment the address. */
23389 /* Not needed with an alignment of 2 */
23391 {
23395 end_0_label);
23400 }
23403 end_0_label);
23406 }
23408 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23409 align this loop. It gives only huge programs, but does not help to
23410 speed up. */
23417 /* This formula yields a nonzero result iff one of the bytes is zero.
23418 This saves three branches inside loop and many cycles. */
23426 align_4_label);
23429 {
23435 /* If zero is not in the first two bytes, move two bytes forward. */
23441 reg,
23442 tmpreg)));
23443 /* Emit lea manually to avoid clobbering of flags. */
23451 reg2,
23452 out)));
23453 }
23454 else
23455 {
23457 /* Is zero in the first two bytes? */
23464 pc_rtx);
23468 /* Not in the first two. Move two bytes forward. */
23474 }
23476 /* Avoid branch in fixing the byte. */
23484 }
23486 /* Expand strlen. */
23488 bool
23490 {
23493 /* The generic case of strlen expander is long. Avoid it's
23494 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23497 && !TARGET_INLINE_ALL_STRINGOPS
23507 {
23508 /* Well it seems that some optimizer does not combine a call like
23509 foo(strlen(bar), strlen(bar));
23510 when the move and the subtraction is done here. It does calculate
23511 the length just once when these instructions are done inside of
23512 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23513 often used and I use one fewer register for the lifetime of
23514 output_strlen_unroll() this is better. */
23520 /* strlensi_unroll_1 returns the address of the zero at the end of
23521 the string, like memchr(), so compute the length by subtracting
23522 the start address. */
23524 }
23525 else
23526 {
23527 rtx unspec;
23529 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23542 /* If .md starts supporting :P, this can be done in .md. */
23548 }
23550 }
23552 /* For given symbol (function) construct code to compute address of it's PLT
23553 entry in large x86-64 PIC model. */
23554 static rtx
23556 {
23569 }
23571 rtx
23573 rtx callarg2,
23575 {
23576 /* We need to represent that SI and DI registers are clobbered
23577 by SYSV calls. */
23583 };
23593 {
23594 #if TARGET_MACHO
23597 #endif
23598 }
23599 else
23600 {
23601 /* Static functions and indirect calls don't need the pic register. */
23606 }
23609 {
23613 }
23623 {
23628 }
23637 {
23641 }
23645 {
23649 UNSPEC_MS_TO_SYSV_CALL);
23657 }
23666 }
23668 /* Output the assembly for a call instruction. */
23672 {
23678 {
23681 /* SEH epilogue detection requires the indirect branch case
23682 to include REX.W. */
23685 else
23690 }
23692 /* SEH unwinding can require an extra nop to be emitted in several
23693 circumstances. Determine if we have one of those. */
23695 {
23696 rtx i;
23699 {
23700 /* If we get to another real insn, we don't need the nop. */
23704 /* If we get to the epilogue note, prevent a catch region from
23705 being adjacent to the standard epilogue sequence. If non-
23706 call-exceptions, we'll have done this during epilogue emission. */
23708 && !flag_non_call_exceptions
23710 {
23713 }
23714 }
23716 /* If we didn't find a real insn following the call, prevent the
23717 unwinder from looking into the next function. */
23720 }
23724 else
23733 }
23734 \f
23735 /* Clear stack slot assignments remembered from previous functions.
23736 This is called from INIT_EXPANDERS once before RTL is emitted for each
23737 function. */
23741 {
23749 }
23751 /* Return a MEM corresponding to a stack slot with mode MODE.
23752 Allocate a new slot if necessary.
23754 The RTL for a function can have several slots available: N is
23755 which slot to use. */
23757 rtx
23759 {
23776 }
23778 static void
23780 {
23786 }
23787 \f
23788 /* Calculate the length of the memory address in the instruction encoding.
23789 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23790 or other prefixes. We never generate addr32 prefix for LEA insn. */
23792 int
23794 {
23811 /* If this is not LEA instruction, add the length of addr32 prefix. */
23816 len++;
23830 /* Rule of thumb:
23831 - esp as the base always wants an index,
23832 - ebp as the base always wants a displacement,
23833 - r12 as the base always wants an index,
23834 - r13 as the base always wants a displacement. */
23836 /* Register Indirect. */
23838 {
23839 /* esp (for its index) and ebp (for its displacement) need
23840 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23841 code. */
23848 len++;
23849 }
23851 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23852 is not disp32, but disp32(%rip), so for disp32
23853 SIB byte is needed, unless print_operand_address
23854 optimizes it into disp32(%rip) or (%rip) is implied
23855 by UNSPEC. */
23857 {
23860 {
23876 len++;
23877 }
23878 }
23879 else
23880 {
23881 /* Find the length of the displacement constant. */
23883 {
23886 else
23888 }
23889 /* ebp always wants a displacement. Similarly r13. */
23891 len++;
23893 /* An index requires the two-byte modrm form.... */
23895 /* ...like esp (or r12), which always wants an index. */
23899 len++;
23900 }
23903 }
23905 /* Compute default value for "length_immediate" attribute. When SHORTFORM
23906 is set, expect that insn have 8bit immediate alternative. */
23907 int
23909 {
23915 {
23920 {
23923 {
23935 }
23937 {
23940 }
23941 }
23943 {
23953 /* Immediates for DImode instructions are encoded
23954 as 32bit sign extended values. */
23960 }
23961 }
23963 }
23965 /* Compute default value for "length_address" attribute. */
23966 int
23968 {
23972 {
23983 }
23988 {
23991 {
23996 constraints++;
23999 ;
24000 /* Skip ignored operands. */
24003 }
24005 }
24007 }
24009 /* Compute default value for "length_vex" attribute. It includes
24010 2 or 3 byte VEX prefix and 1 opcode byte. */
24012 int
24014 {
24017 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24018 byte VEX prefix. */
24022 /* We can always use 2 byte VEX prefix in 32bit. */
24030 {
24031 /* REX.W bit uses 3 byte VEX prefix. */
24035 }
24036 else
24037 {
24038 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24042 }
24045 }
24046 \f
24047 /* Return the maximum number of instructions a cpu can issue. */
24049 static int
24051 {
24053 {
24078 }
24079 }
24081 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24082 by DEP_INSN and nothing set by DEP_INSN. */
24084 static bool
24086 {
24089 /* Simplify the test for uninteresting insns. */
24097 {
24100 }
24105 {
24108 }
24109 else
24115 /* This test is true if the dependent insn reads the flags but
24116 not any other potentially set register. */
24124 }
24126 /* Return true iff USE_INSN has a memory address with operands set by
24127 SET_INSN. */
24129 bool
24131 {
24136 {
24139 }
24141 }
24143 static int
24145 {
24151 /* Anti and output dependencies have zero cost on all CPUs. */
24157 /* If we can't recognize the insns, we can't really do anything. */
24165 {
24167 /* Address Generation Interlock adds a cycle of latency. */
24169 {
24180 }
24184 /* ??? Compares pair with jump/setcc. */
24188 /* Floating point stores require value to be ready one cycle earlier. */
24198 /* INT->FP conversion is expensive. */
24202 /* There is one cycle extra latency between an FP op and a store. */
24210 /* Show ability of reorder buffer to hide latency of load by executing
24211 in parallel with previous instruction in case
24212 previous instruction is not needed to compute the address. */
24215 {
24216 /* Claim moves to take one cycle, as core can issue one load
24217 at time and the next load can start cycle later. */
24222 cost--;
24223 }
24229 /* The esp dependency is resolved before the instruction is really
24230 finished. */
24235 /* INT->FP conversion is expensive. */
24239 /* Show ability of reorder buffer to hide latency of load by executing
24240 in parallel with previous instruction in case
24241 previous instruction is not needed to compute the address. */
24244 {
24245 /* Claim moves to take one cycle, as core can issue one load
24246 at time and the next load can start cycle later. */
24252 else
24254 }
24270 /* Show ability of reorder buffer to hide latency of load by executing
24271 in parallel with previous instruction in case
24272 previous instruction is not needed to compute the address. */
24275 {
24279 /* Because of the difference between the length of integer and
24280 floating unit pipeline preparation stages, the memory operands
24281 for floating point are cheaper.
24283 ??? For Athlon it the difference is most probably 2. */
24286 else
24291 else
24293 }
24297 }
24300 }
24302 /* How many alternative schedules to try. This should be as wide as the
24303 scheduling freedom in the DFA, but no wider. Making this value too
24304 large results extra work for the scheduler. */
24306 static int
24308 {
24310 {
24321 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24322 as many instructions can be executed on a cycle, i.e.,
24323 issue_rate. I wonder why tuning for many CPUs does not do this. */
24326 /* Don't use lookahead for pre-reload schedule to save compile time. */
24331 }
24332 }
24334 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24335 execution. It is applied if
24336 (1) IMUL instruction is on the top of list;
24337 (2) There exists the only producer of independent IMUL instruction in
24338 ready list;
24339 (3) Put found producer on the top of ready list.
24340 Returns issue rate. */
24342 static int
24345 {
24350 sd_iterator_def sd_it;
24351 dep_t dep;
24354 /* Set up issue rate. */
24357 /* Do reodering for Atom only. */
24360 /* Do not perform ready list reodering for pre-reload schedule pass. */
24363 /* Nothing to do if ready list contains only 1 instruction. */
24367 /* Check that IMUL instruction is on the top of ready list. */
24380 /* Search for producer of independent IMUL instruction. */
24382 {
24386 /* Skip IMUL instruction. */
24396 {
24397 rtx con;
24408 {
24409 sd_iterator_def sd_it1;
24410 dep_t dep1;
24411 /* Check if there is no other dependee for IMUL. */
24414 {
24415 rtx pro;
24421 }
24424 }
24425 }
24428 }
24436 /* Put IMUL producer (ready[index]) at the top of ready list. */
24443 }
24445 static bool
24448 /* Returns true if lhs of insn is HW function argument register and set up
24449 is_spilled to true if it is likely spilled HW register. */
24450 static bool
24452 {
24453 rtx dst;
24457 /* Call instructions are not movable, ignore it. */
24468 {
24469 /* Is it likely spilled HW register? */
24474 }
24476 }
24478 /* Add output dependencies for chain of function adjacent arguments if only
24479 there is a move to likely spilled HW register. Return first argument
24480 if at least one dependence was added or NULL otherwise. */
24481 static rtx
24483 {
24484 rtx insn;
24491 /* Find nearest to call argument passing instruction. */
24493 {
24502 }
24506 {
24513 {
24516 }
24518 {
24519 /* Add output depdendence between two function arguments if chain
24520 of output arguments contains likely spilled HW registers. */
24524 }
24525 else
24527 }
24531 }
24533 /* Add output or anti dependency from insn to first_arg to restrict its code
24534 motion. */
24535 static void
24537 {
24538 rtx set;
24539 rtx tmp;
24546 {
24547 /* Add output dependency to the first function argument. */
24550 }
24551 /* Add anti dependency. */
24553 }
24555 /* Avoid cross block motion of function argument through adding dependency
24556 from the first non-jump instruction in bb. */
24557 static void
24559 {
24563 {
24565 {
24568 {
24571 }
24572 }
24576 }
24577 }
24579 /* Hook for pre-reload schedule - avoid motion of function arguments
24580 passed in likely spilled HW registers. */
24581 static void
24583 {
24584 rtx insn;
24592 {
24595 {
24596 /* Add dependee for first argument to predecessors if only
24597 region contains more than one block. */
24601 /* Skip trivial regions and region head blocks that can have
24602 predecessors outside of region. */
24604 {
24605 edge e;
24606 edge_iterator ei;
24607 /* Assume that region is SCC, i.e. all immediate predecessors
24608 of non-head block are in the same region. */
24610 {
24611 /* Avoid creating of loop-carried dependencies through
24612 using topological odering in region. */
24615 }
24616 }
24620 }
24621 }
24624 }
24626 /* Hook for pre-reload schedule - set priority of moves from likely spilled
24627 HW registers to maximum, to schedule them at soon as possible. These are
24628 moves from function argument registers at the top of the function entry
24629 and moves from function return value registers after call. */
24630 static int
24632 {
24633 rtx set;
24643 {
24650 }
24653 }
24655 /* Model decoder of Core 2/i7.
24656 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
24657 track the instruction fetch block boundaries and make sure that long
24658 (9+ bytes) instructions are assigned to D0. */
24660 /* Maximum length of an insn that can be handled by
24661 a secondary decoder unit. '8' for Core 2/i7. */
24664 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
24665 '16' for Core 2/i7. */
24668 /* Maximum number of instructions decoder can handle per cycle.
24669 '6' for Core 2/i7. */
24673 ix86_first_cycle_multipass_data_t;
24675 const_ix86_first_cycle_multipass_data_t;
24677 /* A variable to store target state across calls to max_issue within
24678 one cycle. */
24682 /* Initialize DATA. */
24683 static void
24685 {
24686 ix86_first_cycle_multipass_data_t data
24693 }
24695 /* Advancing the cycle; reset ifetch block counts. */
24696 static void
24698 {
24705 }
24709 /* Filter out insns from ready_try that the core will not be able to issue
24710 on current cycle due to decoder. */
24711 static void
24712 core2i7_first_cycle_multipass_filter_ready_try
24715 {
24717 {
24718 rtx insn;
24728 (!first_cycle_insn_p
24730 /* ... or it would not fit into the ifetch block ... */
24732 /* ... or the decoder is full already ... */
24734 /* ... mask the insn out. */
24735 {
24740 }
24741 }
24742 }
24744 /* Prepare for a new round of multipass lookahead scheduling. */
24745 static void
24748 {
24749 ix86_first_cycle_multipass_data_t data
24751 const_ix86_first_cycle_multipass_data_t prev_data
24754 /* Restore the state from the end of the previous round. */
24758 /* Filter instructions that cannot be issued on current cycle due to
24759 decoder restrictions. */
24761 first_cycle_insn_p);
24762 }
24764 /* INSN is being issued in current solution. Account for its impact on
24765 the decoder model. */
24766 static void
24769 {
24770 ix86_first_cycle_multipass_data_t data
24772 const_ix86_first_cycle_multipass_data_t prev_data
24782 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
24784 {
24787 }
24789 {
24793 }
24796 /* Filter out insns from ready_try that the core will not be able to issue
24797 on current cycle due to decoder. */
24800 }
24802 /* Revert the effect on ready_try. */
24803 static void
24807 {
24808 const_ix86_first_cycle_multipass_data_t data
24811 sbitmap_iterator sbi;
24815 {
24817 }
24818 }
24820 /* Save the result of multipass lookahead scheduling for the next round. */
24821 static void
24823 {
24824 const_ix86_first_cycle_multipass_data_t data
24826 ix86_first_cycle_multipass_data_t next_data
24830 {
24833 }
24834 }
24836 /* Deallocate target data. */
24837 static void
24839 {
24840 ix86_first_cycle_multipass_data_t data
24844 {
24848 }
24849 }
24851 /* Prepare for scheduling pass. */
24852 static void
24856 {
24857 /* Install scheduling hooks for current CPU. Some of these hooks are used
24858 in time-critical parts of the scheduler, so we only set them up when
24859 they are actually used. */
24861 {
24864 /* Do not perform multipass scheduling for pre-reload schedule
24865 to save compile time. */
24867 {
24883 /* Set decoder parameters. */
24888 }
24889 /* ... Fall through ... */
24899 }
24900 }
24902 \f
24903 /* Compute the alignment given to a constant that is being placed in memory.
24904 EXP is the constant and ALIGN is the alignment that the object would
24905 ordinarily have.
24906 The value of this function is used instead of that alignment to align
24907 the object. */
24909 int
24911 {
24914 {
24919 }
24925 }
24927 /* Compute the alignment for a static variable.
24928 TYPE is the data type, and ALIGN is the alignment that
24929 the object would ordinarily have. The value of this function is used
24930 instead of that alignment to align the object. */
24932 int
24934 {
24945 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24946 to 16byte boundary. */
24948 {
24955 }
24958 {
24963 }
24965 {
24972 }
24977 {
24982 }
24985 {
24990 }
24993 }
24995 /* Compute the alignment for a local variable or a stack slot. EXP is
24996 the data type or decl itself, MODE is the widest mode available and
24997 ALIGN is the alignment that the object would ordinarily have. The
24998 value of this macro is used instead of that alignment to align the
24999 object. */
25001 unsigned int
25004 {
25008 {
25011 }
25012 else
25013 {
25016 }
25018 /* Don't do dynamic stack realignment for long long objects with
25019 -mpreferred-stack-boundary=2. */
25028 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25029 register in MODE. We will return the largest alignment of XF
25030 and DF. */
25032 {
25036 }
25038 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25039 to 16byte boundary. Exact wording is:
25041 An array uses the same alignment as its elements, except that a local or
25042 global array variable of length at least 16 bytes or
25043 a C99 variable-length array variable always has alignment of at least 16 bytes.
25045 This was added to allow use of aligned SSE instructions at arrays. This
25046 rule is meant for static storage (where compiler can not do the analysis
25047 by itself). We follow it for automatic variables only when convenient.
25048 We fully control everything in the function compiled and functions from
25049 other unit can not rely on the alignment.
25051 Exclude va_list type. It is the common case of local array where
25052 we can not benefit from the alignment. */
25055 {
25065 }
25067 {
25072 }
25074 {
25080 }
25085 {
25090 }
25093 {
25099 }
25101 }
25103 /* Compute the minimum required alignment for dynamic stack realignment
25104 purposes for a local variable, parameter or a stack slot. EXP is
25105 the data type or decl itself, MODE is its mode and ALIGN is the
25106 alignment that the object would ordinarily have. */
25108 unsigned int
25111 {
25115 {
25118 }
25119 else
25120 {
25123 }
25128 /* Don't do dynamic stack realignment for long long objects with
25129 -mpreferred-stack-boundary=2. */
25136 }
25137 \f
25138 /* Find a location for the static chain incoming to a nested function.
25139 This is a register, unless all free registers are used by arguments. */
25141 static rtx
25143 {
25150 {
25151 /* We always use R10 in 64-bit mode. */
25153 }
25154 else
25155 {
25156 tree fntype;
25159 /* By default in 32-bit mode we use ECX to pass the static chain. */
25165 {
25166 /* Fastcall functions use ecx/edx for arguments, which leaves
25167 us with EAX for the static chain.
25168 Thiscall functions use ecx for arguments, which also
25169 leaves us with EAX for the static chain. */
25171 }
25173 {
25174 /* Thiscall functions use ecx for arguments, which leaves
25175 us with EAX and EDX for the static chain.
25176 We are using for abi-compatibility EAX. */
25178 }
25180 {
25181 /* For regparm 3, we have no free call-clobbered registers in
25182 which to store the static chain. In order to implement this,
25183 we have the trampoline push the static chain to the stack.
25184 However, we can't push a value below the return address when
25185 we call the nested function directly, so we have to use an
25186 alternate entry point. For this we use ESI, and have the
25187 alternate entry point push ESI, so that things appear the
25188 same once we're executing the nested function. */
25190 {
25196 }
25198 }
25199 }
25202 }
25204 /* Emit RTL insns to initialize the variable parts of a trampoline.
25205 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25206 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25207 to be passed to the target function. */
25209 static void
25211 {
25219 {
25222 /* Load the function address to r11. Try to load address using
25223 the shorter movl instead of movabs. We may want to support
25224 movq for kernel mode, but kernel does not use trampolines at
25225 the moment. FNADDR is a 32bit address and may not be in
25226 DImode when ptr_mode == SImode. Always use movl in this
25227 case. */
25230 {
25239 }
25240 else
25241 {
25248 }
25250 /* Load static chain using movabs to r10. Use the shorter movl
25251 instead of movabs when ptr_mode == SImode. */
25253 {
25256 }
25257 else
25258 {
25261 }
25270 /* Jump to r11; the last (unused) byte is a nop, only there to
25271 pad the write out to a single 32-bit store. */
25275 }
25276 else
25277 {
25280 /* Depending on the static chain location, either load a register
25281 with a constant, or push the constant to the stack. All of the
25282 instructions are the same size. */
25285 {
25287 {
25294 }
25295 }
25296 else
25311 /* Compute offset from the end of the jmp to the target function.
25312 In the case in which the trampoline stores the static chain on
25313 the stack, we need to skip the first insn which pushes the
25314 (call-saved) register static chain; this push is 1 byte. */
25321 }
25325 #ifdef HAVE_ENABLE_EXECUTE_STACK
25326 #ifdef CHECK_EXECUTE_STACK_ENABLED
25328 #endif
25331 #endif
25332 }
25333 \f
25334 /* The following file contains several enumerations and data structures
25335 built from the definitions in i386-builtin-types.def. */
25339 /* Table for the ix86 builtin non-function types. */
25342 /* Retrieve an element from the above table, building some of
25343 the types lazily. */
25345 static tree
25347 {
25359 {
25367 }
25368 else
25369 {
25375 else
25383 }
25387 }
25389 /* Table for the ix86 builtin function types. */
25392 /* Retrieve an element from the above table, building some of
25393 the types lazily. */
25395 static tree
25397 {
25398 tree type;
25407 {
25415 {
25418 }
25421 }
25422 else
25423 {
25429 }
25433 }
25436 /* Codes for all the SSE/MMX builtins. */
25437 enum ix86_builtins
25438 {
25439 IX86_BUILTIN_ADDPS,
25440 IX86_BUILTIN_ADDSS,
25441 IX86_BUILTIN_DIVPS,
25442 IX86_BUILTIN_DIVSS,
25443 IX86_BUILTIN_MULPS,
25444 IX86_BUILTIN_MULSS,
25445 IX86_BUILTIN_SUBPS,
25446 IX86_BUILTIN_SUBSS,
25448 IX86_BUILTIN_CMPEQPS,
25449 IX86_BUILTIN_CMPLTPS,
25450 IX86_BUILTIN_CMPLEPS,
25451 IX86_BUILTIN_CMPGTPS,
25452 IX86_BUILTIN_CMPGEPS,
25453 IX86_BUILTIN_CMPNEQPS,
25454 IX86_BUILTIN_CMPNLTPS,
25455 IX86_BUILTIN_CMPNLEPS,
25456 IX86_BUILTIN_CMPNGTPS,
25457 IX86_BUILTIN_CMPNGEPS,
25458 IX86_BUILTIN_CMPORDPS,
25459 IX86_BUILTIN_CMPUNORDPS,
25460 IX86_BUILTIN_CMPEQSS,
25461 IX86_BUILTIN_CMPLTSS,
25462 IX86_BUILTIN_CMPLESS,
25463 IX86_BUILTIN_CMPNEQSS,
25464 IX86_BUILTIN_CMPNLTSS,
25465 IX86_BUILTIN_CMPNLESS,
25466 IX86_BUILTIN_CMPNGTSS,
25467 IX86_BUILTIN_CMPNGESS,
25468 IX86_BUILTIN_CMPORDSS,
25469 IX86_BUILTIN_CMPUNORDSS,
25471 IX86_BUILTIN_COMIEQSS,
25472 IX86_BUILTIN_COMILTSS,
25473 IX86_BUILTIN_COMILESS,
25474 IX86_BUILTIN_COMIGTSS,
25475 IX86_BUILTIN_COMIGESS,
25476 IX86_BUILTIN_COMINEQSS,
25477 IX86_BUILTIN_UCOMIEQSS,
25478 IX86_BUILTIN_UCOMILTSS,
25479 IX86_BUILTIN_UCOMILESS,
25480 IX86_BUILTIN_UCOMIGTSS,
25481 IX86_BUILTIN_UCOMIGESS,
25482 IX86_BUILTIN_UCOMINEQSS,
25484 IX86_BUILTIN_CVTPI2PS,
25485 IX86_BUILTIN_CVTPS2PI,
25486 IX86_BUILTIN_CVTSI2SS,
25487 IX86_BUILTIN_CVTSI642SS,
25488 IX86_BUILTIN_CVTSS2SI,
25489 IX86_BUILTIN_CVTSS2SI64,
25490 IX86_BUILTIN_CVTTPS2PI,
25491 IX86_BUILTIN_CVTTSS2SI,
25492 IX86_BUILTIN_CVTTSS2SI64,
25494 IX86_BUILTIN_MAXPS,
25495 IX86_BUILTIN_MAXSS,
25496 IX86_BUILTIN_MINPS,
25497 IX86_BUILTIN_MINSS,
25499 IX86_BUILTIN_LOADUPS,
25500 IX86_BUILTIN_STOREUPS,
25501 IX86_BUILTIN_MOVSS,
25503 IX86_BUILTIN_MOVHLPS,
25504 IX86_BUILTIN_MOVLHPS,
25505 IX86_BUILTIN_LOADHPS,
25506 IX86_BUILTIN_LOADLPS,
25507 IX86_BUILTIN_STOREHPS,
25508 IX86_BUILTIN_STORELPS,
25510 IX86_BUILTIN_MASKMOVQ,
25511 IX86_BUILTIN_MOVMSKPS,
25512 IX86_BUILTIN_PMOVMSKB,
25514 IX86_BUILTIN_MOVNTPS,
25515 IX86_BUILTIN_MOVNTQ,
25517 IX86_BUILTIN_LOADDQU,
25518 IX86_BUILTIN_STOREDQU,
25520 IX86_BUILTIN_PACKSSWB,
25521 IX86_BUILTIN_PACKSSDW,
25522 IX86_BUILTIN_PACKUSWB,
25524 IX86_BUILTIN_PADDB,
25525 IX86_BUILTIN_PADDW,
25526 IX86_BUILTIN_PADDD,
25527 IX86_BUILTIN_PADDQ,
25528 IX86_BUILTIN_PADDSB,
25529 IX86_BUILTIN_PADDSW,
25530 IX86_BUILTIN_PADDUSB,
25531 IX86_BUILTIN_PADDUSW,
25532 IX86_BUILTIN_PSUBB,
25533 IX86_BUILTIN_PSUBW,
25534 IX86_BUILTIN_PSUBD,
25535 IX86_BUILTIN_PSUBQ,
25536 IX86_BUILTIN_PSUBSB,
25537 IX86_BUILTIN_PSUBSW,
25538 IX86_BUILTIN_PSUBUSB,
25539 IX86_BUILTIN_PSUBUSW,
25541 IX86_BUILTIN_PAND,
25542 IX86_BUILTIN_PANDN,
25543 IX86_BUILTIN_POR,
25544 IX86_BUILTIN_PXOR,
25546 IX86_BUILTIN_PAVGB,
25547 IX86_BUILTIN_PAVGW,
25549 IX86_BUILTIN_PCMPEQB,
25550 IX86_BUILTIN_PCMPEQW,
25551 IX86_BUILTIN_PCMPEQD,
25552 IX86_BUILTIN_PCMPGTB,
25553 IX86_BUILTIN_PCMPGTW,
25554 IX86_BUILTIN_PCMPGTD,
25556 IX86_BUILTIN_PMADDWD,
25558 IX86_BUILTIN_PMAXSW,
25559 IX86_BUILTIN_PMAXUB,
25560 IX86_BUILTIN_PMINSW,
25561 IX86_BUILTIN_PMINUB,
25563 IX86_BUILTIN_PMULHUW,
25564 IX86_BUILTIN_PMULHW,
25565 IX86_BUILTIN_PMULLW,
25567 IX86_BUILTIN_PSADBW,
25568 IX86_BUILTIN_PSHUFW,
25570 IX86_BUILTIN_PSLLW,
25571 IX86_BUILTIN_PSLLD,
25572 IX86_BUILTIN_PSLLQ,
25573 IX86_BUILTIN_PSRAW,
25574 IX86_BUILTIN_PSRAD,
25575 IX86_BUILTIN_PSRLW,
25576 IX86_BUILTIN_PSRLD,
25577 IX86_BUILTIN_PSRLQ,
25578 IX86_BUILTIN_PSLLWI,
25579 IX86_BUILTIN_PSLLDI,
25580 IX86_BUILTIN_PSLLQI,
25581 IX86_BUILTIN_PSRAWI,
25582 IX86_BUILTIN_PSRADI,
25583 IX86_BUILTIN_PSRLWI,
25584 IX86_BUILTIN_PSRLDI,
25585 IX86_BUILTIN_PSRLQI,
25587 IX86_BUILTIN_PUNPCKHBW,
25588 IX86_BUILTIN_PUNPCKHWD,
25589 IX86_BUILTIN_PUNPCKHDQ,
25590 IX86_BUILTIN_PUNPCKLBW,
25591 IX86_BUILTIN_PUNPCKLWD,
25592 IX86_BUILTIN_PUNPCKLDQ,
25594 IX86_BUILTIN_SHUFPS,
25596 IX86_BUILTIN_RCPPS,
25597 IX86_BUILTIN_RCPSS,
25598 IX86_BUILTIN_RSQRTPS,
25599 IX86_BUILTIN_RSQRTPS_NR,
25600 IX86_BUILTIN_RSQRTSS,
25601 IX86_BUILTIN_RSQRTF,
25602 IX86_BUILTIN_SQRTPS,
25603 IX86_BUILTIN_SQRTPS_NR,
25604 IX86_BUILTIN_SQRTSS,
25606 IX86_BUILTIN_UNPCKHPS,
25607 IX86_BUILTIN_UNPCKLPS,
25609 IX86_BUILTIN_ANDPS,
25610 IX86_BUILTIN_ANDNPS,
25611 IX86_BUILTIN_ORPS,
25612 IX86_BUILTIN_XORPS,
25614 IX86_BUILTIN_EMMS,
25615 IX86_BUILTIN_LDMXCSR,
25616 IX86_BUILTIN_STMXCSR,
25617 IX86_BUILTIN_SFENCE,
25619 IX86_BUILTIN_FXSAVE,
25620 IX86_BUILTIN_FXRSTOR,
25621 IX86_BUILTIN_FXSAVE64,
25622 IX86_BUILTIN_FXRSTOR64,
25624 IX86_BUILTIN_XSAVE,
25625 IX86_BUILTIN_XRSTOR,
25626 IX86_BUILTIN_XSAVE64,
25627 IX86_BUILTIN_XRSTOR64,
25629 IX86_BUILTIN_XSAVEOPT,
25630 IX86_BUILTIN_XSAVEOPT64,
25632 /* 3DNow! Original */
25633 IX86_BUILTIN_FEMMS,
25634 IX86_BUILTIN_PAVGUSB,
25635 IX86_BUILTIN_PF2ID,
25636 IX86_BUILTIN_PFACC,
25637 IX86_BUILTIN_PFADD,
25638 IX86_BUILTIN_PFCMPEQ,
25639 IX86_BUILTIN_PFCMPGE,
25640 IX86_BUILTIN_PFCMPGT,
25641 IX86_BUILTIN_PFMAX,
25642 IX86_BUILTIN_PFMIN,
25643 IX86_BUILTIN_PFMUL,
25644 IX86_BUILTIN_PFRCP,
25645 IX86_BUILTIN_PFRCPIT1,
25646 IX86_BUILTIN_PFRCPIT2,
25647 IX86_BUILTIN_PFRSQIT1,
25648 IX86_BUILTIN_PFRSQRT,
25649 IX86_BUILTIN_PFSUB,
25650 IX86_BUILTIN_PFSUBR,
25651 IX86_BUILTIN_PI2FD,
25652 IX86_BUILTIN_PMULHRW,
25654 /* 3DNow! Athlon Extensions */
25655 IX86_BUILTIN_PF2IW,
25656 IX86_BUILTIN_PFNACC,
25657 IX86_BUILTIN_PFPNACC,
25658 IX86_BUILTIN_PI2FW,
25659 IX86_BUILTIN_PSWAPDSI,
25660 IX86_BUILTIN_PSWAPDSF,
25662 /* SSE2 */
25663 IX86_BUILTIN_ADDPD,
25664 IX86_BUILTIN_ADDSD,
25665 IX86_BUILTIN_DIVPD,
25666 IX86_BUILTIN_DIVSD,
25667 IX86_BUILTIN_MULPD,
25668 IX86_BUILTIN_MULSD,
25669 IX86_BUILTIN_SUBPD,
25670 IX86_BUILTIN_SUBSD,
25672 IX86_BUILTIN_CMPEQPD,
25673 IX86_BUILTIN_CMPLTPD,
25674 IX86_BUILTIN_CMPLEPD,
25675 IX86_BUILTIN_CMPGTPD,
25676 IX86_BUILTIN_CMPGEPD,
25677 IX86_BUILTIN_CMPNEQPD,
25678 IX86_BUILTIN_CMPNLTPD,
25679 IX86_BUILTIN_CMPNLEPD,
25680 IX86_BUILTIN_CMPNGTPD,
25681 IX86_BUILTIN_CMPNGEPD,
25682 IX86_BUILTIN_CMPORDPD,
25683 IX86_BUILTIN_CMPUNORDPD,
25684 IX86_BUILTIN_CMPEQSD,
25685 IX86_BUILTIN_CMPLTSD,
25686 IX86_BUILTIN_CMPLESD,
25687 IX86_BUILTIN_CMPNEQSD,
25688 IX86_BUILTIN_CMPNLTSD,
25689 IX86_BUILTIN_CMPNLESD,
25690 IX86_BUILTIN_CMPORDSD,
25691 IX86_BUILTIN_CMPUNORDSD,
25693 IX86_BUILTIN_COMIEQSD,
25694 IX86_BUILTIN_COMILTSD,
25695 IX86_BUILTIN_COMILESD,
25696 IX86_BUILTIN_COMIGTSD,
25697 IX86_BUILTIN_COMIGESD,
25698 IX86_BUILTIN_COMINEQSD,
25699 IX86_BUILTIN_UCOMIEQSD,
25700 IX86_BUILTIN_UCOMILTSD,
25701 IX86_BUILTIN_UCOMILESD,
25702 IX86_BUILTIN_UCOMIGTSD,
25703 IX86_BUILTIN_UCOMIGESD,
25704 IX86_BUILTIN_UCOMINEQSD,
25706 IX86_BUILTIN_MAXPD,
25707 IX86_BUILTIN_MAXSD,
25708 IX86_BUILTIN_MINPD,
25709 IX86_BUILTIN_MINSD,
25711 IX86_BUILTIN_ANDPD,
25712 IX86_BUILTIN_ANDNPD,
25713 IX86_BUILTIN_ORPD,
25714 IX86_BUILTIN_XORPD,
25716 IX86_BUILTIN_SQRTPD,
25717 IX86_BUILTIN_SQRTSD,
25719 IX86_BUILTIN_UNPCKHPD,
25720 IX86_BUILTIN_UNPCKLPD,
25722 IX86_BUILTIN_SHUFPD,
25724 IX86_BUILTIN_LOADUPD,
25725 IX86_BUILTIN_STOREUPD,
25726 IX86_BUILTIN_MOVSD,
25728 IX86_BUILTIN_LOADHPD,
25729 IX86_BUILTIN_LOADLPD,
25731 IX86_BUILTIN_CVTDQ2PD,
25732 IX86_BUILTIN_CVTDQ2PS,
25734 IX86_BUILTIN_CVTPD2DQ,
25735 IX86_BUILTIN_CVTPD2PI,
25736 IX86_BUILTIN_CVTPD2PS,
25737 IX86_BUILTIN_CVTTPD2DQ,
25738 IX86_BUILTIN_CVTTPD2PI,
25740 IX86_BUILTIN_CVTPI2PD,
25741 IX86_BUILTIN_CVTSI2SD,
25742 IX86_BUILTIN_CVTSI642SD,
25744 IX86_BUILTIN_CVTSD2SI,
25745 IX86_BUILTIN_CVTSD2SI64,
25746 IX86_BUILTIN_CVTSD2SS,
25747 IX86_BUILTIN_CVTSS2SD,
25748 IX86_BUILTIN_CVTTSD2SI,
25749 IX86_BUILTIN_CVTTSD2SI64,
25751 IX86_BUILTIN_CVTPS2DQ,
25752 IX86_BUILTIN_CVTPS2PD,
25753 IX86_BUILTIN_CVTTPS2DQ,
25755 IX86_BUILTIN_MOVNTI,
25756 IX86_BUILTIN_MOVNTI64,
25757 IX86_BUILTIN_MOVNTPD,
25758 IX86_BUILTIN_MOVNTDQ,
25760 IX86_BUILTIN_MOVQ128,
25762 /* SSE2 MMX */
25763 IX86_BUILTIN_MASKMOVDQU,
25764 IX86_BUILTIN_MOVMSKPD,
25765 IX86_BUILTIN_PMOVMSKB128,
25767 IX86_BUILTIN_PACKSSWB128,
25768 IX86_BUILTIN_PACKSSDW128,
25769 IX86_BUILTIN_PACKUSWB128,
25771 IX86_BUILTIN_PADDB128,
25772 IX86_BUILTIN_PADDW128,
25773 IX86_BUILTIN_PADDD128,
25774 IX86_BUILTIN_PADDQ128,
25775 IX86_BUILTIN_PADDSB128,
25776 IX86_BUILTIN_PADDSW128,
25777 IX86_BUILTIN_PADDUSB128,
25778 IX86_BUILTIN_PADDUSW128,
25779 IX86_BUILTIN_PSUBB128,
25780 IX86_BUILTIN_PSUBW128,
25781 IX86_BUILTIN_PSUBD128,
25782 IX86_BUILTIN_PSUBQ128,
25783 IX86_BUILTIN_PSUBSB128,
25784 IX86_BUILTIN_PSUBSW128,
25785 IX86_BUILTIN_PSUBUSB128,
25786 IX86_BUILTIN_PSUBUSW128,
25788 IX86_BUILTIN_PAND128,
25789 IX86_BUILTIN_PANDN128,
25790 IX86_BUILTIN_POR128,
25791 IX86_BUILTIN_PXOR128,
25793 IX86_BUILTIN_PAVGB128,
25794 IX86_BUILTIN_PAVGW128,
25796 IX86_BUILTIN_PCMPEQB128,
25797 IX86_BUILTIN_PCMPEQW128,
25798 IX86_BUILTIN_PCMPEQD128,
25799 IX86_BUILTIN_PCMPGTB128,
25800 IX86_BUILTIN_PCMPGTW128,
25801 IX86_BUILTIN_PCMPGTD128,
25803 IX86_BUILTIN_PMADDWD128,
25805 IX86_BUILTIN_PMAXSW128,
25806 IX86_BUILTIN_PMAXUB128,
25807 IX86_BUILTIN_PMINSW128,
25808 IX86_BUILTIN_PMINUB128,
25810 IX86_BUILTIN_PMULUDQ,
25811 IX86_BUILTIN_PMULUDQ128,
25812 IX86_BUILTIN_PMULHUW128,
25813 IX86_BUILTIN_PMULHW128,
25814 IX86_BUILTIN_PMULLW128,
25816 IX86_BUILTIN_PSADBW128,
25817 IX86_BUILTIN_PSHUFHW,
25818 IX86_BUILTIN_PSHUFLW,
25819 IX86_BUILTIN_PSHUFD,
25821 IX86_BUILTIN_PSLLDQI128,
25822 IX86_BUILTIN_PSLLWI128,
25823 IX86_BUILTIN_PSLLDI128,
25824 IX86_BUILTIN_PSLLQI128,
25825 IX86_BUILTIN_PSRAWI128,
25826 IX86_BUILTIN_PSRADI128,
25827 IX86_BUILTIN_PSRLDQI128,
25828 IX86_BUILTIN_PSRLWI128,
25829 IX86_BUILTIN_PSRLDI128,
25830 IX86_BUILTIN_PSRLQI128,
25832 IX86_BUILTIN_PSLLDQ128,
25833 IX86_BUILTIN_PSLLW128,
25834 IX86_BUILTIN_PSLLD128,
25835 IX86_BUILTIN_PSLLQ128,
25836 IX86_BUILTIN_PSRAW128,
25837 IX86_BUILTIN_PSRAD128,
25838 IX86_BUILTIN_PSRLW128,
25839 IX86_BUILTIN_PSRLD128,
25840 IX86_BUILTIN_PSRLQ128,
25842 IX86_BUILTIN_PUNPCKHBW128,
25843 IX86_BUILTIN_PUNPCKHWD128,
25844 IX86_BUILTIN_PUNPCKHDQ128,
25845 IX86_BUILTIN_PUNPCKHQDQ128,
25846 IX86_BUILTIN_PUNPCKLBW128,
25847 IX86_BUILTIN_PUNPCKLWD128,
25848 IX86_BUILTIN_PUNPCKLDQ128,
25849 IX86_BUILTIN_PUNPCKLQDQ128,
25851 IX86_BUILTIN_CLFLUSH,
25852 IX86_BUILTIN_MFENCE,
25853 IX86_BUILTIN_LFENCE,
25854 IX86_BUILTIN_PAUSE,
25856 IX86_BUILTIN_BSRSI,
25857 IX86_BUILTIN_BSRDI,
25858 IX86_BUILTIN_RDPMC,
25859 IX86_BUILTIN_RDTSC,
25860 IX86_BUILTIN_RDTSCP,
25861 IX86_BUILTIN_ROLQI,
25862 IX86_BUILTIN_ROLHI,
25863 IX86_BUILTIN_RORQI,
25864 IX86_BUILTIN_RORHI,
25866 /* SSE3. */
25867 IX86_BUILTIN_ADDSUBPS,
25868 IX86_BUILTIN_HADDPS,
25869 IX86_BUILTIN_HSUBPS,
25870 IX86_BUILTIN_MOVSHDUP,
25871 IX86_BUILTIN_MOVSLDUP,
25872 IX86_BUILTIN_ADDSUBPD,
25873 IX86_BUILTIN_HADDPD,
25874 IX86_BUILTIN_HSUBPD,
25875 IX86_BUILTIN_LDDQU,
25877 IX86_BUILTIN_MONITOR,
25878 IX86_BUILTIN_MWAIT,
25880 /* SSSE3. */
25881 IX86_BUILTIN_PHADDW,
25882 IX86_BUILTIN_PHADDD,
25883 IX86_BUILTIN_PHADDSW,
25884 IX86_BUILTIN_PHSUBW,
25885 IX86_BUILTIN_PHSUBD,
25886 IX86_BUILTIN_PHSUBSW,
25887 IX86_BUILTIN_PMADDUBSW,
25888 IX86_BUILTIN_PMULHRSW,
25889 IX86_BUILTIN_PSHUFB,
25890 IX86_BUILTIN_PSIGNB,
25891 IX86_BUILTIN_PSIGNW,
25892 IX86_BUILTIN_PSIGND,
25893 IX86_BUILTIN_PALIGNR,
25894 IX86_BUILTIN_PABSB,
25895 IX86_BUILTIN_PABSW,
25896 IX86_BUILTIN_PABSD,
25898 IX86_BUILTIN_PHADDW128,
25899 IX86_BUILTIN_PHADDD128,
25900 IX86_BUILTIN_PHADDSW128,
25901 IX86_BUILTIN_PHSUBW128,
25902 IX86_BUILTIN_PHSUBD128,
25903 IX86_BUILTIN_PHSUBSW128,
25904 IX86_BUILTIN_PMADDUBSW128,
25905 IX86_BUILTIN_PMULHRSW128,
25906 IX86_BUILTIN_PSHUFB128,
25907 IX86_BUILTIN_PSIGNB128,
25908 IX86_BUILTIN_PSIGNW128,
25909 IX86_BUILTIN_PSIGND128,
25910 IX86_BUILTIN_PALIGNR128,
25911 IX86_BUILTIN_PABSB128,
25912 IX86_BUILTIN_PABSW128,
25913 IX86_BUILTIN_PABSD128,
25915 /* AMDFAM10 - SSE4A New Instructions. */
25916 IX86_BUILTIN_MOVNTSD,
25917 IX86_BUILTIN_MOVNTSS,
25918 IX86_BUILTIN_EXTRQI,
25919 IX86_BUILTIN_EXTRQ,
25920 IX86_BUILTIN_INSERTQI,
25921 IX86_BUILTIN_INSERTQ,
25923 /* SSE4.1. */
25924 IX86_BUILTIN_BLENDPD,
25925 IX86_BUILTIN_BLENDPS,
25926 IX86_BUILTIN_BLENDVPD,
25927 IX86_BUILTIN_BLENDVPS,
25928 IX86_BUILTIN_PBLENDVB128,
25929 IX86_BUILTIN_PBLENDW128,
25931 IX86_BUILTIN_DPPD,
25932 IX86_BUILTIN_DPPS,
25934 IX86_BUILTIN_INSERTPS128,
25936 IX86_BUILTIN_MOVNTDQA,
25937 IX86_BUILTIN_MPSADBW128,
25938 IX86_BUILTIN_PACKUSDW128,
25939 IX86_BUILTIN_PCMPEQQ,
25940 IX86_BUILTIN_PHMINPOSUW128,
25942 IX86_BUILTIN_PMAXSB128,
25943 IX86_BUILTIN_PMAXSD128,
25944 IX86_BUILTIN_PMAXUD128,
25945 IX86_BUILTIN_PMAXUW128,
25947 IX86_BUILTIN_PMINSB128,
25948 IX86_BUILTIN_PMINSD128,
25949 IX86_BUILTIN_PMINUD128,
25950 IX86_BUILTIN_PMINUW128,
25952 IX86_BUILTIN_PMOVSXBW128,
25953 IX86_BUILTIN_PMOVSXBD128,
25954 IX86_BUILTIN_PMOVSXBQ128,
25955 IX86_BUILTIN_PMOVSXWD128,
25956 IX86_BUILTIN_PMOVSXWQ128,
25957 IX86_BUILTIN_PMOVSXDQ128,
25959 IX86_BUILTIN_PMOVZXBW128,
25960 IX86_BUILTIN_PMOVZXBD128,
25961 IX86_BUILTIN_PMOVZXBQ128,
25962 IX86_BUILTIN_PMOVZXWD128,
25963 IX86_BUILTIN_PMOVZXWQ128,
25964 IX86_BUILTIN_PMOVZXDQ128,
25966 IX86_BUILTIN_PMULDQ128,
25967 IX86_BUILTIN_PMULLD128,
25969 IX86_BUILTIN_ROUNDSD,
25970 IX86_BUILTIN_ROUNDSS,
25972 IX86_BUILTIN_ROUNDPD,
25973 IX86_BUILTIN_ROUNDPS,
25975 IX86_BUILTIN_FLOORPD,
25976 IX86_BUILTIN_CEILPD,
25977 IX86_BUILTIN_TRUNCPD,
25978 IX86_BUILTIN_RINTPD,
25979 IX86_BUILTIN_ROUNDPD_AZ,
25981 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
25982 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
25983 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
25985 IX86_BUILTIN_FLOORPS,
25986 IX86_BUILTIN_CEILPS,
25987 IX86_BUILTIN_TRUNCPS,
25988 IX86_BUILTIN_RINTPS,
25989 IX86_BUILTIN_ROUNDPS_AZ,
25991 IX86_BUILTIN_FLOORPS_SFIX,
25992 IX86_BUILTIN_CEILPS_SFIX,
25993 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
25995 IX86_BUILTIN_PTESTZ,
25996 IX86_BUILTIN_PTESTC,
25997 IX86_BUILTIN_PTESTNZC,
25999 IX86_BUILTIN_VEC_INIT_V2SI,
26000 IX86_BUILTIN_VEC_INIT_V4HI,
26001 IX86_BUILTIN_VEC_INIT_V8QI,
26002 IX86_BUILTIN_VEC_EXT_V2DF,
26003 IX86_BUILTIN_VEC_EXT_V2DI,
26004 IX86_BUILTIN_VEC_EXT_V4SF,
26005 IX86_BUILTIN_VEC_EXT_V4SI,
26006 IX86_BUILTIN_VEC_EXT_V8HI,
26007 IX86_BUILTIN_VEC_EXT_V2SI,
26008 IX86_BUILTIN_VEC_EXT_V4HI,
26009 IX86_BUILTIN_VEC_EXT_V16QI,
26010 IX86_BUILTIN_VEC_SET_V2DI,
26011 IX86_BUILTIN_VEC_SET_V4SF,
26012 IX86_BUILTIN_VEC_SET_V4SI,
26013 IX86_BUILTIN_VEC_SET_V8HI,
26014 IX86_BUILTIN_VEC_SET_V4HI,
26015 IX86_BUILTIN_VEC_SET_V16QI,
26017 IX86_BUILTIN_VEC_PACK_SFIX,
26018 IX86_BUILTIN_VEC_PACK_SFIX256,
26020 /* SSE4.2. */
26021 IX86_BUILTIN_CRC32QI,
26022 IX86_BUILTIN_CRC32HI,
26023 IX86_BUILTIN_CRC32SI,
26024 IX86_BUILTIN_CRC32DI,
26026 IX86_BUILTIN_PCMPESTRI128,
26027 IX86_BUILTIN_PCMPESTRM128,
26028 IX86_BUILTIN_PCMPESTRA128,
26029 IX86_BUILTIN_PCMPESTRC128,
26030 IX86_BUILTIN_PCMPESTRO128,
26031 IX86_BUILTIN_PCMPESTRS128,
26032 IX86_BUILTIN_PCMPESTRZ128,
26033 IX86_BUILTIN_PCMPISTRI128,
26034 IX86_BUILTIN_PCMPISTRM128,
26035 IX86_BUILTIN_PCMPISTRA128,
26036 IX86_BUILTIN_PCMPISTRC128,
26037 IX86_BUILTIN_PCMPISTRO128,
26038 IX86_BUILTIN_PCMPISTRS128,
26039 IX86_BUILTIN_PCMPISTRZ128,
26041 IX86_BUILTIN_PCMPGTQ,
26043 /* AES instructions */
26044 IX86_BUILTIN_AESENC128,
26045 IX86_BUILTIN_AESENCLAST128,
26046 IX86_BUILTIN_AESDEC128,
26047 IX86_BUILTIN_AESDECLAST128,
26048 IX86_BUILTIN_AESIMC128,
26049 IX86_BUILTIN_AESKEYGENASSIST128,
26051 /* PCLMUL instruction */
26052 IX86_BUILTIN_PCLMULQDQ128,
26054 /* AVX */
26055 IX86_BUILTIN_ADDPD256,
26056 IX86_BUILTIN_ADDPS256,
26057 IX86_BUILTIN_ADDSUBPD256,
26058 IX86_BUILTIN_ADDSUBPS256,
26059 IX86_BUILTIN_ANDPD256,
26060 IX86_BUILTIN_ANDPS256,
26061 IX86_BUILTIN_ANDNPD256,
26062 IX86_BUILTIN_ANDNPS256,
26063 IX86_BUILTIN_BLENDPD256,
26064 IX86_BUILTIN_BLENDPS256,
26065 IX86_BUILTIN_BLENDVPD256,
26066 IX86_BUILTIN_BLENDVPS256,
26067 IX86_BUILTIN_DIVPD256,
26068 IX86_BUILTIN_DIVPS256,
26069 IX86_BUILTIN_DPPS256,
26070 IX86_BUILTIN_HADDPD256,
26071 IX86_BUILTIN_HADDPS256,
26072 IX86_BUILTIN_HSUBPD256,
26073 IX86_BUILTIN_HSUBPS256,
26074 IX86_BUILTIN_MAXPD256,
26075 IX86_BUILTIN_MAXPS256,
26076 IX86_BUILTIN_MINPD256,
26077 IX86_BUILTIN_MINPS256,
26078 IX86_BUILTIN_MULPD256,
26079 IX86_BUILTIN_MULPS256,
26080 IX86_BUILTIN_ORPD256,
26081 IX86_BUILTIN_ORPS256,
26082 IX86_BUILTIN_SHUFPD256,
26083 IX86_BUILTIN_SHUFPS256,
26084 IX86_BUILTIN_SUBPD256,
26085 IX86_BUILTIN_SUBPS256,
26086 IX86_BUILTIN_XORPD256,
26087 IX86_BUILTIN_XORPS256,
26088 IX86_BUILTIN_CMPSD,
26089 IX86_BUILTIN_CMPSS,
26090 IX86_BUILTIN_CMPPD,
26091 IX86_BUILTIN_CMPPS,
26092 IX86_BUILTIN_CMPPD256,
26093 IX86_BUILTIN_CMPPS256,
26094 IX86_BUILTIN_CVTDQ2PD256,
26095 IX86_BUILTIN_CVTDQ2PS256,
26096 IX86_BUILTIN_CVTPD2PS256,
26097 IX86_BUILTIN_CVTPS2DQ256,
26098 IX86_BUILTIN_CVTPS2PD256,
26099 IX86_BUILTIN_CVTTPD2DQ256,
26100 IX86_BUILTIN_CVTPD2DQ256,
26101 IX86_BUILTIN_CVTTPS2DQ256,
26102 IX86_BUILTIN_EXTRACTF128PD256,
26103 IX86_BUILTIN_EXTRACTF128PS256,
26104 IX86_BUILTIN_EXTRACTF128SI256,
26105 IX86_BUILTIN_VZEROALL,
26106 IX86_BUILTIN_VZEROUPPER,
26107 IX86_BUILTIN_VPERMILVARPD,
26108 IX86_BUILTIN_VPERMILVARPS,
26109 IX86_BUILTIN_VPERMILVARPD256,
26110 IX86_BUILTIN_VPERMILVARPS256,
26111 IX86_BUILTIN_VPERMILPD,
26112 IX86_BUILTIN_VPERMILPS,
26113 IX86_BUILTIN_VPERMILPD256,
26114 IX86_BUILTIN_VPERMILPS256,
26115 IX86_BUILTIN_VPERMIL2PD,
26116 IX86_BUILTIN_VPERMIL2PS,
26117 IX86_BUILTIN_VPERMIL2PD256,
26118 IX86_BUILTIN_VPERMIL2PS256,
26119 IX86_BUILTIN_VPERM2F128PD256,
26120 IX86_BUILTIN_VPERM2F128PS256,
26121 IX86_BUILTIN_VPERM2F128SI256,
26122 IX86_BUILTIN_VBROADCASTSS,
26123 IX86_BUILTIN_VBROADCASTSD256,
26124 IX86_BUILTIN_VBROADCASTSS256,
26125 IX86_BUILTIN_VBROADCASTPD256,
26126 IX86_BUILTIN_VBROADCASTPS256,
26127 IX86_BUILTIN_VINSERTF128PD256,
26128 IX86_BUILTIN_VINSERTF128PS256,
26129 IX86_BUILTIN_VINSERTF128SI256,
26130 IX86_BUILTIN_LOADUPD256,
26131 IX86_BUILTIN_LOADUPS256,
26132 IX86_BUILTIN_STOREUPD256,
26133 IX86_BUILTIN_STOREUPS256,
26134 IX86_BUILTIN_LDDQU256,
26135 IX86_BUILTIN_MOVNTDQ256,
26136 IX86_BUILTIN_MOVNTPD256,
26137 IX86_BUILTIN_MOVNTPS256,
26138 IX86_BUILTIN_LOADDQU256,
26139 IX86_BUILTIN_STOREDQU256,
26140 IX86_BUILTIN_MASKLOADPD,
26141 IX86_BUILTIN_MASKLOADPS,
26142 IX86_BUILTIN_MASKSTOREPD,
26143 IX86_BUILTIN_MASKSTOREPS,
26144 IX86_BUILTIN_MASKLOADPD256,
26145 IX86_BUILTIN_MASKLOADPS256,
26146 IX86_BUILTIN_MASKSTOREPD256,
26147 IX86_BUILTIN_MASKSTOREPS256,
26148 IX86_BUILTIN_MOVSHDUP256,
26149 IX86_BUILTIN_MOVSLDUP256,
26150 IX86_BUILTIN_MOVDDUP256,
26152 IX86_BUILTIN_SQRTPD256,
26153 IX86_BUILTIN_SQRTPS256,
26154 IX86_BUILTIN_SQRTPS_NR256,
26155 IX86_BUILTIN_RSQRTPS256,
26156 IX86_BUILTIN_RSQRTPS_NR256,
26158 IX86_BUILTIN_RCPPS256,
26160 IX86_BUILTIN_ROUNDPD256,
26161 IX86_BUILTIN_ROUNDPS256,
26163 IX86_BUILTIN_FLOORPD256,
26164 IX86_BUILTIN_CEILPD256,
26165 IX86_BUILTIN_TRUNCPD256,
26166 IX86_BUILTIN_RINTPD256,
26167 IX86_BUILTIN_ROUNDPD_AZ256,
26169 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26170 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26171 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26173 IX86_BUILTIN_FLOORPS256,
26174 IX86_BUILTIN_CEILPS256,
26175 IX86_BUILTIN_TRUNCPS256,
26176 IX86_BUILTIN_RINTPS256,
26177 IX86_BUILTIN_ROUNDPS_AZ256,
26179 IX86_BUILTIN_FLOORPS_SFIX256,
26180 IX86_BUILTIN_CEILPS_SFIX256,
26181 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26183 IX86_BUILTIN_UNPCKHPD256,
26184 IX86_BUILTIN_UNPCKLPD256,
26185 IX86_BUILTIN_UNPCKHPS256,
26186 IX86_BUILTIN_UNPCKLPS256,
26188 IX86_BUILTIN_SI256_SI,
26189 IX86_BUILTIN_PS256_PS,
26190 IX86_BUILTIN_PD256_PD,
26191 IX86_BUILTIN_SI_SI256,
26192 IX86_BUILTIN_PS_PS256,
26193 IX86_BUILTIN_PD_PD256,
26195 IX86_BUILTIN_VTESTZPD,
26196 IX86_BUILTIN_VTESTCPD,
26197 IX86_BUILTIN_VTESTNZCPD,
26198 IX86_BUILTIN_VTESTZPS,
26199 IX86_BUILTIN_VTESTCPS,
26200 IX86_BUILTIN_VTESTNZCPS,
26201 IX86_BUILTIN_VTESTZPD256,
26202 IX86_BUILTIN_VTESTCPD256,
26203 IX86_BUILTIN_VTESTNZCPD256,
26204 IX86_BUILTIN_VTESTZPS256,
26205 IX86_BUILTIN_VTESTCPS256,
26206 IX86_BUILTIN_VTESTNZCPS256,
26207 IX86_BUILTIN_PTESTZ256,
26208 IX86_BUILTIN_PTESTC256,
26209 IX86_BUILTIN_PTESTNZC256,
26211 IX86_BUILTIN_MOVMSKPD256,
26212 IX86_BUILTIN_MOVMSKPS256,
26214 /* AVX2 */
26215 IX86_BUILTIN_MPSADBW256,
26216 IX86_BUILTIN_PABSB256,
26217 IX86_BUILTIN_PABSW256,
26218 IX86_BUILTIN_PABSD256,
26219 IX86_BUILTIN_PACKSSDW256,
26220 IX86_BUILTIN_PACKSSWB256,
26221 IX86_BUILTIN_PACKUSDW256,
26222 IX86_BUILTIN_PACKUSWB256,
26223 IX86_BUILTIN_PADDB256,
26224 IX86_BUILTIN_PADDW256,
26225 IX86_BUILTIN_PADDD256,
26226 IX86_BUILTIN_PADDQ256,
26227 IX86_BUILTIN_PADDSB256,
26228 IX86_BUILTIN_PADDSW256,
26229 IX86_BUILTIN_PADDUSB256,
26230 IX86_BUILTIN_PADDUSW256,
26231 IX86_BUILTIN_PALIGNR256,
26232 IX86_BUILTIN_AND256I,
26233 IX86_BUILTIN_ANDNOT256I,
26234 IX86_BUILTIN_PAVGB256,
26235 IX86_BUILTIN_PAVGW256,
26236 IX86_BUILTIN_PBLENDVB256,
26237 IX86_BUILTIN_PBLENDVW256,
26238 IX86_BUILTIN_PCMPEQB256,
26239 IX86_BUILTIN_PCMPEQW256,
26240 IX86_BUILTIN_PCMPEQD256,
26241 IX86_BUILTIN_PCMPEQQ256,
26242 IX86_BUILTIN_PCMPGTB256,
26243 IX86_BUILTIN_PCMPGTW256,
26244 IX86_BUILTIN_PCMPGTD256,
26245 IX86_BUILTIN_PCMPGTQ256,
26246 IX86_BUILTIN_PHADDW256,
26247 IX86_BUILTIN_PHADDD256,
26248 IX86_BUILTIN_PHADDSW256,
26249 IX86_BUILTIN_PHSUBW256,
26250 IX86_BUILTIN_PHSUBD256,
26251 IX86_BUILTIN_PHSUBSW256,
26252 IX86_BUILTIN_PMADDUBSW256,
26253 IX86_BUILTIN_PMADDWD256,
26254 IX86_BUILTIN_PMAXSB256,
26255 IX86_BUILTIN_PMAXSW256,
26256 IX86_BUILTIN_PMAXSD256,
26257 IX86_BUILTIN_PMAXUB256,
26258 IX86_BUILTIN_PMAXUW256,
26259 IX86_BUILTIN_PMAXUD256,
26260 IX86_BUILTIN_PMINSB256,
26261 IX86_BUILTIN_PMINSW256,
26262 IX86_BUILTIN_PMINSD256,
26263 IX86_BUILTIN_PMINUB256,
26264 IX86_BUILTIN_PMINUW256,
26265 IX86_BUILTIN_PMINUD256,
26266 IX86_BUILTIN_PMOVMSKB256,
26267 IX86_BUILTIN_PMOVSXBW256,
26268 IX86_BUILTIN_PMOVSXBD256,
26269 IX86_BUILTIN_PMOVSXBQ256,
26270 IX86_BUILTIN_PMOVSXWD256,
26271 IX86_BUILTIN_PMOVSXWQ256,
26272 IX86_BUILTIN_PMOVSXDQ256,
26273 IX86_BUILTIN_PMOVZXBW256,
26274 IX86_BUILTIN_PMOVZXBD256,
26275 IX86_BUILTIN_PMOVZXBQ256,
26276 IX86_BUILTIN_PMOVZXWD256,
26277 IX86_BUILTIN_PMOVZXWQ256,
26278 IX86_BUILTIN_PMOVZXDQ256,
26279 IX86_BUILTIN_PMULDQ256,
26280 IX86_BUILTIN_PMULHRSW256,
26281 IX86_BUILTIN_PMULHUW256,
26282 IX86_BUILTIN_PMULHW256,
26283 IX86_BUILTIN_PMULLW256,
26284 IX86_BUILTIN_PMULLD256,
26285 IX86_BUILTIN_PMULUDQ256,
26286 IX86_BUILTIN_POR256,
26287 IX86_BUILTIN_PSADBW256,
26288 IX86_BUILTIN_PSHUFB256,
26289 IX86_BUILTIN_PSHUFD256,
26290 IX86_BUILTIN_PSHUFHW256,
26291 IX86_BUILTIN_PSHUFLW256,
26292 IX86_BUILTIN_PSIGNB256,
26293 IX86_BUILTIN_PSIGNW256,
26294 IX86_BUILTIN_PSIGND256,
26295 IX86_BUILTIN_PSLLDQI256,
26296 IX86_BUILTIN_PSLLWI256,
26297 IX86_BUILTIN_PSLLW256,
26298 IX86_BUILTIN_PSLLDI256,
26299 IX86_BUILTIN_PSLLD256,
26300 IX86_BUILTIN_PSLLQI256,
26301 IX86_BUILTIN_PSLLQ256,
26302 IX86_BUILTIN_PSRAWI256,
26303 IX86_BUILTIN_PSRAW256,
26304 IX86_BUILTIN_PSRADI256,
26305 IX86_BUILTIN_PSRAD256,
26306 IX86_BUILTIN_PSRLDQI256,
26307 IX86_BUILTIN_PSRLWI256,
26308 IX86_BUILTIN_PSRLW256,
26309 IX86_BUILTIN_PSRLDI256,
26310 IX86_BUILTIN_PSRLD256,
26311 IX86_BUILTIN_PSRLQI256,
26312 IX86_BUILTIN_PSRLQ256,
26313 IX86_BUILTIN_PSUBB256,
26314 IX86_BUILTIN_PSUBW256,
26315 IX86_BUILTIN_PSUBD256,
26316 IX86_BUILTIN_PSUBQ256,
26317 IX86_BUILTIN_PSUBSB256,
26318 IX86_BUILTIN_PSUBSW256,
26319 IX86_BUILTIN_PSUBUSB256,
26320 IX86_BUILTIN_PSUBUSW256,
26321 IX86_BUILTIN_PUNPCKHBW256,
26322 IX86_BUILTIN_PUNPCKHWD256,
26323 IX86_BUILTIN_PUNPCKHDQ256,
26324 IX86_BUILTIN_PUNPCKHQDQ256,
26325 IX86_BUILTIN_PUNPCKLBW256,
26326 IX86_BUILTIN_PUNPCKLWD256,
26327 IX86_BUILTIN_PUNPCKLDQ256,
26328 IX86_BUILTIN_PUNPCKLQDQ256,
26329 IX86_BUILTIN_PXOR256,
26330 IX86_BUILTIN_MOVNTDQA256,
26331 IX86_BUILTIN_VBROADCASTSS_PS,
26332 IX86_BUILTIN_VBROADCASTSS_PS256,
26333 IX86_BUILTIN_VBROADCASTSD_PD256,
26334 IX86_BUILTIN_VBROADCASTSI256,
26335 IX86_BUILTIN_PBLENDD256,
26336 IX86_BUILTIN_PBLENDD128,
26337 IX86_BUILTIN_PBROADCASTB256,
26338 IX86_BUILTIN_PBROADCASTW256,
26339 IX86_BUILTIN_PBROADCASTD256,
26340 IX86_BUILTIN_PBROADCASTQ256,
26341 IX86_BUILTIN_PBROADCASTB128,
26342 IX86_BUILTIN_PBROADCASTW128,
26343 IX86_BUILTIN_PBROADCASTD128,
26344 IX86_BUILTIN_PBROADCASTQ128,
26345 IX86_BUILTIN_VPERMVARSI256,
26346 IX86_BUILTIN_VPERMDF256,
26347 IX86_BUILTIN_VPERMVARSF256,
26348 IX86_BUILTIN_VPERMDI256,
26349 IX86_BUILTIN_VPERMTI256,
26350 IX86_BUILTIN_VEXTRACT128I256,
26351 IX86_BUILTIN_VINSERT128I256,
26352 IX86_BUILTIN_MASKLOADD,
26353 IX86_BUILTIN_MASKLOADQ,
26354 IX86_BUILTIN_MASKLOADD256,
26355 IX86_BUILTIN_MASKLOADQ256,
26356 IX86_BUILTIN_MASKSTORED,
26357 IX86_BUILTIN_MASKSTOREQ,
26358 IX86_BUILTIN_MASKSTORED256,
26359 IX86_BUILTIN_MASKSTOREQ256,
26360 IX86_BUILTIN_PSLLVV4DI,
26361 IX86_BUILTIN_PSLLVV2DI,
26362 IX86_BUILTIN_PSLLVV8SI,
26363 IX86_BUILTIN_PSLLVV4SI,
26364 IX86_BUILTIN_PSRAVV8SI,
26365 IX86_BUILTIN_PSRAVV4SI,
26366 IX86_BUILTIN_PSRLVV4DI,
26367 IX86_BUILTIN_PSRLVV2DI,
26368 IX86_BUILTIN_PSRLVV8SI,
26369 IX86_BUILTIN_PSRLVV4SI,
26371 IX86_BUILTIN_GATHERSIV2DF,
26372 IX86_BUILTIN_GATHERSIV4DF,
26373 IX86_BUILTIN_GATHERDIV2DF,
26374 IX86_BUILTIN_GATHERDIV4DF,
26375 IX86_BUILTIN_GATHERSIV4SF,
26376 IX86_BUILTIN_GATHERSIV8SF,
26377 IX86_BUILTIN_GATHERDIV4SF,
26378 IX86_BUILTIN_GATHERDIV8SF,
26379 IX86_BUILTIN_GATHERSIV2DI,
26380 IX86_BUILTIN_GATHERSIV4DI,
26381 IX86_BUILTIN_GATHERDIV2DI,
26382 IX86_BUILTIN_GATHERDIV4DI,
26383 IX86_BUILTIN_GATHERSIV4SI,
26384 IX86_BUILTIN_GATHERSIV8SI,
26385 IX86_BUILTIN_GATHERDIV4SI,
26386 IX86_BUILTIN_GATHERDIV8SI,
26388 /* Alternate 4 element gather for the vectorizer where
26389 all operands are 32-byte wide. */
26390 IX86_BUILTIN_GATHERALTSIV4DF,
26391 IX86_BUILTIN_GATHERALTDIV8SF,
26392 IX86_BUILTIN_GATHERALTSIV4DI,
26393 IX86_BUILTIN_GATHERALTDIV8SI,
26395 /* TFmode support builtins. */
26396 IX86_BUILTIN_INFQ,
26397 IX86_BUILTIN_HUGE_VALQ,
26398 IX86_BUILTIN_FABSQ,
26399 IX86_BUILTIN_COPYSIGNQ,
26401 /* Vectorizer support builtins. */
26402 IX86_BUILTIN_CPYSGNPS,
26403 IX86_BUILTIN_CPYSGNPD,
26404 IX86_BUILTIN_CPYSGNPS256,
26405 IX86_BUILTIN_CPYSGNPD256,
26407 /* FMA4 instructions. */
26408 IX86_BUILTIN_VFMADDSS,
26409 IX86_BUILTIN_VFMADDSD,
26410 IX86_BUILTIN_VFMADDPS,
26411 IX86_BUILTIN_VFMADDPD,
26412 IX86_BUILTIN_VFMADDPS256,
26413 IX86_BUILTIN_VFMADDPD256,
26414 IX86_BUILTIN_VFMADDSUBPS,
26415 IX86_BUILTIN_VFMADDSUBPD,
26416 IX86_BUILTIN_VFMADDSUBPS256,
26417 IX86_BUILTIN_VFMADDSUBPD256,
26419 /* FMA3 instructions. */
26420 IX86_BUILTIN_VFMADDSS3,
26421 IX86_BUILTIN_VFMADDSD3,
26423 /* XOP instructions. */
26424 IX86_BUILTIN_VPCMOV,
26425 IX86_BUILTIN_VPCMOV_V2DI,
26426 IX86_BUILTIN_VPCMOV_V4SI,
26427 IX86_BUILTIN_VPCMOV_V8HI,
26428 IX86_BUILTIN_VPCMOV_V16QI,
26429 IX86_BUILTIN_VPCMOV_V4SF,
26430 IX86_BUILTIN_VPCMOV_V2DF,
26431 IX86_BUILTIN_VPCMOV256,
26432 IX86_BUILTIN_VPCMOV_V4DI256,
26433 IX86_BUILTIN_VPCMOV_V8SI256,
26434 IX86_BUILTIN_VPCMOV_V16HI256,
26435 IX86_BUILTIN_VPCMOV_V32QI256,
26436 IX86_BUILTIN_VPCMOV_V8SF256,
26437 IX86_BUILTIN_VPCMOV_V4DF256,
26439 IX86_BUILTIN_VPPERM,
26441 IX86_BUILTIN_VPMACSSWW,
26442 IX86_BUILTIN_VPMACSWW,
26443 IX86_BUILTIN_VPMACSSWD,
26444 IX86_BUILTIN_VPMACSWD,
26445 IX86_BUILTIN_VPMACSSDD,
26446 IX86_BUILTIN_VPMACSDD,
26447 IX86_BUILTIN_VPMACSSDQL,
26448 IX86_BUILTIN_VPMACSSDQH,
26449 IX86_BUILTIN_VPMACSDQL,
26450 IX86_BUILTIN_VPMACSDQH,
26451 IX86_BUILTIN_VPMADCSSWD,
26452 IX86_BUILTIN_VPMADCSWD,
26454 IX86_BUILTIN_VPHADDBW,
26455 IX86_BUILTIN_VPHADDBD,
26456 IX86_BUILTIN_VPHADDBQ,
26457 IX86_BUILTIN_VPHADDWD,
26458 IX86_BUILTIN_VPHADDWQ,
26459 IX86_BUILTIN_VPHADDDQ,
26460 IX86_BUILTIN_VPHADDUBW,
26461 IX86_BUILTIN_VPHADDUBD,
26462 IX86_BUILTIN_VPHADDUBQ,
26463 IX86_BUILTIN_VPHADDUWD,
26464 IX86_BUILTIN_VPHADDUWQ,
26465 IX86_BUILTIN_VPHADDUDQ,
26466 IX86_BUILTIN_VPHSUBBW,
26467 IX86_BUILTIN_VPHSUBWD,
26468 IX86_BUILTIN_VPHSUBDQ,
26470 IX86_BUILTIN_VPROTB,
26471 IX86_BUILTIN_VPROTW,
26472 IX86_BUILTIN_VPROTD,
26473 IX86_BUILTIN_VPROTQ,
26474 IX86_BUILTIN_VPROTB_IMM,
26475 IX86_BUILTIN_VPROTW_IMM,
26476 IX86_BUILTIN_VPROTD_IMM,
26477 IX86_BUILTIN_VPROTQ_IMM,
26479 IX86_BUILTIN_VPSHLB,
26480 IX86_BUILTIN_VPSHLW,
26481 IX86_BUILTIN_VPSHLD,
26482 IX86_BUILTIN_VPSHLQ,
26483 IX86_BUILTIN_VPSHAB,
26484 IX86_BUILTIN_VPSHAW,
26485 IX86_BUILTIN_VPSHAD,
26486 IX86_BUILTIN_VPSHAQ,
26488 IX86_BUILTIN_VFRCZSS,
26489 IX86_BUILTIN_VFRCZSD,
26490 IX86_BUILTIN_VFRCZPS,
26491 IX86_BUILTIN_VFRCZPD,
26492 IX86_BUILTIN_VFRCZPS256,
26493 IX86_BUILTIN_VFRCZPD256,
26495 IX86_BUILTIN_VPCOMEQUB,
26496 IX86_BUILTIN_VPCOMNEUB,
26497 IX86_BUILTIN_VPCOMLTUB,
26498 IX86_BUILTIN_VPCOMLEUB,
26499 IX86_BUILTIN_VPCOMGTUB,
26500 IX86_BUILTIN_VPCOMGEUB,
26501 IX86_BUILTIN_VPCOMFALSEUB,
26502 IX86_BUILTIN_VPCOMTRUEUB,
26504 IX86_BUILTIN_VPCOMEQUW,
26505 IX86_BUILTIN_VPCOMNEUW,
26506 IX86_BUILTIN_VPCOMLTUW,
26507 IX86_BUILTIN_VPCOMLEUW,
26508 IX86_BUILTIN_VPCOMGTUW,
26509 IX86_BUILTIN_VPCOMGEUW,
26510 IX86_BUILTIN_VPCOMFALSEUW,
26511 IX86_BUILTIN_VPCOMTRUEUW,
26513 IX86_BUILTIN_VPCOMEQUD,
26514 IX86_BUILTIN_VPCOMNEUD,
26515 IX86_BUILTIN_VPCOMLTUD,
26516 IX86_BUILTIN_VPCOMLEUD,
26517 IX86_BUILTIN_VPCOMGTUD,
26518 IX86_BUILTIN_VPCOMGEUD,
26519 IX86_BUILTIN_VPCOMFALSEUD,
26520 IX86_BUILTIN_VPCOMTRUEUD,
26522 IX86_BUILTIN_VPCOMEQUQ,
26523 IX86_BUILTIN_VPCOMNEUQ,
26524 IX86_BUILTIN_VPCOMLTUQ,
26525 IX86_BUILTIN_VPCOMLEUQ,
26526 IX86_BUILTIN_VPCOMGTUQ,
26527 IX86_BUILTIN_VPCOMGEUQ,
26528 IX86_BUILTIN_VPCOMFALSEUQ,
26529 IX86_BUILTIN_VPCOMTRUEUQ,
26531 IX86_BUILTIN_VPCOMEQB,
26532 IX86_BUILTIN_VPCOMNEB,
26533 IX86_BUILTIN_VPCOMLTB,
26534 IX86_BUILTIN_VPCOMLEB,
26535 IX86_BUILTIN_VPCOMGTB,
26536 IX86_BUILTIN_VPCOMGEB,
26537 IX86_BUILTIN_VPCOMFALSEB,
26538 IX86_BUILTIN_VPCOMTRUEB,
26540 IX86_BUILTIN_VPCOMEQW,
26541 IX86_BUILTIN_VPCOMNEW,
26542 IX86_BUILTIN_VPCOMLTW,
26543 IX86_BUILTIN_VPCOMLEW,
26544 IX86_BUILTIN_VPCOMGTW,
26545 IX86_BUILTIN_VPCOMGEW,
26546 IX86_BUILTIN_VPCOMFALSEW,
26547 IX86_BUILTIN_VPCOMTRUEW,
26549 IX86_BUILTIN_VPCOMEQD,
26550 IX86_BUILTIN_VPCOMNED,
26551 IX86_BUILTIN_VPCOMLTD,
26552 IX86_BUILTIN_VPCOMLED,
26553 IX86_BUILTIN_VPCOMGTD,
26554 IX86_BUILTIN_VPCOMGED,
26555 IX86_BUILTIN_VPCOMFALSED,
26556 IX86_BUILTIN_VPCOMTRUED,
26558 IX86_BUILTIN_VPCOMEQQ,
26559 IX86_BUILTIN_VPCOMNEQ,
26560 IX86_BUILTIN_VPCOMLTQ,
26561 IX86_BUILTIN_VPCOMLEQ,
26562 IX86_BUILTIN_VPCOMGTQ,
26563 IX86_BUILTIN_VPCOMGEQ,
26564 IX86_BUILTIN_VPCOMFALSEQ,
26565 IX86_BUILTIN_VPCOMTRUEQ,
26567 /* LWP instructions. */
26568 IX86_BUILTIN_LLWPCB,
26569 IX86_BUILTIN_SLWPCB,
26570 IX86_BUILTIN_LWPVAL32,
26571 IX86_BUILTIN_LWPVAL64,
26572 IX86_BUILTIN_LWPINS32,
26573 IX86_BUILTIN_LWPINS64,
26575 IX86_BUILTIN_CLZS,
26577 /* RTM */
26578 IX86_BUILTIN_XBEGIN,
26579 IX86_BUILTIN_XEND,
26580 IX86_BUILTIN_XABORT,
26581 IX86_BUILTIN_XTEST,
26583 /* BMI instructions. */
26584 IX86_BUILTIN_BEXTR32,
26585 IX86_BUILTIN_BEXTR64,
26586 IX86_BUILTIN_CTZS,
26588 /* TBM instructions. */
26589 IX86_BUILTIN_BEXTRI32,
26590 IX86_BUILTIN_BEXTRI64,
26592 /* BMI2 instructions. */
26593 IX86_BUILTIN_BZHI32,
26594 IX86_BUILTIN_BZHI64,
26595 IX86_BUILTIN_PDEP32,
26596 IX86_BUILTIN_PDEP64,
26597 IX86_BUILTIN_PEXT32,
26598 IX86_BUILTIN_PEXT64,
26600 /* ADX instructions. */
26601 IX86_BUILTIN_ADDCARRYX32,
26602 IX86_BUILTIN_ADDCARRYX64,
26604 /* FSGSBASE instructions. */
26605 IX86_BUILTIN_RDFSBASE32,
26606 IX86_BUILTIN_RDFSBASE64,
26607 IX86_BUILTIN_RDGSBASE32,
26608 IX86_BUILTIN_RDGSBASE64,
26609 IX86_BUILTIN_WRFSBASE32,
26610 IX86_BUILTIN_WRFSBASE64,
26611 IX86_BUILTIN_WRGSBASE32,
26612 IX86_BUILTIN_WRGSBASE64,
26614 /* RDRND instructions. */
26615 IX86_BUILTIN_RDRAND16_STEP,
26616 IX86_BUILTIN_RDRAND32_STEP,
26617 IX86_BUILTIN_RDRAND64_STEP,
26619 /* RDSEED instructions. */
26620 IX86_BUILTIN_RDSEED16_STEP,
26621 IX86_BUILTIN_RDSEED32_STEP,
26622 IX86_BUILTIN_RDSEED64_STEP,
26624 /* F16C instructions. */
26625 IX86_BUILTIN_CVTPH2PS,
26626 IX86_BUILTIN_CVTPH2PS256,
26627 IX86_BUILTIN_CVTPS2PH,
26628 IX86_BUILTIN_CVTPS2PH256,
26630 /* CFString built-in for darwin */
26631 IX86_BUILTIN_CFSTRING,
26633 /* Builtins to get CPU type and supported features. */
26634 IX86_BUILTIN_CPU_INIT,
26635 IX86_BUILTIN_CPU_IS,
26636 IX86_BUILTIN_CPU_SUPPORTS,
26638 IX86_BUILTIN_MAX
26639 };
26641 /* Table for the ix86 builtin decls. */
26644 /* Table of all of the builtin functions that are possible with different ISA's
26645 but are waiting to be built until a function is declared to use that
26646 ISA. */
26653 };
26658 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
26659 of which isa_flags to use in the ix86_builtins_isa array. Stores the
26660 function decl in the ix86_builtins array. Returns the function decl or
26661 NULL_TREE, if the builtin was not added.
26663 If the front end has a special hook for builtin functions, delay adding
26664 builtin functions that aren't in the current ISA until the ISA is changed
26665 with function specific optimization. Doing so, can save about 300K for the
26666 default compiler. When the builtin is expanded, check at that time whether
26667 it is valid.
26669 If the front end doesn't have a special hook, record all builtins, even if
26670 it isn't an instruction set in the current ISA in case the user uses
26671 function specific options for a different ISA, so that we don't get scope
26672 errors if a builtin is added in the middle of a function scope. */
26678 {
26682 {
26691 {
26697 }
26698 else
26699 {
26705 }
26706 }
26709 }
26711 /* Like def_builtin, but also marks the function decl "const". */
26716 {
26720 else
26724 }
26726 /* Add any new builtin functions for a given ISA that may not have been
26727 declared. This saves a bit of space compared to adding all of the
26728 declarations to the tree, even if we didn't use them. */
26730 static void
26732 {
26736 {
26739 {
26742 /* Don't define the builtin again. */
26748 NULL_TREE);
26753 }
26754 }
26755 }
26757 /* Bits for builtin_description.flag. */
26759 /* Set when we don't support the comparison natively, and should
26760 swap_comparison in order to support it. */
26761 #define BUILTIN_DESC_SWAP_OPERANDS 1
26763 struct builtin_description
26764 {
26771 };
26774 {
26775 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
26776 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
26777 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
26778 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
26779 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
26780 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
26781 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
26782 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
26783 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
26784 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
26785 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
26786 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
26787 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
26788 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
26789 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
26790 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
26791 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
26792 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
26793 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
26794 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
26795 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
26796 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
26797 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
26798 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
26799 };
26802 {
26803 /* SSE4.2 */
26804 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
26805 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
26806 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
26807 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
26808 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
26809 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
26810 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
26811 };
26814 {
26815 /* SSE4.2 */
26816 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
26817 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
26818 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
26819 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
26820 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
26821 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
26822 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
26823 };
26825 /* Special builtins with variable number of arguments. */
26827 {
26828 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
26829 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
26830 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
26832 /* MMX */
26833 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26835 /* 3DNow! */
26836 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26838 /* FXSR, XSAVE and XSAVEOPT */
26839 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
26840 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
26841 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26842 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26843 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26845 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26846 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26847 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26848 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26849 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26851 /* SSE */
26852 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26853 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26854 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26856 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26857 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26858 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26859 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26861 /* SSE or 3DNow!A */
26862 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26863 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
26865 /* SSE2 */
26866 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26867 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26868 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
26870 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26871 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
26872 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
26873 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
26874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
26875 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26877 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26878 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26880 /* SSE3 */
26881 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26883 /* SSE4.1 */
26884 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
26886 /* SSE4A */
26887 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26888 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26890 /* AVX */
26891 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
26892 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
26894 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26895 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26896 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26897 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
26898 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
26900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26901 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26902 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26903 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26904 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26905 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
26906 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26908 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
26909 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26910 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26912 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
26913 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
26914 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
26915 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
26916 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
26917 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
26918 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
26919 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
26921 /* AVX2 */
26922 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
26923 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
26924 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
26925 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
26926 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
26927 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
26928 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
26929 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
26930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
26932 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26933 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26934 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
26935 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
26936 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
26937 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
26939 /* FSGSBASE */
26940 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26941 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26942 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26943 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26944 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26945 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26946 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26947 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26949 /* RTM */
26950 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26951 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
26952 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
26953 };
26955 /* Builtins with variable number of arguments. */
26957 {
26958 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
26959 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
26960 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
26961 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26962 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26963 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26964 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26966 /* MMX */
26967 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26968 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26969 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26970 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26971 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26972 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26974 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26975 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26976 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26977 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26978 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26979 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26980 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26981 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26983 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26984 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26986 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26987 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26988 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26989 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26991 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26992 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26993 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26995 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26996 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26999 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27000 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27016 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27020 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27022 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27023 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27025 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27026 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27027 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27028 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27030 /* 3DNow! */
27031 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27032 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27033 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27034 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27036 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27037 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27038 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27039 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27040 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27041 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27042 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27043 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27044 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27045 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27046 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27047 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27048 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27049 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27050 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27052 /* 3DNow!A */
27053 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27054 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27055 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27056 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27057 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27058 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27060 /* SSE */
27061 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27062 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27063 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27064 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27065 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27066 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27067 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27068 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27069 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27070 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27071 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27072 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27074 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27076 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27077 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27078 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27079 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27080 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27081 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27082 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27083 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27086 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27087 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27088 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27089 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27090 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27091 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27092 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27093 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27094 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27095 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27096 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27097 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27098 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27099 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27100 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27101 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27102 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27103 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27104 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27105 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27106 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27108 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27109 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27110 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27111 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27113 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27114 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27115 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27116 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27118 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27120 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27121 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27123 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27124 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27126 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27127 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27128 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27130 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27132 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27133 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27134 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27136 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27137 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27139 /* SSE MMX or 3Dnow!A */
27140 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27141 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27142 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27144 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27145 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27146 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27147 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27149 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27150 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27152 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27154 /* SSE2 */
27155 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27157 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27160 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27161 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27163 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27164 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27167 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27169 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27171 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27172 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27173 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27174 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27176 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27178 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27180 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27181 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27182 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27183 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27191 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27199 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27201 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27206 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27208 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27211 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27215 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27217 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27218 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27220 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27223 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27224 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27226 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27228 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27229 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27230 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27231 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27232 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27233 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27234 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27235 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27238 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27243 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27244 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27246 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27247 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27249 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27250 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27251 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27252 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27254 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27255 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27257 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27264 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27265 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27266 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27269 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27270 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27271 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27272 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27273 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27274 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27275 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27276 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27282 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27283 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27285 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27286 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27291 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27292 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27296 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27297 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27298 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27299 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27300 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27301 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27304 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27305 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27306 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27307 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27308 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27309 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27311 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27312 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27313 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27314 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27322 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27324 /* SSE2 MMX */
27325 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27326 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27328 /* SSE3 */
27329 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27330 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27332 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27333 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27334 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27335 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27336 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27337 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27339 /* SSSE3 */
27340 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27341 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27342 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27343 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27344 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27345 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27347 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27348 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27349 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27350 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27351 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27352 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27353 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27354 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27355 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27356 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27357 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27358 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27359 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27360 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27361 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27362 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27363 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27364 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27365 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27366 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27367 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27368 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27369 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27370 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27372 /* SSSE3. */
27373 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27374 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27376 /* SSE4.1 */
27377 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27378 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27379 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27380 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27381 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27382 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27383 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27384 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27385 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27386 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27388 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27389 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27390 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27391 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27392 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27393 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27394 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27395 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27396 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27397 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27398 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27399 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27400 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27402 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27403 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27404 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27405 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27406 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27407 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27408 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27409 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27410 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27411 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27412 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27413 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27415 /* SSE4.1 */
27416 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27417 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27418 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27419 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27421 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27422 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27423 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27424 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27426 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27427 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27429 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27430 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27432 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27433 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27434 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27435 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27437 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27438 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27440 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27441 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27443 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27444 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27445 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27447 /* SSE4.2 */
27448 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27449 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27450 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27451 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27452 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27454 /* SSE4A */
27455 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27456 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27457 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27458 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27460 /* AES */
27461 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27462 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27464 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27465 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27466 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27467 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27469 /* PCLMUL */
27470 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27472 /* AVX */
27473 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27474 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27475 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27476 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27477 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27478 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27479 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27480 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27481 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27482 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27483 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27484 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27485 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27486 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27487 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27488 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27489 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27490 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27491 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27492 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27493 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27494 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27495 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27496 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27497 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27498 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27500 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
27501 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
27502 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
27503 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27505 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27506 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27507 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
27508 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
27509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27510 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27511 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27512 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27514 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27515 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27516 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27517 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
27519 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
27520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
27521 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
27522 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
27523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
27524 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27525 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
27526 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27527 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27528 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27530 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27531 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27533 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27534 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
27537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
27538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
27540 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27541 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27544 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27546 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27548 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
27556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
27557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
27558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
27560 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27561 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
27567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
27568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
27569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
27571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
27572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
27574 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27575 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27585 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
27586 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
27587 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
27589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27603 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
27606 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
27608 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27609 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27611 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27613 /* AVX2 */
27614 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
27615 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
27616 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
27617 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
27618 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27619 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27620 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27621 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27622 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27623 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27624 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27625 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27626 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27627 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27628 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27629 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27630 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
27631 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27632 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27633 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27634 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27635 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
27636 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
27637 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27638 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27639 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27640 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27641 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27642 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27643 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27644 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27645 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27646 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27647 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27648 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27649 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27650 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27651 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27652 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
27653 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27654 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27655 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27656 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27657 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27658 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27659 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27660 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27661 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27662 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27663 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27664 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
27666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27673 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27674 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27675 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27676 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27677 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27678 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27679 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27680 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27681 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27682 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27683 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27684 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27685 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27686 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27687 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27688 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
27689 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27690 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27691 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27692 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27693 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27694 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27695 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27696 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27697 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27698 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27699 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27700 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27701 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27702 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27703 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27704 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27705 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27706 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27707 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27708 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27709 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27710 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27711 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27712 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27713 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27714 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27715 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27716 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27717 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27718 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27719 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27720 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27721 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27722 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27723 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27724 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27725 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27726 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27727 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27728 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27729 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27730 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27731 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27732 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27733 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
27734 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27735 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
27736 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
27737 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27738 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27739 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27740 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27741 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27742 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27744 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27746 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
27747 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
27748 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
27749 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
27750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27761 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27763 /* BMI */
27764 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27765 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27766 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27768 /* TBM */
27769 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27770 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27772 /* F16C */
27773 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
27774 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
27775 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
27776 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
27778 /* BMI2 */
27779 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27780 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27781 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27782 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27783 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27784 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27785 };
27787 /* FMA4 and XOP. */
27788 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
27789 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
27790 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
27791 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
27792 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
27793 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
27794 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
27795 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
27796 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
27797 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
27798 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
27799 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
27800 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
27801 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
27802 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
27803 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
27804 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
27805 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
27806 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
27807 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
27808 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
27809 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
27810 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
27811 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
27812 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
27813 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
27814 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
27815 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
27816 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
27817 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
27818 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
27819 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
27820 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
27821 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
27822 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
27823 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
27824 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
27825 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
27826 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
27827 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
27828 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
27829 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
27830 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
27831 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
27832 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
27833 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
27834 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
27835 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
27836 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
27837 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
27838 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
27839 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
27842 {
27883 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
27884 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
27885 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
27886 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
27887 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
27888 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
27889 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
27891 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27892 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27893 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
27894 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
27895 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
27896 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
27897 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
27899 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
27901 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27902 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27903 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27904 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27905 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27906 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27907 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27908 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27909 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27910 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27911 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27912 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27914 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27915 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
27916 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
27917 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
27918 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
27919 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
27920 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
27921 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
27922 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27923 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
27924 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
27925 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
27926 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27927 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
27928 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
27929 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
27931 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
27932 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
27933 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
27934 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
27935 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
27936 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
27938 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27939 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27940 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27941 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27942 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27943 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27944 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27945 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27946 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27947 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27948 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27949 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27950 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27951 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27952 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
27955 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27957 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
27958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
27959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
27960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
27962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
27963 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
27966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
27967 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
27968 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
27970 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
27971 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27972 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27973 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
27974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
27975 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
27976 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
27978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
27979 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27980 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27981 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
27982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
27983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
27984 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
27986 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
27987 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
27988 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
27989 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
27990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
27991 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
27992 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
27994 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
27995 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
27996 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
27997 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
27998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
27999 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28000 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28002 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28003 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28004 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28005 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28007 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28008 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28010 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28011 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28012 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28013 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28015 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28016 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28019 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28020 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28024 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28028 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28032 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28034 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28041 };
28042 \f
28043 /* TM vector builtins. */
28045 /* Reuse the existing x86-specific `struct builtin_description' cause
28046 we're lazy. Add casts to make them fit. */
28048 {
28049 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28050 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28051 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28052 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28053 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28054 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28055 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28057 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28058 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28059 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28060 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28061 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28062 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28063 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28065 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28066 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28067 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28068 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28069 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28070 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28071 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28073 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28074 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28075 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28076 };
28078 /* TM callbacks. */
28080 /* Return the builtin decl needed to load a vector of TYPE. */
28082 static tree
28084 {
28086 {
28088 {
28095 }
28096 }
28098 }
28100 /* Return the builtin decl needed to store a vector of TYPE. */
28102 static tree
28104 {
28106 {
28108 {
28115 }
28116 }
28118 }
28119 \f
28120 /* Initialize the transactional memory vector load/store builtins. */
28122 static void
28124 {
28128 tree decl;
28135 /* If there are no builtins defined, we must be compiling in a
28136 language without trans-mem support. */
28140 /* Use whatever attributes a normal TM load has. */
28144 /* Use whatever attributes a normal TM store has. */
28148 /* Use whatever attributes a normal TM log has. */
28156 {
28160 {
28168 {
28171 }
28173 {
28176 }
28177 else
28178 {
28181 }
28183 /* The builtin without the prefix for
28184 calling it directly. */
28186 attrs);
28187 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28188 set the TYPE_ATTRIBUTES. */
28192 }
28193 }
28194 }
28196 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28197 in the current target ISA to allow the user to compile particular modules
28198 with different target specific options that differ from the command line
28199 options. */
28200 static void
28202 {
28207 /* Add all special builtins with variable number of operands. */
28211 {
28217 }
28219 /* Add all builtins with variable number of operands. */
28223 {
28229 }
28231 /* pcmpestr[im] insns. */
28235 {
28238 else
28241 }
28243 /* pcmpistr[im] insns. */
28247 {
28250 else
28253 }
28255 /* comi/ucomi insns. */
28257 {
28260 else
28263 }
28265 /* SSE */
28271 /* SSE or 3DNow!A */
28274 IX86_BUILTIN_MASKMOVQ);
28276 /* SSE2 */
28285 /* SSE3. */
28291 /* AES */
28305 /* PCLMUL */
28309 /* RDRND */
28316 IX86_BUILTIN_RDRAND64_STEP);
28318 /* AVX2 */
28320 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28321 IX86_BUILTIN_GATHERSIV2DF);
28324 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28325 IX86_BUILTIN_GATHERSIV4DF);
28328 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28329 IX86_BUILTIN_GATHERDIV2DF);
28332 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28333 IX86_BUILTIN_GATHERDIV4DF);
28336 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28337 IX86_BUILTIN_GATHERSIV4SF);
28340 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28341 IX86_BUILTIN_GATHERSIV8SF);
28344 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28345 IX86_BUILTIN_GATHERDIV4SF);
28348 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28349 IX86_BUILTIN_GATHERDIV8SF);
28352 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28353 IX86_BUILTIN_GATHERSIV2DI);
28356 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28357 IX86_BUILTIN_GATHERSIV4DI);
28360 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28361 IX86_BUILTIN_GATHERDIV2DI);
28364 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28365 IX86_BUILTIN_GATHERDIV4DI);
28368 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28369 IX86_BUILTIN_GATHERSIV4SI);
28372 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28373 IX86_BUILTIN_GATHERSIV8SI);
28376 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28377 IX86_BUILTIN_GATHERDIV4SI);
28380 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28381 IX86_BUILTIN_GATHERDIV8SI);
28384 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28385 IX86_BUILTIN_GATHERALTSIV4DF);
28388 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28389 IX86_BUILTIN_GATHERALTDIV8SF);
28392 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28393 IX86_BUILTIN_GATHERALTSIV4DI);
28396 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28397 IX86_BUILTIN_GATHERALTDIV8SI);
28399 /* RTM. */
28403 /* MMX access to the vec_init patterns. */
28408 V4HI_FTYPE_HI_HI_HI_HI,
28409 IX86_BUILTIN_VEC_INIT_V4HI);
28412 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28413 IX86_BUILTIN_VEC_INIT_V8QI);
28415 /* Access to the vec_extract patterns. */
28437 /* Access to the vec_set patterns. */
28458 /* RDSEED */
28467 /* ADCX */
28472 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28473 IX86_BUILTIN_ADDCARRYX64);
28475 /* Add FMA4 multi-arg argument instructions */
28477 {
28483 }
28484 }
28486 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
28487 to return a pointer to VERSION_DECL if the outcome of the expression
28488 formed by PREDICATE_CHAIN is true. This function will be called during
28489 version dispatch to decide which function version to execute. It returns
28490 the basic block at the end, to which more conditions can be added. */
28492 static basic_block
28495 {
28496 gimple return_stmt;
28498 gimple convert_stmt;
28499 gimple call_cond_stmt;
28500 gimple if_else_stmt;
28506 gimple_seq gseq;
28523 {
28531 }
28534 {
28549 else
28550 {
28551 gimple assign_stmt;
28552 /* Use MIN_EXPR to check if any integer is zero?.
28553 and_expr_var = min_expr <cond_var, and_expr_var> */
28561 }
28562 }
28565 integer_zero_node,
28595 }
28597 /* This parses the attribute arguments to target in DECL and determines
28598 the right builtin to use to match the platform specification.
28599 It returns the priority value for this version decl. If PREDICATE_LIST
28600 is not NULL, it stores the list of cpu features that need to be checked
28601 before dispatching this function. */
28603 static unsigned int
28605 {
28606 tree attrs;
28608 tree target_node;
28615 /* Priority of i386 features, greater value is higher priority. This is
28616 used to decide the order in which function dispatch must happen. For
28617 instance, a version specialized for SSE4.2 should be checked for dispatch
28618 before a version for SSE3, as SSE4.2 implies SSE3. */
28619 enum feature_priority
28620 {
28622 P_MMX,
28623 P_SSE,
28624 P_SSE2,
28625 P_SSE3,
28626 P_SSSE3,
28627 P_PROC_SSSE3,
28628 P_SSE4_a,
28629 P_PROC_SSE4_a,
28630 P_SSE4_1,
28631 P_SSE4_2,
28632 P_PROC_SSE4_2,
28633 P_POPCNT,
28634 P_AVX,
28635 P_AVX2,
28636 P_FMA,
28637 P_PROC_FMA
28638 };
28642 /* These are the target attribute strings for which a dispatcher is
28643 available, from fold_builtin_cpu. */
28645 static struct _feature_list
28646 {
28649 }
28651 {
28662 };
28665 static unsigned int NUM_FEATURES
28682 /* Handle arch= if specified. For priority, set it to be 1 more than
28683 the best instruction set the processor can handle. For instance, if
28684 there is a version for atom and a version for ssse3 (the highest ISA
28685 priority for atom), the atom version must be checked for dispatch
28686 before the ssse3 version. */
28688 {
28697 {
28699 {
28724 }
28725 }
28730 {
28734 }
28737 {
28739 /* For a C string literal the length includes the trailing NULL. */
28742 predicate_chain);
28743 }
28744 }
28746 /* Process feature name. */
28753 {
28754 /* Do not process "arch=" */
28756 {
28759 }
28761 {
28763 {
28765 {
28770 predicate_chain);
28771 }
28772 /* Find the maximum priority feature. */
28777 }
28778 }
28780 {
28784 }
28786 }
28790 {
28793 attrs_str);
28795 }
28797 {
28800 }
28803 }
28805 /* This compares the priority of target features in function DECL1
28806 and DECL2. It returns positive value if DECL1 is higher priority,
28807 negative value if DECL2 is higher priority and 0 if they are the
28808 same. */
28810 static int
28812 {
28823 }
28825 /* V1 and V2 point to function versions with different priorities
28826 based on the target ISA. This function compares their priorities. */
28828 static int
28830 {
28832 {
28833 tree version_decl;
28834 tree predicate_chain;
28841 }
28843 /* This function generates the dispatch function for
28844 multi-versioned functions. DISPATCH_DECL is the function which will
28845 contain the dispatch logic. FNDECLS are the function choices for
28846 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
28847 in DISPATCH_DECL in which the dispatch code is generated. */
28849 static int
28853 {
28854 tree default_decl;
28855 gimple ifunc_cpu_init_stmt;
28856 gimple_seq gseq;
28858 tree ele;
28864 struct _function_version_info
28865 {
28866 tree version_decl;
28867 tree predicate_chain;
28875 /*fndecls_p is actually a vector. */
28878 /* At least one more version other than the default. */
28885 /* The first version in the vector is the default decl. */
28891 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
28892 constructors, so explicity call __builtin_cpu_init here. */
28903 {
28907 /* Get attribute string, parse it and find the right predicate decl.
28908 The predicate function could be a lengthy combination of many
28909 features, like arch-type and various isa-variants. */
28916 actual_versions++;
28920 }
28922 /* Sort the versions according to descending order of dispatch priority. The
28923 priority is based on the ISA. This is not a perfect solution. There
28924 could still be ambiguity. If more than one function version is suitable
28925 to execute, which one should be dispatched? In future, allow the user
28926 to specify a dispatch priority next to the version. */
28936 /* dispatch default version at the end. */
28942 }
28944 /* This function returns true if FN1 and FN2 are versions of the same function,
28945 that is, the targets of the function decls are different. This assumes
28946 that FN1 and FN2 have the same signature. */
28948 static bool
28950 {
28961 /* Atleast one function decl should have target attribute specified. */
28973 /* target1 and target2 must be different in some way. */
28983 }
28985 /* Comparator function to be used in qsort routine to sort attribute
28986 specification strings to "target". */
28988 static int
28990 {
28994 }
28996 /* STR is the argument to target attribute. This function tokenizes
28997 the comma separated arguments, sorts them and returns a string which
28998 is a unique identifier for the comma separated arguments. It also
28999 replaces non-identifier characters "=,-" with "_". */
29003 {
29012 argnum++;
29017 /* Replace "=,-" with "_". */
29030 {
29032 i++;
29034 }
29041 {
29044 }
29049 }
29051 /* This function changes the assembler name for functions that are
29052 versions. If DECL is a function version and has a "target"
29053 attribute, it appends the attribute string to its assembler name. */
29055 static tree
29057 {
29058 tree version_attr;
29066 "Function versions cannot be marked as gnu_inline,"
29076 /* target attribute string is NULL for default functions. */
29081 version_string
29090 /* Allow assembler name to be modified if already set. */
29095 }
29097 static tree
29099 {
29100 /* For function version, add the target suffix to the assembler name. */
29104 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29106 #endif
29109 }
29111 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29112 is true, append the full path name of the source file. */
29116 {
29124 /* Get a unique name that can be used globally without any chances
29125 of collision at link time. */
29135 /* Use '.' to concatenate names as it is demangler friendly. */
29139 else
29143 }
29145 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29147 /* Make a dispatcher declaration for the multi-versioned function DECL.
29148 Calls to DECL function will be replaced with calls to the dispatcher
29149 by the front-end. Return the decl created. */
29151 static tree
29153 {
29154 tree func_decl;
29175 /* Mark this func as external, the resolver will flip it again if
29176 it gets generated. */
29178 /* This will be of type IFUNCs have to be externally visible. */
29182 }
29184 #endif
29186 /* Returns true if decl is multi-versioned and DECL is the default function,
29187 that is it is not tagged with target specific optimization. */
29189 static bool
29191 {
29195 }
29197 /* Make a dispatcher declaration for the multi-versioned function DECL.
29198 Calls to DECL function will be replaced with calls to the dispatcher
29199 by the front-end. Returns the decl of the dispatcher function. */
29201 static tree
29203 {
29212 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29216 #endif
29231 /* Find the default version and make it the first node. */
29233 /* Go to the beginnig of the chain. */
29238 {
29243 }
29245 /* If there is no default node, just return NULL. */
29249 /* Make default info the first node. */
29251 {
29258 }
29262 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29263 /* Right now, the dispatching is done via ifunc. */
29269 dispatcher_version_info
29274 /* Set the dispatcher for all the versions. */
29277 {
29280 }
29281 #else
29283 "multiversioning needs ifunc which is not supported "
29285 #endif
29287 }
29289 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29290 it to CHAIN. */
29292 static tree
29294 {
29295 tree attr_name;
29296 tree attr_arg_name;
29297 tree attr_args;
29298 tree attr;
29305 }
29307 /* Make the resolver function decl to dispatch the versions of
29308 a multi-versioned function, DEFAULT_DECL. Create an
29309 empty basic block in the resolver and store the pointer in
29310 EMPTY_BB. Return the decl of the resolver function. */
29312 static tree
29316 {
29321 /* IFUNC's have to be globally visible. So, if the default_decl is
29322 not, then the name of the IFUNC should be made unique. */
29326 /* Append the filename to the resolver function if the versions are
29327 not externally visible. This is because the resolver function has
29328 to be externally visible for the loader to find it. So, appending
29329 the filename will prevent conflicts with a resolver function from
29330 another module which is based on the same version name. */
29333 /* The resolver function should return a (void *). */
29344 /* IFUNC resolvers have to be externally visible. */
29348 /* Resolver is not external, body is generated. */
29358 {
29359 /* In this case, each translation unit with a call to this
29360 versioned function will put out a resolver. Ensure it
29361 is comdat to keep just one copy. */
29364 }
29365 /* Build result decl and add to function_decl. */
29381 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29385 /* Create the alias for dispatch to resolver here. */
29386 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29389 }
29391 /* Generate the dispatching code body to dispatch multi-versioned function
29392 DECL. The target hook is called to process the "target" attributes and
29393 provide the code to dispatch the right function at run-time. NODE points
29394 to the dispatcher decl whose body will be created. */
29396 static tree
29398 {
29399 tree resolver_decl;
29400 basic_block empty_bb;
29402 tree default_ver_decl;
29418 /* The first version in the chain corresponds to the default version. */
29421 /* node is going to be an alias, so remove the finalized bit. */
29435 {
29437 /* Check for virtual functions here again, as by this time it should
29438 have been determined if this function needs a vtable index or
29439 not. This happens for methods in derived classes that override
29440 virtual methods in base classes but are not explicitly marked as
29441 virtual. */
29446 }
29453 }
29454 /* This builds the processor_model struct type defined in
29455 libgcc/config/i386/cpuinfo.c */
29457 static tree
29459 {
29466 /* The first 3 fields are unsigned int. */
29468 {
29474 }
29476 /* The last field is an array of unsigned integers of size one. */
29487 }
29489 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
29491 static tree
29493 {
29494 tree new_decl;
29497 VAR_DECL,
29499 type);
29512 }
29514 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
29515 into an integer defined in libgcc/config/i386/cpuinfo.c */
29517 static tree
29519 {
29525 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
29526 enum processor_features
29527 {
29529 F_MMX,
29530 F_POPCNT,
29531 F_SSE,
29532 F_SSE2,
29533 F_SSE3,
29534 F_SSSE3,
29535 F_SSE4_1,
29536 F_SSE4_2,
29537 F_AVX,
29538 F_AVX2,
29539 F_MAX
29540 };
29542 /* These are the values for vendor types and cpu types and subtypes
29543 in cpuinfo.c. Cpu types and subtypes should be subtracted by
29544 the corresponding start value. */
29545 enum processor_model
29546 {
29548 M_AMD,
29549 M_CPU_TYPE_START,
29550 M_INTEL_ATOM,
29551 M_INTEL_CORE2,
29552 M_INTEL_COREI7,
29553 M_AMDFAM10H,
29554 M_AMDFAM15H,
29555 M_CPU_SUBTYPE_START,
29556 M_INTEL_COREI7_NEHALEM,
29557 M_INTEL_COREI7_WESTMERE,
29558 M_INTEL_COREI7_SANDYBRIDGE,
29559 M_AMDFAM10H_BARCELONA,
29560 M_AMDFAM10H_SHANGHAI,
29561 M_AMDFAM10H_ISTANBUL,
29562 M_AMDFAM15H_BDVER1,
29563 M_AMDFAM15H_BDVER2,
29564 M_AMDFAM15H_BDVER3
29565 };
29567 static struct _arch_names_table
29568 {
29571 }
29573 {
29590 };
29592 static struct _isa_names_table
29593 {
29596 }
29598 {
29610 };
29627 {
29628 /* *args must be a expr that can contain other EXPRS leading to a
29629 STRING_CST. */
29631 {
29634 }
29636 }
29641 {
29642 tree ref;
29643 tree field;
29644 tree final;
29647 unsigned int NUM_ARCH_NAMES
29656 {
29660 }
29665 /* CPU types are stored in the next field. */
29668 {
29671 }
29673 /* CPU subtypes are stored in the next field. */
29675 {
29678 }
29680 /* Get the appropriate field in __cpu_model. */
29684 /* Check the value. */
29688 }
29690 {
29691 tree ref;
29692 tree array_elt;
29693 tree field;
29694 tree final;
29697 unsigned int NUM_ISA_NAMES
29706 {
29710 }
29713 /* Get the last field, which is __cpu_features. */
29717 /* Get the appropriate field: __cpu_model.__cpu_features */
29721 /* Access the 0th element of __cpu_features array. */
29726 /* Return __cpu_model.__cpu_features[0] & field_val */
29730 }
29732 }
29734 static tree
29737 {
29739 {
29744 {
29747 }
29748 }
29750 #ifdef SUBTARGET_FOLD_BUILTIN
29752 #endif
29755 }
29757 /* Make builtins to detect cpu type and features supported. NAME is
29758 the builtin name, CODE is the builtin code, and FTYPE is the function
29759 type of the builtin. */
29761 static void
29764 {
29765 tree decl;
29766 tree type;
29774 }
29776 /* Make builtins to get CPU type and features supported. The created
29777 builtins are :
29779 __builtin_cpu_init (), to detect cpu type and features,
29780 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
29781 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
29782 */
29784 static void
29786 {
29793 }
29795 /* Internal method for ix86_init_builtins. */
29797 static void
29799 {
29811 sysv_va_ref =
29814 fnvoid_va_end_ms =
29816 fnvoid_va_start_ms =
29818 fnvoid_va_end_sysv =
29820 fnvoid_va_start_sysv =
29822 NULL_TREE);
29823 fnvoid_va_copy_ms =
29825 NULL_TREE);
29826 fnvoid_va_copy_sysv =
29842 }
29844 static void
29846 {
29849 /* The __float80 type. */
29852 {
29853 /* The __float80 type. */
29858 }
29861 /* The __float128 type. */
29867 /* This macro is built by i386-builtin-types.awk. */
29868 DEFINE_BUILTIN_PRIMITIVE_TYPES;
29869 }
29871 static void
29873 {
29874 tree t;
29878 /* Builtins to get CPU type and features. */
29881 /* TFmode support builtins. */
29887 /* We will expand them to normal call if SSE isn't available since
29888 they are used by libgcc. */
29907 #ifdef SUBTARGET_INIT_BUILTINS
29908 SUBTARGET_INIT_BUILTINS;
29909 #endif
29910 }
29912 /* Return the ix86 builtin for CODE. */
29914 static tree
29916 {
29921 }
29923 /* Errors in the source file can cause expand_expr to return const0_rtx
29924 where we expect a vector. To avoid crashing, use one of the vector
29925 clear instructions. */
29926 static rtx
29928 {
29932 }
29934 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
29936 static rtx
29938 {
29939 rtx pat;
29959 {
29963 }
29977 }
29979 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
29981 static rtx
29985 {
29986 rtx pat;
29994 rtx op;
30001 {
30081 }
30091 {
30098 {
30100 {
30103 {
30121 xop_rotl:
30123 {
30126 gcc_checking_assert
30128 }
30129 else
30130 {
30131 gcc_checking_assert
30142 }
30146 }
30147 }
30148 }
30149 else
30150 {
30151 non_constant:
30155 /* If we aren't optimizing, only allow one memory operand to be
30156 generated. */
30158 num_memory++;
30166 }
30170 }
30173 {
30184 else
30185 {
30191 }
30204 }
30211 }
30213 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30214 insns with vec_merge. */
30216 static rtx
30218 rtx target)
30219 {
30220 rtx pat;
30247 }
30249 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30251 static rtx
30254 {
30255 rtx pat;
30260 rtx op2;
30271 /* Swap operands if we have a comparison that isn't available in
30272 hardware. */
30274 {
30279 }
30299 }
30301 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30303 static rtx
30305 rtx target)
30306 {
30307 rtx pat;
30321 /* Swap operands if we have a comparison that isn't available in
30322 hardware. */
30324 {
30328 }
30349 const0_rtx)));
30352 }
30354 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30356 static rtx
30358 rtx target)
30359 {
30360 rtx pat;
30385 }
30387 static rtx
30390 {
30391 rtx pat;
30396 rtx op2;
30423 }
30425 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
30427 static rtx
30429 rtx target)
30430 {
30431 rtx pat;
30464 const0_rtx)));
30467 }
30469 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
30471 static rtx
30474 {
30475 rtx pat;
30513 {
30516 }
30519 {
30528 }
30530 {
30539 }
30540 else
30541 {
30548 }
30556 {
30561 emit_insn
30565 FLAGS_REG),
30566 const0_rtx)));
30568 }
30569 else
30571 }
30574 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
30576 static rtx
30579 {
30580 rtx pat;
30608 {
30611 }
30614 {
30623 }
30625 {
30634 }
30635 else
30636 {
30643 }
30651 {
30656 emit_insn
30660 FLAGS_REG),
30661 const0_rtx)));
30663 }
30664 else
30666 }
30668 /* Subroutine of ix86_expand_builtin to take care of insns with
30669 variable number of operands. */
30671 static rtx
30674 {
30679 struct
30680 {
30681 rtx op;
30693 {
30972 }
30977 {
30980 }
30983 {
30990 }
30991 else
30992 {
30995 }
30998 {
31005 {
31006 /* SIMD shift insns take either an 8-bit immediate or
31007 register as count. But builtin functions take int as
31008 count. If count doesn't match, we put it in register. */
31010 {
31014 }
31015 }
31017 {
31020 {
31074 {
31077 {
31080 }
31086 }
31088 }
31089 }
31090 else
31091 {
31095 /* If we aren't optimizing, only allow one memory operand to
31096 be generated. */
31098 num_memory++;
31101 {
31104 }
31105 else
31106 {
31109 }
31110 }
31114 }
31117 {
31134 }
31141 }
31143 /* Subroutine of ix86_expand_builtin to take care of special insns
31144 with variable number of operands. */
31146 static rtx
31149 {
31150 tree arg;
31153 struct
31154 {
31155 rtx op;
31165 {
31213 /* Reserve memory operand for target. */
31244 /* Reserve memory operand for target. */
31258 }
31263 {
31268 {
31272 }
31273 else
31276 }
31277 else
31278 {
31285 }
31288 {
31297 {
31299 {
31305 else
31308 }
31309 }
31310 else
31311 {
31313 {
31314 /* This must be the memory operand. */
31320 }
31321 else
31322 {
31323 /* This must be register. */
31330 }
31331 }
31335 }
31338 {
31353 }
31359 }
31361 /* Return the integer constant in ARG. Constrain it to be in the range
31362 of the subparts of VEC_TYPE; issue an error if not. */
31364 static int
31366 {
31371 {
31374 }
31377 }
31379 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31380 ix86_expand_vector_init. We DO have language-level syntax for this, in
31381 the form of (type){ init-list }. Except that since we can't place emms
31382 instructions from inside the compiler, we can't allow the use of MMX
31383 registers unless the user explicitly asks for it. So we do *not* define
31384 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31385 we have builtins invoked by mmintrin.h that gives us license to emit
31386 these sorts of instructions. */
31388 static rtx
31390 {
31400 {
31403 }
31410 }
31412 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31413 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31414 had a language-level syntax for referencing vector elements. */
31416 static rtx
31418 {
31422 rtx op0;
31442 }
31444 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31445 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
31446 a language-level syntax for referencing vector elements. */
31448 static rtx
31450 {
31474 /* OP0 is the source of these builtin functions and shouldn't be
31475 modified. Create a copy, use it and return it as target. */
31481 }
31483 /* Expand an expression EXP that calls a built-in function,
31484 with result going to TARGET if that's convenient
31485 (and in mode MODE if that's convenient).
31486 SUBTARGET may be used as the target for computing one of EXP's operands.
31487 IGNORE is nonzero if the value is to be ignored. */
31489 static rtx
31493 {
31503 /* For CPU builtins that can be folded, fold first and expand the fold. */
31505 {
31507 {
31508 /* Make it call __cpu_indicator_init in libgcc. */
31514 }
31517 {
31522 }
31523 }
31525 /* Determine whether the builtin function is available under the current ISA.
31526 Originally the builtin was not created if it wasn't applicable to the
31527 current ISA based on the command line switches. With function specific
31528 options, we need to check in the context of the function making the call
31529 whether it is supported. */
31532 {
31538 else
31539 {
31543 }
31545 }
31548 {
31552 ? CODE_FOR_mmx_maskmovq
31554 /* Note the arg order is different from the operand order. */
31598 {
31602 }
31615 {
31619 }
31664 {
31665 REAL_VALUE_TYPE inf;
31666 rtx tmp;
31678 }
31688 {
31694 insn = (TARGET_64BIT
31698 }
31700 {
31701 insn = (TARGET_64BIT
31705 }
31706 else
31707 {
31710 insn = (TARGET_64BIT
31718 {
31721 }
31723 }
31729 {
31734 }
31744 {
31759 }
31765 {
31768 }
31788 {
31791 }
31797 {
31801 {
31822 }
31827 }
31828 else
31829 {
31831 {
31843 }
31845 }
31856 {
31860 }
31879 ? CODE_FOR_tbm_bextri_si
31882 {
31885 }
31886 else
31887 {
31896 }
31912 rdrand_step:
31919 {
31922 }
31928 /* Emit SImode conditional move. */
31930 {
31933 }
31936 else
31943 const0_rtx);
31962 rdseed_step:
31969 {
31972 }
31978 const0_rtx);
31996 addcarryx:
32004 /* Generate CF from input operand. */
32011 /* Gen ADCX instruction to compute X+Y+CF. */
32026 /* Store the result. */
32029 {
32032 }
32035 /* Return current CF value. */
32104 gather_gen:
32115 /* Note the arg order is different from the operand order. */
32124 else
32129 {
32135 }
32138 {
32143 else
32153 }
32155 /* Force memory operand only with base register here. But we
32156 don't want to do it on memory operand for other builtin
32157 functions. */
32171 {
32174 }
32176 /* Optimize. If mask is known to have all high bits set,
32177 replace op0 with pc_rtx to signal that the instruction
32178 overwrites the whole destination and doesn't use its
32179 previous contents. */
32181 {
32183 {
32186 {
32190 negative++;
32193 negative++;
32194 }
32197 }
32199 {
32200 /* Recognize also when mask is like:
32201 __v2df src = _mm_setzero_pd ();
32202 __v2df mask = _mm_cmpeq_pd (src, src);
32203 or
32204 __v8sf src = _mm256_setzero_ps ();
32205 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32206 as that is a cheaper way to load all ones into
32207 a register than having to load a constant from
32208 memory. */
32211 {
32216 {
32223 /* FALLTHRU */
32233 }
32234 }
32235 }
32236 }
32245 {
32252 else
32254 }
32255 else
32266 {
32269 }
32275 }
32288 {
32292 /* Emit a normal call if SSE isn't available. */
32296 }
32321 }
32323 /* Returns a function decl for a vectorized version of the builtin function
32324 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32325 if it is not available. */
32327 static tree
32329 tree type_in)
32330 {
32346 {
32349 {
32354 }
32359 {
32364 }
32370 /* The round insn does not trap on denormals. */
32375 {
32380 }
32386 /* The round insn does not trap on denormals. */
32391 {
32396 }
32402 /* The round insn does not trap on denormals. */
32407 {
32412 }
32418 /* The round insn does not trap on denormals. */
32423 {
32428 }
32435 {
32440 }
32447 {
32452 }
32458 /* The round insn does not trap on denormals. */
32463 {
32468 }
32474 /* The round insn does not trap on denormals. */
32479 {
32484 }
32489 {
32494 }
32499 {
32504 }
32508 /* The round insn does not trap on denormals. */
32513 {
32518 }
32522 /* The round insn does not trap on denormals. */
32527 {
32532 }
32536 /* The round insn does not trap on denormals. */
32541 {
32546 }
32550 /* The round insn does not trap on denormals. */
32555 {
32560 }
32564 /* The round insn does not trap on denormals. */
32569 {
32574 }
32578 /* The round insn does not trap on denormals. */
32583 {
32588 }
32592 /* The round insn does not trap on denormals. */
32597 {
32602 }
32606 /* The round insn does not trap on denormals. */
32611 {
32616 }
32620 /* The round insn does not trap on denormals. */
32625 {
32630 }
32634 /* The round insn does not trap on denormals. */
32639 {
32644 }
32649 {
32654 }
32659 {
32664 }
32669 }
32671 /* Dispatch to a handler for a vectorization library. */
32674 type_in);
32677 }
32679 /* Handler for an SVML-style interface to
32680 a library with vectorized intrinsics. */
32682 static tree
32684 {
32692 /* The SVML is suitable for unsafe math only. */
32705 {
32752 }
32761 {
32764 }
32765 else
32768 /* Convert to uppercase. */
32773 args;
32775 arity++;
32779 else
32782 /* Build a function declaration for the vectorized function. */
32791 }
32793 /* Handler for an ACML-style interface to
32794 a library with vectorized intrinsics. */
32796 static tree
32798 {
32806 /* The ACML is 64bits only and suitable for unsafe math only as
32807 it does not correctly support parts of IEEE with the required
32808 precision such as denormals. */
32822 {
32852 }
32859 args;
32861 arity++;
32865 else
32868 /* Build a function declaration for the vectorized function. */
32877 }
32879 /* Returns a decl of a function that implements gather load with
32880 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
32881 Return NULL_TREE if it is not available. */
32883 static tree
32886 {
32902 /* v*gather* insn sign extends index to pointer mode. */
32914 {
32941 }
32944 }
32946 /* Returns a code for a target-specific builtin that implements
32947 reciprocal of the function, or NULL_TREE if not available. */
32949 static tree
32952 {
32959 /* Machine dependent builtins. */
32961 {
32962 /* Vectorized version of sqrt to rsqrt conversion. */
32971 }
32972 else
32973 /* Normal builtins. */
32975 {
32976 /* Sqrt to rsqrt conversion. */
32982 }
32983 }
32984 \f
32985 /* Helper for avx_vpermilps256_operand et al. This is also used by
32986 the expansion functions to turn the parallel back into a mask.
32987 The return value is 0 for no match and the imm8+1 for a match. */
32989 int
32991 {
32999 /* Validate that all of the elements are constants, and not totally
33000 out of range. Copy the data into an integral array to make the
33001 subsequent checks easier. */
33003 {
33013 }
33016 {
33018 /* In the 256-bit DFmode case, we can only move elements within
33019 a 128-bit lane. */
33021 {
33025 }
33027 {
33031 }
33035 /* In the 256-bit SFmode case, we have full freedom of movement
33036 within the low 128-bit lane, but the high 128-bit lane must
33037 mirror the exact same pattern. */
33042 /* FALLTHRU */
33046 /* In the 128-bit case, we've full freedom in the placement of
33047 the elements from the source operand. */
33054 }
33056 /* Make sure success has a non-zero value by adding one. */
33058 }
33060 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33061 the expansion functions to turn the parallel back into a mask.
33062 The return value is 0 for no match and the imm8+1 for a match. */
33064 int
33066 {
33074 /* Validate that all of the elements are constants, and not totally
33075 out of range. Copy the data into an integral array to make the
33076 subsequent checks easier. */
33078 {
33088 }
33090 /* Validate that the halves of the permute are halves. */
33098 /* Reconstruct the mask. */
33100 {
33106 }
33108 /* Make sure success has a non-zero value by adding one. */
33110 }
33111 \f
33112 /* Store OPERAND to the memory after reload is completed. This means
33113 that we can't easily use assign_stack_local. */
33114 rtx
33116 {
33117 rtx result;
33121 {
33124 stack_pointer_rtx,
33127 }
33129 {
33131 {
33135 /* FALLTHRU */
33141 stack_pointer_rtx)),
33142 operand));
33146 }
33148 }
33149 else
33150 {
33152 {
33154 {
33161 stack_pointer_rtx)),
33167 stack_pointer_rtx)),
33169 }
33172 /* Store HImodes as SImodes. */
33174 /* FALLTHRU */
33180 stack_pointer_rtx)),
33181 operand));
33185 }
33187 }
33189 }
33191 /* Free operand from the memory. */
33192 void
33194 {
33196 {
33201 else
33203 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33204 to pop or add instruction if registers are available. */
33208 }
33209 }
33211 /* Return a register priority for hard reg REGNO. */
33212 static int
33214 {
33215 /* ebp and r13 as the base always wants a displacement, r12 as the
33216 base always wants an index. So discourage their usage in an
33217 address. */
33222 /* New x86-64 int registers result in bigger code size. Discourage
33223 them. */
33226 /* New x86-64 SSE registers result in bigger code size. Discourage
33227 them. */
33230 /* Usage of AX register results in smaller code. Prefer it. */
33234 }
33236 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33238 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33239 QImode must go into class Q_REGS.
33240 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33241 movdf to do mem-to-mem moves through integer regs. */
33243 static reg_class_t
33245 {
33248 /* We're only allowed to return a subclass of CLASS. Many of the
33249 following checks fail for NO_REGS, so eliminate that early. */
33253 /* All classes can load zeros. */
33257 /* Force constants into memory if we are loading a (nonzero) constant into
33258 an MMX or SSE register. This is because there are no MMX/SSE instructions
33259 to load from a constant. */
33264 /* Prefer SSE regs only, if we can use them for math. */
33268 /* Floating-point constants need more complex checks. */
33270 {
33271 /* General regs can load everything. */
33275 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33276 zero above. We only want to wind up preferring 80387 registers if
33277 we plan on doing computation with them. */
33280 {
33281 /* Limit class to non-sse. */
33290 }
33293 }
33295 /* Generally when we see PLUS here, it's the function invariant
33296 (plus soft-fp const_int). Which can only be computed into general
33297 regs. */
33301 /* QImode constants are easy to load, but non-constant QImode data
33302 must go into Q_REGS. */
33304 {
33310 }
33313 }
33315 /* Discourage putting floating-point values in SSE registers unless
33316 SSE math is being used, and likewise for the 387 registers. */
33317 static reg_class_t
33319 {
33322 /* Restrict the output reload class to the register bank that we are doing
33323 math on. If we would like not to return a subset of CLASS, reject this
33324 alternative: if reload cannot do this, it will still use its choice. */
33330 {
33335 else
33337 }
33340 }
33342 static reg_class_t
33345 {
33346 /* Double-word spills from general registers to non-offsettable memory
33347 references (zero-extended addresses) require special handling. */
33353 {
33355 ? CODE_FOR_reload_noff_load
33357 /* Add the cost of moving address to a temporary. */
33361 }
33363 /* QImode spills from non-QI registers require
33364 intermediate register on 32bit targets. */
33373 {
33378 else
33384 /* Return Q_REGS if the operand is in memory. */
33387 }
33389 /* This condition handles corner case where an expression involving
33390 pointers gets vectorized. We're trying to use the address of a
33391 stack slot as a vector initializer.
33393 (set (reg:V2DI 74 [ vect_cst_.2 ])
33394 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33396 Eventually frame gets turned into sp+offset like this:
33398 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33399 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33400 (const_int 392 [0x188]))))
33402 That later gets turned into:
33404 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33405 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33406 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33408 We'll have the following reload recorded:
33410 Reload 0: reload_in (DI) =
33411 (plus:DI (reg/f:DI 7 sp)
33412 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33413 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33414 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33415 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33416 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33417 reload_reg_rtx: (reg:V2DI 22 xmm1)
33419 Which isn't going to work since SSE instructions can't handle scalar
33420 additions. Returning GENERAL_REGS forces the addition into integer
33421 register and reload can handle subsequent reloads without problems. */
33429 }
33431 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33433 static bool
33435 {
33437 {
33452 }
33455 }
33457 /* If we are copying between general and FP registers, we need a memory
33458 location. The same is true for SSE and MMX registers.
33460 To optimize register_move_cost performance, allow inline variant.
33462 The macro can't work reliably when one of the CLASSES is class containing
33463 registers from multiple units (SSE, MMX, integer). We avoid this by never
33464 combining those units in single alternative in the machine description.
33465 Ensure that this constraint holds to avoid unexpected surprises.
33467 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
33468 enforce these sanity checks. */
33473 {
33480 {
33483 }
33488 /* ??? This is a lie. We do have moves between mmx/general, and for
33489 mmx/sse2. But by saying we need secondary memory we discourage the
33490 register allocator from using the mmx registers unless needed. */
33495 {
33496 /* SSE1 doesn't have any direct moves from other classes. */
33500 /* If the target says that inter-unit moves are more expensive
33501 than moving through memory, then don't generate them. */
33505 /* Between SSE and general, we have moves no larger than word size. */
33508 }
33511 }
33513 bool
33516 {
33518 }
33520 /* Implement the TARGET_CLASS_MAX_NREGS hook.
33522 On the 80386, this is the size of MODE in words,
33523 except in the FP regs, where a single reg is always enough. */
33525 static unsigned char
33527 {
33529 {
33534 else
33536 }
33537 else
33538 {
33541 else
33543 }
33544 }
33546 /* Return true if the registers in CLASS cannot represent the change from
33547 modes FROM to TO. */
33549 bool
33552 {
33556 /* x87 registers can't do subreg at all, as all values are reformatted
33557 to extended precision. */
33562 {
33563 /* Vector registers do not support QI or HImode loads. If we don't
33564 disallow a change to these modes, reload will assume it's ok to
33565 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
33566 the vec_dupv4hi pattern. */
33570 /* Vector registers do not support subreg with nonzero offsets, which
33571 are otherwise valid for integer registers. Since we can't see
33572 whether we have a nonzero offset from here, prohibit all
33573 nonparadoxical subregs changing size. */
33576 }
33579 }
33581 /* Return the cost of moving data of mode M between a
33582 register and memory. A value of 2 is the default; this cost is
33583 relative to those in `REGISTER_MOVE_COST'.
33585 This function is used extensively by register_move_cost that is used to
33586 build tables at startup. Make it inline in this case.
33587 When IN is 2, return maximum of in and out move cost.
33589 If moving between registers and memory is more expensive than
33590 between two registers, you should define this macro to express the
33591 relative cost.
33593 Model also increased moving costs of QImode registers in non
33594 Q_REGS classes.
33595 */
33599 {
33602 {
33605 {
33617 }
33621 }
33623 {
33626 {
33638 }
33642 }
33644 {
33647 {
33656 }
33660 }
33662 {
33665 {
33671 else
33676 }
33677 else
33678 {
33683 else
33685 }
33692 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
33699 else
33703 }
33704 }
33706 static int
33709 {
33711 }
33714 /* Return the cost of moving data from a register in class CLASS1 to
33715 one in class CLASS2.
33717 It is not required that the cost always equal 2 when FROM is the same as TO;
33718 on some machines it is expensive to move between registers if they are not
33719 general registers. */
33721 static int
33723 reg_class_t class2_i)
33724 {
33728 /* In case we require secondary memory, compute cost of the store followed
33729 by load. In order to avoid bad register allocation choices, we need
33730 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
33733 {
33739 /* In case of copying from general_purpose_register we may emit multiple
33740 stores followed by single load causing memory size mismatch stall.
33741 Count this as arbitrarily high cost of 20. */
33746 /* In the case of FP/MMX moves, the registers actually overlap, and we
33747 have to switch modes in order to treat them differently. */
33753 }
33755 /* Moves between SSE/MMX and integer unit are expensive. */
33759 /* ??? By keeping returned value relatively high, we limit the number
33760 of moves between integer and MMX/SSE registers for all targets.
33761 Additionally, high value prevents problem with x86_modes_tieable_p(),
33762 where integer modes in MMX/SSE registers are not tieable
33763 because of missing QImode and HImode moves to, from or between
33764 MMX/SSE registers. */
33774 }
33776 /* Return TRUE if hard register REGNO can hold a value of machine-mode
33777 MODE. */
33779 bool
33781 {
33782 /* Flags and only flags can only hold CCmode values. */
33792 {
33793 /* We implement the move patterns for all vector modes into and
33794 out of SSE registers, even when no operation instructions
33795 are available. OImode move is available only when AVX is
33796 enabled. */
33803 }
33805 {
33806 /* We implement the move patterns for 3DNOW modes even in MMX mode,
33807 so if the register is available at all, then we can move data of
33808 the given mode into or out of it. */
33811 }
33814 {
33815 /* Take care for QImode values - they can be in non-QI regs,
33816 but then they do cause partial register stalls. */
33822 }
33823 /* We handle both integer and floats in the general purpose registers. */
33830 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
33831 on to use that value in smaller contexts, this can easily force a
33832 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
33833 supporting DImode, allow it. */
33838 }
33840 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
33841 tieable integer mode. */
33843 static bool
33845 {
33847 {
33860 }
33861 }
33863 /* Return true if MODE1 is accessible in a register that can hold MODE2
33864 without copying. That is, all register classes that can hold MODE2
33865 can also hold MODE1. */
33867 bool
33869 {
33877 /* MODE2 being XFmode implies fp stack or general regs, which means we
33878 can tie any smaller floating point modes to it. Note that we do not
33879 tie this with TFmode. */
33883 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
33884 that we can tie it with SFmode. */
33888 /* If MODE2 is only appropriate for an SSE register, then tie with
33889 any other mode acceptable to SSE registers. */
33899 /* If MODE2 is appropriate for an MMX register, then tie
33900 with any other mode acceptable to MMX registers. */
33907 }
33909 /* Return the cost of moving between two registers of mode MODE. */
33911 static int
33913 {
33917 {
33948 }
33950 /* Return the cost of moving between two registers of mode MODE,
33951 assuming that the move will be in pieces of at most UNITS bytes. */
33953 }
33955 /* Compute a (partial) cost for rtx X. Return true if the complete
33956 cost has been computed, and false if subexpressions should be
33957 scanned. In either case, *TOTAL contains the cost result. */
33959 static bool
33962 {
33969 {
33973 {
33976 }
33988 && (!TARGET_64BIT
33993 else
33999 {
34002 }
34004 {
34014 }
34016 {
34019 {
34028 }
34029 }
34030 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34031 it'll probably end up. Add a penalty for size. */
34038 /* The zero extensions is often completely free on x86_64, so make
34039 it as cheap as possible. */
34045 else
34057 {
34060 {
34063 }
34066 {
34069 }
34070 }
34071 /* FALLTHRU */
34078 {
34079 /* ??? Should be SSE vector operation cost. */
34080 /* At least for published AMD latencies, this really is the same
34081 as the latency for a simple fpu operation like fabs. */
34082 /* V*QImode is emulated with 1-11 insns. */
34084 {
34087 {
34088 /* For XOP we use vpshab, which requires a broadcast of the
34089 value to the variable shift insn. For constants this
34090 means a V16Q const in mem; even when we can perform the
34091 shift with one insn set the cost to prefer paddb. */
34093 {
34098 }
34100 }
34104 }
34105 else
34107 }
34109 {
34111 {
34114 else
34116 }
34117 else
34118 {
34121 else
34123 }
34124 }
34125 else
34126 {
34129 else
34131 }
34135 {
34136 rtx sub;
34141 /* ??? SSE scalar/vector cost should be used here. */
34142 /* ??? Bald assumption that fma has the same cost as fmul. */
34146 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34157 }
34161 {
34162 /* ??? SSE scalar cost should be used here. */
34165 }
34167 {
34170 }
34172 {
34173 /* ??? SSE vector cost should be used here. */
34176 }
34178 {
34179 /* V*QImode is emulated with 7-13 insns. */
34181 {
34188 }
34189 /* V*DImode is emulated with 5-8 insns. */
34191 {
34194 else
34196 }
34197 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34198 insns, including two PMULUDQ. */
34201 else
34204 }
34205 else
34206 {
34211 {
34214 nbits++;
34215 }
34216 else
34217 /* This is arbitrary. */
34220 /* Compute costs correctly for widening multiplication. */
34224 {
34231 {
34235 else
34237 }
34241 }
34249 }
34256 /* ??? SSE cost should be used here. */
34261 /* ??? SSE vector cost should be used here. */
34263 else
34270 {
34275 {
34278 {
34286 }
34287 }
34290 {
34293 {
34299 }
34300 }
34302 {
34310 }
34311 }
34312 /* FALLTHRU */
34316 {
34317 /* ??? SSE cost should be used here. */
34320 }
34322 {
34325 }
34327 {
34328 /* ??? SSE vector cost should be used here. */
34331 }
34332 /* FALLTHRU */
34339 {
34346 }
34347 /* FALLTHRU */
34351 {
34352 /* ??? SSE cost should be used here. */
34355 }
34357 {
34360 }
34362 {
34363 /* ??? SSE vector cost should be used here. */
34366 }
34367 /* FALLTHRU */
34371 {
34372 /* ??? Should be SSE vector operation cost. */
34373 /* At least for published AMD latencies, this really is the same
34374 as the latency for a simple fpu operation like fabs. */
34376 }
34379 else
34388 {
34389 /* This kind of construct is implemented using test[bwl].
34390 Treat it as if we had an AND. */
34395 }
34405 /* ??? SSE cost should be used here. */
34410 /* ??? SSE vector cost should be used here. */
34416 /* ??? SSE cost should be used here. */
34421 /* ??? SSE vector cost should be used here. */
34434 /* ??? Assume all of these vector manipulation patterns are
34435 recognizable. In which case they all pretty much have the
34436 same cost. */
34442 }
34443 }
34445 #if TARGET_MACHO
34449 /* Given a symbol name and its associated stub, write out the
34450 definition of the stub. */
34452 void
34454 {
34459 /* For 64-bit we shouldn't get here. */
34462 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34479 else
34486 {
34488 }
34490 {
34491 /* PIC stub. */
34492 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34498 }
34499 else
34502 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
34503 it needs no stub-binding-helper. */
34510 {
34513 }
34514 else
34519 /* N.B. Keep the correspondence of these
34520 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
34521 old-pic/new-pic/non-pic stubs; altering this will break
34522 compatibility with existing dylibs. */
34524 {
34525 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34527 }
34528 else
34529 /* 16-byte -mdynamic-no-pic stub. */
34535 }
34538 /* Order the registers for register allocator. */
34540 void
34542 {
34546 /* First allocate the local general purpose registers. */
34551 /* Global general purpose registers. */
34556 /* x87 registers come first in case we are doing FP math
34557 using them. */
34562 /* SSE registers. */
34568 /* x87 registers. */
34576 /* Initialize the rest of array as we do not allocate some registers
34577 at all. */
34580 }
34582 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
34583 in struct attribute_spec handler. */
34584 static tree
34586 tree args,
34589 {
34594 {
34596 name);
34599 }
34601 {
34603 name);
34606 }
34608 {
34609 tree cst;
34613 {
34616 name);
34618 }
34621 {
34624 name);
34626 }
34629 }
34632 }
34634 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
34635 struct attribute_spec.handler. */
34636 static tree
34638 tree args ATTRIBUTE_UNUSED,
34640 {
34645 {
34647 name);
34650 }
34652 /* Can combine regparm with all attributes but fastcall. */
34654 {
34656 {
34658 }
34661 }
34663 {
34665 {
34667 }
34670 }
34673 }
34675 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34676 struct attribute_spec.handler. */
34677 static tree
34679 tree args ATTRIBUTE_UNUSED,
34681 {
34684 {
34687 }
34688 else
34692 {
34694 name);
34696 }
34702 {
34704 name);
34706 }
34709 }
34711 static tree
34713 tree args ATTRIBUTE_UNUSED,
34715 {
34717 {
34719 name);
34721 }
34723 }
34725 static bool
34727 {
34731 }
34733 /* Returns an expression indicating where the this parameter is
34734 located on entry to the FUNCTION. */
34736 static rtx
34738 {
34744 {
34749 else
34752 }
34757 {
34764 {
34769 }
34770 else
34771 {
34774 {
34780 }
34781 }
34783 }
34787 }
34789 /* Determine whether x86_output_mi_thunk can succeed. */
34791 static bool
34793 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
34795 {
34796 /* 64-bit can handle anything. */
34800 /* For 32-bit, everything's fine if we have one free register. */
34804 /* Need a free register for vcall_offset. */
34808 /* Need a free register for GOT references. */
34812 /* Otherwise ok. */
34814 }
34816 /* Output the assembler code for a thunk function. THUNK_DECL is the
34817 declaration for the thunk function itself, FUNCTION is the decl for
34818 the target function. DELTA is an immediate constant offset to be
34819 added to THIS. If VCALL_OFFSET is nonzero, the word at
34820 *(*this + vcall_offset) should be added to THIS. */
34822 static void
34826 {
34833 else
34834 {
34840 else
34842 }
34846 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
34847 pull it in now and let DELTA benefit. */
34851 {
34852 /* Put the this parameter into %eax. */
34855 }
34856 else
34859 /* Adjust the this parameter by a fixed constant. */
34861 {
34866 {
34868 {
34872 }
34873 }
34876 }
34878 /* Adjust the this parameter by a value stored in the vtable. */
34880 {
34890 /* Adjust the this parameter. */
34894 {
34898 }
34905 vcall_mem));
34906 else
34908 }
34910 /* If necessary, drop THIS back to its stack slot. */
34916 {
34919 ;
34920 else
34921 {
34925 }
34926 }
34927 else
34928 {
34930 ;
34931 #if TARGET_MACHO
34933 {
34936 }
34938 else
34939 {
34946 }
34947 }
34949 /* Our sibling call patterns do not allow memories, because we have no
34950 predicate that can distinguish between frame and non-frame memory.
34951 For our purposes here, we can get away with (ab)using a jump pattern,
34952 because we're going to do no optimization. */
34955 else
34956 {
34962 {
34968 }
34974 }
34977 /* Emit just enough of rest_of_compilation to get the insns emitted.
34978 Note that use_thunk calls assemble_start_function et al. */
34984 }
34986 static void
34988 {
34990 #if TARGET_MACHO
34992 #endif
34999 }
35001 int
35003 {
35015 }
35017 /* Output assembler code to FILE to increment profiler label # LABELNO
35018 for profiling a function entry. */
35019 void
35021 {
35026 {
35027 #ifndef NO_PROFILE_COUNTERS
35029 #endif
35033 else
35035 }
35037 {
35038 #ifndef NO_PROFILE_COUNTERS
35041 #endif
35043 }
35044 else
35045 {
35046 #ifndef NO_PROFILE_COUNTERS
35049 #endif
35051 }
35052 }
35054 /* We don't have exact information about the insn sizes, but we may assume
35055 quite safely that we are informed about all 1 byte insns and memory
35056 address sizes. This is enough to eliminate unnecessary padding in
35057 99% of cases. */
35059 static int
35061 {
35067 /* Discard alignments we've emit and jump instructions. */
35074 /* Important case - calls are always 5 bytes.
35075 It is common to have many calls in the row. */
35084 /* For normal instructions we rely on get_attr_length being exact,
35085 with a few exceptions. */
35087 {
35091 {
35101 /* Otherwise trust get_attr_length. */
35103 }
35108 }
35111 else
35113 }
35115 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35117 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35118 window. */
35120 static void
35122 {
35127 /* Look for all minimal intervals of instructions containing 4 jumps.
35128 The intervals are bounded by START and INSN. NBYTES is the total
35129 size of instructions in the interval including INSN and not including
35130 START. When the NBYTES is smaller than 16 bytes, it is possible
35131 that the end of START and INSN ends up in the same 16byte page.
35133 The smallest offset in the page INSN can start is the case where START
35134 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35135 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35136 */
35138 {
35142 {
35148 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35149 already in the current 16 byte page, because otherwise
35150 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35151 bytes to reach 16 byte boundary. */
35159 {
35161 {
35168 else
35171 }
35172 }
35174 }
35185 njumps++;
35186 else
35190 {
35197 else
35200 }
35207 {
35214 }
35215 }
35216 }
35217 #endif
35219 /* AMD Athlon works faster
35220 when RET is not destination of conditional jump or directly preceded
35221 by other jump instruction. We avoid the penalty by inserting NOP just
35222 before the RET instructions in such cases. */
35223 static void
35225 {
35226 edge e;
35227 edge_iterator ei;
35230 {
35233 rtx prev;
35243 {
35244 edge e;
35245 edge_iterator ei;
35251 }
35253 {
35259 /* Empty functions get branch mispredict even when
35260 the jump destination is not visible to us. */
35263 }
35265 {
35268 }
35269 }
35270 }
35272 /* Count the minimum number of instructions in BB. Return 4 if the
35273 number of instructions >= 4. */
35275 static int
35277 {
35278 rtx insn;
35281 /* Count number of instructions in this block. Return 4 if the number
35282 of instructions >= 4. */
35284 {
35285 /* Only happen in exit blocks. */
35293 {
35294 insn_count++;
35297 }
35298 }
35301 }
35304 /* Count the minimum number of instructions in code path in BB.
35305 Return 4 if the number of instructions >= 4. */
35307 static int
35309 {
35310 edge e;
35311 edge_iterator ei;
35314 /* Only bother counting instructions along paths with no
35315 more than 2 basic blocks between entry and exit. Given
35316 that BB has an edge to exit, determine if a predecessor
35317 of BB has an edge from entry. If so, compute the number
35318 of instructions in the predecessor block. If there
35319 happen to be multiple such blocks, compute the minimum. */
35322 {
35323 edge prev_e;
35324 edge_iterator prev_ei;
35327 {
35330 }
35332 {
35334 {
35339 }
35340 }
35341 }
35347 }
35349 /* Pad short function to 4 instructions. */
35351 static void
35353 {
35354 edge e;
35355 edge_iterator ei;
35358 {
35361 {
35364 /* Pad short function. */
35366 {
35369 /* Find epilogue. */
35378 /* Two NOPs count as one instruction. */
35381 }
35382 }
35383 }
35384 }
35386 /* Implement machine specific optimizations. We implement padding of returns
35387 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35388 static void
35390 {
35391 /* We are freeing block_for_insn in the toplev to keep compatibility
35392 with old MDEP_REORGS that are not CFG based. Recompute it now. */
35396 {
35401 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35404 #endif
35405 }
35406 }
35408 /* Return nonzero when QImode register that must be represented via REX prefix
35409 is used. */
35410 bool
35412 {
35420 }
35422 /* Return nonzero when P points to register encoded via REX prefix.
35423 Called via for_each_rtx. */
35424 static int
35426 {
35432 }
35434 /* Return true when INSN mentions register that must be encoded using REX
35435 prefix. */
35436 bool
35438 {
35441 }
35443 /* If profitable, negate (without causing overflow) integer constant
35444 of mode MODE at location LOC. Return true in this case. */
35445 bool
35447 {
35448 HOST_WIDE_INT val;
35454 {
35456 /* DImode x86_64 constants must fit in 32 bits. */
35469 }
35471 /* Avoid overflows. */
35477 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
35478 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
35481 {
35484 }
35487 }
35489 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
35490 optabs would emit if we didn't have TFmode patterns. */
35492 void
35494 {
35528 }
35529 \f
35530 /* AVX2 does support 32-byte integer vector operations,
35531 thus the longest vector we are faced with is V32QImode. */
35532 #define MAX_VECT_LEN 32
35534 struct expand_vec_perm_d
35535 {
35542 };
35548 /* Get a vector mode of the same size as the original but with elements
35549 twice as wide. This is only guaranteed to apply to integral vectors. */
35553 {
35554 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
35559 }
35561 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35562 with all elements equal to VAR. Return true if successful. */
35564 static bool
35567 {
35571 {
35576 /* FALLTHRU */
35586 {
35589 /* First attempt to recognize VAL as-is. */
35593 {
35594 rtx seq;
35595 /* If that fails, force VAL into a register. */
35606 }
35607 }
35614 {
35615 rtx x;
35622 }
35632 {
35636 permute:
35644 /* Extend to SImode using a paradoxical SUBREG. */
35648 /* Insert the SImode value as low element of a V4SImode vector. */
35656 }
35664 widen:
35665 /* Replicate the value once into the next wider mode and recurse. */
35666 {
35668 rtx x;
35684 }
35688 {
35697 }
35702 }
35703 }
35705 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35706 whose ONE_VAR element is VAR, and other elements are zero. Return true
35707 if successful. */
35709 static bool
35712 {
35714 rtx new_target;
35719 {
35721 /* For SSE4.1, we normally use vector set. But if the second
35722 element is zero and inter-unit moves are OK, we use movq
35723 instead. */
35724 use_vector_set = (TARGET_64BIT
35725 && TARGET_SSE4_1
35726 && !(TARGET_INTER_UNIT_MOVES
35748 /* Use ix86_expand_vector_set in 64bit mode only. */
35753 }
35756 {
35761 }
35764 {
35769 /* FALLTHRU */
35784 else
35791 {
35792 /* We need to shuffle the value to the correct position, so
35793 create a new pseudo to store the intermediate result. */
35795 /* With SSE2, we can use the integer shuffle insns. */
35797 {
35799 const1_rtx,
35806 }
35808 /* Otherwise convert the intermediate result to V4SFmode and
35809 use the SSE1 shuffle instructions. */
35811 {
35814 }
35815 else
35819 const1_rtx,
35828 }
35843 widen:
35847 /* Zero extend the variable element to SImode and recurse. */
35860 }
35861 }
35863 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35864 consisting of the values in VALS. It is known that all elements
35865 except ONE_VAR are constants. Return true if successful. */
35867 static bool
35870 {
35880 {
35885 /* For the two element vectors, it's just as easy to use
35886 the general case. */
35890 /* Use ix86_expand_vector_set in 64bit mode only. */
35912 widen:
35913 /* There's no way to set one QImode entry easily. Combine
35914 the variable value with its adjacent constant value, and
35915 promote to an HImode set. */
35918 {
35923 }
35924 else
35925 {
35928 }
35942 }
35947 }
35949 /* A subroutine of ix86_expand_vector_init_general. Use vector
35950 concatenate to handle the most general case: all values variable,
35951 and none identical. */
35953 static void
35956 {
35959 rtvec v;
35963 {
35966 {
35999 }
36012 {
36027 }
36032 {
36043 }
36046 half:
36047 /* FIXME: We process inputs backward to help RA. PR 36222. */
36051 {
36056 }
36060 {
36063 {
36067 }
36070 }
36071 else
36077 }
36078 }
36080 /* A subroutine of ix86_expand_vector_init_general. Use vector
36081 interleave to handle the most general case: all values variable,
36082 and none identical. */
36084 static void
36087 {
36096 {
36117 }
36120 {
36121 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36125 /* Insert the SImode value as low element of V4SImode vector. */
36129 op0),
36131 const1_rtx);
36134 /* Cast the V4SImode vector back to a vector in orignal mode. */
36138 /* Load even elements into the second positon. */
36142 const1_rtx));
36144 /* Cast vector to FIRST_IMODE vector. */
36147 }
36149 /* Interleave low FIRST_IMODE vectors. */
36151 {
36155 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36158 }
36160 /* Interleave low SECOND_IMODE vectors. */
36162 {
36165 {
36170 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36171 vector. */
36174 }
36177 /* FALLTHRU */
36184 /* Cast the SECOND_IMODE vector back to a vector on original
36185 mode. */
36192 }
36193 }
36195 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36196 all values variable, and none identical. */
36198 static void
36201 {
36207 {
36212 /* FALLTHRU */
36236 half:
36253 /* FALLTHRU */
36259 /* Don't use ix86_expand_vector_init_interleave if we can't
36260 move from GPR to SSE register directly. */
36276 }
36278 {
36290 {
36294 {
36300 else
36301 {
36306 }
36307 }
36310 }
36315 {
36321 }
36323 {
36329 }
36330 else
36332 }
36333 }
36335 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36336 instructions unless MMX_OK is true. */
36338 void
36340 {
36347 rtx x;
36350 {
36360 }
36362 /* Constants are best loaded from the constant pool. */
36364 {
36367 }
36369 /* If all values are identical, broadcast the value. */
36375 /* Values where only one field is non-constant are best loaded from
36376 the pool and overwritten via move later. */
36378 {
36382 one_var))
36387 }
36390 }
36392 void
36394 {
36399 rtx tmp;
36401 = {
36408 };
36410 = {
36417 };
36421 {
36425 {
36430 else
36434 }
36446 else
36452 {
36455 /* For the two element vectors, we implement a VEC_CONCAT with
36456 the extraction of the other element. */
36463 else
36468 }
36477 {
36483 /* tmp = target = A B C D */
36485 /* target = A A B B */
36487 /* target = X A B B */
36489 /* target = A X C D */
36496 /* tmp = target = A B C D */
36498 /* tmp = X B C D */
36500 /* target = A B X D */
36507 /* tmp = target = A B C D */
36509 /* tmp = X B C D */
36511 /* target = A B X D */
36519 }
36527 /* Element 0 handled by vec_merge below. */
36529 {
36532 }
36535 {
36536 /* With SSE2, use integer shuffles to swap element 0 and ELT,
36537 store into element 0, then shuffle them back. */
36554 }
36555 else
36556 {
36557 /* For SSE1, we have to reuse the V4SF code. */
36560 }
36613 half:
36614 /* Compute offset. */
36620 /* Extract the half. */
36624 /* Put val in tmp at elt. */
36627 /* Put it back. */
36633 }
36636 {
36640 }
36641 else
36642 {
36651 }
36652 }
36654 void
36656 {
36660 rtx tmp;
36663 {
36668 /* FALLTHRU */
36681 {
36701 }
36713 {
36715 {
36735 }
36739 }
36740 else
36741 {
36742 /* For SSE1, we have to reuse the V4SF code. */
36746 }
36762 {
36766 else
36770 }
36775 {
36779 else
36783 }
36788 {
36792 else
36796 }
36801 {
36805 else
36809 }
36814 {
36818 else
36822 }
36827 {
36831 else
36835 }
36839 /* ??? Could extract the appropriate HImode element and shift. */
36842 }
36845 {
36849 /* Let the rtl optimizers know about the zero extension performed. */
36851 {
36854 }
36857 }
36858 else
36859 {
36866 }
36867 }
36869 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
36870 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
36871 The upper bits of DEST are undefined, though they shouldn't cause
36872 exceptions (some bits from src or all zeros are ok). */
36874 static void
36876 {
36877 rtx tem;
36879 {
36883 else
36901 else
36908 else
36919 const1_rtx);
36920 else
36927 }
36929 }
36931 /* Expand a vector reduction. FN is the binary pattern to reduce;
36932 DEST is the destination; IN is the input vector. */
36934 void
36936 {
36941 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
36945 {
36948 }
36953 {
36958 else
36962 }
36963 }
36964 \f
36965 /* Target hook for scalar_mode_supported_p. */
36966 static bool
36968 {
36973 else
36975 }
36977 /* Implements target hook vector_mode_supported_p. */
36978 static bool
36980 {
36992 }
36994 /* Target hook for c_mode_for_suffix. */
36995 static enum machine_mode
36997 {
37004 }
37006 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37008 We do this in the new i386 backend to maintain source compatibility
37009 with the old cc0-based compiler. */
37011 static tree
37013 tree inputs ATTRIBUTE_UNUSED,
37014 tree clobbers)
37015 {
37017 clobbers);
37019 clobbers);
37021 }
37023 /* Implements target vector targetm.asm.encode_section_info. */
37025 static void ATTRIBUTE_UNUSED
37027 {
37034 }
37036 /* Worker function for REVERSE_CONDITION. */
37038 enum rtx_code
37040 {
37044 }
37046 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37047 to OPERANDS[0]. */
37051 {
37053 {
37056 {
37060 }
37064 }
37066 {
37070 else
37071 {
37072 /* There is no non-popping store to memory for XFmode.
37073 So if we need one, follow the store with a load. */
37076 else
37078 }
37079 }
37080 else
37082 }
37084 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37085 FP status register is set. */
37087 void
37089 {
37091 rtx temp;
37096 {
37101 }
37102 else
37103 {
37108 }
37112 pc_rtx);
37117 }
37119 /* Output code to perform a log1p XFmode calculation. */
37122 {
37128 rtx test;
37134 XFmode));
37148 }
37150 /* Emit code for round calculation. */
37152 {
37159 rtx insn;
37164 {
37176 }
37179 {
37200 }
37208 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37210 /* scratch = fxam(op1) */
37213 UNSPEC_FXAM)));
37214 /* e1 = fabs(op1) */
37217 /* e2 = e1 + 0.5 */
37222 /* res = floor(e2) */
37224 {
37229 }
37230 else
37234 {
37237 {
37244 UNSPEC_TRUNC_NOOP)));
37245 }
37261 }
37263 /* flags = signbit(a) */
37266 /* if (flags) then res = -res */
37270 pc_rtx);
37281 }
37283 /* Output code to perform a Newton-Rhapson approximation of a single precision
37284 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37287 {
37295 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37299 /* x0 = rcp(b) estimate */
37302 UNSPEC_RCP)));
37303 /* e0 = x0 * b */
37307 /* e0 = x0 * e0 */
37311 /* e1 = x0 + x0 */
37315 /* x1 = e1 - e0 */
37319 /* res = a * x1 */
37322 }
37324 /* Output code to perform a Newton-Rhapson approximation of a
37325 single precision floating point [reciprocal] square root. */
37329 {
37331 REAL_VALUE_TYPE r;
37346 {
37349 }
37351 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37352 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37356 /* x0 = rsqrt(a) estimate */
37359 UNSPEC_RSQRT)));
37361 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37363 {
37375 }
37377 /* e0 = x0 * a */
37380 /* e1 = e0 * x0 */
37384 /* e2 = e1 - 3. */
37391 /* e3 = -.5 * x0 */
37394 else
37395 /* e3 = -.5 * e0 */
37398 /* ret = e2 * e3 */
37401 }
37403 #ifdef TARGET_SOLARIS
37404 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
37406 static void
37408 tree decl)
37409 {
37410 /* With Binutils 2.15, the "@unwind" marker must be specified on
37411 every occurrence of the ".eh_frame" section, not just the first
37412 one. */
37415 {
37419 }
37421 #ifndef USE_GAS
37423 {
37426 }
37427 #endif
37430 }
37433 /* Return the mangling of TYPE if it is an extended fundamental type. */
37437 {
37445 {
37447 /* __float128 is "g". */
37450 /* "long double" or __float80 is "e". */
37454 }
37455 }
37457 /* For 32-bit code we can save PIC register setup by using
37458 __stack_chk_fail_local hidden function instead of calling
37459 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
37460 register, so it is better to call __stack_chk_fail directly. */
37462 static tree ATTRIBUTE_UNUSED
37464 {
37465 return TARGET_64BIT
37468 }
37470 /* Select a format to encode pointers in exception handling data. CODE
37471 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
37472 true if the symbol may be affected by dynamic relocations.
37474 ??? All x86 object file formats are capable of representing this.
37475 After all, the relocation needed is the same as for the call insn.
37476 Whether or not a particular assembler allows us to enter such, I
37477 guess we'll have to see. */
37478 int
37480 {
37482 {
37489 }
37494 }
37495 \f
37496 /* Expand copysign from SIGN to the positive value ABS_VALUE
37497 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
37498 the sign-bit. */
37499 static void
37501 {
37505 {
37512 else
37517 {
37518 /* We need to generate a scalar mode mask in this case. */
37523 }
37524 }
37525 else
37531 }
37533 /* Expand fabs (OP0) and return a new rtx that holds the result. The
37534 mask for masking out the sign-bit is stored in *SMASK, if that is
37535 non-null. */
37536 static rtx
37538 {
37547 else
37551 {
37552 /* We need to generate a scalar mode mask in this case. */
37557 }
37565 }
37567 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
37568 swapping the operands if SWAP_OPERANDS is true. The expanded
37569 code is a forward jump to a newly created label in case the
37570 comparison is true. The generated label rtx is returned. */
37571 static rtx
37574 {
37578 {
37582 }
37595 }
37597 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
37598 using comparison code CODE. Operands are swapped for the comparison if
37599 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
37600 static rtx
37603 {
37609 {
37613 }
37620 }
37622 /* Generate and return a rtx of mode MODE for 2**n where n is the number
37623 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
37624 static rtx
37626 {
37627 REAL_VALUE_TYPE TWO52r;
37628 rtx TWO52;
37635 }
37637 /* Expand SSE sequence for computing lround from OP1 storing
37638 into OP0. */
37639 void
37641 {
37642 /* C code for the stuff we're doing below:
37643 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
37644 return (long)tmp;
37645 */
37649 rtx adj;
37651 /* load nextafter (0.5, 0.0) */
37656 /* adj = copysign (0.5, op1) */
37660 /* adj = op1 + adj */
37663 /* op0 = (imode)adj */
37665 }
37667 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
37668 into OPERAND0. */
37669 void
37671 {
37672 /* C code for the stuff we're doing below (for do_floor):
37673 xi = (long)op1;
37674 xi -= (double)xi > op1 ? 1 : 0;
37675 return xi;
37676 */
37681 /* reg = (long)op1 */
37685 /* freg = (double)reg */
37689 /* ireg = (freg > op1) ? ireg - 1 : ireg */
37700 }
37702 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
37703 result in OPERAND0. */
37704 void
37706 {
37707 /* C code for the stuff we're doing below:
37708 xa = fabs (operand1);
37709 if (!isless (xa, 2**52))
37710 return operand1;
37711 xa = xa + 2**52 - 2**52;
37712 return copysign (xa, operand1);
37713 */
37720 /* xa = abs (operand1) */
37723 /* if (!isless (xa, TWO52)) goto label; */
37736 }
37738 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37739 into OPERAND0. */
37740 void
37742 {
37743 /* C code for the stuff we expand below.
37744 double xa = fabs (x), x2;
37745 if (!isless (xa, TWO52))
37746 return x;
37747 xa = xa + TWO52 - TWO52;
37748 x2 = copysign (xa, x);
37749 Compensate. Floor:
37750 if (x2 > x)
37751 x2 -= 1;
37752 Compensate. Ceil:
37753 if (x2 < x)
37754 x2 -= -1;
37755 return x2;
37756 */
37762 /* Temporary for holding the result, initialized to the input
37763 operand to ease control flow. */
37767 /* xa = abs (operand1) */
37770 /* if (!isless (xa, TWO52)) goto label; */
37773 /* xa = xa + TWO52 - TWO52; */
37777 /* xa = copysign (xa, operand1) */
37780 /* generate 1.0 or -1.0 */
37785 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37789 /* We always need to subtract here to preserve signed zero. */
37798 }
37800 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37801 into OPERAND0. */
37802 void
37804 {
37805 /* C code for the stuff we expand below.
37806 double xa = fabs (x), x2;
37807 if (!isless (xa, TWO52))
37808 return x;
37809 x2 = (double)(long)x;
37810 Compensate. Floor:
37811 if (x2 > x)
37812 x2 -= 1;
37813 Compensate. Ceil:
37814 if (x2 < x)
37815 x2 += 1;
37816 if (HONOR_SIGNED_ZEROS (mode))
37817 return copysign (x2, x);
37818 return x2;
37819 */
37825 /* Temporary for holding the result, initialized to the input
37826 operand to ease control flow. */
37830 /* xa = abs (operand1) */
37833 /* if (!isless (xa, TWO52)) goto label; */
37836 /* xa = (double)(long)x */
37841 /* generate 1.0 */
37844 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37859 }
37861 /* Expand SSE sequence for computing round from OPERAND1 storing
37862 into OPERAND0. Sequence that works without relying on DImode truncation
37863 via cvttsd2siq that is only available on 64bit targets. */
37864 void
37866 {
37867 /* C code for the stuff we expand below.
37868 double xa = fabs (x), xa2, x2;
37869 if (!isless (xa, TWO52))
37870 return x;
37871 Using the absolute value and copying back sign makes
37872 -0.0 -> -0.0 correct.
37873 xa2 = xa + TWO52 - TWO52;
37874 Compensate.
37875 dxa = xa2 - xa;
37876 if (dxa <= -0.5)
37877 xa2 += 1;
37878 else if (dxa > 0.5)
37879 xa2 -= 1;
37880 x2 = copysign (xa2, x);
37881 return x2;
37882 */
37888 /* Temporary for holding the result, initialized to the input
37889 operand to ease control flow. */
37893 /* xa = abs (operand1) */
37896 /* if (!isless (xa, TWO52)) goto label; */
37899 /* xa2 = xa + TWO52 - TWO52; */
37903 /* dxa = xa2 - xa; */
37906 /* generate 0.5, 1.0 and -0.5 */
37912 /* Compensate. */
37914 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
37919 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
37925 /* res = copysign (xa2, operand1) */
37932 }
37934 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37935 into OPERAND0. */
37936 void
37938 {
37939 /* C code for SSE variant we expand below.
37940 double xa = fabs (x), x2;
37941 if (!isless (xa, TWO52))
37942 return x;
37943 x2 = (double)(long)x;
37944 if (HONOR_SIGNED_ZEROS (mode))
37945 return copysign (x2, x);
37946 return x2;
37947 */
37953 /* Temporary for holding the result, initialized to the input
37954 operand to ease control flow. */
37958 /* xa = abs (operand1) */
37961 /* if (!isless (xa, TWO52)) goto label; */
37964 /* x = (double)(long)x */
37976 }
37978 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37979 into OPERAND0. */
37980 void
37982 {
37986 /* C code for SSE variant we expand below.
37987 double xa = fabs (x), x2;
37988 if (!isless (xa, TWO52))
37989 return x;
37990 xa2 = xa + TWO52 - TWO52;
37991 Compensate:
37992 if (xa2 > xa)
37993 xa2 -= 1.0;
37994 x2 = copysign (xa2, x);
37995 return x2;
37996 */
38000 /* Temporary for holding the result, initialized to the input
38001 operand to ease control flow. */
38005 /* xa = abs (operand1) */
38008 /* if (!isless (xa, TWO52)) goto label; */
38011 /* res = xa + TWO52 - TWO52; */
38016 /* generate 1.0 */
38019 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38027 /* res = copysign (res, operand1) */
38034 }
38036 /* Expand SSE sequence for computing round from OPERAND1 storing
38037 into OPERAND0. */
38038 void
38040 {
38041 /* C code for the stuff we're doing below:
38042 double xa = fabs (x);
38043 if (!isless (xa, TWO52))
38044 return x;
38045 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38046 return copysign (xa, x);
38047 */
38053 /* Temporary for holding the result, initialized to the input
38054 operand to ease control flow. */
38062 /* load nextafter (0.5, 0.0) */
38067 /* xa = xa + 0.5 */
38071 /* xa = (double)(int64_t)xa */
38076 /* res = copysign (xa, operand1) */
38083 }
38085 /* Expand SSE sequence for computing round
38086 from OP1 storing into OP0 using sse4 round insn. */
38087 void
38089 {
38098 {
38109 }
38111 /* round (a) = trunc (a + copysign (0.5, a)) */
38113 /* load nextafter (0.5, 0.0) */
38119 /* e1 = copysign (0.5, op1) */
38123 /* e2 = op1 + e1 */
38126 /* res = trunc (e2) */
38131 }
38132 \f
38134 /* Table of valid machine attributes. */
38136 {
38137 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38138 affects_type_identity } */
38139 /* Stdcall attribute says callee is responsible for popping arguments
38140 if they are not variable. */
38143 /* Fastcall attribute says callee is responsible for popping arguments
38144 if they are not variable. */
38147 /* Thiscall attribute says callee is responsible for popping arguments
38148 if they are not variable. */
38151 /* Cdecl attribute says the callee is a normal C declaration */
38154 /* Regparm attribute specifies how many integer arguments are to be
38155 passed in registers. */
38158 /* Sseregparm attribute says we are using x86_64 calling conventions
38159 for FP arguments. */
38162 /* The transactional memory builtins are implicitly regparm or fastcall
38163 depending on the ABI. Override the generic do-nothing attribute that
38164 these builtins were declared with. */
38167 /* force_align_arg_pointer says this function realigns the stack at entry. */
38170 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38175 #endif
38180 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38181 SUBTARGET_ATTRIBUTE_TABLE,
38182 #endif
38183 /* ms_abi and sysv_abi calling convention function attributes. */
38190 /* End element. */
38192 };
38194 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38195 static int
38197 tree vectype,
38199 {
38203 {
38248 }
38249 }
38251 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38252 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38253 insn every time. */
38257 /* Initialize vselect_insn. */
38259 static void
38261 {
38263 rtx x;
38274 }
38276 /* Construct (set target (vec_select op0 (parallel perm))) and
38277 return true if that's a valid instruction in the active ISA. */
38279 static bool
38282 {
38308 }
38310 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38312 static bool
38316 {
38318 rtx x;
38333 }
38335 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38336 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38338 static bool
38340 {
38349 ;
38351 ;
38353 ;
38354 else
38357 /* This is a blend, not a permute. Elements must stay in their
38358 respective lanes. */
38360 {
38364 }
38369 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38370 decision should be extracted elsewhere, so that we only try that
38371 sequence once all budget==3 options have been tried. */
38378 {
38402 /* See if bytes move in pairs so we can use pblendw with
38403 an immediate argument, rather than pblendvb with a vector
38404 argument. */
38407 {
38408 use_pblendvb:
38412 finish_pblendvb:
38418 else
38421 }
38426 /* FALLTHRU */
38428 do_subreg:
38435 /* See if bytes move in pairs. If not, vpblendvb must be used. */
38439 /* See if bytes move in quadruplets. If yes, vpblendd
38440 with immediate can be used. */
38445 {
38446 /* See if bytes move the same in both lanes. If yes,
38447 vpblendw with immediate can be used. */
38452 /* Use vpblendw. */
38457 }
38459 /* Use vpblendd. */
38466 /* See if words move in pairs. If yes, vpblendd can be used. */
38471 {
38472 /* See if words move the same in both lanes. If not,
38473 vpblendvb must be used. */
38476 {
38477 /* Use vpblendvb. */
38487 }
38489 /* Use vpblendw. */
38493 }
38495 /* Use vpblendd. */
38502 /* Use vpblendd. */
38510 }
38512 /* This matches five different patterns with the different modes. */
38518 }
38520 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38521 in terms of the variable form of vpermilps.
38523 Note that we will have already failed the immediate input vpermilps,
38524 which requires that the high and low part shuffle be identical; the
38525 variable form doesn't require that. */
38527 static bool
38529 {
38536 /* We can only permute within the 128-bit lane. */
38538 {
38542 }
38548 {
38551 /* Within each 128-bit lane, the elements of op0 are numbered
38552 from 0 and the elements of op1 are numbered from 4. */
38559 }
38566 }
38568 /* Return true if permutation D can be performed as VMODE permutation
38569 instead. */
38571 static bool
38573 {
38588 else
38594 }
38596 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38597 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
38599 static bool
38601 {
38610 {
38612 {
38615 {
38619 /* Use vperm2i128 insn. The pattern uses
38620 V4DImode instead of V2TImode. */
38629 }
38631 }
38632 }
38633 else
38634 {
38636 {
38639 }
38641 {
38645 /* V4DImode should be already handled through
38646 expand_vselect by vpermq instruction. */
38653 {
38654 /* First see if vpermq can be used for
38655 V8SImode/V16HImode/V32QImode. */
38657 {
38665 }
38667 /* Next see if vpermd can be used. */
38670 }
38671 /* Or if vpermps can be used. */
38676 {
38677 /* vpshufb only works intra lanes, it is not
38678 possible to shuffle bytes in between the lanes. */
38682 }
38683 }
38684 else
38686 }
38694 else
38695 {
38701 else
38705 {
38709 }
38710 }
38719 {
38726 else
38728 }
38729 else
38730 {
38733 }
38736 }
38738 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
38739 in a single instruction. */
38741 static bool
38743 {
38747 /* Check plain VEC_SELECT first, because AVX has instructions that could
38748 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
38749 input where SEL+CONCAT may not. */
38751 {
38757 {
38763 }
38766 {
38770 }
38772 {
38773 /* Use vpbroadcast{b,w,d}. */
38776 {
38795 /* For other modes prefer other shuffles this function creates. */
38797 }
38799 {
38803 }
38804 }
38809 /* There are plenty of patterns in sse.md that are written for
38810 SEL+CONCAT and are not replicated for a single op. Perhaps
38811 that should be changed, to avoid the nastiness here. */
38813 /* Recognize interleave style patterns, which means incrementing
38814 every other permutation operand. */
38816 {
38819 }
38824 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
38826 {
38828 {
38833 }
38838 }
38839 }
38841 /* Finally, try the fully general two operand permute. */
38846 /* Recognize interleave style patterns with reversed operands. */
38848 {
38850 {
38854 else
38857 }
38862 }
38864 /* Try the SSE4.1 blend variable merge instructions. */
38868 /* Try one of the AVX vpermil variable permutations. */
38872 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
38873 vpshufb, vpermd, vpermps or vpermq variable permutation. */
38878 }
38880 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38881 in terms of a pair of pshuflw + pshufhw instructions. */
38883 static bool
38885 {
38893 /* The two permutations only operate in 64-bit lanes. */
38904 /* Emit the pshuflw. */
38911 /* Emit the pshufhw. */
38919 }
38921 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38922 the permutation using the SSSE3 palignr instruction. This succeeds
38923 when all of the elements in PERM fit within one vector and we merely
38924 need to shift them down so that a single vector permutation has a
38925 chance to succeed. */
38927 static bool
38929 {
38933 rtx shift;
38935 /* Even with AVX, palignr only operates on 128-bit vectors. */
38941 {
38947 }
38951 /* Given that we have SSSE3, we know we'll be able to implement the
38952 single operand permutation after the palignr with pshufb. */
38966 {
38971 }
38973 /* Test for the degenerate case where the alignment by itself
38974 produces the desired permutation. */
38982 }
38986 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38987 a two vector permutation into a single vector permutation by using
38988 an interleave operation to merge the vectors. */
38990 static bool
38992 {
38997 rtx seq;
39001 {
39004 }
39006 {
39009 /* For 32-byte modes allow even d->one_operand_p.
39010 The lack of cross-lane shuffling in some instructions
39011 might prevent a single insn shuffle. */
39014 /* If expand_vec_perm_interleave3 can expand this into
39015 a 3 insn sequence, give up and let it be expanded as
39016 3 insn sequence. While that is one insn longer,
39017 it doesn't need a memory operand and in the common
39018 case that both interleave low and high permutations
39019 with the same operands are adjacent needs 4 insns
39020 for both after CSE. */
39023 }
39024 else
39027 /* Examine from whence the elements come. */
39036 {
39039 /* Split the two input vectors into 4 halves. */
39045 /* If the elements from the low halves use interleave low, and similarly
39046 for interleave high. If the elements are from mis-matched halves, we
39047 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39049 {
39050 /* punpckl* */
39052 {
39057 }
39060 }
39062 {
39063 /* punpckh* */
39065 {
39070 }
39073 }
39075 {
39076 /* shufps */
39078 {
39083 }
39085 {
39086 /* shufpd */
39091 }
39092 }
39094 {
39095 /* shufps */
39097 {
39102 }
39104 {
39105 /* shufpd */
39110 }
39111 }
39112 else
39114 }
39115 else
39116 {
39121 /* Split the two input vectors into 8 quarters. */
39127 {
39130 }
39133 {
39137 }
39139 {
39142 }
39145 {
39147 {
39148 /* Attempt to increase the likelihood that dfinal
39149 shuffle will be intra-lane. */
39153 }
39155 /* vperm2f128 or vperm2i128. */
39157 {
39162 }
39167 {
39171 {
39174 }
39175 }
39176 }
39181 {
39182 /* vpunpckl* */
39184 {
39193 }
39194 }
39197 {
39198 /* vpunpckh* */
39200 {
39209 }
39210 }
39211 else
39213 }
39215 /* Use the remapping array set up above to move the elements from their
39216 swizzled locations into their final destinations. */
39219 {
39222 /* If same_halves is true, both halves of the remapped vector are the
39223 same. Avoid cross-lane accesses if possible. */
39225 {
39228 }
39229 else
39231 }
39237 /* Test if the final remap can be done with a single insn. For V4SFmode or
39238 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39251 {
39255 }
39262 }
39264 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39265 a single vector cross-lane permutation into vpermq followed
39266 by any of the single insn permutations. */
39268 static bool
39270 {
39284 {
39287 }
39290 {
39295 }
39308 {
39315 }
39322 {
39327 ;
39330 else
39332 }
39341 }
39343 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39344 a vector permutation using two instructions, vperm2f128 resp.
39345 vperm2i128 followed by any single in-lane permutation. */
39347 static bool
39349 {
39363 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39364 immediate. For perm < 16 the second permutation uses
39365 d->op0 as first operand, for perm >= 16 it uses d->op1
39366 as first operand. The second operand is the result of
39367 vperm2[fi]128. */
39369 {
39370 /* Ignore permutations which do not move anything cross-lane. */
39372 {
39373 /* The second shuffle for e.g. V4DFmode has
39374 0123 and ABCD operands.
39375 Ignore AB23, as 23 is already in the second lane
39376 of the first operand. */
39378 /* And 01CD, as 01 is in the first lane of the first
39379 operand. */
39381 /* And 4567, as then the vperm2[fi]128 doesn't change
39382 anything on the original 4567 second operand. */
39384 }
39385 else
39386 {
39387 /* The second shuffle for e.g. V4DFmode has
39388 4567 and ABCD operands.
39389 Ignore AB67, as 67 is already in the second lane
39390 of the first operand. */
39392 /* And 45CD, as 45 is in the first lane of the first
39393 operand. */
39395 /* And 0123, as then the vperm2[fi]128 doesn't change
39396 anything on the original 0123 first operand. */
39398 }
39401 {
39407 else
39409 }
39412 {
39416 }
39417 else
39421 {
39425 /* Found a usable second shuffle. dfirst will be
39426 vperm2f128 on d->op0 and d->op1. */
39437 /* And dsecond is some single insn shuffle, taking
39438 d->op0 and result of vperm2f128 (if perm < 16) or
39439 d->op1 and result of vperm2f128 (otherwise). */
39448 }
39450 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
39453 }
39456 }
39458 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39459 a two vector permutation using 2 intra-lane interleave insns
39460 and cross-lane shuffle for 32-byte vectors. */
39462 static bool
39464 {
39471 ;
39473 ;
39474 else
39489 {
39493 else
39499 else
39505 else
39511 else
39517 else
39523 else
39528 }
39532 }
39534 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
39535 a single vector permutation using a single intra-lane vector
39536 permutation, vperm2f128 swapping the lanes and vblend* insn blending
39537 the non-swapped and swapped vectors together. */
39539 static bool
39541 {
39544 rtx seq;
39549 || TARGET_AVX2
39558 {
39565 }
39600 }
39602 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
39603 permutation using two vperm2f128, followed by a vshufpd insn blending
39604 the two vectors together. */
39606 static bool
39608 {
39651 }
39653 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
39654 permutation with two pshufb insns and an ior. We should have already
39655 failed all two instruction sequences. */
39657 static bool
39659 {
39670 /* Generate two permutation masks. If the required element is within
39671 the given vector it is shuffled into the proper lane. If the required
39672 element is in the other vector, force a zero into the lane by setting
39673 bit 7 in the permutation mask. */
39676 {
39683 {
39686 }
39687 }
39707 }
39709 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
39710 with two vpshufb insns, vpermq and vpor. We should have already failed
39711 all two or three instruction sequences. */
39713 static bool
39715 {
39730 /* Generate two permutation masks. If the required element is within
39731 the same lane, it is shuffled in. If the required element from the
39732 other lane, force a zero by setting bit 7 in the permutation mask.
39733 In the other mask the mask has non-negative elements if element
39734 is requested from the other lane, but also moved to the other lane,
39735 so that the result of vpshufb can have the two V2TImode halves
39736 swapped. */
39739 {
39744 {
39747 }
39748 }
39757 /* Swap the 128-byte lanes of h into hp. */
39761 const1_rtx));
39774 }
39776 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
39777 and extract-odd permutations of two V32QImode and V16QImode operand
39778 with two vpshufb insns, vpor and vpermq. We should have already
39779 failed all two or three instruction sequences. */
39781 static bool
39783 {
39802 /* Generate two permutation masks. In the first permutation mask
39803 the first quarter will contain indexes for the first half
39804 of the op0, the second quarter will contain bit 7 set, third quarter
39805 will contain indexes for the second half of the op0 and the
39806 last quarter bit 7 set. In the second permutation mask
39807 the first quarter will contain bit 7 set, the second quarter
39808 indexes for the first half of the op1, the third quarter bit 7 set
39809 and last quarter indexes for the second half of the op1.
39810 I.e. the first mask e.g. for V32QImode extract even will be:
39811 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
39812 (all values masked with 0xf except for -128) and second mask
39813 for extract even will be
39814 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
39817 {
39823 {
39826 }
39827 }
39846 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
39853 }
39855 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
39856 and extract-odd permutations. */
39858 static bool
39860 {
39864 {
39869 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39873 /* Now an unpck[lh]pd will produce the result required. */
39876 else
39882 {
39889 /* Shuffle within the 128-bit lanes to produce:
39890 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
39894 /* Shuffle the lanes around to produce:
39895 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
39899 /* Shuffle within the 128-bit lanes to produce:
39900 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
39903 /* Shuffle within the 128-bit lanes to produce:
39904 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
39907 /* Shuffle the lanes around to produce:
39908 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
39911 }
39918 /* These are always directly implementable by expand_vec_perm_1. */
39924 else
39925 {
39926 /* We need 2*log2(N)-1 operations to achieve odd/even
39927 with interleave. */
39936 else
39939 }
39945 else
39946 {
39958 else
39961 }
39970 {
39977 }
39982 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39986 /* Now an vpunpck[lh]qdq will produce the result required. */
39989 else
39996 {
40003 }
40008 /* Shuffle the lanes around into
40009 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40019 /* Swap the 2nd and 3rd position in each lane into
40020 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40026 /* Now an vpunpck[lh]qdq will produce
40027 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40032 else
40041 }
40044 }
40046 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40047 extract-even and extract-odd permutations. */
40049 static bool
40051 {
40063 }
40065 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40066 permutations. We assume that expand_vec_perm_1 has already failed. */
40068 static bool
40070 {
40078 {
40081 /* These are special-cased in sse.md so that we can optionally
40082 use the vbroadcast instruction. They expand to two insns
40083 if the input happens to be in a register. */
40090 /* These are always implementable using standard shuffle patterns. */
40095 /* These can be implemented via interleave. We save one insn by
40096 stopping once we have promoted to V4SImode and then use pshufd. */
40097 do
40098 {
40099 rtx dest;
40105 {
40109 }
40116 }
40129 /* For AVX2 broadcasts of the first element vpbroadcast* or
40130 vpermq should be used by expand_vec_perm_1. */
40136 }
40137 }
40139 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40140 broadcast permutations. */
40142 static bool
40144 {
40156 }
40158 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40159 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40160 all the shorter instruction sequences. */
40162 static bool
40164 {
40180 /* Generate 4 permutation masks. If the required element is within
40181 the same lane, it is shuffled in. If the required element from the
40182 other lane, force a zero by setting bit 7 in the permutation mask.
40183 In the other mask the mask has non-negative elements if element
40184 is requested from the other lane, but also moved to the other lane,
40185 so that the result of vpshufb can have the two V2TImode halves
40186 swapped. */
40189 {
40194 }
40200 {
40208 }
40211 {
40213 {
40216 }
40223 }
40225 /* Swap the 128-byte lanes of h[X]. */
40227 {
40233 const1_rtx));
40235 }
40238 {
40240 {
40243 }
40249 }
40252 {
40254 {
40258 }
40261 }
40267 }
40269 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40270 With all of the interface bits taken care of, perform the expansion
40271 in D and return true on success. */
40273 static bool
40275 {
40276 /* Try a single instruction expansion. */
40280 /* Try sequences of two instructions. */
40300 /* Try sequences of three instructions. */
40314 /* Try sequences of four instructions. */
40322 /* ??? Look for narrow permutations whose element orderings would
40323 allow the promotion to a wider mode. */
40325 /* ??? Look for sequences of interleave or a wider permute that place
40326 the data into the correct lanes for a half-vector shuffle like
40327 pshuf[lh]w or vpermilps. */
40329 /* ??? Look for sequences of interleave that produce the desired results.
40330 The combinatorics of punpck[lh] get pretty ugly... */
40335 /* Even longer sequences. */
40340 }
40342 /* If a permutation only uses one operand, make it clear. Returns true
40343 if the permutation references both operands. */
40345 static bool
40347 {
40355 {
40361 {
40364 }
40365 /* The elements of PERM do not suggest that only the first operand
40366 is used, but both operands are identical. Allow easier matching
40367 of the permutation by folding the permutation into the single
40368 input vector. */
40369 /* FALLTHRU */
40380 }
40383 }
40385 bool
40387 {
40392 rtx sel;
40409 {
40414 }
40421 /* If the selector says both arguments are needed, but the operands are the
40422 same, the above tried to expand with one_operand_p and flattened selector.
40423 If that didn't work, retry without one_operand_p; we succeeded with that
40424 during testing. */
40426 {
40430 }
40433 }
40435 /* Implement targetm.vectorize.vec_perm_const_ok. */
40437 static bool
40440 {
40449 /* Given sufficient ISA support we can just return true here
40450 for selected vector modes. */
40452 {
40453 /* All implementable with a single vpperm insn. */
40456 /* All implementable with 2 pshufb + 1 ior. */
40459 /* All implementable with shufpd or unpck[lh]pd. */
40462 }
40464 /* Extract the values from the vector CST into the permutation
40465 array in D. */
40468 {
40472 }
40474 /* For all elements from second vector, fold the elements to first. */
40479 /* Check whether the mask can be applied to the vector type. */
40482 /* Implementable with shufps or pshufd. */
40486 /* Otherwise we have to go through the motions and see if we can
40487 figure out how to generate the requested permutation. */
40498 }
40500 void
40502 {
40517 /* We'll either be able to implement the permutation directly... */
40521 /* ... or we use the special-case patterns. */
40523 }
40525 static void
40527 {
40542 {
40545 }
40547 /* Note that for AVX this isn't one instruction. */
40550 }
40553 /* Expand a vector operation CODE for a V*QImode in terms of the
40554 same operation on V*HImode. */
40556 void
40558 {
40570 {
40583 }
40587 {
40589 /* Unpack data such that we've got a source byte in each low byte of
40590 each word. We don't care what goes into the high byte of each word.
40591 Rather than trying to get zero in there, most convenient is to let
40592 it be a copy of the low byte. */
40597 /* FALLTHRU */
40609 /* FALLTHRU */
40619 }
40621 /* Perform the operation. */
40628 /* Merge the data back into the right place. */
40638 {
40639 /* For SSE2, we used an full interleave, so the desired
40640 results are in the even elements. */
40643 }
40644 else
40645 {
40646 /* For AVX, the interleave used above was not cross-lane. So the
40647 extraction is evens but with the second and third quarter swapped.
40648 Happily, that is even one insn shorter than even extraction. */
40651 }
40658 }
40660 void
40663 {
40666 rtx x;
40668 /* We only play even/odd games with vectors of SImode. */
40671 /* If we're looking for the odd results, shift those members down to
40672 the even slots. For some cpus this is faster than a PSHUFD. */
40674 {
40676 {
40680 }
40689 }
40692 {
40695 else
40697 }
40702 else
40703 {
40706 /* The easiest way to implement this without PMULDQ is to go through
40707 the motions as if we are performing a full 64-bit multiply. With
40708 the exception that we need to do less shuffling of the elements. */
40710 /* Compute the sign-extension, aka highparts, of the two operands. */
40716 /* Multiply LO(A) * HI(B), and vice-versa. */
40722 /* Multiply LO(A) * LO(B). */
40726 /* Combine and shift the highparts into place. */
40731 /* Combine high and low parts. */
40734 }
40736 }
40738 void
40741 {
40747 {
40752 {
40753 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
40754 shuffle the elements once so that all elements are in the right
40755 place for immediate use: { A C B D }. */
40760 }
40761 else
40762 {
40763 /* Put the elements into place for the multiply. */
40767 }
40772 /* Shuffle the elements between the lanes. After this we
40773 have { A B E F | C D G H } for each operand. */
40783 /* Shuffle the elements within the lanes. After this we
40784 have { A A B B | C C D D } or { E E F F | G G H H }. */
40820 }
40821 }
40823 void
40825 {
40835 /* Move the results in element 2 down to element 1; we don't care
40836 what goes in elements 2 and 3. Then we can merge the parts
40837 back together with an interleave.
40839 Note that two other sequences were tried:
40840 (1) Use interleaves at the start instead of psrldq, which allows
40841 us to use a single shufps to merge things back at the end.
40842 (2) Use shufps here to combine the two vectors, then pshufd to
40843 put the elements in the correct order.
40844 In both cases the cost of the reformatting stall was too high
40845 and the overall sequence slower. */
40854 }
40856 void
40858 {
40863 {
40864 /* op1: A,B,C,D, op2: E,F,G,H */
40873 /* t1: B,A,D,C */
40880 /* t2: (B*E),(A*F),(D*G),(C*H) */
40883 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
40886 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
40889 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
40891 }
40892 else
40893 {
40898 {
40901 }
40903 {
40906 }
40907 else
40911 /* Multiply low parts. */
40915 /* Shift input vectors right 32 bits so we can multiply high parts. */
40920 /* Multiply high parts by low parts. */
40926 /* Combine and shift the highparts back. */
40930 /* Combine high and low parts. */
40932 }
40936 }
40938 /* Expand an insert into a vector register through pinsr insn.
40939 Return true if successful. */
40941 bool
40943 {
40951 {
40954 }
40960 {
40965 {
40972 {
41004 }
41013 }
41017 }
41018 }
41019 \f
41020 /* This function returns the calling abi specific va_list type node.
41021 It returns the FNDECL specific va_list type. */
41023 static tree
41025 {
41032 else
41034 }
41036 /* Returns the canonical va_list type specified by TYPE. If there
41037 is no valid TYPE provided, it return NULL_TREE. */
41039 static tree
41041 {
41044 /* Resolve references and pointers to va_list type. */
41053 {
41058 {
41059 /* If va_list is an array type, the argument may have decayed
41060 to a pointer type, e.g. by being passed to another function.
41061 In that case, unwrap both types so that we can compare the
41062 underlying records. */
41065 {
41068 }
41069 }
41076 {
41077 /* If va_list is an array type, the argument may have decayed
41078 to a pointer type, e.g. by being passed to another function.
41079 In that case, unwrap both types so that we can compare the
41080 underlying records. */
41083 {
41086 }
41087 }
41094 {
41095 /* If va_list is an array type, the argument may have decayed
41096 to a pointer type, e.g. by being passed to another function.
41097 In that case, unwrap both types so that we can compare the
41098 underlying records. */
41101 {
41104 }
41105 }
41109 }
41111 }
41113 /* Iterate through the target-specific builtin types for va_list.
41114 IDX denotes the iterator, *PTREE is set to the result type of
41115 the va_list builtin, and *PNAME to its internal type.
41116 Returns zero if there is no element for this index, otherwise
41117 IDX should be increased upon the next call.
41118 Note, do not iterate a base builtin's name like __builtin_va_list.
41119 Used from c_common_nodes_and_builtins. */
41121 static int
41123 {
41125 {
41127 {
41140 }
41141 }
41144 }
41146 #undef TARGET_SCHED_DISPATCH
41147 #define TARGET_SCHED_DISPATCH has_dispatch
41148 #undef TARGET_SCHED_DISPATCH_DO
41149 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41150 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41151 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41152 #undef TARGET_SCHED_REORDER
41153 #define TARGET_SCHED_REORDER ix86_sched_reorder
41154 #undef TARGET_SCHED_ADJUST_PRIORITY
41155 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41156 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41157 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ix86_dependencies_evaluation_hook
41159 /* The size of the dispatch window is the total number of bytes of
41160 object code allowed in a window. */
41161 #define DISPATCH_WINDOW_SIZE 16
41163 /* Number of dispatch windows considered for scheduling. */
41164 #define MAX_DISPATCH_WINDOWS 3
41166 /* Maximum number of instructions in a window. */
41167 #define MAX_INSN 4
41169 /* Maximum number of immediate operands in a window. */
41170 #define MAX_IMM 4
41172 /* Maximum number of immediate bits allowed in a window. */
41173 #define MAX_IMM_SIZE 128
41175 /* Maximum number of 32 bit immediates allowed in a window. */
41176 #define MAX_IMM_32 4
41178 /* Maximum number of 64 bit immediates allowed in a window. */
41179 #define MAX_IMM_64 2
41181 /* Maximum total of loads or prefetches allowed in a window. */
41182 #define MAX_LOAD 2
41184 /* Maximum total of stores allowed in a window. */
41185 #define MAX_STORE 1
41187 #undef BIG
41188 #define BIG 100
41191 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41194 disp_load,
41195 disp_store,
41196 disp_load_store,
41197 disp_prefetch,
41198 disp_imm,
41199 disp_imm_32,
41200 disp_imm_64,
41201 disp_branch,
41202 disp_cmp,
41203 disp_jcc,
41204 disp_last
41205 };
41207 /* Number of allowable groups in a dispatch window. It is an array
41208 indexed by dispatch_group enum. 100 is used as a big number,
41209 because the number of these kind of operations does not have any
41210 effect in dispatch window, but we need them for other reasons in
41211 the table. */
41214 };
41220 };
41222 /* Instruction path. */
41228 last_path
41229 };
41231 /* sched_insn_info defines a window to the instructions scheduled in
41232 the basic block. It contains a pointer to the insn_info table and
41233 the instruction scheduled.
41235 Windows are allocated for each basic block and are linked
41236 together. */
41238 rtx insn;
41245 /* Linked list of dispatch windows. This is a two way list of
41246 dispatch windows of a basic block. It contains information about
41247 the number of uops in the window and the total number of
41248 instructions and of bytes in the object code for this dispatch
41249 window. */
41267 /* Immediate valuse used in an insn. */
41269 {
41278 /* Get dispatch group of insn. */
41280 static enum dispatch_group
41282 {
41298 }
41300 /* Return true if insn is a compare instruction. */
41302 static bool
41304 {
41312 }
41314 /* Return true if a dispatch violation encountered. */
41316 static bool
41318 {
41322 }
41324 /* Return true if insn is a branch instruction. */
41326 static bool
41328 {
41330 }
41332 /* Return true if insn is a prefetch instruction. */
41334 static bool
41336 {
41338 }
41340 /* This function initializes a dispatch window and the list container holding a
41341 pointer to the window. */
41343 static void
41345 {
41351 else
41369 {
41375 }
41377 }
41379 /* This function allocates and initializes a dispatch window and the
41380 list container holding a pointer to the window. */
41384 {
41389 }
41391 /* This routine initializes the dispatch scheduling information. It
41392 initiates building dispatch scheduler tables and constructs the
41393 first dispatch window. */
41395 static void
41397 {
41398 /* Allocate a dispatch list and a window. */
41403 }
41405 /* This function returns true if a branch is detected. End of a basic block
41406 does not have to be a branch, but here we assume only branches end a
41407 window. */
41409 static bool
41411 {
41413 }
41415 /* This function is called when the end of a window processing is reached. */
41417 static void
41419 {
41422 {
41427 }
41429 }
41431 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
41432 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
41433 for 48 bytes of instructions. Note that these windows are not dispatch
41434 windows that their sizes are DISPATCH_WINDOW_SIZE. */
41438 {
41440 {
41445 }
41451 }
41453 /* Increment the number of immediate operands of an instruction. */
41455 static int
41457 {
41462 {
41469 else
41480 {
41483 }
41488 }
41491 }
41493 /* Compute number of immediate operands of an instruction. */
41495 static void
41497 {
41500 }
41502 /* Return total size of immediate operands of an instruction along with number
41503 of corresponding immediate-operands. It initializes its parameters to zero
41504 befor calling FIND_CONSTANT.
41505 INSN is the input instruction. IMM is the total of immediates.
41506 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
41507 bit immediates. */
41509 static int
41511 {
41519 }
41521 /* This function indicates if an operand of an instruction is an
41522 immediate. */
41524 static bool
41526 {
41535 }
41537 /* Return single or double path for instructions. */
41539 static enum insn_path
41541 {
41551 }
41553 /* Return insn dispatch group. */
41555 static enum dispatch_group
41557 {
41575 }
41577 /* Count number of GROUP restricted instructions in a dispatch
41578 window WINDOW_LIST. */
41580 static int
41582 {
41593 {
41612 }
41625 }
41627 /* This function returns true if insn satisfies dispatch rules on the
41628 last window scheduled. */
41630 static bool
41632 {
41640 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
41641 instructions should be given the lowest priority in the
41642 scheduling process in Haifa scheduler to make sure they will be
41643 scheduled in the same dispatch window as the reference to them. */
41647 /* Check nonrestricted. */
41651 /* Get last dispatch window. */
41656 {
41661 /* Window 1 is full. Go for next window. */
41663 }
41670 /* See if it fits in the first window. */
41672 {
41673 /* The first widow should have only single and double path
41674 uops. */
41680 }
41682 }
41684 /* Add an instruction INSN with NUM_UOPS micro-operations to the
41685 dispatch window WINDOW_LIST. */
41687 static void
41689 {
41707 /* Initialize window with new instruction. */
41728 {
41731 }
41732 }
41734 /* Adds a scheduled instruction, INSN, to the current dispatch window.
41735 If the total bytes of instructions or the number of instructions in
41736 the window exceed allowable, it allocates a new window. */
41738 static void
41740 {
41763 /* Get the last dispatch window. */
41771 else
41774 /* If current window is full, get a new window.
41775 Window number zero is full, if MAX_INSN uops are scheduled in it.
41776 Window number one is full, if window zero's bytes plus window
41777 one's bytes is 32, or if the bytes of the new instruction added
41778 to the total makes it greater than 48, or it has already MAX_INSN
41779 instructions in it. */
41788 {
41791 }
41794 {
41798 {
41801 }
41802 }
41804 {
41809 {
41812 }
41815 }
41816 else
41820 {
41821 /* End of basic block is reached do end-basic-block process. */
41824 }
41825 }
41827 /* Print the dispatch window, WINDOW_NUM, to FILE. */
41829 DEBUG_FUNCTION static void
41831 {
41837 else
41851 {
41854 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
41860 }
41861 }
41863 /* Print to stdout a dispatch window. */
41865 DEBUG_FUNCTION void
41867 {
41869 }
41871 /* Print INSN dispatch information to FILE. */
41873 DEBUG_FUNCTION static void
41875 {
41898 }
41900 /* Print to STDERR the status of the ready list with respect to
41901 dispatch windows. */
41903 DEBUG_FUNCTION void
41905 {
41913 }
41915 /* This routine is the driver of the dispatch scheduler. */
41917 static void
41919 {
41924 }
41926 /* Return TRUE if Dispatch Scheduling is supported. */
41928 static bool
41930 {
41934 {
41950 }
41953 }
41955 /* Implementation of reassociation_width target hook used by
41956 reassoc phase to identify parallelism level in reassociated
41957 tree. Statements tree_code is passed in OPC. Arguments type
41958 is passed in MODE.
41960 Currently parallel reassociation is enabled for Atom
41961 processors only and we set reassociation width to be 2
41962 because Atom may issue up to 2 instructions per cycle.
41964 Return value should be fixed if parallel reassociation is
41965 enabled for other processors. */
41967 static int
41970 {
41979 }
41981 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
41982 place emms and femms instructions. */
41984 static enum machine_mode
41986 {
41991 {
42004 else
42014 /* FALLTHRU */
42018 }
42019 }
42021 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42022 vectors. */
42024 static unsigned int
42026 {
42028 }
42030 \f
42032 /* Return class of registers which could be used for pseudo of MODE
42033 and of class RCLASS for spilling instead of memory. Return NO_REGS
42034 if it is not possible or non-profitable. */
42035 static reg_class_t
42037 {
42044 }
42046 /* Implement targetm.vectorize.init_cost. */
42050 {
42054 }
42056 /* Implement targetm.vectorize.add_stmt_cost. */
42058 static unsigned
42062 {
42067 {
42071 /* Statements in an inner loop relative to the loop being
42072 vectorized are weighted more heavily. The value here is
42073 arbitrary and could potentially be improved with analysis. */
42079 }
42082 }
42084 /* Implement targetm.vectorize.finish_cost. */
42086 static void
42089 {
42094 }
42096 /* Implement targetm.vectorize.destroy_cost_data. */
42098 static void
42100 {
42102 }
42104 /* Validate target specific memory model bits in VAL. */
42106 static unsigned HOST_WIDE_INT
42108 {
42115 {
42119 }
42122 {
42126 }
42128 {
42132 }
42134 }
42136 /* Initialize the GCC target structure. */
42137 #undef TARGET_RETURN_IN_MEMORY
42138 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42140 #undef TARGET_LEGITIMIZE_ADDRESS
42141 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42143 #undef TARGET_ATTRIBUTE_TABLE
42144 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42145 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42146 # undef TARGET_MERGE_DECL_ATTRIBUTES
42147 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42148 #endif
42150 #undef TARGET_COMP_TYPE_ATTRIBUTES
42151 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42153 #undef TARGET_INIT_BUILTINS
42154 #define TARGET_INIT_BUILTINS ix86_init_builtins
42155 #undef TARGET_BUILTIN_DECL
42156 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42157 #undef TARGET_EXPAND_BUILTIN
42158 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42160 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42161 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42162 ix86_builtin_vectorized_function
42164 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42165 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42167 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42168 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42170 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42171 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42173 #undef TARGET_BUILTIN_RECIPROCAL
42174 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42176 #undef TARGET_ASM_FUNCTION_EPILOGUE
42177 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42179 #undef TARGET_ENCODE_SECTION_INFO
42180 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42181 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42182 #else
42183 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42184 #endif
42186 #undef TARGET_ASM_OPEN_PAREN
42188 #undef TARGET_ASM_CLOSE_PAREN
42191 #undef TARGET_ASM_BYTE_OP
42192 #define TARGET_ASM_BYTE_OP ASM_BYTE
42194 #undef TARGET_ASM_ALIGNED_HI_OP
42195 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42196 #undef TARGET_ASM_ALIGNED_SI_OP
42197 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42198 #ifdef ASM_QUAD
42199 #undef TARGET_ASM_ALIGNED_DI_OP
42200 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42201 #endif
42203 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42204 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42206 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42207 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42209 #undef TARGET_ASM_UNALIGNED_HI_OP
42210 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42211 #undef TARGET_ASM_UNALIGNED_SI_OP
42212 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42213 #undef TARGET_ASM_UNALIGNED_DI_OP
42214 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42216 #undef TARGET_PRINT_OPERAND
42217 #define TARGET_PRINT_OPERAND ix86_print_operand
42218 #undef TARGET_PRINT_OPERAND_ADDRESS
42219 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42220 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42221 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42222 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42223 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42225 #undef TARGET_SCHED_INIT_GLOBAL
42226 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42227 #undef TARGET_SCHED_ADJUST_COST
42228 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42229 #undef TARGET_SCHED_ISSUE_RATE
42230 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42231 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42232 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42233 ia32_multipass_dfa_lookahead
42235 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42236 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42238 #undef TARGET_MEMMODEL_CHECK
42239 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42241 #ifdef HAVE_AS_TLS
42242 #undef TARGET_HAVE_TLS
42243 #define TARGET_HAVE_TLS true
42244 #endif
42245 #undef TARGET_CANNOT_FORCE_CONST_MEM
42246 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42247 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42248 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42250 #undef TARGET_DELEGITIMIZE_ADDRESS
42251 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42253 #undef TARGET_MS_BITFIELD_LAYOUT_P
42254 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42256 #if TARGET_MACHO
42257 #undef TARGET_BINDS_LOCAL_P
42258 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42259 #endif
42260 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42261 #undef TARGET_BINDS_LOCAL_P
42262 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42263 #endif
42265 #undef TARGET_ASM_OUTPUT_MI_THUNK
42266 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42267 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42268 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42270 #undef TARGET_ASM_FILE_START
42271 #define TARGET_ASM_FILE_START x86_file_start
42273 #undef TARGET_OPTION_OVERRIDE
42274 #define TARGET_OPTION_OVERRIDE ix86_option_override
42276 #undef TARGET_REGISTER_MOVE_COST
42277 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42278 #undef TARGET_MEMORY_MOVE_COST
42279 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42280 #undef TARGET_RTX_COSTS
42281 #define TARGET_RTX_COSTS ix86_rtx_costs
42282 #undef TARGET_ADDRESS_COST
42283 #define TARGET_ADDRESS_COST ix86_address_cost
42285 #undef TARGET_FIXED_CONDITION_CODE_REGS
42286 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42287 #undef TARGET_CC_MODES_COMPATIBLE
42288 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42290 #undef TARGET_MACHINE_DEPENDENT_REORG
42291 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42293 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42294 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42296 #undef TARGET_BUILD_BUILTIN_VA_LIST
42297 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42299 #undef TARGET_FOLD_BUILTIN
42300 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42302 #undef TARGET_COMPARE_VERSION_PRIORITY
42303 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42305 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42306 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42307 ix86_generate_version_dispatcher_body
42309 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42310 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42311 ix86_get_function_versions_dispatcher
42313 #undef TARGET_ENUM_VA_LIST_P
42314 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42316 #undef TARGET_FN_ABI_VA_LIST
42317 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42319 #undef TARGET_CANONICAL_VA_LIST_TYPE
42320 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42322 #undef TARGET_EXPAND_BUILTIN_VA_START
42323 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42325 #undef TARGET_MD_ASM_CLOBBERS
42326 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
42328 #undef TARGET_PROMOTE_PROTOTYPES
42329 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
42330 #undef TARGET_STRUCT_VALUE_RTX
42331 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
42332 #undef TARGET_SETUP_INCOMING_VARARGS
42333 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
42334 #undef TARGET_MUST_PASS_IN_STACK
42335 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
42336 #undef TARGET_FUNCTION_ARG_ADVANCE
42337 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
42338 #undef TARGET_FUNCTION_ARG
42339 #define TARGET_FUNCTION_ARG ix86_function_arg
42340 #undef TARGET_FUNCTION_ARG_BOUNDARY
42341 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42342 #undef TARGET_PASS_BY_REFERENCE
42343 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42344 #undef TARGET_INTERNAL_ARG_POINTER
42345 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42346 #undef TARGET_UPDATE_STACK_BOUNDARY
42347 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42348 #undef TARGET_GET_DRAP_RTX
42349 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42350 #undef TARGET_STRICT_ARGUMENT_NAMING
42351 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42352 #undef TARGET_STATIC_CHAIN
42353 #define TARGET_STATIC_CHAIN ix86_static_chain
42354 #undef TARGET_TRAMPOLINE_INIT
42355 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42356 #undef TARGET_RETURN_POPS_ARGS
42357 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
42359 #undef TARGET_LEGITIMATE_COMBINED_INSN
42360 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
42362 #undef TARGET_ASAN_SHADOW_OFFSET
42363 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
42365 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
42366 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
42368 #undef TARGET_SCALAR_MODE_SUPPORTED_P
42369 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
42371 #undef TARGET_VECTOR_MODE_SUPPORTED_P
42372 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
42374 #undef TARGET_C_MODE_FOR_SUFFIX
42375 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
42377 #ifdef HAVE_AS_TLS
42378 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
42379 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
42380 #endif
42382 #ifdef SUBTARGET_INSERT_ATTRIBUTES
42383 #undef TARGET_INSERT_ATTRIBUTES
42384 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
42385 #endif
42387 #undef TARGET_MANGLE_TYPE
42388 #define TARGET_MANGLE_TYPE ix86_mangle_type
42390 #if !TARGET_MACHO
42391 #undef TARGET_STACK_PROTECT_FAIL
42392 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
42393 #endif
42395 #undef TARGET_FUNCTION_VALUE
42396 #define TARGET_FUNCTION_VALUE ix86_function_value
42398 #undef TARGET_FUNCTION_VALUE_REGNO_P
42399 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
42401 #undef TARGET_PROMOTE_FUNCTION_MODE
42402 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
42404 #undef TARGET_MEMBER_TYPE_FORCES_BLK
42405 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
42407 #undef TARGET_INSTANTIATE_DECLS
42408 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
42410 #undef TARGET_SECONDARY_RELOAD
42411 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
42413 #undef TARGET_CLASS_MAX_NREGS
42414 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
42416 #undef TARGET_PREFERRED_RELOAD_CLASS
42417 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
42418 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
42419 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
42420 #undef TARGET_CLASS_LIKELY_SPILLED_P
42421 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
42423 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
42424 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
42425 ix86_builtin_vectorization_cost
42426 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
42427 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
42428 ix86_vectorize_vec_perm_const_ok
42429 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
42430 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
42431 ix86_preferred_simd_mode
42432 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
42433 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
42434 ix86_autovectorize_vector_sizes
42435 #undef TARGET_VECTORIZE_INIT_COST
42436 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
42437 #undef TARGET_VECTORIZE_ADD_STMT_COST
42438 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
42439 #undef TARGET_VECTORIZE_FINISH_COST
42440 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
42441 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
42442 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
42444 #undef TARGET_SET_CURRENT_FUNCTION
42445 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
42447 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
42448 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
42450 #undef TARGET_OPTION_SAVE
42451 #define TARGET_OPTION_SAVE ix86_function_specific_save
42453 #undef TARGET_OPTION_RESTORE
42454 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
42456 #undef TARGET_OPTION_PRINT
42457 #define TARGET_OPTION_PRINT ix86_function_specific_print
42459 #undef TARGET_OPTION_FUNCTION_VERSIONS
42460 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
42462 #undef TARGET_CAN_INLINE_P
42463 #define TARGET_CAN_INLINE_P ix86_can_inline_p
42465 #undef TARGET_EXPAND_TO_RTL_HOOK
42466 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
42468 #undef TARGET_LEGITIMATE_ADDRESS_P
42469 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
42471 #undef TARGET_LRA_P
42472 #define TARGET_LRA_P hook_bool_void_true
42474 #undef TARGET_REGISTER_PRIORITY
42475 #define TARGET_REGISTER_PRIORITY ix86_register_priority
42477 #undef TARGET_LEGITIMATE_CONSTANT_P
42478 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
42480 #undef TARGET_FRAME_POINTER_REQUIRED
42481 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
42483 #undef TARGET_CAN_ELIMINATE
42484 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
42486 #undef TARGET_EXTRA_LIVE_ON_ENTRY
42487 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
42489 #undef TARGET_ASM_CODE_END
42490 #define TARGET_ASM_CODE_END ix86_code_end
42492 #undef TARGET_CONDITIONAL_REGISTER_USAGE
42493 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
42495 #if TARGET_MACHO
42496 #undef TARGET_INIT_LIBFUNCS
42497 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
42498 #endif
42500 #undef TARGET_SPILL_CLASS
42501 #define TARGET_SPILL_CLASS ix86_spill_class
42504 \f