| blob | fe6bb91f3e8a247ef02f639b24e5650ba27e18c5 |
1 2024-02-29 David Malcolm <dmalcolm@redhat.com>
3 PR analyzer/114159
4 * function.cc (function_name): Make param const.
5 * function.h (function_name): Likewise.
7 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
9 PR target/114100
10 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
11 * config/avr/avr.opt (-mfuse-add=): New target option.
12 * common/config/avr/avr-common.cc (avr_option_optimization_table)
13 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
14 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
15 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
16 * config/avr/avr-protos.h (avr_split_tiny_move)
17 (make_avr_pass_fuse_add): New protos.
18 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
19 avr_split_tiny_move to split indirect memory accesses.
20 (gen_move_clobbercc): New define_expand helper.
21 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
22 (avr_pass_fuse_add): New class from rtl_opt_pass.
23 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
24 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
25 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
26 of PLUS addressing for AVR_TINY.
27 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
28 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
29 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
31 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
33 PR target/114132
34 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
35 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
36 (avr_function_arg): Set it.
37 (avr_frame_pointer_required_p): Use it instead of .nregs.
39 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
41 PR target/108174
42 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
43 static and mark with GTY.
45 2024-02-29 Xi Ruoyao <xry111@xry111.site>
47 * config/loongarch/loongarch.md
48 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
50 2024-02-29 Xi Ruoyao <xry111@xry111.site>
52 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
53 (crc): New define_int_attr.
54 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
55 into ...
56 (loongarch_<crc>_w_<size>_w): ... here.
58 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
60 PR target/114130
61 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
62 extend the expected value if needed.
64 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
66 * config.gcc (target_gtfiles): Change coreout to btfext-out.
67 (extra_objs): Change coreout to btfext-out.
68 * config/bpf/coreout.cc: Rename to btfext-out.cc.
69 * config/bpf/btfext-out.cc: Add.
70 * config/bpf/coreout.h: Rename to btfext-out.h.
71 * config/bpf/btfext-out.h: Add.
72 * config/bpf/core-builtins.cc: Change include.
73 * config/bpf/core-builtins.h: Change include.
74 * config/bpf/t-bpf: Accomodate renamed files.
76 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
78 PR target/113453
79 * config/bpf/bpf.cc (bpf_function_prologue): Define target
80 hook.
81 * config/bpf/coreout.cc (brf_ext_info_section)
82 (btf_ext_info): Move from coreout.h
83 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
84 (bpf_core_reloc): Rename to btf_ext_core_reloc.
85 (btf_ext): Add static variable.
86 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
87 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
88 (btf_ext_add_string, btf_funcinfo_type_callback)
89 (btf_add_func_info_for, btf_validate_funcinfo)
90 (btf_ext_info_len, output_btfext_func_info): Add function.
91 (output_btfext_header, bpf_core_reloc_add)
92 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
93 Change to support new structs.
94 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
95 Move and change in coreout.cc.
96 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
98 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
100 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
101 enabled by default for BPF.
102 (bpf_file_end): Call BTF deallocation.
103 (bpf_asm_init_sections): Correct condition.
104 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
105 deallocation.
106 (ctf_debuf_finish): Correct condition for calling
107 ctf_debug_finalize.
109 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
111 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
112 (traverse_btf_func_types): Define function.
113 * ctfc.h (funcs_traverse_callback): Typedef for function
114 prototype.
115 (traverse_btf_func_types): Add prototype.
117 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
119 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
121 2024-02-28 Richard Biener <rguenther@suse.de>
123 PR tree-optimization/113831
124 PR tree-optimization/108355
125 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
126 PR113831 fix.
128 2024-02-28 Richard Biener <rguenther@suse.de>
130 PR tree-optimization/114121
131 * tree-ssa-sccvn.h (vn_reference_s::offset,
132 vn_reference_s::max_size): New fields.
133 (vn_reference_insert_pieces): Adjust prototype.
134 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
135 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
136 size, allow using "don't know" state.
137 (vn_walk_cb_data::finish): Pass along offset/max_size.
138 (vn_reference_lookup_or_insert_for_pieces): Take offset and
139 max_size as argument and use it.
140 (vn_reference_lookup_3): Properly adjust offset and max_size
141 according to the adjusted ao_ref.
142 (vn_reference_lookup_pieces): Initialize offset and max_size.
143 (vn_reference_lookup): Likewise.
144 (vn_reference_lookup_call): Likewise.
145 (vn_reference_insert): Likewise.
146 (visit_reference_op_call): Likewise.
147 (vn_reference_insert_pieces): Take offset and max_size
148 as argument and use it.
150 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
152 PR tree-optimization/114075
153 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
154 point vectors
156 2024-02-28 Jakub Jelinek <jakub@redhat.com>
158 PR tree-optimization/114041
159 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
160 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
162 2024-02-28 Jakub Jelinek <jakub@redhat.com>
164 PR tree-optimization/113988
165 * stor-layout.h (bitwise_mode_for_size): Declare.
166 * stor-layout.cc (bitwise_mode_for_size): New function.
167 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
168 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
169 Use BITS_PER_UNIT instead of 8.
171 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
173 PR target/113871
174 * config/i386/mmx.md (V248FI): Add V2BF mode.
175 (V24FI_32): Ditto.
177 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
179 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
180 if either ref->offset is not byte aligned or ref->size is not known
181 to be equal to ref->max_size.
182 (maybe_trim_complex_store): Fix description.
183 (maybe_trim_constructor_store): Likewise.
184 (maybe_trim_partially_dead_store): Likewise.
186 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
188 * config/arm/mmintrin.h: Warn if this header is included without
189 defining __ENABLE_DEPRECATED_IWMMXT.
191 2024-02-27 Richard Biener <rguenther@suse.de>
193 PR tree-optimization/114074
194 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
195 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
196 Handle poly vs. non-poly multiplication correctly with respect
197 to undefined behavior on overflow.
199 2024-02-27 Jakub Jelinek <jakub@redhat.com>
201 PR rtl-optimization/114044
202 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
203 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
204 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
205 expand_PARITY): Declare.
206 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
207 expand_CTZ, expand_FFS, expand_PARITY): New functions.
208 (expand_POPCOUNT): Use expand_bitquery.
210 2024-02-27 Richard Biener <rguenther@suse.de>
212 PR tree-optimization/114081
213 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
214 Perform manual dominator update for prologue peeling.
215 (vect_do_peeling): Properly update dominators after adding the
216 prologue-around guard.
218 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
220 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
221 (mstrict-X): Tag as "Optimization".
223 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
225 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
226 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
228 2024-02-26 Jakub Jelinek <jakub@redhat.com>
229 H.J. Lu <hjl.tools@gmail.com>
231 PR rtl-optimization/113617
232 * varasm.cc (default_elf_select_rtx_section): For
233 references to private symbols in comdat sections
234 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
235 or .rodata.<comdat> comdat sections.
237 2024-02-26 Richard Biener <rguenther@suse.de>
239 PR tree-optimization/114099
240 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
241 Create and fill in a needed virtual LC PHI for the alternate
242 exits. Remove code dealing with that missing.
244 2024-02-26 Richard Biener <rguenther@suse.de>
246 PR tree-optimization/114068
247 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
248 New function.
249 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
250 on the main exit if needed. Remove band-aid for the case
251 it was missing.
253 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
255 PR target/114097
256 * config/i386/i386-options.cc (ix86_set_func_type): Check
257 interrupt instead of noreturn attribute.
259 2024-02-26 Jakub Jelinek <jakub@redhat.com>
261 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
262 !TARGET_64BIT.
264 2024-02-26 Jakub Jelinek <jakub@redhat.com>
266 PR tree-optimization/114090
267 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
268 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
269 types.
270 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
272 2024-02-26 Jakub Jelinek <jakub@redhat.com>
274 PR middle-end/114084
275 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
276 if all subtrees of var0 come from one of the op0 or op1 operands
277 and all subtrees of con0 come from the other one. Don't clear
278 variables which are never used afterwards.
280 2024-02-26 Richard Biener <rguenther@suse.de>
282 PR middle-end/114070
283 * genmatch.cc (parser::parse_c_expr): Do not record operand
284 lists but only mark operators used.
285 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
286 Properly guard the case of tcc_comparison changing the VEC_COND
287 value operand type.
289 2024-02-26 Jakub Jelinek <jakub@redhat.com>
291 PR target/114094
292 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
293 to printed instruction.
295 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
297 PR target/114098
298 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
299 __builtin_ia32_ldtilecfg.
300 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
301 * config/i386/i386-builtin.def (BDESC): Add
302 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
303 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
304 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
305 * config/i386/i386.md (ldtilecfg): New pattern.
306 (sttilecfg): Likewise.
308 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
310 PR tree-optimization/113205
311 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
312 the proposed layout if it does not allow a source partition with
313 layout 2 to keep that layout.
315 2024-02-24 Jakub Jelinek <jakub@redhat.com>
317 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
318 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
319 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
320 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
321 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
322 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
323 macros.
324 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
325 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
326 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
327 HOST_WIDE_INT_UC macros.
328 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
329 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
330 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
331 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
332 macros.
333 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
334 * config/i386/constraints.md (define_constraint "L"): Use
335 HOST_WIDE_INT_C macro.
336 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
337 macro.
338 (movl + movb peephole2): Likewise.
339 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
340 (const_32bit_mask): Likewise.
342 2024-02-24 Jakub Jelinek <jakub@redhat.com>
344 PR middle-end/114073
345 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
346 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
347 types like vector or complex types.
348 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
349 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
350 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
352 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
354 PR target/114028
355 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
356 Return false if inner mode is already Pmode.
357 (rvv_builder::is_all_same_sequence): New function.
358 (expand_vec_init): Emit broadcast if sequence is all same.
360 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
362 PR target/113613
363 * config/aarch64/aarch64-early-ra.cc
364 (early_ra::m_current_region): New member variable.
365 (early_ra::m_fpr_recency): Likewise.
366 (early_ra::start_new_region): Bump m_current_region.
367 (early_ra::allocate_colors): Prefer less recently used registers
368 in the event of a tie. Add a comment to explain why we prefer(ed)
369 higher-numbered registers.
370 (early_ra::find_oldest_color): Prefer less recently used registers
371 here too.
372 (early_ra::finalize_allocation): Update recency information for
373 allocated registers.
374 (early_ra::process_blocks): Initialize m_current_region and
375 m_fpr_recency.
377 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
379 PR target/113295
380 * config/aarch64/aarch64-early-ra.cc
381 (early_ra::test_strictness): New enum.
382 (early_ra::is_chain_candidate): Add a strictness parameter to
383 control whether only correctness matters, or whether both correctness
384 and heuristics should be used. Handle multiple levels of equivalence.
385 (early_ra::find_related_start): Update call accordingly.
386 (early_ra::strided_polarity_pref): Likewise.
387 (early_ra::form_chains): Likewise.
388 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
389 correctness mode rather than trying to inline the test.
391 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
393 PR target/113295
394 * config/aarch64/aarch64-early-ra.cc
395 (early_ra::find_related_start): Account for definitions by shared
396 registers when testing for a single register definition.
397 (early_ra::accumulate_defs): New function.
398 (early_ra::record_copy): If A shares B's register, fold A's
399 definition information into B's. Fold A's use information into B's.
401 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
403 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
404 if R_X86_64_CODE_6_GOTTPOFF is supported.
405 * config.in: Regenerated.
406 * configure: Likewise.
407 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
408 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
410 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
412 PR target/108120
413 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
414 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
416 2024-02-23 Jakub Jelinek <jakub@redhat.com>
418 PR rtl-optimization/114054
419 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
420 temp variable instead of target parameter for result.
422 2024-02-23 Jakub Jelinek <jakub@redhat.com>
424 PR tree-optimization/114040
425 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
426 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
427 probability from likely to unlikely. When handling the true true
428 store, first cast to limb_access_type and then to l's type.
430 2024-02-23 Richard Biener <rguenther@suse.de>
432 PR target/90785
433 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
435 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
437 PR other/109668
438 * config/riscv/arch-canonicalize: Move to python3
439 * config/riscv/multilib-generator: Likewise
441 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
443 * doc/invoke.texi: Document -mcpu.
445 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
447 * configure: Regenerate.
448 * configure.ac: Add parameter "--fatal-warnings" to assemble
449 when checking whether the assemble support conditional branch
450 relaxation.
452 2024-02-22 Jakub Jelinek <jakub@redhat.com>
454 PR c/114007
455 * doc/extend.texi: (__extension__): Remove comments about scope
456 tokens vs. two colons.
458 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
460 PR tree-optimization/109804
461 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
462 DEMANGLE_COMPONENT_UNNAMED_TYPE.
464 2024-02-22 Richard Biener <rguenther@suse.de>
466 PR tree-optimization/114048
467 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
468 can also produce -1 off.
470 2024-02-22 Richard Biener <rguenther@suse.de>
472 PR tree-optimization/114027
473 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
474 condition reduction classification only for single-element
475 chains.
477 2024-02-22 Jakub Jelinek <jakub@redhat.com>
479 PR ipa/111960
480 * profile-count.h (profile_count::dump): Remove overload with
481 char * first argument.
482 * profile-count.cc (profile_count::dump): Change overload with char *
483 first argument which uses sprintf into the overfload with FILE *
484 first argument and use fprintf instead. Remove overload which wrapped
485 it.
487 2024-02-22 Jakub Jelinek <jakub@redhat.com>
489 PR tree-optimization/113993
490 * tree-call-cdce.cc (get_no_error_domain): Handle
491 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
492 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
493 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
494 the as the F128 suffixed cases, otherwise as non-suffixed ones.
495 Handle BUILT_IN_{EXP,POW}10L for
496 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
497 as (-inf, 4932).
499 2024-02-22 Jakub Jelinek <jakub@redhat.com>
501 PR tree-optimization/114038
502 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
503 loop exit condition if end is divisible by limb_prec.
505 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
507 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
508 problem of mabi=, mno-flush-func, mexplicit-relocs;
509 add missing leading - of mbranch-cost option.
510 * config/mips/mips.opt.urls: Regenerate.
512 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
514 PR target/109987
515 * config/rs6000/constraints.md (we): Update internal doc without
516 referring to option -mpower9-vector.
517 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
518 special handlings.
519 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
520 OTHER_P8_VECTOR_MASKS): Merge to ...
521 (OTHER_VSX_VECTOR_MASKS): ... here.
522 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
523 some error message handlings and explicit option mask adjustments on
524 explicit option power{8,9}-vector conflicting with other options.
525 (rs6000_print_isa_options): Update comments.
526 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
527 related array items and handlings.
528 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
529 special handlings.
530 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
531 WarnRemoved.
532 * doc/extend.texi: Remove documentation referring to option
533 -mpower8-vector.
534 * doc/invoke.texi: Remove documentation for option
535 -mpower{8,9}-vector and adjust some documentation referring to them.
536 * doc/md.texi: Update documentation for constraint we.
537 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
539 2024-02-22 Pan Li <pan2.li@intel.com>
541 PR target/114017
542 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
543 the version to 0.12.
545 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
547 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
549 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
550 Robin Dapp <rdapp.gcc@gmail.com>
552 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
553 (generic_ooo_vec_load): Ditto
554 (generic_ooo_vec_store): Ditto
555 (generic_ooo_vec_loadstore_seg): Ditto
556 (generic_ooo_vec_alu): Ditto
557 (generic_ooo_vec_fcmp): Ditto
558 (generic_ooo_vec_imul): Ditto
559 (generic_ooo_vec_fadd): Ditto
560 (generic_ooo_vec_fmul): Ditto
561 (generic_ooo_crypto): Ditto
562 (generic_ooo_perm): Ditto
563 (generic_ooo_vec_reduction): Ditto
564 (generic_ooo_vec_ordered_reduction): Ditto
565 (generic_ooo_vec_idiv): Ditto
566 (generic_ooo_vec_float_divsqrt): Ditto
567 (generic_ooo_vec_mask): Ditto
568 (generic_ooo_vec_vesetvl): Ditto
569 (generic_ooo_vec_setrm): Ditto
570 (generic_ooo_vec_readlen): Ditto
571 * config/riscv/riscv.md: Include generic-vector-ooo
572 * config/riscv/generic-vector-ooo.md: New file. To here
574 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
576 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
577 (generic_ooo_branch): Ditto
578 * config/riscv/generic.md (generic_sfb_alu): Ditto
579 (generic_fmul_half): Ditto
580 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
581 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
582 (sifive_7_popcount): Ditto
583 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
584 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
585 * config/riscv/vector.md: Change rdfrm to fmove
586 * config/riscv/zc.md: Change pushpop to load/store
588 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
590 * doc/invoke.texi (Warning Options): Fix typos.
592 2024-02-21 David Faust <david.faust@oracle.com>
594 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
595 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
596 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
598 2024-02-21 Martin Jambor <mjambor@suse.cz>
600 PR ipa/113476
601 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
602 initializers in the contructor.
603 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
604 * ipa-cp.h: New file.
605 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
606 (ipcp_value_source): Move to ipa-cp.h.
607 (ipcp_value_base): Likewise.
608 (ipcp_value): Likewise.
609 (ipcp_lattice): Likewise.
610 (ipcp_agg_lattice): Likewise.
611 (ipcp_bits_lattice): Likewise.
612 (ipcp_vr_lattice): Likewise.
613 (ipcp_param_lattices): Likewise.
614 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
615 (ipa_value_from_jfunc): Adjust a check for empty lattices.
616 (ipa_context_from_jfunc): Likewise.
617 (ipa_agg_value_from_jfunc): Likewise.
618 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
619 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
620 just in contiguous memory.
621 (ipcp_store_vr_results): Adjust a check for empty lattices.
622 * auto-profile.cc: Include sreal.h and ipa-cp.h.
623 * cgraph.cc: Likewise.
624 * cgraphclones.cc: Likewise.
625 * cgraphunit.cc: Likewise.
626 * config/aarch64/aarch64.cc: Likewise.
627 * config/i386/i386-builtins.cc: Likewise.
628 * config/i386/i386-expand.cc: Likewise.
629 * config/i386/i386-features.cc: Likewise.
630 * config/i386/i386-options.cc: Likewise.
631 * config/i386/i386.cc: Likewise.
632 * config/rs6000/rs6000.cc: Likewise.
633 * config/s390/s390.cc: Likewise.
634 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
635 files to be included in gtype-desc.cc.
636 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
637 * ipa-devirt.cc: Likewise.
638 * ipa-fnsummary.cc: Likewise.
639 * ipa-icf.cc: Likewise.
640 * ipa-inline-analysis.cc: Likewise.
641 * ipa-inline-transform.cc: Likewise.
642 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
643 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
644 * ipa-param-manipulation.cc: Likewise.
645 * ipa-predicate.cc: Likewise.
646 * ipa-profile.cc: Likewise.
647 * ipa-prop.cc: Likewise.
648 (ipa_node_params_t::duplicate): Assert new lattices remain empty
649 instead of setting them to NULL.
650 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
651 * ipa-split.cc: Likewise.
652 * ipa-sra.cc: Likewise.
653 * ipa-strub.cc: Likewise.
654 * ipa-utils.cc: Likewise.
655 * ipa.cc: Likewise.
656 * toplev.cc: Likewise.
657 * tree-ssa-ccp.cc: Likewise.
658 * tree-ssa-sccvn.cc: Likewise.
659 * tree-vrp.cc: Likewise.
661 2024-02-21 Tamar Christina <tamar.christina@arm.com>
663 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
664 Armv8.7-a.
666 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
668 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
669 Use aarch64_gen_compare_zero_and_branch rather than emitting
670 a CBZ directly.
672 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
674 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
675 Remove duplicated call.
677 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
679 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
680 Check that each individual piece of state is shared in the same
681 way, rather than using an aggregate check for PSTATE.ZA.
683 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
685 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
686 In the code that commits a lazy save, only zero ZA if the function
687 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
689 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
691 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
692 directly inserting the associated sequence
693 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
694 ...here instead.
696 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
698 PR target/113995
699 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
700 fold the SVE allocation into the initial allocation if the
701 initial allocation includes a VG save.
703 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
705 PR target/113220
706 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
707 contain jumps even if called after initial RTL expansion.
708 * mode-switching.cc: Include cfgbuild.h.
709 (optimize_mode_switching): Allow the sequence returned by the
710 emit hook to contain internal jumps. Record which blocks
711 contain such jumps and split the blocks at the end.
712 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
713 non-debug insns when scanning the sequence.
715 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
717 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
718 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
720 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
722 * doc/invoke.texi (-mmcu): Add information about MCU specs.
724 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
726 * doc/invoke.texi (-minrt): Clarify that main
727 must take no arguments.
729 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
731 * config/avr/builtins.def: Use function prototypes of given size
732 and signedness.
733 * config/avr/avr.cc (avr_init_builtins): Adjust types required
734 by builtins.def.
735 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
737 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
739 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
740 instead of @table.
742 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
744 * config/bpf/bpf.opt: Add help information for -mcpu.
746 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
748 PR target/113805
749 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
750 New pass.
751 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
752 Declare.
753 * config/aarch64/aarch64.md (is_call): New attribute.
754 (*and<mode>3nr_compare0): Rename to...
755 (@aarch64_and<mode>3nr_compare0): ...this.
756 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
757 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
758 * config/aarch64/aarch64-speculation.cc: Update file comment to
759 describe the new late pass.
760 (aarch64_do_track_speculation): Handle is_call insns like other calls.
761 (pass_track_speculation): Add an is_late member variable.
762 (pass_track_speculation::gate): Run the late pass for streaming-
763 compatible functions and the early pass for other functions.
764 (make_pass_track_speculation): Update accordingly.
765 (make_pass_late_track_speculation): New function.
766 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
767 function.
768 (aarch64_guard_switch_pstate_sm): Use it.
770 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
772 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
773 Register these builtins with a pointer to uint64_t rather than unsigned
774 DI mode.
776 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
778 PR target/113615
779 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
780 Conditionalize on '!TARGET_RDNA2_PLUS'.
781 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
782 (gcn_expand_reduc_scalar):
783 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
785 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
787 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
788 '__gfx90a__' target CPU definition. Add some safeguards for the future.
790 2024-02-19 Richard Biener <rguenther@suse.de>
792 PR rtl-optimization/54052
793 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
794 local defs by LR_OUT.
796 2024-02-19 Jakub Jelinek <jakub@redhat.com>
798 PR tree-optimization/113967
799 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
800 in condition that @rpos is multiple of vector element size.
802 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
804 PR target/113696
805 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
806 Suppress vsetvl fusion.
808 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
810 PR target/113912
811 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
812 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
813 (ix86_emit_save_regs): Don't generate push2 if
814 ix86_can_use_push2pop2 return false.
815 (ix86_expand_epilogue): Don't generate pop2 if
816 ix86_can_use_push2pop2 return false.
818 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
820 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
821 Note on complete device support.
823 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
825 * doc/extend.texi (AVR Function Attributes): Fuse description
826 of "signal" and "interrupt" attribute. Link pseudo instruction.
828 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
830 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
831 symbol type conversions.
832 (__cacop_d): Likewise.
833 (__cpucfg): Likewise.
834 (__asrtle_d): Likewise.
835 (__asrtgt_d): Likewise.
836 (__lddir_d): Likewise.
837 (__ldpte_d): Likewise.
838 (__crc_w_b_w): Likewise.
839 (__crc_w_h_w): Likewise.
840 (__crc_w_w_w): Likewise.
841 (__crc_w_d_w): Likewise.
842 (__crcc_w_b_w): Likewise.
843 (__crcc_w_h_w): Likewise.
844 (__crcc_w_w_w): Likewise.
845 (__crcc_w_d_w): Likewise.
846 (__csrrd_w): Likewise.
847 (__csrwr_w): Likewise.
848 (__csrxchg_w): Likewise.
849 (__csrrd_d): Likewise.
850 (__csrwr_d): Likewise.
851 (__csrxchg_d): Likewise.
852 (__iocsrrd_b): Likewise.
853 (__iocsrrd_h): Likewise.
854 (__iocsrrd_w): Likewise.
855 (__iocsrrd_d): Likewise.
856 (__iocsrwr_b): Likewise.
857 (__iocsrwr_h): Likewise.
858 (__iocsrwr_w): Likewise.
859 (__iocsrwr_d): Likewise.
860 (__frecipe_s): Likewise.
861 (__frecipe_d): Likewise.
862 (__frsqrte_s): Likewise.
863 (__frsqrte_d): Likewise.
865 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
867 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
868 function return value type to unsigned short.
870 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
872 * doc/sourcebuild.texi: add scan-assembler-bound
874 2024-02-16 Jason Merrill <jason@redhat.com>
876 * gdbhooks.py: Fix regex syntax.
878 2024-02-16 Richard Biener <rguenther@suse.de>
880 PR tree-optimization/113895
881 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
882 consistency checking when there are out-of-bound array
883 accesses. Allow -1 off when from an array reference with
884 constant index.
886 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
888 PR target/106543
889 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
890 pattern.
892 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
894 * doc/sourcebuild.texi (Effective-Target Keywords, Other
895 attribugs): Document linker_plugin.
896 (Require Support): Document dg-require-linker-plugin.
898 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
900 PR target/109349
901 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
902 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
903 (RISCV_MINOR_VERSION_BASE): Ditto.
904 (RISCV_REVISION_VERSION_BASE): Ditto.
905 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
906 rather than magic number.
907 * config/riscv/riscv.h (riscv_arch_help): New.
908 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
909 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
910 --print-supported-extensions.
911 * config/riscv/riscv.opt (march=help): New.
912 (print-supported-extensions): New.
913 (-print-supported-extensions): New.
914 * doc/invoke.texi (RISC-V Options): Document -march=help.
916 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
918 PR target/113780
919 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
920 for indirect calls with 4 or more arguments in pac-enabled functions.
922 2024-02-15 David Faust <david.faust@oracle.com>
924 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
925 use ldxb instead of ldxh.
927 2024-02-15 Jakub Jelinek <jakub@redhat.com>
929 PR middle-end/113921
930 * cfgrtl.h (prepend_insn_to_edge): New declaration.
931 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
932 comment.
933 (prepend_insn_to_edge): New function.
934 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
935 insert_insn_on_edge.
937 2024-02-15 Richard Biener <rguenther@suse.de>
939 PR tree-optimization/111156
940 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
941 at the pattern stmt if any.
943 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
945 PR target/113927
946 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
947 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
948 * config/avr/avr.cc (avr_adiw_reg_p): New function.
949 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
950 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
951 * config/avr/avr.md: Same.
952 (attr "isa") <tiny, no_tiny>: Remove.
953 <adiw, no_adiw>: Add.
954 (define_insn, define_insn_and_split): When an alternative has
955 constraint "w", then set attribute "isa" to "adiw".
956 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
957 Built-in define __AVR_HAVE_ADIW__.
958 * doc/invoke.texi (AVR Options): Document it.
960 2024-02-15 Andrew Stubbs <ams@baylibre.com>
962 * config/gcn/gcn-valu.md
963 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
964 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
965 details are supported on RDNA devices.
967 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
969 PR middle-end/113508
970 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
971 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
972 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
973 Add sentence about what the mode m is.
975 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
977 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
978 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
979 var.
981 2024-02-15 Richard Biener <rguenther@suse.de>
983 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
984 stmts.
986 2024-02-15 Jakub Jelinek <jakub@redhat.com>
988 PR tree-optimization/113567
989 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
990 _BitInt multiplication, division or modulo with
991 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
992 force the affected inputs into a new SSA_NAME.
994 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
996 PR target/113871
997 * config/i386/mmx.md (V248FI): New mode iterator.
998 (V24FI_32): DItto.
999 (vec_shl_<V248FI:mode>): New expander.
1000 (vec_shl_<V24FI_32:mode>): Ditto.
1001 (vec_shr_<V248FI:mode>): Ditto.
1002 (vec_shr_<V24FI_32:mode>): Ditto.
1003 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
1004 (vec_shr_<V248FI:mode>): Ditto.
1006 2024-02-14 Jan Hubicka <jh@suse.cz>
1008 PR tree-optimization/111054
1009 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
1011 2024-02-14 Tamar Christina <tamar.christina@arm.com>
1013 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
1015 2024-02-14 Richard Biener <rguenther@suse.de>
1017 PR tree-optimization/113910
1018 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
1019 the hashval_t hash.
1021 2024-02-14 Jakub Jelinek <jakub@redhat.com>
1023 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
1024 (pp_integer_with_precision): For unsigned ptrdiff_t printing
1025 with u, o or x print ptrdiff_t argument converted to
1026 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
1028 2024-02-14 Richard Biener <rguenther@suse.de>
1030 PR middle-end/113576
1031 * expr.cc (do_store_flag): For vector bool compares of vectors
1032 with padding zero that.
1033 * dojump.cc (do_compare_and_jump): Likewise.
1035 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
1037 * doc/install.texi (Prerequisites): Update gettext link.
1039 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
1041 PR target/113876
1042 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
1043 Return false if the incoming stack isn't 16-byte aligned.
1045 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
1047 PR middle-end/113904
1048 * omp-general.cc (struct omp_ts_info): Update for splitting of
1049 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1050 * omp-selectors.h (enum omp_tp_type): Replace
1051 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1053 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
1055 PR target/113742
1056 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
1057 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
1059 2024-02-13 Richard Biener <rguenther@suse.de>
1061 PR tree-optimization/113895
1062 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
1063 offset to discover constant array indices in bits, handle
1064 COMPONENT_REF to bitfields.
1066 2024-02-13 Richard Biener <rguenther@suse.de>
1068 PR tree-optimization/113831
1069 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
1070 typo in comment.
1072 2024-02-13 Richard Biener <rguenther@suse.de>
1074 PR tree-optimization/113902
1075 * tree-vect-loop.cc (move_early_exit_stmts): Track
1076 last_seen_vuse for VUSE updating.
1078 2024-02-13 Tamar Christina <tamar.christina@arm.com>
1080 PR tree-optimization/113734
1081 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
1082 an early break loop as partial.
1084 2024-02-13 Richard Biener <rguenther@suse.de>
1086 PR tree-optimization/113898
1087 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
1088 missing accumulated off adjustment.
1090 2024-02-13 Jakub Jelinek <jakub@redhat.com>
1092 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
1093 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
1094 it against UINT_MAX and ULONG_MAX.
1096 2024-02-13 David Malcolm <dmalcolm@redhat.com>
1098 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
1099 to...
1100 (emit_diagnostic_valist_meta): ...this.
1101 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
1102 (emit_diagnostic_valist_meta): ...this.
1104 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1106 PR tree-optimization/113849
1107 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
1108 fast path for widening casts where !m_upwards_2limb and lhs_type
1109 has precision which is a multiple of limb_prec.
1111 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1113 PR c++/113674
1114 * attribs.cc (extract_attribute_substring): Remove.
1115 (lookup_scoped_attribute_spec): Don't call it.
1117 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1119 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
1120 and cast to fmt_size_t instead of %lu and cast to unsigned long.
1122 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
1124 * Makefile.in: Add no-info dependency.
1125 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
1126 available.
1127 * configure: Regenerate.
1129 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
1131 PR target/113855
1132 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
1133 available to all sub-targets.
1134 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1135 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1137 2024-02-12 Richard Biener <rguenther@suse.de>
1139 PR tree-optimization/113831
1140 PR tree-optimization/108355
1141 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
1142 we see variable array indices and get_ref_base_and_extent
1143 can resolve those to constants fix up the ops to constants
1144 as well.
1145 (ao_ref_init_from_vn_reference): Use 'off' member for
1146 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
1147 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
1149 2024-02-12 Pan Li <pan2.li@intel.com>
1151 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
1152 Replace args to arguments for misspelled term.
1154 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
1156 PR target/112944
1157 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
1158 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
1159 when not linked with -mrodata-in-ram.
1161 2024-02-12 Richard Biener <rguenther@suse.de>
1163 PR tree-optimization/113863
1164 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1165 Record crossed virtual PHIs.
1166 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
1167 virtual PHIs.
1169 2024-02-10 Marek Polacek <polacek@redhat.com>
1171 DR 2237
1172 PR c++/107126
1173 PR c++/97202
1174 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
1176 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1178 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
1179 computation of idx for i == 4 of bitint_prec_huge.
1181 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1183 PR middle-end/110754
1184 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
1185 decls create PARM_DECL with pointer to original type, set
1186 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
1187 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
1188 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
1189 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
1190 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
1191 of the var as argument.
1193 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1195 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
1196 size_t and precision 4 for ptrdiff_t. Formatting fix.
1197 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
1198 Formatting fixes.
1199 (test_pp_format): Test t and z modifiers.
1200 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
1202 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1204 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
1205 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
1206 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
1207 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
1208 and casts to fmt_size_t instead of "%ld" and casts to long.
1209 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
1210 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
1211 instead of "%lu" and casts to unsigned long.
1212 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
1213 unsigned long.
1214 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
1215 and casts to fmt_size_t instead of "%ld" and casts to long.
1216 * cfgexpand.cc (dump_stack_var_partition): Use
1217 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
1218 and casts to unsigned long.
1219 * gengtype.cc (adjust_field_rtx_def): Likewise.
1220 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
1221 and casts to fmt_size_t instead of "%ld" and casts to long.
1222 * postreload-gcse.cc (dump_hash_table): Likewise.
1223 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
1224 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
1225 (ggc_internal_alloc, ggc_free): Likewise.
1226 * genpreds.cc (write_lookup_constraint_1): Likewise.
1227 (write_insn_constraint_len): Likewise.
1228 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
1229 and casts to fmt_size_t instead of "%ld" and casts to long.
1230 * varasm.cc (output_constant_pool_contents): Use
1231 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
1232 * var-tracking.cc (dump_var): Likewise.
1234 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1236 PR tree-optimization/113783
1237 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
1238 through VIEW_CONVERT_EXPR for final cast checks. Handle
1239 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
1240 INTEGER_TYPEs.
1241 (gimple_lower_bitint): Don't merge mergeable operations or other
1242 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
1243 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
1244 mode is BLKmode.
1246 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1248 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
1249 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
1250 HOST_SIZE_T_PRINT_HEX_PURE): Define.
1251 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
1252 fixes.
1254 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1256 PR middle-end/113415
1257 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
1258 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
1259 of hand written loop with emit_insn of copy_insn and emit original
1260 after_rtl_seq on the last edge.
1262 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1264 PR tree-optimization/113818
1265 * gimple-lower-bitint.cc (add_eh_edge): New function.
1266 (bitint_large_huge::handle_load,
1267 bitint_large_huge::lower_mergeable_stmt,
1268 bitint_large_huge::lower_muldiv_stmt): Use it.
1270 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1272 PR tree-optimization/113774
1273 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
1274 emit any comparison if m_first and low + 1 is equal to
1275 m_upwards_2limb, simplify condition for that. If not
1276 single_comparison, not m_first and we can prove that the idx <= low
1277 comparison will be always true, emit instead of idx <= low
1278 comparison low <= low such that cfg cleanup will optimize it at
1279 the end of the pass.
1281 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
1283 PR tree-optimization/113735
1284 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
1285 limit_check().
1287 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1289 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
1290 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
1292 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
1294 PR target/113711
1295 PR target/113733
1296 * config/i386/constraints.md: List all constraints with j prefix.
1297 (j>): Change auto-dec to auto-inc in documentation.
1298 (je): Changed to a memory constraint with APX NDD TLS operand
1299 check.
1300 (jM): New memory constraint for APX NDD instructions.
1301 (jO): Likewise.
1302 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
1303 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
1304 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
1305 (*add<mode>_1[SWI48]): Use je and jM.
1306 (addsi_1_zext): Use jM.
1307 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
1308 (*sub<mode>_1[SWI]): Use jM.
1309 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
1310 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
1311 (*and<dwi>3_doubleword): Likewise.
1312 (*anddi_1): Use jM.
1313 (*andsi_1_zext): Likewise.
1314 (*and<mode>_1[SWI24]): Likewise.
1315 (*<code><dwi>3_doubleword[any_or]): Use rjO
1316 (*code<mode>_1[any_or SWI248]): Use jM.
1317 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
1318 * config/i386/predicates.md (apx_ndd_memory_operand): New.
1319 (apx_ndd_add_memory_operand): Likewise.
1321 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1323 PR target/113824
1324 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
1325 * doc/avr-mmcu.texi: Rebuild.
1327 2024-02-08 Tamar Christina <tamar.christina@arm.com>
1329 PR tree-optimization/113808
1330 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
1331 value cross iterations.
1333 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1335 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
1336 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
1338 2024-02-08 Richard Biener <rguenther@suse.de>
1340 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1341 Revert last change to dr_may_alias_p.
1343 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1345 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
1346 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
1347 Remove spec asm_misc.
1348 * config/avr/specs.h: Same.
1350 2024-02-08 Pan Li <pan2.li@intel.com>
1352 PR target/113766
1353 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
1354 sure the c.arg_num is >= 2 before checking.
1355 (struct build_frm_base): Ditto.
1356 (struct narrow_alu_def): Ditto.
1358 2024-02-07 Richard Biener <rguenther@suse.de>
1360 PR tree-optimization/113796
1361 * tree-if-conv.cc (combine_blocks): Wipe range-info before
1362 replacing PHIs and inserting predicates.
1364 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
1365 Uros Bizjak <ubizjak@gmail.com>
1367 PR target/113690
1368 * config/i386/i386-features.cc (timode_convert_cst): New helper
1369 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
1370 CONST_VECTOR.
1371 (timode_scalar_chain::convert_op): Use timode_convert_cst.
1372 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
1373 Use timode_convert_cst.
1375 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
1377 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
1378 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
1379 (AARCH64_FL_DEBUGv8p9): Likewise.
1380 (AARCH64_FL_FGT2): Likewise.Likewise.
1381 (AARCH64_FL_ITE): Likewise.
1382 (AARCH64_FL_PFAR): Likewise.
1383 (AARCH64_FL_PMUv3_ICNTR): Likewise.
1384 (AARCH64_FL_PMUv3_SS): Likewise.
1385 (AARCH64_FL_PMUv3p9): Likewise.
1386 (AARCH64_FL_RASv2): Likewise.
1387 (AARCH64_FL_S1PIE): Likewise.
1388 (AARCH64_FL_S1POE): Likewise.
1389 (AARCH64_FL_S2PIE): Likewise.
1390 (AARCH64_FL_S2POE): Likewise.
1391 (AARCH64_FL_SCTLR2): Likewise.
1392 (AARCH64_FL_SEBEP): Likewise.
1393 (AARCH64_FL_SPE_FDS): Likewise.
1394 (AARCH64_FL_TCR2): Likewise.
1396 2024-02-07 Richard Biener <rguenther@suse.de>
1398 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1399 Only check whether reads are in-bound in places that are not safe.
1400 Fix dependence check. Add missing newline. Clarify comments.
1402 2024-02-07 Tamar Christina <tamar.christina@arm.com>
1404 PR tree-optimization/113750
1405 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
1406 for single predecessor when doing early break vect.
1407 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
1408 after labels.
1410 2024-02-07 Tamar Christina <tamar.christina@arm.com>
1412 PR tree-optimization/113731
1413 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
1414 method.
1415 * gimple-iterator.h (gsi_move_before): Default new param to
1416 GSI_SAME_STMT.
1417 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
1418 GSI_NEW_STMT.
1420 2024-02-07 Jakub Jelinek <jakub@redhat.com>
1422 PR tree-optimization/113756
1423 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
1424 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
1425 of lh_bits value and mask.
1427 2024-02-07 Jakub Jelinek <jakub@redhat.com>
1429 PR tree-optimization/113753
1430 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
1431 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
1432 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
1433 so that they start with r[half_blocks_needed] lowest bit. Fix up
1434 computation of top mask for SIGNED.
1436 2024-02-07 Pan Li <pan2.li@intel.com>
1438 PR target/113766
1439 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
1440 the signature of func.
1441 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
1442 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
1443 overloaded func with empty args error.
1445 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
1447 PR target/113689
1448 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
1449 R10_REG after sorry.
1451 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
1453 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
1454 Move before new caller, and add ".default" suffix.
1455 (get_suffixed_assembler_name): New.
1456 (make_resolver_func): Use get_suffixed_assembler_name.
1457 (aarch64_generate_version_dispatcher_body): Redo name mangling.
1459 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1461 PR target/113763
1462 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
1463 element from std::pair<unsigned int, char> to an unnamed struct.
1464 Adjust uses of tile range variable.
1466 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1468 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
1469 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
1471 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1473 PR sanitizer/110676
1474 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
1475 reset maxlen to sizetype maximum.
1477 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1479 PR tree-optimization/113736
1480 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
1481 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
1483 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1485 PR tree-optimization/113759
1486 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
1487 or from_unsignedN differs from properties of typeN, update typeN
1488 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
1489 uselessly convertible to typeN, convert it using fold_convert or
1490 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
1491 (convert_plusminus_to_widen): Likewise.
1493 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
1495 PR target/112577
1496 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
1497 vector structure modes correctly.
1499 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
1501 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
1502 warning.
1504 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
1506 PR target/113689
1507 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
1508 (x86_function_profiler): Call x86_64_select_profile_regnum to
1509 get a scratch register for large model profiling.
1511 2024-02-05 Richard Ball <richard.ball@arm.com>
1513 * config/arm/arm.cc (arm_output_mi_thunk): Emit
1514 insn for bti_c when bti is enabled.
1516 2024-02-05 Xi Ruoyao <xry111@xry111.site>
1518 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
1519 neg.
1521 2024-02-05 Xi Ruoyao <xry111@xry111.site>
1523 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
1524 (neg<mode>2): Change the mode iterator from MSA to IMSA because
1525 in FP arithmetic we cannot use (0 - x) for -x.
1526 (neg<mode>2): New define_insn to implement FP vector negation,
1527 using a bnegi instruction to negate the sign bit.
1529 2024-02-05 Richard Biener <rguenther@suse.de>
1531 PR tree-optimization/113707
1532 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
1533 checking the avail set treat out-of-region defines as
1534 available.
1536 2024-02-05 Richard Biener <rguenther@suse.de>
1538 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
1539 the default mode when building a pointer.
1541 2024-02-05 Jakub Jelinek <jakub@redhat.com>
1543 PR tree-optimization/113737
1544 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
1545 has just a single label, remove it and make single successor edge
1546 EDGE_FALLTHRU.
1548 2024-02-05 Jakub Jelinek <jakub@redhat.com>
1550 PR target/113059
1551 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
1552 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
1553 df_analyze call.
1555 2024-02-05 Richard Biener <rguenther@suse.de>
1557 PR target/113255
1558 * config/i386/i386-expand.cc
1559 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
1560 Use a new pseudo for the skipped number of bytes.
1562 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
1564 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
1565 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
1566 sifive-p670.
1568 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
1570 * config/riscv/riscv.md: Include sifive-p400.md.
1571 * config/riscv/sifive-p400.md: New file.
1572 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
1573 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
1574 Add sifive_p400.
1575 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
1576 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
1577 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
1579 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
1581 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
1582 Add missing ":SI" to the match_operator.
1584 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
1586 * config/xtensa/xtensa.md (SHI): New mode iterator.
1587 (2 split patterns related to constsynth):
1588 Change to also accept HImode operands.
1590 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
1592 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
1593 similarly.
1595 2024-02-04 Xi Ruoyao <xry111@xry111.site>
1597 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
1598 incorrect expand.
1599 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
1600 (elmsgnbit): Likewise.
1601 (neg<mode:FVEC>2): New define_insn.
1602 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
1603 are now instantiated in simd.md.
1605 2024-02-04 Xi Ruoyao <xry111@xry111.site>
1607 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
1608 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
1609 MAX_MACHINE_MODE.
1611 2024-02-04 Li Wei <liwei@loongson.cn>
1613 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
1614 (loongarch_expand_vselect_vconcat): Ditto.
1615 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
1616 all 128-bit constant permutation situations.
1617 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
1618 (loongarch_is_imm_set_shuffle): Renamed function name.
1619 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
1620 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
1621 extract-even and extract-odd permutations.
1622 (loongarch_is_odd_extraction): Delete.
1623 (loongarch_is_even_extraction): Ditto.
1624 (loongarch_expand_vec_perm_const): Adjust.
1626 2024-02-03 Jakub Jelinek <jakub@redhat.com>
1628 PR middle-end/113722
1629 * wide-int.cc (wi::bswap_large): Rename third argument from
1630 len to xlen and adjust use in safe_uhwi. Add len variable, set
1631 it to BLOCKS_NEEDED (precision) and use it for clearing of val
1632 and as canonize argument. Clear val using memset instead of
1633 a loop.
1635 2024-02-03 Jakub Jelinek <jakub@redhat.com>
1637 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
1638 mmi.preferred_base + mmi.size - sizeof (void *).
1640 2024-02-03 Xi Ruoyao <xry111@xry111.site>
1642 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
1643 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
1644 the ODR-violating locale declaration.
1646 2024-02-02 Tamar Christina <tamar.christina@arm.com>
1648 PR tree-optimization/113588
1649 PR tree-optimization/113467
1650 * tree-vect-data-refs.cc
1651 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
1652 (vect_analyze_early_break_dependences): Update comments.
1654 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
1656 PR target/59778
1657 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
1658 and PA_BUILTIN_SET_FPSR builtins.
1659 * (pa_builtins_icode): Declare.
1660 * (def_builtin, pa_fpu_init_builtins): New.
1661 * (pa_init_builtins): Initialize FPU builtins.
1662 * (pa_builtin_decl, pa_expand_builtin_1): New.
1663 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
1664 PA_BUILTIN_SET_FPSR builtins.
1665 * (pa_atomic_assign_expand_fenv): New.
1666 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
1667 UNSPECV constants.
1668 (get_fpsr, put_fpsr): New expanders.
1669 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
1670 insn patterns.
1672 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1674 PR target/113697
1675 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
1677 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
1679 * doc/extend.texi (Common Type Attributes): Fix typo in
1680 description of hardbool.
1682 2024-02-02 Jakub Jelinek <jakub@redhat.com>
1684 PR tree-optimization/113692
1685 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
1686 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
1687 final_cast_p.
1689 2024-02-02 Jakub Jelinek <jakub@redhat.com>
1691 PR middle-end/113699
1692 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
1693 uninitialized large/huge _BitInt SSA_NAME inputs.
1695 2024-02-02 Jakub Jelinek <jakub@redhat.com>
1697 PR middle-end/113705
1698 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
1699 around wi::to_wide in order to compare value in prec precision.
1701 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
1703 Revert:
1704 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1706 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
1708 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1710 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
1712 2024-02-02 Pan Li <pan2.li@intel.com>
1714 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
1715 (riscv_pass_by_reference): Ditto.
1716 (riscv_fntype_abi): Ditto.
1718 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1720 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
1721 (pre_vsetvl::cleaup): Remove vsetvl_pre.
1722 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
1724 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
1726 * config/loongarch/larchintrin.h
1727 (__frecipe_s): Update function return type.
1728 (__frecipe_d): Ditto.
1729 (__frsqrte_s): Ditto.
1730 (__frsqrte_d): Ditto.
1732 2024-02-02 Li Wei <liwei@loongson.cn>
1734 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
1735 (loongarch_vector_costs::add_stmt_cost): Adjust.
1737 2024-02-02 Xi Ruoyao <xry111@xry111.site>
1739 * config/loongarch/loongarch.md (unspec): Add
1740 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
1741 (la_pcrel64_two_parts): New define_insn.
1742 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
1743 typo in the comment.
1744 (loongarch_call_tls_get_addr): If -mcmodel=extreme
1745 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
1746 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
1747 note to allow CSE addressing __tls_get_addr.
1748 (loongarch_legitimize_tls_address): If -mcmodel=extreme
1749 -mexplicit-relocs={always,auto}, address TLS IE symbols with
1750 la_pcrel64_two_parts.
1751 (loongarch_split_symbol): If -mcmodel=extreme
1752 -mexplicit-relocs={always,auto}, address symbols with
1753 la_pcrel64_two_parts.
1754 (loongarch_output_mi_thunk): Clean up unreachable code. If
1755 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
1756 thunks with la_pcrel64_two_parts.
1758 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1760 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
1761 Add support for call36.
1763 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1765 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
1766 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
1767 the macro instruction loading symbol address is not applicable.
1768 (loongarch_call_tls_get_addr): Adjust code.
1769 (loongarch_legitimize_tls_address): Likewise.
1771 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1773 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
1774 Add function declaration.
1775 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
1776 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
1777 is not allowed
1778 (loongarch_load_tls): Added macro support in extreme mode.
1779 (loongarch_call_tls_get_addr): Likewise.
1780 (loongarch_legitimize_tls_address): Likewise.
1781 (loongarch_force_address): Likewise.
1782 (loongarch_legitimize_move): Likewise.
1783 (loongarch_output_mi_thunk): Likewise.
1784 (loongarch_option_override_internal): Remove the code that detects
1785 explicit relocs status.
1786 (loongarch_handle_model_attribute): Likewise.
1787 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
1788 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
1789 (symbolic_off64_or_reg_operand): Likewise.
1791 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1793 * config/loongarch/loongarch.cc (loongarch_load_tls):
1794 Load all types of tls symbols through one function.
1795 (loongarch_got_load_tls_gd): Delete.
1796 (loongarch_got_load_tls_ld): Delete.
1797 (loongarch_got_load_tls_ie): Delete.
1798 (loongarch_got_load_tls_le): Delete.
1799 (loongarch_call_tls_get_addr): Modify the called function name.
1800 (loongarch_legitimize_tls_address): Likewise.
1801 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
1802 (@load_tls<mode>): New template.
1803 (@got_load_tls_ld<mode>): Delete.
1804 (@got_load_tls_le<mode>): Delete.
1805 (@got_load_tls_ie<mode>): Delete.
1807 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1809 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
1810 (loongarch_legitimize_address): Add logical transformation code.
1812 2024-02-01 Marek Polacek <polacek@redhat.com>
1814 * doc/invoke.texi: Update -Wdangling-reference documentation.
1816 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
1818 PR target/113701
1819 * config/i386/i386.md (*cmp<dwi>_doubleword):
1820 Do not force SUBREG pieces to pseudos.
1822 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
1824 * config/pa/pa.md (atomic_storedi_1): Fix bug in
1825 alternative 1.
1827 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
1829 * config/avr/avr.cc: Tabify.
1831 2024-02-01 Richard Ball <richard.ball@arm.com>
1833 PR tree-optimization/111268
1834 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
1835 Add variable-length check for vector input arguments
1836 to a function.
1838 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1840 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
1841 hard-code number of SGPR/VGPR/AVGPR registers.
1842 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
1843 SGPR/VGPR/AVGPR registers.
1845 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
1847 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
1848 attribute, and include sifive-p600.md.
1849 * config/riscv/generic-ooo.md: Update type attribute.
1850 * config/riscv/generic.md: Update type attribute.
1851 * config/riscv/sifive-7.md: Update type attribute.
1852 * config/riscv/sifive-p600.md: New file.
1853 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
1854 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
1855 Add sifive_p600.
1856 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
1857 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
1858 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
1860 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
1862 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
1863 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
1864 * config/riscv/riscv.opt: New macro for 7 new unprivileged
1865 extensions.
1866 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
1867 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
1869 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1871 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
1872 -static-libasan. Add missing whitespace.
1874 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1876 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
1877 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
1878 Don't 'define_constants'.
1880 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1882 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
1884 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1886 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
1887 [TARGET_RDNA3]: Adjust.
1889 2024-02-01 Richard Biener <rguenther@suse.de>
1891 PR tree-optimization/113693
1892 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
1893 data when available.
1895 2024-02-01 Jakub Jelinek <jakub@redhat.com>
1896 Jason Merrill <jason@redhat.com>
1898 PR c++/113531
1899 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
1900 on variables which were promoted to TREE_STATIC.
1902 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
1903 Richard Biener <rguenther@suse.de>
1905 PR target/113560
1906 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
1907 information via tree_non_zero_bits to check if this operand
1908 is suitably extended for a widening (or highpart) multiplication.
1909 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
1910 isn't already of the claimed type.
1912 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1914 Revert:
1915 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1917 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1918 (generic_ooo_branch): ditto
1919 * config/riscv/generic.md (generic_sfb_alu): ditto
1920 (generic_fmul_half): ditto
1921 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1922 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
1923 (sifive_7_popcount): ditto
1924 * config/riscv/vector.md: change rdfrm to fmove
1925 * config/riscv/zc.md: change pushpop to load/store
1927 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1929 Revert:
1930 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1931 Robin Dapp <rdapp.gcc@gmail.com>
1933 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1934 (generic_ooo_vec_load): ditto
1935 (generic_ooo_vec_store): ditto
1936 (generic_ooo_vec_loadstore_seg): ditto
1937 (generic_ooo_vec_alu): ditto
1938 (generic_ooo_vec_fcmp): ditto
1939 (generic_ooo_vec_imul): ditto
1940 (generic_ooo_vec_fadd): ditto
1941 (generic_ooo_vec_fmul): ditto
1942 (generic_ooo_crypto): ditto
1943 (generic_ooo_perm): ditto
1944 (generic_ooo_vec_reduction): ditto
1945 (generic_ooo_vec_ordered_reduction): ditto
1946 (generic_ooo_vec_idiv): ditto
1947 (generic_ooo_vec_float_divsqrt): ditto
1948 (generic_ooo_vec_mask): ditto
1949 (generic_ooo_vec_vesetvl): ditto
1950 (generic_ooo_vec_setrm): ditto
1951 (generic_ooo_vec_readlen): ditto
1952 * config/riscv/riscv.md: include generic-vector-ooo
1953 * config/riscv/generic-vector-ooo.md: New file. to here
1955 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1957 Revert:
1958 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1960 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
1962 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1964 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
1966 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1967 Robin Dapp <rdapp.gcc@gmail.com>
1969 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1970 (generic_ooo_vec_load): ditto
1971 (generic_ooo_vec_store): ditto
1972 (generic_ooo_vec_loadstore_seg): ditto
1973 (generic_ooo_vec_alu): ditto
1974 (generic_ooo_vec_fcmp): ditto
1975 (generic_ooo_vec_imul): ditto
1976 (generic_ooo_vec_fadd): ditto
1977 (generic_ooo_vec_fmul): ditto
1978 (generic_ooo_crypto): ditto
1979 (generic_ooo_perm): ditto
1980 (generic_ooo_vec_reduction): ditto
1981 (generic_ooo_vec_ordered_reduction): ditto
1982 (generic_ooo_vec_idiv): ditto
1983 (generic_ooo_vec_float_divsqrt): ditto
1984 (generic_ooo_vec_mask): ditto
1985 (generic_ooo_vec_vesetvl): ditto
1986 (generic_ooo_vec_setrm): ditto
1987 (generic_ooo_vec_readlen): ditto
1988 * config/riscv/riscv.md: include generic-vector-ooo
1989 * config/riscv/generic-vector-ooo.md: New file. to here
1991 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1993 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1994 (generic_ooo_branch): ditto
1995 * config/riscv/generic.md (generic_sfb_alu): ditto
1996 (generic_fmul_half): ditto
1997 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1998 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
1999 (sifive_7_popcount): ditto
2000 * config/riscv/vector.md: change rdfrm to fmove
2001 * config/riscv/zc.md: change pushpop to load/store
2003 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
2005 PR target/113657
2006 * config/aarch64/aarch64-simd.md (split for movv8di):
2007 For strict aligned mode, use DImode instead of TImode.
2009 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
2011 PR middle-end/113607
2012 * match.pd: Make sure else values match when folding a
2013 vec_cond into a conditional operation.
2015 2024-01-31 Marek Polacek <polacek@redhat.com>
2017 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
2019 2024-01-31 Tamar Christina <tamar.christina@arm.com>
2020 Matthew Malcomson <matthew.malcomson@arm.com>
2022 PR sanitizer/112644
2023 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
2024 memcmp.
2025 * builtins.cc (expand_builtin): Include HWASAN when checking for
2026 builtin inlining.
2028 2024-01-31 Richard Biener <rguenther@suse.de>
2030 PR middle-end/110176
2031 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
2032 to match INTEGER_CST only without outstanding conversion.
2034 2024-01-31 Alex Coplan <alex.coplan@arm.com>
2036 PR target/111677
2037 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
2038 V16QImode for the full 16-byte FPR saves in the vector PCS case.
2040 2024-01-31 Richard Biener <rguenther@suse.de>
2042 PR tree-optimization/111444
2043 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
2044 vn_reference_lookup_2 when optimistically skipping may-defs.
2046 2024-01-31 Richard Biener <rguenther@suse.de>
2048 PR tree-optimization/113630
2049 * tree-ssa-pre.cc (compute_avail): Avoid registering a
2050 reference with a representation with not matching base
2051 access size.
2053 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2055 PR rtl-optimization/113656
2056 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
2057 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
2059 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2061 PR debug/113637
2062 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
2063 with BLKmode are larger than DWARF2_ADDR_SIZE.
2065 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2067 PR tree-optimization/113639
2068 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
2069 For VIEW_CONVERT_EXPR set rhs1 to its operand.
2071 2024-01-31 Richard Biener <rguenther@suse.de>
2073 PR tree-optimization/113670
2074 * tree-vect-data-refs.cc (vect_check_gather_scatter):
2075 Make sure we can take the address of the reference base.
2077 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
2079 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
2080 ATA5835, ATtiny64AUTO, ATA5700M322.
2081 * doc/avr-mmcu.texi: Rebuild.
2083 2024-01-31 Alexandre Oliva <oliva@adacore.com>
2085 PR debug/113394
2086 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
2087 caller.
2089 2024-01-31 Alexandre Oliva <oliva@adacore.com>
2091 PR middle-end/112917
2092 PR middle-end/113100
2093 * builtins.cc (expand_builtin_stack_address): Use
2094 STACK_ADDRESS_OFFSET.
2095 * doc/extend.texi (__builtin_stack_address): Adjust.
2096 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
2097 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
2098 * doc/tm.texi: Rebuilt.
2100 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2102 PR target/113495
2103 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
2104 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
2105 (pre_vsetvl::compute_transparent): New function.
2106 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
2108 2024-01-30 Fangrui Song <maskray@google.com>
2110 PR target/105576
2111 * config/i386/constraints.md: Define constraint "Ws".
2112 * doc/md.texi: Document it.
2114 2024-01-30 Marek Polacek <polacek@redhat.com>
2116 PR c++/110358
2117 PR c++/109640
2118 * doc/invoke.texi: Update -Wdangling-reference description.
2120 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2122 * config/xtensa/constraints.md (R, T, U):
2123 Change define_constraint to define_memory_constraint.
2124 * config/xtensa/predicates.md (move_operand): Don't check that a
2125 constant pool operand size is a multiple of UNITS_PER_WORD.
2126 * config/xtensa/xtensa.cc
2127 (xtensa_lra_p, TARGET_LRA_P): Remove.
2128 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
2129 clause as it can no longer be true.
2130 (fixup_subreg_mem): Drop function.
2131 (xtensa_output_integer_literal_parts): Consider 16-bit wide
2132 constants.
2133 (xtensa_legitimate_constant_p): Add short-circuit path for
2134 integer load instructions. Don't check that mode size is
2135 at least UNITS_PER_WORD.
2136 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
2137 rather reload_in_progress and reload_completed.
2138 (doloop_end): Drop operand 2.
2139 (movhi_internal): Add alternative loading constant from a
2140 literal pool.
2141 (define_split for DI register_operand): Don't limit to
2142 !TARGET_AUTO_LITPOOLS.
2143 * config/xtensa/xtensa.opt (mlra): Change to no effect.
2145 2024-01-30 Pan Li <pan2.li@intel.com>
2147 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
2148 calculate the gpr count required by vls mode.
2149 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
2150 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
2151 for vls mode.
2152 (riscv_get_arg_info): Add vls mode handling.
2153 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
2155 2024-01-30 Richard Biener <rguenther@suse.de>
2157 PR tree-optimization/113659
2158 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2159 Handle main exit without virtual use.
2161 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
2163 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
2165 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
2167 PR libgcc/113403
2168 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
2169 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
2170 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
2171 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
2172 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
2173 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
2175 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
2177 PR target/113623
2178 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
2179 Mark all registers that occur in addresses as needing a GPR.
2181 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
2183 PR target/113636
2184 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
2185 the containing insn as an extra parameter. Reset debug instructions
2186 if they reference a register that is no longer used by real insns.
2187 (early_ra::apply_allocation): Update calls accordingly.
2189 2024-01-30 Jakub Jelinek <jakub@redhat.com>
2191 PR tree-optimization/113603
2192 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
2193 count_nonzero_bytes call refetch si using get_strinfo in case it
2194 has been unshared in the meantime.
2196 2024-01-30 Jakub Jelinek <jakub@redhat.com>
2198 PR middle-end/101195
2199 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
2200 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
2202 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
2204 * config/riscv/thead.cc (th_print_operand_address): Change %ld
2205 to %lld.
2207 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
2208 Manolis Tsamis <manolis.tsamis@vrull.eu>
2209 Philipp Tomsich <philipp.tomsich@vrull.eu>
2211 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
2212 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
2213 Likewise.
2214 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
2215 Call on framework moved later.
2217 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
2219 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
2220 instruction in naked function epilogues.
2222 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
2224 PR target/113655
2225 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
2226 gcc_cv_as_mips_explicit_relocs.
2227 * configure: Regnerated.
2229 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
2231 PR target/108933
2232 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
2233 Correct generated RTL.
2234 (arm_rev16si2_alt1): Correctly handle conditional execution.
2235 (arm_rev16si2_alt2): Likewise.
2237 2024-01-29 Richard Biener <rguenther@suse.de>
2239 PR middle-end/113622
2240 * expr.cc (expand_assignment): Spill hard registers if
2241 we index them with a variable offset.
2243 2024-01-29 Richard Biener <rguenther@suse.de>
2245 PR middle-end/113622
2246 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
2247 Also allow DECL_HARD_REGISTER variables.
2249 2024-01-29 Alex Coplan <alex.coplan@arm.com>
2251 PR target/113616
2252 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
2253 Use iterate_safely when iterating over debug uses.
2254 (fixup_debug_uses): Likewise.
2255 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
2256 over nondebug insns instead of manually maintaining the next insn.
2257 * iterator-utils.h (class safe_iterator): New.
2258 (iterate_safely): New.
2260 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
2262 PR target/38534
2263 * config/i386/i386-options.cc (ix86_set_func_type): Save
2264 callee-saved registers in noreturn functions for -O0/-Og.
2266 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2268 PR target/113615
2269 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
2270 define for !TARGET_RDNA2_PLUS.
2272 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
2274 PR target/113281
2275 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
2276 workaround for right shifts.
2277 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
2278 (vect_determine_precisions_from_range): Be more selective about
2279 which codes can be narrowed based on their input and output ranges.
2280 For shifts, require at least one more bit of precision than the
2281 maximum shift amount.
2283 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2285 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
2287 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2289 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
2290 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
2291 LLVM 13.0.1+.
2293 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2295 PR other/111966
2296 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
2297 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
2298 (SET_SRAM_ECC_UNSET): ... this.
2299 (copy_early_debug_info): Remove gfx900 special case, now handled as
2300 part of the generic handling.
2301 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
2303 2024-01-29 Jakub Jelinek <jakub@redhat.com>
2305 PR tree-optimization/110603
2306 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
2307 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
2308 overwritten anyway). Avoid creating invalid range with minlen
2309 larger than maxlen. Formatting fix.
2311 2024-01-29 Richard Biener <rguenther@suse.de>
2313 PR debug/103047
2314 * tree-inline.cc (initialize_inlined_parameters): Reverse
2315 the decl chain of inlined parameters.
2317 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
2319 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
2320 alignment of CFString constants by setting DECL_USER_ALIGN.
2322 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
2323 Jakub Jelinek <jakub@redhat.com>
2325 PR libgcc/113402
2326 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
2327 and BUILT_IN_GCC_NESTED_PTR_DELETED.
2328 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
2329 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
2330 rename the library fallbacks to __gcc_nested_func_ptr_created and
2331 __gcc_nested_func_ptr_deleted.
2332 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
2333 and __gcc_nested_func_ptr_deleted.
2334 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
2335 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
2336 * tree.cc (build_common_builtin_nodes): Build the
2337 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
2338 builtins only for non-explicit.
2340 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
2342 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
2344 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
2346 PR target/38534
2347 * config/i386/i386-options.cc (ix86_set_func_type): Don't
2348 save and restore callee saved registers for a noreturn function
2349 with nothrow or compiled with -fno-exceptions.
2351 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
2353 PR target/103503
2354 PR target/113312
2355 * config/i386/i386-expand.cc (ix86_expand_call): Replace
2356 no_caller_saved_registers check with call_saved_registers check.
2357 Clobber all registers that are not used by the callee with
2358 no_callee_saved_registers attribute.
2359 * config/i386/i386-options.cc (ix86_set_func_type): Set
2360 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
2361 noreturn function. Disallow no_callee_saved_registers with
2362 interrupt or no_caller_saved_registers attributes together.
2363 (ix86_set_current_function): Replace no_caller_saved_registers
2364 check with call_saved_registers check.
2365 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
2366 (ix86_handle_call_saved_registers_attribute): This.
2367 (ix86_gnu_attributes): Add
2368 ix86_handle_call_saved_registers_attribute.
2369 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
2370 no_caller_saved_registers check with call_saved_registers check.
2371 (ix86_function_ok_for_sibcall): Don't allow callee with
2372 no_callee_saved_registers attribute when the calling function
2373 has callee-saved registers.
2374 (ix86_comp_type_attributes): Also check
2375 no_callee_saved_registers.
2376 (ix86_epilogue_uses): Replace no_caller_saved_registers check
2377 with call_saved_registers check.
2378 (ix86_hard_regno_scratch_ok): Likewise.
2379 (ix86_save_reg): Replace no_caller_saved_registers check with
2380 call_saved_registers check. Don't save any registers for
2381 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
2382 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
2383 no_callee_saved_registers attribute is called.
2384 (find_drap_reg): Replace no_caller_saved_registers check with
2385 call_saved_registers check.
2386 * config/i386/i386.h (call_saved_registers_type): New enum.
2387 (machine_function): Replace no_caller_saved_registers with
2388 call_saved_registers.
2389 * doc/extend.texi: Document no_callee_saved_registers attribute.
2391 2024-01-27 Jakub Jelinek <jakub@redhat.com>
2393 PR tree-optimization/113614
2394 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
2395 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
2396 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
2398 2024-01-27 Jakub Jelinek <jakub@redhat.com>
2400 PR tree-optimization/113568
2401 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
2402 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
2403 in the widening extension checks.
2405 2024-01-27 Jakub Jelinek <jakub@redhat.com>
2407 * gimple-lower-bitint.cc (gimple_lower_bitint): For
2408 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
2410 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
2412 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
2413 the warning for an attribute-always_inline without inline declaration.
2415 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
2417 PR other/113575
2418 * genopinit.cc (main): Split init_all_optabs into functions
2419 of 1000 patterns each.
2421 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
2423 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
2424 TM_MULTILIB_CONFIG.
2425 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
2426 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
2427 -march/-mtune.
2429 2024-01-26 Andrew Stubbs <ams@baylibre.com>
2431 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
2432 * config/gcn/gcn-valu.md (all_convert): New iterator.
2433 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
2434 define_expand, and rename the old one to ...
2435 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
2436 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
2437 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
2438 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
2439 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
2440 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
2441 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
2442 (<u>mulqihi3_scalar): Likewise.
2444 2024-01-26 Richard Biener <rguenther@suse.de>
2446 PR tree-optimization/113602
2447 * tree-data-ref.cc (dr_analyze_innermost): Fail when
2448 the base object isn't addressable.
2450 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
2452 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
2453 "--amdhsa-code-object-version=" argument.
2454 (ASM_SPEC): Use it; replace previous version of it.
2456 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2458 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
2459 (pre_vsetvl::emit_vsetvl): Ditto.
2461 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
2463 * config/loongarch/lasx.md (vec_extract<mode>_0):
2464 New define_insn_and_split patten.
2466 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
2468 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
2470 2024-01-26 Li Wei <liwei@loongson.cn>
2472 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
2474 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2476 PR target/113469
2477 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
2479 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
2481 PR target/100212
2482 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
2483 undefined shift after the call to exact_log2.
2485 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
2487 PR target/100204
2488 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
2489 before taking the negative of it.
2491 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
2493 PR target/113526
2494 * lra-constraints.cc (curr_insn_transform): Change class even for
2495 spilled pseudo successfully matched with with NO_REGS.
2497 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
2499 PR target/113601
2500 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
2502 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
2504 PR target/112987
2505 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
2506 (aarch64_expand_epilogue): Use the new function.
2507 (aarch64_split_compare_and_swap): Likewise.
2508 (aarch64_split_atomic_op): Likewise.
2510 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
2512 PR middle-end/112971
2513 * fold-const.cc (simplify_const_binop): New function for binop
2514 simplification of two constant vectors when element-wise
2515 handling is not necessary.
2516 (const_binop): Call new function.
2518 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
2520 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
2521 * config/riscv/constraints.md: Likewise.
2522 * config/riscv/corev.def: Likewise.
2523 * config/riscv/corev.md: Likewise.
2524 * config/riscv/predicates.md: Likewise.
2525 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
2526 * config/riscv/riscv-ftypes.def: Likewise.
2527 * config/riscv/riscv.opt: Likewise.
2528 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
2529 * doc/extend.texi: Add XCVbitmanip builtin documentation.
2530 * doc/sourcebuild.texi: Likewise.
2532 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
2534 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
2536 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
2538 PR target/113538
2539 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
2540 (riscv_fntype_abi): Ditto.
2541 * config/riscv/riscv.opt: Ditto.
2543 2024-01-25 Jakub Jelinek <jakub@redhat.com>
2545 PR middle-end/113574
2546 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
2547 count against TYPE_PRECISION rather than TYPE_SIZE.
2549 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
2551 PR target/113572
2552 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
2553 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
2555 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
2557 PR target/113550
2558 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
2559 whether each split instruction is a load that clobbers the source
2560 address. Emit that instruction last if so.
2562 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
2564 PR target/113485
2565 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
2566 pattern.
2567 (<optab><Vnarrowq><mode>2): Use it instead of generating a
2568 paradoxical subreg for the input.
2570 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2572 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
2573 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
2574 predecessors dump information.
2576 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2578 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
2579 redundant full available computation.
2580 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
2582 2024-01-25 Jakub Jelinek <jakub@redhat.com>
2584 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
2585 * doc/rtl.texi (CONST_VECTOR): Likewise.
2587 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2589 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
2590 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
2591 (pass_vsetvl::execute): Ditto.
2592 * config/riscv/riscv.opt: Ditto.
2594 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
2596 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
2597 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
2599 2024-01-25 Richard Biener <rguenther@suse.de>
2601 PR tree-optimization/113576
2602 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
2603 exits with may_be_zero niters when its the last one.
2605 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
2607 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
2608 For symbols of type tls, non-zero Offset is not generated.
2610 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
2612 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
2613 P9 with m32 and mpowerpc64.
2615 2024-01-25 liuhongt <hongtao.liu@intel.com>
2617 * config/i386/i386-options.cc (ix86_option_override_internal):
2618 Enable -mlam=u57 by default when compiled with
2619 -fsanitize=hwaddress.
2621 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
2623 * common/config/riscv/riscv-common.cc (riscv_implied_info):
2624 Remove {"ztso", "a"}.
2626 2024-01-24 Martin Jambor <mjambor@suse.cz>
2628 PR ipa/108007
2629 PR ipa/112616
2630 * cgraph.h (cgraph_edge): Add a parameter to
2631 redirect_call_stmt_to_callee.
2632 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
2633 parameter to modify_call.
2634 (ipa_release_ssas_in_hash): Declare.
2635 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
2636 parameter killed_ssas, pass it to padjs->modify_call.
2637 * ipa-param-manipulation.cc (purge_all_uses): New function.
2638 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
2639 Instead of substituting uses, invoke purge_all_uses. If
2640 hash of killed SSAs has not been provided, create a temporary one
2641 and release SSAs that have been added to it.
2642 (compare_ssa_versions): New function.
2643 (ipa_release_ssas_in_hash): Likewise.
2644 * tree-inline.cc (redirect_all_calls): Create
2645 id->killed_new_ssa_names earlier, pass it to edge redirection,
2646 adjust a comment.
2647 (copy_body): Release SSAs in id->killed_new_ssa_names.
2649 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
2651 PR target/113486
2652 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
2653 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
2655 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
2657 PR target/113095
2658 * config/riscv/sfb.md: New splitters to rewrite single bit
2659 sign extension as the condition to SFB instructions.
2661 2024-01-24 Jan Hubicka <jh@suse.cz>
2663 PR middle-end/88345
2664 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
2665 (fmin-function-alignment): New parameter.
2666 * doc/invoke.texi: (-fmin-function-alignment): Document.
2667 (-falign-functions,-falign-loops,-falign-labels): Mention that
2668 aglinments are ignored in cold code.
2669 * varasm.cc (assemble_start_function): Handle min-function-alignment.
2671 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2673 PR target/109636
2674 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
2675 mulv2di3): Remove.
2676 * config/aarch64/iterators.md (VQDIV): Remove.
2677 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
2678 SVE_I_SIMD_DI): New.
2679 (VPRED, sve_lane_con): Add V4SI and V2DI.
2680 * config/aarch64/aarch64-sve.md (<optab><mode>3,
2681 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
2682 (mul<mode>3): New, split from <optab><mode>3.
2683 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
2684 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
2685 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
2686 SVE_FULL_HSDI_SIMD_DI.
2688 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2690 PR tree-optimization/113552
2691 * config/aarch64/aarch64.cc
2692 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
2694 2024-01-24 Martin Jambor <mjambor@suse.cz>
2696 PR ipa/113490
2697 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
2698 count is equal or greater than the limit. Use the limit from the
2699 callee.
2701 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
2703 * configure.ac: Detect the explicit relocs support for
2704 mips, and define C macro MIPS_EXPLICIT_RELOCS.
2705 * config.in: Regenerated.
2706 * configure: Regenerated.
2707 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
2708 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
2709 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
2710 !TARGET_EXPLICIT_RELOCS instead of just set it.
2711 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
2712 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
2713 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
2714 and define -m(no-)explicit-relocs as aliases.
2716 2024-01-24 Alex Coplan <alex.coplan@arm.com>
2718 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
2719 to 1.
2720 (-mlate-ldp-fusion): Likewise.
2722 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2724 * tree-vect-loop.cc (vect_get_vect_def,
2725 vect_create_epilog_for_reduction): Rename main_exit_p to
2726 last_val_reduc_p.
2728 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2730 PR tree-optimization/113364
2731 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
2732 early exits then we must reduce from the first offset for all of them.
2734 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2736 PR target/113495
2737 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
2738 (get_regno): Ditto.
2739 (get_bb_index): Ditto.
2740 (pre_vsetvl::compute_avl_def_data): Ditto.
2741 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
2742 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
2744 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
2745 Richard Sandiford <richard.sandiford@arm.com>
2747 PR target/100942
2748 * ccmp.cc (ccmp_candidate_p): Add outer argument.
2749 Allow if the outer is true and the lhs is used more
2750 than once.
2751 (expand_ccmp_expr): Update call to ccmp_candidate_p.
2752 * expr.h (expand_expr_real_gassign): Declare.
2753 * expr.cc (expand_expr_real_gassign): New function, split out from...
2754 (expand_expr_real_1): ...here.
2755 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
2757 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2759 PR target/113089
2760 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
2761 (fixup_debug_use): New.
2762 (fixup_debug_uses_trailing_add): New.
2763 (fixup_debug_uses): New. Use it ...
2764 (ldp_bb_info::fuse_pair): ... here.
2765 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
2766 fix up debug uses of the base register that are affected by
2767 folding in the trailing add insn.
2769 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2771 PR target/113089
2772 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
2773 Update trailing nondebug uses of the base register in the case
2774 of cancelling writeback.
2776 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2778 PR target/113089
2779 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
2780 (debug_insn_use_iterator): New.
2781 (set_info::first_debug_insn_use): New.
2782 (set_info::debug_insn_uses): New.
2783 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
2784 (set_info::first_debug_insn_use): New.
2785 (set_info::debug_insn_uses): New.
2787 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2789 PR target/113356
2790 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
2791 Don't record hazards against the opposite insn in the pair.
2793 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2795 PR target/113070
2796 * config/aarch64/aarch64-ldp-fusion.cc
2797 (struct stp_change_builder): New.
2798 (decide_stp_strategy): Reanme to ...
2799 (try_repurpose_store): ... this.
2800 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
2801 construct stp changes. Fix up uses when inserting new stp insns.
2803 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2805 PR target/113070
2806 * rtl-ssa.h: Include hash-set.h.
2807 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
2808 new_sets parameter and use it to keep track of new user-created sets.
2809 (function_info::apply_changes_to_insn): Also call add_def on new sets.
2810 (function_info::change_insns): Add hash_set to keep track of new
2811 user-created defs. Plumb it through.
2812 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
2813 apply_changes_to_insn.
2815 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2817 PR target/113070
2818 * rtl-ssa/accesses.cc (function_info::create_use): New.
2819 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
2820 Ensure new uses end up referring to permanent defs.
2821 * rtl-ssa/functions.h (function_info::create_use): Declare.
2823 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2825 PR target/113070
2826 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
2827 to finalize_new_accesses from the backwards placement loop, run it
2828 forwards in a separate loop.
2830 2024-01-23 Richard Biener <rguenther@suse.de>
2832 PR tree-optimization/113552
2833 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
2834 floor_log2 instead of exact_log2 on the number of calls.
2836 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
2837 Jakub Jelinek <jakub@redhat.com>
2839 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
2840 decl.
2842 2024-01-23 Richard Biener <rguenther@suse.de>
2844 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2845 Separate single and multi-exit case when creating PHIs between
2846 the main and epilogue.
2848 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
2850 PR target/112989
2851 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
2852 MODE_single variants of functions that don't take tuple arguments.
2854 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2856 PR target/113114
2857 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
2858 Don't assert recog success, just punt if the writeback pair
2859 isn't recognized.
2861 2024-01-23 Jakub Jelinek <jakub@redhat.com>
2863 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
2864 ATTRIBUTE_UNUSED to decl.
2866 2024-01-23 Richard Biener <rguenther@suse.de>
2868 PR debug/107058
2869 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
2870 handle unexpected but bogus DIE contexts when not checking
2871 enabled.
2873 2024-01-23 Jakub Jelinek <jakub@redhat.com>
2875 PR tree-optimization/113462
2876 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
2877 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
2878 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
2879 sizes between 129 and 8192 bytes.
2881 2024-01-23 Xi Ruoyao <xry111@xry111.site>
2883 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
2884 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
2885 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
2886 (loongarch_call_tls_get_addr): Do not split symbols of
2887 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
2888 EXPLICIT_RELOCS_AUTO.
2890 2024-01-23 Richard Biener <rguenther@suse.de>
2892 * alias.cc (known_base_value_p): Remove.
2893 (find_base_value): Remove PLUS/MINUS handling
2894 when both operands are not CONST_INT_P.
2896 2024-01-23 Richard Biener <rguenther@suse.de>
2898 PR rtl-optimization/113255
2899 * alias.cc (find_base_term): Remove PLUS/MINUS handling
2900 when both operands are not CONST_INT_P.
2902 2024-01-23 Richard Biener <rguenther@suse.de>
2904 PR debug/112718
2905 * dwarf2out.cc (dwarf2out_finish): Reset all type units
2906 for the fat part of an LTO compile.
2908 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
2910 * doc/sourcebuild.texi: Add attributes for keywords.
2912 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
2914 PR c++/90463
2915 * doc/invoke.texi (Warning Options): Correct lists of options
2916 enabled by -Wall and -Wextra by checking against common.opt
2917 and c-family/c.opt.
2919 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
2921 PR target/113030
2922 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
2923 instead of cpu_optaliases.
2924 (check_arch): Use arch_opt_alias instead of arch_optaliases.
2926 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2928 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
2929 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
2930 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
2932 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2934 PR target/109092
2935 * config/riscv/riscv.md: Use reg instead of subreg.
2937 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
2939 PR other/111966
2940 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
2941 to match the compiler default.
2942 (simple_object_copy_lto_debug_sections): Never unlink the outfile
2943 on error as the caller does so.
2944 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
2945 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
2947 2024-01-22 Richard Biener <rguenther@suse.de>
2949 PR tree-optimization/113373
2950 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2951 Create LC PHIs in the exit blocks where necessary.
2952 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
2953 to handle missing LC PHIs.
2954 (find_connected_edge): Remove.
2955 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
2957 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2959 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
2961 2024-01-22 xuli <xuli1@eswincomputing.com>
2963 PR target/113420
2964 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
2965 (registered_function::overloaded_hash):refactor.
2966 (resolve_overloaded_builtin):avoid internal ICE.
2968 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
2970 PR target/82420
2971 PR target/111279
2972 * calls.cc (emit_library_call_value_1): Pass valid TYPE
2973 to emit_push_insn.
2974 * expr.cc (emit_push_insn): Likewise.
2976 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
2978 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
2979 correcction version of last change.
2981 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
2983 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
2984 fix bugs in signature.
2986 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
2987 Richard Biener <rguenther@suse.de>
2989 PR rtl-optimization/111267
2990 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
2991 profitable_p method to likely_profitable_p.
2992 (try_fwprop_subst_node): Update call to likely_profitable_p.
2993 Only bail-out early when !prop.likely_profitable_p for instructions
2994 that are not single sets. When comparing costs, bail-out if the
2995 cost is unchanged and !prop.likely_profitable_p.
2997 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
2999 PR c++/90464
3000 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
3001 isn't enabled by -Wunused unless -Wextra is provided, and that
3002 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
3003 -Wunused doesn't enable -Wunused-* options documented as behaving
3004 otherwise, and list them explicitly.
3006 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
3008 PR c/109708
3009 * doc/invoke.texi (Warning Options): Fix broken example and
3010 clean up/reorganize the others. Also describe what the short-form
3011 options mean.
3013 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
3015 PR c/102998
3016 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
3017 (Warning Options): Correct/edit discussion of -Warray-parameter
3018 to make the first example less confusing, and fill in missing info.
3020 2024-01-20 Jakub Jelinek <jakub@redhat.com>
3022 PR tree-optimization/113462
3023 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
3024 Handle rhs1 INTEGER_CST like SSA_NAME.
3026 2024-01-20 Jakub Jelinek <jakub@redhat.com>
3028 PR tree-optimization/113491
3029 * tree-switch-conversion.cc (switch_conversion::build_constructors):
3030 If elt.index has precision higher than sizetype, fold_convert it to
3031 sizetype.
3032 (switch_conversion::array_value_type): Return type if type is
3033 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
3034 (switch_conversion::build_arrays): Use unsigned_type_for rather than
3035 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
3036 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
3037 higher than sizetype, use sizetype as tidx type and fold_convert the
3038 subtraction to sizetype.
3040 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3042 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
3043 (riscv_vector_mode_supported_any_target_p): Ditto.
3045 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
3047 PR target/110934
3048 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
3049 (TARGET_ZERO_CALL_USED_REGS): Define.
3051 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
3053 PR target/108640
3054 * config/m68k/m68k.cc (output_andsi3): Use QImode for
3055 address adjusted for 1-byte RMW access.
3056 (output_iorsi3): Likewise.
3057 (output_xorsi3): Likewise.
3059 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3061 * doc/invoke.texi (RISC-V Options): Add list of supported
3062 extensions.
3064 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3066 PR target/113495
3067 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
3068 (RVV_VUNDEF): Ditto.
3069 * config/riscv/riscv-vsetvl.cc: Add timevar.
3071 2024-01-19 Richard Biener <rguenther@suse.de>
3073 PR debug/113488
3074 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
3075 an early DIE but there should be, do not pretend there is.
3077 2024-01-19 Richard Biener <rguenther@suse.de>
3079 PR tree-optimization/113494
3080 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3081 Handle endless loop on exit. Handle re-allocated PHI.
3083 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3085 PR tree-optimization/113464
3086 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
3087 optimize loads into GIMPLE_ASM stmts.
3089 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3091 PR tree-optimization/113463
3092 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
3093 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
3094 lhs.
3096 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3098 PR tree-optimization/113459
3099 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
3100 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
3101 of SCALAR_INT_TYPE_MODE if type has BLKmode.
3102 (vn_reference_lookup_3): Likewise. Formatting fix.
3104 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3105 Richard Biener <rguenther@suse.de>
3107 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
3108 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
3109 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
3110 but adjust_address also for BLKmode mode and MEM op0.
3112 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
3114 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
3115 extensions.
3117 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3119 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
3121 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3123 * common/config/riscv/riscv-common.cc
3124 (riscv_subset_list::parse_std_ext): Remove.
3125 (riscv_subset_list::parse_multiletter_ext): Remove.
3126 * config/riscv/riscv-subset.h
3127 (riscv_subset_list::parse_std_ext): Remove.
3128 (riscv_subset_list::parse_multiletter_ext): Remove.
3130 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3132 * common/config/riscv/riscv-common.cc
3133 (riscv_subset_list::parse_single_std_ext): New parameter.
3134 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3135 (riscv_subset_list::parse_single_ext): Ditto.
3136 (riscv_subset_list::parse): Relax the order for the input of ISA
3137 string.
3138 * config/riscv/riscv-subset.h
3139 (riscv_subset_list::parse_single_std_ext): New parameter.
3140 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3141 (riscv_subset_list::parse_single_ext): Ditto.
3143 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3145 * common/config/riscv/riscv-common.cc
3146 (riscv_subset_list::parse_base_ext): New.
3147 (riscv_subset_list::parse): Extract part of logic into
3148 riscv_subset_list::parse_base_ext.
3149 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
3150 New.
3152 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3154 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
3155 sorry message.
3157 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
3159 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
3160 UNSPEC_CLMUL_VC.
3162 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
3164 PR c/110029
3165 * doc/extend.texi (Common Variable Attributes): Explain what
3166 happens when multiple variables with cleanups are in the same scope.
3168 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3170 PR ipa/108470
3171 * doc/extend.texi (Common Function Attributes): Document that
3172 noinline also disables some interprocedural optimizations and
3173 improve flow to the part about using inline asm instead to
3174 disable calls from being optimized away completely. Remove the
3175 sentence that says noipa is mainly for internal compiler testing.
3177 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
3179 PR tree-optimization/69807
3180 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
3182 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
3184 PR target/108521
3185 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
3186 from x86 Windows Options.
3188 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3190 PR c/107942
3191 * doc/extend.texi (C Extensions): Add new section to menu.
3192 (Function Attributes): Move dangling index entries to....
3193 (Const and Volatile Functions): New section.
3195 2024-01-18 David Malcolm <dmalcolm@redhat.com>
3197 PR middle-end/112684
3198 * toplev.cc (toplev::main): Don't ICE in
3199 -fdiagnostics-generate-patch when exiting after options,
3200 since no edit context will have been created.
3202 2024-01-18 Richard Biener <rguenther@suse.de>
3204 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
3205 operands vector.
3207 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3209 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
3210 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
3212 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3213 Jin Ma <jinma@linux.alibaba.com>
3214 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3215 Christoph Müllner <christoph.muellner@vrull.eu>
3217 * config/riscv/thead.cc
3218 (th_asm_output_opcode): Rewrite some instructions.
3220 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3221 Jin Ma <jinma@linux.alibaba.com>
3222 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3223 Christoph Müllner <christoph.muellner@vrull.eu>
3225 * config/riscv/riscv.md (none,thv,rvv): New attribute.
3226 (no,yes): Add an attribute to disable alternative
3227 for xtheadvector or RVV1.0.
3228 * config/riscv/vector.md:
3229 Disable alternatives that destination register overlaps
3230 source register group for xtheadvector.
3232 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3233 Jin Ma <jinma@linux.alibaba.com>
3234 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3235 Christoph Müllner <christoph.muellner@vrull.eu>
3237 * config/riscv/riscv-vector-builtins-bases.cc
3238 (class th_loadstore_width): Define new builtin bases.
3239 (class th_extract): Define new builtin bases.
3240 (BASE): Define new builtin bases.
3241 * config/riscv/riscv-vector-builtins-bases.h:
3242 Define new builtin class.
3243 * config/riscv/riscv-vector-builtins-shapes.cc
3244 (struct th_loadstore_width_def): Define new builtin shapes.
3245 (struct th_indexed_loadstore_width_def):
3246 Define new builtin shapes.
3247 (struct th_extract_def): Define new builtin shapes.
3248 (SHAPE): Define new builtin shapes.
3249 * config/riscv/riscv-vector-builtins-shapes.h:
3250 Define new builtin shapes.
3251 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
3252 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
3253 * config/riscv/riscv-vector-builtins.h
3254 (enum required_ext): Add new XTheadVector member.
3255 (struct function_group_info): Likewise.
3256 * config/riscv/t-riscv:
3257 Add thead-vector-builtins-functions.def
3258 * config/riscv/thead-vector.md
3259 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
3260 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
3261 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
3262 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
3263 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
3264 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
3265 (@pred_th_extract<mode>): Likewise.
3266 (*pred_th_extract<mode>): Likewise.
3267 * config/riscv/thead-vector-builtins-functions.def: New file.
3269 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3270 Jin Ma <jinma@linux.alibaba.com>
3271 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3272 Christoph Müllner <christoph.muellner@vrull.eu>
3274 * config.gcc: Add files for XTheadVector intrinsics.
3275 * config/riscv/autovec.md: Guard XTheadVector.
3276 * config/riscv/predicates.md: Disable immediate vl
3277 for XTheadVector.
3278 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
3279 Add pragma for XTheadVector.
3280 * config/riscv/riscv-string.cc (riscv_expand_block_move):
3281 Guard XTheadVector.
3282 * config/riscv/riscv-v.cc (vls_mode_valid_p):
3283 Avoid autovec.
3284 * config/riscv/riscv-vector-builtins-bases.cc:
3285 Do not normalize vsetvl instructions for XTheadVector.
3286 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
3287 New check type function.
3288 (build_one): Adjust for XTheadVector.
3289 * config/riscv/riscv-vector-switch.def (ENTRY):
3290 Disable fractional mode for the XTheadVector extension.
3291 (TUPLE_ENTRY): Likewise.
3292 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
3293 Guard XTheadVector.
3294 (riscv_preferred_simd_mode): Likewsie.
3295 (riscv_autovectorize_vector_modes): Likewise.
3296 (riscv_vector_mode_supported_any_target_p): Likewise.
3297 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
3298 * config/riscv/thead.cc (th_asm_output_opcode):
3299 Rewrite vsetvl instructions.
3300 * config/riscv/vector.md:
3301 Include thead-vector.md and change fractional LMUL
3302 into 1 for vbool.
3303 * config/riscv/riscv_th_vector.h: New file.
3304 * config/riscv/thead-vector.md: New file.
3306 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3307 Jin Ma <jinma@linux.alibaba.com>
3308 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3309 Christoph Müllner <christoph.muellner@vrull.eu>
3311 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
3312 Add new function to add assembler insn code prefix/suffix.
3313 (th_asm_output_opcode):
3314 Add Thead function to add assembler insn code prefix/suffix.
3315 * config/riscv/riscv.cc (riscv_asm_output_opcode):
3316 Implement function to add assembler insn code prefix/suffix.
3317 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
3318 Add new function to add assembler insn code prefix/suffix.
3319 * config/riscv/thead.cc (th_asm_output_opcode):
3320 Implement Thead function to add assembler insn code
3321 prefix/suffix.
3323 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3324 Jin Ma <jinma@linux.alibaba.com>
3325 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3326 Christoph Müllner <christoph.muellner@vrull.eu>
3328 * common/config/riscv/riscv-common.cc
3329 (riscv_subset_list::parse): Add new vendor extension.
3330 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
3331 Add test marco.
3332 * config/riscv/riscv.opt: Add new mask.
3334 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3336 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
3337 to be conditional on macosx-version-min.
3339 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3341 * config/darwin.cc (darwin_objc1_section): Use the correct
3342 meta-data version for constant strings.
3343 (machopic_select_section): Assert if we fail to handle CFString
3344 sections as Obejctive-C meta-data or drectly.
3346 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3348 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
3349 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
3350 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
3351 versions when the object format is Mach-O.
3353 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3355 PR target/105522
3356 * config/darwin.cc (machopic_select_section): Handle C and C++
3357 CFStrings.
3358 (darwin_rename_builtins): Move this out of the CFString code.
3359 (darwin_libc_has_function): Likewise.
3360 (darwin_build_constant_cfstring): Create an anonymous var to
3361 hold each CFString.
3362 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
3363 CFstrings.
3365 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
3367 PR bootstrap/113445
3368 * haifa-sched.cc (dep_list_size): Make global.
3369 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
3370 * sched-int.h (dep_list_size): Declare.
3372 2024-01-18 Martin Jambor <mjambor@suse.cz>
3374 PR tree-optimization/110422
3375 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
3376 gotos.
3378 2024-01-18 Richard Biener <rguenther@suse.de>
3380 PR tree-optimization/113475
3381 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
3382 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
3383 (phi_analyzer::~phi_analyzer): Deallocate and free collected
3384 phi_grous.
3385 (phi_analyzer::process_phi): Record allocated phi_groups.
3387 2024-01-18 Richard Biener <rguenther@suse.de>
3389 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
3390 storage for gvec_oprnds elements.
3392 2024-01-18 Richard Biener <rguenther@suse.de>
3394 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
3395 prefer all later exits we can handle.
3396 (vect_analyze_loop_form): Free the allocated loop body.
3397 Adjust comments.
3399 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3401 * config/avr/avr-log.cc: Tabify.
3403 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3405 * config/riscv/autovec.md: Support vi variant.
3407 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3409 * config/avr/avr-devices.cc: Tabify.
3411 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3413 * config/avr/avr-c.cc: Tabify.
3415 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3417 * config/avr/driver-avr.cc: Tabify.
3419 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3421 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
3423 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3425 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
3427 2024-01-18 Jakub Jelinek <jakub@redhat.com>
3429 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
3430 minline-strcmp, minline-strncmp, minline-strlen,
3431 -param=riscv-vector-abi): Remove Bool keywords.
3433 2024-01-18 Jakub Jelinek <jakub@redhat.com>
3435 PR target/113122
3436 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
3437 support. Add missing space after , in emitted assembly in some
3438 cases. Formatting fixes.
3440 2024-01-18 Xi Ruoyao <xry111@xry111.site>
3442 * config/loongarch/loongarch.md (movsi_internal): Remove
3443 constraint z.
3445 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3447 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
3448 in the diagnostic, and capitalize the device name.
3449 (print_mcu): Generate specs such that:
3450 <*check_rodata_in_ram>: New.
3451 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
3452 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
3453 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
3455 2024-01-18 Jakub Jelinek <jakub@redhat.com>
3457 PR other/113399
3458 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
3459 Common and Optimization.
3461 2024-01-18 Richard Biener <rguenther@suse.de>
3463 PR tree-optimization/113431
3464 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
3465 When there is an invariant load we might not preserve
3466 scalar order.
3468 2024-01-18 Richard Biener <rguenther@suse.de>
3470 PR tree-optimization/113374
3471 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
3472 * tree-vect-loop.cc (move_early_exit_stmts): Update
3473 virtual LC PHIs.
3474 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3475 Refactor. Preserve virtual LC PHIs on all exits.
3477 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
3479 * config/loongarch/loongarch.cc (loongarch_split_symbol):
3480 Assign the '/u' attribute to the mem.
3482 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3484 PR middle-end/110847
3485 * doc/invoke.texi (Option Summary): Document negative forms of
3486 -Wtsan and -Wxor-used-as-pow.
3487 (Warning Options): Likewise.
3489 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3491 PR target/113429
3492 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
3494 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3496 * doc/extend.texi (Common Function Attributes): Re-alphabetize
3497 the table.
3498 (Common Variable Attributes): Likewise.
3499 (Common Type Attributes): Likewise.
3501 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
3503 PR middle-end/111659
3504 * doc/extend.texi (Common Variable Attributes): Fix long lines
3505 in documentation of strict_flex_array + other minor copy-editing.
3506 Add a cross-reference to -Wstrict-flex-arrays.
3507 * doc/invoke.texi (Option Summary): Fix whitespace in tables
3508 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
3509 (C Dialect Options): Combine the docs for the two
3510 -fstrict-flex-arrays forms into a single entry. Note this option
3511 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
3512 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
3513 Minor copy-editing. Add cross references to the strict_flex_array
3514 attribute and -fstrict-flex-arrays option. Add note that this
3515 option depends on -ftree-vrp.
3517 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
3519 PR target/113221
3520 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
3521 only allow REG operands instead of allowing all.
3523 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
3525 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
3526 Remove redundant checks in else condition for readablity.
3527 (earliest_fuse_vsetvl_info) Print iteration count in debug
3528 prints.
3529 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
3530 dump details in certain cases.
3532 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
3534 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
3535 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
3536 * config/riscv/riscv-vsetvl.cc
3537 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
3538 (pass_vsetvl::execute): Use vsetvl_strategy.
3540 2024-01-17 Jan Hubicka <jh@suse.cz>
3542 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
3543 accidental hack reseting offset.
3545 2024-01-17 Jan Hubicka <jh@suse.cz>
3547 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
3548 handling of X86_TUNE_AVOID_512FMA_CHAINS.
3550 2024-01-17 Jan Hubicka <jh@suse.cz>
3551 Jakub Jelinek <jakub@redhat.com>
3553 PR tree-optimization/110852
3554 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
3555 binary operations
3556 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
3557 PRED_COMBINED_VALUE_PREDICTIONS_PHI
3558 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
3559 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
3561 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3563 PR tree-optimization/113421
3564 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
3565 comment.
3566 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
3567 formatting. Start at vop rather than cvop even if stmt is a store
3568 and needs_operand_addr.
3570 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3572 PR middle-end/113410
3573 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
3574 If access_nelts is integral with larger precision than sizetype,
3575 fold_convert it to sizetype.
3577 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3579 PR tree-optimization/113408
3580 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
3581 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
3582 to handle_cast.
3584 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3586 PR middle-end/113406
3587 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
3588 regardless of whether is_gimple_reg_type (restype) or not.
3590 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3592 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
3593 funcions -> functions, and use were instead of was.
3594 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
3595 and guaranteee -> guarantee.
3596 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
3598 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3600 PR middle-end/113409
3601 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
3602 INTEGER_TYPE.
3603 (omp_extract_for_data): Use build_bitint_type rather than
3604 build_nonstandard_integer_type if either iter_type or loop->v type
3605 is BITINT_TYPE.
3606 * omp-expand.cc (expand_omp_for_generic,
3607 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
3608 BITINT_TYPE like INTEGER_TYPE.
3610 2024-01-17 Richard Biener <rguenther@suse.de>
3612 PR tree-optimization/113371
3613 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
3614 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
3615 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
3616 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
3618 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
3620 PR rtl-optimization/96388
3621 PR rtl-optimization/111554
3622 * sched-deps.cc (find_inc): Avoid exponential behavior.
3624 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
3626 PR c/111693
3627 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
3628 from C++ Language Options to Warning Options. Add entry for
3629 -Wuse-after-free.
3630 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
3631 from here....
3632 (Warning Options): ...to here. Minor copy-editing to fix typo
3633 and grammar.
3635 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
3637 * config/mips/mips.cc (mips_compute_frame_info): If another
3638 register is used as global_pointer, mark $GP live false.
3640 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
3642 PR target/112973
3643 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
3644 give the section a light copy-editing pass.
3646 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
3648 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
3649 * config/aarch64/aarch64-tune.md: Regenerated.
3650 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
3652 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
3654 PR target/112573
3655 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
3656 badly formed CONST expressions.
3658 2024-01-16 Daniel Cederman <cederman@gaisler.com>
3660 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
3662 2024-01-16 Daniel Cederman <cederman@gaisler.com>
3664 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
3665 * config/sparc/sync.md (membar_storeload): Turn into named insn
3666 and add GR712RC errata workaround.
3667 (membar_v8): Add GR712RC errata workaround.
3669 2024-01-16 Andreas Larsson <andreas@gaisler.com>
3671 * config/sparc/sync.md (*membar_storeload_leon3): Remove
3672 (*membar_storeload): Enable for LEON
3674 2024-01-16 Jakub Jelinek <jakub@redhat.com>
3676 PR tree-optimization/113372
3677 PR middle-end/90348
3678 PR middle-end/110115
3679 PR middle-end/111422
3680 * cfgexpand.cc (add_scope_conflicts_2): New function.
3681 (add_scope_conflicts_1): Use it.
3683 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
3685 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
3686 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
3687 * doc/avr-mmcu.texi: Regenerate.
3689 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
3691 PR tree-optimization/113091
3692 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
3693 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
3694 scalar use with new function.
3695 (vect_bb_slp_mark_live_stmts): New function as entry to existing
3696 overriden functions with same name.
3697 (vect_slp_analyze_operations): Call new entry function to mark
3698 live statements.
3700 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3702 PR target/113404
3703 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
3704 for RVV in big-endian mode.
3706 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
3708 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
3709 (riscv_pass_in_vector_p): Delete.
3710 (riscv_init_cumulative_args): Delete the checking.
3711 (riscv_get_arg_info): Delete the checking.
3712 (riscv_function_value): Delete the checking.
3713 * config/riscv/riscv.h: Delete the member for checking.
3715 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
3717 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
3719 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
3721 * config.gcc: Include riscv_bitmanip.h.
3722 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
3723 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
3724 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
3725 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
3726 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
3727 * config/riscv/riscv-ftypes.def (2): New ftypes.
3728 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
3729 (RISCV_BUILTIN_NO_PREFIX): Likewise.
3730 * config/riscv/riscv_bitmanip.h: New file.
3732 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
3734 * config.gcc: Include riscv_crypto.h.
3735 * config/riscv/riscv_crypto.h: New file.
3737 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
3739 PR middle-end/113354
3740 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
3741 in the insn if the corresponding operand does not require hard
3742 register anymore.
3744 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
3746 PR target/107201
3747 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
3748 * config/avr/driver-avr.cc (avr_no_devlib): New function.
3749 (avr_devicespecs_file): Use it to remove -nodevicelib from the
3750 options for cores only.
3751 * config/avr/avr-arch.h (avr_get_parch): New prototype.
3752 * config/avr/avr-devices.cc (avr_get_parch): New function.
3754 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3756 PR target/113247
3757 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
3758 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
3759 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
3761 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3763 PR target/113281
3764 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
3765 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
3766 * config/riscv/riscv-vector-costs.h: New function.
3768 2024-01-15 Richard Biener <rguenther@suse.de>
3770 PR tree-optimization/113385
3771 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3772 First redirect, then split the exit edge.
3774 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3776 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
3777 Remove m_num_vector_iterations.
3778 * config/riscv/riscv-vector-costs.h: Ditto.
3780 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
3782 PR target/113156
3783 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
3784 (-mbranch-cost): Set "Optimization" flag.
3786 2024-01-15 Jakub Jelinek <jakub@redhat.com>
3788 PR tree-optimization/113370
3789 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
3790 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
3791 set it to just prec % limb_prec.
3793 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3795 PR target/113393
3796 * config/riscv/vector.md: Fix ternary attributes.
3798 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
3800 PR target/112944
3801 * configure.ac [target=avr]: Check availability of emulations
3802 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
3803 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
3804 * configure: Regenerate.
3805 * config.in: Regenerate.
3806 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
3807 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
3808 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
3809 * config/avr/avr-arch.h (enum avr_device_specific_features):
3810 Add AVR_ISA_FLMAP.
3811 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
3812 AVR_ISA_FLMAP.
3813 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
3814 (avr_set_core_architecture): Set avr_arch_index.
3815 (have_avrxmega2_flmap, have_avrxmega4_flmap)
3816 (have_avrxmega3_rodata_in_flash): Set new static const bool according
3817 to configure results.
3818 (avr_rodata_in_flash_p): New function using them.
3819 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
3820 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
3821 (avr_asm_named_section): Track avr_has_rodata_p.
3822 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
3823 and not avr_rodata_in_flash_p ().
3824 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
3825 (LINK_SPEC): Add %(link_rodata_in_ram).
3826 (LINK_ARCH_SPEC): Remove.
3827 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
3828 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
3829 const bool according to configure results.
3830 (diagnose_mrodata_in_ram): New function.
3831 (print_mcu): Generate specs with the following changes:
3832 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
3833 need to extend avr/specs.h each time we add a new bell or whistle.
3834 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
3835 -m[no-]rodata-in-ram.
3836 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
3837 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
3838 <*cpp>: Add %(cpp_rodata_in_ram).
3839 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
3840 requested.
3841 <*self_spec>: Add -mflmap or %<mflmap as needed.
3843 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
3845 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
3846 not the GPR iterator. Adjust pattern name and mode attribute
3847 accordingly.
3849 2024-01-13 Jakub Jelinek <jakub@redhat.com>
3851 PR tree-optimization/113361
3852 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
3853 Fix up determination of the type for > limb_prec constants.
3855 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
3857 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
3858 Add web-link to the avr-gcc wiki.
3860 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
3862 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
3863 documentation for a version without argument, which is not supported.
3865 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3867 * config/arm/arm_neon.h
3868 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
3869 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
3870 (vld1_f16_x4, vld1_f32_x4): New.
3871 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
3872 (vld1_bf16_x4): New.
3873 (vld1q_types_x4): Updated to use vld1q_x4
3874 from arm_neon_builtins.def
3875 * config/arm/arm_neon_builtins.def
3876 (vld1_x4): Updated entries.
3877 (vld1q_x4): New entries, but comes from the old vld1_x4
3878 * config/arm/neon.md
3879 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
3881 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3883 * config/arm/arm_neon.h
3884 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
3885 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
3886 (vld1_f16_x3, vld1_f32_x3): New.
3887 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
3888 (vld1_bf16_x3): New.
3889 (vld1q_types_x3): Updated to use vld1q_x3 from
3890 arm_neon_builtins.def
3891 * config/arm/arm_neon_builtins.def
3892 (vld1_x3): Updated entries.
3893 (vld1q_x3): New entries, but comes from the old vld1_x2
3894 * config/arm/neon.md
3895 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
3897 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3899 * config/arm/arm_neon.h
3900 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
3901 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
3902 (vld1_f16_x2, vld1_f32_x2): New.
3903 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
3904 (vld1_bf16_x2): New.
3905 (vld1q_types_x2): Updated to use vld1q_x2 from
3906 arm_neon_builtins.def
3907 * config/arm/arm_neon_builtins.def
3908 (vld1_x2): Updated entries.
3909 (vld1q_x2): New entries, but comes from the old vld1_x2
3910 * config/arm/neon.md
3911 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
3912 neon_vld1_x2<mode>.
3914 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3916 * config/arm/arm_neon.h
3917 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
3918 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
3919 (vst1q_f16_x4, vst1q_f32_x4): New.
3920 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
3921 (vst1q_bf16_x4): New.
3922 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
3923 * config/arm/neon.md
3924 (neon_vst1q_x4<mode>): New.
3925 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
3926 * config/arm/unspecs.md
3927 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
3929 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3931 * config/arm/arm_neon.h
3932 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
3933 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
3934 (vst1q_f16_x3, vst1q_f32_x3): New.
3935 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
3936 (vst1q_bf16_x3): New.
3937 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
3938 * config/arm/neon.md
3939 (neon_vst1q_x3<mode>): New.
3940 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
3941 * config/arm/unspecs.md
3942 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
3944 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3946 * config/arm/arm_neon.h
3947 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
3948 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
3949 (vst1q_f16_x2, vst1q_f32_x2): New.
3950 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
3951 (vst1q_bf16_x2): New.
3952 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
3953 * config/arm/neon.md
3954 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
3955 neon_vst1_x2<mode>.
3956 * config/arm/iterators.md
3957 (VMEMX2): New mode iterator.
3958 (VMEMX2_q): New mode attribute.
3960 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3962 * config/arm/arm_neon.h
3963 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
3964 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
3965 (vst1_f16_x4, vst1_f32_x4): New.
3966 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
3967 (vst1_bf16_x4): New.
3968 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
3969 * config/arm/neon.md (vst1_x4<mode>): New.
3971 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3973 * config/arm/arm_neon.h
3974 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
3975 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
3976 (vst1_f16_x3, vst1_f32_x3): New.
3977 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
3978 (vst1_bf16_x3): New.
3979 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
3980 * config/arm/neon.md (vst1_x3<mode>): New.
3982 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3984 * config/arm/arm_neon.h
3985 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
3986 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
3987 (vst1_f16_x2, vst1_f32_x2): New.
3988 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
3989 (vst1_bf16_x2): New.
3990 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
3991 * config/arm/neon.md (vst1_x2<mode>): New.
3993 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3995 * config/arm/arm_neon.h
3996 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
3997 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
3998 (vld1q_f16_x4, vld1q_f32_x4): New.
3999 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
4000 (vld1q_bf16_x4): New.
4001 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
4002 * config/arm/neon.md
4003 (neon_vld1_x4<mode>): New.
4004 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
4005 * config/arm/unspecs.md
4006 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
4008 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4010 * config/arm/arm_neon.h
4011 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
4012 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
4013 (vld1q_f16_x3, vld1q_f32_x3): New.
4014 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
4015 (vld1q_bf16_x3): New.
4016 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
4017 * config/arm/neon.md
4018 (neon_vld1_x3<mode>): New.
4019 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
4020 * config/arm/unspecs.md
4021 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
4023 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4025 * config/arm/arm_neon.h
4026 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
4027 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
4028 (vld1q_f16_x2, vld1q_f32_x2): New.
4029 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
4030 (vld1q_bf16_x2): New.
4031 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
4032 * config/arm/neon.md (vld1_x2<mode>): New.
4034 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4036 PR tree-optimization/113287
4037 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
4039 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4041 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
4042 * tree-vect-loop.cc (vect_transform_loop): Likewise.
4044 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4046 PR tree-optimization/113178
4047 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
4048 alternate exits.
4050 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4052 PR tree-optimization/113237
4053 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
4054 existing LCSSA variable for exit when all exits are early break.
4056 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4058 PR tree-optimization/113137
4059 PR tree-optimization/113136
4060 PR tree-optimization/113172
4061 PR tree-optimization/113178
4062 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4063 Maintain PHIs on inverted loops.
4064 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
4065 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
4066 latch.
4067 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
4069 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4071 PR tree-optimization/113135
4072 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
4073 dependency analysis.
4075 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
4077 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
4078 diagnostics class member name for abort of error.
4080 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4082 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
4083 format string to %s argument.
4085 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
4086 Jakub Jelinek <jakub@redhat.com>
4088 PR middle-end/113182
4089 * varasm.cc (process_pending_assemble_externals,
4090 assemble_external_libcall): Use targetm.strip_name_encoding
4091 before calling get_identifier.
4093 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4095 PR target/113196
4096 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
4097 New member variable.
4098 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
4099 Declare.
4100 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
4101 * config/aarch64/aarch64-simd.md
4102 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
4103 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
4104 zip2 for zero-extends to...
4105 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
4106 instruction. Fix big-endian handling.
4107 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
4108 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
4109 zip1 for zero-extends to...
4110 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
4111 Fix big-endian handling.
4112 (*aarch64_zip1_uxtl): New pattern.
4113 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
4114 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
4115 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
4116 (aarch64_gen_shareable_zero): Use it.
4117 (aarch64_split_simd_shift_p): New function.
4119 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4121 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
4122 (function_beg_insn): New macro.
4123 * function.cc (expand_function_start): Initialize function_beg_insn.
4125 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4127 PR target/112989
4128 * config/aarch64/aarch64-sve-builtins.h
4129 (function_builder::m_overload_names): Replace with...
4130 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
4131 new global.
4132 (add_overloaded_function): Update accordingly, using get_identifier
4133 to get a GGC-friendly record of the name.
4135 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4137 PR target/112989
4138 * config/aarch64/aarch64-sve-builtins.def: Don't include
4139 aarch64-sve-builtins-sme.def.
4140 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
4141 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
4142 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
4143 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
4144 requires AARCH64_FL_SME2.
4145 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
4146 AARCH64_FL_SME adjustment here.
4147 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
4148 include SME intrinsics.
4149 (sme_function_groups): New array.
4150 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
4151 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
4153 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4155 PR target/113281
4156 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
4157 (struct cpu_vector_cost): Add regmove struct.
4158 (get_vector_costs): Export as global.
4159 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
4160 (costs::add_stmt_cost): Ditto.
4161 * config/riscv/riscv.cc (get_common_costs): Export global function.
4163 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4165 PR tree-optimization/113334
4166 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
4167 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
4168 to determine if number should be extended by all ones rather than zero
4169 extended.
4171 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4173 PR tree-optimization/113330
4174 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
4175 too large size.
4177 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4179 PR tree-optimization/113323
4180 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
4181 check for lhs being large/huge _BitInt not in m_names.
4183 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4185 PR tree-optimization/113316
4186 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
4187 uninitialized large/huge _BitInt arguments to calls.
4189 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4191 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
4192 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
4193 CEIL (TYPE_PRECISION (t), limb_prec).
4194 (bitint_large_huge::handle_cast): Likewise.
4196 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
4198 PR sanitizer/113284
4199 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
4200 Use assemble_function_label_final () for Power ELF V1 ABI.
4201 * output.h (assemble_function_label_final): New function.
4202 * varasm.cc (assemble_function_label_raw): Use
4203 assemble_function_label_final ().
4204 (assemble_function_label_final): New function.
4206 2024-01-12 Richard Biener <rguenther@suse.de>
4208 PR middle-end/113344
4209 * match.pd ((double)float CMP (double)float -> float CMP float):
4210 Perform result type check only for vectors.
4211 * fold-const.cc (fold_binary_loc): Likewise.
4213 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
4215 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
4216 (usdot_prod<mode>): Ditto.
4217 (sdot_prod<mode>): Ditto.
4218 (udot_prod<mode>): Ditto.
4220 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
4222 PR target/113288
4223 * config/i386/i386-c.cc (ix86_target_macros_internal):
4224 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
4226 2024-01-12 Richard Biener <rguenther@suse.de>
4228 PR target/112280
4229 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
4230 Do not generate code when d.testing_p.
4232 2024-01-12 liuhongt <hongtao.liu@intel.com>
4234 PR target/113039
4235 * doc/invoke.texi (fcf-protection=): Update documents.
4237 2024-01-12 Pan Li <pan2.li@intel.com>
4239 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
4240 comments of predicate func riscv_v_ext_mode_p.
4242 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
4244 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
4245 Modify ABI-name length of vfloat16m8_t
4247 2024-01-12 Li Wei <liwei@loongson.cn>
4249 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
4250 Adjust.
4252 2024-01-12 Li Wei <liwei@loongson.cn>
4254 * config/loongarch/loongarch.md (add<mode>3): Removed.
4255 (*addsi3): New.
4256 (addsi3): Ditto.
4257 (adddi3): Ditto.
4258 (*addsi3_extended): Removed.
4259 (addsi3_extended): New.
4261 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
4263 * config/riscv/thead.md: Add limits for splits.
4265 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
4267 PR middle-end/113322
4268 * expr.cc (do_store_flag): Don't try single bit tests with
4269 comparison on vector types.
4271 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
4273 PR tree-optimization/113301
4274 * match.pd (`1/x`): Delay signed case until late.
4276 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
4278 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
4279 and -msp8 to...
4280 (AVR Internal Options): ...this new @subsubsection.
4282 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
4284 PR rtl-optimization/112918
4285 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
4286 (in_class_p): Restrict condition for narrowing class in case of
4287 allow_all_reload_class_changes_p.
4288 (process_alt_operands): Try to match operand without and with
4289 narrowing reg class. Discourage narrowing the class. Finish insn
4290 matching only if there is no class narrowing.
4291 (curr_insn_transform): Pass true to in_class_p for reg operand win.
4293 2024-01-11 Richard Biener <rguenther@suse.de>
4295 PR tree-optimization/112505
4296 * tree-vect-loop.cc (vectorizable_induction): Reject
4297 bit-precision induction.
4299 2024-01-11 Richard Biener <rguenther@suse.de>
4301 PR tree-optimization/113126
4302 * match.pd ((double)float CMP (double)float -> float CMP float):
4303 Make sure the boolean type is the same.
4304 * fold-const.cc (fold_binary_loc): Likewise.
4306 2024-01-11 Richard Biener <rguenther@suse.de>
4308 PR tree-optimization/112636
4309 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
4310 estimate_numbers_of_iterations before querying
4311 get_max_loop_iterations_int.
4312 (pass_ch::execute): Initialize SCEV and loops appropriately.
4314 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
4316 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
4317 Reduced Tiny.
4318 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
4319 * doc/extend.texi (AVR Variable Attributes): Improve documentation
4320 of io, io_low and address attributes.
4321 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
4322 * doc/avr-mmcu.texi: Rebuild.
4324 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
4326 PR target/113233
4327 * config/loongarch/genopts/loongarch.opt.in: Mark options with
4328 the "Save" property.
4329 * config/loongarch/loongarch.opt: Same.
4330 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
4331 according to la_target.
4332 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
4333 RESTORE} for the la_target structure; Rename option conditions
4334 to have the same "la_" prefix.
4335 * config/loongarch/loongarch.h: Same.
4337 2024-01-11 Pan Li <pan2.li@intel.com>
4339 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
4340 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
4342 2024-01-11 Alex Coplan <alex.coplan@arm.com>
4344 PR target/113077
4345 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
4346 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
4347 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
4348 synthesize these if needed. Update caller ...
4349 (ldp_bb_info::fuse_pair): ... here.
4350 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
4351 and either insn is frame-related.
4352 (find_trailing_add): Punt on frame-related insns.
4353 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
4354 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
4356 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
4358 * config/mips/mips.cc (mips_start_function_definition):
4359 Add ATTRIBUTE_UNUSED.
4361 2024-01-11 Richard Biener <rguenther@suse.de>
4363 PR middle-end/112740
4364 * expr.cc (store_constructor): Check the integer vector
4365 mask has a single bit per element before using sign-extension
4366 to expand an uniform vector.
4368 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4370 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
4371 preempt VLS on unknown NITERS loop.
4373 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
4375 * doc/invoke.texi: Add -mevex512.
4377 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
4379 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
4380 (*nor<mode>3): Likewise.
4381 (nor<mode>3): Likewise.
4382 (*negsi2_extended): New template.
4383 (*<optab>si3_internal): Likewise.
4384 (*one_cmplsi2_internal): Likewise.
4385 (*norsi3_internal): Likewise.
4386 (*<optab>nsi_internal): Likewise.
4387 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
4388 modified bit operation to make the optimization work.
4390 2024-01-11 liuhongt <hongtao.liu@intel.com>
4392 PR target/104401
4393 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
4395 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4397 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
4398 (get_vector_costs): Ditto.
4399 (riscv_builtin_vectorization_cost): Ditto.
4401 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4403 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
4405 2024-01-10 Antoni Boucher <bouanto@zoho.com>
4407 PR jit/111396
4408 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
4409 ipa_free_size_summary.
4410 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
4411 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
4412 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
4413 * ipa-prop.h (ipa_prop_cc_finalize): New function.
4414 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
4415 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
4416 ipa_sra_cc_finalize): New functions.
4417 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
4418 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
4419 ipa_sra_cc_finalize
4420 Include ipa-utils.h.
4422 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
4424 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
4425 (th_int_get_save_adjustment): Likewise.
4426 (th_int_adjust_cfi_prologue): Likewise.
4427 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
4428 (TH_INT_INTERRUPT): New macro.
4429 (riscv_expand_prologue): Add the processing of XTheadInt.
4430 (riscv_expand_epilogue): Likewise.
4431 * config/riscv/riscv.h (BITSET_P): Moved to here.
4432 * config/riscv/riscv.md: New unspec.
4433 * config/riscv/thead.cc (th_int_get_mask): New function.
4434 (th_int_get_save_adjustment): Likewise.
4435 (th_int_adjust_cfi_prologue): Likewise.
4436 * config/riscv/thead.md (th_int_push): New pattern.
4437 (th_int_pop): new pattern.
4439 2024-01-10 Tamar Christina <tamar.christina@arm.com>
4441 PR tree-optimization/112468
4442 * doc/sourcebuild.texi: Document ifn_copysign.
4443 * match.pd: Only apply transformation if target supports the IFN.
4445 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
4447 PR tree-optimization/112581
4448 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
4449 mark_ssa_maybe_undefs.
4450 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
4451 variables can not be reassociated.
4452 (init_range_entry): Check for uninitialized variables too.
4453 (init_reassoc): Call mark_ssa_maybe_undefs.
4455 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
4457 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
4458 Also handle sign extension.
4460 2024-01-10 Alex Coplan <alex.coplan@arm.com>
4462 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4463 to 0.
4464 (-mlate-ldp-fusion): Likewise.
4466 2024-01-10 Tamar Christina <tamar.christina@arm.com>
4468 PR tree-optimization/113287
4469 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
4470 instead of using BRANCH_EDGE to determine true edge.
4472 2024-01-10 Richard Biener <rguenther@suse.de>
4474 PR tree-optimization/113078
4475 * tree-vect-loop.cc (check_reduction_path): Canonicalize
4476 .COND_SUB to .COND_ADD.
4478 2024-01-10 David Malcolm <dmalcolm@redhat.com>
4480 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
4481 Handle prefix mappings before calling find_opt.
4482 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
4483 "-fno-"-prefixed command-line option.
4484 * opts-common.cc (get_option_prefix_remapping): New.
4485 * opts.h (get_option_prefix_remapping): New decl.
4487 2024-01-10 David Malcolm <dmalcolm@redhat.com>
4489 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
4490 m_urlifier to pp_output_formatted_text.
4491 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
4492 (obstack_append_string): New overload, taking a length.
4493 (urlify_quoted_string): Pass in an obstack ptr, rather than using
4494 that of the pp's buffer. Generalize to handle trailing text in
4495 the buffer beyond the run of quoted text.
4496 (class quoting_info): New.
4497 (on_begin_quote): New.
4498 (on_end_quote): New.
4499 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
4500 it to calls to on_begin_quote and on_end_quote.
4501 (struct auto_obstack): New.
4502 (quoting_info::handle_phase_3): New.
4503 (pp_output_formatted_text): Add urlifier param. Use it if there
4504 is deferred urlification. Delete m_quotes.
4505 (selftest::pp_printf_with_urlifier): Pass urlifier to
4506 pp_output_formatted_text.
4507 (selftest::test_urlification): Update results for the existing
4508 case of quoted text stradding chunks; add more such test cases.
4509 * pretty-print.h (class quoting_info): New forward decl.
4510 (chunk_info::m_quotes): New field.
4511 (pp_output_formatted_text): Add optional urlifier param.
4513 2024-01-10 David Malcolm <dmalcolm@redhat.com>
4515 * pretty-print.cc (selftest::test_pp_format): Add selftest
4516 coverage for numbered args.
4518 2024-01-10 Tamar Christina <tamar.christina@arm.com>
4520 PR tree-optimization/113144
4521 PR tree-optimization/113145
4522 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4523 Update all BB that the original exits dominated.
4525 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
4527 * dwarf2out.cc (modified_type_die): Extend the support of reverse
4528 storage order to enumeration types if -gstrict-dwarf is not passed.
4529 (gen_enumeration_type_die): Add REVERSE parameter and generate the
4530 DIE immediately after the existing one if it is true.
4531 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
4532 call to gen_enumeration_type_die.
4533 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
4534 first recursive call as well as the call to gen_tagged_type_die.
4535 (gen_type_die): Add REVERSE parameter and pass it in the call to
4536 gen_type_die_with_usage.
4538 2024-01-10 Jakub Jelinek <jakub@redhat.com>
4540 PR tree-optimization/113120
4541 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
4542 with root->size TYPE_PRECISION don't build anything new.
4543 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
4544 rather than build_nonstandard_integer_type.
4546 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
4548 * config/i386/i386.opt: Adjust document.
4549 * doc/invoke.texi: Add description for
4550 -mapx-inline-asm-use-gpr32.
4552 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4554 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
4555 (avg<v_double_trunc>3_floor): New pattern.
4556 (<u>avg<v_double_trunc>3_ceil): Remove.
4557 (avg<v_double_trunc>3_ceil): New pattern.
4558 (uavg<mode>3_floor): Ditto.
4559 (uavg<mode>3_ceil): Ditto.
4560 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
4561 (enum insn_type): Ditto.
4562 * config/riscv/riscv-v.cc: Ditto.
4563 * config/riscv/vector-iterators.md (ashiftrt): Remove.
4564 (ASHIFTRT): Ditto.
4565 * config/riscv/vector.md: Add VLS modes.
4567 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
4569 PR target/111480
4570 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
4571 (vczlsbb_char): New int attribute.
4572 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
4573 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
4574 (*vctzlsbb_zext_<mode>): Rename to ...
4575 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
4576 cover vclzlsbb.
4578 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
4580 PR target/112606
4581 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
4582 of the last argument from altivec_register_operand to any_operand. If
4583 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
4584 otherwise if it doesn't satisfy altivec_register_operand, force it to
4585 REG using copy_to_mode_reg.
4587 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
4589 PR middle-end/113100
4590 * builtins.cc (expand_builtin_stack_address): Guard stack point
4591 adjustment with SPARC_STACK_BOUNDARY_HACK.
4593 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4595 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
4596 argument string definitions.
4597 * config/loongarch/loongarch-str.h: Same.
4598 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
4599 as aliases to -mexplicit-relocs={always,none}
4600 * config/loongarch/loongarch.opt: Regenerate.
4601 * config/loongarch/loongarch.cc: Same.
4603 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4605 * config/loongarch/loongarch-def.h: Define constants with
4606 enums instead of Macros.
4608 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4610 * config/loongarch/genopts/loongarch-strings: Rename.
4611 * config/loongarch/genopts/loongarch.opt.in: Same.
4612 * config/loongarch/loongarch-cpu.cc: Same.
4613 * config/loongarch/loongarch-def.cc: Same.
4614 * config/loongarch/loongarch-def.h: Same.
4615 * config/loongarch/loongarch-opts.cc: Same.
4616 * config/loongarch/loongarch-opts.h: Same.
4617 * config/loongarch/loongarch-str.h: Same.
4618 * config/loongarch/loongarch.opt: Same.
4620 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4622 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
4623 variable with the common la_ prefix.
4624 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
4625 flags as saved using TargetVariable.
4626 * config/loongarch/loongarch.opt: Same.
4627 * config/loongarch/loongarch-def.h: Define evolution_set to
4628 mark changes to the -march default.
4629 * config/loongarch/loongarch-driver.cc: Same.
4630 * config/loongarch/loongarch-opts.cc: Same.
4631 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
4632 conditions around the la_target structure.
4633 * config/loongarch/loongarch.cc: Same.
4634 * config/loongarch/loongarch.md: Same.
4635 * config/loongarch/loongarch-builtins.cc: Same.
4636 * config/loongarch/loongarch-c.cc: Same.
4637 * config/loongarch/lasx.md: Same.
4638 * config/loongarch/lsx.md: Same.
4639 * config/loongarch/sync.md: Same.
4641 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
4643 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
4644 no less.
4646 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
4648 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
4650 2024-01-09 Tamar Christina <tamar.christina@arm.com>
4652 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
4653 restart_loop.
4654 (vectorizable_live_operation): Likewise.
4656 2024-01-09 Tamar Christina <tamar.christina@arm.com>
4658 PR tree-optimization/113199
4659 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
4660 BIT_FIELD_REF.
4662 2024-01-09 Jakub Jelinek <jakub@redhat.com>
4664 PR target/113270
4665 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
4666 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
4667 GTY(()) declaration before the definition, drop GTY(()) drom the
4668 definition.
4670 2024-01-09 Richard Biener <rguenther@suse.de>
4672 PR tree-optimization/113026
4673 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
4674 redundant and wrong niter bound setting. Move niter
4675 bound adjustment down.
4677 2024-01-09 Tamar Christina <tamar.christina@arm.com>
4679 PR middle-end/113163
4680 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
4681 Reject non-linear inductions that aren't supported.
4683 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
4685 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
4686 left shift implementation strategies.
4687 (arc_shift_info): Type for each entry of the shift strategy table.
4688 (arc_shift_context_idx): Return a integer value for each code
4689 generation context, used as an index
4690 (arc_ashl_alg): Table indexed by context and shifted bit count.
4691 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
4692 left shift implementation.
4693 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
4694 provide accurate costs, when optimizing for speed or size.
4696 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4698 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
4700 2024-01-09 Julian Brown <julian@codesourcery.com>
4702 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
4703 processed out before gimplification.
4704 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
4705 * tree.def (OMP_ARRAY_SECTION): New tree code.
4707 2024-01-09 Jakub Jelinek <jakub@redhat.com>
4709 PR tree-optimization/113210
4710 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
4711 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
4712 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
4713 minus 1.
4715 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
4717 PR rtl-optimization/113140
4718 * reorg.cc (fill_slots_from_thread): If we are to branch after the
4719 last instruction of the function, create an end label.
4721 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
4722 Hongtao Liu <hongtao.liu@intel.com>
4724 PR target/112992
4725 * config/i386/i386-expand.cc
4726 (ix86_convert_const_wide_int_to_broadcast): Allow call to
4727 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
4728 (ix86_broadcast_from_constant): Revert recent change; Return a
4729 suitable MEMREF independently of mode/target combinations.
4730 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
4731 to decide whether expansion is possible/preferrable. Only try
4732 forcing DImode constants to memory (and trying again) if calling
4733 ix86_expand_vector_init_duplicate fails with an DImode immediate
4734 constant.
4735 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
4736 V4SImode for suitable immediate constants.
4737 <case E_V4DImode>: Try using V8SImode for suitable constants.
4738 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
4739 <case E_V2HImode>: Likewise.
4740 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
4741 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
4742 <label widen>: Handle CONT_INTs via simplify_binary_operation.
4743 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
4744 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
4745 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
4746 (ix86_expand_vector_init): Move try using a broadcast for all_same
4747 with ix86_expand_vector_init_duplicate before using constant pool.
4749 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
4751 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
4753 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
4755 * config/arm/arm-cpus.in (cortex-m52): New cpu.
4756 * config/arm/arm-tables.opt: Regenerate.
4757 * config/arm/arm-tune.md: Regenerate.
4759 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
4761 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
4762 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
4763 (@vec_concatz<mode>): New insn pattern.
4764 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
4765 Handle VALS containing two vectors.
4767 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4769 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
4770 (vundefined): Ditto.
4772 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
4774 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
4775 Add new function_base for crypto vector.
4776 (class bitmanip): Ditto.
4777 (class b_reverse):Ditto.
4778 (class vwsll): Ditto.
4779 (class clmul): Ditto.
4780 (class vg_nhab): Ditto.
4781 (class crypto_vv):Ditto.
4782 (class crypto_vi):Ditto.
4783 (class vaeskf2_vsm3c):Ditto.
4784 (class vsm3me): Ditto.
4785 (BASE): Add BASE declaration for crypto vector.
4786 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
4787 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
4788 Add crypto vector intrinsic definition.
4789 (vbrev): Ditto.
4790 (vclz): Ditto.
4791 (vctz): Ditto.
4792 (vwsll): Ditto.
4793 (vandn): Ditto.
4794 (vbrev8): Ditto.
4795 (vrev8): Ditto.
4796 (vrol): Ditto.
4797 (vror): Ditto.
4798 (vclmul): Ditto.
4799 (vclmulh): Ditto.
4800 (vghsh): Ditto.
4801 (vgmul): Ditto.
4802 (vaesef): Ditto.
4803 (vaesem): Ditto.
4804 (vaesdf): Ditto.
4805 (vaesdm): Ditto.
4806 (vaesz): Ditto.
4807 (vaeskf1): Ditto.
4808 (vaeskf2): Ditto.
4809 (vsha2ms): Ditto.
4810 (vsha2ch): Ditto.
4811 (vsha2cl): Ditto.
4812 (vsm4k): Ditto.
4813 (vsm4r): Ditto.
4814 (vsm3me): Ditto.
4815 (vsm3c): Ditto.
4816 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
4817 Add new function_shape for crypto vector.
4818 (struct crypto_vi_def): Ditto.
4819 (struct crypto_vv_no_op_type_def): Ditto.
4820 (SHAPE): Add SHAPE declaration of crypto vector.
4821 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
4822 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
4823 Add new data type for crypto vector.
4824 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4825 (vuint32mf2_t): Ditto.
4826 (vuint32m1_t): Ditto.
4827 (vuint32m2_t): Ditto.
4828 (vuint32m4_t): Ditto.
4829 (vuint32m8_t): Ditto.
4830 (vuint64m1_t): Ditto.
4831 (vuint64m2_t): Ditto.
4832 (vuint64m4_t): Ditto.
4833 (vuint64m8_t): Ditto.
4834 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
4835 Add new data struct for crypto vector.
4836 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4837 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
4838 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
4840 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
4842 PR sanitizer/113251
4843 * varasm.cc (assemble_function_label_raw): Do not call
4844 asan_function_start () without the current function.
4846 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
4848 PR target/113225
4849 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
4850 extern and kernel_helper attributed function decls.
4852 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
4854 * btfout.cc (output_btf_strs): Changed.
4856 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
4858 * config/gcn/mkoffload.cc (main): Handle gfx1100
4859 when setting the default XNACK.
4861 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
4863 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
4864 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
4865 (ASM_SPEC): Handle gfx1100.
4866 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
4867 (enum gcn_isa): Add ISA_RDNA3.
4868 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
4869 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4870 * config/gcn/gcn.cc (gcn_option_override,
4871 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
4872 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
4873 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4874 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
4875 with gfx1100.
4876 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
4877 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
4878 __gfx1100__.
4879 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4880 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
4881 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
4882 (isa_has_combined_avgprs, main): Handle gfx1100.
4883 * config/gcn/t-omp-device (isa): Add gfx1100.
4885 2024-01-08 Richard Biener <rguenther@suse.de>
4887 * doc/invoke.texi (-mmovbe): Clarify.
4889 2024-01-08 Richard Biener <rguenther@suse.de>
4891 PR tree-optimization/113026
4892 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
4893 Avoid an epilog in more cases.
4894 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
4895 epilogues niter upper bounds and estimates.
4897 2024-01-08 Jakub Jelinek <jakub@redhat.com>
4899 PR tree-optimization/113228
4900 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
4902 2024-01-08 Jakub Jelinek <jakub@redhat.com>
4904 PR tree-optimization/113120
4905 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
4906 large _BitInt zero INTEGER_CST PHI argument.
4908 2024-01-08 Jakub Jelinek <jakub@redhat.com>
4910 PR tree-optimization/113119
4911 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
4912 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
4913 is before REALPART_EXPR.
4915 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
4917 PR target/112952
4918 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
4919 range when diagnosing attribute "io" and "io_low" are out of range.
4920 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
4921 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
4922 in contexts other than static storage.
4923 (avr_asm_output_aligned_decl_common): Move output of decls with
4924 attribute "address", "io", and "io_low" to...
4925 (avr_output_addr_attrib): ...this new function.
4926 (avr_asm_asm_output_aligned_bss): Remove output for decls with
4927 attribute "address", "io", and "io_low".
4928 (avr_encode_section_info): Rectify handling of decls with attribute
4929 "address", "io", and "io_low".
4931 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
4933 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
4934 (elf_flags): Remove XNACK from the default value.
4935 (main): Set a default XNACK according to the arch.
4937 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
4939 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
4940 (process_asm): Don't count avgprs.
4942 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
4944 * config/i386/i386.opt: Add supported sub-features.
4945 * doc/extend.texi: Add description for target attribute.
4947 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
4949 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
4951 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
4952 Uros Bizjak <ubizjak@gmail.com>
4954 PR target/113231
4955 * config/i386/i386-features.cc (compute_convert_gain): Include
4956 the overhead of explicit load and store (movd) instructions when
4957 converting non-store scalar operations with memory destinations.
4958 Various indentation whitespace fixes.
4960 2024-01-07 Tamar Christina <tamar.christina@arm.com>
4962 * config/arm/neon.md (cbranch<mode>4): New.
4964 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4966 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
4968 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
4970 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
4972 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4974 PR target/113248
4975 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
4976 Update the MAX_SEW.
4978 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4980 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
4981 (variable_vectorized_p): Teach loop invariant.
4982 (has_unexpected_spills_p): Ditto.
4984 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4986 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
4987 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
4988 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
4990 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
4992 PR target/113104
4993 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
4994 (aarch64-vect-compare-costs): ...this.
4995 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
4996 Replace with...
4997 (-param=aarch64-vect-compare-costs=): ...this new param.
4998 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
4999 Don't disable it when vectorizing for Advanced SIMD only.
5000 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
5001 whenever aarch64_vect_compare_costs is true.
5003 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
5005 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
5006 Modify the method of determining the memory offset of [x]vld/[x]vst.
5007 (lasx_mxst_<lasxfmt_f>): Likewise.
5008 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
5009 (loongarch_address_insns): Likewise.
5010 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
5011 (lsx_st_<lsxfmt_f>): Likewise.
5012 * config/loongarch/predicates.md (aq10b_operand): Likewise.
5013 (aq10h_operand): Likewise.
5014 (aq10w_operand): Likewise.
5015 (aq10d_operand): Likewise.
5017 2024-01-05 Alex Coplan <alex.coplan@arm.com>
5019 PR target/113217
5020 * config/aarch64/aarch64-ldp-fusion.cc
5021 (ldp_bb_info::try_fuse_pair): If the second access can throw,
5022 narrow the move range to exactly that insn.
5024 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
5026 * asan.cc (asan_function_start): Drop switch_to_section ().
5027 (asan_emit_stack_protection): Set .LASANPC alignment.
5028 * config/i386/i386.cc: Use assemble_function_label_raw ()
5029 instead of ASM_OUTPUT_LABEL ().
5030 * config/s390/s390.cc (s390_asm_output_function_label):
5031 Likewise.
5032 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
5033 * final.cc (final_start_function_1): Drop
5034 asan_function_start ().
5035 * output.h (assemble_function_label_raw): New function.
5036 * varasm.cc (assemble_function_label_raw): Likewise.
5038 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
5040 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
5041 Use ASM_OUTPUT_FUNCTION_LABEL ().
5042 * config/alpha/alpha.cc (alpha_start_function): Likewise.
5043 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5044 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
5045 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5046 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5047 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
5048 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5049 * config/ia64/ia64.cc (ia64_start_function): Likewise.
5050 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
5051 Likewise.
5052 * config/microblaze/microblaze.cc (microblaze_function_prologue):
5053 Likewise.
5054 * config/mips/mips.cc (mips_start_unique_function): Return the
5055 tree.
5056 (mips_start_function_definition): Use
5057 ASM_OUTPUT_FUNCTION_LABEL ().
5058 (mips_finish_stub): Pass the tree to
5059 mips_start_function_definition ().
5060 (mips16_build_function_stub): Likewise.
5061 (mips16_build_call_stub): Likewise.
5062 (mips_output_function_prologue): Likewise.
5063 * config/pa/pa.cc (pa_output_function_label): Use
5064 ASM_OUTPUT_FUNCTION_LABEL ().
5065 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
5066 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5067 Likewise.
5068 (rs6000_xcoff_declare_function_name): Likewise.
5070 2024-01-05 Jakub Jelinek <jakub@redhat.com>
5072 PR tree-optimization/113201
5073 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
5074 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
5076 2024-01-05 Jakub Jelinek <jakub@redhat.com>
5078 PR tree-optimization/90693
5079 * tree-ssa-math-opts.cc (match_single_bit_test): If
5080 tree_expr_nonzero_p (arg), remember it in the second argument to
5081 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
5082 arg ^ (arg - 1) > arg - 1.
5083 * internal-fn.cc (expand_POPCOUNT): If second argument to
5084 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
5085 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
5087 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
5089 * config/riscv/riscv-v.cc (expand_load_store):
5090 Remove `value`.
5091 (expand_cond_len_op): Ditto.
5092 (expand_gather_scatter): Ditto.
5093 (expand_lanes_load_store): Ditto.
5094 (expand_fold_extract_last): Ditto.
5096 2024-01-05 Pan Li <pan2.li@intel.com>
5098 Revert:
5099 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
5101 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5102 Add new function_base for crypto vector.
5103 (class bitmanip): Ditto.
5104 (class b_reverse):Ditto.
5105 (class vwsll): Ditto.
5106 (class clmul): Ditto.
5107 (class vg_nhab): Ditto.
5108 (class crypto_vv):Ditto.
5109 (class crypto_vi):Ditto.
5110 (class vaeskf2_vsm3c):Ditto.
5111 (class vsm3me): Ditto.
5112 (BASE): Add BASE declaration for crypto vector.
5113 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5114 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5115 Add crypto vector intrinsic definition.
5116 (vbrev): Ditto.
5117 (vclz): Ditto.
5118 (vctz): Ditto.
5119 (vwsll): Ditto.
5120 (vandn): Ditto.
5121 (vbrev8): Ditto.
5122 (vrev8): Ditto.
5123 (vrol): Ditto.
5124 (vror): Ditto.
5125 (vclmul): Ditto.
5126 (vclmulh): Ditto.
5127 (vghsh): Ditto.
5128 (vgmul): Ditto.
5129 (vaesef): Ditto.
5130 (vaesem): Ditto.
5131 (vaesdf): Ditto.
5132 (vaesdm): Ditto.
5133 (vaesz): Ditto.
5134 (vaeskf1): Ditto.
5135 (vaeskf2): Ditto.
5136 (vsha2ms): Ditto.
5137 (vsha2ch): Ditto.
5138 (vsha2cl): Ditto.
5139 (vsm4k): Ditto.
5140 (vsm4r): Ditto.
5141 (vsm3me): Ditto.
5142 (vsm3c): Ditto.
5143 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5144 Add new function_shape for crypto vector.
5145 (struct crypto_vi_def): Ditto.
5146 (struct crypto_vv_no_op_type_def): Ditto.
5147 (SHAPE): Add SHAPE declaration of crypto vector.
5148 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5149 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5150 Add new data type for crypto vector.
5151 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5152 (vuint32mf2_t): Ditto.
5153 (vuint32m1_t): Ditto.
5154 (vuint32m2_t): Ditto.
5155 (vuint32m4_t): Ditto.
5156 (vuint32m8_t): Ditto.
5157 (vuint64m1_t): Ditto.
5158 (vuint64m2_t): Ditto.
5159 (vuint64m4_t): Ditto.
5160 (vuint64m8_t): Ditto.
5161 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5162 Add new data struct for crypto vector.
5163 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5164 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5165 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5167 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
5169 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5170 Add new function_base for crypto vector.
5171 (class bitmanip): Ditto.
5172 (class b_reverse):Ditto.
5173 (class vwsll): Ditto.
5174 (class clmul): Ditto.
5175 (class vg_nhab): Ditto.
5176 (class crypto_vv):Ditto.
5177 (class crypto_vi):Ditto.
5178 (class vaeskf2_vsm3c):Ditto.
5179 (class vsm3me): Ditto.
5180 (BASE): Add BASE declaration for crypto vector.
5181 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5182 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5183 Add crypto vector intrinsic definition.
5184 (vbrev): Ditto.
5185 (vclz): Ditto.
5186 (vctz): Ditto.
5187 (vwsll): Ditto.
5188 (vandn): Ditto.
5189 (vbrev8): Ditto.
5190 (vrev8): Ditto.
5191 (vrol): Ditto.
5192 (vror): Ditto.
5193 (vclmul): Ditto.
5194 (vclmulh): Ditto.
5195 (vghsh): Ditto.
5196 (vgmul): Ditto.
5197 (vaesef): Ditto.
5198 (vaesem): Ditto.
5199 (vaesdf): Ditto.
5200 (vaesdm): Ditto.
5201 (vaesz): Ditto.
5202 (vaeskf1): Ditto.
5203 (vaeskf2): Ditto.
5204 (vsha2ms): Ditto.
5205 (vsha2ch): Ditto.
5206 (vsha2cl): Ditto.
5207 (vsm4k): Ditto.
5208 (vsm4r): Ditto.
5209 (vsm3me): Ditto.
5210 (vsm3c): Ditto.
5211 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5212 Add new function_shape for crypto vector.
5213 (struct crypto_vi_def): Ditto.
5214 (struct crypto_vv_no_op_type_def): Ditto.
5215 (SHAPE): Add SHAPE declaration of crypto vector.
5216 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5217 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5218 Add new data type for crypto vector.
5219 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5220 (vuint32mf2_t): Ditto.
5221 (vuint32m1_t): Ditto.
5222 (vuint32m2_t): Ditto.
5223 (vuint32m4_t): Ditto.
5224 (vuint32m8_t): Ditto.
5225 (vuint64m1_t): Ditto.
5226 (vuint64m2_t): Ditto.
5227 (vuint64m4_t): Ditto.
5228 (vuint64m8_t): Ditto.
5229 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5230 Add new data struct for crypto vector.
5231 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5232 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5233 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5235 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5237 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5239 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
5241 PR tree-optimization/113186
5242 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
5243 Match `^` with the `==` for 1bit integral types.
5244 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
5245 integral types.
5247 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5249 * toplev.cc (general_init): Pass lang_mask to urlifier.
5251 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5253 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
5254 param.
5255 (diagnostic_context::make_option_url): Update for lang_mask param.
5256 * gcc-urlifier.cc: Include "opts.h" and "options.h".
5257 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
5258 (gcc_urlifier::m_lang_mask): New field.
5259 (doc_urls): Make static.
5260 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
5261 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
5262 Look for an option by name before trying a binary search in
5263 doc_urls.
5264 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
5265 (gcc_urlifier::get_url_suffix_for_option): New.
5266 (make_gcc_urlifier): Add lang_mask param.
5267 (selftest::gcc_urlifier_cc_tests): Update for above changes.
5268 Verify that a URL is found for "-fpack-struct".
5269 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
5270 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
5271 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
5272 to make_gcc_urlifier.
5273 * opts-diagnostic.h (get_option_url): Add lang_mask param.
5274 * opts.cc (get_option_html_page): Remove special-casing for
5275 analyzer and LTO.
5276 (get_option_url_suffix): New.
5277 (get_option_url): Reimplement.
5278 (selftest::test_get_option_html_page): Rename to...
5279 (selftest::test_get_option_url_suffix): ...this and update for
5280 above changes.
5281 (selftest::opts_cc_tests): Update for renaming.
5282 * opts.h: Include "rich-location.h".
5283 (get_option_url_suffix): New decl.
5285 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5287 * Makefile.in (ALL_OPT_URL_FILES): New.
5288 (GCC_OBJS): Add options-urls.o.
5289 (OBJS): Likewise.
5290 (OBJS-libcommon): Likewise.
5291 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
5292 inputs to opt-gather.awk.
5293 (options-urls.cc): New Makefile target.
5294 * opt-functions.awk (url_suffix): New function.
5295 (lang_url_suffix): New function.
5296 * options-urls-cc-gen.awk: New file.
5297 * opts.h (get_opt_url_suffix): New decl.
5299 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5301 * params.opt.urls: New file, autogenerated by
5302 regenerate-opt-urls.py.
5304 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5306 * common.opt.urls: New file, autogenerated by
5307 regenerate-opt-urls.py.
5308 * config/aarch64/aarch64.opt.urls: Likewise.
5309 * config/alpha/alpha.opt.urls: Likewise.
5310 * config/alpha/elf.opt.urls: Likewise.
5311 * config/arc/arc-tables.opt.urls: Likewise.
5312 * config/arc/arc.opt.urls: Likewise.
5313 * config/arm/arm-tables.opt.urls: Likewise.
5314 * config/arm/arm.opt.urls: Likewise.
5315 * config/arm/vxworks.opt.urls: Likewise.
5316 * config/avr/avr.opt.urls: Likewise.
5317 * config/bpf/bpf.opt.urls: Likewise.
5318 * config/c6x/c6x-tables.opt.urls: Likewise.
5319 * config/c6x/c6x.opt.urls: Likewise.
5320 * config/cris/cris.opt.urls: Likewise.
5321 * config/cris/elf.opt.urls: Likewise.
5322 * config/csky/csky.opt.urls: Likewise.
5323 * config/csky/csky_tables.opt.urls: Likewise.
5324 * config/darwin.opt.urls: Likewise.
5325 * config/dragonfly.opt.urls: Likewise.
5326 * config/epiphany/epiphany.opt.urls: Likewise.
5327 * config/fr30/fr30.opt.urls: Likewise.
5328 * config/freebsd.opt.urls: Likewise.
5329 * config/frv/frv.opt.urls: Likewise.
5330 * config/ft32/ft32.opt.urls: Likewise.
5331 * config/fused-madd.opt.urls: Likewise.
5332 * config/g.opt.urls: Likewise.
5333 * config/gcn/gcn.opt.urls: Likewise.
5334 * config/gnu-user.opt.urls: Likewise.
5335 * config/h8300/h8300.opt.urls: Likewise.
5336 * config/hpux11.opt.urls: Likewise.
5337 * config/i386/cygming.opt.urls: Likewise.
5338 * config/i386/cygwin.opt.urls: Likewise.
5339 * config/i386/djgpp.opt.urls: Likewise.
5340 * config/i386/i386.opt.urls: Likewise.
5341 * config/i386/mingw-w64.opt.urls: Likewise.
5342 * config/i386/mingw.opt.urls: Likewise.
5343 * config/i386/nto.opt.urls: Likewise.
5344 * config/ia64/ia64.opt.urls: Likewise.
5345 * config/ia64/ilp32.opt.urls: Likewise.
5346 * config/ia64/vms.opt.urls: Likewise.
5347 * config/iq2000/iq2000.opt.urls: Likewise.
5348 * config/linux-android.opt.urls: Likewise.
5349 * config/linux.opt.urls: Likewise.
5350 * config/lm32/lm32.opt.urls: Likewise.
5351 * config/loongarch/loongarch.opt.urls: Likewise.
5352 * config/lynx.opt.urls: Likewise.
5353 * config/m32c/m32c.opt.urls: Likewise.
5354 * config/m32r/m32r.opt.urls: Likewise.
5355 * config/m68k/ieee.opt.urls: Likewise.
5356 * config/m68k/m68k-tables.opt.urls: Likewise.
5357 * config/m68k/m68k.opt.urls: Likewise.
5358 * config/m68k/uclinux.opt.urls: Likewise.
5359 * config/mcore/mcore.opt.urls: Likewise.
5360 * config/microblaze/microblaze.opt.urls: Likewise.
5361 * config/mips/mips-tables.opt.urls: Likewise.
5362 * config/mips/mips.opt.urls: Likewise.
5363 * config/mips/sde.opt.urls: Likewise.
5364 * config/mmix/mmix.opt.urls: Likewise.
5365 * config/mn10300/mn10300.opt.urls: Likewise.
5366 * config/moxie/moxie.opt.urls: Likewise.
5367 * config/msp430/msp430.opt.urls: Likewise.
5368 * config/nds32/nds32-elf.opt.urls: Likewise.
5369 * config/nds32/nds32-linux.opt.urls: Likewise.
5370 * config/nds32/nds32.opt.urls: Likewise.
5371 * config/netbsd-elf.opt.urls: Likewise.
5372 * config/netbsd.opt.urls: Likewise.
5373 * config/nios2/elf.opt.urls: Likewise.
5374 * config/nios2/nios2.opt.urls: Likewise.
5375 * config/nvptx/nvptx-gen.opt.urls: Likewise.
5376 * config/nvptx/nvptx.opt.urls: Likewise.
5377 * config/openbsd.opt.urls: Likewise.
5378 * config/or1k/elf.opt.urls: Likewise.
5379 * config/or1k/or1k.opt.urls: Likewise.
5380 * config/pa/pa-hpux.opt.urls: Likewise.
5381 * config/pa/pa-hpux1010.opt.urls: Likewise.
5382 * config/pa/pa-hpux1111.opt.urls: Likewise.
5383 * config/pa/pa-hpux1131.opt.urls: Likewise.
5384 * config/pa/pa.opt.urls: Likewise.
5385 * config/pa/pa64-hpux.opt.urls: Likewise.
5386 * config/pdp11/pdp11.opt.urls: Likewise.
5387 * config/pru/pru.opt.urls: Likewise.
5388 * config/riscv/riscv.opt.urls: Likewise.
5389 * config/rl78/rl78.opt.urls: Likewise.
5390 * config/rpath.opt.urls: Likewise.
5391 * config/rs6000/476.opt.urls: Likewise.
5392 * config/rs6000/aix64.opt.urls: Likewise.
5393 * config/rs6000/darwin.opt.urls: Likewise.
5394 * config/rs6000/linux64.opt.urls: Likewise.
5395 * config/rs6000/rs6000-tables.opt.urls: Likewise.
5396 * config/rs6000/rs6000.opt.urls: Likewise.
5397 * config/rs6000/sysv4.opt.urls: Likewise.
5398 * config/rtems.opt.urls: Likewise.
5399 * config/rx/elf.opt.urls: Likewise.
5400 * config/rx/rx.opt.urls: Likewise.
5401 * config/s390/s390.opt.urls: Likewise.
5402 * config/s390/tpf.opt.urls: Likewise.
5403 * config/sh/sh.opt.urls: Likewise.
5404 * config/sh/superh.opt.urls: Likewise.
5405 * config/sol2.opt.urls: Likewise.
5406 * config/sparc/long-double-switch.opt.urls: Likewise.
5407 * config/sparc/sparc.opt.urls: Likewise.
5408 * config/stormy16/stormy16.opt.urls: Likewise.
5409 * config/v850/v850.opt.urls: Likewise.
5410 * config/vax/elf.opt.urls: Likewise.
5411 * config/vax/vax.opt.urls: Likewise.
5412 * config/visium/visium.opt.urls: Likewise.
5413 * config/vms/vms.opt.urls: Likewise.
5414 * config/vxworks-smp.opt.urls: Likewise.
5415 * config/vxworks.opt.urls: Likewise.
5416 * config/xtensa/elf.opt.urls: Likewise.
5417 * config/xtensa/uclinux.opt.urls: Likewise.
5418 * config/xtensa/xtensa.opt.urls: Likewise.
5419 * config/bfin/bfin.opt.urls: New file.
5421 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5423 * Makefile.in (OPT_URLS_HTML_DEPS): New.
5424 (regenerate-opt-urls): New target.
5425 (regenerate-opt-urls-unit-test): New target.
5426 * doc/options.texi (Option properties): Add UrlSuffix and
5427 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
5428 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
5429 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
5430 and Makefile.in's OPT_URLS_HTML_DEPS.
5431 (Anatomy of a Target Back End): Add
5432 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
5433 * regenerate-opt-urls.py: New file.
5435 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5437 * diagnostic-format-sarif.cc
5438 (sarif_builder::make_logical_location_object): Convert to...
5439 (make_sarif_logical_location_object): ...this.
5440 (sarif_builder::set_any_logical_locs_arr): Update for above
5441 change.
5442 (sarif_builder::make_thread_flow_location_object): Call
5443 maybe_add_sarif_properties on each diagnostic_event.
5444 * diagnostic-format-sarif.h (class logical_location): New forward
5445 decl.
5446 (make_sarif_logical_location_object): New decl.
5447 * diagnostic-path.h (class sarif_object): New forward decl.
5448 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
5450 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
5451 Patrick Lin <patrick@andestech.com>
5452 Rufus Chen <rufus@andestech.com>
5453 Monk Chiang <monk.chiang@sifive.com>
5455 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
5456 with Nan-boxing value.
5457 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
5459 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
5460 Jeff Law <jlaw@ventanamicro.com>
5462 PR rtl-optimization/104914
5463 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
5464 a sign or zero extension is only required if the modified field
5465 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
5466 targets, don't refer to the temporarily incorrectly extended value
5467 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
5469 2024-01-04 Pan Li <pan2.li@intel.com>
5471 Revert:
5472 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5474 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5476 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5478 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5480 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
5482 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
5483 offset of fcsr.
5485 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5487 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
5488 (compute_nregs_for_mode): Refine LMUL.
5489 (max_number_of_live_regs): Ditto.
5490 (compute_estimated_lmul): Ditto.
5491 (has_unexpected_spills_p): Ditto.
5493 2024-01-04 Li Wei <liwei@loongson.cn>
5495 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
5496 Remove useless forward declaration.
5497 (loongarch_is_even_extraction): Remove useless forward declaration.
5498 (loongarch_try_expand_lsx_vshuf_const): Removed.
5499 (loongarch_expand_vec_perm_const_1): Merged.
5500 (loongarch_is_double_duplicate): Removed.
5501 (loongarch_is_center_extraction): Ditto.
5502 (loongarch_is_reversing_permutation): Ditto.
5503 (loongarch_is_di_misalign_extract): Ditto.
5504 (loongarch_is_si_misalign_extract): Ditto.
5505 (loongarch_is_lasx_lowpart_extract): Ditto.
5506 (loongarch_is_op_reverse_perm): Ditto.
5507 (loongarch_is_single_op_perm): Ditto.
5508 (loongarch_is_divisible_perm): Ditto.
5509 (loongarch_is_triple_stride_extract): Ditto.
5510 (loongarch_expand_vec_perm_const_2): Merged.
5511 (loongarch_expand_vec_perm_const): New.
5512 (loongarch_vectorize_vec_perm_const): Adjust.
5514 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
5516 * omp-general.cc: Fix comment typos and misplaced/confusing
5517 comments. Delete redundant include of omp-general.h.
5519 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
5521 PR rtl-optimization/104914
5522 * config/mips/mips.md (insqisi_extended): New patterns.
5523 (inshisi_extended): Ditto.
5525 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
5527 * config/mips/mips.cc (mips_insn_cost): New function.
5529 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
5531 * config/mips/mips.md (perf_ratio): New attribute.
5533 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5535 PR target/113206
5536 PR target/113209
5537 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
5538 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
5539 blocks belong to infinite loop.
5540 (pre_vsetvl::emit_vsetvl): Remove fake edges.
5541 * config/riscv/t-riscv: Add a new include file.
5543 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5545 * config/riscv/vector.md: Fix indent.
5547 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
5549 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
5550 OMP_CLAUSE__SIMDUID_.
5551 * tree.cc (omp_clause_num_ops): Update position of entry for
5552 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
5553 (omp_clause_code_name): Likewise.
5555 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
5557 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
5558 printing of FUNC_MAP/IND_FUNC_MAP labels.
5560 2024-01-03 Jakub Jelinek <jakub@redhat.com>
5562 * gcc.cc (process_command): Update copyright notice dates.
5563 * gcov-dump.cc (print_version): Ditto.
5564 * gcov.cc (print_version): Ditto.
5565 * gcov-tool.cc (print_version): Ditto.
5566 * gengtype.cc (create_file): Ditto.
5567 * doc/cpp.texi: Bump @copying's copyright year.
5568 * doc/cppinternals.texi: Ditto.
5569 * doc/gcc.texi: Ditto.
5570 * doc/gccint.texi: Ditto.
5571 * doc/gcov.texi: Ditto.
5572 * doc/install.texi: Ditto.
5573 * doc/invoke.texi: Ditto.
5575 2024-01-03 Xi Ruoyao <xry111@xry111.site>
5577 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
5578 (fmin<mode>3): Likewise.
5579 (reduc_fmax_scal_<mode>3): New define_expand.
5580 (reduc_fmin_scal_<mode>3): Likewise.
5582 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5584 PR target/113112
5585 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
5586 (max_number_of_live_regs): Ditto.
5587 (has_unexpected_spills_p): Ditto.
5589 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5590 Jin Ma <jinma@linux.alibaba.com>
5591 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5592 Christoph Müllner <christoph.muellner@vrull.eu>
5594 * config/riscv/vector.md:
5595 Use vector_length_operand for vsetvl patterns.
5597 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5599 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
5600 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
5602 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
5604 * config/aarch64/aarch64-tuning-flags.def
5605 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
5606 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
5607 * config/aarch64/aarch64.cc
5608 (aarch64_override_options_internal): Set
5609 param_fully_pipelined_fma according to tuning option.
5610 * config/aarch64/tuning_models/ampere1.h: Add
5611 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
5612 * config/aarch64/tuning_models/ampere1a.h: Likewise.
5613 * config/aarch64/tuning_models/ampere1b.h: Likewise.
5615 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
5617 * config/riscv/vector-crypto.md: Modify copyright year.
5619 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5621 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
5623 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
5625 * config.in: Regenerate.
5626 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
5627 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
5628 Added TLS Le Relax support.
5629 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
5630 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
5631 * configure: Regenerate.
5632 * configure.ac: Check if binutils supports TLS le relax.
5634 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
5636 * config/riscv/iterators.md: Add rotate insn name.
5637 * config/riscv/riscv.md: Add new insns name for crypto vector.
5638 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
5639 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
5640 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
5642 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5644 PR target/113112
5645 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
5646 pointer type liveness count.
5647 \f
5648 Copyright (C) 2024 Free Software Foundation, Inc.
5650 Copying and distribution of this file, with or without modification,
5651 are permitted in any medium without royalty provided the copyright
5652 notice and this notice are preserved.