gcc/rtl.def

   1 /* This file contains the definitions and documentation for the
   2    Register Transfer Expressions (rtx's) that make up the
   3    Register Transfer Language (rtl) used in the Back End of the GNU compiler.
   4    Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
   5    2005
   6    Free Software Foundation, Inc.
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify it under
  11 the terms of the GNU General Public License as published by the Free
  12 Software Foundation; either version 2, or (at your option) any later
  13 version.
  14
  15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18 for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING.  If not, write to the Free
  22 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  23 02110-1301, USA.  */
  24
  25
  26 /* Expression definitions and descriptions for all targets are in this file.
  27    Some will not be used for some targets.
  28
  29    The fields in the cpp macro call "DEF_RTL_EXPR()"
  30    are used to create declarations in the C source of the compiler.
  31
  32    The fields are:
  33
  34    1.  The internal name of the rtx used in the C source.
  35    It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
  36    By convention these are in UPPER_CASE.
  37
  38    2.  The name of the rtx in the external ASCII format read by
  39    read_rtx(), and printed by print_rtx().
  40    These names are stored in rtx_name[].
  41    By convention these are the internal (field 1) names in lower_case.
  42
  43    3.  The print format, and type of each rtx->u.fld[] (field) in this rtx.
  44    These formats are stored in rtx_format[].
  45    The meaning of the formats is documented in front of this array in rtl.c
  46
  47    4.  The class of the rtx.  These are stored in rtx_class and are accessed
  48    via the GET_RTX_CLASS macro.  They are defined as follows:
  49
  50      RTX_CONST_OBJ
  51          an rtx code that can be used to represent a constant object
  52          (e.g, CONST_INT)
  53      RTX_OBJ
  54          an rtx code that can be used to represent an object (e.g, REG, MEM)
  55      RTX_COMPARE
  56          an rtx code for a comparison (e.g, LT, GT)
  57      RTX_COMM_COMPARE
  58          an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
  59      RTX_UNARY
  60          an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
  61      RTX_COMM_ARITH
  62          an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
  63      RTX_TERNARY
  64          an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
  65      RTX_BIN_ARITH
  66          an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
  67      RTX_BITFIELD_OPS
  68          an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
  69      RTX_INSN
  70          an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
  71      RTX_MATCH
  72          an rtx code for something that matches in insns (e.g, MATCH_DUP)
  73      RTX_AUTOINC
  74          an rtx code for autoincrement addressing modes (e.g. POST_DEC)
  75      RTX_EXTRA
  76          everything else
  77
  78    All of the expressions that appear only in machine descriptions,
  79    not in RTL used by the compiler itself, are at the end of the file.  */
  80
  81 /* Unknown, or no such operation; the enumeration constant should have
  82    value zero.  */
  83 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
  84
  85 /* ---------------------------------------------------------------------
  86    Expressions used in constructing lists.
  87    --------------------------------------------------------------------- */
  88
  89 /* a linked list of expressions */
  90 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
  91
  92 /* a linked list of instructions.
  93    The insns are represented in print by their uids.  */
  94 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
  95
  96 /* SEQUENCE appears in the result of a `gen_...' function
  97    for a DEFINE_EXPAND that wants to make several insns.
  98    Its elements are the bodies of the insns that should be made.
  99    `emit_insn' takes the SEQUENCE apart and makes separate insns.  */
 100 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
 101
 102 /* Refers to the address of its argument.  This is only used in alias.c.  */
 103 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
 104
 105 /* ----------------------------------------------------------------------
 106    Expression types used for things in the instruction chain.
 107
 108    All formats must start with "iuu" to handle the chain.
 109    Each insn expression holds an rtl instruction and its semantics
 110    during back-end processing.
 111    See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
 112
 113    ---------------------------------------------------------------------- */
 114
 115 /* An instruction that cannot jump.  */
 116 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
 117
 118 /* An instruction that can possibly jump.
 119    Fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
 120 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
 121
 122 /* An instruction that can possibly call a subroutine
 123    but which will not change which instruction comes next
 124    in the current function.
 125    Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
 126    All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
 127 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
 128
 129 /* A marker that indicates that control will not flow through.  */
 130 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
 131
 132 /* Holds a label that is followed by instructions.
 133    Operand:
 134    4: is used in jump.c for the use-count of the label.
 135    5: is used in flow.c to point to the chain of label_ref's to this label.
 136    6: is a number that is unique in the entire compilation.
 137    7: is the user-given name of the label, if any.  */
 138 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
 139
 140 #ifdef USE_MAPPED_LOCATION
 141 /* Say where in the code a source line starts, for symbol table's sake.
 142    Operand:
 143    4: unused if line number > 0, note-specific data otherwise.
 144    5: line number if > 0, enum note_insn otherwise.
 145    6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL.  */
 146 #else
 147 /* Say where in the code a source line starts, for symbol table's sake.
 148    Operand:
 149    4: filename, if line number > 0, note-specific data otherwise.
 150    5: line number if > 0, enum note_insn otherwise.
 151    6: unique number if line number == note_insn_deleted_label.  */
 152 #endif
 153 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
 154
 155 /* ----------------------------------------------------------------------
 156    Top level constituents of INSN, JUMP_INSN and CALL_INSN.
 157    ---------------------------------------------------------------------- */
 158
 159 /* Conditionally execute code.
 160    Operand 0 is the condition that if true, the code is executed.
 161    Operand 1 is the code to be executed (typically a SET).
 162
 163    Semantics are that there are no side effects if the condition
 164    is false.  This pattern is created automatically by the if_convert
 165    pass run after reload or by target-specific splitters.  */
 166 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
 167
 168 /* Several operations to be done in parallel (perhaps under COND_EXEC).  */
 169 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
 170
 171 /* A string that is passed through to the assembler as input.
 172      One can obviously pass comments through by using the
 173      assembler comment syntax.
 174      These occur in an insn all by themselves as the PATTERN.
 175      They also appear inside an ASM_OPERANDS
 176      as a convenient way to hold a string.  */
 177 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
 178
 179 #ifdef USE_MAPPED_LOCATION
 180 /* An assembler instruction with operands.
 181    1st operand is the instruction template.
 182    2nd operand is the constraint for the output.
 183    3rd operand is the number of the output this expression refers to.
 184      When an insn stores more than one value, a separate ASM_OPERANDS
 185      is made for each output; this integer distinguishes them.
 186    4th is a vector of values of input operands.
 187    5th is a vector of modes and constraints for the input operands.
 188      Each element is an ASM_INPUT containing a constraint string
 189      and whose mode indicates the mode of the input operand.
 190    6th is the source line number.  */
 191 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
 192 #else
 193 /* An assembler instruction with operands.
 194    1st operand is the instruction template.
 195    2nd operand is the constraint for the output.
 196    3rd operand is the number of the output this expression refers to.
 197      When an insn stores more than one value, a separate ASM_OPERANDS
 198      is made for each output; this integer distinguishes them.
 199    4th is a vector of values of input operands.
 200    5th is a vector of modes and constraints for the input operands.
 201      Each element is an ASM_INPUT containing a constraint string
 202      and whose mode indicates the mode of the input operand.
 203    6th is the name of the containing source file.
 204    7th is the source line number.  */
 205 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
 206 #endif
 207
 208 /* A machine-specific operation.
 209    1st operand is a vector of operands being used by the operation so that
 210      any needed reloads can be done.
 211    2nd operand is a unique value saying which of a number of machine-specific
 212      operations is to be performed.
 213    (Note that the vector must be the first operand because of the way that
 214    genrecog.c record positions within an insn.)
 215    This can occur all by itself in a PATTERN, as a component of a PARALLEL,
 216    or inside an expression.  */
 217 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
 218
 219 /* Similar, but a volatile operation and one which may trap.  */
 220 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
 221
 222 /* Vector of addresses, stored as full words.  */
 223 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want.  */
 224 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
 225
 226 /* Vector of address differences X0 - BASE, X1 - BASE, ...
 227    First operand is BASE; the vector contains the X's.
 228    The machine mode of this rtx says how much space to leave
 229    for each difference and is adjusted by branch shortening if
 230    CASE_VECTOR_SHORTEN_MODE is defined.
 231    The third and fourth operands store the target labels with the
 232    minimum and maximum addresses respectively.
 233    The fifth operand stores flags for use by branch shortening.
 234   Set at the start of shorten_branches:
 235    min_align: the minimum alignment for any of the target labels.
 236    base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
 237    min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
 238    max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
 239    min_after_base: true iff minimum address target label is after BASE.
 240    max_after_base: true iff maximum address target label is after BASE.
 241   Set by the actual branch shortening process:
 242    offset_unsigned: true iff offsets have to be treated as unsigned.
 243    scale: scaling that is necessary to make offsets fit into the mode.
 244
 245    The third, fourth and fifth operands are only valid when
 246    CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
 247    compilations.  */
 248
 249 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
 250
 251 /* Memory prefetch, with attributes supported on some targets.
 252    Operand 1 is the address of the memory to fetch.
 253    Operand 2 is 1 for a write access, 0 otherwise.
 254    Operand 3 is the level of temporal locality; 0 means there is no
 255    temporal locality and 1, 2, and 3 are for increasing levels of temporal
 256    locality.
 257
 258    The attributes specified by operands 2 and 3 are ignored for targets
 259    whose prefetch instructions do not support them.  */
 260 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
 261
 262 /* ----------------------------------------------------------------------
 263    At the top level of an instruction (perhaps under PARALLEL).
 264    ---------------------------------------------------------------------- */
 265
 266 /* Assignment.
 267    Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
 268    Operand 2 is the value stored there.
 269    ALL assignment must use SET.
 270    Instructions that do multiple assignments must use multiple SET,
 271    under PARALLEL.  */
 272 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
 273
 274 /* Indicate something is used in a way that we don't want to explain.
 275    For example, subroutine calls will use the register
 276    in which the static chain is passed.  */
 277 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
 278
 279 /* Indicate something is clobbered in a way that we don't want to explain.
 280    For example, subroutine calls will clobber some physical registers
 281    (the ones that are by convention not saved).  */
 282 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
 283
 284 /* Call a subroutine.
 285    Operand 1 is the address to call.
 286    Operand 2 is the number of arguments.  */
 287
 288 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
 289
 290 /* Return from a subroutine.  */
 291
 292 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
 293
 294 /* Conditional trap.
 295    Operand 1 is the condition.
 296    Operand 2 is the trap code.
 297    For an unconditional trap, make the condition (const_int 1).  */
 298 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
 299
 300 /* Placeholder for _Unwind_Resume before we know if a function call
 301    or a branch is needed.  Operand 1 is the exception region from
 302    which control is flowing.  */
 303 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
 304
 305 /* ----------------------------------------------------------------------
 306    Primitive values for use in expressions.
 307    ---------------------------------------------------------------------- */
 308
 309 /* numeric integer constant */
 310 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
 311
 312 /* numeric floating point constant.
 313    Operands hold the value.  They are all 'w' and there may be from 2 to 6;
 314    see real.h.  */
 315 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
 316
 317 /* Describes a vector constant.  */
 318 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
 319
 320 /* String constant.  Used for attributes in machine descriptions and
 321    for special cases in DWARF2 debug output.  NOT used for source-
 322    language string constants.  */
 323 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
 324
 325 /* This is used to encapsulate an expression whose value is constant
 326    (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
 327    recognized as a constant operand rather than by arithmetic instructions.  */
 328
 329 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
 330
 331 /* program counter.  Ordinary jumps are represented
 332    by a SET whose first operand is (PC).  */
 333 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
 334
 335 /* Used in the cselib routines to describe a value.  Objects of this
 336    kind are only allocated in cselib.c, in an alloc pool instead of
 337    in GC memory.  The only operand of a VALUE is a cselib_val_struct.  */
 338 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
 339
 340 /* A register.  The "operand" is the register number, accessed with
 341    the REGNO macro.  If this number is less than FIRST_PSEUDO_REGISTER
 342    than a hardware register is being referred to.  The second operand
 343    holds the original register number - this will be different for a
 344    pseudo register that got turned into a hard register.  The third
 345    operand points to a reg_attrs structure.
 346    This rtx needs to have as many (or more) fields as a MEM, since we
 347    can change REG rtx's into MEMs during reload.  */
 348 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
 349
 350 /* A scratch register.  This represents a register used only within a
 351    single insn.  It will be turned into a REG during register allocation
 352    or reload unless the constraint indicates that the register won't be
 353    needed, in which case it can remain a SCRATCH.  This code is
 354    marked as having one operand so it can be turned into a REG.  */
 355 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
 356
 357 /* One word of a multi-word value.
 358    The first operand is the complete value; the second says which word.
 359    The WORDS_BIG_ENDIAN flag controls whether word number 0
 360    (as numbered in a SUBREG) is the most or least significant word.
 361
 362    This is also used to refer to a value in a different machine mode.
 363    For example, it can be used to refer to a SImode value as if it were
 364    Qimode, or vice versa.  Then the word number is always 0.  */
 365 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
 366
 367 /* This one-argument rtx is used for move instructions
 368    that are guaranteed to alter only the low part of a destination.
 369    Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
 370    has an unspecified effect on the high part of REG,
 371    but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
 372    is guaranteed to alter only the bits of REG that are in HImode.
 373
 374    The actual instruction used is probably the same in both cases,
 375    but the register constraints may be tighter when STRICT_LOW_PART
 376    is in use.  */
 377
 378 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
 379
 380 /* (CONCAT a b) represents the virtual concatenation of a and b
 381    to make a value that has as many bits as a and b put together.
 382    This is used for complex values.  Normally it appears only
 383    in DECL_RTLs and during RTL generation, but not in the insn chain.  */
 384 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
 385
 386 /* A memory location; operand is the address.  The second operand is the
 387    alias set to which this MEM belongs.  We use `0' instead of `w' for this
 388    field so that the field need not be specified in machine descriptions.  */
 389 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
 390
 391 /* Reference to an assembler label in the code for this function.
 392    The operand is a CODE_LABEL found in the insn chain.  */
 393 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
 394
 395 /* Reference to a named label:
 396    Operand 0: label name
 397    Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
 398    Operand 2: tree from which this symbol is derived, or null.
 399    This is either a DECL node, or some kind of constant.  */
 400 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
 401
 402 /* The condition code register is represented, in our imagination,
 403    as a register holding a value that can be compared to zero.
 404    In fact, the machine has already compared them and recorded the
 405    results; but instructions that look at the condition code
 406    pretend to be looking at the entire value and comparing it.  */
 407 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
 408
 409 /* ----------------------------------------------------------------------
 410    Expressions for operators in an rtl pattern
 411    ---------------------------------------------------------------------- */
 412
 413 /* if_then_else.  This is used in representing ordinary
 414    conditional jump instructions.
 415      Operand:
 416      0:  condition
 417      1:  then expr
 418      2:  else expr */
 419 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
 420
 421 /* Comparison, produces a condition code result.  */
 422 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
 423
 424 /* plus */
 425 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
 426
 427 /* Operand 0 minus operand 1.  */
 428 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
 429
 430 /* Minus operand 0.  */
 431 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
 432
 433 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
 434
 435 /* Operand 0 divided by operand 1.  */
 436 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
 437 /* Remainder of operand 0 divided by operand 1.  */
 438 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
 439
 440 /* Unsigned divide and remainder.  */
 441 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
 442 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
 443
 444 /* Bitwise operations.  */
 445 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
 446 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
 447 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
 448 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
 449
 450 /* Operand:
 451      0:  value to be shifted.
 452      1:  number of bits.  */
 453 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
 454 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
 455 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
 456 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
 457 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
 458
 459 /* Minimum and maximum values of two operands.  We need both signed and
 460    unsigned forms.  (We cannot use MIN for SMIN because it conflicts
 461    with a macro of the same name.)   The signed variants should be used
 462    with floating point.  Further, if both operands are zeros, or if either
 463    operand is NaN, then it is unspecified which of the two operands is
 464    returned as the result.  */
 465
 466 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
 467 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
 468 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
 469 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
 470
 471 /* These unary operations are used to represent incrementation
 472    and decrementation as they occur in memory addresses.
 473    The amount of increment or decrement are not represented
 474    because they can be understood from the machine-mode of the
 475    containing MEM.  These operations exist in only two cases:
 476    1. pushes onto the stack.
 477    2. created automatically by the life_analysis pass in flow.c.  */
 478 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
 479 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
 480 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
 481 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
 482
 483 /* These binary operations are used to represent generic address
 484    side-effects in memory addresses, except for simple incrementation
 485    or decrementation which use the above operations.  They are
 486    created automatically by the life_analysis pass in flow.c.
 487    The first operand is a REG which is used as the address.
 488    The second operand is an expression that is assigned to the
 489    register, either before (PRE_MODIFY) or after (POST_MODIFY)
 490    evaluating the address.
 491    Currently, the compiler can only handle second operands of the
 492    form (plus (reg) (reg)) and (plus (reg) (const_int)), where
 493    the first operand of the PLUS has to be the same register as
 494    the first operand of the *_MODIFY.  */
 495 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
 496 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
 497
 498 /* Comparison operations.  The ordered comparisons exist in two
 499    flavors, signed and unsigned.  */
 500 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
 501 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
 502 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
 503 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
 504 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
 505 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
 506 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
 507 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
 508 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
 509 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
 510
 511 /* Additional floating point unordered comparison flavors.  */
 512 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
 513 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
 514
 515 /* These are equivalent to unordered or ...  */
 516 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
 517 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
 518 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
 519 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
 520 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
 521
 522 /* This is an ordered NE, ie !UNEQ, ie false for NaN.  */
 523 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
 524
 525 /* Represents the result of sign-extending the sole operand.
 526    The machine modes of the operand and of the SIGN_EXTEND expression
 527    determine how much sign-extension is going on.  */
 528 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
 529
 530 /* Similar for zero-extension (such as unsigned short to int).  */
 531 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
 532
 533 /* Similar but here the operand has a wider mode.  */
 534 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
 535
 536 /* Similar for extending floating-point values (such as SFmode to DFmode).  */
 537 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
 538 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
 539
 540 /* Conversion of fixed point operand to floating point value.  */
 541 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
 542
 543 /* With fixed-point machine mode:
 544    Conversion of floating point operand to fixed point value.
 545    Value is defined only when the operand's value is an integer.
 546    With floating-point machine mode (and operand with same mode):
 547    Operand is rounded toward zero to produce an integer value
 548    represented in floating point.  */
 549 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
 550
 551 /* Conversion of unsigned fixed point operand to floating point value.  */
 552 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
 553
 554 /* With fixed-point machine mode:
 555    Conversion of floating point operand to *unsigned* fixed point value.
 556    Value is defined only when the operand's value is an integer.  */
 557 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
 558
 559 /* Absolute value */
 560 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
 561
 562 /* Square root */
 563 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
 564
 565 /* Find first bit that is set.
 566    Value is 1 + number of trailing zeros in the arg.,
 567    or 0 if arg is 0.  */
 568 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
 569
 570 /* Count leading zeros.  */
 571 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
 572
 573 /* Count trailing zeros.  */
 574 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
 575
 576 /* Population count (number of 1 bits).  */
 577 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
 578
 579 /* Population parity (number of 1 bits modulo 2).  */
 580 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
 581
 582 /* Reference to a signed bit-field of specified size and position.
 583    Operand 0 is the memory unit (usually SImode or QImode) which
 584    contains the field's first bit.  Operand 1 is the width, in bits.
 585    Operand 2 is the number of bits in the memory unit before the
 586    first bit of this field.
 587    If BITS_BIG_ENDIAN is defined, the first bit is the msb and
 588    operand 2 counts from the msb of the memory unit.
 589    Otherwise, the first bit is the lsb and operand 2 counts from
 590    the lsb of the memory unit.
 591    This kind of expression can not appear as an lvalue in RTL.  */
 592 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
 593
 594 /* Similar for unsigned bit-field.
 595    But note!  This kind of expression _can_ appear as an lvalue.  */
 596 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
 597
 598 /* For RISC machines.  These save memory when splitting insns.  */
 599
 600 /* HIGH are the high-order bits of a constant expression.  */
 601 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
 602
 603 /* LO_SUM is the sum of a register and the low-order bits
 604    of a constant expression.  */
 605 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
 606
 607 /* Describes a merge operation between two vector values.
 608    Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
 609    that specifies where the parts of the result are taken from.  Set bits
 610    indicate operand 0, clear bits indicate operand 1.  The parts are defined
 611    by the mode of the vectors.  */
 612 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
 613
 614 /* Describes an operation that selects parts of a vector.
 615    Operands 0 is the source vector, operand 1 is a PARALLEL that contains
 616    a CONST_INT for each of the subparts of the result vector, giving the
 617    number of the source subpart that should be stored into it.  */
 618 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
 619
 620 /* Describes a vector concat operation.  Operands 0 and 1 are the source
 621    vectors, the result is a vector that is as long as operands 0 and 1
 622    combined and is the concatenation of the two source vectors.  */
 623 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
 624
 625 /* Describes an operation that converts a small vector into a larger one by
 626    duplicating the input values.  The output vector mode must have the same
 627    submodes as the input vector mode, and the number of output parts must be
 628    an integer multiple of the number of input parts.  */
 629 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
 630
 631 /* Addition with signed saturation */
 632 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
 633
 634 /* Addition with unsigned saturation */
 635 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
 636
 637 /* Operand 0 minus operand 1, with signed saturation.  */
 638 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
 639
 640 /* Operand 0 minus operand 1, with unsigned saturation.  */
 641 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
 642
 643 /* Signed saturating truncate.  */
 644 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
 645
 646 /* Unsigned saturating truncate.  */
 647 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
 648
 649 /* Information about the variable and its location.  */
 650 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
 651
 652 /* All expressions from this point forward appear only in machine
 653    descriptions.  */
 654 #ifdef GENERATOR_FILE
 655
 656 /* Include a secondary machine-description file at this point.  */
 657 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
 658
 659 /* Pattern-matching operators:  */
 660
 661 /* Use the function named by the second arg (the string)
 662    as a predicate; if matched, store the structure that was matched
 663    in the operand table at index specified by the first arg (the integer).
 664    If the second arg is the null string, the structure is just stored.
 665
 666    A third string argument indicates to the register allocator restrictions
 667    on where the operand can be allocated.
 668
 669    If the target needs no restriction on any instruction this field should
 670    be the null string.
 671
 672    The string is prepended by:
 673    '=' to indicate the operand is only written to.
 674    '+' to indicate the operand is both read and written to.
 675
 676    Each character in the string represents an allocable class for an operand.
 677    'g' indicates the operand can be any valid class.
 678    'i' indicates the operand can be immediate (in the instruction) data.
 679    'r' indicates the operand can be in a register.
 680    'm' indicates the operand can be in memory.
 681    'o' a subset of the 'm' class.  Those memory addressing modes that
 682        can be offset at compile time (have a constant added to them).
 683
 684    Other characters indicate target dependent operand classes and
 685    are described in each target's machine description.
 686
 687    For instructions with more than one operand, sets of classes can be
 688    separated by a comma to indicate the appropriate multi-operand constraints.
 689    There must be a 1 to 1 correspondence between these sets of classes in
 690    all operands for an instruction.
 691    */
 692 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
 693
 694 /* Match a SCRATCH or a register.  When used to generate rtl, a
 695    SCRATCH is generated.  As for MATCH_OPERAND, the mode specifies
 696    the desired mode and the first argument is the operand number.
 697    The second argument is the constraint.  */
 698 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
 699
 700 /* Apply a predicate, AND match recursively the operands of the rtx.
 701    Operand 0 is the operand-number, as in match_operand.
 702    Operand 1 is a predicate to apply (as a string, a function name).
 703    Operand 2 is a vector of expressions, each of which must match
 704    one subexpression of the rtx this construct is matching.  */
 705 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
 706
 707 /* Match a PARALLEL of arbitrary length.  The predicate is applied
 708    to the PARALLEL and the initial expressions in the PARALLEL are matched.
 709    Operand 0 is the operand-number, as in match_operand.
 710    Operand 1 is a predicate to apply to the PARALLEL.
 711    Operand 2 is a vector of expressions, each of which must match the
 712    corresponding element in the PARALLEL.  */
 713 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
 714
 715 /* Match only something equal to what is stored in the operand table
 716    at the index specified by the argument.  Use with MATCH_OPERAND.  */
 717 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
 718
 719 /* Match only something equal to what is stored in the operand table
 720    at the index specified by the argument.  Use with MATCH_OPERATOR.  */
 721 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
 722
 723 /* Match only something equal to what is stored in the operand table
 724    at the index specified by the argument.  Use with MATCH_PARALLEL.  */
 725 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
 726
 727 /* Appears only in define_predicate/define_special_predicate
 728    expressions.  Evaluates true only if the operand has an RTX code
 729    from the set given by the argument (a comma-separated list).  If the
 730    second argument is present and nonempty, it is a sequence of digits
 731    and/or letters which indicates the subexpression to test, using the
 732    same syntax as genextract/genrecog's location strings: 0-9 for
 733    XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
 734    the result of the one before it.  */
 735 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
 736
 737 /* Appears only in define_predicate/define_special_predicate
 738     expressions.  The argument is a C expression to be injected at this
 739     point in the predicate formula.  */
 740 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
 741
 742 /* Insn (and related) definitions.  */
 743
 744 /* Definition of the pattern for one kind of instruction.
 745    Operand:
 746    0: names this instruction.
 747       If the name is the null string, the instruction is in the
 748       machine description just to be recognized, and will never be emitted by
 749       the tree to rtl expander.
 750    1: is the pattern.
 751    2: is a string which is a C expression
 752       giving an additional condition for recognizing this pattern.
 753       A null string means no extra condition.
 754    3: is the action to execute if this pattern is matched.
 755       If this assembler code template starts with a * then it is a fragment of
 756       C code to run to decide on a template to use.  Otherwise, it is the
 757       template to use.
 758    4: optionally, a vector of attributes for this insn.
 759      */
 760 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
 761
 762 /* Definition of a peephole optimization.
 763    1st operand: vector of insn patterns to match
 764    2nd operand: C expression that must be true
 765    3rd operand: template or C code to produce assembler output.
 766    4: optionally, a vector of attributes for this insn.
 767
 768    This form is deprecated; use define_peephole2 instead.  */
 769 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
 770
 771 /* Definition of a split operation.
 772    1st operand: insn pattern to match
 773    2nd operand: C expression that must be true
 774    3rd operand: vector of insn patterns to place into a SEQUENCE
 775    4th operand: optionally, some C code to execute before generating the
 776         insns.  This might, for example, create some RTX's and store them in
 777         elements of `recog_data.operand' for use by the vector of
 778         insn-patterns.
 779         (`operands' is an alias here for `recog_data.operand').  */
 780 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
 781
 782 /* Definition of an insn and associated split.
 783    This is the concatenation, with a few modifications, of a define_insn
 784    and a define_split which share the same pattern.
 785    Operand:
 786    0: names this instruction.
 787       If the name is the null string, the instruction is in the
 788       machine description just to be recognized, and will never be emitted by
 789       the tree to rtl expander.
 790    1: is the pattern.
 791    2: is a string which is a C expression
 792       giving an additional condition for recognizing this pattern.
 793       A null string means no extra condition.
 794    3: is the action to execute if this pattern is matched.
 795       If this assembler code template starts with a * then it is a fragment of
 796       C code to run to decide on a template to use.  Otherwise, it is the
 797       template to use.
 798    4: C expression that must be true for split.  This may start with "&&"
 799       in which case the split condition is the logical and of the insn
 800       condition and what follows the "&&" of this operand.
 801    5: vector of insn patterns to place into a SEQUENCE
 802    6: optionally, some C code to execute before generating the
 803         insns.  This might, for example, create some RTX's and store them in
 804         elements of `recog_data.operand' for use by the vector of
 805         insn-patterns.
 806         (`operands' is an alias here for `recog_data.operand').
 807    7: optionally, a vector of attributes for this insn.  */
 808 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
 809
 810 /* Definition of an RTL peephole operation.
 811    Follows the same arguments as define_split.  */
 812 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
 813
 814 /* Define how to generate multiple insns for a standard insn name.
 815    1st operand: the insn name.
 816    2nd operand: vector of insn-patterns.
 817         Use match_operand to substitute an element of `recog_data.operand'.
 818    3rd operand: C expression that must be true for this to be available.
 819         This may not test any operands.
 820    4th operand: Extra C code to execute before generating the insns.
 821         This might, for example, create some RTX's and store them in
 822         elements of `recog_data.operand' for use by the vector of
 823         insn-patterns.
 824         (`operands' is an alias here for `recog_data.operand').  */
 825 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
 826
 827 /* Define a requirement for delay slots.
 828    1st operand: Condition involving insn attributes that, if true,
 829                 indicates that the insn requires the number of delay slots
 830                 shown.
 831    2nd operand: Vector whose length is the three times the number of delay
 832                 slots required.
 833                 Each entry gives three conditions, each involving attributes.
 834                 The first must be true for an insn to occupy that delay slot
 835                 location.  The second is true for all insns that can be
 836                 annulled if the branch is true and the third is true for all
 837                 insns that can be annulled if the branch is false.
 838
 839    Multiple DEFINE_DELAYs may be present.  They indicate differing
 840    requirements for delay slots.  */
 841 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
 842
 843 /* Define attribute computation for `asm' instructions.  */
 844 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
 845
 846 /* Definition of a conditional execution meta operation.  Automatically
 847    generates new instances of DEFINE_INSN, selected by having attribute
 848    "predicable" true.  The new pattern will contain a COND_EXEC and the
 849    predicate at top-level.
 850
 851    Operand:
 852    0: The predicate pattern.  The top-level form should match a
 853       relational operator.  Operands should have only one alternative.
 854    1: A C expression giving an additional condition for recognizing
 855       the generated pattern.
 856    2: A template or C code to produce assembler output.  */
 857 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
 858
 859 /* Definition of an operand predicate.  The difference between
 860    DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
 861    not warn about a match_operand with no mode if it has a predicate
 862    defined with DEFINE_SPECIAL_PREDICATE.
 863
 864    Operand:
 865    0: The name of the predicate.
 866    1: A boolean expression which computes whether or not the predicate
 867       matches.  This expression can use IOR, AND, NOT, MATCH_OPERAND,
 868       MATCH_CODE, and MATCH_TEST.  It must be specific enough that genrecog
 869       can calculate the set of RTX codes that can possibly match.
 870    2: A C function body which must return true for the predicate to match.
 871       Optional.  Use this when the test is too complicated to fit into a
 872       match_test expression.  */
 873 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
 874 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
 875
 876 /* Definition of a register operand constraint.  This simply maps the
 877    constraint string to a register class.
 878
 879    Operand:
 880    0: The name of the constraint (often, but not always, a single letter).
 881    1: A C expression which evaluates to the appropriate register class for
 882       this constraint.  If this is not just a constant, it should look only
 883       at -m switches and the like.
 884    2: A docstring for this constraint, in Texinfo syntax; not currently
 885       used, in future will be incorporated into the manual's list of
 886       machine-specific operand constraints.  */
 887 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
 888
 889 /* Definition of a non-register operand constraint.  These look at the
 890    operand and decide whether it fits the constraint.
 891
 892    DEFINE_CONSTRAINT gets no special treatment if it fails to match.
 893    It is appropriate for constant-only constraints, and most others.
 894
 895    DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
 896    to match, if it doesn't already, by converting the operand to the form
 897    (mem (reg X)) where X is a base register.  It is suitable for constraints
 898    that describe a subset of all memory references.
 899
 900    DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
 901    to match, if it doesn't already, by converting the operand to the form
 902    (reg X) where X is a base register.  It is suitable for constraints that
 903    describe a subset of all address references.
 904
 905    When in doubt, use plain DEFINE_CONSTRAINT.
 906
 907    Operand:
 908    0: The name of the constraint (often, but not always, a single letter).
 909    1: A docstring for this constraint, in Texinfo syntax; not currently
 910       used, in future will be incorporated into the manual's list of
 911       machine-specific operand constraints.
 912    2: A boolean expression which computes whether or not the constraint
 913       matches.  It should follow the same rules as a define_predicate
 914       expression, including the bit about specifying the set of RTX codes
 915       that could possibly match.  MATCH_TEST subexpressions may make use of
 916       these variables:
 917         `op'    - the RTL object defining the operand.
 918         `mode'  - the mode of `op'.
 919         `ival'  - INTVAL(op), if op is a CONST_INT.
 920         `hval'  - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
 921         `lval'  - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
 922         `rval'  - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
 923                   CONST_DOUBLE.
 924       Do not use ival/hval/lval/rval if op is not the appropriate kind of
 925       RTL object.  */
 926 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
 927 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
 928 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
 929
 930
 931 /* Constructions for CPU pipeline description described by NDFAs.  */
 932
 933 /* (define_cpu_unit string [string]) describes cpu functional
 934    units (separated by comma).
 935
 936    1st operand: Names of cpu functional units.
 937    2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
 938
 939    All define_reservations, define_cpu_units, and
 940    define_query_cpu_units should have unique names which may not be
 941    "nothing".  */
 942 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
 943
 944 /* (define_query_cpu_unit string [string]) describes cpu functional
 945    units analogously to define_cpu_unit.  The reservation of such
 946    units can be queried for automaton state.  */
 947 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
 948
 949 /* (exclusion_set string string) means that each CPU functional unit
 950    in the first string can not be reserved simultaneously with any
 951    unit whose name is in the second string and vise versa.  CPU units
 952    in the string are separated by commas.  For example, it is useful
 953    for description CPU with fully pipelined floating point functional
 954    unit which can execute simultaneously only single floating point
 955    insns or only double floating point insns.  All CPU functional
 956    units in a set should belong to the same automaton.  */
 957 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
 958
 959 /* (presence_set string string) means that each CPU functional unit in
 960    the first string can not be reserved unless at least one of pattern
 961    of units whose names are in the second string is reserved.  This is
 962    an asymmetric relation.  CPU units or unit patterns in the strings
 963    are separated by commas.  Pattern is one unit name or unit names
 964    separated by white-spaces.
 965
 966    For example, it is useful for description that slot1 is reserved
 967    after slot0 reservation for a VLIW processor.  We could describe it
 968    by the following construction
 969
 970       (presence_set "slot1" "slot0")
 971
 972    Or slot1 is reserved only after slot0 and unit b0 reservation.  In
 973    this case we could write
 974
 975       (presence_set "slot1" "slot0 b0")
 976
 977    All CPU functional units in a set should belong to the same
 978    automaton.  */
 979 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
 980
 981 /* (final_presence_set string string) is analogous to `presence_set'.
 982    The difference between them is when checking is done.  When an
 983    instruction is issued in given automaton state reflecting all
 984    current and planned unit reservations, the automaton state is
 985    changed.  The first state is a source state, the second one is a
 986    result state.  Checking for `presence_set' is done on the source
 987    state reservation, checking for `final_presence_set' is done on the
 988    result reservation.  This construction is useful to describe a
 989    reservation which is actually two subsequent reservations.  For
 990    example, if we use
 991
 992       (presence_set "slot1" "slot0")
 993
 994    the following insn will be never issued (because slot1 requires
 995    slot0 which is absent in the source state).
 996
 997       (define_reservation "insn_and_nop" "slot0 + slot1")
 998
 999    but it can be issued if we use analogous `final_presence_set'.  */
1000 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1001
1002 /* (absence_set string string) means that each CPU functional unit in
1003    the first string can be reserved only if each pattern of units
1004    whose names are in the second string is not reserved.  This is an
1005    asymmetric relation (actually exclusion set is analogous to this
1006    one but it is symmetric).  CPU units or unit patterns in the string
1007    are separated by commas.  Pattern is one unit name or unit names
1008    separated by white-spaces.
1009
1010    For example, it is useful for description that slot0 can not be
1011    reserved after slot1 or slot2 reservation for a VLIW processor.  We
1012    could describe it by the following construction
1013
1014       (absence_set "slot2" "slot0, slot1")
1015
1016    Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1017    slot1 and unit b1 are reserved .  In this case we could write
1018
1019       (absence_set "slot2" "slot0 b0, slot1 b1")
1020
1021    All CPU functional units in a set should to belong the same
1022    automaton.  */
1023 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1024
1025 /* (final_absence_set string string) is analogous to `absence_set' but
1026    checking is done on the result (state) reservation.  See comments
1027    for `final_presence_set'.  */
1028 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1029
1030 /* (define_bypass number out_insn_names in_insn_names) names bypass
1031    with given latency (the first number) from insns given by the first
1032    string (see define_insn_reservation) into insns given by the second
1033    string.  Insn names in the strings are separated by commas.  The
1034    third operand is optional name of function which is additional
1035    guard for the bypass.  The function will get the two insns as
1036    parameters.  If the function returns zero the bypass will be
1037    ignored for this case.  Additional guard is necessary to recognize
1038    complicated bypasses, e.g. when consumer is load address.  */
1039 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1040
1041 /* (define_automaton string) describes names of automata generated and
1042    used for pipeline hazards recognition.  The names are separated by
1043    comma.  Actually it is possibly to generate the single automaton
1044    but unfortunately it can be very large.  If we use more one
1045    automata, the summary size of the automata usually is less than the
1046    single one.  The automaton name is used in define_cpu_unit and
1047    define_query_cpu_unit.  All automata should have unique names.  */
1048 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1049
1050 /* (automata_option string) describes option for generation of
1051    automata.  Currently there are the following options:
1052
1053    o "no-minimization" which makes no minimization of automata.  This
1054      is only worth to do when we are debugging the description and
1055      need to look more accurately at reservations of states.
1056
1057    o "time" which means printing additional time statistics about
1058       generation of automata.
1059
1060    o "v" which means generation of file describing the result
1061      automata.  The file has suffix `.dfa' and can be used for the
1062      description verification and debugging.
1063
1064    o "w" which means generation of warning instead of error for
1065      non-critical errors.
1066
1067    o "ndfa" which makes nondeterministic finite state automata.
1068
1069    o "progress" which means output of a progress bar showing how many
1070      states were generated so far for automaton being processed.  */
1071 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1072
1073 /* (define_reservation string string) names reservation (the first
1074    string) of cpu functional units (the 2nd string).  Sometimes unit
1075    reservations for different insns contain common parts.  In such
1076    case, you can describe common part and use its name (the 1st
1077    parameter) in regular expression in define_insn_reservation.  All
1078    define_reservations, define_cpu_units, and define_query_cpu_units
1079    should have unique names which may not be "nothing".  */
1080 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1081
1082 /* (define_insn_reservation name default_latency condition regexpr)
1083    describes reservation of cpu functional units (the 3nd operand) for
1084    instruction which is selected by the condition (the 2nd parameter).
1085    The first parameter is used for output of debugging information.
1086    The reservations are described by a regular expression according
1087    the following syntax:
1088
1089        regexp = regexp "," oneof
1090               | oneof
1091
1092        oneof = oneof "|" allof
1093              | allof
1094
1095        allof = allof "+" repeat
1096              | repeat
1097
1098        repeat = element "*" number
1099               | element
1100
1101        element = cpu_function_unit_name
1102                | reservation_name
1103                | result_name
1104                | "nothing"
1105                | "(" regexp ")"
1106
1107        1. "," is used for describing start of the next cycle in
1108        reservation.
1109
1110        2. "|" is used for describing the reservation described by the
1111        first regular expression *or* the reservation described by the
1112        second regular expression *or* etc.
1113
1114        3. "+" is used for describing the reservation described by the
1115        first regular expression *and* the reservation described by the
1116        second regular expression *and* etc.
1117
1118        4. "*" is used for convenience and simply means sequence in
1119        which the regular expression are repeated NUMBER times with
1120        cycle advancing (see ",").
1121
1122        5. cpu functional unit name which means its reservation.
1123
1124        6. reservation name -- see define_reservation.
1125
1126        7. string "nothing" means no units reservation.  */
1127
1128 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1129
1130 /* Expressions used for insn attributes.  */
1131
1132 /* Definition of an insn attribute.
1133    1st operand: name of the attribute
1134    2nd operand: comma-separated list of possible attribute values
1135    3rd operand: expression for the default value of the attribute.  */
1136 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1137
1138 /* Marker for the name of an attribute.  */
1139 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1140
1141 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1142    in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1143    pattern.
1144
1145    (set_attr "name" "value") is equivalent to
1146    (set (attr "name") (const_string "value"))  */
1147 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1148
1149 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1150    specify that attribute values are to be assigned according to the
1151    alternative matched.
1152
1153    The following three expressions are equivalent:
1154
1155    (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1156                             (eq_attrq "alternative" "2") (const_string "a2")]
1157                            (const_string "a3")))
1158    (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1159                                  (const_string "a3")])
1160    (set_attr "att" "a1,a2,a3")
1161  */
1162 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1163
1164 /* A conditional expression true if the value of the specified attribute of
1165    the current insn equals the specified value.  The first operand is the
1166    attribute name and the second is the comparison value.  */
1167 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1168
1169 /* A special case of the above representing a set of alternatives.  The first
1170    operand is bitmap of the set, the second one is the default value.  */
1171 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1172
1173 /* A conditional expression which is true if the specified flag is
1174    true for the insn being scheduled in reorg.
1175
1176    genattr.c defines the following flags which can be tested by
1177    (attr_flag "foo") expressions in eligible_for_delay.
1178
1179    forward, backward, very_likely, likely, very_unlikely, and unlikely.  */
1180
1181 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1182
1183 /* General conditional. The first operand is a vector composed of pairs of
1184    expressions.  The first element of each pair is evaluated, in turn.
1185    The value of the conditional is the second expression of the first pair
1186    whose first expression evaluates nonzero.  If none of the expressions is
1187    true, the second operand will be used as the value of the conditional.  */
1188 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1189
1190 #endif /* GENERATOR_FILE */
1191
1192 /*
1193 Local variables:
1194 mode:c
1195 End:
1196 */