| blob | 5290e2b68c1ebcd23a24b832ed76629d36c5fb80 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
85 (UNSPEC_STFIWX 32)
86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
101 (UNSPEC_RSQRT 48)
102 (UNSPEC_TOCREL 49)
103 (UNSPEC_MACHOPIC_OFFSET 50)
104 ])
106 ;;
107 ;; UNSPEC_VOLATILE usage
108 ;;
110 (define_constants
111 [(UNSPECV_BLOCK 0)
112 (UNSPECV_LL 1) ; load-locked
113 (UNSPECV_SC 2) ; store-conditional
114 (UNSPECV_EH_RR 9) ; eh_reg_restore
115 ])
116 \f
117 ;; Define an insn type attribute. This is used in function unit delay
118 ;; computations.
119 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
120 (const_string "integer"))
122 ;; Define floating point instruction sub-types for use with Xfpu.md
123 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
125 ;; Length (in bytes).
126 ; '(pc)' in the following doesn't include the instruction itself; it is
127 ; calculated as if the instruction had zero size.
128 (define_attr "length" ""
129 (if_then_else (eq_attr "type" "branch")
130 (if_then_else (and (ge (minus (match_dup 0) (pc))
131 (const_int -32768))
132 (lt (minus (match_dup 0) (pc))
133 (const_int 32764)))
134 (const_int 4)
135 (const_int 8))
136 (const_int 4)))
138 ;; Processor type -- this attribute must exactly match the processor_type
139 ;; enumeration in rs6000.h.
141 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell"
142 (const (symbol_ref "rs6000_cpu_attr")))
145 ;; If this instruction is microcoded on the CELL processor
146 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
147 (define_attr "cell_micro" "not,conditional,always"
148 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
149 (const_string "always")
150 (const_string "not")))
152 (automata_option "ndfa")
154 (include "rios1.md")
155 (include "rios2.md")
156 (include "rs64.md")
157 (include "mpc.md")
158 (include "40x.md")
159 (include "440.md")
160 (include "603.md")
161 (include "6xx.md")
162 (include "7xx.md")
163 (include "7450.md")
164 (include "8540.md")
165 (include "e300c2c3.md")
166 (include "e500mc.md")
167 (include "power4.md")
168 (include "power5.md")
169 (include "power6.md")
170 (include "cell.md")
171 (include "xfpu.md")
173 (include "predicates.md")
174 (include "constraints.md")
176 (include "darwin.md")
178 \f
179 ;; Mode iterators
181 ; This mode iterator allows :GPR to be used to indicate the allowable size
182 ; of whole values in GPRs.
183 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
185 ; Any supported integer mode.
186 (define_mode_iterator INT [QI HI SI DI TI])
188 ; Any supported integer mode that fits in one register.
189 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
191 ; extend modes for DImode
192 (define_mode_iterator QHSI [QI HI SI])
194 ; SImode or DImode, even if DImode doesn't fit in GPRs.
195 (define_mode_iterator SDI [SI DI])
197 ; The size of a pointer. Also, the size of the value that a record-condition
198 ; (one with a '.') will compare.
199 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
201 ; Any hardware-supported floating-point mode
202 (define_mode_iterator FP [
203 (SF "TARGET_HARD_FLOAT
204 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
205 (DF "TARGET_HARD_FLOAT
206 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
207 (TF "!TARGET_IEEEQUAD
208 && TARGET_HARD_FLOAT
209 && (TARGET_FPRS || TARGET_E500_DOUBLE)
210 && TARGET_LONG_DOUBLE_128")
211 (DD "TARGET_DFP")
212 (TD "TARGET_DFP")])
214 ; Various instructions that come in SI and DI forms.
215 ; A generic w/d attribute, for things like cmpw/cmpd.
216 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
218 ; DImode bits
219 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
221 \f
222 ;; Start with fixed-point load and store insns. Here we put only the more
223 ;; complex forms. Basic data transfer is done later.
225 (define_expand "zero_extend<mode>di2"
226 [(set (match_operand:DI 0 "gpc_reg_operand" "")
227 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
228 "TARGET_POWERPC64"
229 "")
231 (define_insn "*zero_extend<mode>di2_internal1"
232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
233 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
234 "TARGET_POWERPC64"
235 "@
236 l<wd>z%U1%X1 %0,%1
237 rldicl %0,%1,0,<dbits>"
238 [(set_attr "type" "load,*")])
240 (define_insn "*zero_extend<mode>di2_internal2"
241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
242 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
243 (const_int 0)))
244 (clobber (match_scratch:DI 2 "=r,r"))]
245 "TARGET_64BIT"
246 "@
247 rldicl. %2,%1,0,<dbits>
248 #"
249 [(set_attr "type" "compare")
250 (set_attr "length" "4,8")])
252 (define_split
253 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
254 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
255 (const_int 0)))
256 (clobber (match_scratch:DI 2 ""))]
257 "TARGET_POWERPC64 && reload_completed"
258 [(set (match_dup 2)
259 (zero_extend:DI (match_dup 1)))
260 (set (match_dup 0)
261 (compare:CC (match_dup 2)
262 (const_int 0)))]
263 "")
265 (define_insn "*zero_extend<mode>di2_internal3"
266 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
267 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
268 (const_int 0)))
269 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
270 (zero_extend:DI (match_dup 1)))]
271 "TARGET_64BIT"
272 "@
273 rldicl. %0,%1,0,<dbits>
274 #"
275 [(set_attr "type" "compare")
276 (set_attr "length" "4,8")])
278 (define_split
279 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
280 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
281 (const_int 0)))
282 (set (match_operand:DI 0 "gpc_reg_operand" "")
283 (zero_extend:DI (match_dup 1)))]
284 "TARGET_POWERPC64 && reload_completed"
285 [(set (match_dup 0)
286 (zero_extend:DI (match_dup 1)))
287 (set (match_dup 2)
288 (compare:CC (match_dup 0)
289 (const_int 0)))]
290 "")
292 (define_insn "extendqidi2"
293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
294 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
295 "TARGET_POWERPC64"
296 "extsb %0,%1"
297 [(set_attr "type" "exts")])
299 (define_insn ""
300 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
301 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
302 (const_int 0)))
303 (clobber (match_scratch:DI 2 "=r,r"))]
304 "TARGET_64BIT"
305 "@
306 extsb. %2,%1
307 #"
308 [(set_attr "type" "compare")
309 (set_attr "length" "4,8")])
311 (define_split
312 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
313 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
314 (const_int 0)))
315 (clobber (match_scratch:DI 2 ""))]
316 "TARGET_POWERPC64 && reload_completed"
317 [(set (match_dup 2)
318 (sign_extend:DI (match_dup 1)))
319 (set (match_dup 0)
320 (compare:CC (match_dup 2)
321 (const_int 0)))]
322 "")
324 (define_insn ""
325 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
326 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
327 (const_int 0)))
328 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
329 (sign_extend:DI (match_dup 1)))]
330 "TARGET_64BIT"
331 "@
332 extsb. %0,%1
333 #"
334 [(set_attr "type" "compare")
335 (set_attr "length" "4,8")])
337 (define_split
338 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
339 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
340 (const_int 0)))
341 (set (match_operand:DI 0 "gpc_reg_operand" "")
342 (sign_extend:DI (match_dup 1)))]
343 "TARGET_POWERPC64 && reload_completed"
344 [(set (match_dup 0)
345 (sign_extend:DI (match_dup 1)))
346 (set (match_dup 2)
347 (compare:CC (match_dup 0)
348 (const_int 0)))]
349 "")
351 (define_expand "extendhidi2"
352 [(set (match_operand:DI 0 "gpc_reg_operand" "")
353 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
354 "TARGET_POWERPC64"
355 "")
357 (define_insn ""
358 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
359 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
360 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
361 "@
362 lha%U1%X1 %0,%1
363 extsh %0,%1"
364 [(set_attr "type" "load_ext,exts")])
366 (define_insn ""
367 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
368 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
369 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
370 "extsh %0,%1"
371 [(set_attr "type" "exts")])
373 (define_insn ""
374 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
375 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
376 (const_int 0)))
377 (clobber (match_scratch:DI 2 "=r,r"))]
378 "TARGET_64BIT"
379 "@
380 extsh. %2,%1
381 #"
382 [(set_attr "type" "compare")
383 (set_attr "length" "4,8")])
385 (define_split
386 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
387 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
388 (const_int 0)))
389 (clobber (match_scratch:DI 2 ""))]
390 "TARGET_POWERPC64 && reload_completed"
391 [(set (match_dup 2)
392 (sign_extend:DI (match_dup 1)))
393 (set (match_dup 0)
394 (compare:CC (match_dup 2)
395 (const_int 0)))]
396 "")
398 (define_insn ""
399 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
400 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
401 (const_int 0)))
402 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
403 (sign_extend:DI (match_dup 1)))]
404 "TARGET_64BIT"
405 "@
406 extsh. %0,%1
407 #"
408 [(set_attr "type" "compare")
409 (set_attr "length" "4,8")])
411 (define_split
412 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
413 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
414 (const_int 0)))
415 (set (match_operand:DI 0 "gpc_reg_operand" "")
416 (sign_extend:DI (match_dup 1)))]
417 "TARGET_POWERPC64 && reload_completed"
418 [(set (match_dup 0)
419 (sign_extend:DI (match_dup 1)))
420 (set (match_dup 2)
421 (compare:CC (match_dup 0)
422 (const_int 0)))]
423 "")
425 (define_expand "extendsidi2"
426 [(set (match_operand:DI 0 "gpc_reg_operand" "")
427 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
428 "TARGET_POWERPC64"
429 "")
431 (define_insn ""
432 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
433 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
434 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
435 "@
436 lwa%U1%X1 %0,%1
437 extsw %0,%1"
438 [(set_attr "type" "load_ext,exts")])
440 (define_insn ""
441 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
442 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
443 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
444 "extsw %0,%1"
445 [(set_attr "type" "exts")])
447 (define_insn ""
448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
449 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
450 (const_int 0)))
451 (clobber (match_scratch:DI 2 "=r,r"))]
452 "TARGET_64BIT"
453 "@
454 extsw. %2,%1
455 #"
456 [(set_attr "type" "compare")
457 (set_attr "length" "4,8")])
459 (define_split
460 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
461 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
462 (const_int 0)))
463 (clobber (match_scratch:DI 2 ""))]
464 "TARGET_POWERPC64 && reload_completed"
465 [(set (match_dup 2)
466 (sign_extend:DI (match_dup 1)))
467 (set (match_dup 0)
468 (compare:CC (match_dup 2)
469 (const_int 0)))]
470 "")
472 (define_insn ""
473 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
474 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
475 (const_int 0)))
476 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
477 (sign_extend:DI (match_dup 1)))]
478 "TARGET_64BIT"
479 "@
480 extsw. %0,%1
481 #"
482 [(set_attr "type" "compare")
483 (set_attr "length" "4,8")])
485 (define_split
486 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
487 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
488 (const_int 0)))
489 (set (match_operand:DI 0 "gpc_reg_operand" "")
490 (sign_extend:DI (match_dup 1)))]
491 "TARGET_POWERPC64 && reload_completed"
492 [(set (match_dup 0)
493 (sign_extend:DI (match_dup 1)))
494 (set (match_dup 2)
495 (compare:CC (match_dup 0)
496 (const_int 0)))]
497 "")
499 (define_expand "zero_extendqisi2"
500 [(set (match_operand:SI 0 "gpc_reg_operand" "")
501 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
502 ""
503 "")
505 (define_insn ""
506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
507 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
508 ""
509 "@
510 lbz%U1%X1 %0,%1
511 {rlinm|rlwinm} %0,%1,0,0xff"
512 [(set_attr "type" "load,*")])
514 (define_insn ""
515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
516 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
517 (const_int 0)))
518 (clobber (match_scratch:SI 2 "=r,r"))]
519 ""
520 "@
521 {andil.|andi.} %2,%1,0xff
522 #"
523 [(set_attr "type" "compare")
524 (set_attr "length" "4,8")])
526 (define_split
527 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
528 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
529 (const_int 0)))
530 (clobber (match_scratch:SI 2 ""))]
531 "reload_completed"
532 [(set (match_dup 2)
533 (zero_extend:SI (match_dup 1)))
534 (set (match_dup 0)
535 (compare:CC (match_dup 2)
536 (const_int 0)))]
537 "")
539 (define_insn ""
540 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
541 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
542 (const_int 0)))
543 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
544 (zero_extend:SI (match_dup 1)))]
545 ""
546 "@
547 {andil.|andi.} %0,%1,0xff
548 #"
549 [(set_attr "type" "compare")
550 (set_attr "length" "4,8")])
552 (define_split
553 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
554 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
555 (const_int 0)))
556 (set (match_operand:SI 0 "gpc_reg_operand" "")
557 (zero_extend:SI (match_dup 1)))]
558 "reload_completed"
559 [(set (match_dup 0)
560 (zero_extend:SI (match_dup 1)))
561 (set (match_dup 2)
562 (compare:CC (match_dup 0)
563 (const_int 0)))]
564 "")
566 (define_expand "extendqisi2"
567 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
568 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
569 ""
570 "
571 {
572 if (TARGET_POWERPC)
573 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
574 else if (TARGET_POWER)
575 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
576 else
577 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
578 DONE;
579 }")
581 (define_insn "extendqisi2_ppc"
582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
583 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
584 "TARGET_POWERPC"
585 "extsb %0,%1"
586 [(set_attr "type" "exts")])
588 (define_insn ""
589 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
590 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
591 (const_int 0)))
592 (clobber (match_scratch:SI 2 "=r,r"))]
593 "TARGET_POWERPC"
594 "@
595 extsb. %2,%1
596 #"
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
600 (define_split
601 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
602 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
603 (const_int 0)))
604 (clobber (match_scratch:SI 2 ""))]
605 "TARGET_POWERPC && reload_completed"
606 [(set (match_dup 2)
607 (sign_extend:SI (match_dup 1)))
608 (set (match_dup 0)
609 (compare:CC (match_dup 2)
610 (const_int 0)))]
611 "")
613 (define_insn ""
614 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
615 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
616 (const_int 0)))
617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
618 (sign_extend:SI (match_dup 1)))]
619 "TARGET_POWERPC"
620 "@
621 extsb. %0,%1
622 #"
623 [(set_attr "type" "compare")
624 (set_attr "length" "4,8")])
626 (define_split
627 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
628 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
629 (const_int 0)))
630 (set (match_operand:SI 0 "gpc_reg_operand" "")
631 (sign_extend:SI (match_dup 1)))]
632 "TARGET_POWERPC && reload_completed"
633 [(set (match_dup 0)
634 (sign_extend:SI (match_dup 1)))
635 (set (match_dup 2)
636 (compare:CC (match_dup 0)
637 (const_int 0)))]
638 "")
640 (define_expand "extendqisi2_power"
641 [(parallel [(set (match_dup 2)
642 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
643 (const_int 24)))
644 (clobber (scratch:SI))])
645 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
646 (ashiftrt:SI (match_dup 2)
647 (const_int 24)))
648 (clobber (scratch:SI))])]
649 "TARGET_POWER"
650 "
651 { operands[1] = gen_lowpart (SImode, operands[1]);
652 operands[2] = gen_reg_rtx (SImode); }")
654 (define_expand "extendqisi2_no_power"
655 [(set (match_dup 2)
656 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
657 (const_int 24)))
658 (set (match_operand:SI 0 "gpc_reg_operand" "")
659 (ashiftrt:SI (match_dup 2)
660 (const_int 24)))]
661 "! TARGET_POWER && ! TARGET_POWERPC"
662 "
663 { operands[1] = gen_lowpart (SImode, operands[1]);
664 operands[2] = gen_reg_rtx (SImode); }")
666 (define_expand "zero_extendqihi2"
667 [(set (match_operand:HI 0 "gpc_reg_operand" "")
668 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
669 ""
670 "")
672 (define_insn ""
673 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
674 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
675 ""
676 "@
677 lbz%U1%X1 %0,%1
678 {rlinm|rlwinm} %0,%1,0,0xff"
679 [(set_attr "type" "load,*")])
681 (define_insn ""
682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
683 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
684 (const_int 0)))
685 (clobber (match_scratch:HI 2 "=r,r"))]
686 ""
687 "@
688 {andil.|andi.} %2,%1,0xff
689 #"
690 [(set_attr "type" "compare")
691 (set_attr "length" "4,8")])
693 (define_split
694 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
695 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
696 (const_int 0)))
697 (clobber (match_scratch:HI 2 ""))]
698 "reload_completed"
699 [(set (match_dup 2)
700 (zero_extend:HI (match_dup 1)))
701 (set (match_dup 0)
702 (compare:CC (match_dup 2)
703 (const_int 0)))]
704 "")
706 (define_insn ""
707 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
708 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
709 (const_int 0)))
710 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
711 (zero_extend:HI (match_dup 1)))]
712 ""
713 "@
714 {andil.|andi.} %0,%1,0xff
715 #"
716 [(set_attr "type" "compare")
717 (set_attr "length" "4,8")])
719 (define_split
720 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
721 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
722 (const_int 0)))
723 (set (match_operand:HI 0 "gpc_reg_operand" "")
724 (zero_extend:HI (match_dup 1)))]
725 "reload_completed"
726 [(set (match_dup 0)
727 (zero_extend:HI (match_dup 1)))
728 (set (match_dup 2)
729 (compare:CC (match_dup 0)
730 (const_int 0)))]
731 "")
733 (define_expand "extendqihi2"
734 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
735 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
736 ""
737 "
738 {
739 if (TARGET_POWERPC)
740 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
741 else if (TARGET_POWER)
742 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
743 else
744 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
745 DONE;
746 }")
748 (define_insn "extendqihi2_ppc"
749 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
750 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
751 "TARGET_POWERPC"
752 "extsb %0,%1"
753 [(set_attr "type" "exts")])
755 (define_insn ""
756 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
757 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
758 (const_int 0)))
759 (clobber (match_scratch:HI 2 "=r,r"))]
760 "TARGET_POWERPC"
761 "@
762 extsb. %2,%1
763 #"
764 [(set_attr "type" "compare")
765 (set_attr "length" "4,8")])
767 (define_split
768 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
769 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
770 (const_int 0)))
771 (clobber (match_scratch:HI 2 ""))]
772 "TARGET_POWERPC && reload_completed"
773 [(set (match_dup 2)
774 (sign_extend:HI (match_dup 1)))
775 (set (match_dup 0)
776 (compare:CC (match_dup 2)
777 (const_int 0)))]
778 "")
780 (define_insn ""
781 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
782 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
783 (const_int 0)))
784 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
785 (sign_extend:HI (match_dup 1)))]
786 "TARGET_POWERPC"
787 "@
788 extsb. %0,%1
789 #"
790 [(set_attr "type" "compare")
791 (set_attr "length" "4,8")])
793 (define_split
794 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
795 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
796 (const_int 0)))
797 (set (match_operand:HI 0 "gpc_reg_operand" "")
798 (sign_extend:HI (match_dup 1)))]
799 "TARGET_POWERPC && reload_completed"
800 [(set (match_dup 0)
801 (sign_extend:HI (match_dup 1)))
802 (set (match_dup 2)
803 (compare:CC (match_dup 0)
804 (const_int 0)))]
805 "")
807 (define_expand "extendqihi2_power"
808 [(parallel [(set (match_dup 2)
809 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
810 (const_int 24)))
811 (clobber (scratch:SI))])
812 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
813 (ashiftrt:SI (match_dup 2)
814 (const_int 24)))
815 (clobber (scratch:SI))])]
816 "TARGET_POWER"
817 "
818 { operands[0] = gen_lowpart (SImode, operands[0]);
819 operands[1] = gen_lowpart (SImode, operands[1]);
820 operands[2] = gen_reg_rtx (SImode); }")
822 (define_expand "extendqihi2_no_power"
823 [(set (match_dup 2)
824 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
825 (const_int 24)))
826 (set (match_operand:HI 0 "gpc_reg_operand" "")
827 (ashiftrt:SI (match_dup 2)
828 (const_int 24)))]
829 "! TARGET_POWER && ! TARGET_POWERPC"
830 "
831 { operands[0] = gen_lowpart (SImode, operands[0]);
832 operands[1] = gen_lowpart (SImode, operands[1]);
833 operands[2] = gen_reg_rtx (SImode); }")
835 (define_expand "zero_extendhisi2"
836 [(set (match_operand:SI 0 "gpc_reg_operand" "")
837 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
838 ""
839 "")
841 (define_insn ""
842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
843 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
844 ""
845 "@
846 lhz%U1%X1 %0,%1
847 {rlinm|rlwinm} %0,%1,0,0xffff"
848 [(set_attr "type" "load,*")])
850 (define_insn ""
851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
852 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
853 (const_int 0)))
854 (clobber (match_scratch:SI 2 "=r,r"))]
855 ""
856 "@
857 {andil.|andi.} %2,%1,0xffff
858 #"
859 [(set_attr "type" "compare")
860 (set_attr "length" "4,8")])
862 (define_split
863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
864 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
865 (const_int 0)))
866 (clobber (match_scratch:SI 2 ""))]
867 "reload_completed"
868 [(set (match_dup 2)
869 (zero_extend:SI (match_dup 1)))
870 (set (match_dup 0)
871 (compare:CC (match_dup 2)
872 (const_int 0)))]
873 "")
875 (define_insn ""
876 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
878 (const_int 0)))
879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
880 (zero_extend:SI (match_dup 1)))]
881 ""
882 "@
883 {andil.|andi.} %0,%1,0xffff
884 #"
885 [(set_attr "type" "compare")
886 (set_attr "length" "4,8")])
888 (define_split
889 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
891 (const_int 0)))
892 (set (match_operand:SI 0 "gpc_reg_operand" "")
893 (zero_extend:SI (match_dup 1)))]
894 "reload_completed"
895 [(set (match_dup 0)
896 (zero_extend:SI (match_dup 1)))
897 (set (match_dup 2)
898 (compare:CC (match_dup 0)
899 (const_int 0)))]
900 "")
902 (define_expand "extendhisi2"
903 [(set (match_operand:SI 0 "gpc_reg_operand" "")
904 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
905 ""
906 "")
908 (define_insn ""
909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
910 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
911 "rs6000_gen_cell_microcode"
912 "@
913 lha%U1%X1 %0,%1
914 {exts|extsh} %0,%1"
915 [(set_attr "type" "load_ext,exts")])
917 (define_insn ""
918 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
919 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
920 "!rs6000_gen_cell_microcode"
921 "{exts|extsh} %0,%1"
922 [(set_attr "type" "exts")])
924 (define_insn ""
925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
926 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
927 (const_int 0)))
928 (clobber (match_scratch:SI 2 "=r,r"))]
929 ""
930 "@
931 {exts.|extsh.} %2,%1
932 #"
933 [(set_attr "type" "compare")
934 (set_attr "length" "4,8")])
936 (define_split
937 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
938 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
939 (const_int 0)))
940 (clobber (match_scratch:SI 2 ""))]
941 "reload_completed"
942 [(set (match_dup 2)
943 (sign_extend:SI (match_dup 1)))
944 (set (match_dup 0)
945 (compare:CC (match_dup 2)
946 (const_int 0)))]
947 "")
949 (define_insn ""
950 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
951 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
952 (const_int 0)))
953 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
954 (sign_extend:SI (match_dup 1)))]
955 ""
956 "@
957 {exts.|extsh.} %0,%1
958 #"
959 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")])
961 \f
962 ;; IBM 405, 440 and 464 half-word multiplication operations.
964 (define_insn "*macchwc"
965 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
966 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
967 (match_operand:SI 2 "gpc_reg_operand" "r")
968 (const_int 16))
969 (sign_extend:SI
970 (match_operand:HI 1 "gpc_reg_operand" "r")))
971 (match_operand:SI 4 "gpc_reg_operand" "0"))
972 (const_int 0)))
973 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
974 (plus:SI (mult:SI (ashiftrt:SI
975 (match_dup 2)
976 (const_int 16))
977 (sign_extend:SI
978 (match_dup 1)))
979 (match_dup 4)))]
980 "TARGET_MULHW"
981 "macchw. %0, %1, %2"
982 [(set_attr "type" "imul3")])
984 (define_insn "*macchw"
985 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
986 (plus:SI (mult:SI (ashiftrt:SI
987 (match_operand:SI 2 "gpc_reg_operand" "r")
988 (const_int 16))
989 (sign_extend:SI
990 (match_operand:HI 1 "gpc_reg_operand" "r")))
991 (match_operand:SI 3 "gpc_reg_operand" "0")))]
992 "TARGET_MULHW"
993 "macchw %0, %1, %2"
994 [(set_attr "type" "imul3")])
996 (define_insn "*macchwuc"
997 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
998 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
999 (match_operand:SI 2 "gpc_reg_operand" "r")
1000 (const_int 16))
1001 (zero_extend:SI
1002 (match_operand:HI 1 "gpc_reg_operand" "r")))
1003 (match_operand:SI 4 "gpc_reg_operand" "0"))
1004 (const_int 0)))
1005 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1006 (plus:SI (mult:SI (lshiftrt:SI
1007 (match_dup 2)
1008 (const_int 16))
1009 (zero_extend:SI
1010 (match_dup 1)))
1011 (match_dup 4)))]
1012 "TARGET_MULHW"
1013 "macchwu. %0, %1, %2"
1014 [(set_attr "type" "imul3")])
1016 (define_insn "*macchwu"
1017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1018 (plus:SI (mult:SI (lshiftrt:SI
1019 (match_operand:SI 2 "gpc_reg_operand" "r")
1020 (const_int 16))
1021 (zero_extend:SI
1022 (match_operand:HI 1 "gpc_reg_operand" "r")))
1023 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1024 "TARGET_MULHW"
1025 "macchwu %0, %1, %2"
1026 [(set_attr "type" "imul3")])
1028 (define_insn "*machhwc"
1029 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1030 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1031 (match_operand:SI 1 "gpc_reg_operand" "%r")
1032 (const_int 16))
1033 (ashiftrt:SI
1034 (match_operand:SI 2 "gpc_reg_operand" "r")
1035 (const_int 16)))
1036 (match_operand:SI 4 "gpc_reg_operand" "0"))
1037 (const_int 0)))
1038 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1039 (plus:SI (mult:SI (ashiftrt:SI
1040 (match_dup 1)
1041 (const_int 16))
1042 (ashiftrt:SI
1043 (match_dup 2)
1044 (const_int 16)))
1045 (match_dup 4)))]
1046 "TARGET_MULHW"
1047 "machhw. %0, %1, %2"
1048 [(set_attr "type" "imul3")])
1050 (define_insn "*machhw"
1051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (ashiftrt:SI
1053 (match_operand:SI 1 "gpc_reg_operand" "%r")
1054 (const_int 16))
1055 (ashiftrt:SI
1056 (match_operand:SI 2 "gpc_reg_operand" "r")
1057 (const_int 16)))
1058 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1059 "TARGET_MULHW"
1060 "machhw %0, %1, %2"
1061 [(set_attr "type" "imul3")])
1063 (define_insn "*machhwuc"
1064 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1065 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1066 (match_operand:SI 1 "gpc_reg_operand" "%r")
1067 (const_int 16))
1068 (lshiftrt:SI
1069 (match_operand:SI 2 "gpc_reg_operand" "r")
1070 (const_int 16)))
1071 (match_operand:SI 4 "gpc_reg_operand" "0"))
1072 (const_int 0)))
1073 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1074 (plus:SI (mult:SI (lshiftrt:SI
1075 (match_dup 1)
1076 (const_int 16))
1077 (lshiftrt:SI
1078 (match_dup 2)
1079 (const_int 16)))
1080 (match_dup 4)))]
1081 "TARGET_MULHW"
1082 "machhwu. %0, %1, %2"
1083 [(set_attr "type" "imul3")])
1085 (define_insn "*machhwu"
1086 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1087 (plus:SI (mult:SI (lshiftrt:SI
1088 (match_operand:SI 1 "gpc_reg_operand" "%r")
1089 (const_int 16))
1090 (lshiftrt:SI
1091 (match_operand:SI 2 "gpc_reg_operand" "r")
1092 (const_int 16)))
1093 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1094 "TARGET_MULHW"
1095 "machhwu %0, %1, %2"
1096 [(set_attr "type" "imul3")])
1098 (define_insn "*maclhwc"
1099 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1100 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1101 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1102 (sign_extend:SI
1103 (match_operand:HI 2 "gpc_reg_operand" "r")))
1104 (match_operand:SI 4 "gpc_reg_operand" "0"))
1105 (const_int 0)))
1106 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1107 (plus:SI (mult:SI (sign_extend:SI
1108 (match_dup 1))
1109 (sign_extend:SI
1110 (match_dup 2)))
1111 (match_dup 4)))]
1112 "TARGET_MULHW"
1113 "maclhw. %0, %1, %2"
1114 [(set_attr "type" "imul3")])
1116 (define_insn "*maclhw"
1117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1118 (plus:SI (mult:SI (sign_extend:SI
1119 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1120 (sign_extend:SI
1121 (match_operand:HI 2 "gpc_reg_operand" "r")))
1122 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1123 "TARGET_MULHW"
1124 "maclhw %0, %1, %2"
1125 [(set_attr "type" "imul3")])
1127 (define_insn "*maclhwuc"
1128 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1129 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1130 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1131 (zero_extend:SI
1132 (match_operand:HI 2 "gpc_reg_operand" "r")))
1133 (match_operand:SI 4 "gpc_reg_operand" "0"))
1134 (const_int 0)))
1135 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1136 (plus:SI (mult:SI (zero_extend:SI
1137 (match_dup 1))
1138 (zero_extend:SI
1139 (match_dup 2)))
1140 (match_dup 4)))]
1141 "TARGET_MULHW"
1142 "maclhwu. %0, %1, %2"
1143 [(set_attr "type" "imul3")])
1145 (define_insn "*maclhwu"
1146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1147 (plus:SI (mult:SI (zero_extend:SI
1148 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1149 (zero_extend:SI
1150 (match_operand:HI 2 "gpc_reg_operand" "r")))
1151 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1152 "TARGET_MULHW"
1153 "maclhwu %0, %1, %2"
1154 [(set_attr "type" "imul3")])
1156 (define_insn "*nmacchwc"
1157 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1158 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1159 (mult:SI (ashiftrt:SI
1160 (match_operand:SI 2 "gpc_reg_operand" "r")
1161 (const_int 16))
1162 (sign_extend:SI
1163 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1164 (const_int 0)))
1165 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166 (minus:SI (match_dup 4)
1167 (mult:SI (ashiftrt:SI
1168 (match_dup 2)
1169 (const_int 16))
1170 (sign_extend:SI
1171 (match_dup 1)))))]
1172 "TARGET_MULHW"
1173 "nmacchw. %0, %1, %2"
1174 [(set_attr "type" "imul3")])
1176 (define_insn "*nmacchw"
1177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1178 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1179 (mult:SI (ashiftrt:SI
1180 (match_operand:SI 2 "gpc_reg_operand" "r")
1181 (const_int 16))
1182 (sign_extend:SI
1183 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1184 "TARGET_MULHW"
1185 "nmacchw %0, %1, %2"
1186 [(set_attr "type" "imul3")])
1188 (define_insn "*nmachhwc"
1189 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1190 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1191 (mult:SI (ashiftrt:SI
1192 (match_operand:SI 1 "gpc_reg_operand" "%r")
1193 (const_int 16))
1194 (ashiftrt:SI
1195 (match_operand:SI 2 "gpc_reg_operand" "r")
1196 (const_int 16))))
1197 (const_int 0)))
1198 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1199 (minus:SI (match_dup 4)
1200 (mult:SI (ashiftrt:SI
1201 (match_dup 1)
1202 (const_int 16))
1203 (ashiftrt:SI
1204 (match_dup 2)
1205 (const_int 16)))))]
1206 "TARGET_MULHW"
1207 "nmachhw. %0, %1, %2"
1208 [(set_attr "type" "imul3")])
1210 (define_insn "*nmachhw"
1211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1212 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1213 (mult:SI (ashiftrt:SI
1214 (match_operand:SI 1 "gpc_reg_operand" "%r")
1215 (const_int 16))
1216 (ashiftrt:SI
1217 (match_operand:SI 2 "gpc_reg_operand" "r")
1218 (const_int 16)))))]
1219 "TARGET_MULHW"
1220 "nmachhw %0, %1, %2"
1221 [(set_attr "type" "imul3")])
1223 (define_insn "*nmaclhwc"
1224 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1225 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1226 (mult:SI (sign_extend:SI
1227 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1228 (sign_extend:SI
1229 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1230 (const_int 0)))
1231 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1232 (minus:SI (match_dup 4)
1233 (mult:SI (sign_extend:SI
1234 (match_dup 1))
1235 (sign_extend:SI
1236 (match_dup 2)))))]
1237 "TARGET_MULHW"
1238 "nmaclhw. %0, %1, %2"
1239 [(set_attr "type" "imul3")])
1241 (define_insn "*nmaclhw"
1242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1243 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1244 (mult:SI (sign_extend:SI
1245 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1246 (sign_extend:SI
1247 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1248 "TARGET_MULHW"
1249 "nmaclhw %0, %1, %2"
1250 [(set_attr "type" "imul3")])
1252 (define_insn "*mulchwc"
1253 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1254 (compare:CC (mult:SI (ashiftrt:SI
1255 (match_operand:SI 2 "gpc_reg_operand" "r")
1256 (const_int 16))
1257 (sign_extend:SI
1258 (match_operand:HI 1 "gpc_reg_operand" "r")))
1259 (const_int 0)))
1260 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1261 (mult:SI (ashiftrt:SI
1262 (match_dup 2)
1263 (const_int 16))
1264 (sign_extend:SI
1265 (match_dup 1))))]
1266 "TARGET_MULHW"
1267 "mulchw. %0, %1, %2"
1268 [(set_attr "type" "imul3")])
1270 (define_insn "*mulchw"
1271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1272 (mult:SI (ashiftrt:SI
1273 (match_operand:SI 2 "gpc_reg_operand" "r")
1274 (const_int 16))
1275 (sign_extend:SI
1276 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1277 "TARGET_MULHW"
1278 "mulchw %0, %1, %2"
1279 [(set_attr "type" "imul3")])
1281 (define_insn "*mulchwuc"
1282 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1283 (compare:CC (mult:SI (lshiftrt:SI
1284 (match_operand:SI 2 "gpc_reg_operand" "r")
1285 (const_int 16))
1286 (zero_extend:SI
1287 (match_operand:HI 1 "gpc_reg_operand" "r")))
1288 (const_int 0)))
1289 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1290 (mult:SI (lshiftrt:SI
1291 (match_dup 2)
1292 (const_int 16))
1293 (zero_extend:SI
1294 (match_dup 1))))]
1295 "TARGET_MULHW"
1296 "mulchwu. %0, %1, %2"
1297 [(set_attr "type" "imul3")])
1299 (define_insn "*mulchwu"
1300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1301 (mult:SI (lshiftrt:SI
1302 (match_operand:SI 2 "gpc_reg_operand" "r")
1303 (const_int 16))
1304 (zero_extend:SI
1305 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1306 "TARGET_MULHW"
1307 "mulchwu %0, %1, %2"
1308 [(set_attr "type" "imul3")])
1310 (define_insn "*mulhhwc"
1311 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1312 (compare:CC (mult:SI (ashiftrt:SI
1313 (match_operand:SI 1 "gpc_reg_operand" "%r")
1314 (const_int 16))
1315 (ashiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16)))
1318 (const_int 0)))
1319 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1320 (mult:SI (ashiftrt:SI
1321 (match_dup 1)
1322 (const_int 16))
1323 (ashiftrt:SI
1324 (match_dup 2)
1325 (const_int 16))))]
1326 "TARGET_MULHW"
1327 "mulhhw. %0, %1, %2"
1328 [(set_attr "type" "imul3")])
1330 (define_insn "*mulhhw"
1331 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1332 (mult:SI (ashiftrt:SI
1333 (match_operand:SI 1 "gpc_reg_operand" "%r")
1334 (const_int 16))
1335 (ashiftrt:SI
1336 (match_operand:SI 2 "gpc_reg_operand" "r")
1337 (const_int 16))))]
1338 "TARGET_MULHW"
1339 "mulhhw %0, %1, %2"
1340 [(set_attr "type" "imul3")])
1342 (define_insn "*mulhhwuc"
1343 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1344 (compare:CC (mult:SI (lshiftrt:SI
1345 (match_operand:SI 1 "gpc_reg_operand" "%r")
1346 (const_int 16))
1347 (lshiftrt:SI
1348 (match_operand:SI 2 "gpc_reg_operand" "r")
1349 (const_int 16)))
1350 (const_int 0)))
1351 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1352 (mult:SI (lshiftrt:SI
1353 (match_dup 1)
1354 (const_int 16))
1355 (lshiftrt:SI
1356 (match_dup 2)
1357 (const_int 16))))]
1358 "TARGET_MULHW"
1359 "mulhhwu. %0, %1, %2"
1360 [(set_attr "type" "imul3")])
1362 (define_insn "*mulhhwu"
1363 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1364 (mult:SI (lshiftrt:SI
1365 (match_operand:SI 1 "gpc_reg_operand" "%r")
1366 (const_int 16))
1367 (lshiftrt:SI
1368 (match_operand:SI 2 "gpc_reg_operand" "r")
1369 (const_int 16))))]
1370 "TARGET_MULHW"
1371 "mulhhwu %0, %1, %2"
1372 [(set_attr "type" "imul3")])
1374 (define_insn "*mullhwc"
1375 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1376 (compare:CC (mult:SI (sign_extend:SI
1377 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1378 (sign_extend:SI
1379 (match_operand:HI 2 "gpc_reg_operand" "r")))
1380 (const_int 0)))
1381 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1382 (mult:SI (sign_extend:SI
1383 (match_dup 1))
1384 (sign_extend:SI
1385 (match_dup 2))))]
1386 "TARGET_MULHW"
1387 "mullhw. %0, %1, %2"
1388 [(set_attr "type" "imul3")])
1390 (define_insn "*mullhw"
1391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1392 (mult:SI (sign_extend:SI
1393 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1394 (sign_extend:SI
1395 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1396 "TARGET_MULHW"
1397 "mullhw %0, %1, %2"
1398 [(set_attr "type" "imul3")])
1400 (define_insn "*mullhwuc"
1401 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1402 (compare:CC (mult:SI (zero_extend:SI
1403 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1404 (zero_extend:SI
1405 (match_operand:HI 2 "gpc_reg_operand" "r")))
1406 (const_int 0)))
1407 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1408 (mult:SI (zero_extend:SI
1409 (match_dup 1))
1410 (zero_extend:SI
1411 (match_dup 2))))]
1412 "TARGET_MULHW"
1413 "mullhwu. %0, %1, %2"
1414 [(set_attr "type" "imul3")])
1416 (define_insn "*mullhwu"
1417 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1418 (mult:SI (zero_extend:SI
1419 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1420 (zero_extend:SI
1421 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1422 "TARGET_MULHW"
1423 "mullhwu %0, %1, %2"
1424 [(set_attr "type" "imul3")])
1425 \f
1426 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1427 (define_insn "dlmzb"
1428 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1429 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1430 (match_operand:SI 2 "gpc_reg_operand" "r")]
1431 UNSPEC_DLMZB_CR))
1432 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1433 (unspec:SI [(match_dup 1)
1434 (match_dup 2)]
1435 UNSPEC_DLMZB))]
1436 "TARGET_DLMZB"
1437 "dlmzb. %0, %1, %2")
1439 (define_expand "strlensi"
1440 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1441 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1442 (match_operand:QI 2 "const_int_operand" "")
1443 (match_operand 3 "const_int_operand" "")]
1444 UNSPEC_DLMZB_STRLEN))
1445 (clobber (match_scratch:CC 4 "=x"))]
1446 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1447 {
1448 rtx result = operands[0];
1449 rtx src = operands[1];
1450 rtx search_char = operands[2];
1451 rtx align = operands[3];
1452 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1453 rtx loop_label, end_label, mem, cr0, cond;
1454 if (search_char != const0_rtx
1455 || GET_CODE (align) != CONST_INT
1456 || INTVAL (align) < 8)
1457 FAIL;
1458 word1 = gen_reg_rtx (SImode);
1459 word2 = gen_reg_rtx (SImode);
1460 scratch_dlmzb = gen_reg_rtx (SImode);
1461 scratch_string = gen_reg_rtx (Pmode);
1462 loop_label = gen_label_rtx ();
1463 end_label = gen_label_rtx ();
1464 addr = force_reg (Pmode, XEXP (src, 0));
1465 emit_move_insn (scratch_string, addr);
1466 emit_label (loop_label);
1467 mem = change_address (src, SImode, scratch_string);
1468 emit_move_insn (word1, mem);
1469 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1470 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1471 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1472 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1473 emit_jump_insn (gen_rtx_SET (VOIDmode,
1474 pc_rtx,
1475 gen_rtx_IF_THEN_ELSE (VOIDmode,
1476 cond,
1477 gen_rtx_LABEL_REF
1478 (VOIDmode,
1479 end_label),
1480 pc_rtx)));
1481 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1482 emit_jump_insn (gen_rtx_SET (VOIDmode,
1483 pc_rtx,
1484 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1485 emit_barrier ();
1486 emit_label (end_label);
1487 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1488 emit_insn (gen_subsi3 (result, scratch_string, addr));
1489 emit_insn (gen_subsi3 (result, result, const1_rtx));
1490 DONE;
1491 })
1492 \f
1493 (define_split
1494 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1495 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1496 (const_int 0)))
1497 (set (match_operand:SI 0 "gpc_reg_operand" "")
1498 (sign_extend:SI (match_dup 1)))]
1499 "reload_completed"
1500 [(set (match_dup 0)
1501 (sign_extend:SI (match_dup 1)))
1502 (set (match_dup 2)
1503 (compare:CC (match_dup 0)
1504 (const_int 0)))]
1505 "")
1507 ;; Fixed-point arithmetic insns.
1509 (define_expand "add<mode>3"
1510 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1511 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1512 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1513 ""
1514 {
1515 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1516 {
1517 if (non_short_cint_operand (operands[2], DImode))
1518 FAIL;
1519 }
1520 else if (GET_CODE (operands[2]) == CONST_INT
1521 && ! add_operand (operands[2], <MODE>mode))
1522 {
1523 rtx tmp = ((!can_create_pseudo_p ()
1524 || rtx_equal_p (operands[0], operands[1]))
1525 ? operands[0] : gen_reg_rtx (<MODE>mode));
1527 HOST_WIDE_INT val = INTVAL (operands[2]);
1528 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1529 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1531 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1532 FAIL;
1534 /* The ordering here is important for the prolog expander.
1535 When space is allocated from the stack, adding 'low' first may
1536 produce a temporary deallocation (which would be bad). */
1537 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1538 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1539 DONE;
1540 }
1541 })
1543 ;; Discourage ai/addic because of carry but provide it in an alternative
1544 ;; allowing register zero as source.
1545 (define_insn "*add<mode>3_internal1"
1546 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1547 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1548 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1549 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1550 "@
1551 {cax|add} %0,%1,%2
1552 {cal %0,%2(%1)|addi %0,%1,%2}
1553 {ai|addic} %0,%1,%2
1554 {cau|addis} %0,%1,%v2"
1555 [(set_attr "length" "4,4,4,4")])
1557 (define_insn "addsi3_high"
1558 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1559 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1560 (high:SI (match_operand 2 "" ""))))]
1561 "TARGET_MACHO && !TARGET_64BIT"
1562 "{cau|addis} %0,%1,ha16(%2)"
1563 [(set_attr "length" "4")])
1565 (define_insn "*add<mode>3_internal2"
1566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1567 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1568 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1569 (const_int 0)))
1570 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1571 ""
1572 "@
1573 {cax.|add.} %3,%1,%2
1574 {ai.|addic.} %3,%1,%2
1575 #
1576 #"
1577 [(set_attr "type" "fast_compare,compare,compare,compare")
1578 (set_attr "length" "4,4,8,8")])
1580 (define_split
1581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1582 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1583 (match_operand:GPR 2 "reg_or_short_operand" ""))
1584 (const_int 0)))
1585 (clobber (match_scratch:GPR 3 ""))]
1586 "reload_completed"
1587 [(set (match_dup 3)
1588 (plus:GPR (match_dup 1)
1589 (match_dup 2)))
1590 (set (match_dup 0)
1591 (compare:CC (match_dup 3)
1592 (const_int 0)))]
1593 "")
1595 (define_insn "*add<mode>3_internal3"
1596 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1597 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1598 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1599 (const_int 0)))
1600 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1601 (plus:P (match_dup 1)
1602 (match_dup 2)))]
1603 ""
1604 "@
1605 {cax.|add.} %0,%1,%2
1606 {ai.|addic.} %0,%1,%2
1607 #
1608 #"
1609 [(set_attr "type" "fast_compare,compare,compare,compare")
1610 (set_attr "length" "4,4,8,8")])
1612 (define_split
1613 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1614 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1615 (match_operand:P 2 "reg_or_short_operand" ""))
1616 (const_int 0)))
1617 (set (match_operand:P 0 "gpc_reg_operand" "")
1618 (plus:P (match_dup 1) (match_dup 2)))]
1619 "reload_completed"
1620 [(set (match_dup 0)
1621 (plus:P (match_dup 1)
1622 (match_dup 2)))
1623 (set (match_dup 3)
1624 (compare:CC (match_dup 0)
1625 (const_int 0)))]
1626 "")
1628 ;; Split an add that we can't do in one insn into two insns, each of which
1629 ;; does one 16-bit part. This is used by combine. Note that the low-order
1630 ;; add should be last in case the result gets used in an address.
1632 (define_split
1633 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1634 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1635 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1636 ""
1637 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1638 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1639 {
1640 HOST_WIDE_INT val = INTVAL (operands[2]);
1641 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1642 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1644 operands[4] = GEN_INT (low);
1645 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1646 operands[3] = GEN_INT (rest);
1647 else if (can_create_pseudo_p ())
1648 {
1649 operands[3] = gen_reg_rtx (DImode);
1650 emit_move_insn (operands[3], operands[2]);
1651 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1652 DONE;
1653 }
1654 else
1655 FAIL;
1656 })
1658 (define_insn "one_cmpl<mode>2"
1659 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1660 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1661 ""
1662 "nor %0,%1,%1")
1664 (define_insn ""
1665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1666 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1667 (const_int 0)))
1668 (clobber (match_scratch:P 2 "=r,r"))]
1669 ""
1670 "@
1671 nor. %2,%1,%1
1672 #"
1673 [(set_attr "type" "compare")
1674 (set_attr "length" "4,8")])
1676 (define_split
1677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1678 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1679 (const_int 0)))
1680 (clobber (match_scratch:P 2 ""))]
1681 "reload_completed"
1682 [(set (match_dup 2)
1683 (not:P (match_dup 1)))
1684 (set (match_dup 0)
1685 (compare:CC (match_dup 2)
1686 (const_int 0)))]
1687 "")
1689 (define_insn ""
1690 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1691 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1692 (const_int 0)))
1693 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1694 (not:P (match_dup 1)))]
1695 ""
1696 "@
1697 nor. %0,%1,%1
1698 #"
1699 [(set_attr "type" "compare")
1700 (set_attr "length" "4,8")])
1702 (define_split
1703 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1705 (const_int 0)))
1706 (set (match_operand:P 0 "gpc_reg_operand" "")
1707 (not:P (match_dup 1)))]
1708 "reload_completed"
1709 [(set (match_dup 0)
1710 (not:P (match_dup 1)))
1711 (set (match_dup 2)
1712 (compare:CC (match_dup 0)
1713 (const_int 0)))]
1714 "")
1716 (define_insn ""
1717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1718 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1719 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1720 "! TARGET_POWERPC"
1721 "{sf%I1|subf%I1c} %0,%2,%1")
1723 (define_insn ""
1724 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1725 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1726 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1727 "TARGET_POWERPC"
1728 "@
1729 subf %0,%2,%1
1730 subfic %0,%2,%1")
1732 (define_insn ""
1733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1734 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1735 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1736 (const_int 0)))
1737 (clobber (match_scratch:SI 3 "=r,r"))]
1738 "! TARGET_POWERPC"
1739 "@
1740 {sf.|subfc.} %3,%2,%1
1741 #"
1742 [(set_attr "type" "compare")
1743 (set_attr "length" "4,8")])
1745 (define_insn ""
1746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1747 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1748 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1749 (const_int 0)))
1750 (clobber (match_scratch:P 3 "=r,r"))]
1751 "TARGET_POWERPC"
1752 "@
1753 subf. %3,%2,%1
1754 #"
1755 [(set_attr "type" "fast_compare")
1756 (set_attr "length" "4,8")])
1758 (define_split
1759 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1760 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1761 (match_operand:P 2 "gpc_reg_operand" ""))
1762 (const_int 0)))
1763 (clobber (match_scratch:P 3 ""))]
1764 "reload_completed"
1765 [(set (match_dup 3)
1766 (minus:P (match_dup 1)
1767 (match_dup 2)))
1768 (set (match_dup 0)
1769 (compare:CC (match_dup 3)
1770 (const_int 0)))]
1771 "")
1773 (define_insn ""
1774 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1775 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1776 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1777 (const_int 0)))
1778 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1779 (minus:SI (match_dup 1) (match_dup 2)))]
1780 "! TARGET_POWERPC"
1781 "@
1782 {sf.|subfc.} %0,%2,%1
1783 #"
1784 [(set_attr "type" "compare")
1785 (set_attr "length" "4,8")])
1787 (define_insn ""
1788 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1789 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1790 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1791 (const_int 0)))
1792 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1793 (minus:P (match_dup 1)
1794 (match_dup 2)))]
1795 "TARGET_POWERPC"
1796 "@
1797 subf. %0,%2,%1
1798 #"
1799 [(set_attr "type" "fast_compare")
1800 (set_attr "length" "4,8")])
1802 (define_split
1803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1804 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1805 (match_operand:P 2 "gpc_reg_operand" ""))
1806 (const_int 0)))
1807 (set (match_operand:P 0 "gpc_reg_operand" "")
1808 (minus:P (match_dup 1)
1809 (match_dup 2)))]
1810 "reload_completed"
1811 [(set (match_dup 0)
1812 (minus:P (match_dup 1)
1813 (match_dup 2)))
1814 (set (match_dup 3)
1815 (compare:CC (match_dup 0)
1816 (const_int 0)))]
1817 "")
1819 (define_expand "sub<mode>3"
1820 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1821 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1822 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1823 ""
1824 "
1825 {
1826 if (GET_CODE (operands[2]) == CONST_INT)
1827 {
1828 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1829 negate_rtx (<MODE>mode, operands[2])));
1830 DONE;
1831 }
1832 }")
1834 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1835 ;; instruction and some auxiliary computations. Then we just have a single
1836 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1837 ;; combine.
1839 (define_expand "sminsi3"
1840 [(set (match_dup 3)
1841 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1842 (match_operand:SI 2 "reg_or_short_operand" ""))
1843 (const_int 0)
1844 (minus:SI (match_dup 2) (match_dup 1))))
1845 (set (match_operand:SI 0 "gpc_reg_operand" "")
1846 (minus:SI (match_dup 2) (match_dup 3)))]
1847 "TARGET_POWER || TARGET_ISEL"
1848 "
1849 {
1850 if (TARGET_ISEL)
1851 {
1852 operands[2] = force_reg (SImode, operands[2]);
1853 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1854 DONE;
1855 }
1857 operands[3] = gen_reg_rtx (SImode);
1858 }")
1860 (define_split
1861 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1862 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1863 (match_operand:SI 2 "reg_or_short_operand" "")))
1864 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1865 "TARGET_POWER"
1866 [(set (match_dup 3)
1867 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1868 (const_int 0)
1869 (minus:SI (match_dup 2) (match_dup 1))))
1870 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1871 "")
1873 (define_expand "smaxsi3"
1874 [(set (match_dup 3)
1875 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1876 (match_operand:SI 2 "reg_or_short_operand" ""))
1877 (const_int 0)
1878 (minus:SI (match_dup 2) (match_dup 1))))
1879 (set (match_operand:SI 0 "gpc_reg_operand" "")
1880 (plus:SI (match_dup 3) (match_dup 1)))]
1881 "TARGET_POWER || TARGET_ISEL"
1882 "
1883 {
1884 if (TARGET_ISEL)
1885 {
1886 operands[2] = force_reg (SImode, operands[2]);
1887 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1888 DONE;
1889 }
1890 operands[3] = gen_reg_rtx (SImode);
1891 }")
1893 (define_split
1894 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1895 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1896 (match_operand:SI 2 "reg_or_short_operand" "")))
1897 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1898 "TARGET_POWER"
1899 [(set (match_dup 3)
1900 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1901 (const_int 0)
1902 (minus:SI (match_dup 2) (match_dup 1))))
1903 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1904 "")
1906 (define_expand "uminsi3"
1907 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1908 (match_dup 5)))
1909 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1910 (match_dup 5)))
1911 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1912 (const_int 0)
1913 (minus:SI (match_dup 4) (match_dup 3))))
1914 (set (match_operand:SI 0 "gpc_reg_operand" "")
1915 (minus:SI (match_dup 2) (match_dup 3)))]
1916 "TARGET_POWER || TARGET_ISEL"
1917 "
1918 {
1919 if (TARGET_ISEL)
1920 {
1921 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1922 DONE;
1923 }
1924 operands[3] = gen_reg_rtx (SImode);
1925 operands[4] = gen_reg_rtx (SImode);
1926 operands[5] = GEN_INT (-2147483647 - 1);
1927 }")
1929 (define_expand "umaxsi3"
1930 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1931 (match_dup 5)))
1932 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1933 (match_dup 5)))
1934 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1935 (const_int 0)
1936 (minus:SI (match_dup 4) (match_dup 3))))
1937 (set (match_operand:SI 0 "gpc_reg_operand" "")
1938 (plus:SI (match_dup 3) (match_dup 1)))]
1939 "TARGET_POWER || TARGET_ISEL"
1940 "
1941 {
1942 if (TARGET_ISEL)
1943 {
1944 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1945 DONE;
1946 }
1947 operands[3] = gen_reg_rtx (SImode);
1948 operands[4] = gen_reg_rtx (SImode);
1949 operands[5] = GEN_INT (-2147483647 - 1);
1950 }")
1952 (define_insn ""
1953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1954 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1955 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1956 (const_int 0)
1957 (minus:SI (match_dup 2) (match_dup 1))))]
1958 "TARGET_POWER"
1959 "doz%I2 %0,%1,%2")
1961 (define_insn ""
1962 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1963 (compare:CC
1964 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1965 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1966 (const_int 0)
1967 (minus:SI (match_dup 2) (match_dup 1)))
1968 (const_int 0)))
1969 (clobber (match_scratch:SI 3 "=r,r"))]
1970 "TARGET_POWER"
1971 "@
1972 doz%I2. %3,%1,%2
1973 #"
1974 [(set_attr "type" "delayed_compare")
1975 (set_attr "length" "4,8")])
1977 (define_split
1978 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1979 (compare:CC
1980 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1981 (match_operand:SI 2 "reg_or_short_operand" ""))
1982 (const_int 0)
1983 (minus:SI (match_dup 2) (match_dup 1)))
1984 (const_int 0)))
1985 (clobber (match_scratch:SI 3 ""))]
1986 "TARGET_POWER && reload_completed"
1987 [(set (match_dup 3)
1988 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1989 (const_int 0)
1990 (minus:SI (match_dup 2) (match_dup 1))))
1991 (set (match_dup 0)
1992 (compare:CC (match_dup 3)
1993 (const_int 0)))]
1994 "")
1996 (define_insn ""
1997 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1998 (compare:CC
1999 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2000 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2001 (const_int 0)
2002 (minus:SI (match_dup 2) (match_dup 1)))
2003 (const_int 0)))
2004 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2005 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2006 (const_int 0)
2007 (minus:SI (match_dup 2) (match_dup 1))))]
2008 "TARGET_POWER"
2009 "@
2010 doz%I2. %0,%1,%2
2011 #"
2012 [(set_attr "type" "delayed_compare")
2013 (set_attr "length" "4,8")])
2015 (define_split
2016 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2017 (compare:CC
2018 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2019 (match_operand:SI 2 "reg_or_short_operand" ""))
2020 (const_int 0)
2021 (minus:SI (match_dup 2) (match_dup 1)))
2022 (const_int 0)))
2023 (set (match_operand:SI 0 "gpc_reg_operand" "")
2024 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2025 (const_int 0)
2026 (minus:SI (match_dup 2) (match_dup 1))))]
2027 "TARGET_POWER && reload_completed"
2028 [(set (match_dup 0)
2029 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2030 (const_int 0)
2031 (minus:SI (match_dup 2) (match_dup 1))))
2032 (set (match_dup 3)
2033 (compare:CC (match_dup 0)
2034 (const_int 0)))]
2035 "")
2037 ;; We don't need abs with condition code because such comparisons should
2038 ;; never be done.
2039 (define_expand "abssi2"
2040 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2041 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2042 ""
2043 "
2044 {
2045 if (TARGET_ISEL)
2046 {
2047 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2048 DONE;
2049 }
2050 else if (! TARGET_POWER)
2051 {
2052 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2053 DONE;
2054 }
2055 }")
2057 (define_insn "*abssi2_power"
2058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2059 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2060 "TARGET_POWER"
2061 "abs %0,%1")
2063 (define_insn_and_split "abssi2_isel"
2064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2065 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2066 (clobber (match_scratch:SI 2 "=&b"))
2067 (clobber (match_scratch:CC 3 "=y"))]
2068 "TARGET_ISEL"
2069 "#"
2070 "&& reload_completed"
2071 [(set (match_dup 2) (neg:SI (match_dup 1)))
2072 (set (match_dup 3)
2073 (compare:CC (match_dup 1)
2074 (const_int 0)))
2075 (set (match_dup 0)
2076 (if_then_else:SI (ge (match_dup 3)
2077 (const_int 0))
2078 (match_dup 1)
2079 (match_dup 2)))]
2080 "")
2082 (define_insn_and_split "abssi2_nopower"
2083 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2084 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2085 (clobber (match_scratch:SI 2 "=&r,&r"))]
2086 "! TARGET_POWER && ! TARGET_ISEL"
2087 "#"
2088 "&& reload_completed"
2089 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2090 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2091 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2092 "")
2094 (define_insn "*nabs_power"
2095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2096 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2097 "TARGET_POWER"
2098 "nabs %0,%1")
2100 (define_insn_and_split "*nabs_nopower"
2101 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2102 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2103 (clobber (match_scratch:SI 2 "=&r,&r"))]
2104 "! TARGET_POWER"
2105 "#"
2106 "&& reload_completed"
2107 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2108 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2109 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2110 "")
2112 (define_expand "neg<mode>2"
2113 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2114 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2115 ""
2116 "")
2118 (define_insn "*neg<mode>2_internal"
2119 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2120 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2121 ""
2122 "neg %0,%1")
2124 (define_insn ""
2125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2126 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2127 (const_int 0)))
2128 (clobber (match_scratch:P 2 "=r,r"))]
2129 ""
2130 "@
2131 neg. %2,%1
2132 #"
2133 [(set_attr "type" "fast_compare")
2134 (set_attr "length" "4,8")])
2136 (define_split
2137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2138 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2139 (const_int 0)))
2140 (clobber (match_scratch:P 2 ""))]
2141 "reload_completed"
2142 [(set (match_dup 2)
2143 (neg:P (match_dup 1)))
2144 (set (match_dup 0)
2145 (compare:CC (match_dup 2)
2146 (const_int 0)))]
2147 "")
2149 (define_insn ""
2150 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2151 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2152 (const_int 0)))
2153 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2154 (neg:P (match_dup 1)))]
2155 ""
2156 "@
2157 neg. %0,%1
2158 #"
2159 [(set_attr "type" "fast_compare")
2160 (set_attr "length" "4,8")])
2162 (define_split
2163 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2164 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2165 (const_int 0)))
2166 (set (match_operand:P 0 "gpc_reg_operand" "")
2167 (neg:P (match_dup 1)))]
2168 "reload_completed"
2169 [(set (match_dup 0)
2170 (neg:P (match_dup 1)))
2171 (set (match_dup 2)
2172 (compare:CC (match_dup 0)
2173 (const_int 0)))]
2174 "")
2176 (define_insn "clz<mode>2"
2177 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2178 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2179 ""
2180 "{cntlz|cntlz<wd>} %0,%1"
2181 [(set_attr "type" "cntlz")])
2183 (define_expand "ctz<mode>2"
2184 [(set (match_dup 2)
2185 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2186 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2187 (match_dup 2)))
2188 (clobber (scratch:CC))])
2189 (set (match_dup 4) (clz:GPR (match_dup 3)))
2190 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2191 (minus:GPR (match_dup 5) (match_dup 4)))]
2192 ""
2193 {
2194 operands[2] = gen_reg_rtx (<MODE>mode);
2195 operands[3] = gen_reg_rtx (<MODE>mode);
2196 operands[4] = gen_reg_rtx (<MODE>mode);
2197 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2198 })
2200 (define_expand "ffs<mode>2"
2201 [(set (match_dup 2)
2202 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2203 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2204 (match_dup 2)))
2205 (clobber (scratch:CC))])
2206 (set (match_dup 4) (clz:GPR (match_dup 3)))
2207 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2208 (minus:GPR (match_dup 5) (match_dup 4)))]
2209 ""
2210 {
2211 operands[2] = gen_reg_rtx (<MODE>mode);
2212 operands[3] = gen_reg_rtx (<MODE>mode);
2213 operands[4] = gen_reg_rtx (<MODE>mode);
2214 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2215 })
2217 (define_insn "popcntb<mode>2"
2218 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2219 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2220 UNSPEC_POPCNTB))]
2221 "TARGET_POPCNTB"
2222 "popcntb %0,%1")
2224 (define_expand "popcount<mode>2"
2225 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2226 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2227 "TARGET_POPCNTB"
2228 {
2229 rs6000_emit_popcount (operands[0], operands[1]);
2230 DONE;
2231 })
2233 (define_expand "parity<mode>2"
2234 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2235 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2236 "TARGET_POPCNTB"
2237 {
2238 rs6000_emit_parity (operands[0], operands[1]);
2239 DONE;
2240 })
2242 (define_insn "bswapsi2"
2243 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2244 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2245 ""
2246 "@
2247 {lbrx|lwbrx} %0,%y1
2248 {stbrx|stwbrx} %1,%y0
2249 #"
2250 [(set_attr "length" "4,4,12")])
2252 (define_split
2253 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2254 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2255 "reload_completed"
2256 [(set (match_dup 0)
2257 (rotate:SI (match_dup 1) (const_int 8)))
2258 (set (zero_extract:SI (match_dup 0)
2259 (const_int 8)
2260 (const_int 0))
2261 (match_dup 1))
2262 (set (zero_extract:SI (match_dup 0)
2263 (const_int 8)
2264 (const_int 16))
2265 (rotate:SI (match_dup 1)
2266 (const_int 16)))]
2267 "")
2269 (define_expand "mulsi3"
2270 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2271 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2272 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2273 ""
2274 "
2275 {
2276 if (TARGET_POWER)
2277 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2278 else
2279 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2280 DONE;
2281 }")
2283 (define_insn "mulsi3_mq"
2284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2285 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2286 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2287 (clobber (match_scratch:SI 3 "=q,q"))]
2288 "TARGET_POWER"
2289 "@
2290 {muls|mullw} %0,%1,%2
2291 {muli|mulli} %0,%1,%2"
2292 [(set (attr "type")
2293 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2294 (const_string "imul3")
2295 (match_operand:SI 2 "short_cint_operand" "")
2296 (const_string "imul2")]
2297 (const_string "imul")))])
2299 (define_insn "mulsi3_no_mq"
2300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2301 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2302 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2303 "! TARGET_POWER"
2304 "@
2305 {muls|mullw} %0,%1,%2
2306 {muli|mulli} %0,%1,%2"
2307 [(set (attr "type")
2308 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2309 (const_string "imul3")
2310 (match_operand:SI 2 "short_cint_operand" "")
2311 (const_string "imul2")]
2312 (const_string "imul")))])
2314 (define_insn "*mulsi3_mq_internal1"
2315 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2316 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2317 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2318 (const_int 0)))
2319 (clobber (match_scratch:SI 3 "=r,r"))
2320 (clobber (match_scratch:SI 4 "=q,q"))]
2321 "TARGET_POWER"
2322 "@
2323 {muls.|mullw.} %3,%1,%2
2324 #"
2325 [(set_attr "type" "imul_compare")
2326 (set_attr "length" "4,8")])
2328 (define_split
2329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2330 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2331 (match_operand:SI 2 "gpc_reg_operand" ""))
2332 (const_int 0)))
2333 (clobber (match_scratch:SI 3 ""))
2334 (clobber (match_scratch:SI 4 ""))]
2335 "TARGET_POWER && reload_completed"
2336 [(parallel [(set (match_dup 3)
2337 (mult:SI (match_dup 1) (match_dup 2)))
2338 (clobber (match_dup 4))])
2339 (set (match_dup 0)
2340 (compare:CC (match_dup 3)
2341 (const_int 0)))]
2342 "")
2344 (define_insn "*mulsi3_no_mq_internal1"
2345 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2346 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2347 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2348 (const_int 0)))
2349 (clobber (match_scratch:SI 3 "=r,r"))]
2350 "! TARGET_POWER"
2351 "@
2352 {muls.|mullw.} %3,%1,%2
2353 #"
2354 [(set_attr "type" "imul_compare")
2355 (set_attr "length" "4,8")])
2357 (define_split
2358 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2359 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2360 (match_operand:SI 2 "gpc_reg_operand" ""))
2361 (const_int 0)))
2362 (clobber (match_scratch:SI 3 ""))]
2363 "! TARGET_POWER && reload_completed"
2364 [(set (match_dup 3)
2365 (mult:SI (match_dup 1) (match_dup 2)))
2366 (set (match_dup 0)
2367 (compare:CC (match_dup 3)
2368 (const_int 0)))]
2369 "")
2371 (define_insn "*mulsi3_mq_internal2"
2372 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2373 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2374 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2375 (const_int 0)))
2376 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2377 (mult:SI (match_dup 1) (match_dup 2)))
2378 (clobber (match_scratch:SI 4 "=q,q"))]
2379 "TARGET_POWER"
2380 "@
2381 {muls.|mullw.} %0,%1,%2
2382 #"
2383 [(set_attr "type" "imul_compare")
2384 (set_attr "length" "4,8")])
2386 (define_split
2387 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2388 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2389 (match_operand:SI 2 "gpc_reg_operand" ""))
2390 (const_int 0)))
2391 (set (match_operand:SI 0 "gpc_reg_operand" "")
2392 (mult:SI (match_dup 1) (match_dup 2)))
2393 (clobber (match_scratch:SI 4 ""))]
2394 "TARGET_POWER && reload_completed"
2395 [(parallel [(set (match_dup 0)
2396 (mult:SI (match_dup 1) (match_dup 2)))
2397 (clobber (match_dup 4))])
2398 (set (match_dup 3)
2399 (compare:CC (match_dup 0)
2400 (const_int 0)))]
2401 "")
2403 (define_insn "*mulsi3_no_mq_internal2"
2404 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2405 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2406 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2407 (const_int 0)))
2408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2409 (mult:SI (match_dup 1) (match_dup 2)))]
2410 "! TARGET_POWER"
2411 "@
2412 {muls.|mullw.} %0,%1,%2
2413 #"
2414 [(set_attr "type" "imul_compare")
2415 (set_attr "length" "4,8")])
2417 (define_split
2418 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2419 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2420 (match_operand:SI 2 "gpc_reg_operand" ""))
2421 (const_int 0)))
2422 (set (match_operand:SI 0 "gpc_reg_operand" "")
2423 (mult:SI (match_dup 1) (match_dup 2)))]
2424 "! TARGET_POWER && reload_completed"
2425 [(set (match_dup 0)
2426 (mult:SI (match_dup 1) (match_dup 2)))
2427 (set (match_dup 3)
2428 (compare:CC (match_dup 0)
2429 (const_int 0)))]
2430 "")
2432 ;; Operand 1 is divided by operand 2; quotient goes to operand
2433 ;; 0 and remainder to operand 3.
2434 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2436 (define_expand "divmodsi4"
2437 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2438 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2439 (match_operand:SI 2 "gpc_reg_operand" "")))
2440 (set (match_operand:SI 3 "register_operand" "")
2441 (mod:SI (match_dup 1) (match_dup 2)))])]
2442 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2443 "
2444 {
2445 if (! TARGET_POWER && ! TARGET_POWERPC)
2446 {
2447 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2448 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2449 emit_insn (gen_divss_call ());
2450 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2451 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2452 DONE;
2453 }
2454 }")
2456 (define_insn "*divmodsi4_internal"
2457 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2458 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2459 (match_operand:SI 2 "gpc_reg_operand" "r")))
2460 (set (match_operand:SI 3 "register_operand" "=q")
2461 (mod:SI (match_dup 1) (match_dup 2)))]
2462 "TARGET_POWER"
2463 "divs %0,%1,%2"
2464 [(set_attr "type" "idiv")])
2466 (define_expand "udiv<mode>3"
2467 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2468 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2469 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2470 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2471 "
2472 {
2473 if (! TARGET_POWER && ! TARGET_POWERPC)
2474 {
2475 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2476 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2477 emit_insn (gen_quous_call ());
2478 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2479 DONE;
2480 }
2481 else if (TARGET_POWER)
2482 {
2483 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2484 DONE;
2485 }
2486 }")
2488 (define_insn "udivsi3_mq"
2489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2490 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2491 (match_operand:SI 2 "gpc_reg_operand" "r")))
2492 (clobber (match_scratch:SI 3 "=q"))]
2493 "TARGET_POWERPC && TARGET_POWER"
2494 "divwu %0,%1,%2"
2495 [(set_attr "type" "idiv")])
2497 (define_insn "*udivsi3_no_mq"
2498 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2499 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2500 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2501 "TARGET_POWERPC && ! TARGET_POWER"
2502 "div<wd>u %0,%1,%2"
2503 [(set (attr "type")
2504 (cond [(match_operand:SI 0 "" "")
2505 (const_string "idiv")]
2506 (const_string "ldiv")))])
2509 ;; For powers of two we can do srai/aze for divide and then adjust for
2510 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2511 ;; used; for PowerPC, force operands into register and do a normal divide;
2512 ;; for AIX common-mode, use quoss call on register operands.
2513 (define_expand "div<mode>3"
2514 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2515 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2516 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2517 ""
2518 "
2519 {
2520 if (GET_CODE (operands[2]) == CONST_INT
2521 && INTVAL (operands[2]) > 0
2522 && exact_log2 (INTVAL (operands[2])) >= 0)
2523 ;
2524 else if (TARGET_POWERPC)
2525 {
2526 operands[2] = force_reg (<MODE>mode, operands[2]);
2527 if (TARGET_POWER)
2528 {
2529 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2530 DONE;
2531 }
2532 }
2533 else if (TARGET_POWER)
2534 FAIL;
2535 else
2536 {
2537 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2538 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2539 emit_insn (gen_quoss_call ());
2540 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2541 DONE;
2542 }
2543 }")
2545 (define_insn "divsi3_mq"
2546 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2547 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2548 (match_operand:SI 2 "gpc_reg_operand" "r")))
2549 (clobber (match_scratch:SI 3 "=q"))]
2550 "TARGET_POWERPC && TARGET_POWER"
2551 "divw %0,%1,%2"
2552 [(set_attr "type" "idiv")])
2554 (define_insn "*div<mode>3_no_mq"
2555 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2556 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2557 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2558 "TARGET_POWERPC && ! TARGET_POWER"
2559 "div<wd> %0,%1,%2"
2560 [(set (attr "type")
2561 (cond [(match_operand:SI 0 "" "")
2562 (const_string "idiv")]
2563 (const_string "ldiv")))])
2565 (define_expand "mod<mode>3"
2566 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2567 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2568 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2569 ""
2570 "
2571 {
2572 int i;
2573 rtx temp1;
2574 rtx temp2;
2576 if (GET_CODE (operands[2]) != CONST_INT
2577 || INTVAL (operands[2]) <= 0
2578 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2579 FAIL;
2581 temp1 = gen_reg_rtx (<MODE>mode);
2582 temp2 = gen_reg_rtx (<MODE>mode);
2584 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2585 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2586 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2587 DONE;
2588 }")
2590 (define_insn ""
2591 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2592 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2593 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2594 ""
2595 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2596 [(set_attr "type" "two")
2597 (set_attr "length" "8")])
2599 (define_insn ""
2600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2601 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2602 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2603 (const_int 0)))
2604 (clobber (match_scratch:P 3 "=r,r"))]
2605 ""
2606 "@
2607 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2608 #"
2609 [(set_attr "type" "compare")
2610 (set_attr "length" "8,12")
2611 (set_attr "cell_micro" "not")])
2613 (define_split
2614 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2615 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2616 (match_operand:GPR 2 "exact_log2_cint_operand"
2617 ""))
2618 (const_int 0)))
2619 (clobber (match_scratch:GPR 3 ""))]
2620 "reload_completed"
2621 [(set (match_dup 3)
2622 (div:<MODE> (match_dup 1) (match_dup 2)))
2623 (set (match_dup 0)
2624 (compare:CC (match_dup 3)
2625 (const_int 0)))]
2626 "")
2628 (define_insn ""
2629 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2630 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2631 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2632 (const_int 0)))
2633 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2634 (div:P (match_dup 1) (match_dup 2)))]
2635 ""
2636 "@
2637 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2638 #"
2639 [(set_attr "type" "compare")
2640 (set_attr "length" "8,12")
2641 (set_attr "cell_micro" "not")])
2643 (define_split
2644 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2645 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2646 (match_operand:GPR 2 "exact_log2_cint_operand"
2647 ""))
2648 (const_int 0)))
2649 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2650 (div:GPR (match_dup 1) (match_dup 2)))]
2651 "reload_completed"
2652 [(set (match_dup 0)
2653 (div:<MODE> (match_dup 1) (match_dup 2)))
2654 (set (match_dup 3)
2655 (compare:CC (match_dup 0)
2656 (const_int 0)))]
2657 "")
2659 (define_insn ""
2660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2661 (udiv:SI
2662 (plus:DI (ashift:DI
2663 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2664 (const_int 32))
2665 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2666 (match_operand:SI 3 "gpc_reg_operand" "r")))
2667 (set (match_operand:SI 2 "register_operand" "=*q")
2668 (umod:SI
2669 (plus:DI (ashift:DI
2670 (zero_extend:DI (match_dup 1)) (const_int 32))
2671 (zero_extend:DI (match_dup 4)))
2672 (match_dup 3)))]
2673 "TARGET_POWER"
2674 "div %0,%1,%3"
2675 [(set_attr "type" "idiv")])
2677 ;; To do unsigned divide we handle the cases of the divisor looking like a
2678 ;; negative number. If it is a constant that is less than 2**31, we don't
2679 ;; have to worry about the branches. So make a few subroutines here.
2680 ;;
2681 ;; First comes the normal case.
2682 (define_expand "udivmodsi4_normal"
2683 [(set (match_dup 4) (const_int 0))
2684 (parallel [(set (match_operand:SI 0 "" "")
2685 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2686 (const_int 32))
2687 (zero_extend:DI (match_operand:SI 1 "" "")))
2688 (match_operand:SI 2 "" "")))
2689 (set (match_operand:SI 3 "" "")
2690 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2691 (const_int 32))
2692 (zero_extend:DI (match_dup 1)))
2693 (match_dup 2)))])]
2694 "TARGET_POWER"
2695 "
2696 { operands[4] = gen_reg_rtx (SImode); }")
2698 ;; This handles the branches.
2699 (define_expand "udivmodsi4_tests"
2700 [(set (match_operand:SI 0 "" "") (const_int 0))
2701 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2702 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2703 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2704 (label_ref (match_operand:SI 4 "" "")) (pc)))
2705 (set (match_dup 0) (const_int 1))
2706 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2707 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2708 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2709 (label_ref (match_dup 4)) (pc)))]
2710 "TARGET_POWER"
2711 "
2712 { operands[5] = gen_reg_rtx (CCUNSmode);
2713 operands[6] = gen_reg_rtx (CCmode);
2714 }")
2716 (define_expand "udivmodsi4"
2717 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2718 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2719 (match_operand:SI 2 "reg_or_cint_operand" "")))
2720 (set (match_operand:SI 3 "gpc_reg_operand" "")
2721 (umod:SI (match_dup 1) (match_dup 2)))])]
2722 ""
2723 "
2724 {
2725 rtx label = 0;
2727 if (! TARGET_POWER)
2728 {
2729 if (! TARGET_POWERPC)
2730 {
2731 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2732 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2733 emit_insn (gen_divus_call ());
2734 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2735 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2736 DONE;
2737 }
2738 else
2739 FAIL;
2740 }
2742 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2743 {
2744 operands[2] = force_reg (SImode, operands[2]);
2745 label = gen_label_rtx ();
2746 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2747 operands[3], label));
2748 }
2749 else
2750 operands[2] = force_reg (SImode, operands[2]);
2752 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2753 operands[3]));
2754 if (label)
2755 emit_label (label);
2757 DONE;
2758 }")
2760 ;; AIX architecture-independent common-mode multiply (DImode),
2761 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2762 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2763 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2764 ;; assumed unused if generating common-mode, so ignore.
2765 (define_insn "mulh_call"
2766 [(set (reg:SI 3)
2767 (truncate:SI
2768 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2769 (sign_extend:DI (reg:SI 4)))
2770 (const_int 32))))
2771 (clobber (reg:SI LR_REGNO))]
2772 "! TARGET_POWER && ! TARGET_POWERPC"
2773 "bla __mulh"
2774 [(set_attr "type" "imul")])
2776 (define_insn "mull_call"
2777 [(set (reg:DI 3)
2778 (mult:DI (sign_extend:DI (reg:SI 3))
2779 (sign_extend:DI (reg:SI 4))))
2780 (clobber (reg:SI LR_REGNO))
2781 (clobber (reg:SI 0))]
2782 "! TARGET_POWER && ! TARGET_POWERPC"
2783 "bla __mull"
2784 [(set_attr "type" "imul")])
2786 (define_insn "divss_call"
2787 [(set (reg:SI 3)
2788 (div:SI (reg:SI 3) (reg:SI 4)))
2789 (set (reg:SI 4)
2790 (mod:SI (reg:SI 3) (reg:SI 4)))
2791 (clobber (reg:SI LR_REGNO))
2792 (clobber (reg:SI 0))]
2793 "! TARGET_POWER && ! TARGET_POWERPC"
2794 "bla __divss"
2795 [(set_attr "type" "idiv")])
2797 (define_insn "divus_call"
2798 [(set (reg:SI 3)
2799 (udiv:SI (reg:SI 3) (reg:SI 4)))
2800 (set (reg:SI 4)
2801 (umod:SI (reg:SI 3) (reg:SI 4)))
2802 (clobber (reg:SI LR_REGNO))
2803 (clobber (reg:SI 0))
2804 (clobber (match_scratch:CC 0 "=x"))
2805 (clobber (reg:CC CR1_REGNO))]
2806 "! TARGET_POWER && ! TARGET_POWERPC"
2807 "bla __divus"
2808 [(set_attr "type" "idiv")])
2810 (define_insn "quoss_call"
2811 [(set (reg:SI 3)
2812 (div:SI (reg:SI 3) (reg:SI 4)))
2813 (clobber (reg:SI LR_REGNO))]
2814 "! TARGET_POWER && ! TARGET_POWERPC"
2815 "bla __quoss"
2816 [(set_attr "type" "idiv")])
2818 (define_insn "quous_call"
2819 [(set (reg:SI 3)
2820 (udiv:SI (reg:SI 3) (reg:SI 4)))
2821 (clobber (reg:SI LR_REGNO))
2822 (clobber (reg:SI 0))
2823 (clobber (match_scratch:CC 0 "=x"))
2824 (clobber (reg:CC CR1_REGNO))]
2825 "! TARGET_POWER && ! TARGET_POWERPC"
2826 "bla __quous"
2827 [(set_attr "type" "idiv")])
2828 \f
2829 ;; Logical instructions
2830 ;; The logical instructions are mostly combined by using match_operator,
2831 ;; but the plain AND insns are somewhat different because there is no
2832 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2833 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2835 (define_expand "andsi3"
2836 [(parallel
2837 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2838 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2839 (match_operand:SI 2 "and_operand" "")))
2840 (clobber (match_scratch:CC 3 ""))])]
2841 ""
2842 "")
2844 (define_insn "andsi3_mc"
2845 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2846 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2847 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2848 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2849 "rs6000_gen_cell_microcode"
2850 "@
2851 and %0,%1,%2
2852 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2853 {andil.|andi.} %0,%1,%b2
2854 {andiu.|andis.} %0,%1,%u2"
2855 [(set_attr "type" "*,*,compare,compare")])
2857 (define_insn "andsi3_nomc"
2858 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2859 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2860 (match_operand:SI 2 "and_operand" "?r,T")))
2861 (clobber (match_scratch:CC 3 "=X,X"))]
2862 "!rs6000_gen_cell_microcode"
2863 "@
2864 and %0,%1,%2
2865 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
2867 (define_insn "andsi3_internal0_nomc"
2868 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2869 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2870 (match_operand:SI 2 "and_operand" "?r,T")))]
2871 "!rs6000_gen_cell_microcode"
2872 "@
2873 and %0,%1,%2
2874 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
2877 ;; Note to set cr's other than cr0 we do the and immediate and then
2878 ;; the test again -- this avoids a mfcr which on the higher end
2879 ;; machines causes an execution serialization
2881 (define_insn "*andsi3_internal2_mc"
2882 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2883 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2884 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2885 (const_int 0)))
2886 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2887 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2888 "TARGET_32BIT && rs6000_gen_cell_microcode"
2889 "@
2890 and. %3,%1,%2
2891 {andil.|andi.} %3,%1,%b2
2892 {andiu.|andis.} %3,%1,%u2
2893 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2894 #
2895 #
2896 #
2897 #"
2898 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2899 (set_attr "length" "4,4,4,4,8,8,8,8")])
2901 (define_insn "*andsi3_internal3_mc"
2902 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2903 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2904 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2905 (const_int 0)))
2906 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2907 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2908 "TARGET_64BIT && rs6000_gen_cell_microcode"
2909 "@
2910 #
2911 {andil.|andi.} %3,%1,%b2
2912 {andiu.|andis.} %3,%1,%u2
2913 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2914 #
2915 #
2916 #
2917 #"
2918 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2919 (set_attr "length" "8,4,4,4,8,8,8,8")])
2921 (define_split
2922 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2923 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2924 (match_operand:GPR 2 "and_operand" ""))
2925 (const_int 0)))
2926 (clobber (match_scratch:GPR 3 ""))
2927 (clobber (match_scratch:CC 4 ""))]
2928 "reload_completed"
2929 [(parallel [(set (match_dup 3)
2930 (and:<MODE> (match_dup 1)
2931 (match_dup 2)))
2932 (clobber (match_dup 4))])
2933 (set (match_dup 0)
2934 (compare:CC (match_dup 3)
2935 (const_int 0)))]
2936 "")
2938 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2939 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2941 (define_split
2942 [(set (match_operand:CC 0 "cc_reg_operand" "")
2943 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2944 (match_operand:SI 2 "gpc_reg_operand" ""))
2945 (const_int 0)))
2946 (clobber (match_scratch:SI 3 ""))
2947 (clobber (match_scratch:CC 4 ""))]
2948 "TARGET_POWERPC64 && reload_completed"
2949 [(parallel [(set (match_dup 3)
2950 (and:SI (match_dup 1)
2951 (match_dup 2)))
2952 (clobber (match_dup 4))])
2953 (set (match_dup 0)
2954 (compare:CC (match_dup 3)
2955 (const_int 0)))]
2956 "")
2958 (define_insn "*andsi3_internal4"
2959 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2960 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2961 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2962 (const_int 0)))
2963 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2964 (and:SI (match_dup 1)
2965 (match_dup 2)))
2966 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2967 "TARGET_32BIT && rs6000_gen_cell_microcode"
2968 "@
2969 and. %0,%1,%2
2970 {andil.|andi.} %0,%1,%b2
2971 {andiu.|andis.} %0,%1,%u2
2972 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2973 #
2974 #
2975 #
2976 #"
2977 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2978 (set_attr "length" "4,4,4,4,8,8,8,8")])
2980 (define_insn "*andsi3_internal5_mc"
2981 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2982 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2983 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2984 (const_int 0)))
2985 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2986 (and:SI (match_dup 1)
2987 (match_dup 2)))
2988 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2989 "TARGET_64BIT && rs6000_gen_cell_microcode"
2990 "@
2991 #
2992 {andil.|andi.} %0,%1,%b2
2993 {andiu.|andis.} %0,%1,%u2
2994 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2995 #
2996 #
2997 #
2998 #"
2999 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
3000 (set_attr "length" "8,4,4,4,8,8,8,8")])
3002 (define_insn "*andsi3_internal5_nomc"
3003 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y,??y,??y,?y")
3004 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
3005 (match_operand:SI 2 "and_operand" "r,r,K,L,T"))
3006 (const_int 0)))
3007 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
3008 (and:SI (match_dup 1)
3009 (match_dup 2)))
3010 (clobber (match_scratch:CC 4 "=X,X,x,x,X"))]
3011 "TARGET_64BIT && !rs6000_gen_cell_microcode"
3012 "#"
3013 [(set_attr "type" "compare")
3014 (set_attr "length" "8,8,8,8,8")])
3016 (define_split
3017 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3018 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3019 (match_operand:SI 2 "and_operand" ""))
3020 (const_int 0)))
3021 (set (match_operand:SI 0 "gpc_reg_operand" "")
3022 (and:SI (match_dup 1)
3023 (match_dup 2)))
3024 (clobber (match_scratch:CC 4 ""))]
3025 "reload_completed"
3026 [(parallel [(set (match_dup 0)
3027 (and:SI (match_dup 1)
3028 (match_dup 2)))
3029 (clobber (match_dup 4))])
3030 (set (match_dup 3)
3031 (compare:CC (match_dup 0)
3032 (const_int 0)))]
3033 "")
3035 (define_split
3036 [(set (match_operand:CC 3 "cc_reg_operand" "")
3037 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3038 (match_operand:SI 2 "gpc_reg_operand" ""))
3039 (const_int 0)))
3040 (set (match_operand:SI 0 "gpc_reg_operand" "")
3041 (and:SI (match_dup 1)
3042 (match_dup 2)))
3043 (clobber (match_scratch:CC 4 ""))]
3044 "TARGET_POWERPC64 && reload_completed"
3045 [(parallel [(set (match_dup 0)
3046 (and:SI (match_dup 1)
3047 (match_dup 2)))
3048 (clobber (match_dup 4))])
3049 (set (match_dup 3)
3050 (compare:CC (match_dup 0)
3051 (const_int 0)))]
3052 "")
3054 ;; Handle the PowerPC64 rlwinm corner case
3056 (define_insn_and_split "*andsi3_internal6"
3057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3058 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3059 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3060 "TARGET_POWERPC64"
3061 "#"
3062 "TARGET_POWERPC64"
3063 [(set (match_dup 0)
3064 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3065 (match_dup 4)))
3066 (set (match_dup 0)
3067 (rotate:SI (match_dup 0) (match_dup 5)))]
3068 "
3069 {
3070 int mb = extract_MB (operands[2]);
3071 int me = extract_ME (operands[2]);
3072 operands[3] = GEN_INT (me + 1);
3073 operands[5] = GEN_INT (32 - (me + 1));
3074 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3075 }"
3076 [(set_attr "length" "8")])
3078 (define_expand "iorsi3"
3079 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3080 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3081 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3082 ""
3083 "
3084 {
3085 if (GET_CODE (operands[2]) == CONST_INT
3086 && ! logical_operand (operands[2], SImode))
3087 {
3088 HOST_WIDE_INT value = INTVAL (operands[2]);
3089 rtx tmp = ((!can_create_pseudo_p ()
3090 || rtx_equal_p (operands[0], operands[1]))
3091 ? operands[0] : gen_reg_rtx (SImode));
3093 emit_insn (gen_iorsi3 (tmp, operands[1],
3094 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3095 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3096 DONE;
3097 }
3098 }")
3100 (define_expand "xorsi3"
3101 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3102 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3103 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3104 ""
3105 "
3106 {
3107 if (GET_CODE (operands[2]) == CONST_INT
3108 && ! logical_operand (operands[2], SImode))
3109 {
3110 HOST_WIDE_INT value = INTVAL (operands[2]);
3111 rtx tmp = ((!can_create_pseudo_p ()
3112 || rtx_equal_p (operands[0], operands[1]))
3113 ? operands[0] : gen_reg_rtx (SImode));
3115 emit_insn (gen_xorsi3 (tmp, operands[1],
3116 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3117 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3118 DONE;
3119 }
3120 }")
3122 (define_insn "*boolsi3_internal1"
3123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3124 (match_operator:SI 3 "boolean_or_operator"
3125 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3126 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3127 ""
3128 "@
3129 %q3 %0,%1,%2
3130 {%q3il|%q3i} %0,%1,%b2
3131 {%q3iu|%q3is} %0,%1,%u2")
3133 (define_insn "*boolsi3_internal2"
3134 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3135 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3136 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3137 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3138 (const_int 0)))
3139 (clobber (match_scratch:SI 3 "=r,r"))]
3140 "TARGET_32BIT"
3141 "@
3142 %q4. %3,%1,%2
3143 #"
3144 [(set_attr "type" "compare")
3145 (set_attr "length" "4,8")])
3147 (define_split
3148 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3149 (compare:CC (match_operator:SI 4 "boolean_operator"
3150 [(match_operand:SI 1 "gpc_reg_operand" "")
3151 (match_operand:SI 2 "gpc_reg_operand" "")])
3152 (const_int 0)))
3153 (clobber (match_scratch:SI 3 ""))]
3154 "TARGET_32BIT && reload_completed"
3155 [(set (match_dup 3) (match_dup 4))
3156 (set (match_dup 0)
3157 (compare:CC (match_dup 3)
3158 (const_int 0)))]
3159 "")
3161 (define_insn "*boolsi3_internal3"
3162 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3163 (compare:CC (match_operator:SI 4 "boolean_operator"
3164 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3165 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3166 (const_int 0)))
3167 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3168 (match_dup 4))]
3169 "TARGET_32BIT"
3170 "@
3171 %q4. %0,%1,%2
3172 #"
3173 [(set_attr "type" "compare")
3174 (set_attr "length" "4,8")])
3176 (define_split
3177 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3178 (compare:CC (match_operator:SI 4 "boolean_operator"
3179 [(match_operand:SI 1 "gpc_reg_operand" "")
3180 (match_operand:SI 2 "gpc_reg_operand" "")])
3181 (const_int 0)))
3182 (set (match_operand:SI 0 "gpc_reg_operand" "")
3183 (match_dup 4))]
3184 "TARGET_32BIT && reload_completed"
3185 [(set (match_dup 0) (match_dup 4))
3186 (set (match_dup 3)
3187 (compare:CC (match_dup 0)
3188 (const_int 0)))]
3189 "")
3191 ;; Split a logical operation that we can't do in one insn into two insns,
3192 ;; each of which does one 16-bit part. This is used by combine.
3194 (define_split
3195 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3196 (match_operator:SI 3 "boolean_or_operator"
3197 [(match_operand:SI 1 "gpc_reg_operand" "")
3198 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3199 ""
3200 [(set (match_dup 0) (match_dup 4))
3201 (set (match_dup 0) (match_dup 5))]
3202 "
3203 {
3204 rtx i;
3205 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3206 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3207 operands[1], i);
3208 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3209 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3210 operands[0], i);
3211 }")
3213 (define_insn "*boolcsi3_internal1"
3214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3215 (match_operator:SI 3 "boolean_operator"
3216 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3217 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3218 ""
3219 "%q3 %0,%2,%1")
3221 (define_insn "*boolcsi3_internal2"
3222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3223 (compare:CC (match_operator:SI 4 "boolean_operator"
3224 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3225 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3226 (const_int 0)))
3227 (clobber (match_scratch:SI 3 "=r,r"))]
3228 "TARGET_32BIT"
3229 "@
3230 %q4. %3,%2,%1
3231 #"
3232 [(set_attr "type" "compare")
3233 (set_attr "length" "4,8")])
3235 (define_split
3236 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3237 (compare:CC (match_operator:SI 4 "boolean_operator"
3238 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3239 (match_operand:SI 2 "gpc_reg_operand" "")])
3240 (const_int 0)))
3241 (clobber (match_scratch:SI 3 ""))]
3242 "TARGET_32BIT && reload_completed"
3243 [(set (match_dup 3) (match_dup 4))
3244 (set (match_dup 0)
3245 (compare:CC (match_dup 3)
3246 (const_int 0)))]
3247 "")
3249 (define_insn "*boolcsi3_internal3"
3250 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3251 (compare:CC (match_operator:SI 4 "boolean_operator"
3252 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3253 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3254 (const_int 0)))
3255 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3256 (match_dup 4))]
3257 "TARGET_32BIT"
3258 "@
3259 %q4. %0,%2,%1
3260 #"
3261 [(set_attr "type" "compare")
3262 (set_attr "length" "4,8")])
3264 (define_split
3265 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3266 (compare:CC (match_operator:SI 4 "boolean_operator"
3267 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3268 (match_operand:SI 2 "gpc_reg_operand" "")])
3269 (const_int 0)))
3270 (set (match_operand:SI 0 "gpc_reg_operand" "")
3271 (match_dup 4))]
3272 "TARGET_32BIT && reload_completed"
3273 [(set (match_dup 0) (match_dup 4))
3274 (set (match_dup 3)
3275 (compare:CC (match_dup 0)
3276 (const_int 0)))]
3277 "")
3279 (define_insn "*boolccsi3_internal1"
3280 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3281 (match_operator:SI 3 "boolean_operator"
3282 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3283 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3284 ""
3285 "%q3 %0,%1,%2")
3287 (define_insn "*boolccsi3_internal2"
3288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3289 (compare:CC (match_operator:SI 4 "boolean_operator"
3290 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3291 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3292 (const_int 0)))
3293 (clobber (match_scratch:SI 3 "=r,r"))]
3294 "TARGET_32BIT"
3295 "@
3296 %q4. %3,%1,%2
3297 #"
3298 [(set_attr "type" "compare")
3299 (set_attr "length" "4,8")])
3301 (define_split
3302 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3303 (compare:CC (match_operator:SI 4 "boolean_operator"
3304 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3305 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3306 (const_int 0)))
3307 (clobber (match_scratch:SI 3 ""))]
3308 "TARGET_32BIT && reload_completed"
3309 [(set (match_dup 3) (match_dup 4))
3310 (set (match_dup 0)
3311 (compare:CC (match_dup 3)
3312 (const_int 0)))]
3313 "")
3315 (define_insn "*boolccsi3_internal3"
3316 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3317 (compare:CC (match_operator:SI 4 "boolean_operator"
3318 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3319 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3320 (const_int 0)))
3321 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3322 (match_dup 4))]
3323 "TARGET_32BIT"
3324 "@
3325 %q4. %0,%1,%2
3326 #"
3327 [(set_attr "type" "compare")
3328 (set_attr "length" "4,8")])
3330 (define_split
3331 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3332 (compare:CC (match_operator:SI 4 "boolean_operator"
3333 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3334 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3335 (const_int 0)))
3336 (set (match_operand:SI 0 "gpc_reg_operand" "")
3337 (match_dup 4))]
3338 "TARGET_32BIT && reload_completed"
3339 [(set (match_dup 0) (match_dup 4))
3340 (set (match_dup 3)
3341 (compare:CC (match_dup 0)
3342 (const_int 0)))]
3343 "")
3345 ;; maskir insn. We need four forms because things might be in arbitrary
3346 ;; orders. Don't define forms that only set CR fields because these
3347 ;; would modify an input register.
3349 (define_insn "*maskir_internal1"
3350 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3351 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3352 (match_operand:SI 1 "gpc_reg_operand" "0"))
3353 (and:SI (match_dup 2)
3354 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3355 "TARGET_POWER"
3356 "maskir %0,%3,%2")
3358 (define_insn "*maskir_internal2"
3359 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3360 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3361 (match_operand:SI 1 "gpc_reg_operand" "0"))
3362 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3363 (match_dup 2))))]
3364 "TARGET_POWER"
3365 "maskir %0,%3,%2")
3367 (define_insn "*maskir_internal3"
3368 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3369 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3370 (match_operand:SI 3 "gpc_reg_operand" "r"))
3371 (and:SI (not:SI (match_dup 2))
3372 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3373 "TARGET_POWER"
3374 "maskir %0,%3,%2")
3376 (define_insn "*maskir_internal4"
3377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3378 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3379 (match_operand:SI 2 "gpc_reg_operand" "r"))
3380 (and:SI (not:SI (match_dup 2))
3381 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3382 "TARGET_POWER"
3383 "maskir %0,%3,%2")
3385 (define_insn "*maskir_internal5"
3386 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3387 (compare:CC
3388 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3389 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3390 (and:SI (match_dup 2)
3391 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3392 (const_int 0)))
3393 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3394 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3395 (and:SI (match_dup 2) (match_dup 3))))]
3396 "TARGET_POWER"
3397 "@
3398 maskir. %0,%3,%2
3399 #"
3400 [(set_attr "type" "compare")
3401 (set_attr "length" "4,8")])
3403 (define_split
3404 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3405 (compare:CC
3406 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3407 (match_operand:SI 1 "gpc_reg_operand" ""))
3408 (and:SI (match_dup 2)
3409 (match_operand:SI 3 "gpc_reg_operand" "")))
3410 (const_int 0)))
3411 (set (match_operand:SI 0 "gpc_reg_operand" "")
3412 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3413 (and:SI (match_dup 2) (match_dup 3))))]
3414 "TARGET_POWER && reload_completed"
3415 [(set (match_dup 0)
3416 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3417 (and:SI (match_dup 2) (match_dup 3))))
3418 (set (match_dup 4)
3419 (compare:CC (match_dup 0)
3420 (const_int 0)))]
3421 "")
3423 (define_insn "*maskir_internal6"
3424 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3425 (compare:CC
3426 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3427 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3428 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3429 (match_dup 2)))
3430 (const_int 0)))
3431 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3432 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3433 (and:SI (match_dup 3) (match_dup 2))))]
3434 "TARGET_POWER"
3435 "@
3436 maskir. %0,%3,%2
3437 #"
3438 [(set_attr "type" "compare")
3439 (set_attr "length" "4,8")])
3441 (define_split
3442 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3443 (compare:CC
3444 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3445 (match_operand:SI 1 "gpc_reg_operand" ""))
3446 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3447 (match_dup 2)))
3448 (const_int 0)))
3449 (set (match_operand:SI 0 "gpc_reg_operand" "")
3450 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3451 (and:SI (match_dup 3) (match_dup 2))))]
3452 "TARGET_POWER && reload_completed"
3453 [(set (match_dup 0)
3454 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3455 (and:SI (match_dup 3) (match_dup 2))))
3456 (set (match_dup 4)
3457 (compare:CC (match_dup 0)
3458 (const_int 0)))]
3459 "")
3461 (define_insn "*maskir_internal7"
3462 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3463 (compare:CC
3464 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3465 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3466 (and:SI (not:SI (match_dup 2))
3467 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3468 (const_int 0)))
3469 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3470 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3471 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3472 "TARGET_POWER"
3473 "@
3474 maskir. %0,%3,%2
3475 #"
3476 [(set_attr "type" "compare")
3477 (set_attr "length" "4,8")])
3479 (define_split
3480 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3481 (compare:CC
3482 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3483 (match_operand:SI 3 "gpc_reg_operand" ""))
3484 (and:SI (not:SI (match_dup 2))
3485 (match_operand:SI 1 "gpc_reg_operand" "")))
3486 (const_int 0)))
3487 (set (match_operand:SI 0 "gpc_reg_operand" "")
3488 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3489 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3490 "TARGET_POWER && reload_completed"
3491 [(set (match_dup 0)
3492 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3493 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3494 (set (match_dup 4)
3495 (compare:CC (match_dup 0)
3496 (const_int 0)))]
3497 "")
3499 (define_insn "*maskir_internal8"
3500 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3501 (compare:CC
3502 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3503 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3504 (and:SI (not:SI (match_dup 2))
3505 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3506 (const_int 0)))
3507 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3508 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3509 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3510 "TARGET_POWER"
3511 "@
3512 maskir. %0,%3,%2
3513 #"
3514 [(set_attr "type" "compare")
3515 (set_attr "length" "4,8")])
3517 (define_split
3518 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3519 (compare:CC
3520 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3521 (match_operand:SI 2 "gpc_reg_operand" ""))
3522 (and:SI (not:SI (match_dup 2))
3523 (match_operand:SI 1 "gpc_reg_operand" "")))
3524 (const_int 0)))
3525 (set (match_operand:SI 0 "gpc_reg_operand" "")
3526 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3527 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3528 "TARGET_POWER && reload_completed"
3529 [(set (match_dup 0)
3530 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3531 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3532 (set (match_dup 4)
3533 (compare:CC (match_dup 0)
3534 (const_int 0)))]
3535 "")
3536 \f
3537 ;; Rotate and shift insns, in all their variants. These support shifts,
3538 ;; field inserts and extracts, and various combinations thereof.
3539 (define_expand "insv"
3540 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3541 (match_operand:SI 1 "const_int_operand" "")
3542 (match_operand:SI 2 "const_int_operand" ""))
3543 (match_operand 3 "gpc_reg_operand" ""))]
3544 ""
3545 "
3546 {
3547 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3548 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3549 compiler if the address of the structure is taken later. Likewise, do
3550 not handle invalid E500 subregs. */
3551 if (GET_CODE (operands[0]) == SUBREG
3552 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3553 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3554 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3555 FAIL;
3557 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3558 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3559 else
3560 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3561 DONE;
3562 }")
3564 (define_insn "insvsi"
3565 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3566 (match_operand:SI 1 "const_int_operand" "i")
3567 (match_operand:SI 2 "const_int_operand" "i"))
3568 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3569 ""
3570 "*
3571 {
3572 int start = INTVAL (operands[2]) & 31;
3573 int size = INTVAL (operands[1]) & 31;
3575 operands[4] = GEN_INT (32 - start - size);
3576 operands[1] = GEN_INT (start + size - 1);
3577 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3578 }"
3579 [(set_attr "type" "insert_word")])
3581 (define_insn "*insvsi_internal1"
3582 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3583 (match_operand:SI 1 "const_int_operand" "i")
3584 (match_operand:SI 2 "const_int_operand" "i"))
3585 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3586 (match_operand:SI 4 "const_int_operand" "i")))]
3587 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3588 "*
3589 {
3590 int shift = INTVAL (operands[4]) & 31;
3591 int start = INTVAL (operands[2]) & 31;
3592 int size = INTVAL (operands[1]) & 31;
3594 operands[4] = GEN_INT (shift - start - size);
3595 operands[1] = GEN_INT (start + size - 1);
3596 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3597 }"
3598 [(set_attr "type" "insert_word")])
3600 (define_insn "*insvsi_internal2"
3601 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3602 (match_operand:SI 1 "const_int_operand" "i")
3603 (match_operand:SI 2 "const_int_operand" "i"))
3604 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3605 (match_operand:SI 4 "const_int_operand" "i")))]
3606 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3607 "*
3608 {
3609 int shift = INTVAL (operands[4]) & 31;
3610 int start = INTVAL (operands[2]) & 31;
3611 int size = INTVAL (operands[1]) & 31;
3613 operands[4] = GEN_INT (32 - shift - start - size);
3614 operands[1] = GEN_INT (start + size - 1);
3615 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3616 }"
3617 [(set_attr "type" "insert_word")])
3619 (define_insn "*insvsi_internal3"
3620 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3621 (match_operand:SI 1 "const_int_operand" "i")
3622 (match_operand:SI 2 "const_int_operand" "i"))
3623 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3624 (match_operand:SI 4 "const_int_operand" "i")))]
3625 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3626 "*
3627 {
3628 int shift = INTVAL (operands[4]) & 31;
3629 int start = INTVAL (operands[2]) & 31;
3630 int size = INTVAL (operands[1]) & 31;
3632 operands[4] = GEN_INT (32 - shift - start - size);
3633 operands[1] = GEN_INT (start + size - 1);
3634 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3635 }"
3636 [(set_attr "type" "insert_word")])
3638 (define_insn "*insvsi_internal4"
3639 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3640 (match_operand:SI 1 "const_int_operand" "i")
3641 (match_operand:SI 2 "const_int_operand" "i"))
3642 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3643 (match_operand:SI 4 "const_int_operand" "i")
3644 (match_operand:SI 5 "const_int_operand" "i")))]
3645 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3646 "*
3647 {
3648 int extract_start = INTVAL (operands[5]) & 31;
3649 int extract_size = INTVAL (operands[4]) & 31;
3650 int insert_start = INTVAL (operands[2]) & 31;
3651 int insert_size = INTVAL (operands[1]) & 31;
3653 /* Align extract field with insert field */
3654 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3655 operands[1] = GEN_INT (insert_start + insert_size - 1);
3656 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3657 }"
3658 [(set_attr "type" "insert_word")])
3660 ;; combine patterns for rlwimi
3661 (define_insn "*insvsi_internal5"
3662 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3663 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3664 (match_operand:SI 1 "mask_operand" "i"))
3665 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3666 (match_operand:SI 2 "const_int_operand" "i"))
3667 (match_operand:SI 5 "mask_operand" "i"))))]
3668 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3669 "*
3670 {
3671 int me = extract_ME(operands[5]);
3672 int mb = extract_MB(operands[5]);
3673 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3674 operands[2] = GEN_INT(mb);
3675 operands[1] = GEN_INT(me);
3676 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3677 }"
3678 [(set_attr "type" "insert_word")])
3680 (define_insn "*insvsi_internal6"
3681 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3682 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3683 (match_operand:SI 2 "const_int_operand" "i"))
3684 (match_operand:SI 5 "mask_operand" "i"))
3685 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3686 (match_operand:SI 1 "mask_operand" "i"))))]
3687 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3688 "*
3689 {
3690 int me = extract_ME(operands[5]);
3691 int mb = extract_MB(operands[5]);
3692 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3693 operands[2] = GEN_INT(mb);
3694 operands[1] = GEN_INT(me);
3695 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3696 }"
3697 [(set_attr "type" "insert_word")])
3699 (define_insn "insvdi"
3700 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3701 (match_operand:SI 1 "const_int_operand" "i")
3702 (match_operand:SI 2 "const_int_operand" "i"))
3703 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3704 "TARGET_POWERPC64"
3705 "*
3706 {
3707 int start = INTVAL (operands[2]) & 63;
3708 int size = INTVAL (operands[1]) & 63;
3710 operands[1] = GEN_INT (64 - start - size);
3711 return \"rldimi %0,%3,%H1,%H2\";
3712 }"
3713 [(set_attr "type" "insert_dword")])
3715 (define_insn "*insvdi_internal2"
3716 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3717 (match_operand:SI 1 "const_int_operand" "i")
3718 (match_operand:SI 2 "const_int_operand" "i"))
3719 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3720 (match_operand:SI 4 "const_int_operand" "i")))]
3721 "TARGET_POWERPC64
3722 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3723 "*
3724 {
3725 int shift = INTVAL (operands[4]) & 63;
3726 int start = (INTVAL (operands[2]) & 63) - 32;
3727 int size = INTVAL (operands[1]) & 63;
3729 operands[4] = GEN_INT (64 - shift - start - size);
3730 operands[2] = GEN_INT (start);
3731 operands[1] = GEN_INT (start + size - 1);
3732 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3733 }")
3735 (define_insn "*insvdi_internal3"
3736 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3737 (match_operand:SI 1 "const_int_operand" "i")
3738 (match_operand:SI 2 "const_int_operand" "i"))
3739 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3740 (match_operand:SI 4 "const_int_operand" "i")))]
3741 "TARGET_POWERPC64
3742 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3743 "*
3744 {
3745 int shift = INTVAL (operands[4]) & 63;
3746 int start = (INTVAL (operands[2]) & 63) - 32;
3747 int size = INTVAL (operands[1]) & 63;
3749 operands[4] = GEN_INT (64 - shift - start - size);
3750 operands[2] = GEN_INT (start);
3751 operands[1] = GEN_INT (start + size - 1);
3752 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3753 }")
3755 (define_expand "extzv"
3756 [(set (match_operand 0 "gpc_reg_operand" "")
3757 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3758 (match_operand:SI 2 "const_int_operand" "")
3759 (match_operand:SI 3 "const_int_operand" "")))]
3760 ""
3761 "
3762 {
3763 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3764 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3765 compiler if the address of the structure is taken later. */
3766 if (GET_CODE (operands[0]) == SUBREG
3767 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3768 FAIL;
3770 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3771 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3772 else
3773 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3774 DONE;
3775 }")
3777 (define_insn "extzvsi"
3778 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3779 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3780 (match_operand:SI 2 "const_int_operand" "i")
3781 (match_operand:SI 3 "const_int_operand" "i")))]
3782 ""
3783 "*
3784 {
3785 int start = INTVAL (operands[3]) & 31;
3786 int size = INTVAL (operands[2]) & 31;
3788 if (start + size >= 32)
3789 operands[3] = const0_rtx;
3790 else
3791 operands[3] = GEN_INT (start + size);
3792 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3793 }")
3795 (define_insn "*extzvsi_internal1"
3796 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3797 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3798 (match_operand:SI 2 "const_int_operand" "i,i")
3799 (match_operand:SI 3 "const_int_operand" "i,i"))
3800 (const_int 0)))
3801 (clobber (match_scratch:SI 4 "=r,r"))]
3802 ""
3803 "*
3804 {
3805 int start = INTVAL (operands[3]) & 31;
3806 int size = INTVAL (operands[2]) & 31;
3808 /* Force split for non-cc0 compare. */
3809 if (which_alternative == 1)
3810 return \"#\";
3812 /* If the bit-field being tested fits in the upper or lower half of a
3813 word, it is possible to use andiu. or andil. to test it. This is
3814 useful because the condition register set-use delay is smaller for
3815 andi[ul]. than for rlinm. This doesn't work when the starting bit
3816 position is 0 because the LT and GT bits may be set wrong. */
3818 if ((start > 0 && start + size <= 16) || start >= 16)
3819 {
3820 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3821 - (1 << (16 - (start & 15) - size))));
3822 if (start < 16)
3823 return \"{andiu.|andis.} %4,%1,%3\";
3824 else
3825 return \"{andil.|andi.} %4,%1,%3\";
3826 }
3828 if (start + size >= 32)
3829 operands[3] = const0_rtx;
3830 else
3831 operands[3] = GEN_INT (start + size);
3832 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3833 }"
3834 [(set_attr "type" "delayed_compare")
3835 (set_attr "length" "4,8")])
3837 (define_split
3838 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3839 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3840 (match_operand:SI 2 "const_int_operand" "")
3841 (match_operand:SI 3 "const_int_operand" ""))
3842 (const_int 0)))
3843 (clobber (match_scratch:SI 4 ""))]
3844 "reload_completed"
3845 [(set (match_dup 4)
3846 (zero_extract:SI (match_dup 1) (match_dup 2)
3847 (match_dup 3)))
3848 (set (match_dup 0)
3849 (compare:CC (match_dup 4)
3850 (const_int 0)))]
3851 "")
3853 (define_insn "*extzvsi_internal2"
3854 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3855 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3856 (match_operand:SI 2 "const_int_operand" "i,i")
3857 (match_operand:SI 3 "const_int_operand" "i,i"))
3858 (const_int 0)))
3859 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3860 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3861 ""
3862 "*
3863 {
3864 int start = INTVAL (operands[3]) & 31;
3865 int size = INTVAL (operands[2]) & 31;
3867 /* Force split for non-cc0 compare. */
3868 if (which_alternative == 1)
3869 return \"#\";
3871 /* Since we are using the output value, we can't ignore any need for
3872 a shift. The bit-field must end at the LSB. */
3873 if (start >= 16 && start + size == 32)
3874 {
3875 operands[3] = GEN_INT ((1 << size) - 1);
3876 return \"{andil.|andi.} %0,%1,%3\";
3877 }
3879 if (start + size >= 32)
3880 operands[3] = const0_rtx;
3881 else
3882 operands[3] = GEN_INT (start + size);
3883 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3884 }"
3885 [(set_attr "type" "delayed_compare")
3886 (set_attr "length" "4,8")])
3888 (define_split
3889 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3890 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3891 (match_operand:SI 2 "const_int_operand" "")
3892 (match_operand:SI 3 "const_int_operand" ""))
3893 (const_int 0)))
3894 (set (match_operand:SI 0 "gpc_reg_operand" "")
3895 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3896 "reload_completed"
3897 [(set (match_dup 0)
3898 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3899 (set (match_dup 4)
3900 (compare:CC (match_dup 0)
3901 (const_int 0)))]
3902 "")
3904 (define_insn "extzvdi"
3905 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3906 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3907 (match_operand:SI 2 "const_int_operand" "i")
3908 (match_operand:SI 3 "const_int_operand" "i")))]
3909 "TARGET_POWERPC64"
3910 "*
3911 {
3912 int start = INTVAL (operands[3]) & 63;
3913 int size = INTVAL (operands[2]) & 63;
3915 if (start + size >= 64)
3916 operands[3] = const0_rtx;
3917 else
3918 operands[3] = GEN_INT (start + size);
3919 operands[2] = GEN_INT (64 - size);
3920 return \"rldicl %0,%1,%3,%2\";
3921 }")
3923 (define_insn "*extzvdi_internal1"
3924 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3925 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3926 (match_operand:SI 2 "const_int_operand" "i")
3927 (match_operand:SI 3 "const_int_operand" "i"))
3928 (const_int 0)))
3929 (clobber (match_scratch:DI 4 "=r"))]
3930 "TARGET_64BIT && rs6000_gen_cell_microcode"
3931 "*
3932 {
3933 int start = INTVAL (operands[3]) & 63;
3934 int size = INTVAL (operands[2]) & 63;
3936 if (start + size >= 64)
3937 operands[3] = const0_rtx;
3938 else
3939 operands[3] = GEN_INT (start + size);
3940 operands[2] = GEN_INT (64 - size);
3941 return \"rldicl. %4,%1,%3,%2\";
3942 }"
3943 [(set_attr "type" "compare")])
3945 (define_insn "*extzvdi_internal2"
3946 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3947 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3948 (match_operand:SI 2 "const_int_operand" "i")
3949 (match_operand:SI 3 "const_int_operand" "i"))
3950 (const_int 0)))
3951 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3952 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3953 "TARGET_64BIT && rs6000_gen_cell_microcode"
3954 "*
3955 {
3956 int start = INTVAL (operands[3]) & 63;
3957 int size = INTVAL (operands[2]) & 63;
3959 if (start + size >= 64)
3960 operands[3] = const0_rtx;
3961 else
3962 operands[3] = GEN_INT (start + size);
3963 operands[2] = GEN_INT (64 - size);
3964 return \"rldicl. %0,%1,%3,%2\";
3965 }"
3966 [(set_attr "type" "compare")])
3968 (define_insn "rotlsi3"
3969 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3970 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3971 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3972 ""
3973 "@
3974 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3975 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3976 [(set_attr "type" "var_shift_rotate,integer")])
3978 (define_insn "*rotlsi3_internal2"
3979 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3980 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3981 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3982 (const_int 0)))
3983 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3984 ""
3985 "@
3986 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3987 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3988 #
3989 #"
3990 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3991 (set_attr "length" "4,4,8,8")])
3993 (define_split
3994 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3995 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3996 (match_operand:SI 2 "reg_or_cint_operand" ""))
3997 (const_int 0)))
3998 (clobber (match_scratch:SI 3 ""))]
3999 "reload_completed"
4000 [(set (match_dup 3)
4001 (rotate:SI (match_dup 1) (match_dup 2)))
4002 (set (match_dup 0)
4003 (compare:CC (match_dup 3)
4004 (const_int 0)))]
4005 "")
4007 (define_insn "*rotlsi3_internal3"
4008 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4009 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4010 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4011 (const_int 0)))
4012 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4013 (rotate:SI (match_dup 1) (match_dup 2)))]
4014 ""
4015 "@
4016 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4017 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4018 #
4019 #"
4020 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4021 (set_attr "length" "4,4,8,8")])
4023 (define_split
4024 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4025 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4026 (match_operand:SI 2 "reg_or_cint_operand" ""))
4027 (const_int 0)))
4028 (set (match_operand:SI 0 "gpc_reg_operand" "")
4029 (rotate:SI (match_dup 1) (match_dup 2)))]
4030 "reload_completed"
4031 [(set (match_dup 0)
4032 (rotate:SI (match_dup 1) (match_dup 2)))
4033 (set (match_dup 3)
4034 (compare:CC (match_dup 0)
4035 (const_int 0)))]
4036 "")
4038 (define_insn "*rotlsi3_internal4"
4039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4040 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4041 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4042 (match_operand:SI 3 "mask_operand" "n,n")))]
4043 ""
4044 "@
4045 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4046 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4047 [(set_attr "type" "var_shift_rotate,integer")])
4049 (define_insn "*rotlsi3_internal5"
4050 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4051 (compare:CC (and:SI
4052 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4053 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4054 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4055 (const_int 0)))
4056 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4057 ""
4058 "@
4059 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4060 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4061 #
4062 #"
4063 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4064 (set_attr "length" "4,4,8,8")])
4066 (define_split
4067 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4068 (compare:CC (and:SI
4069 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4070 (match_operand:SI 2 "reg_or_cint_operand" ""))
4071 (match_operand:SI 3 "mask_operand" ""))
4072 (const_int 0)))
4073 (clobber (match_scratch:SI 4 ""))]
4074 "reload_completed"
4075 [(set (match_dup 4)
4076 (and:SI (rotate:SI (match_dup 1)
4077 (match_dup 2))
4078 (match_dup 3)))
4079 (set (match_dup 0)
4080 (compare:CC (match_dup 4)
4081 (const_int 0)))]
4082 "")
4084 (define_insn "*rotlsi3_internal6"
4085 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4086 (compare:CC (and:SI
4087 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4088 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4089 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4090 (const_int 0)))
4091 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4092 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4093 ""
4094 "@
4095 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4096 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4097 #
4098 #"
4099 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4100 (set_attr "length" "4,4,8,8")])
4102 (define_split
4103 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4104 (compare:CC (and:SI
4105 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4106 (match_operand:SI 2 "reg_or_cint_operand" ""))
4107 (match_operand:SI 3 "mask_operand" ""))
4108 (const_int 0)))
4109 (set (match_operand:SI 0 "gpc_reg_operand" "")
4110 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4111 "reload_completed"
4112 [(set (match_dup 0)
4113 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4114 (set (match_dup 4)
4115 (compare:CC (match_dup 0)
4116 (const_int 0)))]
4117 "")
4119 (define_insn "*rotlsi3_internal7"
4120 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4121 (zero_extend:SI
4122 (subreg:QI
4123 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4124 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4125 ""
4126 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4127 [(set (attr "cell_micro")
4128 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4129 (const_string "not")
4130 (const_string "always")))])
4132 (define_insn "*rotlsi3_internal8"
4133 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4134 (compare:CC (zero_extend:SI
4135 (subreg:QI
4136 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4137 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4138 (const_int 0)))
4139 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4140 ""
4141 "@
4142 {rlnm.|rlwnm.} %3,%1,%2,0xff
4143 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4144 #
4145 #"
4146 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4147 (set_attr "length" "4,4,8,8")])
4149 (define_split
4150 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4151 (compare:CC (zero_extend:SI
4152 (subreg:QI
4153 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4154 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4155 (const_int 0)))
4156 (clobber (match_scratch:SI 3 ""))]
4157 "reload_completed"
4158 [(set (match_dup 3)
4159 (zero_extend:SI (subreg:QI
4160 (rotate:SI (match_dup 1)
4161 (match_dup 2)) 0)))
4162 (set (match_dup 0)
4163 (compare:CC (match_dup 3)
4164 (const_int 0)))]
4165 "")
4167 (define_insn "*rotlsi3_internal9"
4168 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4169 (compare:CC (zero_extend:SI
4170 (subreg:QI
4171 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4172 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4173 (const_int 0)))
4174 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4175 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4176 ""
4177 "@
4178 {rlnm.|rlwnm.} %0,%1,%2,0xff
4179 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4180 #
4181 #"
4182 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4183 (set_attr "length" "4,4,8,8")])
4185 (define_split
4186 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4187 (compare:CC (zero_extend:SI
4188 (subreg:QI
4189 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4190 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4191 (const_int 0)))
4192 (set (match_operand:SI 0 "gpc_reg_operand" "")
4193 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4194 "reload_completed"
4195 [(set (match_dup 0)
4196 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4197 (set (match_dup 3)
4198 (compare:CC (match_dup 0)
4199 (const_int 0)))]
4200 "")
4202 (define_insn "*rotlsi3_internal10"
4203 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4204 (zero_extend:SI
4205 (subreg:HI
4206 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4207 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4208 ""
4209 "@
4210 {rlnm|rlwnm} %0,%1,%2,0xffff
4211 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4212 [(set_attr "type" "var_shift_rotate,integer")])
4215 (define_insn "*rotlsi3_internal11"
4216 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4217 (compare:CC (zero_extend:SI
4218 (subreg:HI
4219 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4220 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4221 (const_int 0)))
4222 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4223 ""
4224 "@
4225 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4226 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4227 #
4228 #"
4229 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4230 (set_attr "length" "4,4,8,8")])
4232 (define_split
4233 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4234 (compare:CC (zero_extend:SI
4235 (subreg:HI
4236 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4237 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4238 (const_int 0)))
4239 (clobber (match_scratch:SI 3 ""))]
4240 "reload_completed"
4241 [(set (match_dup 3)
4242 (zero_extend:SI (subreg:HI
4243 (rotate:SI (match_dup 1)
4244 (match_dup 2)) 0)))
4245 (set (match_dup 0)
4246 (compare:CC (match_dup 3)
4247 (const_int 0)))]
4248 "")
4250 (define_insn "*rotlsi3_internal12"
4251 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4252 (compare:CC (zero_extend:SI
4253 (subreg:HI
4254 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4255 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4256 (const_int 0)))
4257 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4258 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4259 ""
4260 "@
4261 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4262 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4263 #
4264 #"
4265 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4266 (set_attr "length" "4,4,8,8")])
4268 (define_split
4269 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4270 (compare:CC (zero_extend:SI
4271 (subreg:HI
4272 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4273 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4274 (const_int 0)))
4275 (set (match_operand:SI 0 "gpc_reg_operand" "")
4276 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4277 "reload_completed"
4278 [(set (match_dup 0)
4279 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4280 (set (match_dup 3)
4281 (compare:CC (match_dup 0)
4282 (const_int 0)))]
4283 "")
4285 ;; Note that we use "sle." instead of "sl." so that we can set
4286 ;; SHIFT_COUNT_TRUNCATED.
4288 (define_expand "ashlsi3"
4289 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4290 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4291 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4292 ""
4293 "
4294 {
4295 if (TARGET_POWER)
4296 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4297 else
4298 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4299 DONE;
4300 }")
4302 (define_insn "ashlsi3_power"
4303 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4304 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4305 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4306 (clobber (match_scratch:SI 3 "=q,X"))]
4307 "TARGET_POWER"
4308 "@
4309 sle %0,%1,%2
4310 {sli|slwi} %0,%1,%h2")
4312 (define_insn "ashlsi3_no_power"
4313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4314 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4315 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4316 "! TARGET_POWER"
4317 "@
4318 {sl|slw} %0,%1,%2
4319 {sli|slwi} %0,%1,%h2"
4320 [(set_attr "type" "var_shift_rotate,shift")])
4322 (define_insn ""
4323 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4324 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4325 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4326 (const_int 0)))
4327 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4328 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4329 "TARGET_POWER"
4330 "@
4331 sle. %3,%1,%2
4332 {sli.|slwi.} %3,%1,%h2
4333 #
4334 #"
4335 [(set_attr "type" "delayed_compare")
4336 (set_attr "length" "4,4,8,8")])
4338 (define_split
4339 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4340 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4341 (match_operand:SI 2 "reg_or_cint_operand" ""))
4342 (const_int 0)))
4343 (clobber (match_scratch:SI 3 ""))
4344 (clobber (match_scratch:SI 4 ""))]
4345 "TARGET_POWER && reload_completed"
4346 [(parallel [(set (match_dup 3)
4347 (ashift:SI (match_dup 1) (match_dup 2)))
4348 (clobber (match_dup 4))])
4349 (set (match_dup 0)
4350 (compare:CC (match_dup 3)
4351 (const_int 0)))]
4352 "")
4354 (define_insn ""
4355 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4356 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4357 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4358 (const_int 0)))
4359 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4360 "! TARGET_POWER && TARGET_32BIT"
4361 "@
4362 {sl.|slw.} %3,%1,%2
4363 {sli.|slwi.} %3,%1,%h2
4364 #
4365 #"
4366 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4367 (set_attr "length" "4,4,8,8")])
4369 (define_split
4370 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4371 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4372 (match_operand:SI 2 "reg_or_cint_operand" ""))
4373 (const_int 0)))
4374 (clobber (match_scratch:SI 3 ""))]
4375 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4376 [(set (match_dup 3)
4377 (ashift:SI (match_dup 1) (match_dup 2)))
4378 (set (match_dup 0)
4379 (compare:CC (match_dup 3)
4380 (const_int 0)))]
4381 "")
4383 (define_insn ""
4384 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4385 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4386 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4387 (const_int 0)))
4388 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4389 (ashift:SI (match_dup 1) (match_dup 2)))
4390 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4391 "TARGET_POWER"
4392 "@
4393 sle. %0,%1,%2
4394 {sli.|slwi.} %0,%1,%h2
4395 #
4396 #"
4397 [(set_attr "type" "delayed_compare")
4398 (set_attr "length" "4,4,8,8")])
4400 (define_split
4401 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4402 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4403 (match_operand:SI 2 "reg_or_cint_operand" ""))
4404 (const_int 0)))
4405 (set (match_operand:SI 0 "gpc_reg_operand" "")
4406 (ashift:SI (match_dup 1) (match_dup 2)))
4407 (clobber (match_scratch:SI 4 ""))]
4408 "TARGET_POWER && reload_completed"
4409 [(parallel [(set (match_dup 0)
4410 (ashift:SI (match_dup 1) (match_dup 2)))
4411 (clobber (match_dup 4))])
4412 (set (match_dup 3)
4413 (compare:CC (match_dup 0)
4414 (const_int 0)))]
4415 "")
4417 (define_insn ""
4418 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4419 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4420 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4421 (const_int 0)))
4422 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4423 (ashift:SI (match_dup 1) (match_dup 2)))]
4424 "! TARGET_POWER && TARGET_32BIT"
4425 "@
4426 {sl.|slw.} %0,%1,%2
4427 {sli.|slwi.} %0,%1,%h2
4428 #
4429 #"
4430 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4431 (set_attr "length" "4,4,8,8")])
4433 (define_split
4434 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4435 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4436 (match_operand:SI 2 "reg_or_cint_operand" ""))
4437 (const_int 0)))
4438 (set (match_operand:SI 0 "gpc_reg_operand" "")
4439 (ashift:SI (match_dup 1) (match_dup 2)))]
4440 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4441 [(set (match_dup 0)
4442 (ashift:SI (match_dup 1) (match_dup 2)))
4443 (set (match_dup 3)
4444 (compare:CC (match_dup 0)
4445 (const_int 0)))]
4446 "")
4448 (define_insn "rlwinm"
4449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4450 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4451 (match_operand:SI 2 "const_int_operand" "i"))
4452 (match_operand:SI 3 "mask_operand" "n")))]
4453 "includes_lshift_p (operands[2], operands[3])"
4454 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4456 (define_insn ""
4457 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4458 (compare:CC
4459 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4460 (match_operand:SI 2 "const_int_operand" "i,i"))
4461 (match_operand:SI 3 "mask_operand" "n,n"))
4462 (const_int 0)))
4463 (clobber (match_scratch:SI 4 "=r,r"))]
4464 "includes_lshift_p (operands[2], operands[3])"
4465 "@
4466 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4467 #"
4468 [(set_attr "type" "delayed_compare")
4469 (set_attr "length" "4,8")])
4471 (define_split
4472 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4473 (compare:CC
4474 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4475 (match_operand:SI 2 "const_int_operand" ""))
4476 (match_operand:SI 3 "mask_operand" ""))
4477 (const_int 0)))
4478 (clobber (match_scratch:SI 4 ""))]
4479 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4480 [(set (match_dup 4)
4481 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4482 (match_dup 3)))
4483 (set (match_dup 0)
4484 (compare:CC (match_dup 4)
4485 (const_int 0)))]
4486 "")
4488 (define_insn ""
4489 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4490 (compare:CC
4491 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4492 (match_operand:SI 2 "const_int_operand" "i,i"))
4493 (match_operand:SI 3 "mask_operand" "n,n"))
4494 (const_int 0)))
4495 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4496 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4497 "includes_lshift_p (operands[2], operands[3])"
4498 "@
4499 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4500 #"
4501 [(set_attr "type" "delayed_compare")
4502 (set_attr "length" "4,8")])
4504 (define_split
4505 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4506 (compare:CC
4507 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4508 (match_operand:SI 2 "const_int_operand" ""))
4509 (match_operand:SI 3 "mask_operand" ""))
4510 (const_int 0)))
4511 (set (match_operand:SI 0 "gpc_reg_operand" "")
4512 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4513 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4514 [(set (match_dup 0)
4515 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4516 (set (match_dup 4)
4517 (compare:CC (match_dup 0)
4518 (const_int 0)))]
4519 "")
4521 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4522 ;; "sli x,x,0".
4523 (define_expand "lshrsi3"
4524 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4525 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4526 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4527 ""
4528 "
4529 {
4530 if (TARGET_POWER)
4531 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4532 else
4533 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4534 DONE;
4535 }")
4537 (define_insn "lshrsi3_power"
4538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4539 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4540 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4541 (clobber (match_scratch:SI 3 "=q,X,X"))]
4542 "TARGET_POWER"
4543 "@
4544 sre %0,%1,%2
4545 mr %0,%1
4546 {s%A2i|s%A2wi} %0,%1,%h2")
4548 (define_insn "lshrsi3_no_power"
4549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4550 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4551 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4552 "! TARGET_POWER"
4553 "@
4554 mr %0,%1
4555 {sr|srw} %0,%1,%2
4556 {sri|srwi} %0,%1,%h2"
4557 [(set_attr "type" "integer,var_shift_rotate,shift")])
4559 (define_insn ""
4560 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4561 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4562 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4563 (const_int 0)))
4564 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4565 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4566 "TARGET_POWER"
4567 "@
4568 sre. %3,%1,%2
4569 mr. %1,%1
4570 {s%A2i.|s%A2wi.} %3,%1,%h2
4571 #
4572 #
4573 #"
4574 [(set_attr "type" "delayed_compare")
4575 (set_attr "length" "4,4,4,8,8,8")])
4577 (define_split
4578 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4579 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4580 (match_operand:SI 2 "reg_or_cint_operand" ""))
4581 (const_int 0)))
4582 (clobber (match_scratch:SI 3 ""))
4583 (clobber (match_scratch:SI 4 ""))]
4584 "TARGET_POWER && reload_completed"
4585 [(parallel [(set (match_dup 3)
4586 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4587 (clobber (match_dup 4))])
4588 (set (match_dup 0)
4589 (compare:CC (match_dup 3)
4590 (const_int 0)))]
4591 "")
4593 (define_insn ""
4594 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4595 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4596 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4597 (const_int 0)))
4598 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4599 "! TARGET_POWER && TARGET_32BIT"
4600 "@
4601 mr. %1,%1
4602 {sr.|srw.} %3,%1,%2
4603 {sri.|srwi.} %3,%1,%h2
4604 #
4605 #
4606 #"
4607 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4608 (set_attr "length" "4,4,4,8,8,8")])
4610 (define_split
4611 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4612 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4613 (match_operand:SI 2 "reg_or_cint_operand" ""))
4614 (const_int 0)))
4615 (clobber (match_scratch:SI 3 ""))]
4616 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4617 [(set (match_dup 3)
4618 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4619 (set (match_dup 0)
4620 (compare:CC (match_dup 3)
4621 (const_int 0)))]
4622 "")
4624 (define_insn ""
4625 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4626 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4627 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4628 (const_int 0)))
4629 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4630 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4631 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4632 "TARGET_POWER"
4633 "@
4634 sre. %0,%1,%2
4635 mr. %0,%1
4636 {s%A2i.|s%A2wi.} %0,%1,%h2
4637 #
4638 #
4639 #"
4640 [(set_attr "type" "delayed_compare")
4641 (set_attr "length" "4,4,4,8,8,8")])
4643 (define_split
4644 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4645 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4646 (match_operand:SI 2 "reg_or_cint_operand" ""))
4647 (const_int 0)))
4648 (set (match_operand:SI 0 "gpc_reg_operand" "")
4649 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4650 (clobber (match_scratch:SI 4 ""))]
4651 "TARGET_POWER && reload_completed"
4652 [(parallel [(set (match_dup 0)
4653 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4654 (clobber (match_dup 4))])
4655 (set (match_dup 3)
4656 (compare:CC (match_dup 0)
4657 (const_int 0)))]
4658 "")
4660 (define_insn ""
4661 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4662 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4663 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4664 (const_int 0)))
4665 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4666 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4667 "! TARGET_POWER && TARGET_32BIT"
4668 "@
4669 mr. %0,%1
4670 {sr.|srw.} %0,%1,%2
4671 {sri.|srwi.} %0,%1,%h2
4672 #
4673 #
4674 #"
4675 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4676 (set_attr "length" "4,4,4,8,8,8")])
4678 (define_split
4679 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4680 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4681 (match_operand:SI 2 "reg_or_cint_operand" ""))
4682 (const_int 0)))
4683 (set (match_operand:SI 0 "gpc_reg_operand" "")
4684 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4685 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4686 [(set (match_dup 0)
4687 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4688 (set (match_dup 3)
4689 (compare:CC (match_dup 0)
4690 (const_int 0)))]
4691 "")
4693 (define_insn ""
4694 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4695 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4696 (match_operand:SI 2 "const_int_operand" "i"))
4697 (match_operand:SI 3 "mask_operand" "n")))]
4698 "includes_rshift_p (operands[2], operands[3])"
4699 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4701 (define_insn ""
4702 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4703 (compare:CC
4704 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4705 (match_operand:SI 2 "const_int_operand" "i,i"))
4706 (match_operand:SI 3 "mask_operand" "n,n"))
4707 (const_int 0)))
4708 (clobber (match_scratch:SI 4 "=r,r"))]
4709 "includes_rshift_p (operands[2], operands[3])"
4710 "@
4711 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4712 #"
4713 [(set_attr "type" "delayed_compare")
4714 (set_attr "length" "4,8")])
4716 (define_split
4717 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4718 (compare:CC
4719 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4720 (match_operand:SI 2 "const_int_operand" ""))
4721 (match_operand:SI 3 "mask_operand" ""))
4722 (const_int 0)))
4723 (clobber (match_scratch:SI 4 ""))]
4724 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4725 [(set (match_dup 4)
4726 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4727 (match_dup 3)))
4728 (set (match_dup 0)
4729 (compare:CC (match_dup 4)
4730 (const_int 0)))]
4731 "")
4733 (define_insn ""
4734 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4735 (compare:CC
4736 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4737 (match_operand:SI 2 "const_int_operand" "i,i"))
4738 (match_operand:SI 3 "mask_operand" "n,n"))
4739 (const_int 0)))
4740 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4741 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4742 "includes_rshift_p (operands[2], operands[3])"
4743 "@
4744 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4745 #"
4746 [(set_attr "type" "delayed_compare")
4747 (set_attr "length" "4,8")])
4749 (define_split
4750 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4751 (compare:CC
4752 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4753 (match_operand:SI 2 "const_int_operand" ""))
4754 (match_operand:SI 3 "mask_operand" ""))
4755 (const_int 0)))
4756 (set (match_operand:SI 0 "gpc_reg_operand" "")
4757 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4758 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4759 [(set (match_dup 0)
4760 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4761 (set (match_dup 4)
4762 (compare:CC (match_dup 0)
4763 (const_int 0)))]
4764 "")
4766 (define_insn ""
4767 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4768 (zero_extend:SI
4769 (subreg:QI
4770 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4771 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4772 "includes_rshift_p (operands[2], GEN_INT (255))"
4773 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4775 (define_insn ""
4776 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4777 (compare:CC
4778 (zero_extend:SI
4779 (subreg:QI
4780 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4781 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4782 (const_int 0)))
4783 (clobber (match_scratch:SI 3 "=r,r"))]
4784 "includes_rshift_p (operands[2], GEN_INT (255))"
4785 "@
4786 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4787 #"
4788 [(set_attr "type" "delayed_compare")
4789 (set_attr "length" "4,8")])
4791 (define_split
4792 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4793 (compare:CC
4794 (zero_extend:SI
4795 (subreg:QI
4796 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4797 (match_operand:SI 2 "const_int_operand" "")) 0))
4798 (const_int 0)))
4799 (clobber (match_scratch:SI 3 ""))]
4800 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4801 [(set (match_dup 3)
4802 (zero_extend:SI (subreg:QI
4803 (lshiftrt:SI (match_dup 1)
4804 (match_dup 2)) 0)))
4805 (set (match_dup 0)
4806 (compare:CC (match_dup 3)
4807 (const_int 0)))]
4808 "")
4810 (define_insn ""
4811 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4812 (compare:CC
4813 (zero_extend:SI
4814 (subreg:QI
4815 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4816 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4817 (const_int 0)))
4818 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4819 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4820 "includes_rshift_p (operands[2], GEN_INT (255))"
4821 "@
4822 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4823 #"
4824 [(set_attr "type" "delayed_compare")
4825 (set_attr "length" "4,8")])
4827 (define_split
4828 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4829 (compare:CC
4830 (zero_extend:SI
4831 (subreg:QI
4832 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4833 (match_operand:SI 2 "const_int_operand" "")) 0))
4834 (const_int 0)))
4835 (set (match_operand:SI 0 "gpc_reg_operand" "")
4836 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4837 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4838 [(set (match_dup 0)
4839 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4840 (set (match_dup 3)
4841 (compare:CC (match_dup 0)
4842 (const_int 0)))]
4843 "")
4845 (define_insn ""
4846 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4847 (zero_extend:SI
4848 (subreg:HI
4849 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4850 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4851 "includes_rshift_p (operands[2], GEN_INT (65535))"
4852 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4854 (define_insn ""
4855 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4856 (compare:CC
4857 (zero_extend:SI
4858 (subreg:HI
4859 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4860 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4861 (const_int 0)))
4862 (clobber (match_scratch:SI 3 "=r,r"))]
4863 "includes_rshift_p (operands[2], GEN_INT (65535))"
4864 "@
4865 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4866 #"
4867 [(set_attr "type" "delayed_compare")
4868 (set_attr "length" "4,8")])
4870 (define_split
4871 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4872 (compare:CC
4873 (zero_extend:SI
4874 (subreg:HI
4875 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4876 (match_operand:SI 2 "const_int_operand" "")) 0))
4877 (const_int 0)))
4878 (clobber (match_scratch:SI 3 ""))]
4879 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4880 [(set (match_dup 3)
4881 (zero_extend:SI (subreg:HI
4882 (lshiftrt:SI (match_dup 1)
4883 (match_dup 2)) 0)))
4884 (set (match_dup 0)
4885 (compare:CC (match_dup 3)
4886 (const_int 0)))]
4887 "")
4889 (define_insn ""
4890 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4891 (compare:CC
4892 (zero_extend:SI
4893 (subreg:HI
4894 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4895 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4896 (const_int 0)))
4897 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4898 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4899 "includes_rshift_p (operands[2], GEN_INT (65535))"
4900 "@
4901 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4902 #"
4903 [(set_attr "type" "delayed_compare")
4904 (set_attr "length" "4,8")])
4906 (define_split
4907 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4908 (compare:CC
4909 (zero_extend:SI
4910 (subreg:HI
4911 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4912 (match_operand:SI 2 "const_int_operand" "")) 0))
4913 (const_int 0)))
4914 (set (match_operand:SI 0 "gpc_reg_operand" "")
4915 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4916 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4917 [(set (match_dup 0)
4918 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4919 (set (match_dup 3)
4920 (compare:CC (match_dup 0)
4921 (const_int 0)))]
4922 "")
4924 (define_insn ""
4925 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4926 (const_int 1)
4927 (match_operand:SI 1 "gpc_reg_operand" "r"))
4928 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4929 (const_int 31)))]
4930 "TARGET_POWER"
4931 "rrib %0,%1,%2")
4933 (define_insn ""
4934 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4935 (const_int 1)
4936 (match_operand:SI 1 "gpc_reg_operand" "r"))
4937 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4938 (const_int 31)))]
4939 "TARGET_POWER"
4940 "rrib %0,%1,%2")
4942 (define_insn ""
4943 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4944 (const_int 1)
4945 (match_operand:SI 1 "gpc_reg_operand" "r"))
4946 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4947 (const_int 1)
4948 (const_int 0)))]
4949 "TARGET_POWER"
4950 "rrib %0,%1,%2")
4952 (define_expand "ashrsi3"
4953 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4954 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4955 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4956 ""
4957 "
4958 {
4959 if (TARGET_POWER)
4960 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4961 else
4962 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4963 DONE;
4964 }")
4966 (define_insn "ashrsi3_power"
4967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4968 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4969 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4970 (clobber (match_scratch:SI 3 "=q,X"))]
4971 "TARGET_POWER"
4972 "@
4973 srea %0,%1,%2
4974 {srai|srawi} %0,%1,%h2"
4975 [(set_attr "type" "shift")])
4977 (define_insn "ashrsi3_no_power"
4978 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4979 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4980 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4981 "! TARGET_POWER"
4982 "@
4983 {sra|sraw} %0,%1,%2
4984 {srai|srawi} %0,%1,%h2"
4985 [(set_attr "type" "var_shift_rotate,shift")])
4987 (define_insn ""
4988 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4989 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4990 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4991 (const_int 0)))
4992 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4993 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4994 "TARGET_POWER"
4995 "@
4996 srea. %3,%1,%2
4997 {srai.|srawi.} %3,%1,%h2
4998 #
4999 #"
5000 [(set_attr "type" "delayed_compare")
5001 (set_attr "length" "4,4,8,8")])
5003 (define_split
5004 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5005 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5006 (match_operand:SI 2 "reg_or_cint_operand" ""))
5007 (const_int 0)))
5008 (clobber (match_scratch:SI 3 ""))
5009 (clobber (match_scratch:SI 4 ""))]
5010 "TARGET_POWER && reload_completed"
5011 [(parallel [(set (match_dup 3)
5012 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5013 (clobber (match_dup 4))])
5014 (set (match_dup 0)
5015 (compare:CC (match_dup 3)
5016 (const_int 0)))]
5017 "")
5019 (define_insn ""
5020 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5021 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5022 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5023 (const_int 0)))
5024 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5025 "! TARGET_POWER"
5026 "@
5027 {sra.|sraw.} %3,%1,%2
5028 {srai.|srawi.} %3,%1,%h2
5029 #
5030 #"
5031 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5032 (set_attr "length" "4,4,8,8")])
5034 (define_split
5035 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5036 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5037 (match_operand:SI 2 "reg_or_cint_operand" ""))
5038 (const_int 0)))
5039 (clobber (match_scratch:SI 3 ""))]
5040 "! TARGET_POWER && reload_completed"
5041 [(set (match_dup 3)
5042 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5043 (set (match_dup 0)
5044 (compare:CC (match_dup 3)
5045 (const_int 0)))]
5046 "")
5048 (define_insn ""
5049 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5050 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5051 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5052 (const_int 0)))
5053 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5054 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5055 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5056 "TARGET_POWER"
5057 "@
5058 srea. %0,%1,%2
5059 {srai.|srawi.} %0,%1,%h2
5060 #
5061 #"
5062 [(set_attr "type" "delayed_compare")
5063 (set_attr "length" "4,4,8,8")])
5065 (define_split
5066 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5067 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5068 (match_operand:SI 2 "reg_or_cint_operand" ""))
5069 (const_int 0)))
5070 (set (match_operand:SI 0 "gpc_reg_operand" "")
5071 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5072 (clobber (match_scratch:SI 4 ""))]
5073 "TARGET_POWER && reload_completed"
5074 [(parallel [(set (match_dup 0)
5075 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5076 (clobber (match_dup 4))])
5077 (set (match_dup 3)
5078 (compare:CC (match_dup 0)
5079 (const_int 0)))]
5080 "")
5082 (define_insn ""
5083 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5084 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5085 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5086 (const_int 0)))
5087 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5088 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5089 "! TARGET_POWER"
5090 "@
5091 {sra.|sraw.} %0,%1,%2
5092 {srai.|srawi.} %0,%1,%h2
5093 #
5094 #"
5095 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5096 (set_attr "length" "4,4,8,8")])
5097 \f
5098 (define_split
5099 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5100 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5101 (match_operand:SI 2 "reg_or_cint_operand" ""))
5102 (const_int 0)))
5103 (set (match_operand:SI 0 "gpc_reg_operand" "")
5104 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5105 "! TARGET_POWER && reload_completed"
5106 [(set (match_dup 0)
5107 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5108 (set (match_dup 3)
5109 (compare:CC (match_dup 0)
5110 (const_int 0)))]
5111 "")
5113 ;; Floating-point insns, excluding normal data motion.
5114 ;;
5115 ;; PowerPC has a full set of single-precision floating point instructions.
5116 ;;
5117 ;; For the POWER architecture, we pretend that we have both SFmode and
5118 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5119 ;; The only conversions we will do will be when storing to memory. In that
5120 ;; case, we will use the "frsp" instruction before storing.
5121 ;;
5122 ;; Note that when we store into a single-precision memory location, we need to
5123 ;; use the frsp insn first. If the register being stored isn't dead, we
5124 ;; need a scratch register for the frsp. But this is difficult when the store
5125 ;; is done by reload. It is not incorrect to do the frsp on the register in
5126 ;; this case, we just lose precision that we would have otherwise gotten but
5127 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5129 (define_expand "extendsfdf2"
5130 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5131 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5132 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5133 "")
5135 (define_insn_and_split "*extendsfdf2_fpr"
5136 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5137 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5138 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5139 "@
5140 #
5141 fmr %0,%1
5142 lfs%U1%X1 %0,%1"
5143 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5144 [(const_int 0)]
5145 {
5146 emit_note (NOTE_INSN_DELETED);
5147 DONE;
5148 }
5149 [(set_attr "type" "fp,fp,fpload")])
5151 (define_expand "truncdfsf2"
5152 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5153 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5154 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5155 "")
5157 (define_insn "*truncdfsf2_fpr"
5158 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5159 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5160 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5161 "frsp %0,%1"
5162 [(set_attr "type" "fp")])
5164 (define_insn "aux_truncdfsf2"
5165 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5166 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5167 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5168 "frsp %0,%1"
5169 [(set_attr "type" "fp")])
5171 (define_expand "negsf2"
5172 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5173 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5174 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5175 "")
5177 (define_insn "*negsf2"
5178 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5179 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5180 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5181 "fneg %0,%1"
5182 [(set_attr "type" "fp")])
5184 (define_expand "abssf2"
5185 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5186 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5187 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5188 "")
5190 (define_insn "*abssf2"
5191 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5192 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5193 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5194 "fabs %0,%1"
5195 [(set_attr "type" "fp")])
5197 (define_insn ""
5198 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5199 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5200 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5201 "fnabs %0,%1"
5202 [(set_attr "type" "fp")])
5204 (define_expand "addsf3"
5205 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5206 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5207 (match_operand:SF 2 "gpc_reg_operand" "")))]
5208 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5209 "")
5211 (define_insn ""
5212 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5213 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5214 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5215 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5216 "fadds %0,%1,%2"
5217 [(set_attr "type" "fp")
5218 (set_attr "fp_type" "fp_addsub_s")])
5220 (define_insn ""
5221 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5222 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5223 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5224 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5225 "{fa|fadd} %0,%1,%2"
5226 [(set_attr "type" "fp")])
5228 (define_expand "subsf3"
5229 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5230 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5231 (match_operand:SF 2 "gpc_reg_operand" "")))]
5232 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5233 "")
5235 (define_insn ""
5236 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5237 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5238 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5239 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5240 "fsubs %0,%1,%2"
5241 [(set_attr "type" "fp")
5242 (set_attr "fp_type" "fp_addsub_s")])
5244 (define_insn ""
5245 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5246 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5247 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5248 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5249 "{fs|fsub} %0,%1,%2"
5250 [(set_attr "type" "fp")])
5252 (define_expand "mulsf3"
5253 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5254 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5255 (match_operand:SF 2 "gpc_reg_operand" "")))]
5256 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5257 "")
5259 (define_insn ""
5260 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5261 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5262 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5263 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5264 "fmuls %0,%1,%2"
5265 [(set_attr "type" "fp")
5266 (set_attr "fp_type" "fp_mul_s")])
5268 (define_insn ""
5269 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5270 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5271 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5272 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5273 "{fm|fmul} %0,%1,%2"
5274 [(set_attr "type" "dmul")])
5276 (define_expand "divsf3"
5277 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5278 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5279 (match_operand:SF 2 "gpc_reg_operand" "")))]
5280 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5281 "")
5283 (define_insn ""
5284 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5285 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5286 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5287 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5288 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5289 "fdivs %0,%1,%2"
5290 [(set_attr "type" "sdiv")])
5292 (define_insn ""
5293 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5294 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5295 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5296 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5297 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5298 "{fd|fdiv} %0,%1,%2"
5299 [(set_attr "type" "ddiv")])
5301 (define_expand "recipsf3"
5302 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5303 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5304 (match_operand:SF 2 "gpc_reg_operand" "f")]
5305 UNSPEC_FRES))]
5306 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5307 && flag_finite_math_only && !flag_trapping_math"
5308 {
5309 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5310 DONE;
5311 })
5313 (define_insn "fres"
5314 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5315 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5316 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5317 "fres %0,%1"
5318 [(set_attr "type" "fp")])
5320 (define_insn ""
5321 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5322 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5323 (match_operand:SF 2 "gpc_reg_operand" "f"))
5324 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5325 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5326 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5327 "fmadds %0,%1,%2,%3"
5328 [(set_attr "type" "fp")
5329 (set_attr "fp_type" "fp_maddsub_s")])
5331 (define_insn ""
5332 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5333 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5334 (match_operand:SF 2 "gpc_reg_operand" "f"))
5335 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5336 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5337 "{fma|fmadd} %0,%1,%2,%3"
5338 [(set_attr "type" "dmul")])
5340 (define_insn ""
5341 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5342 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5343 (match_operand:SF 2 "gpc_reg_operand" "f"))
5344 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5345 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5346 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5347 "fmsubs %0,%1,%2,%3"
5348 [(set_attr "type" "fp")
5349 (set_attr "fp_type" "fp_maddsub_s")])
5351 (define_insn ""
5352 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5353 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5354 (match_operand:SF 2 "gpc_reg_operand" "f"))
5355 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5356 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5357 "{fms|fmsub} %0,%1,%2,%3"
5358 [(set_attr "type" "dmul")])
5360 (define_insn ""
5361 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5362 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5363 (match_operand:SF 2 "gpc_reg_operand" "f"))
5364 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5365 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5366 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5367 "fnmadds %0,%1,%2,%3"
5368 [(set_attr "type" "fp")
5369 (set_attr "fp_type" "fp_maddsub_s")])
5371 (define_insn ""
5372 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5373 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5374 (match_operand:SF 2 "gpc_reg_operand" "f"))
5375 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5376 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5377 && ! HONOR_SIGNED_ZEROS (SFmode)"
5378 "fnmadds %0,%1,%2,%3"
5379 [(set_attr "type" "fp")
5380 (set_attr "fp_type" "fp_maddsub_s")])
5382 (define_insn ""
5383 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5384 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5385 (match_operand:SF 2 "gpc_reg_operand" "f"))
5386 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5387 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5388 "{fnma|fnmadd} %0,%1,%2,%3"
5389 [(set_attr "type" "dmul")])
5391 (define_insn ""
5392 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5393 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5394 (match_operand:SF 2 "gpc_reg_operand" "f"))
5395 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5396 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5397 && ! HONOR_SIGNED_ZEROS (SFmode)"
5398 "{fnma|fnmadd} %0,%1,%2,%3"
5399 [(set_attr "type" "dmul")])
5401 (define_insn ""
5402 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5403 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5404 (match_operand:SF 2 "gpc_reg_operand" "f"))
5405 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5406 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5407 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5408 "fnmsubs %0,%1,%2,%3"
5409 [(set_attr "type" "fp")
5410 (set_attr "fp_type" "fp_maddsub_s")])
5412 (define_insn ""
5413 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5414 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5415 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5416 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5417 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5418 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5419 "fnmsubs %0,%1,%2,%3"
5420 [(set_attr "type" "fp")
5421 (set_attr "fp_type" "fp_maddsub_s")])
5423 (define_insn ""
5424 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5425 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5426 (match_operand:SF 2 "gpc_reg_operand" "f"))
5427 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5428 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5429 "{fnms|fnmsub} %0,%1,%2,%3"
5430 [(set_attr "type" "dmul")])
5432 (define_insn ""
5433 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5434 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5435 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5436 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5437 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5438 && ! HONOR_SIGNED_ZEROS (SFmode)"
5439 "{fnms|fnmsub} %0,%1,%2,%3"
5440 [(set_attr "type" "dmul")])
5442 (define_expand "sqrtsf2"
5443 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5444 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5445 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5446 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5447 && !TARGET_SIMPLE_FPU"
5448 "")
5450 (define_insn ""
5451 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5452 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5453 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5454 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5455 "fsqrts %0,%1"
5456 [(set_attr "type" "ssqrt")])
5458 (define_insn ""
5459 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5460 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5461 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5462 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5463 "fsqrt %0,%1"
5464 [(set_attr "type" "dsqrt")])
5466 (define_expand "rsqrtsf2"
5467 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5468 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5469 UNSPEC_RSQRT))]
5470 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5471 && flag_finite_math_only && !flag_trapping_math"
5472 {
5473 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5474 DONE;
5475 })
5477 (define_insn "*rsqrt_internal1"
5478 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5479 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5480 UNSPEC_RSQRT))]
5481 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5482 "frsqrte %0,%1"
5483 [(set_attr "type" "fp")])
5485 (define_expand "copysignsf3"
5486 [(set (match_dup 3)
5487 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5488 (set (match_dup 4)
5489 (neg:SF (abs:SF (match_dup 1))))
5490 (set (match_operand:SF 0 "gpc_reg_operand" "")
5491 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5492 (match_dup 5))
5493 (match_dup 3)
5494 (match_dup 4)))]
5495 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5496 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5497 {
5498 operands[3] = gen_reg_rtx (SFmode);
5499 operands[4] = gen_reg_rtx (SFmode);
5500 operands[5] = CONST0_RTX (SFmode);
5501 })
5503 (define_expand "copysigndf3"
5504 [(set (match_dup 3)
5505 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5506 (set (match_dup 4)
5507 (neg:DF (abs:DF (match_dup 1))))
5508 (set (match_operand:DF 0 "gpc_reg_operand" "")
5509 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5510 (match_dup 5))
5511 (match_dup 3)
5512 (match_dup 4)))]
5513 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5514 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5515 {
5516 operands[3] = gen_reg_rtx (DFmode);
5517 operands[4] = gen_reg_rtx (DFmode);
5518 operands[5] = CONST0_RTX (DFmode);
5519 })
5521 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5522 ;; fsel instruction and some auxiliary computations. Then we just have a
5523 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5524 ;; combine.
5525 (define_expand "smaxsf3"
5526 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5527 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5528 (match_operand:SF 2 "gpc_reg_operand" ""))
5529 (match_dup 1)
5530 (match_dup 2)))]
5531 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5532 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5533 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5535 (define_expand "sminsf3"
5536 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5537 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5538 (match_operand:SF 2 "gpc_reg_operand" ""))
5539 (match_dup 2)
5540 (match_dup 1)))]
5541 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5542 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5543 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5545 (define_split
5546 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5547 (match_operator:SF 3 "min_max_operator"
5548 [(match_operand:SF 1 "gpc_reg_operand" "")
5549 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5550 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5551 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5552 [(const_int 0)]
5553 "
5554 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5555 operands[1], operands[2]);
5556 DONE;
5557 }")
5559 (define_expand "movsicc"
5560 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5561 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5562 (match_operand:SI 2 "gpc_reg_operand" "")
5563 (match_operand:SI 3 "gpc_reg_operand" "")))]
5564 "TARGET_ISEL"
5565 "
5566 {
5567 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5568 DONE;
5569 else
5570 FAIL;
5571 }")
5573 ;; We use the BASE_REGS for the isel input operands because, if rA is
5574 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5575 ;; because we may switch the operands and rB may end up being rA.
5576 ;;
5577 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5578 ;; leave out the mode in operand 4 and use one pattern, but reload can
5579 ;; change the mode underneath our feet and then gets confused trying
5580 ;; to reload the value.
5581 (define_insn "isel_signed"
5582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5583 (if_then_else:SI
5584 (match_operator 1 "comparison_operator"
5585 [(match_operand:CC 4 "cc_reg_operand" "y")
5586 (const_int 0)])
5587 (match_operand:SI 2 "gpc_reg_operand" "b")
5588 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5589 "TARGET_ISEL"
5590 "*
5591 { return output_isel (operands); }"
5592 [(set_attr "length" "4")])
5594 (define_insn "isel_unsigned"
5595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5596 (if_then_else:SI
5597 (match_operator 1 "comparison_operator"
5598 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5599 (const_int 0)])
5600 (match_operand:SI 2 "gpc_reg_operand" "b")
5601 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5602 "TARGET_ISEL"
5603 "*
5604 { return output_isel (operands); }"
5605 [(set_attr "length" "4")])
5607 (define_expand "movsfcc"
5608 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5609 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5610 (match_operand:SF 2 "gpc_reg_operand" "")
5611 (match_operand:SF 3 "gpc_reg_operand" "")))]
5612 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5613 "
5614 {
5615 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5616 DONE;
5617 else
5618 FAIL;
5619 }")
5621 (define_insn "*fselsfsf4"
5622 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5623 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5624 (match_operand:SF 4 "zero_fp_constant" "F"))
5625 (match_operand:SF 2 "gpc_reg_operand" "f")
5626 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5627 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5628 "fsel %0,%1,%2,%3"
5629 [(set_attr "type" "fp")])
5631 (define_insn "*fseldfsf4"
5632 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5633 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5634 (match_operand:DF 4 "zero_fp_constant" "F"))
5635 (match_operand:SF 2 "gpc_reg_operand" "f")
5636 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5637 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5638 "fsel %0,%1,%2,%3"
5639 [(set_attr "type" "fp")])
5641 (define_expand "negdf2"
5642 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5643 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5644 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5645 "")
5647 (define_insn "*negdf2_fpr"
5648 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5649 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5650 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5651 "fneg %0,%1"
5652 [(set_attr "type" "fp")])
5654 (define_expand "absdf2"
5655 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5656 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5657 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5658 "")
5660 (define_insn "*absdf2_fpr"
5661 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5662 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5663 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5664 "fabs %0,%1"
5665 [(set_attr "type" "fp")])
5667 (define_insn "*nabsdf2_fpr"
5668 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5669 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5670 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5671 "fnabs %0,%1"
5672 [(set_attr "type" "fp")])
5674 (define_expand "adddf3"
5675 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5676 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5677 (match_operand:DF 2 "gpc_reg_operand" "")))]
5678 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5679 "")
5681 (define_insn "*adddf3_fpr"
5682 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5683 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5684 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5685 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5686 "{fa|fadd} %0,%1,%2"
5687 [(set_attr "type" "fp")
5688 (set_attr "fp_type" "fp_addsub_d")])
5690 (define_expand "subdf3"
5691 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5692 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5693 (match_operand:DF 2 "gpc_reg_operand" "")))]
5694 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5695 "")
5697 (define_insn "*subdf3_fpr"
5698 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5699 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5700 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5701 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5702 "{fs|fsub} %0,%1,%2"
5703 [(set_attr "type" "fp")
5704 (set_attr "fp_type" "fp_addsub_d")])
5706 (define_expand "muldf3"
5707 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5708 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5709 (match_operand:DF 2 "gpc_reg_operand" "")))]
5710 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5711 "")
5713 (define_insn "*muldf3_fpr"
5714 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5715 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5716 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5717 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5718 "{fm|fmul} %0,%1,%2"
5719 [(set_attr "type" "dmul")
5720 (set_attr "fp_type" "fp_mul_d")])
5722 (define_expand "divdf3"
5723 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5724 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5725 (match_operand:DF 2 "gpc_reg_operand" "")))]
5726 "TARGET_HARD_FLOAT
5727 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5728 && !TARGET_SIMPLE_FPU"
5729 "")
5731 (define_insn "*divdf3_fpr"
5732 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5733 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5734 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5735 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
5736 "{fd|fdiv} %0,%1,%2"
5737 [(set_attr "type" "ddiv")])
5739 (define_expand "recipdf3"
5740 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5741 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5742 (match_operand:DF 2 "gpc_reg_operand" "f")]
5743 UNSPEC_FRES))]
5744 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5745 && flag_finite_math_only && !flag_trapping_math"
5746 {
5747 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5748 DONE;
5749 })
5751 (define_insn "fred"
5752 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5753 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5754 "TARGET_POPCNTB && flag_finite_math_only"
5755 "fre %0,%1"
5756 [(set_attr "type" "fp")])
5758 (define_insn ""
5759 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5760 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5761 (match_operand:DF 2 "gpc_reg_operand" "f"))
5762 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5763 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5764 "{fma|fmadd} %0,%1,%2,%3"
5765 [(set_attr "type" "dmul")
5766 (set_attr "fp_type" "fp_maddsub_d")])
5768 (define_insn ""
5769 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5770 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5771 (match_operand:DF 2 "gpc_reg_operand" "f"))
5772 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5773 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5774 "{fms|fmsub} %0,%1,%2,%3"
5775 [(set_attr "type" "dmul")
5776 (set_attr "fp_type" "fp_maddsub_d")])
5778 (define_insn ""
5779 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5780 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5781 (match_operand:DF 2 "gpc_reg_operand" "f"))
5782 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5783 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5784 && HONOR_SIGNED_ZEROS (DFmode)"
5785 "{fnma|fnmadd} %0,%1,%2,%3"
5786 [(set_attr "type" "dmul")
5787 (set_attr "fp_type" "fp_maddsub_d")])
5789 (define_insn ""
5790 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5791 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5792 (match_operand:DF 2 "gpc_reg_operand" "f"))
5793 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5794 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5795 && ! HONOR_SIGNED_ZEROS (DFmode)"
5796 "{fnma|fnmadd} %0,%1,%2,%3"
5797 [(set_attr "type" "dmul")
5798 (set_attr "fp_type" "fp_maddsub_d")])
5800 (define_insn ""
5801 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5802 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5803 (match_operand:DF 2 "gpc_reg_operand" "f"))
5804 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5805 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5806 && HONOR_SIGNED_ZEROS (DFmode)"
5807 "{fnms|fnmsub} %0,%1,%2,%3"
5808 [(set_attr "type" "dmul")
5809 (set_attr "fp_type" "fp_maddsub_d")])
5811 (define_insn ""
5812 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5813 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5814 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5815 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5816 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5817 && ! HONOR_SIGNED_ZEROS (DFmode)"
5818 "{fnms|fnmsub} %0,%1,%2,%3"
5819 [(set_attr "type" "dmul")
5820 (set_attr "fp_type" "fp_maddsub_d")])
5822 (define_insn "sqrtdf2"
5823 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5824 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5825 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
5826 && TARGET_DOUBLE_FLOAT"
5827 "fsqrt %0,%1"
5828 [(set_attr "type" "dsqrt")])
5830 ;; The conditional move instructions allow us to perform max and min
5831 ;; operations even when
5833 (define_expand "smaxdf3"
5834 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5835 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5836 (match_operand:DF 2 "gpc_reg_operand" ""))
5837 (match_dup 1)
5838 (match_dup 2)))]
5839 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5840 && !flag_trapping_math"
5841 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5843 (define_expand "smindf3"
5844 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5845 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5846 (match_operand:DF 2 "gpc_reg_operand" ""))
5847 (match_dup 2)
5848 (match_dup 1)))]
5849 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5850 && !flag_trapping_math"
5851 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5853 (define_split
5854 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5855 (match_operator:DF 3 "min_max_operator"
5856 [(match_operand:DF 1 "gpc_reg_operand" "")
5857 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5858 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5859 && !flag_trapping_math"
5860 [(const_int 0)]
5861 "
5862 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5863 operands[1], operands[2]);
5864 DONE;
5865 }")
5867 (define_expand "movdfcc"
5868 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5869 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5870 (match_operand:DF 2 "gpc_reg_operand" "")
5871 (match_operand:DF 3 "gpc_reg_operand" "")))]
5872 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5873 "
5874 {
5875 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5876 DONE;
5877 else
5878 FAIL;
5879 }")
5881 (define_insn "*fseldfdf4"
5882 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5883 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5884 (match_operand:DF 4 "zero_fp_constant" "F"))
5885 (match_operand:DF 2 "gpc_reg_operand" "f")
5886 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5887 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5888 "fsel %0,%1,%2,%3"
5889 [(set_attr "type" "fp")])
5891 (define_insn "*fselsfdf4"
5892 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5893 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5894 (match_operand:SF 4 "zero_fp_constant" "F"))
5895 (match_operand:DF 2 "gpc_reg_operand" "f")
5896 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5897 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5898 "fsel %0,%1,%2,%3"
5899 [(set_attr "type" "fp")])
5900 \f
5901 ;; Conversions to and from floating-point.
5903 (define_expand "fixuns_truncsfsi2"
5904 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5905 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5906 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5907 "")
5909 (define_expand "fix_truncsfsi2"
5910 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5911 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5912 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5913 "")
5915 ; For each of these conversions, there is a define_expand, a define_insn
5916 ; with a '#' template, and a define_split (with C code). The idea is
5917 ; to allow constant folding with the template of the define_insn,
5918 ; then to have the insns split later (between sched1 and final).
5920 (define_expand "floatsidf2"
5921 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5922 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5923 (use (match_dup 2))
5924 (use (match_dup 3))
5925 (clobber (match_dup 4))
5926 (clobber (match_dup 5))
5927 (clobber (match_dup 6))])]
5928 "TARGET_HARD_FLOAT
5929 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5930 "
5931 {
5932 if (TARGET_E500_DOUBLE)
5933 {
5934 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5935 DONE;
5936 }
5937 if (TARGET_POWERPC64)
5938 {
5939 rtx x = convert_to_mode (DImode, operands[1], 0);
5940 emit_insn (gen_floatdidf2 (operands[0], x));
5941 DONE;
5942 }
5944 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5945 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5946 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5947 operands[5] = gen_reg_rtx (DFmode);
5948 operands[6] = gen_reg_rtx (SImode);
5949 }")
5951 (define_insn_and_split "*floatsidf2_internal"
5952 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5953 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5954 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5955 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5956 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5957 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5958 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5959 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5960 "#"
5961 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5962 [(pc)]
5963 "
5964 {
5965 rtx lowword, highword;
5966 gcc_assert (MEM_P (operands[4]));
5967 highword = adjust_address (operands[4], SImode, 0);
5968 lowword = adjust_address (operands[4], SImode, 4);
5969 if (! WORDS_BIG_ENDIAN)
5970 {
5971 rtx tmp;
5972 tmp = highword; highword = lowword; lowword = tmp;
5973 }
5975 emit_insn (gen_xorsi3 (operands[6], operands[1],
5976 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5977 emit_move_insn (lowword, operands[6]);
5978 emit_move_insn (highword, operands[2]);
5979 emit_move_insn (operands[5], operands[4]);
5980 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5981 DONE;
5982 }"
5983 [(set_attr "length" "24")])
5985 (define_expand "floatunssisf2"
5986 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5987 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5988 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5989 "")
5991 (define_expand "floatunssidf2"
5992 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5993 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5994 (use (match_dup 2))
5995 (use (match_dup 3))
5996 (clobber (match_dup 4))
5997 (clobber (match_dup 5))])]
5998 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5999 "
6000 {
6001 if (TARGET_E500_DOUBLE)
6002 {
6003 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6004 DONE;
6005 }
6006 if (TARGET_POWERPC64)
6007 {
6008 rtx x = convert_to_mode (DImode, operands[1], 1);
6009 emit_insn (gen_floatdidf2 (operands[0], x));
6010 DONE;
6011 }
6013 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6014 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6015 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6016 operands[5] = gen_reg_rtx (DFmode);
6017 }")
6019 (define_insn_and_split "*floatunssidf2_internal"
6020 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
6021 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6022 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6023 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
6024 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6025 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
6026 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6027 "#"
6028 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
6029 [(pc)]
6030 "
6031 {
6032 rtx lowword, highword;
6033 gcc_assert (MEM_P (operands[4]));
6034 highword = adjust_address (operands[4], SImode, 0);
6035 lowword = adjust_address (operands[4], SImode, 4);
6036 if (! WORDS_BIG_ENDIAN)
6037 {
6038 rtx tmp;
6039 tmp = highword; highword = lowword; lowword = tmp;
6040 }
6042 emit_move_insn (lowword, operands[1]);
6043 emit_move_insn (highword, operands[2]);
6044 emit_move_insn (operands[5], operands[4]);
6045 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6046 DONE;
6047 }"
6048 [(set_attr "length" "20")])
6050 (define_expand "fix_truncdfsi2"
6051 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6052 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6053 (clobber (match_dup 2))
6054 (clobber (match_dup 3))])]
6055 "(TARGET_POWER2 || TARGET_POWERPC)
6056 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6057 "
6058 {
6059 if (TARGET_E500_DOUBLE)
6060 {
6061 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6062 DONE;
6063 }
6064 operands[2] = gen_reg_rtx (DImode);
6065 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6066 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6067 {
6068 operands[3] = gen_reg_rtx (DImode);
6069 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6070 operands[2], operands[3]));
6071 DONE;
6072 }
6073 if (TARGET_PPC_GFXOPT)
6074 {
6075 rtx orig_dest = operands[0];
6076 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6077 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6078 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6079 operands[2]));
6080 if (operands[0] != orig_dest)
6081 emit_move_insn (orig_dest, operands[0]);
6082 DONE;
6083 }
6084 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6085 }")
6087 (define_insn_and_split "*fix_truncdfsi2_internal"
6088 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6089 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6090 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6091 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6092 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6093 && TARGET_DOUBLE_FLOAT"
6094 "#"
6095 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
6096 [(pc)]
6097 "
6098 {
6099 rtx lowword;
6100 gcc_assert (MEM_P (operands[3]));
6101 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6103 emit_insn (gen_fctiwz (operands[2], operands[1]));
6104 emit_move_insn (operands[3], operands[2]);
6105 emit_move_insn (operands[0], lowword);
6106 DONE;
6107 }"
6108 [(set_attr "length" "16")])
6110 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6111 [(set (match_operand:SI 0 "memory_operand" "=Z")
6112 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6113 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
6114 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6115 && TARGET_DOUBLE_FLOAT
6116 && TARGET_PPC_GFXOPT"
6117 "#"
6118 "&& 1"
6119 [(pc)]
6120 "
6121 {
6122 emit_insn (gen_fctiwz (operands[2], operands[1]));
6123 emit_insn (gen_stfiwx (operands[0], operands[2]));
6124 DONE;
6125 }"
6126 [(set_attr "length" "16")])
6128 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6129 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6130 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6131 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6132 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6133 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6134 && TARGET_DOUBLE_FLOAT"
6135 "#"
6136 "&& 1"
6137 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6138 (set (match_dup 3) (match_dup 2))
6139 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6140 ""
6141 [(set_attr "length" "12")])
6143 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6144 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6145 ; because the first makes it clear that operand 0 is not live
6146 ; before the instruction.
6147 (define_insn "fctiwz"
6148 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
6149 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6150 UNSPEC_FCTIWZ))]
6151 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6152 && TARGET_DOUBLE_FLOAT"
6153 "{fcirz|fctiwz} %0,%1"
6154 [(set_attr "type" "fp")])
6156 (define_insn "btruncdf2"
6157 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6158 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6159 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6160 "friz %0,%1"
6161 [(set_attr "type" "fp")])
6163 (define_insn "btruncsf2"
6164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6165 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6166 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6167 "friz %0,%1"
6168 [(set_attr "type" "fp")])
6170 (define_insn "ceildf2"
6171 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6172 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6173 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6174 "frip %0,%1"
6175 [(set_attr "type" "fp")])
6177 (define_insn "ceilsf2"
6178 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6179 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6180 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6181 "frip %0,%1"
6182 [(set_attr "type" "fp")])
6184 (define_insn "floordf2"
6185 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6186 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6187 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6188 "frim %0,%1"
6189 [(set_attr "type" "fp")])
6191 (define_insn "floorsf2"
6192 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6193 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6194 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6195 "frim %0,%1"
6196 [(set_attr "type" "fp")])
6198 (define_insn "rounddf2"
6199 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6200 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6201 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6202 "frin %0,%1"
6203 [(set_attr "type" "fp")])
6205 (define_insn "roundsf2"
6206 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6207 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6208 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6209 "frin %0,%1"
6210 [(set_attr "type" "fp")])
6212 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6213 (define_insn "stfiwx"
6214 [(set (match_operand:SI 0 "memory_operand" "=Z")
6215 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6216 UNSPEC_STFIWX))]
6217 "TARGET_PPC_GFXOPT"
6218 "stfiwx %1,%y0"
6219 [(set_attr "type" "fpstore")])
6221 (define_expand "floatsisf2"
6222 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6223 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6224 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6225 "")
6227 (define_insn "floatdidf2"
6228 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6229 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
6230 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6231 "fcfid %0,%1"
6232 [(set_attr "type" "fp")])
6234 (define_insn "fix_truncdfdi2"
6235 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
6236 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6237 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6238 "fctidz %0,%1"
6239 [(set_attr "type" "fp")])
6241 (define_expand "floatdisf2"
6242 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6243 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6244 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6245 "
6246 {
6247 rtx val = operands[1];
6248 if (!flag_unsafe_math_optimizations)
6249 {
6250 rtx label = gen_label_rtx ();
6251 val = gen_reg_rtx (DImode);
6252 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6253 emit_label (label);
6254 }
6255 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6256 DONE;
6257 }")
6259 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6260 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6261 ;; from double rounding.
6262 (define_insn_and_split "floatdisf2_internal1"
6263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6264 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
6265 (clobber (match_scratch:DF 2 "=f"))]
6266 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6267 "#"
6268 "&& reload_completed"
6269 [(set (match_dup 2)
6270 (float:DF (match_dup 1)))
6271 (set (match_dup 0)
6272 (float_truncate:SF (match_dup 2)))]
6273 "")
6275 ;; Twiddles bits to avoid double rounding.
6276 ;; Bits that might be truncated when converting to DFmode are replaced
6277 ;; by a bit that won't be lost at that stage, but is below the SFmode
6278 ;; rounding position.
6279 (define_expand "floatdisf2_internal2"
6280 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6281 (const_int 53)))
6282 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6283 (const_int 2047)))
6284 (clobber (scratch:CC))])
6285 (set (match_dup 3) (plus:DI (match_dup 3)
6286 (const_int 1)))
6287 (set (match_dup 0) (plus:DI (match_dup 0)
6288 (const_int 2047)))
6289 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6290 (const_int 2)))
6291 (set (match_dup 0) (ior:DI (match_dup 0)
6292 (match_dup 1)))
6293 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6294 (const_int -2048)))
6295 (clobber (scratch:CC))])
6296 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6297 (label_ref (match_operand:DI 2 "" ""))
6298 (pc)))
6299 (set (match_dup 0) (match_dup 1))]
6300 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6301 "
6302 {
6303 operands[3] = gen_reg_rtx (DImode);
6304 operands[4] = gen_reg_rtx (CCUNSmode);
6305 }")
6306 \f
6307 ;; Define the DImode operations that can be done in a small number
6308 ;; of instructions. The & constraints are to prevent the register
6309 ;; allocator from allocating registers that overlap with the inputs
6310 ;; (for example, having an input in 7,8 and an output in 6,7). We
6311 ;; also allow for the output being the same as one of the inputs.
6313 (define_insn "*adddi3_noppc64"
6314 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6315 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6316 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6317 "! TARGET_POWERPC64"
6318 "*
6319 {
6320 if (WORDS_BIG_ENDIAN)
6321 return (GET_CODE (operands[2])) != CONST_INT
6322 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6323 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6324 else
6325 return (GET_CODE (operands[2])) != CONST_INT
6326 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6327 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6328 }"
6329 [(set_attr "type" "two")
6330 (set_attr "length" "8")])
6332 (define_insn "*subdi3_noppc64"
6333 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6334 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6335 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6336 "! TARGET_POWERPC64"
6337 "*
6338 {
6339 if (WORDS_BIG_ENDIAN)
6340 return (GET_CODE (operands[1]) != CONST_INT)
6341 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6342 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6343 else
6344 return (GET_CODE (operands[1]) != CONST_INT)
6345 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6346 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6347 }"
6348 [(set_attr "type" "two")
6349 (set_attr "length" "8")])
6351 (define_insn "*negdi2_noppc64"
6352 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6353 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6354 "! TARGET_POWERPC64"
6355 "*
6356 {
6357 return (WORDS_BIG_ENDIAN)
6358 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6359 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6360 }"
6361 [(set_attr "type" "two")
6362 (set_attr "length" "8")])
6364 (define_expand "mulsidi3"
6365 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6366 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6367 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6368 "! TARGET_POWERPC64"
6369 "
6370 {
6371 if (! TARGET_POWER && ! TARGET_POWERPC)
6372 {
6373 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6374 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6375 emit_insn (gen_mull_call ());
6376 if (WORDS_BIG_ENDIAN)
6377 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6378 else
6379 {
6380 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6381 gen_rtx_REG (SImode, 3));
6382 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6383 gen_rtx_REG (SImode, 4));
6384 }
6385 DONE;
6386 }
6387 else if (TARGET_POWER)
6388 {
6389 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6390 DONE;
6391 }
6392 }")
6394 (define_insn "mulsidi3_mq"
6395 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6396 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6397 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6398 (clobber (match_scratch:SI 3 "=q"))]
6399 "TARGET_POWER"
6400 "mul %0,%1,%2\;mfmq %L0"
6401 [(set_attr "type" "imul")
6402 (set_attr "length" "8")])
6404 (define_insn "*mulsidi3_no_mq"
6405 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6406 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6407 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6408 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6409 "*
6410 {
6411 return (WORDS_BIG_ENDIAN)
6412 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6413 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6414 }"
6415 [(set_attr "type" "imul")
6416 (set_attr "length" "8")])
6418 (define_split
6419 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6420 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6421 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6422 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6423 [(set (match_dup 3)
6424 (truncate:SI
6425 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6426 (sign_extend:DI (match_dup 2)))
6427 (const_int 32))))
6428 (set (match_dup 4)
6429 (mult:SI (match_dup 1)
6430 (match_dup 2)))]
6431 "
6432 {
6433 int endian = (WORDS_BIG_ENDIAN == 0);
6434 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6435 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6436 }")
6438 (define_expand "umulsidi3"
6439 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6440 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6441 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6442 "TARGET_POWERPC && ! TARGET_POWERPC64"
6443 "
6444 {
6445 if (TARGET_POWER)
6446 {
6447 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6448 DONE;
6449 }
6450 }")
6452 (define_insn "umulsidi3_mq"
6453 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6454 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6455 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6456 (clobber (match_scratch:SI 3 "=q"))]
6457 "TARGET_POWERPC && TARGET_POWER"
6458 "*
6459 {
6460 return (WORDS_BIG_ENDIAN)
6461 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6462 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6463 }"
6464 [(set_attr "type" "imul")
6465 (set_attr "length" "8")])
6467 (define_insn "*umulsidi3_no_mq"
6468 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6469 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6470 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6471 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6472 "*
6473 {
6474 return (WORDS_BIG_ENDIAN)
6475 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6476 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6477 }"
6478 [(set_attr "type" "imul")
6479 (set_attr "length" "8")])
6481 (define_split
6482 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6483 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6484 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6485 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6486 [(set (match_dup 3)
6487 (truncate:SI
6488 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6489 (zero_extend:DI (match_dup 2)))
6490 (const_int 32))))
6491 (set (match_dup 4)
6492 (mult:SI (match_dup 1)
6493 (match_dup 2)))]
6494 "
6495 {
6496 int endian = (WORDS_BIG_ENDIAN == 0);
6497 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6498 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6499 }")
6501 (define_expand "smulsi3_highpart"
6502 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6503 (truncate:SI
6504 (lshiftrt:DI (mult:DI (sign_extend:DI
6505 (match_operand:SI 1 "gpc_reg_operand" ""))
6506 (sign_extend:DI
6507 (match_operand:SI 2 "gpc_reg_operand" "")))
6508 (const_int 32))))]
6509 ""
6510 "
6511 {
6512 if (! TARGET_POWER && ! TARGET_POWERPC)
6513 {
6514 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6515 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6516 emit_insn (gen_mulh_call ());
6517 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6518 DONE;
6519 }
6520 else if (TARGET_POWER)
6521 {
6522 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6523 DONE;
6524 }
6525 }")
6527 (define_insn "smulsi3_highpart_mq"
6528 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6529 (truncate:SI
6530 (lshiftrt:DI (mult:DI (sign_extend:DI
6531 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6532 (sign_extend:DI
6533 (match_operand:SI 2 "gpc_reg_operand" "r")))
6534 (const_int 32))))
6535 (clobber (match_scratch:SI 3 "=q"))]
6536 "TARGET_POWER"
6537 "mul %0,%1,%2"
6538 [(set_attr "type" "imul")])
6540 (define_insn "*smulsi3_highpart_no_mq"
6541 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6542 (truncate:SI
6543 (lshiftrt:DI (mult:DI (sign_extend:DI
6544 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6545 (sign_extend:DI
6546 (match_operand:SI 2 "gpc_reg_operand" "r")))
6547 (const_int 32))))]
6548 "TARGET_POWERPC && ! TARGET_POWER"
6549 "mulhw %0,%1,%2"
6550 [(set_attr "type" "imul")])
6552 (define_expand "umulsi3_highpart"
6553 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6554 (truncate:SI
6555 (lshiftrt:DI (mult:DI (zero_extend:DI
6556 (match_operand:SI 1 "gpc_reg_operand" ""))
6557 (zero_extend:DI
6558 (match_operand:SI 2 "gpc_reg_operand" "")))
6559 (const_int 32))))]
6560 "TARGET_POWERPC"
6561 "
6562 {
6563 if (TARGET_POWER)
6564 {
6565 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6566 DONE;
6567 }
6568 }")
6570 (define_insn "umulsi3_highpart_mq"
6571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6572 (truncate:SI
6573 (lshiftrt:DI (mult:DI (zero_extend:DI
6574 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6575 (zero_extend:DI
6576 (match_operand:SI 2 "gpc_reg_operand" "r")))
6577 (const_int 32))))
6578 (clobber (match_scratch:SI 3 "=q"))]
6579 "TARGET_POWERPC && TARGET_POWER"
6580 "mulhwu %0,%1,%2"
6581 [(set_attr "type" "imul")])
6583 (define_insn "*umulsi3_highpart_no_mq"
6584 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6585 (truncate:SI
6586 (lshiftrt:DI (mult:DI (zero_extend:DI
6587 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6588 (zero_extend:DI
6589 (match_operand:SI 2 "gpc_reg_operand" "r")))
6590 (const_int 32))))]
6591 "TARGET_POWERPC && ! TARGET_POWER"
6592 "mulhwu %0,%1,%2"
6593 [(set_attr "type" "imul")])
6595 ;; If operands 0 and 2 are in the same register, we have a problem. But
6596 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6597 ;; why we have the strange constraints below.
6598 (define_insn "ashldi3_power"
6599 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6600 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6601 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6602 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6603 "TARGET_POWER"
6604 "@
6605 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6606 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6607 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6608 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6609 [(set_attr "length" "8")])
6611 (define_insn "lshrdi3_power"
6612 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6613 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6614 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6615 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6616 "TARGET_POWER"
6617 "@
6618 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6619 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6620 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6621 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6622 [(set_attr "length" "8")])
6624 ;; Shift by a variable amount is too complex to be worth open-coding. We
6625 ;; just handle shifts by constants.
6626 (define_insn "ashrdi3_power"
6627 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6628 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6629 (match_operand:SI 2 "const_int_operand" "M,i")))
6630 (clobber (match_scratch:SI 3 "=X,q"))]
6631 "TARGET_POWER"
6632 "@
6633 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6634 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6635 [(set_attr "type" "shift")
6636 (set_attr "length" "8")])
6638 (define_insn "ashrdi3_no_power"
6639 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6640 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6641 (match_operand:SI 2 "const_int_operand" "M,i")))]
6642 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6643 "@
6644 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6645 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6646 [(set_attr "type" "two,three")
6647 (set_attr "length" "8,12")])
6649 (define_insn "*ashrdisi3_noppc64"
6650 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6651 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6652 (const_int 32)) 4))]
6653 "TARGET_32BIT && !TARGET_POWERPC64"
6654 "*
6655 {
6656 if (REGNO (operands[0]) == REGNO (operands[1]))
6657 return \"\";
6658 else
6659 return \"mr %0,%1\";
6660 }"
6661 [(set_attr "length" "4")])
6663 \f
6664 ;; PowerPC64 DImode operations.
6666 (define_insn_and_split "absdi2"
6667 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6668 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6669 (clobber (match_scratch:DI 2 "=&r,&r"))]
6670 "TARGET_POWERPC64"
6671 "#"
6672 "&& reload_completed"
6673 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6674 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6675 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6676 "")
6678 (define_insn_and_split "*nabsdi2"
6679 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6680 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6681 (clobber (match_scratch:DI 2 "=&r,&r"))]
6682 "TARGET_POWERPC64"
6683 "#"
6684 "&& reload_completed"
6685 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6686 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6687 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6688 "")
6690 (define_insn "muldi3"
6691 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6692 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6693 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6694 "TARGET_POWERPC64"
6695 "@
6696 mulld %0,%1,%2
6697 mulli %0,%1,%2"
6698 [(set (attr "type")
6699 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6700 (const_string "imul3")
6701 (match_operand:SI 2 "short_cint_operand" "")
6702 (const_string "imul2")]
6703 (const_string "lmul")))])
6705 (define_insn "*muldi3_internal1"
6706 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6707 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6708 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6709 (const_int 0)))
6710 (clobber (match_scratch:DI 3 "=r,r"))]
6711 "TARGET_POWERPC64"
6712 "@
6713 mulld. %3,%1,%2
6714 #"
6715 [(set_attr "type" "lmul_compare")
6716 (set_attr "length" "4,8")])
6718 (define_split
6719 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6720 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6721 (match_operand:DI 2 "gpc_reg_operand" ""))
6722 (const_int 0)))
6723 (clobber (match_scratch:DI 3 ""))]
6724 "TARGET_POWERPC64 && reload_completed"
6725 [(set (match_dup 3)
6726 (mult:DI (match_dup 1) (match_dup 2)))
6727 (set (match_dup 0)
6728 (compare:CC (match_dup 3)
6729 (const_int 0)))]
6730 "")
6732 (define_insn "*muldi3_internal2"
6733 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6734 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6735 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6736 (const_int 0)))
6737 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6738 (mult:DI (match_dup 1) (match_dup 2)))]
6739 "TARGET_POWERPC64"
6740 "@
6741 mulld. %0,%1,%2
6742 #"
6743 [(set_attr "type" "lmul_compare")
6744 (set_attr "length" "4,8")])
6746 (define_split
6747 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6748 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6749 (match_operand:DI 2 "gpc_reg_operand" ""))
6750 (const_int 0)))
6751 (set (match_operand:DI 0 "gpc_reg_operand" "")
6752 (mult:DI (match_dup 1) (match_dup 2)))]
6753 "TARGET_POWERPC64 && reload_completed"
6754 [(set (match_dup 0)
6755 (mult:DI (match_dup 1) (match_dup 2)))
6756 (set (match_dup 3)
6757 (compare:CC (match_dup 0)
6758 (const_int 0)))]
6759 "")
6761 (define_insn "smuldi3_highpart"
6762 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6763 (truncate:DI
6764 (lshiftrt:TI (mult:TI (sign_extend:TI
6765 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6766 (sign_extend:TI
6767 (match_operand:DI 2 "gpc_reg_operand" "r")))
6768 (const_int 64))))]
6769 "TARGET_POWERPC64"
6770 "mulhd %0,%1,%2"
6771 [(set_attr "type" "lmul")])
6773 (define_insn "umuldi3_highpart"
6774 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6775 (truncate:DI
6776 (lshiftrt:TI (mult:TI (zero_extend:TI
6777 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6778 (zero_extend:TI
6779 (match_operand:DI 2 "gpc_reg_operand" "r")))
6780 (const_int 64))))]
6781 "TARGET_POWERPC64"
6782 "mulhdu %0,%1,%2"
6783 [(set_attr "type" "lmul")])
6785 (define_insn "rotldi3"
6786 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6787 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6788 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6789 "TARGET_POWERPC64"
6790 "@
6791 rldcl %0,%1,%2,0
6792 rldicl %0,%1,%H2,0"
6793 [(set_attr "type" "var_shift_rotate,integer")])
6795 (define_insn "*rotldi3_internal2"
6796 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6797 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6798 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6799 (const_int 0)))
6800 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6801 "TARGET_64BIT"
6802 "@
6803 rldcl. %3,%1,%2,0
6804 rldicl. %3,%1,%H2,0
6805 #
6806 #"
6807 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6808 (set_attr "length" "4,4,8,8")])
6810 (define_split
6811 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6812 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6813 (match_operand:DI 2 "reg_or_cint_operand" ""))
6814 (const_int 0)))
6815 (clobber (match_scratch:DI 3 ""))]
6816 "TARGET_POWERPC64 && reload_completed"
6817 [(set (match_dup 3)
6818 (rotate:DI (match_dup 1) (match_dup 2)))
6819 (set (match_dup 0)
6820 (compare:CC (match_dup 3)
6821 (const_int 0)))]
6822 "")
6824 (define_insn "*rotldi3_internal3"
6825 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6826 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6827 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6828 (const_int 0)))
6829 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6830 (rotate:DI (match_dup 1) (match_dup 2)))]
6831 "TARGET_64BIT"
6832 "@
6833 rldcl. %0,%1,%2,0
6834 rldicl. %0,%1,%H2,0
6835 #
6836 #"
6837 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6838 (set_attr "length" "4,4,8,8")])
6840 (define_split
6841 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6842 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6843 (match_operand:DI 2 "reg_or_cint_operand" ""))
6844 (const_int 0)))
6845 (set (match_operand:DI 0 "gpc_reg_operand" "")
6846 (rotate:DI (match_dup 1) (match_dup 2)))]
6847 "TARGET_POWERPC64 && reload_completed"
6848 [(set (match_dup 0)
6849 (rotate:DI (match_dup 1) (match_dup 2)))
6850 (set (match_dup 3)
6851 (compare:CC (match_dup 0)
6852 (const_int 0)))]
6853 "")
6855 (define_insn "*rotldi3_internal4"
6856 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6857 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6858 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6859 (match_operand:DI 3 "mask64_operand" "n,n")))]
6860 "TARGET_POWERPC64"
6861 "@
6862 rldc%B3 %0,%1,%2,%S3
6863 rldic%B3 %0,%1,%H2,%S3"
6864 [(set_attr "type" "var_shift_rotate,integer")])
6866 (define_insn "*rotldi3_internal5"
6867 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6868 (compare:CC (and:DI
6869 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6870 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6871 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6872 (const_int 0)))
6873 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6874 "TARGET_64BIT"
6875 "@
6876 rldc%B3. %4,%1,%2,%S3
6877 rldic%B3. %4,%1,%H2,%S3
6878 #
6879 #"
6880 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6881 (set_attr "length" "4,4,8,8")])
6883 (define_split
6884 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6885 (compare:CC (and:DI
6886 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6887 (match_operand:DI 2 "reg_or_cint_operand" ""))
6888 (match_operand:DI 3 "mask64_operand" ""))
6889 (const_int 0)))
6890 (clobber (match_scratch:DI 4 ""))]
6891 "TARGET_POWERPC64 && reload_completed"
6892 [(set (match_dup 4)
6893 (and:DI (rotate:DI (match_dup 1)
6894 (match_dup 2))
6895 (match_dup 3)))
6896 (set (match_dup 0)
6897 (compare:CC (match_dup 4)
6898 (const_int 0)))]
6899 "")
6901 (define_insn "*rotldi3_internal6"
6902 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6903 (compare:CC (and:DI
6904 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6905 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6906 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6907 (const_int 0)))
6908 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6909 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6910 "TARGET_64BIT"
6911 "@
6912 rldc%B3. %0,%1,%2,%S3
6913 rldic%B3. %0,%1,%H2,%S3
6914 #
6915 #"
6916 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6917 (set_attr "length" "4,4,8,8")])
6919 (define_split
6920 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6921 (compare:CC (and:DI
6922 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6923 (match_operand:DI 2 "reg_or_cint_operand" ""))
6924 (match_operand:DI 3 "mask64_operand" ""))
6925 (const_int 0)))
6926 (set (match_operand:DI 0 "gpc_reg_operand" "")
6927 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6928 "TARGET_POWERPC64 && reload_completed"
6929 [(set (match_dup 0)
6930 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6931 (set (match_dup 4)
6932 (compare:CC (match_dup 0)
6933 (const_int 0)))]
6934 "")
6936 (define_insn "*rotldi3_internal7"
6937 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6938 (zero_extend:DI
6939 (subreg:QI
6940 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6941 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6942 "TARGET_POWERPC64"
6943 "@
6944 rldcl %0,%1,%2,56
6945 rldicl %0,%1,%H2,56"
6946 [(set_attr "type" "var_shift_rotate,integer")])
6948 (define_insn "*rotldi3_internal8"
6949 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6950 (compare:CC (zero_extend:DI
6951 (subreg:QI
6952 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6953 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6954 (const_int 0)))
6955 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6956 "TARGET_64BIT"
6957 "@
6958 rldcl. %3,%1,%2,56
6959 rldicl. %3,%1,%H2,56
6960 #
6961 #"
6962 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6963 (set_attr "length" "4,4,8,8")])
6965 (define_split
6966 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6967 (compare:CC (zero_extend:DI
6968 (subreg:QI
6969 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6970 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6971 (const_int 0)))
6972 (clobber (match_scratch:DI 3 ""))]
6973 "TARGET_POWERPC64 && reload_completed"
6974 [(set (match_dup 3)
6975 (zero_extend:DI (subreg:QI
6976 (rotate:DI (match_dup 1)
6977 (match_dup 2)) 0)))
6978 (set (match_dup 0)
6979 (compare:CC (match_dup 3)
6980 (const_int 0)))]
6981 "")
6983 (define_insn "*rotldi3_internal9"
6984 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6985 (compare:CC (zero_extend:DI
6986 (subreg:QI
6987 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6988 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6989 (const_int 0)))
6990 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6991 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6992 "TARGET_64BIT"
6993 "@
6994 rldcl. %0,%1,%2,56
6995 rldicl. %0,%1,%H2,56
6996 #
6997 #"
6998 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6999 (set_attr "length" "4,4,8,8")])
7001 (define_split
7002 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7003 (compare:CC (zero_extend:DI
7004 (subreg:QI
7005 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7006 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7007 (const_int 0)))
7008 (set (match_operand:DI 0 "gpc_reg_operand" "")
7009 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7010 "TARGET_POWERPC64 && reload_completed"
7011 [(set (match_dup 0)
7012 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7013 (set (match_dup 3)
7014 (compare:CC (match_dup 0)
7015 (const_int 0)))]
7016 "")
7018 (define_insn "*rotldi3_internal10"
7019 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7020 (zero_extend:DI
7021 (subreg:HI
7022 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7023 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7024 "TARGET_POWERPC64"
7025 "@
7026 rldcl %0,%1,%2,48
7027 rldicl %0,%1,%H2,48"
7028 [(set_attr "type" "var_shift_rotate,integer")])
7030 (define_insn "*rotldi3_internal11"
7031 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7032 (compare:CC (zero_extend:DI
7033 (subreg:HI
7034 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7035 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7036 (const_int 0)))
7037 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7038 "TARGET_64BIT"
7039 "@
7040 rldcl. %3,%1,%2,48
7041 rldicl. %3,%1,%H2,48
7042 #
7043 #"
7044 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7045 (set_attr "length" "4,4,8,8")])
7047 (define_split
7048 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7049 (compare:CC (zero_extend:DI
7050 (subreg:HI
7051 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7052 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7053 (const_int 0)))
7054 (clobber (match_scratch:DI 3 ""))]
7055 "TARGET_POWERPC64 && reload_completed"
7056 [(set (match_dup 3)
7057 (zero_extend:DI (subreg:HI
7058 (rotate:DI (match_dup 1)
7059 (match_dup 2)) 0)))
7060 (set (match_dup 0)
7061 (compare:CC (match_dup 3)
7062 (const_int 0)))]
7063 "")
7065 (define_insn "*rotldi3_internal12"
7066 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7067 (compare:CC (zero_extend:DI
7068 (subreg:HI
7069 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7070 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7071 (const_int 0)))
7072 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7073 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7074 "TARGET_64BIT"
7075 "@
7076 rldcl. %0,%1,%2,48
7077 rldicl. %0,%1,%H2,48
7078 #
7079 #"
7080 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7081 (set_attr "length" "4,4,8,8")])
7083 (define_split
7084 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7085 (compare:CC (zero_extend:DI
7086 (subreg:HI
7087 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7088 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7089 (const_int 0)))
7090 (set (match_operand:DI 0 "gpc_reg_operand" "")
7091 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7092 "TARGET_POWERPC64 && reload_completed"
7093 [(set (match_dup 0)
7094 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7095 (set (match_dup 3)
7096 (compare:CC (match_dup 0)
7097 (const_int 0)))]
7098 "")
7100 (define_insn "*rotldi3_internal13"
7101 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7102 (zero_extend:DI
7103 (subreg:SI
7104 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7105 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7106 "TARGET_POWERPC64"
7107 "@
7108 rldcl %0,%1,%2,32
7109 rldicl %0,%1,%H2,32"
7110 [(set_attr "type" "var_shift_rotate,integer")])
7112 (define_insn "*rotldi3_internal14"
7113 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7114 (compare:CC (zero_extend:DI
7115 (subreg:SI
7116 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7117 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7118 (const_int 0)))
7119 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7120 "TARGET_64BIT"
7121 "@
7122 rldcl. %3,%1,%2,32
7123 rldicl. %3,%1,%H2,32
7124 #
7125 #"
7126 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7127 (set_attr "length" "4,4,8,8")])
7129 (define_split
7130 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7131 (compare:CC (zero_extend:DI
7132 (subreg:SI
7133 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7134 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7135 (const_int 0)))
7136 (clobber (match_scratch:DI 3 ""))]
7137 "TARGET_POWERPC64 && reload_completed"
7138 [(set (match_dup 3)
7139 (zero_extend:DI (subreg:SI
7140 (rotate:DI (match_dup 1)
7141 (match_dup 2)) 0)))
7142 (set (match_dup 0)
7143 (compare:CC (match_dup 3)
7144 (const_int 0)))]
7145 "")
7147 (define_insn "*rotldi3_internal15"
7148 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7149 (compare:CC (zero_extend:DI
7150 (subreg:SI
7151 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7152 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7153 (const_int 0)))
7154 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7155 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7156 "TARGET_64BIT"
7157 "@
7158 rldcl. %0,%1,%2,32
7159 rldicl. %0,%1,%H2,32
7160 #
7161 #"
7162 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7163 (set_attr "length" "4,4,8,8")])
7165 (define_split
7166 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7167 (compare:CC (zero_extend:DI
7168 (subreg:SI
7169 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7170 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7171 (const_int 0)))
7172 (set (match_operand:DI 0 "gpc_reg_operand" "")
7173 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7174 "TARGET_POWERPC64 && reload_completed"
7175 [(set (match_dup 0)
7176 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7177 (set (match_dup 3)
7178 (compare:CC (match_dup 0)
7179 (const_int 0)))]
7180 "")
7182 (define_expand "ashldi3"
7183 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7184 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7185 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7186 "TARGET_POWERPC64 || TARGET_POWER"
7187 "
7188 {
7189 if (TARGET_POWERPC64)
7190 ;
7191 else if (TARGET_POWER)
7192 {
7193 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7194 DONE;
7195 }
7196 else
7197 FAIL;
7198 }")
7200 (define_insn "*ashldi3_internal1"
7201 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7202 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7203 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7204 "TARGET_POWERPC64"
7205 "@
7206 sld %0,%1,%2
7207 sldi %0,%1,%H2"
7208 [(set_attr "type" "var_shift_rotate,shift")])
7210 (define_insn "*ashldi3_internal2"
7211 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7212 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7213 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7214 (const_int 0)))
7215 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7216 "TARGET_64BIT"
7217 "@
7218 sld. %3,%1,%2
7219 sldi. %3,%1,%H2
7220 #
7221 #"
7222 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7223 (set_attr "length" "4,4,8,8")])
7225 (define_split
7226 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7227 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7228 (match_operand:SI 2 "reg_or_cint_operand" ""))
7229 (const_int 0)))
7230 (clobber (match_scratch:DI 3 ""))]
7231 "TARGET_POWERPC64 && reload_completed"
7232 [(set (match_dup 3)
7233 (ashift:DI (match_dup 1) (match_dup 2)))
7234 (set (match_dup 0)
7235 (compare:CC (match_dup 3)
7236 (const_int 0)))]
7237 "")
7239 (define_insn "*ashldi3_internal3"
7240 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7241 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7242 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7243 (const_int 0)))
7244 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7245 (ashift:DI (match_dup 1) (match_dup 2)))]
7246 "TARGET_64BIT"
7247 "@
7248 sld. %0,%1,%2
7249 sldi. %0,%1,%H2
7250 #
7251 #"
7252 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7253 (set_attr "length" "4,4,8,8")])
7255 (define_split
7256 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7257 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7258 (match_operand:SI 2 "reg_or_cint_operand" ""))
7259 (const_int 0)))
7260 (set (match_operand:DI 0 "gpc_reg_operand" "")
7261 (ashift:DI (match_dup 1) (match_dup 2)))]
7262 "TARGET_POWERPC64 && reload_completed"
7263 [(set (match_dup 0)
7264 (ashift:DI (match_dup 1) (match_dup 2)))
7265 (set (match_dup 3)
7266 (compare:CC (match_dup 0)
7267 (const_int 0)))]
7268 "")
7270 (define_insn "*ashldi3_internal4"
7271 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7272 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7273 (match_operand:SI 2 "const_int_operand" "i"))
7274 (match_operand:DI 3 "const_int_operand" "n")))]
7275 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7276 "rldic %0,%1,%H2,%W3")
7278 (define_insn "ashldi3_internal5"
7279 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7280 (compare:CC
7281 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7282 (match_operand:SI 2 "const_int_operand" "i,i"))
7283 (match_operand:DI 3 "const_int_operand" "n,n"))
7284 (const_int 0)))
7285 (clobber (match_scratch:DI 4 "=r,r"))]
7286 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7287 "@
7288 rldic. %4,%1,%H2,%W3
7289 #"
7290 [(set_attr "type" "compare")
7291 (set_attr "length" "4,8")])
7293 (define_split
7294 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7295 (compare:CC
7296 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7297 (match_operand:SI 2 "const_int_operand" ""))
7298 (match_operand:DI 3 "const_int_operand" ""))
7299 (const_int 0)))
7300 (clobber (match_scratch:DI 4 ""))]
7301 "TARGET_POWERPC64 && reload_completed
7302 && includes_rldic_lshift_p (operands[2], operands[3])"
7303 [(set (match_dup 4)
7304 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7305 (match_dup 3)))
7306 (set (match_dup 0)
7307 (compare:CC (match_dup 4)
7308 (const_int 0)))]
7309 "")
7311 (define_insn "*ashldi3_internal6"
7312 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7313 (compare:CC
7314 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7315 (match_operand:SI 2 "const_int_operand" "i,i"))
7316 (match_operand:DI 3 "const_int_operand" "n,n"))
7317 (const_int 0)))
7318 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7319 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7320 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7321 "@
7322 rldic. %0,%1,%H2,%W3
7323 #"
7324 [(set_attr "type" "compare")
7325 (set_attr "length" "4,8")])
7327 (define_split
7328 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7329 (compare:CC
7330 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7331 (match_operand:SI 2 "const_int_operand" ""))
7332 (match_operand:DI 3 "const_int_operand" ""))
7333 (const_int 0)))
7334 (set (match_operand:DI 0 "gpc_reg_operand" "")
7335 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7336 "TARGET_POWERPC64 && reload_completed
7337 && includes_rldic_lshift_p (operands[2], operands[3])"
7338 [(set (match_dup 0)
7339 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7340 (match_dup 3)))
7341 (set (match_dup 4)
7342 (compare:CC (match_dup 0)
7343 (const_int 0)))]
7344 "")
7346 (define_insn "*ashldi3_internal7"
7347 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7348 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7349 (match_operand:SI 2 "const_int_operand" "i"))
7350 (match_operand:DI 3 "mask64_operand" "n")))]
7351 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7352 "rldicr %0,%1,%H2,%S3")
7354 (define_insn "ashldi3_internal8"
7355 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7356 (compare:CC
7357 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7358 (match_operand:SI 2 "const_int_operand" "i,i"))
7359 (match_operand:DI 3 "mask64_operand" "n,n"))
7360 (const_int 0)))
7361 (clobber (match_scratch:DI 4 "=r,r"))]
7362 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7363 "@
7364 rldicr. %4,%1,%H2,%S3
7365 #"
7366 [(set_attr "type" "compare")
7367 (set_attr "length" "4,8")])
7369 (define_split
7370 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7371 (compare:CC
7372 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7373 (match_operand:SI 2 "const_int_operand" ""))
7374 (match_operand:DI 3 "mask64_operand" ""))
7375 (const_int 0)))
7376 (clobber (match_scratch:DI 4 ""))]
7377 "TARGET_POWERPC64 && reload_completed
7378 && includes_rldicr_lshift_p (operands[2], operands[3])"
7379 [(set (match_dup 4)
7380 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7381 (match_dup 3)))
7382 (set (match_dup 0)
7383 (compare:CC (match_dup 4)
7384 (const_int 0)))]
7385 "")
7387 (define_insn "*ashldi3_internal9"
7388 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7389 (compare:CC
7390 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7391 (match_operand:SI 2 "const_int_operand" "i,i"))
7392 (match_operand:DI 3 "mask64_operand" "n,n"))
7393 (const_int 0)))
7394 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7395 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7396 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7397 "@
7398 rldicr. %0,%1,%H2,%S3
7399 #"
7400 [(set_attr "type" "compare")
7401 (set_attr "length" "4,8")])
7403 (define_split
7404 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7405 (compare:CC
7406 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7407 (match_operand:SI 2 "const_int_operand" ""))
7408 (match_operand:DI 3 "mask64_operand" ""))
7409 (const_int 0)))
7410 (set (match_operand:DI 0 "gpc_reg_operand" "")
7411 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7412 "TARGET_POWERPC64 && reload_completed
7413 && includes_rldicr_lshift_p (operands[2], operands[3])"
7414 [(set (match_dup 0)
7415 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7416 (match_dup 3)))
7417 (set (match_dup 4)
7418 (compare:CC (match_dup 0)
7419 (const_int 0)))]
7420 "")
7422 (define_expand "lshrdi3"
7423 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7424 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7425 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7426 "TARGET_POWERPC64 || TARGET_POWER"
7427 "
7428 {
7429 if (TARGET_POWERPC64)
7430 ;
7431 else if (TARGET_POWER)
7432 {
7433 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7434 DONE;
7435 }
7436 else
7437 FAIL;
7438 }")
7440 (define_insn "*lshrdi3_internal1"
7441 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7442 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7443 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7444 "TARGET_POWERPC64"
7445 "@
7446 srd %0,%1,%2
7447 srdi %0,%1,%H2"
7448 [(set_attr "type" "var_shift_rotate,shift")])
7450 (define_insn "*lshrdi3_internal2"
7451 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7452 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7453 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7454 (const_int 0)))
7455 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7456 "TARGET_64BIT "
7457 "@
7458 srd. %3,%1,%2
7459 srdi. %3,%1,%H2
7460 #
7461 #"
7462 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7463 (set_attr "length" "4,4,8,8")])
7465 (define_split
7466 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7467 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7468 (match_operand:SI 2 "reg_or_cint_operand" ""))
7469 (const_int 0)))
7470 (clobber (match_scratch:DI 3 ""))]
7471 "TARGET_POWERPC64 && reload_completed"
7472 [(set (match_dup 3)
7473 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7474 (set (match_dup 0)
7475 (compare:CC (match_dup 3)
7476 (const_int 0)))]
7477 "")
7479 (define_insn "*lshrdi3_internal3"
7480 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7481 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7482 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7483 (const_int 0)))
7484 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7485 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7486 "TARGET_64BIT"
7487 "@
7488 srd. %0,%1,%2
7489 srdi. %0,%1,%H2
7490 #
7491 #"
7492 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7493 (set_attr "length" "4,4,8,8")])
7495 (define_split
7496 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7497 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7498 (match_operand:SI 2 "reg_or_cint_operand" ""))
7499 (const_int 0)))
7500 (set (match_operand:DI 0 "gpc_reg_operand" "")
7501 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7502 "TARGET_POWERPC64 && reload_completed"
7503 [(set (match_dup 0)
7504 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7505 (set (match_dup 3)
7506 (compare:CC (match_dup 0)
7507 (const_int 0)))]
7508 "")
7510 (define_expand "ashrdi3"
7511 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7512 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7513 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7514 "WORDS_BIG_ENDIAN"
7515 "
7516 {
7517 if (TARGET_POWERPC64)
7518 ;
7519 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7520 {
7521 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7522 DONE;
7523 }
7524 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7525 && WORDS_BIG_ENDIAN)
7526 {
7527 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7528 DONE;
7529 }
7530 else
7531 FAIL;
7532 }")
7534 (define_insn "*ashrdi3_internal1"
7535 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7536 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7537 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7538 "TARGET_POWERPC64"
7539 "@
7540 srad %0,%1,%2
7541 sradi %0,%1,%H2"
7542 [(set_attr "type" "var_shift_rotate,shift")])
7544 (define_insn "*ashrdi3_internal2"
7545 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7546 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7547 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7548 (const_int 0)))
7549 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7550 "TARGET_64BIT"
7551 "@
7552 srad. %3,%1,%2
7553 sradi. %3,%1,%H2
7554 #
7555 #"
7556 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7557 (set_attr "length" "4,4,8,8")])
7559 (define_split
7560 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7561 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7562 (match_operand:SI 2 "reg_or_cint_operand" ""))
7563 (const_int 0)))
7564 (clobber (match_scratch:DI 3 ""))]
7565 "TARGET_POWERPC64 && reload_completed"
7566 [(set (match_dup 3)
7567 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7568 (set (match_dup 0)
7569 (compare:CC (match_dup 3)
7570 (const_int 0)))]
7571 "")
7573 (define_insn "*ashrdi3_internal3"
7574 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7575 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7576 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7577 (const_int 0)))
7578 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7579 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7580 "TARGET_64BIT"
7581 "@
7582 srad. %0,%1,%2
7583 sradi. %0,%1,%H2
7584 #
7585 #"
7586 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7587 (set_attr "length" "4,4,8,8")])
7589 (define_split
7590 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7591 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7592 (match_operand:SI 2 "reg_or_cint_operand" ""))
7593 (const_int 0)))
7594 (set (match_operand:DI 0 "gpc_reg_operand" "")
7595 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7596 "TARGET_POWERPC64 && reload_completed"
7597 [(set (match_dup 0)
7598 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7599 (set (match_dup 3)
7600 (compare:CC (match_dup 0)
7601 (const_int 0)))]
7602 "")
7604 (define_expand "anddi3"
7605 [(parallel
7606 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7607 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7608 (match_operand:DI 2 "and64_2_operand" "")))
7609 (clobber (match_scratch:CC 3 ""))])]
7610 "TARGET_POWERPC64"
7611 "")
7613 (define_insn "anddi3_mc"
7614 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7615 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7616 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7617 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7618 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7619 "@
7620 and %0,%1,%2
7621 rldic%B2 %0,%1,0,%S2
7622 rlwinm %0,%1,0,%m2,%M2
7623 andi. %0,%1,%b2
7624 andis. %0,%1,%u2
7625 #"
7626 [(set_attr "type" "*,*,*,compare,compare,*")
7627 (set_attr "length" "4,4,4,4,4,8")])
7629 (define_insn "anddi3_nomc"
7630 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7631 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7632 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7633 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7634 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7635 "@
7636 and %0,%1,%2
7637 rldic%B2 %0,%1,0,%S2
7638 rlwinm %0,%1,0,%m2,%M2
7639 #"
7640 [(set_attr "length" "4,4,4,8")])
7642 (define_split
7643 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7644 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7645 (match_operand:DI 2 "mask64_2_operand" "")))
7646 (clobber (match_scratch:CC 3 ""))]
7647 "TARGET_POWERPC64
7648 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7649 && !mask_operand (operands[2], DImode)
7650 && !mask64_operand (operands[2], DImode)"
7651 [(set (match_dup 0)
7652 (and:DI (rotate:DI (match_dup 1)
7653 (match_dup 4))
7654 (match_dup 5)))
7655 (set (match_dup 0)
7656 (and:DI (rotate:DI (match_dup 0)
7657 (match_dup 6))
7658 (match_dup 7)))]
7659 {
7660 build_mask64_2_operands (operands[2], &operands[4]);
7661 })
7663 (define_insn "*anddi3_internal2_mc"
7664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7665 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7666 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7667 (const_int 0)))
7668 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7669 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7670 "TARGET_64BIT && rs6000_gen_cell_microcode"
7671 "@
7672 and. %3,%1,%2
7673 rldic%B2. %3,%1,0,%S2
7674 rlwinm. %3,%1,0,%m2,%M2
7675 andi. %3,%1,%b2
7676 andis. %3,%1,%u2
7677 #
7678 #
7679 #
7680 #
7681 #
7682 #
7683 #"
7684 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7685 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7687 (define_insn "*anddi3_internal2_nomc"
7688 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y,?y,??y,??y,?y")
7689 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7690 (match_operand:DI 2 "and64_2_operand" "t,r,S,K,J,t"))
7691 (const_int 0)))
7692 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r"))
7693 (clobber (match_scratch:CC 4 "=X,X,X,x,x,X"))]
7694 "TARGET_64BIT && !rs6000_gen_cell_microcode"
7695 "#"
7696 [(set_attr "type" "delayed_compare,compare,compare,compare,compare,compare")
7697 (set_attr "length" "8,8,8,8,8,12")])
7699 (define_split
7700 [(set (match_operand:CC 0 "cc_reg_operand" "")
7701 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7702 (match_operand:DI 2 "mask64_2_operand" ""))
7703 (const_int 0)))
7704 (clobber (match_scratch:DI 3 ""))
7705 (clobber (match_scratch:CC 4 ""))]
7706 "TARGET_64BIT && reload_completed
7707 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7708 && !mask_operand (operands[2], DImode)
7709 && !mask64_operand (operands[2], DImode)"
7710 [(set (match_dup 3)
7711 (and:DI (rotate:DI (match_dup 1)
7712 (match_dup 5))
7713 (match_dup 6)))
7714 (parallel [(set (match_dup 0)
7715 (compare:CC (and:DI (rotate:DI (match_dup 3)
7716 (match_dup 7))
7717 (match_dup 8))
7718 (const_int 0)))
7719 (clobber (match_dup 3))])]
7720 "
7721 {
7722 build_mask64_2_operands (operands[2], &operands[5]);
7723 }")
7725 (define_insn "*anddi3_internal3_mc"
7726 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7727 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7728 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7729 (const_int 0)))
7730 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7731 (and:DI (match_dup 1) (match_dup 2)))
7732 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7733 "TARGET_64BIT && rs6000_gen_cell_microcode"
7734 "@
7735 and. %0,%1,%2
7736 rldic%B2. %0,%1,0,%S2
7737 rlwinm. %0,%1,0,%m2,%M2
7738 andi. %0,%1,%b2
7739 andis. %0,%1,%u2
7740 #
7741 #
7742 #
7743 #
7744 #
7745 #
7746 #"
7747 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7748 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7750 (define_insn "*anddi3_internal3_nomc"
7751 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y,?y,??y,??y,?y")
7752 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7753 (match_operand:DI 2 "and64_2_operand" "t,r,S,K,J,t"))
7754 (const_int 0)))
7755 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7756 (and:DI (match_dup 1) (match_dup 2)))
7757 (clobber (match_scratch:CC 4 "=X,X,X,x,x,X"))]
7758 "TARGET_64BIT && !rs6000_gen_cell_microcode"
7759 "#"
7760 [(set_attr "type" "delayed_compare,compare,compare,compare,compare,compare")
7761 (set_attr "length" "8,8,8,8,8,12")])
7762 (define_split
7763 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7764 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7765 (match_operand:DI 2 "and64_2_operand" ""))
7766 (const_int 0)))
7767 (set (match_operand:DI 0 "gpc_reg_operand" "")
7768 (and:DI (match_dup 1) (match_dup 2)))
7769 (clobber (match_scratch:CC 4 ""))]
7770 "TARGET_64BIT && reload_completed"
7771 [(parallel [(set (match_dup 0)
7772 (and:DI (match_dup 1) (match_dup 2)))
7773 (clobber (match_dup 4))])
7774 (set (match_dup 3)
7775 (compare:CC (match_dup 0)
7776 (const_int 0)))]
7777 "")
7779 (define_split
7780 [(set (match_operand:CC 3 "cc_reg_operand" "")
7781 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7782 (match_operand:DI 2 "mask64_2_operand" ""))
7783 (const_int 0)))
7784 (set (match_operand:DI 0 "gpc_reg_operand" "")
7785 (and:DI (match_dup 1) (match_dup 2)))
7786 (clobber (match_scratch:CC 4 ""))]
7787 "TARGET_64BIT && reload_completed
7788 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7789 && !mask_operand (operands[2], DImode)
7790 && !mask64_operand (operands[2], DImode)"
7791 [(set (match_dup 0)
7792 (and:DI (rotate:DI (match_dup 1)
7793 (match_dup 5))
7794 (match_dup 6)))
7795 (parallel [(set (match_dup 3)
7796 (compare:CC (and:DI (rotate:DI (match_dup 0)
7797 (match_dup 7))
7798 (match_dup 8))
7799 (const_int 0)))
7800 (set (match_dup 0)
7801 (and:DI (rotate:DI (match_dup 0)
7802 (match_dup 7))
7803 (match_dup 8)))])]
7804 "
7805 {
7806 build_mask64_2_operands (operands[2], &operands[5]);
7807 }")
7809 (define_expand "iordi3"
7810 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7811 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7812 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7813 "TARGET_POWERPC64"
7814 "
7815 {
7816 if (non_logical_cint_operand (operands[2], DImode))
7817 {
7818 HOST_WIDE_INT value;
7819 rtx tmp = ((!can_create_pseudo_p ()
7820 || rtx_equal_p (operands[0], operands[1]))
7821 ? operands[0] : gen_reg_rtx (DImode));
7823 if (GET_CODE (operands[2]) == CONST_INT)
7824 {
7825 value = INTVAL (operands[2]);
7826 emit_insn (gen_iordi3 (tmp, operands[1],
7827 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7828 }
7829 else
7830 {
7831 value = CONST_DOUBLE_LOW (operands[2]);
7832 emit_insn (gen_iordi3 (tmp, operands[1],
7833 immed_double_const (value
7834 & (~ (HOST_WIDE_INT) 0xffff),
7835 0, DImode)));
7836 }
7838 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7839 DONE;
7840 }
7841 }")
7843 (define_expand "xordi3"
7844 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7845 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7846 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7847 "TARGET_POWERPC64"
7848 "
7849 {
7850 if (non_logical_cint_operand (operands[2], DImode))
7851 {
7852 HOST_WIDE_INT value;
7853 rtx tmp = ((!can_create_pseudo_p ()
7854 || rtx_equal_p (operands[0], operands[1]))
7855 ? operands[0] : gen_reg_rtx (DImode));
7857 if (GET_CODE (operands[2]) == CONST_INT)
7858 {
7859 value = INTVAL (operands[2]);
7860 emit_insn (gen_xordi3 (tmp, operands[1],
7861 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7862 }
7863 else
7864 {
7865 value = CONST_DOUBLE_LOW (operands[2]);
7866 emit_insn (gen_xordi3 (tmp, operands[1],
7867 immed_double_const (value
7868 & (~ (HOST_WIDE_INT) 0xffff),
7869 0, DImode)));
7870 }
7872 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7873 DONE;
7874 }
7875 }")
7877 (define_insn "*booldi3_internal1"
7878 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7879 (match_operator:DI 3 "boolean_or_operator"
7880 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7881 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7882 "TARGET_POWERPC64"
7883 "@
7884 %q3 %0,%1,%2
7885 %q3i %0,%1,%b2
7886 %q3is %0,%1,%u2")
7888 (define_insn "*booldi3_internal2"
7889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7890 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7891 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7892 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7893 (const_int 0)))
7894 (clobber (match_scratch:DI 3 "=r,r"))]
7895 "TARGET_64BIT"
7896 "@
7897 %q4. %3,%1,%2
7898 #"
7899 [(set_attr "type" "compare")
7900 (set_attr "length" "4,8")])
7902 (define_split
7903 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7904 (compare:CC (match_operator:DI 4 "boolean_operator"
7905 [(match_operand:DI 1 "gpc_reg_operand" "")
7906 (match_operand:DI 2 "gpc_reg_operand" "")])
7907 (const_int 0)))
7908 (clobber (match_scratch:DI 3 ""))]
7909 "TARGET_POWERPC64 && reload_completed"
7910 [(set (match_dup 3) (match_dup 4))
7911 (set (match_dup 0)
7912 (compare:CC (match_dup 3)
7913 (const_int 0)))]
7914 "")
7916 (define_insn "*booldi3_internal3"
7917 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7918 (compare:CC (match_operator:DI 4 "boolean_operator"
7919 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7920 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7921 (const_int 0)))
7922 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7923 (match_dup 4))]
7924 "TARGET_64BIT"
7925 "@
7926 %q4. %0,%1,%2
7927 #"
7928 [(set_attr "type" "compare")
7929 (set_attr "length" "4,8")])
7931 (define_split
7932 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7933 (compare:CC (match_operator:DI 4 "boolean_operator"
7934 [(match_operand:DI 1 "gpc_reg_operand" "")
7935 (match_operand:DI 2 "gpc_reg_operand" "")])
7936 (const_int 0)))
7937 (set (match_operand:DI 0 "gpc_reg_operand" "")
7938 (match_dup 4))]
7939 "TARGET_POWERPC64 && reload_completed"
7940 [(set (match_dup 0) (match_dup 4))
7941 (set (match_dup 3)
7942 (compare:CC (match_dup 0)
7943 (const_int 0)))]
7944 "")
7946 ;; Split a logical operation that we can't do in one insn into two insns,
7947 ;; each of which does one 16-bit part. This is used by combine.
7949 (define_split
7950 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7951 (match_operator:DI 3 "boolean_or_operator"
7952 [(match_operand:DI 1 "gpc_reg_operand" "")
7953 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7954 "TARGET_POWERPC64"
7955 [(set (match_dup 0) (match_dup 4))
7956 (set (match_dup 0) (match_dup 5))]
7957 "
7958 {
7959 rtx i3,i4;
7961 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7962 {
7963 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7964 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7965 0, DImode);
7966 i4 = GEN_INT (value & 0xffff);
7967 }
7968 else
7969 {
7970 i3 = GEN_INT (INTVAL (operands[2])
7971 & (~ (HOST_WIDE_INT) 0xffff));
7972 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7973 }
7974 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7975 operands[1], i3);
7976 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7977 operands[0], i4);
7978 }")
7980 (define_insn "*boolcdi3_internal1"
7981 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7982 (match_operator:DI 3 "boolean_operator"
7983 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7984 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7985 "TARGET_POWERPC64"
7986 "%q3 %0,%2,%1")
7988 (define_insn "*boolcdi3_internal2"
7989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7990 (compare:CC (match_operator:DI 4 "boolean_operator"
7991 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7992 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7993 (const_int 0)))
7994 (clobber (match_scratch:DI 3 "=r,r"))]
7995 "TARGET_64BIT"
7996 "@
7997 %q4. %3,%2,%1
7998 #"
7999 [(set_attr "type" "compare")
8000 (set_attr "length" "4,8")])
8002 (define_split
8003 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8004 (compare:CC (match_operator:DI 4 "boolean_operator"
8005 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8006 (match_operand:DI 2 "gpc_reg_operand" "")])
8007 (const_int 0)))
8008 (clobber (match_scratch:DI 3 ""))]
8009 "TARGET_POWERPC64 && reload_completed"
8010 [(set (match_dup 3) (match_dup 4))
8011 (set (match_dup 0)
8012 (compare:CC (match_dup 3)
8013 (const_int 0)))]
8014 "")
8016 (define_insn "*boolcdi3_internal3"
8017 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8018 (compare:CC (match_operator:DI 4 "boolean_operator"
8019 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8020 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8021 (const_int 0)))
8022 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8023 (match_dup 4))]
8024 "TARGET_64BIT"
8025 "@
8026 %q4. %0,%2,%1
8027 #"
8028 [(set_attr "type" "compare")
8029 (set_attr "length" "4,8")])
8031 (define_split
8032 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8033 (compare:CC (match_operator:DI 4 "boolean_operator"
8034 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8035 (match_operand:DI 2 "gpc_reg_operand" "")])
8036 (const_int 0)))
8037 (set (match_operand:DI 0 "gpc_reg_operand" "")
8038 (match_dup 4))]
8039 "TARGET_POWERPC64 && reload_completed"
8040 [(set (match_dup 0) (match_dup 4))
8041 (set (match_dup 3)
8042 (compare:CC (match_dup 0)
8043 (const_int 0)))]
8044 "")
8046 (define_insn "*boolccdi3_internal1"
8047 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8048 (match_operator:DI 3 "boolean_operator"
8049 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8050 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8051 "TARGET_POWERPC64"
8052 "%q3 %0,%1,%2")
8054 (define_insn "*boolccdi3_internal2"
8055 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8056 (compare:CC (match_operator:DI 4 "boolean_operator"
8057 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8058 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8059 (const_int 0)))
8060 (clobber (match_scratch:DI 3 "=r,r"))]
8061 "TARGET_64BIT"
8062 "@
8063 %q4. %3,%1,%2
8064 #"
8065 [(set_attr "type" "compare")
8066 (set_attr "length" "4,8")])
8068 (define_split
8069 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8070 (compare:CC (match_operator:DI 4 "boolean_operator"
8071 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8072 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8073 (const_int 0)))
8074 (clobber (match_scratch:DI 3 ""))]
8075 "TARGET_POWERPC64 && reload_completed"
8076 [(set (match_dup 3) (match_dup 4))
8077 (set (match_dup 0)
8078 (compare:CC (match_dup 3)
8079 (const_int 0)))]
8080 "")
8082 (define_insn "*boolccdi3_internal3"
8083 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8084 (compare:CC (match_operator:DI 4 "boolean_operator"
8085 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8086 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8087 (const_int 0)))
8088 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8089 (match_dup 4))]
8090 "TARGET_64BIT"
8091 "@
8092 %q4. %0,%1,%2
8093 #"
8094 [(set_attr "type" "compare")
8095 (set_attr "length" "4,8")])
8097 (define_split
8098 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8099 (compare:CC (match_operator:DI 4 "boolean_operator"
8100 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8101 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8102 (const_int 0)))
8103 (set (match_operand:DI 0 "gpc_reg_operand" "")
8104 (match_dup 4))]
8105 "TARGET_POWERPC64 && reload_completed"
8106 [(set (match_dup 0) (match_dup 4))
8107 (set (match_dup 3)
8108 (compare:CC (match_dup 0)
8109 (const_int 0)))]
8110 "")
8111 \f
8112 ;; Now define ways of moving data around.
8114 ;; Set up a register with a value from the GOT table
8116 (define_expand "movsi_got"
8117 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8118 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8119 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8120 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8121 "
8122 {
8123 if (GET_CODE (operands[1]) == CONST)
8124 {
8125 rtx offset = const0_rtx;
8126 HOST_WIDE_INT value;
8128 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8129 value = INTVAL (offset);
8130 if (value != 0)
8131 {
8132 rtx tmp = (!can_create_pseudo_p ()
8133 ? operands[0]
8134 : gen_reg_rtx (Pmode));
8135 emit_insn (gen_movsi_got (tmp, operands[1]));
8136 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8137 DONE;
8138 }
8139 }
8141 operands[2] = rs6000_got_register (operands[1]);
8142 }")
8144 (define_insn "*movsi_got_internal"
8145 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8146 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8147 (match_operand:SI 2 "gpc_reg_operand" "b")]
8148 UNSPEC_MOVSI_GOT))]
8149 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8150 "{l|lwz} %0,%a1@got(%2)"
8151 [(set_attr "type" "load")])
8153 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8154 ;; didn't get allocated to a hard register.
8155 (define_split
8156 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8157 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8158 (match_operand:SI 2 "memory_operand" "")]
8159 UNSPEC_MOVSI_GOT))]
8160 "DEFAULT_ABI == ABI_V4
8161 && flag_pic == 1
8162 && (reload_in_progress || reload_completed)"
8163 [(set (match_dup 0) (match_dup 2))
8164 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8165 UNSPEC_MOVSI_GOT))]
8166 "")
8168 ;; For SI, we special-case integers that can't be loaded in one insn. We
8169 ;; do the load 16-bits at a time. We could do this by loading from memory,
8170 ;; and this is even supposed to be faster, but it is simpler not to get
8171 ;; integers in the TOC.
8172 (define_insn "movsi_low"
8173 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8174 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8175 (match_operand 2 "" ""))))]
8176 "TARGET_MACHO && ! TARGET_64BIT"
8177 "{l|lwz} %0,lo16(%2)(%1)"
8178 [(set_attr "type" "load")
8179 (set_attr "length" "4")])
8181 (define_insn "*movsi_internal1"
8182 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8183 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8184 "gpc_reg_operand (operands[0], SImode)
8185 || gpc_reg_operand (operands[1], SImode)"
8186 "@
8187 mr %0,%1
8188 {cal|la} %0,%a1
8189 {l%U1%X1|lwz%U1%X1} %0,%1
8190 {st%U0%X0|stw%U0%X0} %1,%0
8191 {lil|li} %0,%1
8192 {liu|lis} %0,%v1
8193 #
8194 {cal|la} %0,%a1
8195 mf%1 %0
8196 mt%0 %1
8197 mt%0 %1
8198 mt%0 %1
8199 {cror 0,0,0|nop}"
8200 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8201 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8203 ;; Split a load of a large constant into the appropriate two-insn
8204 ;; sequence.
8206 (define_split
8207 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8208 (match_operand:SI 1 "const_int_operand" ""))]
8209 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8210 && (INTVAL (operands[1]) & 0xffff) != 0"
8211 [(set (match_dup 0)
8212 (match_dup 2))
8213 (set (match_dup 0)
8214 (ior:SI (match_dup 0)
8215 (match_dup 3)))]
8216 "
8217 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8219 if (tem == operands[0])
8220 DONE;
8221 else
8222 FAIL;
8223 }")
8225 (define_insn "*mov<mode>_internal2"
8226 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8227 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8228 (const_int 0)))
8229 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8230 ""
8231 "@
8232 {cmpi|cmp<wd>i} %2,%0,0
8233 mr. %0,%1
8234 #"
8235 [(set_attr "type" "cmp,compare,cmp")
8236 (set_attr "length" "4,4,8")])
8238 (define_split
8239 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8240 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8241 (const_int 0)))
8242 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8243 "reload_completed"
8244 [(set (match_dup 0) (match_dup 1))
8245 (set (match_dup 2)
8246 (compare:CC (match_dup 0)
8247 (const_int 0)))]
8248 "")
8249 \f
8250 (define_insn "*movhi_internal"
8251 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8252 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8253 "gpc_reg_operand (operands[0], HImode)
8254 || gpc_reg_operand (operands[1], HImode)"
8255 "@
8256 mr %0,%1
8257 lhz%U1%X1 %0,%1
8258 sth%U0%X0 %1,%0
8259 {lil|li} %0,%w1
8260 mf%1 %0
8261 mt%0 %1
8262 mt%0 %1
8263 {cror 0,0,0|nop}"
8264 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8266 (define_expand "mov<mode>"
8267 [(set (match_operand:INT 0 "general_operand" "")
8268 (match_operand:INT 1 "any_operand" ""))]
8269 ""
8270 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8272 (define_insn "*movqi_internal"
8273 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8274 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8275 "gpc_reg_operand (operands[0], QImode)
8276 || gpc_reg_operand (operands[1], QImode)"
8277 "@
8278 mr %0,%1
8279 lbz%U1%X1 %0,%1
8280 stb%U0%X0 %1,%0
8281 {lil|li} %0,%1
8282 mf%1 %0
8283 mt%0 %1
8284 mt%0 %1
8285 {cror 0,0,0|nop}"
8286 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8287 \f
8288 ;; Here is how to move condition codes around. When we store CC data in
8289 ;; an integer register or memory, we store just the high-order 4 bits.
8290 ;; This lets us not shift in the most common case of CR0.
8291 (define_expand "movcc"
8292 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8293 (match_operand:CC 1 "nonimmediate_operand" ""))]
8294 ""
8295 "")
8297 (define_insn "*movcc_internal1"
8298 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8299 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8300 "register_operand (operands[0], CCmode)
8301 || register_operand (operands[1], CCmode)"
8302 "@
8303 mcrf %0,%1
8304 mtcrf 128,%1
8305 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8306 crxor %0,%0,%0
8307 mfcr %0%Q1
8308 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8309 mr %0,%1
8310 {lil|li} %0,%1
8311 mf%1 %0
8312 mt%0 %1
8313 mt%0 %1
8314 {l%U1%X1|lwz%U1%X1} %0,%1
8315 {st%U0%U1|stw%U0%U1} %1,%0"
8316 [(set (attr "type")
8317 (cond [(eq_attr "alternative" "0,3")
8318 (const_string "cr_logical")
8319 (eq_attr "alternative" "1,2")
8320 (const_string "mtcr")
8321 (eq_attr "alternative" "6,7,9")
8322 (const_string "integer")
8323 (eq_attr "alternative" "8")
8324 (const_string "mfjmpr")
8325 (eq_attr "alternative" "10")
8326 (const_string "mtjmpr")
8327 (eq_attr "alternative" "11")
8328 (const_string "load")
8329 (eq_attr "alternative" "12")
8330 (const_string "store")
8331 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8332 (const_string "mfcrf")
8333 ]
8334 (const_string "mfcr")))
8335 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8336 \f
8337 ;; For floating-point, we normally deal with the floating-point registers
8338 ;; unless -msoft-float is used. The sole exception is that parameter passing
8339 ;; can produce floating-point values in fixed-point registers. Unless the
8340 ;; value is a simple constant or already in memory, we deal with this by
8341 ;; allocating memory and copying the value explicitly via that memory location.
8342 (define_expand "movsf"
8343 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8344 (match_operand:SF 1 "any_operand" ""))]
8345 ""
8346 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8348 (define_split
8349 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8350 (match_operand:SF 1 "const_double_operand" ""))]
8351 "reload_completed
8352 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8353 || (GET_CODE (operands[0]) == SUBREG
8354 && GET_CODE (SUBREG_REG (operands[0])) == REG
8355 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8356 [(set (match_dup 2) (match_dup 3))]
8357 "
8358 {
8359 long l;
8360 REAL_VALUE_TYPE rv;
8362 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8363 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8365 if (! TARGET_POWERPC64)
8366 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8367 else
8368 operands[2] = gen_lowpart (SImode, operands[0]);
8370 operands[3] = gen_int_mode (l, SImode);
8371 }")
8373 (define_insn "*movsf_hardfloat"
8374 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8375 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8376 "(gpc_reg_operand (operands[0], SFmode)
8377 || gpc_reg_operand (operands[1], SFmode))
8378 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8379 "@
8380 mr %0,%1
8381 {l%U1%X1|lwz%U1%X1} %0,%1
8382 {st%U0%X0|stw%U0%X0} %1,%0
8383 fmr %0,%1
8384 lfs%U1%X1 %0,%1
8385 stfs%U0%X0 %1,%0
8386 mt%0 %1
8387 mt%0 %1
8388 mf%1 %0
8389 {cror 0,0,0|nop}
8390 #
8391 #"
8392 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8393 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8395 (define_insn "*movsf_softfloat"
8396 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8397 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8398 "(gpc_reg_operand (operands[0], SFmode)
8399 || gpc_reg_operand (operands[1], SFmode))
8400 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8401 "@
8402 mr %0,%1
8403 mt%0 %1
8404 mt%0 %1
8405 mf%1 %0
8406 {l%U1%X1|lwz%U1%X1} %0,%1
8407 {st%U0%X0|stw%U0%X0} %1,%0
8408 {lil|li} %0,%1
8409 {liu|lis} %0,%v1
8410 {cal|la} %0,%a1
8411 #
8412 #
8413 {cror 0,0,0|nop}"
8414 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8415 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8417 \f
8418 (define_expand "movdf"
8419 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8420 (match_operand:DF 1 "any_operand" ""))]
8421 ""
8422 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8424 (define_split
8425 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8426 (match_operand:DF 1 "const_int_operand" ""))]
8427 "! TARGET_POWERPC64 && reload_completed
8428 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8429 || (GET_CODE (operands[0]) == SUBREG
8430 && GET_CODE (SUBREG_REG (operands[0])) == REG
8431 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8432 [(set (match_dup 2) (match_dup 4))
8433 (set (match_dup 3) (match_dup 1))]
8434 "
8435 {
8436 int endian = (WORDS_BIG_ENDIAN == 0);
8437 HOST_WIDE_INT value = INTVAL (operands[1]);
8439 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8440 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8441 #if HOST_BITS_PER_WIDE_INT == 32
8442 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8443 #else
8444 operands[4] = GEN_INT (value >> 32);
8445 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8446 #endif
8447 }")
8449 (define_split
8450 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8451 (match_operand:DF 1 "const_double_operand" ""))]
8452 "! TARGET_POWERPC64 && reload_completed
8453 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8454 || (GET_CODE (operands[0]) == SUBREG
8455 && GET_CODE (SUBREG_REG (operands[0])) == REG
8456 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8457 [(set (match_dup 2) (match_dup 4))
8458 (set (match_dup 3) (match_dup 5))]
8459 "
8460 {
8461 int endian = (WORDS_BIG_ENDIAN == 0);
8462 long l[2];
8463 REAL_VALUE_TYPE rv;
8465 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8466 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8468 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8469 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8470 operands[4] = gen_int_mode (l[endian], SImode);
8471 operands[5] = gen_int_mode (l[1 - endian], SImode);
8472 }")
8474 (define_split
8475 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8476 (match_operand:DF 1 "const_double_operand" ""))]
8477 "TARGET_POWERPC64 && reload_completed
8478 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8479 || (GET_CODE (operands[0]) == SUBREG
8480 && GET_CODE (SUBREG_REG (operands[0])) == REG
8481 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8482 [(set (match_dup 2) (match_dup 3))]
8483 "
8484 {
8485 int endian = (WORDS_BIG_ENDIAN == 0);
8486 long l[2];
8487 REAL_VALUE_TYPE rv;
8488 #if HOST_BITS_PER_WIDE_INT >= 64
8489 HOST_WIDE_INT val;
8490 #endif
8492 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8493 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8495 operands[2] = gen_lowpart (DImode, operands[0]);
8496 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8497 #if HOST_BITS_PER_WIDE_INT >= 64
8498 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8499 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8501 operands[3] = gen_int_mode (val, DImode);
8502 #else
8503 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8504 #endif
8505 }")
8507 ;; Don't have reload use general registers to load a constant. First,
8508 ;; it might not work if the output operand is the equivalent of
8509 ;; a non-offsettable memref, but also it is less efficient than loading
8510 ;; the constant into an FP register, since it will probably be used there.
8511 ;; The "??" is a kludge until we can figure out a more reasonable way
8512 ;; of handling these non-offsettable values.
8513 (define_insn "*movdf_hardfloat32"
8514 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8515 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8516 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8517 && (gpc_reg_operand (operands[0], DFmode)
8518 || gpc_reg_operand (operands[1], DFmode))"
8519 "*
8520 {
8521 switch (which_alternative)
8522 {
8523 default:
8524 gcc_unreachable ();
8525 case 0:
8526 /* We normally copy the low-numbered register first. However, if
8527 the first register operand 0 is the same as the second register
8528 of operand 1, we must copy in the opposite order. */
8529 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8530 return \"mr %L0,%L1\;mr %0,%1\";
8531 else
8532 return \"mr %0,%1\;mr %L0,%L1\";
8533 case 1:
8534 if (rs6000_offsettable_memref_p (operands[1])
8535 || (GET_CODE (operands[1]) == MEM
8536 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8537 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8538 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8539 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8540 {
8541 /* If the low-address word is used in the address, we must load
8542 it last. Otherwise, load it first. Note that we cannot have
8543 auto-increment in that case since the address register is
8544 known to be dead. */
8545 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8546 operands[1], 0))
8547 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8548 else
8549 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8550 }
8551 else
8552 {
8553 rtx addreg;
8555 addreg = find_addr_reg (XEXP (operands[1], 0));
8556 if (refers_to_regno_p (REGNO (operands[0]),
8557 REGNO (operands[0]) + 1,
8558 operands[1], 0))
8559 {
8560 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8561 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8562 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8563 return \"{l%X1|lwz%X1} %0,%1\";
8564 }
8565 else
8566 {
8567 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8568 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8569 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8570 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8571 return \"\";
8572 }
8573 }
8574 case 2:
8575 if (rs6000_offsettable_memref_p (operands[0])
8576 || (GET_CODE (operands[0]) == MEM
8577 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8578 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8579 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8580 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8581 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8582 else
8583 {
8584 rtx addreg;
8586 addreg = find_addr_reg (XEXP (operands[0], 0));
8587 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8588 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8589 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8590 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8591 return \"\";
8592 }
8593 case 3:
8594 return \"fmr %0,%1\";
8595 case 4:
8596 return \"lfd%U1%X1 %0,%1\";
8597 case 5:
8598 return \"stfd%U0%X0 %1,%0\";
8599 case 6:
8600 case 7:
8601 case 8:
8602 return \"#\";
8603 }
8604 }"
8605 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8606 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8608 (define_insn "*movdf_softfloat32"
8609 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8610 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8611 "! TARGET_POWERPC64
8612 && ((TARGET_FPRS && !TARGET_DOUBLE_FLOAT)
8613 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8614 && (gpc_reg_operand (operands[0], DFmode)
8615 || gpc_reg_operand (operands[1], DFmode))"
8616 "*
8617 {
8618 switch (which_alternative)
8619 {
8620 default:
8621 gcc_unreachable ();
8622 case 0:
8623 /* We normally copy the low-numbered register first. However, if
8624 the first register operand 0 is the same as the second register of
8625 operand 1, we must copy in the opposite order. */
8626 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8627 return \"mr %L0,%L1\;mr %0,%1\";
8628 else
8629 return \"mr %0,%1\;mr %L0,%L1\";
8630 case 1:
8631 /* If the low-address word is used in the address, we must load
8632 it last. Otherwise, load it first. Note that we cannot have
8633 auto-increment in that case since the address register is
8634 known to be dead. */
8635 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8636 operands[1], 0))
8637 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8638 else
8639 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8640 case 2:
8641 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8642 case 3:
8643 case 4:
8644 case 5:
8645 return \"#\";
8646 }
8647 }"
8648 [(set_attr "type" "two,load,store,*,*,*")
8649 (set_attr "length" "8,8,8,8,12,16")])
8651 ; ld/std require word-aligned displacements -> 'Y' constraint.
8652 ; List Y->r and r->Y before r->r for reload.
8653 (define_insn "*movdf_hardfloat64_mfpgpr"
8654 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8655 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8656 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8657 && TARGET_DOUBLE_FLOAT
8658 && (gpc_reg_operand (operands[0], DFmode)
8659 || gpc_reg_operand (operands[1], DFmode))"
8660 "@
8661 std%U0%X0 %1,%0
8662 ld%U1%X1 %0,%1
8663 mr %0,%1
8664 fmr %0,%1
8665 lfd%U1%X1 %0,%1
8666 stfd%U0%X0 %1,%0
8667 mt%0 %1
8668 mf%1 %0
8669 {cror 0,0,0|nop}
8670 #
8671 #
8672 #
8673 mftgpr %0,%1
8674 mffgpr %0,%1"
8675 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8676 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8678 ; ld/std require word-aligned displacements -> 'Y' constraint.
8679 ; List Y->r and r->Y before r->r for reload.
8680 (define_insn "*movdf_hardfloat64"
8681 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8682 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8683 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8684 && TARGET_DOUBLE_FLOAT
8685 && (gpc_reg_operand (operands[0], DFmode)
8686 || gpc_reg_operand (operands[1], DFmode))"
8687 "@
8688 std%U0%X0 %1,%0
8689 ld%U1%X1 %0,%1
8690 mr %0,%1
8691 fmr %0,%1
8692 lfd%U1%X1 %0,%1
8693 stfd%U0%X0 %1,%0
8694 mt%0 %1
8695 mf%1 %0
8696 {cror 0,0,0|nop}
8697 #
8698 #
8699 #"
8700 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8701 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8703 (define_insn "*movdf_softfloat64"
8704 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8705 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8706 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8707 && (gpc_reg_operand (operands[0], DFmode)
8708 || gpc_reg_operand (operands[1], DFmode))"
8709 "@
8710 ld%U1%X1 %0,%1
8711 std%U0%X0 %1,%0
8712 mr %0,%1
8713 mt%0 %1
8714 mf%1 %0
8715 #
8716 #
8717 #
8718 {cror 0,0,0|nop}"
8719 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8720 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8721 \f
8722 (define_expand "movtf"
8723 [(set (match_operand:TF 0 "general_operand" "")
8724 (match_operand:TF 1 "any_operand" ""))]
8725 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8726 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8728 ; It's important to list the o->f and f->o moves before f->f because
8729 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8730 ; which doesn't make progress. Likewise r->Y must be before r->r.
8731 (define_insn_and_split "*movtf_internal"
8732 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8733 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8734 "!TARGET_IEEEQUAD
8735 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8736 && (gpc_reg_operand (operands[0], TFmode)
8737 || gpc_reg_operand (operands[1], TFmode))"
8738 "#"
8739 "&& reload_completed"
8740 [(pc)]
8741 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8742 [(set_attr "length" "8,8,8,20,20,16")])
8744 (define_insn_and_split "*movtf_softfloat"
8745 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8746 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8747 "!TARGET_IEEEQUAD
8748 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8749 && (gpc_reg_operand (operands[0], TFmode)
8750 || gpc_reg_operand (operands[1], TFmode))"
8751 "#"
8752 "&& reload_completed"
8753 [(pc)]
8754 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8755 [(set_attr "length" "20,20,16")])
8757 (define_expand "extenddftf2"
8758 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8759 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8760 "!TARGET_IEEEQUAD
8761 && TARGET_HARD_FLOAT
8762 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8763 && TARGET_LONG_DOUBLE_128"
8764 {
8765 if (TARGET_E500_DOUBLE)
8766 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8767 else
8768 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8769 DONE;
8770 })
8772 (define_expand "extenddftf2_fprs"
8773 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8774 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8775 (use (match_dup 2))])]
8776 "!TARGET_IEEEQUAD
8777 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8778 && TARGET_LONG_DOUBLE_128"
8779 {
8780 operands[2] = CONST0_RTX (DFmode);
8781 /* Generate GOT reference early for SVR4 PIC. */
8782 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8783 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8784 })
8786 (define_insn_and_split "*extenddftf2_internal"
8787 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8788 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8789 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8790 "!TARGET_IEEEQUAD
8791 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8792 && TARGET_LONG_DOUBLE_128"
8793 "#"
8794 "&& reload_completed"
8795 [(pc)]
8796 {
8797 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8798 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8799 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8800 operands[1]);
8801 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8802 operands[2]);
8803 DONE;
8804 })
8806 (define_expand "extendsftf2"
8807 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8808 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8809 "!TARGET_IEEEQUAD
8810 && TARGET_HARD_FLOAT
8811 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8812 && TARGET_LONG_DOUBLE_128"
8813 {
8814 rtx tmp = gen_reg_rtx (DFmode);
8815 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8816 emit_insn (gen_extenddftf2 (operands[0], tmp));
8817 DONE;
8818 })
8820 (define_expand "trunctfdf2"
8821 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8822 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8823 "!TARGET_IEEEQUAD
8824 && TARGET_HARD_FLOAT
8825 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8826 && TARGET_LONG_DOUBLE_128"
8827 "")
8829 (define_insn_and_split "trunctfdf2_internal1"
8830 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8831 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8832 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8833 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8834 "@
8835 #
8836 fmr %0,%1"
8837 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8838 [(const_int 0)]
8839 {
8840 emit_note (NOTE_INSN_DELETED);
8841 DONE;
8842 }
8843 [(set_attr "type" "fp")])
8845 (define_insn "trunctfdf2_internal2"
8846 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8847 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8848 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8849 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8850 && TARGET_LONG_DOUBLE_128"
8851 "fadd %0,%1,%L1"
8852 [(set_attr "type" "fp")
8853 (set_attr "fp_type" "fp_addsub_d")])
8855 (define_expand "trunctfsf2"
8856 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8857 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8858 "!TARGET_IEEEQUAD
8859 && TARGET_HARD_FLOAT
8860 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8861 && TARGET_LONG_DOUBLE_128"
8862 {
8863 if (TARGET_E500_DOUBLE)
8864 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8865 else
8866 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8867 DONE;
8868 })
8870 (define_insn_and_split "trunctfsf2_fprs"
8871 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8872 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8873 (clobber (match_scratch:DF 2 "=f"))]
8874 "!TARGET_IEEEQUAD
8875 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8876 && TARGET_LONG_DOUBLE_128"
8877 "#"
8878 "&& reload_completed"
8879 [(set (match_dup 2)
8880 (float_truncate:DF (match_dup 1)))
8881 (set (match_dup 0)
8882 (float_truncate:SF (match_dup 2)))]
8883 "")
8885 (define_expand "floatsitf2"
8886 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8887 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8888 "!TARGET_IEEEQUAD
8889 && TARGET_HARD_FLOAT
8890 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8891 && TARGET_LONG_DOUBLE_128"
8892 {
8893 rtx tmp = gen_reg_rtx (DFmode);
8894 expand_float (tmp, operands[1], false);
8895 emit_insn (gen_extenddftf2 (operands[0], tmp));
8896 DONE;
8897 })
8899 ; fadd, but rounding towards zero.
8900 ; This is probably not the optimal code sequence.
8901 (define_insn "fix_trunc_helper"
8902 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8903 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8904 UNSPEC_FIX_TRUNC_TF))
8905 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8906 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8907 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8908 [(set_attr "type" "fp")
8909 (set_attr "length" "20")])
8911 (define_expand "fix_trunctfsi2"
8912 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8913 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8914 "!TARGET_IEEEQUAD
8915 && (TARGET_POWER2 || TARGET_POWERPC)
8916 && TARGET_HARD_FLOAT
8917 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8918 && TARGET_LONG_DOUBLE_128"
8919 {
8920 if (TARGET_E500_DOUBLE)
8921 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8922 else
8923 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8924 DONE;
8925 })
8927 (define_expand "fix_trunctfsi2_fprs"
8928 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8929 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8930 (clobber (match_dup 2))
8931 (clobber (match_dup 3))
8932 (clobber (match_dup 4))
8933 (clobber (match_dup 5))])]
8934 "!TARGET_IEEEQUAD
8935 && (TARGET_POWER2 || TARGET_POWERPC)
8936 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8937 {
8938 operands[2] = gen_reg_rtx (DFmode);
8939 operands[3] = gen_reg_rtx (DFmode);
8940 operands[4] = gen_reg_rtx (DImode);
8941 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8942 })
8944 (define_insn_and_split "*fix_trunctfsi2_internal"
8945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8946 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8947 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8948 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8949 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8950 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8951 "!TARGET_IEEEQUAD
8952 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8953 "#"
8954 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
8955 [(pc)]
8956 {
8957 rtx lowword;
8958 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8960 gcc_assert (MEM_P (operands[5]));
8961 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8963 emit_insn (gen_fctiwz (operands[4], operands[2]));
8964 emit_move_insn (operands[5], operands[4]);
8965 emit_move_insn (operands[0], lowword);
8966 DONE;
8967 })
8969 (define_expand "negtf2"
8970 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8971 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8972 "!TARGET_IEEEQUAD
8973 && TARGET_HARD_FLOAT
8974 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8975 && TARGET_LONG_DOUBLE_128"
8976 "")
8978 (define_insn "negtf2_internal"
8979 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8980 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8981 "!TARGET_IEEEQUAD
8982 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8983 "*
8984 {
8985 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8986 return \"fneg %L0,%L1\;fneg %0,%1\";
8987 else
8988 return \"fneg %0,%1\;fneg %L0,%L1\";
8989 }"
8990 [(set_attr "type" "fp")
8991 (set_attr "length" "8")])
8993 (define_expand "abstf2"
8994 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8995 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8996 "!TARGET_IEEEQUAD
8997 && TARGET_HARD_FLOAT
8998 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8999 && TARGET_LONG_DOUBLE_128"
9000 "
9001 {
9002 rtx label = gen_label_rtx ();
9003 if (TARGET_E500_DOUBLE)
9004 {
9005 if (flag_finite_math_only && !flag_trapping_math)
9006 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9007 else
9008 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9009 }
9010 else
9011 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9012 emit_label (label);
9013 DONE;
9014 }")
9016 (define_expand "abstf2_internal"
9017 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9018 (match_operand:TF 1 "gpc_reg_operand" ""))
9019 (set (match_dup 3) (match_dup 5))
9020 (set (match_dup 5) (abs:DF (match_dup 5)))
9021 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9022 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9023 (label_ref (match_operand 2 "" ""))
9024 (pc)))
9025 (set (match_dup 6) (neg:DF (match_dup 6)))]
9026 "!TARGET_IEEEQUAD
9027 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9028 && TARGET_LONG_DOUBLE_128"
9029 "
9030 {
9031 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9032 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9033 operands[3] = gen_reg_rtx (DFmode);
9034 operands[4] = gen_reg_rtx (CCFPmode);
9035 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9036 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9037 }")
9038 \f
9039 ;; Next come the multi-word integer load and store and the load and store
9040 ;; multiple insns.
9042 ; List r->r after r->"o<>", otherwise reload will try to reload a
9043 ; non-offsettable address by using r->r which won't make progress.
9044 (define_insn "*movdi_internal32"
9045 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
9046 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
9047 "! TARGET_POWERPC64
9048 && (gpc_reg_operand (operands[0], DImode)
9049 || gpc_reg_operand (operands[1], DImode))"
9050 "@
9051 #
9052 #
9053 #
9054 fmr %0,%1
9055 lfd%U1%X1 %0,%1
9056 stfd%U0%X0 %1,%0
9057 #"
9058 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9060 (define_split
9061 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9062 (match_operand:DI 1 "const_int_operand" ""))]
9063 "! TARGET_POWERPC64 && reload_completed"
9064 [(set (match_dup 2) (match_dup 4))
9065 (set (match_dup 3) (match_dup 1))]
9066 "
9067 {
9068 HOST_WIDE_INT value = INTVAL (operands[1]);
9069 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9070 DImode);
9071 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9072 DImode);
9073 #if HOST_BITS_PER_WIDE_INT == 32
9074 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9075 #else
9076 operands[4] = GEN_INT (value >> 32);
9077 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9078 #endif
9079 }")
9081 (define_split
9082 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
9083 (match_operand:DI 1 "input_operand" ""))]
9084 "reload_completed && !TARGET_POWERPC64
9085 && gpr_or_gpr_p (operands[0], operands[1])"
9086 [(pc)]
9087 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9089 (define_insn "*movdi_mfpgpr"
9090 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
9091 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
9092 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9093 && (gpc_reg_operand (operands[0], DImode)
9094 || gpc_reg_operand (operands[1], DImode))"
9095 "@
9096 mr %0,%1
9097 ld%U1%X1 %0,%1
9098 std%U0%X0 %1,%0
9099 li %0,%1
9100 lis %0,%v1
9101 #
9102 {cal|la} %0,%a1
9103 fmr %0,%1
9104 lfd%U1%X1 %0,%1
9105 stfd%U0%X0 %1,%0
9106 mf%1 %0
9107 mt%0 %1
9108 {cror 0,0,0|nop}
9109 mftgpr %0,%1
9110 mffgpr %0,%1"
9111 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9112 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9114 (define_insn "*movdi_internal64"
9115 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9116 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
9117 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9118 && (gpc_reg_operand (operands[0], DImode)
9119 || gpc_reg_operand (operands[1], DImode))"
9120 "@
9121 mr %0,%1
9122 ld%U1%X1 %0,%1
9123 std%U0%X0 %1,%0
9124 li %0,%1
9125 lis %0,%v1
9126 #
9127 {cal|la} %0,%a1
9128 fmr %0,%1
9129 lfd%U1%X1 %0,%1
9130 stfd%U0%X0 %1,%0
9131 mf%1 %0
9132 mt%0 %1
9133 {cror 0,0,0|nop}"
9134 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9135 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9137 ;; immediate value valid for a single instruction hiding in a const_double
9138 (define_insn ""
9139 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9140 (match_operand:DI 1 "const_double_operand" "F"))]
9141 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9142 && GET_CODE (operands[1]) == CONST_DOUBLE
9143 && num_insns_constant (operands[1], DImode) == 1"
9144 "*
9145 {
9146 return ((unsigned HOST_WIDE_INT)
9147 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9148 ? \"li %0,%1\" : \"lis %0,%v1\";
9149 }")
9151 ;; Generate all one-bits and clear left or right.
9152 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9153 (define_split
9154 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9155 (match_operand:DI 1 "mask64_operand" ""))]
9156 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9157 [(set (match_dup 0) (const_int -1))
9158 (set (match_dup 0)
9159 (and:DI (rotate:DI (match_dup 0)
9160 (const_int 0))
9161 (match_dup 1)))]
9162 "")
9164 ;; Split a load of a large constant into the appropriate five-instruction
9165 ;; sequence. Handle anything in a constant number of insns.
9166 ;; When non-easy constants can go in the TOC, this should use
9167 ;; easy_fp_constant predicate.
9168 (define_split
9169 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9170 (match_operand:DI 1 "const_int_operand" ""))]
9171 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9172 [(set (match_dup 0) (match_dup 2))
9173 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9174 "
9175 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9177 if (tem == operands[0])
9178 DONE;
9179 else
9180 FAIL;
9181 }")
9183 (define_split
9184 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9185 (match_operand:DI 1 "const_double_operand" ""))]
9186 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9187 [(set (match_dup 0) (match_dup 2))
9188 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9189 "
9190 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9192 if (tem == operands[0])
9193 DONE;
9194 else
9195 FAIL;
9196 }")
9197 \f
9198 ;; TImode is similar, except that we usually want to compute the address into
9199 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9200 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9202 ;; We say that MQ is clobbered in the last alternative because the first
9203 ;; alternative would never get used otherwise since it would need a reload
9204 ;; while the 2nd alternative would not. We put memory cases first so they
9205 ;; are preferred. Otherwise, we'd try to reload the output instead of
9206 ;; giving the SCRATCH mq.
9208 (define_insn "*movti_power"
9209 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9210 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9211 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9212 "TARGET_POWER && ! TARGET_POWERPC64
9213 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9214 "*
9215 {
9216 switch (which_alternative)
9217 {
9218 default:
9219 gcc_unreachable ();
9221 case 0:
9222 if (TARGET_STRING)
9223 return \"{stsi|stswi} %1,%P0,16\";
9224 case 1:
9225 case 2:
9226 return \"#\";
9227 case 3:
9228 /* If the address is not used in the output, we can use lsi. Otherwise,
9229 fall through to generating four loads. */
9230 if (TARGET_STRING
9231 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9232 return \"{lsi|lswi} %0,%P1,16\";
9233 /* ... fall through ... */
9234 case 4:
9235 case 5:
9236 return \"#\";
9237 }
9238 }"
9239 [(set_attr "type" "store,store,*,load,load,*")])
9241 (define_insn "*movti_string"
9242 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9243 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9244 "! TARGET_POWER && ! TARGET_POWERPC64
9245 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9246 "*
9247 {
9248 switch (which_alternative)
9249 {
9250 default:
9251 gcc_unreachable ();
9252 case 0:
9253 if (TARGET_STRING)
9254 return \"{stsi|stswi} %1,%P0,16\";
9255 case 1:
9256 case 2:
9257 return \"#\";
9258 case 3:
9259 /* If the address is not used in the output, we can use lsi. Otherwise,
9260 fall through to generating four loads. */
9261 if (TARGET_STRING
9262 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9263 return \"{lsi|lswi} %0,%P1,16\";
9264 /* ... fall through ... */
9265 case 4:
9266 case 5:
9267 return \"#\";
9268 }
9269 }"
9270 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9271 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9272 (const_string "always")
9273 (const_string "conditional")))])
9275 (define_insn "*movti_ppc64"
9276 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9277 (match_operand:TI 1 "input_operand" "r,r,m"))]
9278 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9279 || gpc_reg_operand (operands[1], TImode))"
9280 "#"
9281 [(set_attr "type" "*,load,store")])
9283 (define_split
9284 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9285 (match_operand:TI 1 "const_double_operand" ""))]
9286 "TARGET_POWERPC64"
9287 [(set (match_dup 2) (match_dup 4))
9288 (set (match_dup 3) (match_dup 5))]
9289 "
9290 {
9291 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9292 TImode);
9293 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9294 TImode);
9295 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9296 {
9297 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9298 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9299 }
9300 else if (GET_CODE (operands[1]) == CONST_INT)
9301 {
9302 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9303 operands[5] = operands[1];
9304 }
9305 else
9306 FAIL;
9307 }")
9309 (define_split
9310 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9311 (match_operand:TI 1 "input_operand" ""))]
9312 "reload_completed
9313 && gpr_or_gpr_p (operands[0], operands[1])"
9314 [(pc)]
9315 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9316 \f
9317 (define_expand "load_multiple"
9318 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9319 (match_operand:SI 1 "" ""))
9320 (use (match_operand:SI 2 "" ""))])]
9321 "TARGET_STRING && !TARGET_POWERPC64"
9322 "
9323 {
9324 int regno;
9325 int count;
9326 rtx op1;
9327 int i;
9329 /* Support only loading a constant number of fixed-point registers from
9330 memory and only bother with this if more than two; the machine
9331 doesn't support more than eight. */
9332 if (GET_CODE (operands[2]) != CONST_INT
9333 || INTVAL (operands[2]) <= 2
9334 || INTVAL (operands[2]) > 8
9335 || GET_CODE (operands[1]) != MEM
9336 || GET_CODE (operands[0]) != REG
9337 || REGNO (operands[0]) >= 32)
9338 FAIL;
9340 count = INTVAL (operands[2]);
9341 regno = REGNO (operands[0]);
9343 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9344 op1 = replace_equiv_address (operands[1],
9345 force_reg (SImode, XEXP (operands[1], 0)));
9347 for (i = 0; i < count; i++)
9348 XVECEXP (operands[3], 0, i)
9349 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9350 adjust_address_nv (op1, SImode, i * 4));
9351 }")
9353 (define_insn "*ldmsi8"
9354 [(match_parallel 0 "load_multiple_operation"
9355 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9356 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9357 (set (match_operand:SI 3 "gpc_reg_operand" "")
9358 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9359 (set (match_operand:SI 4 "gpc_reg_operand" "")
9360 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9361 (set (match_operand:SI 5 "gpc_reg_operand" "")
9362 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9363 (set (match_operand:SI 6 "gpc_reg_operand" "")
9364 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9365 (set (match_operand:SI 7 "gpc_reg_operand" "")
9366 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9367 (set (match_operand:SI 8 "gpc_reg_operand" "")
9368 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9369 (set (match_operand:SI 9 "gpc_reg_operand" "")
9370 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9371 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9372 "*
9373 { return rs6000_output_load_multiple (operands); }"
9374 [(set_attr "type" "load_ux")
9375 (set_attr "length" "32")])
9377 (define_insn "*ldmsi7"
9378 [(match_parallel 0 "load_multiple_operation"
9379 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9380 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9381 (set (match_operand:SI 3 "gpc_reg_operand" "")
9382 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9383 (set (match_operand:SI 4 "gpc_reg_operand" "")
9384 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9385 (set (match_operand:SI 5 "gpc_reg_operand" "")
9386 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9387 (set (match_operand:SI 6 "gpc_reg_operand" "")
9388 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9389 (set (match_operand:SI 7 "gpc_reg_operand" "")
9390 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9391 (set (match_operand:SI 8 "gpc_reg_operand" "")
9392 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9393 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9394 "*
9395 { return rs6000_output_load_multiple (operands); }"
9396 [(set_attr "type" "load_ux")
9397 (set_attr "length" "32")])
9399 (define_insn "*ldmsi6"
9400 [(match_parallel 0 "load_multiple_operation"
9401 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9402 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9403 (set (match_operand:SI 3 "gpc_reg_operand" "")
9404 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9405 (set (match_operand:SI 4 "gpc_reg_operand" "")
9406 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9407 (set (match_operand:SI 5 "gpc_reg_operand" "")
9408 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9409 (set (match_operand:SI 6 "gpc_reg_operand" "")
9410 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9411 (set (match_operand:SI 7 "gpc_reg_operand" "")
9412 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9413 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9414 "*
9415 { return rs6000_output_load_multiple (operands); }"
9416 [(set_attr "type" "load_ux")
9417 (set_attr "length" "32")])
9419 (define_insn "*ldmsi5"
9420 [(match_parallel 0 "load_multiple_operation"
9421 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9422 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9423 (set (match_operand:SI 3 "gpc_reg_operand" "")
9424 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9425 (set (match_operand:SI 4 "gpc_reg_operand" "")
9426 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9427 (set (match_operand:SI 5 "gpc_reg_operand" "")
9428 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9429 (set (match_operand:SI 6 "gpc_reg_operand" "")
9430 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9431 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9432 "*
9433 { return rs6000_output_load_multiple (operands); }"
9434 [(set_attr "type" "load_ux")
9435 (set_attr "length" "32")])
9437 (define_insn "*ldmsi4"
9438 [(match_parallel 0 "load_multiple_operation"
9439 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9440 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9441 (set (match_operand:SI 3 "gpc_reg_operand" "")
9442 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9443 (set (match_operand:SI 4 "gpc_reg_operand" "")
9444 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9445 (set (match_operand:SI 5 "gpc_reg_operand" "")
9446 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9447 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9448 "*
9449 { return rs6000_output_load_multiple (operands); }"
9450 [(set_attr "type" "load_ux")
9451 (set_attr "length" "32")])
9453 (define_insn "*ldmsi3"
9454 [(match_parallel 0 "load_multiple_operation"
9455 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9456 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9457 (set (match_operand:SI 3 "gpc_reg_operand" "")
9458 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9459 (set (match_operand:SI 4 "gpc_reg_operand" "")
9460 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9461 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9462 "*
9463 { return rs6000_output_load_multiple (operands); }"
9464 [(set_attr "type" "load_ux")
9465 (set_attr "length" "32")])
9467 (define_expand "store_multiple"
9468 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9469 (match_operand:SI 1 "" ""))
9470 (clobber (scratch:SI))
9471 (use (match_operand:SI 2 "" ""))])]
9472 "TARGET_STRING && !TARGET_POWERPC64"
9473 "
9474 {
9475 int regno;
9476 int count;
9477 rtx to;
9478 rtx op0;
9479 int i;
9481 /* Support only storing a constant number of fixed-point registers to
9482 memory and only bother with this if more than two; the machine
9483 doesn't support more than eight. */
9484 if (GET_CODE (operands[2]) != CONST_INT
9485 || INTVAL (operands[2]) <= 2
9486 || INTVAL (operands[2]) > 8
9487 || GET_CODE (operands[0]) != MEM
9488 || GET_CODE (operands[1]) != REG
9489 || REGNO (operands[1]) >= 32)
9490 FAIL;
9492 count = INTVAL (operands[2]);
9493 regno = REGNO (operands[1]);
9495 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9496 to = force_reg (SImode, XEXP (operands[0], 0));
9497 op0 = replace_equiv_address (operands[0], to);
9499 XVECEXP (operands[3], 0, 0)
9500 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9501 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9502 gen_rtx_SCRATCH (SImode));
9504 for (i = 1; i < count; i++)
9505 XVECEXP (operands[3], 0, i + 1)
9506 = gen_rtx_SET (VOIDmode,
9507 adjust_address_nv (op0, SImode, i * 4),
9508 gen_rtx_REG (SImode, regno + i));
9509 }")
9511 (define_insn "*stmsi8"
9512 [(match_parallel 0 "store_multiple_operation"
9513 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9514 (match_operand:SI 2 "gpc_reg_operand" "r"))
9515 (clobber (match_scratch:SI 3 "=X"))
9516 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9517 (match_operand:SI 4 "gpc_reg_operand" "r"))
9518 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9519 (match_operand:SI 5 "gpc_reg_operand" "r"))
9520 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9521 (match_operand:SI 6 "gpc_reg_operand" "r"))
9522 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9523 (match_operand:SI 7 "gpc_reg_operand" "r"))
9524 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9525 (match_operand:SI 8 "gpc_reg_operand" "r"))
9526 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9527 (match_operand:SI 9 "gpc_reg_operand" "r"))
9528 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9529 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9530 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9531 "{stsi|stswi} %2,%1,%O0"
9532 [(set_attr "type" "store_ux")
9533 (set_attr "cell_micro" "always")])
9535 (define_insn "*stmsi7"
9536 [(match_parallel 0 "store_multiple_operation"
9537 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9538 (match_operand:SI 2 "gpc_reg_operand" "r"))
9539 (clobber (match_scratch:SI 3 "=X"))
9540 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9541 (match_operand:SI 4 "gpc_reg_operand" "r"))
9542 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9543 (match_operand:SI 5 "gpc_reg_operand" "r"))
9544 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9545 (match_operand:SI 6 "gpc_reg_operand" "r"))
9546 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9547 (match_operand:SI 7 "gpc_reg_operand" "r"))
9548 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9549 (match_operand:SI 8 "gpc_reg_operand" "r"))
9550 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9551 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9552 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9553 "{stsi|stswi} %2,%1,%O0"
9554 [(set_attr "type" "store_ux")
9555 (set_attr "cell_micro" "always")])
9557 (define_insn "*stmsi6"
9558 [(match_parallel 0 "store_multiple_operation"
9559 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9560 (match_operand:SI 2 "gpc_reg_operand" "r"))
9561 (clobber (match_scratch:SI 3 "=X"))
9562 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9563 (match_operand:SI 4 "gpc_reg_operand" "r"))
9564 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9565 (match_operand:SI 5 "gpc_reg_operand" "r"))
9566 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9567 (match_operand:SI 6 "gpc_reg_operand" "r"))
9568 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9569 (match_operand:SI 7 "gpc_reg_operand" "r"))
9570 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9571 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9572 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9573 "{stsi|stswi} %2,%1,%O0"
9574 [(set_attr "type" "store_ux")
9575 (set_attr "cell_micro" "always")])
9577 (define_insn "*stmsi5"
9578 [(match_parallel 0 "store_multiple_operation"
9579 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9580 (match_operand:SI 2 "gpc_reg_operand" "r"))
9581 (clobber (match_scratch:SI 3 "=X"))
9582 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9583 (match_operand:SI 4 "gpc_reg_operand" "r"))
9584 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9585 (match_operand:SI 5 "gpc_reg_operand" "r"))
9586 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9587 (match_operand:SI 6 "gpc_reg_operand" "r"))
9588 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9589 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9590 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9591 "{stsi|stswi} %2,%1,%O0"
9592 [(set_attr "type" "store_ux")
9593 (set_attr "cell_micro" "always")])
9595 (define_insn "*stmsi4"
9596 [(match_parallel 0 "store_multiple_operation"
9597 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9598 (match_operand:SI 2 "gpc_reg_operand" "r"))
9599 (clobber (match_scratch:SI 3 "=X"))
9600 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9601 (match_operand:SI 4 "gpc_reg_operand" "r"))
9602 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9603 (match_operand:SI 5 "gpc_reg_operand" "r"))
9604 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9605 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9606 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9607 "{stsi|stswi} %2,%1,%O0"
9608 [(set_attr "type" "store_ux")
9609 (set_attr "cell_micro" "always")])
9611 (define_insn "*stmsi3"
9612 [(match_parallel 0 "store_multiple_operation"
9613 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9614 (match_operand:SI 2 "gpc_reg_operand" "r"))
9615 (clobber (match_scratch:SI 3 "=X"))
9616 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9617 (match_operand:SI 4 "gpc_reg_operand" "r"))
9618 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9619 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9620 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9621 "{stsi|stswi} %2,%1,%O0"
9622 [(set_attr "type" "store_ux")
9623 (set_attr "cell_micro" "always")])
9625 (define_insn "*stmsi8_power"
9626 [(match_parallel 0 "store_multiple_operation"
9627 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9628 (match_operand:SI 2 "gpc_reg_operand" "r"))
9629 (clobber (match_scratch:SI 3 "=q"))
9630 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9631 (match_operand:SI 4 "gpc_reg_operand" "r"))
9632 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9633 (match_operand:SI 5 "gpc_reg_operand" "r"))
9634 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9635 (match_operand:SI 6 "gpc_reg_operand" "r"))
9636 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9637 (match_operand:SI 7 "gpc_reg_operand" "r"))
9638 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9639 (match_operand:SI 8 "gpc_reg_operand" "r"))
9640 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9641 (match_operand:SI 9 "gpc_reg_operand" "r"))
9642 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9643 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9644 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9645 "{stsi|stswi} %2,%1,%O0"
9646 [(set_attr "type" "store_ux")
9647 (set_attr "cell_micro" "always")])
9649 (define_insn "*stmsi7_power"
9650 [(match_parallel 0 "store_multiple_operation"
9651 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9652 (match_operand:SI 2 "gpc_reg_operand" "r"))
9653 (clobber (match_scratch:SI 3 "=q"))
9654 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9655 (match_operand:SI 4 "gpc_reg_operand" "r"))
9656 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9657 (match_operand:SI 5 "gpc_reg_operand" "r"))
9658 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9659 (match_operand:SI 6 "gpc_reg_operand" "r"))
9660 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9661 (match_operand:SI 7 "gpc_reg_operand" "r"))
9662 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9663 (match_operand:SI 8 "gpc_reg_operand" "r"))
9664 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9665 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9666 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9667 "{stsi|stswi} %2,%1,%O0"
9668 [(set_attr "type" "store_ux")
9669 (set_attr "cell_micro" "always")])
9671 (define_insn "*stmsi6_power"
9672 [(match_parallel 0 "store_multiple_operation"
9673 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9674 (match_operand:SI 2 "gpc_reg_operand" "r"))
9675 (clobber (match_scratch:SI 3 "=q"))
9676 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9677 (match_operand:SI 4 "gpc_reg_operand" "r"))
9678 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9679 (match_operand:SI 5 "gpc_reg_operand" "r"))
9680 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9681 (match_operand:SI 6 "gpc_reg_operand" "r"))
9682 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9683 (match_operand:SI 7 "gpc_reg_operand" "r"))
9684 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9685 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9686 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9687 "{stsi|stswi} %2,%1,%O0"
9688 [(set_attr "type" "store_ux")
9689 (set_attr "cell_micro" "always")])
9691 (define_insn "*stmsi5_power"
9692 [(match_parallel 0 "store_multiple_operation"
9693 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9694 (match_operand:SI 2 "gpc_reg_operand" "r"))
9695 (clobber (match_scratch:SI 3 "=q"))
9696 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9697 (match_operand:SI 4 "gpc_reg_operand" "r"))
9698 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9699 (match_operand:SI 5 "gpc_reg_operand" "r"))
9700 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9701 (match_operand:SI 6 "gpc_reg_operand" "r"))
9702 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9703 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9704 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9705 "{stsi|stswi} %2,%1,%O0"
9706 [(set_attr "type" "store_ux")
9707 (set_attr "cell_micro" "always")])
9709 (define_insn "*stmsi4_power"
9710 [(match_parallel 0 "store_multiple_operation"
9711 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9712 (match_operand:SI 2 "gpc_reg_operand" "r"))
9713 (clobber (match_scratch:SI 3 "=q"))
9714 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9715 (match_operand:SI 4 "gpc_reg_operand" "r"))
9716 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9717 (match_operand:SI 5 "gpc_reg_operand" "r"))
9718 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9719 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9720 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9721 "{stsi|stswi} %2,%1,%O0"
9722 [(set_attr "type" "store_ux")
9723 (set_attr "cell_micro" "always")])
9725 (define_insn "*stmsi3_power"
9726 [(match_parallel 0 "store_multiple_operation"
9727 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9728 (match_operand:SI 2 "gpc_reg_operand" "r"))
9729 (clobber (match_scratch:SI 3 "=q"))
9730 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9731 (match_operand:SI 4 "gpc_reg_operand" "r"))
9732 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9733 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9734 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9735 "{stsi|stswi} %2,%1,%O0"
9736 [(set_attr "type" "store_ux")
9737 (set_attr "cell_micro" "always")])
9738 \f
9739 (define_expand "setmemsi"
9740 [(parallel [(set (match_operand:BLK 0 "" "")
9741 (match_operand 2 "const_int_operand" ""))
9742 (use (match_operand:SI 1 "" ""))
9743 (use (match_operand:SI 3 "" ""))])]
9744 ""
9745 "
9746 {
9747 /* If value to set is not zero, use the library routine. */
9748 if (operands[2] != const0_rtx)
9749 FAIL;
9751 if (expand_block_clear (operands))
9752 DONE;
9753 else
9754 FAIL;
9755 }")
9757 ;; String/block move insn.
9758 ;; Argument 0 is the destination
9759 ;; Argument 1 is the source
9760 ;; Argument 2 is the length
9761 ;; Argument 3 is the alignment
9763 (define_expand "movmemsi"
9764 [(parallel [(set (match_operand:BLK 0 "" "")
9765 (match_operand:BLK 1 "" ""))
9766 (use (match_operand:SI 2 "" ""))
9767 (use (match_operand:SI 3 "" ""))])]
9768 ""
9769 "
9770 {
9771 if (expand_block_move (operands))
9772 DONE;
9773 else
9774 FAIL;
9775 }")
9777 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9778 ;; register allocator doesn't have a clue about allocating 8 word registers.
9779 ;; rD/rS = r5 is preferred, efficient form.
9780 (define_expand "movmemsi_8reg"
9781 [(parallel [(set (match_operand 0 "" "")
9782 (match_operand 1 "" ""))
9783 (use (match_operand 2 "" ""))
9784 (use (match_operand 3 "" ""))
9785 (clobber (reg:SI 5))
9786 (clobber (reg:SI 6))
9787 (clobber (reg:SI 7))
9788 (clobber (reg:SI 8))
9789 (clobber (reg:SI 9))
9790 (clobber (reg:SI 10))
9791 (clobber (reg:SI 11))
9792 (clobber (reg:SI 12))
9793 (clobber (match_scratch:SI 4 ""))])]
9794 "TARGET_STRING"
9795 "")
9797 (define_insn ""
9798 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9799 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9800 (use (match_operand:SI 2 "immediate_operand" "i"))
9801 (use (match_operand:SI 3 "immediate_operand" "i"))
9802 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9803 (clobber (reg:SI 6))
9804 (clobber (reg:SI 7))
9805 (clobber (reg:SI 8))
9806 (clobber (reg:SI 9))
9807 (clobber (reg:SI 10))
9808 (clobber (reg:SI 11))
9809 (clobber (reg:SI 12))
9810 (clobber (match_scratch:SI 5 "=q"))]
9811 "TARGET_STRING && TARGET_POWER
9812 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9813 || INTVAL (operands[2]) == 0)
9814 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9815 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9816 && REGNO (operands[4]) == 5"
9817 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9818 [(set_attr "type" "store_ux")
9819 (set_attr "cell_micro" "always")
9820 (set_attr "length" "8")])
9822 (define_insn ""
9823 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9824 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9825 (use (match_operand:SI 2 "immediate_operand" "i"))
9826 (use (match_operand:SI 3 "immediate_operand" "i"))
9827 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9828 (clobber (reg:SI 6))
9829 (clobber (reg:SI 7))
9830 (clobber (reg:SI 8))
9831 (clobber (reg:SI 9))
9832 (clobber (reg:SI 10))
9833 (clobber (reg:SI 11))
9834 (clobber (reg:SI 12))
9835 (clobber (match_scratch:SI 5 "=X"))]
9836 "TARGET_STRING && ! TARGET_POWER
9837 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9838 || INTVAL (operands[2]) == 0)
9839 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9840 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9841 && REGNO (operands[4]) == 5"
9842 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9843 [(set_attr "type" "store_ux")
9844 (set_attr "cell_micro" "always")
9845 (set_attr "length" "8")])
9847 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9848 ;; register allocator doesn't have a clue about allocating 6 word registers.
9849 ;; rD/rS = r5 is preferred, efficient form.
9850 (define_expand "movmemsi_6reg"
9851 [(parallel [(set (match_operand 0 "" "")
9852 (match_operand 1 "" ""))
9853 (use (match_operand 2 "" ""))
9854 (use (match_operand 3 "" ""))
9855 (clobber (reg:SI 5))
9856 (clobber (reg:SI 6))
9857 (clobber (reg:SI 7))
9858 (clobber (reg:SI 8))
9859 (clobber (reg:SI 9))
9860 (clobber (reg:SI 10))
9861 (clobber (match_scratch:SI 4 ""))])]
9862 "TARGET_STRING"
9863 "")
9865 (define_insn ""
9866 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9867 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9868 (use (match_operand:SI 2 "immediate_operand" "i"))
9869 (use (match_operand:SI 3 "immediate_operand" "i"))
9870 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9871 (clobber (reg:SI 6))
9872 (clobber (reg:SI 7))
9873 (clobber (reg:SI 8))
9874 (clobber (reg:SI 9))
9875 (clobber (reg:SI 10))
9876 (clobber (match_scratch:SI 5 "=q"))]
9877 "TARGET_STRING && TARGET_POWER
9878 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9879 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9880 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9881 && REGNO (operands[4]) == 5"
9882 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9883 [(set_attr "type" "store_ux")
9884 (set_attr "cell_micro" "always")
9885 (set_attr "length" "8")])
9887 (define_insn ""
9888 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9889 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9890 (use (match_operand:SI 2 "immediate_operand" "i"))
9891 (use (match_operand:SI 3 "immediate_operand" "i"))
9892 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9893 (clobber (reg:SI 6))
9894 (clobber (reg:SI 7))
9895 (clobber (reg:SI 8))
9896 (clobber (reg:SI 9))
9897 (clobber (reg:SI 10))
9898 (clobber (match_scratch:SI 5 "=X"))]
9899 "TARGET_STRING && ! TARGET_POWER
9900 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9901 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9902 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9903 && REGNO (operands[4]) == 5"
9904 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9905 [(set_attr "type" "store_ux")
9906 (set_attr "cell_micro" "always")
9907 (set_attr "length" "8")])
9909 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9910 ;; problems with TImode.
9911 ;; rD/rS = r5 is preferred, efficient form.
9912 (define_expand "movmemsi_4reg"
9913 [(parallel [(set (match_operand 0 "" "")
9914 (match_operand 1 "" ""))
9915 (use (match_operand 2 "" ""))
9916 (use (match_operand 3 "" ""))
9917 (clobber (reg:SI 5))
9918 (clobber (reg:SI 6))
9919 (clobber (reg:SI 7))
9920 (clobber (reg:SI 8))
9921 (clobber (match_scratch:SI 4 ""))])]
9922 "TARGET_STRING"
9923 "")
9925 (define_insn ""
9926 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9927 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9928 (use (match_operand:SI 2 "immediate_operand" "i"))
9929 (use (match_operand:SI 3 "immediate_operand" "i"))
9930 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9931 (clobber (reg:SI 6))
9932 (clobber (reg:SI 7))
9933 (clobber (reg:SI 8))
9934 (clobber (match_scratch:SI 5 "=q"))]
9935 "TARGET_STRING && TARGET_POWER
9936 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9937 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9938 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9939 && REGNO (operands[4]) == 5"
9940 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9941 [(set_attr "type" "store_ux")
9942 (set_attr "cell_micro" "always")
9943 (set_attr "length" "8")])
9945 (define_insn ""
9946 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9947 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9948 (use (match_operand:SI 2 "immediate_operand" "i"))
9949 (use (match_operand:SI 3 "immediate_operand" "i"))
9950 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9951 (clobber (reg:SI 6))
9952 (clobber (reg:SI 7))
9953 (clobber (reg:SI 8))
9954 (clobber (match_scratch:SI 5 "=X"))]
9955 "TARGET_STRING && ! TARGET_POWER
9956 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9957 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9958 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9959 && REGNO (operands[4]) == 5"
9960 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9961 [(set_attr "type" "store_ux")
9962 (set_attr "cell_micro" "always")
9963 (set_attr "length" "8")])
9965 ;; Move up to 8 bytes at a time.
9966 (define_expand "movmemsi_2reg"
9967 [(parallel [(set (match_operand 0 "" "")
9968 (match_operand 1 "" ""))
9969 (use (match_operand 2 "" ""))
9970 (use (match_operand 3 "" ""))
9971 (clobber (match_scratch:DI 4 ""))
9972 (clobber (match_scratch:SI 5 ""))])]
9973 "TARGET_STRING && ! TARGET_POWERPC64"
9974 "")
9976 (define_insn ""
9977 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9978 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9979 (use (match_operand:SI 2 "immediate_operand" "i"))
9980 (use (match_operand:SI 3 "immediate_operand" "i"))
9981 (clobber (match_scratch:DI 4 "=&r"))
9982 (clobber (match_scratch:SI 5 "=q"))]
9983 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9984 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9985 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9986 [(set_attr "type" "store_ux")
9987 (set_attr "cell_micro" "always")
9988 (set_attr "length" "8")])
9990 (define_insn ""
9991 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9992 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9993 (use (match_operand:SI 2 "immediate_operand" "i"))
9994 (use (match_operand:SI 3 "immediate_operand" "i"))
9995 (clobber (match_scratch:DI 4 "=&r"))
9996 (clobber (match_scratch:SI 5 "=X"))]
9997 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9998 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9999 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10000 [(set_attr "type" "store_ux")
10001 (set_attr "cell_micro" "always")
10002 (set_attr "length" "8")])
10004 ;; Move up to 4 bytes at a time.
10005 (define_expand "movmemsi_1reg"
10006 [(parallel [(set (match_operand 0 "" "")
10007 (match_operand 1 "" ""))
10008 (use (match_operand 2 "" ""))
10009 (use (match_operand 3 "" ""))
10010 (clobber (match_scratch:SI 4 ""))
10011 (clobber (match_scratch:SI 5 ""))])]
10012 "TARGET_STRING"
10013 "")
10015 (define_insn ""
10016 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10017 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10018 (use (match_operand:SI 2 "immediate_operand" "i"))
10019 (use (match_operand:SI 3 "immediate_operand" "i"))
10020 (clobber (match_scratch:SI 4 "=&r"))
10021 (clobber (match_scratch:SI 5 "=q"))]
10022 "TARGET_STRING && TARGET_POWER
10023 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10024 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10025 [(set_attr "type" "store_ux")
10026 (set_attr "cell_micro" "always")
10027 (set_attr "length" "8")])
10029 (define_insn ""
10030 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10031 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10032 (use (match_operand:SI 2 "immediate_operand" "i"))
10033 (use (match_operand:SI 3 "immediate_operand" "i"))
10034 (clobber (match_scratch:SI 4 "=&r"))
10035 (clobber (match_scratch:SI 5 "=X"))]
10036 "TARGET_STRING && ! TARGET_POWER
10037 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10038 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10039 [(set_attr "type" "store_ux")
10040 (set_attr "cell_micro" "always")
10041 (set_attr "length" "8")])
10042 \f
10043 ;; Define insns that do load or store with update. Some of these we can
10044 ;; get by using pre-decrement or pre-increment, but the hardware can also
10045 ;; do cases where the increment is not the size of the object.
10046 ;;
10047 ;; In all these cases, we use operands 0 and 1 for the register being
10048 ;; incremented because those are the operands that local-alloc will
10049 ;; tie and these are the pair most likely to be tieable (and the ones
10050 ;; that will benefit the most).
10052 (define_insn "*movdi_update1"
10053 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10054 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10055 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10056 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10057 (plus:DI (match_dup 1) (match_dup 2)))]
10058 "TARGET_POWERPC64 && TARGET_UPDATE
10059 && (!avoiding_indexed_address_p (DImode)
10060 || !gpc_reg_operand (operands[2], DImode))"
10061 "@
10062 ldux %3,%0,%2
10063 ldu %3,%2(%0)"
10064 [(set_attr "type" "load_ux,load_u")])
10066 (define_insn "movdi_<mode>_update"
10067 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10068 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10069 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10070 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10071 (plus:P (match_dup 1) (match_dup 2)))]
10072 "TARGET_POWERPC64 && TARGET_UPDATE
10073 && (!avoiding_indexed_address_p (Pmode)
10074 || !gpc_reg_operand (operands[2], Pmode)
10075 || (REG_P (operands[0])
10076 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10077 "@
10078 stdux %3,%0,%2
10079 stdu %3,%2(%0)"
10080 [(set_attr "type" "store_ux,store_u")])
10082 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10083 ;; needed for stack allocation, even if the user passes -mno-update.
10084 (define_insn "movdi_<mode>_update_stack"
10085 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10086 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10087 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10088 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10089 (plus:P (match_dup 1) (match_dup 2)))]
10090 "TARGET_POWERPC64"
10091 "@
10092 stdux %3,%0,%2
10093 stdu %3,%2(%0)"
10094 [(set_attr "type" "store_ux,store_u")])
10096 (define_insn "*movsi_update1"
10097 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10098 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10099 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10100 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10101 (plus:SI (match_dup 1) (match_dup 2)))]
10102 "TARGET_UPDATE
10103 && (!avoiding_indexed_address_p (SImode)
10104 || !gpc_reg_operand (operands[2], SImode))"
10105 "@
10106 {lux|lwzux} %3,%0,%2
10107 {lu|lwzu} %3,%2(%0)"
10108 [(set_attr "type" "load_ux,load_u")])
10110 (define_insn "*movsi_update2"
10111 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10112 (sign_extend:DI
10113 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10114 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10115 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10116 (plus:DI (match_dup 1) (match_dup 2)))]
10117 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10118 && !avoiding_indexed_address_p (DImode)"
10119 "lwaux %3,%0,%2"
10120 [(set_attr "type" "load_ext_ux")])
10122 (define_insn "movsi_update"
10123 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10124 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10125 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10126 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10127 (plus:SI (match_dup 1) (match_dup 2)))]
10128 "TARGET_UPDATE
10129 && (!avoiding_indexed_address_p (SImode)
10130 || !gpc_reg_operand (operands[2], SImode)
10131 || (REG_P (operands[0])
10132 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10133 "@
10134 {stux|stwux} %3,%0,%2
10135 {stu|stwu} %3,%2(%0)"
10136 [(set_attr "type" "store_ux,store_u")])
10138 ;; This is an unconditional pattern; needed for stack allocation, even
10139 ;; if the user passes -mno-update.
10140 (define_insn "movsi_update_stack"
10141 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10142 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10143 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10144 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10145 (plus:SI (match_dup 1) (match_dup 2)))]
10146 ""
10147 "@
10148 {stux|stwux} %3,%0,%2
10149 {stu|stwu} %3,%2(%0)"
10150 [(set_attr "type" "store_ux,store_u")])
10152 (define_insn "*movhi_update1"
10153 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10154 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10155 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10156 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10157 (plus:SI (match_dup 1) (match_dup 2)))]
10158 "TARGET_UPDATE
10159 && (!avoiding_indexed_address_p (SImode)
10160 || !gpc_reg_operand (operands[2], SImode))"
10161 "@
10162 lhzux %3,%0,%2
10163 lhzu %3,%2(%0)"
10164 [(set_attr "type" "load_ux,load_u")])
10166 (define_insn "*movhi_update2"
10167 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10168 (zero_extend:SI
10169 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10170 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10171 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10172 (plus:SI (match_dup 1) (match_dup 2)))]
10173 "TARGET_UPDATE
10174 && (!avoiding_indexed_address_p (SImode)
10175 || !gpc_reg_operand (operands[2], SImode))"
10176 "@
10177 lhzux %3,%0,%2
10178 lhzu %3,%2(%0)"
10179 [(set_attr "type" "load_ux,load_u")])
10181 (define_insn "*movhi_update3"
10182 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10183 (sign_extend:SI
10184 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10185 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10186 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10187 (plus:SI (match_dup 1) (match_dup 2)))]
10188 "TARGET_UPDATE && rs6000_gen_cell_microcode
10189 && (!avoiding_indexed_address_p (SImode)
10190 || !gpc_reg_operand (operands[2], SImode))"
10191 "@
10192 lhaux %3,%0,%2
10193 lhau %3,%2(%0)"
10194 [(set_attr "type" "load_ext_ux,load_ext_u")])
10196 (define_insn "*movhi_update4"
10197 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10198 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10199 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10200 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10201 (plus:SI (match_dup 1) (match_dup 2)))]
10202 "TARGET_UPDATE
10203 && (!avoiding_indexed_address_p (SImode)
10204 || !gpc_reg_operand (operands[2], SImode))"
10205 "@
10206 sthux %3,%0,%2
10207 sthu %3,%2(%0)"
10208 [(set_attr "type" "store_ux,store_u")])
10210 (define_insn "*movqi_update1"
10211 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10212 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10213 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10214 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10215 (plus:SI (match_dup 1) (match_dup 2)))]
10216 "TARGET_UPDATE
10217 && (!avoiding_indexed_address_p (SImode)
10218 || !gpc_reg_operand (operands[2], SImode))"
10219 "@
10220 lbzux %3,%0,%2
10221 lbzu %3,%2(%0)"
10222 [(set_attr "type" "load_ux,load_u")])
10224 (define_insn "*movqi_update2"
10225 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10226 (zero_extend:SI
10227 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10228 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10229 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10230 (plus:SI (match_dup 1) (match_dup 2)))]
10231 "TARGET_UPDATE
10232 && (!avoiding_indexed_address_p (SImode)
10233 || !gpc_reg_operand (operands[2], SImode))"
10234 "@
10235 lbzux %3,%0,%2
10236 lbzu %3,%2(%0)"
10237 [(set_attr "type" "load_ux,load_u")])
10239 (define_insn "*movqi_update3"
10240 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10241 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10242 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10243 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10244 (plus:SI (match_dup 1) (match_dup 2)))]
10245 "TARGET_UPDATE
10246 && (!avoiding_indexed_address_p (SImode)
10247 || !gpc_reg_operand (operands[2], SImode))"
10248 "@
10249 stbux %3,%0,%2
10250 stbu %3,%2(%0)"
10251 [(set_attr "type" "store_ux,store_u")])
10253 (define_insn "*movsf_update1"
10254 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10255 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10256 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10257 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10258 (plus:SI (match_dup 1) (match_dup 2)))]
10259 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10260 && (!avoiding_indexed_address_p (SImode)
10261 || !gpc_reg_operand (operands[2], SImode))"
10262 "@
10263 lfsux %3,%0,%2
10264 lfsu %3,%2(%0)"
10265 [(set_attr "type" "fpload_ux,fpload_u")])
10267 (define_insn "*movsf_update2"
10268 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10269 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10270 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10271 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10272 (plus:SI (match_dup 1) (match_dup 2)))]
10273 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10274 && (!avoiding_indexed_address_p (SImode)
10275 || !gpc_reg_operand (operands[2], SImode))"
10276 "@
10277 stfsux %3,%0,%2
10278 stfsu %3,%2(%0)"
10279 [(set_attr "type" "fpstore_ux,fpstore_u")])
10281 (define_insn "*movsf_update3"
10282 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10283 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10284 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10285 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10286 (plus:SI (match_dup 1) (match_dup 2)))]
10287 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10288 && (!avoiding_indexed_address_p (SImode)
10289 || !gpc_reg_operand (operands[2], SImode))"
10290 "@
10291 {lux|lwzux} %3,%0,%2
10292 {lu|lwzu} %3,%2(%0)"
10293 [(set_attr "type" "load_ux,load_u")])
10295 (define_insn "*movsf_update4"
10296 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10297 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10298 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10299 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10300 (plus:SI (match_dup 1) (match_dup 2)))]
10301 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10302 && (!avoiding_indexed_address_p (SImode)
10303 || !gpc_reg_operand (operands[2], SImode))"
10304 "@
10305 {stux|stwux} %3,%0,%2
10306 {stu|stwu} %3,%2(%0)"
10307 [(set_attr "type" "store_ux,store_u")])
10309 (define_insn "*movdf_update1"
10310 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10311 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10312 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10313 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10314 (plus:SI (match_dup 1) (match_dup 2)))]
10315 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10316 && (!avoiding_indexed_address_p (SImode)
10317 || !gpc_reg_operand (operands[2], SImode))"
10318 "@
10319 lfdux %3,%0,%2
10320 lfdu %3,%2(%0)"
10321 [(set_attr "type" "fpload_ux,fpload_u")])
10323 (define_insn "*movdf_update2"
10324 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10325 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10326 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10327 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10328 (plus:SI (match_dup 1) (match_dup 2)))]
10329 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10330 && (!avoiding_indexed_address_p (SImode)
10331 || !gpc_reg_operand (operands[2], SImode))"
10332 "@
10333 stfdux %3,%0,%2
10334 stfdu %3,%2(%0)"
10335 [(set_attr "type" "fpstore_ux,fpstore_u")])
10337 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10339 (define_insn "*lfq_power2"
10340 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10341 (match_operand:V2DF 1 "memory_operand" ""))]
10342 "TARGET_POWER2
10343 && TARGET_HARD_FLOAT && TARGET_FPRS"
10344 "lfq%U1%X1 %0,%1")
10346 (define_peephole2
10347 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10348 (match_operand:DF 1 "memory_operand" ""))
10349 (set (match_operand:DF 2 "gpc_reg_operand" "")
10350 (match_operand:DF 3 "memory_operand" ""))]
10351 "TARGET_POWER2
10352 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10353 && registers_ok_for_quad_peep (operands[0], operands[2])
10354 && mems_ok_for_quad_peep (operands[1], operands[3])"
10355 [(set (match_dup 0)
10356 (match_dup 1))]
10357 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10358 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10360 (define_insn "*stfq_power2"
10361 [(set (match_operand:V2DF 0 "memory_operand" "")
10362 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10363 "TARGET_POWER2
10364 && TARGET_HARD_FLOAT && TARGET_FPRS"
10365 "stfq%U0%X0 %1,%0")
10368 (define_peephole2
10369 [(set (match_operand:DF 0 "memory_operand" "")
10370 (match_operand:DF 1 "gpc_reg_operand" ""))
10371 (set (match_operand:DF 2 "memory_operand" "")
10372 (match_operand:DF 3 "gpc_reg_operand" ""))]
10373 "TARGET_POWER2
10374 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10375 && registers_ok_for_quad_peep (operands[1], operands[3])
10376 && mems_ok_for_quad_peep (operands[0], operands[2])"
10377 [(set (match_dup 0)
10378 (match_dup 1))]
10379 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10380 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10382 ;; After inserting conditional returns we can sometimes have
10383 ;; unnecessary register moves. Unfortunately we cannot have a
10384 ;; modeless peephole here, because some single SImode sets have early
10385 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10386 ;; sequences, using get_attr_length here will smash the operands
10387 ;; array. Neither is there an early_cobbler_p predicate.
10388 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10389 (define_peephole2
10390 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10391 (match_operand:DF 1 "any_operand" ""))
10392 (set (match_operand:DF 2 "gpc_reg_operand" "")
10393 (match_dup 0))]
10394 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10395 && peep2_reg_dead_p (2, operands[0])"
10396 [(set (match_dup 2) (match_dup 1))])
10398 (define_peephole2
10399 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10400 (match_operand:SF 1 "any_operand" ""))
10401 (set (match_operand:SF 2 "gpc_reg_operand" "")
10402 (match_dup 0))]
10403 "peep2_reg_dead_p (2, operands[0])"
10404 [(set (match_dup 2) (match_dup 1))])
10406 \f
10407 ;; TLS support.
10409 ;; Mode attributes for different ABIs.
10410 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10411 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10412 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10413 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10415 (define_insn "tls_gd_aix<TLSmode:tls_abi_suffix>"
10416 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10417 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10418 (match_operand 4 "" "g")))
10419 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10420 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10421 UNSPEC_TLSGD)
10422 (clobber (reg:SI LR_REGNO))]
10423 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10424 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10425 [(set_attr "type" "two")
10426 (set_attr "length" "12")])
10428 (define_insn "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10429 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10430 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10431 (match_operand 4 "" "g")))
10432 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10433 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10434 UNSPEC_TLSGD)
10435 (clobber (reg:SI LR_REGNO))]
10436 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10437 {
10438 if (flag_pic)
10439 {
10440 if (TARGET_SECURE_PLT && flag_pic == 2)
10441 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10442 else
10443 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10444 }
10445 else
10446 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10447 }
10448 [(set_attr "type" "two")
10449 (set_attr "length" "8")])
10451 (define_insn "tls_ld_aix<TLSmode:tls_abi_suffix>"
10452 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10453 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10454 (match_operand 3 "" "g")))
10455 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10456 UNSPEC_TLSLD)
10457 (clobber (reg:SI LR_REGNO))]
10458 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10459 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
10460 [(set_attr "length" "12")])
10462 (define_insn "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10463 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10464 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10465 (match_operand 3 "" "g")))
10466 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10467 UNSPEC_TLSLD)
10468 (clobber (reg:SI LR_REGNO))]
10469 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10470 {
10471 if (flag_pic)
10472 {
10473 if (TARGET_SECURE_PLT && flag_pic == 2)
10474 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10475 else
10476 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10477 }
10478 else
10479 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10480 }
10481 [(set_attr "length" "8")])
10483 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10484 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10485 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10486 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10487 UNSPEC_TLSDTPREL))]
10488 "HAVE_AS_TLS"
10489 "addi %0,%1,%2@dtprel")
10491 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10492 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10493 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10494 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10495 UNSPEC_TLSDTPRELHA))]
10496 "HAVE_AS_TLS"
10497 "addis %0,%1,%2@dtprel@ha")
10499 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10500 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10501 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10502 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10503 UNSPEC_TLSDTPRELLO))]
10504 "HAVE_AS_TLS"
10505 "addi %0,%1,%2@dtprel@l")
10507 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10508 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10509 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10510 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10511 UNSPEC_TLSGOTDTPREL))]
10512 "HAVE_AS_TLS"
10513 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10515 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10516 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10517 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10518 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10519 UNSPEC_TLSTPREL))]
10520 "HAVE_AS_TLS"
10521 "addi %0,%1,%2@tprel")
10523 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10524 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10525 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10526 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10527 UNSPEC_TLSTPRELHA))]
10528 "HAVE_AS_TLS"
10529 "addis %0,%1,%2@tprel@ha")
10531 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10532 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10533 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10534 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10535 UNSPEC_TLSTPRELLO))]
10536 "HAVE_AS_TLS"
10537 "addi %0,%1,%2@tprel@l")
10539 ;; "b" output constraint here and on tls_tls input to support linker tls
10540 ;; optimization. The linker may edit the instructions emitted by a
10541 ;; tls_got_tprel/tls_tls pair to addis,addi.
10542 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10543 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10544 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10545 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10546 UNSPEC_TLSGOTTPREL))]
10547 "HAVE_AS_TLS"
10548 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10550 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10551 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10552 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10553 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10554 UNSPEC_TLSTLS))]
10555 "HAVE_AS_TLS"
10556 "add %0,%1,%2@tls")
10558 \f
10559 ;; Next come insns related to the calling sequence.
10560 ;;
10561 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10562 ;; We move the back-chain and decrement the stack pointer.
10564 (define_expand "allocate_stack"
10565 [(set (match_operand 0 "gpc_reg_operand" "")
10566 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10567 (set (reg 1)
10568 (minus (reg 1) (match_dup 1)))]
10569 ""
10570 "
10571 { rtx chain = gen_reg_rtx (Pmode);
10572 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10573 rtx neg_op0;
10574 rtx insn, par, set, mem;
10576 emit_move_insn (chain, stack_bot);
10578 /* Check stack bounds if necessary. */
10579 if (crtl->limit_stack)
10580 {
10581 rtx available;
10582 available = expand_binop (Pmode, sub_optab,
10583 stack_pointer_rtx, stack_limit_rtx,
10584 NULL_RTX, 1, OPTAB_WIDEN);
10585 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10586 }
10588 if (GET_CODE (operands[1]) != CONST_INT
10589 || INTVAL (operands[1]) < -32767
10590 || INTVAL (operands[1]) > 32768)
10591 {
10592 neg_op0 = gen_reg_rtx (Pmode);
10593 if (TARGET_32BIT)
10594 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10595 else
10596 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10597 }
10598 else
10599 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10601 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10602 : gen_movdi_di_update_stack))
10603 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10604 chain));
10605 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10606 it now and set the alias set/attributes. The above gen_*_update
10607 calls will generate a PARALLEL with the MEM set being the first
10608 operation. */
10609 par = PATTERN (insn);
10610 gcc_assert (GET_CODE (par) == PARALLEL);
10611 set = XVECEXP (par, 0, 0);
10612 gcc_assert (GET_CODE (set) == SET);
10613 mem = SET_DEST (set);
10614 gcc_assert (MEM_P (mem));
10615 MEM_NOTRAP_P (mem) = 1;
10616 set_mem_alias_set (mem, get_frame_alias_set ());
10618 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10619 DONE;
10620 }")
10622 ;; These patterns say how to save and restore the stack pointer. We need not
10623 ;; save the stack pointer at function level since we are careful to
10624 ;; preserve the backchain. At block level, we have to restore the backchain
10625 ;; when we restore the stack pointer.
10626 ;;
10627 ;; For nonlocal gotos, we must save both the stack pointer and its
10628 ;; backchain and restore both. Note that in the nonlocal case, the
10629 ;; save area is a memory location.
10631 (define_expand "save_stack_function"
10632 [(match_operand 0 "any_operand" "")
10633 (match_operand 1 "any_operand" "")]
10634 ""
10635 "DONE;")
10637 (define_expand "restore_stack_function"
10638 [(match_operand 0 "any_operand" "")
10639 (match_operand 1 "any_operand" "")]
10640 ""
10641 "DONE;")
10643 ;; Adjust stack pointer (op0) to a new value (op1).
10644 ;; First copy old stack backchain to new location, and ensure that the
10645 ;; scheduler won't reorder the sp assignment before the backchain write.
10646 (define_expand "restore_stack_block"
10647 [(set (match_dup 2) (match_dup 3))
10648 (set (match_dup 4) (match_dup 2))
10649 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10650 (set (match_operand 0 "register_operand" "")
10651 (match_operand 1 "register_operand" ""))]
10652 ""
10653 "
10654 {
10655 operands[1] = force_reg (Pmode, operands[1]);
10656 operands[2] = gen_reg_rtx (Pmode);
10657 operands[3] = gen_frame_mem (Pmode, operands[0]);
10658 operands[4] = gen_frame_mem (Pmode, operands[1]);
10659 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10660 }")
10662 (define_expand "save_stack_nonlocal"
10663 [(set (match_dup 3) (match_dup 4))
10664 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10665 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10666 ""
10667 "
10668 {
10669 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10671 /* Copy the backchain to the first word, sp to the second. */
10672 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10673 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10674 operands[3] = gen_reg_rtx (Pmode);
10675 operands[4] = gen_frame_mem (Pmode, operands[1]);
10676 }")
10678 (define_expand "restore_stack_nonlocal"
10679 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10680 (set (match_dup 3) (match_dup 4))
10681 (set (match_dup 5) (match_dup 2))
10682 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10683 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10684 ""
10685 "
10686 {
10687 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10689 /* Restore the backchain from the first word, sp from the second. */
10690 operands[2] = gen_reg_rtx (Pmode);
10691 operands[3] = gen_reg_rtx (Pmode);
10692 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10693 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10694 operands[5] = gen_frame_mem (Pmode, operands[3]);
10695 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10696 }")
10697 \f
10698 ;; TOC register handling.
10700 ;; Code to initialize the TOC register...
10702 (define_insn "load_toc_aix_si"
10703 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10704 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10705 (use (reg:SI 2))])]
10706 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10707 "*
10708 {
10709 char buf[30];
10710 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10711 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10712 operands[2] = gen_rtx_REG (Pmode, 2);
10713 return \"{l|lwz} %0,%1(%2)\";
10714 }"
10715 [(set_attr "type" "load")])
10717 (define_insn "load_toc_aix_di"
10718 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10719 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10720 (use (reg:DI 2))])]
10721 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10722 "*
10723 {
10724 char buf[30];
10725 #ifdef TARGET_RELOCATABLE
10726 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10727 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10728 #else
10729 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10730 #endif
10731 if (TARGET_ELF)
10732 strcat (buf, \"@toc\");
10733 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10734 operands[2] = gen_rtx_REG (Pmode, 2);
10735 return \"ld %0,%1(%2)\";
10736 }"
10737 [(set_attr "type" "load")])
10739 (define_insn "load_toc_v4_pic_si"
10740 [(set (reg:SI LR_REGNO)
10741 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10742 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10743 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10744 [(set_attr "type" "branch")
10745 (set_attr "length" "4")])
10747 (define_insn "load_toc_v4_PIC_1"
10748 [(set (reg:SI LR_REGNO)
10749 (match_operand:SI 0 "immediate_operand" "s"))
10750 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10751 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10752 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10753 "bcl 20,31,%0\\n%0:"
10754 [(set_attr "type" "branch")
10755 (set_attr "length" "4")])
10757 (define_insn "load_toc_v4_PIC_1b"
10758 [(set (reg:SI LR_REGNO)
10759 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10760 UNSPEC_TOCPTR))]
10761 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10762 "bcl 20,31,$+8\\n\\t.long %0-$"
10763 [(set_attr "type" "branch")
10764 (set_attr "length" "8")])
10766 (define_insn "load_toc_v4_PIC_2"
10767 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10768 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10769 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10770 (match_operand:SI 3 "immediate_operand" "s")))))]
10771 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10772 "{l|lwz} %0,%2-%3(%1)"
10773 [(set_attr "type" "load")])
10775 (define_insn "load_toc_v4_PIC_3b"
10776 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10777 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10778 (high:SI
10779 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10780 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10781 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10782 "{cau|addis} %0,%1,%2-%3@ha")
10784 (define_insn "load_toc_v4_PIC_3c"
10785 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10786 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10787 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10788 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10789 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10790 "{cal|addi} %0,%1,%2-%3@l")
10792 ;; If the TOC is shared over a translation unit, as happens with all
10793 ;; the kinds of PIC that we support, we need to restore the TOC
10794 ;; pointer only when jumping over units of translation.
10795 ;; On Darwin, we need to reload the picbase.
10797 (define_expand "builtin_setjmp_receiver"
10798 [(use (label_ref (match_operand 0 "" "")))]
10799 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10800 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10801 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10802 "
10803 {
10804 #if TARGET_MACHO
10805 if (DEFAULT_ABI == ABI_DARWIN)
10806 {
10807 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10808 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10809 rtx tmplabrtx;
10810 char tmplab[20];
10812 crtl->uses_pic_offset_table = 1;
10813 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10814 CODE_LABEL_NUMBER (operands[0]));
10815 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10817 emit_insn (gen_load_macho_picbase (tmplabrtx));
10818 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10819 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10820 }
10821 else
10822 #endif
10823 rs6000_emit_load_toc_table (FALSE);
10824 DONE;
10825 }")
10827 ;; Elf specific ways of loading addresses for non-PIC code.
10828 ;; The output of this could be r0, but we make a very strong
10829 ;; preference for a base register because it will usually
10830 ;; be needed there.
10831 (define_insn "elf_high"
10832 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10833 (high:SI (match_operand 1 "" "")))]
10834 "TARGET_ELF && ! TARGET_64BIT"
10835 "{liu|lis} %0,%1@ha")
10837 (define_insn "elf_low"
10838 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10839 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10840 (match_operand 2 "" "")))]
10841 "TARGET_ELF && ! TARGET_64BIT"
10842 "@
10843 {cal|la} %0,%2@l(%1)
10844 {ai|addic} %0,%1,%K2")
10845 \f
10846 ;; A function pointer under AIX is a pointer to a data area whose first word
10847 ;; contains the actual address of the function, whose second word contains a
10848 ;; pointer to its TOC, and whose third word contains a value to place in the
10849 ;; static chain register (r11). Note that if we load the static chain, our
10850 ;; "trampoline" need not have any executable code.
10852 (define_expand "call_indirect_aix32"
10853 [(set (match_dup 2)
10854 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10855 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10856 (reg:SI 2))
10857 (set (reg:SI 11)
10858 (mem:SI (plus:SI (match_dup 0)
10859 (const_int 8))))
10860 (parallel [(call (mem:SI (match_dup 2))
10861 (match_operand 1 "" ""))
10862 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
10863 (use (reg:SI 11))
10864 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10865 (clobber (reg:SI LR_REGNO))])]
10866 "TARGET_32BIT"
10867 "
10868 { operands[2] = gen_reg_rtx (SImode); }")
10870 (define_expand "call_indirect_aix64"
10871 [(set (match_dup 2)
10872 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10873 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10874 (reg:DI 2))
10875 (set (reg:DI 11)
10876 (mem:DI (plus:DI (match_dup 0)
10877 (const_int 16))))
10878 (parallel [(call (mem:SI (match_dup 2))
10879 (match_operand 1 "" ""))
10880 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
10881 (use (reg:DI 11))
10882 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10883 (clobber (reg:SI LR_REGNO))])]
10884 "TARGET_64BIT"
10885 "
10886 { operands[2] = gen_reg_rtx (DImode); }")
10888 (define_expand "call_value_indirect_aix32"
10889 [(set (match_dup 3)
10890 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10891 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10892 (reg:SI 2))
10893 (set (reg:SI 11)
10894 (mem:SI (plus:SI (match_dup 1)
10895 (const_int 8))))
10896 (parallel [(set (match_operand 0 "" "")
10897 (call (mem:SI (match_dup 3))
10898 (match_operand 2 "" "")))
10899 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10900 (use (reg:SI 11))
10901 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10902 (clobber (reg:SI LR_REGNO))])]
10903 "TARGET_32BIT"
10904 "
10905 { operands[3] = gen_reg_rtx (SImode); }")
10907 (define_expand "call_value_indirect_aix64"
10908 [(set (match_dup 3)
10909 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10910 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10911 (reg:DI 2))
10912 (set (reg:DI 11)
10913 (mem:DI (plus:DI (match_dup 1)
10914 (const_int 16))))
10915 (parallel [(set (match_operand 0 "" "")
10916 (call (mem:SI (match_dup 3))
10917 (match_operand 2 "" "")))
10918 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
10919 (use (reg:DI 11))
10920 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10921 (clobber (reg:SI LR_REGNO))])]
10922 "TARGET_64BIT"
10923 "
10924 { operands[3] = gen_reg_rtx (DImode); }")
10926 ;; Now the definitions for the call and call_value insns
10927 (define_expand "call"
10928 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10929 (match_operand 1 "" ""))
10930 (use (match_operand 2 "" ""))
10931 (clobber (reg:SI LR_REGNO))])]
10932 ""
10933 "
10934 {
10935 #if TARGET_MACHO
10936 if (MACHOPIC_INDIRECT)
10937 operands[0] = machopic_indirect_call_target (operands[0]);
10938 #endif
10940 gcc_assert (GET_CODE (operands[0]) == MEM);
10941 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10943 operands[0] = XEXP (operands[0], 0);
10945 if (GET_CODE (operands[0]) != SYMBOL_REF
10946 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10947 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10948 {
10949 if (INTVAL (operands[2]) & CALL_LONG)
10950 operands[0] = rs6000_longcall_ref (operands[0]);
10952 switch (DEFAULT_ABI)
10953 {
10954 case ABI_V4:
10955 case ABI_DARWIN:
10956 operands[0] = force_reg (Pmode, operands[0]);
10957 break;
10959 case ABI_AIX:
10960 /* AIX function pointers are really pointers to a three word
10961 area. */
10962 emit_call_insn (TARGET_32BIT
10963 ? gen_call_indirect_aix32 (force_reg (SImode,
10964 operands[0]),
10965 operands[1])
10966 : gen_call_indirect_aix64 (force_reg (DImode,
10967 operands[0]),
10968 operands[1]));
10969 DONE;
10971 default:
10972 gcc_unreachable ();
10973 }
10974 }
10975 }")
10977 (define_expand "call_value"
10978 [(parallel [(set (match_operand 0 "" "")
10979 (call (mem:SI (match_operand 1 "address_operand" ""))
10980 (match_operand 2 "" "")))
10981 (use (match_operand 3 "" ""))
10982 (clobber (reg:SI LR_REGNO))])]
10983 ""
10984 "
10985 {
10986 #if TARGET_MACHO
10987 if (MACHOPIC_INDIRECT)
10988 operands[1] = machopic_indirect_call_target (operands[1]);
10989 #endif
10991 gcc_assert (GET_CODE (operands[1]) == MEM);
10992 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10994 operands[1] = XEXP (operands[1], 0);
10996 if (GET_CODE (operands[1]) != SYMBOL_REF
10997 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10998 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10999 {
11000 if (INTVAL (operands[3]) & CALL_LONG)
11001 operands[1] = rs6000_longcall_ref (operands[1]);
11003 switch (DEFAULT_ABI)
11004 {
11005 case ABI_V4:
11006 case ABI_DARWIN:
11007 operands[1] = force_reg (Pmode, operands[1]);
11008 break;
11010 case ABI_AIX:
11011 /* AIX function pointers are really pointers to a three word
11012 area. */
11013 emit_call_insn (TARGET_32BIT
11014 ? gen_call_value_indirect_aix32 (operands[0],
11015 force_reg (SImode,
11016 operands[1]),
11017 operands[2])
11018 : gen_call_value_indirect_aix64 (operands[0],
11019 force_reg (DImode,
11020 operands[1]),
11021 operands[2]));
11022 DONE;
11024 default:
11025 gcc_unreachable ();
11026 }
11027 }
11028 }")
11030 ;; Call to function in current module. No TOC pointer reload needed.
11031 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11032 ;; either the function was not prototyped, or it was prototyped as a
11033 ;; variable argument function. It is > 0 if FP registers were passed
11034 ;; and < 0 if they were not.
11036 (define_insn "*call_local32"
11037 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11038 (match_operand 1 "" "g,g"))
11039 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11040 (clobber (reg:SI LR_REGNO))]
11041 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11042 "*
11043 {
11044 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11045 output_asm_insn (\"crxor 6,6,6\", operands);
11047 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11048 output_asm_insn (\"creqv 6,6,6\", operands);
11050 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11051 }"
11052 [(set_attr "type" "branch")
11053 (set_attr "length" "4,8")])
11055 (define_insn "*call_local64"
11056 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11057 (match_operand 1 "" "g,g"))
11058 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11059 (clobber (reg:SI LR_REGNO))]
11060 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11061 "*
11062 {
11063 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11064 output_asm_insn (\"crxor 6,6,6\", operands);
11066 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11067 output_asm_insn (\"creqv 6,6,6\", operands);
11069 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11070 }"
11071 [(set_attr "type" "branch")
11072 (set_attr "length" "4,8")])
11074 (define_insn "*call_value_local32"
11075 [(set (match_operand 0 "" "")
11076 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11077 (match_operand 2 "" "g,g")))
11078 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11079 (clobber (reg:SI LR_REGNO))]
11080 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11081 "*
11082 {
11083 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11084 output_asm_insn (\"crxor 6,6,6\", operands);
11086 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11087 output_asm_insn (\"creqv 6,6,6\", operands);
11089 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11090 }"
11091 [(set_attr "type" "branch")
11092 (set_attr "length" "4,8")])
11095 (define_insn "*call_value_local64"
11096 [(set (match_operand 0 "" "")
11097 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11098 (match_operand 2 "" "g,g")))
11099 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11100 (clobber (reg:SI LR_REGNO))]
11101 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11102 "*
11103 {
11104 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11105 output_asm_insn (\"crxor 6,6,6\", operands);
11107 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11108 output_asm_insn (\"creqv 6,6,6\", operands);
11110 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11111 }"
11112 [(set_attr "type" "branch")
11113 (set_attr "length" "4,8")])
11115 ;; Call to function which may be in another module. Restore the TOC
11116 ;; pointer (r2) after the call unless this is System V.
11117 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11118 ;; either the function was not prototyped, or it was prototyped as a
11119 ;; variable argument function. It is > 0 if FP registers were passed
11120 ;; and < 0 if they were not.
11122 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11123 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11124 (match_operand 1 "" "g,g"))
11125 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11126 (use (reg:SI 11))
11127 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11128 (clobber (reg:SI LR_REGNO))]
11129 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11130 "#"
11131 "&& reload_completed"
11132 [(set (reg:SI 2)
11133 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11134 (parallel [(call (mem:SI (match_dup 0))
11135 (match_dup 1))
11136 (use (reg:SI 2))
11137 (use (reg:SI 11))
11138 (set (reg:SI 2)
11139 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11140 (clobber (reg:SI LR_REGNO))])]
11141 ""
11142 [(set_attr "type" "jmpreg")
11143 (set_attr "length" "12")])
11145 (define_insn "*call_indirect_nonlocal_aix32"
11146 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11147 (match_operand 1 "" "g,g"))
11148 (use (reg:SI 2))
11149 (use (reg:SI 11))
11150 (set (reg:SI 2)
11151 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11152 (clobber (reg:SI LR_REGNO))]
11153 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11154 "b%T0l\;{l|lwz} 2,20(1)"
11155 [(set_attr "type" "jmpreg")
11156 (set_attr "length" "8")])
11158 (define_insn "*call_nonlocal_aix32"
11159 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11160 (match_operand 1 "" "g"))
11161 (use (match_operand:SI 2 "immediate_operand" "O"))
11162 (clobber (reg:SI LR_REGNO))]
11163 "TARGET_32BIT
11164 && DEFAULT_ABI == ABI_AIX
11165 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11166 "bl %z0\;%."
11167 [(set_attr "type" "branch")
11168 (set_attr "length" "8")])
11170 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11171 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11172 (match_operand 1 "" "g,g"))
11173 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11174 (const_int 8))))
11175 (use (reg:DI 11))
11176 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11177 (clobber (reg:SI LR_REGNO))]
11178 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11179 "#"
11180 "&& reload_completed"
11181 [(set (reg:DI 2)
11182 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11183 (parallel [(call (mem:SI (match_dup 0))
11184 (match_dup 1))
11185 (use (reg:DI 2))
11186 (use (reg:DI 11))
11187 (set (reg:DI 2)
11188 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11189 (clobber (reg:SI LR_REGNO))])]
11190 ""
11191 [(set_attr "type" "jmpreg")
11192 (set_attr "length" "12")])
11194 (define_insn "*call_indirect_nonlocal_aix64"
11195 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11196 (match_operand 1 "" "g,g"))
11197 (use (reg:DI 2))
11198 (use (reg:DI 11))
11199 (set (reg:DI 2)
11200 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11201 (clobber (reg:SI LR_REGNO))]
11202 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11203 "b%T0l\;ld 2,40(1)"
11204 [(set_attr "type" "jmpreg")
11205 (set_attr "length" "8")])
11207 (define_insn "*call_nonlocal_aix64"
11208 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11209 (match_operand 1 "" "g"))
11210 (use (match_operand:SI 2 "immediate_operand" "O"))
11211 (clobber (reg:SI LR_REGNO))]
11212 "TARGET_64BIT
11213 && DEFAULT_ABI == ABI_AIX
11214 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11215 "bl %z0\;%."
11216 [(set_attr "type" "branch")
11217 (set_attr "length" "8")])
11219 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11220 [(set (match_operand 0 "" "")
11221 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11222 (match_operand 2 "" "g,g")))
11223 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11224 (const_int 4))))
11225 (use (reg:SI 11))
11226 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11227 (clobber (reg:SI LR_REGNO))]
11228 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11229 "#"
11230 "&& reload_completed"
11231 [(set (reg:SI 2)
11232 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11233 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11234 (match_dup 2)))
11235 (use (reg:SI 2))
11236 (use (reg:SI 11))
11237 (set (reg:SI 2)
11238 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11239 (clobber (reg:SI LR_REGNO))])]
11240 ""
11241 [(set_attr "type" "jmpreg")
11242 (set_attr "length" "12")])
11244 (define_insn "*call_value_indirect_nonlocal_aix32"
11245 [(set (match_operand 0 "" "")
11246 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11247 (match_operand 2 "" "g,g")))
11248 (use (reg:SI 2))
11249 (use (reg:SI 11))
11250 (set (reg:SI 2)
11251 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11252 (clobber (reg:SI LR_REGNO))]
11253 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11254 "b%T1l\;{l|lwz} 2,20(1)"
11255 [(set_attr "type" "jmpreg")
11256 (set_attr "length" "8")])
11258 (define_insn "*call_value_nonlocal_aix32"
11259 [(set (match_operand 0 "" "")
11260 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11261 (match_operand 2 "" "g")))
11262 (use (match_operand:SI 3 "immediate_operand" "O"))
11263 (clobber (reg:SI LR_REGNO))]
11264 "TARGET_32BIT
11265 && DEFAULT_ABI == ABI_AIX
11266 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11267 "bl %z1\;%."
11268 [(set_attr "type" "branch")
11269 (set_attr "length" "8")])
11271 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11272 [(set (match_operand 0 "" "")
11273 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11274 (match_operand 2 "" "g,g")))
11275 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
11276 (const_int 8))))
11277 (use (reg:DI 11))
11278 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11279 (clobber (reg:SI LR_REGNO))]
11280 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11281 "#"
11282 "&& reload_completed"
11283 [(set (reg:DI 2)
11284 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
11285 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11286 (match_dup 2)))
11287 (use (reg:DI 2))
11288 (use (reg:DI 11))
11289 (set (reg:DI 2)
11290 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11291 (clobber (reg:SI LR_REGNO))])]
11292 ""
11293 [(set_attr "type" "jmpreg")
11294 (set_attr "length" "12")])
11296 (define_insn "*call_value_indirect_nonlocal_aix64"
11297 [(set (match_operand 0 "" "")
11298 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11299 (match_operand 2 "" "g,g")))
11300 (use (reg:DI 2))
11301 (use (reg:DI 11))
11302 (set (reg:DI 2)
11303 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11304 (clobber (reg:SI LR_REGNO))]
11305 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11306 "b%T1l\;ld 2,40(1)"
11307 [(set_attr "type" "jmpreg")
11308 (set_attr "length" "8")])
11310 (define_insn "*call_value_nonlocal_aix64"
11311 [(set (match_operand 0 "" "")
11312 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11313 (match_operand 2 "" "g")))
11314 (use (match_operand:SI 3 "immediate_operand" "O"))
11315 (clobber (reg:SI LR_REGNO))]
11316 "TARGET_64BIT
11317 && DEFAULT_ABI == ABI_AIX
11318 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11319 "bl %z1\;%."
11320 [(set_attr "type" "branch")
11321 (set_attr "length" "8")])
11323 ;; A function pointer under System V is just a normal pointer
11324 ;; operands[0] is the function pointer
11325 ;; operands[1] is the stack size to clean up
11326 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11327 ;; which indicates how to set cr1
11329 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11330 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11331 (match_operand 1 "" "g,g,g,g"))
11332 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11333 (clobber (reg:SI LR_REGNO))]
11334 "DEFAULT_ABI == ABI_V4
11335 || DEFAULT_ABI == ABI_DARWIN"
11336 {
11337 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11338 output_asm_insn ("crxor 6,6,6", operands);
11340 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11341 output_asm_insn ("creqv 6,6,6", operands);
11343 return "b%T0l";
11344 }
11345 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11346 (set_attr "length" "4,4,8,8")])
11348 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11349 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11350 (match_operand 1 "" "g,g"))
11351 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11352 (clobber (reg:SI LR_REGNO))]
11353 "(DEFAULT_ABI == ABI_DARWIN
11354 || (DEFAULT_ABI == ABI_V4
11355 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11356 {
11357 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11358 output_asm_insn ("crxor 6,6,6", operands);
11360 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11361 output_asm_insn ("creqv 6,6,6", operands);
11363 #if TARGET_MACHO
11364 return output_call(insn, operands, 0, 2);
11365 #else
11366 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11367 {
11368 gcc_assert (!TARGET_SECURE_PLT);
11369 return "bl %z0@plt";
11370 }
11371 else
11372 return "bl %z0";
11373 #endif
11374 }
11375 "DEFAULT_ABI == ABI_V4
11376 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11377 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11378 [(parallel [(call (mem:SI (match_dup 0))
11379 (match_dup 1))
11380 (use (match_dup 2))
11381 (use (match_dup 3))
11382 (clobber (reg:SI LR_REGNO))])]
11383 {
11384 operands[3] = pic_offset_table_rtx;
11385 }
11386 [(set_attr "type" "branch,branch")
11387 (set_attr "length" "4,8")])
11389 (define_insn "*call_nonlocal_sysv_secure<mode>"
11390 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11391 (match_operand 1 "" "g,g"))
11392 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11393 (use (match_operand:SI 3 "register_operand" "r,r"))
11394 (clobber (reg:SI LR_REGNO))]
11395 "(DEFAULT_ABI == ABI_V4
11396 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11397 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11398 {
11399 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11400 output_asm_insn ("crxor 6,6,6", operands);
11402 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11403 output_asm_insn ("creqv 6,6,6", operands);
11405 if (flag_pic == 2)
11406 /* The magic 32768 offset here and in the other sysv call insns
11407 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11408 See sysv4.h:toc_section. */
11409 return "bl %z0+32768@plt";
11410 else
11411 return "bl %z0@plt";
11412 }
11413 [(set_attr "type" "branch,branch")
11414 (set_attr "length" "4,8")])
11416 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11417 [(set (match_operand 0 "" "")
11418 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11419 (match_operand 2 "" "g,g,g,g")))
11420 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11421 (clobber (reg:SI LR_REGNO))]
11422 "DEFAULT_ABI == ABI_V4
11423 || DEFAULT_ABI == ABI_DARWIN"
11424 {
11425 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11426 output_asm_insn ("crxor 6,6,6", operands);
11428 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11429 output_asm_insn ("creqv 6,6,6", operands);
11431 return "b%T1l";
11432 }
11433 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11434 (set_attr "length" "4,4,8,8")])
11436 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11437 [(set (match_operand 0 "" "")
11438 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11439 (match_operand 2 "" "g,g")))
11440 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11441 (clobber (reg:SI LR_REGNO))]
11442 "(DEFAULT_ABI == ABI_DARWIN
11443 || (DEFAULT_ABI == ABI_V4
11444 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11445 {
11446 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11447 output_asm_insn ("crxor 6,6,6", operands);
11449 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11450 output_asm_insn ("creqv 6,6,6", operands);
11452 #if TARGET_MACHO
11453 return output_call(insn, operands, 1, 3);
11454 #else
11455 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11456 {
11457 gcc_assert (!TARGET_SECURE_PLT);
11458 return "bl %z1@plt";
11459 }
11460 else
11461 return "bl %z1";
11462 #endif
11463 }
11464 "DEFAULT_ABI == ABI_V4
11465 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11466 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11467 [(parallel [(set (match_dup 0)
11468 (call (mem:SI (match_dup 1))
11469 (match_dup 2)))
11470 (use (match_dup 3))
11471 (use (match_dup 4))
11472 (clobber (reg:SI LR_REGNO))])]
11473 {
11474 operands[4] = pic_offset_table_rtx;
11475 }
11476 [(set_attr "type" "branch,branch")
11477 (set_attr "length" "4,8")])
11479 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11480 [(set (match_operand 0 "" "")
11481 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11482 (match_operand 2 "" "g,g")))
11483 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11484 (use (match_operand:SI 4 "register_operand" "r,r"))
11485 (clobber (reg:SI LR_REGNO))]
11486 "(DEFAULT_ABI == ABI_V4
11487 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11488 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11489 {
11490 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11491 output_asm_insn ("crxor 6,6,6", operands);
11493 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11494 output_asm_insn ("creqv 6,6,6", operands);
11496 if (flag_pic == 2)
11497 return "bl %z1+32768@plt";
11498 else
11499 return "bl %z1@plt";
11500 }
11501 [(set_attr "type" "branch,branch")
11502 (set_attr "length" "4,8")])
11504 ;; Call subroutine returning any type.
11505 (define_expand "untyped_call"
11506 [(parallel [(call (match_operand 0 "" "")
11507 (const_int 0))
11508 (match_operand 1 "" "")
11509 (match_operand 2 "" "")])]
11510 ""
11511 "
11512 {
11513 int i;
11515 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11517 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11518 {
11519 rtx set = XVECEXP (operands[2], 0, i);
11520 emit_move_insn (SET_DEST (set), SET_SRC (set));
11521 }
11523 /* The optimizer does not know that the call sets the function value
11524 registers we stored in the result block. We avoid problems by
11525 claiming that all hard registers are used and clobbered at this
11526 point. */
11527 emit_insn (gen_blockage ());
11529 DONE;
11530 }")
11532 ;; sibling call patterns
11533 (define_expand "sibcall"
11534 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11535 (match_operand 1 "" ""))
11536 (use (match_operand 2 "" ""))
11537 (use (reg:SI LR_REGNO))
11538 (return)])]
11539 ""
11540 "
11541 {
11542 #if TARGET_MACHO
11543 if (MACHOPIC_INDIRECT)
11544 operands[0] = machopic_indirect_call_target (operands[0]);
11545 #endif
11547 gcc_assert (GET_CODE (operands[0]) == MEM);
11548 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11550 operands[0] = XEXP (operands[0], 0);
11551 }")
11553 ;; this and similar patterns must be marked as using LR, otherwise
11554 ;; dataflow will try to delete the store into it. This is true
11555 ;; even when the actual reg to jump to is in CTR, when LR was
11556 ;; saved and restored around the PIC-setting BCL.
11557 (define_insn "*sibcall_local32"
11558 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11559 (match_operand 1 "" "g,g"))
11560 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11561 (use (reg:SI LR_REGNO))
11562 (return)]
11563 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11564 "*
11565 {
11566 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11567 output_asm_insn (\"crxor 6,6,6\", operands);
11569 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11570 output_asm_insn (\"creqv 6,6,6\", operands);
11572 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11573 }"
11574 [(set_attr "type" "branch")
11575 (set_attr "length" "4,8")])
11577 (define_insn "*sibcall_local64"
11578 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11579 (match_operand 1 "" "g,g"))
11580 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11581 (use (reg:SI LR_REGNO))
11582 (return)]
11583 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11584 "*
11585 {
11586 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11587 output_asm_insn (\"crxor 6,6,6\", operands);
11589 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11590 output_asm_insn (\"creqv 6,6,6\", operands);
11592 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11593 }"
11594 [(set_attr "type" "branch")
11595 (set_attr "length" "4,8")])
11597 (define_insn "*sibcall_value_local32"
11598 [(set (match_operand 0 "" "")
11599 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11600 (match_operand 2 "" "g,g")))
11601 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11602 (use (reg:SI LR_REGNO))
11603 (return)]
11604 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11605 "*
11606 {
11607 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11608 output_asm_insn (\"crxor 6,6,6\", operands);
11610 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11611 output_asm_insn (\"creqv 6,6,6\", operands);
11613 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11614 }"
11615 [(set_attr "type" "branch")
11616 (set_attr "length" "4,8")])
11619 (define_insn "*sibcall_value_local64"
11620 [(set (match_operand 0 "" "")
11621 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11622 (match_operand 2 "" "g,g")))
11623 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11624 (use (reg:SI LR_REGNO))
11625 (return)]
11626 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11627 "*
11628 {
11629 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11630 output_asm_insn (\"crxor 6,6,6\", operands);
11632 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11633 output_asm_insn (\"creqv 6,6,6\", operands);
11635 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11636 }"
11637 [(set_attr "type" "branch")
11638 (set_attr "length" "4,8")])
11640 (define_insn "*sibcall_nonlocal_aix32"
11641 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11642 (match_operand 1 "" "g"))
11643 (use (match_operand:SI 2 "immediate_operand" "O"))
11644 (use (reg:SI LR_REGNO))
11645 (return)]
11646 "TARGET_32BIT
11647 && DEFAULT_ABI == ABI_AIX
11648 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11649 "b %z0"
11650 [(set_attr "type" "branch")
11651 (set_attr "length" "4")])
11653 (define_insn "*sibcall_nonlocal_aix64"
11654 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11655 (match_operand 1 "" "g"))
11656 (use (match_operand:SI 2 "immediate_operand" "O"))
11657 (use (reg:SI LR_REGNO))
11658 (return)]
11659 "TARGET_64BIT
11660 && DEFAULT_ABI == ABI_AIX
11661 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11662 "b %z0"
11663 [(set_attr "type" "branch")
11664 (set_attr "length" "4")])
11666 (define_insn "*sibcall_value_nonlocal_aix32"
11667 [(set (match_operand 0 "" "")
11668 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11669 (match_operand 2 "" "g")))
11670 (use (match_operand:SI 3 "immediate_operand" "O"))
11671 (use (reg:SI LR_REGNO))
11672 (return)]
11673 "TARGET_32BIT
11674 && DEFAULT_ABI == ABI_AIX
11675 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11676 "b %z1"
11677 [(set_attr "type" "branch")
11678 (set_attr "length" "4")])
11680 (define_insn "*sibcall_value_nonlocal_aix64"
11681 [(set (match_operand 0 "" "")
11682 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11683 (match_operand 2 "" "g")))
11684 (use (match_operand:SI 3 "immediate_operand" "O"))
11685 (use (reg:SI LR_REGNO))
11686 (return)]
11687 "TARGET_64BIT
11688 && DEFAULT_ABI == ABI_AIX
11689 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11690 "b %z1"
11691 [(set_attr "type" "branch")
11692 (set_attr "length" "4")])
11694 (define_insn "*sibcall_nonlocal_sysv<mode>"
11695 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11696 (match_operand 1 "" ""))
11697 (use (match_operand 2 "immediate_operand" "O,n"))
11698 (use (reg:SI LR_REGNO))
11699 (return)]
11700 "(DEFAULT_ABI == ABI_DARWIN
11701 || DEFAULT_ABI == ABI_V4)
11702 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11703 "*
11704 {
11705 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11706 output_asm_insn (\"crxor 6,6,6\", operands);
11708 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11709 output_asm_insn (\"creqv 6,6,6\", operands);
11711 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11712 {
11713 gcc_assert (!TARGET_SECURE_PLT);
11714 return \"b %z0@plt\";
11715 }
11716 else
11717 return \"b %z0\";
11718 }"
11719 [(set_attr "type" "branch,branch")
11720 (set_attr "length" "4,8")])
11722 (define_expand "sibcall_value"
11723 [(parallel [(set (match_operand 0 "register_operand" "")
11724 (call (mem:SI (match_operand 1 "address_operand" ""))
11725 (match_operand 2 "" "")))
11726 (use (match_operand 3 "" ""))
11727 (use (reg:SI LR_REGNO))
11728 (return)])]
11729 ""
11730 "
11731 {
11732 #if TARGET_MACHO
11733 if (MACHOPIC_INDIRECT)
11734 operands[1] = machopic_indirect_call_target (operands[1]);
11735 #endif
11737 gcc_assert (GET_CODE (operands[1]) == MEM);
11738 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11740 operands[1] = XEXP (operands[1], 0);
11741 }")
11743 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11744 [(set (match_operand 0 "" "")
11745 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11746 (match_operand 2 "" "")))
11747 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11748 (use (reg:SI LR_REGNO))
11749 (return)]
11750 "(DEFAULT_ABI == ABI_DARWIN
11751 || DEFAULT_ABI == ABI_V4)
11752 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11753 "*
11754 {
11755 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11756 output_asm_insn (\"crxor 6,6,6\", operands);
11758 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11759 output_asm_insn (\"creqv 6,6,6\", operands);
11761 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11762 {
11763 gcc_assert (!TARGET_SECURE_PLT);
11764 return \"b %z1@plt\";
11765 }
11766 else
11767 return \"b %z1\";
11768 }"
11769 [(set_attr "type" "branch,branch")
11770 (set_attr "length" "4,8")])
11772 (define_expand "sibcall_epilogue"
11773 [(use (const_int 0))]
11774 "TARGET_SCHED_PROLOG"
11775 "
11776 {
11777 rs6000_emit_epilogue (TRUE);
11778 DONE;
11779 }")
11781 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11782 ;; all of memory. This blocks insns from being moved across this point.
11784 (define_insn "blockage"
11785 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11786 ""
11787 "")
11788 \f
11789 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11790 ;; signed & unsigned, and one type of branch.
11791 ;;
11792 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11793 ;; insns, and branches. We store the operands of compares until we see
11794 ;; how it is used.
11795 (define_expand "cmp<mode>"
11796 [(set (cc0)
11797 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11798 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11799 ""
11800 "
11801 {
11802 /* Take care of the possibility that operands[1] might be negative but
11803 this might be a logical operation. That insn doesn't exist. */
11804 if (GET_CODE (operands[1]) == CONST_INT
11805 && INTVAL (operands[1]) < 0)
11806 operands[1] = force_reg (<MODE>mode, operands[1]);
11808 rs6000_compare_op0 = operands[0];
11809 rs6000_compare_op1 = operands[1];
11810 rs6000_compare_fp_p = 0;
11811 DONE;
11812 }")
11814 (define_expand "cmp<mode>"
11815 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11816 (match_operand:FP 1 "gpc_reg_operand" "")))]
11817 ""
11818 "
11819 {
11820 rs6000_compare_op0 = operands[0];
11821 rs6000_compare_op1 = operands[1];
11822 rs6000_compare_fp_p = 1;
11823 DONE;
11824 }")
11826 (define_expand "beq"
11827 [(use (match_operand 0 "" ""))]
11828 ""
11829 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11831 (define_expand "bne"
11832 [(use (match_operand 0 "" ""))]
11833 ""
11834 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11836 (define_expand "bge"
11837 [(use (match_operand 0 "" ""))]
11838 ""
11839 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11841 (define_expand "bgt"
11842 [(use (match_operand 0 "" ""))]
11843 ""
11844 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11846 (define_expand "ble"
11847 [(use (match_operand 0 "" ""))]
11848 ""
11849 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11851 (define_expand "blt"
11852 [(use (match_operand 0 "" ""))]
11853 ""
11854 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11856 (define_expand "bgeu"
11857 [(use (match_operand 0 "" ""))]
11858 ""
11859 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11861 (define_expand "bgtu"
11862 [(use (match_operand 0 "" ""))]
11863 ""
11864 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11866 (define_expand "bleu"
11867 [(use (match_operand 0 "" ""))]
11868 ""
11869 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11871 (define_expand "bltu"
11872 [(use (match_operand 0 "" ""))]
11873 ""
11874 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11876 (define_expand "bunordered"
11877 [(use (match_operand 0 "" ""))]
11878 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11879 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11881 (define_expand "bordered"
11882 [(use (match_operand 0 "" ""))]
11883 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11884 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11886 (define_expand "buneq"
11887 [(use (match_operand 0 "" ""))]
11888 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11889 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11891 (define_expand "bunge"
11892 [(use (match_operand 0 "" ""))]
11893 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11894 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11896 (define_expand "bungt"
11897 [(use (match_operand 0 "" ""))]
11898 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11899 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11901 (define_expand "bunle"
11902 [(use (match_operand 0 "" ""))]
11903 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11904 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11906 (define_expand "bunlt"
11907 [(use (match_operand 0 "" ""))]
11908 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11909 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11911 (define_expand "bltgt"
11912 [(use (match_operand 0 "" ""))]
11913 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11914 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11916 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11917 ;; For SEQ, likewise, except that comparisons with zero should be done
11918 ;; with an scc insns. However, due to the order that combine see the
11919 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11920 ;; the cases we don't want to handle.
11921 (define_expand "seq"
11922 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11923 ""
11924 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11926 (define_expand "sne"
11927 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11928 ""
11929 "
11930 {
11931 if (! rs6000_compare_fp_p)
11932 FAIL;
11934 rs6000_emit_sCOND (NE, operands[0]);
11935 DONE;
11936 }")
11938 ;; A >= 0 is best done the portable way for A an integer.
11939 (define_expand "sge"
11940 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11941 ""
11942 "
11943 {
11944 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11945 FAIL;
11947 rs6000_emit_sCOND (GE, operands[0]);
11948 DONE;
11949 }")
11951 ;; A > 0 is best done using the portable sequence, so fail in that case.
11952 (define_expand "sgt"
11953 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11954 ""
11955 "
11956 {
11957 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11958 FAIL;
11960 rs6000_emit_sCOND (GT, operands[0]);
11961 DONE;
11962 }")
11964 ;; A <= 0 is best done the portable way for A an integer.
11965 (define_expand "sle"
11966 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11967 ""
11968 "
11969 {
11970 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11971 FAIL;
11973 rs6000_emit_sCOND (LE, operands[0]);
11974 DONE;
11975 }")
11977 ;; A < 0 is best done in the portable way for A an integer.
11978 (define_expand "slt"
11979 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11980 ""
11981 "
11982 {
11983 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11984 FAIL;
11986 rs6000_emit_sCOND (LT, operands[0]);
11987 DONE;
11988 }")
11990 (define_expand "sgeu"
11991 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11992 ""
11993 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11995 (define_expand "sgtu"
11996 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11997 ""
11998 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
12000 (define_expand "sleu"
12001 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12002 ""
12003 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
12005 (define_expand "sltu"
12006 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12007 ""
12008 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
12010 (define_expand "sunordered"
12011 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12012 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12013 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
12015 (define_expand "sordered"
12016 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12017 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12018 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
12020 (define_expand "suneq"
12021 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12022 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12023 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
12025 (define_expand "sunge"
12026 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12027 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12028 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
12030 (define_expand "sungt"
12031 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12032 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12033 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
12035 (define_expand "sunle"
12036 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12037 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12038 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
12040 (define_expand "sunlt"
12041 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12042 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12043 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
12045 (define_expand "sltgt"
12046 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12047 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12048 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
12050 (define_expand "stack_protect_set"
12051 [(match_operand 0 "memory_operand" "")
12052 (match_operand 1 "memory_operand" "")]
12053 ""
12054 {
12055 #ifdef TARGET_THREAD_SSP_OFFSET
12056 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12057 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12058 operands[1] = gen_rtx_MEM (Pmode, addr);
12059 #endif
12060 if (TARGET_64BIT)
12061 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12062 else
12063 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12064 DONE;
12065 })
12067 (define_insn "stack_protect_setsi"
12068 [(set (match_operand:SI 0 "memory_operand" "=m")
12069 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12070 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12071 "TARGET_32BIT"
12072 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12073 [(set_attr "type" "three")
12074 (set_attr "length" "12")])
12076 (define_insn "stack_protect_setdi"
12077 [(set (match_operand:DI 0 "memory_operand" "=m")
12078 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12079 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12080 "TARGET_64BIT"
12081 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12082 [(set_attr "type" "three")
12083 (set_attr "length" "12")])
12085 (define_expand "stack_protect_test"
12086 [(match_operand 0 "memory_operand" "")
12087 (match_operand 1 "memory_operand" "")
12088 (match_operand 2 "" "")]
12089 ""
12090 {
12091 #ifdef TARGET_THREAD_SSP_OFFSET
12092 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12093 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12094 operands[1] = gen_rtx_MEM (Pmode, addr);
12095 #endif
12096 rs6000_compare_op0 = operands[0];
12097 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
12098 UNSPEC_SP_TEST);
12099 rs6000_compare_fp_p = 0;
12100 emit_jump_insn (gen_beq (operands[2]));
12101 DONE;
12102 })
12104 (define_insn "stack_protect_testsi"
12105 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12106 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12107 (match_operand:SI 2 "memory_operand" "m,m")]
12108 UNSPEC_SP_TEST))
12109 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12110 (clobber (match_scratch:SI 3 "=&r,&r"))]
12111 "TARGET_32BIT"
12112 "@
12113 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12114 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12115 [(set_attr "length" "16,20")])
12117 (define_insn "stack_protect_testdi"
12118 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12119 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12120 (match_operand:DI 2 "memory_operand" "m,m")]
12121 UNSPEC_SP_TEST))
12122 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12123 (clobber (match_scratch:DI 3 "=&r,&r"))]
12124 "TARGET_64BIT"
12125 "@
12126 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12127 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12128 [(set_attr "length" "16,20")])
12130 \f
12131 ;; Here are the actual compare insns.
12132 (define_insn "*cmp<mode>_internal1"
12133 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12134 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12135 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12136 ""
12137 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
12138 [(set_attr "type" "cmp")])
12140 ;; If we are comparing a register for equality with a large constant,
12141 ;; we can do this with an XOR followed by a compare. But this is profitable
12142 ;; only if the large constant is only used for the comparison (and in this
12143 ;; case we already have a register to reuse as scratch).
12144 ;;
12145 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12146 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12148 (define_peephole2
12149 [(set (match_operand:SI 0 "register_operand")
12150 (match_operand:SI 1 "logical_const_operand" ""))
12151 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12152 [(match_dup 0)
12153 (match_operand:SI 2 "logical_const_operand" "")]))
12154 (set (match_operand:CC 4 "cc_reg_operand" "")
12155 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12156 (match_dup 0)))
12157 (set (pc)
12158 (if_then_else (match_operator 6 "equality_operator"
12159 [(match_dup 4) (const_int 0)])
12160 (match_operand 7 "" "")
12161 (match_operand 8 "" "")))]
12162 "peep2_reg_dead_p (3, operands[0])
12163 && peep2_reg_dead_p (4, operands[4])"
12164 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12165 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12166 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12168 {
12169 /* Get the constant we are comparing against, and see what it looks like
12170 when sign-extended from 16 to 32 bits. Then see what constant we could
12171 XOR with SEXTC to get the sign-extended value. */
12172 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12173 SImode,
12174 operands[1], operands[2]);
12175 HOST_WIDE_INT c = INTVAL (cnst);
12176 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12177 HOST_WIDE_INT xorv = c ^ sextc;
12179 operands[9] = GEN_INT (xorv);
12180 operands[10] = GEN_INT (sextc);
12181 })
12183 (define_insn "*cmpsi_internal2"
12184 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12185 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12186 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12187 ""
12188 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12189 [(set_attr "type" "cmp")])
12191 (define_insn "*cmpdi_internal2"
12192 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12193 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12194 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12195 ""
12196 "cmpld%I2 %0,%1,%b2"
12197 [(set_attr "type" "cmp")])
12199 ;; The following two insns don't exist as single insns, but if we provide
12200 ;; them, we can swap an add and compare, which will enable us to overlap more
12201 ;; of the required delay between a compare and branch. We generate code for
12202 ;; them by splitting.
12204 (define_insn ""
12205 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12206 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12207 (match_operand:SI 2 "short_cint_operand" "i")))
12208 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12209 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12210 ""
12211 "#"
12212 [(set_attr "length" "8")])
12214 (define_insn ""
12215 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12216 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12217 (match_operand:SI 2 "u_short_cint_operand" "i")))
12218 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12219 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12220 ""
12221 "#"
12222 [(set_attr "length" "8")])
12224 (define_split
12225 [(set (match_operand:CC 3 "cc_reg_operand" "")
12226 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12227 (match_operand:SI 2 "short_cint_operand" "")))
12228 (set (match_operand:SI 0 "gpc_reg_operand" "")
12229 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12230 ""
12231 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12232 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12234 (define_split
12235 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12236 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12237 (match_operand:SI 2 "u_short_cint_operand" "")))
12238 (set (match_operand:SI 0 "gpc_reg_operand" "")
12239 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12240 ""
12241 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12242 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12244 (define_insn "*cmpsf_internal1"
12245 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12246 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12247 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12248 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12249 "fcmpu %0,%1,%2"
12250 [(set_attr "type" "fpcompare")])
12252 (define_insn "*cmpdf_internal1"
12253 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12254 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
12255 (match_operand:DF 2 "gpc_reg_operand" "f")))]
12256 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
12257 "fcmpu %0,%1,%2"
12258 [(set_attr "type" "fpcompare")])
12260 ;; Only need to compare second words if first words equal
12261 (define_insn "*cmptf_internal1"
12262 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12263 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
12264 (match_operand:TF 2 "gpc_reg_operand" "f")))]
12265 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12266 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12267 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12268 [(set_attr "type" "fpcompare")
12269 (set_attr "length" "12")])
12271 (define_insn_and_split "*cmptf_internal2"
12272 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12273 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
12274 (match_operand:TF 2 "gpc_reg_operand" "f")))
12275 (clobber (match_scratch:DF 3 "=f"))
12276 (clobber (match_scratch:DF 4 "=f"))
12277 (clobber (match_scratch:DF 5 "=f"))
12278 (clobber (match_scratch:DF 6 "=f"))
12279 (clobber (match_scratch:DF 7 "=f"))
12280 (clobber (match_scratch:DF 8 "=f"))
12281 (clobber (match_scratch:DF 9 "=f"))
12282 (clobber (match_scratch:DF 10 "=f"))]
12283 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12284 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12285 "#"
12286 "&& reload_completed"
12287 [(set (match_dup 3) (match_dup 13))
12288 (set (match_dup 4) (match_dup 14))
12289 (set (match_dup 9) (abs:DF (match_dup 5)))
12290 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12291 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12292 (label_ref (match_dup 11))
12293 (pc)))
12294 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12295 (set (pc) (label_ref (match_dup 12)))
12296 (match_dup 11)
12297 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12298 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12299 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12300 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12301 (match_dup 12)]
12302 {
12303 REAL_VALUE_TYPE rv;
12304 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12305 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12307 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12308 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12309 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12310 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12311 operands[11] = gen_label_rtx ();
12312 operands[12] = gen_label_rtx ();
12313 real_inf (&rv);
12314 operands[13] = force_const_mem (DFmode,
12315 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12316 operands[14] = force_const_mem (DFmode,
12317 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12318 DFmode));
12319 if (TARGET_TOC)
12320 {
12321 operands[13] = gen_const_mem (DFmode,
12322 create_TOC_reference (XEXP (operands[13], 0)));
12323 operands[14] = gen_const_mem (DFmode,
12324 create_TOC_reference (XEXP (operands[14], 0)));
12325 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12326 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12327 }
12328 })
12329 \f
12330 ;; Now we have the scc insns. We can do some combinations because of the
12331 ;; way the machine works.
12332 ;;
12333 ;; Note that this is probably faster if we can put an insn between the
12334 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12335 ;; cases the insns below which don't use an intermediate CR field will
12336 ;; be used instead.
12337 (define_insn ""
12338 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12339 (match_operator:SI 1 "scc_comparison_operator"
12340 [(match_operand 2 "cc_reg_operand" "y")
12341 (const_int 0)]))]
12342 ""
12343 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12344 [(set (attr "type")
12345 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12346 (const_string "mfcrf")
12347 ]
12348 (const_string "mfcr")))
12349 (set_attr "length" "8")])
12351 ;; Same as above, but get the GT bit.
12352 (define_insn "move_from_CR_gt_bit"
12353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12354 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12355 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12356 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12357 [(set_attr "type" "mfcr")
12358 (set_attr "length" "8")])
12360 ;; Same as above, but get the OV/ORDERED bit.
12361 (define_insn "move_from_CR_ov_bit"
12362 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12363 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12364 "TARGET_ISEL"
12365 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12366 [(set_attr "type" "mfcr")
12367 (set_attr "length" "8")])
12369 (define_insn ""
12370 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12371 (match_operator:DI 1 "scc_comparison_operator"
12372 [(match_operand 2 "cc_reg_operand" "y")
12373 (const_int 0)]))]
12374 "TARGET_POWERPC64"
12375 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12376 [(set (attr "type")
12377 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12378 (const_string "mfcrf")
12379 ]
12380 (const_string "mfcr")))
12381 (set_attr "length" "8")])
12383 (define_insn ""
12384 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12385 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12386 [(match_operand 2 "cc_reg_operand" "y,y")
12387 (const_int 0)])
12388 (const_int 0)))
12389 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12390 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12391 "TARGET_32BIT"
12392 "@
12393 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12394 #"
12395 [(set_attr "type" "delayed_compare")
12396 (set_attr "length" "8,16")])
12398 (define_split
12399 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12400 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12401 [(match_operand 2 "cc_reg_operand" "")
12402 (const_int 0)])
12403 (const_int 0)))
12404 (set (match_operand:SI 3 "gpc_reg_operand" "")
12405 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12406 "TARGET_32BIT && reload_completed"
12407 [(set (match_dup 3)
12408 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12409 (set (match_dup 0)
12410 (compare:CC (match_dup 3)
12411 (const_int 0)))]
12412 "")
12414 (define_insn ""
12415 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12416 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12417 [(match_operand 2 "cc_reg_operand" "y")
12418 (const_int 0)])
12419 (match_operand:SI 3 "const_int_operand" "n")))]
12420 ""
12421 "*
12422 {
12423 int is_bit = ccr_bit (operands[1], 1);
12424 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12425 int count;
12427 if (is_bit >= put_bit)
12428 count = is_bit - put_bit;
12429 else
12430 count = 32 - (put_bit - is_bit);
12432 operands[4] = GEN_INT (count);
12433 operands[5] = GEN_INT (put_bit);
12435 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12436 }"
12437 [(set (attr "type")
12438 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12439 (const_string "mfcrf")
12440 ]
12441 (const_string "mfcr")))
12442 (set_attr "length" "8")])
12444 (define_insn ""
12445 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12446 (compare:CC
12447 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12448 [(match_operand 2 "cc_reg_operand" "y,y")
12449 (const_int 0)])
12450 (match_operand:SI 3 "const_int_operand" "n,n"))
12451 (const_int 0)))
12452 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12453 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12454 (match_dup 3)))]
12455 ""
12456 "*
12457 {
12458 int is_bit = ccr_bit (operands[1], 1);
12459 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12460 int count;
12462 /* Force split for non-cc0 compare. */
12463 if (which_alternative == 1)
12464 return \"#\";
12466 if (is_bit >= put_bit)
12467 count = is_bit - put_bit;
12468 else
12469 count = 32 - (put_bit - is_bit);
12471 operands[5] = GEN_INT (count);
12472 operands[6] = GEN_INT (put_bit);
12474 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12475 }"
12476 [(set_attr "type" "delayed_compare")
12477 (set_attr "length" "8,16")])
12479 (define_split
12480 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12481 (compare:CC
12482 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12483 [(match_operand 2 "cc_reg_operand" "")
12484 (const_int 0)])
12485 (match_operand:SI 3 "const_int_operand" ""))
12486 (const_int 0)))
12487 (set (match_operand:SI 4 "gpc_reg_operand" "")
12488 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12489 (match_dup 3)))]
12490 "reload_completed"
12491 [(set (match_dup 4)
12492 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12493 (match_dup 3)))
12494 (set (match_dup 0)
12495 (compare:CC (match_dup 4)
12496 (const_int 0)))]
12497 "")
12499 ;; There is a 3 cycle delay between consecutive mfcr instructions
12500 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12502 (define_peephole
12503 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12504 (match_operator:SI 1 "scc_comparison_operator"
12505 [(match_operand 2 "cc_reg_operand" "y")
12506 (const_int 0)]))
12507 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12508 (match_operator:SI 4 "scc_comparison_operator"
12509 [(match_operand 5 "cc_reg_operand" "y")
12510 (const_int 0)]))]
12511 "REGNO (operands[2]) != REGNO (operands[5])"
12512 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12513 [(set_attr "type" "mfcr")
12514 (set_attr "length" "12")])
12516 (define_peephole
12517 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12518 (match_operator:DI 1 "scc_comparison_operator"
12519 [(match_operand 2 "cc_reg_operand" "y")
12520 (const_int 0)]))
12521 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12522 (match_operator:DI 4 "scc_comparison_operator"
12523 [(match_operand 5 "cc_reg_operand" "y")
12524 (const_int 0)]))]
12525 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12526 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12527 [(set_attr "type" "mfcr")
12528 (set_attr "length" "12")])
12530 ;; There are some scc insns that can be done directly, without a compare.
12531 ;; These are faster because they don't involve the communications between
12532 ;; the FXU and branch units. In fact, we will be replacing all of the
12533 ;; integer scc insns here or in the portable methods in emit_store_flag.
12534 ;;
12535 ;; Also support (neg (scc ..)) since that construct is used to replace
12536 ;; branches, (plus (scc ..) ..) since that construct is common and
12537 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12538 ;; cases where it is no more expensive than (neg (scc ..)).
12540 ;; Have reload force a constant into a register for the simple insns that
12541 ;; otherwise won't accept constants. We do this because it is faster than
12542 ;; the cmp/mfcr sequence we would otherwise generate.
12544 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12545 (DI "rKJI")])
12547 (define_insn_and_split "*eq<mode>"
12548 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12549 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12550 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12551 "!TARGET_POWER"
12552 "#"
12553 "!TARGET_POWER"
12554 [(set (match_dup 0)
12555 (clz:GPR (match_dup 3)))
12556 (set (match_dup 0)
12557 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12558 {
12559 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12560 {
12561 /* Use output operand as intermediate. */
12562 operands[3] = operands[0];
12564 if (logical_operand (operands[2], <MODE>mode))
12565 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12566 gen_rtx_XOR (<MODE>mode,
12567 operands[1], operands[2])));
12568 else
12569 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12570 gen_rtx_PLUS (<MODE>mode, operands[1],
12571 negate_rtx (<MODE>mode,
12572 operands[2]))));
12573 }
12574 else
12575 operands[3] = operands[1];
12577 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12578 })
12580 (define_insn_and_split "*eq<mode>_compare"
12581 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12582 (compare:CC
12583 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12584 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12585 (const_int 0)))
12586 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12587 (eq:P (match_dup 1) (match_dup 2)))]
12588 "!TARGET_POWER && optimize_size"
12589 "#"
12590 "!TARGET_POWER && optimize_size"
12591 [(set (match_dup 0)
12592 (clz:P (match_dup 4)))
12593 (parallel [(set (match_dup 3)
12594 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12595 (const_int 0)))
12596 (set (match_dup 0)
12597 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12598 {
12599 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12600 {
12601 /* Use output operand as intermediate. */
12602 operands[4] = operands[0];
12604 if (logical_operand (operands[2], <MODE>mode))
12605 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12606 gen_rtx_XOR (<MODE>mode,
12607 operands[1], operands[2])));
12608 else
12609 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12610 gen_rtx_PLUS (<MODE>mode, operands[1],
12611 negate_rtx (<MODE>mode,
12612 operands[2]))));
12613 }
12614 else
12615 operands[4] = operands[1];
12617 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12618 })
12620 (define_insn "*eqsi_power"
12621 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12622 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12623 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12624 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12625 "TARGET_POWER"
12626 "@
12627 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12628 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12629 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12630 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12631 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12632 [(set_attr "type" "three,two,three,three,three")
12633 (set_attr "length" "12,8,12,12,12")])
12635 ;; We have insns of the form shown by the first define_insn below. If
12636 ;; there is something inside the comparison operation, we must split it.
12637 (define_split
12638 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12639 (plus:SI (match_operator 1 "comparison_operator"
12640 [(match_operand:SI 2 "" "")
12641 (match_operand:SI 3
12642 "reg_or_cint_operand" "")])
12643 (match_operand:SI 4 "gpc_reg_operand" "")))
12644 (clobber (match_operand:SI 5 "register_operand" ""))]
12645 "! gpc_reg_operand (operands[2], SImode)"
12646 [(set (match_dup 5) (match_dup 2))
12647 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12648 (match_dup 4)))])
12650 (define_insn "*plus_eqsi"
12651 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12652 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12653 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12654 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12655 "TARGET_32BIT"
12656 "@
12657 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12658 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12659 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12660 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12661 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12662 [(set_attr "type" "three,two,three,three,three")
12663 (set_attr "length" "12,8,12,12,12")])
12665 (define_insn "*compare_plus_eqsi"
12666 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12667 (compare:CC
12668 (plus:SI
12669 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12670 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12671 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12672 (const_int 0)))
12673 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12674 "TARGET_32BIT && optimize_size"
12675 "@
12676 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12677 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12678 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12679 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12680 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12681 #
12682 #
12683 #
12684 #
12685 #"
12686 [(set_attr "type" "compare")
12687 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12689 (define_split
12690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12691 (compare:CC
12692 (plus:SI
12693 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12694 (match_operand:SI 2 "scc_eq_operand" ""))
12695 (match_operand:SI 3 "gpc_reg_operand" ""))
12696 (const_int 0)))
12697 (clobber (match_scratch:SI 4 ""))]
12698 "TARGET_32BIT && optimize_size && reload_completed"
12699 [(set (match_dup 4)
12700 (plus:SI (eq:SI (match_dup 1)
12701 (match_dup 2))
12702 (match_dup 3)))
12703 (set (match_dup 0)
12704 (compare:CC (match_dup 4)
12705 (const_int 0)))]
12706 "")
12708 (define_insn "*plus_eqsi_compare"
12709 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12710 (compare:CC
12711 (plus:SI
12712 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12713 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12714 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12715 (const_int 0)))
12716 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12717 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12718 "TARGET_32BIT && optimize_size"
12719 "@
12720 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12721 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12722 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12723 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12724 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12725 #
12726 #
12727 #
12728 #
12729 #"
12730 [(set_attr "type" "compare")
12731 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12733 (define_split
12734 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12735 (compare:CC
12736 (plus:SI
12737 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12738 (match_operand:SI 2 "scc_eq_operand" ""))
12739 (match_operand:SI 3 "gpc_reg_operand" ""))
12740 (const_int 0)))
12741 (set (match_operand:SI 0 "gpc_reg_operand" "")
12742 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12743 "TARGET_32BIT && optimize_size && reload_completed"
12744 [(set (match_dup 0)
12745 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12746 (set (match_dup 4)
12747 (compare:CC (match_dup 0)
12748 (const_int 0)))]
12749 "")
12751 (define_insn "*neg_eq0<mode>"
12752 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12753 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12754 (const_int 0))))]
12755 ""
12756 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12757 [(set_attr "type" "two")
12758 (set_attr "length" "8")])
12760 (define_insn_and_split "*neg_eq<mode>"
12761 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12762 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12763 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12764 ""
12765 "#"
12766 ""
12767 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12768 {
12769 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12770 {
12771 /* Use output operand as intermediate. */
12772 operands[3] = operands[0];
12774 if (logical_operand (operands[2], <MODE>mode))
12775 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12776 gen_rtx_XOR (<MODE>mode,
12777 operands[1], operands[2])));
12778 else
12779 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12780 gen_rtx_PLUS (<MODE>mode, operands[1],
12781 negate_rtx (<MODE>mode,
12782 operands[2]))));
12783 }
12784 else
12785 operands[3] = operands[1];
12786 })
12788 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12789 ;; since it nabs/sr is just as fast.
12790 (define_insn "*ne0si"
12791 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12792 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12793 (const_int 31)))
12794 (clobber (match_scratch:SI 2 "=&r"))]
12795 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12796 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12797 [(set_attr "type" "two")
12798 (set_attr "length" "8")])
12800 (define_insn "*ne0di"
12801 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12802 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12803 (const_int 63)))
12804 (clobber (match_scratch:DI 2 "=&r"))]
12805 "TARGET_64BIT"
12806 "addic %2,%1,-1\;subfe %0,%2,%1"
12807 [(set_attr "type" "two")
12808 (set_attr "length" "8")])
12810 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12811 (define_insn "*plus_ne0si"
12812 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12813 (plus:SI (lshiftrt:SI
12814 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12815 (const_int 31))
12816 (match_operand:SI 2 "gpc_reg_operand" "r")))
12817 (clobber (match_scratch:SI 3 "=&r"))]
12818 "TARGET_32BIT"
12819 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12820 [(set_attr "type" "two")
12821 (set_attr "length" "8")])
12823 (define_insn "*plus_ne0di"
12824 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12825 (plus:DI (lshiftrt:DI
12826 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12827 (const_int 63))
12828 (match_operand:DI 2 "gpc_reg_operand" "r")))
12829 (clobber (match_scratch:DI 3 "=&r"))]
12830 "TARGET_64BIT"
12831 "addic %3,%1,-1\;addze %0,%2"
12832 [(set_attr "type" "two")
12833 (set_attr "length" "8")])
12835 (define_insn "*compare_plus_ne0si"
12836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12837 (compare:CC
12838 (plus:SI (lshiftrt:SI
12839 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12840 (const_int 31))
12841 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12842 (const_int 0)))
12843 (clobber (match_scratch:SI 3 "=&r,&r"))
12844 (clobber (match_scratch:SI 4 "=X,&r"))]
12845 "TARGET_32BIT"
12846 "@
12847 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12848 #"
12849 [(set_attr "type" "compare")
12850 (set_attr "length" "8,12")])
12852 (define_split
12853 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12854 (compare:CC
12855 (plus:SI (lshiftrt:SI
12856 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12857 (const_int 31))
12858 (match_operand:SI 2 "gpc_reg_operand" ""))
12859 (const_int 0)))
12860 (clobber (match_scratch:SI 3 ""))
12861 (clobber (match_scratch:SI 4 ""))]
12862 "TARGET_32BIT && reload_completed"
12863 [(parallel [(set (match_dup 3)
12864 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12865 (const_int 31))
12866 (match_dup 2)))
12867 (clobber (match_dup 4))])
12868 (set (match_dup 0)
12869 (compare:CC (match_dup 3)
12870 (const_int 0)))]
12871 "")
12873 (define_insn "*compare_plus_ne0di"
12874 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12875 (compare:CC
12876 (plus:DI (lshiftrt:DI
12877 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12878 (const_int 63))
12879 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12880 (const_int 0)))
12881 (clobber (match_scratch:DI 3 "=&r,&r"))]
12882 "TARGET_64BIT"
12883 "@
12884 addic %3,%1,-1\;addze. %3,%2
12885 #"
12886 [(set_attr "type" "compare")
12887 (set_attr "length" "8,12")])
12889 (define_split
12890 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12891 (compare:CC
12892 (plus:DI (lshiftrt:DI
12893 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12894 (const_int 63))
12895 (match_operand:DI 2 "gpc_reg_operand" ""))
12896 (const_int 0)))
12897 (clobber (match_scratch:DI 3 ""))]
12898 "TARGET_64BIT && reload_completed"
12899 [(set (match_dup 3)
12900 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12901 (const_int 63))
12902 (match_dup 2)))
12903 (set (match_dup 0)
12904 (compare:CC (match_dup 3)
12905 (const_int 0)))]
12906 "")
12908 (define_insn "*plus_ne0si_compare"
12909 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12910 (compare:CC
12911 (plus:SI (lshiftrt:SI
12912 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12913 (const_int 31))
12914 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12915 (const_int 0)))
12916 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12917 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12918 (match_dup 2)))
12919 (clobber (match_scratch:SI 3 "=&r,&r"))]
12920 "TARGET_32BIT"
12921 "@
12922 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12923 #"
12924 [(set_attr "type" "compare")
12925 (set_attr "length" "8,12")])
12927 (define_split
12928 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12929 (compare:CC
12930 (plus:SI (lshiftrt:SI
12931 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12932 (const_int 31))
12933 (match_operand:SI 2 "gpc_reg_operand" ""))
12934 (const_int 0)))
12935 (set (match_operand:SI 0 "gpc_reg_operand" "")
12936 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12937 (match_dup 2)))
12938 (clobber (match_scratch:SI 3 ""))]
12939 "TARGET_32BIT && reload_completed"
12940 [(parallel [(set (match_dup 0)
12941 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12942 (match_dup 2)))
12943 (clobber (match_dup 3))])
12944 (set (match_dup 4)
12945 (compare:CC (match_dup 0)
12946 (const_int 0)))]
12947 "")
12949 (define_insn "*plus_ne0di_compare"
12950 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12951 (compare:CC
12952 (plus:DI (lshiftrt:DI
12953 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12954 (const_int 63))
12955 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12956 (const_int 0)))
12957 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12958 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12959 (match_dup 2)))
12960 (clobber (match_scratch:DI 3 "=&r,&r"))]
12961 "TARGET_64BIT"
12962 "@
12963 addic %3,%1,-1\;addze. %0,%2
12964 #"
12965 [(set_attr "type" "compare")
12966 (set_attr "length" "8,12")])
12968 (define_split
12969 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12970 (compare:CC
12971 (plus:DI (lshiftrt:DI
12972 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12973 (const_int 63))
12974 (match_operand:DI 2 "gpc_reg_operand" ""))
12975 (const_int 0)))
12976 (set (match_operand:DI 0 "gpc_reg_operand" "")
12977 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12978 (match_dup 2)))
12979 (clobber (match_scratch:DI 3 ""))]
12980 "TARGET_64BIT && reload_completed"
12981 [(parallel [(set (match_dup 0)
12982 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12983 (match_dup 2)))
12984 (clobber (match_dup 3))])
12985 (set (match_dup 4)
12986 (compare:CC (match_dup 0)
12987 (const_int 0)))]
12988 "")
12990 (define_insn ""
12991 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12992 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12993 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12994 (clobber (match_scratch:SI 3 "=r,X"))]
12995 "TARGET_POWER"
12996 "@
12997 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12998 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12999 [(set_attr "length" "12")])
13001 (define_insn ""
13002 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13003 (compare:CC
13004 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13005 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13006 (const_int 0)))
13007 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13008 (le:SI (match_dup 1) (match_dup 2)))
13009 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13010 "TARGET_POWER"
13011 "@
13012 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13013 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13014 #
13015 #"
13016 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13017 (set_attr "length" "12,12,16,16")])
13019 (define_split
13020 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13021 (compare:CC
13022 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13023 (match_operand:SI 2 "reg_or_short_operand" ""))
13024 (const_int 0)))
13025 (set (match_operand:SI 0 "gpc_reg_operand" "")
13026 (le:SI (match_dup 1) (match_dup 2)))
13027 (clobber (match_scratch:SI 3 ""))]
13028 "TARGET_POWER && reload_completed"
13029 [(parallel [(set (match_dup 0)
13030 (le:SI (match_dup 1) (match_dup 2)))
13031 (clobber (match_dup 3))])
13032 (set (match_dup 4)
13033 (compare:CC (match_dup 0)
13034 (const_int 0)))]
13035 "")
13037 (define_insn ""
13038 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13039 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13040 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13041 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13042 "TARGET_POWER"
13043 "@
13044 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13045 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13046 [(set_attr "length" "12")])
13048 (define_insn ""
13049 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13050 (compare:CC
13051 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13052 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13053 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13054 (const_int 0)))
13055 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13056 "TARGET_POWER"
13057 "@
13058 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13059 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13060 #
13061 #"
13062 [(set_attr "type" "compare")
13063 (set_attr "length" "12,12,16,16")])
13065 (define_split
13066 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13067 (compare:CC
13068 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13069 (match_operand:SI 2 "reg_or_short_operand" ""))
13070 (match_operand:SI 3 "gpc_reg_operand" ""))
13071 (const_int 0)))
13072 (clobber (match_scratch:SI 4 ""))]
13073 "TARGET_POWER && reload_completed"
13074 [(set (match_dup 4)
13075 (plus:SI (le:SI (match_dup 1) (match_dup 2))
13076 (match_dup 3)))
13077 (set (match_dup 0)
13078 (compare:CC (match_dup 4)
13079 (const_int 0)))]
13080 "")
13082 (define_insn ""
13083 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13084 (compare:CC
13085 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13086 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13087 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13088 (const_int 0)))
13089 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13090 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13091 "TARGET_POWER"
13092 "@
13093 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13094 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13095 #
13096 #"
13097 [(set_attr "type" "compare")
13098 (set_attr "length" "12,12,16,16")])
13100 (define_split
13101 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13102 (compare:CC
13103 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13104 (match_operand:SI 2 "reg_or_short_operand" ""))
13105 (match_operand:SI 3 "gpc_reg_operand" ""))
13106 (const_int 0)))
13107 (set (match_operand:SI 0 "gpc_reg_operand" "")
13108 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13109 "TARGET_POWER && reload_completed"
13110 [(set (match_dup 0)
13111 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13112 (set (match_dup 4)
13113 (compare:CC (match_dup 0)
13114 (const_int 0)))]
13115 "")
13117 (define_insn ""
13118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13119 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13120 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13121 "TARGET_POWER"
13122 "@
13123 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13124 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13125 [(set_attr "length" "12")])
13127 (define_insn "*leu<mode>"
13128 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13129 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13130 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13131 ""
13132 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13133 [(set_attr "type" "three")
13134 (set_attr "length" "12")])
13136 (define_insn "*leu<mode>_compare"
13137 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13138 (compare:CC
13139 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13140 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13141 (const_int 0)))
13142 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13143 (leu:P (match_dup 1) (match_dup 2)))]
13144 ""
13145 "@
13146 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13147 #"
13148 [(set_attr "type" "compare")
13149 (set_attr "length" "12,16")])
13151 (define_split
13152 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13153 (compare:CC
13154 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13155 (match_operand:P 2 "reg_or_short_operand" ""))
13156 (const_int 0)))
13157 (set (match_operand:P 0 "gpc_reg_operand" "")
13158 (leu:P (match_dup 1) (match_dup 2)))]
13159 "reload_completed"
13160 [(set (match_dup 0)
13161 (leu:P (match_dup 1) (match_dup 2)))
13162 (set (match_dup 3)
13163 (compare:CC (match_dup 0)
13164 (const_int 0)))]
13165 "")
13167 (define_insn "*plus_leu<mode>"
13168 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13169 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13170 (match_operand:P 2 "reg_or_short_operand" "rI"))
13171 (match_operand:P 3 "gpc_reg_operand" "r")))]
13172 ""
13173 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13174 [(set_attr "type" "two")
13175 (set_attr "length" "8")])
13177 (define_insn ""
13178 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13179 (compare:CC
13180 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13181 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13182 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13183 (const_int 0)))
13184 (clobber (match_scratch:SI 4 "=&r,&r"))]
13185 "TARGET_32BIT"
13186 "@
13187 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13188 #"
13189 [(set_attr "type" "compare")
13190 (set_attr "length" "8,12")])
13192 (define_split
13193 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13194 (compare:CC
13195 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13196 (match_operand:SI 2 "reg_or_short_operand" ""))
13197 (match_operand:SI 3 "gpc_reg_operand" ""))
13198 (const_int 0)))
13199 (clobber (match_scratch:SI 4 ""))]
13200 "TARGET_32BIT && reload_completed"
13201 [(set (match_dup 4)
13202 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13203 (match_dup 3)))
13204 (set (match_dup 0)
13205 (compare:CC (match_dup 4)
13206 (const_int 0)))]
13207 "")
13209 (define_insn ""
13210 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13211 (compare:CC
13212 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13213 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13214 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13215 (const_int 0)))
13216 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13217 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13218 "TARGET_32BIT"
13219 "@
13220 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13221 #"
13222 [(set_attr "type" "compare")
13223 (set_attr "length" "8,12")])
13225 (define_split
13226 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13227 (compare:CC
13228 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13229 (match_operand:SI 2 "reg_or_short_operand" ""))
13230 (match_operand:SI 3 "gpc_reg_operand" ""))
13231 (const_int 0)))
13232 (set (match_operand:SI 0 "gpc_reg_operand" "")
13233 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13234 "TARGET_32BIT && reload_completed"
13235 [(set (match_dup 0)
13236 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13237 (set (match_dup 4)
13238 (compare:CC (match_dup 0)
13239 (const_int 0)))]
13240 "")
13242 (define_insn "*neg_leu<mode>"
13243 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13244 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13245 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13246 ""
13247 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13248 [(set_attr "type" "three")
13249 (set_attr "length" "12")])
13251 (define_insn "*and_neg_leu<mode>"
13252 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13253 (and:P (neg:P
13254 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13255 (match_operand:P 2 "reg_or_short_operand" "rI")))
13256 (match_operand:P 3 "gpc_reg_operand" "r")))]
13257 ""
13258 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13259 [(set_attr "type" "three")
13260 (set_attr "length" "12")])
13262 (define_insn ""
13263 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13264 (compare:CC
13265 (and:SI (neg:SI
13266 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13267 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13268 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13269 (const_int 0)))
13270 (clobber (match_scratch:SI 4 "=&r,&r"))]
13271 "TARGET_32BIT"
13272 "@
13273 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13274 #"
13275 [(set_attr "type" "compare")
13276 (set_attr "length" "12,16")])
13278 (define_split
13279 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13280 (compare:CC
13281 (and:SI (neg:SI
13282 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13283 (match_operand:SI 2 "reg_or_short_operand" "")))
13284 (match_operand:SI 3 "gpc_reg_operand" ""))
13285 (const_int 0)))
13286 (clobber (match_scratch:SI 4 ""))]
13287 "TARGET_32BIT && reload_completed"
13288 [(set (match_dup 4)
13289 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13290 (match_dup 3)))
13291 (set (match_dup 0)
13292 (compare:CC (match_dup 4)
13293 (const_int 0)))]
13294 "")
13296 (define_insn ""
13297 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13298 (compare:CC
13299 (and:SI (neg:SI
13300 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13301 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13302 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13303 (const_int 0)))
13304 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13305 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13306 "TARGET_32BIT"
13307 "@
13308 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13309 #"
13310 [(set_attr "type" "compare")
13311 (set_attr "length" "12,16")])
13313 (define_split
13314 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13315 (compare:CC
13316 (and:SI (neg:SI
13317 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13318 (match_operand:SI 2 "reg_or_short_operand" "")))
13319 (match_operand:SI 3 "gpc_reg_operand" ""))
13320 (const_int 0)))
13321 (set (match_operand:SI 0 "gpc_reg_operand" "")
13322 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13323 "TARGET_32BIT && reload_completed"
13324 [(set (match_dup 0)
13325 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13326 (match_dup 3)))
13327 (set (match_dup 4)
13328 (compare:CC (match_dup 0)
13329 (const_int 0)))]
13330 "")
13332 (define_insn ""
13333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13334 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13335 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13336 "TARGET_POWER"
13337 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13338 [(set_attr "length" "12")])
13340 (define_insn ""
13341 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13342 (compare:CC
13343 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13344 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13345 (const_int 0)))
13346 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13347 (lt:SI (match_dup 1) (match_dup 2)))]
13348 "TARGET_POWER"
13349 "@
13350 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13351 #"
13352 [(set_attr "type" "delayed_compare")
13353 (set_attr "length" "12,16")])
13355 (define_split
13356 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13357 (compare:CC
13358 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13359 (match_operand:SI 2 "reg_or_short_operand" ""))
13360 (const_int 0)))
13361 (set (match_operand:SI 0 "gpc_reg_operand" "")
13362 (lt:SI (match_dup 1) (match_dup 2)))]
13363 "TARGET_POWER && reload_completed"
13364 [(set (match_dup 0)
13365 (lt:SI (match_dup 1) (match_dup 2)))
13366 (set (match_dup 3)
13367 (compare:CC (match_dup 0)
13368 (const_int 0)))]
13369 "")
13371 (define_insn ""
13372 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13373 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13374 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13375 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13376 "TARGET_POWER"
13377 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13378 [(set_attr "length" "12")])
13380 (define_insn ""
13381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13382 (compare:CC
13383 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13384 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13385 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13386 (const_int 0)))
13387 (clobber (match_scratch:SI 4 "=&r,&r"))]
13388 "TARGET_POWER"
13389 "@
13390 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13391 #"
13392 [(set_attr "type" "compare")
13393 (set_attr "length" "12,16")])
13395 (define_split
13396 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13397 (compare:CC
13398 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13399 (match_operand:SI 2 "reg_or_short_operand" ""))
13400 (match_operand:SI 3 "gpc_reg_operand" ""))
13401 (const_int 0)))
13402 (clobber (match_scratch:SI 4 ""))]
13403 "TARGET_POWER && reload_completed"
13404 [(set (match_dup 4)
13405 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13406 (match_dup 3)))
13407 (set (match_dup 0)
13408 (compare:CC (match_dup 4)
13409 (const_int 0)))]
13410 "")
13412 (define_insn ""
13413 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13414 (compare:CC
13415 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13416 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13417 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13418 (const_int 0)))
13419 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13420 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13421 "TARGET_POWER"
13422 "@
13423 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13424 #"
13425 [(set_attr "type" "compare")
13426 (set_attr "length" "12,16")])
13428 (define_split
13429 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13430 (compare:CC
13431 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13432 (match_operand:SI 2 "reg_or_short_operand" ""))
13433 (match_operand:SI 3 "gpc_reg_operand" ""))
13434 (const_int 0)))
13435 (set (match_operand:SI 0 "gpc_reg_operand" "")
13436 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13437 "TARGET_POWER && reload_completed"
13438 [(set (match_dup 0)
13439 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13440 (set (match_dup 4)
13441 (compare:CC (match_dup 0)
13442 (const_int 0)))]
13443 "")
13445 (define_insn ""
13446 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13447 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13448 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13449 "TARGET_POWER"
13450 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13451 [(set_attr "length" "12")])
13453 (define_insn_and_split "*ltu<mode>"
13454 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13455 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13456 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13457 ""
13458 "#"
13459 ""
13460 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13461 (set (match_dup 0) (neg:P (match_dup 0)))]
13462 "")
13464 (define_insn_and_split "*ltu<mode>_compare"
13465 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13466 (compare:CC
13467 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13468 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13469 (const_int 0)))
13470 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13471 (ltu:P (match_dup 1) (match_dup 2)))]
13472 ""
13473 "#"
13474 ""
13475 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13476 (parallel [(set (match_dup 3)
13477 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13478 (set (match_dup 0) (neg:P (match_dup 0)))])]
13479 "")
13481 (define_insn_and_split "*plus_ltu<mode>"
13482 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13483 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13484 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13485 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13486 ""
13487 "#"
13488 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13489 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13490 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13491 "")
13493 (define_insn_and_split "*plus_ltu<mode>_compare"
13494 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13495 (compare:CC
13496 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13497 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13498 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13499 (const_int 0)))
13500 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13501 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13502 ""
13503 "#"
13504 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13505 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13506 (parallel [(set (match_dup 4)
13507 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13508 (const_int 0)))
13509 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13510 "")
13512 (define_insn "*neg_ltu<mode>"
13513 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13514 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13515 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13516 ""
13517 "@
13518 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13519 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13520 [(set_attr "type" "two")
13521 (set_attr "length" "8")])
13523 (define_insn ""
13524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13525 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13526 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13527 (clobber (match_scratch:SI 3 "=r"))]
13528 "TARGET_POWER"
13529 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13530 [(set_attr "length" "12")])
13532 (define_insn ""
13533 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13534 (compare:CC
13535 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13536 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13537 (const_int 0)))
13538 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13539 (ge:SI (match_dup 1) (match_dup 2)))
13540 (clobber (match_scratch:SI 3 "=r,r"))]
13541 "TARGET_POWER"
13542 "@
13543 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13544 #"
13545 [(set_attr "type" "compare")
13546 (set_attr "length" "12,16")])
13548 (define_split
13549 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13550 (compare:CC
13551 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13552 (match_operand:SI 2 "reg_or_short_operand" ""))
13553 (const_int 0)))
13554 (set (match_operand:SI 0 "gpc_reg_operand" "")
13555 (ge:SI (match_dup 1) (match_dup 2)))
13556 (clobber (match_scratch:SI 3 ""))]
13557 "TARGET_POWER && reload_completed"
13558 [(parallel [(set (match_dup 0)
13559 (ge:SI (match_dup 1) (match_dup 2)))
13560 (clobber (match_dup 3))])
13561 (set (match_dup 4)
13562 (compare:CC (match_dup 0)
13563 (const_int 0)))]
13564 "")
13566 (define_insn ""
13567 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13568 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13569 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13570 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13571 "TARGET_POWER"
13572 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13573 [(set_attr "length" "12")])
13575 (define_insn ""
13576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13577 (compare:CC
13578 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13579 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13580 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13581 (const_int 0)))
13582 (clobber (match_scratch:SI 4 "=&r,&r"))]
13583 "TARGET_POWER"
13584 "@
13585 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13586 #"
13587 [(set_attr "type" "compare")
13588 (set_attr "length" "12,16")])
13590 (define_split
13591 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13592 (compare:CC
13593 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13594 (match_operand:SI 2 "reg_or_short_operand" ""))
13595 (match_operand:SI 3 "gpc_reg_operand" ""))
13596 (const_int 0)))
13597 (clobber (match_scratch:SI 4 ""))]
13598 "TARGET_POWER && reload_completed"
13599 [(set (match_dup 4)
13600 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13601 (match_dup 3)))
13602 (set (match_dup 0)
13603 (compare:CC (match_dup 4)
13604 (const_int 0)))]
13605 "")
13607 (define_insn ""
13608 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13609 (compare:CC
13610 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13611 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13612 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13613 (const_int 0)))
13614 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13615 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13616 "TARGET_POWER"
13617 "@
13618 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13619 #"
13620 [(set_attr "type" "compare")
13621 (set_attr "length" "12,16")])
13623 (define_split
13624 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13625 (compare:CC
13626 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13627 (match_operand:SI 2 "reg_or_short_operand" ""))
13628 (match_operand:SI 3 "gpc_reg_operand" ""))
13629 (const_int 0)))
13630 (set (match_operand:SI 0 "gpc_reg_operand" "")
13631 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13632 "TARGET_POWER && reload_completed"
13633 [(set (match_dup 0)
13634 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13635 (set (match_dup 4)
13636 (compare:CC (match_dup 0)
13637 (const_int 0)))]
13638 "")
13640 (define_insn ""
13641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13642 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13643 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13644 "TARGET_POWER"
13645 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13646 [(set_attr "length" "12")])
13648 (define_insn "*geu<mode>"
13649 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13650 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13651 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13652 ""
13653 "@
13654 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13655 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13656 [(set_attr "type" "three")
13657 (set_attr "length" "12")])
13659 (define_insn "*geu<mode>_compare"
13660 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13661 (compare:CC
13662 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13663 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13664 (const_int 0)))
13665 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13666 (geu:P (match_dup 1) (match_dup 2)))]
13667 ""
13668 "@
13669 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13670 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13671 #
13672 #"
13673 [(set_attr "type" "compare")
13674 (set_attr "length" "12,12,16,16")])
13676 (define_split
13677 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13678 (compare:CC
13679 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13680 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13681 (const_int 0)))
13682 (set (match_operand:P 0 "gpc_reg_operand" "")
13683 (geu:P (match_dup 1) (match_dup 2)))]
13684 "reload_completed"
13685 [(set (match_dup 0)
13686 (geu:P (match_dup 1) (match_dup 2)))
13687 (set (match_dup 3)
13688 (compare:CC (match_dup 0)
13689 (const_int 0)))]
13690 "")
13692 (define_insn "*plus_geu<mode>"
13693 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13694 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13695 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13696 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13697 ""
13698 "@
13699 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13700 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13701 [(set_attr "type" "two")
13702 (set_attr "length" "8")])
13704 (define_insn ""
13705 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13706 (compare:CC
13707 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13708 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13709 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13710 (const_int 0)))
13711 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13712 "TARGET_32BIT"
13713 "@
13714 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13715 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13716 #
13717 #"
13718 [(set_attr "type" "compare")
13719 (set_attr "length" "8,8,12,12")])
13721 (define_split
13722 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13723 (compare:CC
13724 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13725 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13726 (match_operand:SI 3 "gpc_reg_operand" ""))
13727 (const_int 0)))
13728 (clobber (match_scratch:SI 4 ""))]
13729 "TARGET_32BIT && reload_completed"
13730 [(set (match_dup 4)
13731 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13732 (match_dup 3)))
13733 (set (match_dup 0)
13734 (compare:CC (match_dup 4)
13735 (const_int 0)))]
13736 "")
13738 (define_insn ""
13739 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13740 (compare:CC
13741 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13742 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13743 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13744 (const_int 0)))
13745 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13746 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13747 "TARGET_32BIT"
13748 "@
13749 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13750 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13751 #
13752 #"
13753 [(set_attr "type" "compare")
13754 (set_attr "length" "8,8,12,12")])
13756 (define_split
13757 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13758 (compare:CC
13759 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13760 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13761 (match_operand:SI 3 "gpc_reg_operand" ""))
13762 (const_int 0)))
13763 (set (match_operand:SI 0 "gpc_reg_operand" "")
13764 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13765 "TARGET_32BIT && reload_completed"
13766 [(set (match_dup 0)
13767 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13768 (set (match_dup 4)
13769 (compare:CC (match_dup 0)
13770 (const_int 0)))]
13771 "")
13773 (define_insn "*neg_geu<mode>"
13774 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13775 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13776 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13777 ""
13778 "@
13779 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13780 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13781 [(set_attr "type" "three")
13782 (set_attr "length" "12")])
13784 (define_insn "*and_neg_geu<mode>"
13785 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13786 (and:P (neg:P
13787 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13788 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13789 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13790 ""
13791 "@
13792 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13793 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13794 [(set_attr "type" "three")
13795 (set_attr "length" "12")])
13797 (define_insn ""
13798 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13799 (compare:CC
13800 (and:SI (neg:SI
13801 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13802 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13803 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13804 (const_int 0)))
13805 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13806 "TARGET_32BIT"
13807 "@
13808 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13809 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13810 #
13811 #"
13812 [(set_attr "type" "compare")
13813 (set_attr "length" "12,12,16,16")])
13815 (define_split
13816 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13817 (compare:CC
13818 (and:SI (neg:SI
13819 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13820 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13821 (match_operand:SI 3 "gpc_reg_operand" ""))
13822 (const_int 0)))
13823 (clobber (match_scratch:SI 4 ""))]
13824 "TARGET_32BIT && reload_completed"
13825 [(set (match_dup 4)
13826 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13827 (match_dup 3)))
13828 (set (match_dup 0)
13829 (compare:CC (match_dup 4)
13830 (const_int 0)))]
13831 "")
13833 (define_insn ""
13834 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13835 (compare:CC
13836 (and:SI (neg:SI
13837 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13838 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13839 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13840 (const_int 0)))
13841 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13842 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13843 "TARGET_32BIT"
13844 "@
13845 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13846 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13847 #
13848 #"
13849 [(set_attr "type" "compare")
13850 (set_attr "length" "12,12,16,16")])
13852 (define_split
13853 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13854 (compare:CC
13855 (and:SI (neg:SI
13856 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13857 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13858 (match_operand:SI 3 "gpc_reg_operand" ""))
13859 (const_int 0)))
13860 (set (match_operand:SI 0 "gpc_reg_operand" "")
13861 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13862 "TARGET_32BIT && reload_completed"
13863 [(set (match_dup 0)
13864 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13865 (set (match_dup 4)
13866 (compare:CC (match_dup 0)
13867 (const_int 0)))]
13868 "")
13870 (define_insn ""
13871 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13872 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13873 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13874 "TARGET_POWER"
13875 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13876 [(set_attr "length" "12")])
13878 (define_insn ""
13879 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13880 (compare:CC
13881 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13882 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13883 (const_int 0)))
13884 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13885 (gt:SI (match_dup 1) (match_dup 2)))]
13886 "TARGET_POWER"
13887 "@
13888 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13889 #"
13890 [(set_attr "type" "delayed_compare")
13891 (set_attr "length" "12,16")])
13893 (define_split
13894 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13895 (compare:CC
13896 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13897 (match_operand:SI 2 "reg_or_short_operand" ""))
13898 (const_int 0)))
13899 (set (match_operand:SI 0 "gpc_reg_operand" "")
13900 (gt:SI (match_dup 1) (match_dup 2)))]
13901 "TARGET_POWER && reload_completed"
13902 [(set (match_dup 0)
13903 (gt:SI (match_dup 1) (match_dup 2)))
13904 (set (match_dup 3)
13905 (compare:CC (match_dup 0)
13906 (const_int 0)))]
13907 "")
13909 (define_insn "*plus_gt0<mode>"
13910 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13911 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13912 (const_int 0))
13913 (match_operand:P 2 "gpc_reg_operand" "r")))]
13914 ""
13915 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13916 [(set_attr "type" "three")
13917 (set_attr "length" "12")])
13919 (define_insn ""
13920 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13921 (compare:CC
13922 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13923 (const_int 0))
13924 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13925 (const_int 0)))
13926 (clobber (match_scratch:SI 3 "=&r,&r"))]
13927 "TARGET_32BIT"
13928 "@
13929 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13930 #"
13931 [(set_attr "type" "compare")
13932 (set_attr "length" "12,16")])
13934 (define_split
13935 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13936 (compare:CC
13937 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13938 (const_int 0))
13939 (match_operand:SI 2 "gpc_reg_operand" ""))
13940 (const_int 0)))
13941 (clobber (match_scratch:SI 3 ""))]
13942 "TARGET_32BIT && reload_completed"
13943 [(set (match_dup 3)
13944 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13945 (match_dup 2)))
13946 (set (match_dup 0)
13947 (compare:CC (match_dup 3)
13948 (const_int 0)))]
13949 "")
13951 (define_insn ""
13952 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13953 (compare:CC
13954 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13955 (const_int 0))
13956 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13957 (const_int 0)))
13958 (clobber (match_scratch:DI 3 "=&r,&r"))]
13959 "TARGET_64BIT"
13960 "@
13961 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13962 #"
13963 [(set_attr "type" "compare")
13964 (set_attr "length" "12,16")])
13966 (define_split
13967 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13968 (compare:CC
13969 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13970 (const_int 0))
13971 (match_operand:DI 2 "gpc_reg_operand" ""))
13972 (const_int 0)))
13973 (clobber (match_scratch:DI 3 ""))]
13974 "TARGET_64BIT && reload_completed"
13975 [(set (match_dup 3)
13976 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13977 (match_dup 2)))
13978 (set (match_dup 0)
13979 (compare:CC (match_dup 3)
13980 (const_int 0)))]
13981 "")
13983 (define_insn ""
13984 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13985 (compare:CC
13986 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13987 (const_int 0))
13988 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13989 (const_int 0)))
13990 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13991 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13992 "TARGET_32BIT"
13993 "@
13994 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13995 #"
13996 [(set_attr "type" "compare")
13997 (set_attr "length" "12,16")])
13999 (define_split
14000 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14001 (compare:CC
14002 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14003 (const_int 0))
14004 (match_operand:SI 2 "gpc_reg_operand" ""))
14005 (const_int 0)))
14006 (set (match_operand:SI 0 "gpc_reg_operand" "")
14007 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14008 "TARGET_32BIT && reload_completed"
14009 [(set (match_dup 0)
14010 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14011 (set (match_dup 3)
14012 (compare:CC (match_dup 0)
14013 (const_int 0)))]
14014 "")
14016 (define_insn ""
14017 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14018 (compare:CC
14019 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14020 (const_int 0))
14021 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14022 (const_int 0)))
14023 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14024 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14025 "TARGET_64BIT"
14026 "@
14027 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14028 #"
14029 [(set_attr "type" "compare")
14030 (set_attr "length" "12,16")])
14032 (define_split
14033 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14034 (compare:CC
14035 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14036 (const_int 0))
14037 (match_operand:DI 2 "gpc_reg_operand" ""))
14038 (const_int 0)))
14039 (set (match_operand:DI 0 "gpc_reg_operand" "")
14040 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14041 "TARGET_64BIT && reload_completed"
14042 [(set (match_dup 0)
14043 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14044 (set (match_dup 3)
14045 (compare:CC (match_dup 0)
14046 (const_int 0)))]
14047 "")
14049 (define_insn ""
14050 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14051 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14052 (match_operand:SI 2 "reg_or_short_operand" "r"))
14053 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14054 "TARGET_POWER"
14055 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14056 [(set_attr "length" "12")])
14058 (define_insn ""
14059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14060 (compare:CC
14061 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14062 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14063 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14064 (const_int 0)))
14065 (clobber (match_scratch:SI 4 "=&r,&r"))]
14066 "TARGET_POWER"
14067 "@
14068 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14069 #"
14070 [(set_attr "type" "compare")
14071 (set_attr "length" "12,16")])
14073 (define_split
14074 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14075 (compare:CC
14076 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14077 (match_operand:SI 2 "reg_or_short_operand" ""))
14078 (match_operand:SI 3 "gpc_reg_operand" ""))
14079 (const_int 0)))
14080 (clobber (match_scratch:SI 4 ""))]
14081 "TARGET_POWER && reload_completed"
14082 [(set (match_dup 4)
14083 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14084 (set (match_dup 0)
14085 (compare:CC (match_dup 4)
14086 (const_int 0)))]
14087 "")
14089 (define_insn ""
14090 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14091 (compare:CC
14092 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14093 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14094 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14095 (const_int 0)))
14096 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14097 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14098 "TARGET_POWER"
14099 "@
14100 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14101 #"
14102 [(set_attr "type" "compare")
14103 (set_attr "length" "12,16")])
14105 (define_split
14106 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14107 (compare:CC
14108 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14109 (match_operand:SI 2 "reg_or_short_operand" ""))
14110 (match_operand:SI 3 "gpc_reg_operand" ""))
14111 (const_int 0)))
14112 (set (match_operand:SI 0 "gpc_reg_operand" "")
14113 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14114 "TARGET_POWER && reload_completed"
14115 [(set (match_dup 0)
14116 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14117 (set (match_dup 4)
14118 (compare:CC (match_dup 0)
14119 (const_int 0)))]
14120 "")
14122 (define_insn ""
14123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14124 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14125 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14126 "TARGET_POWER"
14127 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14128 [(set_attr "length" "12")])
14130 (define_insn_and_split "*gtu<mode>"
14131 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14132 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14133 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14134 ""
14135 "#"
14136 ""
14137 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14138 (set (match_dup 0) (neg:P (match_dup 0)))]
14139 "")
14141 (define_insn_and_split "*gtu<mode>_compare"
14142 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14143 (compare:CC
14144 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14145 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14146 (const_int 0)))
14147 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14148 (gtu:P (match_dup 1) (match_dup 2)))]
14149 ""
14150 "#"
14151 ""
14152 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14153 (parallel [(set (match_dup 3)
14154 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14155 (set (match_dup 0) (neg:P (match_dup 0)))])]
14156 "")
14158 (define_insn_and_split "*plus_gtu<mode>"
14159 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14160 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14161 (match_operand:P 2 "reg_or_short_operand" "rI"))
14162 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14163 ""
14164 "#"
14165 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14166 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14167 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14168 "")
14170 (define_insn_and_split "*plus_gtu<mode>_compare"
14171 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14172 (compare:CC
14173 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14174 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14175 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14176 (const_int 0)))
14177 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14178 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14179 ""
14180 "#"
14181 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14182 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14183 (parallel [(set (match_dup 4)
14184 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14185 (const_int 0)))
14186 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14187 "")
14189 (define_insn "*neg_gtu<mode>"
14190 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14191 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14192 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14193 ""
14194 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14195 [(set_attr "type" "two")
14196 (set_attr "length" "8")])
14198 \f
14199 ;; Define both directions of branch and return. If we need a reload
14200 ;; register, we'd rather use CR0 since it is much easier to copy a
14201 ;; register CC value to there.
14203 (define_insn ""
14204 [(set (pc)
14205 (if_then_else (match_operator 1 "branch_comparison_operator"
14206 [(match_operand 2
14207 "cc_reg_operand" "y")
14208 (const_int 0)])
14209 (label_ref (match_operand 0 "" ""))
14210 (pc)))]
14211 ""
14212 "*
14213 {
14214 return output_cbranch (operands[1], \"%l0\", 0, insn);
14215 }"
14216 [(set_attr "type" "branch")])
14218 (define_insn ""
14219 [(set (pc)
14220 (if_then_else (match_operator 0 "branch_comparison_operator"
14221 [(match_operand 1
14222 "cc_reg_operand" "y")
14223 (const_int 0)])
14224 (return)
14225 (pc)))]
14226 "direct_return ()"
14227 "*
14228 {
14229 return output_cbranch (operands[0], NULL, 0, insn);
14230 }"
14231 [(set_attr "type" "jmpreg")
14232 (set_attr "length" "4")])
14234 (define_insn ""
14235 [(set (pc)
14236 (if_then_else (match_operator 1 "branch_comparison_operator"
14237 [(match_operand 2
14238 "cc_reg_operand" "y")
14239 (const_int 0)])
14240 (pc)
14241 (label_ref (match_operand 0 "" ""))))]
14242 ""
14243 "*
14244 {
14245 return output_cbranch (operands[1], \"%l0\", 1, insn);
14246 }"
14247 [(set_attr "type" "branch")])
14249 (define_insn ""
14250 [(set (pc)
14251 (if_then_else (match_operator 0 "branch_comparison_operator"
14252 [(match_operand 1
14253 "cc_reg_operand" "y")
14254 (const_int 0)])
14255 (pc)
14256 (return)))]
14257 "direct_return ()"
14258 "*
14259 {
14260 return output_cbranch (operands[0], NULL, 1, insn);
14261 }"
14262 [(set_attr "type" "jmpreg")
14263 (set_attr "length" "4")])
14265 ;; Logic on condition register values.
14267 ; This pattern matches things like
14268 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14269 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14270 ; (const_int 1)))
14271 ; which are generated by the branch logic.
14272 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14274 (define_insn "*cceq_ior_compare"
14275 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14276 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14277 [(match_operator:SI 2
14278 "branch_positive_comparison_operator"
14279 [(match_operand 3
14280 "cc_reg_operand" "y,y")
14281 (const_int 0)])
14282 (match_operator:SI 4
14283 "branch_positive_comparison_operator"
14284 [(match_operand 5
14285 "cc_reg_operand" "0,y")
14286 (const_int 0)])])
14287 (const_int 1)))]
14288 ""
14289 "cr%q1 %E0,%j2,%j4"
14290 [(set_attr "type" "cr_logical,delayed_cr")])
14292 ; Why is the constant -1 here, but 1 in the previous pattern?
14293 ; Because ~1 has all but the low bit set.
14294 (define_insn ""
14295 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14296 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14297 [(not:SI (match_operator:SI 2
14298 "branch_positive_comparison_operator"
14299 [(match_operand 3
14300 "cc_reg_operand" "y,y")
14301 (const_int 0)]))
14302 (match_operator:SI 4
14303 "branch_positive_comparison_operator"
14304 [(match_operand 5
14305 "cc_reg_operand" "0,y")
14306 (const_int 0)])])
14307 (const_int -1)))]
14308 ""
14309 "cr%q1 %E0,%j2,%j4"
14310 [(set_attr "type" "cr_logical,delayed_cr")])
14312 (define_insn "*cceq_rev_compare"
14313 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14314 (compare:CCEQ (match_operator:SI 1
14315 "branch_positive_comparison_operator"
14316 [(match_operand 2
14317 "cc_reg_operand" "0,y")
14318 (const_int 0)])
14319 (const_int 0)))]
14320 ""
14321 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14322 [(set_attr "type" "cr_logical,delayed_cr")])
14324 ;; If we are comparing the result of two comparisons, this can be done
14325 ;; using creqv or crxor.
14327 (define_insn_and_split ""
14328 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14329 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14330 [(match_operand 2 "cc_reg_operand" "y")
14331 (const_int 0)])
14332 (match_operator 3 "branch_comparison_operator"
14333 [(match_operand 4 "cc_reg_operand" "y")
14334 (const_int 0)])))]
14335 ""
14336 "#"
14337 ""
14338 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14339 (match_dup 5)))]
14340 "
14341 {
14342 int positive_1, positive_2;
14344 positive_1 = branch_positive_comparison_operator (operands[1],
14345 GET_MODE (operands[1]));
14346 positive_2 = branch_positive_comparison_operator (operands[3],
14347 GET_MODE (operands[3]));
14349 if (! positive_1)
14350 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14351 GET_CODE (operands[1])),
14352 SImode,
14353 operands[2], const0_rtx);
14354 else if (GET_MODE (operands[1]) != SImode)
14355 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14356 operands[2], const0_rtx);
14358 if (! positive_2)
14359 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14360 GET_CODE (operands[3])),
14361 SImode,
14362 operands[4], const0_rtx);
14363 else if (GET_MODE (operands[3]) != SImode)
14364 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14365 operands[4], const0_rtx);
14367 if (positive_1 == positive_2)
14368 {
14369 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14370 operands[5] = constm1_rtx;
14371 }
14372 else
14373 {
14374 operands[5] = const1_rtx;
14375 }
14376 }")
14378 ;; Unconditional branch and return.
14380 (define_insn "jump"
14381 [(set (pc)
14382 (label_ref (match_operand 0 "" "")))]
14383 ""
14384 "b %l0"
14385 [(set_attr "type" "branch")])
14387 (define_insn "return"
14388 [(return)]
14389 "direct_return ()"
14390 "{br|blr}"
14391 [(set_attr "type" "jmpreg")])
14393 (define_expand "indirect_jump"
14394 [(set (pc) (match_operand 0 "register_operand" ""))])
14396 (define_insn "*indirect_jump<mode>"
14397 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14398 ""
14399 "@
14400 bctr
14401 {br|blr}"
14402 [(set_attr "type" "jmpreg")])
14404 ;; Table jump for switch statements:
14405 (define_expand "tablejump"
14406 [(use (match_operand 0 "" ""))
14407 (use (label_ref (match_operand 1 "" "")))]
14408 ""
14409 "
14410 {
14411 if (TARGET_32BIT)
14412 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14413 else
14414 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14415 DONE;
14416 }")
14418 (define_expand "tablejumpsi"
14419 [(set (match_dup 3)
14420 (plus:SI (match_operand:SI 0 "" "")
14421 (match_dup 2)))
14422 (parallel [(set (pc) (match_dup 3))
14423 (use (label_ref (match_operand 1 "" "")))])]
14424 "TARGET_32BIT"
14425 "
14426 { operands[0] = force_reg (SImode, operands[0]);
14427 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14428 operands[3] = gen_reg_rtx (SImode);
14429 }")
14431 (define_expand "tablejumpdi"
14432 [(set (match_dup 4)
14433 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14434 (set (match_dup 3)
14435 (plus:DI (match_dup 4)
14436 (match_dup 2)))
14437 (parallel [(set (pc) (match_dup 3))
14438 (use (label_ref (match_operand 1 "" "")))])]
14439 "TARGET_64BIT"
14440 "
14441 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14442 operands[3] = gen_reg_rtx (DImode);
14443 operands[4] = gen_reg_rtx (DImode);
14444 }")
14446 (define_insn "*tablejump<mode>_internal1"
14447 [(set (pc)
14448 (match_operand:P 0 "register_operand" "c,*l"))
14449 (use (label_ref (match_operand 1 "" "")))]
14450 ""
14451 "@
14452 bctr
14453 {br|blr}"
14454 [(set_attr "type" "jmpreg")])
14456 (define_insn "nop"
14457 [(const_int 0)]
14458 ""
14459 "{cror 0,0,0|nop}")
14460 \f
14461 ;; Define the subtract-one-and-jump insns, starting with the template
14462 ;; so loop.c knows what to generate.
14464 (define_expand "doloop_end"
14465 [(use (match_operand 0 "" "")) ; loop pseudo
14466 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14467 (use (match_operand 2 "" "")) ; max iterations
14468 (use (match_operand 3 "" "")) ; loop level
14469 (use (match_operand 4 "" ""))] ; label
14470 ""
14471 "
14472 {
14473 /* Only use this on innermost loops. */
14474 if (INTVAL (operands[3]) > 1)
14475 FAIL;
14476 if (TARGET_64BIT)
14477 {
14478 if (GET_MODE (operands[0]) != DImode)
14479 FAIL;
14480 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14481 }
14482 else
14483 {
14484 if (GET_MODE (operands[0]) != SImode)
14485 FAIL;
14486 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14487 }
14488 DONE;
14489 }")
14491 (define_expand "ctr<mode>"
14492 [(parallel [(set (pc)
14493 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14494 (const_int 1))
14495 (label_ref (match_operand 1 "" ""))
14496 (pc)))
14497 (set (match_dup 0)
14498 (plus:P (match_dup 0)
14499 (const_int -1)))
14500 (clobber (match_scratch:CC 2 ""))
14501 (clobber (match_scratch:P 3 ""))])]
14502 ""
14503 "")
14505 ;; We need to be able to do this for any operand, including MEM, or we
14506 ;; will cause reload to blow up since we don't allow output reloads on
14507 ;; JUMP_INSNs.
14508 ;; For the length attribute to be calculated correctly, the
14509 ;; label MUST be operand 0.
14511 (define_insn "*ctr<mode>_internal1"
14512 [(set (pc)
14513 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14514 (const_int 1))
14515 (label_ref (match_operand 0 "" ""))
14516 (pc)))
14517 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14518 (plus:P (match_dup 1)
14519 (const_int -1)))
14520 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14521 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14522 ""
14523 "*
14524 {
14525 if (which_alternative != 0)
14526 return \"#\";
14527 else if (get_attr_length (insn) == 4)
14528 return \"{bdn|bdnz} %l0\";
14529 else
14530 return \"bdz $+8\;b %l0\";
14531 }"
14532 [(set_attr "type" "branch")
14533 (set_attr "length" "*,12,16,16")])
14535 (define_insn "*ctr<mode>_internal2"
14536 [(set (pc)
14537 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14538 (const_int 1))
14539 (pc)
14540 (label_ref (match_operand 0 "" ""))))
14541 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14542 (plus:P (match_dup 1)
14543 (const_int -1)))
14544 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14545 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14546 ""
14547 "*
14548 {
14549 if (which_alternative != 0)
14550 return \"#\";
14551 else if (get_attr_length (insn) == 4)
14552 return \"bdz %l0\";
14553 else
14554 return \"{bdn|bdnz} $+8\;b %l0\";
14555 }"
14556 [(set_attr "type" "branch")
14557 (set_attr "length" "*,12,16,16")])
14559 ;; Similar but use EQ
14561 (define_insn "*ctr<mode>_internal5"
14562 [(set (pc)
14563 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14564 (const_int 1))
14565 (label_ref (match_operand 0 "" ""))
14566 (pc)))
14567 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14568 (plus:P (match_dup 1)
14569 (const_int -1)))
14570 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14571 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14572 ""
14573 "*
14574 {
14575 if (which_alternative != 0)
14576 return \"#\";
14577 else if (get_attr_length (insn) == 4)
14578 return \"bdz %l0\";
14579 else
14580 return \"{bdn|bdnz} $+8\;b %l0\";
14581 }"
14582 [(set_attr "type" "branch")
14583 (set_attr "length" "*,12,16,16")])
14585 (define_insn "*ctr<mode>_internal6"
14586 [(set (pc)
14587 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14588 (const_int 1))
14589 (pc)
14590 (label_ref (match_operand 0 "" ""))))
14591 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14592 (plus:P (match_dup 1)
14593 (const_int -1)))
14594 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14595 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14596 ""
14597 "*
14598 {
14599 if (which_alternative != 0)
14600 return \"#\";
14601 else if (get_attr_length (insn) == 4)
14602 return \"{bdn|bdnz} %l0\";
14603 else
14604 return \"bdz $+8\;b %l0\";
14605 }"
14606 [(set_attr "type" "branch")
14607 (set_attr "length" "*,12,16,16")])
14609 ;; Now the splitters if we could not allocate the CTR register
14611 (define_split
14612 [(set (pc)
14613 (if_then_else (match_operator 2 "comparison_operator"
14614 [(match_operand:P 1 "gpc_reg_operand" "")
14615 (const_int 1)])
14616 (match_operand 5 "" "")
14617 (match_operand 6 "" "")))
14618 (set (match_operand:P 0 "gpc_reg_operand" "")
14619 (plus:P (match_dup 1) (const_int -1)))
14620 (clobber (match_scratch:CC 3 ""))
14621 (clobber (match_scratch:P 4 ""))]
14622 "reload_completed"
14623 [(parallel [(set (match_dup 3)
14624 (compare:CC (plus:P (match_dup 1)
14625 (const_int -1))
14626 (const_int 0)))
14627 (set (match_dup 0)
14628 (plus:P (match_dup 1)
14629 (const_int -1)))])
14630 (set (pc) (if_then_else (match_dup 7)
14631 (match_dup 5)
14632 (match_dup 6)))]
14633 "
14634 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14635 operands[3], const0_rtx); }")
14637 (define_split
14638 [(set (pc)
14639 (if_then_else (match_operator 2 "comparison_operator"
14640 [(match_operand:P 1 "gpc_reg_operand" "")
14641 (const_int 1)])
14642 (match_operand 5 "" "")
14643 (match_operand 6 "" "")))
14644 (set (match_operand:P 0 "nonimmediate_operand" "")
14645 (plus:P (match_dup 1) (const_int -1)))
14646 (clobber (match_scratch:CC 3 ""))
14647 (clobber (match_scratch:P 4 ""))]
14648 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14649 [(parallel [(set (match_dup 3)
14650 (compare:CC (plus:P (match_dup 1)
14651 (const_int -1))
14652 (const_int 0)))
14653 (set (match_dup 4)
14654 (plus:P (match_dup 1)
14655 (const_int -1)))])
14656 (set (match_dup 0)
14657 (match_dup 4))
14658 (set (pc) (if_then_else (match_dup 7)
14659 (match_dup 5)
14660 (match_dup 6)))]
14661 "
14662 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14663 operands[3], const0_rtx); }")
14664 \f
14665 (define_insn "trap"
14666 [(trap_if (const_int 1) (const_int 0))]
14667 ""
14668 "{t 31,0,0|trap}"
14669 [(set_attr "type" "trap")])
14671 (define_expand "conditional_trap"
14672 [(trap_if (match_operator 0 "trap_comparison_operator"
14673 [(match_dup 2) (match_dup 3)])
14674 (match_operand 1 "const_int_operand" ""))]
14675 ""
14676 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14677 operands[2] = rs6000_compare_op0;
14678 operands[3] = rs6000_compare_op1;")
14680 (define_insn ""
14681 [(trap_if (match_operator 0 "trap_comparison_operator"
14682 [(match_operand:GPR 1 "register_operand" "r")
14683 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14684 (const_int 0))]
14685 ""
14686 "{t|t<wd>}%V0%I2 %1,%2"
14687 [(set_attr "type" "trap")])
14688 \f
14689 ;; Insns related to generating the function prologue and epilogue.
14691 (define_expand "prologue"
14692 [(use (const_int 0))]
14693 "TARGET_SCHED_PROLOG"
14694 "
14695 {
14696 rs6000_emit_prologue ();
14697 DONE;
14698 }")
14700 (define_insn "*movesi_from_cr_one"
14701 [(match_parallel 0 "mfcr_operation"
14702 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14703 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14704 (match_operand 3 "immediate_operand" "n")]
14705 UNSPEC_MOVESI_FROM_CR))])]
14706 "TARGET_MFCRF"
14707 "*
14708 {
14709 int mask = 0;
14710 int i;
14711 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14712 {
14713 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14714 operands[4] = GEN_INT (mask);
14715 output_asm_insn (\"mfcr %1,%4\", operands);
14716 }
14717 return \"\";
14718 }"
14719 [(set_attr "type" "mfcrf")])
14721 (define_insn "movesi_from_cr"
14722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14723 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14724 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14725 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14726 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14727 UNSPEC_MOVESI_FROM_CR))]
14728 ""
14729 "mfcr %0"
14730 [(set_attr "type" "mfcr")])
14732 (define_insn "*stmw"
14733 [(match_parallel 0 "stmw_operation"
14734 [(set (match_operand:SI 1 "memory_operand" "=m")
14735 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14736 "TARGET_MULTIPLE"
14737 "{stm|stmw} %2,%1"
14738 [(set_attr "type" "store_ux")])
14740 (define_insn "*save_gpregs_<mode>"
14741 [(match_parallel 0 "any_parallel_operand"
14742 [(clobber (reg:P 65))
14743 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14744 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14745 (set (match_operand:P 3 "memory_operand" "=m")
14746 (match_operand:P 4 "gpc_reg_operand" "r"))])]
14747 ""
14748 "bl %z1"
14749 [(set_attr "type" "branch")
14750 (set_attr "length" "4")])
14752 (define_insn "*save_fpregs_<mode>"
14753 [(match_parallel 0 "any_parallel_operand"
14754 [(clobber (reg:P 65))
14755 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14756 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14757 (set (match_operand:DF 3 "memory_operand" "=m")
14758 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14759 ""
14760 "bl %z1"
14761 [(set_attr "type" "branch")
14762 (set_attr "length" "4")])
14764 ; These are to explain that changes to the stack pointer should
14765 ; not be moved over stores to stack memory.
14766 (define_insn "stack_tie"
14767 [(set (match_operand:BLK 0 "memory_operand" "+m")
14768 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14769 ""
14770 ""
14771 [(set_attr "length" "0")])
14774 (define_expand "epilogue"
14775 [(use (const_int 0))]
14776 "TARGET_SCHED_PROLOG"
14777 "
14778 {
14779 rs6000_emit_epilogue (FALSE);
14780 DONE;
14781 }")
14783 ; On some processors, doing the mtcrf one CC register at a time is
14784 ; faster (like on the 604e). On others, doing them all at once is
14785 ; faster; for instance, on the 601 and 750.
14787 (define_expand "movsi_to_cr_one"
14788 [(set (match_operand:CC 0 "cc_reg_operand" "")
14789 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14790 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14791 ""
14792 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14794 (define_insn "*movsi_to_cr"
14795 [(match_parallel 0 "mtcrf_operation"
14796 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14797 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14798 (match_operand 3 "immediate_operand" "n")]
14799 UNSPEC_MOVESI_TO_CR))])]
14800 ""
14801 "*
14802 {
14803 int mask = 0;
14804 int i;
14805 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14806 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14807 operands[4] = GEN_INT (mask);
14808 return \"mtcrf %4,%2\";
14809 }"
14810 [(set_attr "type" "mtcr")])
14812 (define_insn "*mtcrfsi"
14813 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14814 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14815 (match_operand 2 "immediate_operand" "n")]
14816 UNSPEC_MOVESI_TO_CR))]
14817 "GET_CODE (operands[0]) == REG
14818 && CR_REGNO_P (REGNO (operands[0]))
14819 && GET_CODE (operands[2]) == CONST_INT
14820 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14821 "mtcrf %R0,%1"
14822 [(set_attr "type" "mtcr")])
14824 ; The load-multiple instructions have similar properties.
14825 ; Note that "load_multiple" is a name known to the machine-independent
14826 ; code that actually corresponds to the PowerPC load-string.
14828 (define_insn "*lmw"
14829 [(match_parallel 0 "lmw_operation"
14830 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14831 (match_operand:SI 2 "memory_operand" "m"))])]
14832 "TARGET_MULTIPLE"
14833 "{lm|lmw} %1,%2"
14834 [(set_attr "type" "load_ux")
14835 (set_attr "cell_micro" "always")])
14837 (define_insn "*return_internal_<mode>"
14838 [(return)
14839 (use (match_operand:P 0 "register_operand" "lc"))]
14840 ""
14841 "b%T0"
14842 [(set_attr "type" "jmpreg")])
14844 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14845 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14847 (define_insn "*restore_gpregs_<mode>"
14848 [(match_parallel 0 "any_parallel_operand"
14849 [(clobber (match_operand:P 1 "register_operand" "=l"))
14850 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14851 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14852 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14853 (match_operand:P 5 "memory_operand" "m"))])]
14854 ""
14855 "bl %z2"
14856 [(set_attr "type" "branch")
14857 (set_attr "length" "4")])
14859 (define_insn "*return_and_restore_gpregs_<mode>"
14860 [(match_parallel 0 "any_parallel_operand"
14861 [(return)
14862 (clobber (match_operand:P 1 "register_operand" "=l"))
14863 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14864 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14865 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14866 (match_operand:P 5 "memory_operand" "m"))])]
14867 ""
14868 "b %z2"
14869 [(set_attr "type" "branch")
14870 (set_attr "length" "4")])
14872 (define_insn "*return_and_restore_fpregs_<mode>"
14873 [(match_parallel 0 "any_parallel_operand"
14874 [(return)
14875 (clobber (match_operand:P 1 "register_operand" "=l"))
14876 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14877 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14878 (set (match_operand:DF 4 "gpc_reg_operand" "=f")
14879 (match_operand:DF 5 "memory_operand" "m"))])]
14880 ""
14881 "b %z2"
14882 [(set_attr "type" "branch")
14883 (set_attr "length" "4")])
14885 ; This is used in compiling the unwind routines.
14886 (define_expand "eh_return"
14887 [(use (match_operand 0 "general_operand" ""))]
14888 ""
14889 "
14890 {
14891 if (TARGET_32BIT)
14892 emit_insn (gen_eh_set_lr_si (operands[0]));
14893 else
14894 emit_insn (gen_eh_set_lr_di (operands[0]));
14895 DONE;
14896 }")
14898 ; We can't expand this before we know where the link register is stored.
14899 (define_insn "eh_set_lr_<mode>"
14900 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14901 UNSPECV_EH_RR)
14902 (clobber (match_scratch:P 1 "=&b"))]
14903 ""
14904 "#")
14906 (define_split
14907 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14908 (clobber (match_scratch 1 ""))]
14909 "reload_completed"
14910 [(const_int 0)]
14911 "
14912 {
14913 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14914 DONE;
14915 }")
14917 (define_insn "prefetch"
14918 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14919 (match_operand:SI 1 "const_int_operand" "n")
14920 (match_operand:SI 2 "const_int_operand" "n"))]
14921 "TARGET_POWERPC"
14922 "*
14923 {
14924 if (GET_CODE (operands[0]) == REG)
14925 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14926 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14927 }"
14928 [(set_attr "type" "load")])
14929 \f
14931 (include "sync.md")
14932 (include "altivec.md")
14933 (include "spe.md")
14934 (include "dfp.md")
14935 (include "paired.md")