1 ;; Machine Descriptions for R8C/M16C/M32C
2 ;; Copyright (C) 2005, 2007, 2008
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; move, push, extend, etc.
24 ;; Be careful to never create an alternative that has memory as both
25 ;; src and dest, as that makes gcc think that mem-mem moves in general
26 ;; are supported. While the chip does support this, it only has two
27 ;; address registers and sometimes gcc requires more than that. One
28 ;; example is code like this: a = *b where both a and b are spilled to
31 ;; Match push/pop before mov.b for passing char as arg,
32 ;; e.g. stdlib/efgcvt.c.
33 (define_insn "movqi_op"
34 [(set (match_operand:QI 0 "m32c_nonimmediate_operand"
35 "=Rqi*Rmm, <, RqiSd*Rmm, SdSs, Rqi*Rmm, Sd")
36 (match_operand:QI 1 "m32c_any_operand"
37 "iRqi*Rmm, iRqiSd*Rmm, >, Rqi*Rmm, SdSs, i"))]
38 "m32c_mov_ok (operands, QImode)"
46 [(set_attr "flags" "sz,*,*,sz,sz,sz")]
49 (define_expand "movqi"
50 [(set (match_operand:QI 0 "nonimmediate_operand" "=RqiSd*Rmm")
51 (match_operand:QI 1 "general_operand" "iRqiSd*Rmm"))]
53 "if (m32c_prepare_move (operands, QImode)) DONE;"
57 (define_insn "movhi_op"
58 [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
59 "=Rhi*Rmm, Sd, SdSs, *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
60 (match_operand:HI 1 "m32c_any_operand"
61 "iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
62 "m32c_mov_ok (operands, HImode)"
73 [(set_attr "flags" "sz,sz,sz,n,n,n,n,n,n")]
76 (define_expand "movhi"
77 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhiSd*Rmm")
78 (match_operand:HI 1 "m32c_any_operand" "iRhiSd*Rmm"))]
80 "if (m32c_prepare_move (operands, HImode)) DONE;"
84 (define_insn "movpsi_op"
85 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand"
86 "=Raa, SdRmmRpi, Rcl, RpiSd*Rmm, <, <, Rcl, RpiRaa*Rmm")
87 (match_operand:PSI 1 "m32c_any_operand"
88 "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rpi*Rmm, Rcl, >, >"))]
89 "TARGET_A24 && m32c_mov_ok (operands, PSImode)"
99 [(set_attr "flags" "sz,sz,n,n,n,n,n,*")]
103 ;; The intention here is to combine the add with the move to create an
104 ;; indexed move. GCC doesn't always figure this out itself.
107 [(set (match_operand:HPSI 0 "register_operand" "")
108 (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
109 (match_operand:HPSI 2 "immediate_operand" "")))
110 (set (match_operand:QHSI 3 "nonimmediate_operand" "")
111 (mem:QHSI (match_operand:HPSI 4 "register_operand" "")))]
112 "REGNO (operands[0]) == REGNO (operands[1])
113 && REGNO (operands[0]) == REGNO (operands[4])
114 && (rtx_equal_p (operands[0], operands[3])
115 || (dead_or_set_p (peep2_next_insn (1), operands[4])
116 && ! reg_mentioned_p (operands[0], operands[3])))"
118 (mem:QHSI (plus:HPSI (match_dup 1)
123 [(set (match_operand:HPSI 0 "register_operand" "")
124 (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
125 (match_operand:HPSI 2 "immediate_operand" "")))
126 (set (mem:QHSI (match_operand:HPSI 4 "register_operand" ""))
127 (match_operand:QHSI 3 "m32c_any_operand" ""))]
128 "REGNO (operands[0]) == REGNO (operands[1])
129 && REGNO (operands[0]) == REGNO (operands[4])
130 && dead_or_set_p (peep2_next_insn (1), operands[4])
131 && ! reg_mentioned_p (operands[0], operands[3])"
132 [(set (mem:QHSI (plus:HPSI (match_dup 1)
137 ; Peephole to generate SImode mov instructions for storing an
138 ; immediate double data to a memory location.
140 [(set (match_operand:HI 0 "memory_operand" "")
141 (match_operand 1 "const_int_operand" ""))
142 (set (match_operand:HI 2 "memory_operand" "")
143 (match_operand 3 "const_int_operand" ""))]
144 "TARGET_A24 && m32c_immd_dbl_mov (operands, HImode)"
145 [(set (match_dup 4) (match_dup 5))]
149 ; Some PSI moves must be split.
151 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
152 (match_operand:PSI 1 "m32c_any_operand" ""))]
153 "reload_completed && m32c_split_psi_p (operands)"
158 "m32c_split_move (operands, PSImode, 3);"
161 (define_expand "movpsi"
162 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
163 (match_operand:PSI 1 "m32c_any_operand" ""))]
165 "if (m32c_prepare_move (operands, PSImode)) DONE;"
170 (define_expand "movsi"
171 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm")
172 (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm"))]
174 "if (m32c_split_move (operands, SImode, 0)) DONE;"
177 ; All SI moves are split if TARGET_A16
178 (define_insn_and_split "movsi_splittable"
179 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=Rsi<*Rmm,RsiSd*Rmm,Ss")
180 (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm,iRsi>*Rmm,Rsi*Rmm"))]
183 "TARGET_A16 && reload_completed"
185 "m32c_split_move (operands, SImode, 1); DONE;"
188 ; The movsi pattern doesn't always match because sometimes the modes
190 (define_insn "push_a01_l"
191 [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
192 (match_operand 0 "a_operand" "Raa"))]
195 [(set_attr "flags" "n")]
198 (define_insn "movsi_24"
199 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=Rsi*Rmm, Sd, RsiSd*Rmm, <")
200 (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
207 [(set_attr "flags" "sz,sz,*,n")]
210 (define_expand "movdi"
211 [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=RdiSd*Rmm")
212 (match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm"))]
214 "if (m32c_split_move (operands, DImode, 0)) DONE;"
217 (define_insn_and_split "movdi_splittable"
218 [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=Rdi<*Rmm,RdiSd*Rmm")
219 (match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
224 "m32c_split_move (operands, DImode, 1); DONE;"
230 (define_insn "pushqi"
231 [(set (mem:QI (pre_dec:PSI (reg:PSI SP_REGNO)))
232 (match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))]
235 [(set_attr "flags" "n")]
238 (define_expand "pushhi"
239 [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
240 (match_operand:HI 0 "" ""))]
243 gen_pushhi_16 (operands[0]);
245 gen_pushhi_24 (operands[0]);
249 (define_insn "pushhi_16"
250 [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
251 (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm,Rcr"))]
256 [(set_attr "flags" "n,n")]
259 (define_insn "pushhi_24"
260 [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
261 (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))]
264 [(set_attr "flags" "n")]
267 ;(define_insn "pushpi"
268 ; [(set (mem:PSI (pre_dec:PSI (reg:PSI SP_REGNO)))
269 ; (match_operand:PI 0 "mrai_operand" "iRaa,Rcr"))]
276 (define_insn "pushsi"
277 [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
278 (match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))]
281 [(set_attr "flags" "n")]
284 (define_expand "pophi"
285 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
286 (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
289 gen_pophi_16 (operands[0]);
291 gen_pophi_24 (operands[0]);
295 (define_insn "pophi_16"
296 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
297 (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
302 [(set_attr "flags" "n,n")]
305 (define_insn "pophi_24"
306 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm")
307 (mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]
310 [(set_attr "flags" "n")]
313 (define_insn "poppsi"
314 [(set (match_operand:PSI 0 "cr_operand" "=Rcl")
315 (mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]
318 [(set_attr "flags" "n")]
322 ;; Rhl used here as an HI-mode Rxl
323 (define_insn "extendqihi2"
324 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhlSd*Rmm")
325 (sign_extend:HI (match_operand:QI 1 "mra_operand" "0")))]
328 [(set_attr "flags" "sz")]
331 (define_insn "extendhisi2"
332 [(set (match_operand:SI 0 "register_operand" "=R03")
333 (sign_extend:SI (match_operand:HI 1 "r0123_operand" "0")))]
336 if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
337 else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
338 [(set_attr "flags" "x")]
341 (define_insn "extendhipsi2"
342 [(set (match_operand:PSI 0 "register_operand" "=R03")
343 (sign_extend:PSI (match_operand:HI 1 "register_operand" "0")))]
346 if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
347 else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
348 [(set_attr "flags" "x")]
351 (define_insn "extendpsisi2"
352 [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
353 (sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
355 "; expand psi %1 to si %0"
356 [(set_attr "flags" "n")]
359 (define_insn "zero_extendpsisi2"
360 [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
361 (zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
363 "; expand psi %1 to si %0"
364 [(set_attr "flags" "n")]
367 (define_insn "zero_extendhipsi2"
368 [(set (match_operand:PSI 0 "register_operand" "=Raa")
369 (truncate:PSI (zero_extend:SI (match_operand:HI 1 "register_operand" "R03"))))]
372 [(set_attr "flags" "sz")]
375 (define_insn "zero_extendhisi2"
376 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd")
377 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
380 [(set_attr "flags" "x")]
383 (define_insn "zero_extendqihi2"
384 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=?Rhl,RhiSd*Rmm")
385 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
390 [(set_attr "flags" "x,x")]
393 (define_insn "truncsipsi2_16"
394 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
395 (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
398 ; no-op trunc si %1 to psi %0
402 [(set_attr "flags" "n,*,n,n")]
405 (define_insn "trunchiqi2"
406 [(set (match_operand:QI 0 "m32c_nonimmediate_operand" "=RqiRmmSd")
407 (truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
409 "; no-op trunc hi %1 to qi %0"
410 [(set_attr "flags" "n")]
413 (define_insn "truncsipsi2_24"
414 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
415 (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
418 ; no-op trunc si %1 to psi %0
422 [(set_attr "flags" "n,sz,n,n")]
425 (define_expand "truncsipsi2"
426 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
427 (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
432 (define_expand "reload_inqi"
433 [(set (match_operand:QI 2 "" "=&Rqi")
434 (match_operand:QI 1 "" ""))
435 (set (match_operand:QI 0 "" "")
441 (define_expand "reload_outqi"
442 [(set (match_operand:QI 2 "" "=&Rqi")
443 (match_operand:QI 1 "" ""))
444 (set (match_operand:QI 0 "" "")
450 (define_expand "reload_inhi"
451 [(set (match_operand:HI 2 "" "=&Rhi")
452 (match_operand:HI 1 "" ""))
453 (set (match_operand:HI 0 "" "")
459 (define_expand "reload_outhi"
460 [(set (match_operand:HI 2 "" "=&Rhi")
461 (match_operand:HI 1 "" ""))
462 (set (match_operand:HI 0 "" "")