gcc/config/m32c/m32c.h

   1 /* Target Definitions for R8C/M16C/M32C
   2    Copyright (C) 2005, 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4    Contributed by Red Hat.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_M32C_H
  23 #define GCC_M32C_H
  24
  25 /* Controlling the Compilation Driver, `gcc'.  */
  26
  27 #undef  STARTFILE_SPEC
  28 #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
  29
  30 /* There are four CPU series we support, but they basically break down
  31    into two families - the R8C/M16C families, with 16-bit address
  32    registers and one set of opcodes, and the M32CM/M32C group, with
  33    24-bit address registers and a different set of opcodes.  The
  34    assembler doesn't care except for which opcode set is needed; the
  35    big difference is in the memory maps, which we cover in
  36    LIB_SPEC.  */
  37
  38 #undef  ASM_SPEC
  39 #define ASM_SPEC "\
  40 %{mcpu=r8c:--m16c} \
  41 %{mcpu=m16c:--m16c} \
  42 %{mcpu=m32cm:--m32c} \
  43 %{mcpu=m32c:--m32c} "
  44
  45 /* The default is R8C hardware.  We support a simulator, which has its
  46    own libgloss and link map, plus one default link map for each chip
  47    family.  Most of the logic here is making sure we do the right
  48    thing when no CPU is specified, which defaults to R8C.  */
  49 #undef  LIB_SPEC
  50 #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
  51 %{msim*:%{!T*: %{mcpu=m32cm:-Tsim24.ld}%{mcpu=m32c:-Tsim24.ld} \
  52         %{!mcpu=m32cm:%{!mcpu=m32c:-Tsim16.ld}}}} \
  53 %{!T*:%{!msim*: %{mcpu=m16c:-Tm16c.ld} \
  54                 %{mcpu=m32cm:-Tm32cm.ld} \
  55                 %{mcpu=m32c:-Tm32c.ld} \
  56                 %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:-Tr8c.ld}}}}} \
  57 "
  58
  59 /* Run-time Target Specification */
  60
  61 /* Nothing unusual here.  */
  62 #define TARGET_CPU_CPP_BUILTINS() \
  63   { \
  64     builtin_assert ("cpu=m32c"); \
  65     builtin_assert ("machine=m32c"); \
  66     builtin_define ("__m32c__=1"); \
  67     if (TARGET_R8C) \
  68       builtin_define ("__r8c_cpu__=1"); \
  69     if (TARGET_M16C) \
  70       builtin_define ("__m16c_cpu__=1"); \
  71     if (TARGET_M32CM) \
  72       builtin_define ("__m32cm_cpu__=1"); \
  73     if (TARGET_M32C) \
  74       builtin_define ("__m32c_cpu__=1"); \
  75   }
  76
  77 /* The pragma handlers need to know if we've started processing
  78    functions yet, as the memregs pragma should only be given at the
  79    beginning of the file.  This variable starts off TRUE and later
  80    becomes FALSE.  */
  81 extern int ok_to_change_target_memregs;
  82 extern int target_memregs;
  83
  84 /* TARGET_CPU is a multi-way option set in m32c.opt.  While we could
  85    use enums or defines for this, this and m32c.opt are the only
  86    places that know (or care) what values are being used.  */
  87 #define TARGET_R8C      (target_cpu == 'r')
  88 #define TARGET_M16C     (target_cpu == '6')
  89 #define TARGET_M32CM    (target_cpu == 'm')
  90 #define TARGET_M32C     (target_cpu == '3')
  91
  92 /* Address register sizes.  Warning: these are used all over the place
  93    to select between the two CPU families in general.  */
  94 #define TARGET_A16      (TARGET_R8C || TARGET_M16C)
  95 #define TARGET_A24      (TARGET_M32CM || TARGET_M32C)
  96
  97 #define TARGET_VERSION fprintf (stderr, " (m32c)");
  98
  99 #define OVERRIDE_OPTIONS m32c_override_options ()
 100
 101 /* Defining data structures for per-function information */
 102
 103 typedef struct machine_function GTY (())
 104 {
 105   /* How much we adjust the stack when returning from an exception
 106      handler.  */
 107   rtx eh_stack_adjust;
 108
 109   /* TRUE if the current function is an interrupt handler.  */
 110   int is_interrupt;
 111
 112   /* TRUE if the current function is a leaf function.  Currently, this
 113      only affects saving $a0 in interrupt functions.  */
 114   int is_leaf;
 115
 116   /* Bitmask that keeps track of which registers are used in an
 117      interrupt function, so we know which ones need to be saved and
 118      restored.  */
 119   int intr_pushm;
 120   /* Likewise, one element for each memreg that needs to be saved.  */
 121   char intr_pushmem[16];
 122
 123   /* TRUE if the current function can use a simple RTS to return, instead
 124      of the longer ENTER/EXIT pair.  */
 125   int use_rts;
 126 }
 127 machine_function;
 128
 129 #define INIT_EXPANDERS m32c_init_expanders ()
 130
 131 /* Storage Layout */
 132
 133 #define BITS_BIG_ENDIAN 0
 134 #define BYTES_BIG_ENDIAN 0
 135 #define WORDS_BIG_ENDIAN 0
 136
 137 /* We can do QI, HI, and SI operations pretty much equally well, but
 138    GCC expects us to have a "native" format, so we pick the one that
 139    matches "int".  Pointers are 16 bits for R8C/M16C (when TARGET_A16
 140    is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
 141    24-bit pointers are stored in 32-bit words.  */
 142 #define BITS_PER_UNIT 8
 143 #define UNITS_PER_WORD 2
 144 #define POINTER_SIZE (TARGET_A16 ? 16 : 32)
 145 #define POINTERS_EXTEND_UNSIGNED 1
 146 /* We have a problem with libgcc2.  It only defines two versions of
 147    each function, one for "int" and one for "long long".  Ie it assumes
 148    that "sizeof (int) == sizeof (long)".  For the M32C this is not true
 149    and we need a third set of functions.  We explicitly define
 150    LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
 151    to get the SI and DI versions from the libgcc2.c sources, and we
 152    provide our own set of HI functions in m32c-lib2.c, which is why this
 153    definition is surrounded by #ifndef..#endif.  */
 154 #ifndef LIBGCC2_UNITS_PER_WORD
 155 #define LIBGCC2_UNITS_PER_WORD 4
 156 #endif
 157
 158 /* These match the alignment enforced by the two types of stack operations.  */
 159 #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
 160 #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
 161
 162 /* We do this because we care more about space than about speed.  For
 163    the chips with 16-bit busses, we could set these to 16 if
 164    desired.  */
 165 #define FUNCTION_BOUNDARY 8
 166 #define BIGGEST_ALIGNMENT 8
 167
 168 /* Since we have a maximum structure alignment of 8 there
 169    is no need to enforce any alignment of bitfield types.  */
 170 #undef  PCC_BITFIELD_TYPE_MATTERS
 171 #define PCC_BITFIELD_TYPE_MATTERS 0
 172
 173 #define STRICT_ALIGNMENT 0
 174 #define SLOW_BYTE_ACCESS 1
 175
 176 /* Layout of Source Language Data Types */
 177
 178 #define INT_TYPE_SIZE 16
 179 #define SHORT_TYPE_SIZE 16
 180 #define LONG_TYPE_SIZE 32
 181 #define LONG_LONG_TYPE_SIZE 64
 182
 183 #define FLOAT_TYPE_SIZE 32
 184 #define DOUBLE_TYPE_SIZE 64
 185 #define LONG_DOUBLE_TYPE_SIZE 64
 186
 187 #define DEFAULT_SIGNED_CHAR 1
 188
 189 #undef PTRDIFF_TYPE
 190 #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
 191
 192 /* REGISTER USAGE */
 193
 194 /* Register Basics */
 195
 196 /* Register layout:
 197
 198         [r0h][r0l]  $r0  (16 bits, or two 8-bit halves)
 199         [--------]  $r2  (16 bits)
 200         [r1h][r1l]  $r1  (16 bits, or two 8-bit halves)
 201         [--------]  $r3  (16 bits)
 202    [---][--------]  $a0  (might be 24 bits)
 203    [---][--------]  $a1  (might be 24 bits)
 204    [---][--------]  $sb  (might be 24 bits)
 205    [---][--------]  $fb  (might be 24 bits)
 206    [---][--------]  $sp  (might be 24 bits)
 207    [-------------]  $pc  (20 or 24 bits)
 208              [---]  $flg (CPU flags)
 209    [---][--------]  $argp (virtual)
 210         [--------]  $mem0 (all 16 bits)
 211           . . .
 212         [--------]  $mem14
 213 */
 214
 215 #define FIRST_PSEUDO_REGISTER   20
 216
 217 /* Note that these two tables are modified based on which CPU family
 218    you select; see m32c_conditional_register_usage for details.  */
 219
 220 /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
 221 #define FIXED_REGISTERS     { 0, 0, 0, 0, \
 222                               0, 0, 1, 0, \
 223                               1, 1, 0, 1, \
 224                               0, 0, 0, 0, 0, 0, 0, 0 }
 225 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \
 226                               1, 1, 1, 0, \
 227                               1, 1, 1, 1, \
 228                               1, 1, 1, 1, 1, 1, 1, 1 }
 229
 230 #define CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage ();
 231
 232 /* The *_REGNO theme matches m32c.md and most register number
 233    arguments; the PC_REGNUM is the odd one out.  */
 234 #ifndef PC_REGNO
 235 #define PC_REGNO 9
 236 #endif
 237 #define PC_REGNUM PC_REGNO
 238
 239 /* Order of Allocation of Registers */
 240
 241 #define REG_ALLOC_ORDER { \
 242         0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
 243         12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */        \
 244         6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
 245
 246 /* How Values Fit in Registers */
 247
 248 #define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
 249 #define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
 250 #define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
 251 #define AVOID_CCMODE_COPIES
 252
 253 /* Register Classes */
 254
 255 /* Most registers are special purpose in some form or another, so this
 256    table is pretty big.  Class names are used for constraints also;
 257    for example the HL_REGS class (HL below) is "Rhl" in the md files.
 258    See m32c_reg_class_from_constraint for the mapping.  There's some
 259    duplication so that we can better isolate the reason for using
 260    constraints in the md files from the actual registers used; for
 261    example we may want to exclude a1a0 from SI_REGS in the future,
 262    without precluding their use as HImode registers.  */
 263
 264 /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
 265 /*       mmPAR */
 266 #define REG_CLASS_CONTENTS \
 267 { { 0x00000000 }, /* NO */\
 268   { 0x00000100 }, /* SP  - sp */\
 269   { 0x00000080 }, /* FB  - fb */\
 270   { 0x00000040 }, /* SB  - sb */\
 271   { 0x000001c0 }, /* CR  - sb fb sp */\
 272   { 0x00000001 }, /* R0  - r0 */\
 273   { 0x00000004 }, /* R1  - r1 */\
 274   { 0x00000002 }, /* R2  - r2 */\
 275   { 0x00000008 }, /* R3  - r3 */\
 276   { 0x00000003 }, /* R02 - r0r2 */\
 277   { 0x00000005 }, /* HL  - r0 r1 */\
 278   { 0x00000005 }, /* QI  - r0 r1 */\
 279   { 0x0000000a }, /* R23 - r2 r3 */\
 280   { 0x0000000f }, /* R03 - r0r2 r1r3 */\
 281   { 0x0000000f }, /* DI  - r0r2r1r3 + mems */\
 282   { 0x00000010 }, /* A0  - a0 */\
 283   { 0x00000020 }, /* A1  - a1 */\
 284   { 0x00000030 }, /* A   - a0 a1 */\
 285   { 0x000000f0 }, /* AD  - a0 a1 sb fp */\
 286   { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\
 287   { 0x0000000f }, /* SI  - r0r2 r1r3 a0a1 */\
 288   { 0x0000003f }, /* HI  - r0 r1 r2 r3 a0 a1 */\
 289   { 0x00000033 }, /* R02A  - r0r2 a0 a1 */ \
 290   { 0x0000003f }, /* RA  - r0..r3 a0 a1 */\
 291   { 0x0000007f }, /* GENERAL */\
 292   { 0x00000400 }, /* FLG */\
 293   { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\
 294   { 0x000ff000 }, /* MEM */\
 295   { 0x000ff003 }, /* R02_A_MEM */\
 296   { 0x000ff005 }, /* A_HL_MEM */\
 297   { 0x000ff00c }, /* R1_R3_A_MEM */\
 298   { 0x000ff00f }, /* R03_MEM */\
 299   { 0x000ff03f }, /* A_HI_MEM */\
 300   { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
 301   { 0x000ff1ff }, /* ALL */\
 302 }
 303
 304 enum reg_class
 305 {
 306   NO_REGS,
 307   SP_REGS,
 308   FB_REGS,
 309   SB_REGS,
 310   CR_REGS,
 311   R0_REGS,
 312   R1_REGS,
 313   R2_REGS,
 314   R3_REGS,
 315   R02_REGS,
 316   HL_REGS,
 317   QI_REGS,
 318   R23_REGS,
 319   R03_REGS,
 320   DI_REGS,
 321   A0_REGS,
 322   A1_REGS,
 323   A_REGS,
 324   AD_REGS,
 325   PS_REGS,
 326   SI_REGS,
 327   HI_REGS,
 328   R02A_REGS,
 329   RA_REGS,
 330   GENERAL_REGS,
 331   FLG_REGS,
 332   HC_REGS,
 333   MEM_REGS,
 334   R02_A_MEM_REGS,
 335   A_HL_MEM_REGS,
 336   R1_R3_A_MEM_REGS,
 337   R03_MEM_REGS,
 338   A_HI_MEM_REGS,
 339   A_AD_CR_MEM_SI_REGS,
 340   ALL_REGS,
 341   LIM_REG_CLASSES
 342 };
 343
 344 #define N_REG_CLASSES LIM_REG_CLASSES
 345
 346 #define REG_CLASS_NAMES {\
 347 "NO_REGS", \
 348 "SP_REGS", \
 349 "FB_REGS", \
 350 "SB_REGS", \
 351 "CR_REGS", \
 352 "R0_REGS", \
 353 "R1_REGS", \
 354 "R2_REGS", \
 355 "R3_REGS", \
 356 "R02_REGS", \
 357 "HL_REGS", \
 358 "QI_REGS", \
 359 "R23_REGS", \
 360 "R03_REGS", \
 361 "DI_REGS", \
 362 "A0_REGS", \
 363 "A1_REGS", \
 364 "A_REGS", \
 365 "AD_REGS", \
 366 "PS_REGS", \
 367 "SI_REGS", \
 368 "HI_REGS", \
 369 "R02A_REGS", \
 370 "RA_REGS", \
 371 "GENERAL_REGS", \
 372 "FLG_REGS", \
 373 "HC_REGS", \
 374 "MEM_REGS", \
 375 "R02_A_MEM_REGS", \
 376 "A_HL_MEM_REGS", \
 377 "R1_R3_A_MEM_REGS", \
 378 "R03_MEM_REGS", \
 379 "A_HI_MEM_REGS", \
 380 "A_AD_CR_MEM_SI_REGS", \
 381 "ALL_REGS", \
 382 }
 383
 384 #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
 385
 386 /* We support simple displacements off address registers, nothing else.  */
 387 #define BASE_REG_CLASS A_REGS
 388 #define INDEX_REG_CLASS NO_REGS
 389
 390 /* We primarily use the new "long" constraint names, with the initial
 391    letter classifying the constraint type and following letters
 392    specifying which.  The types are:
 393
 394    I - integer values
 395    R - register classes
 396    S - memory references (M was used)
 397    A - addresses (currently unused)
 398 */
 399
 400 #define CONSTRAINT_LEN(CHAR,STR) \
 401         ((CHAR) == 'I' ? 3 \
 402          : (CHAR) == 'R' ? 3 \
 403          : (CHAR) == 'S' ? 2 \
 404          : (CHAR) == 'A' ? 2 \
 405          : DEFAULT_CONSTRAINT_LEN(CHAR,STR))
 406 #define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
 407         m32c_reg_class_from_constraint (CHAR, STR)
 408
 409 #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
 410 #define REGNO_OK_FOR_INDEX_P(NUM) 0
 411
 412 #define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
 413 #define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
 414 #define LIMIT_RELOAD_CLASS(MODE,CLASS) m32c_limit_reload_class (MODE, CLASS)
 415
 416 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) m32c_secondary_reload_class (CLASS, MODE, X)
 417
 418 #define SMALL_REGISTER_CLASSES 1
 419
 420 #define CLASS_LIKELY_SPILLED_P(C) m32c_class_likely_spilled_p (C)
 421
 422 #define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
 423
 424 #define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
 425
 426 #define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
 427         m32c_const_ok_for_constraint_p (VALUE, C, STR)
 428 #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
 429 #define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
 430         m32c_extra_constraint_p (VALUE, C, STR)
 431 #define EXTRA_MEMORY_CONSTRAINT(C,STR) \
 432         m32c_extra_memory_constraint (C, STR)
 433 #define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
 434         m32c_extra_address_constraint (C, STR)
 435
 436 /* STACK AND CALLING */
 437
 438 /* Frame Layout */
 439
 440 /* Standard push/pop stack, no surprises here.  */
 441
 442 #define STACK_GROWS_DOWNWARD 1
 443 #define STACK_PUSH_CODE PRE_DEC
 444 #define FRAME_GROWS_DOWNWARD 1
 445
 446 #define STARTING_FRAME_OFFSET 0
 447 #define FIRST_PARM_OFFSET(F) 0
 448
 449 #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
 450
 451 #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
 452 #define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
 453
 454 /* Exception Handling Support */
 455
 456 #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
 457 #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
 458
 459 /* Registers That Address the Stack Frame */
 460
 461 #ifndef FP_REGNO
 462 #define FP_REGNO 7
 463 #endif
 464 #ifndef SP_REGNO
 465 #define SP_REGNO 8
 466 #endif
 467 #define AP_REGNO 11
 468
 469 #define STACK_POINTER_REGNUM    SP_REGNO
 470 #define FRAME_POINTER_REGNUM    FP_REGNO
 471 #define ARG_POINTER_REGNUM      AP_REGNO
 472
 473 /* The static chain must be pointer-capable.  */
 474 #define STATIC_CHAIN_REGNUM A0_REGNO
 475
 476 #define DWARF_FRAME_REGISTERS 20
 477 #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
 478 #define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
 479
 480 #undef ASM_PREFERRED_EH_DATA_FORMAT
 481 /* This is the same as the default in practice, except that by making
 482    it explicit we tell binutils what size pointers to use.  */
 483 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 484   (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4)
 485
 486 /* Eliminating Frame Pointer and Arg Pointer */
 487
 488 /* If the frame pointer isn't used, we detect it manually.  But the
 489    stack pointer doesn't have as flexible addressing as the frame
 490    pointer, so we always assume we have it.  */
 491 #define FRAME_POINTER_REQUIRED 1
 492
 493 #define ELIMINABLE_REGS \
 494   {{AP_REGNO, SP_REGNO}, \
 495    {AP_REGNO, FB_REGNO}, \
 496    {FB_REGNO, SP_REGNO}}
 497
 498 #define CAN_ELIMINATE(FROM,TO) 1
 499 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
 500         (VAR) = m32c_initial_elimination_offset(FROM,TO)
 501
 502 /* Passing Function Arguments on the Stack */
 503
 504 #define PUSH_ARGS 1
 505 #define PUSH_ROUNDING(N) m32c_push_rounding (N)
 506 #define RETURN_POPS_ARGS(D,T,S) 0
 507 #define CALL_POPS_ARGS(C) 0
 508
 509 /* Passing Arguments in Registers */
 510
 511 #define FUNCTION_ARG(CA,MODE,TYPE,NAMED) \
 512         m32c_function_arg (&(CA),MODE,TYPE,NAMED)
 513
 514 typedef struct m32c_cumulative_args
 515 {
 516   /* For address of return value buffer (structures are returned by
 517      passing the address of a buffer as an invisible first argument.
 518      This identifies it).  If set, the current parameter will be put
 519      on the stack, regardless of type.  */
 520   int force_mem;
 521   /* First parm is 1, parm 0 is hidden pointer for returning
 522      aggregates.  */
 523   int parm_num;
 524 } m32c_cumulative_args;
 525
 526 #define CUMULATIVE_ARGS m32c_cumulative_args
 527 #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
 528         m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
 529 #define FUNCTION_ARG_ADVANCE(CA,MODE,TYPE,NAMED) \
 530         m32c_function_arg_advance (&(CA),MODE,TYPE,NAMED)
 531 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) (TARGET_A16 ? 8 : 16)
 532 #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
 533
 534 /* How Scalar Function Values Are Returned */
 535
 536 #define FUNCTION_VALUE(VT,F) m32c_function_value (VT, F)
 537 #define LIBCALL_VALUE(MODE) m32c_libcall_value (MODE)
 538
 539 #define FUNCTION_VALUE_REGNO_P(r) ((r) == R0_REGNO || (r) == MEM0_REGNO)
 540
 541 /* How Large Values Are Returned */
 542
 543 #define DEFAULT_PCC_STRUCT_RETURN 1
 544
 545 /* Function Entry and Exit */
 546
 547 #define EXIT_IGNORE_STACK 0
 548 #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
 549 #define EH_USES(REGNO) 0        /* FIXME */
 550
 551 /* Generating Code for Profiling */
 552
 553 #define FUNCTION_PROFILER(FILE,LABELNO)
 554
 555 /* Implementing the Varargs Macros */
 556
 557 /* Trampolines for Nested Functions */
 558
 559 #define TRAMPOLINE_SIZE m32c_trampoline_size ()
 560 #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
 561 #define INITIALIZE_TRAMPOLINE(a,fn,sc) m32c_initialize_trampoline (a, fn, sc)
 562
 563 /* Addressing Modes */
 564
 565 #define HAVE_PRE_DECREMENT 1
 566 #define HAVE_POST_INCREMENT 1
 567 #define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
 568 #define MAX_REGS_PER_ADDRESS 1
 569
 570 /* This is passed to the macros below, so that they can be implemented
 571    in m32c.c.  */
 572 #ifdef REG_OK_STRICT
 573 #define REG_OK_STRICT_V 1
 574 #else
 575 #define REG_OK_STRICT_V 0
 576 #endif
 577
 578 #define GO_IF_LEGITIMATE_ADDRESS(MODE,X,LABEL) \
 579         if (m32c_legitimate_address_p (MODE, X, REG_OK_STRICT_V)) \
 580           goto LABEL;
 581
 582 #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
 583 #define REG_OK_FOR_INDEX_P(X) 0
 584
 585 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
 586
 587 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
 588         if (m32c_legitimize_address(&(X),OLDX,MODE)) \
 589           goto WIN;
 590
 591 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
 592         if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
 593           goto WIN;
 594
 595 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
 596
 597 #define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
 598
 599 /* Condition Code Status */
 600
 601 #define REVERSIBLE_CC_MODE(MODE) 1
 602
 603 /* Describing Relative Costs of Operations */
 604
 605 #define REGISTER_MOVE_COST(MODE,FROM,TO) \
 606         m32c_register_move_cost (MODE, FROM, TO)
 607 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
 608         m32c_memory_move_cost (MODE, CLASS, IN)
 609
 610 /* Dividing the Output into Sections (Texts, Data, ...) */
 611
 612 #define TEXT_SECTION_ASM_OP ".text"
 613 #define DATA_SECTION_ASM_OP ".data"
 614 #define BSS_SECTION_ASM_OP ".bss"
 615
 616 #define CTOR_LIST_BEGIN
 617 #define CTOR_LIST_END
 618 #define DTOR_LIST_BEGIN
 619 #define DTOR_LIST_END
 620 #define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 621 #define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 622 #define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 623 #define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 624
 625 /* The Overall Framework of an Assembler File */
 626
 627 #define ASM_COMMENT_START ";"
 628 #define ASM_APP_ON ""
 629 #define ASM_APP_OFF ""
 630
 631 /* Output and Generation of Labels */
 632
 633 #define GLOBAL_ASM_OP "\t.global\t"
 634
 635 /* Output of Assembler Instructions */
 636
 637 #define REGISTER_NAMES {        \
 638   "r0", "r2", "r1", "r3", \
 639   "a0", "a1", "sb", "fb", "sp", \
 640   "pc", "flg", "argp", \
 641   "mem0",  "mem2",  "mem4",  "mem6",  "mem8",  "mem10",  "mem12",  "mem14", \
 642 }
 643
 644 #define ADDITIONAL_REGISTER_NAMES { \
 645   {"r0l", 0}, \
 646   {"r1l", 2}, \
 647   {"r0r2", 0}, \
 648   {"r1r3", 2}, \
 649   {"a0a1", 4}, \
 650   {"r0r2r1r3", 0} }
 651
 652 #define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
 653 #define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
 654 #define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
 655
 656 #undef USER_LABEL_PREFIX
 657 #define USER_LABEL_PREFIX "_"
 658
 659 #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
 660 #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
 661
 662 /* Output of Dispatch Tables */
 663
 664 #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
 665         fprintf (S, "\t.word L%d\n", V)
 666
 667 /* Assembler Commands for Exception Regions */
 668
 669 #define DWARF_CIE_DATA_ALIGNMENT -1
 670
 671 /* Assembler Commands for Alignment */
 672
 673 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 674         fprintf (STREAM, "\t.p2align\t%d\n", POWER);
 675
 676 /* Controlling Debugging Information Format */
 677
 678 #define DWARF2_ADDR_SIZE        4
 679
 680 /* Miscellaneous Parameters */
 681
 682 #define HAS_LONG_COND_BRANCH false
 683 #define HAS_LONG_UNCOND_BRANCH true
 684 #define CASE_VECTOR_MODE SImode
 685 #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
 686
 687 #define MOVE_MAX 4
 688 #define TRULY_NOOP_TRUNCATION(op,ip) 1
 689
 690 #define STORE_FLAG_VALUE 1
 691
 692 /* 16- or 24-bit pointers */
 693 #define Pmode (TARGET_A16 ? HImode : PSImode)
 694 #define FUNCTION_MODE QImode
 695
 696 #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
 697
 698 #endif