gcc/config/arm/cortex-a15.md

   1 ;; ARM Cortex-A15 pipeline description
   2 ;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
   3 ;;
   4 ;; Written by Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
   5
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful, but
  14 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 ;; General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 (define_automaton "cortex_a15")
  23
  24 ;; The Cortex-A15 core is modelled as a triple issue pipeline that has
  25 ;; the following dispatch units.
  26 ;; 1. Two pipelines for simple integer operations: SX1, SX2
  27 ;; 2. Individual units for Neon and FP operations as in cortex-a15-neon.md
  28 ;; 3. One pipeline for branch operations: BX
  29 ;; 4. One pipeline for integer multiply and divide operations: MX
  30 ;; 5. Two pipelines for load and store operations: LS1, LS2
  31 ;;
  32 ;; We can issue into three pipelines per-cycle.
  33 ;;
  34 ;; We assume that where we have unit pairs xx1 is always filled before xx2.
  35
  36 ;; The three issue units
  37 (define_cpu_unit "ca15_i0, ca15_i1, ca15_i2" "cortex_a15")
  38
  39 (define_reservation "ca15_issue1" "(ca15_i0|ca15_i1|ca15_i2)")
  40 (define_reservation "ca15_issue2" "((ca15_i0+ca15_i1)|(ca15_i1+ca15_i2))")
  41 (define_reservation "ca15_issue3" "(ca15_i0+ca15_i1+ca15_i2)")
  42 (final_presence_set "ca15_i1" "ca15_i0")
  43 (final_presence_set "ca15_i2" "ca15_i1")
  44
  45 ;; The main dispatch units
  46 (define_cpu_unit "ca15_sx1, ca15_sx2" "cortex_a15")
  47 (define_cpu_unit "ca15_ls1, ca15_ls2" "cortex_a15")
  48 (define_cpu_unit "ca15_bx, ca15_mx" "cortex_a15")
  49
  50 (define_reservation "ca15_ls" "(ca15_ls1|ca15_ls2)")
  51
  52 ;; The extended load-store pipeline
  53 (define_cpu_unit "ca15_ldr, ca15_str" "cortex_a15")
  54
  55 ;; The extended ALU pipeline
  56 (define_cpu_unit "ca15_sx1_alu, ca15_sx1_shf, ca15_sx1_sat" "cortex_a15")
  57 (define_cpu_unit "ca15_sx2_alu, ca15_sx2_shf, ca15_sx2_sat" "cortex_a15")
  58
  59 ;; Simple Execution Unit:
  60 ;;
  61 ;; Simple ALU without shift
  62 (define_insn_reservation "cortex_a15_alu" 2
  63   (and (eq_attr "tune" "cortexa15")
  64        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
  65                         alu_reg,alus_reg,logic_reg,logics_reg,\
  66                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
  67                         adr,bfm,clz,rbit,rev,\
  68                         shift_imm,shift_reg,\
  69                         mov_imm,mov_reg,\
  70                         mvn_imm,mvn_reg,\
  71                         mrs,multiple,no_insn"))
  72   "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
  73
  74 ;; ALU ops with immediate shift
  75 (define_insn_reservation "cortex_a15_alu_shift" 3
  76   (and (eq_attr "tune" "cortexa15")
  77        (eq_attr "type" "extend,\
  78                         alu_shift_imm,alus_shift_imm,\
  79                         logic_shift_imm,logics_shift_imm,\
  80                         mov_shift,mvn_shift"))
  81   "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
  82                |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
  83
  84 ;; ALU ops with register controlled shift
  85 (define_insn_reservation "cortex_a15_alu_shift_reg" 3
  86   (and (eq_attr "tune" "cortexa15")
  87        (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
  88                         logic_shift_reg,logics_shift_reg,\
  89                         mov_shift_reg,mvn_shift_reg"))
  90   "(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
  91    |(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
  92    |(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)")
  93
  94 ;; Multiply Execution Unit:
  95 ;;
  96 ;; 32-bit multiplies
  97 (define_insn_reservation "cortex_a15_mult32" 3
  98   (and (eq_attr "tune" "cortexa15")
  99        (eq_attr "mul32" "yes"))
 100   "ca15_issue1,ca15_mx")
 101
 102 ;; 64-bit multiplies
 103 (define_insn_reservation "cortex_a15_mult64" 4
 104   (and (eq_attr "tune" "cortexa15")
 105        (eq_attr "mul64" "yes"))
 106   "ca15_issue1,ca15_mx*2")
 107
 108 ;; Integer divide
 109 (define_insn_reservation "cortex_a15_udiv" 9
 110   (and (eq_attr "tune" "cortexa15")
 111        (eq_attr "type" "udiv"))
 112   "ca15_issue1,ca15_mx")
 113
 114 (define_insn_reservation "cortex_a15_sdiv" 10
 115   (and (eq_attr "tune" "cortexa15")
 116        (eq_attr "type" "sdiv"))
 117   "ca15_issue1,ca15_mx")
 118
 119 ;; Block all issue pipes for a cycle
 120 (define_insn_reservation "cortex_a15_block" 1
 121   (and (eq_attr "tune" "cortexa15")
 122        (eq_attr "type" "block"))
 123   "ca15_issue3")
 124
 125 ;; Branch execution Unit
 126 ;;
 127 ;; Branches take one issue slot.
 128 ;; No latency as there is no result
 129 (define_insn_reservation "cortex_a15_branch" 0
 130   (and (eq_attr "tune" "cortexa15")
 131        (eq_attr "type" "branch"))
 132   "ca15_issue1,ca15_bx")
 133
 134 ;; Load-store execution Unit
 135 ;;
 136 ;; Loads of up to two words.
 137 (define_insn_reservation "cortex_a15_load1" 4
 138   (and (eq_attr "tune" "cortexa15")
 139        (eq_attr "type" "load_byte,load1,load2"))
 140   "ca15_issue1,ca15_ls,ca15_ldr,nothing")
 141
 142 ;; Loads of three or four words.
 143 (define_insn_reservation "cortex_a15_load3" 5
 144   (and (eq_attr "tune" "cortexa15")
 145        (eq_attr "type" "load3,load4"))
 146   "ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr,nothing")
 147
 148 ;; Stores of up to two words.
 149 (define_insn_reservation "cortex_a15_store1" 0
 150   (and (eq_attr "tune" "cortexa15")
 151        (eq_attr "type" "store1,store2"))
 152   "ca15_issue1,ca15_ls,ca15_str")
 153
 154 ;; Stores of three or four words.
 155 (define_insn_reservation "cortex_a15_store3" 0
 156   (and (eq_attr "tune" "cortexa15")
 157        (eq_attr "type" "store3,store4"))
 158   "ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str")
 159
 160 ;; We include Neon.md here to ensure that the branch can block the Neon units.
 161 (include "../arm/cortex-a15-neon.md")
 162
 163 ;; We lie with calls.  They take up all issue slots, and form a block in the
 164 ;; pipeline.  The result however is available the next cycle.
 165 (define_insn_reservation "cortex_a15_call" 1
 166   (and (eq_attr "tune" "cortexa15")
 167        (eq_attr "type" "call"))
 168   "ca15_issue3,\
 169    ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx_ij+ca15_cx_ik+ca15_ls1+ca15_ls2+\
 170    ca15_cx_imac1+ca15_cx_ialu1+ca15_cx_ialu2+ca15_cx_ishf+\
 171    ca15_cx_acc+ca15_cx_fmul1+ca15_cx_fmul2+ca15_cx_fmul3+ca15_cx_fmul4+\
 172    ca15_cx_falu1+ca15_cx_falu2+ca15_cx_falu3+ca15_cx_falu4+ca15_cx_vfp_i,\
 173    ca15_sx1_alu+ca15_sx1_shf+ca15_sx1_sat+ca15_sx2_alu+\
 174    ca15_sx2_shf+ca15_sx2_sat+ca15_ldr+ca15_str")
 175
 176 ;; Simple execution unit bypasses
 177 (define_bypass 1 "cortex_a15_alu"
 178                "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
 179 (define_bypass 2 "cortex_a15_alu_shift"
 180                "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
 181 (define_bypass 2 "cortex_a15_alu_shift_reg"
 182                "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
 183 (define_bypass 1 "cortex_a15_alu" "cortex_a15_load1,cortex_a15_load3")
 184 (define_bypass 2 "cortex_a15_alu_shift" "cortex_a15_load1,cortex_a15_load3")
 185 (define_bypass 2 "cortex_a15_alu_shift_reg"
 186                "cortex_a15_load1,cortex_a15_load3")