old-autovect-branch/libjava/sysdep/s390/locks.h

   1 // locks.h - Thread synchronization primitives. S/390 implementation.
   2
   3 /* Copyright (C) 2002  Free Software Foundation
   4
   5    This file is part of libgcj.
   6
   7 This software is copyrighted work licensed under the terms of the
   8 Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
   9 details.  */
  10
  11 #ifndef __SYSDEP_LOCKS_H__
  12 #define __SYSDEP_LOCKS_H__
  13
  14 typedef size_t obj_addr_t;      /* Integer type big enough for object   */
  15                                 /* address.                             */
  16
  17 // Atomically replace *addr by new_val if it was initially equal to old.
  18 // Return true if the comparison succeeded.
  19 // Assumed to have acquire semantics, i.e. later memory operations
  20 // cannot execute before the compare_and_swap finishes.
  21 inline static bool
  22 compare_and_swap(volatile obj_addr_t *addr,
  23                  obj_addr_t old, obj_addr_t new_val)
  24 {
  25   int result;
  26
  27   __asm__ __volatile__ (
  28 #ifndef __s390x__
  29     "       cs  %1,%2,0(%3)\n"
  30 #else
  31     "       csg %1,%2,0(%3)\n"
  32 #endif
  33     "       ipm %0\n"
  34     "       srl %0,28\n"
  35     : "=&d" (result), "+d" (old)
  36     : "d" (new_val), "a" (addr)
  37     : "cc", "memory");
  38
  39   return result == 0;
  40 }
  41
  42 // Set *addr to new_val with release semantics, i.e. making sure
  43 // that prior loads and stores complete before this
  44 // assignment.
  45 inline static void
  46 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
  47 {
  48   __asm__ __volatile__("bcr 15,0" : : : "memory");
  49   *(addr) = new_val;
  50 }
  51
  52 // Compare_and_swap with release semantics instead of acquire semantics.
  53 // On many architecture, the operation makes both guarantees, so the
  54 // implementation can be the same.
  55 inline static bool
  56 compare_and_swap_release(volatile obj_addr_t *addr,
  57                          obj_addr_t old, obj_addr_t new_val)
  58 {
  59   return compare_and_swap(addr, old, new_val);
  60 }
  61
  62 // Ensure that subsequent instructions do not execute on stale
  63 // data that was loaded from memory before the barrier.
  64 inline static void
  65 read_barrier()
  66 {
  67   __asm__ __volatile__("bcr 15,0" : : : "memory");
  68 }
  69
  70 // Ensure that prior stores to memory are completed with respect to other
  71 // processors.
  72 inline static void
  73 write_barrier()
  74 {
  75   __asm__ __volatile__("bcr 15,0" : : : "memory");
  76 }
  77 #endif