1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; O -- Multiple letter constraint followed by 1 parameter.
51 ;; s: Signed extended immediate value (-2G .. 2G-1).
52 ;; p: Positive extended immediate value (0 .. 4G-1).
53 ;; n: Negative extended immediate value (-4G .. -1).
54 ;; These constraints do not accept any operand if the machine does
55 ;; not provide the extended-immediate facility.
56 ;; P -- Any integer constant that can be loaded without literal pool.
57 ;; Q -- Memory reference without index register and with short displacement.
58 ;; R -- Memory reference with index register and short displacement.
59 ;; S -- Memory reference without index register but with long displacement.
60 ;; T -- Memory reference with index register and long displacement.
61 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
62 ;; Offsettable memory reference of type specified by second letter.
63 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
64 ;; Memory reference of the type specified by second letter that
65 ;; does *not* refer to a literal pool entry.
66 ;; U -- Pointer with short displacement.
67 ;; W -- Pointer with long displacement.
68 ;; Y -- Shift count operand.
70 ;; Special formats used for outputting 390 instructions.
72 ;; %C: print opcode suffix for branch condition.
73 ;; %D: print opcode suffix for inverse branch condition.
74 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
75 ;; %G: print the size of the operand in bytes.
76 ;; %O: print only the displacement of a memory reference.
77 ;; %R: print only the base register of a memory reference.
78 ;; %S: print S-type memory reference (base+displacement).
79 ;; %N: print the second word of a DImode operand.
80 ;; %M: print the second word of a TImode operand.
81 ;; %Y: print shift count operand.
83 ;; %b: print integer X as if it's an unsigned byte.
84 ;; %x: print integer X as if it's an unsigned halfword.
85 ;; %h: print integer X as if it's a signed halfword.
86 ;; %i: print the first nonzero HImode part of X.
87 ;; %j: print the first HImode part unequal to -1 of X.
88 ;; %k: print the first nonzero SImode part of X.
89 ;; %m: print the first SImode part unequal to -1 of X.
90 ;; %o: print integer X as if it's an unsigned 32bit word.
92 ;; We have a special constraint for pattern matching.
94 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
107 ; GOT/PLT and lt-relative accesses
108 (UNSPEC_LTREL_OFFSET 100)
109 (UNSPEC_LTREL_BASE 101)
117 (UNSPEC_RELOAD_BASE 210)
118 (UNSPEC_MAIN_BASE 211)
123 ; TLS relocation specifiers
128 (UNSPEC_GOTNTPOFF 504)
129 (UNSPEC_INDNTPOFF 505)
132 (UNSPEC_TLSLDM_NTPOFF 511)
133 (UNSPEC_TLS_LOAD 512)
139 ; Stack Smashing Protector
145 ;; UNSPEC_VOLATILE usage
153 (UNSPECV_TPF_PROLOGUE 20)
154 (UNSPECV_TPF_EPILOGUE 21)
158 (UNSPECV_POOL_SECTION 201)
159 (UNSPECV_POOL_ALIGN 202)
160 (UNSPECV_POOL_ENTRY 203)
161 (UNSPECV_MAIN_POOL 300)
177 ; Sibling call register.
179 ; Literal pool base register.
181 ; Return address register.
183 ; Condition code register.
185 ; Thread local storage pointer register.
190 ;; Instruction operand type as used in the Principles of Operation.
191 ;; Used to determine defaults for length and other attribute values.
193 (define_attr "op_type"
194 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
197 ;; Instruction type attribute used for scheduling.
199 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
200 cs,vs,store,sem,idiv,
201 imulhi,imulsi,imuldi,
202 branch,jsr,fsimpdf,fsimpsf,
203 floaddf,floadsf,fstoredf,fstoresf,
204 fmuldf,fmulsf,fdivdf,fdivsf,
205 ftoi,itof,fsqrtdf,fsqrtsf,
207 (cond [(eq_attr "op_type" "NN") (const_string "other")
208 (eq_attr "op_type" "SS") (const_string "cs")]
209 (const_string "integer")))
211 ;; Another attribute used for scheduling purposes:
212 ;; agen: Instruction uses the address generation unit
213 ;; reg: Instruction does not use the agen unit
215 (define_attr "atype" "agen,reg"
216 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
218 (const_string "agen")))
222 (define_attr "length" ""
223 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
224 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
228 ;; Processor type. This attribute must exactly match the processor_type
229 ;; enumeration in s390.h. The current machine description does not
230 ;; distinguish between g5 and g6, but there are differences between the two
231 ;; CPUs could in theory be modeled.
233 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
234 (const (symbol_ref "s390_tune")))
236 ;; Pipeline description for z900. For lack of anything better,
237 ;; this description is also used for the g5 and g6.
240 ;; Pipeline description for z990.
244 (include "predicates.md")
251 ;; This mode macro allows DF and SF patterns to be generated from the
253 (define_mode_macro FPR [DF SF])
255 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
256 ;; from the same template.
257 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
259 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
260 ;; from the same template.
261 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
262 (define_mode_macro DSI [DI SI])
264 ;; This mode macro allows :P to be used for patterns that operate on
265 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
266 (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
267 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
269 ;; This mode macro allows the QI and HI patterns to be defined from
270 ;; the same template.
271 (define_mode_macro HQI [HI QI])
273 ;; This mode macro allows the integer patterns to be defined from the
275 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
277 ;; This macro allows to unify all 'bCOND' expander patterns.
278 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
279 ordered uneq unlt ungt unle unge ltgt])
281 ;; This macro allows to unify all 'sCOND' patterns.
282 (define_code_macro SCOND [ltu gtu leu geu])
284 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
285 ;; the same template.
286 (define_code_macro SHIFT [ashift lshiftrt])
288 ;; These macros allow to combine most atomic operations.
289 (define_code_macro ATOMIC [and ior xor plus minus mult])
290 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
291 (plus "add") (minus "sub") (mult "nand")])
294 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
295 ;; and "ltebr" in SFmode.
296 (define_mode_attr de [(DF "d") (SF "e")])
298 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
299 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
300 (define_mode_attr dee [(DF "d") (SF "ee")])
302 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
303 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
304 ;; version only operates on one register.
305 (define_mode_attr d0 [(DI "d") (SI "0")])
307 ;; In combination with d0 this allows to combine instructions of which the 31bit
308 ;; version only operates on one register. The DImode version needs an additional
309 ;; register for the assembler output.
310 (define_mode_attr 1 [(DI "%1,") (SI "")])
312 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
313 ;; 'ashift' and "srdl" in 'lshiftrt'.
314 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
316 ;; In SHIFT templates, this attribute holds the correct standard name for the
317 ;; pattern itself and the corresponding function calls.
318 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
320 ;; This attribute handles differences in the instruction 'type' and will result
321 ;; in "RRE" for DImode and "RR" for SImode.
322 (define_mode_attr E [(DI "E") (SI "")])
324 ;; This attribute handles differences in the instruction 'type' and will result
325 ;; in "RSE" for TImode and "RS" for DImode.
326 (define_mode_attr TE [(TI "E") (DI "")])
328 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
329 ;; and "lcr" in SImode.
330 (define_mode_attr g [(DI "g") (SI "")])
332 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
333 ;; and "cds" in DImode.
334 (define_mode_attr tg [(TI "g") (DI "")])
336 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
337 ;; and "cfdbr" in SImode.
338 (define_mode_attr gf [(DI "g") (SI "f")])
340 ;; ICM mask required to load MODE value into the lowest subreg
341 ;; of a SImode register.
342 (define_mode_attr icm_lo [(HI "3") (QI "1")])
344 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
345 ;; HImode and "llgc" in QImode.
346 (define_mode_attr hc [(HI "h") (QI "c")])
348 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
350 (define_mode_attr DBL [(DI "TI") (SI "DI")])
352 ;; Maximum unsigned integer that fits in MODE.
353 (define_mode_attr max_uint [(HI "65535") (QI "255")])
357 ;;- Compare instructions.
360 (define_expand "cmp<mode>"
361 [(set (reg:CC CC_REGNUM)
362 (compare:CC (match_operand:GPR 0 "register_operand" "")
363 (match_operand:GPR 1 "general_operand" "")))]
366 s390_compare_op0 = operands[0];
367 s390_compare_op1 = operands[1];
371 (define_expand "cmp<mode>"
372 [(set (reg:CC CC_REGNUM)
373 (compare:CC (match_operand:FPR 0 "register_operand" "")
374 (match_operand:FPR 1 "general_operand" "")))]
377 s390_compare_op0 = operands[0];
378 s390_compare_op1 = operands[1];
383 ; Test-under-Mask instructions
385 (define_insn "*tmqi_mem"
386 [(set (reg CC_REGNUM)
387 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
388 (match_operand:QI 1 "immediate_operand" "n,n"))
389 (match_operand:QI 2 "immediate_operand" "n,n")))]
390 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
394 [(set_attr "op_type" "SI,SIY")])
396 (define_insn "*tmdi_reg"
397 [(set (reg CC_REGNUM)
398 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
399 (match_operand:DI 1 "immediate_operand"
400 "N0HD0,N1HD0,N2HD0,N3HD0"))
401 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
403 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
404 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
410 [(set_attr "op_type" "RI")])
412 (define_insn "*tmsi_reg"
413 [(set (reg CC_REGNUM)
414 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
415 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
416 (match_operand:SI 2 "immediate_operand" "n,n")))]
417 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
418 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
422 [(set_attr "op_type" "RI")])
424 (define_insn "*tm<mode>_full"
425 [(set (reg CC_REGNUM)
426 (compare (match_operand:HQI 0 "register_operand" "d")
427 (match_operand:HQI 1 "immediate_operand" "n")))]
428 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
430 [(set_attr "op_type" "RI")])
434 ; Load-and-Test instructions
437 ; tst(di|si) intruction pattern(s).
439 (define_insn "*tstdi_sign"
440 [(set (reg CC_REGNUM)
441 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
442 (const_int 32)) (const_int 32))
443 (match_operand:DI 1 "const0_operand" "")))
444 (set (match_operand:DI 2 "register_operand" "=d")
445 (sign_extend:DI (match_dup 0)))]
446 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
448 [(set_attr "op_type" "RRE")])
450 (define_insn "*tst<mode>_extimm"
451 [(set (reg CC_REGNUM)
452 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
453 (match_operand:GPR 1 "const0_operand" "")))
454 (set (match_operand:GPR 2 "register_operand" "=d,d")
456 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
460 [(set_attr "op_type" "RR<E>,RXY")])
462 (define_insn "*tst<mode>_cconly_extimm"
463 [(set (reg CC_REGNUM)
464 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
465 (match_operand:GPR 1 "const0_operand" "")))
466 (clobber (match_scratch:GPR 2 "=X,d"))]
467 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
471 [(set_attr "op_type" "RR<E>,RXY")])
473 (define_insn "*tstdi"
474 [(set (reg CC_REGNUM)
475 (compare (match_operand:DI 0 "register_operand" "d")
476 (match_operand:DI 1 "const0_operand" "")))
477 (set (match_operand:DI 2 "register_operand" "=d")
479 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
481 [(set_attr "op_type" "RRE")])
483 (define_insn "*tstsi"
484 [(set (reg CC_REGNUM)
485 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
486 (match_operand:SI 1 "const0_operand" "")))
487 (set (match_operand:SI 2 "register_operand" "=d,d,d")
489 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
494 [(set_attr "op_type" "RR,RS,RSY")])
496 (define_insn "*tstsi_cconly"
497 [(set (reg CC_REGNUM)
498 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
499 (match_operand:SI 1 "const0_operand" "")))
500 (clobber (match_scratch:SI 2 "=X,d,d"))]
501 "s390_match_ccmode(insn, CCSmode)"
506 [(set_attr "op_type" "RR,RS,RSY")])
508 (define_insn "*tstdi_cconly_31"
509 [(set (reg CC_REGNUM)
510 (compare (match_operand:DI 0 "register_operand" "d")
511 (match_operand:DI 1 "const0_operand" "")))]
512 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
514 [(set_attr "op_type" "RS")
515 (set_attr "atype" "reg")])
517 (define_insn "*tst<mode>_cconly2"
518 [(set (reg CC_REGNUM)
519 (compare (match_operand:GPR 0 "register_operand" "d")
520 (match_operand:GPR 1 "const0_operand" "")))]
521 "s390_match_ccmode(insn, CCSmode)"
523 [(set_attr "op_type" "RR<E>")])
525 ; tst(hi|qi) intruction pattern(s).
527 (define_insn "*tst<mode>CCT"
528 [(set (reg CC_REGNUM)
529 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
530 (match_operand:HQI 1 "const0_operand" "")))
531 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
533 "s390_match_ccmode(insn, CCTmode)"
536 icmy\t%2,<icm_lo>,%S0
538 [(set_attr "op_type" "RS,RSY,RI")])
540 (define_insn "*tsthiCCT_cconly"
541 [(set (reg CC_REGNUM)
542 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
543 (match_operand:HI 1 "const0_operand" "")))
544 (clobber (match_scratch:HI 2 "=d,d,X"))]
545 "s390_match_ccmode(insn, CCTmode)"
550 [(set_attr "op_type" "RS,RSY,RI")])
552 (define_insn "*tstqiCCT_cconly"
553 [(set (reg CC_REGNUM)
554 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
555 (match_operand:QI 1 "const0_operand" "")))]
556 "s390_match_ccmode(insn, CCTmode)"
561 [(set_attr "op_type" "SI,SIY,RI")])
563 (define_insn "*tst<mode>"
564 [(set (reg CC_REGNUM)
565 (compare (match_operand:HQI 0 "s_operand" "Q,S")
566 (match_operand:HQI 1 "const0_operand" "")))
567 (set (match_operand:HQI 2 "register_operand" "=d,d")
569 "s390_match_ccmode(insn, CCSmode)"
572 icmy\t%2,<icm_lo>,%S0"
573 [(set_attr "op_type" "RS,RSY")])
575 (define_insn "*tst<mode>_cconly"
576 [(set (reg CC_REGNUM)
577 (compare (match_operand:HQI 0 "s_operand" "Q,S")
578 (match_operand:HQI 1 "const0_operand" "")))
579 (clobber (match_scratch:HQI 2 "=d,d"))]
580 "s390_match_ccmode(insn, CCSmode)"
583 icmy\t%2,<icm_lo>,%S0"
584 [(set_attr "op_type" "RS,RSY")])
587 ; Compare (equality) instructions
589 (define_insn "*cmpdi_cct"
590 [(set (reg CC_REGNUM)
591 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
592 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
593 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
600 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
602 (define_insn "*cmpsi_cct"
603 [(set (reg CC_REGNUM)
604 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
605 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
606 "s390_match_ccmode (insn, CCTmode)"
614 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
617 ; Compare (signed) instructions
619 (define_insn "*cmpdi_ccs_sign"
620 [(set (reg CC_REGNUM)
621 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
622 (match_operand:DI 0 "register_operand" "d,d")))]
623 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
627 [(set_attr "op_type" "RRE,RXY")])
629 (define_insn "*cmpdi_ccs"
630 [(set (reg CC_REGNUM)
631 (compare (match_operand:DI 0 "register_operand" "d,d,d,d")
632 (match_operand:DI 1 "general_operand" "d,K,Os,m")))]
633 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
639 [(set_attr "op_type" "RRE,RI,RIL,RXY")])
641 (define_insn "*cmpsi_ccs_sign"
642 [(set (reg CC_REGNUM)
643 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
644 (match_operand:SI 0 "register_operand" "d,d")))]
645 "s390_match_ccmode(insn, CCSRmode)"
649 [(set_attr "op_type" "RX,RXY")])
651 (define_insn "*cmpsi_ccs"
652 [(set (reg CC_REGNUM)
653 (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d")
654 (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))]
655 "s390_match_ccmode(insn, CCSmode)"
662 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
665 ; Compare (unsigned) instructions
667 (define_insn "*cmpdi_ccu_zero"
668 [(set (reg CC_REGNUM)
669 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
670 (match_operand:DI 0 "register_operand" "d,d")))]
671 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
675 [(set_attr "op_type" "RRE,RXY")])
677 (define_insn "*cmpdi_ccu"
678 [(set (reg CC_REGNUM)
679 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
680 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
681 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
688 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
690 (define_insn "*cmpsi_ccu"
691 [(set (reg CC_REGNUM)
692 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
693 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
694 "s390_match_ccmode (insn, CCUmode)"
702 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
704 (define_insn "*cmphi_ccu"
705 [(set (reg CC_REGNUM)
706 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
707 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
708 "s390_match_ccmode (insn, CCUmode)
709 && !register_operand (operands[1], HImode)"
715 [(set_attr "op_type" "RS,RSY,SS,SS")])
717 (define_insn "*cmpqi_ccu"
718 [(set (reg CC_REGNUM)
719 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
720 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
721 "s390_match_ccmode (insn, CCUmode)
722 && !register_operand (operands[1], QImode)"
730 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
733 ; Block compare (CLC) instruction patterns.
736 [(set (reg CC_REGNUM)
737 (compare (match_operand:BLK 0 "memory_operand" "Q")
738 (match_operand:BLK 1 "memory_operand" "Q")))
739 (use (match_operand 2 "const_int_operand" "n"))]
740 "s390_match_ccmode (insn, CCUmode)
741 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
742 "clc\t%O0(%2,%R0),%S1"
743 [(set_attr "op_type" "SS")])
746 [(set (reg CC_REGNUM)
747 (compare (match_operand 0 "memory_operand" "")
748 (match_operand 1 "memory_operand" "")))]
750 && s390_match_ccmode (insn, CCUmode)
751 && GET_MODE (operands[0]) == GET_MODE (operands[1])
752 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
754 [(set (match_dup 0) (match_dup 1))
755 (use (match_dup 2))])]
757 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
758 operands[0] = adjust_address (operands[0], BLKmode, 0);
759 operands[1] = adjust_address (operands[1], BLKmode, 0);
761 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
762 operands[0], operands[1]);
763 operands[0] = SET_DEST (PATTERN (curr_insn));
767 ; (DF|SF) instructions
769 (define_insn "*cmp<mode>_ccs_0"
770 [(set (reg CC_REGNUM)
771 (compare (match_operand:FPR 0 "register_operand" "f")
772 (match_operand:FPR 1 "const0_operand" "")))]
773 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
775 [(set_attr "op_type" "RRE")
776 (set_attr "type" "fsimp<mode>")])
778 (define_insn "*cmp<mode>_ccs_0_ibm"
779 [(set (reg CC_REGNUM)
780 (compare (match_operand:FPR 0 "register_operand" "f")
781 (match_operand:FPR 1 "const0_operand" "")))]
782 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
784 [(set_attr "op_type" "RR")
785 (set_attr "type" "fsimp<mode>")])
787 (define_insn "*cmp<mode>_ccs"
788 [(set (reg CC_REGNUM)
789 (compare (match_operand:FPR 0 "register_operand" "f,f")
790 (match_operand:FPR 1 "general_operand" "f,R")))]
791 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
795 [(set_attr "op_type" "RRE,RXE")
796 (set_attr "type" "fsimp<mode>")])
798 (define_insn "*cmp<mode>_ccs_ibm"
799 [(set (reg CC_REGNUM)
800 (compare (match_operand:FPR 0 "register_operand" "f,f")
801 (match_operand:FPR 1 "general_operand" "f,R")))]
802 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
806 [(set_attr "op_type" "RR,RX")
807 (set_attr "type" "fsimp<mode>")])
811 ;;- Move instructions.
815 ; movti instruction pattern(s).
819 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
820 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
828 [(set_attr "op_type" "RSY,RSY,*,*,SS")
829 (set_attr "type" "lm,stm,*,*,*")])
832 [(set (match_operand:TI 0 "nonimmediate_operand" "")
833 (match_operand:TI 1 "general_operand" ""))]
834 "TARGET_64BIT && reload_completed
835 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
836 [(set (match_dup 2) (match_dup 4))
837 (set (match_dup 3) (match_dup 5))]
839 operands[2] = operand_subword (operands[0], 0, 0, TImode);
840 operands[3] = operand_subword (operands[0], 1, 0, TImode);
841 operands[4] = operand_subword (operands[1], 0, 0, TImode);
842 operands[5] = operand_subword (operands[1], 1, 0, TImode);
846 [(set (match_operand:TI 0 "nonimmediate_operand" "")
847 (match_operand:TI 1 "general_operand" ""))]
848 "TARGET_64BIT && reload_completed
849 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
850 [(set (match_dup 2) (match_dup 4))
851 (set (match_dup 3) (match_dup 5))]
853 operands[2] = operand_subword (operands[0], 1, 0, TImode);
854 operands[3] = operand_subword (operands[0], 0, 0, TImode);
855 operands[4] = operand_subword (operands[1], 1, 0, TImode);
856 operands[5] = operand_subword (operands[1], 0, 0, TImode);
860 [(set (match_operand:TI 0 "register_operand" "")
861 (match_operand:TI 1 "memory_operand" ""))]
862 "TARGET_64BIT && reload_completed
863 && !s_operand (operands[1], VOIDmode)"
864 [(set (match_dup 0) (match_dup 1))]
866 rtx addr = operand_subword (operands[0], 1, 0, TImode);
867 s390_load_address (addr, XEXP (operands[1], 0));
868 operands[1] = replace_equiv_address (operands[1], addr);
871 (define_expand "reload_outti"
872 [(parallel [(match_operand:TI 0 "" "")
873 (match_operand:TI 1 "register_operand" "d")
874 (match_operand:DI 2 "register_operand" "=&a")])]
877 gcc_assert (MEM_P (operands[0]));
878 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
879 operands[0] = replace_equiv_address (operands[0], operands[2]);
880 emit_move_insn (operands[0], operands[1]);
885 ; movdi instruction pattern(s).
888 (define_expand "movdi"
889 [(set (match_operand:DI 0 "general_operand" "")
890 (match_operand:DI 1 "general_operand" ""))]
893 /* Handle symbolic constants. */
894 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
895 emit_symbolic_move (operands);
898 (define_insn "*movdi_larl"
899 [(set (match_operand:DI 0 "register_operand" "=d")
900 (match_operand:DI 1 "larl_operand" "X"))]
902 && !FP_REG_P (operands[0])"
904 [(set_attr "op_type" "RIL")
905 (set_attr "type" "larl")])
907 (define_insn "*movdi_64extimm"
908 [(set (match_operand:DI 0 "nonimmediate_operand"
909 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
910 (match_operand:DI 1 "general_operand"
911 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
912 "TARGET_64BIT && TARGET_EXTIMM"
936 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
937 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
938 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
939 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
941 (define_insn "*movdi_64"
942 [(set (match_operand:DI 0 "nonimmediate_operand"
943 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
944 (match_operand:DI 1 "general_operand"
945 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
946 "TARGET_64BIT && !TARGET_EXTIMM"
967 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
968 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
969 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
970 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
973 [(set (match_operand:DI 0 "register_operand" "")
974 (match_operand:DI 1 "register_operand" ""))]
975 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
976 [(set (match_dup 2) (match_dup 3))
977 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
978 (set (strict_low_part (match_dup 2)) (match_dup 4))]
979 "operands[2] = gen_lowpart (SImode, operands[0]);
980 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
983 [(set (match_operand:DI 0 "register_operand" "")
984 (match_operand:DI 1 "register_operand" ""))]
985 "TARGET_64BIT && ACCESS_REG_P (operands[0])
986 && dead_or_set_p (insn, operands[1])"
987 [(set (match_dup 3) (match_dup 2))
988 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
989 (set (match_dup 4) (match_dup 2))]
990 "operands[2] = gen_lowpart (SImode, operands[1]);
991 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
994 [(set (match_operand:DI 0 "register_operand" "")
995 (match_operand:DI 1 "register_operand" ""))]
996 "TARGET_64BIT && ACCESS_REG_P (operands[0])
997 && !dead_or_set_p (insn, operands[1])"
998 [(set (match_dup 3) (match_dup 2))
999 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1000 (set (match_dup 4) (match_dup 2))
1001 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1002 "operands[2] = gen_lowpart (SImode, operands[1]);
1003 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1005 (define_insn "*movdi_31"
1006 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1007 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1022 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1023 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1026 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1027 (match_operand:DI 1 "general_operand" ""))]
1028 "!TARGET_64BIT && reload_completed
1029 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1030 [(set (match_dup 2) (match_dup 4))
1031 (set (match_dup 3) (match_dup 5))]
1033 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1034 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1035 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1036 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1040 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1041 (match_operand:DI 1 "general_operand" ""))]
1042 "!TARGET_64BIT && reload_completed
1043 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1044 [(set (match_dup 2) (match_dup 4))
1045 (set (match_dup 3) (match_dup 5))]
1047 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1048 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1049 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1050 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1054 [(set (match_operand:DI 0 "register_operand" "")
1055 (match_operand:DI 1 "memory_operand" ""))]
1056 "!TARGET_64BIT && reload_completed
1057 && !FP_REG_P (operands[0])
1058 && !s_operand (operands[1], VOIDmode)"
1059 [(set (match_dup 0) (match_dup 1))]
1061 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1062 s390_load_address (addr, XEXP (operands[1], 0));
1063 operands[1] = replace_equiv_address (operands[1], addr);
1066 (define_expand "reload_outdi"
1067 [(parallel [(match_operand:DI 0 "" "")
1068 (match_operand:DI 1 "register_operand" "d")
1069 (match_operand:SI 2 "register_operand" "=&a")])]
1072 gcc_assert (MEM_P (operands[0]));
1073 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1074 operands[0] = replace_equiv_address (operands[0], operands[2]);
1075 emit_move_insn (operands[0], operands[1]);
1080 [(set (match_operand:DI 0 "register_operand" "")
1081 (mem:DI (match_operand 1 "address_operand" "")))]
1083 && !FP_REG_P (operands[0])
1084 && GET_CODE (operands[1]) == SYMBOL_REF
1085 && CONSTANT_POOL_ADDRESS_P (operands[1])
1086 && get_pool_mode (operands[1]) == DImode
1087 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1088 [(set (match_dup 0) (match_dup 2))]
1089 "operands[2] = get_pool_constant (operands[1]);")
1091 (define_insn "*la_64"
1092 [(set (match_operand:DI 0 "register_operand" "=d,d")
1093 (match_operand:QI 1 "address_operand" "U,W"))]
1098 [(set_attr "op_type" "RX,RXY")
1099 (set_attr "type" "la")])
1103 [(set (match_operand:DI 0 "register_operand" "")
1104 (match_operand:QI 1 "address_operand" ""))
1105 (clobber (reg:CC CC_REGNUM))])]
1107 && preferred_la_operand_p (operands[1], const0_rtx)"
1108 [(set (match_dup 0) (match_dup 1))]
1112 [(set (match_operand:DI 0 "register_operand" "")
1113 (match_operand:DI 1 "register_operand" ""))
1116 (plus:DI (match_dup 0)
1117 (match_operand:DI 2 "nonmemory_operand" "")))
1118 (clobber (reg:CC CC_REGNUM))])]
1120 && !reg_overlap_mentioned_p (operands[0], operands[2])
1121 && preferred_la_operand_p (operands[1], operands[2])"
1122 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1125 (define_expand "reload_indi"
1126 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1127 (match_operand:DI 1 "s390_plus_operand" "")
1128 (match_operand:DI 2 "register_operand" "=&a")])]
1131 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1136 ; movsi instruction pattern(s).
1139 (define_expand "movsi"
1140 [(set (match_operand:SI 0 "general_operand" "")
1141 (match_operand:SI 1 "general_operand" ""))]
1144 /* Handle symbolic constants. */
1145 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1146 emit_symbolic_move (operands);
1149 (define_insn "*movsi_larl"
1150 [(set (match_operand:SI 0 "register_operand" "=d")
1151 (match_operand:SI 1 "larl_operand" "X"))]
1152 "!TARGET_64BIT && TARGET_CPU_ZARCH
1153 && !FP_REG_P (operands[0])"
1155 [(set_attr "op_type" "RIL")
1156 (set_attr "type" "larl")])
1158 (define_insn "*movsi_zarch"
1159 [(set (match_operand:SI 0 "nonimmediate_operand"
1160 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1161 (match_operand:SI 1 "general_operand"
1162 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1185 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1186 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1187 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1188 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1190 (define_insn "*movsi_esa"
1191 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1192 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1207 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1208 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1211 [(set (match_operand:SI 0 "register_operand" "")
1212 (mem:SI (match_operand 1 "address_operand" "")))]
1213 "!FP_REG_P (operands[0])
1214 && GET_CODE (operands[1]) == SYMBOL_REF
1215 && CONSTANT_POOL_ADDRESS_P (operands[1])
1216 && get_pool_mode (operands[1]) == SImode
1217 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1218 [(set (match_dup 0) (match_dup 2))]
1219 "operands[2] = get_pool_constant (operands[1]);")
1221 (define_insn "*la_31"
1222 [(set (match_operand:SI 0 "register_operand" "=d,d")
1223 (match_operand:QI 1 "address_operand" "U,W"))]
1224 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1228 [(set_attr "op_type" "RX,RXY")
1229 (set_attr "type" "la")])
1233 [(set (match_operand:SI 0 "register_operand" "")
1234 (match_operand:QI 1 "address_operand" ""))
1235 (clobber (reg:CC CC_REGNUM))])]
1237 && preferred_la_operand_p (operands[1], const0_rtx)"
1238 [(set (match_dup 0) (match_dup 1))]
1242 [(set (match_operand:SI 0 "register_operand" "")
1243 (match_operand:SI 1 "register_operand" ""))
1246 (plus:SI (match_dup 0)
1247 (match_operand:SI 2 "nonmemory_operand" "")))
1248 (clobber (reg:CC CC_REGNUM))])]
1250 && !reg_overlap_mentioned_p (operands[0], operands[2])
1251 && preferred_la_operand_p (operands[1], operands[2])"
1252 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1255 (define_insn "*la_31_and"
1256 [(set (match_operand:SI 0 "register_operand" "=d,d")
1257 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1258 (const_int 2147483647)))]
1263 [(set_attr "op_type" "RX,RXY")
1264 (set_attr "type" "la")])
1266 (define_insn_and_split "*la_31_and_cc"
1267 [(set (match_operand:SI 0 "register_operand" "=d")
1268 (and:SI (match_operand:QI 1 "address_operand" "p")
1269 (const_int 2147483647)))
1270 (clobber (reg:CC CC_REGNUM))]
1273 "&& reload_completed"
1275 (and:SI (match_dup 1) (const_int 2147483647)))]
1277 [(set_attr "op_type" "RX")
1278 (set_attr "type" "la")])
1280 (define_insn "force_la_31"
1281 [(set (match_operand:SI 0 "register_operand" "=d,d")
1282 (match_operand:QI 1 "address_operand" "U,W"))
1283 (use (const_int 0))]
1288 [(set_attr "op_type" "RX")
1289 (set_attr "type" "la")])
1291 (define_expand "reload_insi"
1292 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1293 (match_operand:SI 1 "s390_plus_operand" "")
1294 (match_operand:SI 2 "register_operand" "=&a")])]
1297 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1302 ; movhi instruction pattern(s).
1305 (define_expand "movhi"
1306 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1307 (match_operand:HI 1 "general_operand" ""))]
1310 /* Make it explicit that loading a register from memory
1311 always sign-extends (at least) to SImode. */
1312 if (optimize && !no_new_pseudos
1313 && register_operand (operands[0], VOIDmode)
1314 && GET_CODE (operands[1]) == MEM)
1316 rtx tmp = gen_reg_rtx (SImode);
1317 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1318 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1319 operands[1] = gen_lowpart (HImode, tmp);
1323 (define_insn "*movhi"
1324 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1325 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1335 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1336 (set_attr "type" "lr,*,*,*,store,store,*")])
1339 [(set (match_operand:HI 0 "register_operand" "")
1340 (mem:HI (match_operand 1 "address_operand" "")))]
1341 "GET_CODE (operands[1]) == SYMBOL_REF
1342 && CONSTANT_POOL_ADDRESS_P (operands[1])
1343 && get_pool_mode (operands[1]) == HImode
1344 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1345 [(set (match_dup 0) (match_dup 2))]
1346 "operands[2] = get_pool_constant (operands[1]);")
1349 ; movqi instruction pattern(s).
1352 (define_expand "movqi"
1353 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1354 (match_operand:QI 1 "general_operand" ""))]
1357 /* On z/Architecture, zero-extending from memory to register
1358 is just as fast as a QImode load. */
1359 if (TARGET_ZARCH && optimize && !no_new_pseudos
1360 && register_operand (operands[0], VOIDmode)
1361 && GET_CODE (operands[1]) == MEM)
1363 rtx tmp = gen_reg_rtx (word_mode);
1364 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1365 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1366 operands[1] = gen_lowpart (QImode, tmp);
1370 (define_insn "*movqi"
1371 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1372 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1384 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1385 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1388 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1389 (mem:QI (match_operand 1 "address_operand" "")))]
1390 "GET_CODE (operands[1]) == SYMBOL_REF
1391 && CONSTANT_POOL_ADDRESS_P (operands[1])
1392 && get_pool_mode (operands[1]) == QImode
1393 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1394 [(set (match_dup 0) (match_dup 2))]
1395 "operands[2] = get_pool_constant (operands[1]);")
1398 ; movstrictqi instruction pattern(s).
1401 (define_insn "*movstrictqi"
1402 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1403 (match_operand:QI 1 "memory_operand" "R,T"))]
1408 [(set_attr "op_type" "RX,RXY")])
1411 ; movstricthi instruction pattern(s).
1414 (define_insn "*movstricthi"
1415 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1416 (match_operand:HI 1 "memory_operand" "Q,S"))
1417 (clobber (reg:CC CC_REGNUM))]
1422 [(set_attr "op_type" "RS,RSY")])
1425 ; movstrictsi instruction pattern(s).
1428 (define_insn "movstrictsi"
1429 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1430 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1437 [(set_attr "op_type" "RR,RX,RXY,RRE")
1438 (set_attr "type" "lr,load,load,*")])
1441 ; movdf instruction pattern(s).
1444 (define_expand "movdf"
1445 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1446 (match_operand:DF 1 "general_operand" ""))]
1450 (define_insn "*movdf_64"
1451 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1452 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1465 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1466 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1468 (define_insn "*movdf_31"
1469 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1470 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1486 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1487 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1488 lm,lm,stm,stm,*,*,*")])
1491 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1492 (match_operand:DF 1 "general_operand" ""))]
1493 "!TARGET_64BIT && reload_completed
1494 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1495 [(set (match_dup 2) (match_dup 4))
1496 (set (match_dup 3) (match_dup 5))]
1498 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1499 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1500 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1501 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1505 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1506 (match_operand:DF 1 "general_operand" ""))]
1507 "!TARGET_64BIT && reload_completed
1508 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1509 [(set (match_dup 2) (match_dup 4))
1510 (set (match_dup 3) (match_dup 5))]
1512 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1513 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1514 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1515 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1519 [(set (match_operand:DF 0 "register_operand" "")
1520 (match_operand:DF 1 "memory_operand" ""))]
1521 "!TARGET_64BIT && reload_completed
1522 && !FP_REG_P (operands[0])
1523 && !s_operand (operands[1], VOIDmode)"
1524 [(set (match_dup 0) (match_dup 1))]
1526 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1527 s390_load_address (addr, XEXP (operands[1], 0));
1528 operands[1] = replace_equiv_address (operands[1], addr);
1531 (define_expand "reload_outdf"
1532 [(parallel [(match_operand:DF 0 "" "")
1533 (match_operand:DF 1 "register_operand" "d")
1534 (match_operand:SI 2 "register_operand" "=&a")])]
1537 gcc_assert (MEM_P (operands[0]));
1538 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1539 operands[0] = replace_equiv_address (operands[0], operands[2]);
1540 emit_move_insn (operands[0], operands[1]);
1545 ; movsf instruction pattern(s).
1548 (define_insn "movsf"
1549 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1550 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1565 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1566 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1567 lr,load,load,store,store,*")])
1570 ; movcc instruction pattern
1573 (define_insn "movcc"
1574 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1575 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1585 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1586 (set_attr "type" "lr,*,*,store,store,load,load")])
1589 ; Block move (MVC) patterns.
1593 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1594 (match_operand:BLK 1 "memory_operand" "Q"))
1595 (use (match_operand 2 "const_int_operand" "n"))]
1596 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1597 "mvc\t%O0(%2,%R0),%S1"
1598 [(set_attr "op_type" "SS")])
1601 [(set (match_operand 0 "memory_operand" "")
1602 (match_operand 1 "memory_operand" ""))]
1604 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1605 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1607 [(set (match_dup 0) (match_dup 1))
1608 (use (match_dup 2))])]
1610 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1611 operands[0] = adjust_address (operands[0], BLKmode, 0);
1612 operands[1] = adjust_address (operands[1], BLKmode, 0);
1617 [(set (match_operand:BLK 0 "memory_operand" "")
1618 (match_operand:BLK 1 "memory_operand" ""))
1619 (use (match_operand 2 "const_int_operand" ""))])
1621 [(set (match_operand:BLK 3 "memory_operand" "")
1622 (match_operand:BLK 4 "memory_operand" ""))
1623 (use (match_operand 5 "const_int_operand" ""))])]
1624 "s390_offset_p (operands[0], operands[3], operands[2])
1625 && s390_offset_p (operands[1], operands[4], operands[2])
1626 && !s390_overlap_p (operands[0], operands[1],
1627 INTVAL (operands[2]) + INTVAL (operands[5]))
1628 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1630 [(set (match_dup 6) (match_dup 7))
1631 (use (match_dup 8))])]
1632 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1633 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1634 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1638 ; load_multiple pattern(s).
1640 ; ??? Due to reload problems with replacing registers inside match_parallel
1641 ; we currently support load_multiple/store_multiple only after reload.
1644 (define_expand "load_multiple"
1645 [(match_par_dup 3 [(set (match_operand 0 "" "")
1646 (match_operand 1 "" ""))
1647 (use (match_operand 2 "" ""))])]
1650 enum machine_mode mode;
1656 /* Support only loading a constant number of fixed-point registers from
1657 memory and only bother with this if more than two */
1658 if (GET_CODE (operands[2]) != CONST_INT
1659 || INTVAL (operands[2]) < 2
1660 || INTVAL (operands[2]) > 16
1661 || GET_CODE (operands[1]) != MEM
1662 || GET_CODE (operands[0]) != REG
1663 || REGNO (operands[0]) >= 16)
1666 count = INTVAL (operands[2]);
1667 regno = REGNO (operands[0]);
1668 mode = GET_MODE (operands[0]);
1669 if (mode != SImode && mode != word_mode)
1672 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1675 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1677 from = XEXP (operands[1], 0);
1680 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1681 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1682 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1684 from = XEXP (XEXP (operands[1], 0), 0);
1685 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1692 from = force_reg (Pmode, XEXP (operands[1], 0));
1696 for (i = 0; i < count; i++)
1697 XVECEXP (operands[3], 0, i)
1698 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1699 change_address (operands[1], mode,
1700 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1703 (define_insn "*load_multiple_di"
1704 [(match_parallel 0 "load_multiple_operation"
1705 [(set (match_operand:DI 1 "register_operand" "=r")
1706 (match_operand:DI 2 "s_operand" "QS"))])]
1707 "reload_completed && word_mode == DImode"
1709 int words = XVECLEN (operands[0], 0);
1710 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1711 return "lmg\t%1,%0,%S2";
1713 [(set_attr "op_type" "RSY")
1714 (set_attr "type" "lm")])
1716 (define_insn "*load_multiple_si"
1717 [(match_parallel 0 "load_multiple_operation"
1718 [(set (match_operand:SI 1 "register_operand" "=r,r")
1719 (match_operand:SI 2 "s_operand" "Q,S"))])]
1722 int words = XVECLEN (operands[0], 0);
1723 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1724 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1726 [(set_attr "op_type" "RS,RSY")
1727 (set_attr "type" "lm")])
1730 ; store multiple pattern(s).
1733 (define_expand "store_multiple"
1734 [(match_par_dup 3 [(set (match_operand 0 "" "")
1735 (match_operand 1 "" ""))
1736 (use (match_operand 2 "" ""))])]
1739 enum machine_mode mode;
1745 /* Support only storing a constant number of fixed-point registers to
1746 memory and only bother with this if more than two. */
1747 if (GET_CODE (operands[2]) != CONST_INT
1748 || INTVAL (operands[2]) < 2
1749 || INTVAL (operands[2]) > 16
1750 || GET_CODE (operands[0]) != MEM
1751 || GET_CODE (operands[1]) != REG
1752 || REGNO (operands[1]) >= 16)
1755 count = INTVAL (operands[2]);
1756 regno = REGNO (operands[1]);
1757 mode = GET_MODE (operands[1]);
1758 if (mode != SImode && mode != word_mode)
1761 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1765 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1767 to = XEXP (operands[0], 0);
1770 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1771 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1772 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1774 to = XEXP (XEXP (operands[0], 0), 0);
1775 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1782 to = force_reg (Pmode, XEXP (operands[0], 0));
1786 for (i = 0; i < count; i++)
1787 XVECEXP (operands[3], 0, i)
1788 = gen_rtx_SET (VOIDmode,
1789 change_address (operands[0], mode,
1790 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1791 gen_rtx_REG (mode, regno + i));
1794 (define_insn "*store_multiple_di"
1795 [(match_parallel 0 "store_multiple_operation"
1796 [(set (match_operand:DI 1 "s_operand" "=QS")
1797 (match_operand:DI 2 "register_operand" "r"))])]
1798 "reload_completed && word_mode == DImode"
1800 int words = XVECLEN (operands[0], 0);
1801 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1802 return "stmg\t%2,%0,%S1";
1804 [(set_attr "op_type" "RSY")
1805 (set_attr "type" "stm")])
1808 (define_insn "*store_multiple_si"
1809 [(match_parallel 0 "store_multiple_operation"
1810 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1811 (match_operand:SI 2 "register_operand" "r,r"))])]
1814 int words = XVECLEN (operands[0], 0);
1815 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1816 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1818 [(set_attr "op_type" "RS,RSY")
1819 (set_attr "type" "stm")])
1822 ;; String instructions.
1825 (define_insn "*execute"
1826 [(match_parallel 0 ""
1827 [(unspec [(match_operand 1 "register_operand" "a")
1828 (match_operand:BLK 2 "memory_operand" "R")
1829 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1830 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1831 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1833 [(set_attr "op_type" "RX")
1834 (set_attr "type" "cs")])
1838 ; strlenM instruction pattern(s).
1841 (define_expand "strlen<mode>"
1842 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1845 (unspec:P [(const_int 0)
1846 (match_operand:BLK 1 "memory_operand" "")
1848 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1849 (clobber (scratch:P))
1850 (clobber (reg:CC CC_REGNUM))])
1852 [(set (match_operand:P 0 "register_operand" "")
1853 (minus:P (match_dup 4) (match_dup 5)))
1854 (clobber (reg:CC CC_REGNUM))])]
1857 operands[4] = gen_reg_rtx (Pmode);
1858 operands[5] = gen_reg_rtx (Pmode);
1859 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1860 operands[1] = replace_equiv_address (operands[1], operands[5]);
1863 (define_insn "*strlen<mode>"
1864 [(set (match_operand:P 0 "register_operand" "=a")
1865 (unspec:P [(match_operand:P 2 "general_operand" "0")
1866 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1868 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1869 (clobber (match_scratch:P 1 "=a"))
1870 (clobber (reg:CC CC_REGNUM))]
1872 "srst\t%0,%1\;jo\t.-4"
1873 [(set_attr "length" "8")
1874 (set_attr "type" "vs")])
1877 ; cmpstrM instruction pattern(s).
1880 (define_expand "cmpstrsi"
1881 [(set (reg:SI 0) (const_int 0))
1883 [(clobber (match_operand 3 "" ""))
1884 (clobber (match_dup 4))
1885 (set (reg:CCU CC_REGNUM)
1886 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
1887 (match_operand:BLK 2 "memory_operand" "")))
1890 [(set (match_operand:SI 0 "register_operand" "=d")
1891 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
1892 (clobber (reg:CC CC_REGNUM))])]
1895 /* As the result of CMPINT is inverted compared to what we need,
1896 we have to swap the operands. */
1897 rtx op1 = operands[2];
1898 rtx op2 = operands[1];
1899 rtx addr1 = gen_reg_rtx (Pmode);
1900 rtx addr2 = gen_reg_rtx (Pmode);
1902 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
1903 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
1904 operands[1] = replace_equiv_address_nv (op1, addr1);
1905 operands[2] = replace_equiv_address_nv (op2, addr2);
1906 operands[3] = addr1;
1907 operands[4] = addr2;
1910 (define_insn "*cmpstr<mode>"
1911 [(clobber (match_operand:P 0 "register_operand" "=d"))
1912 (clobber (match_operand:P 1 "register_operand" "=d"))
1913 (set (reg:CCU CC_REGNUM)
1914 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
1915 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
1918 "clst\t%0,%1\;jo\t.-4"
1919 [(set_attr "length" "8")
1920 (set_attr "type" "vs")])
1923 ; movstr instruction pattern.
1926 (define_expand "movstr"
1927 [(set (reg:SI 0) (const_int 0))
1929 [(clobber (match_dup 3))
1930 (set (match_operand:BLK 1 "memory_operand" "")
1931 (match_operand:BLK 2 "memory_operand" ""))
1932 (set (match_operand 0 "register_operand" "")
1933 (unspec [(match_dup 1)
1935 (reg:SI 0)] UNSPEC_MVST))
1936 (clobber (reg:CC CC_REGNUM))])]
1939 rtx addr1 = gen_reg_rtx (Pmode);
1940 rtx addr2 = gen_reg_rtx (Pmode);
1942 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1943 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
1944 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1945 operands[2] = replace_equiv_address_nv (operands[2], addr2);
1946 operands[3] = addr2;
1949 (define_insn "*movstr"
1950 [(clobber (match_operand:P 2 "register_operand" "=d"))
1951 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
1952 (mem:BLK (match_operand:P 3 "register_operand" "2")))
1953 (set (match_operand:P 0 "register_operand" "=d")
1954 (unspec [(mem:BLK (match_dup 1))
1955 (mem:BLK (match_dup 3))
1956 (reg:SI 0)] UNSPEC_MVST))
1957 (clobber (reg:CC CC_REGNUM))]
1959 "mvst\t%1,%2\;jo\t.-4"
1960 [(set_attr "length" "8")
1961 (set_attr "type" "vs")])
1965 ; movmemM instruction pattern(s).
1968 (define_expand "movmem<mode>"
1969 [(set (match_operand:BLK 0 "memory_operand" "")
1970 (match_operand:BLK 1 "memory_operand" ""))
1971 (use (match_operand:GPR 2 "general_operand" ""))
1972 (match_operand 3 "" "")]
1974 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1976 ; Move a block that is up to 256 bytes in length.
1977 ; The block length is taken as (operands[2] % 256) + 1.
1979 (define_expand "movmem_short"
1981 [(set (match_operand:BLK 0 "memory_operand" "")
1982 (match_operand:BLK 1 "memory_operand" ""))
1983 (use (match_operand 2 "nonmemory_operand" ""))
1984 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1985 (clobber (match_dup 3))])]
1987 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1989 (define_insn "*movmem_short"
1990 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1991 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1992 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1993 (use (match_operand 3 "immediate_operand" "X,R,X"))
1994 (clobber (match_scratch 4 "=X,X,&a"))]
1995 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1996 && GET_MODE (operands[4]) == Pmode"
1998 [(set_attr "type" "cs")])
2001 [(set (match_operand:BLK 0 "memory_operand" "")
2002 (match_operand:BLK 1 "memory_operand" ""))
2003 (use (match_operand 2 "const_int_operand" ""))
2004 (use (match_operand 3 "immediate_operand" ""))
2005 (clobber (scratch))]
2008 [(set (match_dup 0) (match_dup 1))
2009 (use (match_dup 2))])]
2010 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2013 [(set (match_operand:BLK 0 "memory_operand" "")
2014 (match_operand:BLK 1 "memory_operand" ""))
2015 (use (match_operand 2 "register_operand" ""))
2016 (use (match_operand 3 "memory_operand" ""))
2017 (clobber (scratch))]
2020 [(unspec [(match_dup 2) (match_dup 3)
2021 (const_int 0)] UNSPEC_EXECUTE)
2022 (set (match_dup 0) (match_dup 1))
2023 (use (const_int 1))])]
2027 [(set (match_operand:BLK 0 "memory_operand" "")
2028 (match_operand:BLK 1 "memory_operand" ""))
2029 (use (match_operand 2 "register_operand" ""))
2030 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2031 (clobber (match_operand 3 "register_operand" ""))]
2032 "reload_completed && TARGET_CPU_ZARCH"
2033 [(set (match_dup 3) (label_ref (match_dup 4)))
2035 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2036 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2037 (set (match_dup 0) (match_dup 1))
2038 (use (const_int 1))])]
2039 "operands[4] = gen_label_rtx ();")
2041 ; Move a block of arbitrary length.
2043 (define_expand "movmem_long"
2045 [(clobber (match_dup 2))
2046 (clobber (match_dup 3))
2047 (set (match_operand:BLK 0 "memory_operand" "")
2048 (match_operand:BLK 1 "memory_operand" ""))
2049 (use (match_operand 2 "general_operand" ""))
2051 (clobber (reg:CC CC_REGNUM))])]
2054 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2055 rtx reg0 = gen_reg_rtx (dword_mode);
2056 rtx reg1 = gen_reg_rtx (dword_mode);
2057 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2058 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2059 rtx len0 = gen_lowpart (Pmode, reg0);
2060 rtx len1 = gen_lowpart (Pmode, reg1);
2062 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2063 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2064 emit_move_insn (len0, operands[2]);
2066 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2067 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2068 emit_move_insn (len1, operands[2]);
2070 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2071 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2076 (define_insn "*movmem_long"
2077 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2078 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2079 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2080 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2083 (clobber (reg:CC CC_REGNUM))]
2085 "mvcle\t%0,%1,0\;jo\t.-4"
2086 [(set_attr "length" "8")
2087 (set_attr "type" "vs")])
2090 ; setmemM instruction pattern(s).
2093 (define_expand "setmem<mode>"
2094 [(set (match_operand:BLK 0 "memory_operand" "")
2095 (match_operand:QI 2 "general_operand" ""))
2096 (use (match_operand:GPR 1 "general_operand" ""))
2097 (match_operand 3 "" "")]
2099 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2101 ; Clear a block that is up to 256 bytes in length.
2102 ; The block length is taken as (operands[1] % 256) + 1.
2104 (define_expand "clrmem_short"
2106 [(set (match_operand:BLK 0 "memory_operand" "")
2108 (use (match_operand 1 "nonmemory_operand" ""))
2109 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2110 (clobber (match_dup 2))
2111 (clobber (reg:CC CC_REGNUM))])]
2113 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2115 (define_insn "*clrmem_short"
2116 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2118 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2119 (use (match_operand 2 "immediate_operand" "X,R,X"))
2120 (clobber (match_scratch 3 "=X,X,&a"))
2121 (clobber (reg:CC CC_REGNUM))]
2122 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2123 && GET_MODE (operands[3]) == Pmode"
2125 [(set_attr "type" "cs")])
2128 [(set (match_operand:BLK 0 "memory_operand" "")
2130 (use (match_operand 1 "const_int_operand" ""))
2131 (use (match_operand 2 "immediate_operand" ""))
2133 (clobber (reg:CC CC_REGNUM))]
2136 [(set (match_dup 0) (const_int 0))
2138 (clobber (reg:CC CC_REGNUM))])]
2139 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2142 [(set (match_operand:BLK 0 "memory_operand" "")
2144 (use (match_operand 1 "register_operand" ""))
2145 (use (match_operand 2 "memory_operand" ""))
2147 (clobber (reg:CC CC_REGNUM))]
2150 [(unspec [(match_dup 1) (match_dup 2)
2151 (const_int 0)] UNSPEC_EXECUTE)
2152 (set (match_dup 0) (const_int 0))
2154 (clobber (reg:CC CC_REGNUM))])]
2158 [(set (match_operand:BLK 0 "memory_operand" "")
2160 (use (match_operand 1 "register_operand" ""))
2161 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2162 (clobber (match_operand 2 "register_operand" ""))
2163 (clobber (reg:CC CC_REGNUM))]
2164 "reload_completed && TARGET_CPU_ZARCH"
2165 [(set (match_dup 2) (label_ref (match_dup 3)))
2167 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2168 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2169 (set (match_dup 0) (const_int 0))
2171 (clobber (reg:CC CC_REGNUM))])]
2172 "operands[3] = gen_label_rtx ();")
2174 ; Initialize a block of arbitrary length with (operands[2] % 256).
2176 (define_expand "setmem_long"
2178 [(clobber (match_dup 1))
2179 (set (match_operand:BLK 0 "memory_operand" "")
2180 (match_operand 2 "shift_count_or_setmem_operand" ""))
2181 (use (match_operand 1 "general_operand" ""))
2183 (clobber (reg:CC CC_REGNUM))])]
2186 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2187 rtx reg0 = gen_reg_rtx (dword_mode);
2188 rtx reg1 = gen_reg_rtx (dword_mode);
2189 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2190 rtx len0 = gen_lowpart (Pmode, reg0);
2192 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2193 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2194 emit_move_insn (len0, operands[1]);
2196 emit_move_insn (reg1, const0_rtx);
2198 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2203 (define_insn "*setmem_long"
2204 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2205 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2206 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2208 (use (match_operand:<DBL> 1 "register_operand" "d"))
2209 (clobber (reg:CC CC_REGNUM))]
2211 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2212 [(set_attr "length" "8")
2213 (set_attr "type" "vs")])
2215 (define_insn "*setmem_long_and"
2216 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2217 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2218 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2219 (match_operand 4 "const_int_operand" "n")))
2221 (use (match_operand:<DBL> 1 "register_operand" "d"))
2222 (clobber (reg:CC CC_REGNUM))]
2223 "(INTVAL (operands[4]) & 255) == 255"
2224 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2225 [(set_attr "length" "8")
2226 (set_attr "type" "vs")])
2228 ; cmpmemM instruction pattern(s).
2231 (define_expand "cmpmemsi"
2232 [(set (match_operand:SI 0 "register_operand" "")
2233 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2234 (match_operand:BLK 2 "memory_operand" "") ) )
2235 (use (match_operand:SI 3 "general_operand" ""))
2236 (use (match_operand:SI 4 "" ""))]
2238 "s390_expand_cmpmem (operands[0], operands[1],
2239 operands[2], operands[3]); DONE;")
2241 ; Compare a block that is up to 256 bytes in length.
2242 ; The block length is taken as (operands[2] % 256) + 1.
2244 (define_expand "cmpmem_short"
2246 [(set (reg:CCU CC_REGNUM)
2247 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2248 (match_operand:BLK 1 "memory_operand" "")))
2249 (use (match_operand 2 "nonmemory_operand" ""))
2250 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2251 (clobber (match_dup 3))])]
2253 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2255 (define_insn "*cmpmem_short"
2256 [(set (reg:CCU CC_REGNUM)
2257 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2258 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2259 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2260 (use (match_operand 3 "immediate_operand" "X,R,X"))
2261 (clobber (match_scratch 4 "=X,X,&a"))]
2262 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2263 && GET_MODE (operands[4]) == Pmode"
2265 [(set_attr "type" "cs")])
2268 [(set (reg:CCU CC_REGNUM)
2269 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2270 (match_operand:BLK 1 "memory_operand" "")))
2271 (use (match_operand 2 "const_int_operand" ""))
2272 (use (match_operand 3 "immediate_operand" ""))
2273 (clobber (scratch))]
2276 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2277 (use (match_dup 2))])]
2278 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2281 [(set (reg:CCU CC_REGNUM)
2282 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2283 (match_operand:BLK 1 "memory_operand" "")))
2284 (use (match_operand 2 "register_operand" ""))
2285 (use (match_operand 3 "memory_operand" ""))
2286 (clobber (scratch))]
2289 [(unspec [(match_dup 2) (match_dup 3)
2290 (const_int 0)] UNSPEC_EXECUTE)
2291 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2292 (use (const_int 1))])]
2296 [(set (reg:CCU CC_REGNUM)
2297 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2298 (match_operand:BLK 1 "memory_operand" "")))
2299 (use (match_operand 2 "register_operand" ""))
2300 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2301 (clobber (match_operand 3 "register_operand" ""))]
2302 "reload_completed && TARGET_CPU_ZARCH"
2303 [(set (match_dup 3) (label_ref (match_dup 4)))
2305 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2306 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2307 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2308 (use (const_int 1))])]
2309 "operands[4] = gen_label_rtx ();")
2311 ; Compare a block of arbitrary length.
2313 (define_expand "cmpmem_long"
2315 [(clobber (match_dup 2))
2316 (clobber (match_dup 3))
2317 (set (reg:CCU CC_REGNUM)
2318 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2319 (match_operand:BLK 1 "memory_operand" "")))
2320 (use (match_operand 2 "general_operand" ""))
2321 (use (match_dup 3))])]
2324 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2325 rtx reg0 = gen_reg_rtx (dword_mode);
2326 rtx reg1 = gen_reg_rtx (dword_mode);
2327 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2328 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2329 rtx len0 = gen_lowpart (Pmode, reg0);
2330 rtx len1 = gen_lowpart (Pmode, reg1);
2332 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2333 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2334 emit_move_insn (len0, operands[2]);
2336 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2337 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2338 emit_move_insn (len1, operands[2]);
2340 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2341 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2346 (define_insn "*cmpmem_long"
2347 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2348 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2349 (set (reg:CCU CC_REGNUM)
2350 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2351 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2353 (use (match_dup 3))]
2355 "clcle\t%0,%1,0\;jo\t.-4"
2356 [(set_attr "length" "8")
2357 (set_attr "type" "vs")])
2359 ; Convert CCUmode condition code to integer.
2360 ; Result is zero if EQ, positive if LTU, negative if GTU.
2362 (define_insn_and_split "cmpint"
2363 [(set (match_operand:SI 0 "register_operand" "=d")
2364 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2366 (clobber (reg:CC CC_REGNUM))]
2370 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2372 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2373 (clobber (reg:CC CC_REGNUM))])])
2375 (define_insn_and_split "*cmpint_cc"
2376 [(set (reg CC_REGNUM)
2377 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2380 (set (match_operand:SI 0 "register_operand" "=d")
2381 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2382 "s390_match_ccmode (insn, CCSmode)"
2384 "&& reload_completed"
2385 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2387 [(set (match_dup 2) (match_dup 3))
2388 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2390 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2391 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2392 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2395 (define_insn_and_split "*cmpint_sign"
2396 [(set (match_operand:DI 0 "register_operand" "=d")
2397 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2399 (clobber (reg:CC CC_REGNUM))]
2402 "&& reload_completed"
2403 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2405 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2406 (clobber (reg:CC CC_REGNUM))])])
2408 (define_insn_and_split "*cmpint_sign_cc"
2409 [(set (reg CC_REGNUM)
2410 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2411 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2413 (const_int 32)) (const_int 32))
2415 (set (match_operand:DI 0 "register_operand" "=d")
2416 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2417 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2419 "&& reload_completed"
2420 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2422 [(set (match_dup 2) (match_dup 3))
2423 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2425 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2426 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2427 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2432 ;;- Conversion instructions.
2435 (define_insn "*sethighpartsi"
2436 [(set (match_operand:SI 0 "register_operand" "=d,d")
2437 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
2438 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2439 (clobber (reg:CC CC_REGNUM))]
2444 [(set_attr "op_type" "RS,RSY")])
2446 (define_insn "*sethighpartdi_64"
2447 [(set (match_operand:DI 0 "register_operand" "=d")
2448 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
2449 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
2450 (clobber (reg:CC CC_REGNUM))]
2453 [(set_attr "op_type" "RSY")])
2455 (define_insn "*sethighpartdi_31"
2456 [(set (match_operand:DI 0 "register_operand" "=d,d")
2457 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
2458 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2459 (clobber (reg:CC CC_REGNUM))]
2464 [(set_attr "op_type" "RS,RSY")])
2466 (define_insn_and_split "*extzv<mode>"
2467 [(set (match_operand:GPR 0 "register_operand" "=d")
2468 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2469 (match_operand 2 "const_int_operand" "n")
2471 (clobber (reg:CC CC_REGNUM))]
2472 "INTVAL (operands[2]) > 0
2473 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2475 "&& reload_completed"
2477 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2478 (clobber (reg:CC CC_REGNUM))])
2479 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
2481 int bitsize = INTVAL (operands[2]);
2482 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2483 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2485 operands[1] = adjust_address (operands[1], BLKmode, 0);
2486 set_mem_size (operands[1], GEN_INT (size));
2487 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2488 operands[3] = GEN_INT (mask);
2491 (define_insn_and_split "*extv<mode>"
2492 [(set (match_operand:GPR 0 "register_operand" "=d")
2493 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2494 (match_operand 2 "const_int_operand" "n")
2496 (clobber (reg:CC CC_REGNUM))]
2497 "INTVAL (operands[2]) > 0
2498 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2500 "&& reload_completed"
2502 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2503 (clobber (reg:CC CC_REGNUM))])
2505 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2506 (clobber (reg:CC CC_REGNUM))])]
2508 int bitsize = INTVAL (operands[2]);
2509 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2510 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2512 operands[1] = adjust_address (operands[1], BLKmode, 0);
2513 set_mem_size (operands[1], GEN_INT (size));
2514 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2515 operands[3] = GEN_INT (mask);
2519 ; insv instruction patterns
2522 (define_expand "insv"
2523 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2524 (match_operand 1 "const_int_operand" "")
2525 (match_operand 2 "const_int_operand" ""))
2526 (match_operand 3 "general_operand" ""))]
2529 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
2534 (define_insn "*insv<mode>_mem_reg"
2535 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
2536 (match_operand 1 "const_int_operand" "n,n")
2538 (match_operand:P 2 "register_operand" "d,d"))]
2539 "INTVAL (operands[1]) > 0
2540 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2541 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2543 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2545 operands[1] = GEN_INT ((1ul << size) - 1);
2546 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
2547 : "stcmy\t%2,%1,%S0";
2549 [(set_attr "op_type" "RS,RSY")])
2551 (define_insn "*insvdi_mem_reghigh"
2552 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
2553 (match_operand 1 "const_int_operand" "n")
2555 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
2558 && INTVAL (operands[1]) > 0
2559 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2560 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2562 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2564 operands[1] = GEN_INT ((1ul << size) - 1);
2565 return "stcmh\t%2,%1,%S0";
2567 [(set_attr "op_type" "RSY")])
2569 (define_insn "*insv<mode>_reg_imm"
2570 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2572 (match_operand 1 "const_int_operand" "n"))
2573 (match_operand:P 2 "const_int_operand" "n"))]
2575 && INTVAL (operands[1]) >= 0
2576 && INTVAL (operands[1]) < BITS_PER_WORD
2577 && INTVAL (operands[1]) % 16 == 0"
2579 switch (BITS_PER_WORD - INTVAL (operands[1]))
2581 case 64: return "iihh\t%0,%x2"; break;
2582 case 48: return "iihl\t%0,%x2"; break;
2583 case 32: return "iilh\t%0,%x2"; break;
2584 case 16: return "iill\t%0,%x2"; break;
2585 default: gcc_unreachable();
2588 [(set_attr "op_type" "RI")])
2590 (define_insn "*insv<mode>_reg_extimm"
2591 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2593 (match_operand 1 "const_int_operand" "n"))
2594 (match_operand:P 2 "const_int_operand" "n"))]
2596 && INTVAL (operands[1]) >= 0
2597 && INTVAL (operands[1]) < BITS_PER_WORD
2598 && INTVAL (operands[1]) % 32 == 0"
2600 switch (BITS_PER_WORD - INTVAL (operands[1]))
2602 case 64: return "iihf\t%0,%o2"; break;
2603 case 32: return "iilf\t%0,%o2"; break;
2604 default: gcc_unreachable();
2607 [(set_attr "op_type" "RIL")])
2610 ; extendsidi2 instruction pattern(s).
2613 (define_expand "extendsidi2"
2614 [(set (match_operand:DI 0 "register_operand" "")
2615 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2620 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2621 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2622 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2623 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2628 (define_insn "*extendsidi2"
2629 [(set (match_operand:DI 0 "register_operand" "=d,d")
2630 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2635 [(set_attr "op_type" "RRE,RXY")])
2638 ; extend(hi|qi)(si|di)2 instruction pattern(s).
2641 (define_expand "extend<HQI:mode><DSI:mode>2"
2642 [(set (match_operand:DSI 0 "register_operand" "")
2643 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2646 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
2648 rtx tmp = gen_reg_rtx (SImode);
2649 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
2650 emit_insn (gen_extendsidi2 (operands[0], tmp));
2653 else if (!TARGET_EXTIMM)
2655 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
2656 GET_MODE_BITSIZE (<HQI:MODE>mode));
2658 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
2659 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
2660 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
2666 ; extendhidi2 instruction pattern(s).
2669 (define_insn "*extendhidi2_extimm"
2670 [(set (match_operand:DI 0 "register_operand" "=d,d")
2671 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2672 "TARGET_64BIT && TARGET_EXTIMM"
2676 [(set_attr "op_type" "RRE,RXY")])
2678 (define_insn "*extendhidi2"
2679 [(set (match_operand:DI 0 "register_operand" "=d")
2680 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2683 [(set_attr "op_type" "RXY")])
2686 ; extendhisi2 instruction pattern(s).
2689 (define_insn "*extendhisi2_extimm"
2690 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2691 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2697 [(set_attr "op_type" "RRE,RX,RXY")])
2699 (define_insn "*extendhisi2"
2700 [(set (match_operand:SI 0 "register_operand" "=d,d")
2701 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2706 [(set_attr "op_type" "RX,RXY")])
2709 ; extendqi(si|di)2 instruction pattern(s).
2712 (define_insn "*extendqi<mode>2_extimm"
2713 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2714 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2719 [(set_attr "op_type" "RRE,RXY")])
2721 (define_insn "*extendqi<mode>2"
2722 [(set (match_operand:GPR 0 "register_operand" "=d")
2723 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
2724 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
2726 [(set_attr "op_type" "RXY")])
2728 (define_insn_and_split "*extendqi<mode>2_short_displ"
2729 [(set (match_operand:GPR 0 "register_operand" "=d")
2730 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
2731 (clobber (reg:CC CC_REGNUM))]
2732 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
2734 "&& reload_completed"
2736 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2737 (clobber (reg:CC CC_REGNUM))])
2739 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2740 (clobber (reg:CC CC_REGNUM))])]
2742 operands[1] = adjust_address (operands[1], BLKmode, 0);
2743 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2744 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
2745 - GET_MODE_BITSIZE (QImode));
2749 ; extendqihi2 instruction pattern(s).
2754 ; zero_extendsidi2 instruction pattern(s).
2757 (define_expand "zero_extendsidi2"
2758 [(set (match_operand:DI 0 "register_operand" "")
2759 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2764 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2765 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2766 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2771 (define_insn "*zero_extendsidi2"
2772 [(set (match_operand:DI 0 "register_operand" "=d,d")
2773 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2778 [(set_attr "op_type" "RRE,RXY")])
2781 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2784 (define_insn "*llgt_sidi"
2785 [(set (match_operand:DI 0 "register_operand" "=d")
2786 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2787 (const_int 2147483647)))]
2790 [(set_attr "op_type" "RXE")])
2792 (define_insn_and_split "*llgt_sidi_split"
2793 [(set (match_operand:DI 0 "register_operand" "=d")
2794 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2795 (const_int 2147483647)))
2796 (clobber (reg:CC CC_REGNUM))]
2799 "&& reload_completed"
2801 (and:DI (subreg:DI (match_dup 1) 0)
2802 (const_int 2147483647)))]
2805 (define_insn "*llgt_sisi"
2806 [(set (match_operand:SI 0 "register_operand" "=d,d")
2807 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2808 (const_int 2147483647)))]
2813 [(set_attr "op_type" "RRE,RXE")])
2815 (define_insn "*llgt_didi"
2816 [(set (match_operand:DI 0 "register_operand" "=d,d")
2817 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2818 (const_int 2147483647)))]
2823 [(set_attr "op_type" "RRE,RXE")])
2826 [(set (match_operand:GPR 0 "register_operand" "")
2827 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2828 (const_int 2147483647)))
2829 (clobber (reg:CC CC_REGNUM))]
2830 "TARGET_ZARCH && reload_completed"
2832 (and:GPR (match_dup 1)
2833 (const_int 2147483647)))]
2837 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
2840 (define_expand "zero_extend<mode>di2"
2841 [(set (match_operand:DI 0 "register_operand" "")
2842 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2847 rtx tmp = gen_reg_rtx (SImode);
2848 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2849 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2852 else if (!TARGET_EXTIMM)
2854 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2855 GET_MODE_BITSIZE(<MODE>mode));
2856 operands[1] = gen_lowpart (DImode, operands[1]);
2857 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2858 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2863 (define_expand "zero_extend<mode>si2"
2864 [(set (match_operand:SI 0 "register_operand" "")
2865 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2870 operands[1] = gen_lowpart (SImode, operands[1]);
2871 emit_insn (gen_andsi3 (operands[0], operands[1],
2872 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2877 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
2878 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2879 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2884 [(set_attr "op_type" "RRE,RXY")])
2886 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
2887 [(set (match_operand:GPR 0 "register_operand" "=d")
2888 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
2889 "TARGET_ZARCH && !TARGET_EXTIMM"
2891 [(set_attr "op_type" "RXY")])
2893 (define_insn_and_split "*zero_extendhisi2_31"
2894 [(set (match_operand:SI 0 "register_operand" "=&d")
2895 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2896 (clobber (reg:CC CC_REGNUM))]
2899 "&& reload_completed"
2900 [(set (match_dup 0) (const_int 0))
2902 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2903 (clobber (reg:CC CC_REGNUM))])]
2904 "operands[2] = gen_lowpart (HImode, operands[0]);")
2906 (define_insn_and_split "*zero_extendqisi2_31"
2907 [(set (match_operand:SI 0 "register_operand" "=&d")
2908 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2911 "&& reload_completed"
2912 [(set (match_dup 0) (const_int 0))
2913 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2914 "operands[2] = gen_lowpart (QImode, operands[0]);")
2917 ; zero_extendqihi2 instruction pattern(s).
2920 (define_expand "zero_extendqihi2"
2921 [(set (match_operand:HI 0 "register_operand" "")
2922 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2923 "TARGET_ZARCH && !TARGET_EXTIMM"
2925 operands[1] = gen_lowpart (HImode, operands[1]);
2926 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2930 (define_insn "*zero_extendqihi2_64"
2931 [(set (match_operand:HI 0 "register_operand" "=d")
2932 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2933 "TARGET_ZARCH && !TARGET_EXTIMM"
2935 [(set_attr "op_type" "RXY")])
2937 (define_insn_and_split "*zero_extendqihi2_31"
2938 [(set (match_operand:HI 0 "register_operand" "=&d")
2939 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2942 "&& reload_completed"
2943 [(set (match_dup 0) (const_int 0))
2944 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2945 "operands[2] = gen_lowpart (QImode, operands[0]);")
2949 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2952 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2953 [(set (match_operand:GPR 0 "register_operand" "")
2954 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2955 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2957 rtx label1 = gen_label_rtx ();
2958 rtx label2 = gen_label_rtx ();
2959 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2960 REAL_VALUE_TYPE cmp, sub;
2962 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2963 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2964 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2966 emit_insn (gen_cmp<FPR:mode> (operands[1],
2967 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2968 emit_jump_insn (gen_blt (label1));
2969 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2970 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2971 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2975 emit_label (label1);
2976 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2977 operands[1], GEN_INT(5)));
2978 emit_label (label2);
2982 (define_expand "fix_trunc<FPR:mode>di2"
2983 [(set (match_operand:DI 0 "register_operand" "")
2984 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2985 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2987 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2988 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2993 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2994 [(set (match_operand:GPR 0 "register_operand" "=d")
2995 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2996 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2997 (clobber (reg:CC CC_REGNUM))]
2998 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2999 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
3000 [(set_attr "op_type" "RRE")
3001 (set_attr "type" "ftoi")])
3004 ; fix_truncdfsi2 instruction pattern(s).
3007 (define_expand "fix_truncdfsi2"
3008 [(set (match_operand:SI 0 "register_operand" "")
3009 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
3012 if (TARGET_IBM_FLOAT)
3014 /* This is the algorithm from POP chapter A.5.7.2. */
3016 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3017 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
3018 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
3020 operands[1] = force_reg (DFmode, operands[1]);
3021 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
3022 two31r, two32, temp));
3026 operands[1] = force_reg (DFmode, operands[1]);
3027 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3033 (define_insn "fix_truncdfsi2_ibm"
3034 [(set (match_operand:SI 0 "register_operand" "=d")
3035 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
3036 (use (match_operand:DI 2 "immediate_operand" "m"))
3037 (use (match_operand:DI 3 "immediate_operand" "m"))
3038 (use (match_operand:BLK 4 "memory_operand" "m"))
3039 (clobber (reg:CC CC_REGNUM))]
3040 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3042 output_asm_insn ("sd\t%1,%2", operands);
3043 output_asm_insn ("aw\t%1,%3", operands);
3044 output_asm_insn ("std\t%1,%4", operands);
3045 output_asm_insn ("xi\t%N4,128", operands);
3048 [(set_attr "length" "20")])
3051 ; fix_truncsfsi2 instruction pattern(s).
3054 (define_expand "fix_truncsfsi2"
3055 [(set (match_operand:SI 0 "register_operand" "")
3056 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3059 if (TARGET_IBM_FLOAT)
3061 /* Convert to DFmode and then use the POP algorithm. */
3062 rtx temp = gen_reg_rtx (DFmode);
3063 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3064 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3068 operands[1] = force_reg (SFmode, operands[1]);
3069 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3076 ; floatdi(df|sf)2 instruction pattern(s).
3079 (define_insn "floatdi<mode>2"
3080 [(set (match_operand:FPR 0 "register_operand" "=f")
3081 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
3082 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3084 [(set_attr "op_type" "RRE")
3085 (set_attr "type" "itof" )])
3088 ; floatsidf2 instruction pattern(s).
3091 (define_expand "floatsidf2"
3092 [(set (match_operand:DF 0 "register_operand" "")
3093 (float:DF (match_operand:SI 1 "register_operand" "")))]
3096 if (TARGET_IBM_FLOAT)
3098 /* This is the algorithm from POP chapter A.5.7.1. */
3100 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3101 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3103 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3108 (define_insn "floatsidf2_ieee"
3109 [(set (match_operand:DF 0 "register_operand" "=f")
3110 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3111 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3113 [(set_attr "op_type" "RRE")
3114 (set_attr "type" "itof" )])
3116 (define_insn "floatsidf2_ibm"
3117 [(set (match_operand:DF 0 "register_operand" "=f")
3118 (float:DF (match_operand:SI 1 "register_operand" "d")))
3119 (use (match_operand:DI 2 "immediate_operand" "m"))
3120 (use (match_operand:BLK 3 "memory_operand" "m"))
3121 (clobber (reg:CC CC_REGNUM))]
3122 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3124 output_asm_insn ("st\t%1,%N3", operands);
3125 output_asm_insn ("xi\t%N3,128", operands);
3126 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3127 output_asm_insn ("ld\t%0,%3", operands);
3130 [(set_attr "length" "20")])
3133 ; floatsisf2 instruction pattern(s).
3136 (define_expand "floatsisf2"
3137 [(set (match_operand:SF 0 "register_operand" "")
3138 (float:SF (match_operand:SI 1 "register_operand" "")))]
3141 if (TARGET_IBM_FLOAT)
3143 /* Use the POP algorithm to convert to DFmode and then truncate. */
3144 rtx temp = gen_reg_rtx (DFmode);
3145 emit_insn (gen_floatsidf2 (temp, operands[1]));
3146 emit_insn (gen_truncdfsf2 (operands[0], temp));
3151 (define_insn "floatsisf2_ieee"
3152 [(set (match_operand:SF 0 "register_operand" "=f")
3153 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3154 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3156 [(set_attr "op_type" "RRE")
3157 (set_attr "type" "itof" )])
3160 ; truncdfsf2 instruction pattern(s).
3163 (define_expand "truncdfsf2"
3164 [(set (match_operand:SF 0 "register_operand" "")
3165 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3169 (define_insn "truncdfsf2_ieee"
3170 [(set (match_operand:SF 0 "register_operand" "=f")
3171 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3172 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3174 [(set_attr "op_type" "RRE")])
3176 (define_insn "truncdfsf2_ibm"
3177 [(set (match_operand:SF 0 "register_operand" "=f,f")
3178 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3179 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3183 [(set_attr "op_type" "RR,RX")
3184 (set_attr "type" "floadsf")])
3187 ; extendsfdf2 instruction pattern(s).
3190 (define_expand "extendsfdf2"
3191 [(set (match_operand:DF 0 "register_operand" "")
3192 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3195 if (TARGET_IBM_FLOAT)
3197 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3202 (define_insn "extendsfdf2_ieee"
3203 [(set (match_operand:DF 0 "register_operand" "=f,f")
3204 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3205 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3209 [(set_attr "op_type" "RRE,RXE")
3210 (set_attr "type" "floadsf")])
3212 (define_insn "extendsfdf2_ibm"
3213 [(set (match_operand:DF 0 "register_operand" "=f,f")
3214 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3215 (clobber (reg:CC CC_REGNUM))]
3216 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3218 sdr\t%0,%0\;ler\t%0,%1
3219 sdr\t%0,%0\;le\t%0,%1"
3220 [(set_attr "length" "4,6")
3221 (set_attr "type" "floadsf")])
3225 ;; ARITHMETIC OPERATIONS
3227 ; arithmetic operations set the ConditionCode,
3228 ; because of unpredictable Bits in Register for Halfword and Byte
3229 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3232 ;;- Add instructions.
3236 ; addti3 instruction pattern(s).
3239 (define_insn_and_split "addti3"
3240 [(set (match_operand:TI 0 "register_operand" "=&d")
3241 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3242 (match_operand:TI 2 "general_operand" "do") ) )
3243 (clobber (reg:CC CC_REGNUM))]
3246 "&& reload_completed"
3248 [(set (reg:CCL1 CC_REGNUM)
3249 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3251 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3253 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3254 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3255 (clobber (reg:CC CC_REGNUM))])]
3256 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3257 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3258 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3259 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3260 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3261 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3264 ; adddi3 instruction pattern(s).
3267 (define_insn "*adddi3_sign"
3268 [(set (match_operand:DI 0 "register_operand" "=d,d")
3269 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3270 (match_operand:DI 1 "register_operand" "0,0")))
3271 (clobber (reg:CC CC_REGNUM))]
3276 [(set_attr "op_type" "RRE,RXY")])
3278 (define_insn "*adddi3_zero_cc"
3279 [(set (reg CC_REGNUM)
3280 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3281 (match_operand:DI 1 "register_operand" "0,0"))
3283 (set (match_operand:DI 0 "register_operand" "=d,d")
3284 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3285 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3289 [(set_attr "op_type" "RRE,RXY")])
3291 (define_insn "*adddi3_zero_cconly"
3292 [(set (reg CC_REGNUM)
3293 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3294 (match_operand:DI 1 "register_operand" "0,0"))
3296 (clobber (match_scratch:DI 0 "=d,d"))]
3297 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3301 [(set_attr "op_type" "RRE,RXY")])
3303 (define_insn "*adddi3_zero"
3304 [(set (match_operand:DI 0 "register_operand" "=d,d")
3305 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3306 (match_operand:DI 1 "register_operand" "0,0")))
3307 (clobber (reg:CC CC_REGNUM))]
3312 [(set_attr "op_type" "RRE,RXY")])
3314 (define_insn "*adddi3_imm_cc"
3315 [(set (reg CC_REGNUM)
3316 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
3317 (match_operand:DI 2 "const_int_operand" "K,Os"))
3319 (set (match_operand:DI 0 "register_operand" "=d,d")
3320 (plus:DI (match_dup 1) (match_dup 2)))]
3322 && s390_match_ccmode (insn, CCAmode)
3323 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3324 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))"
3328 [(set_attr "op_type" "RI,RIL")])
3330 (define_insn "*adddi3_carry1_cc"
3331 [(set (reg CC_REGNUM)
3332 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3333 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3335 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3336 (plus:DI (match_dup 1) (match_dup 2)))]
3337 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3343 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3345 (define_insn "*adddi3_carry1_cconly"
3346 [(set (reg CC_REGNUM)
3347 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3348 (match_operand:DI 2 "general_operand" "d,m"))
3350 (clobber (match_scratch:DI 0 "=d,d"))]
3351 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3355 [(set_attr "op_type" "RRE,RXY")])
3357 (define_insn "*adddi3_carry2_cc"
3358 [(set (reg CC_REGNUM)
3359 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3360 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3362 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3363 (plus:DI (match_dup 1) (match_dup 2)))]
3364 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3370 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3372 (define_insn "*adddi3_carry2_cconly"
3373 [(set (reg CC_REGNUM)
3374 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3375 (match_operand:DI 2 "general_operand" "d,m"))
3377 (clobber (match_scratch:DI 0 "=d,d"))]
3378 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3382 [(set_attr "op_type" "RRE,RXY")])
3384 (define_insn "*adddi3_cc"
3385 [(set (reg CC_REGNUM)
3386 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3387 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3389 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3390 (plus:DI (match_dup 1) (match_dup 2)))]
3391 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3397 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3399 (define_insn "*adddi3_cconly"
3400 [(set (reg CC_REGNUM)
3401 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3402 (match_operand:DI 2 "general_operand" "d,m"))
3404 (clobber (match_scratch:DI 0 "=d,d"))]
3405 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3409 [(set_attr "op_type" "RRE,RXY")])
3411 (define_insn "*adddi3_cconly2"
3412 [(set (reg CC_REGNUM)
3413 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3414 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3415 (clobber (match_scratch:DI 0 "=d,d"))]
3416 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3420 [(set_attr "op_type" "RRE,RXY")])
3422 (define_insn "*adddi3_64"
3423 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
3424 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0")
3425 (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) )
3426 (clobber (reg:CC CC_REGNUM))]
3434 [(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")])
3436 (define_insn_and_split "*adddi3_31z"
3437 [(set (match_operand:DI 0 "register_operand" "=&d")
3438 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3439 (match_operand:DI 2 "general_operand" "do") ) )
3440 (clobber (reg:CC CC_REGNUM))]
3441 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3443 "&& reload_completed"
3445 [(set (reg:CCL1 CC_REGNUM)
3446 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3448 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3450 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3451 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3452 (clobber (reg:CC CC_REGNUM))])]
3453 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3454 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3455 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3456 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3457 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3458 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3460 (define_insn_and_split "*adddi3_31"
3461 [(set (match_operand:DI 0 "register_operand" "=&d")
3462 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3463 (match_operand:DI 2 "general_operand" "do") ) )
3464 (clobber (reg:CC CC_REGNUM))]
3467 "&& reload_completed"
3469 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3470 (clobber (reg:CC CC_REGNUM))])
3472 [(set (reg:CCL1 CC_REGNUM)
3473 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3475 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3477 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3479 (label_ref (match_dup 9))))
3481 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3482 (clobber (reg:CC CC_REGNUM))])
3484 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3485 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3486 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3487 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3488 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3489 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3490 operands[9] = gen_label_rtx ();")
3492 (define_expand "adddi3"
3494 [(set (match_operand:DI 0 "register_operand" "")
3495 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3496 (match_operand:DI 2 "general_operand" "")))
3497 (clobber (reg:CC CC_REGNUM))])]
3502 ; addsi3 instruction pattern(s).
3505 (define_insn "*addsi3_imm_cc"
3506 [(set (reg CC_REGNUM)
3507 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
3508 (match_operand:SI 2 "const_int_operand" "K,Os"))
3510 (set (match_operand:SI 0 "register_operand" "=d,d")
3511 (plus:SI (match_dup 1) (match_dup 2)))]
3512 "s390_match_ccmode (insn, CCAmode)
3513 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3514 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3515 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)"
3519 [(set_attr "op_type" "RI,RIL")])
3521 (define_insn "*addsi3_carry1_cc"
3522 [(set (reg CC_REGNUM)
3523 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3524 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3526 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3527 (plus:SI (match_dup 1) (match_dup 2)))]
3528 "s390_match_ccmode (insn, CCL1mode)"
3534 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3536 (define_insn "*addsi3_carry1_cconly"
3537 [(set (reg CC_REGNUM)
3538 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3539 (match_operand:SI 2 "general_operand" "d,R,T"))
3541 (clobber (match_scratch:SI 0 "=d,d,d"))]
3542 "s390_match_ccmode (insn, CCL1mode)"
3547 [(set_attr "op_type" "RR,RX,RXY")])
3549 (define_insn "*addsi3_carry2_cc"
3550 [(set (reg CC_REGNUM)
3551 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3552 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3554 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3555 (plus:SI (match_dup 1) (match_dup 2)))]
3556 "s390_match_ccmode (insn, CCL1mode)"
3562 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3564 (define_insn "*addsi3_carry2_cconly"
3565 [(set (reg CC_REGNUM)
3566 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3567 (match_operand:SI 2 "general_operand" "d,R,T"))
3569 (clobber (match_scratch:SI 0 "=d,d,d"))]
3570 "s390_match_ccmode (insn, CCL1mode)"
3575 [(set_attr "op_type" "RR,RX,RXY")])
3577 (define_insn "*addsi3_cc"
3578 [(set (reg CC_REGNUM)
3579 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3580 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3582 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3583 (plus:SI (match_dup 1) (match_dup 2)))]
3584 "s390_match_ccmode (insn, CCLmode)"
3590 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3592 (define_insn "*addsi3_cconly"
3593 [(set (reg CC_REGNUM)
3594 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3595 (match_operand:SI 2 "general_operand" "d,R,T"))
3597 (clobber (match_scratch:SI 0 "=d,d,d"))]
3598 "s390_match_ccmode (insn, CCLmode)"
3603 [(set_attr "op_type" "RR,RX,RXY")])
3605 (define_insn "*addsi3_cconly2"
3606 [(set (reg CC_REGNUM)
3607 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3608 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3609 (clobber (match_scratch:SI 0 "=d,d,d"))]
3610 "s390_match_ccmode (insn, CCLmode)"
3615 [(set_attr "op_type" "RR,RX,RXY")])
3617 (define_insn "*addsi3_sign"
3618 [(set (match_operand:SI 0 "register_operand" "=d,d")
3619 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3620 (match_operand:SI 1 "register_operand" "0,0")))
3621 (clobber (reg:CC CC_REGNUM))]
3626 [(set_attr "op_type" "RX,RXY")])
3628 (define_insn "addsi3"
3629 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
3630 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
3631 (match_operand:SI 2 "general_operand" "d,K,Os,R,T")))
3632 (clobber (reg:CC CC_REGNUM))]
3640 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
3643 ; add(df|sf)3 instruction pattern(s).
3646 (define_expand "add<mode>3"
3648 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3649 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3650 (match_operand:FPR 2 "general_operand" "f,R")))
3651 (clobber (reg:CC CC_REGNUM))])]
3655 (define_insn "*add<mode>3"
3656 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3657 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3658 (match_operand:FPR 2 "general_operand" "f,R")))
3659 (clobber (reg:CC CC_REGNUM))]
3660 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3664 [(set_attr "op_type" "RRE,RXE")
3665 (set_attr "type" "fsimp<mode>")])
3667 (define_insn "*add<mode>3_cc"
3668 [(set (reg CC_REGNUM)
3669 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3670 (match_operand:FPR 2 "general_operand" "f,R"))
3671 (match_operand:FPR 3 "const0_operand" "")))
3672 (set (match_operand:FPR 0 "register_operand" "=f,f")
3673 (plus:FPR (match_dup 1) (match_dup 2)))]
3674 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3678 [(set_attr "op_type" "RRE,RXE")
3679 (set_attr "type" "fsimp<mode>")])
3681 (define_insn "*add<mode>3_cconly"
3682 [(set (reg CC_REGNUM)
3683 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3684 (match_operand:FPR 2 "general_operand" "f,R"))
3685 (match_operand:FPR 3 "const0_operand" "")))
3686 (clobber (match_scratch:FPR 0 "=f,f"))]
3687 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3691 [(set_attr "op_type" "RRE,RXE")
3692 (set_attr "type" "fsimp<mode>")])
3694 (define_insn "*add<mode>3_ibm"
3695 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3696 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3697 (match_operand:FPR 2 "general_operand" "f,R")))
3698 (clobber (reg:CC CC_REGNUM))]
3699 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3703 [(set_attr "op_type" "RR,RX")
3704 (set_attr "type" "fsimp<mode>")])
3708 ;;- Subtract instructions.
3712 ; subti3 instruction pattern(s).
3715 (define_insn_and_split "subti3"
3716 [(set (match_operand:TI 0 "register_operand" "=&d")
3717 (minus:TI (match_operand:TI 1 "register_operand" "0")
3718 (match_operand:TI 2 "general_operand" "do") ) )
3719 (clobber (reg:CC CC_REGNUM))]
3722 "&& reload_completed"
3724 [(set (reg:CCL2 CC_REGNUM)
3725 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3727 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3729 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3730 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3731 (clobber (reg:CC CC_REGNUM))])]
3732 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3733 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3734 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3735 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3736 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3737 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3740 ; subdi3 instruction pattern(s).
3743 (define_insn "*subdi3_sign"
3744 [(set (match_operand:DI 0 "register_operand" "=d,d")
3745 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3746 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3747 (clobber (reg:CC CC_REGNUM))]
3752 [(set_attr "op_type" "RRE,RXY")])
3754 (define_insn "*subdi3_zero_cc"
3755 [(set (reg CC_REGNUM)
3756 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3757 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3759 (set (match_operand:DI 0 "register_operand" "=d,d")
3760 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3761 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3765 [(set_attr "op_type" "RRE,RXY")])
3767 (define_insn "*subdi3_zero_cconly"
3768 [(set (reg CC_REGNUM)
3769 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3770 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3772 (clobber (match_scratch:DI 0 "=d,d"))]
3773 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3777 [(set_attr "op_type" "RRE,RXY")])
3779 (define_insn "*subdi3_zero"
3780 [(set (match_operand:DI 0 "register_operand" "=d,d")
3781 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3782 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3783 (clobber (reg:CC CC_REGNUM))]
3788 [(set_attr "op_type" "RRE,RXY")])
3790 (define_insn "*subdi3_borrow_cc"
3791 [(set (reg CC_REGNUM)
3792 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3793 (match_operand:DI 2 "general_operand" "d,m"))
3795 (set (match_operand:DI 0 "register_operand" "=d,d")
3796 (minus:DI (match_dup 1) (match_dup 2)))]
3797 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3801 [(set_attr "op_type" "RRE,RXY")])
3803 (define_insn "*subdi3_borrow_cconly"
3804 [(set (reg CC_REGNUM)
3805 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3806 (match_operand:DI 2 "general_operand" "d,m"))
3808 (clobber (match_scratch:DI 0 "=d,d"))]
3809 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3813 [(set_attr "op_type" "RRE,RXY")])
3815 (define_insn "*subdi3_cc"
3816 [(set (reg CC_REGNUM)
3817 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3818 (match_operand:DI 2 "general_operand" "d,m"))
3820 (set (match_operand:DI 0 "register_operand" "=d,d")
3821 (minus:DI (match_dup 1) (match_dup 2)))]
3822 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3826 [(set_attr "op_type" "RRE,RXY")])
3828 (define_insn "*subdi3_cc2"
3829 [(set (reg CC_REGNUM)
3830 (compare (match_operand:DI 1 "register_operand" "0,0")
3831 (match_operand:DI 2 "general_operand" "d,m")))
3832 (set (match_operand:DI 0 "register_operand" "=d,d")
3833 (minus:DI (match_dup 1) (match_dup 2)))]
3834 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3838 [(set_attr "op_type" "RRE,RXY")])
3840 (define_insn "*subdi3_cconly"
3841 [(set (reg CC_REGNUM)
3842 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3843 (match_operand:DI 2 "general_operand" "d,m"))
3845 (clobber (match_scratch:DI 0 "=d,d"))]
3846 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3850 [(set_attr "op_type" "RRE,RXY")])
3852 (define_insn "*subdi3_cconly2"
3853 [(set (reg CC_REGNUM)
3854 (compare (match_operand:DI 1 "register_operand" "0,0")
3855 (match_operand:DI 2 "general_operand" "d,m")))
3856 (clobber (match_scratch:DI 0 "=d,d"))]
3857 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3861 [(set_attr "op_type" "RRE,RXY")])
3863 (define_insn "*subdi3_64"
3864 [(set (match_operand:DI 0 "register_operand" "=d,d")
3865 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3866 (match_operand:DI 2 "general_operand" "d,m") ) )
3867 (clobber (reg:CC CC_REGNUM))]
3872 [(set_attr "op_type" "RRE,RRE")])
3874 (define_insn_and_split "*subdi3_31z"
3875 [(set (match_operand:DI 0 "register_operand" "=&d")
3876 (minus:DI (match_operand:DI 1 "register_operand" "0")
3877 (match_operand:DI 2 "general_operand" "do") ) )
3878 (clobber (reg:CC CC_REGNUM))]
3879 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3881 "&& reload_completed"
3883 [(set (reg:CCL2 CC_REGNUM)
3884 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3886 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3888 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3889 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3890 (clobber (reg:CC CC_REGNUM))])]
3891 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3892 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3893 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3894 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3895 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3896 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3898 (define_insn_and_split "*subdi3_31"
3899 [(set (match_operand:DI 0 "register_operand" "=&d")
3900 (minus:DI (match_operand:DI 1 "register_operand" "0")
3901 (match_operand:DI 2 "general_operand" "do") ) )
3902 (clobber (reg:CC CC_REGNUM))]
3905 "&& reload_completed"
3907 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3908 (clobber (reg:CC CC_REGNUM))])
3910 [(set (reg:CCL2 CC_REGNUM)
3911 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3913 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3915 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3917 (label_ref (match_dup 9))))
3919 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3920 (clobber (reg:CC CC_REGNUM))])
3922 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3923 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3924 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3925 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3926 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3927 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3928 operands[9] = gen_label_rtx ();")
3930 (define_expand "subdi3"
3932 [(set (match_operand:DI 0 "register_operand" "")
3933 (minus:DI (match_operand:DI 1 "register_operand" "")
3934 (match_operand:DI 2 "general_operand" "")))
3935 (clobber (reg:CC CC_REGNUM))])]
3940 ; subsi3 instruction pattern(s).
3943 (define_insn "*subsi3_borrow_cc"
3944 [(set (reg CC_REGNUM)
3945 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3946 (match_operand:SI 2 "general_operand" "d,R,T"))
3948 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3949 (minus:SI (match_dup 1) (match_dup 2)))]
3950 "s390_match_ccmode (insn, CCL2mode)"
3955 [(set_attr "op_type" "RR,RX,RXY")])
3957 (define_insn "*subsi3_borrow_cconly"
3958 [(set (reg CC_REGNUM)
3959 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3960 (match_operand:SI 2 "general_operand" "d,R,T"))
3962 (clobber (match_scratch:SI 0 "=d,d,d"))]
3963 "s390_match_ccmode (insn, CCL2mode)"
3968 [(set_attr "op_type" "RR,RX,RXY")])
3970 (define_insn "*subsi3_cc"
3971 [(set (reg CC_REGNUM)
3972 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3973 (match_operand:SI 2 "general_operand" "d,R,T"))
3975 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3976 (minus:SI (match_dup 1) (match_dup 2)))]
3977 "s390_match_ccmode (insn, CCLmode)"
3982 [(set_attr "op_type" "RR,RX,RXY")])
3984 (define_insn "*subsi3_cc2"
3985 [(set (reg CC_REGNUM)
3986 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3987 (match_operand:SI 2 "general_operand" "d,R,T")))
3988 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3989 (minus:SI (match_dup 1) (match_dup 2)))]
3990 "s390_match_ccmode (insn, CCL3mode)"
3995 [(set_attr "op_type" "RR,RX,RXY")])
3997 (define_insn "*subsi3_cconly"
3998 [(set (reg CC_REGNUM)
3999 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4000 (match_operand:SI 2 "general_operand" "d,R,T"))
4002 (clobber (match_scratch:SI 0 "=d,d,d"))]
4003 "s390_match_ccmode (insn, CCLmode)"
4008 [(set_attr "op_type" "RR,RX,RXY")])
4010 (define_insn "*subsi3_cconly2"
4011 [(set (reg CC_REGNUM)
4012 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4013 (match_operand:SI 2 "general_operand" "d,R,T")))
4014 (clobber (match_scratch:SI 0 "=d,d,d"))]
4015 "s390_match_ccmode (insn, CCL3mode)"
4020 [(set_attr "op_type" "RR,RX,RXY")])
4022 (define_insn "*subsi3_sign"
4023 [(set (match_operand:SI 0 "register_operand" "=d,d")
4024 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4025 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4026 (clobber (reg:CC CC_REGNUM))]
4031 [(set_attr "op_type" "RX,RXY")])
4033 (define_insn "subsi3"
4034 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4035 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4036 (match_operand:SI 2 "general_operand" "d,R,T")))
4037 (clobber (reg:CC CC_REGNUM))]
4043 [(set_attr "op_type" "RR,RX,RXY")])
4047 ; sub(df|sf)3 instruction pattern(s).
4050 (define_expand "sub<mode>3"
4052 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4053 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4054 (match_operand:FPR 2 "general_operand" "f,R")))
4055 (clobber (reg:CC CC_REGNUM))])]
4059 (define_insn "*sub<mode>3"
4060 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4061 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4062 (match_operand:FPR 2 "general_operand" "f,R")))
4063 (clobber (reg:CC CC_REGNUM))]
4064 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4068 [(set_attr "op_type" "RRE,RXE")
4069 (set_attr "type" "fsimp<mode>")])
4071 (define_insn "*sub<mode>3_cc"
4072 [(set (reg CC_REGNUM)
4073 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4074 (match_operand:FPR 2 "general_operand" "f,R"))
4075 (match_operand:FPR 3 "const0_operand" "")))
4076 (set (match_operand:FPR 0 "register_operand" "=f,f")
4077 (minus:FPR (match_dup 1) (match_dup 2)))]
4078 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4082 [(set_attr "op_type" "RRE,RXE")
4083 (set_attr "type" "fsimp<mode>")])
4085 (define_insn "*sub<mode>3_cconly"
4086 [(set (reg CC_REGNUM)
4087 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4088 (match_operand:FPR 2 "general_operand" "f,R"))
4089 (match_operand:FPR 3 "const0_operand" "")))
4090 (clobber (match_scratch:FPR 0 "=f,f"))]
4091 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4095 [(set_attr "op_type" "RRE,RXE")
4096 (set_attr "type" "fsimp<mode>")])
4098 (define_insn "*sub<mode>3_ibm"
4099 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4100 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4101 (match_operand:FPR 2 "general_operand" "f,R")))
4102 (clobber (reg:CC CC_REGNUM))]
4103 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4107 [(set_attr "op_type" "RR,RX")
4108 (set_attr "type" "fsimp<mode>")])
4112 ;;- Conditional add/subtract instructions.
4116 ; add(di|si)cc instruction pattern(s).
4119 (define_insn "*add<mode>3_alc_cc"
4120 [(set (reg CC_REGNUM)
4122 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4123 (match_operand:GPR 2 "general_operand" "d,m"))
4124 (match_operand:GPR 3 "s390_alc_comparison" ""))
4126 (set (match_operand:GPR 0 "register_operand" "=d,d")
4127 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4128 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4132 [(set_attr "op_type" "RRE,RXY")])
4134 (define_insn "*add<mode>3_alc"
4135 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4136 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4137 (match_operand:GPR 2 "general_operand" "d,m"))
4138 (match_operand:GPR 3 "s390_alc_comparison" "")))
4139 (clobber (reg:CC CC_REGNUM))]
4144 [(set_attr "op_type" "RRE,RXY")])
4146 (define_insn "*sub<mode>3_slb_cc"
4147 [(set (reg CC_REGNUM)
4149 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4150 (match_operand:GPR 2 "general_operand" "d,m"))
4151 (match_operand:GPR 3 "s390_slb_comparison" ""))
4153 (set (match_operand:GPR 0 "register_operand" "=d,d")
4154 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4155 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4159 [(set_attr "op_type" "RRE,RXY")])
4161 (define_insn "*sub<mode>3_slb"
4162 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4163 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4164 (match_operand:GPR 2 "general_operand" "d,m"))
4165 (match_operand:GPR 3 "s390_slb_comparison" "")))
4166 (clobber (reg:CC CC_REGNUM))]
4171 [(set_attr "op_type" "RRE,RXY")])
4173 (define_expand "add<mode>cc"
4174 [(match_operand:GPR 0 "register_operand" "")
4175 (match_operand 1 "comparison_operator" "")
4176 (match_operand:GPR 2 "register_operand" "")
4177 (match_operand:GPR 3 "const_int_operand" "")]
4179 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4180 s390_compare_op0, s390_compare_op1,
4181 operands[0], operands[2],
4182 operands[3])) FAIL; DONE;")
4185 ; scond instruction pattern(s).
4188 (define_insn_and_split "*scond<mode>"
4189 [(set (match_operand:GPR 0 "register_operand" "=&d")
4190 (match_operand:GPR 1 "s390_alc_comparison" ""))
4191 (clobber (reg:CC CC_REGNUM))]
4194 "&& reload_completed"
4195 [(set (match_dup 0) (const_int 0))
4197 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4199 (clobber (reg:CC CC_REGNUM))])]
4202 (define_insn_and_split "*scond<mode>_neg"
4203 [(set (match_operand:GPR 0 "register_operand" "=&d")
4204 (match_operand:GPR 1 "s390_slb_comparison" ""))
4205 (clobber (reg:CC CC_REGNUM))]
4208 "&& reload_completed"
4209 [(set (match_dup 0) (const_int 0))
4211 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4213 (clobber (reg:CC CC_REGNUM))])
4215 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4216 (clobber (reg:CC CC_REGNUM))])]
4220 (define_expand "s<code>"
4221 [(set (match_operand:SI 0 "register_operand" "")
4222 (SCOND (match_dup 0)
4225 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4226 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4228 (define_expand "seq"
4230 [(set (match_operand:SI 0 "register_operand" "=d")
4232 (clobber (reg:CC CC_REGNUM))])
4234 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4235 (clobber (reg:CC CC_REGNUM))])]
4238 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4240 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4241 PUT_MODE (operands[1], SImode);
4244 (define_insn_and_split "*sne"
4245 [(set (match_operand:SI 0 "register_operand" "=d")
4246 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4248 (clobber (reg:CC CC_REGNUM))]
4253 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4254 (clobber (reg:CC CC_REGNUM))])])
4258 ;;- Multiply instructions.
4262 ; muldi3 instruction pattern(s).
4265 (define_insn "*muldi3_sign"
4266 [(set (match_operand:DI 0 "register_operand" "=d,d")
4267 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4268 (match_operand:DI 1 "register_operand" "0,0")))]
4273 [(set_attr "op_type" "RRE,RXY")
4274 (set_attr "type" "imuldi")])
4276 (define_insn "muldi3"
4277 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4278 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4279 (match_operand:DI 2 "general_operand" "d,K,m")))]
4285 [(set_attr "op_type" "RRE,RI,RXY")
4286 (set_attr "type" "imuldi")])
4289 ; mulsi3 instruction pattern(s).
4292 (define_insn "*mulsi3_sign"
4293 [(set (match_operand:SI 0 "register_operand" "=d")
4294 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4295 (match_operand:SI 1 "register_operand" "0")))]
4298 [(set_attr "op_type" "RX")
4299 (set_attr "type" "imulhi")])
4301 (define_insn "mulsi3"
4302 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4303 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4304 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4311 [(set_attr "op_type" "RRE,RI,RX,RXY")
4312 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4315 ; mulsidi3 instruction pattern(s).
4318 (define_insn "mulsidi3"
4319 [(set (match_operand:DI 0 "register_operand" "=d,d")
4320 (mult:DI (sign_extend:DI
4321 (match_operand:SI 1 "register_operand" "%0,0"))
4323 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4328 [(set_attr "op_type" "RR,RX")
4329 (set_attr "type" "imulsi")])
4332 ; umulsidi3 instruction pattern(s).
4335 (define_insn "umulsidi3"
4336 [(set (match_operand:DI 0 "register_operand" "=d,d")
4337 (mult:DI (zero_extend:DI
4338 (match_operand:SI 1 "register_operand" "%0,0"))
4340 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4341 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4345 [(set_attr "op_type" "RRE,RXY")
4346 (set_attr "type" "imulsi")])
4349 ; mul(df|sf)3 instruction pattern(s).
4352 (define_expand "mul<mode>3"
4353 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4354 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4355 (match_operand:FPR 2 "general_operand" "f,R")))]
4359 (define_insn "*mul<mode>3"
4360 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4361 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4362 (match_operand:FPR 2 "general_operand" "f,R")))]
4363 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4367 [(set_attr "op_type" "RRE,RXE")
4368 (set_attr "type" "fmul<mode>")])
4370 (define_insn "*mul<mode>3_ibm"
4371 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4372 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4373 (match_operand:FPR 2 "general_operand" "f,R")))]
4374 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4378 [(set_attr "op_type" "RR,RX")
4379 (set_attr "type" "fmul<mode>")])
4381 (define_insn "*fmadd<mode>"
4382 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4383 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4384 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4385 (match_operand:FPR 3 "register_operand" "0,0")))]
4386 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4390 [(set_attr "op_type" "RRE,RXE")
4391 (set_attr "type" "fmul<mode>")])
4393 (define_insn "*fmsub<mode>"
4394 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4395 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4396 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4397 (match_operand:FPR 3 "register_operand" "0,0")))]
4398 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4402 [(set_attr "op_type" "RRE,RXE")
4403 (set_attr "type" "fmul<mode>")])
4406 ;;- Divide and modulo instructions.
4410 ; divmoddi4 instruction pattern(s).
4413 (define_expand "divmoddi4"
4414 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4415 (div:DI (match_operand:DI 1 "register_operand" "")
4416 (match_operand:DI 2 "general_operand" "")))
4417 (set (match_operand:DI 3 "general_operand" "")
4418 (mod:DI (match_dup 1) (match_dup 2)))])
4419 (clobber (match_dup 4))]
4422 rtx insn, div_equal, mod_equal;
4424 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4425 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4427 operands[4] = gen_reg_rtx(TImode);
4428 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4430 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4432 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4434 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4436 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4441 (define_insn "divmodtidi3"
4442 [(set (match_operand:TI 0 "register_operand" "=d,d")
4446 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4447 (match_operand:DI 2 "general_operand" "d,m")))
4449 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4454 [(set_attr "op_type" "RRE,RXY")
4455 (set_attr "type" "idiv")])
4457 (define_insn "divmodtisi3"
4458 [(set (match_operand:TI 0 "register_operand" "=d,d")
4462 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4464 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4467 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4472 [(set_attr "op_type" "RRE,RXY")
4473 (set_attr "type" "idiv")])
4476 ; udivmoddi4 instruction pattern(s).
4479 (define_expand "udivmoddi4"
4480 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4481 (udiv:DI (match_operand:DI 1 "general_operand" "")
4482 (match_operand:DI 2 "nonimmediate_operand" "")))
4483 (set (match_operand:DI 3 "general_operand" "")
4484 (umod:DI (match_dup 1) (match_dup 2)))])
4485 (clobber (match_dup 4))]
4488 rtx insn, div_equal, mod_equal, equal;
4490 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4491 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4492 equal = gen_rtx_IOR (TImode,
4493 gen_rtx_ASHIFT (TImode,
4494 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4496 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4498 operands[4] = gen_reg_rtx(TImode);
4499 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4500 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4501 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4502 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4504 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4506 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4508 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4510 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4512 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4517 (define_insn "udivmodtidi3"
4518 [(set (match_operand:TI 0 "register_operand" "=d,d")
4523 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4525 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4529 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4534 [(set_attr "op_type" "RRE,RXY")
4535 (set_attr "type" "idiv")])
4538 ; divmodsi4 instruction pattern(s).
4541 (define_expand "divmodsi4"
4542 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4543 (div:SI (match_operand:SI 1 "general_operand" "")
4544 (match_operand:SI 2 "nonimmediate_operand" "")))
4545 (set (match_operand:SI 3 "general_operand" "")
4546 (mod:SI (match_dup 1) (match_dup 2)))])
4547 (clobber (match_dup 4))]
4550 rtx insn, div_equal, mod_equal, equal;
4552 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4553 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4554 equal = gen_rtx_IOR (DImode,
4555 gen_rtx_ASHIFT (DImode,
4556 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4558 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4560 operands[4] = gen_reg_rtx(DImode);
4561 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4562 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4564 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4566 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4568 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4570 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4572 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4577 (define_insn "divmoddisi3"
4578 [(set (match_operand:DI 0 "register_operand" "=d,d")
4583 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4585 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4589 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4594 [(set_attr "op_type" "RR,RX")
4595 (set_attr "type" "idiv")])
4598 ; udivsi3 and umodsi3 instruction pattern(s).
4601 (define_expand "udivmodsi4"
4602 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4603 (udiv:SI (match_operand:SI 1 "general_operand" "")
4604 (match_operand:SI 2 "nonimmediate_operand" "")))
4605 (set (match_operand:SI 3 "general_operand" "")
4606 (umod:SI (match_dup 1) (match_dup 2)))])
4607 (clobber (match_dup 4))]
4608 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4610 rtx insn, div_equal, mod_equal, equal;
4612 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4613 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4614 equal = gen_rtx_IOR (DImode,
4615 gen_rtx_ASHIFT (DImode,
4616 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4618 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4620 operands[4] = gen_reg_rtx(DImode);
4621 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4622 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4623 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4624 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4626 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4628 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4630 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4632 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4634 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4639 (define_insn "udivmoddisi3"
4640 [(set (match_operand:DI 0 "register_operand" "=d,d")
4645 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4647 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4651 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4652 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4656 [(set_attr "op_type" "RRE,RXY")
4657 (set_attr "type" "idiv")])
4659 (define_expand "udivsi3"
4660 [(set (match_operand:SI 0 "register_operand" "=d")
4661 (udiv:SI (match_operand:SI 1 "general_operand" "")
4662 (match_operand:SI 2 "general_operand" "")))
4663 (clobber (match_dup 3))]
4664 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4666 rtx insn, udiv_equal, umod_equal, equal;
4668 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4669 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4670 equal = gen_rtx_IOR (DImode,
4671 gen_rtx_ASHIFT (DImode,
4672 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4674 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4676 operands[3] = gen_reg_rtx (DImode);
4678 if (CONSTANT_P (operands[2]))
4680 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4682 rtx label1 = gen_label_rtx ();
4684 operands[1] = make_safe_from (operands[1], operands[0]);
4685 emit_move_insn (operands[0], const0_rtx);
4686 emit_insn (gen_cmpsi (operands[1], operands[2]));
4687 emit_jump_insn (gen_bltu (label1));
4688 emit_move_insn (operands[0], const1_rtx);
4689 emit_label (label1);
4693 operands[2] = force_reg (SImode, operands[2]);
4694 operands[2] = make_safe_from (operands[2], operands[0]);
4696 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4697 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4700 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4702 insn = emit_move_insn (operands[0],
4703 gen_lowpart (SImode, operands[3]));
4705 gen_rtx_EXPR_LIST (REG_EQUAL,
4706 udiv_equal, REG_NOTES (insn));
4711 rtx label1 = gen_label_rtx ();
4712 rtx label2 = gen_label_rtx ();
4713 rtx label3 = gen_label_rtx ();
4715 operands[1] = force_reg (SImode, operands[1]);
4716 operands[1] = make_safe_from (operands[1], operands[0]);
4717 operands[2] = force_reg (SImode, operands[2]);
4718 operands[2] = make_safe_from (operands[2], operands[0]);
4720 emit_move_insn (operands[0], const0_rtx);
4721 emit_insn (gen_cmpsi (operands[2], operands[1]));
4722 emit_jump_insn (gen_bgtu (label3));
4723 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4724 emit_jump_insn (gen_blt (label2));
4725 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4726 emit_jump_insn (gen_beq (label1));
4727 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4728 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4731 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4733 insn = emit_move_insn (operands[0],
4734 gen_lowpart (SImode, operands[3]));
4736 gen_rtx_EXPR_LIST (REG_EQUAL,
4737 udiv_equal, REG_NOTES (insn));
4739 emit_label (label1);
4740 emit_move_insn (operands[0], operands[1]);
4742 emit_label (label2);
4743 emit_move_insn (operands[0], const1_rtx);
4744 emit_label (label3);
4746 emit_move_insn (operands[0], operands[0]);
4750 (define_expand "umodsi3"
4751 [(set (match_operand:SI 0 "register_operand" "=d")
4752 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4753 (match_operand:SI 2 "nonimmediate_operand" "")))
4754 (clobber (match_dup 3))]
4755 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4757 rtx insn, udiv_equal, umod_equal, equal;
4759 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4760 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4761 equal = gen_rtx_IOR (DImode,
4762 gen_rtx_ASHIFT (DImode,
4763 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4765 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4767 operands[3] = gen_reg_rtx (DImode);
4769 if (CONSTANT_P (operands[2]))
4771 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4773 rtx label1 = gen_label_rtx ();
4775 operands[1] = make_safe_from (operands[1], operands[0]);
4776 emit_move_insn (operands[0], operands[1]);
4777 emit_insn (gen_cmpsi (operands[0], operands[2]));
4778 emit_jump_insn (gen_bltu (label1));
4779 emit_insn (gen_abssi2 (operands[0], operands[2]));
4780 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4781 emit_label (label1);
4785 operands[2] = force_reg (SImode, operands[2]);
4786 operands[2] = make_safe_from (operands[2], operands[0]);
4788 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4789 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4792 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4794 insn = emit_move_insn (operands[0],
4795 gen_highpart (SImode, operands[3]));
4797 gen_rtx_EXPR_LIST (REG_EQUAL,
4798 umod_equal, REG_NOTES (insn));
4803 rtx label1 = gen_label_rtx ();
4804 rtx label2 = gen_label_rtx ();
4805 rtx label3 = gen_label_rtx ();
4807 operands[1] = force_reg (SImode, operands[1]);
4808 operands[1] = make_safe_from (operands[1], operands[0]);
4809 operands[2] = force_reg (SImode, operands[2]);
4810 operands[2] = make_safe_from (operands[2], operands[0]);
4812 emit_move_insn(operands[0], operands[1]);
4813 emit_insn (gen_cmpsi (operands[2], operands[1]));
4814 emit_jump_insn (gen_bgtu (label3));
4815 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4816 emit_jump_insn (gen_blt (label2));
4817 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4818 emit_jump_insn (gen_beq (label1));
4819 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4820 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4823 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4825 insn = emit_move_insn (operands[0],
4826 gen_highpart (SImode, operands[3]));
4828 gen_rtx_EXPR_LIST (REG_EQUAL,
4829 umod_equal, REG_NOTES (insn));
4831 emit_label (label1);
4832 emit_move_insn (operands[0], const0_rtx);
4834 emit_label (label2);
4835 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4836 emit_label (label3);
4842 ; div(df|sf)3 instruction pattern(s).
4845 (define_expand "div<mode>3"
4846 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4847 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4848 (match_operand:FPR 2 "general_operand" "f,R")))]
4852 (define_insn "*div<mode>3"
4853 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4854 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4855 (match_operand:FPR 2 "general_operand" "f,R")))]
4856 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4860 [(set_attr "op_type" "RRE,RXE")
4861 (set_attr "type" "fdiv<mode>")])
4863 (define_insn "*div<mode>3_ibm"
4864 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4865 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4866 (match_operand:FPR 2 "general_operand" "f,R")))]
4867 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4871 [(set_attr "op_type" "RR,RX")
4872 (set_attr "type" "fdiv<mode>")])
4876 ;;- And instructions.
4879 (define_expand "and<mode>3"
4880 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4881 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4882 (match_operand:INT 2 "general_operand" "")))
4883 (clobber (reg:CC CC_REGNUM))]
4885 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4888 ; anddi3 instruction pattern(s).
4891 (define_insn "*anddi3_cc"
4892 [(set (reg CC_REGNUM)
4893 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4894 (match_operand:DI 2 "general_operand" "d,m"))
4896 (set (match_operand:DI 0 "register_operand" "=d,d")
4897 (and:DI (match_dup 1) (match_dup 2)))]
4898 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4902 [(set_attr "op_type" "RRE,RXY")])
4904 (define_insn "*anddi3_cconly"
4905 [(set (reg CC_REGNUM)
4906 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4907 (match_operand:DI 2 "general_operand" "d,m"))
4909 (clobber (match_scratch:DI 0 "=d,d"))]
4910 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4911 /* Do not steal TM patterns. */
4912 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4916 [(set_attr "op_type" "RRE,RXY")])
4918 (define_insn "*anddi3_extimm"
4919 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
4920 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4921 "%d,o,0,0,0,0,0,0,0,0,0,0")
4922 (match_operand:DI 2 "general_operand"
4923 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
4924 (clobber (reg:CC CC_REGNUM))]
4925 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
4939 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
4941 (define_insn "*anddi3"
4942 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4943 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4944 "%d,o,0,0,0,0,0,0,0,0")
4945 (match_operand:DI 2 "general_operand"
4946 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4947 (clobber (reg:CC CC_REGNUM))]
4948 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
4960 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4963 [(set (match_operand:DI 0 "s_operand" "")
4964 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4965 (clobber (reg:CC CC_REGNUM))]
4968 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4969 (clobber (reg:CC CC_REGNUM))])]
4970 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4974 ; andsi3 instruction pattern(s).
4977 (define_insn "*andsi3_cc"
4978 [(set (reg CC_REGNUM)
4979 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4980 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
4982 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4983 (and:SI (match_dup 1) (match_dup 2)))]
4984 "s390_match_ccmode(insn, CCTmode)"
4990 [(set_attr "op_type" "RIL,RR,RX,RXY")])
4992 (define_insn "*andsi3_cconly"
4993 [(set (reg CC_REGNUM)
4994 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4995 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
4997 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
4998 "s390_match_ccmode(insn, CCTmode)
4999 /* Do not steal TM patterns. */
5000 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5006 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5008 (define_insn "*andsi3_zarch"
5009 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5010 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5011 "%d,o,0,0,0,0,0,0,0,0")
5012 (match_operand:SI 2 "general_operand"
5013 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5014 (clobber (reg:CC CC_REGNUM))]
5015 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5027 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
5029 (define_insn "*andsi3_esa"
5030 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5031 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5032 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5033 (clobber (reg:CC CC_REGNUM))]
5034 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5040 [(set_attr "op_type" "RR,RX,SI,SS")])
5043 [(set (match_operand:SI 0 "s_operand" "")
5044 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5045 (clobber (reg:CC CC_REGNUM))]
5048 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5049 (clobber (reg:CC CC_REGNUM))])]
5050 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5053 ; andhi3 instruction pattern(s).
5056 (define_insn "*andhi3_zarch"
5057 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5058 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5059 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5060 (clobber (reg:CC CC_REGNUM))]
5061 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5067 [(set_attr "op_type" "RR,RI,SI,SS")])
5069 (define_insn "*andhi3_esa"
5070 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5071 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5072 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5073 (clobber (reg:CC CC_REGNUM))]
5074 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5079 [(set_attr "op_type" "RR,SI,SS")])
5082 [(set (match_operand:HI 0 "s_operand" "")
5083 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5084 (clobber (reg:CC CC_REGNUM))]
5087 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5088 (clobber (reg:CC CC_REGNUM))])]
5089 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5092 ; andqi3 instruction pattern(s).
5095 (define_insn "*andqi3_zarch"
5096 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5097 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5098 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5099 (clobber (reg:CC CC_REGNUM))]
5100 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5107 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5109 (define_insn "*andqi3_esa"
5110 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5111 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5112 (match_operand:QI 2 "general_operand" "d,n,Q")))
5113 (clobber (reg:CC CC_REGNUM))]
5114 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5119 [(set_attr "op_type" "RR,SI,SS")])
5122 ; Block and (NC) patterns.
5126 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5127 (and:BLK (match_dup 0)
5128 (match_operand:BLK 1 "memory_operand" "Q")))
5129 (use (match_operand 2 "const_int_operand" "n"))
5130 (clobber (reg:CC CC_REGNUM))]
5131 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5132 "nc\t%O0(%2,%R0),%S1"
5133 [(set_attr "op_type" "SS")])
5136 [(set (match_operand 0 "memory_operand" "")
5138 (match_operand 1 "memory_operand" "")))
5139 (clobber (reg:CC CC_REGNUM))]
5141 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5142 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5144 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5146 (clobber (reg:CC CC_REGNUM))])]
5148 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5149 operands[0] = adjust_address (operands[0], BLKmode, 0);
5150 operands[1] = adjust_address (operands[1], BLKmode, 0);
5155 [(set (match_operand:BLK 0 "memory_operand" "")
5156 (and:BLK (match_dup 0)
5157 (match_operand:BLK 1 "memory_operand" "")))
5158 (use (match_operand 2 "const_int_operand" ""))
5159 (clobber (reg:CC CC_REGNUM))])
5161 [(set (match_operand:BLK 3 "memory_operand" "")
5162 (and:BLK (match_dup 3)
5163 (match_operand:BLK 4 "memory_operand" "")))
5164 (use (match_operand 5 "const_int_operand" ""))
5165 (clobber (reg:CC CC_REGNUM))])]
5166 "s390_offset_p (operands[0], operands[3], operands[2])
5167 && s390_offset_p (operands[1], operands[4], operands[2])
5168 && !s390_overlap_p (operands[0], operands[1],
5169 INTVAL (operands[2]) + INTVAL (operands[5]))
5170 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5172 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5174 (clobber (reg:CC CC_REGNUM))])]
5175 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5176 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5177 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5181 ;;- Bit set (inclusive or) instructions.
5184 (define_expand "ior<mode>3"
5185 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5186 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5187 (match_operand:INT 2 "general_operand" "")))
5188 (clobber (reg:CC CC_REGNUM))]
5190 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5193 ; iordi3 instruction pattern(s).
5196 (define_insn "*iordi3_cc"
5197 [(set (reg CC_REGNUM)
5198 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5199 (match_operand:DI 2 "general_operand" "d,m"))
5201 (set (match_operand:DI 0 "register_operand" "=d,d")
5202 (ior:DI (match_dup 1) (match_dup 2)))]
5203 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5207 [(set_attr "op_type" "RRE,RXY")])
5209 (define_insn "*iordi3_cconly"
5210 [(set (reg CC_REGNUM)
5211 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5212 (match_operand:DI 2 "general_operand" "d,m"))
5214 (clobber (match_scratch:DI 0 "=d,d"))]
5215 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5219 [(set_attr "op_type" "RRE,RXY")])
5221 (define_insn "*iordi3_extimm"
5222 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5223 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5224 (match_operand:DI 2 "general_operand"
5225 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5226 (clobber (reg:CC CC_REGNUM))]
5227 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5239 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5241 (define_insn "*iordi3"
5242 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5243 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5244 (match_operand:DI 2 "general_operand"
5245 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5246 (clobber (reg:CC CC_REGNUM))]
5247 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5257 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5260 [(set (match_operand:DI 0 "s_operand" "")
5261 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5262 (clobber (reg:CC CC_REGNUM))]
5265 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5266 (clobber (reg:CC CC_REGNUM))])]
5267 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5270 ; iorsi3 instruction pattern(s).
5273 (define_insn "*iorsi3_cc"
5274 [(set (reg CC_REGNUM)
5275 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5276 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5278 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5279 (ior:SI (match_dup 1) (match_dup 2)))]
5280 "s390_match_ccmode(insn, CCTmode)"
5286 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5288 (define_insn "*iorsi3_cconly"
5289 [(set (reg CC_REGNUM)
5290 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5291 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5293 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5294 "s390_match_ccmode(insn, CCTmode)"
5300 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5302 (define_insn "*iorsi3_zarch"
5303 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5304 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5305 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5306 (clobber (reg:CC CC_REGNUM))]
5307 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5317 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5319 (define_insn "*iorsi3_esa"
5320 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5321 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5322 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5323 (clobber (reg:CC CC_REGNUM))]
5324 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5330 [(set_attr "op_type" "RR,RX,SI,SS")])
5333 [(set (match_operand:SI 0 "s_operand" "")
5334 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5335 (clobber (reg:CC CC_REGNUM))]
5338 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5339 (clobber (reg:CC CC_REGNUM))])]
5340 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5343 ; iorhi3 instruction pattern(s).
5346 (define_insn "*iorhi3_zarch"
5347 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5348 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5349 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5350 (clobber (reg:CC CC_REGNUM))]
5351 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5357 [(set_attr "op_type" "RR,RI,SI,SS")])
5359 (define_insn "*iorhi3_esa"
5360 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5361 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5362 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5363 (clobber (reg:CC CC_REGNUM))]
5364 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5369 [(set_attr "op_type" "RR,SI,SS")])
5372 [(set (match_operand:HI 0 "s_operand" "")
5373 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5374 (clobber (reg:CC CC_REGNUM))]
5377 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5378 (clobber (reg:CC CC_REGNUM))])]
5379 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5382 ; iorqi3 instruction pattern(s).
5385 (define_insn "*iorqi3_zarch"
5386 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5387 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5388 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5389 (clobber (reg:CC CC_REGNUM))]
5390 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5397 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5399 (define_insn "*iorqi3_esa"
5400 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5401 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5402 (match_operand:QI 2 "general_operand" "d,n,Q")))
5403 (clobber (reg:CC CC_REGNUM))]
5404 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5409 [(set_attr "op_type" "RR,SI,SS")])
5412 ; Block inclusive or (OC) patterns.
5416 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5417 (ior:BLK (match_dup 0)
5418 (match_operand:BLK 1 "memory_operand" "Q")))
5419 (use (match_operand 2 "const_int_operand" "n"))
5420 (clobber (reg:CC CC_REGNUM))]
5421 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5422 "oc\t%O0(%2,%R0),%S1"
5423 [(set_attr "op_type" "SS")])
5426 [(set (match_operand 0 "memory_operand" "")
5428 (match_operand 1 "memory_operand" "")))
5429 (clobber (reg:CC CC_REGNUM))]
5431 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5432 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5434 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5436 (clobber (reg:CC CC_REGNUM))])]
5438 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5439 operands[0] = adjust_address (operands[0], BLKmode, 0);
5440 operands[1] = adjust_address (operands[1], BLKmode, 0);
5445 [(set (match_operand:BLK 0 "memory_operand" "")
5446 (ior:BLK (match_dup 0)
5447 (match_operand:BLK 1 "memory_operand" "")))
5448 (use (match_operand 2 "const_int_operand" ""))
5449 (clobber (reg:CC CC_REGNUM))])
5451 [(set (match_operand:BLK 3 "memory_operand" "")
5452 (ior:BLK (match_dup 3)
5453 (match_operand:BLK 4 "memory_operand" "")))
5454 (use (match_operand 5 "const_int_operand" ""))
5455 (clobber (reg:CC CC_REGNUM))])]
5456 "s390_offset_p (operands[0], operands[3], operands[2])
5457 && s390_offset_p (operands[1], operands[4], operands[2])
5458 && !s390_overlap_p (operands[0], operands[1],
5459 INTVAL (operands[2]) + INTVAL (operands[5]))
5460 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5462 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5464 (clobber (reg:CC CC_REGNUM))])]
5465 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5466 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5467 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5471 ;;- Xor instructions.
5474 (define_expand "xor<mode>3"
5475 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5476 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5477 (match_operand:INT 2 "general_operand" "")))
5478 (clobber (reg:CC CC_REGNUM))]
5480 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5483 ; xordi3 instruction pattern(s).
5486 (define_insn "*xordi3_cc"
5487 [(set (reg CC_REGNUM)
5488 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5489 (match_operand:DI 2 "general_operand" "d,m"))
5491 (set (match_operand:DI 0 "register_operand" "=d,d")
5492 (xor:DI (match_dup 1) (match_dup 2)))]
5493 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5497 [(set_attr "op_type" "RRE,RXY")])
5499 (define_insn "*xordi3_cconly"
5500 [(set (reg CC_REGNUM)
5501 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5502 (match_operand:DI 2 "general_operand" "d,m"))
5504 (clobber (match_scratch:DI 0 "=d,d"))]
5505 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5509 [(set_attr "op_type" "RRE,RXY")])
5511 (define_insn "*xordi3_extimm"
5512 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5513 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5514 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5515 (clobber (reg:CC CC_REGNUM))]
5516 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5524 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5526 (define_insn "*xordi3"
5527 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5528 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5529 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5530 (clobber (reg:CC CC_REGNUM))]
5531 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5537 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5540 [(set (match_operand:DI 0 "s_operand" "")
5541 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5542 (clobber (reg:CC CC_REGNUM))]
5545 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5546 (clobber (reg:CC CC_REGNUM))])]
5547 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5550 ; xorsi3 instruction pattern(s).
5553 (define_insn "*xorsi3_cc"
5554 [(set (reg CC_REGNUM)
5555 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5556 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5558 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5559 (xor:SI (match_dup 1) (match_dup 2)))]
5560 "s390_match_ccmode(insn, CCTmode)"
5566 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5568 (define_insn "*xorsi3_cconly"
5569 [(set (reg CC_REGNUM)
5570 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5571 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5573 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5574 "s390_match_ccmode(insn, CCTmode)"
5580 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5582 (define_insn "*xorsi3"
5583 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5584 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5585 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5586 (clobber (reg:CC CC_REGNUM))]
5587 "s390_logical_operator_ok_p (operands)"
5595 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5598 [(set (match_operand:SI 0 "s_operand" "")
5599 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5600 (clobber (reg:CC CC_REGNUM))]
5603 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5604 (clobber (reg:CC CC_REGNUM))])]
5605 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5608 ; xorhi3 instruction pattern(s).
5611 (define_insn "*xorhi3"
5612 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5613 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5614 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5615 (clobber (reg:CC CC_REGNUM))]
5616 "s390_logical_operator_ok_p (operands)"
5622 [(set_attr "op_type" "RIL,RR,SI,SS")])
5625 [(set (match_operand:HI 0 "s_operand" "")
5626 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5627 (clobber (reg:CC CC_REGNUM))]
5630 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5631 (clobber (reg:CC CC_REGNUM))])]
5632 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5635 ; xorqi3 instruction pattern(s).
5638 (define_insn "*xorqi3"
5639 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5640 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5641 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5642 (clobber (reg:CC CC_REGNUM))]
5643 "s390_logical_operator_ok_p (operands)"
5650 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5653 ; Block exclusive or (XC) patterns.
5657 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5658 (xor:BLK (match_dup 0)
5659 (match_operand:BLK 1 "memory_operand" "Q")))
5660 (use (match_operand 2 "const_int_operand" "n"))
5661 (clobber (reg:CC CC_REGNUM))]
5662 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5663 "xc\t%O0(%2,%R0),%S1"
5664 [(set_attr "op_type" "SS")])
5667 [(set (match_operand 0 "memory_operand" "")
5669 (match_operand 1 "memory_operand" "")))
5670 (clobber (reg:CC CC_REGNUM))]
5672 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5673 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5675 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5677 (clobber (reg:CC CC_REGNUM))])]
5679 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5680 operands[0] = adjust_address (operands[0], BLKmode, 0);
5681 operands[1] = adjust_address (operands[1], BLKmode, 0);
5686 [(set (match_operand:BLK 0 "memory_operand" "")
5687 (xor:BLK (match_dup 0)
5688 (match_operand:BLK 1 "memory_operand" "")))
5689 (use (match_operand 2 "const_int_operand" ""))
5690 (clobber (reg:CC CC_REGNUM))])
5692 [(set (match_operand:BLK 3 "memory_operand" "")
5693 (xor:BLK (match_dup 3)
5694 (match_operand:BLK 4 "memory_operand" "")))
5695 (use (match_operand 5 "const_int_operand" ""))
5696 (clobber (reg:CC CC_REGNUM))])]
5697 "s390_offset_p (operands[0], operands[3], operands[2])
5698 && s390_offset_p (operands[1], operands[4], operands[2])
5699 && !s390_overlap_p (operands[0], operands[1],
5700 INTVAL (operands[2]) + INTVAL (operands[5]))
5701 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5703 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5705 (clobber (reg:CC CC_REGNUM))])]
5706 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5707 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5708 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5711 ; Block xor (XC) patterns with src == dest.
5714 (define_insn "*xc_zero"
5715 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5717 (use (match_operand 1 "const_int_operand" "n"))
5718 (clobber (reg:CC CC_REGNUM))]
5719 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5720 "xc\t%O0(%1,%R0),%S0"
5721 [(set_attr "op_type" "SS")])
5725 [(set (match_operand:BLK 0 "memory_operand" "")
5727 (use (match_operand 1 "const_int_operand" ""))
5728 (clobber (reg:CC CC_REGNUM))])
5730 [(set (match_operand:BLK 2 "memory_operand" "")
5732 (use (match_operand 3 "const_int_operand" ""))
5733 (clobber (reg:CC CC_REGNUM))])]
5734 "s390_offset_p (operands[0], operands[2], operands[1])
5735 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5737 [(set (match_dup 4) (const_int 0))
5739 (clobber (reg:CC CC_REGNUM))])]
5740 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5741 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5745 ;;- Negate instructions.
5749 ; neg(di|si)2 instruction pattern(s).
5752 (define_expand "neg<mode>2"
5754 [(set (match_operand:DSI 0 "register_operand" "=d")
5755 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5756 (clobber (reg:CC CC_REGNUM))])]
5760 (define_insn "*negdi2_sign_cc"
5761 [(set (reg CC_REGNUM)
5762 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5763 (match_operand:SI 1 "register_operand" "d") 0)
5764 (const_int 32)) (const_int 32)))
5766 (set (match_operand:DI 0 "register_operand" "=d")
5767 (neg:DI (sign_extend:DI (match_dup 1))))]
5768 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5770 [(set_attr "op_type" "RRE")])
5772 (define_insn "*negdi2_sign"
5773 [(set (match_operand:DI 0 "register_operand" "=d")
5774 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5775 (clobber (reg:CC CC_REGNUM))]
5778 [(set_attr "op_type" "RRE")])
5780 (define_insn "*neg<mode>2_cc"
5781 [(set (reg CC_REGNUM)
5782 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5784 (set (match_operand:GPR 0 "register_operand" "=d")
5785 (neg:GPR (match_dup 1)))]
5786 "s390_match_ccmode (insn, CCAmode)"
5788 [(set_attr "op_type" "RR<E>")])
5790 (define_insn "*neg<mode>2_cconly"
5791 [(set (reg CC_REGNUM)
5792 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5794 (clobber (match_scratch:GPR 0 "=d"))]
5795 "s390_match_ccmode (insn, CCAmode)"
5797 [(set_attr "op_type" "RR<E>")])
5799 (define_insn "*neg<mode>2"
5800 [(set (match_operand:GPR 0 "register_operand" "=d")
5801 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5802 (clobber (reg:CC CC_REGNUM))]
5805 [(set_attr "op_type" "RR<E>")])
5807 (define_insn_and_split "*negdi2_31"
5808 [(set (match_operand:DI 0 "register_operand" "=d")
5809 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5810 (clobber (reg:CC CC_REGNUM))]
5813 "&& reload_completed"
5815 [(set (match_dup 2) (neg:SI (match_dup 3)))
5816 (clobber (reg:CC CC_REGNUM))])
5818 [(set (reg:CCAP CC_REGNUM)
5819 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5820 (set (match_dup 4) (neg:SI (match_dup 5)))])
5822 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5824 (label_ref (match_dup 6))))
5826 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5827 (clobber (reg:CC CC_REGNUM))])
5829 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5830 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5831 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5832 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5833 operands[6] = gen_label_rtx ();")
5836 ; neg(df|sf)2 instruction pattern(s).
5839 (define_expand "neg<mode>2"
5841 [(set (match_operand:FPR 0 "register_operand" "=f")
5842 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5843 (clobber (reg:CC CC_REGNUM))])]
5847 (define_insn "*neg<mode>2_cc"
5848 [(set (reg CC_REGNUM)
5849 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5850 (match_operand:FPR 2 "const0_operand" "")))
5851 (set (match_operand:FPR 0 "register_operand" "=f")
5852 (neg:FPR (match_dup 1)))]
5853 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5855 [(set_attr "op_type" "RRE")
5856 (set_attr "type" "fsimp<mode>")])
5858 (define_insn "*neg<mode>2_cconly"
5859 [(set (reg CC_REGNUM)
5860 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5861 (match_operand:FPR 2 "const0_operand" "")))
5862 (clobber (match_scratch:FPR 0 "=f"))]
5863 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5865 [(set_attr "op_type" "RRE")
5866 (set_attr "type" "fsimp<mode>")])
5868 (define_insn "*neg<mode>2"
5869 [(set (match_operand:FPR 0 "register_operand" "=f")
5870 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5871 (clobber (reg:CC CC_REGNUM))]
5872 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5874 [(set_attr "op_type" "RRE")
5875 (set_attr "type" "fsimp<mode>")])
5877 (define_insn "*neg<mode>2_ibm"
5878 [(set (match_operand:FPR 0 "register_operand" "=f")
5879 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5880 (clobber (reg:CC CC_REGNUM))]
5881 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5883 [(set_attr "op_type" "RR")
5884 (set_attr "type" "fsimp<mode>")])
5888 ;;- Absolute value instructions.
5892 ; abs(di|si)2 instruction pattern(s).
5895 (define_insn "*absdi2_sign_cc"
5896 [(set (reg CC_REGNUM)
5897 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5898 (match_operand:SI 1 "register_operand" "d") 0)
5899 (const_int 32)) (const_int 32)))
5901 (set (match_operand:DI 0 "register_operand" "=d")
5902 (abs:DI (sign_extend:DI (match_dup 1))))]
5903 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5905 [(set_attr "op_type" "RRE")])
5907 (define_insn "*absdi2_sign"
5908 [(set (match_operand:DI 0 "register_operand" "=d")
5909 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5910 (clobber (reg:CC CC_REGNUM))]
5913 [(set_attr "op_type" "RRE")])
5915 (define_insn "*abs<mode>2_cc"
5916 [(set (reg CC_REGNUM)
5917 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5919 (set (match_operand:GPR 0 "register_operand" "=d")
5920 (abs:GPR (match_dup 1)))]
5921 "s390_match_ccmode (insn, CCAmode)"
5923 [(set_attr "op_type" "RR<E>")])
5925 (define_insn "*abs<mode>2_cconly"
5926 [(set (reg CC_REGNUM)
5927 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5929 (clobber (match_scratch:GPR 0 "=d"))]
5930 "s390_match_ccmode (insn, CCAmode)"
5932 [(set_attr "op_type" "RR<E>")])
5934 (define_insn "abs<mode>2"
5935 [(set (match_operand:GPR 0 "register_operand" "=d")
5936 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5937 (clobber (reg:CC CC_REGNUM))]
5940 [(set_attr "op_type" "RR<E>")])
5943 ; abs(df|sf)2 instruction pattern(s).
5946 (define_expand "abs<mode>2"
5948 [(set (match_operand:FPR 0 "register_operand" "=f")
5949 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5950 (clobber (reg:CC CC_REGNUM))])]
5954 (define_insn "*abs<mode>2_cc"
5955 [(set (reg CC_REGNUM)
5956 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5957 (match_operand:FPR 2 "const0_operand" "")))
5958 (set (match_operand:FPR 0 "register_operand" "=f")
5959 (abs:FPR (match_dup 1)))]
5960 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5962 [(set_attr "op_type" "RRE")
5963 (set_attr "type" "fsimp<mode>")])
5965 (define_insn "*abs<mode>2_cconly"
5966 [(set (reg CC_REGNUM)
5967 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5968 (match_operand:FPR 2 "const0_operand" "")))
5969 (clobber (match_scratch:FPR 0 "=f"))]
5970 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5972 [(set_attr "op_type" "RRE")
5973 (set_attr "type" "fsimp<mode>")])
5975 (define_insn "*abs<mode>2"
5976 [(set (match_operand:FPR 0 "register_operand" "=f")
5977 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5978 (clobber (reg:CC CC_REGNUM))]
5979 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5981 [(set_attr "op_type" "RRE")
5982 (set_attr "type" "fsimp<mode>")])
5984 (define_insn "*abs<mode>2_ibm"
5985 [(set (match_operand:FPR 0 "register_operand" "=f")
5986 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5987 (clobber (reg:CC CC_REGNUM))]
5988 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5990 [(set_attr "op_type" "RR")
5991 (set_attr "type" "fsimp<mode>")])
5994 ;;- Negated absolute value instructions
6001 (define_insn "*negabsdi2_sign_cc"
6002 [(set (reg CC_REGNUM)
6003 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6004 (match_operand:SI 1 "register_operand" "d") 0)
6005 (const_int 32)) (const_int 32))))
6007 (set (match_operand:DI 0 "register_operand" "=d")
6008 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6009 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6011 [(set_attr "op_type" "RRE")])
6013 (define_insn "*negabsdi2_sign"
6014 [(set (match_operand:DI 0 "register_operand" "=d")
6015 (neg:DI (abs:DI (sign_extend:DI
6016 (match_operand:SI 1 "register_operand" "d")))))
6017 (clobber (reg:CC CC_REGNUM))]
6020 [(set_attr "op_type" "RRE")])
6022 (define_insn "*negabs<mode>2_cc"
6023 [(set (reg CC_REGNUM)
6024 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6026 (set (match_operand:GPR 0 "register_operand" "=d")
6027 (neg:GPR (abs:GPR (match_dup 1))))]
6028 "s390_match_ccmode (insn, CCAmode)"
6030 [(set_attr "op_type" "RR<E>")])
6032 (define_insn "*negabs<mode>2_cconly"
6033 [(set (reg CC_REGNUM)
6034 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6036 (clobber (match_scratch:GPR 0 "=d"))]
6037 "s390_match_ccmode (insn, CCAmode)"
6039 [(set_attr "op_type" "RR<E>")])
6041 (define_insn "*negabs<mode>2"
6042 [(set (match_operand:GPR 0 "register_operand" "=d")
6043 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6044 (clobber (reg:CC CC_REGNUM))]
6047 [(set_attr "op_type" "RR<E>")])
6053 (define_insn "*negabs<mode>2_cc"
6054 [(set (reg CC_REGNUM)
6055 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6056 (match_operand:FPR 2 "const0_operand" "")))
6057 (set (match_operand:FPR 0 "register_operand" "=f")
6058 (neg:FPR (abs:FPR (match_dup 1))))]
6059 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6061 [(set_attr "op_type" "RRE")
6062 (set_attr "type" "fsimp<mode>")])
6064 (define_insn "*negabs<mode>2_cconly"
6065 [(set (reg CC_REGNUM)
6066 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6067 (match_operand:FPR 2 "const0_operand" "")))
6068 (clobber (match_scratch:FPR 0 "=f"))]
6069 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6071 [(set_attr "op_type" "RRE")
6072 (set_attr "type" "fsimp<mode>")])
6074 (define_insn "*negabs<mode>2"
6075 [(set (match_operand:FPR 0 "register_operand" "=f")
6076 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
6077 (clobber (reg:CC CC_REGNUM))]
6078 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6080 [(set_attr "op_type" "RRE")
6081 (set_attr "type" "fsimp<mode>")])
6084 ;;- Square root instructions.
6088 ; sqrt(df|sf)2 instruction pattern(s).
6091 (define_insn "sqrt<mode>2"
6092 [(set (match_operand:FPR 0 "register_operand" "=f,f")
6093 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
6094 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6098 [(set_attr "op_type" "RRE,RXE")
6099 (set_attr "type" "fsqrt<mode>")])
6103 ;;- One complement instructions.
6107 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6110 (define_expand "one_cmpl<mode>2"
6112 [(set (match_operand:INT 0 "register_operand" "")
6113 (xor:INT (match_operand:INT 1 "register_operand" "")
6115 (clobber (reg:CC CC_REGNUM))])]
6121 ;; Find leftmost bit instructions.
6124 (define_expand "clzdi2"
6125 [(set (match_operand:DI 0 "register_operand" "=d")
6126 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6127 "TARGET_EXTIMM && TARGET_64BIT"
6129 rtx insn, clz_equal;
6130 rtx wide_reg = gen_reg_rtx (TImode);
6131 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6133 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6135 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6137 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6139 gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
6144 (define_insn "clztidi2"
6145 [(set (match_operand:TI 0 "register_operand" "=d")
6149 (xor:DI (match_operand:DI 1 "register_operand" "d")
6150 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6151 (subreg:SI (clz:DI (match_dup 1)) 4))))
6154 (zero_extend:TI (clz:DI (match_dup 1)))))
6155 (clobber (reg:CC CC_REGNUM))]
6156 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6157 == (unsigned HOST_WIDE_INT) 1 << 63
6158 && TARGET_EXTIMM && TARGET_64BIT"
6160 [(set_attr "op_type" "RRE")])
6164 ;;- Rotate instructions.
6168 ; rotl(di|si)3 instruction pattern(s).
6171 (define_insn "rotl<mode>3"
6172 [(set (match_operand:GPR 0 "register_operand" "=d")
6173 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6174 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6177 [(set_attr "op_type" "RSE")
6178 (set_attr "atype" "reg")])
6180 (define_insn "*rotl<mode>3_and"
6181 [(set (match_operand:GPR 0 "register_operand" "=d")
6182 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6183 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6184 (match_operand:SI 3 "const_int_operand" "n"))))]
6185 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
6187 [(set_attr "op_type" "RSE")
6188 (set_attr "atype" "reg")])
6192 ;;- Shift instructions.
6196 ; (ashl|lshr)(di|si)3 instruction pattern(s).
6199 (define_expand "<shift><mode>3"
6200 [(set (match_operand:DSI 0 "register_operand" "")
6201 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
6202 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
6206 (define_insn "*<shift>di3_31"
6207 [(set (match_operand:DI 0 "register_operand" "=d")
6208 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6209 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6212 [(set_attr "op_type" "RS")
6213 (set_attr "atype" "reg")])
6215 (define_insn "*<shift><mode>3"
6216 [(set (match_operand:GPR 0 "register_operand" "=d")
6217 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6218 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6220 "s<lr>l<g>\t%0,<1>%Y2"
6221 [(set_attr "op_type" "RS<E>")
6222 (set_attr "atype" "reg")])
6224 (define_insn "*<shift>di3_31_and"
6225 [(set (match_operand:DI 0 "register_operand" "=d")
6226 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6227 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6228 (match_operand:SI 3 "const_int_operand" "n"))))]
6229 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6231 [(set_attr "op_type" "RS")
6232 (set_attr "atype" "reg")])
6234 (define_insn "*<shift><mode>3_and"
6235 [(set (match_operand:GPR 0 "register_operand" "=d")
6236 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6237 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6238 (match_operand:SI 3 "const_int_operand" "n"))))]
6239 "(INTVAL (operands[3]) & 63) == 63"
6240 "s<lr>l<g>\t%0,<1>%Y2"
6241 [(set_attr "op_type" "RS<E>")
6242 (set_attr "atype" "reg")])
6245 ; ashr(di|si)3 instruction pattern(s).
6248 (define_expand "ashr<mode>3"
6250 [(set (match_operand:DSI 0 "register_operand" "")
6251 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
6252 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
6253 (clobber (reg:CC CC_REGNUM))])]
6257 (define_insn "*ashrdi3_cc_31"
6258 [(set (reg CC_REGNUM)
6259 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6260 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6262 (set (match_operand:DI 0 "register_operand" "=d")
6263 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6264 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6266 [(set_attr "op_type" "RS")
6267 (set_attr "atype" "reg")])
6269 (define_insn "*ashrdi3_cconly_31"
6270 [(set (reg CC_REGNUM)
6271 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6272 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6274 (clobber (match_scratch:DI 0 "=d"))]
6275 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6277 [(set_attr "op_type" "RS")
6278 (set_attr "atype" "reg")])
6280 (define_insn "*ashrdi3_31"
6281 [(set (match_operand:DI 0 "register_operand" "=d")
6282 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6283 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6284 (clobber (reg:CC CC_REGNUM))]
6287 [(set_attr "op_type" "RS")
6288 (set_attr "atype" "reg")])
6290 (define_insn "*ashr<mode>3_cc"
6291 [(set (reg CC_REGNUM)
6292 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6293 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6295 (set (match_operand:GPR 0 "register_operand" "=d")
6296 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
6297 "s390_match_ccmode(insn, CCSmode)"
6299 [(set_attr "op_type" "RS<E>")
6300 (set_attr "atype" "reg")])
6302 (define_insn "*ashr<mode>3_cconly"
6303 [(set (reg CC_REGNUM)
6304 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6305 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6307 (clobber (match_scratch:GPR 0 "=d"))]
6308 "s390_match_ccmode(insn, CCSmode)"
6310 [(set_attr "op_type" "RS<E>")
6311 (set_attr "atype" "reg")])
6313 (define_insn "*ashr<mode>3"
6314 [(set (match_operand:GPR 0 "register_operand" "=d")
6315 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6316 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6317 (clobber (reg:CC CC_REGNUM))]
6320 [(set_attr "op_type" "RS<E>")
6321 (set_attr "atype" "reg")])
6324 ; shift pattern with implicit ANDs
6326 (define_insn "*ashrdi3_cc_31_and"
6327 [(set (reg CC_REGNUM)
6328 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6329 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6330 (match_operand:SI 3 "const_int_operand" "n")))
6332 (set (match_operand:DI 0 "register_operand" "=d")
6333 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6334 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6335 && (INTVAL (operands[3]) & 63) == 63"
6337 [(set_attr "op_type" "RS")
6338 (set_attr "atype" "reg")])
6340 (define_insn "*ashrdi3_cconly_31_and"
6341 [(set (reg CC_REGNUM)
6342 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6343 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6344 (match_operand:SI 3 "const_int_operand" "n")))
6346 (clobber (match_scratch:DI 0 "=d"))]
6347 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6348 && (INTVAL (operands[3]) & 63) == 63"
6350 [(set_attr "op_type" "RS")
6351 (set_attr "atype" "reg")])
6353 (define_insn "*ashrdi3_31_and"
6354 [(set (match_operand:DI 0 "register_operand" "=d")
6355 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6356 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6357 (match_operand:SI 3 "const_int_operand" "n"))))
6358 (clobber (reg:CC CC_REGNUM))]
6359 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6361 [(set_attr "op_type" "RS")
6362 (set_attr "atype" "reg")])
6364 (define_insn "*ashr<mode>3_cc_and"
6365 [(set (reg CC_REGNUM)
6366 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6367 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6368 (match_operand:SI 3 "const_int_operand" "n")))
6370 (set (match_operand:GPR 0 "register_operand" "=d")
6371 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6372 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6374 [(set_attr "op_type" "RS<E>")
6375 (set_attr "atype" "reg")])
6377 (define_insn "*ashr<mode>3_cconly_and"
6378 [(set (reg CC_REGNUM)
6379 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6380 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6381 (match_operand:SI 3 "const_int_operand" "n")))
6383 (clobber (match_scratch:GPR 0 "=d"))]
6384 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6386 [(set_attr "op_type" "RS<E>")
6387 (set_attr "atype" "reg")])
6389 (define_insn "*ashr<mode>3_and"
6390 [(set (match_operand:GPR 0 "register_operand" "=d")
6391 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6392 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6393 (match_operand:SI 3 "const_int_operand" "n"))))
6394 (clobber (reg:CC CC_REGNUM))]
6395 "(INTVAL (operands[3]) & 63) == 63"
6397 [(set_attr "op_type" "RS<E>")
6398 (set_attr "atype" "reg")])
6402 ;; Branch instruction patterns.
6405 (define_expand "b<code>"
6407 (if_then_else (COMPARE (match_operand 0 "" "")
6412 "s390_emit_jump (operands[0],
6413 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6417 ;;- Conditional jump instructions.
6420 (define_insn "*cjump_64"
6423 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6424 (label_ref (match_operand 0 "" ""))
6428 if (get_attr_length (insn) == 4)
6431 return "jg%C1\t%l0";
6433 [(set_attr "op_type" "RI")
6434 (set_attr "type" "branch")
6435 (set (attr "length")
6436 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6437 (const_int 4) (const_int 6)))])
6439 (define_insn "*cjump_31"
6442 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6443 (label_ref (match_operand 0 "" ""))
6447 gcc_assert (get_attr_length (insn) == 4);
6450 [(set_attr "op_type" "RI")
6451 (set_attr "type" "branch")
6452 (set (attr "length")
6453 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6454 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6455 (const_int 4) (const_int 6))
6456 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6457 (const_int 4) (const_int 8))))])
6459 (define_insn "*cjump_long"
6462 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6463 (match_operand 0 "address_operand" "U")
6467 if (get_attr_op_type (insn) == OP_TYPE_RR)
6472 [(set (attr "op_type")
6473 (if_then_else (match_operand 0 "register_operand" "")
6474 (const_string "RR") (const_string "RX")))
6475 (set_attr "type" "branch")
6476 (set_attr "atype" "agen")])
6480 ;;- Negated conditional jump instructions.
6483 (define_insn "*icjump_64"
6486 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6488 (label_ref (match_operand 0 "" ""))))]
6491 if (get_attr_length (insn) == 4)
6494 return "jg%D1\t%l0";
6496 [(set_attr "op_type" "RI")
6497 (set_attr "type" "branch")
6498 (set (attr "length")
6499 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6500 (const_int 4) (const_int 6)))])
6502 (define_insn "*icjump_31"
6505 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6507 (label_ref (match_operand 0 "" ""))))]
6510 gcc_assert (get_attr_length (insn) == 4);
6513 [(set_attr "op_type" "RI")
6514 (set_attr "type" "branch")
6515 (set (attr "length")
6516 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6517 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6518 (const_int 4) (const_int 6))
6519 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6520 (const_int 4) (const_int 8))))])
6522 (define_insn "*icjump_long"
6525 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6527 (match_operand 0 "address_operand" "U")))]
6530 if (get_attr_op_type (insn) == OP_TYPE_RR)
6535 [(set (attr "op_type")
6536 (if_then_else (match_operand 0 "register_operand" "")
6537 (const_string "RR") (const_string "RX")))
6538 (set_attr "type" "branch")
6539 (set_attr "atype" "agen")])
6542 ;;- Trap instructions.
6546 [(trap_if (const_int 1) (const_int 0))]
6549 [(set_attr "op_type" "RI")
6550 (set_attr "type" "branch")])
6552 (define_expand "conditional_trap"
6553 [(trap_if (match_operand 0 "comparison_operator" "")
6554 (match_operand 1 "general_operand" ""))]
6557 if (operands[1] != const0_rtx) FAIL;
6558 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6559 s390_compare_op0, s390_compare_op1);
6562 (define_insn "*trap"
6563 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6567 [(set_attr "op_type" "RI")
6568 (set_attr "type" "branch")])
6571 ;;- Loop instructions.
6573 ;; This is all complicated by the fact that since this is a jump insn
6574 ;; we must handle our own output reloads.
6576 (define_expand "doloop_end"
6577 [(use (match_operand 0 "" "")) ; loop pseudo
6578 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6579 (use (match_operand 2 "" "")) ; max iterations
6580 (use (match_operand 3 "" "")) ; loop level
6581 (use (match_operand 4 "" ""))] ; label
6584 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6585 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6586 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6587 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6588 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6589 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6596 (define_insn_and_split "doloop_si64"
6599 (ne (match_operand:SI 1 "register_operand" "d,d")
6601 (label_ref (match_operand 0 "" ""))
6603 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6604 (plus:SI (match_dup 1) (const_int -1)))
6605 (clobber (match_scratch:SI 3 "=X,&1"))
6606 (clobber (reg:CC CC_REGNUM))]
6609 if (which_alternative != 0)
6611 else if (get_attr_length (insn) == 4)
6612 return "brct\t%1,%l0";
6614 return "ahi\t%1,-1\;jgne\t%l0";
6616 "&& reload_completed
6617 && (! REG_P (operands[2])
6618 || ! rtx_equal_p (operands[1], operands[2]))"
6619 [(parallel [(set (reg:CCAN CC_REGNUM)
6620 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6622 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6623 (set (match_dup 2) (match_dup 3))
6624 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6625 (label_ref (match_dup 0))
6628 [(set_attr "op_type" "RI")
6629 (set_attr "type" "branch")
6630 (set (attr "length")
6631 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6632 (const_int 4) (const_int 10)))])
6634 (define_insn_and_split "doloop_si31"
6637 (ne (match_operand:SI 1 "register_operand" "d,d")
6639 (label_ref (match_operand 0 "" ""))
6641 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6642 (plus:SI (match_dup 1) (const_int -1)))
6643 (clobber (match_scratch:SI 3 "=X,&1"))
6644 (clobber (reg:CC CC_REGNUM))]
6647 if (which_alternative != 0)
6649 else if (get_attr_length (insn) == 4)
6650 return "brct\t%1,%l0";
6654 "&& reload_completed
6655 && (! REG_P (operands[2])
6656 || ! rtx_equal_p (operands[1], operands[2]))"
6657 [(parallel [(set (reg:CCAN CC_REGNUM)
6658 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6660 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6661 (set (match_dup 2) (match_dup 3))
6662 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6663 (label_ref (match_dup 0))
6666 [(set_attr "op_type" "RI")
6667 (set_attr "type" "branch")
6668 (set (attr "length")
6669 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6670 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6671 (const_int 4) (const_int 6))
6672 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6673 (const_int 4) (const_int 8))))])
6675 (define_insn "*doloop_si_long"
6678 (ne (match_operand:SI 1 "register_operand" "d,d")
6680 (match_operand 0 "address_operand" "U,U")
6682 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6683 (plus:SI (match_dup 1) (const_int -1)))
6684 (clobber (match_scratch:SI 3 "=X,&1"))
6685 (clobber (reg:CC CC_REGNUM))]
6688 if (get_attr_op_type (insn) == OP_TYPE_RR)
6689 return "bctr\t%1,%0";
6691 return "bct\t%1,%a0";
6693 [(set (attr "op_type")
6694 (if_then_else (match_operand 0 "register_operand" "")
6695 (const_string "RR") (const_string "RX")))
6696 (set_attr "type" "branch")
6697 (set_attr "atype" "agen")])
6699 (define_insn_and_split "doloop_di"
6702 (ne (match_operand:DI 1 "register_operand" "d,d")
6704 (label_ref (match_operand 0 "" ""))
6706 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6707 (plus:DI (match_dup 1) (const_int -1)))
6708 (clobber (match_scratch:DI 3 "=X,&1"))
6709 (clobber (reg:CC CC_REGNUM))]
6712 if (which_alternative != 0)
6714 else if (get_attr_length (insn) == 4)
6715 return "brctg\t%1,%l0";
6717 return "aghi\t%1,-1\;jgne\t%l0";
6719 "&& reload_completed
6720 && (! REG_P (operands[2])
6721 || ! rtx_equal_p (operands[1], operands[2]))"
6722 [(parallel [(set (reg:CCAN CC_REGNUM)
6723 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6725 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6726 (set (match_dup 2) (match_dup 3))
6727 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6728 (label_ref (match_dup 0))
6731 [(set_attr "op_type" "RI")
6732 (set_attr "type" "branch")
6733 (set (attr "length")
6734 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6735 (const_int 4) (const_int 10)))])
6738 ;;- Unconditional jump instructions.
6742 ; jump instruction pattern(s).
6745 (define_expand "jump"
6746 [(match_operand 0 "" "")]
6748 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6750 (define_insn "*jump64"
6751 [(set (pc) (label_ref (match_operand 0 "" "")))]
6754 if (get_attr_length (insn) == 4)
6759 [(set_attr "op_type" "RI")
6760 (set_attr "type" "branch")
6761 (set (attr "length")
6762 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6763 (const_int 4) (const_int 6)))])
6765 (define_insn "*jump31"
6766 [(set (pc) (label_ref (match_operand 0 "" "")))]
6769 gcc_assert (get_attr_length (insn) == 4);
6772 [(set_attr "op_type" "RI")
6773 (set_attr "type" "branch")
6774 (set (attr "length")
6775 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6776 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6777 (const_int 4) (const_int 6))
6778 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6779 (const_int 4) (const_int 8))))])
6782 ; indirect-jump instruction pattern(s).
6785 (define_insn "indirect_jump"
6786 [(set (pc) (match_operand 0 "address_operand" "U"))]
6789 if (get_attr_op_type (insn) == OP_TYPE_RR)
6794 [(set (attr "op_type")
6795 (if_then_else (match_operand 0 "register_operand" "")
6796 (const_string "RR") (const_string "RX")))
6797 (set_attr "type" "branch")
6798 (set_attr "atype" "agen")])
6801 ; casesi instruction pattern(s).
6804 (define_insn "casesi_jump"
6805 [(set (pc) (match_operand 0 "address_operand" "U"))
6806 (use (label_ref (match_operand 1 "" "")))]
6809 if (get_attr_op_type (insn) == OP_TYPE_RR)
6814 [(set (attr "op_type")
6815 (if_then_else (match_operand 0 "register_operand" "")
6816 (const_string "RR") (const_string "RX")))
6817 (set_attr "type" "branch")
6818 (set_attr "atype" "agen")])
6820 (define_expand "casesi"
6821 [(match_operand:SI 0 "general_operand" "")
6822 (match_operand:SI 1 "general_operand" "")
6823 (match_operand:SI 2 "general_operand" "")
6824 (label_ref (match_operand 3 "" ""))
6825 (label_ref (match_operand 4 "" ""))]
6828 rtx index = gen_reg_rtx (SImode);
6829 rtx base = gen_reg_rtx (Pmode);
6830 rtx target = gen_reg_rtx (Pmode);
6832 emit_move_insn (index, operands[0]);
6833 emit_insn (gen_subsi3 (index, index, operands[1]));
6834 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6837 if (Pmode != SImode)
6838 index = convert_to_mode (Pmode, index, 1);
6839 if (GET_CODE (index) != REG)
6840 index = copy_to_mode_reg (Pmode, index);
6843 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6845 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6847 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6849 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6850 emit_move_insn (target, index);
6853 target = gen_rtx_PLUS (Pmode, base, target);
6854 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6861 ;;- Jump to subroutine.
6866 ; untyped call instruction pattern(s).
6869 ;; Call subroutine returning any type.
6870 (define_expand "untyped_call"
6871 [(parallel [(call (match_operand 0 "" "")
6873 (match_operand 1 "" "")
6874 (match_operand 2 "" "")])]
6879 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6881 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6883 rtx set = XVECEXP (operands[2], 0, i);
6884 emit_move_insn (SET_DEST (set), SET_SRC (set));
6887 /* The optimizer does not know that the call sets the function value
6888 registers we stored in the result block. We avoid problems by
6889 claiming that all hard registers are used and clobbered at this
6891 emit_insn (gen_blockage ());
6896 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6897 ;; all of memory. This blocks insns from being moved across this point.
6899 (define_insn "blockage"
6900 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6903 [(set_attr "type" "none")
6904 (set_attr "length" "0")])
6910 (define_expand "sibcall"
6911 [(call (match_operand 0 "" "")
6912 (match_operand 1 "" ""))]
6915 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6919 (define_insn "*sibcall_br"
6920 [(call (mem:QI (reg SIBCALL_REGNUM))
6921 (match_operand 0 "const_int_operand" "n"))]
6922 "SIBLING_CALL_P (insn)
6923 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6925 [(set_attr "op_type" "RR")
6926 (set_attr "type" "branch")
6927 (set_attr "atype" "agen")])
6929 (define_insn "*sibcall_brc"
6930 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6931 (match_operand 1 "const_int_operand" "n"))]
6932 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6934 [(set_attr "op_type" "RI")
6935 (set_attr "type" "branch")])
6937 (define_insn "*sibcall_brcl"
6938 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6939 (match_operand 1 "const_int_operand" "n"))]
6940 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6942 [(set_attr "op_type" "RIL")
6943 (set_attr "type" "branch")])
6946 ; sibcall_value patterns
6949 (define_expand "sibcall_value"
6950 [(set (match_operand 0 "" "")
6951 (call (match_operand 1 "" "")
6952 (match_operand 2 "" "")))]
6955 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6959 (define_insn "*sibcall_value_br"
6960 [(set (match_operand 0 "" "")
6961 (call (mem:QI (reg SIBCALL_REGNUM))
6962 (match_operand 1 "const_int_operand" "n")))]
6963 "SIBLING_CALL_P (insn)
6964 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6966 [(set_attr "op_type" "RR")
6967 (set_attr "type" "branch")
6968 (set_attr "atype" "agen")])
6970 (define_insn "*sibcall_value_brc"
6971 [(set (match_operand 0 "" "")
6972 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6973 (match_operand 2 "const_int_operand" "n")))]
6974 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6976 [(set_attr "op_type" "RI")
6977 (set_attr "type" "branch")])
6979 (define_insn "*sibcall_value_brcl"
6980 [(set (match_operand 0 "" "")
6981 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6982 (match_operand 2 "const_int_operand" "n")))]
6983 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6985 [(set_attr "op_type" "RIL")
6986 (set_attr "type" "branch")])
6990 ; call instruction pattern(s).
6993 (define_expand "call"
6994 [(call (match_operand 0 "" "")
6995 (match_operand 1 "" ""))
6996 (use (match_operand 2 "" ""))]
6999 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7000 gen_rtx_REG (Pmode, RETURN_REGNUM));
7004 (define_insn "*bras"
7005 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7006 (match_operand 1 "const_int_operand" "n"))
7007 (clobber (match_operand 2 "register_operand" "=r"))]
7008 "!SIBLING_CALL_P (insn)
7009 && TARGET_SMALL_EXEC
7010 && GET_MODE (operands[2]) == Pmode"
7012 [(set_attr "op_type" "RI")
7013 (set_attr "type" "jsr")])
7015 (define_insn "*brasl"
7016 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7017 (match_operand 1 "const_int_operand" "n"))
7018 (clobber (match_operand 2 "register_operand" "=r"))]
7019 "!SIBLING_CALL_P (insn)
7021 && GET_MODE (operands[2]) == Pmode"
7023 [(set_attr "op_type" "RIL")
7024 (set_attr "type" "jsr")])
7026 (define_insn "*basr"
7027 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7028 (match_operand 1 "const_int_operand" "n"))
7029 (clobber (match_operand 2 "register_operand" "=r"))]
7030 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7032 if (get_attr_op_type (insn) == OP_TYPE_RR)
7033 return "basr\t%2,%0";
7035 return "bas\t%2,%a0";
7037 [(set (attr "op_type")
7038 (if_then_else (match_operand 0 "register_operand" "")
7039 (const_string "RR") (const_string "RX")))
7040 (set_attr "type" "jsr")
7041 (set_attr "atype" "agen")])
7044 ; call_value instruction pattern(s).
7047 (define_expand "call_value"
7048 [(set (match_operand 0 "" "")
7049 (call (match_operand 1 "" "")
7050 (match_operand 2 "" "")))
7051 (use (match_operand 3 "" ""))]
7054 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7055 gen_rtx_REG (Pmode, RETURN_REGNUM));
7059 (define_insn "*bras_r"
7060 [(set (match_operand 0 "" "")
7061 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7062 (match_operand:SI 2 "const_int_operand" "n")))
7063 (clobber (match_operand 3 "register_operand" "=r"))]
7064 "!SIBLING_CALL_P (insn)
7065 && TARGET_SMALL_EXEC
7066 && GET_MODE (operands[3]) == Pmode"
7068 [(set_attr "op_type" "RI")
7069 (set_attr "type" "jsr")])
7071 (define_insn "*brasl_r"
7072 [(set (match_operand 0 "" "")
7073 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7074 (match_operand 2 "const_int_operand" "n")))
7075 (clobber (match_operand 3 "register_operand" "=r"))]
7076 "!SIBLING_CALL_P (insn)
7078 && GET_MODE (operands[3]) == Pmode"
7080 [(set_attr "op_type" "RIL")
7081 (set_attr "type" "jsr")])
7083 (define_insn "*basr_r"
7084 [(set (match_operand 0 "" "")
7085 (call (mem:QI (match_operand 1 "address_operand" "U"))
7086 (match_operand 2 "const_int_operand" "n")))
7087 (clobber (match_operand 3 "register_operand" "=r"))]
7088 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7090 if (get_attr_op_type (insn) == OP_TYPE_RR)
7091 return "basr\t%3,%1";
7093 return "bas\t%3,%a1";
7095 [(set (attr "op_type")
7096 (if_then_else (match_operand 1 "register_operand" "")
7097 (const_string "RR") (const_string "RX")))
7098 (set_attr "type" "jsr")
7099 (set_attr "atype" "agen")])
7102 ;;- Thread-local storage support.
7105 (define_expand "get_tp_64"
7106 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7110 (define_expand "get_tp_31"
7111 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7115 (define_expand "set_tp_64"
7116 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7117 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7121 (define_expand "set_tp_31"
7122 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7123 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7127 (define_insn "*set_tp"
7128 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7131 [(set_attr "type" "none")
7132 (set_attr "length" "0")])
7134 (define_insn "*tls_load_64"
7135 [(set (match_operand:DI 0 "register_operand" "=d")
7136 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7137 (match_operand:DI 2 "" "")]
7141 [(set_attr "op_type" "RXE")])
7143 (define_insn "*tls_load_31"
7144 [(set (match_operand:SI 0 "register_operand" "=d,d")
7145 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7146 (match_operand:SI 2 "" "")]
7152 [(set_attr "op_type" "RX,RXY")])
7154 (define_insn "*bras_tls"
7155 [(set (match_operand 0 "" "")
7156 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7157 (match_operand 2 "const_int_operand" "n")))
7158 (clobber (match_operand 3 "register_operand" "=r"))
7159 (use (match_operand 4 "" ""))]
7160 "!SIBLING_CALL_P (insn)
7161 && TARGET_SMALL_EXEC
7162 && GET_MODE (operands[3]) == Pmode"
7164 [(set_attr "op_type" "RI")
7165 (set_attr "type" "jsr")])
7167 (define_insn "*brasl_tls"
7168 [(set (match_operand 0 "" "")
7169 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7170 (match_operand 2 "const_int_operand" "n")))
7171 (clobber (match_operand 3 "register_operand" "=r"))
7172 (use (match_operand 4 "" ""))]
7173 "!SIBLING_CALL_P (insn)
7175 && GET_MODE (operands[3]) == Pmode"
7177 [(set_attr "op_type" "RIL")
7178 (set_attr "type" "jsr")])
7180 (define_insn "*basr_tls"
7181 [(set (match_operand 0 "" "")
7182 (call (mem:QI (match_operand 1 "address_operand" "U"))
7183 (match_operand 2 "const_int_operand" "n")))
7184 (clobber (match_operand 3 "register_operand" "=r"))
7185 (use (match_operand 4 "" ""))]
7186 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7188 if (get_attr_op_type (insn) == OP_TYPE_RR)
7189 return "basr\t%3,%1%J4";
7191 return "bas\t%3,%a1%J4";
7193 [(set (attr "op_type")
7194 (if_then_else (match_operand 1 "register_operand" "")
7195 (const_string "RR") (const_string "RX")))
7196 (set_attr "type" "jsr")
7197 (set_attr "atype" "agen")])
7200 ;;- Atomic operations
7204 ; memory barrier pattern.
7207 (define_expand "memory_barrier"
7208 [(set (mem:BLK (match_dup 0))
7209 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7212 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7213 MEM_VOLATILE_P (operands[0]) = 1;
7216 (define_insn "*memory_barrier"
7217 [(set (match_operand:BLK 0 "" "")
7218 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7221 [(set_attr "op_type" "RR")])
7224 ; compare and swap patterns.
7227 (define_expand "sync_compare_and_swap<mode>"
7229 [(set (match_operand:TDSI 0 "register_operand" "")
7230 (match_operand:TDSI 1 "memory_operand" ""))
7232 (unspec_volatile:TDSI
7234 (match_operand:TDSI 2 "register_operand" "")
7235 (match_operand:TDSI 3 "register_operand" "")]
7237 (set (reg:CCZ1 CC_REGNUM)
7238 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7241 (define_expand "sync_compare_and_swap<mode>"
7243 [(set (match_operand:HQI 0 "register_operand" "")
7244 (match_operand:HQI 1 "memory_operand" ""))
7246 (unspec_volatile:HQI
7248 (match_operand:HQI 2 "general_operand" "")
7249 (match_operand:HQI 3 "general_operand" "")]
7251 (set (reg:CCZ1 CC_REGNUM)
7252 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7254 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
7255 operands[2], operands[3]); DONE;")
7257 (define_expand "sync_compare_and_swap_cc<mode>"
7259 [(set (match_operand:TDSI 0 "register_operand" "")
7260 (match_operand:TDSI 1 "memory_operand" ""))
7262 (unspec_volatile:TDSI
7264 (match_operand:TDSI 2 "register_operand" "")
7265 (match_operand:TDSI 3 "register_operand" "")]
7268 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7271 /* Emulate compare. */
7272 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7273 s390_compare_op0 = operands[1];
7274 s390_compare_op1 = operands[2];
7275 s390_compare_emitted = operands[4];
7278 (define_insn "*sync_compare_and_swap<mode>"
7279 [(set (match_operand:DP 0 "register_operand" "=r")
7280 (match_operand:DP 1 "memory_operand" "+Q"))
7284 (match_operand:DP 2 "register_operand" "0")
7285 (match_operand:DP 3 "register_operand" "r")]
7287 (set (reg:CCZ1 CC_REGNUM)
7288 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7290 "cds<tg>\t%0,%3,%S1"
7291 [(set_attr "op_type" "RS<TE>")
7292 (set_attr "type" "sem")])
7294 (define_insn "*sync_compare_and_swap<mode>"
7295 [(set (match_operand:GPR 0 "register_operand" "=r")
7296 (match_operand:GPR 1 "memory_operand" "+Q"))
7298 (unspec_volatile:GPR
7300 (match_operand:GPR 2 "register_operand" "0")
7301 (match_operand:GPR 3 "register_operand" "r")]
7303 (set (reg:CCZ1 CC_REGNUM)
7304 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7307 [(set_attr "op_type" "RS<E>")
7308 (set_attr "type" "sem")])
7312 ; Other atomic instruction patterns.
7315 (define_expand "sync_lock_test_and_set<mode>"
7316 [(match_operand:HQI 0 "register_operand")
7317 (match_operand:HQI 1 "memory_operand")
7318 (match_operand:HQI 2 "general_operand")]
7320 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
7321 operands[2], false); DONE;")
7323 (define_expand "sync_<atomic><mode>"
7324 [(set (match_operand:HQI 0 "memory_operand")
7325 (ATOMIC:HQI (match_dup 0)
7326 (match_operand:HQI 1 "general_operand")))]
7328 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
7329 operands[1], false); DONE;")
7331 (define_expand "sync_old_<atomic><mode>"
7332 [(set (match_operand:HQI 0 "register_operand")
7333 (match_operand:HQI 1 "memory_operand"))
7335 (ATOMIC:HQI (match_dup 1)
7336 (match_operand:HQI 2 "general_operand")))]
7338 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7339 operands[2], false); DONE;")
7341 (define_expand "sync_new_<atomic><mode>"
7342 [(set (match_operand:HQI 0 "register_operand")
7343 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
7344 (match_operand:HQI 2 "general_operand")))
7345 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
7347 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7348 operands[2], true); DONE;")
7351 ;;- Miscellaneous instructions.
7355 ; allocate stack instruction pattern(s).
7358 (define_expand "allocate_stack"
7359 [(match_operand 0 "general_operand" "")
7360 (match_operand 1 "general_operand" "")]
7363 rtx temp = gen_reg_rtx (Pmode);
7365 emit_move_insn (temp, s390_back_chain_rtx ());
7366 anti_adjust_stack (operands[1]);
7367 emit_move_insn (s390_back_chain_rtx (), temp);
7369 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7375 ; setjmp instruction pattern.
7378 (define_expand "builtin_setjmp_receiver"
7379 [(match_operand 0 "" "")]
7382 emit_insn (s390_load_got ());
7383 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7387 ;; These patterns say how to save and restore the stack pointer. We need not
7388 ;; save the stack pointer at function level since we are careful to
7389 ;; preserve the backchain. At block level, we have to restore the backchain
7390 ;; when we restore the stack pointer.
7392 ;; For nonlocal gotos, we must save both the stack pointer and its
7393 ;; backchain and restore both. Note that in the nonlocal case, the
7394 ;; save area is a memory location.
7396 (define_expand "save_stack_function"
7397 [(match_operand 0 "general_operand" "")
7398 (match_operand 1 "general_operand" "")]
7402 (define_expand "restore_stack_function"
7403 [(match_operand 0 "general_operand" "")
7404 (match_operand 1 "general_operand" "")]
7408 (define_expand "restore_stack_block"
7409 [(match_operand 0 "register_operand" "")
7410 (match_operand 1 "register_operand" "")]
7413 rtx temp = gen_reg_rtx (Pmode);
7415 emit_move_insn (temp, s390_back_chain_rtx ());
7416 emit_move_insn (operands[0], operands[1]);
7417 emit_move_insn (s390_back_chain_rtx (), temp);
7422 (define_expand "save_stack_nonlocal"
7423 [(match_operand 0 "memory_operand" "")
7424 (match_operand 1 "register_operand" "")]
7427 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7428 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7430 /* Copy the backchain to the first word, sp to the second and the
7431 literal pool base to the third. */
7433 if (TARGET_BACKCHAIN)
7435 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7436 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7439 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7440 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7445 (define_expand "restore_stack_nonlocal"
7446 [(match_operand 0 "register_operand" "")
7447 (match_operand 1 "memory_operand" "")]
7450 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7451 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7452 rtx temp = NULL_RTX;
7454 /* Restore the backchain from the first word, sp from the second and the
7455 literal pool base from the third. */
7457 if (TARGET_BACKCHAIN)
7458 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7460 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7461 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7464 emit_move_insn (s390_back_chain_rtx (), temp);
7466 emit_insn (gen_rtx_USE (VOIDmode, base));
7470 (define_expand "exception_receiver"
7474 s390_set_has_landing_pad_p (true);
7479 ; nop instruction pattern(s).
7486 [(set_attr "op_type" "RR")])
7490 ; Special literal pool access instruction pattern(s).
7493 (define_insn "*pool_entry"
7494 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7495 UNSPECV_POOL_ENTRY)]
7498 enum machine_mode mode = GET_MODE (PATTERN (insn));
7499 unsigned int align = GET_MODE_BITSIZE (mode);
7500 s390_output_pool_entry (operands[0], mode, align);
7503 [(set (attr "length")
7504 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7506 (define_insn "pool_align"
7507 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7508 UNSPECV_POOL_ALIGN)]
7511 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7513 (define_insn "pool_section_start"
7514 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7517 [(set_attr "length" "0")])
7519 (define_insn "pool_section_end"
7520 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7523 [(set_attr "length" "0")])
7525 (define_insn "main_base_31_small"
7526 [(set (match_operand 0 "register_operand" "=a")
7527 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7528 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7530 [(set_attr "op_type" "RR")
7531 (set_attr "type" "la")])
7533 (define_insn "main_base_31_large"
7534 [(set (match_operand 0 "register_operand" "=a")
7535 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7536 (set (pc) (label_ref (match_operand 2 "" "")))]
7537 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7539 [(set_attr "op_type" "RI")])
7541 (define_insn "main_base_64"
7542 [(set (match_operand 0 "register_operand" "=a")
7543 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7544 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7546 [(set_attr "op_type" "RIL")
7547 (set_attr "type" "larl")])
7549 (define_insn "main_pool"
7550 [(set (match_operand 0 "register_operand" "=a")
7551 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7552 "GET_MODE (operands[0]) == Pmode"
7557 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7558 (const_string "larl") (const_string "la")))])
7560 (define_insn "reload_base_31"
7561 [(set (match_operand 0 "register_operand" "=a")
7562 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7563 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7564 "basr\t%0,0\;la\t%0,%1-.(%0)"
7565 [(set_attr "length" "6")
7566 (set_attr "type" "la")])
7568 (define_insn "reload_base_64"
7569 [(set (match_operand 0 "register_operand" "=a")
7570 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7571 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7573 [(set_attr "op_type" "RIL")
7574 (set_attr "type" "larl")])
7577 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7582 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7585 ;; Insns related to generating the function prologue and epilogue.
7589 (define_expand "prologue"
7590 [(use (const_int 0))]
7592 "s390_emit_prologue (); DONE;")
7594 (define_expand "epilogue"
7595 [(use (const_int 1))]
7597 "s390_emit_epilogue (false); DONE;")
7599 (define_expand "sibcall_epilogue"
7600 [(use (const_int 0))]
7602 "s390_emit_epilogue (true); DONE;")
7604 (define_insn "*return"
7606 (use (match_operand 0 "register_operand" "a"))]
7607 "GET_MODE (operands[0]) == Pmode"
7609 [(set_attr "op_type" "RR")
7610 (set_attr "type" "jsr")
7611 (set_attr "atype" "agen")])
7614 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7615 ;; pointer. This is used for compatibility.
7617 (define_expand "ptr_extend"
7618 [(set (match_operand:DI 0 "register_operand" "=r")
7619 (match_operand:SI 1 "register_operand" "r"))]
7622 emit_insn (gen_anddi3 (operands[0],
7623 gen_lowpart (DImode, operands[1]),
7624 GEN_INT (0x7fffffff)));
7628 ;; Instruction definition to expand eh_return macro to support
7629 ;; swapping in special linkage return addresses.
7631 (define_expand "eh_return"
7632 [(use (match_operand 0 "register_operand" ""))]
7635 s390_emit_tpf_eh_return (operands[0]);
7640 ; Stack Protector Patterns
7643 (define_expand "stack_protect_set"
7644 [(set (match_operand 0 "memory_operand" "")
7645 (match_operand 1 "memory_operand" ""))]
7648 #ifdef TARGET_THREAD_SSP_OFFSET
7650 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7651 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7654 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7656 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7661 (define_insn "stack_protect_set<mode>"
7662 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7663 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7665 "mvc\t%O0(%G0,%R0),%S1"
7666 [(set_attr "op_type" "SS")])
7668 (define_expand "stack_protect_test"
7669 [(set (reg:CC CC_REGNUM)
7670 (compare (match_operand 0 "memory_operand" "")
7671 (match_operand 1 "memory_operand" "")))
7672 (match_operand 2 "" "")]
7675 #ifdef TARGET_THREAD_SSP_OFFSET
7677 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7678 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7680 s390_compare_op0 = operands[0];
7681 s390_compare_op1 = operands[1];
7682 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7685 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7687 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7689 emit_jump_insn (gen_beq (operands[2]));
7694 (define_insn "stack_protect_test<mode>"
7695 [(set (reg:CCZ CC_REGNUM)
7696 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7697 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7699 "clc\t%O0(%G0,%R0),%S1"
7700 [(set_attr "op_type" "SS")])