1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "tree-flow.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
58 #include "tree-data-ref.h"
59 #include "tree-vectorizer.h"
63 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
66 #include "gstab.h" /* for N_SLINE */
69 #ifndef TARGET_NO_PROTOTYPE
70 #define TARGET_NO_PROTOTYPE 0
73 #define min(A,B) ((A) < (B) ? (A) : (B))
74 #define max(A,B) ((A) > (B) ? (A) : (B))
76 /* Structure used to define the rs6000 stack */
77 typedef struct rs6000_stack
{
78 int first_gp_reg_save
; /* first callee saved GP register used */
79 int first_fp_reg_save
; /* first callee saved FP register used */
80 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
81 int lr_save_p
; /* true if the link reg needs to be saved */
82 int cr_save_p
; /* true if the CR reg needs to be saved */
83 unsigned int vrsave_mask
; /* mask of vec registers to save */
84 int push_p
; /* true if we need to allocate stack space */
85 int calls_p
; /* true if the function makes any calls */
86 int world_save_p
; /* true if we're saving *everything*:
87 r13-r31, cr, f14-f31, vrsave, v20-v31 */
88 enum rs6000_abi abi
; /* which ABI to use */
89 int gp_save_offset
; /* offset to save GP regs from initial SP */
90 int fp_save_offset
; /* offset to save FP regs from initial SP */
91 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
92 int lr_save_offset
; /* offset to save LR from initial SP */
93 int cr_save_offset
; /* offset to save CR from initial SP */
94 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
95 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
96 int varargs_save_offset
; /* offset to save the varargs registers */
97 int ehrd_offset
; /* offset to EH return data */
98 int reg_size
; /* register size (4 or 8) */
99 HOST_WIDE_INT vars_size
; /* variable save area size */
100 int parm_size
; /* outgoing parameter size */
101 int save_size
; /* save area size */
102 int fixed_size
; /* fixed size of stack frame */
103 int gp_size
; /* size of saved GP registers */
104 int fp_size
; /* size of saved FP registers */
105 int altivec_size
; /* size of saved AltiVec registers */
106 int cr_size
; /* size to hold CR if not in save_size */
107 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
108 int altivec_padding_size
; /* size of altivec alignment padding if
110 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
111 int spe_padding_size
;
112 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
113 int spe_64bit_regs_used
;
116 /* A C structure for machine-specific, per-function data.
117 This is added to the cfun structure. */
118 typedef struct machine_function
GTY(())
120 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
121 int ra_needs_full_frame
;
122 /* Some local-dynamic symbol. */
123 const char *some_ld_name
;
124 /* Whether the instruction chain has been scanned already. */
125 int insn_chain_scanned_p
;
126 /* Flags if __builtin_return_address (0) was used. */
128 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
129 varargs save area. */
130 HOST_WIDE_INT varargs_save_offset
;
133 /* Target cpu type */
135 enum processor_type rs6000_cpu
;
136 struct rs6000_cpu_select rs6000_select
[3] =
138 /* switch name, tune arch */
139 { (const char *)0, "--with-cpu=", 1, 1 },
140 { (const char *)0, "-mcpu=", 1, 1 },
141 { (const char *)0, "-mtune=", 1, 0 },
144 /* Always emit branch hint bits. */
145 static GTY(()) bool rs6000_always_hint
;
147 /* Schedule instructions for group formation. */
148 static GTY(()) bool rs6000_sched_groups
;
150 /* Support for -msched-costly-dep option. */
151 const char *rs6000_sched_costly_dep_str
;
152 enum rs6000_dependence_cost rs6000_sched_costly_dep
;
154 /* Support for -minsert-sched-nops option. */
155 const char *rs6000_sched_insert_nops_str
;
156 enum rs6000_nop_insertion rs6000_sched_insert_nops
;
158 /* Support targetm.vectorize.builtin_mask_for_load. */
159 static GTY(()) tree altivec_builtin_mask_for_load
;
161 /* Size of long double */
162 int rs6000_long_double_type_size
;
164 /* Whether -mabi=altivec has appeared */
165 int rs6000_altivec_abi
;
167 /* Nonzero if we want SPE ABI extensions. */
170 /* Nonzero if floating point operations are done in the GPRs. */
171 int rs6000_float_gprs
= 0;
173 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
174 int rs6000_darwin64_abi
;
176 /* Set to nonzero once AIX common-mode calls have been defined. */
177 static GTY(()) int common_mode_defined
;
179 /* Save information from a "cmpxx" operation until the branch or scc is
181 rtx rs6000_compare_op0
, rs6000_compare_op1
;
182 int rs6000_compare_fp_p
;
184 /* Label number of label created for -mrelocatable, to call to so we can
185 get the address of the GOT section */
186 int rs6000_pic_labelno
;
189 /* Which abi to adhere to */
190 const char *rs6000_abi_name
;
192 /* Semantics of the small data area */
193 enum rs6000_sdata_type rs6000_sdata
= SDATA_DATA
;
195 /* Which small data model to use */
196 const char *rs6000_sdata_name
= (char *)0;
198 /* Counter for labels which are to be placed in .fixup. */
199 int fixuplabelno
= 0;
202 /* Bit size of immediate TLS offsets and string from which it is decoded. */
203 int rs6000_tls_size
= 32;
204 const char *rs6000_tls_size_string
;
206 /* ABI enumeration available for subtarget to use. */
207 enum rs6000_abi rs6000_current_abi
;
209 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
213 const char *rs6000_debug_name
;
214 int rs6000_debug_stack
; /* debug stack applications */
215 int rs6000_debug_arg
; /* debug argument handling */
217 /* Value is TRUE if register/mode pair is acceptable. */
218 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
220 /* Built in types. */
222 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
223 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
225 const char *rs6000_traceback_name
;
227 traceback_default
= 0,
233 /* Flag to say the TOC is initialized */
235 char toc_label_name
[10];
237 static GTY(()) section
*read_only_data_section
;
238 static GTY(()) section
*private_data_section
;
239 static GTY(()) section
*read_only_private_data_section
;
240 static GTY(()) section
*sdata2_section
;
241 static GTY(()) section
*toc_section
;
243 /* Control alignment for fields within structures. */
244 /* String from -malign-XXXXX. */
245 int rs6000_alignment_flags
;
247 /* True for any options that were explicitly set. */
249 bool aix_struct_ret
; /* True if -maix-struct-ret was used. */
250 bool alignment
; /* True if -malign- was used. */
251 bool abi
; /* True if -mabi= was used. */
252 bool spe
; /* True if -mspe= was used. */
253 bool float_gprs
; /* True if -mfloat-gprs= was used. */
254 bool isel
; /* True if -misel was used. */
255 bool long_double
; /* True if -mlong-double- was used. */
256 } rs6000_explicit_options
;
258 struct builtin_description
260 /* mask is not const because we're going to alter it below. This
261 nonsense will go away when we rewrite the -march infrastructure
262 to give us more target flag bits. */
264 const enum insn_code icode
;
265 const char *const name
;
266 const enum rs6000_builtins code
;
269 /* Target cpu costs. */
271 struct processor_costs
{
272 const int mulsi
; /* cost of SImode multiplication. */
273 const int mulsi_const
; /* cost of SImode multiplication by constant. */
274 const int mulsi_const9
; /* cost of SImode mult by short constant. */
275 const int muldi
; /* cost of DImode multiplication. */
276 const int divsi
; /* cost of SImode division. */
277 const int divdi
; /* cost of DImode division. */
278 const int fp
; /* cost of simple SFmode and DFmode insns. */
279 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
280 const int sdiv
; /* cost of SFmode division (fdivs). */
281 const int ddiv
; /* cost of DFmode division (fdiv). */
284 const struct processor_costs
*rs6000_cost
;
286 /* Processor costs (relative to an add) */
288 /* Instruction size costs on 32bit processors. */
290 struct processor_costs size32_cost
= {
291 COSTS_N_INSNS (1), /* mulsi */
292 COSTS_N_INSNS (1), /* mulsi_const */
293 COSTS_N_INSNS (1), /* mulsi_const9 */
294 COSTS_N_INSNS (1), /* muldi */
295 COSTS_N_INSNS (1), /* divsi */
296 COSTS_N_INSNS (1), /* divdi */
297 COSTS_N_INSNS (1), /* fp */
298 COSTS_N_INSNS (1), /* dmul */
299 COSTS_N_INSNS (1), /* sdiv */
300 COSTS_N_INSNS (1), /* ddiv */
303 /* Instruction size costs on 64bit processors. */
305 struct processor_costs size64_cost
= {
306 COSTS_N_INSNS (1), /* mulsi */
307 COSTS_N_INSNS (1), /* mulsi_const */
308 COSTS_N_INSNS (1), /* mulsi_const9 */
309 COSTS_N_INSNS (1), /* muldi */
310 COSTS_N_INSNS (1), /* divsi */
311 COSTS_N_INSNS (1), /* divdi */
312 COSTS_N_INSNS (1), /* fp */
313 COSTS_N_INSNS (1), /* dmul */
314 COSTS_N_INSNS (1), /* sdiv */
315 COSTS_N_INSNS (1), /* ddiv */
318 /* Instruction costs on RIOS1 processors. */
320 struct processor_costs rios1_cost
= {
321 COSTS_N_INSNS (5), /* mulsi */
322 COSTS_N_INSNS (4), /* mulsi_const */
323 COSTS_N_INSNS (3), /* mulsi_const9 */
324 COSTS_N_INSNS (5), /* muldi */
325 COSTS_N_INSNS (19), /* divsi */
326 COSTS_N_INSNS (19), /* divdi */
327 COSTS_N_INSNS (2), /* fp */
328 COSTS_N_INSNS (2), /* dmul */
329 COSTS_N_INSNS (19), /* sdiv */
330 COSTS_N_INSNS (19), /* ddiv */
333 /* Instruction costs on RIOS2 processors. */
335 struct processor_costs rios2_cost
= {
336 COSTS_N_INSNS (2), /* mulsi */
337 COSTS_N_INSNS (2), /* mulsi_const */
338 COSTS_N_INSNS (2), /* mulsi_const9 */
339 COSTS_N_INSNS (2), /* muldi */
340 COSTS_N_INSNS (13), /* divsi */
341 COSTS_N_INSNS (13), /* divdi */
342 COSTS_N_INSNS (2), /* fp */
343 COSTS_N_INSNS (2), /* dmul */
344 COSTS_N_INSNS (17), /* sdiv */
345 COSTS_N_INSNS (17), /* ddiv */
348 /* Instruction costs on RS64A processors. */
350 struct processor_costs rs64a_cost
= {
351 COSTS_N_INSNS (20), /* mulsi */
352 COSTS_N_INSNS (12), /* mulsi_const */
353 COSTS_N_INSNS (8), /* mulsi_const9 */
354 COSTS_N_INSNS (34), /* muldi */
355 COSTS_N_INSNS (65), /* divsi */
356 COSTS_N_INSNS (67), /* divdi */
357 COSTS_N_INSNS (4), /* fp */
358 COSTS_N_INSNS (4), /* dmul */
359 COSTS_N_INSNS (31), /* sdiv */
360 COSTS_N_INSNS (31), /* ddiv */
363 /* Instruction costs on MPCCORE processors. */
365 struct processor_costs mpccore_cost
= {
366 COSTS_N_INSNS (2), /* mulsi */
367 COSTS_N_INSNS (2), /* mulsi_const */
368 COSTS_N_INSNS (2), /* mulsi_const9 */
369 COSTS_N_INSNS (2), /* muldi */
370 COSTS_N_INSNS (6), /* divsi */
371 COSTS_N_INSNS (6), /* divdi */
372 COSTS_N_INSNS (4), /* fp */
373 COSTS_N_INSNS (5), /* dmul */
374 COSTS_N_INSNS (10), /* sdiv */
375 COSTS_N_INSNS (17), /* ddiv */
378 /* Instruction costs on PPC403 processors. */
380 struct processor_costs ppc403_cost
= {
381 COSTS_N_INSNS (4), /* mulsi */
382 COSTS_N_INSNS (4), /* mulsi_const */
383 COSTS_N_INSNS (4), /* mulsi_const9 */
384 COSTS_N_INSNS (4), /* muldi */
385 COSTS_N_INSNS (33), /* divsi */
386 COSTS_N_INSNS (33), /* divdi */
387 COSTS_N_INSNS (11), /* fp */
388 COSTS_N_INSNS (11), /* dmul */
389 COSTS_N_INSNS (11), /* sdiv */
390 COSTS_N_INSNS (11), /* ddiv */
393 /* Instruction costs on PPC405 processors. */
395 struct processor_costs ppc405_cost
= {
396 COSTS_N_INSNS (5), /* mulsi */
397 COSTS_N_INSNS (4), /* mulsi_const */
398 COSTS_N_INSNS (3), /* mulsi_const9 */
399 COSTS_N_INSNS (5), /* muldi */
400 COSTS_N_INSNS (35), /* divsi */
401 COSTS_N_INSNS (35), /* divdi */
402 COSTS_N_INSNS (11), /* fp */
403 COSTS_N_INSNS (11), /* dmul */
404 COSTS_N_INSNS (11), /* sdiv */
405 COSTS_N_INSNS (11), /* ddiv */
408 /* Instruction costs on PPC440 processors. */
410 struct processor_costs ppc440_cost
= {
411 COSTS_N_INSNS (3), /* mulsi */
412 COSTS_N_INSNS (2), /* mulsi_const */
413 COSTS_N_INSNS (2), /* mulsi_const9 */
414 COSTS_N_INSNS (3), /* muldi */
415 COSTS_N_INSNS (34), /* divsi */
416 COSTS_N_INSNS (34), /* divdi */
417 COSTS_N_INSNS (5), /* fp */
418 COSTS_N_INSNS (5), /* dmul */
419 COSTS_N_INSNS (19), /* sdiv */
420 COSTS_N_INSNS (33), /* ddiv */
423 /* Instruction costs on PPC601 processors. */
425 struct processor_costs ppc601_cost
= {
426 COSTS_N_INSNS (5), /* mulsi */
427 COSTS_N_INSNS (5), /* mulsi_const */
428 COSTS_N_INSNS (5), /* mulsi_const9 */
429 COSTS_N_INSNS (5), /* muldi */
430 COSTS_N_INSNS (36), /* divsi */
431 COSTS_N_INSNS (36), /* divdi */
432 COSTS_N_INSNS (4), /* fp */
433 COSTS_N_INSNS (5), /* dmul */
434 COSTS_N_INSNS (17), /* sdiv */
435 COSTS_N_INSNS (31), /* ddiv */
438 /* Instruction costs on PPC603 processors. */
440 struct processor_costs ppc603_cost
= {
441 COSTS_N_INSNS (5), /* mulsi */
442 COSTS_N_INSNS (3), /* mulsi_const */
443 COSTS_N_INSNS (2), /* mulsi_const9 */
444 COSTS_N_INSNS (5), /* muldi */
445 COSTS_N_INSNS (37), /* divsi */
446 COSTS_N_INSNS (37), /* divdi */
447 COSTS_N_INSNS (3), /* fp */
448 COSTS_N_INSNS (4), /* dmul */
449 COSTS_N_INSNS (18), /* sdiv */
450 COSTS_N_INSNS (33), /* ddiv */
453 /* Instruction costs on PPC604 processors. */
455 struct processor_costs ppc604_cost
= {
456 COSTS_N_INSNS (4), /* mulsi */
457 COSTS_N_INSNS (4), /* mulsi_const */
458 COSTS_N_INSNS (4), /* mulsi_const9 */
459 COSTS_N_INSNS (4), /* muldi */
460 COSTS_N_INSNS (20), /* divsi */
461 COSTS_N_INSNS (20), /* divdi */
462 COSTS_N_INSNS (3), /* fp */
463 COSTS_N_INSNS (3), /* dmul */
464 COSTS_N_INSNS (18), /* sdiv */
465 COSTS_N_INSNS (32), /* ddiv */
468 /* Instruction costs on PPC604e processors. */
470 struct processor_costs ppc604e_cost
= {
471 COSTS_N_INSNS (2), /* mulsi */
472 COSTS_N_INSNS (2), /* mulsi_const */
473 COSTS_N_INSNS (2), /* mulsi_const9 */
474 COSTS_N_INSNS (2), /* muldi */
475 COSTS_N_INSNS (20), /* divsi */
476 COSTS_N_INSNS (20), /* divdi */
477 COSTS_N_INSNS (3), /* fp */
478 COSTS_N_INSNS (3), /* dmul */
479 COSTS_N_INSNS (18), /* sdiv */
480 COSTS_N_INSNS (32), /* ddiv */
483 /* Instruction costs on PPC620 processors. */
485 struct processor_costs ppc620_cost
= {
486 COSTS_N_INSNS (5), /* mulsi */
487 COSTS_N_INSNS (4), /* mulsi_const */
488 COSTS_N_INSNS (3), /* mulsi_const9 */
489 COSTS_N_INSNS (7), /* muldi */
490 COSTS_N_INSNS (21), /* divsi */
491 COSTS_N_INSNS (37), /* divdi */
492 COSTS_N_INSNS (3), /* fp */
493 COSTS_N_INSNS (3), /* dmul */
494 COSTS_N_INSNS (18), /* sdiv */
495 COSTS_N_INSNS (32), /* ddiv */
498 /* Instruction costs on PPC630 processors. */
500 struct processor_costs ppc630_cost
= {
501 COSTS_N_INSNS (5), /* mulsi */
502 COSTS_N_INSNS (4), /* mulsi_const */
503 COSTS_N_INSNS (3), /* mulsi_const9 */
504 COSTS_N_INSNS (7), /* muldi */
505 COSTS_N_INSNS (21), /* divsi */
506 COSTS_N_INSNS (37), /* divdi */
507 COSTS_N_INSNS (3), /* fp */
508 COSTS_N_INSNS (3), /* dmul */
509 COSTS_N_INSNS (17), /* sdiv */
510 COSTS_N_INSNS (21), /* ddiv */
513 /* Instruction costs on PPC750 and PPC7400 processors. */
515 struct processor_costs ppc750_cost
= {
516 COSTS_N_INSNS (5), /* mulsi */
517 COSTS_N_INSNS (3), /* mulsi_const */
518 COSTS_N_INSNS (2), /* mulsi_const9 */
519 COSTS_N_INSNS (5), /* muldi */
520 COSTS_N_INSNS (17), /* divsi */
521 COSTS_N_INSNS (17), /* divdi */
522 COSTS_N_INSNS (3), /* fp */
523 COSTS_N_INSNS (3), /* dmul */
524 COSTS_N_INSNS (17), /* sdiv */
525 COSTS_N_INSNS (31), /* ddiv */
528 /* Instruction costs on PPC7450 processors. */
530 struct processor_costs ppc7450_cost
= {
531 COSTS_N_INSNS (4), /* mulsi */
532 COSTS_N_INSNS (3), /* mulsi_const */
533 COSTS_N_INSNS (3), /* mulsi_const9 */
534 COSTS_N_INSNS (4), /* muldi */
535 COSTS_N_INSNS (23), /* divsi */
536 COSTS_N_INSNS (23), /* divdi */
537 COSTS_N_INSNS (5), /* fp */
538 COSTS_N_INSNS (5), /* dmul */
539 COSTS_N_INSNS (21), /* sdiv */
540 COSTS_N_INSNS (35), /* ddiv */
543 /* Instruction costs on PPC8540 processors. */
545 struct processor_costs ppc8540_cost
= {
546 COSTS_N_INSNS (4), /* mulsi */
547 COSTS_N_INSNS (4), /* mulsi_const */
548 COSTS_N_INSNS (4), /* mulsi_const9 */
549 COSTS_N_INSNS (4), /* muldi */
550 COSTS_N_INSNS (19), /* divsi */
551 COSTS_N_INSNS (19), /* divdi */
552 COSTS_N_INSNS (4), /* fp */
553 COSTS_N_INSNS (4), /* dmul */
554 COSTS_N_INSNS (29), /* sdiv */
555 COSTS_N_INSNS (29), /* ddiv */
558 /* Instruction costs on POWER4 and POWER5 processors. */
560 struct processor_costs power4_cost
= {
561 COSTS_N_INSNS (3), /* mulsi */
562 COSTS_N_INSNS (2), /* mulsi_const */
563 COSTS_N_INSNS (2), /* mulsi_const9 */
564 COSTS_N_INSNS (4), /* muldi */
565 COSTS_N_INSNS (18), /* divsi */
566 COSTS_N_INSNS (34), /* divdi */
567 COSTS_N_INSNS (3), /* fp */
568 COSTS_N_INSNS (3), /* dmul */
569 COSTS_N_INSNS (17), /* sdiv */
570 COSTS_N_INSNS (17), /* ddiv */
574 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
575 static const char *rs6000_invalid_within_doloop (rtx
);
576 static rtx
rs6000_generate_compare (enum rtx_code
);
577 static void rs6000_maybe_dead (rtx
);
578 static void rs6000_emit_stack_tie (void);
579 static void rs6000_frame_related (rtx
, rtx
, HOST_WIDE_INT
, rtx
, rtx
);
580 static rtx
spe_synthesize_frame_save (rtx
);
581 static bool spe_func_has_64bit_regs_p (void);
582 static void emit_frame_save (rtx
, rtx
, enum machine_mode
, unsigned int,
584 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
585 static void rs6000_emit_allocate_stack (HOST_WIDE_INT
, int);
586 static unsigned rs6000_hash_constant (rtx
);
587 static unsigned toc_hash_function (const void *);
588 static int toc_hash_eq (const void *, const void *);
589 static int constant_pool_expr_1 (rtx
, int *, int *);
590 static bool constant_pool_expr_p (rtx
);
591 static bool legitimate_indexed_address_p (rtx
, int);
592 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
593 static struct machine_function
* rs6000_init_machine_status (void);
594 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
595 static bool no_global_regs_above (int);
596 #ifdef HAVE_GAS_HIDDEN
597 static void rs6000_assemble_visibility (tree
, int);
599 static int rs6000_ra_ever_killed (void);
600 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
601 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
602 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
603 static const char *rs6000_mangle_fundamental_type (tree
);
604 extern const struct attribute_spec rs6000_attribute_table
[];
605 static void rs6000_set_default_type_attributes (tree
);
606 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
607 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
608 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
610 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
611 static bool rs6000_return_in_memory (tree
, tree
);
612 static void rs6000_file_start (void);
614 static unsigned int rs6000_elf_section_type_flags (tree
, const char *, int);
615 static void rs6000_elf_asm_out_constructor (rtx
, int);
616 static void rs6000_elf_asm_out_destructor (rtx
, int);
617 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED
;
618 static void rs6000_elf_asm_init_sections (void);
619 static section
*rs6000_elf_select_section (tree
, int, unsigned HOST_WIDE_INT
);
620 static void rs6000_elf_unique_section (tree
, int);
621 static section
*rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
622 unsigned HOST_WIDE_INT
);
623 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
627 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
628 static void rs6000_xcoff_asm_init_sections (void);
629 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
630 static section
*rs6000_xcoff_select_section (tree
, int,
631 unsigned HOST_WIDE_INT
);
632 static void rs6000_xcoff_unique_section (tree
, int);
633 static section
*rs6000_xcoff_select_rtx_section
634 (enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
);
635 static const char * rs6000_xcoff_strip_name_encoding (const char *);
636 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
637 static void rs6000_xcoff_file_start (void);
638 static void rs6000_xcoff_file_end (void);
640 static int rs6000_variable_issue (FILE *, int, rtx
, int);
641 static bool rs6000_rtx_costs (rtx
, int, int, int *);
642 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
643 static bool is_microcoded_insn (rtx
);
644 static int is_dispatch_slot_restricted (rtx
);
645 static bool is_cracked_insn (rtx
);
646 static bool is_branch_slot_insn (rtx
);
647 static int rs6000_adjust_priority (rtx
, int);
648 static int rs6000_issue_rate (void);
649 static bool rs6000_is_costly_dependence (rtx
, rtx
, rtx
, int, int);
650 static rtx
get_next_active_insn (rtx
, rtx
);
651 static bool insn_terminates_group_p (rtx
, enum group_termination
);
652 static bool is_costly_group (rtx
*, rtx
);
653 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
654 static int redefine_groups (FILE *, int, rtx
, rtx
);
655 static int pad_groups (FILE *, int, rtx
, rtx
);
656 static void rs6000_sched_finish (FILE *, int);
657 static int rs6000_use_sched_lookahead (void);
658 static tree
rs6000_builtin_mask_for_load (void);
659 static tree
rs6000_builtin_mul_widen_even (tree
);
660 static tree
rs6000_builtin_mul_widen_odd (tree
);
662 static void def_builtin (int, const char *, tree
, int);
663 static void rs6000_init_builtins (void);
664 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
665 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
666 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
667 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
668 static void altivec_init_builtins (void);
669 static void rs6000_common_init_builtins (void);
670 static void rs6000_init_libfuncs (void);
672 static void enable_mask_for_builtins (struct builtin_description
*, int,
673 enum rs6000_builtins
,
674 enum rs6000_builtins
);
675 static tree
build_opaque_vector_type (tree
, int);
676 static void spe_init_builtins (void);
677 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
678 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
679 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
680 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
681 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
682 static rs6000_stack_t
*rs6000_stack_info (void);
683 static void debug_stack_info (rs6000_stack_t
*);
685 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
686 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
687 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
688 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
689 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
690 static rtx
altivec_expand_predicate_builtin (enum insn_code
,
691 const char *, tree
, rtx
);
692 static rtx
altivec_expand_lv_builtin (enum insn_code
, tree
, rtx
);
693 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
694 static rtx
altivec_expand_vec_init_builtin (tree
, tree
, rtx
);
695 static rtx
altivec_expand_vec_set_builtin (tree
);
696 static rtx
altivec_expand_vec_ext_builtin (tree
, rtx
);
697 static int get_element_number (tree
, tree
);
698 static bool rs6000_handle_option (size_t, const char *, int);
699 static void rs6000_parse_tls_size_option (void);
700 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
701 static int first_altivec_reg_to_save (void);
702 static unsigned int compute_vrsave_mask (void);
703 static void compute_save_world_info (rs6000_stack_t
*info_ptr
);
704 static void is_altivec_return_reg (rtx
, void *);
705 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
706 int easy_vector_constant (rtx
, enum machine_mode
);
707 static bool rs6000_is_opaque_type (tree
);
708 static rtx
rs6000_dwarf_register_span (rtx
);
709 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
710 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
711 static rtx
rs6000_tls_get_addr (void);
712 static rtx
rs6000_got_sym (void);
713 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
714 static const char *rs6000_get_some_local_dynamic_name (void);
715 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
716 static rtx
rs6000_complex_function_value (enum machine_mode
);
717 static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS
*,
718 enum machine_mode
, tree
);
719 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*,
721 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*,
722 tree
, HOST_WIDE_INT
);
723 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*,
726 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*,
729 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, tree
, int, bool);
730 static rtx
rs6000_mixed_function_arg (enum machine_mode
, tree
, int);
731 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
732 static void setup_incoming_varargs (CUMULATIVE_ARGS
*,
733 enum machine_mode
, tree
,
735 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
737 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
739 static const char *invalid_arg_for_unprototyped_fn (tree
, tree
, tree
);
741 static void macho_branch_islands (void);
742 static void add_compiler_branch_island (tree
, tree
, int);
743 static int no_previous_def (tree function_name
);
744 static tree
get_prev_label (tree function_name
);
745 static void rs6000_darwin_file_start (void);
748 static tree
rs6000_build_builtin_va_list (void);
749 static tree
rs6000_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
750 static bool rs6000_must_pass_in_stack (enum machine_mode
, tree
);
751 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
752 static int get_vec_cmp_insn (enum rtx_code
, enum machine_mode
,
754 static rtx
rs6000_emit_vector_compare (enum rtx_code
, rtx
, rtx
,
755 enum machine_mode
, bool *);
756 static int get_vsel_insn (enum machine_mode
);
757 static void rs6000_emit_vector_select (rtx
, rtx
, rtx
, rtx
);
758 static tree
rs6000_stack_protect_fail (void);
760 const int INSN_NOT_AVAILABLE
= -1;
761 static enum machine_mode
rs6000_eh_return_filter_mode (void);
763 /* Hash table stuff for keeping track of TOC entries. */
765 struct toc_hash_struct
GTY(())
767 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
768 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
770 enum machine_mode key_mode
;
774 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
776 /* Default register names. */
777 char rs6000_reg_names
[][8] =
779 "0", "1", "2", "3", "4", "5", "6", "7",
780 "8", "9", "10", "11", "12", "13", "14", "15",
781 "16", "17", "18", "19", "20", "21", "22", "23",
782 "24", "25", "26", "27", "28", "29", "30", "31",
783 "0", "1", "2", "3", "4", "5", "6", "7",
784 "8", "9", "10", "11", "12", "13", "14", "15",
785 "16", "17", "18", "19", "20", "21", "22", "23",
786 "24", "25", "26", "27", "28", "29", "30", "31",
787 "mq", "lr", "ctr","ap",
788 "0", "1", "2", "3", "4", "5", "6", "7",
790 /* AltiVec registers. */
791 "0", "1", "2", "3", "4", "5", "6", "7",
792 "8", "9", "10", "11", "12", "13", "14", "15",
793 "16", "17", "18", "19", "20", "21", "22", "23",
794 "24", "25", "26", "27", "28", "29", "30", "31",
797 "spe_acc", "spefscr",
798 /* Soft frame pointer. */
802 #ifdef TARGET_REGNAMES
803 static const char alt_reg_names
[][8] =
805 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
806 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
807 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
808 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
809 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
810 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
811 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
812 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
813 "mq", "lr", "ctr", "ap",
814 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
816 /* AltiVec registers. */
817 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
818 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
819 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
820 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
823 "spe_acc", "spefscr",
824 /* Soft frame pointer. */
829 #ifndef MASK_STRICT_ALIGN
830 #define MASK_STRICT_ALIGN 0
832 #ifndef TARGET_PROFILE_KERNEL
833 #define TARGET_PROFILE_KERNEL 0
836 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
837 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
839 /* Initialize the GCC target structure. */
840 #undef TARGET_ATTRIBUTE_TABLE
841 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
842 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
843 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
845 #undef TARGET_ASM_ALIGNED_DI_OP
846 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
848 /* Default unaligned ops are only provided for ELF. Find the ops needed
849 for non-ELF systems. */
850 #ifndef OBJECT_FORMAT_ELF
852 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
854 #undef TARGET_ASM_UNALIGNED_HI_OP
855 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
856 #undef TARGET_ASM_UNALIGNED_SI_OP
857 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
858 #undef TARGET_ASM_UNALIGNED_DI_OP
859 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
862 #undef TARGET_ASM_UNALIGNED_HI_OP
863 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
864 #undef TARGET_ASM_UNALIGNED_SI_OP
865 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
866 #undef TARGET_ASM_UNALIGNED_DI_OP
867 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
868 #undef TARGET_ASM_ALIGNED_DI_OP
869 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
873 /* This hook deals with fixups for relocatable code and DI-mode objects
875 #undef TARGET_ASM_INTEGER
876 #define TARGET_ASM_INTEGER rs6000_assemble_integer
878 #ifdef HAVE_GAS_HIDDEN
879 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
880 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
883 #undef TARGET_HAVE_TLS
884 #define TARGET_HAVE_TLS HAVE_AS_TLS
886 #undef TARGET_CANNOT_FORCE_CONST_MEM
887 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
889 #undef TARGET_ASM_FUNCTION_PROLOGUE
890 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
891 #undef TARGET_ASM_FUNCTION_EPILOGUE
892 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
894 #undef TARGET_SCHED_VARIABLE_ISSUE
895 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
897 #undef TARGET_SCHED_ISSUE_RATE
898 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
899 #undef TARGET_SCHED_ADJUST_COST
900 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
901 #undef TARGET_SCHED_ADJUST_PRIORITY
902 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
903 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
904 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
905 #undef TARGET_SCHED_FINISH
906 #define TARGET_SCHED_FINISH rs6000_sched_finish
908 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
909 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
911 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
912 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
914 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
915 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
916 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
917 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
919 #undef TARGET_INIT_BUILTINS
920 #define TARGET_INIT_BUILTINS rs6000_init_builtins
922 #undef TARGET_EXPAND_BUILTIN
923 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
925 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
926 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
928 #undef TARGET_INIT_LIBFUNCS
929 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
932 #undef TARGET_BINDS_LOCAL_P
933 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
936 #undef TARGET_ASM_OUTPUT_MI_THUNK
937 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
939 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
940 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
942 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
943 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
945 #undef TARGET_INVALID_WITHIN_DOLOOP
946 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
948 #undef TARGET_RTX_COSTS
949 #define TARGET_RTX_COSTS rs6000_rtx_costs
950 #undef TARGET_ADDRESS_COST
951 #define TARGET_ADDRESS_COST hook_int_rtx_0
953 #undef TARGET_VECTOR_OPAQUE_P
954 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
956 #undef TARGET_DWARF_REGISTER_SPAN
957 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
959 /* On rs6000, function arguments are promoted, as are function return
961 #undef TARGET_PROMOTE_FUNCTION_ARGS
962 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
963 #undef TARGET_PROMOTE_FUNCTION_RETURN
964 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
966 #undef TARGET_RETURN_IN_MEMORY
967 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
969 #undef TARGET_SETUP_INCOMING_VARARGS
970 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
972 /* Always strict argument naming on rs6000. */
973 #undef TARGET_STRICT_ARGUMENT_NAMING
974 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
975 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
976 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
977 #undef TARGET_SPLIT_COMPLEX_ARG
978 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
979 #undef TARGET_MUST_PASS_IN_STACK
980 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
981 #undef TARGET_PASS_BY_REFERENCE
982 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
983 #undef TARGET_ARG_PARTIAL_BYTES
984 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
986 #undef TARGET_BUILD_BUILTIN_VA_LIST
987 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
989 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
990 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
992 #undef TARGET_EH_RETURN_FILTER_MODE
993 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
995 #undef TARGET_VECTOR_MODE_SUPPORTED_P
996 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
998 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
999 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1001 #undef TARGET_HANDLE_OPTION
1002 #define TARGET_HANDLE_OPTION rs6000_handle_option
1004 #undef TARGET_DEFAULT_TARGET_FLAGS
1005 #define TARGET_DEFAULT_TARGET_FLAGS \
1006 (TARGET_DEFAULT | MASK_SCHED_PROLOG)
1008 #undef TARGET_STACK_PROTECT_FAIL
1009 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1011 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1012 The PowerPC architecture requires only weak consistency among
1013 processors--that is, memory accesses between processors need not be
1014 sequentially consistent and memory accesses among processors can occur
1015 in any order. The ability to order memory accesses weakly provides
1016 opportunities for more efficient use of the system bus. Unless a
1017 dependency exists, the 604e allows read operations to precede store
1019 #undef TARGET_RELAXED_ORDERING
1020 #define TARGET_RELAXED_ORDERING true
1023 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1024 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1027 struct gcc_target targetm
= TARGET_INITIALIZER
;
1030 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1033 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1035 /* The GPRs can hold any mode, but values bigger than one register
1036 cannot go past R31. */
1037 if (INT_REGNO_P (regno
))
1038 return INT_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1);
1040 /* The float registers can only hold floating modes and DImode. */
1041 if (FP_REGNO_P (regno
))
1043 (SCALAR_FLOAT_MODE_P (mode
)
1044 && FP_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1))
1045 || (GET_MODE_CLASS (mode
) == MODE_INT
1046 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
);
1048 /* The CR register can only hold CC modes. */
1049 if (CR_REGNO_P (regno
))
1050 return GET_MODE_CLASS (mode
) == MODE_CC
;
1052 if (XER_REGNO_P (regno
))
1053 return mode
== PSImode
;
1055 /* AltiVec only in AldyVec registers. */
1056 if (ALTIVEC_REGNO_P (regno
))
1057 return ALTIVEC_VECTOR_MODE (mode
);
1059 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1060 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1063 /* We cannot put TImode anywhere except general register and it must be
1064 able to fit within the register set. */
1066 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1069 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1071 rs6000_init_hard_regno_mode_ok (void)
1075 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1076 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1077 if (rs6000_hard_regno_mode_ok (r
, m
))
1078 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
1081 /* If not otherwise specified by a target, make 'long double' equivalent to
1084 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1085 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1088 /* Override command line options. Mostly we process the processor
1089 type and sometimes adjust other TARGET_ options. */
1092 rs6000_override_options (const char *default_cpu
)
1095 struct rs6000_cpu_select
*ptr
;
1098 /* Simplifications for entries below. */
1101 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1102 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1105 /* This table occasionally claims that a processor does not support
1106 a particular feature even though it does, but the feature is slower
1107 than the alternative. Thus, it shouldn't be relied on as a
1108 complete description of the processor's support.
1110 Please keep this list in order, and don't forget to update the
1111 documentation in invoke.texi when adding a new processor or
1115 const char *const name
; /* Canonical processor name. */
1116 const enum processor_type processor
; /* Processor type enum value. */
1117 const int target_enable
; /* Target flags to enable. */
1118 } const processor_target_table
[]
1119 = {{"401", PROCESSOR_PPC403
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1120 {"403", PROCESSOR_PPC403
,
1121 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_STRICT_ALIGN
},
1122 {"405", PROCESSOR_PPC405
,
1123 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
},
1124 {"405fp", PROCESSOR_PPC405
, POWERPC_BASE_MASK
| MASK_MULHW
},
1125 {"440", PROCESSOR_PPC440
,
1126 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
},
1127 {"440fp", PROCESSOR_PPC440
, POWERPC_BASE_MASK
| MASK_MULHW
},
1128 {"505", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
},
1129 {"601", PROCESSOR_PPC601
,
1130 MASK_POWER
| POWERPC_BASE_MASK
| MASK_MULTIPLE
| MASK_STRING
},
1131 {"602", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1132 {"603", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1133 {"603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1134 {"604", PROCESSOR_PPC604
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1135 {"604e", PROCESSOR_PPC604e
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1136 {"620", PROCESSOR_PPC620
,
1137 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1138 {"630", PROCESSOR_PPC630
,
1139 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1140 {"740", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1141 {"7400", PROCESSOR_PPC7400
, POWERPC_7400_MASK
},
1142 {"7450", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1143 {"750", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1144 {"801", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1145 {"821", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1146 {"823", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1147 {"8540", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1148 /* 8548 has a dummy entry for now. */
1149 {"8548", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1150 {"860", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1151 {"970", PROCESSOR_POWER4
,
1152 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1153 {"common", PROCESSOR_COMMON
, MASK_NEW_MNEMONICS
},
1154 {"ec603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1155 {"G3", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1156 {"G4", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1157 {"G5", PROCESSOR_POWER4
,
1158 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1159 {"power", PROCESSOR_POWER
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1160 {"power2", PROCESSOR_POWER
,
1161 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1162 {"power3", PROCESSOR_PPC630
,
1163 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1164 {"power4", PROCESSOR_POWER4
,
1165 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1166 {"power5", PROCESSOR_POWER5
,
1167 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GFXOPT
1168 | MASK_MFCRF
| MASK_POPCNTB
},
1169 {"power5+", PROCESSOR_POWER5
,
1170 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GFXOPT
1171 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
},
1172 {"powerpc", PROCESSOR_POWERPC
, POWERPC_BASE_MASK
},
1173 {"powerpc64", PROCESSOR_POWERPC64
,
1174 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1175 {"rios", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1176 {"rios1", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1177 {"rios2", PROCESSOR_RIOS2
,
1178 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1179 {"rsc", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1180 {"rsc1", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1181 {"rs64", PROCESSOR_RS64A
,
1182 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
}
1185 const size_t ptt_size
= ARRAY_SIZE (processor_target_table
);
1187 /* Some OSs don't support saving the high part of 64-bit registers on
1188 context switch. Other OSs don't support saving Altivec registers.
1189 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1190 settings; if the user wants either, the user must explicitly specify
1191 them and we won't interfere with the user's specification. */
1194 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1195 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
1196 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1197 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
| MASK_MULHW
)
1200 rs6000_init_hard_regno_mode_ok ();
1202 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
1203 #ifdef OS_MISSING_POWERPC64
1204 if (OS_MISSING_POWERPC64
)
1205 set_masks
&= ~MASK_POWERPC64
;
1207 #ifdef OS_MISSING_ALTIVEC
1208 if (OS_MISSING_ALTIVEC
)
1209 set_masks
&= ~MASK_ALTIVEC
;
1212 /* Don't override by the processor default if given explicitly. */
1213 set_masks
&= ~target_flags_explicit
;
1215 /* Identify the processor type. */
1216 rs6000_select
[0].string
= default_cpu
;
1217 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
1219 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1221 ptr
= &rs6000_select
[i
];
1222 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1224 for (j
= 0; j
< ptt_size
; j
++)
1225 if (! strcmp (ptr
->string
, processor_target_table
[j
].name
))
1227 if (ptr
->set_tune_p
)
1228 rs6000_cpu
= processor_target_table
[j
].processor
;
1230 if (ptr
->set_arch_p
)
1232 target_flags
&= ~set_masks
;
1233 target_flags
|= (processor_target_table
[j
].target_enable
1240 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1247 /* If we are optimizing big endian systems for space, use the load/store
1248 multiple and string instructions. */
1249 if (BYTES_BIG_ENDIAN
&& optimize_size
)
1250 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
1252 /* Don't allow -mmultiple or -mstring on little endian systems
1253 unless the cpu is a 750, because the hardware doesn't support the
1254 instructions used in little endian mode, and causes an alignment
1255 trap. The 750 does not cause an alignment trap (except when the
1256 target is unaligned). */
1258 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
1260 if (TARGET_MULTIPLE
)
1262 target_flags
&= ~MASK_MULTIPLE
;
1263 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
1264 warning (0, "-mmultiple is not supported on little endian systems");
1269 target_flags
&= ~MASK_STRING
;
1270 if ((target_flags_explicit
& MASK_STRING
) != 0)
1271 warning (0, "-mstring is not supported on little endian systems");
1275 /* Set debug flags */
1276 if (rs6000_debug_name
)
1278 if (! strcmp (rs6000_debug_name
, "all"))
1279 rs6000_debug_stack
= rs6000_debug_arg
= 1;
1280 else if (! strcmp (rs6000_debug_name
, "stack"))
1281 rs6000_debug_stack
= 1;
1282 else if (! strcmp (rs6000_debug_name
, "arg"))
1283 rs6000_debug_arg
= 1;
1285 error ("unknown -mdebug-%s switch", rs6000_debug_name
);
1288 if (rs6000_traceback_name
)
1290 if (! strncmp (rs6000_traceback_name
, "full", 4))
1291 rs6000_traceback
= traceback_full
;
1292 else if (! strncmp (rs6000_traceback_name
, "part", 4))
1293 rs6000_traceback
= traceback_part
;
1294 else if (! strncmp (rs6000_traceback_name
, "no", 2))
1295 rs6000_traceback
= traceback_none
;
1297 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1298 rs6000_traceback_name
);
1301 if (!rs6000_explicit_options
.long_double
)
1302 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1304 /* Set Altivec ABI as default for powerpc64 linux. */
1305 if (TARGET_ELF
&& TARGET_64BIT
)
1307 rs6000_altivec_abi
= 1;
1308 TARGET_ALTIVEC_VRSAVE
= 1;
1311 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1312 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1314 rs6000_darwin64_abi
= 1;
1316 darwin_one_byte_bool
= 1;
1318 /* Default to natural alignment, for better performance. */
1319 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1322 /* Handle -mtls-size option. */
1323 rs6000_parse_tls_size_option ();
1325 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1326 SUBTARGET_OVERRIDE_OPTIONS
;
1328 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1329 SUBSUBTARGET_OVERRIDE_OPTIONS
;
1331 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1332 SUB3TARGET_OVERRIDE_OPTIONS
;
1338 error ("AltiVec and E500 instructions cannot coexist");
1340 /* The e500 does not have string instructions, and we set
1341 MASK_STRING above when optimizing for size. */
1342 if ((target_flags
& MASK_STRING
) != 0)
1343 target_flags
= target_flags
& ~MASK_STRING
;
1345 else if (rs6000_select
[1].string
!= NULL
)
1347 /* For the powerpc-eabispe configuration, we set all these by
1348 default, so let's unset them if we manually set another
1349 CPU that is not the E500. */
1350 if (!rs6000_explicit_options
.abi
)
1352 if (!rs6000_explicit_options
.spe
)
1354 if (!rs6000_explicit_options
.float_gprs
)
1355 rs6000_float_gprs
= 0;
1356 if (!rs6000_explicit_options
.isel
)
1358 if (!rs6000_explicit_options
.long_double
)
1359 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1362 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
1363 && rs6000_cpu
!= PROCESSOR_POWER5
);
1364 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
1365 || rs6000_cpu
== PROCESSOR_POWER5
);
1367 rs6000_sched_restricted_insns_priority
1368 = (rs6000_sched_groups
? 1 : 0);
1370 /* Handle -msched-costly-dep option. */
1371 rs6000_sched_costly_dep
1372 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
1374 if (rs6000_sched_costly_dep_str
)
1376 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
1377 rs6000_sched_costly_dep
= no_dep_costly
;
1378 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
1379 rs6000_sched_costly_dep
= all_deps_costly
;
1380 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
1381 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
1382 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
1383 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
1385 rs6000_sched_costly_dep
= atoi (rs6000_sched_costly_dep_str
);
1388 /* Handle -minsert-sched-nops option. */
1389 rs6000_sched_insert_nops
1390 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
1392 if (rs6000_sched_insert_nops_str
)
1394 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
1395 rs6000_sched_insert_nops
= sched_finish_none
;
1396 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
1397 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
1398 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
1399 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
1401 rs6000_sched_insert_nops
= atoi (rs6000_sched_insert_nops_str
);
1404 #ifdef TARGET_REGNAMES
1405 /* If the user desires alternate register names, copy in the
1406 alternate names now. */
1407 if (TARGET_REGNAMES
)
1408 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
1411 /* Set aix_struct_return last, after the ABI is determined.
1412 If -maix-struct-return or -msvr4-struct-return was explicitly
1413 used, don't override with the ABI default. */
1414 if (!rs6000_explicit_options
.aix_struct_ret
)
1415 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
1417 if (TARGET_LONG_DOUBLE_128
1418 && (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
))
1419 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
1422 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
1424 /* We can only guarantee the availability of DI pseudo-ops when
1425 assembling for 64-bit targets. */
1428 targetm
.asm_out
.aligned_op
.di
= NULL
;
1429 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1432 /* Set branch target alignment, if not optimizing for size. */
1435 if (rs6000_sched_groups
)
1437 if (align_functions
<= 0)
1438 align_functions
= 16;
1439 if (align_jumps
<= 0)
1441 if (align_loops
<= 0)
1444 if (align_jumps_max_skip
<= 0)
1445 align_jumps_max_skip
= 15;
1446 if (align_loops_max_skip
<= 0)
1447 align_loops_max_skip
= 15;
1450 /* Arrange to save and restore machine status around nested functions. */
1451 init_machine_status
= rs6000_init_machine_status
;
1453 /* We should always be splitting complex arguments, but we can't break
1454 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1455 if (DEFAULT_ABI
!= ABI_AIX
)
1456 targetm
.calls
.split_complex_arg
= NULL
;
1458 /* Initialize rs6000_cost with the appropriate target costs. */
1460 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
1464 case PROCESSOR_RIOS1
:
1465 rs6000_cost
= &rios1_cost
;
1468 case PROCESSOR_RIOS2
:
1469 rs6000_cost
= &rios2_cost
;
1472 case PROCESSOR_RS64A
:
1473 rs6000_cost
= &rs64a_cost
;
1476 case PROCESSOR_MPCCORE
:
1477 rs6000_cost
= &mpccore_cost
;
1480 case PROCESSOR_PPC403
:
1481 rs6000_cost
= &ppc403_cost
;
1484 case PROCESSOR_PPC405
:
1485 rs6000_cost
= &ppc405_cost
;
1488 case PROCESSOR_PPC440
:
1489 rs6000_cost
= &ppc440_cost
;
1492 case PROCESSOR_PPC601
:
1493 rs6000_cost
= &ppc601_cost
;
1496 case PROCESSOR_PPC603
:
1497 rs6000_cost
= &ppc603_cost
;
1500 case PROCESSOR_PPC604
:
1501 rs6000_cost
= &ppc604_cost
;
1504 case PROCESSOR_PPC604e
:
1505 rs6000_cost
= &ppc604e_cost
;
1508 case PROCESSOR_PPC620
:
1509 rs6000_cost
= &ppc620_cost
;
1512 case PROCESSOR_PPC630
:
1513 rs6000_cost
= &ppc630_cost
;
1516 case PROCESSOR_PPC750
:
1517 case PROCESSOR_PPC7400
:
1518 rs6000_cost
= &ppc750_cost
;
1521 case PROCESSOR_PPC7450
:
1522 rs6000_cost
= &ppc7450_cost
;
1525 case PROCESSOR_PPC8540
:
1526 rs6000_cost
= &ppc8540_cost
;
1529 case PROCESSOR_POWER4
:
1530 case PROCESSOR_POWER5
:
1531 rs6000_cost
= &power4_cost
;
1539 /* Implement targetm.vectorize.builtin_mask_for_load. */
1541 rs6000_builtin_mask_for_load (void)
1544 return altivec_builtin_mask_for_load
;
1549 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1551 rs6000_builtin_mul_widen_even (tree type
)
1553 if (!TARGET_ALTIVEC
)
1556 switch (TYPE_MODE (type
))
1559 return TYPE_UNSIGNED (type
) ?
1560 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUH
] :
1561 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESH
];
1563 return TYPE_UNSIGNED (type
) ?
1564 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUB
] :
1565 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESB
];
1571 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1573 rs6000_builtin_mul_widen_odd (tree type
)
1575 if (!TARGET_ALTIVEC
)
1578 switch (TYPE_MODE (type
))
1581 return TYPE_UNSIGNED (type
) ?
1582 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUH
] :
1583 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSH
];
1585 return TYPE_UNSIGNED (type
) ?
1586 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUB
] :
1587 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSB
];
1594 /* Handle generic options of the form -mfoo=yes/no.
1595 NAME is the option name.
1596 VALUE is the option value.
1597 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1598 whether the option value is 'yes' or 'no' respectively. */
1600 rs6000_parse_yes_no_option (const char *name
, const char *value
, int *flag
)
1604 else if (!strcmp (value
, "yes"))
1606 else if (!strcmp (value
, "no"))
1609 error ("unknown -m%s= option specified: '%s'", name
, value
);
1612 /* Validate and record the size specified with the -mtls-size option. */
1615 rs6000_parse_tls_size_option (void)
1617 if (rs6000_tls_size_string
== 0)
1619 else if (strcmp (rs6000_tls_size_string
, "16") == 0)
1620 rs6000_tls_size
= 16;
1621 else if (strcmp (rs6000_tls_size_string
, "32") == 0)
1622 rs6000_tls_size
= 32;
1623 else if (strcmp (rs6000_tls_size_string
, "64") == 0)
1624 rs6000_tls_size
= 64;
1626 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string
);
1630 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
1632 if (DEFAULT_ABI
== ABI_DARWIN
)
1633 /* The Darwin libraries never set errno, so we might as well
1634 avoid calling them when that's the only reason we would. */
1635 flag_errno_math
= 0;
1637 /* Double growth factor to counter reduced min jump length. */
1638 set_param_value ("max-grow-copy-bb-insns", 16);
1641 /* Implement TARGET_HANDLE_OPTION. */
1644 rs6000_handle_option (size_t code
, const char *arg
, int value
)
1649 target_flags
&= ~(MASK_POWER
| MASK_POWER2
1650 | MASK_MULTIPLE
| MASK_STRING
);
1651 target_flags_explicit
|= (MASK_POWER
| MASK_POWER2
1652 | MASK_MULTIPLE
| MASK_STRING
);
1654 case OPT_mno_powerpc
:
1655 target_flags
&= ~(MASK_POWERPC
| MASK_PPC_GPOPT
1656 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
1657 target_flags_explicit
|= (MASK_POWERPC
| MASK_PPC_GPOPT
1658 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
1661 target_flags
&= ~(MASK_MINIMAL_TOC
| MASK_NO_FP_IN_TOC
1662 | MASK_NO_SUM_IN_TOC
);
1663 target_flags_explicit
|= (MASK_MINIMAL_TOC
| MASK_NO_FP_IN_TOC
1664 | MASK_NO_SUM_IN_TOC
);
1665 #ifdef TARGET_USES_SYSV4_OPT
1666 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1667 just the same as -mminimal-toc. */
1668 target_flags
|= MASK_MINIMAL_TOC
;
1669 target_flags_explicit
|= MASK_MINIMAL_TOC
;
1673 #ifdef TARGET_USES_SYSV4_OPT
1675 /* Make -mtoc behave like -mminimal-toc. */
1676 target_flags
|= MASK_MINIMAL_TOC
;
1677 target_flags_explicit
|= MASK_MINIMAL_TOC
;
1681 #ifdef TARGET_USES_AIX64_OPT
1686 target_flags
|= MASK_POWERPC64
| MASK_POWERPC
;
1687 target_flags
|= ~target_flags_explicit
& MASK_PPC_GFXOPT
;
1688 target_flags_explicit
|= MASK_POWERPC64
| MASK_POWERPC
;
1691 #ifdef TARGET_USES_AIX64_OPT
1696 target_flags
&= ~MASK_POWERPC64
;
1697 target_flags_explicit
|= MASK_POWERPC64
;
1700 case OPT_minsert_sched_nops_
:
1701 rs6000_sched_insert_nops_str
= arg
;
1704 case OPT_mminimal_toc
:
1707 target_flags
&= ~(MASK_NO_FP_IN_TOC
| MASK_NO_SUM_IN_TOC
);
1708 target_flags_explicit
|= (MASK_NO_FP_IN_TOC
| MASK_NO_SUM_IN_TOC
);
1715 target_flags
|= (MASK_MULTIPLE
| MASK_STRING
);
1716 target_flags_explicit
|= (MASK_MULTIPLE
| MASK_STRING
);
1723 target_flags
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
1724 target_flags_explicit
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
1728 case OPT_mpowerpc_gpopt
:
1729 case OPT_mpowerpc_gfxopt
:
1732 target_flags
|= MASK_POWERPC
;
1733 target_flags_explicit
|= MASK_POWERPC
;
1737 case OPT_maix_struct_return
:
1738 case OPT_msvr4_struct_return
:
1739 rs6000_explicit_options
.aix_struct_ret
= true;
1743 rs6000_parse_yes_no_option ("vrsave", arg
, &(TARGET_ALTIVEC_VRSAVE
));
1747 rs6000_explicit_options
.isel
= true;
1748 rs6000_parse_yes_no_option ("isel", arg
, &(rs6000_isel
));
1752 rs6000_explicit_options
.spe
= true;
1753 rs6000_parse_yes_no_option ("spe", arg
, &(rs6000_spe
));
1754 /* No SPE means 64-bit long doubles, even if an E500. */
1756 rs6000_long_double_type_size
= 64;
1760 rs6000_debug_name
= arg
;
1763 #ifdef TARGET_USES_SYSV4_OPT
1765 rs6000_abi_name
= arg
;
1769 rs6000_sdata_name
= arg
;
1772 case OPT_mtls_size_
:
1773 rs6000_tls_size_string
= arg
;
1776 case OPT_mrelocatable
:
1779 target_flags
|= MASK_MINIMAL_TOC
| MASK_NO_FP_IN_TOC
;
1780 target_flags_explicit
|= MASK_MINIMAL_TOC
| MASK_NO_FP_IN_TOC
;
1784 case OPT_mrelocatable_lib
:
1787 target_flags
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
1788 | MASK_NO_FP_IN_TOC
;
1789 target_flags_explicit
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
1790 | MASK_NO_FP_IN_TOC
;
1794 target_flags
&= ~MASK_RELOCATABLE
;
1795 target_flags_explicit
|= MASK_RELOCATABLE
;
1801 rs6000_explicit_options
.abi
= true;
1802 if (!strcmp (arg
, "altivec"))
1804 rs6000_altivec_abi
= 1;
1807 else if (! strcmp (arg
, "no-altivec"))
1808 rs6000_altivec_abi
= 0;
1809 else if (! strcmp (arg
, "spe"))
1812 rs6000_altivec_abi
= 0;
1813 if (!TARGET_SPE_ABI
)
1814 error ("not configured for ABI: '%s'", arg
);
1816 else if (! strcmp (arg
, "no-spe"))
1819 /* These are here for testing during development only, do not
1820 document in the manual please. */
1821 else if (! strcmp (arg
, "d64"))
1823 rs6000_darwin64_abi
= 1;
1824 warning (0, "Using darwin64 ABI");
1826 else if (! strcmp (arg
, "d32"))
1828 rs6000_darwin64_abi
= 0;
1829 warning (0, "Using old darwin ABI");
1834 error ("unknown ABI specified: '%s'", arg
);
1840 rs6000_select
[1].string
= arg
;
1844 rs6000_select
[2].string
= arg
;
1847 case OPT_mtraceback_
:
1848 rs6000_traceback_name
= arg
;
1851 case OPT_mfloat_gprs_
:
1852 rs6000_explicit_options
.float_gprs
= true;
1853 if (! strcmp (arg
, "yes") || ! strcmp (arg
, "single"))
1854 rs6000_float_gprs
= 1;
1855 else if (! strcmp (arg
, "double"))
1856 rs6000_float_gprs
= 2;
1857 else if (! strcmp (arg
, "no"))
1858 rs6000_float_gprs
= 0;
1861 error ("invalid option for -mfloat-gprs: '%s'", arg
);
1866 case OPT_mlong_double_
:
1867 rs6000_explicit_options
.long_double
= true;
1868 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1869 if (value
!= 64 && value
!= 128)
1871 error ("Unknown switch -mlong-double-%s", arg
);
1872 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1876 rs6000_long_double_type_size
= value
;
1879 case OPT_msched_costly_dep_
:
1880 rs6000_sched_costly_dep_str
= arg
;
1884 rs6000_explicit_options
.alignment
= true;
1885 if (! strcmp (arg
, "power"))
1887 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1888 some C library functions, so warn about it. The flag may be
1889 useful for performance studies from time to time though, so
1890 don't disable it entirely. */
1891 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1892 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1893 " it is incompatible with the installed C and C++ libraries");
1894 rs6000_alignment_flags
= MASK_ALIGN_POWER
;
1896 else if (! strcmp (arg
, "natural"))
1897 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1900 error ("unknown -malign-XXXXX option specified: '%s'", arg
);
1908 /* Do anything needed at the start of the asm file. */
1911 rs6000_file_start (void)
1915 const char *start
= buffer
;
1916 struct rs6000_cpu_select
*ptr
;
1917 const char *default_cpu
= TARGET_CPU_DEFAULT
;
1918 FILE *file
= asm_out_file
;
1920 default_file_start ();
1922 #ifdef TARGET_BI_ARCH
1923 if ((TARGET_DEFAULT
^ target_flags
) & MASK_64BIT
)
1927 if (flag_verbose_asm
)
1929 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
1930 rs6000_select
[0].string
= default_cpu
;
1932 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1934 ptr
= &rs6000_select
[i
];
1935 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1937 fprintf (file
, "%s %s%s", start
, ptr
->name
, ptr
->string
);
1942 if (PPC405_ERRATUM77
)
1944 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
1948 #ifdef USING_ELFOS_H
1949 switch (rs6000_sdata
)
1951 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
1952 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
1953 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
1954 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
1957 if (rs6000_sdata
&& g_switch_value
)
1959 fprintf (file
, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED
, start
,
1969 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
1971 switch_to_section (toc_section
);
1972 switch_to_section (text_section
);
1977 /* Return nonzero if this function is known to have a null epilogue. */
1980 direct_return (void)
1982 if (reload_completed
)
1984 rs6000_stack_t
*info
= rs6000_stack_info ();
1986 if (info
->first_gp_reg_save
== 32
1987 && info
->first_fp_reg_save
== 64
1988 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
1989 && ! info
->lr_save_p
1990 && ! info
->cr_save_p
1991 && info
->vrsave_mask
== 0
1999 /* Return the number of instructions it takes to form a constant in an
2000 integer register. */
2003 num_insns_constant_wide (HOST_WIDE_INT value
)
2005 /* signed constant loadable with {cal|addi} */
2006 if (CONST_OK_FOR_LETTER_P (value
, 'I'))
2009 /* constant loadable with {cau|addis} */
2010 else if (CONST_OK_FOR_LETTER_P (value
, 'L'))
2013 #if HOST_BITS_PER_WIDE_INT == 64
2014 else if (TARGET_POWERPC64
)
2016 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2017 HOST_WIDE_INT high
= value
>> 31;
2019 if (high
== 0 || high
== -1)
2025 return num_insns_constant_wide (high
) + 1;
2027 return (num_insns_constant_wide (high
)
2028 + num_insns_constant_wide (low
) + 1);
2037 num_insns_constant (rtx op
, enum machine_mode mode
)
2039 HOST_WIDE_INT low
, high
;
2041 switch (GET_CODE (op
))
2044 #if HOST_BITS_PER_WIDE_INT == 64
2045 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
2046 && mask64_operand (op
, mode
))
2050 return num_insns_constant_wide (INTVAL (op
));
2058 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2059 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2060 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
2063 if (mode
== VOIDmode
|| mode
== DImode
)
2065 high
= CONST_DOUBLE_HIGH (op
);
2066 low
= CONST_DOUBLE_LOW (op
);
2073 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2074 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
2075 high
= l
[WORDS_BIG_ENDIAN
== 0];
2076 low
= l
[WORDS_BIG_ENDIAN
!= 0];
2080 return (num_insns_constant_wide (low
)
2081 + num_insns_constant_wide (high
));
2084 if ((high
== 0 && low
>= 0)
2085 || (high
== -1 && low
< 0))
2086 return num_insns_constant_wide (low
);
2088 else if (mask64_operand (op
, mode
))
2092 return num_insns_constant_wide (high
) + 1;
2095 return (num_insns_constant_wide (high
)
2096 + num_insns_constant_wide (low
) + 1);
2105 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2106 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2107 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2108 all items are set to the same value and contain COPIES replicas of the
2109 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2110 operand and the others are set to the value of the operand's msb. */
2113 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
2115 enum machine_mode mode
= GET_MODE (op
);
2116 enum machine_mode inner
= GET_MODE_INNER (mode
);
2119 unsigned nunits
= GET_MODE_NUNITS (mode
);
2120 unsigned bitsize
= GET_MODE_BITSIZE (inner
);
2121 unsigned mask
= GET_MODE_MASK (inner
);
2123 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
2124 HOST_WIDE_INT val
= INTVAL (last
);
2125 HOST_WIDE_INT splat_val
= val
;
2126 HOST_WIDE_INT msb_val
= val
> 0 ? 0 : -1;
2128 /* Construct the value to be splatted, if possible. If not, return 0. */
2129 for (i
= 2; i
<= copies
; i
*= 2)
2131 HOST_WIDE_INT small_val
;
2133 small_val
= splat_val
>> bitsize
;
2135 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
2137 splat_val
= small_val
;
2140 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2141 if (EASY_VECTOR_15 (splat_val
))
2144 /* Also check if we can splat, and then add the result to itself. Do so if
2145 the value is positive, of if the splat instruction is using OP's mode;
2146 for splat_val < 0, the splat and the add should use the same mode. */
2147 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
2148 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
2154 /* Check if VAL is present in every STEP-th element, and the
2155 other elements are filled with its most significant bit. */
2156 for (i
= 0; i
< nunits
- 1; ++i
)
2158 HOST_WIDE_INT desired_val
;
2159 if (((i
+ 1) & (step
- 1)) == 0)
2162 desired_val
= msb_val
;
2164 if (desired_val
!= INTVAL (CONST_VECTOR_ELT (op
, i
)))
2172 /* Return true if OP is of the given MODE and can be synthesized
2173 with a vspltisb, vspltish or vspltisw. */
2176 easy_altivec_constant (rtx op
, enum machine_mode mode
)
2178 unsigned step
, copies
;
2180 if (mode
== VOIDmode
)
2181 mode
= GET_MODE (op
);
2182 else if (mode
!= GET_MODE (op
))
2185 /* Start with a vspltisw. */
2186 step
= GET_MODE_NUNITS (mode
) / 4;
2189 if (vspltis_constant (op
, step
, copies
))
2192 /* Then try with a vspltish. */
2198 if (vspltis_constant (op
, step
, copies
))
2201 /* And finally a vspltisb. */
2207 if (vspltis_constant (op
, step
, copies
))
2213 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2214 result is OP. Abort if it is not possible. */
2217 gen_easy_altivec_constant (rtx op
)
2219 enum machine_mode mode
= GET_MODE (op
);
2220 int nunits
= GET_MODE_NUNITS (mode
);
2221 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
2222 unsigned step
= nunits
/ 4;
2223 unsigned copies
= 1;
2225 /* Start with a vspltisw. */
2226 if (vspltis_constant (op
, step
, copies
))
2227 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, last
));
2229 /* Then try with a vspltish. */
2235 if (vspltis_constant (op
, step
, copies
))
2236 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, last
));
2238 /* And finally a vspltisb. */
2244 if (vspltis_constant (op
, step
, copies
))
2245 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, last
));
2251 output_vec_const_move (rtx
*operands
)
2254 enum machine_mode mode
;
2259 mode
= GET_MODE (dest
);
2264 if (zero_constant (vec
, mode
))
2265 return "vxor %0,%0,%0";
2267 splat_vec
= gen_easy_altivec_constant (vec
);
2268 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
2269 operands
[1] = XEXP (splat_vec
, 0);
2270 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
2273 switch (GET_MODE (splat_vec
))
2276 return "vspltisw %0,%1";
2279 return "vspltish %0,%1";
2282 return "vspltisb %0,%1";
2289 gcc_assert (TARGET_SPE
);
2291 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2292 pattern of V1DI, V4HI, and V2SF.
2294 FIXME: We should probably return # and add post reload
2295 splitters for these, but this way is so easy ;-). */
2296 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
2297 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
2298 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
2299 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
2301 return "li %0,%1\n\tevmergelo %0,%0,%0";
2303 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2306 /* Initialize vector TARGET to VALS. */
2309 rs6000_expand_vector_init (rtx target
, rtx vals
)
2311 enum machine_mode mode
= GET_MODE (target
);
2312 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
2313 int n_elts
= GET_MODE_NUNITS (mode
);
2314 int n_var
= 0, one_var
= -1;
2315 bool all_same
= true, all_const_zero
= true;
2319 for (i
= 0; i
< n_elts
; ++i
)
2321 x
= XVECEXP (vals
, 0, i
);
2322 if (!CONSTANT_P (x
))
2323 ++n_var
, one_var
= i
;
2324 else if (x
!= CONST0_RTX (inner_mode
))
2325 all_const_zero
= false;
2327 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
2333 if (mode
!= V4SFmode
&& all_const_zero
)
2335 /* Zero register. */
2336 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2337 gen_rtx_XOR (mode
, target
, target
)));
2340 else if (mode
!= V4SFmode
&& easy_vector_constant (vals
, mode
))
2342 /* Splat immediate. */
2343 emit_insn (gen_rtx_SET (VOIDmode
, target
, vals
));
2347 ; /* Splat vector element. */
2350 /* Load from constant pool. */
2351 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
2356 /* Store value to stack temp. Load vector element. Splat. */
2359 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
2360 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
2361 XVECEXP (vals
, 0, 0));
2362 x
= gen_rtx_UNSPEC (VOIDmode
,
2363 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
2364 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
2366 gen_rtx_SET (VOIDmode
,
2369 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
2370 gen_rtx_PARALLEL (VOIDmode
,
2371 gen_rtvec (1, const0_rtx
)));
2372 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2373 gen_rtx_VEC_DUPLICATE (mode
, x
)));
2377 /* One field is non-constant. Load constant then overwrite
2381 rtx copy
= copy_rtx (vals
);
2383 /* Load constant part of vector, substitute neighboring value for
2385 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
2386 rs6000_expand_vector_init (target
, copy
);
2388 /* Insert variable. */
2389 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
2393 /* Construct the vector in memory one field at a time
2394 and load the whole vector. */
2395 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
2396 for (i
= 0; i
< n_elts
; i
++)
2397 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
2398 i
* GET_MODE_SIZE (inner_mode
)),
2399 XVECEXP (vals
, 0, i
));
2400 emit_move_insn (target
, mem
);
2403 /* Set field ELT of TARGET to VAL. */
2406 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
2408 enum machine_mode mode
= GET_MODE (target
);
2409 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
2410 rtx reg
= gen_reg_rtx (mode
);
2412 int width
= GET_MODE_SIZE (inner_mode
);
2415 /* Load single variable value. */
2416 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
2417 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
2418 x
= gen_rtx_UNSPEC (VOIDmode
,
2419 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
2420 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
2422 gen_rtx_SET (VOIDmode
,
2426 /* Linear sequence. */
2427 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
2428 for (i
= 0; i
< 16; ++i
)
2429 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
2431 /* Set permute mask to insert element into target. */
2432 for (i
= 0; i
< width
; ++i
)
2433 XVECEXP (mask
, 0, elt
*width
+ i
)
2434 = GEN_INT (i
+ 0x10);
2435 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
2436 x
= gen_rtx_UNSPEC (mode
,
2437 gen_rtvec (3, target
, reg
,
2438 force_reg (V16QImode
, x
)),
2440 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
2443 /* Extract field ELT from VEC into TARGET. */
2446 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
2448 enum machine_mode mode
= GET_MODE (vec
);
2449 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
2452 /* Allocate mode-sized buffer. */
2453 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
2455 /* Add offset to field within buffer matching vector element. */
2456 mem
= adjust_address_nv (mem
, mode
, elt
* GET_MODE_SIZE (inner_mode
));
2458 /* Store single field into mode-sized buffer. */
2459 x
= gen_rtx_UNSPEC (VOIDmode
,
2460 gen_rtvec (1, const0_rtx
), UNSPEC_STVE
);
2461 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
2463 gen_rtx_SET (VOIDmode
,
2466 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
2469 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2470 implement ANDing by the mask IN. */
2472 build_mask64_2_operands (rtx in
, rtx
*out
)
2474 #if HOST_BITS_PER_WIDE_INT >= 64
2475 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
2478 gcc_assert (GET_CODE (in
) == CONST_INT
);
2483 /* Assume c initially something like 0x00fff000000fffff. The idea
2484 is to rotate the word so that the middle ^^^^^^ group of zeros
2485 is at the MS end and can be cleared with an rldicl mask. We then
2486 rotate back and clear off the MS ^^ group of zeros with a
2488 c
= ~c
; /* c == 0xff000ffffff00000 */
2489 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
2490 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
2491 c
= ~c
; /* c == 0x00fff000000fffff */
2492 c
&= -lsb
; /* c == 0x00fff00000000000 */
2493 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2494 c
= ~c
; /* c == 0xff000fffffffffff */
2495 c
&= -lsb
; /* c == 0xff00000000000000 */
2497 while ((lsb
>>= 1) != 0)
2498 shift
++; /* shift == 44 on exit from loop */
2499 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
2500 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
2501 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
2505 /* Assume c initially something like 0xff000f0000000000. The idea
2506 is to rotate the word so that the ^^^ middle group of zeros
2507 is at the LS end and can be cleared with an rldicr mask. We then
2508 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2510 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
2511 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
2512 c
= ~c
; /* c == 0x00fff0ffffffffff */
2513 c
&= -lsb
; /* c == 0x00fff00000000000 */
2514 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2515 c
= ~c
; /* c == 0xff000fffffffffff */
2516 c
&= -lsb
; /* c == 0xff00000000000000 */
2518 while ((lsb
>>= 1) != 0)
2519 shift
++; /* shift == 44 on exit from loop */
2520 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
2521 m1
>>= shift
; /* m1 == 0x0000000000000fff */
2522 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
2525 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2526 masks will be all 1's. We are guaranteed more than one transition. */
2527 out
[0] = GEN_INT (64 - shift
);
2528 out
[1] = GEN_INT (m1
);
2529 out
[2] = GEN_INT (shift
);
2530 out
[3] = GEN_INT (m2
);
2538 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2541 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
2543 /* Reject (subreg:SI (reg:DF)). */
2544 if (GET_CODE (op
) == SUBREG
2546 && REG_P (SUBREG_REG (op
))
2547 && GET_MODE (SUBREG_REG (op
)) == DFmode
)
2550 /* Reject (subreg:DF (reg:DI)). */
2551 if (GET_CODE (op
) == SUBREG
2553 && REG_P (SUBREG_REG (op
))
2554 && GET_MODE (SUBREG_REG (op
)) == DImode
)
2560 /* Darwin, AIX increases natural record alignment to doubleword if the first
2561 field is an FP double while the FP fields remain word aligned. */
2564 rs6000_special_round_type_align (tree type
, unsigned int computed
,
2565 unsigned int specified
)
2567 unsigned int align
= MAX (computed
, specified
);
2568 tree field
= TYPE_FIELDS (type
);
2570 /* Skip all non field decls */
2571 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
2572 field
= TREE_CHAIN (field
);
2574 if (field
!= NULL
&& field
!= type
)
2576 type
= TREE_TYPE (field
);
2577 while (TREE_CODE (type
) == ARRAY_TYPE
)
2578 type
= TREE_TYPE (type
);
2580 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
2581 align
= MAX (align
, 64);
2587 /* Return 1 for an operand in small memory on V.4/eabi. */
2590 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
2591 enum machine_mode mode ATTRIBUTE_UNUSED
)
2596 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
2599 if (DEFAULT_ABI
!= ABI_V4
)
2602 if (GET_CODE (op
) == SYMBOL_REF
)
2605 else if (GET_CODE (op
) != CONST
2606 || GET_CODE (XEXP (op
, 0)) != PLUS
2607 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
2608 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
2613 rtx sum
= XEXP (op
, 0);
2614 HOST_WIDE_INT summand
;
2616 /* We have to be careful here, because it is the referenced address
2617 that must be 32k from _SDA_BASE_, not just the symbol. */
2618 summand
= INTVAL (XEXP (sum
, 1));
2619 if (summand
< 0 || (unsigned HOST_WIDE_INT
) summand
> g_switch_value
)
2622 sym_ref
= XEXP (sum
, 0);
2625 return SYMBOL_REF_SMALL_P (sym_ref
);
2631 /* Return true if either operand is a general purpose register. */
2634 gpr_or_gpr_p (rtx op0
, rtx op1
)
2636 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
2637 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
2641 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2644 constant_pool_expr_1 (rtx op
, int *have_sym
, int *have_toc
)
2646 switch (GET_CODE (op
))
2649 if (RS6000_SYMBOL_REF_TLS_P (op
))
2651 else if (CONSTANT_POOL_ADDRESS_P (op
))
2653 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op
), Pmode
))
2661 else if (! strcmp (XSTR (op
, 0), toc_label_name
))
2670 return (constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
)
2671 && constant_pool_expr_1 (XEXP (op
, 1), have_sym
, have_toc
));
2673 return constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
);
2682 constant_pool_expr_p (rtx op
)
2686 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_sym
;
2690 toc_relative_expr_p (rtx op
)
2694 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_toc
;
2698 legitimate_constant_pool_address_p (rtx x
)
2701 && GET_CODE (x
) == PLUS
2702 && GET_CODE (XEXP (x
, 0)) == REG
2703 && (TARGET_MINIMAL_TOC
|| REGNO (XEXP (x
, 0)) == TOC_REGISTER
)
2704 && constant_pool_expr_p (XEXP (x
, 1)));
2708 rs6000_legitimate_small_data_p (enum machine_mode mode
, rtx x
)
2710 return (DEFAULT_ABI
== ABI_V4
2711 && !flag_pic
&& !TARGET_TOC
2712 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
2713 && small_data_operand (x
, mode
));
2716 /* SPE offset addressing is limited to 5-bits worth of double words. */
2717 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2720 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
2722 unsigned HOST_WIDE_INT offset
, extra
;
2724 if (GET_CODE (x
) != PLUS
)
2726 if (GET_CODE (XEXP (x
, 0)) != REG
)
2728 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
2730 if (legitimate_constant_pool_address_p (x
))
2732 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2735 offset
= INTVAL (XEXP (x
, 1));
2743 /* AltiVec vector modes. Only reg+reg addressing is valid and
2744 constant offset zero should not occur due to canonicalization.
2745 Allow any offset when not strict before reload. */
2752 /* SPE vector modes. */
2753 return SPE_CONST_OFFSET_OK (offset
);
2756 if (TARGET_E500_DOUBLE
)
2757 return SPE_CONST_OFFSET_OK (offset
);
2760 /* On e500v2, we may have:
2762 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2764 Which gets addressed with evldd instructions. */
2765 if (TARGET_E500_DOUBLE
)
2766 return SPE_CONST_OFFSET_OK (offset
);
2768 if (mode
== DFmode
|| !TARGET_POWERPC64
)
2770 else if (offset
& 3)
2776 if (mode
== TFmode
|| !TARGET_POWERPC64
)
2778 else if (offset
& 3)
2789 return (offset
< 0x10000) && (offset
+ extra
< 0x10000);
2793 legitimate_indexed_address_p (rtx x
, int strict
)
2797 if (GET_CODE (x
) != PLUS
)
2803 /* Recognize the rtl generated by reload which we know will later be
2804 replaced with proper base and index regs. */
2806 && reload_in_progress
2807 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
2811 return (REG_P (op0
) && REG_P (op1
)
2812 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
2813 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
2814 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
2815 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
2819 legitimate_indirect_address_p (rtx x
, int strict
)
2821 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
2825 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
2827 if (!TARGET_MACHO
|| !flag_pic
2828 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
2832 if (GET_CODE (x
) != LO_SUM
)
2834 if (GET_CODE (XEXP (x
, 0)) != REG
)
2836 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
2840 return CONSTANT_P (x
);
2844 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
2846 if (GET_CODE (x
) != LO_SUM
)
2848 if (GET_CODE (XEXP (x
, 0)) != REG
)
2850 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
2852 /* Restrict addressing for DI because of our SUBREG hackery. */
2853 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
2857 if (TARGET_ELF
|| TARGET_MACHO
)
2859 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
2863 if (GET_MODE_NUNITS (mode
) != 1)
2865 if (GET_MODE_BITSIZE (mode
) > 64
2866 || (GET_MODE_BITSIZE (mode
) > 32 && !TARGET_POWERPC64
2867 && !(TARGET_HARD_FLOAT
&& TARGET_FPRS
&& mode
== DFmode
)))
2870 return CONSTANT_P (x
);
2877 /* Try machine-dependent ways of modifying an illegitimate address
2878 to be legitimate. If we find one, return the new, valid address.
2879 This is used from only one place: `memory_address' in explow.c.
2881 OLDX is the address as it was before break_out_memory_refs was
2882 called. In some cases it is useful to look at this to decide what
2885 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2887 It is always safe for this function to do nothing. It exists to
2888 recognize opportunities to optimize the output.
2890 On RS/6000, first check for the sum of a register with a constant
2891 integer that is out of range. If so, generate code to add the
2892 constant with the low-order 16 bits masked to the register and force
2893 this result into another register (this can be done with `cau').
2894 Then generate an address of REG+(CONST&0xffff), allowing for the
2895 possibility of bit 16 being a one.
2897 Then check for the sum of a register and something not constant, try to
2898 load the other things into a register and return the sum. */
2901 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
2902 enum machine_mode mode
)
2904 if (GET_CODE (x
) == SYMBOL_REF
)
2906 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
2908 return rs6000_legitimize_tls_address (x
, model
);
2911 if (GET_CODE (x
) == PLUS
2912 && GET_CODE (XEXP (x
, 0)) == REG
2913 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2914 && (unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000) >= 0x10000)
2916 HOST_WIDE_INT high_int
, low_int
;
2918 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2919 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
2920 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
2921 GEN_INT (high_int
)), 0);
2922 return gen_rtx_PLUS (Pmode
, sum
, GEN_INT (low_int
));
2924 else if (GET_CODE (x
) == PLUS
2925 && GET_CODE (XEXP (x
, 0)) == REG
2926 && GET_CODE (XEXP (x
, 1)) != CONST_INT
2927 && GET_MODE_NUNITS (mode
) == 1
2928 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2930 || (((mode
!= DImode
&& mode
!= DFmode
) || TARGET_E500_DOUBLE
)
2932 && (TARGET_POWERPC64
|| mode
!= DImode
)
2935 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
2936 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
2938 else if (ALTIVEC_VECTOR_MODE (mode
))
2942 /* Make sure both operands are registers. */
2943 if (GET_CODE (x
) == PLUS
)
2944 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
2945 force_reg (Pmode
, XEXP (x
, 1)));
2947 reg
= force_reg (Pmode
, x
);
2950 else if (SPE_VECTOR_MODE (mode
)
2951 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
2952 || mode
== DImode
)))
2956 /* We accept [reg + reg] and [reg + OFFSET]. */
2958 if (GET_CODE (x
) == PLUS
)
2960 rtx op1
= XEXP (x
, 0);
2961 rtx op2
= XEXP (x
, 1);
2963 op1
= force_reg (Pmode
, op1
);
2965 if (GET_CODE (op2
) != REG
2966 && (GET_CODE (op2
) != CONST_INT
2967 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))))
2968 op2
= force_reg (Pmode
, op2
);
2970 return gen_rtx_PLUS (Pmode
, op1
, op2
);
2973 return force_reg (Pmode
, x
);
2979 && GET_CODE (x
) != CONST_INT
2980 && GET_CODE (x
) != CONST_DOUBLE
2982 && GET_MODE_NUNITS (mode
) == 1
2983 && (GET_MODE_BITSIZE (mode
) <= 32
2984 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) && mode
== DFmode
)))
2986 rtx reg
= gen_reg_rtx (Pmode
);
2987 emit_insn (gen_elf_high (reg
, x
));
2988 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
2990 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
2993 && ! MACHO_DYNAMIC_NO_PIC_P
2995 && GET_CODE (x
) != CONST_INT
2996 && GET_CODE (x
) != CONST_DOUBLE
2998 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) || mode
!= DFmode
)
3002 rtx reg
= gen_reg_rtx (Pmode
);
3003 emit_insn (gen_macho_high (reg
, x
));
3004 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3007 && constant_pool_expr_p (x
)
3008 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
3010 return create_TOC_reference (x
);
3016 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3017 We need to emit DTP-relative relocations. */
3020 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3025 fputs ("\t.long\t", file
);
3028 fputs (DOUBLE_INT_ASM_OP
, file
);
3033 output_addr_const (file
, x
);
3034 fputs ("@dtprel+0x8000", file
);
3037 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3039 static GTY(()) rtx rs6000_tls_symbol
;
3041 rs6000_tls_get_addr (void)
3043 if (!rs6000_tls_symbol
)
3044 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3046 return rs6000_tls_symbol
;
3049 /* Construct the SYMBOL_REF for TLS GOT references. */
3051 static GTY(()) rtx rs6000_got_symbol
;
3053 rs6000_got_sym (void)
3055 if (!rs6000_got_symbol
)
3057 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3058 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
3059 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
3062 return rs6000_got_symbol
;
3065 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3066 this (thread-local) address. */
3069 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
3073 dest
= gen_reg_rtx (Pmode
);
3074 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
3080 tlsreg
= gen_rtx_REG (Pmode
, 13);
3081 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
3085 tlsreg
= gen_rtx_REG (Pmode
, 2);
3086 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
3090 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
3094 tmp
= gen_reg_rtx (Pmode
);
3097 tlsreg
= gen_rtx_REG (Pmode
, 13);
3098 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
3102 tlsreg
= gen_rtx_REG (Pmode
, 2);
3103 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
3107 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
3109 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
3114 rtx r3
, got
, tga
, tmp1
, tmp2
, eqv
;
3116 /* We currently use relocations like @got@tlsgd for tls, which
3117 means the linker will handle allocation of tls entries, placing
3118 them in the .got section. So use a pointer to the .got section,
3119 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3120 or to secondary GOT sections used by 32-bit -fPIC. */
3122 got
= gen_rtx_REG (Pmode
, 2);
3126 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
3129 rtx gsym
= rs6000_got_sym ();
3130 got
= gen_reg_rtx (Pmode
);
3132 rs6000_emit_move (got
, gsym
, Pmode
);
3135 rtx tempLR
, tmp3
, mem
;
3138 tempLR
= gen_reg_rtx (Pmode
);
3139 tmp1
= gen_reg_rtx (Pmode
);
3140 tmp2
= gen_reg_rtx (Pmode
);
3141 tmp3
= gen_reg_rtx (Pmode
);
3142 mem
= gen_const_mem (Pmode
, tmp1
);
3144 first
= emit_insn (gen_load_toc_v4_PIC_1b (tempLR
, gsym
));
3145 emit_move_insn (tmp1
, tempLR
);
3146 emit_move_insn (tmp2
, mem
);
3147 emit_insn (gen_addsi3 (tmp3
, tmp1
, tmp2
));
3148 last
= emit_move_insn (got
, tmp3
);
3149 REG_NOTES (last
) = gen_rtx_EXPR_LIST (REG_EQUAL
, gsym
,
3151 REG_NOTES (first
) = gen_rtx_INSN_LIST (REG_LIBCALL
, last
,
3153 REG_NOTES (last
) = gen_rtx_INSN_LIST (REG_RETVAL
, first
,
3159 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
3161 r3
= gen_rtx_REG (Pmode
, 3);
3163 insn
= gen_tls_gd_64 (r3
, got
, addr
);
3165 insn
= gen_tls_gd_32 (r3
, got
, addr
);
3168 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3169 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3170 insn
= emit_call_insn (insn
);
3171 CONST_OR_PURE_CALL_P (insn
) = 1;
3172 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3173 insn
= get_insns ();
3175 emit_libcall_block (insn
, dest
, r3
, addr
);
3177 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
3179 r3
= gen_rtx_REG (Pmode
, 3);
3181 insn
= gen_tls_ld_64 (r3
, got
);
3183 insn
= gen_tls_ld_32 (r3
, got
);
3186 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3187 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3188 insn
= emit_call_insn (insn
);
3189 CONST_OR_PURE_CALL_P (insn
) = 1;
3190 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3191 insn
= get_insns ();
3193 tmp1
= gen_reg_rtx (Pmode
);
3194 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3196 emit_libcall_block (insn
, tmp1
, r3
, eqv
);
3197 if (rs6000_tls_size
== 16)
3200 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
3202 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
3204 else if (rs6000_tls_size
== 32)
3206 tmp2
= gen_reg_rtx (Pmode
);
3208 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
3210 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
3213 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
3215 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
3219 tmp2
= gen_reg_rtx (Pmode
);
3221 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
3223 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
3225 insn
= gen_rtx_SET (Pmode
, dest
,
3226 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
3232 /* IE, or 64 bit offset LE. */
3233 tmp2
= gen_reg_rtx (Pmode
);
3235 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
3237 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
3240 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
3242 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
3250 /* Return 1 if X contains a thread-local symbol. */
3253 rs6000_tls_referenced_p (rtx x
)
3255 if (! TARGET_HAVE_TLS
)
3258 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
3261 /* Return 1 if *X is a thread-local symbol. This is the same as
3262 rs6000_tls_symbol_ref except for the type of the unused argument. */
3265 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
3267 return RS6000_SYMBOL_REF_TLS_P (*x
);
3270 /* The convention appears to be to define this wherever it is used.
3271 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3272 is now used here. */
3273 #ifndef REG_MODE_OK_FOR_BASE_P
3274 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3277 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3278 replace the input X, or the original X if no replacement is called for.
3279 The output parameter *WIN is 1 if the calling macro should goto WIN,
3282 For RS/6000, we wish to handle large displacements off a base
3283 register by splitting the addend across an addiu/addis and the mem insn.
3284 This cuts number of extra insns needed from 3 to 1.
3286 On Darwin, we use this to generate code for floating point constants.
3287 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3288 The Darwin code is inside #if TARGET_MACHO because only then is
3289 machopic_function_base_name() defined. */
3291 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3292 int opnum
, int type
,
3293 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3295 /* We must recognize output that we have already generated ourselves. */
3296 if (GET_CODE (x
) == PLUS
3297 && GET_CODE (XEXP (x
, 0)) == PLUS
3298 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
3299 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3300 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3302 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3303 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3304 opnum
, (enum reload_type
)type
);
3310 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
3311 && GET_CODE (x
) == LO_SUM
3312 && GET_CODE (XEXP (x
, 0)) == PLUS
3313 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
3314 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
3315 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 0)) == CONST
3316 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
3317 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == MINUS
3318 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 0)) == SYMBOL_REF
3319 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == SYMBOL_REF
)
3321 /* Result of previous invocation of this function on Darwin
3322 floating point constant. */
3323 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3324 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3325 opnum
, (enum reload_type
)type
);
3331 /* Force ld/std non-word aligned offset into base register by wrapping
3333 if (GET_CODE (x
) == PLUS
3334 && GET_CODE (XEXP (x
, 0)) == REG
3335 && REGNO (XEXP (x
, 0)) < 32
3336 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
3337 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3338 && (INTVAL (XEXP (x
, 1)) & 3) != 0
3339 && !ALTIVEC_VECTOR_MODE (mode
)
3340 && GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
3341 && TARGET_POWERPC64
)
3343 x
= gen_rtx_PLUS (GET_MODE (x
), x
, GEN_INT (0));
3344 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3345 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3346 opnum
, (enum reload_type
) type
);
3351 if (GET_CODE (x
) == PLUS
3352 && GET_CODE (XEXP (x
, 0)) == REG
3353 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
3354 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
3355 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3356 && !SPE_VECTOR_MODE (mode
)
3357 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
3359 && !ALTIVEC_VECTOR_MODE (mode
))
3361 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
3362 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
3364 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3366 /* Check for 32-bit overflow. */
3367 if (high
+ low
!= val
)
3373 /* Reload the high part into a base reg; leave the low part
3374 in the mem directly. */
3376 x
= gen_rtx_PLUS (GET_MODE (x
),
3377 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
3381 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3382 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3383 opnum
, (enum reload_type
)type
);
3388 if (GET_CODE (x
) == SYMBOL_REF
3389 && !ALTIVEC_VECTOR_MODE (mode
)
3391 && DEFAULT_ABI
== ABI_DARWIN
3392 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
3394 && DEFAULT_ABI
== ABI_V4
3397 /* Don't do this for TFmode, since the result isn't offsettable.
3398 The same goes for DImode without 64-bit gprs. */
3400 && (mode
!= DImode
|| TARGET_POWERPC64
))
3405 rtx offset
= gen_rtx_CONST (Pmode
,
3406 gen_rtx_MINUS (Pmode
, x
,
3407 machopic_function_base_sym ()));
3408 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3409 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3410 gen_rtx_HIGH (Pmode
, offset
)), offset
);
3414 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3415 gen_rtx_HIGH (Pmode
, x
), x
);
3417 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3418 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3419 opnum
, (enum reload_type
)type
);
3424 /* Reload an offset address wrapped by an AND that represents the
3425 masking of the lower bits. Strip the outer AND and let reload
3426 convert the offset address into an indirect address. */
3428 && ALTIVEC_VECTOR_MODE (mode
)
3429 && GET_CODE (x
) == AND
3430 && GET_CODE (XEXP (x
, 0)) == PLUS
3431 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
3432 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3433 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3434 && INTVAL (XEXP (x
, 1)) == -16)
3442 && constant_pool_expr_p (x
)
3443 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
3445 (x
) = create_TOC_reference (x
);
3453 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3454 that is a valid memory address for an instruction.
3455 The MODE argument is the machine mode for the MEM expression
3456 that wants to use this address.
3458 On the RS/6000, there are four valid address: a SYMBOL_REF that
3459 refers to a constant pool entry of an address (or the sum of it
3460 plus a constant), a short (16-bit signed) constant plus a register,
3461 the sum of two registers, or a register indirect, possibly with an
3462 auto-increment. For DFmode and DImode with a constant plus register,
3463 we must ensure that both words are addressable or PowerPC64 with offset
3466 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3467 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3468 adjacent memory cells are accessed by adding word-sized offsets
3469 during assembly output. */
3471 rs6000_legitimate_address (enum machine_mode mode
, rtx x
, int reg_ok_strict
)
3473 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3475 && ALTIVEC_VECTOR_MODE (mode
)
3476 && GET_CODE (x
) == AND
3477 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3478 && INTVAL (XEXP (x
, 1)) == -16)
3481 if (RS6000_SYMBOL_REF_TLS_P (x
))
3483 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
3485 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
3486 && !ALTIVEC_VECTOR_MODE (mode
)
3487 && !SPE_VECTOR_MODE (mode
)
3488 /* Restrict addressing for DI because of our SUBREG hackery. */
3489 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
3491 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
3493 if (rs6000_legitimate_small_data_p (mode
, x
))
3495 if (legitimate_constant_pool_address_p (x
))
3497 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3499 && GET_CODE (x
) == PLUS
3500 && GET_CODE (XEXP (x
, 0)) == REG
3501 && (XEXP (x
, 0) == virtual_stack_vars_rtx
3502 || XEXP (x
, 0) == arg_pointer_rtx
)
3503 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3505 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
3509 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3511 || ((mode
!= DFmode
|| TARGET_E500_DOUBLE
) && mode
!= TFmode
))
3512 && (TARGET_POWERPC64
|| mode
!= DImode
)
3513 && legitimate_indexed_address_p (x
, reg_ok_strict
))
3515 if (legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
3520 /* Go to LABEL if ADDR (a legitimate address expression)
3521 has an effect that depends on the machine mode it is used for.
3523 On the RS/6000 this is true of all integral offsets (since AltiVec
3524 modes don't allow them) or is a pre-increment or decrement.
3526 ??? Except that due to conceptual problems in offsettable_address_p
3527 we can't really report the problems of integral offsets. So leave
3528 this assuming that the adjustable offset must be valid for the
3529 sub-words of a TFmode operand, which is what we had before. */
3532 rs6000_mode_dependent_address (rtx addr
)
3534 switch (GET_CODE (addr
))
3537 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3539 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
3540 return val
+ 12 + 0x8000 >= 0x10000;
3549 return TARGET_UPDATE
;
3558 /* Return number of consecutive hard regs needed starting at reg REGNO
3559 to hold something of mode MODE.
3560 This is ordinarily the length in words of a value of mode MODE
3561 but can be less for certain modes in special long registers.
3563 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3564 scalar instructions. The upper 32 bits are only available to the
3567 POWER and PowerPC GPRs hold 32 bits worth;
3568 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3571 rs6000_hard_regno_nregs (int regno
, enum machine_mode mode
)
3573 if (FP_REGNO_P (regno
))
3574 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
3576 if (TARGET_E500_DOUBLE
&& mode
== DFmode
)
3579 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
3580 return (GET_MODE_SIZE (mode
) + UNITS_PER_SPE_WORD
- 1) / UNITS_PER_SPE_WORD
;
3582 if (ALTIVEC_REGNO_P (regno
))
3584 (GET_MODE_SIZE (mode
) + UNITS_PER_ALTIVEC_WORD
- 1) / UNITS_PER_ALTIVEC_WORD
;
3586 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3589 /* Change register usage conditional on target flags. */
3591 rs6000_conditional_register_usage (void)
3595 /* Set MQ register fixed (already call_used) if not POWER
3596 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3601 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3603 fixed_regs
[13] = call_used_regs
[13]
3604 = call_really_used_regs
[13] = 1;
3606 /* Conditionally disable FPRs. */
3607 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
3608 for (i
= 32; i
< 64; i
++)
3609 fixed_regs
[i
] = call_used_regs
[i
]
3610 = call_really_used_regs
[i
] = 1;
3612 /* The TOC register is not killed across calls in a way that is
3613 visible to the compiler. */
3614 if (DEFAULT_ABI
== ABI_AIX
)
3615 call_really_used_regs
[2] = 0;
3617 if (DEFAULT_ABI
== ABI_V4
3618 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
3620 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3622 if (DEFAULT_ABI
== ABI_V4
3623 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
3625 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3626 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3627 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3629 if (DEFAULT_ABI
== ABI_DARWIN
3630 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
3631 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3632 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3633 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3635 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
3636 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3637 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3640 global_regs
[VSCR_REGNO
] = 1;
3644 global_regs
[SPEFSCR_REGNO
] = 1;
3645 fixed_regs
[FIXED_SCRATCH
]
3646 = call_used_regs
[FIXED_SCRATCH
]
3647 = call_really_used_regs
[FIXED_SCRATCH
] = 1;
3650 if (! TARGET_ALTIVEC
)
3652 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
3653 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
3654 call_really_used_regs
[VRSAVE_REGNO
] = 1;
3657 if (TARGET_ALTIVEC_ABI
)
3658 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
3659 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
3662 /* Try to output insns to set TARGET equal to the constant C if it can
3663 be done in less than N insns. Do all computations in MODE.
3664 Returns the place where the output has been placed if it can be
3665 done and the insns have been emitted. If it would take more than N
3666 insns, zero is returned and no insns and emitted. */
3669 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
3670 rtx source
, int n ATTRIBUTE_UNUSED
)
3672 rtx result
, insn
, set
;
3673 HOST_WIDE_INT c0
, c1
;
3680 dest
= gen_reg_rtx (mode
);
3681 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
3685 result
= no_new_pseudos
? dest
: gen_reg_rtx (SImode
);
3687 emit_insn (gen_rtx_SET (VOIDmode
, result
,
3688 GEN_INT (INTVAL (source
)
3689 & (~ (HOST_WIDE_INT
) 0xffff))));
3690 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
3691 gen_rtx_IOR (SImode
, result
,
3692 GEN_INT (INTVAL (source
) & 0xffff))));
3697 switch (GET_CODE (source
))
3700 c0
= INTVAL (source
);
3705 #if HOST_BITS_PER_WIDE_INT >= 64
3706 c0
= CONST_DOUBLE_LOW (source
);
3709 c0
= CONST_DOUBLE_LOW (source
);
3710 c1
= CONST_DOUBLE_HIGH (source
);
3718 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
3725 insn
= get_last_insn ();
3726 set
= single_set (insn
);
3727 if (! CONSTANT_P (SET_SRC (set
)))
3728 set_unique_reg_note (insn
, REG_EQUAL
, source
);
3733 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3734 fall back to a straight forward decomposition. We do this to avoid
3735 exponential run times encountered when looking for longer sequences
3736 with rs6000_emit_set_const. */
3738 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
3740 if (!TARGET_POWERPC64
)
3742 rtx operand1
, operand2
;
3744 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
3746 operand2
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
3748 emit_move_insn (operand1
, GEN_INT (c1
));
3749 emit_move_insn (operand2
, GEN_INT (c2
));
3753 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
3756 ud2
= (c1
& 0xffff0000) >> 16;
3757 #if HOST_BITS_PER_WIDE_INT >= 64
3761 ud4
= (c2
& 0xffff0000) >> 16;
3763 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
3764 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
3767 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
3769 emit_move_insn (dest
, GEN_INT (ud1
));
3772 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
3773 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
3776 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
3779 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
3781 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
3783 else if ((ud4
== 0xffff && (ud3
& 0x8000))
3784 || (ud4
== 0 && ! (ud3
& 0x8000)))
3787 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
3790 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
3793 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud2
)));
3794 emit_move_insn (dest
, gen_rtx_ASHIFT (DImode
, dest
, GEN_INT (16)));
3796 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
3801 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
3804 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
3807 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud3
)));
3809 emit_move_insn (dest
, gen_rtx_ASHIFT (DImode
, dest
, GEN_INT (32)));
3811 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
,
3812 GEN_INT (ud2
<< 16)));
3814 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
3820 /* Helper for the following. Get rid of [r+r] memory refs
3821 in cases where it won't work (TImode, TFmode). */
3824 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
3826 if (GET_CODE (operands
[0]) == MEM
3827 && GET_CODE (XEXP (operands
[0], 0)) != REG
3828 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0))
3829 && ! reload_in_progress
)
3831 = replace_equiv_address (operands
[0],
3832 copy_addr_to_reg (XEXP (operands
[0], 0)));
3834 if (GET_CODE (operands
[1]) == MEM
3835 && GET_CODE (XEXP (operands
[1], 0)) != REG
3836 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0))
3837 && ! reload_in_progress
)
3839 = replace_equiv_address (operands
[1],
3840 copy_addr_to_reg (XEXP (operands
[1], 0)));
3843 /* Emit a move from SOURCE to DEST in mode MODE. */
3845 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
3849 operands
[1] = source
;
3851 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3852 if (GET_CODE (operands
[1]) == CONST_DOUBLE
3853 && ! FLOAT_MODE_P (mode
)
3854 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3856 /* FIXME. This should never happen. */
3857 /* Since it seems that it does, do the safe thing and convert
3859 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
3861 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
3862 || FLOAT_MODE_P (mode
)
3863 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
3864 || CONST_DOUBLE_LOW (operands
[1]) < 0)
3865 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
3866 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
3868 /* Check if GCC is setting up a block move that will end up using FP
3869 registers as temporaries. We must make sure this is acceptable. */
3870 if (GET_CODE (operands
[0]) == MEM
3871 && GET_CODE (operands
[1]) == MEM
3873 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
3874 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
3875 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
3876 ? 32 : MEM_ALIGN (operands
[0])))
3877 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
3879 : MEM_ALIGN (operands
[1]))))
3880 && ! MEM_VOLATILE_P (operands
[0])
3881 && ! MEM_VOLATILE_P (operands
[1]))
3883 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
3884 adjust_address (operands
[1], SImode
, 0));
3885 emit_move_insn (adjust_address (operands
[0], SImode
, 4),
3886 adjust_address (operands
[1], SImode
, 4));
3890 if (!no_new_pseudos
&& GET_CODE (operands
[0]) == MEM
3891 && !gpc_reg_operand (operands
[1], mode
))
3892 operands
[1] = force_reg (mode
, operands
[1]);
3894 if (mode
== SFmode
&& ! TARGET_POWERPC
3895 && TARGET_HARD_FLOAT
&& TARGET_FPRS
3896 && GET_CODE (operands
[0]) == MEM
)
3900 if (reload_in_progress
|| reload_completed
)
3901 regnum
= true_regnum (operands
[1]);
3902 else if (GET_CODE (operands
[1]) == REG
)
3903 regnum
= REGNO (operands
[1]);
3907 /* If operands[1] is a register, on POWER it may have
3908 double-precision data in it, so truncate it to single
3910 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
3913 newreg
= (no_new_pseudos
? operands
[1] : gen_reg_rtx (mode
));
3914 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
3915 operands
[1] = newreg
;
3919 /* Recognize the case where operand[1] is a reference to thread-local
3920 data and load its address to a register. */
3921 if (rs6000_tls_referenced_p (operands
[1]))
3923 enum tls_model model
;
3924 rtx tmp
= operands
[1];
3927 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
3929 addend
= XEXP (XEXP (tmp
, 0), 1);
3930 tmp
= XEXP (XEXP (tmp
, 0), 0);
3933 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
3934 model
= SYMBOL_REF_TLS_MODEL (tmp
);
3935 gcc_assert (model
!= 0);
3937 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
3940 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
3941 tmp
= force_operand (tmp
, operands
[0]);
3946 /* Handle the case where reload calls us with an invalid address. */
3947 if (reload_in_progress
&& mode
== Pmode
3948 && (! general_operand (operands
[1], mode
)
3949 || ! nonimmediate_operand (operands
[0], mode
)))
3952 /* 128-bit constant floating-point values on Darwin should really be
3953 loaded as two parts. */
3954 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
)
3955 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
3956 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
3958 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3959 know how to get a DFmode SUBREG of a TFmode. */
3960 rs6000_emit_move (simplify_gen_subreg (DImode
, operands
[0], mode
, 0),
3961 simplify_gen_subreg (DImode
, operands
[1], mode
, 0),
3963 rs6000_emit_move (simplify_gen_subreg (DImode
, operands
[0], mode
,
3964 GET_MODE_SIZE (DImode
)),
3965 simplify_gen_subreg (DImode
, operands
[1], mode
,
3966 GET_MODE_SIZE (DImode
)),
3971 /* FIXME: In the long term, this switch statement should go away
3972 and be replaced by a sequence of tests based on things like
3978 if (CONSTANT_P (operands
[1])
3979 && GET_CODE (operands
[1]) != CONST_INT
)
3980 operands
[1] = force_const_mem (mode
, operands
[1]);
3984 rs6000_eliminate_indexed_memrefs (operands
);
3989 if (CONSTANT_P (operands
[1])
3990 && ! easy_fp_constant (operands
[1], mode
))
3991 operands
[1] = force_const_mem (mode
, operands
[1]);
4002 if (CONSTANT_P (operands
[1])
4003 && !easy_vector_constant (operands
[1], mode
))
4004 operands
[1] = force_const_mem (mode
, operands
[1]);
4009 /* Use default pattern for address of ELF small data */
4012 && DEFAULT_ABI
== ABI_V4
4013 && (GET_CODE (operands
[1]) == SYMBOL_REF
4014 || GET_CODE (operands
[1]) == CONST
)
4015 && small_data_operand (operands
[1], mode
))
4017 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4021 if (DEFAULT_ABI
== ABI_V4
4022 && mode
== Pmode
&& mode
== SImode
4023 && flag_pic
== 1 && got_operand (operands
[1], mode
))
4025 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
4029 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
4033 && CONSTANT_P (operands
[1])
4034 && GET_CODE (operands
[1]) != HIGH
4035 && GET_CODE (operands
[1]) != CONST_INT
)
4037 rtx target
= (no_new_pseudos
? operands
[0] : gen_reg_rtx (mode
));
4039 /* If this is a function address on -mcall-aixdesc,
4040 convert it to the address of the descriptor. */
4041 if (DEFAULT_ABI
== ABI_AIX
4042 && GET_CODE (operands
[1]) == SYMBOL_REF
4043 && XSTR (operands
[1], 0)[0] == '.')
4045 const char *name
= XSTR (operands
[1], 0);
4047 while (*name
== '.')
4049 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
4050 CONSTANT_POOL_ADDRESS_P (new_ref
)
4051 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
4052 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
4053 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
4054 SYMBOL_REF_DECL (new_ref
) = SYMBOL_REF_DECL (operands
[1]);
4055 operands
[1] = new_ref
;
4058 if (DEFAULT_ABI
== ABI_DARWIN
)
4061 if (MACHO_DYNAMIC_NO_PIC_P
)
4063 /* Take care of any required data indirection. */
4064 operands
[1] = rs6000_machopic_legitimize_pic_address (
4065 operands
[1], mode
, operands
[0]);
4066 if (operands
[0] != operands
[1])
4067 emit_insn (gen_rtx_SET (VOIDmode
,
4068 operands
[0], operands
[1]));
4072 emit_insn (gen_macho_high (target
, operands
[1]));
4073 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
4077 emit_insn (gen_elf_high (target
, operands
[1]));
4078 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
4082 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4083 and we have put it in the TOC, we just need to make a TOC-relative
4086 && GET_CODE (operands
[1]) == SYMBOL_REF
4087 && constant_pool_expr_p (operands
[1])
4088 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
4089 get_pool_mode (operands
[1])))
4091 operands
[1] = create_TOC_reference (operands
[1]);
4093 else if (mode
== Pmode
4094 && CONSTANT_P (operands
[1])
4095 && ((GET_CODE (operands
[1]) != CONST_INT
4096 && ! easy_fp_constant (operands
[1], mode
))
4097 || (GET_CODE (operands
[1]) == CONST_INT
4098 && num_insns_constant (operands
[1], mode
) > 2)
4099 || (GET_CODE (operands
[0]) == REG
4100 && FP_REGNO_P (REGNO (operands
[0]))))
4101 && GET_CODE (operands
[1]) != HIGH
4102 && ! legitimate_constant_pool_address_p (operands
[1])
4103 && ! toc_relative_expr_p (operands
[1]))
4105 /* Emit a USE operation so that the constant isn't deleted if
4106 expensive optimizations are turned on because nobody
4107 references it. This should only be done for operands that
4108 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4109 This should not be done for operands that contain LABEL_REFs.
4110 For now, we just handle the obvious case. */
4111 if (GET_CODE (operands
[1]) != LABEL_REF
)
4112 emit_insn (gen_rtx_USE (VOIDmode
, operands
[1]));
4115 /* Darwin uses a special PIC legitimizer. */
4116 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
4119 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
4121 if (operands
[0] != operands
[1])
4122 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4127 /* If we are to limit the number of things we put in the TOC and
4128 this is a symbol plus a constant we can add in one insn,
4129 just put the symbol in the TOC and add the constant. Don't do
4130 this if reload is in progress. */
4131 if (GET_CODE (operands
[1]) == CONST
4132 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
4133 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
4134 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
4135 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
4136 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
4137 && ! side_effects_p (operands
[0]))
4140 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
4141 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
4143 sym
= force_reg (mode
, sym
);
4145 emit_insn (gen_addsi3 (operands
[0], sym
, other
));
4147 emit_insn (gen_adddi3 (operands
[0], sym
, other
));
4151 operands
[1] = force_const_mem (mode
, operands
[1]);
4154 && constant_pool_expr_p (XEXP (operands
[1], 0))
4155 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4156 get_pool_constant (XEXP (operands
[1], 0)),
4157 get_pool_mode (XEXP (operands
[1], 0))))
4160 = gen_const_mem (mode
,
4161 create_TOC_reference (XEXP (operands
[1], 0)));
4162 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
4168 rs6000_eliminate_indexed_memrefs (operands
);
4172 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4174 gen_rtx_SET (VOIDmode
,
4175 operands
[0], operands
[1]),
4176 gen_rtx_CLOBBER (VOIDmode
,
4177 gen_rtx_SCRATCH (SImode
)))));
4186 /* Above, we may have called force_const_mem which may have returned
4187 an invalid address. If we can, fix this up; otherwise, reload will
4188 have to deal with it. */
4189 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
4190 operands
[1] = validize_mem (operands
[1]);
4193 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4196 /* Nonzero if we can use a floating-point register to pass this arg. */
4197 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4198 (SCALAR_FLOAT_MODE_P (MODE) \
4199 && (CUM)->fregno <= FP_ARG_MAX_REG \
4200 && TARGET_HARD_FLOAT && TARGET_FPRS)
4202 /* Nonzero if we can use an AltiVec register to pass this arg. */
4203 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4204 (ALTIVEC_VECTOR_MODE (MODE) \
4205 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4206 && TARGET_ALTIVEC_ABI \
4209 /* Return a nonzero value to say to return the function value in
4210 memory, just as large structures are always returned. TYPE will be
4211 the data type of the value, and FNTYPE will be the type of the
4212 function doing the returning, or @code{NULL} for libcalls.
4214 The AIX ABI for the RS/6000 specifies that all structures are
4215 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4216 specifies that structures <= 8 bytes are returned in r3/r4, but a
4217 draft put them in memory, and GCC used to implement the draft
4218 instead of the final standard. Therefore, aix_struct_return
4219 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4220 compatibility can change DRAFT_V4_STRUCT_RET to override the
4221 default, and -m switches get the final word. See
4222 rs6000_override_options for more details.
4224 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4225 long double support is enabled. These values are returned in memory.
4227 int_size_in_bytes returns -1 for variable size objects, which go in
4228 memory always. The cast to unsigned makes -1 > 8. */
4231 rs6000_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
4233 /* In the darwin64 abi, try to use registers for larger structs
4235 if (rs6000_darwin64_abi
4236 && TREE_CODE (type
) == RECORD_TYPE
4237 && int_size_in_bytes (type
) > 0)
4239 CUMULATIVE_ARGS valcum
;
4243 valcum
.fregno
= FP_ARG_MIN_REG
;
4244 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
4245 /* Do a trial code generation as if this were going to be passed
4246 as an argument; if any part goes in memory, we return NULL. */
4247 valret
= rs6000_darwin64_record_arg (&valcum
, type
, 1, true);
4250 /* Otherwise fall through to more conventional ABI rules. */
4253 if (AGGREGATE_TYPE_P (type
)
4254 && (aix_struct_return
4255 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
4258 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4259 modes only exist for GCC vector types if -maltivec. */
4260 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
4261 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
4264 /* Return synthetic vectors in memory. */
4265 if (TREE_CODE (type
) == VECTOR_TYPE
4266 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
4268 static bool warned_for_return_big_vectors
= false;
4269 if (!warned_for_return_big_vectors
)
4271 warning (0, "GCC vector returned by reference: "
4272 "non-standard ABI extension with no compatibility guarantee");
4273 warned_for_return_big_vectors
= true;
4278 if (DEFAULT_ABI
== ABI_V4
&& TYPE_MODE (type
) == TFmode
)
4284 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4285 for a call to a function whose data type is FNTYPE.
4286 For a library call, FNTYPE is 0.
4288 For incoming args we set the number of arguments in the prototype large
4289 so we never return a PARALLEL. */
4292 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
4293 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
4294 int libcall
, int n_named_args
)
4296 static CUMULATIVE_ARGS zero_cumulative
;
4298 *cum
= zero_cumulative
;
4300 cum
->fregno
= FP_ARG_MIN_REG
;
4301 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
4302 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
4303 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
4304 ? CALL_LIBCALL
: CALL_NORMAL
);
4305 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
4306 cum
->stdarg
= fntype
4307 && (TYPE_ARG_TYPES (fntype
) != 0
4308 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
4309 != void_type_node
));
4311 cum
->nargs_prototype
= 0;
4312 if (incoming
|| cum
->prototype
)
4313 cum
->nargs_prototype
= n_named_args
;
4315 /* Check for a longcall attribute. */
4316 if ((!fntype
&& rs6000_default_long_calls
)
4318 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
4319 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
4320 cum
->call_cookie
|= CALL_LONG
;
4322 if (TARGET_DEBUG_ARG
)
4324 fprintf (stderr
, "\ninit_cumulative_args:");
4327 tree ret_type
= TREE_TYPE (fntype
);
4328 fprintf (stderr
, " ret code = %s,",
4329 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
4332 if (cum
->call_cookie
& CALL_LONG
)
4333 fprintf (stderr
, " longcall,");
4335 fprintf (stderr
, " proto = %d, nargs = %d\n",
4336 cum
->prototype
, cum
->nargs_prototype
);
4341 && TARGET_ALTIVEC_ABI
4342 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
4344 error ("cannot return value in vector register because"
4345 " altivec instructions are disabled, use -maltivec"
4350 /* Return true if TYPE must be passed on the stack and not in registers. */
4353 rs6000_must_pass_in_stack (enum machine_mode mode
, tree type
)
4355 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
4356 return must_pass_in_stack_var_size (mode
, type
);
4358 return must_pass_in_stack_var_size_or_pad (mode
, type
);
4361 /* If defined, a C expression which determines whether, and in which
4362 direction, to pad out an argument with extra space. The value
4363 should be of type `enum direction': either `upward' to pad above
4364 the argument, `downward' to pad below, or `none' to inhibit
4367 For the AIX ABI structs are always stored left shifted in their
4371 function_arg_padding (enum machine_mode mode
, tree type
)
4373 #ifndef AGGREGATE_PADDING_FIXED
4374 #define AGGREGATE_PADDING_FIXED 0
4376 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4377 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4380 if (!AGGREGATE_PADDING_FIXED
)
4382 /* GCC used to pass structures of the same size as integer types as
4383 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4384 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4385 passed padded downward, except that -mstrict-align further
4386 muddied the water in that multi-component structures of 2 and 4
4387 bytes in size were passed padded upward.
4389 The following arranges for best compatibility with previous
4390 versions of gcc, but removes the -mstrict-align dependency. */
4391 if (BYTES_BIG_ENDIAN
)
4393 HOST_WIDE_INT size
= 0;
4395 if (mode
== BLKmode
)
4397 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
4398 size
= int_size_in_bytes (type
);
4401 size
= GET_MODE_SIZE (mode
);
4403 if (size
== 1 || size
== 2 || size
== 4)
4409 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
4411 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
4415 /* Fall back to the default. */
4416 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
4419 /* If defined, a C expression that gives the alignment boundary, in bits,
4420 of an argument with the specified mode and type. If it is not defined,
4421 PARM_BOUNDARY is used for all arguments.
4423 V.4 wants long longs to be double word aligned.
4424 Doubleword align SPE vectors.
4425 Quadword align Altivec vectors.
4426 Quadword align large synthetic vector types. */
4429 function_arg_boundary (enum machine_mode mode
, tree type
)
4431 if (DEFAULT_ABI
== ABI_V4
&& GET_MODE_SIZE (mode
) == 8)
4433 else if (SPE_VECTOR_MODE (mode
)
4434 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4435 && int_size_in_bytes (type
) >= 8
4436 && int_size_in_bytes (type
) < 16))
4438 else if (ALTIVEC_VECTOR_MODE (mode
)
4439 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4440 && int_size_in_bytes (type
) >= 16))
4442 else if (rs6000_darwin64_abi
&& mode
== BLKmode
4443 && type
&& TYPE_ALIGN (type
) > 64)
4446 return PARM_BOUNDARY
;
4449 /* For a function parm of MODE and TYPE, return the starting word in
4450 the parameter area. NWORDS of the parameter area are already used. */
4453 rs6000_parm_start (enum machine_mode mode
, tree type
, unsigned int nwords
)
4456 unsigned int parm_offset
;
4458 align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
4459 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
4460 return nwords
+ (-(parm_offset
+ nwords
) & align
);
4463 /* Compute the size (in words) of a function argument. */
4465 static unsigned long
4466 rs6000_arg_size (enum machine_mode mode
, tree type
)
4470 if (mode
!= BLKmode
)
4471 size
= GET_MODE_SIZE (mode
);
4473 size
= int_size_in_bytes (type
);
4476 return (size
+ 3) >> 2;
4478 return (size
+ 7) >> 3;
4481 /* Use this to flush pending int fields. */
4484 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
4485 HOST_WIDE_INT bitpos
)
4487 unsigned int startbit
, endbit
;
4488 int intregs
, intoffset
;
4489 enum machine_mode mode
;
4491 if (cum
->intoffset
== -1)
4494 intoffset
= cum
->intoffset
;
4495 cum
->intoffset
= -1;
4497 if (intoffset
% BITS_PER_WORD
!= 0)
4499 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4501 if (mode
== BLKmode
)
4503 /* We couldn't find an appropriate mode, which happens,
4504 e.g., in packed structs when there are 3 bytes to load.
4505 Back intoffset back to the beginning of the word in this
4507 intoffset
= intoffset
& -BITS_PER_WORD
;
4511 startbit
= intoffset
& -BITS_PER_WORD
;
4512 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4513 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
4514 cum
->words
+= intregs
;
4517 /* The darwin64 ABI calls for us to recurse down through structs,
4518 looking for elements passed in registers. Unfortunately, we have
4519 to track int register count here also because of misalignments
4520 in powerpc alignment mode. */
4523 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
4525 HOST_WIDE_INT startbitpos
)
4529 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
4530 if (TREE_CODE (f
) == FIELD_DECL
)
4532 HOST_WIDE_INT bitpos
= startbitpos
;
4533 tree ftype
= TREE_TYPE (f
);
4534 enum machine_mode mode
= TYPE_MODE (ftype
);
4536 if (DECL_SIZE (f
) != 0
4537 && host_integerp (bit_position (f
), 1))
4538 bitpos
+= int_bit_position (f
);
4540 /* ??? FIXME: else assume zero offset. */
4542 if (TREE_CODE (ftype
) == RECORD_TYPE
)
4543 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
4544 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
4546 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
4547 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
4548 cum
->words
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
4550 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
4552 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
4556 else if (cum
->intoffset
== -1)
4557 cum
->intoffset
= bitpos
;
4561 /* Update the data in CUM to advance over an argument
4562 of mode MODE and data type TYPE.
4563 (TYPE is null for libcalls where that information may not be available.)
4565 Note that for args passed by reference, function_arg will be called
4566 with MODE and TYPE set to that of the pointer to the arg, not the arg
4570 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4571 tree type
, int named
, int depth
)
4575 /* Only tick off an argument if we're not recursing. */
4577 cum
->nargs_prototype
--;
4579 if (TARGET_ALTIVEC_ABI
4580 && (ALTIVEC_VECTOR_MODE (mode
)
4581 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4582 && int_size_in_bytes (type
) == 16)))
4586 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
4589 if (!TARGET_ALTIVEC
)
4590 error ("cannot pass argument in vector register because"
4591 " altivec instructions are disabled, use -maltivec"
4594 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4595 even if it is going to be passed in a vector register.
4596 Darwin does the same for variable-argument functions. */
4597 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
4598 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
4608 /* Vector parameters must be 16-byte aligned. This places
4609 them at 2 mod 4 in terms of words in 32-bit mode, since
4610 the parameter save area starts at offset 24 from the
4611 stack. In 64-bit mode, they just have to start on an
4612 even word, since the parameter save area is 16-byte
4613 aligned. Space for GPRs is reserved even if the argument
4614 will be passed in memory. */
4616 align
= (2 - cum
->words
) & 3;
4618 align
= cum
->words
& 1;
4619 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
4621 if (TARGET_DEBUG_ARG
)
4623 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
4625 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
4626 cum
->nargs_prototype
, cum
->prototype
,
4627 GET_MODE_NAME (mode
));
4631 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
4633 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
4636 else if (rs6000_darwin64_abi
4638 && TREE_CODE (type
) == RECORD_TYPE
4639 && (size
= int_size_in_bytes (type
)) > 0)
4641 /* Variable sized types have size == -1 and are
4642 treated as if consisting entirely of ints.
4643 Pad to 16 byte boundary if needed. */
4644 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
4645 && (cum
->words
% 2) != 0)
4647 /* For varargs, we can just go up by the size of the struct. */
4649 cum
->words
+= (size
+ 7) / 8;
4652 /* It is tempting to say int register count just goes up by
4653 sizeof(type)/8, but this is wrong in a case such as
4654 { int; double; int; } [powerpc alignment]. We have to
4655 grovel through the fields for these too. */
4657 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
4658 rs6000_darwin64_record_arg_advance_flush (cum
,
4659 size
* BITS_PER_UNIT
);
4662 else if (DEFAULT_ABI
== ABI_V4
)
4664 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
4665 && (mode
== SFmode
|| mode
== DFmode
))
4667 if (cum
->fregno
<= FP_ARG_V4_MAX_REG
)
4672 cum
->words
+= cum
->words
& 1;
4673 cum
->words
+= rs6000_arg_size (mode
, type
);
4678 int n_words
= rs6000_arg_size (mode
, type
);
4679 int gregno
= cum
->sysv_gregno
;
4681 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4682 (r7,r8) or (r9,r10). As does any other 2 word item such
4683 as complex int due to a historical mistake. */
4685 gregno
+= (1 - gregno
) & 1;
4687 /* Multi-reg args are not split between registers and stack. */
4688 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
4690 /* Long long and SPE vectors are aligned on the stack.
4691 So are other 2 word items such as complex int due to
4692 a historical mistake. */
4694 cum
->words
+= cum
->words
& 1;
4695 cum
->words
+= n_words
;
4698 /* Note: continuing to accumulate gregno past when we've started
4699 spilling to the stack indicates the fact that we've started
4700 spilling to the stack to expand_builtin_saveregs. */
4701 cum
->sysv_gregno
= gregno
+ n_words
;
4704 if (TARGET_DEBUG_ARG
)
4706 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
4707 cum
->words
, cum
->fregno
);
4708 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
4709 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
4710 fprintf (stderr
, "mode = %4s, named = %d\n",
4711 GET_MODE_NAME (mode
), named
);
4716 int n_words
= rs6000_arg_size (mode
, type
);
4717 int start_words
= cum
->words
;
4718 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
4720 cum
->words
= align_words
+ n_words
;
4722 if (SCALAR_FLOAT_MODE_P (mode
)
4723 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4724 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
4726 if (TARGET_DEBUG_ARG
)
4728 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
4729 cum
->words
, cum
->fregno
);
4730 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
4731 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
4732 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
4733 named
, align_words
- start_words
, depth
);
4739 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
4746 r1
= gen_rtx_REG (DImode
, gregno
);
4747 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
4748 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
4751 r1
= gen_rtx_REG (DImode
, gregno
);
4752 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
4753 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
4754 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
4755 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
4762 /* Determine where to put a SIMD argument on the SPE. */
4764 rs6000_spe_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4767 int gregno
= cum
->sysv_gregno
;
4769 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4770 are passed and returned in a pair of GPRs for ABI compatibility. */
4771 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DCmode
))
4773 int n_words
= rs6000_arg_size (mode
, type
);
4775 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4777 gregno
+= (1 - gregno
) & 1;
4779 /* Multi-reg args are not split between registers and stack. */
4780 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
4783 return spe_build_register_parallel (mode
, gregno
);
4787 int n_words
= rs6000_arg_size (mode
, type
);
4789 /* SPE vectors are put in odd registers. */
4790 if (n_words
== 2 && (gregno
& 1) == 0)
4793 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
4796 enum machine_mode m
= SImode
;
4798 r1
= gen_rtx_REG (m
, gregno
);
4799 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
4800 r2
= gen_rtx_REG (m
, gregno
+ 1);
4801 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
4802 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
4809 if (gregno
<= GP_ARG_MAX_REG
)
4810 return gen_rtx_REG (mode
, gregno
);
4816 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4817 structure between cum->intoffset and bitpos to integer registers. */
4820 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
4821 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
4823 enum machine_mode mode
;
4825 unsigned int startbit
, endbit
;
4826 int this_regno
, intregs
, intoffset
;
4829 if (cum
->intoffset
== -1)
4832 intoffset
= cum
->intoffset
;
4833 cum
->intoffset
= -1;
4835 /* If this is the trailing part of a word, try to only load that
4836 much into the register. Otherwise load the whole register. Note
4837 that in the latter case we may pick up unwanted bits. It's not a
4838 problem at the moment but may wish to revisit. */
4840 if (intoffset
% BITS_PER_WORD
!= 0)
4842 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4844 if (mode
== BLKmode
)
4846 /* We couldn't find an appropriate mode, which happens,
4847 e.g., in packed structs when there are 3 bytes to load.
4848 Back intoffset back to the beginning of the word in this
4850 intoffset
= intoffset
& -BITS_PER_WORD
;
4857 startbit
= intoffset
& -BITS_PER_WORD
;
4858 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4859 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
4860 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
4862 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
4865 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
4869 intoffset
/= BITS_PER_UNIT
;
4872 regno
= GP_ARG_MIN_REG
+ this_regno
;
4873 reg
= gen_rtx_REG (mode
, regno
);
4875 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
4878 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
4882 while (intregs
> 0);
4885 /* Recursive workhorse for the following. */
4888 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, tree type
,
4889 HOST_WIDE_INT startbitpos
, rtx rvec
[],
4894 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
4895 if (TREE_CODE (f
) == FIELD_DECL
)
4897 HOST_WIDE_INT bitpos
= startbitpos
;
4898 tree ftype
= TREE_TYPE (f
);
4899 enum machine_mode mode
= TYPE_MODE (ftype
);
4901 if (DECL_SIZE (f
) != 0
4902 && host_integerp (bit_position (f
), 1))
4903 bitpos
+= int_bit_position (f
);
4905 /* ??? FIXME: else assume zero offset. */
4907 if (TREE_CODE (ftype
) == RECORD_TYPE
)
4908 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
4909 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
4914 case SCmode
: mode
= SFmode
; break;
4915 case DCmode
: mode
= DFmode
; break;
4916 case TCmode
: mode
= TFmode
; break;
4920 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
4922 = gen_rtx_EXPR_LIST (VOIDmode
,
4923 gen_rtx_REG (mode
, cum
->fregno
++),
4924 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4928 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
4930 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
4932 = gen_rtx_EXPR_LIST (VOIDmode
,
4933 gen_rtx_REG (mode
, cum
->vregno
++),
4934 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4936 else if (cum
->intoffset
== -1)
4937 cum
->intoffset
= bitpos
;
4941 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4942 the register(s) to be used for each field and subfield of a struct
4943 being passed by value, along with the offset of where the
4944 register's value may be found in the block. FP fields go in FP
4945 register, vector fields go in vector registers, and everything
4946 else goes in int registers, packed as in memory.
4948 This code is also used for function return values. RETVAL indicates
4949 whether this is the case.
4951 Much of this is taken from the SPARC V9 port, which has a similar
4952 calling convention. */
4955 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, tree type
,
4956 int named
, bool retval
)
4958 rtx rvec
[FIRST_PSEUDO_REGISTER
];
4959 int k
= 1, kbase
= 1;
4960 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
4961 /* This is a copy; modifications are not visible to our caller. */
4962 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
4963 CUMULATIVE_ARGS
*cum
= ©_cum
;
4965 /* Pad to 16 byte boundary if needed. */
4966 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
4967 && (cum
->words
% 2) != 0)
4974 /* Put entries into rvec[] for individual FP and vector fields, and
4975 for the chunks of memory that go in int regs. Note we start at
4976 element 1; 0 is reserved for an indication of using memory, and
4977 may or may not be filled in below. */
4978 rs6000_darwin64_record_arg_recurse (cum
, type
, 0, rvec
, &k
);
4979 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
4981 /* If any part of the struct went on the stack put all of it there.
4982 This hack is because the generic code for
4983 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4984 parts of the struct are not at the beginning. */
4988 return NULL_RTX
; /* doesn't go in registers at all */
4990 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4992 if (k
> 1 || cum
->use_stack
)
4993 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
4998 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5001 rs6000_mixed_function_arg (enum machine_mode mode
, tree type
, int align_words
)
5005 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5007 if (align_words
>= GP_ARG_NUM_REG
)
5010 n_units
= rs6000_arg_size (mode
, type
);
5012 /* Optimize the simple case where the arg fits in one gpr, except in
5013 the case of BLKmode due to assign_parms assuming that registers are
5014 BITS_PER_WORD wide. */
5016 || (n_units
== 1 && mode
!= BLKmode
))
5017 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5020 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
5021 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5022 using a magic NULL_RTX component.
5023 FIXME: This is not strictly correct. Only some of the arg
5024 belongs in memory, not all of it. However, there isn't any way
5025 to do this currently, apart from building rtx descriptions for
5026 the pieces of memory we want stored. Due to bugs in the generic
5027 code we can't use the normal function_arg_partial_nregs scheme
5028 with the PARALLEL arg description we emit here.
5029 In any case, the code to store the whole arg to memory is often
5030 more efficient than code to store pieces, and we know that space
5031 is available in the right place for the whole arg. */
5032 /* FIXME: This should be fixed since the conversion to
5033 TARGET_ARG_PARTIAL_BYTES. */
5034 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5039 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
5040 rtx off
= GEN_INT (i
++ * 4);
5041 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
5043 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
5045 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5048 /* Determine where to put an argument to a function.
5049 Value is zero to push the argument on the stack,
5050 or a hard register in which to store the argument.
5052 MODE is the argument's machine mode.
5053 TYPE is the data type of the argument (as a tree).
5054 This is null for libcalls where that information may
5056 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5057 the preceding args and about the function being called. It is
5058 not modified in this routine.
5059 NAMED is nonzero if this argument is a named parameter
5060 (otherwise it is an extra parameter matching an ellipsis).
5062 On RS/6000 the first eight words of non-FP are normally in registers
5063 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5064 Under V.4, the first 8 FP args are in registers.
5066 If this is floating-point and no prototype is specified, we use
5067 both an FP and integer register (or possibly FP reg and stack). Library
5068 functions (when CALL_LIBCALL is set) always have the proper types for args,
5069 so we can pass the FP value just in one register. emit_library_function
5070 doesn't support PARALLEL anyway.
5072 Note that for args passed by reference, function_arg will be called
5073 with MODE and TYPE set to that of the pointer to the arg, not the arg
5077 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5078 tree type
, int named
)
5080 enum rs6000_abi abi
= DEFAULT_ABI
;
5082 /* Return a marker to indicate whether CR1 needs to set or clear the
5083 bit that V.4 uses to say fp args were passed in registers.
5084 Assume that we don't need the marker for software floating point,
5085 or compiler generated library calls. */
5086 if (mode
== VOIDmode
)
5089 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
5091 || (cum
->nargs_prototype
< 0
5092 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
5094 /* For the SPE, we need to crxor CR6 always. */
5096 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
5097 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5098 return GEN_INT (cum
->call_cookie
5099 | ((cum
->fregno
== FP_ARG_MIN_REG
)
5100 ? CALL_V4_SET_FP_ARGS
5101 : CALL_V4_CLEAR_FP_ARGS
));
5104 return GEN_INT (cum
->call_cookie
);
5107 if (rs6000_darwin64_abi
&& mode
== BLKmode
5108 && TREE_CODE (type
) == RECORD_TYPE
)
5110 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, false);
5111 if (rslt
!= NULL_RTX
)
5113 /* Else fall through to usual handling. */
5116 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5117 if (TARGET_64BIT
&& ! cum
->prototype
)
5119 /* Vector parameters get passed in vector register
5120 and also in GPRs or memory, in absence of prototype. */
5123 align_words
= (cum
->words
+ 1) & ~1;
5125 if (align_words
>= GP_ARG_NUM_REG
)
5131 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5133 return gen_rtx_PARALLEL (mode
,
5135 gen_rtx_EXPR_LIST (VOIDmode
,
5137 gen_rtx_EXPR_LIST (VOIDmode
,
5138 gen_rtx_REG (mode
, cum
->vregno
),
5142 return gen_rtx_REG (mode
, cum
->vregno
);
5143 else if (TARGET_ALTIVEC_ABI
5144 && (ALTIVEC_VECTOR_MODE (mode
)
5145 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5146 && int_size_in_bytes (type
) == 16)))
5148 if (named
|| abi
== ABI_V4
)
5152 /* Vector parameters to varargs functions under AIX or Darwin
5153 get passed in memory and possibly also in GPRs. */
5154 int align
, align_words
, n_words
;
5155 enum machine_mode part_mode
;
5157 /* Vector parameters must be 16-byte aligned. This places them at
5158 2 mod 4 in terms of words in 32-bit mode, since the parameter
5159 save area starts at offset 24 from the stack. In 64-bit mode,
5160 they just have to start on an even word, since the parameter
5161 save area is 16-byte aligned. */
5163 align
= (2 - cum
->words
) & 3;
5165 align
= cum
->words
& 1;
5166 align_words
= cum
->words
+ align
;
5168 /* Out of registers? Memory, then. */
5169 if (align_words
>= GP_ARG_NUM_REG
)
5172 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5173 return rs6000_mixed_function_arg (mode
, type
, align_words
);
5175 /* The vector value goes in GPRs. Only the part of the
5176 value in GPRs is reported here. */
5178 n_words
= rs6000_arg_size (mode
, type
);
5179 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
5180 /* Fortunately, there are only two possibilities, the value
5181 is either wholly in GPRs or half in GPRs and half not. */
5184 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
5187 else if (TARGET_SPE_ABI
&& TARGET_SPE
5188 && (SPE_VECTOR_MODE (mode
)
5189 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
5190 || mode
== DCmode
))))
5191 return rs6000_spe_function_arg (cum
, mode
, type
);
5193 else if (abi
== ABI_V4
)
5195 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5196 && (mode
== SFmode
|| mode
== DFmode
))
5198 if (cum
->fregno
<= FP_ARG_V4_MAX_REG
)
5199 return gen_rtx_REG (mode
, cum
->fregno
);
5205 int n_words
= rs6000_arg_size (mode
, type
);
5206 int gregno
= cum
->sysv_gregno
;
5208 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5209 (r7,r8) or (r9,r10). As does any other 2 word item such
5210 as complex int due to a historical mistake. */
5212 gregno
+= (1 - gregno
) & 1;
5214 /* Multi-reg args are not split between registers and stack. */
5215 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5218 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5219 return rs6000_mixed_function_arg (mode
, type
,
5220 gregno
- GP_ARG_MIN_REG
);
5221 return gen_rtx_REG (mode
, gregno
);
5226 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
5228 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
5230 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5234 enum machine_mode fmode
= mode
;
5235 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
5237 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
5239 /* Currently, we only ever need one reg here because complex
5240 doubles are split. */
5241 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
&& fmode
== TFmode
);
5243 /* Long double split over regs and memory. */
5247 /* Do we also need to pass this arg in the parameter save
5250 && (cum
->nargs_prototype
<= 0
5251 || (DEFAULT_ABI
== ABI_AIX
5253 && align_words
>= GP_ARG_NUM_REG
)));
5255 if (!needs_psave
&& mode
== fmode
)
5256 return gen_rtx_REG (fmode
, cum
->fregno
);
5261 /* Describe the part that goes in gprs or the stack.
5262 This piece must come first, before the fprs. */
5263 if (align_words
< GP_ARG_NUM_REG
)
5265 unsigned long n_words
= rs6000_arg_size (mode
, type
);
5267 if (align_words
+ n_words
> GP_ARG_NUM_REG
5268 || (TARGET_32BIT
&& TARGET_POWERPC64
))
5270 /* If this is partially on the stack, then we only
5271 include the portion actually in registers here. */
5272 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
5275 if (align_words
+ n_words
> GP_ARG_NUM_REG
5276 && (TARGET_32BIT
&& TARGET_POWERPC64
))
5277 /* Not all of the arg fits in gprs. Say that it
5278 goes in memory too, using a magic NULL_RTX
5279 component. Also see comment in
5280 rs6000_mixed_function_arg for why the normal
5281 function_arg_partial_nregs scheme doesn't work
5283 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
5287 r
= gen_rtx_REG (rmode
,
5288 GP_ARG_MIN_REG
+ align_words
);
5289 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
5290 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
5292 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
5296 /* The whole arg fits in gprs. */
5297 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5298 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
5302 /* It's entirely in memory. */
5303 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5306 /* Describe where this piece goes in the fprs. */
5307 r
= gen_rtx_REG (fmode
, cum
->fregno
);
5308 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
5310 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5312 else if (align_words
< GP_ARG_NUM_REG
)
5314 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5315 return rs6000_mixed_function_arg (mode
, type
, align_words
);
5317 if (mode
== BLKmode
)
5320 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5327 /* For an arg passed partly in registers and partly in memory, this is
5328 the number of bytes passed in registers. For args passed entirely in
5329 registers or entirely in memory, zero. When an arg is described by a
5330 PARALLEL, perhaps using more than one register type, this function
5331 returns the number of bytes used by the first element of the PARALLEL. */
5334 rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5335 tree type
, bool named
)
5340 if (DEFAULT_ABI
== ABI_V4
)
5343 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
5344 && cum
->nargs_prototype
>= 0)
5347 /* In this complicated case we just disable the partial_nregs code. */
5348 if (rs6000_darwin64_abi
&& mode
== BLKmode
5349 && TREE_CODE (type
) == RECORD_TYPE
5350 && int_size_in_bytes (type
) > 0)
5353 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
5355 if (USE_FP_FOR_ARG_P (cum
, mode
, type
)
5356 /* If we are passing this arg in the fixed parameter save area
5357 (gprs or memory) as well as fprs, then this function should
5358 return the number of bytes passed in the parameter save area
5359 rather than bytes passed in fprs. */
5361 && (cum
->nargs_prototype
<= 0
5362 || (DEFAULT_ABI
== ABI_AIX
5364 && align_words
>= GP_ARG_NUM_REG
))))
5366 if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3) > FP_ARG_MAX_REG
+ 1)
5367 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
5368 else if (cum
->nargs_prototype
>= 0)
5372 if (align_words
< GP_ARG_NUM_REG
5373 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
5374 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
5376 if (ret
!= 0 && TARGET_DEBUG_ARG
)
5377 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
5382 /* A C expression that indicates when an argument must be passed by
5383 reference. If nonzero for an argument, a copy of that argument is
5384 made in memory and a pointer to the argument is passed instead of
5385 the argument itself. The pointer is passed in whatever way is
5386 appropriate for passing a pointer to that type.
5388 Under V.4, aggregates and long double are passed by reference.
5390 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5391 reference unless the AltiVec vector extension ABI is in force.
5393 As an extension to all ABIs, variable sized types are passed by
5397 rs6000_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5398 enum machine_mode mode
, tree type
,
5399 bool named ATTRIBUTE_UNUSED
)
5401 if (DEFAULT_ABI
== ABI_V4
&& mode
== TFmode
)
5403 if (TARGET_DEBUG_ARG
)
5404 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
5411 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
5413 if (TARGET_DEBUG_ARG
)
5414 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
5418 if (int_size_in_bytes (type
) < 0)
5420 if (TARGET_DEBUG_ARG
)
5421 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
5425 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5426 modes only exist for GCC vector types if -maltivec. */
5427 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
5429 if (TARGET_DEBUG_ARG
)
5430 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
5434 /* Pass synthetic vectors in memory. */
5435 if (TREE_CODE (type
) == VECTOR_TYPE
5436 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
5438 static bool warned_for_pass_big_vectors
= false;
5439 if (TARGET_DEBUG_ARG
)
5440 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
5441 if (!warned_for_pass_big_vectors
)
5443 warning (0, "GCC vector passed by reference: "
5444 "non-standard ABI extension with no compatibility guarantee");
5445 warned_for_pass_big_vectors
= true;
5454 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
5457 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
5462 for (i
= 0; i
< nregs
; i
++)
5464 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
5465 if (reload_completed
)
5467 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
5470 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
5471 i
* GET_MODE_SIZE (reg_mode
));
5474 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
5478 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
5482 /* Perform any needed actions needed for a function that is receiving a
5483 variable number of arguments.
5487 MODE and TYPE are the mode and type of the current parameter.
5489 PRETEND_SIZE is a variable that should be set to the amount of stack
5490 that must be pushed by the prolog to pretend that our caller pushed
5493 Normally, this macro will push all remaining incoming registers on the
5494 stack and set PRETEND_SIZE to the length of the registers pushed. */
5497 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5498 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5501 CUMULATIVE_ARGS next_cum
;
5502 int reg_size
= TARGET_32BIT
? 4 : 8;
5503 rtx save_area
= NULL_RTX
, mem
;
5504 int first_reg_offset
, set
;
5506 /* Skip the last named argument. */
5508 function_arg_advance (&next_cum
, mode
, type
, 1, 0);
5510 if (DEFAULT_ABI
== ABI_V4
)
5512 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
5516 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
5517 HOST_WIDE_INT offset
= 0;
5519 /* Try to optimize the size of the varargs save area.
5520 The ABI requires that ap.reg_save_area is doubleword
5521 aligned, but we don't need to allocate space for all
5522 the bytes, only those to which we actually will save
5524 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
5525 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
5526 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5527 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
5528 && cfun
->va_list_fpr_size
)
5531 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
5532 * UNITS_PER_FP_WORD
;
5533 if (cfun
->va_list_fpr_size
5534 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
5535 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
5537 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
5538 * UNITS_PER_FP_WORD
;
5542 offset
= -((first_reg_offset
* reg_size
) & ~7);
5543 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
5545 gpr_reg_num
= cfun
->va_list_gpr_size
;
5546 if (reg_size
== 4 && (first_reg_offset
& 1))
5549 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
5552 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
5554 - (int) (GP_ARG_NUM_REG
* reg_size
);
5556 if (gpr_size
+ fpr_size
)
5559 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
5560 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
5561 reg_save_area
= XEXP (reg_save_area
, 0);
5562 if (GET_CODE (reg_save_area
) == PLUS
)
5564 gcc_assert (XEXP (reg_save_area
, 0)
5565 == virtual_stack_vars_rtx
);
5566 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
5567 offset
+= INTVAL (XEXP (reg_save_area
, 1));
5570 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
5573 cfun
->machine
->varargs_save_offset
= offset
;
5574 save_area
= plus_constant (virtual_stack_vars_rtx
, offset
);
5579 first_reg_offset
= next_cum
.words
;
5580 save_area
= virtual_incoming_args_rtx
;
5582 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5583 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
5586 set
= get_varargs_alias_set ();
5587 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
5588 && cfun
->va_list_gpr_size
)
5590 int nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
5592 if (va_list_gpr_counter_field
)
5594 /* V4 va_list_gpr_size counts number of registers needed. */
5595 if (nregs
> cfun
->va_list_gpr_size
)
5596 nregs
= cfun
->va_list_gpr_size
;
5600 /* char * va_list instead counts number of bytes needed. */
5601 if (nregs
> cfun
->va_list_gpr_size
/ reg_size
)
5602 nregs
= cfun
->va_list_gpr_size
/ reg_size
;
5605 mem
= gen_rtx_MEM (BLKmode
,
5606 plus_constant (save_area
,
5607 first_reg_offset
* reg_size
));
5608 MEM_NOTRAP_P (mem
) = 1;
5609 set_mem_alias_set (mem
, set
);
5610 set_mem_align (mem
, BITS_PER_WORD
);
5612 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
5616 /* Save FP registers if needed. */
5617 if (DEFAULT_ABI
== ABI_V4
5618 && TARGET_HARD_FLOAT
&& TARGET_FPRS
5620 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
5621 && cfun
->va_list_fpr_size
)
5623 int fregno
= next_cum
.fregno
, nregs
;
5624 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
5625 rtx lab
= gen_label_rtx ();
5626 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
5627 * UNITS_PER_FP_WORD
);
5630 (gen_rtx_SET (VOIDmode
,
5632 gen_rtx_IF_THEN_ELSE (VOIDmode
,
5633 gen_rtx_NE (VOIDmode
, cr1
,
5635 gen_rtx_LABEL_REF (VOIDmode
, lab
),
5639 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
5640 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
5642 mem
= gen_rtx_MEM (DFmode
, plus_constant (save_area
, off
));
5643 MEM_NOTRAP_P (mem
) = 1;
5644 set_mem_alias_set (mem
, set
);
5645 set_mem_align (mem
, GET_MODE_ALIGNMENT (DFmode
));
5646 emit_move_insn (mem
, gen_rtx_REG (DFmode
, fregno
));
5653 /* Create the va_list data type. */
5656 rs6000_build_builtin_va_list (void)
5658 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
5660 /* For AIX, prefer 'char *' because that's what the system
5661 header files like. */
5662 if (DEFAULT_ABI
!= ABI_V4
)
5663 return build_pointer_type (char_type_node
);
5665 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5666 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5668 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gpr"),
5669 unsigned_char_type_node
);
5670 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fpr"),
5671 unsigned_char_type_node
);
5672 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5674 f_res
= build_decl (FIELD_DECL
, get_identifier ("reserved"),
5675 short_unsigned_type_node
);
5676 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
5678 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
5681 va_list_gpr_counter_field
= f_gpr
;
5682 va_list_fpr_counter_field
= f_fpr
;
5684 DECL_FIELD_CONTEXT (f_gpr
) = record
;
5685 DECL_FIELD_CONTEXT (f_fpr
) = record
;
5686 DECL_FIELD_CONTEXT (f_res
) = record
;
5687 DECL_FIELD_CONTEXT (f_ovf
) = record
;
5688 DECL_FIELD_CONTEXT (f_sav
) = record
;
5690 TREE_CHAIN (record
) = type_decl
;
5691 TYPE_NAME (record
) = type_decl
;
5692 TYPE_FIELDS (record
) = f_gpr
;
5693 TREE_CHAIN (f_gpr
) = f_fpr
;
5694 TREE_CHAIN (f_fpr
) = f_res
;
5695 TREE_CHAIN (f_res
) = f_ovf
;
5696 TREE_CHAIN (f_ovf
) = f_sav
;
5698 layout_type (record
);
5700 /* The correct type is an array type of one element. */
5701 return build_array_type (record
, build_index_type (size_zero_node
));
5704 /* Implement va_start. */
5707 rs6000_va_start (tree valist
, rtx nextarg
)
5709 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
5710 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
5711 tree gpr
, fpr
, ovf
, sav
, t
;
5713 /* Only SVR4 needs something special. */
5714 if (DEFAULT_ABI
!= ABI_V4
)
5716 std_expand_builtin_va_start (valist
, nextarg
);
5720 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
5721 f_fpr
= TREE_CHAIN (f_gpr
);
5722 f_res
= TREE_CHAIN (f_fpr
);
5723 f_ovf
= TREE_CHAIN (f_res
);
5724 f_sav
= TREE_CHAIN (f_ovf
);
5726 valist
= build_va_arg_indirect_ref (valist
);
5727 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
5728 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
5729 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
5730 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
5732 /* Count number of gp and fp argument registers used. */
5733 words
= current_function_args_info
.words
;
5734 n_gpr
= MIN (current_function_args_info
.sysv_gregno
- GP_ARG_MIN_REG
,
5736 n_fpr
= MIN (current_function_args_info
.fregno
- FP_ARG_MIN_REG
,
5739 if (TARGET_DEBUG_ARG
)
5740 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
5741 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
5742 words
, n_gpr
, n_fpr
);
5744 if (cfun
->va_list_gpr_size
)
5746 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
5747 build_int_cst (NULL_TREE
, n_gpr
));
5748 TREE_SIDE_EFFECTS (t
) = 1;
5749 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5752 if (cfun
->va_list_fpr_size
)
5754 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
5755 build_int_cst (NULL_TREE
, n_fpr
));
5756 TREE_SIDE_EFFECTS (t
) = 1;
5757 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5760 /* Find the overflow area. */
5761 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
5763 t
= build2 (PLUS_EXPR
, TREE_TYPE (ovf
), t
,
5764 build_int_cst (NULL_TREE
, words
* UNITS_PER_WORD
));
5765 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
5766 TREE_SIDE_EFFECTS (t
) = 1;
5767 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5769 /* If there were no va_arg invocations, don't set up the register
5771 if (!cfun
->va_list_gpr_size
5772 && !cfun
->va_list_fpr_size
5773 && n_gpr
< GP_ARG_NUM_REG
5774 && n_fpr
< FP_ARG_V4_MAX_REG
)
5777 /* Find the register save area. */
5778 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
5779 if (cfun
->machine
->varargs_save_offset
)
5780 t
= build2 (PLUS_EXPR
, TREE_TYPE (sav
), t
,
5781 build_int_cst (NULL_TREE
, cfun
->machine
->varargs_save_offset
));
5782 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
5783 TREE_SIDE_EFFECTS (t
) = 1;
5784 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5787 /* Implement va_arg. */
5790 rs6000_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
5792 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
5793 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
5794 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
5795 tree lab_false
, lab_over
, addr
;
5797 tree ptrtype
= build_pointer_type (type
);
5799 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
5801 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
5802 return build_va_arg_indirect_ref (t
);
5805 if (DEFAULT_ABI
!= ABI_V4
)
5807 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
5809 tree elem_type
= TREE_TYPE (type
);
5810 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
5811 int elem_size
= GET_MODE_SIZE (elem_mode
);
5813 if (elem_size
< UNITS_PER_WORD
)
5815 tree real_part
, imag_part
;
5816 tree post
= NULL_TREE
;
5818 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
5820 /* Copy the value into a temporary, lest the formal temporary
5821 be reused out from under us. */
5822 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
5823 append_to_statement_list (post
, pre_p
);
5825 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
5828 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
5832 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5835 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
5836 f_fpr
= TREE_CHAIN (f_gpr
);
5837 f_res
= TREE_CHAIN (f_fpr
);
5838 f_ovf
= TREE_CHAIN (f_res
);
5839 f_sav
= TREE_CHAIN (f_ovf
);
5841 valist
= build_va_arg_indirect_ref (valist
);
5842 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
5843 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
5844 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
5845 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
5847 size
= int_size_in_bytes (type
);
5848 rsize
= (size
+ 3) / 4;
5851 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5852 && (TYPE_MODE (type
) == SFmode
|| TYPE_MODE (type
) == DFmode
))
5854 /* FP args go in FP registers, if present. */
5859 if (TYPE_MODE (type
) == DFmode
)
5864 /* Otherwise into GP registers. */
5873 /* Pull the value out of the saved registers.... */
5876 addr
= create_tmp_var (ptr_type_node
, "addr");
5877 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
5879 /* AltiVec vectors never go in registers when -mabi=altivec. */
5880 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
5884 lab_false
= create_artificial_label ();
5885 lab_over
= create_artificial_label ();
5887 /* Long long and SPE vectors are aligned in the registers.
5888 As are any other 2 gpr item such as complex int due to a
5889 historical mistake. */
5893 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), reg
,
5894 size_int (n_reg
- 1));
5895 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, u
);
5898 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
5899 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
5900 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
5901 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
5902 gimplify_and_add (t
, pre_p
);
5906 t
= build2 (PLUS_EXPR
, ptr_type_node
, sav
, size_int (sav_ofs
));
5908 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, size_int (n_reg
));
5909 u
= build1 (CONVERT_EXPR
, integer_type_node
, u
);
5910 u
= build2 (MULT_EXPR
, integer_type_node
, u
, size_int (sav_scale
));
5911 t
= build2 (PLUS_EXPR
, ptr_type_node
, t
, u
);
5913 t
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
5914 gimplify_and_add (t
, pre_p
);
5916 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
5917 gimplify_and_add (t
, pre_p
);
5919 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
5920 append_to_statement_list (t
, pre_p
);
5924 /* Ensure that we don't find any more args in regs.
5925 Alignment has taken care of the n_reg == 2 case. */
5926 t
= build2 (MODIFY_EXPR
, TREE_TYPE (reg
), reg
, size_int (8));
5927 gimplify_and_add (t
, pre_p
);
5931 /* ... otherwise out of the overflow area. */
5933 /* Care for on-stack alignment if needed. */
5937 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (align
- 1));
5938 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
5939 build_int_cst (NULL_TREE
, -align
));
5941 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
5943 u
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
5944 gimplify_and_add (u
, pre_p
);
5946 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
5947 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
5948 gimplify_and_add (t
, pre_p
);
5952 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
5953 append_to_statement_list (t
, pre_p
);
5956 addr
= fold_convert (ptrtype
, addr
);
5957 return build_va_arg_indirect_ref (addr
);
5963 def_builtin (int mask
, const char *name
, tree type
, int code
)
5965 if (mask
& target_flags
)
5967 if (rs6000_builtin_decls
[code
])
5970 rs6000_builtin_decls
[code
] =
5971 lang_hooks
.builtin_function (name
, type
, code
, BUILT_IN_MD
,
5976 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5978 static const struct builtin_description bdesc_3arg
[] =
5980 { MASK_ALTIVEC
, CODE_FOR_altivec_vmaddfp
, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP
},
5981 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhaddshs
, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS
},
5982 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhraddshs
, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS
},
5983 { MASK_ALTIVEC
, CODE_FOR_altivec_vmladduhm
, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM
},
5984 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumubm
, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM
},
5985 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsummbm
, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM
},
5986 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhm
, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM
},
5987 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshm
, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM
},
5988 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhs
, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS
},
5989 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshs
, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS
},
5990 { MASK_ALTIVEC
, CODE_FOR_altivec_vnmsubfp
, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP
},
5991 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4sf
, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF
},
5992 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4si
, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI
},
5993 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v8hi
, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI
},
5994 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v16qi
, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI
},
5995 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4sf
, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF
},
5996 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4si
, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI
},
5997 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v8hi
, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI
},
5998 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v16qi
, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI
},
5999 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v16qi
, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI
},
6000 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v8hi
, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI
},
6001 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4si
, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI
},
6002 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4sf
, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF
},
6004 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD
},
6005 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS
},
6006 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD
},
6007 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS
},
6008 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM
},
6009 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM
},
6010 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM
},
6011 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM
},
6012 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM
},
6013 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS
},
6014 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS
},
6015 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS
},
6016 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB
},
6017 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM
},
6018 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL
},
6021 /* DST operations: void foo (void *, const int, const char). */
6023 static const struct builtin_description bdesc_dst
[] =
6025 { MASK_ALTIVEC
, CODE_FOR_altivec_dst
, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST
},
6026 { MASK_ALTIVEC
, CODE_FOR_altivec_dstt
, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT
},
6027 { MASK_ALTIVEC
, CODE_FOR_altivec_dstst
, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST
},
6028 { MASK_ALTIVEC
, CODE_FOR_altivec_dststt
, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT
},
6030 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST
},
6031 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT
},
6032 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST
},
6033 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT
}
6036 /* Simple binary operations: VECc = foo (VECa, VECb). */
6038 static struct builtin_description bdesc_2arg
[] =
6040 { MASK_ALTIVEC
, CODE_FOR_addv16qi3
, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM
},
6041 { MASK_ALTIVEC
, CODE_FOR_addv8hi3
, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM
},
6042 { MASK_ALTIVEC
, CODE_FOR_addv4si3
, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM
},
6043 { MASK_ALTIVEC
, CODE_FOR_addv4sf3
, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP
},
6044 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddcuw
, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW
},
6045 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddubs
, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS
},
6046 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsbs
, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS
},
6047 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduhs
, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS
},
6048 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddshs
, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS
},
6049 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduws
, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS
},
6050 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsws
, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS
},
6051 { MASK_ALTIVEC
, CODE_FOR_andv4si3
, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND
},
6052 { MASK_ALTIVEC
, CODE_FOR_andcv4si3
, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC
},
6053 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgub
, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB
},
6054 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsb
, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB
},
6055 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguh
, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH
},
6056 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsh
, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH
},
6057 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguw
, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW
},
6058 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsw
, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW
},
6059 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfux
, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX
},
6060 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfsx
, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX
},
6061 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpbfp
, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP
},
6062 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequb
, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB
},
6063 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequh
, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH
},
6064 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequw
, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW
},
6065 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpeqfp
, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP
},
6066 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgefp
, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP
},
6067 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtub
, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB
},
6068 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsb
, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB
},
6069 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuh
, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH
},
6070 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsh
, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH
},
6071 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuw
, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW
},
6072 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsw
, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW
},
6073 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtfp
, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP
},
6074 { MASK_ALTIVEC
, CODE_FOR_altivec_vctsxs
, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS
},
6075 { MASK_ALTIVEC
, CODE_FOR_altivec_vctuxs
, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS
},
6076 { MASK_ALTIVEC
, CODE_FOR_umaxv16qi3
, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB
},
6077 { MASK_ALTIVEC
, CODE_FOR_smaxv16qi3
, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB
},
6078 { MASK_ALTIVEC
, CODE_FOR_umaxv8hi3
, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH
},
6079 { MASK_ALTIVEC
, CODE_FOR_smaxv8hi3
, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH
},
6080 { MASK_ALTIVEC
, CODE_FOR_umaxv4si3
, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW
},
6081 { MASK_ALTIVEC
, CODE_FOR_smaxv4si3
, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW
},
6082 { MASK_ALTIVEC
, CODE_FOR_smaxv4sf3
, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP
},
6083 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB
},
6084 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH
},
6085 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW
},
6086 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB
},
6087 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH
},
6088 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW
},
6089 { MASK_ALTIVEC
, CODE_FOR_uminv16qi3
, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB
},
6090 { MASK_ALTIVEC
, CODE_FOR_sminv16qi3
, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB
},
6091 { MASK_ALTIVEC
, CODE_FOR_uminv8hi3
, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH
},
6092 { MASK_ALTIVEC
, CODE_FOR_sminv8hi3
, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH
},
6093 { MASK_ALTIVEC
, CODE_FOR_uminv4si3
, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW
},
6094 { MASK_ALTIVEC
, CODE_FOR_sminv4si3
, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW
},
6095 { MASK_ALTIVEC
, CODE_FOR_sminv4sf3
, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP
},
6096 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleub
, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB
},
6097 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesb
, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB
},
6098 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleuh
, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH
},
6099 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesh
, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH
},
6100 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuloub
, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB
},
6101 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosb
, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB
},
6102 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulouh
, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH
},
6103 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosh
, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH
},
6104 { MASK_ALTIVEC
, CODE_FOR_altivec_norv4si3
, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR
},
6105 { MASK_ALTIVEC
, CODE_FOR_iorv4si3
, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR
},
6106 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM
},
6107 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM
},
6108 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkpx
, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX
},
6109 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshss
, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS
},
6110 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswss
, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS
},
6111 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhus
, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS
},
6112 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshus
, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS
},
6113 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwus
, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS
},
6114 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswus
, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS
},
6115 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlb
, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB
},
6116 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlh
, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH
},
6117 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlw
, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW
},
6118 { MASK_ALTIVEC
, CODE_FOR_altivec_vslb
, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB
},
6119 { MASK_ALTIVEC
, CODE_FOR_altivec_vslh
, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH
},
6120 { MASK_ALTIVEC
, CODE_FOR_altivec_vslw
, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW
},
6121 { MASK_ALTIVEC
, CODE_FOR_altivec_vsl
, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL
},
6122 { MASK_ALTIVEC
, CODE_FOR_altivec_vslo
, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO
},
6123 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltb
, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB
},
6124 { MASK_ALTIVEC
, CODE_FOR_altivec_vsplth
, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH
},
6125 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltw
, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW
},
6126 { MASK_ALTIVEC
, CODE_FOR_lshrv16qi3
, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB
},
6127 { MASK_ALTIVEC
, CODE_FOR_lshrv8hi3
, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH
},
6128 { MASK_ALTIVEC
, CODE_FOR_lshrv4si3
, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW
},
6129 { MASK_ALTIVEC
, CODE_FOR_ashrv16qi3
, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB
},
6130 { MASK_ALTIVEC
, CODE_FOR_ashrv8hi3
, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH
},
6131 { MASK_ALTIVEC
, CODE_FOR_ashrv4si3
, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW
},
6132 { MASK_ALTIVEC
, CODE_FOR_altivec_vsr
, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR
},
6133 { MASK_ALTIVEC
, CODE_FOR_altivec_vsro
, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO
},
6134 { MASK_ALTIVEC
, CODE_FOR_subv16qi3
, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM
},
6135 { MASK_ALTIVEC
, CODE_FOR_subv8hi3
, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM
},
6136 { MASK_ALTIVEC
, CODE_FOR_subv4si3
, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM
},
6137 { MASK_ALTIVEC
, CODE_FOR_subv4sf3
, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP
},
6138 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubcuw
, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW
},
6139 { MASK_ALTIVEC
, CODE_FOR_altivec_vsububs
, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS
},
6140 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsbs
, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS
},
6141 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuhs
, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS
},
6142 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubshs
, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS
},
6143 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuws
, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS
},
6144 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsws
, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS
},
6145 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4ubs
, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS
},
6146 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4sbs
, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS
},
6147 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4shs
, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS
},
6148 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum2sws
, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS
},
6149 { MASK_ALTIVEC
, CODE_FOR_altivec_vsumsws
, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS
},
6150 { MASK_ALTIVEC
, CODE_FOR_xorv4si3
, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR
},
6152 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD
},
6153 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP
},
6154 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM
},
6155 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM
},
6156 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM
},
6157 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC
},
6158 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS
},
6159 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS
},
6160 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS
},
6161 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS
},
6162 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS
},
6163 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS
},
6164 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS
},
6165 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND
},
6166 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC
},
6167 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG
},
6168 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW
},
6169 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW
},
6170 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH
},
6171 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH
},
6172 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB
},
6173 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB
},
6174 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB
},
6175 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ
},
6176 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP
},
6177 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW
},
6178 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH
},
6179 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB
},
6180 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE
},
6181 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT
},
6182 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP
},
6183 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW
},
6184 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW
},
6185 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH
},
6186 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH
},
6187 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB
},
6188 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB
},
6189 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE
},
6190 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT
},
6191 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX
},
6192 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP
},
6193 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW
},
6194 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW
},
6195 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH
},
6196 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH
},
6197 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB
},
6198 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB
},
6199 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH
},
6200 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW
},
6201 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH
},
6202 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB
},
6203 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL
},
6204 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW
},
6205 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH
},
6206 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB
},
6207 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN
},
6208 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP
},
6209 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW
},
6210 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW
},
6211 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH
},
6212 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH
},
6213 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB
},
6214 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB
},
6215 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE
},
6216 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB
},
6217 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB
},
6218 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH
},
6219 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH
},
6220 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO
},
6221 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH
},
6222 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH
},
6223 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB
},
6224 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB
},
6225 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR
},
6226 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR
},
6227 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK
},
6228 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM
},
6229 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM
},
6230 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX
},
6231 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS
},
6232 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS
},
6233 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS
},
6234 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS
},
6235 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS
},
6236 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU
},
6237 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS
},
6238 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS
},
6239 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL
},
6240 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW
},
6241 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH
},
6242 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB
},
6243 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL
},
6244 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW
},
6245 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH
},
6246 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB
},
6247 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL
},
6248 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO
},
6249 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR
},
6250 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW
},
6251 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH
},
6252 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB
},
6253 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA
},
6254 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW
},
6255 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH
},
6256 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB
},
6257 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL
},
6258 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO
},
6259 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB
},
6260 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP
},
6261 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM
},
6262 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM
},
6263 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM
},
6264 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC
},
6265 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS
},
6266 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS
},
6267 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS
},
6268 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS
},
6269 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS
},
6270 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS
},
6271 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS
},
6272 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S
},
6273 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS
},
6274 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS
},
6275 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS
},
6276 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S
},
6277 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS
},
6278 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR
},
6280 /* Place holder, leave as first spe builtin. */
6281 { 0, CODE_FOR_spe_evaddw
, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW
},
6282 { 0, CODE_FOR_spe_evand
, "__builtin_spe_evand", SPE_BUILTIN_EVAND
},
6283 { 0, CODE_FOR_spe_evandc
, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC
},
6284 { 0, CODE_FOR_spe_evdivws
, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS
},
6285 { 0, CODE_FOR_spe_evdivwu
, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU
},
6286 { 0, CODE_FOR_spe_eveqv
, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV
},
6287 { 0, CODE_FOR_spe_evfsadd
, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD
},
6288 { 0, CODE_FOR_spe_evfsdiv
, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV
},
6289 { 0, CODE_FOR_spe_evfsmul
, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL
},
6290 { 0, CODE_FOR_spe_evfssub
, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB
},
6291 { 0, CODE_FOR_spe_evmergehi
, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI
},
6292 { 0, CODE_FOR_spe_evmergehilo
, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO
},
6293 { 0, CODE_FOR_spe_evmergelo
, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO
},
6294 { 0, CODE_FOR_spe_evmergelohi
, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI
},
6295 { 0, CODE_FOR_spe_evmhegsmfaa
, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA
},
6296 { 0, CODE_FOR_spe_evmhegsmfan
, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN
},
6297 { 0, CODE_FOR_spe_evmhegsmiaa
, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA
},
6298 { 0, CODE_FOR_spe_evmhegsmian
, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN
},
6299 { 0, CODE_FOR_spe_evmhegumiaa
, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA
},
6300 { 0, CODE_FOR_spe_evmhegumian
, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN
},
6301 { 0, CODE_FOR_spe_evmhesmf
, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF
},
6302 { 0, CODE_FOR_spe_evmhesmfa
, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA
},
6303 { 0, CODE_FOR_spe_evmhesmfaaw
, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW
},
6304 { 0, CODE_FOR_spe_evmhesmfanw
, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW
},
6305 { 0, CODE_FOR_spe_evmhesmi
, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI
},
6306 { 0, CODE_FOR_spe_evmhesmia
, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA
},
6307 { 0, CODE_FOR_spe_evmhesmiaaw
, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW
},
6308 { 0, CODE_FOR_spe_evmhesmianw
, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW
},
6309 { 0, CODE_FOR_spe_evmhessf
, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF
},
6310 { 0, CODE_FOR_spe_evmhessfa
, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA
},
6311 { 0, CODE_FOR_spe_evmhessfaaw
, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW
},
6312 { 0, CODE_FOR_spe_evmhessfanw
, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW
},
6313 { 0, CODE_FOR_spe_evmhessiaaw
, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW
},
6314 { 0, CODE_FOR_spe_evmhessianw
, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW
},
6315 { 0, CODE_FOR_spe_evmheumi
, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI
},
6316 { 0, CODE_FOR_spe_evmheumia
, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA
},
6317 { 0, CODE_FOR_spe_evmheumiaaw
, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW
},
6318 { 0, CODE_FOR_spe_evmheumianw
, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW
},
6319 { 0, CODE_FOR_spe_evmheusiaaw
, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW
},
6320 { 0, CODE_FOR_spe_evmheusianw
, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW
},
6321 { 0, CODE_FOR_spe_evmhogsmfaa
, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA
},
6322 { 0, CODE_FOR_spe_evmhogsmfan
, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN
},
6323 { 0, CODE_FOR_spe_evmhogsmiaa
, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA
},
6324 { 0, CODE_FOR_spe_evmhogsmian
, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN
},
6325 { 0, CODE_FOR_spe_evmhogumiaa
, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA
},
6326 { 0, CODE_FOR_spe_evmhogumian
, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN
},
6327 { 0, CODE_FOR_spe_evmhosmf
, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF
},
6328 { 0, CODE_FOR_spe_evmhosmfa
, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA
},
6329 { 0, CODE_FOR_spe_evmhosmfaaw
, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW
},
6330 { 0, CODE_FOR_spe_evmhosmfanw
, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW
},
6331 { 0, CODE_FOR_spe_evmhosmi
, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI
},
6332 { 0, CODE_FOR_spe_evmhosmia
, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA
},
6333 { 0, CODE_FOR_spe_evmhosmiaaw
, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW
},
6334 { 0, CODE_FOR_spe_evmhosmianw
, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW
},
6335 { 0, CODE_FOR_spe_evmhossf
, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF
},
6336 { 0, CODE_FOR_spe_evmhossfa
, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA
},
6337 { 0, CODE_FOR_spe_evmhossfaaw
, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW
},
6338 { 0, CODE_FOR_spe_evmhossfanw
, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW
},
6339 { 0, CODE_FOR_spe_evmhossiaaw
, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW
},
6340 { 0, CODE_FOR_spe_evmhossianw
, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW
},
6341 { 0, CODE_FOR_spe_evmhoumi
, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI
},
6342 { 0, CODE_FOR_spe_evmhoumia
, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA
},
6343 { 0, CODE_FOR_spe_evmhoumiaaw
, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW
},
6344 { 0, CODE_FOR_spe_evmhoumianw
, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW
},
6345 { 0, CODE_FOR_spe_evmhousiaaw
, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW
},
6346 { 0, CODE_FOR_spe_evmhousianw
, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW
},
6347 { 0, CODE_FOR_spe_evmwhsmf
, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF
},
6348 { 0, CODE_FOR_spe_evmwhsmfa
, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA
},
6349 { 0, CODE_FOR_spe_evmwhsmi
, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI
},
6350 { 0, CODE_FOR_spe_evmwhsmia
, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA
},
6351 { 0, CODE_FOR_spe_evmwhssf
, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF
},
6352 { 0, CODE_FOR_spe_evmwhssfa
, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA
},
6353 { 0, CODE_FOR_spe_evmwhumi
, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI
},
6354 { 0, CODE_FOR_spe_evmwhumia
, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA
},
6355 { 0, CODE_FOR_spe_evmwlsmiaaw
, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW
},
6356 { 0, CODE_FOR_spe_evmwlsmianw
, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW
},
6357 { 0, CODE_FOR_spe_evmwlssiaaw
, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW
},
6358 { 0, CODE_FOR_spe_evmwlssianw
, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW
},
6359 { 0, CODE_FOR_spe_evmwlumi
, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI
},
6360 { 0, CODE_FOR_spe_evmwlumia
, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA
},
6361 { 0, CODE_FOR_spe_evmwlumiaaw
, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW
},
6362 { 0, CODE_FOR_spe_evmwlumianw
, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW
},
6363 { 0, CODE_FOR_spe_evmwlusiaaw
, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW
},
6364 { 0, CODE_FOR_spe_evmwlusianw
, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW
},
6365 { 0, CODE_FOR_spe_evmwsmf
, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF
},
6366 { 0, CODE_FOR_spe_evmwsmfa
, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA
},
6367 { 0, CODE_FOR_spe_evmwsmfaa
, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA
},
6368 { 0, CODE_FOR_spe_evmwsmfan
, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN
},
6369 { 0, CODE_FOR_spe_evmwsmi
, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI
},
6370 { 0, CODE_FOR_spe_evmwsmia
, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA
},
6371 { 0, CODE_FOR_spe_evmwsmiaa
, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA
},
6372 { 0, CODE_FOR_spe_evmwsmian
, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN
},
6373 { 0, CODE_FOR_spe_evmwssf
, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF
},
6374 { 0, CODE_FOR_spe_evmwssfa
, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA
},
6375 { 0, CODE_FOR_spe_evmwssfaa
, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA
},
6376 { 0, CODE_FOR_spe_evmwssfan
, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN
},
6377 { 0, CODE_FOR_spe_evmwumi
, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI
},
6378 { 0, CODE_FOR_spe_evmwumia
, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA
},
6379 { 0, CODE_FOR_spe_evmwumiaa
, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA
},
6380 { 0, CODE_FOR_spe_evmwumian
, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN
},
6381 { 0, CODE_FOR_spe_evnand
, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND
},
6382 { 0, CODE_FOR_spe_evnor
, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR
},
6383 { 0, CODE_FOR_spe_evor
, "__builtin_spe_evor", SPE_BUILTIN_EVOR
},
6384 { 0, CODE_FOR_spe_evorc
, "__builtin_spe_evorc", SPE_BUILTIN_EVORC
},
6385 { 0, CODE_FOR_spe_evrlw
, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW
},
6386 { 0, CODE_FOR_spe_evslw
, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW
},
6387 { 0, CODE_FOR_spe_evsrws
, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS
},
6388 { 0, CODE_FOR_spe_evsrwu
, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU
},
6389 { 0, CODE_FOR_spe_evsubfw
, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW
},
6391 /* SPE binary operations expecting a 5-bit unsigned literal. */
6392 { 0, CODE_FOR_spe_evaddiw
, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW
},
6394 { 0, CODE_FOR_spe_evrlwi
, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI
},
6395 { 0, CODE_FOR_spe_evslwi
, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI
},
6396 { 0, CODE_FOR_spe_evsrwis
, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS
},
6397 { 0, CODE_FOR_spe_evsrwiu
, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU
},
6398 { 0, CODE_FOR_spe_evsubifw
, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW
},
6399 { 0, CODE_FOR_spe_evmwhssfaa
, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA
},
6400 { 0, CODE_FOR_spe_evmwhssmaa
, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA
},
6401 { 0, CODE_FOR_spe_evmwhsmfaa
, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA
},
6402 { 0, CODE_FOR_spe_evmwhsmiaa
, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA
},
6403 { 0, CODE_FOR_spe_evmwhusiaa
, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA
},
6404 { 0, CODE_FOR_spe_evmwhumiaa
, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA
},
6405 { 0, CODE_FOR_spe_evmwhssfan
, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN
},
6406 { 0, CODE_FOR_spe_evmwhssian
, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN
},
6407 { 0, CODE_FOR_spe_evmwhsmfan
, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN
},
6408 { 0, CODE_FOR_spe_evmwhsmian
, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN
},
6409 { 0, CODE_FOR_spe_evmwhusian
, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN
},
6410 { 0, CODE_FOR_spe_evmwhumian
, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN
},
6411 { 0, CODE_FOR_spe_evmwhgssfaa
, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA
},
6412 { 0, CODE_FOR_spe_evmwhgsmfaa
, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA
},
6413 { 0, CODE_FOR_spe_evmwhgsmiaa
, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA
},
6414 { 0, CODE_FOR_spe_evmwhgumiaa
, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA
},
6415 { 0, CODE_FOR_spe_evmwhgssfan
, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN
},
6416 { 0, CODE_FOR_spe_evmwhgsmfan
, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN
},
6417 { 0, CODE_FOR_spe_evmwhgsmian
, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN
},
6418 { 0, CODE_FOR_spe_evmwhgumian
, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN
},
6419 { 0, CODE_FOR_spe_brinc
, "__builtin_spe_brinc", SPE_BUILTIN_BRINC
},
6421 /* Place-holder. Leave as last binary SPE builtin. */
6422 { 0, CODE_FOR_xorv2si3
, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR
}
6425 /* AltiVec predicates. */
6427 struct builtin_description_predicates
6429 const unsigned int mask
;
6430 const enum insn_code icode
;
6432 const char *const name
;
6433 const enum rs6000_builtins code
;
6436 static const struct builtin_description_predicates bdesc_altivec_preds
[] =
6438 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P
},
6439 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P
},
6440 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P
},
6441 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P
},
6442 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P
},
6443 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P
},
6444 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P
},
6445 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P
},
6446 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P
},
6447 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P
},
6448 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P
},
6449 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P
},
6450 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P
},
6452 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P
},
6453 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P
},
6454 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P
}
6457 /* SPE predicates. */
6458 static struct builtin_description bdesc_spe_predicates
[] =
6460 /* Place-holder. Leave as first. */
6461 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ
},
6462 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS
},
6463 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU
},
6464 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS
},
6465 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU
},
6466 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ
},
6467 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT
},
6468 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT
},
6469 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ
},
6470 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT
},
6471 /* Place-holder. Leave as last. */
6472 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT
},
6475 /* SPE evsel predicates. */
6476 static struct builtin_description bdesc_spe_evsel
[] =
6478 /* Place-holder. Leave as first. */
6479 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS
},
6480 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU
},
6481 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS
},
6482 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU
},
6483 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ
},
6484 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT
},
6485 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT
},
6486 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ
},
6487 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT
},
6488 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT
},
6489 /* Place-holder. Leave as last. */
6490 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ
},
6493 /* ABS* operations. */
6495 static const struct builtin_description bdesc_abs
[] =
6497 { MASK_ALTIVEC
, CODE_FOR_absv4si2
, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI
},
6498 { MASK_ALTIVEC
, CODE_FOR_absv8hi2
, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI
},
6499 { MASK_ALTIVEC
, CODE_FOR_absv4sf2
, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF
},
6500 { MASK_ALTIVEC
, CODE_FOR_absv16qi2
, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI
},
6501 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v4si
, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI
},
6502 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v8hi
, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI
},
6503 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v16qi
, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI
}
6506 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6509 static struct builtin_description bdesc_1arg
[] =
6511 { MASK_ALTIVEC
, CODE_FOR_altivec_vexptefp
, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP
},
6512 { MASK_ALTIVEC
, CODE_FOR_altivec_vlogefp
, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP
},
6513 { MASK_ALTIVEC
, CODE_FOR_altivec_vrefp
, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP
},
6514 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfim
, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM
},
6515 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfin
, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN
},
6516 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfip
, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP
},
6517 { MASK_ALTIVEC
, CODE_FOR_ftruncv4sf2
, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ
},
6518 { MASK_ALTIVEC
, CODE_FOR_altivec_vrsqrtefp
, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP
},
6519 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisb
, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB
},
6520 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltish
, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH
},
6521 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisw
, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW
},
6522 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsb
, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB
},
6523 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhpx
, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX
},
6524 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsh
, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH
},
6525 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsb
, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB
},
6526 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklpx
, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX
},
6527 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsh
, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH
},
6529 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS
},
6530 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS
},
6531 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL
},
6532 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE
},
6533 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR
},
6534 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE
},
6535 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR
},
6536 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE
},
6537 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND
},
6538 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE
},
6539 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC
},
6540 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH
},
6541 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH
},
6542 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX
},
6543 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB
},
6544 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL
},
6545 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX
},
6546 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH
},
6547 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB
},
6549 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6550 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6551 { 0, CODE_FOR_spe_evabs
, "__builtin_spe_evabs", SPE_BUILTIN_EVABS
},
6552 { 0, CODE_FOR_spe_evaddsmiaaw
, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW
},
6553 { 0, CODE_FOR_spe_evaddssiaaw
, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW
},
6554 { 0, CODE_FOR_spe_evaddumiaaw
, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW
},
6555 { 0, CODE_FOR_spe_evaddusiaaw
, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW
},
6556 { 0, CODE_FOR_spe_evcntlsw
, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW
},
6557 { 0, CODE_FOR_spe_evcntlzw
, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW
},
6558 { 0, CODE_FOR_spe_evextsb
, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB
},
6559 { 0, CODE_FOR_spe_evextsh
, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH
},
6560 { 0, CODE_FOR_spe_evfsabs
, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS
},
6561 { 0, CODE_FOR_spe_evfscfsf
, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF
},
6562 { 0, CODE_FOR_spe_evfscfsi
, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI
},
6563 { 0, CODE_FOR_spe_evfscfuf
, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF
},
6564 { 0, CODE_FOR_spe_evfscfui
, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI
},
6565 { 0, CODE_FOR_spe_evfsctsf
, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF
},
6566 { 0, CODE_FOR_spe_evfsctsi
, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI
},
6567 { 0, CODE_FOR_spe_evfsctsiz
, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ
},
6568 { 0, CODE_FOR_spe_evfsctuf
, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF
},
6569 { 0, CODE_FOR_spe_evfsctui
, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI
},
6570 { 0, CODE_FOR_spe_evfsctuiz
, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ
},
6571 { 0, CODE_FOR_spe_evfsnabs
, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS
},
6572 { 0, CODE_FOR_spe_evfsneg
, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG
},
6573 { 0, CODE_FOR_spe_evmra
, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA
},
6574 { 0, CODE_FOR_negv2si2
, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG
},
6575 { 0, CODE_FOR_spe_evrndw
, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW
},
6576 { 0, CODE_FOR_spe_evsubfsmiaaw
, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW
},
6577 { 0, CODE_FOR_spe_evsubfssiaaw
, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW
},
6578 { 0, CODE_FOR_spe_evsubfumiaaw
, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW
},
6580 /* Place-holder. Leave as last unary SPE builtin. */
6581 { 0, CODE_FOR_spe_evsubfusiaaw
, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW
}
6585 rs6000_expand_unop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6588 tree arg0
= TREE_VALUE (arglist
);
6589 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6590 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6591 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6593 if (icode
== CODE_FOR_nothing
)
6594 /* Builtin not supported on this processor. */
6597 /* If we got invalid arguments bail out before generating bad rtl. */
6598 if (arg0
== error_mark_node
)
6601 if (icode
== CODE_FOR_altivec_vspltisb
6602 || icode
== CODE_FOR_altivec_vspltish
6603 || icode
== CODE_FOR_altivec_vspltisw
6604 || icode
== CODE_FOR_spe_evsplatfi
6605 || icode
== CODE_FOR_spe_evsplati
)
6607 /* Only allow 5-bit *signed* literals. */
6608 if (GET_CODE (op0
) != CONST_INT
6609 || INTVAL (op0
) > 15
6610 || INTVAL (op0
) < -16)
6612 error ("argument 1 must be a 5-bit signed literal");
6618 || GET_MODE (target
) != tmode
6619 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6620 target
= gen_reg_rtx (tmode
);
6622 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6623 op0
= copy_to_mode_reg (mode0
, op0
);
6625 pat
= GEN_FCN (icode
) (target
, op0
);
6634 altivec_expand_abs_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6636 rtx pat
, scratch1
, scratch2
;
6637 tree arg0
= TREE_VALUE (arglist
);
6638 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6639 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6640 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6642 /* If we have invalid arguments, bail out before generating bad rtl. */
6643 if (arg0
== error_mark_node
)
6647 || GET_MODE (target
) != tmode
6648 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6649 target
= gen_reg_rtx (tmode
);
6651 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6652 op0
= copy_to_mode_reg (mode0
, op0
);
6654 scratch1
= gen_reg_rtx (mode0
);
6655 scratch2
= gen_reg_rtx (mode0
);
6657 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
6666 rs6000_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6669 tree arg0
= TREE_VALUE (arglist
);
6670 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6671 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6672 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6673 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6674 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6675 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6677 if (icode
== CODE_FOR_nothing
)
6678 /* Builtin not supported on this processor. */
6681 /* If we got invalid arguments bail out before generating bad rtl. */
6682 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6685 if (icode
== CODE_FOR_altivec_vcfux
6686 || icode
== CODE_FOR_altivec_vcfsx
6687 || icode
== CODE_FOR_altivec_vctsxs
6688 || icode
== CODE_FOR_altivec_vctuxs
6689 || icode
== CODE_FOR_altivec_vspltb
6690 || icode
== CODE_FOR_altivec_vsplth
6691 || icode
== CODE_FOR_altivec_vspltw
6692 || icode
== CODE_FOR_spe_evaddiw
6693 || icode
== CODE_FOR_spe_evldd
6694 || icode
== CODE_FOR_spe_evldh
6695 || icode
== CODE_FOR_spe_evldw
6696 || icode
== CODE_FOR_spe_evlhhesplat
6697 || icode
== CODE_FOR_spe_evlhhossplat
6698 || icode
== CODE_FOR_spe_evlhhousplat
6699 || icode
== CODE_FOR_spe_evlwhe
6700 || icode
== CODE_FOR_spe_evlwhos
6701 || icode
== CODE_FOR_spe_evlwhou
6702 || icode
== CODE_FOR_spe_evlwhsplat
6703 || icode
== CODE_FOR_spe_evlwwsplat
6704 || icode
== CODE_FOR_spe_evrlwi
6705 || icode
== CODE_FOR_spe_evslwi
6706 || icode
== CODE_FOR_spe_evsrwis
6707 || icode
== CODE_FOR_spe_evsubifw
6708 || icode
== CODE_FOR_spe_evsrwiu
)
6710 /* Only allow 5-bit unsigned literals. */
6712 if (TREE_CODE (arg1
) != INTEGER_CST
6713 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
6715 error ("argument 2 must be a 5-bit unsigned literal");
6721 || GET_MODE (target
) != tmode
6722 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6723 target
= gen_reg_rtx (tmode
);
6725 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6726 op0
= copy_to_mode_reg (mode0
, op0
);
6727 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6728 op1
= copy_to_mode_reg (mode1
, op1
);
6730 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
6739 altivec_expand_predicate_builtin (enum insn_code icode
, const char *opcode
,
6740 tree arglist
, rtx target
)
6743 tree cr6_form
= TREE_VALUE (arglist
);
6744 tree arg0
= TREE_VALUE (TREE_CHAIN (arglist
));
6745 tree arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6746 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6747 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6748 enum machine_mode tmode
= SImode
;
6749 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6750 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6753 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
6755 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6759 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
6761 gcc_assert (mode0
== mode1
);
6763 /* If we have invalid arguments, bail out before generating bad rtl. */
6764 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6768 || GET_MODE (target
) != tmode
6769 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6770 target
= gen_reg_rtx (tmode
);
6772 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6773 op0
= copy_to_mode_reg (mode0
, op0
);
6774 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6775 op1
= copy_to_mode_reg (mode1
, op1
);
6777 scratch
= gen_reg_rtx (mode0
);
6779 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
,
6780 gen_rtx_SYMBOL_REF (Pmode
, opcode
));
6785 /* The vec_any* and vec_all* predicates use the same opcodes for two
6786 different operations, but the bits in CR6 will be different
6787 depending on what information we want. So we have to play tricks
6788 with CR6 to get the right bits out.
6790 If you think this is disgusting, look at the specs for the
6791 AltiVec predicates. */
6793 switch (cr6_form_int
)
6796 emit_insn (gen_cr6_test_for_zero (target
));
6799 emit_insn (gen_cr6_test_for_zero_reverse (target
));
6802 emit_insn (gen_cr6_test_for_lt (target
));
6805 emit_insn (gen_cr6_test_for_lt_reverse (target
));
6808 error ("argument 1 of __builtin_altivec_predicate is out of range");
6816 altivec_expand_lv_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6819 tree arg0
= TREE_VALUE (arglist
);
6820 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6821 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6822 enum machine_mode mode0
= Pmode
;
6823 enum machine_mode mode1
= Pmode
;
6824 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6825 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6827 if (icode
== CODE_FOR_nothing
)
6828 /* Builtin not supported on this processor. */
6831 /* If we got invalid arguments bail out before generating bad rtl. */
6832 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6836 || GET_MODE (target
) != tmode
6837 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6838 target
= gen_reg_rtx (tmode
);
6840 op1
= copy_to_mode_reg (mode1
, op1
);
6842 if (op0
== const0_rtx
)
6844 addr
= gen_rtx_MEM (tmode
, op1
);
6848 op0
= copy_to_mode_reg (mode0
, op0
);
6849 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
6852 pat
= GEN_FCN (icode
) (target
, addr
);
6862 spe_expand_stv_builtin (enum insn_code icode
, tree arglist
)
6864 tree arg0
= TREE_VALUE (arglist
);
6865 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6866 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6867 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6868 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6869 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6871 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
6872 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
6873 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
6875 /* Invalid arguments. Bail before doing anything stoopid! */
6876 if (arg0
== error_mark_node
6877 || arg1
== error_mark_node
6878 || arg2
== error_mark_node
)
6881 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
6882 op0
= copy_to_mode_reg (mode2
, op0
);
6883 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
6884 op1
= copy_to_mode_reg (mode0
, op1
);
6885 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
6886 op2
= copy_to_mode_reg (mode1
, op2
);
6888 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
6895 altivec_expand_stv_builtin (enum insn_code icode
, tree arglist
)
6897 tree arg0
= TREE_VALUE (arglist
);
6898 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6899 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6900 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6901 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6902 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6904 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6905 enum machine_mode mode1
= Pmode
;
6906 enum machine_mode mode2
= Pmode
;
6908 /* Invalid arguments. Bail before doing anything stoopid! */
6909 if (arg0
== error_mark_node
6910 || arg1
== error_mark_node
6911 || arg2
== error_mark_node
)
6914 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
6915 op0
= copy_to_mode_reg (tmode
, op0
);
6917 op2
= copy_to_mode_reg (mode2
, op2
);
6919 if (op1
== const0_rtx
)
6921 addr
= gen_rtx_MEM (tmode
, op2
);
6925 op1
= copy_to_mode_reg (mode1
, op1
);
6926 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
6929 pat
= GEN_FCN (icode
) (addr
, op0
);
6936 rs6000_expand_ternop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6939 tree arg0
= TREE_VALUE (arglist
);
6940 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6941 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6942 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6943 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6944 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6945 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6946 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6947 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6948 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
6950 if (icode
== CODE_FOR_nothing
)
6951 /* Builtin not supported on this processor. */
6954 /* If we got invalid arguments bail out before generating bad rtl. */
6955 if (arg0
== error_mark_node
6956 || arg1
== error_mark_node
6957 || arg2
== error_mark_node
)
6960 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
6961 || icode
== CODE_FOR_altivec_vsldoi_v4si
6962 || icode
== CODE_FOR_altivec_vsldoi_v8hi
6963 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
6965 /* Only allow 4-bit unsigned literals. */
6967 if (TREE_CODE (arg2
) != INTEGER_CST
6968 || TREE_INT_CST_LOW (arg2
) & ~0xf)
6970 error ("argument 3 must be a 4-bit unsigned literal");
6976 || GET_MODE (target
) != tmode
6977 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6978 target
= gen_reg_rtx (tmode
);
6980 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6981 op0
= copy_to_mode_reg (mode0
, op0
);
6982 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6983 op1
= copy_to_mode_reg (mode1
, op1
);
6984 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
6985 op2
= copy_to_mode_reg (mode2
, op2
);
6987 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
6995 /* Expand the lvx builtins. */
6997 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
6999 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7000 tree arglist
= TREE_OPERAND (exp
, 1);
7001 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7003 enum machine_mode tmode
, mode0
;
7005 enum insn_code icode
;
7009 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
7010 icode
= CODE_FOR_altivec_lvx_v16qi
;
7012 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
7013 icode
= CODE_FOR_altivec_lvx_v8hi
;
7015 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
7016 icode
= CODE_FOR_altivec_lvx_v4si
;
7018 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
7019 icode
= CODE_FOR_altivec_lvx_v4sf
;
7028 arg0
= TREE_VALUE (arglist
);
7029 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7030 tmode
= insn_data
[icode
].operand
[0].mode
;
7031 mode0
= insn_data
[icode
].operand
[1].mode
;
7034 || GET_MODE (target
) != tmode
7035 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7036 target
= gen_reg_rtx (tmode
);
7038 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7039 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
7041 pat
= GEN_FCN (icode
) (target
, op0
);
7048 /* Expand the stvx builtins. */
7050 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
7053 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7054 tree arglist
= TREE_OPERAND (exp
, 1);
7055 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7057 enum machine_mode mode0
, mode1
;
7059 enum insn_code icode
;
7063 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
7064 icode
= CODE_FOR_altivec_stvx_v16qi
;
7066 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
7067 icode
= CODE_FOR_altivec_stvx_v8hi
;
7069 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
7070 icode
= CODE_FOR_altivec_stvx_v4si
;
7072 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
7073 icode
= CODE_FOR_altivec_stvx_v4sf
;
7080 arg0
= TREE_VALUE (arglist
);
7081 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7082 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7083 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7084 mode0
= insn_data
[icode
].operand
[0].mode
;
7085 mode1
= insn_data
[icode
].operand
[1].mode
;
7087 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7088 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
7089 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
7090 op1
= copy_to_mode_reg (mode1
, op1
);
7092 pat
= GEN_FCN (icode
) (op0
, op1
);
7100 /* Expand the dst builtins. */
7102 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
7105 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7106 tree arglist
= TREE_OPERAND (exp
, 1);
7107 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7108 tree arg0
, arg1
, arg2
;
7109 enum machine_mode mode0
, mode1
, mode2
;
7110 rtx pat
, op0
, op1
, op2
;
7111 struct builtin_description
*d
;
7116 /* Handle DST variants. */
7117 d
= (struct builtin_description
*) bdesc_dst
;
7118 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
7119 if (d
->code
== fcode
)
7121 arg0
= TREE_VALUE (arglist
);
7122 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7123 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7124 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7125 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7126 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
7127 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
7128 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
7129 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
7131 /* Invalid arguments, bail out before generating bad rtl. */
7132 if (arg0
== error_mark_node
7133 || arg1
== error_mark_node
7134 || arg2
== error_mark_node
)
7139 if (TREE_CODE (arg2
) != INTEGER_CST
7140 || TREE_INT_CST_LOW (arg2
) & ~0x3)
7142 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
7146 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
7147 op0
= copy_to_mode_reg (Pmode
, op0
);
7148 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
7149 op1
= copy_to_mode_reg (mode1
, op1
);
7151 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
7161 /* Expand vec_init builtin. */
7163 altivec_expand_vec_init_builtin (tree type
, tree arglist
, rtx target
)
7165 enum machine_mode tmode
= TYPE_MODE (type
);
7166 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
7167 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
7168 rtvec v
= rtvec_alloc (n_elt
);
7170 gcc_assert (VECTOR_MODE_P (tmode
));
7172 for (i
= 0; i
< n_elt
; ++i
, arglist
= TREE_CHAIN (arglist
))
7174 rtx x
= expand_expr (TREE_VALUE (arglist
), NULL_RTX
, VOIDmode
, 0);
7175 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
7178 gcc_assert (arglist
== NULL
);
7180 if (!target
|| !register_operand (target
, tmode
))
7181 target
= gen_reg_rtx (tmode
);
7183 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
7187 /* Return the integer constant in ARG. Constrain it to be in the range
7188 of the subparts of VEC_TYPE; issue an error if not. */
7191 get_element_number (tree vec_type
, tree arg
)
7193 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
7195 if (!host_integerp (arg
, 1)
7196 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
7198 error ("selector must be an integer constant in the range 0..%wi", max
);
7205 /* Expand vec_set builtin. */
7207 altivec_expand_vec_set_builtin (tree arglist
)
7209 enum machine_mode tmode
, mode1
;
7210 tree arg0
, arg1
, arg2
;
7214 arg0
= TREE_VALUE (arglist
);
7215 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7216 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7218 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
7219 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
7220 gcc_assert (VECTOR_MODE_P (tmode
));
7222 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, 0);
7223 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, 0);
7224 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
7226 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
7227 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
7229 op0
= force_reg (tmode
, op0
);
7230 op1
= force_reg (mode1
, op1
);
7232 rs6000_expand_vector_set (op0
, op1
, elt
);
7237 /* Expand vec_ext builtin. */
7239 altivec_expand_vec_ext_builtin (tree arglist
, rtx target
)
7241 enum machine_mode tmode
, mode0
;
7246 arg0
= TREE_VALUE (arglist
);
7247 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7249 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7250 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
7252 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
7253 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
7254 gcc_assert (VECTOR_MODE_P (mode0
));
7256 op0
= force_reg (mode0
, op0
);
7258 if (optimize
|| !target
|| !register_operand (target
, tmode
))
7259 target
= gen_reg_rtx (tmode
);
7261 rs6000_expand_vector_extract (target
, op0
, elt
);
7266 /* Expand the builtin in EXP and store the result in TARGET. Store
7267 true in *EXPANDEDP if we found a builtin to expand. */
7269 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
7271 struct builtin_description
*d
;
7272 struct builtin_description_predicates
*dp
;
7274 enum insn_code icode
;
7275 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7276 tree arglist
= TREE_OPERAND (exp
, 1);
7279 enum machine_mode tmode
, mode0
;
7280 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7282 if (fcode
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7283 && fcode
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
)
7286 error ("unresolved overload for Altivec builtin %qF", fndecl
);
7290 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
7294 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
7298 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
7306 case ALTIVEC_BUILTIN_STVX
:
7307 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx
, arglist
);
7308 case ALTIVEC_BUILTIN_STVEBX
:
7309 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, arglist
);
7310 case ALTIVEC_BUILTIN_STVEHX
:
7311 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, arglist
);
7312 case ALTIVEC_BUILTIN_STVEWX
:
7313 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, arglist
);
7314 case ALTIVEC_BUILTIN_STVXL
:
7315 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, arglist
);
7317 case ALTIVEC_BUILTIN_MFVSCR
:
7318 icode
= CODE_FOR_altivec_mfvscr
;
7319 tmode
= insn_data
[icode
].operand
[0].mode
;
7322 || GET_MODE (target
) != tmode
7323 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7324 target
= gen_reg_rtx (tmode
);
7326 pat
= GEN_FCN (icode
) (target
);
7332 case ALTIVEC_BUILTIN_MTVSCR
:
7333 icode
= CODE_FOR_altivec_mtvscr
;
7334 arg0
= TREE_VALUE (arglist
);
7335 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7336 mode0
= insn_data
[icode
].operand
[0].mode
;
7338 /* If we got invalid arguments bail out before generating bad rtl. */
7339 if (arg0
== error_mark_node
)
7342 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7343 op0
= copy_to_mode_reg (mode0
, op0
);
7345 pat
= GEN_FCN (icode
) (op0
);
7350 case ALTIVEC_BUILTIN_DSSALL
:
7351 emit_insn (gen_altivec_dssall ());
7354 case ALTIVEC_BUILTIN_DSS
:
7355 icode
= CODE_FOR_altivec_dss
;
7356 arg0
= TREE_VALUE (arglist
);
7358 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7359 mode0
= insn_data
[icode
].operand
[0].mode
;
7361 /* If we got invalid arguments bail out before generating bad rtl. */
7362 if (arg0
== error_mark_node
)
7365 if (TREE_CODE (arg0
) != INTEGER_CST
7366 || TREE_INT_CST_LOW (arg0
) & ~0x3)
7368 error ("argument to dss must be a 2-bit unsigned literal");
7372 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7373 op0
= copy_to_mode_reg (mode0
, op0
);
7375 emit_insn (gen_altivec_dss (op0
));
7378 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
7379 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
7380 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
7381 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
7382 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), arglist
, target
);
7384 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
7385 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
7386 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
7387 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
7388 return altivec_expand_vec_set_builtin (arglist
);
7390 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
7391 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
7392 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
7393 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
7394 return altivec_expand_vec_ext_builtin (arglist
, target
);
7401 /* Expand abs* operations. */
7402 d
= (struct builtin_description
*) bdesc_abs
;
7403 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
7404 if (d
->code
== fcode
)
7405 return altivec_expand_abs_builtin (d
->icode
, arglist
, target
);
7407 /* Expand the AltiVec predicates. */
7408 dp
= (struct builtin_description_predicates
*) bdesc_altivec_preds
;
7409 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
7410 if (dp
->code
== fcode
)
7411 return altivec_expand_predicate_builtin (dp
->icode
, dp
->opcode
,
7414 /* LV* are funky. We initialized them differently. */
7417 case ALTIVEC_BUILTIN_LVSL
:
7418 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
7420 case ALTIVEC_BUILTIN_LVSR
:
7421 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
7423 case ALTIVEC_BUILTIN_LVEBX
:
7424 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
7426 case ALTIVEC_BUILTIN_LVEHX
:
7427 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
7429 case ALTIVEC_BUILTIN_LVEWX
:
7430 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
7432 case ALTIVEC_BUILTIN_LVXL
:
7433 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
7435 case ALTIVEC_BUILTIN_LVX
:
7436 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx
,
7447 /* Binops that need to be initialized manually, but can be expanded
7448 automagically by rs6000_expand_binop_builtin. */
7449 static struct builtin_description bdesc_2arg_spe
[] =
7451 { 0, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
7452 { 0, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
7453 { 0, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
7454 { 0, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
7455 { 0, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
7456 { 0, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
7457 { 0, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
7458 { 0, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
7459 { 0, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
7460 { 0, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
7461 { 0, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
7462 { 0, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
7463 { 0, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
7464 { 0, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
7465 { 0, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
7466 { 0, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
7467 { 0, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
7468 { 0, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
7469 { 0, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
7470 { 0, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
7471 { 0, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
7472 { 0, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
7475 /* Expand the builtin in EXP and store the result in TARGET. Store
7476 true in *EXPANDEDP if we found a builtin to expand.
7478 This expands the SPE builtins that are not simple unary and binary
7481 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
7483 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7484 tree arglist
= TREE_OPERAND (exp
, 1);
7486 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7487 enum insn_code icode
;
7488 enum machine_mode tmode
, mode0
;
7490 struct builtin_description
*d
;
7495 /* Syntax check for a 5-bit unsigned immediate. */
7498 case SPE_BUILTIN_EVSTDD
:
7499 case SPE_BUILTIN_EVSTDH
:
7500 case SPE_BUILTIN_EVSTDW
:
7501 case SPE_BUILTIN_EVSTWHE
:
7502 case SPE_BUILTIN_EVSTWHO
:
7503 case SPE_BUILTIN_EVSTWWE
:
7504 case SPE_BUILTIN_EVSTWWO
:
7505 arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7506 if (TREE_CODE (arg1
) != INTEGER_CST
7507 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
7509 error ("argument 2 must be a 5-bit unsigned literal");
7517 /* The evsplat*i instructions are not quite generic. */
7520 case SPE_BUILTIN_EVSPLATFI
:
7521 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
7523 case SPE_BUILTIN_EVSPLATI
:
7524 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
7530 d
= (struct builtin_description
*) bdesc_2arg_spe
;
7531 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
7532 if (d
->code
== fcode
)
7533 return rs6000_expand_binop_builtin (d
->icode
, arglist
, target
);
7535 d
= (struct builtin_description
*) bdesc_spe_predicates
;
7536 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
7537 if (d
->code
== fcode
)
7538 return spe_expand_predicate_builtin (d
->icode
, arglist
, target
);
7540 d
= (struct builtin_description
*) bdesc_spe_evsel
;
7541 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
7542 if (d
->code
== fcode
)
7543 return spe_expand_evsel_builtin (d
->icode
, arglist
, target
);
7547 case SPE_BUILTIN_EVSTDDX
:
7548 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, arglist
);
7549 case SPE_BUILTIN_EVSTDHX
:
7550 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, arglist
);
7551 case SPE_BUILTIN_EVSTDWX
:
7552 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, arglist
);
7553 case SPE_BUILTIN_EVSTWHEX
:
7554 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, arglist
);
7555 case SPE_BUILTIN_EVSTWHOX
:
7556 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, arglist
);
7557 case SPE_BUILTIN_EVSTWWEX
:
7558 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, arglist
);
7559 case SPE_BUILTIN_EVSTWWOX
:
7560 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, arglist
);
7561 case SPE_BUILTIN_EVSTDD
:
7562 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, arglist
);
7563 case SPE_BUILTIN_EVSTDH
:
7564 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, arglist
);
7565 case SPE_BUILTIN_EVSTDW
:
7566 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, arglist
);
7567 case SPE_BUILTIN_EVSTWHE
:
7568 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, arglist
);
7569 case SPE_BUILTIN_EVSTWHO
:
7570 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, arglist
);
7571 case SPE_BUILTIN_EVSTWWE
:
7572 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, arglist
);
7573 case SPE_BUILTIN_EVSTWWO
:
7574 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, arglist
);
7575 case SPE_BUILTIN_MFSPEFSCR
:
7576 icode
= CODE_FOR_spe_mfspefscr
;
7577 tmode
= insn_data
[icode
].operand
[0].mode
;
7580 || GET_MODE (target
) != tmode
7581 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7582 target
= gen_reg_rtx (tmode
);
7584 pat
= GEN_FCN (icode
) (target
);
7589 case SPE_BUILTIN_MTSPEFSCR
:
7590 icode
= CODE_FOR_spe_mtspefscr
;
7591 arg0
= TREE_VALUE (arglist
);
7592 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7593 mode0
= insn_data
[icode
].operand
[0].mode
;
7595 if (arg0
== error_mark_node
)
7598 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7599 op0
= copy_to_mode_reg (mode0
, op0
);
7601 pat
= GEN_FCN (icode
) (op0
);
7614 spe_expand_predicate_builtin (enum insn_code icode
, tree arglist
, rtx target
)
7616 rtx pat
, scratch
, tmp
;
7617 tree form
= TREE_VALUE (arglist
);
7618 tree arg0
= TREE_VALUE (TREE_CHAIN (arglist
));
7619 tree arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7620 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7621 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7622 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7623 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7627 if (TREE_CODE (form
) != INTEGER_CST
)
7629 error ("argument 1 of __builtin_spe_predicate must be a constant");
7633 form_int
= TREE_INT_CST_LOW (form
);
7635 gcc_assert (mode0
== mode1
);
7637 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7641 || GET_MODE (target
) != SImode
7642 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
7643 target
= gen_reg_rtx (SImode
);
7645 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7646 op0
= copy_to_mode_reg (mode0
, op0
);
7647 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7648 op1
= copy_to_mode_reg (mode1
, op1
);
7650 scratch
= gen_reg_rtx (CCmode
);
7652 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
7657 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7658 _lower_. We use one compare, but look in different bits of the
7659 CR for each variant.
7661 There are 2 elements in each SPE simd type (upper/lower). The CR
7662 bits are set as follows:
7664 BIT0 | BIT 1 | BIT 2 | BIT 3
7665 U | L | (U | L) | (U & L)
7667 So, for an "all" relationship, BIT 3 would be set.
7668 For an "any" relationship, BIT 2 would be set. Etc.
7670 Following traditional nomenclature, these bits map to:
7672 BIT0 | BIT 1 | BIT 2 | BIT 3
7675 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7680 /* All variant. OV bit. */
7682 /* We need to get to the OV bit, which is the ORDERED bit. We
7683 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7684 that's ugly and will make validate_condition_mode die.
7685 So let's just use another pattern. */
7686 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
7688 /* Any variant. EQ bit. */
7692 /* Upper variant. LT bit. */
7696 /* Lower variant. GT bit. */
7701 error ("argument 1 of __builtin_spe_predicate is out of range");
7705 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
7706 emit_move_insn (target
, tmp
);
7711 /* The evsel builtins look like this:
7713 e = __builtin_spe_evsel_OP (a, b, c, d);
7717 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7718 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7722 spe_expand_evsel_builtin (enum insn_code icode
, tree arglist
, rtx target
)
7725 tree arg0
= TREE_VALUE (arglist
);
7726 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7727 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7728 tree arg3
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist
))));
7729 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7730 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7731 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
7732 rtx op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, 0);
7733 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7734 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7736 gcc_assert (mode0
== mode1
);
7738 if (arg0
== error_mark_node
|| arg1
== error_mark_node
7739 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
7743 || GET_MODE (target
) != mode0
7744 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
7745 target
= gen_reg_rtx (mode0
);
7747 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7748 op0
= copy_to_mode_reg (mode0
, op0
);
7749 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
7750 op1
= copy_to_mode_reg (mode0
, op1
);
7751 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
7752 op2
= copy_to_mode_reg (mode0
, op2
);
7753 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
7754 op3
= copy_to_mode_reg (mode0
, op3
);
7756 /* Generate the compare. */
7757 scratch
= gen_reg_rtx (CCmode
);
7758 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
7763 if (mode0
== V2SImode
)
7764 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
7766 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
7771 /* Expand an expression EXP that calls a built-in function,
7772 with result going to TARGET if that's convenient
7773 (and in mode MODE if that's convenient).
7774 SUBTARGET may be used as the target for computing one of EXP's operands.
7775 IGNORE is nonzero if the value is to be ignored. */
7778 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
7779 enum machine_mode mode ATTRIBUTE_UNUSED
,
7780 int ignore ATTRIBUTE_UNUSED
)
7782 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7783 tree arglist
= TREE_OPERAND (exp
, 1);
7784 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7785 struct builtin_description
*d
;
7790 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_LOAD
7791 || fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
7793 int icode
= (int) CODE_FOR_altivec_lvsr
;
7794 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7795 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
7799 gcc_assert (TARGET_ALTIVEC
);
7801 arg
= TREE_VALUE (arglist
);
7802 gcc_assert (TREE_CODE (TREE_TYPE (arg
)) == POINTER_TYPE
);
7803 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
7804 addr
= memory_address (mode
, op
);
7805 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
7809 /* For the load case need to negate the address. */
7810 op
= gen_reg_rtx (GET_MODE (addr
));
7811 emit_insn (gen_rtx_SET (VOIDmode
, op
,
7812 gen_rtx_NEG (GET_MODE (addr
), addr
)));
7814 op
= gen_rtx_MEM (mode
, op
);
7817 || GET_MODE (target
) != tmode
7818 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7819 target
= gen_reg_rtx (tmode
);
7821 /*pat = gen_altivec_lvsr (target, op);*/
7822 pat
= GEN_FCN (icode
) (target
, op
);
7832 ret
= altivec_expand_builtin (exp
, target
, &success
);
7839 ret
= spe_expand_builtin (exp
, target
, &success
);
7845 gcc_assert (TARGET_ALTIVEC
|| TARGET_SPE
);
7847 /* Handle simple unary operations. */
7848 d
= (struct builtin_description
*) bdesc_1arg
;
7849 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
7850 if (d
->code
== fcode
)
7851 return rs6000_expand_unop_builtin (d
->icode
, arglist
, target
);
7853 /* Handle simple binary operations. */
7854 d
= (struct builtin_description
*) bdesc_2arg
;
7855 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
7856 if (d
->code
== fcode
)
7857 return rs6000_expand_binop_builtin (d
->icode
, arglist
, target
);
7859 /* Handle simple ternary operations. */
7860 d
= (struct builtin_description
*) bdesc_3arg
;
7861 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
7862 if (d
->code
== fcode
)
7863 return rs6000_expand_ternop_builtin (d
->icode
, arglist
, target
);
7869 build_opaque_vector_type (tree node
, int nunits
)
7871 node
= copy_node (node
);
7872 TYPE_MAIN_VARIANT (node
) = node
;
7873 return build_vector_type (node
, nunits
);
7877 rs6000_init_builtins (void)
7879 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
7880 V2SF_type_node
= build_vector_type (float_type_node
, 2);
7881 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
7882 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
7883 V4SF_type_node
= build_vector_type (float_type_node
, 4);
7884 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
7885 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
7887 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
7888 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
7889 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
7891 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
7892 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
7893 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
7894 opaque_V4SI_type_node
= copy_node (V4SI_type_node
);
7896 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7897 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7898 'vector unsigned short'. */
7900 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
7901 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
7902 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
7903 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
7905 long_integer_type_internal_node
= long_integer_type_node
;
7906 long_unsigned_type_internal_node
= long_unsigned_type_node
;
7907 intQI_type_internal_node
= intQI_type_node
;
7908 uintQI_type_internal_node
= unsigned_intQI_type_node
;
7909 intHI_type_internal_node
= intHI_type_node
;
7910 uintHI_type_internal_node
= unsigned_intHI_type_node
;
7911 intSI_type_internal_node
= intSI_type_node
;
7912 uintSI_type_internal_node
= unsigned_intSI_type_node
;
7913 float_type_internal_node
= float_type_node
;
7914 void_type_internal_node
= void_type_node
;
7916 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7917 get_identifier ("__bool char"),
7918 bool_char_type_node
));
7919 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7920 get_identifier ("__bool short"),
7921 bool_short_type_node
));
7922 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7923 get_identifier ("__bool int"),
7924 bool_int_type_node
));
7925 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7926 get_identifier ("__pixel"),
7929 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
7930 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
7931 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
7932 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
7934 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7935 get_identifier ("__vector unsigned char"),
7936 unsigned_V16QI_type_node
));
7937 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7938 get_identifier ("__vector signed char"),
7940 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7941 get_identifier ("__vector __bool char"),
7942 bool_V16QI_type_node
));
7944 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7945 get_identifier ("__vector unsigned short"),
7946 unsigned_V8HI_type_node
));
7947 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7948 get_identifier ("__vector signed short"),
7950 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7951 get_identifier ("__vector __bool short"),
7952 bool_V8HI_type_node
));
7954 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7955 get_identifier ("__vector unsigned int"),
7956 unsigned_V4SI_type_node
));
7957 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7958 get_identifier ("__vector signed int"),
7960 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7961 get_identifier ("__vector __bool int"),
7962 bool_V4SI_type_node
));
7964 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7965 get_identifier ("__vector float"),
7967 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7968 get_identifier ("__vector __pixel"),
7969 pixel_V8HI_type_node
));
7972 spe_init_builtins ();
7974 altivec_init_builtins ();
7975 if (TARGET_ALTIVEC
|| TARGET_SPE
)
7976 rs6000_common_init_builtins ();
7979 /* Search through a set of builtins and enable the mask bits.
7980 DESC is an array of builtins.
7981 SIZE is the total number of builtins.
7982 START is the builtin enum at which to start.
7983 END is the builtin enum at which to end. */
7985 enable_mask_for_builtins (struct builtin_description
*desc
, int size
,
7986 enum rs6000_builtins start
,
7987 enum rs6000_builtins end
)
7991 for (i
= 0; i
< size
; ++i
)
7992 if (desc
[i
].code
== start
)
7998 for (; i
< size
; ++i
)
8000 /* Flip all the bits on. */
8001 desc
[i
].mask
= target_flags
;
8002 if (desc
[i
].code
== end
)
8008 spe_init_builtins (void)
8010 tree endlink
= void_list_node
;
8011 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
8012 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
8013 struct builtin_description
*d
;
8016 tree v2si_ftype_4_v2si
8017 = build_function_type
8018 (opaque_V2SI_type_node
,
8019 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8020 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8021 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8022 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8025 tree v2sf_ftype_4_v2sf
8026 = build_function_type
8027 (opaque_V2SF_type_node
,
8028 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8029 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8030 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8031 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8034 tree int_ftype_int_v2si_v2si
8035 = build_function_type
8037 tree_cons (NULL_TREE
, integer_type_node
,
8038 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8039 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8042 tree int_ftype_int_v2sf_v2sf
8043 = build_function_type
8045 tree_cons (NULL_TREE
, integer_type_node
,
8046 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8047 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8050 tree void_ftype_v2si_puint_int
8051 = build_function_type (void_type_node
,
8052 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8053 tree_cons (NULL_TREE
, puint_type_node
,
8054 tree_cons (NULL_TREE
,
8058 tree void_ftype_v2si_puint_char
8059 = build_function_type (void_type_node
,
8060 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8061 tree_cons (NULL_TREE
, puint_type_node
,
8062 tree_cons (NULL_TREE
,
8066 tree void_ftype_v2si_pv2si_int
8067 = build_function_type (void_type_node
,
8068 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8069 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
8070 tree_cons (NULL_TREE
,
8074 tree void_ftype_v2si_pv2si_char
8075 = build_function_type (void_type_node
,
8076 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8077 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
8078 tree_cons (NULL_TREE
,
8083 = build_function_type (void_type_node
,
8084 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
8087 = build_function_type (integer_type_node
, endlink
);
8089 tree v2si_ftype_pv2si_int
8090 = build_function_type (opaque_V2SI_type_node
,
8091 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
8092 tree_cons (NULL_TREE
, integer_type_node
,
8095 tree v2si_ftype_puint_int
8096 = build_function_type (opaque_V2SI_type_node
,
8097 tree_cons (NULL_TREE
, puint_type_node
,
8098 tree_cons (NULL_TREE
, integer_type_node
,
8101 tree v2si_ftype_pushort_int
8102 = build_function_type (opaque_V2SI_type_node
,
8103 tree_cons (NULL_TREE
, pushort_type_node
,
8104 tree_cons (NULL_TREE
, integer_type_node
,
8107 tree v2si_ftype_signed_char
8108 = build_function_type (opaque_V2SI_type_node
,
8109 tree_cons (NULL_TREE
, signed_char_type_node
,
8112 /* The initialization of the simple binary and unary builtins is
8113 done in rs6000_common_init_builtins, but we have to enable the
8114 mask bits here manually because we have run out of `target_flags'
8115 bits. We really need to redesign this mask business. */
8117 enable_mask_for_builtins ((struct builtin_description
*) bdesc_2arg
,
8118 ARRAY_SIZE (bdesc_2arg
),
8121 enable_mask_for_builtins ((struct builtin_description
*) bdesc_1arg
,
8122 ARRAY_SIZE (bdesc_1arg
),
8124 SPE_BUILTIN_EVSUBFUSIAAW
);
8125 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_predicates
,
8126 ARRAY_SIZE (bdesc_spe_predicates
),
8127 SPE_BUILTIN_EVCMPEQ
,
8128 SPE_BUILTIN_EVFSTSTLT
);
8129 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_evsel
,
8130 ARRAY_SIZE (bdesc_spe_evsel
),
8131 SPE_BUILTIN_EVSEL_CMPGTS
,
8132 SPE_BUILTIN_EVSEL_FSTSTEQ
);
8134 (*lang_hooks
.decls
.pushdecl
)
8135 (build_decl (TYPE_DECL
, get_identifier ("__ev64_opaque__"),
8136 opaque_V2SI_type_node
));
8138 /* Initialize irregular SPE builtins. */
8140 def_builtin (target_flags
, "__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
8141 def_builtin (target_flags
, "__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
8142 def_builtin (target_flags
, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
8143 def_builtin (target_flags
, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
8144 def_builtin (target_flags
, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
8145 def_builtin (target_flags
, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
8146 def_builtin (target_flags
, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
8147 def_builtin (target_flags
, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
8148 def_builtin (target_flags
, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
8149 def_builtin (target_flags
, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
8150 def_builtin (target_flags
, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
8151 def_builtin (target_flags
, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
8152 def_builtin (target_flags
, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
8153 def_builtin (target_flags
, "__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
8154 def_builtin (target_flags
, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
8155 def_builtin (target_flags
, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
8156 def_builtin (target_flags
, "__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
8157 def_builtin (target_flags
, "__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
8160 def_builtin (target_flags
, "__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
8161 def_builtin (target_flags
, "__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
8162 def_builtin (target_flags
, "__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
8163 def_builtin (target_flags
, "__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
8164 def_builtin (target_flags
, "__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
8165 def_builtin (target_flags
, "__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
8166 def_builtin (target_flags
, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
8167 def_builtin (target_flags
, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
8168 def_builtin (target_flags
, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
8169 def_builtin (target_flags
, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
8170 def_builtin (target_flags
, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
8171 def_builtin (target_flags
, "__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
8172 def_builtin (target_flags
, "__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
8173 def_builtin (target_flags
, "__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
8174 def_builtin (target_flags
, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
8175 def_builtin (target_flags
, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
8176 def_builtin (target_flags
, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
8177 def_builtin (target_flags
, "__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
8178 def_builtin (target_flags
, "__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
8179 def_builtin (target_flags
, "__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
8180 def_builtin (target_flags
, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
8181 def_builtin (target_flags
, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
8184 d
= (struct builtin_description
*) bdesc_spe_predicates
;
8185 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
8189 switch (insn_data
[d
->icode
].operand
[1].mode
)
8192 type
= int_ftype_int_v2si_v2si
;
8195 type
= int_ftype_int_v2sf_v2sf
;
8201 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8204 /* Evsel predicates. */
8205 d
= (struct builtin_description
*) bdesc_spe_evsel
;
8206 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
8210 switch (insn_data
[d
->icode
].operand
[1].mode
)
8213 type
= v2si_ftype_4_v2si
;
8216 type
= v2sf_ftype_4_v2sf
;
8222 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8227 altivec_init_builtins (void)
8229 struct builtin_description
*d
;
8230 struct builtin_description_predicates
*dp
;
8234 tree pfloat_type_node
= build_pointer_type (float_type_node
);
8235 tree pint_type_node
= build_pointer_type (integer_type_node
);
8236 tree pshort_type_node
= build_pointer_type (short_integer_type_node
);
8237 tree pchar_type_node
= build_pointer_type (char_type_node
);
8239 tree pvoid_type_node
= build_pointer_type (void_type_node
);
8241 tree pcfloat_type_node
= build_pointer_type (build_qualified_type (float_type_node
, TYPE_QUAL_CONST
));
8242 tree pcint_type_node
= build_pointer_type (build_qualified_type (integer_type_node
, TYPE_QUAL_CONST
));
8243 tree pcshort_type_node
= build_pointer_type (build_qualified_type (short_integer_type_node
, TYPE_QUAL_CONST
));
8244 tree pcchar_type_node
= build_pointer_type (build_qualified_type (char_type_node
, TYPE_QUAL_CONST
));
8246 tree pcvoid_type_node
= build_pointer_type (build_qualified_type (void_type_node
, TYPE_QUAL_CONST
));
8248 tree int_ftype_opaque
8249 = build_function_type_list (integer_type_node
,
8250 opaque_V4SI_type_node
, NULL_TREE
);
8252 tree opaque_ftype_opaque_int
8253 = build_function_type_list (opaque_V4SI_type_node
,
8254 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
8255 tree opaque_ftype_opaque_opaque_int
8256 = build_function_type_list (opaque_V4SI_type_node
,
8257 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
8258 integer_type_node
, NULL_TREE
);
8259 tree int_ftype_int_opaque_opaque
8260 = build_function_type_list (integer_type_node
,
8261 integer_type_node
, opaque_V4SI_type_node
,
8262 opaque_V4SI_type_node
, NULL_TREE
);
8263 tree int_ftype_int_v4si_v4si
8264 = build_function_type_list (integer_type_node
,
8265 integer_type_node
, V4SI_type_node
,
8266 V4SI_type_node
, NULL_TREE
);
8267 tree v4sf_ftype_pcfloat
8268 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
8269 tree void_ftype_pfloat_v4sf
8270 = build_function_type_list (void_type_node
,
8271 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
8272 tree v4si_ftype_pcint
8273 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
8274 tree void_ftype_pint_v4si
8275 = build_function_type_list (void_type_node
,
8276 pint_type_node
, V4SI_type_node
, NULL_TREE
);
8277 tree v8hi_ftype_pcshort
8278 = build_function_type_list (V8HI_type_node
, pcshort_type_node
, NULL_TREE
);
8279 tree void_ftype_pshort_v8hi
8280 = build_function_type_list (void_type_node
,
8281 pshort_type_node
, V8HI_type_node
, NULL_TREE
);
8282 tree v16qi_ftype_pcchar
8283 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
8284 tree void_ftype_pchar_v16qi
8285 = build_function_type_list (void_type_node
,
8286 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
8287 tree void_ftype_v4si
8288 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
8289 tree v8hi_ftype_void
8290 = build_function_type (V8HI_type_node
, void_list_node
);
8291 tree void_ftype_void
8292 = build_function_type (void_type_node
, void_list_node
);
8294 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
8296 tree opaque_ftype_long_pcvoid
8297 = build_function_type_list (opaque_V4SI_type_node
,
8298 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
8299 tree v16qi_ftype_long_pcvoid
8300 = build_function_type_list (V16QI_type_node
,
8301 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
8302 tree v8hi_ftype_long_pcvoid
8303 = build_function_type_list (V8HI_type_node
,
8304 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
8305 tree v4si_ftype_long_pcvoid
8306 = build_function_type_list (V4SI_type_node
,
8307 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
8309 tree void_ftype_opaque_long_pvoid
8310 = build_function_type_list (void_type_node
,
8311 opaque_V4SI_type_node
, long_integer_type_node
,
8312 pvoid_type_node
, NULL_TREE
);
8313 tree void_ftype_v4si_long_pvoid
8314 = build_function_type_list (void_type_node
,
8315 V4SI_type_node
, long_integer_type_node
,
8316 pvoid_type_node
, NULL_TREE
);
8317 tree void_ftype_v16qi_long_pvoid
8318 = build_function_type_list (void_type_node
,
8319 V16QI_type_node
, long_integer_type_node
,
8320 pvoid_type_node
, NULL_TREE
);
8321 tree void_ftype_v8hi_long_pvoid
8322 = build_function_type_list (void_type_node
,
8323 V8HI_type_node
, long_integer_type_node
,
8324 pvoid_type_node
, NULL_TREE
);
8325 tree int_ftype_int_v8hi_v8hi
8326 = build_function_type_list (integer_type_node
,
8327 integer_type_node
, V8HI_type_node
,
8328 V8HI_type_node
, NULL_TREE
);
8329 tree int_ftype_int_v16qi_v16qi
8330 = build_function_type_list (integer_type_node
,
8331 integer_type_node
, V16QI_type_node
,
8332 V16QI_type_node
, NULL_TREE
);
8333 tree int_ftype_int_v4sf_v4sf
8334 = build_function_type_list (integer_type_node
,
8335 integer_type_node
, V4SF_type_node
,
8336 V4SF_type_node
, NULL_TREE
);
8337 tree v4si_ftype_v4si
8338 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8339 tree v8hi_ftype_v8hi
8340 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8341 tree v16qi_ftype_v16qi
8342 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8343 tree v4sf_ftype_v4sf
8344 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8345 tree void_ftype_pcvoid_int_int
8346 = build_function_type_list (void_type_node
,
8347 pcvoid_type_node
, integer_type_node
,
8348 integer_type_node
, NULL_TREE
);
8350 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat
,
8351 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
);
8352 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf
,
8353 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
);
8354 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint
,
8355 ALTIVEC_BUILTIN_LD_INTERNAL_4si
);
8356 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si
,
8357 ALTIVEC_BUILTIN_ST_INTERNAL_4si
);
8358 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort
,
8359 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
);
8360 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi
,
8361 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
);
8362 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar
,
8363 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
);
8364 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi
,
8365 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
);
8366 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
8367 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
8368 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
8369 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
8370 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
8371 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
8372 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
8373 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
8374 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
8375 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
8376 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
8377 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
8378 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
8379 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
8380 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
8381 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
8382 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
8383 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
8384 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
8385 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
8386 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
8387 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
8388 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
8389 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
8390 def_builtin (MASK_ALTIVEC
, "__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
8391 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
8392 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
8393 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
8394 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
8395 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
8397 def_builtin (MASK_ALTIVEC
, "__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
8399 def_builtin (MASK_ALTIVEC
, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
8400 def_builtin (MASK_ALTIVEC
, "__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
8401 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
8402 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
8403 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
8404 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
8405 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
8406 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
8407 def_builtin (MASK_ALTIVEC
, "__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
8408 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
8410 /* Add the DST variants. */
8411 d
= (struct builtin_description
*) bdesc_dst
;
8412 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
8413 def_builtin (d
->mask
, d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
8415 /* Initialize the predicates. */
8416 dp
= (struct builtin_description_predicates
*) bdesc_altivec_preds
;
8417 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
8419 enum machine_mode mode1
;
8421 bool is_overloaded
= dp
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8422 && dp
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
8427 mode1
= insn_data
[dp
->icode
].operand
[1].mode
;
8432 type
= int_ftype_int_opaque_opaque
;
8435 type
= int_ftype_int_v4si_v4si
;
8438 type
= int_ftype_int_v8hi_v8hi
;
8441 type
= int_ftype_int_v16qi_v16qi
;
8444 type
= int_ftype_int_v4sf_v4sf
;
8450 def_builtin (dp
->mask
, dp
->name
, type
, dp
->code
);
8453 /* Initialize the abs* operators. */
8454 d
= (struct builtin_description
*) bdesc_abs
;
8455 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
8457 enum machine_mode mode0
;
8460 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8465 type
= v4si_ftype_v4si
;
8468 type
= v8hi_ftype_v8hi
;
8471 type
= v16qi_ftype_v16qi
;
8474 type
= v4sf_ftype_v4sf
;
8480 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8483 /* Initialize target builtin that implements
8484 targetm.vectorize.builtin_mask_for_load. */
8486 altivec_builtin_mask_for_load
=
8487 lang_hooks
.builtin_function ("__builtin_altivec_mask_for_load",
8488 v16qi_ftype_long_pcvoid
,
8489 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
8491 tree_cons (get_identifier ("const"),
8492 NULL_TREE
, NULL_TREE
));
8494 /* Access to the vec_init patterns. */
8495 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
8496 integer_type_node
, integer_type_node
,
8497 integer_type_node
, NULL_TREE
);
8498 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4si", ftype
,
8499 ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
8501 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
8502 short_integer_type_node
,
8503 short_integer_type_node
,
8504 short_integer_type_node
,
8505 short_integer_type_node
,
8506 short_integer_type_node
,
8507 short_integer_type_node
,
8508 short_integer_type_node
, NULL_TREE
);
8509 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v8hi", ftype
,
8510 ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
8512 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
8513 char_type_node
, char_type_node
,
8514 char_type_node
, char_type_node
,
8515 char_type_node
, char_type_node
,
8516 char_type_node
, char_type_node
,
8517 char_type_node
, char_type_node
,
8518 char_type_node
, char_type_node
,
8519 char_type_node
, char_type_node
,
8520 char_type_node
, NULL_TREE
);
8521 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v16qi", ftype
,
8522 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
8524 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
8525 float_type_node
, float_type_node
,
8526 float_type_node
, NULL_TREE
);
8527 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4sf", ftype
,
8528 ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
8530 /* Access to the vec_set patterns. */
8531 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
8533 integer_type_node
, NULL_TREE
);
8534 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4si", ftype
,
8535 ALTIVEC_BUILTIN_VEC_SET_V4SI
);
8537 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
8539 integer_type_node
, NULL_TREE
);
8540 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v8hi", ftype
,
8541 ALTIVEC_BUILTIN_VEC_SET_V8HI
);
8543 ftype
= build_function_type_list (V8HI_type_node
, V16QI_type_node
,
8545 integer_type_node
, NULL_TREE
);
8546 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v16qi", ftype
,
8547 ALTIVEC_BUILTIN_VEC_SET_V16QI
);
8549 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
8551 integer_type_node
, NULL_TREE
);
8552 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4sf", ftype
,
8553 ALTIVEC_BUILTIN_VEC_SET_V4SF
);
8555 /* Access to the vec_extract patterns. */
8556 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
8557 integer_type_node
, NULL_TREE
);
8558 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4si", ftype
,
8559 ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
8561 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
8562 integer_type_node
, NULL_TREE
);
8563 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v8hi", ftype
,
8564 ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
8566 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
8567 integer_type_node
, NULL_TREE
);
8568 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v16qi", ftype
,
8569 ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
8571 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
8572 integer_type_node
, NULL_TREE
);
8573 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4sf", ftype
,
8574 ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
8578 rs6000_common_init_builtins (void)
8580 struct builtin_description
*d
;
8583 tree v4sf_ftype_v4sf_v4sf_v16qi
8584 = build_function_type_list (V4SF_type_node
,
8585 V4SF_type_node
, V4SF_type_node
,
8586 V16QI_type_node
, NULL_TREE
);
8587 tree v4si_ftype_v4si_v4si_v16qi
8588 = build_function_type_list (V4SI_type_node
,
8589 V4SI_type_node
, V4SI_type_node
,
8590 V16QI_type_node
, NULL_TREE
);
8591 tree v8hi_ftype_v8hi_v8hi_v16qi
8592 = build_function_type_list (V8HI_type_node
,
8593 V8HI_type_node
, V8HI_type_node
,
8594 V16QI_type_node
, NULL_TREE
);
8595 tree v16qi_ftype_v16qi_v16qi_v16qi
8596 = build_function_type_list (V16QI_type_node
,
8597 V16QI_type_node
, V16QI_type_node
,
8598 V16QI_type_node
, NULL_TREE
);
8600 = build_function_type_list (V4SI_type_node
, integer_type_node
, NULL_TREE
);
8602 = build_function_type_list (V8HI_type_node
, integer_type_node
, NULL_TREE
);
8603 tree v16qi_ftype_int
8604 = build_function_type_list (V16QI_type_node
, integer_type_node
, NULL_TREE
);
8605 tree v8hi_ftype_v16qi
8606 = build_function_type_list (V8HI_type_node
, V16QI_type_node
, NULL_TREE
);
8607 tree v4sf_ftype_v4sf
8608 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8610 tree v2si_ftype_v2si_v2si
8611 = build_function_type_list (opaque_V2SI_type_node
,
8612 opaque_V2SI_type_node
,
8613 opaque_V2SI_type_node
, NULL_TREE
);
8615 tree v2sf_ftype_v2sf_v2sf
8616 = build_function_type_list (opaque_V2SF_type_node
,
8617 opaque_V2SF_type_node
,
8618 opaque_V2SF_type_node
, NULL_TREE
);
8620 tree v2si_ftype_int_int
8621 = build_function_type_list (opaque_V2SI_type_node
,
8622 integer_type_node
, integer_type_node
,
8625 tree opaque_ftype_opaque
8626 = build_function_type_list (opaque_V4SI_type_node
,
8627 opaque_V4SI_type_node
, NULL_TREE
);
8629 tree v2si_ftype_v2si
8630 = build_function_type_list (opaque_V2SI_type_node
,
8631 opaque_V2SI_type_node
, NULL_TREE
);
8633 tree v2sf_ftype_v2sf
8634 = build_function_type_list (opaque_V2SF_type_node
,
8635 opaque_V2SF_type_node
, NULL_TREE
);
8637 tree v2sf_ftype_v2si
8638 = build_function_type_list (opaque_V2SF_type_node
,
8639 opaque_V2SI_type_node
, NULL_TREE
);
8641 tree v2si_ftype_v2sf
8642 = build_function_type_list (opaque_V2SI_type_node
,
8643 opaque_V2SF_type_node
, NULL_TREE
);
8645 tree v2si_ftype_v2si_char
8646 = build_function_type_list (opaque_V2SI_type_node
,
8647 opaque_V2SI_type_node
,
8648 char_type_node
, NULL_TREE
);
8650 tree v2si_ftype_int_char
8651 = build_function_type_list (opaque_V2SI_type_node
,
8652 integer_type_node
, char_type_node
, NULL_TREE
);
8654 tree v2si_ftype_char
8655 = build_function_type_list (opaque_V2SI_type_node
,
8656 char_type_node
, NULL_TREE
);
8658 tree int_ftype_int_int
8659 = build_function_type_list (integer_type_node
,
8660 integer_type_node
, integer_type_node
,
8663 tree opaque_ftype_opaque_opaque
8664 = build_function_type_list (opaque_V4SI_type_node
,
8665 opaque_V4SI_type_node
, opaque_V4SI_type_node
, NULL_TREE
);
8666 tree v4si_ftype_v4si_v4si
8667 = build_function_type_list (V4SI_type_node
,
8668 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8669 tree v4sf_ftype_v4si_int
8670 = build_function_type_list (V4SF_type_node
,
8671 V4SI_type_node
, integer_type_node
, NULL_TREE
);
8672 tree v4si_ftype_v4sf_int
8673 = build_function_type_list (V4SI_type_node
,
8674 V4SF_type_node
, integer_type_node
, NULL_TREE
);
8675 tree v4si_ftype_v4si_int
8676 = build_function_type_list (V4SI_type_node
,
8677 V4SI_type_node
, integer_type_node
, NULL_TREE
);
8678 tree v8hi_ftype_v8hi_int
8679 = build_function_type_list (V8HI_type_node
,
8680 V8HI_type_node
, integer_type_node
, NULL_TREE
);
8681 tree v16qi_ftype_v16qi_int
8682 = build_function_type_list (V16QI_type_node
,
8683 V16QI_type_node
, integer_type_node
, NULL_TREE
);
8684 tree v16qi_ftype_v16qi_v16qi_int
8685 = build_function_type_list (V16QI_type_node
,
8686 V16QI_type_node
, V16QI_type_node
,
8687 integer_type_node
, NULL_TREE
);
8688 tree v8hi_ftype_v8hi_v8hi_int
8689 = build_function_type_list (V8HI_type_node
,
8690 V8HI_type_node
, V8HI_type_node
,
8691 integer_type_node
, NULL_TREE
);
8692 tree v4si_ftype_v4si_v4si_int
8693 = build_function_type_list (V4SI_type_node
,
8694 V4SI_type_node
, V4SI_type_node
,
8695 integer_type_node
, NULL_TREE
);
8696 tree v4sf_ftype_v4sf_v4sf_int
8697 = build_function_type_list (V4SF_type_node
,
8698 V4SF_type_node
, V4SF_type_node
,
8699 integer_type_node
, NULL_TREE
);
8700 tree v4sf_ftype_v4sf_v4sf
8701 = build_function_type_list (V4SF_type_node
,
8702 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8703 tree opaque_ftype_opaque_opaque_opaque
8704 = build_function_type_list (opaque_V4SI_type_node
,
8705 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
8706 opaque_V4SI_type_node
, NULL_TREE
);
8707 tree v4sf_ftype_v4sf_v4sf_v4si
8708 = build_function_type_list (V4SF_type_node
,
8709 V4SF_type_node
, V4SF_type_node
,
8710 V4SI_type_node
, NULL_TREE
);
8711 tree v4sf_ftype_v4sf_v4sf_v4sf
8712 = build_function_type_list (V4SF_type_node
,
8713 V4SF_type_node
, V4SF_type_node
,
8714 V4SF_type_node
, NULL_TREE
);
8715 tree v4si_ftype_v4si_v4si_v4si
8716 = build_function_type_list (V4SI_type_node
,
8717 V4SI_type_node
, V4SI_type_node
,
8718 V4SI_type_node
, NULL_TREE
);
8719 tree v8hi_ftype_v8hi_v8hi
8720 = build_function_type_list (V8HI_type_node
,
8721 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8722 tree v8hi_ftype_v8hi_v8hi_v8hi
8723 = build_function_type_list (V8HI_type_node
,
8724 V8HI_type_node
, V8HI_type_node
,
8725 V8HI_type_node
, NULL_TREE
);
8726 tree v4si_ftype_v8hi_v8hi_v4si
8727 = build_function_type_list (V4SI_type_node
,
8728 V8HI_type_node
, V8HI_type_node
,
8729 V4SI_type_node
, NULL_TREE
);
8730 tree v4si_ftype_v16qi_v16qi_v4si
8731 = build_function_type_list (V4SI_type_node
,
8732 V16QI_type_node
, V16QI_type_node
,
8733 V4SI_type_node
, NULL_TREE
);
8734 tree v16qi_ftype_v16qi_v16qi
8735 = build_function_type_list (V16QI_type_node
,
8736 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8737 tree v4si_ftype_v4sf_v4sf
8738 = build_function_type_list (V4SI_type_node
,
8739 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8740 tree v8hi_ftype_v16qi_v16qi
8741 = build_function_type_list (V8HI_type_node
,
8742 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8743 tree v4si_ftype_v8hi_v8hi
8744 = build_function_type_list (V4SI_type_node
,
8745 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8746 tree v8hi_ftype_v4si_v4si
8747 = build_function_type_list (V8HI_type_node
,
8748 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8749 tree v16qi_ftype_v8hi_v8hi
8750 = build_function_type_list (V16QI_type_node
,
8751 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8752 tree v4si_ftype_v16qi_v4si
8753 = build_function_type_list (V4SI_type_node
,
8754 V16QI_type_node
, V4SI_type_node
, NULL_TREE
);
8755 tree v4si_ftype_v16qi_v16qi
8756 = build_function_type_list (V4SI_type_node
,
8757 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8758 tree v4si_ftype_v8hi_v4si
8759 = build_function_type_list (V4SI_type_node
,
8760 V8HI_type_node
, V4SI_type_node
, NULL_TREE
);
8761 tree v4si_ftype_v8hi
8762 = build_function_type_list (V4SI_type_node
, V8HI_type_node
, NULL_TREE
);
8763 tree int_ftype_v4si_v4si
8764 = build_function_type_list (integer_type_node
,
8765 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8766 tree int_ftype_v4sf_v4sf
8767 = build_function_type_list (integer_type_node
,
8768 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8769 tree int_ftype_v16qi_v16qi
8770 = build_function_type_list (integer_type_node
,
8771 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8772 tree int_ftype_v8hi_v8hi
8773 = build_function_type_list (integer_type_node
,
8774 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8776 /* Add the simple ternary operators. */
8777 d
= (struct builtin_description
*) bdesc_3arg
;
8778 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
8780 enum machine_mode mode0
, mode1
, mode2
, mode3
;
8782 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8783 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
8794 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8797 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8798 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8799 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8800 mode3
= insn_data
[d
->icode
].operand
[3].mode
;
8803 /* When all four are of the same mode. */
8804 if (mode0
== mode1
&& mode1
== mode2
&& mode2
== mode3
)
8809 type
= opaque_ftype_opaque_opaque_opaque
;
8812 type
= v4si_ftype_v4si_v4si_v4si
;
8815 type
= v4sf_ftype_v4sf_v4sf_v4sf
;
8818 type
= v8hi_ftype_v8hi_v8hi_v8hi
;
8821 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
8827 else if (mode0
== mode1
&& mode1
== mode2
&& mode3
== V16QImode
)
8832 type
= v4si_ftype_v4si_v4si_v16qi
;
8835 type
= v4sf_ftype_v4sf_v4sf_v16qi
;
8838 type
= v8hi_ftype_v8hi_v8hi_v16qi
;
8841 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
8847 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
8848 && mode3
== V4SImode
)
8849 type
= v4si_ftype_v16qi_v16qi_v4si
;
8850 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
8851 && mode3
== V4SImode
)
8852 type
= v4si_ftype_v8hi_v8hi_v4si
;
8853 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
8854 && mode3
== V4SImode
)
8855 type
= v4sf_ftype_v4sf_v4sf_v4si
;
8857 /* vchar, vchar, vchar, 4 bit literal. */
8858 else if (mode0
== V16QImode
&& mode1
== mode0
&& mode2
== mode0
8860 type
= v16qi_ftype_v16qi_v16qi_int
;
8862 /* vshort, vshort, vshort, 4 bit literal. */
8863 else if (mode0
== V8HImode
&& mode1
== mode0
&& mode2
== mode0
8865 type
= v8hi_ftype_v8hi_v8hi_int
;
8867 /* vint, vint, vint, 4 bit literal. */
8868 else if (mode0
== V4SImode
&& mode1
== mode0
&& mode2
== mode0
8870 type
= v4si_ftype_v4si_v4si_int
;
8872 /* vfloat, vfloat, vfloat, 4 bit literal. */
8873 else if (mode0
== V4SFmode
&& mode1
== mode0
&& mode2
== mode0
8875 type
= v4sf_ftype_v4sf_v4sf_int
;
8880 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8883 /* Add the simple binary operators. */
8884 d
= (struct builtin_description
*) bdesc_2arg
;
8885 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
8887 enum machine_mode mode0
, mode1
, mode2
;
8889 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8890 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
8900 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8903 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8904 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8905 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8908 /* When all three operands are of the same mode. */
8909 if (mode0
== mode1
&& mode1
== mode2
)
8914 type
= opaque_ftype_opaque_opaque
;
8917 type
= v4sf_ftype_v4sf_v4sf
;
8920 type
= v4si_ftype_v4si_v4si
;
8923 type
= v16qi_ftype_v16qi_v16qi
;
8926 type
= v8hi_ftype_v8hi_v8hi
;
8929 type
= v2si_ftype_v2si_v2si
;
8932 type
= v2sf_ftype_v2sf_v2sf
;
8935 type
= int_ftype_int_int
;
8942 /* A few other combos we really don't want to do manually. */
8944 /* vint, vfloat, vfloat. */
8945 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
)
8946 type
= v4si_ftype_v4sf_v4sf
;
8948 /* vshort, vchar, vchar. */
8949 else if (mode0
== V8HImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
8950 type
= v8hi_ftype_v16qi_v16qi
;
8952 /* vint, vshort, vshort. */
8953 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
8954 type
= v4si_ftype_v8hi_v8hi
;
8956 /* vshort, vint, vint. */
8957 else if (mode0
== V8HImode
&& mode1
== V4SImode
&& mode2
== V4SImode
)
8958 type
= v8hi_ftype_v4si_v4si
;
8960 /* vchar, vshort, vshort. */
8961 else if (mode0
== V16QImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
8962 type
= v16qi_ftype_v8hi_v8hi
;
8964 /* vint, vchar, vint. */
8965 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V4SImode
)
8966 type
= v4si_ftype_v16qi_v4si
;
8968 /* vint, vchar, vchar. */
8969 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
8970 type
= v4si_ftype_v16qi_v16qi
;
8972 /* vint, vshort, vint. */
8973 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V4SImode
)
8974 type
= v4si_ftype_v8hi_v4si
;
8976 /* vint, vint, 5 bit literal. */
8977 else if (mode0
== V4SImode
&& mode1
== V4SImode
&& mode2
== QImode
)
8978 type
= v4si_ftype_v4si_int
;
8980 /* vshort, vshort, 5 bit literal. */
8981 else if (mode0
== V8HImode
&& mode1
== V8HImode
&& mode2
== QImode
)
8982 type
= v8hi_ftype_v8hi_int
;
8984 /* vchar, vchar, 5 bit literal. */
8985 else if (mode0
== V16QImode
&& mode1
== V16QImode
&& mode2
== QImode
)
8986 type
= v16qi_ftype_v16qi_int
;
8988 /* vfloat, vint, 5 bit literal. */
8989 else if (mode0
== V4SFmode
&& mode1
== V4SImode
&& mode2
== QImode
)
8990 type
= v4sf_ftype_v4si_int
;
8992 /* vint, vfloat, 5 bit literal. */
8993 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== QImode
)
8994 type
= v4si_ftype_v4sf_int
;
8996 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== SImode
)
8997 type
= v2si_ftype_int_int
;
8999 else if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
9000 type
= v2si_ftype_v2si_char
;
9002 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== QImode
)
9003 type
= v2si_ftype_int_char
;
9008 gcc_assert (mode0
== SImode
);
9012 type
= int_ftype_v4si_v4si
;
9015 type
= int_ftype_v4sf_v4sf
;
9018 type
= int_ftype_v16qi_v16qi
;
9021 type
= int_ftype_v8hi_v8hi
;
9028 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9031 /* Add the simple unary operators. */
9032 d
= (struct builtin_description
*) bdesc_1arg
;
9033 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9035 enum machine_mode mode0
, mode1
;
9037 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9038 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
9047 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
9050 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
9051 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
9054 if (mode0
== V4SImode
&& mode1
== QImode
)
9055 type
= v4si_ftype_int
;
9056 else if (mode0
== V8HImode
&& mode1
== QImode
)
9057 type
= v8hi_ftype_int
;
9058 else if (mode0
== V16QImode
&& mode1
== QImode
)
9059 type
= v16qi_ftype_int
;
9060 else if (mode0
== VOIDmode
&& mode1
== VOIDmode
)
9061 type
= opaque_ftype_opaque
;
9062 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
)
9063 type
= v4sf_ftype_v4sf
;
9064 else if (mode0
== V8HImode
&& mode1
== V16QImode
)
9065 type
= v8hi_ftype_v16qi
;
9066 else if (mode0
== V4SImode
&& mode1
== V8HImode
)
9067 type
= v4si_ftype_v8hi
;
9068 else if (mode0
== V2SImode
&& mode1
== V2SImode
)
9069 type
= v2si_ftype_v2si
;
9070 else if (mode0
== V2SFmode
&& mode1
== V2SFmode
)
9071 type
= v2sf_ftype_v2sf
;
9072 else if (mode0
== V2SFmode
&& mode1
== V2SImode
)
9073 type
= v2sf_ftype_v2si
;
9074 else if (mode0
== V2SImode
&& mode1
== V2SFmode
)
9075 type
= v2si_ftype_v2sf
;
9076 else if (mode0
== V2SImode
&& mode1
== QImode
)
9077 type
= v2si_ftype_char
;
9081 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9086 rs6000_init_libfuncs (void)
9088 if (!TARGET_HARD_FLOAT
)
9091 if (DEFAULT_ABI
!= ABI_V4
)
9093 if (TARGET_XCOFF
&& ! TARGET_POWER2
&& ! TARGET_POWERPC
)
9095 /* AIX library routines for float->int conversion. */
9096 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
9097 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
9098 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
9099 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
9102 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9103 if (!TARGET_XL_COMPAT
)
9105 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
9106 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
9107 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
9108 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
9112 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
9113 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
9114 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
9115 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
9120 /* 32-bit SVR4 quad floating point routines. */
9122 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
9123 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
9124 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
9125 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
9126 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
9127 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
9128 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
9130 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
9131 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
9132 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
9133 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
9134 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
9135 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
9137 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
9138 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
9139 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
9140 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
9141 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
9142 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
9143 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
9144 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
9149 /* Expand a block clear operation, and return 1 if successful. Return 0
9150 if we should let the compiler generate normal code.
9152 operands[0] is the destination
9153 operands[1] is the length
9154 operands[3] is the alignment */
9157 expand_block_clear (rtx operands
[])
9159 rtx orig_dest
= operands
[0];
9160 rtx bytes_rtx
= operands
[1];
9161 rtx align_rtx
= operands
[3];
9162 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
9163 HOST_WIDE_INT align
;
9164 HOST_WIDE_INT bytes
;
9169 /* If this is not a fixed size move, just call memcpy */
9173 /* This must be a fixed size alignment */
9174 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
9175 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
9177 /* Anything to clear? */
9178 bytes
= INTVAL (bytes_rtx
);
9182 /* Use the builtin memset after a point, to avoid huge code bloat.
9183 When optimize_size, avoid any significant code bloat; calling
9184 memset is about 4 instructions, so allow for one instruction to
9185 load zero and three to do clearing. */
9186 if (TARGET_ALTIVEC
&& align
>= 128)
9188 else if (TARGET_POWERPC64
&& align
>= 32)
9193 if (optimize_size
&& bytes
> 3 * clear_step
)
9195 if (! optimize_size
&& bytes
> 8 * clear_step
)
9198 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
9200 enum machine_mode mode
= BLKmode
;
9203 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
9208 else if (bytes
>= 8 && TARGET_POWERPC64
9209 /* 64-bit loads and stores require word-aligned
9211 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
9216 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
9217 { /* move 4 bytes */
9221 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
9222 { /* move 2 bytes */
9226 else /* move 1 byte at a time */
9232 dest
= adjust_address (orig_dest
, mode
, offset
);
9234 emit_move_insn (dest
, CONST0_RTX (mode
));
9241 /* Expand a block move operation, and return 1 if successful. Return 0
9242 if we should let the compiler generate normal code.
9244 operands[0] is the destination
9245 operands[1] is the source
9246 operands[2] is the length
9247 operands[3] is the alignment */
9249 #define MAX_MOVE_REG 4
9252 expand_block_move (rtx operands
[])
9254 rtx orig_dest
= operands
[0];
9255 rtx orig_src
= operands
[1];
9256 rtx bytes_rtx
= operands
[2];
9257 rtx align_rtx
= operands
[3];
9258 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
9263 rtx stores
[MAX_MOVE_REG
];
9266 /* If this is not a fixed size move, just call memcpy */
9270 /* This must be a fixed size alignment */
9271 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
9272 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
9274 /* Anything to move? */
9275 bytes
= INTVAL (bytes_rtx
);
9279 /* store_one_arg depends on expand_block_move to handle at least the size of
9280 reg_parm_stack_space. */
9281 if (bytes
> (TARGET_POWERPC64
? 64 : 32))
9284 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
9287 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
9288 rtx (*mov
) (rtx
, rtx
);
9290 enum machine_mode mode
= BLKmode
;
9293 /* Altivec first, since it will be faster than a string move
9294 when it applies, and usually not significantly larger. */
9295 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
9299 gen_func
.mov
= gen_movv4si
;
9301 else if (TARGET_STRING
9302 && bytes
> 24 /* move up to 32 bytes at a time */
9310 && ! fixed_regs
[12])
9312 move_bytes
= (bytes
> 32) ? 32 : bytes
;
9313 gen_func
.movmemsi
= gen_movmemsi_8reg
;
9315 else if (TARGET_STRING
9316 && bytes
> 16 /* move up to 24 bytes at a time */
9322 && ! fixed_regs
[10])
9324 move_bytes
= (bytes
> 24) ? 24 : bytes
;
9325 gen_func
.movmemsi
= gen_movmemsi_6reg
;
9327 else if (TARGET_STRING
9328 && bytes
> 8 /* move up to 16 bytes at a time */
9334 move_bytes
= (bytes
> 16) ? 16 : bytes
;
9335 gen_func
.movmemsi
= gen_movmemsi_4reg
;
9337 else if (bytes
>= 8 && TARGET_POWERPC64
9338 /* 64-bit loads and stores require word-aligned
9340 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
9344 gen_func
.mov
= gen_movdi
;
9346 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
9347 { /* move up to 8 bytes at a time */
9348 move_bytes
= (bytes
> 8) ? 8 : bytes
;
9349 gen_func
.movmemsi
= gen_movmemsi_2reg
;
9351 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
9352 { /* move 4 bytes */
9355 gen_func
.mov
= gen_movsi
;
9357 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
9358 { /* move 2 bytes */
9361 gen_func
.mov
= gen_movhi
;
9363 else if (TARGET_STRING
&& bytes
> 1)
9364 { /* move up to 4 bytes at a time */
9365 move_bytes
= (bytes
> 4) ? 4 : bytes
;
9366 gen_func
.movmemsi
= gen_movmemsi_1reg
;
9368 else /* move 1 byte at a time */
9372 gen_func
.mov
= gen_movqi
;
9375 src
= adjust_address (orig_src
, mode
, offset
);
9376 dest
= adjust_address (orig_dest
, mode
, offset
);
9378 if (mode
!= BLKmode
)
9380 rtx tmp_reg
= gen_reg_rtx (mode
);
9382 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
9383 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
9386 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
9389 for (i
= 0; i
< num_reg
; i
++)
9390 emit_insn (stores
[i
]);
9394 if (mode
== BLKmode
)
9396 /* Move the address into scratch registers. The movmemsi
9397 patterns require zero offset. */
9398 if (!REG_P (XEXP (src
, 0)))
9400 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
9401 src
= replace_equiv_address (src
, src_reg
);
9403 set_mem_size (src
, GEN_INT (move_bytes
));
9405 if (!REG_P (XEXP (dest
, 0)))
9407 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
9408 dest
= replace_equiv_address (dest
, dest_reg
);
9410 set_mem_size (dest
, GEN_INT (move_bytes
));
9412 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
9413 GEN_INT (move_bytes
& 31),
9422 /* Return a string to perform a load_multiple operation.
9423 operands[0] is the vector.
9424 operands[1] is the source address.
9425 operands[2] is the first destination register. */
9428 rs6000_output_load_multiple (rtx operands
[3])
9430 /* We have to handle the case where the pseudo used to contain the address
9431 is assigned to one of the output registers. */
9433 int words
= XVECLEN (operands
[0], 0);
9436 if (XVECLEN (operands
[0], 0) == 1)
9437 return "{l|lwz} %2,0(%1)";
9439 for (i
= 0; i
< words
; i
++)
9440 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
9441 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
9445 xop
[0] = GEN_INT (4 * (words
-1));
9446 xop
[1] = operands
[1];
9447 xop
[2] = operands
[2];
9448 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
9453 xop
[0] = GEN_INT (4 * (words
-1));
9454 xop
[1] = operands
[1];
9455 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
9456 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
9461 for (j
= 0; j
< words
; j
++)
9464 xop
[0] = GEN_INT (j
* 4);
9465 xop
[1] = operands
[1];
9466 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
9467 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
9469 xop
[0] = GEN_INT (i
* 4);
9470 xop
[1] = operands
[1];
9471 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
9476 return "{lsi|lswi} %2,%1,%N0";
9480 /* A validation routine: say whether CODE, a condition code, and MODE
9481 match. The other alternatives either don't make sense or should
9482 never be generated. */
9485 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
9487 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
9488 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
9489 && GET_MODE_CLASS (mode
) == MODE_CC
);
9491 /* These don't make sense. */
9492 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
9493 || mode
!= CCUNSmode
);
9495 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
9496 || mode
== CCUNSmode
);
9498 gcc_assert (mode
== CCFPmode
9499 || (code
!= ORDERED
&& code
!= UNORDERED
9500 && code
!= UNEQ
&& code
!= LTGT
9501 && code
!= UNGT
&& code
!= UNLT
9502 && code
!= UNGE
&& code
!= UNLE
));
9504 /* These should never be generated except for
9505 flag_finite_math_only. */
9506 gcc_assert (mode
!= CCFPmode
9507 || flag_finite_math_only
9508 || (code
!= LE
&& code
!= GE
9509 && code
!= UNEQ
&& code
!= LTGT
9510 && code
!= UNGT
&& code
!= UNLT
));
9512 /* These are invalid; the information is not there. */
9513 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
9517 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9518 mask required to convert the result of a rotate insn into a shift
9519 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9522 includes_lshift_p (rtx shiftop
, rtx andop
)
9524 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
9526 shift_mask
<<= INTVAL (shiftop
);
9528 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
9531 /* Similar, but for right shift. */
9534 includes_rshift_p (rtx shiftop
, rtx andop
)
9536 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
9538 shift_mask
>>= INTVAL (shiftop
);
9540 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
9543 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9544 to perform a left shift. It must have exactly SHIFTOP least
9545 significant 0's, then one or more 1's, then zero or more 0's. */
9548 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
9550 if (GET_CODE (andop
) == CONST_INT
)
9552 HOST_WIDE_INT c
, lsb
, shift_mask
;
9555 if (c
== 0 || c
== ~0)
9559 shift_mask
<<= INTVAL (shiftop
);
9561 /* Find the least significant one bit. */
9564 /* It must coincide with the LSB of the shift mask. */
9565 if (-lsb
!= shift_mask
)
9568 /* Invert to look for the next transition (if any). */
9571 /* Remove the low group of ones (originally low group of zeros). */
9574 /* Again find the lsb, and check we have all 1's above. */
9578 else if (GET_CODE (andop
) == CONST_DOUBLE
9579 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
9581 HOST_WIDE_INT low
, high
, lsb
;
9582 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
9584 low
= CONST_DOUBLE_LOW (andop
);
9585 if (HOST_BITS_PER_WIDE_INT
< 64)
9586 high
= CONST_DOUBLE_HIGH (andop
);
9588 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
9589 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
9592 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
9594 shift_mask_high
= ~0;
9595 if (INTVAL (shiftop
) > 32)
9596 shift_mask_high
<<= INTVAL (shiftop
) - 32;
9600 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
9607 return high
== -lsb
;
9610 shift_mask_low
= ~0;
9611 shift_mask_low
<<= INTVAL (shiftop
);
9615 if (-lsb
!= shift_mask_low
)
9618 if (HOST_BITS_PER_WIDE_INT
< 64)
9623 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
9626 return high
== -lsb
;
9630 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
9636 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9637 to perform a left shift. It must have SHIFTOP or more least
9638 significant 0's, with the remainder of the word 1's. */
9641 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
9643 if (GET_CODE (andop
) == CONST_INT
)
9645 HOST_WIDE_INT c
, lsb
, shift_mask
;
9648 shift_mask
<<= INTVAL (shiftop
);
9651 /* Find the least significant one bit. */
9654 /* It must be covered by the shift mask.
9655 This test also rejects c == 0. */
9656 if ((lsb
& shift_mask
) == 0)
9659 /* Check we have all 1's above the transition, and reject all 1's. */
9660 return c
== -lsb
&& lsb
!= 1;
9662 else if (GET_CODE (andop
) == CONST_DOUBLE
9663 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
9665 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
9667 low
= CONST_DOUBLE_LOW (andop
);
9669 if (HOST_BITS_PER_WIDE_INT
< 64)
9671 HOST_WIDE_INT high
, shift_mask_high
;
9673 high
= CONST_DOUBLE_HIGH (andop
);
9677 shift_mask_high
= ~0;
9678 if (INTVAL (shiftop
) > 32)
9679 shift_mask_high
<<= INTVAL (shiftop
) - 32;
9683 if ((lsb
& shift_mask_high
) == 0)
9686 return high
== -lsb
;
9692 shift_mask_low
= ~0;
9693 shift_mask_low
<<= INTVAL (shiftop
);
9697 if ((lsb
& shift_mask_low
) == 0)
9700 return low
== -lsb
&& lsb
!= 1;
9706 /* Return 1 if operands will generate a valid arguments to rlwimi
9707 instruction for insert with right shift in 64-bit mode. The mask may
9708 not start on the first bit or stop on the last bit because wrap-around
9709 effects of instruction do not correspond to semantics of RTL insn. */
9712 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
9714 if (INTVAL (startop
) < 64
9715 && INTVAL (startop
) > 32
9716 && (INTVAL (sizeop
) + INTVAL (startop
) < 64)
9717 && (INTVAL (sizeop
) + INTVAL (startop
) > 33)
9718 && (INTVAL (sizeop
) + INTVAL (startop
) + INTVAL (shiftop
) < 96)
9719 && (INTVAL (sizeop
) + INTVAL (startop
) + INTVAL (shiftop
) >= 64)
9720 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
9726 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9727 for lfq and stfq insns iff the registers are hard registers. */
9730 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
9732 /* We might have been passed a SUBREG. */
9733 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
9736 /* We might have been passed non floating point registers. */
9737 if (!FP_REGNO_P (REGNO (reg1
))
9738 || !FP_REGNO_P (REGNO (reg2
)))
9741 return (REGNO (reg1
) == REGNO (reg2
) - 1);
9744 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9745 addr1 and addr2 must be in consecutive memory locations
9746 (addr2 == addr1 + 8). */
9749 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
9752 unsigned int reg1
, reg2
;
9753 int offset1
, offset2
;
9755 /* The mems cannot be volatile. */
9756 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
9759 addr1
= XEXP (mem1
, 0);
9760 addr2
= XEXP (mem2
, 0);
9762 /* Extract an offset (if used) from the first addr. */
9763 if (GET_CODE (addr1
) == PLUS
)
9765 /* If not a REG, return zero. */
9766 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
9770 reg1
= REGNO (XEXP (addr1
, 0));
9771 /* The offset must be constant! */
9772 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
9774 offset1
= INTVAL (XEXP (addr1
, 1));
9777 else if (GET_CODE (addr1
) != REG
)
9781 reg1
= REGNO (addr1
);
9782 /* This was a simple (mem (reg)) expression. Offset is 0. */
9786 /* And now for the second addr. */
9787 if (GET_CODE (addr2
) == PLUS
)
9789 /* If not a REG, return zero. */
9790 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
9794 reg2
= REGNO (XEXP (addr2
, 0));
9795 /* The offset must be constant. */
9796 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
9798 offset2
= INTVAL (XEXP (addr2
, 1));
9801 else if (GET_CODE (addr2
) != REG
)
9805 reg2
= REGNO (addr2
);
9806 /* This was a simple (mem (reg)) expression. Offset is 0. */
9810 /* Both of these must have the same base register. */
9814 /* The offset for the second addr must be 8 more than the first addr. */
9815 if (offset2
!= offset1
+ 8)
9818 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9823 /* Return the register class of a scratch register needed to copy IN into
9824 or out of a register in CLASS in MODE. If it can be done directly,
9825 NO_REGS is returned. */
9828 rs6000_secondary_reload_class (enum reg_class
class,
9829 enum machine_mode mode ATTRIBUTE_UNUSED
,
9834 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
9836 && MACHOPIC_INDIRECT
9840 /* We cannot copy a symbolic operand directly into anything
9841 other than BASE_REGS for TARGET_ELF. So indicate that a
9842 register from BASE_REGS is needed as an intermediate
9845 On Darwin, pic addresses require a load from memory, which
9846 needs a base register. */
9847 if (class != BASE_REGS
9848 && (GET_CODE (in
) == SYMBOL_REF
9849 || GET_CODE (in
) == HIGH
9850 || GET_CODE (in
) == LABEL_REF
9851 || GET_CODE (in
) == CONST
))
9855 if (GET_CODE (in
) == REG
)
9858 if (regno
>= FIRST_PSEUDO_REGISTER
)
9860 regno
= true_regnum (in
);
9861 if (regno
>= FIRST_PSEUDO_REGISTER
)
9865 else if (GET_CODE (in
) == SUBREG
)
9867 regno
= true_regnum (in
);
9868 if (regno
>= FIRST_PSEUDO_REGISTER
)
9874 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9876 if (class == GENERAL_REGS
|| class == BASE_REGS
9877 || (regno
>= 0 && INT_REGNO_P (regno
)))
9880 /* Constants, memory, and FP registers can go into FP registers. */
9881 if ((regno
== -1 || FP_REGNO_P (regno
))
9882 && (class == FLOAT_REGS
|| class == NON_SPECIAL_REGS
))
9885 /* Memory, and AltiVec registers can go into AltiVec registers. */
9886 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
9887 && class == ALTIVEC_REGS
)
9890 /* We can copy among the CR registers. */
9891 if ((class == CR_REGS
|| class == CR0_REGS
)
9892 && regno
>= 0 && CR_REGNO_P (regno
))
9895 /* Otherwise, we need GENERAL_REGS. */
9896 return GENERAL_REGS
;
9899 /* Given a comparison operation, return the bit number in CCR to test. We
9900 know this is a valid comparison.
9902 SCC_P is 1 if this is for an scc. That means that %D will have been
9903 used instead of %C, so the bits will be in different places.
9905 Return -1 if OP isn't a valid comparison for some reason. */
9908 ccr_bit (rtx op
, int scc_p
)
9910 enum rtx_code code
= GET_CODE (op
);
9911 enum machine_mode cc_mode
;
9916 if (!COMPARISON_P (op
))
9921 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
9923 cc_mode
= GET_MODE (reg
);
9924 cc_regnum
= REGNO (reg
);
9925 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
9927 validate_condition_mode (code
, cc_mode
);
9929 /* When generating a sCOND operation, only positive conditions are
9932 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
9933 || code
== GTU
|| code
== LTU
);
9938 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
9940 return base_bit
+ 2;
9941 case GT
: case GTU
: case UNLE
:
9942 return base_bit
+ 1;
9943 case LT
: case LTU
: case UNGE
:
9945 case ORDERED
: case UNORDERED
:
9946 return base_bit
+ 3;
9949 /* If scc, we will have done a cror to put the bit in the
9950 unordered position. So test that bit. For integer, this is ! LT
9951 unless this is an scc insn. */
9952 return scc_p
? base_bit
+ 3 : base_bit
;
9955 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
9962 /* Return the GOT register. */
9965 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
9967 /* The second flow pass currently (June 1999) can't update
9968 regs_ever_live without disturbing other parts of the compiler, so
9969 update it here to make the prolog/epilogue code happy. */
9970 if (no_new_pseudos
&& ! regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
])
9971 regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9973 current_function_uses_pic_offset_table
= 1;
9975 return pic_offset_table_rtx
;
9978 /* Function to init struct machine_function.
9979 This will be called, via a pointer variable,
9980 from push_function_context. */
9982 static struct machine_function
*
9983 rs6000_init_machine_status (void)
9985 return ggc_alloc_cleared (sizeof (machine_function
));
9988 /* These macros test for integers and extract the low-order bits. */
9990 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9991 && GET_MODE (X) == VOIDmode)
9993 #define INT_LOWPART(X) \
9994 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10000 unsigned long val
= INT_LOWPART (op
);
10002 /* If the high bit is zero, the value is the first 1 bit we find
10004 if ((val
& 0x80000000) == 0)
10006 gcc_assert (val
& 0xffffffff);
10009 while (((val
<<= 1) & 0x80000000) == 0)
10014 /* If the high bit is set and the low bit is not, or the mask is all
10015 1's, the value is zero. */
10016 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
10019 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10022 while (((val
>>= 1) & 1) != 0)
10029 extract_ME (rtx op
)
10032 unsigned long val
= INT_LOWPART (op
);
10034 /* If the low bit is zero, the value is the first 1 bit we find from
10036 if ((val
& 1) == 0)
10038 gcc_assert (val
& 0xffffffff);
10041 while (((val
>>= 1) & 1) == 0)
10047 /* If the low bit is set and the high bit is not, or the mask is all
10048 1's, the value is 31. */
10049 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
10052 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10055 while (((val
<<= 1) & 0x80000000) != 0)
10061 /* Locate some local-dynamic symbol still in use by this function
10062 so that we can print its name in some tls_ld pattern. */
10064 static const char *
10065 rs6000_get_some_local_dynamic_name (void)
10069 if (cfun
->machine
->some_ld_name
)
10070 return cfun
->machine
->some_ld_name
;
10072 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10074 && for_each_rtx (&PATTERN (insn
),
10075 rs6000_get_some_local_dynamic_name_1
, 0))
10076 return cfun
->machine
->some_ld_name
;
10078 gcc_unreachable ();
10081 /* Helper function for rs6000_get_some_local_dynamic_name. */
10084 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
10088 if (GET_CODE (x
) == SYMBOL_REF
)
10090 const char *str
= XSTR (x
, 0);
10091 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
10093 cfun
->machine
->some_ld_name
= str
;
10101 /* Write out a function code label. */
10104 rs6000_output_function_entry (FILE *file
, const char *fname
)
10106 if (fname
[0] != '.')
10108 switch (DEFAULT_ABI
)
10111 gcc_unreachable ();
10117 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
10126 RS6000_OUTPUT_BASENAME (file
, fname
);
10128 assemble_name (file
, fname
);
10131 /* Print an operand. Recognize special options, documented below. */
10134 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10135 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10137 #define SMALL_DATA_RELOC "sda21"
10138 #define SMALL_DATA_REG 0
10142 print_operand (FILE *file
, rtx x
, int code
)
10146 unsigned HOST_WIDE_INT uval
;
10151 /* Write out an instruction after the call which may be replaced
10152 with glue code by the loader. This depends on the AIX version. */
10153 asm_fprintf (file
, RS6000_CALL_GLUE
);
10156 /* %a is output_address. */
10159 /* If X is a constant integer whose low-order 5 bits are zero,
10160 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10161 in the AIX assembler where "sri" with a zero shift count
10162 writes a trash instruction. */
10163 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
10170 /* If constant, low-order 16 bits of constant, unsigned.
10171 Otherwise, write normally. */
10173 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
10175 print_operand (file
, x
, 0);
10179 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10180 for 64-bit mask direction. */
10181 putc (((INT_LOWPART (x
) & 1) == 0 ? 'r' : 'l'), file
);
10184 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10188 /* X is a CR register. Print the number of the GT bit of the CR. */
10189 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10190 output_operand_lossage ("invalid %%E value");
10192 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
10196 /* Like 'J' but get to the EQ bit. */
10197 gcc_assert (GET_CODE (x
) == REG
);
10199 /* Bit 1 is EQ bit. */
10200 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 2;
10202 fprintf (file
, "%d", i
);
10206 /* X is a CR register. Print the number of the EQ bit of the CR */
10207 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10208 output_operand_lossage ("invalid %%E value");
10210 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
10214 /* X is a CR register. Print the shift count needed to move it
10215 to the high-order four bits. */
10216 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10217 output_operand_lossage ("invalid %%f value");
10219 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
10223 /* Similar, but print the count for the rotate in the opposite
10225 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10226 output_operand_lossage ("invalid %%F value");
10228 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
10232 /* X is a constant integer. If it is negative, print "m",
10233 otherwise print "z". This is to make an aze or ame insn. */
10234 if (GET_CODE (x
) != CONST_INT
)
10235 output_operand_lossage ("invalid %%G value");
10236 else if (INTVAL (x
) >= 0)
10243 /* If constant, output low-order five bits. Otherwise, write
10246 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
10248 print_operand (file
, x
, 0);
10252 /* If constant, output low-order six bits. Otherwise, write
10255 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
10257 print_operand (file
, x
, 0);
10261 /* Print `i' if this is a constant, else nothing. */
10267 /* Write the bit number in CCR for jump. */
10268 i
= ccr_bit (x
, 0);
10270 output_operand_lossage ("invalid %%j code");
10272 fprintf (file
, "%d", i
);
10276 /* Similar, but add one for shift count in rlinm for scc and pass
10277 scc flag to `ccr_bit'. */
10278 i
= ccr_bit (x
, 1);
10280 output_operand_lossage ("invalid %%J code");
10282 /* If we want bit 31, write a shift count of zero, not 32. */
10283 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
10287 /* X must be a constant. Write the 1's complement of the
10290 output_operand_lossage ("invalid %%k value");
10292 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
10296 /* X must be a symbolic constant on ELF. Write an
10297 expression suitable for an 'addi' that adds in the low 16
10298 bits of the MEM. */
10299 if (GET_CODE (x
) != CONST
)
10301 print_operand_address (file
, x
);
10302 fputs ("@l", file
);
10306 if (GET_CODE (XEXP (x
, 0)) != PLUS
10307 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
10308 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
10309 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
10310 output_operand_lossage ("invalid %%K value");
10311 print_operand_address (file
, XEXP (XEXP (x
, 0), 0));
10312 fputs ("@l", file
);
10313 /* For GNU as, there must be a non-alphanumeric character
10314 between 'l' and the number. The '-' is added by
10315 print_operand() already. */
10316 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
10318 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
10322 /* %l is output_asm_label. */
10325 /* Write second word of DImode or DFmode reference. Works on register
10326 or non-indexed memory only. */
10327 if (GET_CODE (x
) == REG
)
10328 fputs (reg_names
[REGNO (x
) + 1], file
);
10329 else if (GET_CODE (x
) == MEM
)
10331 /* Handle possible auto-increment. Since it is pre-increment and
10332 we have already done it, we can just use an offset of word. */
10333 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
10334 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10335 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
10338 output_address (XEXP (adjust_address_nv (x
, SImode
,
10342 if (small_data_operand (x
, GET_MODE (x
)))
10343 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10344 reg_names
[SMALL_DATA_REG
]);
10349 /* MB value for a mask operand. */
10350 if (! mask_operand (x
, SImode
))
10351 output_operand_lossage ("invalid %%m value");
10353 fprintf (file
, "%d", extract_MB (x
));
10357 /* ME value for a mask operand. */
10358 if (! mask_operand (x
, SImode
))
10359 output_operand_lossage ("invalid %%M value");
10361 fprintf (file
, "%d", extract_ME (x
));
10364 /* %n outputs the negative of its operand. */
10367 /* Write the number of elements in the vector times 4. */
10368 if (GET_CODE (x
) != PARALLEL
)
10369 output_operand_lossage ("invalid %%N value");
10371 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
10375 /* Similar, but subtract 1 first. */
10376 if (GET_CODE (x
) != PARALLEL
)
10377 output_operand_lossage ("invalid %%O value");
10379 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
10383 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10385 || INT_LOWPART (x
) < 0
10386 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
10387 output_operand_lossage ("invalid %%p value");
10389 fprintf (file
, "%d", i
);
10393 /* The operand must be an indirect memory reference. The result
10394 is the register name. */
10395 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
10396 || REGNO (XEXP (x
, 0)) >= 32)
10397 output_operand_lossage ("invalid %%P value");
10399 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
10403 /* This outputs the logical code corresponding to a boolean
10404 expression. The expression may have one or both operands
10405 negated (if one, only the first one). For condition register
10406 logical operations, it will also treat the negated
10407 CR codes as NOTs, but not handle NOTs of them. */
10409 const char *const *t
= 0;
10411 enum rtx_code code
= GET_CODE (x
);
10412 static const char * const tbl
[3][3] = {
10413 { "and", "andc", "nor" },
10414 { "or", "orc", "nand" },
10415 { "xor", "eqv", "xor" } };
10419 else if (code
== IOR
)
10421 else if (code
== XOR
)
10424 output_operand_lossage ("invalid %%q value");
10426 if (GET_CODE (XEXP (x
, 0)) != NOT
)
10430 if (GET_CODE (XEXP (x
, 1)) == NOT
)
10448 /* X is a CR register. Print the mask for `mtcrf'. */
10449 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10450 output_operand_lossage ("invalid %%R value");
10452 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
10456 /* Low 5 bits of 32 - value */
10458 output_operand_lossage ("invalid %%s value");
10460 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
10464 /* PowerPC64 mask position. All 0's is excluded.
10465 CONST_INT 32-bit mask is considered sign-extended so any
10466 transition must occur within the CONST_INT, not on the boundary. */
10467 if (! mask64_operand (x
, DImode
))
10468 output_operand_lossage ("invalid %%S value");
10470 uval
= INT_LOWPART (x
);
10472 if (uval
& 1) /* Clear Left */
10474 #if HOST_BITS_PER_WIDE_INT > 64
10475 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
10479 else /* Clear Right */
10482 #if HOST_BITS_PER_WIDE_INT > 64
10483 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
10489 gcc_assert (i
>= 0);
10490 fprintf (file
, "%d", i
);
10494 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10495 gcc_assert (GET_CODE (x
) == REG
&& GET_MODE (x
) == CCmode
);
10497 /* Bit 3 is OV bit. */
10498 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
10500 /* If we want bit 31, write a shift count of zero, not 32. */
10501 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
10505 /* Print the symbolic name of a branch target register. */
10506 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LINK_REGISTER_REGNUM
10507 && REGNO (x
) != COUNT_REGISTER_REGNUM
))
10508 output_operand_lossage ("invalid %%T value");
10509 else if (REGNO (x
) == LINK_REGISTER_REGNUM
)
10510 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
10512 fputs ("ctr", file
);
10516 /* High-order 16 bits of constant for use in unsigned operand. */
10518 output_operand_lossage ("invalid %%u value");
10520 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
10521 (INT_LOWPART (x
) >> 16) & 0xffff);
10525 /* High-order 16 bits of constant for use in signed operand. */
10527 output_operand_lossage ("invalid %%v value");
10529 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
10530 (INT_LOWPART (x
) >> 16) & 0xffff);
10534 /* Print `u' if this has an auto-increment or auto-decrement. */
10535 if (GET_CODE (x
) == MEM
10536 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
10537 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
))
10542 /* Print the trap code for this operand. */
10543 switch (GET_CODE (x
))
10546 fputs ("eq", file
); /* 4 */
10549 fputs ("ne", file
); /* 24 */
10552 fputs ("lt", file
); /* 16 */
10555 fputs ("le", file
); /* 20 */
10558 fputs ("gt", file
); /* 8 */
10561 fputs ("ge", file
); /* 12 */
10564 fputs ("llt", file
); /* 2 */
10567 fputs ("lle", file
); /* 6 */
10570 fputs ("lgt", file
); /* 1 */
10573 fputs ("lge", file
); /* 5 */
10576 gcc_unreachable ();
10581 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10584 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
10585 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
10587 print_operand (file
, x
, 0);
10591 /* MB value for a PowerPC64 rldic operand. */
10592 val
= (GET_CODE (x
) == CONST_INT
10593 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
10598 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
10599 if ((val
<<= 1) < 0)
10602 #if HOST_BITS_PER_WIDE_INT == 32
10603 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
10604 i
+= 32; /* zero-extend high-part was all 0's */
10605 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
10607 val
= CONST_DOUBLE_LOW (x
);
10613 for ( ; i
< 64; i
++)
10614 if ((val
<<= 1) < 0)
10619 fprintf (file
, "%d", i
+ 1);
10623 if (GET_CODE (x
) == MEM
10624 && legitimate_indexed_address_p (XEXP (x
, 0), 0))
10629 /* Like 'L', for third word of TImode */
10630 if (GET_CODE (x
) == REG
)
10631 fputs (reg_names
[REGNO (x
) + 2], file
);
10632 else if (GET_CODE (x
) == MEM
)
10634 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
10635 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10636 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
10638 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
10639 if (small_data_operand (x
, GET_MODE (x
)))
10640 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10641 reg_names
[SMALL_DATA_REG
]);
10646 /* X is a SYMBOL_REF. Write out the name preceded by a
10647 period and without any trailing data in brackets. Used for function
10648 names. If we are configured for System V (or the embedded ABI) on
10649 the PowerPC, do not emit the period, since those systems do not use
10650 TOCs and the like. */
10651 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
10653 /* Mark the decl as referenced so that cgraph will output the
10655 if (SYMBOL_REF_DECL (x
))
10656 mark_decl_referenced (SYMBOL_REF_DECL (x
));
10658 /* For macho, check to see if we need a stub. */
10661 const char *name
= XSTR (x
, 0);
10663 if (MACHOPIC_INDIRECT
10664 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
10665 name
= machopic_indirection_name (x
, /*stub_p=*/true);
10667 assemble_name (file
, name
);
10669 else if (!DOT_SYMBOLS
)
10670 assemble_name (file
, XSTR (x
, 0));
10672 rs6000_output_function_entry (file
, XSTR (x
, 0));
10676 /* Like 'L', for last word of TImode. */
10677 if (GET_CODE (x
) == REG
)
10678 fputs (reg_names
[REGNO (x
) + 3], file
);
10679 else if (GET_CODE (x
) == MEM
)
10681 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
10682 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10683 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
10685 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
10686 if (small_data_operand (x
, GET_MODE (x
)))
10687 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10688 reg_names
[SMALL_DATA_REG
]);
10692 /* Print AltiVec or SPE memory operand. */
10697 gcc_assert (GET_CODE (x
) == MEM
);
10703 /* Handle [reg]. */
10704 if (GET_CODE (tmp
) == REG
)
10706 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
10709 /* Handle [reg+UIMM]. */
10710 else if (GET_CODE (tmp
) == PLUS
&&
10711 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
10715 gcc_assert (GET_CODE (XEXP (tmp
, 0)) == REG
);
10717 x
= INTVAL (XEXP (tmp
, 1));
10718 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
10722 /* Fall through. Must be [reg+reg]. */
10725 && GET_CODE (tmp
) == AND
10726 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
10727 && INTVAL (XEXP (tmp
, 1)) == -16)
10728 tmp
= XEXP (tmp
, 0);
10729 if (GET_CODE (tmp
) == REG
)
10730 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
10733 gcc_assert (GET_CODE (tmp
) == PLUS
10734 && REG_P (XEXP (tmp
, 0))
10735 && REG_P (XEXP (tmp
, 1)));
10737 if (REGNO (XEXP (tmp
, 0)) == 0)
10738 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
10739 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
10741 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
10742 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
10748 if (GET_CODE (x
) == REG
)
10749 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
10750 else if (GET_CODE (x
) == MEM
)
10752 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10753 know the width from the mode. */
10754 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
10755 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
10756 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
10757 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10758 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
10759 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
10761 output_address (XEXP (x
, 0));
10764 output_addr_const (file
, x
);
10768 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
10772 output_operand_lossage ("invalid %%xn code");
10776 /* Print the address of an operand. */
10779 print_operand_address (FILE *file
, rtx x
)
10781 if (GET_CODE (x
) == REG
)
10782 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
10783 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
10784 || GET_CODE (x
) == LABEL_REF
)
10786 output_addr_const (file
, x
);
10787 if (small_data_operand (x
, GET_MODE (x
)))
10788 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10789 reg_names
[SMALL_DATA_REG
]);
10791 gcc_assert (!TARGET_TOC
);
10793 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
10795 gcc_assert (REG_P (XEXP (x
, 0)));
10796 if (REGNO (XEXP (x
, 0)) == 0)
10797 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
10798 reg_names
[ REGNO (XEXP (x
, 0)) ]);
10800 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
10801 reg_names
[ REGNO (XEXP (x
, 1)) ]);
10803 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
10804 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
10805 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
10807 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
10808 && CONSTANT_P (XEXP (x
, 1)))
10810 output_addr_const (file
, XEXP (x
, 1));
10811 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
10815 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
10816 && CONSTANT_P (XEXP (x
, 1)))
10818 fprintf (file
, "lo16(");
10819 output_addr_const (file
, XEXP (x
, 1));
10820 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
10823 else if (legitimate_constant_pool_address_p (x
))
10825 if (TARGET_AIX
&& (!TARGET_ELF
|| !TARGET_MINIMAL_TOC
))
10827 rtx contains_minus
= XEXP (x
, 1);
10831 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10832 turn it into (sym) for output_addr_const. */
10833 while (GET_CODE (XEXP (contains_minus
, 0)) != MINUS
)
10834 contains_minus
= XEXP (contains_minus
, 0);
10836 minus
= XEXP (contains_minus
, 0);
10837 symref
= XEXP (minus
, 0);
10838 XEXP (contains_minus
, 0) = symref
;
10843 name
= XSTR (symref
, 0);
10844 newname
= alloca (strlen (name
) + sizeof ("@toc"));
10845 strcpy (newname
, name
);
10846 strcat (newname
, "@toc");
10847 XSTR (symref
, 0) = newname
;
10849 output_addr_const (file
, XEXP (x
, 1));
10851 XSTR (symref
, 0) = name
;
10852 XEXP (contains_minus
, 0) = minus
;
10855 output_addr_const (file
, XEXP (x
, 1));
10857 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
10860 gcc_unreachable ();
10863 /* Target hook for assembling integer objects. The PowerPC version has
10864 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10865 is defined. It also needs to handle DI-mode objects on 64-bit
10869 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
10871 #ifdef RELOCATABLE_NEEDS_FIXUP
10872 /* Special handling for SI values. */
10873 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
10875 static int recurse
= 0;
10877 /* For -mrelocatable, we mark all addresses that need to be fixed up
10878 in the .fixup section. */
10879 if (TARGET_RELOCATABLE
10880 && in_section
!= toc_section
10881 && in_section
!= text_section
10882 && unlikely_text_section_p (in_section
)
10884 && GET_CODE (x
) != CONST_INT
10885 && GET_CODE (x
) != CONST_DOUBLE
10891 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
10893 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
10894 fprintf (asm_out_file
, "\t.long\t(");
10895 output_addr_const (asm_out_file
, x
);
10896 fprintf (asm_out_file
, ")@fixup\n");
10897 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
10898 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
10899 fprintf (asm_out_file
, "\t.long\t");
10900 assemble_name (asm_out_file
, buf
);
10901 fprintf (asm_out_file
, "\n\t.previous\n");
10905 /* Remove initial .'s to turn a -mcall-aixdesc function
10906 address into the address of the descriptor, not the function
10908 else if (GET_CODE (x
) == SYMBOL_REF
10909 && XSTR (x
, 0)[0] == '.'
10910 && DEFAULT_ABI
== ABI_AIX
)
10912 const char *name
= XSTR (x
, 0);
10913 while (*name
== '.')
10916 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
10920 #endif /* RELOCATABLE_NEEDS_FIXUP */
10921 return default_assemble_integer (x
, size
, aligned_p
);
10924 #ifdef HAVE_GAS_HIDDEN
10925 /* Emit an assembler directive to set symbol visibility for DECL to
10926 VISIBILITY_TYPE. */
10929 rs6000_assemble_visibility (tree decl
, int vis
)
10931 /* Functions need to have their entry point symbol visibility set as
10932 well as their descriptor symbol visibility. */
10933 if (DEFAULT_ABI
== ABI_AIX
10935 && TREE_CODE (decl
) == FUNCTION_DECL
)
10937 static const char * const visibility_types
[] = {
10938 NULL
, "internal", "hidden", "protected"
10941 const char *name
, *type
;
10943 name
= ((* targetm
.strip_name_encoding
)
10944 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
10945 type
= visibility_types
[vis
];
10947 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
10948 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
10951 default_assemble_visibility (decl
, vis
);
10956 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
10958 /* Reversal of FP compares takes care -- an ordered compare
10959 becomes an unordered compare and vice versa. */
10960 if (mode
== CCFPmode
10961 && (!flag_finite_math_only
10962 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
10963 || code
== UNEQ
|| code
== LTGT
))
10964 return reverse_condition_maybe_unordered (code
);
10966 return reverse_condition (code
);
10969 /* Generate a compare for CODE. Return a brand-new rtx that
10970 represents the result of the compare. */
10973 rs6000_generate_compare (enum rtx_code code
)
10975 enum machine_mode comp_mode
;
10976 rtx compare_result
;
10978 if (rs6000_compare_fp_p
)
10979 comp_mode
= CCFPmode
;
10980 else if (code
== GTU
|| code
== LTU
10981 || code
== GEU
|| code
== LEU
)
10982 comp_mode
= CCUNSmode
;
10983 else if ((code
== EQ
|| code
== NE
)
10984 && GET_CODE (rs6000_compare_op0
) == SUBREG
10985 && GET_CODE (rs6000_compare_op1
) == SUBREG
10986 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0
)
10987 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1
))
10988 /* These are unsigned values, perhaps there will be a later
10989 ordering compare that can be shared with this one.
10990 Unfortunately we cannot detect the signedness of the operands
10991 for non-subregs. */
10992 comp_mode
= CCUNSmode
;
10994 comp_mode
= CCmode
;
10996 /* First, the compare. */
10997 compare_result
= gen_reg_rtx (comp_mode
);
10999 /* SPE FP compare instructions on the GPRs. Yuck! */
11000 if ((TARGET_E500
&& !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
11001 && rs6000_compare_fp_p
)
11003 rtx cmp
, or_result
, compare_result2
;
11004 enum machine_mode op_mode
= GET_MODE (rs6000_compare_op0
);
11006 if (op_mode
== VOIDmode
)
11007 op_mode
= GET_MODE (rs6000_compare_op1
);
11009 /* Note: The E500 comparison instructions set the GT bit (x +
11010 1), on success. This explains the mess. */
11014 case EQ
: case UNEQ
: case NE
: case LTGT
:
11018 cmp
= flag_unsafe_math_optimizations
11019 ? gen_tstsfeq_gpr (compare_result
, rs6000_compare_op0
,
11020 rs6000_compare_op1
)
11021 : gen_cmpsfeq_gpr (compare_result
, rs6000_compare_op0
,
11022 rs6000_compare_op1
);
11026 cmp
= flag_unsafe_math_optimizations
11027 ? gen_tstdfeq_gpr (compare_result
, rs6000_compare_op0
,
11028 rs6000_compare_op1
)
11029 : gen_cmpdfeq_gpr (compare_result
, rs6000_compare_op0
,
11030 rs6000_compare_op1
);
11034 gcc_unreachable ();
11038 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
11042 cmp
= flag_unsafe_math_optimizations
11043 ? gen_tstsfgt_gpr (compare_result
, rs6000_compare_op0
,
11044 rs6000_compare_op1
)
11045 : gen_cmpsfgt_gpr (compare_result
, rs6000_compare_op0
,
11046 rs6000_compare_op1
);
11050 cmp
= flag_unsafe_math_optimizations
11051 ? gen_tstdfgt_gpr (compare_result
, rs6000_compare_op0
,
11052 rs6000_compare_op1
)
11053 : gen_cmpdfgt_gpr (compare_result
, rs6000_compare_op0
,
11054 rs6000_compare_op1
);
11058 gcc_unreachable ();
11062 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
11066 cmp
= flag_unsafe_math_optimizations
11067 ? gen_tstsflt_gpr (compare_result
, rs6000_compare_op0
,
11068 rs6000_compare_op1
)
11069 : gen_cmpsflt_gpr (compare_result
, rs6000_compare_op0
,
11070 rs6000_compare_op1
);
11074 cmp
= flag_unsafe_math_optimizations
11075 ? gen_tstdflt_gpr (compare_result
, rs6000_compare_op0
,
11076 rs6000_compare_op1
)
11077 : gen_cmpdflt_gpr (compare_result
, rs6000_compare_op0
,
11078 rs6000_compare_op1
);
11082 gcc_unreachable ();
11086 gcc_unreachable ();
11089 /* Synthesize LE and GE from LT/GT || EQ. */
11090 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
11096 case LE
: code
= LT
; break;
11097 case GE
: code
= GT
; break;
11098 case LEU
: code
= LT
; break;
11099 case GEU
: code
= GT
; break;
11100 default: gcc_unreachable ();
11103 compare_result2
= gen_reg_rtx (CCFPmode
);
11109 cmp
= flag_unsafe_math_optimizations
11110 ? gen_tstsfeq_gpr (compare_result2
, rs6000_compare_op0
,
11111 rs6000_compare_op1
)
11112 : gen_cmpsfeq_gpr (compare_result2
, rs6000_compare_op0
,
11113 rs6000_compare_op1
);
11117 cmp
= flag_unsafe_math_optimizations
11118 ? gen_tstdfeq_gpr (compare_result2
, rs6000_compare_op0
,
11119 rs6000_compare_op1
)
11120 : gen_cmpdfeq_gpr (compare_result2
, rs6000_compare_op0
,
11121 rs6000_compare_op1
);
11125 gcc_unreachable ();
11129 /* OR them together. */
11130 or_result
= gen_reg_rtx (CCFPmode
);
11131 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
11133 compare_result
= or_result
;
11138 if (code
== NE
|| code
== LTGT
)
11148 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11149 CLOBBERs to match cmptf_internal2 pattern. */
11150 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
11151 && GET_MODE (rs6000_compare_op0
) == TFmode
11152 && (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
)
11153 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
11154 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
11156 gen_rtx_SET (VOIDmode
,
11158 gen_rtx_COMPARE (comp_mode
,
11159 rs6000_compare_op0
,
11160 rs6000_compare_op1
)),
11161 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11162 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11163 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11164 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11165 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11166 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11167 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11168 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)))));
11169 else if (GET_CODE (rs6000_compare_op1
) == UNSPEC
11170 && XINT (rs6000_compare_op1
, 1) == UNSPEC_SP_TEST
)
11172 rtx op1
= XVECEXP (rs6000_compare_op1
, 0, 0);
11173 comp_mode
= CCEQmode
;
11174 compare_result
= gen_reg_rtx (CCEQmode
);
11176 emit_insn (gen_stack_protect_testdi (compare_result
,
11177 rs6000_compare_op0
, op1
));
11179 emit_insn (gen_stack_protect_testsi (compare_result
,
11180 rs6000_compare_op0
, op1
));
11183 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
11184 gen_rtx_COMPARE (comp_mode
,
11185 rs6000_compare_op0
,
11186 rs6000_compare_op1
)));
11189 /* Some kinds of FP comparisons need an OR operation;
11190 under flag_finite_math_only we don't bother. */
11191 if (rs6000_compare_fp_p
11192 && !flag_finite_math_only
11193 && !(TARGET_HARD_FLOAT
&& TARGET_E500
&& !TARGET_FPRS
)
11194 && (code
== LE
|| code
== GE
11195 || code
== UNEQ
|| code
== LTGT
11196 || code
== UNGT
|| code
== UNLT
))
11198 enum rtx_code or1
, or2
;
11199 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
11200 rtx or_result
= gen_reg_rtx (CCEQmode
);
11204 case LE
: or1
= LT
; or2
= EQ
; break;
11205 case GE
: or1
= GT
; or2
= EQ
; break;
11206 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
11207 case LTGT
: or1
= LT
; or2
= GT
; break;
11208 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
11209 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
11210 default: gcc_unreachable ();
11212 validate_condition_mode (or1
, comp_mode
);
11213 validate_condition_mode (or2
, comp_mode
);
11214 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
11215 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
11216 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
11217 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
11219 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
11221 compare_result
= or_result
;
11225 validate_condition_mode (code
, GET_MODE (compare_result
));
11227 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
11231 /* Emit the RTL for an sCOND pattern. */
11234 rs6000_emit_sCOND (enum rtx_code code
, rtx result
)
11237 enum machine_mode op_mode
;
11238 enum rtx_code cond_code
;
11240 condition_rtx
= rs6000_generate_compare (code
);
11241 cond_code
= GET_CODE (condition_rtx
);
11243 if (TARGET_E500
&& rs6000_compare_fp_p
11244 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
11248 PUT_MODE (condition_rtx
, SImode
);
11249 t
= XEXP (condition_rtx
, 0);
11251 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
11253 if (cond_code
== NE
)
11254 emit_insn (gen_e500_flip_gt_bit (t
, t
));
11256 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
11260 if (cond_code
== NE
11261 || cond_code
== GE
|| cond_code
== LE
11262 || cond_code
== GEU
|| cond_code
== LEU
11263 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
11265 rtx not_result
= gen_reg_rtx (CCEQmode
);
11266 rtx not_op
, rev_cond_rtx
;
11267 enum machine_mode cc_mode
;
11269 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
11271 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
11272 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
11273 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
11274 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
11275 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
11278 op_mode
= GET_MODE (rs6000_compare_op0
);
11279 if (op_mode
== VOIDmode
)
11280 op_mode
= GET_MODE (rs6000_compare_op1
);
11282 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| rs6000_compare_fp_p
))
11284 PUT_MODE (condition_rtx
, DImode
);
11285 convert_move (result
, condition_rtx
, 0);
11289 PUT_MODE (condition_rtx
, SImode
);
11290 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
11294 /* Emit a branch of kind CODE to location LOC. */
11297 rs6000_emit_cbranch (enum rtx_code code
, rtx loc
)
11299 rtx condition_rtx
, loc_ref
;
11301 condition_rtx
= rs6000_generate_compare (code
);
11302 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, loc
);
11303 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
11304 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
11305 loc_ref
, pc_rtx
)));
11308 /* Return the string to output a conditional branch to LABEL, which is
11309 the operand number of the label, or -1 if the branch is really a
11310 conditional return.
11312 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11313 condition code register and its mode specifies what kind of
11314 comparison we made.
11316 REVERSED is nonzero if we should reverse the sense of the comparison.
11318 INSN is the insn. */
11321 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
11323 static char string
[64];
11324 enum rtx_code code
= GET_CODE (op
);
11325 rtx cc_reg
= XEXP (op
, 0);
11326 enum machine_mode mode
= GET_MODE (cc_reg
);
11327 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
11328 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
11329 int really_reversed
= reversed
^ need_longbranch
;
11335 validate_condition_mode (code
, mode
);
11337 /* Work out which way this really branches. We could use
11338 reverse_condition_maybe_unordered here always but this
11339 makes the resulting assembler clearer. */
11340 if (really_reversed
)
11342 /* Reversal of FP compares takes care -- an ordered compare
11343 becomes an unordered compare and vice versa. */
11344 if (mode
== CCFPmode
)
11345 code
= reverse_condition_maybe_unordered (code
);
11347 code
= reverse_condition (code
);
11350 if ((TARGET_E500
&& !TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
11352 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11357 /* Opposite of GT. */
11366 gcc_unreachable ();
11372 /* Not all of these are actually distinct opcodes, but
11373 we distinguish them for clarity of the resulting assembler. */
11374 case NE
: case LTGT
:
11375 ccode
= "ne"; break;
11376 case EQ
: case UNEQ
:
11377 ccode
= "eq"; break;
11379 ccode
= "ge"; break;
11380 case GT
: case GTU
: case UNGT
:
11381 ccode
= "gt"; break;
11383 ccode
= "le"; break;
11384 case LT
: case LTU
: case UNLT
:
11385 ccode
= "lt"; break;
11386 case UNORDERED
: ccode
= "un"; break;
11387 case ORDERED
: ccode
= "nu"; break;
11388 case UNGE
: ccode
= "nl"; break;
11389 case UNLE
: ccode
= "ng"; break;
11391 gcc_unreachable ();
11394 /* Maybe we have a guess as to how likely the branch is.
11395 The old mnemonics don't have a way to specify this information. */
11397 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
11398 if (note
!= NULL_RTX
)
11400 /* PROB is the difference from 50%. */
11401 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
11403 /* Only hint for highly probable/improbable branches on newer
11404 cpus as static prediction overrides processor dynamic
11405 prediction. For older cpus we may as well always hint, but
11406 assume not taken for branches that are very close to 50% as a
11407 mispredicted taken branch is more expensive than a
11408 mispredicted not-taken branch. */
11409 if (rs6000_always_hint
11410 || abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48)
11412 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
11413 && ((prob
> 0) ^ need_longbranch
))
11421 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
11423 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
11425 /* We need to escape any '%' characters in the reg_names string.
11426 Assume they'd only be the first character.... */
11427 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
11429 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
11433 /* If the branch distance was too far, we may have to use an
11434 unconditional branch to go the distance. */
11435 if (need_longbranch
)
11436 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
11438 s
+= sprintf (s
, ",%s", label
);
11444 /* Return the string to flip the GT bit on a CR. */
11446 output_e500_flip_gt_bit (rtx dst
, rtx src
)
11448 static char string
[64];
11451 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
11452 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
11455 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
11456 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
11458 sprintf (string
, "crnot %d,%d", a
, b
);
11462 /* Return insn index for the vector compare instruction for given CODE,
11463 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11467 get_vec_cmp_insn (enum rtx_code code
,
11468 enum machine_mode dest_mode
,
11469 enum machine_mode op_mode
)
11471 if (!TARGET_ALTIVEC
)
11472 return INSN_NOT_AVAILABLE
;
11477 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
11478 return UNSPEC_VCMPEQUB
;
11479 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
11480 return UNSPEC_VCMPEQUH
;
11481 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
11482 return UNSPEC_VCMPEQUW
;
11483 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
11484 return UNSPEC_VCMPEQFP
;
11487 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
11488 return UNSPEC_VCMPGEFP
;
11490 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
11491 return UNSPEC_VCMPGTSB
;
11492 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
11493 return UNSPEC_VCMPGTSH
;
11494 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
11495 return UNSPEC_VCMPGTSW
;
11496 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
11497 return UNSPEC_VCMPGTFP
;
11500 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
11501 return UNSPEC_VCMPGTUB
;
11502 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
11503 return UNSPEC_VCMPGTUH
;
11504 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
11505 return UNSPEC_VCMPGTUW
;
11510 return INSN_NOT_AVAILABLE
;
11513 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11514 DMODE is expected destination mode. If RCODE is not supported,
11515 inverse condition and return in SWAP_SELECT_OPERANDS whether
11516 the operands of a following call to rs6000_emit_vector_select
11517 need to be swapped. */
11520 rs6000_emit_vector_compare (enum rtx_code rcode
,
11522 enum machine_mode dmode
,
11523 bool * swap_select_operands
)
11527 enum machine_mode dest_mode
;
11528 enum machine_mode op_mode
= GET_MODE (op1
);
11530 gcc_assert (TARGET_ALTIVEC
);
11531 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
11533 /* Floating point vector compare instructions uses destination V4SImode.
11534 Move destination to appropriate mode later. */
11535 if (dmode
== V4SFmode
)
11536 dest_mode
= V4SImode
;
11540 mask
= gen_reg_rtx (dest_mode
);
11541 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
11542 *swap_select_operands
= false;
11544 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
11546 bool swap_compare_operands
= false;
11552 swap_compare_operands
= true;
11557 swap_compare_operands
= true;
11562 *swap_select_operands
= true;
11567 swap_compare_operands
= true;
11568 *swap_select_operands
= true;
11573 swap_compare_operands
= true;
11574 *swap_select_operands
= true;
11579 *swap_select_operands
= true;
11584 *swap_select_operands
= true;
11588 gcc_unreachable ();
11591 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
11592 /* You only get two chances. */
11593 gcc_assert (vec_cmp_insn
!= INSN_NOT_AVAILABLE
);
11595 if (swap_compare_operands
)
11604 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
11605 gen_rtx_UNSPEC (dest_mode
,
11606 gen_rtvec (2, op0
, op1
),
11608 if (dmode
!= dest_mode
)
11610 rtx temp
= gen_reg_rtx (dest_mode
);
11611 convert_move (temp
, mask
, 0);
11617 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11618 valid insn doesn exist for given mode. */
11621 get_vsel_insn (enum machine_mode mode
)
11626 return UNSPEC_VSEL4SI
;
11629 return UNSPEC_VSEL4SF
;
11632 return UNSPEC_VSEL8HI
;
11635 return UNSPEC_VSEL16QI
;
11638 return INSN_NOT_AVAILABLE
;
11641 return INSN_NOT_AVAILABLE
;
11644 /* Emit vector select insn where DEST is destination using
11645 operands OP1, OP2 and MASK. */
11648 rs6000_emit_vector_select (rtx dest
, rtx op1
, rtx op2
, rtx mask
)
11651 enum machine_mode dest_mode
= GET_MODE (dest
);
11652 int vsel_insn_index
= get_vsel_insn (GET_MODE (dest
));
11654 temp
= gen_reg_rtx (dest_mode
);
11656 /* For each vector element, select op1 when mask is 1 otherwise
11658 t
= gen_rtx_SET (VOIDmode
, temp
,
11659 gen_rtx_UNSPEC (dest_mode
,
11660 gen_rtvec (3, op2
, op1
, mask
),
11663 emit_move_insn (dest
, temp
);
11667 /* Emit vector conditional expression.
11668 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11669 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11672 rs6000_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
11673 rtx cond
, rtx cc_op0
, rtx cc_op1
)
11675 enum machine_mode dest_mode
= GET_MODE (dest
);
11676 enum rtx_code rcode
= GET_CODE (cond
);
11678 bool swap_select_operands
= false;
11680 if (!TARGET_ALTIVEC
)
11683 /* Get the vector mask for the given relational operations. */
11685 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, dest_mode
,
11686 &swap_select_operands
);
11687 if (swap_select_operands
)
11693 rs6000_emit_vector_select (dest
, op1
, op2
, mask
);
11698 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11699 operands of the last comparison is nonzero/true, FALSE_COND if it
11700 is zero/false. Return 0 if the hardware has no such operation. */
11703 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
11705 enum rtx_code code
= GET_CODE (op
);
11706 rtx op0
= rs6000_compare_op0
;
11707 rtx op1
= rs6000_compare_op1
;
11708 REAL_VALUE_TYPE c1
;
11709 enum machine_mode compare_mode
= GET_MODE (op0
);
11710 enum machine_mode result_mode
= GET_MODE (dest
);
11712 bool is_against_zero
;
11714 /* These modes should always match. */
11715 if (GET_MODE (op1
) != compare_mode
11716 /* In the isel case however, we can use a compare immediate, so
11717 op1 may be a small constant. */
11718 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
11720 if (GET_MODE (true_cond
) != result_mode
)
11722 if (GET_MODE (false_cond
) != result_mode
)
11725 /* First, work out if the hardware can do this at all, or
11726 if it's too slow.... */
11727 if (! rs6000_compare_fp_p
)
11730 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
11733 else if (TARGET_E500
&& TARGET_HARD_FLOAT
&& !TARGET_FPRS
11734 && SCALAR_FLOAT_MODE_P (compare_mode
))
11737 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
11739 /* A floating-point subtract might overflow, underflow, or produce
11740 an inexact result, thus changing the floating-point flags, so it
11741 can't be generated if we care about that. It's safe if one side
11742 of the construct is zero, since then no subtract will be
11744 if (SCALAR_FLOAT_MODE_P (compare_mode
)
11745 && flag_trapping_math
&& ! is_against_zero
)
11748 /* Eliminate half of the comparisons by switching operands, this
11749 makes the remaining code simpler. */
11750 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
11751 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
11753 code
= reverse_condition_maybe_unordered (code
);
11755 true_cond
= false_cond
;
11759 /* UNEQ and LTGT take four instructions for a comparison with zero,
11760 it'll probably be faster to use a branch here too. */
11761 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
11764 if (GET_CODE (op1
) == CONST_DOUBLE
)
11765 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
11767 /* We're going to try to implement comparisons by performing
11768 a subtract, then comparing against zero. Unfortunately,
11769 Inf - Inf is NaN which is not zero, and so if we don't
11770 know that the operand is finite and the comparison
11771 would treat EQ different to UNORDERED, we can't do it. */
11772 if (HONOR_INFINITIES (compare_mode
)
11773 && code
!= GT
&& code
!= UNGE
11774 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
11775 /* Constructs of the form (a OP b ? a : b) are safe. */
11776 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
11777 || (! rtx_equal_p (op0
, true_cond
)
11778 && ! rtx_equal_p (op1
, true_cond
))))
11781 /* At this point we know we can use fsel. */
11783 /* Reduce the comparison to a comparison against zero. */
11784 if (! is_against_zero
)
11786 temp
= gen_reg_rtx (compare_mode
);
11787 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
11788 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
11790 op1
= CONST0_RTX (compare_mode
);
11793 /* If we don't care about NaNs we can reduce some of the comparisons
11794 down to faster ones. */
11795 if (! HONOR_NANS (compare_mode
))
11801 true_cond
= false_cond
;
11814 /* Now, reduce everything down to a GE. */
11821 temp
= gen_reg_rtx (compare_mode
);
11822 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
11827 temp
= gen_reg_rtx (compare_mode
);
11828 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
11833 temp
= gen_reg_rtx (compare_mode
);
11834 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
11835 gen_rtx_NEG (compare_mode
,
11836 gen_rtx_ABS (compare_mode
, op0
))));
11841 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11842 temp
= gen_reg_rtx (result_mode
);
11843 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
11844 gen_rtx_IF_THEN_ELSE (result_mode
,
11845 gen_rtx_GE (VOIDmode
,
11847 true_cond
, false_cond
)));
11848 false_cond
= true_cond
;
11851 temp
= gen_reg_rtx (compare_mode
);
11852 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
11857 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11858 temp
= gen_reg_rtx (result_mode
);
11859 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
11860 gen_rtx_IF_THEN_ELSE (result_mode
,
11861 gen_rtx_GE (VOIDmode
,
11863 true_cond
, false_cond
)));
11864 true_cond
= false_cond
;
11867 temp
= gen_reg_rtx (compare_mode
);
11868 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
11873 gcc_unreachable ();
11876 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
11877 gen_rtx_IF_THEN_ELSE (result_mode
,
11878 gen_rtx_GE (VOIDmode
,
11880 true_cond
, false_cond
)));
11884 /* Same as above, but for ints (isel). */
11887 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
11889 rtx condition_rtx
, cr
;
11891 /* All isel implementations thus far are 32-bits. */
11892 if (GET_MODE (rs6000_compare_op0
) != SImode
)
11895 /* We still have to do the compare, because isel doesn't do a
11896 compare, it just looks at the CRx bits set by a previous compare
11898 condition_rtx
= rs6000_generate_compare (GET_CODE (op
));
11899 cr
= XEXP (condition_rtx
, 0);
11901 if (GET_MODE (cr
) == CCmode
)
11902 emit_insn (gen_isel_signed (dest
, condition_rtx
,
11903 true_cond
, false_cond
, cr
));
11905 emit_insn (gen_isel_unsigned (dest
, condition_rtx
,
11906 true_cond
, false_cond
, cr
));
11912 output_isel (rtx
*operands
)
11914 enum rtx_code code
;
11916 code
= GET_CODE (operands
[1]);
11917 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
11919 PUT_CODE (operands
[1], reverse_condition (code
));
11920 return "isel %0,%3,%2,%j1";
11923 return "isel %0,%2,%3,%j1";
11927 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
11929 enum machine_mode mode
= GET_MODE (op0
);
11933 if (code
== SMAX
|| code
== SMIN
)
11938 if (code
== SMAX
|| code
== UMAX
)
11939 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
11940 op0
, op1
, mode
, 0);
11942 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
11943 op1
, op0
, mode
, 0);
11944 gcc_assert (target
);
11945 if (target
!= dest
)
11946 emit_move_insn (dest
, target
);
11949 /* Emit instructions to perform a load-reserved/store-conditional operation.
11950 The operation performed is an atomic
11951 (set M (CODE:MODE M OP))
11952 If not NULL, BEFORE is atomically set to M before the operation, and
11953 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11954 If SYNC_P then a memory barrier is emitted before the operation.
11955 Either OP or M may be wrapped in a NOT operation. */
11958 rs6000_emit_sync (enum rtx_code code
, enum machine_mode mode
,
11959 rtx m
, rtx op
, rtx before_param
, rtx after_param
,
11962 enum machine_mode used_mode
;
11963 rtx the_op
, set_before
, set_after
, set_atomic
, cc_scratch
, before
, after
;
11966 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
11967 rtx shift
= NULL_RTX
;
11970 emit_insn (gen_memory_barrier ());
11972 if (GET_CODE (m
) == NOT
)
11973 used_m
= XEXP (m
, 0);
11977 /* If this is smaller than SImode, we'll have to use SImode with
11979 if (mode
== QImode
|| mode
== HImode
)
11983 if (MEM_ALIGN (used_m
) >= 32)
11986 if (BYTES_BIG_ENDIAN
)
11987 ishift
= GET_MODE_BITSIZE (SImode
) - GET_MODE_BITSIZE (mode
);
11989 shift
= GEN_INT (ishift
);
11993 rtx addrSI
, aligned_addr
;
11994 int shift_mask
= mode
== QImode
? 0x18 : 0x10;
11996 addrSI
= force_reg (SImode
, gen_lowpart_common (SImode
,
11997 XEXP (used_m
, 0)));
11998 shift
= gen_reg_rtx (SImode
);
12000 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
12001 GEN_INT (shift_mask
)));
12002 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
12004 aligned_addr
= expand_binop (Pmode
, and_optab
,
12006 GEN_INT (-4), NULL_RTX
,
12007 1, OPTAB_LIB_WIDEN
);
12008 used_m
= change_address (used_m
, SImode
, aligned_addr
);
12009 set_mem_align (used_m
, 32);
12010 /* It's safe to keep the old alias set of USED_M, because
12011 the operation is atomic and only affects the original
12013 if (GET_CODE (m
) == NOT
)
12014 m
= gen_rtx_NOT (SImode
, used_m
);
12019 if (GET_CODE (op
) == NOT
)
12021 oldop
= lowpart_subreg (SImode
, XEXP (op
, 0), mode
);
12022 oldop
= gen_rtx_NOT (SImode
, oldop
);
12025 oldop
= lowpart_subreg (SImode
, op
, mode
);
12031 newop
= expand_binop (SImode
, and_optab
,
12032 oldop
, GEN_INT (imask
), NULL_RTX
,
12033 1, OPTAB_LIB_WIDEN
);
12034 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
12038 newop
= expand_binop (SImode
, ior_optab
,
12039 oldop
, GEN_INT (~imask
), NULL_RTX
,
12040 1, OPTAB_LIB_WIDEN
);
12041 emit_insn (gen_rotlsi3 (newop
, newop
, shift
));
12049 newop
= expand_binop (SImode
, and_optab
,
12050 oldop
, GEN_INT (imask
), NULL_RTX
,
12051 1, OPTAB_LIB_WIDEN
);
12052 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
12054 mask
= gen_reg_rtx (SImode
);
12055 emit_move_insn (mask
, GEN_INT (imask
));
12056 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
12059 newop
= gen_rtx_PLUS (SImode
, m
, newop
);
12061 newop
= gen_rtx_MINUS (SImode
, m
, newop
);
12062 newop
= gen_rtx_AND (SImode
, newop
, mask
);
12063 newop
= gen_rtx_IOR (SImode
, newop
,
12064 gen_rtx_AND (SImode
,
12065 gen_rtx_NOT (SImode
, mask
),
12071 gcc_unreachable ();
12074 if (GET_CODE (m
) == NOT
)
12078 mask
= gen_reg_rtx (SImode
);
12079 emit_move_insn (mask
, GEN_INT (imask
));
12080 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
12082 xorm
= gen_rtx_XOR (SImode
, used_m
, mask
);
12083 /* Depending on the value of 'op', the XOR or the operation might
12084 be able to be simplified away. */
12085 newop
= simplify_gen_binary (code
, SImode
, xorm
, newop
);
12088 used_mode
= SImode
;
12089 before
= gen_reg_rtx (used_mode
);
12090 after
= gen_reg_rtx (used_mode
);
12095 before
= before_param
;
12096 after
= after_param
;
12098 if (before
== NULL_RTX
)
12099 before
= gen_reg_rtx (used_mode
);
12100 if (after
== NULL_RTX
)
12101 after
= gen_reg_rtx (used_mode
);
12104 if ((code
== PLUS
|| code
== MINUS
|| GET_CODE (m
) == NOT
)
12105 && used_mode
!= mode
)
12106 the_op
= op
; /* Computed above. */
12107 else if (GET_CODE (op
) == NOT
&& GET_CODE (m
) != NOT
)
12108 the_op
= gen_rtx_fmt_ee (code
, used_mode
, op
, m
);
12110 the_op
= gen_rtx_fmt_ee (code
, used_mode
, m
, op
);
12112 set_after
= gen_rtx_SET (VOIDmode
, after
, the_op
);
12113 set_before
= gen_rtx_SET (VOIDmode
, before
, used_m
);
12114 set_atomic
= gen_rtx_SET (VOIDmode
, used_m
,
12115 gen_rtx_UNSPEC (used_mode
,
12116 gen_rtvec (1, the_op
),
12118 cc_scratch
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
12120 if ((code
== PLUS
|| code
== MINUS
) && used_mode
!= mode
)
12121 vec
= gen_rtvec (5, set_after
, set_before
, set_atomic
, cc_scratch
,
12122 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (SImode
)));
12124 vec
= gen_rtvec (4, set_after
, set_before
, set_atomic
, cc_scratch
);
12125 emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
12127 /* Shift and mask the return values properly. */
12128 if (used_mode
!= mode
&& before_param
)
12130 emit_insn (gen_lshrsi3 (before
, before
, shift
));
12131 convert_move (before_param
, before
, 1);
12134 if (used_mode
!= mode
&& after_param
)
12136 emit_insn (gen_lshrsi3 (after
, after
, shift
));
12137 convert_move (after_param
, after
, 1);
12140 /* The previous sequence will end with a branch that's dependent on
12141 the conditional store, so placing an isync will ensure that no
12142 other instructions (especially, no load or store instructions)
12143 can start before the atomic operation completes. */
12145 emit_insn (gen_isync ());
12148 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12149 COND is true. Mark the jump as unlikely to be taken. */
12152 emit_unlikely_jump (rtx cond
, rtx label
)
12154 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
12157 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
12158 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
12159 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_BR_PROB
, very_unlikely
, NULL_RTX
);
12162 /* A subroutine of the atomic operation splitters. Emit a load-locked
12163 instruction in MODE. */
12166 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
12168 rtx (*fn
) (rtx
, rtx
) = NULL
;
12169 if (mode
== SImode
)
12170 fn
= gen_load_locked_si
;
12171 else if (mode
== DImode
)
12172 fn
= gen_load_locked_di
;
12173 emit_insn (fn (reg
, mem
));
12176 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12177 instruction in MODE. */
12180 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
12182 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
12183 if (mode
== SImode
)
12184 fn
= gen_store_conditional_si
;
12185 else if (mode
== DImode
)
12186 fn
= gen_store_conditional_di
;
12188 /* Emit sync before stwcx. to address PPC405 Erratum. */
12189 if (PPC405_ERRATUM77
)
12190 emit_insn (gen_memory_barrier ());
12192 emit_insn (fn (res
, mem
, val
));
12195 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12196 to perform. MEM is the memory on which to operate. VAL is the second
12197 operand of the binary operator. BEFORE and AFTER are optional locations to
12198 return the value of MEM either before of after the operation. SCRATCH is
12199 a scratch register. */
12202 rs6000_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
12203 rtx before
, rtx after
, rtx scratch
)
12205 enum machine_mode mode
= GET_MODE (mem
);
12206 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
12208 emit_insn (gen_memory_barrier ());
12210 label
= gen_label_rtx ();
12211 emit_label (label
);
12212 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
12214 if (before
== NULL_RTX
)
12216 emit_load_locked (mode
, before
, mem
);
12219 x
= gen_rtx_AND (mode
, gen_rtx_NOT (mode
, before
), val
);
12220 else if (code
== AND
)
12221 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (2, before
, val
), UNSPEC_AND
);
12223 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
12225 if (after
!= NULL_RTX
)
12226 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
12227 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
12229 emit_store_conditional (mode
, cond
, mem
, scratch
);
12231 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
12232 emit_unlikely_jump (x
, label
);
12234 emit_insn (gen_isync ());
12237 /* Expand an atomic compare and swap operation. MEM is the memory on which
12238 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12239 value to be stored. SCRATCH is a scratch GPR. */
12242 rs6000_split_compare_and_swap (rtx retval
, rtx mem
, rtx oldval
, rtx newval
,
12245 enum machine_mode mode
= GET_MODE (mem
);
12246 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
12248 emit_insn (gen_memory_barrier ());
12250 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
12251 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
12252 emit_label (XEXP (label1
, 0));
12254 emit_load_locked (mode
, retval
, mem
);
12256 x
= gen_rtx_COMPARE (CCmode
, retval
, oldval
);
12257 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
12259 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
12260 emit_unlikely_jump (x
, label2
);
12262 emit_move_insn (scratch
, newval
);
12263 emit_store_conditional (mode
, cond
, mem
, scratch
);
12265 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
12266 emit_unlikely_jump (x
, label1
);
12268 emit_insn (gen_isync ());
12269 emit_label (XEXP (label2
, 0));
12272 /* Expand an atomic test and set operation. MEM is the memory on which
12273 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12276 rs6000_split_lock_test_and_set (rtx retval
, rtx mem
, rtx val
, rtx scratch
)
12278 enum machine_mode mode
= GET_MODE (mem
);
12279 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
12281 emit_insn (gen_memory_barrier ());
12283 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
12284 emit_label (XEXP (label
, 0));
12286 emit_load_locked (mode
, retval
, mem
);
12287 emit_move_insn (scratch
, val
);
12288 emit_store_conditional (mode
, cond
, mem
, scratch
);
12290 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
12291 emit_unlikely_jump (x
, label
);
12293 emit_insn (gen_isync ());
12296 /* Emit instructions to move SRC to DST. Called by splitters for
12297 multi-register moves. It will emit at most one instruction for
12298 each register that is accessed; that is, it won't emit li/lis pairs
12299 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12303 rs6000_split_multireg_move (rtx dst
, rtx src
)
12305 /* The register number of the first register being moved. */
12307 /* The mode that is to be moved. */
12308 enum machine_mode mode
;
12309 /* The mode that the move is being done in, and its size. */
12310 enum machine_mode reg_mode
;
12312 /* The number of registers that will be moved. */
12315 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
12316 mode
= GET_MODE (dst
);
12317 nregs
= hard_regno_nregs
[reg
][mode
];
12318 if (FP_REGNO_P (reg
))
12320 else if (ALTIVEC_REGNO_P (reg
))
12321 reg_mode
= V16QImode
;
12323 reg_mode
= word_mode
;
12324 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
12326 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
12328 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
12330 /* Move register range backwards, if we might have destructive
12333 for (i
= nregs
- 1; i
>= 0; i
--)
12334 emit_insn (gen_rtx_SET (VOIDmode
,
12335 simplify_gen_subreg (reg_mode
, dst
, mode
,
12336 i
* reg_mode_size
),
12337 simplify_gen_subreg (reg_mode
, src
, mode
,
12338 i
* reg_mode_size
)));
12344 bool used_update
= false;
12346 if (MEM_P (src
) && INT_REGNO_P (reg
))
12350 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
12351 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
12354 breg
= XEXP (XEXP (src
, 0), 0);
12355 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
12356 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
12357 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
12358 emit_insn (TARGET_32BIT
12359 ? gen_addsi3 (breg
, breg
, delta_rtx
)
12360 : gen_adddi3 (breg
, breg
, delta_rtx
));
12361 src
= replace_equiv_address (src
, breg
);
12363 else if (! offsettable_memref_p (src
))
12366 basereg
= gen_rtx_REG (Pmode
, reg
);
12367 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
12368 src
= replace_equiv_address (src
, basereg
);
12371 breg
= XEXP (src
, 0);
12372 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
12373 breg
= XEXP (breg
, 0);
12375 /* If the base register we are using to address memory is
12376 also a destination reg, then change that register last. */
12378 && REGNO (breg
) >= REGNO (dst
)
12379 && REGNO (breg
) < REGNO (dst
) + nregs
)
12380 j
= REGNO (breg
) - REGNO (dst
);
12383 if (GET_CODE (dst
) == MEM
&& INT_REGNO_P (reg
))
12387 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
12388 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
12391 breg
= XEXP (XEXP (dst
, 0), 0);
12392 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
12393 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
12394 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
12396 /* We have to update the breg before doing the store.
12397 Use store with update, if available. */
12401 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
12402 emit_insn (TARGET_32BIT
12403 ? (TARGET_POWERPC64
12404 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
12405 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
12406 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
12407 used_update
= true;
12410 emit_insn (TARGET_32BIT
12411 ? gen_addsi3 (breg
, breg
, delta_rtx
)
12412 : gen_adddi3 (breg
, breg
, delta_rtx
));
12413 dst
= replace_equiv_address (dst
, breg
);
12416 gcc_assert (offsettable_memref_p (dst
));
12419 for (i
= 0; i
< nregs
; i
++)
12421 /* Calculate index to next subword. */
12426 /* If compiler already emitted move of first word by
12427 store with update, no need to do anything. */
12428 if (j
== 0 && used_update
)
12431 emit_insn (gen_rtx_SET (VOIDmode
,
12432 simplify_gen_subreg (reg_mode
, dst
, mode
,
12433 j
* reg_mode_size
),
12434 simplify_gen_subreg (reg_mode
, src
, mode
,
12435 j
* reg_mode_size
)));
12441 /* This page contains routines that are used to determine what the
12442 function prologue and epilogue code will do and write them out. */
12444 /* Return the first fixed-point register that is required to be
12445 saved. 32 if none. */
12448 first_reg_to_save (void)
12452 /* Find lowest numbered live register. */
12453 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
12454 if (regs_ever_live
[first_reg
]
12455 && (! call_used_regs
[first_reg
]
12456 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
12457 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
12458 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
12459 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
12464 && current_function_uses_pic_offset_table
12465 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
12466 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
12472 /* Similar, for FP regs. */
12475 first_fp_reg_to_save (void)
12479 /* Find lowest numbered live register. */
12480 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
12481 if (regs_ever_live
[first_reg
])
12487 /* Similar, for AltiVec regs. */
12490 first_altivec_reg_to_save (void)
12494 /* Stack frame remains as is unless we are in AltiVec ABI. */
12495 if (! TARGET_ALTIVEC_ABI
)
12496 return LAST_ALTIVEC_REGNO
+ 1;
12498 /* Find lowest numbered live register. */
12499 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
12500 if (regs_ever_live
[i
])
12506 /* Return a 32-bit mask of the AltiVec registers we need to set in
12507 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12508 the 32-bit word is 0. */
12510 static unsigned int
12511 compute_vrsave_mask (void)
12513 unsigned int i
, mask
= 0;
12515 /* First, find out if we use _any_ altivec registers. */
12516 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
12517 if (regs_ever_live
[i
])
12518 mask
|= ALTIVEC_REG_BIT (i
);
12523 /* Next, remove the argument registers from the set. These must
12524 be in the VRSAVE mask set by the caller, so we don't need to add
12525 them in again. More importantly, the mask we compute here is
12526 used to generate CLOBBERs in the set_vrsave insn, and we do not
12527 wish the argument registers to die. */
12528 for (i
= cfun
->args_info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
12529 mask
&= ~ALTIVEC_REG_BIT (i
);
12531 /* Similarly, remove the return value from the set. */
12534 diddle_return_value (is_altivec_return_reg
, &yes
);
12536 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
12542 /* For a very restricted set of circumstances, we can cut down the
12543 size of prologues/epilogues by calling our own save/restore-the-world
12547 compute_save_world_info (rs6000_stack_t
*info_ptr
)
12549 info_ptr
->world_save_p
= 1;
12550 info_ptr
->world_save_p
12551 = (WORLD_SAVE_P (info_ptr
)
12552 && DEFAULT_ABI
== ABI_DARWIN
12553 && ! (current_function_calls_setjmp
&& flag_exceptions
)
12554 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
12555 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
12556 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
12557 && info_ptr
->cr_save_p
);
12559 /* This will not work in conjunction with sibcalls. Make sure there
12560 are none. (This check is expensive, but seldom executed.) */
12561 if (WORLD_SAVE_P (info_ptr
))
12564 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
12565 if ( GET_CODE (insn
) == CALL_INSN
12566 && SIBLING_CALL_P (insn
))
12568 info_ptr
->world_save_p
= 0;
12573 if (WORLD_SAVE_P (info_ptr
))
12575 /* Even if we're not touching VRsave, make sure there's room on the
12576 stack for it, if it looks like we're calling SAVE_WORLD, which
12577 will attempt to save it. */
12578 info_ptr
->vrsave_size
= 4;
12580 /* "Save" the VRsave register too if we're saving the world. */
12581 if (info_ptr
->vrsave_mask
== 0)
12582 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
12584 /* Because the Darwin register save/restore routines only handle
12585 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12587 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
12588 && (info_ptr
->first_altivec_reg_save
12589 >= FIRST_SAVED_ALTIVEC_REGNO
));
12596 is_altivec_return_reg (rtx reg
, void *xyes
)
12598 bool *yes
= (bool *) xyes
;
12599 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
12604 /* Calculate the stack information for the current function. This is
12605 complicated by having two separate calling sequences, the AIX calling
12606 sequence and the V.4 calling sequence.
12608 AIX (and Darwin/Mac OS X) stack frames look like:
12610 SP----> +---------------------------------------+
12611 | back chain to caller | 0 0
12612 +---------------------------------------+
12613 | saved CR | 4 8 (8-11)
12614 +---------------------------------------+
12616 +---------------------------------------+
12617 | reserved for compilers | 12 24
12618 +---------------------------------------+
12619 | reserved for binders | 16 32
12620 +---------------------------------------+
12621 | saved TOC pointer | 20 40
12622 +---------------------------------------+
12623 | Parameter save area (P) | 24 48
12624 +---------------------------------------+
12625 | Alloca space (A) | 24+P etc.
12626 +---------------------------------------+
12627 | Local variable space (L) | 24+P+A
12628 +---------------------------------------+
12629 | Float/int conversion temporary (X) | 24+P+A+L
12630 +---------------------------------------+
12631 | Save area for AltiVec registers (W) | 24+P+A+L+X
12632 +---------------------------------------+
12633 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12634 +---------------------------------------+
12635 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12636 +---------------------------------------+
12637 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12638 +---------------------------------------+
12639 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12640 +---------------------------------------+
12641 old SP->| back chain to caller's caller |
12642 +---------------------------------------+
12644 The required alignment for AIX configurations is two words (i.e., 8
12648 V.4 stack frames look like:
12650 SP----> +---------------------------------------+
12651 | back chain to caller | 0
12652 +---------------------------------------+
12653 | caller's saved LR | 4
12654 +---------------------------------------+
12655 | Parameter save area (P) | 8
12656 +---------------------------------------+
12657 | Alloca space (A) | 8+P
12658 +---------------------------------------+
12659 | Varargs save area (V) | 8+P+A
12660 +---------------------------------------+
12661 | Local variable space (L) | 8+P+A+V
12662 +---------------------------------------+
12663 | Float/int conversion temporary (X) | 8+P+A+V+L
12664 +---------------------------------------+
12665 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12666 +---------------------------------------+
12667 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12668 +---------------------------------------+
12669 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12670 +---------------------------------------+
12671 | SPE: area for 64-bit GP registers |
12672 +---------------------------------------+
12673 | SPE alignment padding |
12674 +---------------------------------------+
12675 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12676 +---------------------------------------+
12677 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12678 +---------------------------------------+
12679 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12680 +---------------------------------------+
12681 old SP->| back chain to caller's caller |
12682 +---------------------------------------+
12684 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12685 given. (But note below and in sysv4.h that we require only 8 and
12686 may round up the size of our stack frame anyways. The historical
12687 reason is early versions of powerpc-linux which didn't properly
12688 align the stack at program startup. A happy side-effect is that
12689 -mno-eabi libraries can be used with -meabi programs.)
12691 The EABI configuration defaults to the V.4 layout. However,
12692 the stack alignment requirements may differ. If -mno-eabi is not
12693 given, the required stack alignment is 8 bytes; if -mno-eabi is
12694 given, the required alignment is 16 bytes. (But see V.4 comment
12697 #ifndef ABI_STACK_BOUNDARY
12698 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12701 static rs6000_stack_t
*
12702 rs6000_stack_info (void)
12704 static rs6000_stack_t info
;
12705 rs6000_stack_t
*info_ptr
= &info
;
12706 int reg_size
= TARGET_32BIT
? 4 : 8;
12709 HOST_WIDE_INT non_fixed_size
;
12711 memset (&info
, 0, sizeof (info
));
12715 /* Cache value so we don't rescan instruction chain over and over. */
12716 if (cfun
->machine
->insn_chain_scanned_p
== 0)
12717 cfun
->machine
->insn_chain_scanned_p
12718 = spe_func_has_64bit_regs_p () + 1;
12719 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
12722 /* Select which calling sequence. */
12723 info_ptr
->abi
= DEFAULT_ABI
;
12725 /* Calculate which registers need to be saved & save area size. */
12726 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
12727 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12728 even if it currently looks like we won't. */
12729 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
12730 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
12731 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
12732 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
12733 info_ptr
->gp_size
= reg_size
* (32 - RS6000_PIC_OFFSET_TABLE_REGNUM
);
12735 info_ptr
->gp_size
= reg_size
* (32 - info_ptr
->first_gp_reg_save
);
12737 /* For the SPE, we have an additional upper 32-bits on each GPR.
12738 Ideally we should save the entire 64-bits only when the upper
12739 half is used in SIMD instructions. Since we only record
12740 registers live (not the size they are used in), this proves
12741 difficult because we'd have to traverse the instruction chain at
12742 the right time, taking reload into account. This is a real pain,
12743 so we opt to save the GPRs in 64-bits always if but one register
12744 gets used in 64-bits. Otherwise, all the registers in the frame
12745 get saved in 32-bits.
12747 So... since when we save all GPRs (except the SP) in 64-bits, the
12748 traditional GP save area will be empty. */
12749 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
12750 info_ptr
->gp_size
= 0;
12752 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
12753 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
12755 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
12756 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
12757 - info_ptr
->first_altivec_reg_save
);
12759 /* Does this function call anything? */
12760 info_ptr
->calls_p
= (! current_function_is_leaf
12761 || cfun
->machine
->ra_needs_full_frame
);
12763 /* Determine if we need to save the link register. */
12764 if ((DEFAULT_ABI
== ABI_AIX
12765 && current_function_profile
12766 && !TARGET_PROFILE_KERNEL
)
12767 #ifdef TARGET_RELOCATABLE
12768 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
12770 || (info_ptr
->first_fp_reg_save
!= 64
12771 && !FP_SAVE_INLINE (info_ptr
->first_fp_reg_save
))
12772 || info_ptr
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
12773 || (DEFAULT_ABI
== ABI_V4
&& current_function_calls_alloca
)
12774 || info_ptr
->calls_p
12775 || rs6000_ra_ever_killed ())
12777 info_ptr
->lr_save_p
= 1;
12778 regs_ever_live
[LINK_REGISTER_REGNUM
] = 1;
12781 /* Determine if we need to save the condition code registers. */
12782 if (regs_ever_live
[CR2_REGNO
]
12783 || regs_ever_live
[CR3_REGNO
]
12784 || regs_ever_live
[CR4_REGNO
])
12786 info_ptr
->cr_save_p
= 1;
12787 if (DEFAULT_ABI
== ABI_V4
)
12788 info_ptr
->cr_size
= reg_size
;
12791 /* If the current function calls __builtin_eh_return, then we need
12792 to allocate stack space for registers that will hold data for
12793 the exception handler. */
12794 if (current_function_calls_eh_return
)
12797 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
12800 /* SPE saves EH registers in 64-bits. */
12801 ehrd_size
= i
* (TARGET_SPE_ABI
12802 && info_ptr
->spe_64bit_regs_used
!= 0
12803 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
12808 /* Determine various sizes. */
12809 info_ptr
->reg_size
= reg_size
;
12810 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
12811 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
12812 info_ptr
->parm_size
= RS6000_ALIGN (current_function_outgoing_args_size
,
12813 TARGET_ALTIVEC
? 16 : 8);
12814 if (FRAME_GROWS_DOWNWARD
)
12815 info_ptr
->vars_size
12816 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
12817 + info_ptr
->parm_size
,
12818 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
12819 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
12820 + info_ptr
->parm_size
);
12822 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
12823 info_ptr
->spe_gp_size
= 8 * (32 - info_ptr
->first_gp_reg_save
);
12825 info_ptr
->spe_gp_size
= 0;
12827 if (TARGET_ALTIVEC_ABI
)
12828 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
12830 info_ptr
->vrsave_mask
= 0;
12832 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
12833 info_ptr
->vrsave_size
= 4;
12835 info_ptr
->vrsave_size
= 0;
12837 compute_save_world_info (info_ptr
);
12839 /* Calculate the offsets. */
12840 switch (DEFAULT_ABI
)
12844 gcc_unreachable ();
12848 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
12849 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
12851 if (TARGET_ALTIVEC_ABI
)
12853 info_ptr
->vrsave_save_offset
12854 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
12856 /* Align stack so vector save area is on a quadword boundary. */
12857 if (info_ptr
->altivec_size
!= 0)
12858 info_ptr
->altivec_padding_size
12859 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
12861 info_ptr
->altivec_padding_size
= 0;
12863 info_ptr
->altivec_save_offset
12864 = info_ptr
->vrsave_save_offset
12865 - info_ptr
->altivec_padding_size
12866 - info_ptr
->altivec_size
;
12868 /* Adjust for AltiVec case. */
12869 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
12872 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
12873 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
12874 info_ptr
->lr_save_offset
= 2*reg_size
;
12878 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
12879 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
12880 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
12882 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
12884 /* Align stack so SPE GPR save area is aligned on a
12885 double-word boundary. */
12886 if (info_ptr
->spe_gp_size
!= 0)
12887 info_ptr
->spe_padding_size
12888 = 8 - (-info_ptr
->cr_save_offset
% 8);
12890 info_ptr
->spe_padding_size
= 0;
12892 info_ptr
->spe_gp_save_offset
12893 = info_ptr
->cr_save_offset
12894 - info_ptr
->spe_padding_size
12895 - info_ptr
->spe_gp_size
;
12897 /* Adjust for SPE case. */
12898 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
12900 else if (TARGET_ALTIVEC_ABI
)
12902 info_ptr
->vrsave_save_offset
12903 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
12905 /* Align stack so vector save area is on a quadword boundary. */
12906 if (info_ptr
->altivec_size
!= 0)
12907 info_ptr
->altivec_padding_size
12908 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
12910 info_ptr
->altivec_padding_size
= 0;
12912 info_ptr
->altivec_save_offset
12913 = info_ptr
->vrsave_save_offset
12914 - info_ptr
->altivec_padding_size
12915 - info_ptr
->altivec_size
;
12917 /* Adjust for AltiVec case. */
12918 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
12921 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
12922 info_ptr
->ehrd_offset
-= ehrd_size
;
12923 info_ptr
->lr_save_offset
= reg_size
;
12927 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
12928 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
12929 + info_ptr
->gp_size
12930 + info_ptr
->altivec_size
12931 + info_ptr
->altivec_padding_size
12932 + info_ptr
->spe_gp_size
12933 + info_ptr
->spe_padding_size
12935 + info_ptr
->cr_size
12936 + info_ptr
->vrsave_size
,
12939 non_fixed_size
= (info_ptr
->vars_size
12940 + info_ptr
->parm_size
12941 + info_ptr
->save_size
);
12943 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
12944 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
12946 /* Determine if we need to allocate any stack frame:
12948 For AIX we need to push the stack if a frame pointer is needed
12949 (because the stack might be dynamically adjusted), if we are
12950 debugging, if we make calls, or if the sum of fp_save, gp_save,
12951 and local variables are more than the space needed to save all
12952 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12953 + 18*8 = 288 (GPR13 reserved).
12955 For V.4 we don't have the stack cushion that AIX uses, but assume
12956 that the debugger can handle stackless frames. */
12958 if (info_ptr
->calls_p
)
12959 info_ptr
->push_p
= 1;
12961 else if (DEFAULT_ABI
== ABI_V4
)
12962 info_ptr
->push_p
= non_fixed_size
!= 0;
12964 else if (frame_pointer_needed
)
12965 info_ptr
->push_p
= 1;
12967 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
12968 info_ptr
->push_p
= 1;
12971 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
12973 /* Zero offsets if we're not saving those registers. */
12974 if (info_ptr
->fp_size
== 0)
12975 info_ptr
->fp_save_offset
= 0;
12977 if (info_ptr
->gp_size
== 0)
12978 info_ptr
->gp_save_offset
= 0;
12980 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
12981 info_ptr
->altivec_save_offset
= 0;
12983 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
12984 info_ptr
->vrsave_save_offset
= 0;
12986 if (! TARGET_SPE_ABI
12987 || info_ptr
->spe_64bit_regs_used
== 0
12988 || info_ptr
->spe_gp_size
== 0)
12989 info_ptr
->spe_gp_save_offset
= 0;
12991 if (! info_ptr
->lr_save_p
)
12992 info_ptr
->lr_save_offset
= 0;
12994 if (! info_ptr
->cr_save_p
)
12995 info_ptr
->cr_save_offset
= 0;
13000 /* Return true if the current function uses any GPRs in 64-bit SIMD
13004 spe_func_has_64bit_regs_p (void)
13008 /* Functions that save and restore all the call-saved registers will
13009 need to save/restore the registers in 64-bits. */
13010 if (current_function_calls_eh_return
13011 || current_function_calls_setjmp
13012 || current_function_has_nonlocal_goto
)
13015 insns
= get_insns ();
13017 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
13023 /* FIXME: This should be implemented with attributes...
13025 (set_attr "spe64" "true")....then,
13026 if (get_spe64(insn)) return true;
13028 It's the only reliable way to do the stuff below. */
13030 i
= PATTERN (insn
);
13031 if (GET_CODE (i
) == SET
)
13033 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
13035 if (SPE_VECTOR_MODE (mode
))
13037 if (TARGET_E500_DOUBLE
&& mode
== DFmode
)
13047 debug_stack_info (rs6000_stack_t
*info
)
13049 const char *abi_string
;
13052 info
= rs6000_stack_info ();
13054 fprintf (stderr
, "\nStack information for function %s:\n",
13055 ((current_function_decl
&& DECL_NAME (current_function_decl
))
13056 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
13061 default: abi_string
= "Unknown"; break;
13062 case ABI_NONE
: abi_string
= "NONE"; break;
13063 case ABI_AIX
: abi_string
= "AIX"; break;
13064 case ABI_DARWIN
: abi_string
= "Darwin"; break;
13065 case ABI_V4
: abi_string
= "V.4"; break;
13068 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
13070 if (TARGET_ALTIVEC_ABI
)
13071 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
13073 if (TARGET_SPE_ABI
)
13074 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
13076 if (info
->first_gp_reg_save
!= 32)
13077 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
13079 if (info
->first_fp_reg_save
!= 64)
13080 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
13082 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
13083 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
13084 info
->first_altivec_reg_save
);
13086 if (info
->lr_save_p
)
13087 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
13089 if (info
->cr_save_p
)
13090 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
13092 if (info
->vrsave_mask
)
13093 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
13096 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
13099 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
13101 if (info
->gp_save_offset
)
13102 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
13104 if (info
->fp_save_offset
)
13105 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
13107 if (info
->altivec_save_offset
)
13108 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
13109 info
->altivec_save_offset
);
13111 if (info
->spe_gp_save_offset
)
13112 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
13113 info
->spe_gp_save_offset
);
13115 if (info
->vrsave_save_offset
)
13116 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
13117 info
->vrsave_save_offset
);
13119 if (info
->lr_save_offset
)
13120 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
13122 if (info
->cr_save_offset
)
13123 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
13125 if (info
->varargs_save_offset
)
13126 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
13128 if (info
->total_size
)
13129 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
13132 if (info
->vars_size
)
13133 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
13136 if (info
->parm_size
)
13137 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
13139 if (info
->fixed_size
)
13140 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
13143 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
13145 if (info
->spe_gp_size
)
13146 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
13149 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
13151 if (info
->altivec_size
)
13152 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
13154 if (info
->vrsave_size
)
13155 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
13157 if (info
->altivec_padding_size
)
13158 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
13159 info
->altivec_padding_size
);
13161 if (info
->spe_padding_size
)
13162 fprintf (stderr
, "\tspe_padding_size = %5d\n",
13163 info
->spe_padding_size
);
13166 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
13168 if (info
->save_size
)
13169 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
13171 if (info
->reg_size
!= 4)
13172 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
13174 fprintf (stderr
, "\n");
13178 rs6000_return_addr (int count
, rtx frame
)
13180 /* Currently we don't optimize very well between prolog and body
13181 code and for PIC code the code can be actually quite bad, so
13182 don't try to be too clever here. */
13183 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
13185 cfun
->machine
->ra_needs_full_frame
= 1;
13192 plus_constant (copy_to_reg
13193 (gen_rtx_MEM (Pmode
,
13194 memory_address (Pmode
, frame
))),
13195 RETURN_ADDRESS_OFFSET
)));
13198 cfun
->machine
->ra_need_lr
= 1;
13199 return get_hard_reg_initial_val (Pmode
, LINK_REGISTER_REGNUM
);
13202 /* Say whether a function is a candidate for sibcall handling or not.
13203 We do not allow indirect calls to be optimized into sibling calls.
13204 Also, we can't do it if there are any vector parameters; there's
13205 nowhere to put the VRsave code so it works; note that functions with
13206 vector parameters are required to have a prototype, so the argument
13207 type info must be available here. (The tail recursion case can work
13208 with vector parameters, but there's no way to distinguish here.) */
13210 rs6000_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
13215 if (TARGET_ALTIVEC_VRSAVE
)
13217 for (type
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
13218 type
; type
= TREE_CHAIN (type
))
13220 if (TREE_CODE (TREE_VALUE (type
)) == VECTOR_TYPE
)
13224 if (DEFAULT_ABI
== ABI_DARWIN
13225 || (*targetm
.binds_local_p
) (decl
))
13227 tree attr_list
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
13229 if (!lookup_attribute ("longcall", attr_list
)
13230 || lookup_attribute ("shortcall", attr_list
))
13237 /* NULL if INSN insn is valid within a low-overhead loop.
13238 Otherwise return why doloop cannot be applied.
13239 PowerPC uses the COUNT register for branch on table instructions. */
13241 static const char *
13242 rs6000_invalid_within_doloop (rtx insn
)
13245 return "Function call in the loop.";
13248 && (GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
13249 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
))
13250 return "Computed branch in the loop.";
13256 rs6000_ra_ever_killed (void)
13262 if (current_function_is_thunk
)
13265 /* regs_ever_live has LR marked as used if any sibcalls are present,
13266 but this should not force saving and restoring in the
13267 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13268 clobbers LR, so that is inappropriate. */
13270 /* Also, the prologue can generate a store into LR that
13271 doesn't really count, like this:
13274 bcl to set PIC register
13278 When we're called from the epilogue, we need to avoid counting
13279 this as a store. */
13281 push_topmost_sequence ();
13282 top
= get_insns ();
13283 pop_topmost_sequence ();
13284 reg
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
13286 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
13292 if (!SIBLING_CALL_P (insn
))
13295 else if (find_regno_note (insn
, REG_INC
, LINK_REGISTER_REGNUM
))
13297 else if (set_of (reg
, insn
) != NULL_RTX
13298 && !prologue_epilogue_contains (insn
))
13305 /* Add a REG_MAYBE_DEAD note to the insn. */
13307 rs6000_maybe_dead (rtx insn
)
13309 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
13314 /* Emit instructions needed to load the TOC register.
13315 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13316 a constant pool; or for SVR4 -fpic. */
13319 rs6000_emit_load_toc_table (int fromprolog
)
13322 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
13324 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
13327 rtx lab
, tmp1
, tmp2
, got
, tempLR
;
13329 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
13330 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13332 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
13334 got
= rs6000_got_sym ();
13335 tmp1
= tmp2
= dest
;
13338 tmp1
= gen_reg_rtx (Pmode
);
13339 tmp2
= gen_reg_rtx (Pmode
);
13341 tempLR
= (fromprolog
13342 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
13343 : gen_reg_rtx (Pmode
));
13344 insn
= emit_insn (gen_load_toc_v4_PIC_1 (tempLR
, lab
));
13346 rs6000_maybe_dead (insn
);
13347 insn
= emit_move_insn (tmp1
, tempLR
);
13349 rs6000_maybe_dead (insn
);
13350 insn
= emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
13352 rs6000_maybe_dead (insn
);
13353 insn
= emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
13355 rs6000_maybe_dead (insn
);
13357 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
13359 rtx tempLR
= (fromprolog
13360 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
13361 : gen_reg_rtx (Pmode
));
13363 insn
= emit_insn (gen_load_toc_v4_pic_si (tempLR
));
13365 rs6000_maybe_dead (insn
);
13366 insn
= emit_move_insn (dest
, tempLR
);
13368 rs6000_maybe_dead (insn
);
13370 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
13373 rtx tempLR
= (fromprolog
13374 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
13375 : gen_reg_rtx (Pmode
));
13376 rtx temp0
= (fromprolog
13377 ? gen_rtx_REG (Pmode
, 0)
13378 : gen_reg_rtx (Pmode
));
13384 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
13385 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13387 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
13388 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13390 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR
,
13392 rs6000_maybe_dead (emit_move_insn (dest
, tempLR
));
13393 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
,
13401 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
13402 emit_insn (gen_load_toc_v4_PIC_1b (tempLR
, tocsym
));
13403 emit_move_insn (dest
, tempLR
);
13404 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
13406 insn
= emit_insn (gen_addsi3 (dest
, temp0
, dest
));
13408 rs6000_maybe_dead (insn
);
13410 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
13412 /* This is for AIX code running in non-PIC ELF32. */
13415 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
13416 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13418 insn
= emit_insn (gen_elf_high (dest
, realsym
));
13420 rs6000_maybe_dead (insn
);
13421 insn
= emit_insn (gen_elf_low (dest
, dest
, realsym
));
13423 rs6000_maybe_dead (insn
);
13427 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
13430 insn
= emit_insn (gen_load_toc_aix_si (dest
));
13432 insn
= emit_insn (gen_load_toc_aix_di (dest
));
13434 rs6000_maybe_dead (insn
);
13438 /* Emit instructions to restore the link register after determining where
13439 its value has been stored. */
13442 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
13444 rs6000_stack_t
*info
= rs6000_stack_info ();
13447 operands
[0] = source
;
13448 operands
[1] = scratch
;
13450 if (info
->lr_save_p
)
13452 rtx frame_rtx
= stack_pointer_rtx
;
13453 HOST_WIDE_INT sp_offset
= 0;
13456 if (frame_pointer_needed
13457 || current_function_calls_alloca
13458 || info
->total_size
> 32767)
13460 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
13461 emit_move_insn (operands
[1], tmp
);
13462 frame_rtx
= operands
[1];
13464 else if (info
->push_p
)
13465 sp_offset
= info
->total_size
;
13467 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
13468 tmp
= gen_frame_mem (Pmode
, tmp
);
13469 emit_move_insn (tmp
, operands
[0]);
13472 emit_move_insn (gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
), operands
[0]);
13475 static GTY(()) int set
= -1;
13478 get_TOC_alias_set (void)
13481 set
= new_alias_set ();
13485 /* This returns nonzero if the current function uses the TOC. This is
13486 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13487 is generated by the ABI_V4 load_toc_* patterns. */
13494 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13497 rtx pat
= PATTERN (insn
);
13500 if (GET_CODE (pat
) == PARALLEL
)
13501 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
13503 rtx sub
= XVECEXP (pat
, 0, i
);
13504 if (GET_CODE (sub
) == USE
)
13506 sub
= XEXP (sub
, 0);
13507 if (GET_CODE (sub
) == UNSPEC
13508 && XINT (sub
, 1) == UNSPEC_TOC
)
13518 create_TOC_reference (rtx symbol
)
13520 return gen_rtx_PLUS (Pmode
,
13521 gen_rtx_REG (Pmode
, TOC_REGISTER
),
13522 gen_rtx_CONST (Pmode
,
13523 gen_rtx_MINUS (Pmode
, symbol
,
13524 gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
))));
13527 /* If _Unwind_* has been called from within the same module,
13528 toc register is not guaranteed to be saved to 40(1) on function
13529 entry. Save it there in that case. */
13532 rs6000_aix_emit_builtin_unwind_init (void)
13535 rtx stack_top
= gen_reg_rtx (Pmode
);
13536 rtx opcode_addr
= gen_reg_rtx (Pmode
);
13537 rtx opcode
= gen_reg_rtx (SImode
);
13538 rtx tocompare
= gen_reg_rtx (SImode
);
13539 rtx no_toc_save_needed
= gen_label_rtx ();
13541 mem
= gen_frame_mem (Pmode
, hard_frame_pointer_rtx
);
13542 emit_move_insn (stack_top
, mem
);
13544 mem
= gen_frame_mem (Pmode
,
13545 gen_rtx_PLUS (Pmode
, stack_top
,
13546 GEN_INT (2 * GET_MODE_SIZE (Pmode
))));
13547 emit_move_insn (opcode_addr
, mem
);
13548 emit_move_insn (opcode
, gen_rtx_MEM (SImode
, opcode_addr
));
13549 emit_move_insn (tocompare
, gen_int_mode (TARGET_32BIT
? 0x80410014
13550 : 0xE8410028, SImode
));
13552 do_compare_rtx_and_jump (opcode
, tocompare
, EQ
, 1,
13553 SImode
, NULL_RTX
, NULL_RTX
,
13554 no_toc_save_needed
);
13556 mem
= gen_frame_mem (Pmode
,
13557 gen_rtx_PLUS (Pmode
, stack_top
,
13558 GEN_INT (5 * GET_MODE_SIZE (Pmode
))));
13559 emit_move_insn (mem
, gen_rtx_REG (Pmode
, 2));
13560 emit_label (no_toc_save_needed
);
13563 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13564 and the change to the stack pointer. */
13567 rs6000_emit_stack_tie (void)
13569 rtx mem
= gen_frame_mem (BLKmode
,
13570 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
13572 emit_insn (gen_stack_tie (mem
));
13575 /* Emit the correct code for allocating stack space, as insns.
13576 If COPY_R12, make sure a copy of the old frame is left in r12.
13577 The generated code may use hard register 0 as a temporary. */
13580 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, int copy_r12
)
13583 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
13584 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
13585 rtx todec
= gen_int_mode (-size
, Pmode
);
13587 if (INTVAL (todec
) != -size
)
13589 warning (0, "stack frame too large");
13590 emit_insn (gen_trap ());
13594 if (current_function_limit_stack
)
13596 if (REG_P (stack_limit_rtx
)
13597 && REGNO (stack_limit_rtx
) > 1
13598 && REGNO (stack_limit_rtx
) <= 31)
13600 emit_insn (TARGET_32BIT
13601 ? gen_addsi3 (tmp_reg
,
13604 : gen_adddi3 (tmp_reg
,
13608 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
13611 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
13613 && DEFAULT_ABI
== ABI_V4
)
13615 rtx toload
= gen_rtx_CONST (VOIDmode
,
13616 gen_rtx_PLUS (Pmode
,
13620 emit_insn (gen_elf_high (tmp_reg
, toload
));
13621 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
13622 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
13626 warning (0, "stack limit expression is not supported");
13629 if (copy_r12
|| ! TARGET_UPDATE
)
13630 emit_move_insn (gen_rtx_REG (Pmode
, 12), stack_reg
);
13636 /* Need a note here so that try_split doesn't get confused. */
13637 if (get_last_insn () == NULL_RTX
)
13638 emit_note (NOTE_INSN_DELETED
);
13639 insn
= emit_move_insn (tmp_reg
, todec
);
13640 try_split (PATTERN (insn
), insn
, 0);
13644 insn
= emit_insn (TARGET_32BIT
13645 ? gen_movsi_update (stack_reg
, stack_reg
,
13647 : gen_movdi_di_update (stack_reg
, stack_reg
,
13648 todec
, stack_reg
));
13652 insn
= emit_insn (TARGET_32BIT
13653 ? gen_addsi3 (stack_reg
, stack_reg
, todec
)
13654 : gen_adddi3 (stack_reg
, stack_reg
, todec
));
13655 emit_move_insn (gen_rtx_MEM (Pmode
, stack_reg
),
13656 gen_rtx_REG (Pmode
, 12));
13659 RTX_FRAME_RELATED_P (insn
) = 1;
13661 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
13662 gen_rtx_SET (VOIDmode
, stack_reg
,
13663 gen_rtx_PLUS (Pmode
, stack_reg
,
13668 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13669 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13670 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13671 deduce these equivalences by itself so it wasn't necessary to hold
13672 its hand so much. */
13675 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
13676 rtx reg2
, rtx rreg
)
13680 /* copy_rtx will not make unique copies of registers, so we need to
13681 ensure we don't have unwanted sharing here. */
13683 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
13686 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
13688 real
= copy_rtx (PATTERN (insn
));
13690 if (reg2
!= NULL_RTX
)
13691 real
= replace_rtx (real
, reg2
, rreg
);
13693 real
= replace_rtx (real
, reg
,
13694 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
13695 STACK_POINTER_REGNUM
),
13698 /* We expect that 'real' is either a SET or a PARALLEL containing
13699 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13700 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13702 if (GET_CODE (real
) == SET
)
13706 temp
= simplify_rtx (SET_SRC (set
));
13708 SET_SRC (set
) = temp
;
13709 temp
= simplify_rtx (SET_DEST (set
));
13711 SET_DEST (set
) = temp
;
13712 if (GET_CODE (SET_DEST (set
)) == MEM
)
13714 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
13716 XEXP (SET_DEST (set
), 0) = temp
;
13723 gcc_assert (GET_CODE (real
) == PARALLEL
);
13724 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
13725 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
13727 rtx set
= XVECEXP (real
, 0, i
);
13729 temp
= simplify_rtx (SET_SRC (set
));
13731 SET_SRC (set
) = temp
;
13732 temp
= simplify_rtx (SET_DEST (set
));
13734 SET_DEST (set
) = temp
;
13735 if (GET_CODE (SET_DEST (set
)) == MEM
)
13737 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
13739 XEXP (SET_DEST (set
), 0) = temp
;
13741 RTX_FRAME_RELATED_P (set
) = 1;
13746 real
= spe_synthesize_frame_save (real
);
13748 RTX_FRAME_RELATED_P (insn
) = 1;
13749 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
13754 /* Given an SPE frame note, return a PARALLEL of SETs with the
13755 original note, plus a synthetic register save. */
13758 spe_synthesize_frame_save (rtx real
)
13760 rtx synth
, offset
, reg
, real2
;
13762 if (GET_CODE (real
) != SET
13763 || GET_MODE (SET_SRC (real
)) != V2SImode
)
13766 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13767 frame related note. The parallel contains a set of the register
13768 being saved, and another set to a synthetic register (n+1200).
13769 This is so we can differentiate between 64-bit and 32-bit saves.
13770 Words cannot describe this nastiness. */
13772 gcc_assert (GET_CODE (SET_DEST (real
)) == MEM
13773 && GET_CODE (XEXP (SET_DEST (real
), 0)) == PLUS
13774 && GET_CODE (SET_SRC (real
)) == REG
);
13777 (set (mem (plus (reg x) (const y)))
13780 (set (mem (plus (reg x) (const y+4)))
13784 real2
= copy_rtx (real
);
13785 PUT_MODE (SET_DEST (real2
), SImode
);
13786 reg
= SET_SRC (real2
);
13787 real2
= replace_rtx (real2
, reg
, gen_rtx_REG (SImode
, REGNO (reg
)));
13788 synth
= copy_rtx (real2
);
13790 if (BYTES_BIG_ENDIAN
)
13792 offset
= XEXP (XEXP (SET_DEST (real2
), 0), 1);
13793 real2
= replace_rtx (real2
, offset
, GEN_INT (INTVAL (offset
) + 4));
13796 reg
= SET_SRC (synth
);
13798 synth
= replace_rtx (synth
, reg
,
13799 gen_rtx_REG (SImode
, REGNO (reg
) + 1200));
13801 offset
= XEXP (XEXP (SET_DEST (synth
), 0), 1);
13802 synth
= replace_rtx (synth
, offset
,
13803 GEN_INT (INTVAL (offset
)
13804 + (BYTES_BIG_ENDIAN
? 0 : 4)));
13806 RTX_FRAME_RELATED_P (synth
) = 1;
13807 RTX_FRAME_RELATED_P (real2
) = 1;
13808 if (BYTES_BIG_ENDIAN
)
13809 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, synth
, real2
));
13811 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, real2
, synth
));
13816 /* Returns an insn that has a vrsave set operation with the
13817 appropriate CLOBBERs. */
13820 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
13823 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
13824 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
13827 = gen_rtx_SET (VOIDmode
,
13829 gen_rtx_UNSPEC_VOLATILE (SImode
,
13830 gen_rtvec (2, reg
, vrsave
),
13831 UNSPECV_SET_VRSAVE
));
13835 /* We need to clobber the registers in the mask so the scheduler
13836 does not move sets to VRSAVE before sets of AltiVec registers.
13838 However, if the function receives nonlocal gotos, reload will set
13839 all call saved registers live. We will end up with:
13841 (set (reg 999) (mem))
13842 (parallel [ (set (reg vrsave) (unspec blah))
13843 (clobber (reg 999))])
13845 The clobber will cause the store into reg 999 to be dead, and
13846 flow will attempt to delete an epilogue insn. In this case, we
13847 need an unspec use/set of the register. */
13849 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
13850 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
13852 if (!epiloguep
|| call_used_regs
[i
])
13853 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
13854 gen_rtx_REG (V4SImode
, i
));
13857 rtx reg
= gen_rtx_REG (V4SImode
, i
);
13860 = gen_rtx_SET (VOIDmode
,
13862 gen_rtx_UNSPEC (V4SImode
,
13863 gen_rtvec (1, reg
), 27));
13867 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
13869 for (i
= 0; i
< nclobs
; ++i
)
13870 XVECEXP (insn
, 0, i
) = clobs
[i
];
13875 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13876 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13879 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
13880 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
13882 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
13883 rtx replacea
, replaceb
;
13885 int_rtx
= GEN_INT (offset
);
13887 /* Some cases that need register indexed addressing. */
13888 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
13889 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
13891 && SPE_VECTOR_MODE (mode
)
13892 && !SPE_CONST_OFFSET_OK (offset
)))
13894 /* Whomever calls us must make sure r11 is available in the
13895 flow path of instructions in the prologue. */
13896 offset_rtx
= gen_rtx_REG (Pmode
, 11);
13897 emit_move_insn (offset_rtx
, int_rtx
);
13899 replacea
= offset_rtx
;
13900 replaceb
= int_rtx
;
13904 offset_rtx
= int_rtx
;
13905 replacea
= NULL_RTX
;
13906 replaceb
= NULL_RTX
;
13909 reg
= gen_rtx_REG (mode
, regno
);
13910 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
13911 mem
= gen_frame_mem (mode
, addr
);
13913 insn
= emit_move_insn (mem
, reg
);
13915 rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
13918 /* Emit an offset memory reference suitable for a frame store, while
13919 converting to a valid addressing mode. */
13922 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
13924 rtx int_rtx
, offset_rtx
;
13926 int_rtx
= GEN_INT (offset
);
13928 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
13929 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
13931 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
13932 emit_move_insn (offset_rtx
, int_rtx
);
13935 offset_rtx
= int_rtx
;
13937 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
13940 /* Look for user-defined global regs. We should not save and restore these,
13941 and cannot use stmw/lmw if there are any in its range. */
13944 no_global_regs_above (int first_greg
)
13947 for (i
= 0; i
< 32 - first_greg
; i
++)
13948 if (global_regs
[first_greg
+ i
])
13953 #ifndef TARGET_FIX_AND_CONTINUE
13954 #define TARGET_FIX_AND_CONTINUE 0
13957 /* Emit function prologue as insns. */
13960 rs6000_emit_prologue (void)
13962 rs6000_stack_t
*info
= rs6000_stack_info ();
13963 enum machine_mode reg_mode
= Pmode
;
13964 int reg_size
= TARGET_32BIT
? 4 : 8;
13965 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
13966 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
13967 rtx frame_reg_rtx
= sp_reg_rtx
;
13968 rtx cr_save_rtx
= NULL_RTX
;
13970 int saving_FPRs_inline
;
13971 int using_store_multiple
;
13972 HOST_WIDE_INT sp_offset
= 0;
13974 if (TARGET_FIX_AND_CONTINUE
)
13976 /* gdb on darwin arranges to forward a function from the old
13977 address by modifying the first 5 instructions of the function
13978 to branch to the overriding function. This is necessary to
13979 permit function pointers that point to the old function to
13980 actually forward to the new function. */
13981 emit_insn (gen_nop ());
13982 emit_insn (gen_nop ());
13983 emit_insn (gen_nop ());
13984 emit_insn (gen_nop ());
13985 emit_insn (gen_nop ());
13988 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
13990 reg_mode
= V2SImode
;
13994 using_store_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
13995 && (!TARGET_SPE_ABI
13996 || info
->spe_64bit_regs_used
== 0)
13997 && info
->first_gp_reg_save
< 31
13998 && no_global_regs_above (info
->first_gp_reg_save
));
13999 saving_FPRs_inline
= (info
->first_fp_reg_save
== 64
14000 || FP_SAVE_INLINE (info
->first_fp_reg_save
)
14001 || current_function_calls_eh_return
14002 || cfun
->machine
->ra_need_lr
);
14004 /* For V.4, update stack before we do any saving and set back pointer. */
14006 && (DEFAULT_ABI
== ABI_V4
14007 || current_function_calls_eh_return
))
14009 if (info
->total_size
< 32767)
14010 sp_offset
= info
->total_size
;
14012 frame_reg_rtx
= frame_ptr_rtx
;
14013 rs6000_emit_allocate_stack (info
->total_size
,
14014 (frame_reg_rtx
!= sp_reg_rtx
14015 && (info
->cr_save_p
14017 || info
->first_fp_reg_save
< 64
14018 || info
->first_gp_reg_save
< 32
14020 if (frame_reg_rtx
!= sp_reg_rtx
)
14021 rs6000_emit_stack_tie ();
14024 /* Handle world saves specially here. */
14025 if (WORLD_SAVE_P (info
))
14031 /* save_world expects lr in r0. */
14032 if (info
->lr_save_p
)
14034 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
14035 gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
));
14036 RTX_FRAME_RELATED_P (insn
) = 1;
14039 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14040 assumptions about the offsets of various bits of the stack
14042 gcc_assert (info
->gp_save_offset
== -220
14043 && info
->fp_save_offset
== -144
14044 && info
->lr_save_offset
== 8
14045 && info
->cr_save_offset
== 4
14048 && (!current_function_calls_eh_return
14049 || info
->ehrd_offset
== -432)
14050 && info
->vrsave_save_offset
== -224
14051 && info
->altivec_save_offset
== (-224 -16 -192));
14053 treg
= gen_rtx_REG (SImode
, 11);
14054 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
14056 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14057 in R11. It also clobbers R12, so beware! */
14059 /* Preserve CR2 for save_world prologues */
14061 sz
+= 32 - info
->first_gp_reg_save
;
14062 sz
+= 64 - info
->first_fp_reg_save
;
14063 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
14064 p
= rtvec_alloc (sz
);
14066 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
14067 gen_rtx_REG (Pmode
,
14068 LINK_REGISTER_REGNUM
));
14069 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
14070 gen_rtx_SYMBOL_REF (Pmode
,
14072 /* We do floats first so that the instruction pattern matches
14074 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14076 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
14077 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14078 GEN_INT (info
->fp_save_offset
14079 + sp_offset
+ 8 * i
));
14080 rtx mem
= gen_frame_mem (DFmode
, addr
);
14082 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14084 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
14086 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
14087 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14088 GEN_INT (info
->altivec_save_offset
14089 + sp_offset
+ 16 * i
));
14090 rtx mem
= gen_frame_mem (V4SImode
, addr
);
14092 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14094 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14096 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14097 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14098 GEN_INT (info
->gp_save_offset
14099 + sp_offset
+ reg_size
* i
));
14100 rtx mem
= gen_frame_mem (reg_mode
, addr
);
14102 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14106 /* CR register traditionally saved as CR2. */
14107 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
14108 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14109 GEN_INT (info
->cr_save_offset
14111 rtx mem
= gen_frame_mem (reg_mode
, addr
);
14113 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14115 /* Prevent any attempt to delete the setting of r0 and treg! */
14116 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
14117 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
, treg
);
14118 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
, sp_reg_rtx
);
14120 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14121 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14122 NULL_RTX
, NULL_RTX
);
14124 if (current_function_calls_eh_return
)
14129 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
14130 if (regno
== INVALID_REGNUM
)
14132 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
14133 info
->ehrd_offset
+ sp_offset
14134 + reg_size
* (int) i
,
14140 /* Save AltiVec registers if needed. */
14141 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
14145 /* There should be a non inline version of this, for when we
14146 are saving lots of vector registers. */
14147 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14148 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
14150 rtx areg
, savereg
, mem
;
14153 offset
= info
->altivec_save_offset
+ sp_offset
14154 + 16 * (i
- info
->first_altivec_reg_save
);
14156 savereg
= gen_rtx_REG (V4SImode
, i
);
14158 areg
= gen_rtx_REG (Pmode
, 0);
14159 emit_move_insn (areg
, GEN_INT (offset
));
14161 /* AltiVec addressing mode is [reg+reg]. */
14162 mem
= gen_frame_mem (V4SImode
,
14163 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
14165 insn
= emit_move_insn (mem
, savereg
);
14167 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14168 areg
, GEN_INT (offset
));
14172 /* VRSAVE is a bit vector representing which AltiVec registers
14173 are used. The OS uses this to determine which vector
14174 registers to save on a context switch. We need to save
14175 VRSAVE on the stack frame, add whatever AltiVec registers we
14176 used in this function, and do the corresponding magic in the
14179 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
14180 && info
->vrsave_mask
!= 0)
14182 rtx reg
, mem
, vrsave
;
14185 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14186 as frame_reg_rtx and r11 as the static chain pointer for
14187 nested functions. */
14188 reg
= gen_rtx_REG (SImode
, 0);
14189 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
14191 emit_insn (gen_get_vrsave_internal (reg
));
14193 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
14195 if (!WORLD_SAVE_P (info
))
14198 offset
= info
->vrsave_save_offset
+ sp_offset
;
14199 mem
= gen_frame_mem (SImode
,
14200 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14201 GEN_INT (offset
)));
14202 insn
= emit_move_insn (mem
, reg
);
14205 /* Include the registers in the mask. */
14206 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
14208 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
14211 /* If we use the link register, get it into r0. */
14212 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
14214 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
14215 gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
));
14216 RTX_FRAME_RELATED_P (insn
) = 1;
14219 /* If we need to save CR, put it into r12. */
14220 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
14224 cr_save_rtx
= gen_rtx_REG (SImode
, 12);
14225 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
14226 RTX_FRAME_RELATED_P (insn
) = 1;
14227 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14228 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14229 But that's OK. All we have to do is specify that _one_ condition
14230 code register is saved in this stack slot. The thrower's epilogue
14231 will then restore all the call-saved registers.
14232 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14233 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
14234 gen_rtx_REG (SImode
, CR2_REGNO
));
14235 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
14240 /* Do any required saving of fpr's. If only one or two to save, do
14241 it ourselves. Otherwise, call function. */
14242 if (!WORLD_SAVE_P (info
) && saving_FPRs_inline
)
14245 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14246 if ((regs_ever_live
[info
->first_fp_reg_save
+i
]
14247 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
14248 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, DFmode
,
14249 info
->first_fp_reg_save
+ i
,
14250 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
14253 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
14257 const char *alloc_rname
;
14259 p
= rtvec_alloc (2 + 64 - info
->first_fp_reg_save
);
14261 RTVEC_ELT (p
, 0) = gen_rtx_CLOBBER (VOIDmode
,
14262 gen_rtx_REG (Pmode
,
14263 LINK_REGISTER_REGNUM
));
14264 sprintf (rname
, "%s%d%s", SAVE_FP_PREFIX
,
14265 info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
);
14266 alloc_rname
= ggc_strdup (rname
);
14267 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
14268 gen_rtx_SYMBOL_REF (Pmode
,
14270 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14272 rtx addr
, reg
, mem
;
14273 reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
14274 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14275 GEN_INT (info
->fp_save_offset
14276 + sp_offset
+ 8*i
));
14277 mem
= gen_frame_mem (DFmode
, addr
);
14279 RTVEC_ELT (p
, i
+ 2) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14281 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14282 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14283 NULL_RTX
, NULL_RTX
);
14286 /* Save GPRs. This is done as a PARALLEL if we are using
14287 the store-multiple instructions. */
14288 if (!WORLD_SAVE_P (info
) && using_store_multiple
)
14292 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
14293 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14295 rtx addr
, reg
, mem
;
14296 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14297 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14298 GEN_INT (info
->gp_save_offset
14301 mem
= gen_frame_mem (reg_mode
, addr
);
14303 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14305 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14306 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14307 NULL_RTX
, NULL_RTX
);
14309 else if (!WORLD_SAVE_P (info
))
14312 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14313 if ((regs_ever_live
[info
->first_gp_reg_save
+ i
]
14314 && (!call_used_regs
[info
->first_gp_reg_save
+ i
]
14315 || (i
+ info
->first_gp_reg_save
14316 == RS6000_PIC_OFFSET_TABLE_REGNUM
14317 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
14318 || (i
+ info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
14319 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
14320 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))))
14322 rtx addr
, reg
, mem
;
14323 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14325 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
14327 int offset
= info
->spe_gp_save_offset
+ sp_offset
+ 8 * i
;
14330 if (!SPE_CONST_OFFSET_OK (offset
))
14332 b
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
14333 emit_move_insn (b
, GEN_INT (offset
));
14336 b
= GEN_INT (offset
);
14338 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, b
);
14339 mem
= gen_frame_mem (V2SImode
, addr
);
14340 insn
= emit_move_insn (mem
, reg
);
14342 if (GET_CODE (b
) == CONST_INT
)
14343 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14344 NULL_RTX
, NULL_RTX
);
14346 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14347 b
, GEN_INT (offset
));
14351 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14352 GEN_INT (info
->gp_save_offset
14355 mem
= gen_frame_mem (reg_mode
, addr
);
14357 insn
= emit_move_insn (mem
, reg
);
14358 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14359 NULL_RTX
, NULL_RTX
);
14364 /* ??? There's no need to emit actual instructions here, but it's the
14365 easiest way to get the frame unwind information emitted. */
14366 if (!WORLD_SAVE_P (info
) && current_function_calls_eh_return
)
14368 unsigned int i
, regno
;
14370 /* In AIX ABI we need to pretend we save r2 here. */
14373 rtx addr
, reg
, mem
;
14375 reg
= gen_rtx_REG (reg_mode
, 2);
14376 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14377 GEN_INT (sp_offset
+ 5 * reg_size
));
14378 mem
= gen_frame_mem (reg_mode
, addr
);
14380 insn
= emit_move_insn (mem
, reg
);
14381 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14382 NULL_RTX
, NULL_RTX
);
14383 PATTERN (insn
) = gen_blockage ();
14388 regno
= EH_RETURN_DATA_REGNO (i
);
14389 if (regno
== INVALID_REGNUM
)
14392 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
14393 info
->ehrd_offset
+ sp_offset
14394 + reg_size
* (int) i
,
14399 /* Save lr if we used it. */
14400 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
14402 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14403 GEN_INT (info
->lr_save_offset
+ sp_offset
));
14404 rtx reg
= gen_rtx_REG (Pmode
, 0);
14405 rtx mem
= gen_rtx_MEM (Pmode
, addr
);
14406 /* This should not be of frame_alias_set, because of
14407 __builtin_return_address. */
14409 insn
= emit_move_insn (mem
, reg
);
14410 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14411 NULL_RTX
, NULL_RTX
);
14414 /* Save CR if we use any that must be preserved. */
14415 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
14417 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14418 GEN_INT (info
->cr_save_offset
+ sp_offset
));
14419 rtx mem
= gen_frame_mem (SImode
, addr
);
14420 /* See the large comment above about why CR2_REGNO is used. */
14421 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
14423 /* If r12 was used to hold the original sp, copy cr into r0 now
14425 if (REGNO (frame_reg_rtx
) == 12)
14429 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
14430 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
14431 RTX_FRAME_RELATED_P (insn
) = 1;
14432 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
14433 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
14438 insn
= emit_move_insn (mem
, cr_save_rtx
);
14440 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14441 NULL_RTX
, NULL_RTX
);
14444 /* Update stack and set back pointer unless this is V.4,
14445 for which it was done previously. */
14446 if (!WORLD_SAVE_P (info
) && info
->push_p
14447 && !(DEFAULT_ABI
== ABI_V4
|| current_function_calls_eh_return
))
14448 rs6000_emit_allocate_stack (info
->total_size
, FALSE
);
14450 /* Set frame pointer, if needed. */
14451 if (frame_pointer_needed
)
14453 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
14455 RTX_FRAME_RELATED_P (insn
) = 1;
14458 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14459 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
14460 || (DEFAULT_ABI
== ABI_V4
14461 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
14462 && regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
]))
14464 /* If emit_load_toc_table will use the link register, we need to save
14465 it. We use R12 for this purpose because emit_load_toc_table
14466 can use register 0. This allows us to use a plain 'blr' to return
14467 from the procedure more often. */
14468 int save_LR_around_toc_setup
= (TARGET_ELF
14469 && DEFAULT_ABI
!= ABI_AIX
14471 && ! info
->lr_save_p
14472 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
14473 if (save_LR_around_toc_setup
)
14475 rtx lr
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
14477 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
14478 rs6000_maybe_dead (insn
);
14479 RTX_FRAME_RELATED_P (insn
) = 1;
14481 rs6000_emit_load_toc_table (TRUE
);
14483 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
14484 rs6000_maybe_dead (insn
);
14485 RTX_FRAME_RELATED_P (insn
) = 1;
14488 rs6000_emit_load_toc_table (TRUE
);
14492 if (DEFAULT_ABI
== ABI_DARWIN
14493 && flag_pic
&& current_function_uses_pic_offset_table
)
14495 rtx lr
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
14496 rtx src
= machopic_function_base_sym ();
14498 /* Save and restore LR locally around this call (in R0). */
14499 if (!info
->lr_save_p
)
14500 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
));
14502 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr
, src
)));
14504 insn
= emit_move_insn (gen_rtx_REG (Pmode
,
14505 RS6000_PIC_OFFSET_TABLE_REGNUM
),
14507 rs6000_maybe_dead (insn
);
14509 if (!info
->lr_save_p
)
14510 rs6000_maybe_dead (emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0)));
14515 /* Write function prologue. */
14518 rs6000_output_function_prologue (FILE *file
,
14519 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
14521 rs6000_stack_t
*info
= rs6000_stack_info ();
14523 if (TARGET_DEBUG_STACK
)
14524 debug_stack_info (info
);
14526 /* Write .extern for any function we will call to save and restore
14528 if (info
->first_fp_reg_save
< 64
14529 && !FP_SAVE_INLINE (info
->first_fp_reg_save
))
14530 fprintf (file
, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14531 SAVE_FP_PREFIX
, info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
,
14532 RESTORE_FP_PREFIX
, info
->first_fp_reg_save
- 32,
14533 RESTORE_FP_SUFFIX
);
14535 /* Write .extern for AIX common mode routines, if needed. */
14536 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
14538 fputs ("\t.extern __mulh\n", file
);
14539 fputs ("\t.extern __mull\n", file
);
14540 fputs ("\t.extern __divss\n", file
);
14541 fputs ("\t.extern __divus\n", file
);
14542 fputs ("\t.extern __quoss\n", file
);
14543 fputs ("\t.extern __quous\n", file
);
14544 common_mode_defined
= 1;
14547 if (! HAVE_prologue
)
14551 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14552 the "toplevel" insn chain. */
14553 emit_note (NOTE_INSN_DELETED
);
14554 rs6000_emit_prologue ();
14555 emit_note (NOTE_INSN_DELETED
);
14557 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14561 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
14563 INSN_ADDRESSES_NEW (insn
, addr
);
14568 if (TARGET_DEBUG_STACK
)
14569 debug_rtx_list (get_insns (), 100);
14570 final (get_insns (), file
, FALSE
);
14574 rs6000_pic_labelno
++;
14577 /* Emit function epilogue as insns.
14579 At present, dwarf2out_frame_debug_expr doesn't understand
14580 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14581 anywhere in the epilogue. Most of the insns below would in any case
14582 need special notes to explain where r11 is in relation to the stack. */
14585 rs6000_emit_epilogue (int sibcall
)
14587 rs6000_stack_t
*info
;
14588 int restoring_FPRs_inline
;
14589 int using_load_multiple
;
14590 int using_mfcr_multiple
;
14591 int use_backchain_to_restore_sp
;
14593 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
14594 rtx frame_reg_rtx
= sp_reg_rtx
;
14595 enum machine_mode reg_mode
= Pmode
;
14596 int reg_size
= TARGET_32BIT
? 4 : 8;
14599 info
= rs6000_stack_info ();
14601 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
14603 reg_mode
= V2SImode
;
14607 using_load_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
14608 && (!TARGET_SPE_ABI
14609 || info
->spe_64bit_regs_used
== 0)
14610 && info
->first_gp_reg_save
< 31
14611 && no_global_regs_above (info
->first_gp_reg_save
));
14612 restoring_FPRs_inline
= (sibcall
14613 || current_function_calls_eh_return
14614 || info
->first_fp_reg_save
== 64
14615 || FP_SAVE_INLINE (info
->first_fp_reg_save
));
14616 use_backchain_to_restore_sp
= (frame_pointer_needed
14617 || current_function_calls_alloca
14618 || info
->total_size
> 32767);
14619 using_mfcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
14620 || rs6000_cpu
== PROCESSOR_PPC603
14621 || rs6000_cpu
== PROCESSOR_PPC750
14624 if (WORLD_SAVE_P (info
))
14628 const char *alloc_rname
;
14631 /* eh_rest_world_r10 will return to the location saved in the LR
14632 stack slot (which is not likely to be our caller.)
14633 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14634 rest_world is similar, except any R10 parameter is ignored.
14635 The exception-handling stuff that was here in 2.95 is no
14636 longer necessary. */
14640 + 32 - info
->first_gp_reg_save
14641 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
14642 + 63 + 1 - info
->first_fp_reg_save
);
14644 strcpy (rname
, ((current_function_calls_eh_return
) ?
14645 "*eh_rest_world_r10" : "*rest_world"));
14646 alloc_rname
= ggc_strdup (rname
);
14649 RTVEC_ELT (p
, j
++) = gen_rtx_RETURN (VOIDmode
);
14650 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
14651 gen_rtx_REG (Pmode
,
14652 LINK_REGISTER_REGNUM
));
14654 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
14655 /* The instruction pattern requires a clobber here;
14656 it is shared with the restVEC helper. */
14658 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
14661 /* CR register traditionally saved as CR2. */
14662 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
14663 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14664 GEN_INT (info
->cr_save_offset
));
14665 rtx mem
= gen_frame_mem (reg_mode
, addr
);
14667 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14670 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14672 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14673 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14674 GEN_INT (info
->gp_save_offset
14676 rtx mem
= gen_frame_mem (reg_mode
, addr
);
14678 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14680 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
14682 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
14683 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14684 GEN_INT (info
->altivec_save_offset
14686 rtx mem
= gen_frame_mem (V4SImode
, addr
);
14688 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14690 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
14692 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
14693 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14694 GEN_INT (info
->fp_save_offset
14696 rtx mem
= gen_frame_mem (DFmode
, addr
);
14698 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14701 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
14703 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
14705 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
14707 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
14709 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
14710 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14715 /* If we have a frame pointer, a call to alloca, or a large stack
14716 frame, restore the old stack pointer using the backchain. Otherwise,
14717 we know what size to update it with. */
14718 if (use_backchain_to_restore_sp
)
14720 /* Under V.4, don't reset the stack pointer until after we're done
14721 loading the saved registers. */
14722 if (DEFAULT_ABI
== ABI_V4
)
14723 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
14725 emit_move_insn (frame_reg_rtx
,
14726 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
14728 else if (info
->push_p
)
14730 if (DEFAULT_ABI
== ABI_V4
14731 || current_function_calls_eh_return
)
14732 sp_offset
= info
->total_size
;
14735 emit_insn (TARGET_32BIT
14736 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
14737 GEN_INT (info
->total_size
))
14738 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
14739 GEN_INT (info
->total_size
)));
14743 /* Restore AltiVec registers if needed. */
14744 if (TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
14748 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14749 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
14751 rtx addr
, areg
, mem
;
14753 areg
= gen_rtx_REG (Pmode
, 0);
14755 (areg
, GEN_INT (info
->altivec_save_offset
14757 + 16 * (i
- info
->first_altivec_reg_save
)));
14759 /* AltiVec addressing mode is [reg+reg]. */
14760 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
14761 mem
= gen_frame_mem (V4SImode
, addr
);
14763 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
14767 /* Restore VRSAVE if needed. */
14768 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
14769 && info
->vrsave_mask
!= 0)
14771 rtx addr
, mem
, reg
;
14773 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14774 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
14775 mem
= gen_frame_mem (SImode
, addr
);
14776 reg
= gen_rtx_REG (SImode
, 12);
14777 emit_move_insn (reg
, mem
);
14779 emit_insn (generate_set_vrsave (reg
, info
, 1));
14782 /* Get the old lr if we saved it. */
14783 if (info
->lr_save_p
)
14785 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
14786 info
->lr_save_offset
+ sp_offset
);
14788 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
14791 /* Get the old cr if we saved it. */
14792 if (info
->cr_save_p
)
14794 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14795 GEN_INT (info
->cr_save_offset
+ sp_offset
));
14796 rtx mem
= gen_frame_mem (SImode
, addr
);
14798 emit_move_insn (gen_rtx_REG (SImode
, 12), mem
);
14801 /* Set LR here to try to overlap restores below. */
14802 if (info
->lr_save_p
)
14803 emit_move_insn (gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
),
14804 gen_rtx_REG (Pmode
, 0));
14806 /* Load exception handler data registers, if needed. */
14807 if (current_function_calls_eh_return
)
14809 unsigned int i
, regno
;
14813 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14814 GEN_INT (sp_offset
+ 5 * reg_size
));
14815 rtx mem
= gen_frame_mem (reg_mode
, addr
);
14817 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
14824 regno
= EH_RETURN_DATA_REGNO (i
);
14825 if (regno
== INVALID_REGNUM
)
14828 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
14829 info
->ehrd_offset
+ sp_offset
14830 + reg_size
* (int) i
);
14832 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
14836 /* Restore GPRs. This is done as a PARALLEL if we are using
14837 the load-multiple instructions. */
14838 if (using_load_multiple
)
14841 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
14842 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14844 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14845 GEN_INT (info
->gp_save_offset
14848 rtx mem
= gen_frame_mem (reg_mode
, addr
);
14851 gen_rtx_SET (VOIDmode
,
14852 gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
14855 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14858 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14859 if ((regs_ever_live
[info
->first_gp_reg_save
+ i
]
14860 && (!call_used_regs
[info
->first_gp_reg_save
+ i
]
14861 || (i
+ info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
14862 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
14863 || (i
+ info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
14864 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
14865 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))))
14867 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14868 GEN_INT (info
->gp_save_offset
14871 rtx mem
= gen_frame_mem (reg_mode
, addr
);
14873 /* Restore 64-bit quantities for SPE. */
14874 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
14876 int offset
= info
->spe_gp_save_offset
+ sp_offset
+ 8 * i
;
14879 if (!SPE_CONST_OFFSET_OK (offset
))
14881 b
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
14882 emit_move_insn (b
, GEN_INT (offset
));
14885 b
= GEN_INT (offset
);
14887 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, b
);
14888 mem
= gen_frame_mem (V2SImode
, addr
);
14891 emit_move_insn (gen_rtx_REG (reg_mode
,
14892 info
->first_gp_reg_save
+ i
), mem
);
14895 /* Restore fpr's if we need to do it without calling a function. */
14896 if (restoring_FPRs_inline
)
14897 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14898 if ((regs_ever_live
[info
->first_fp_reg_save
+i
]
14899 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
14902 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14903 GEN_INT (info
->fp_save_offset
14906 mem
= gen_frame_mem (DFmode
, addr
);
14908 emit_move_insn (gen_rtx_REG (DFmode
,
14909 info
->first_fp_reg_save
+ i
),
14913 /* If we saved cr, restore it here. Just those that were used. */
14914 if (info
->cr_save_p
)
14916 rtx r12_rtx
= gen_rtx_REG (SImode
, 12);
14919 if (using_mfcr_multiple
)
14921 for (i
= 0; i
< 8; i
++)
14922 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
14924 gcc_assert (count
);
14927 if (using_mfcr_multiple
&& count
> 1)
14932 p
= rtvec_alloc (count
);
14935 for (i
= 0; i
< 8; i
++)
14936 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
14938 rtvec r
= rtvec_alloc (2);
14939 RTVEC_ELT (r
, 0) = r12_rtx
;
14940 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
14941 RTVEC_ELT (p
, ndx
) =
14942 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
14943 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
14946 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14947 gcc_assert (ndx
== count
);
14950 for (i
= 0; i
< 8; i
++)
14951 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
14953 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
14959 /* If this is V.4, unwind the stack pointer after all of the loads
14961 if (frame_reg_rtx
!= sp_reg_rtx
)
14963 /* This blockage is needed so that sched doesn't decide to move
14964 the sp change before the register restores. */
14965 rs6000_emit_stack_tie ();
14966 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
14968 else if (sp_offset
!= 0)
14969 emit_insn (TARGET_32BIT
14970 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
14971 GEN_INT (sp_offset
))
14972 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
14973 GEN_INT (sp_offset
)));
14975 if (current_function_calls_eh_return
)
14977 rtx sa
= EH_RETURN_STACKADJ_RTX
;
14978 emit_insn (TARGET_32BIT
14979 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
, sa
)
14980 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
, sa
));
14986 if (! restoring_FPRs_inline
)
14987 p
= rtvec_alloc (3 + 64 - info
->first_fp_reg_save
);
14989 p
= rtvec_alloc (2);
14991 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
14992 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
14993 gen_rtx_REG (Pmode
,
14994 LINK_REGISTER_REGNUM
));
14996 /* If we have to restore more than two FP registers, branch to the
14997 restore function. It will return to our caller. */
14998 if (! restoring_FPRs_inline
)
15002 const char *alloc_rname
;
15004 sprintf (rname
, "%s%d%s", RESTORE_FP_PREFIX
,
15005 info
->first_fp_reg_save
- 32, RESTORE_FP_SUFFIX
);
15006 alloc_rname
= ggc_strdup (rname
);
15007 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
,
15008 gen_rtx_SYMBOL_REF (Pmode
,
15011 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
15014 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
15015 GEN_INT (info
->fp_save_offset
+ 8*i
));
15016 mem
= gen_frame_mem (DFmode
, addr
);
15018 RTVEC_ELT (p
, i
+3) =
15019 gen_rtx_SET (VOIDmode
,
15020 gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
),
15025 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
15029 /* Write function epilogue. */
15032 rs6000_output_function_epilogue (FILE *file
,
15033 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
15035 rs6000_stack_t
*info
= rs6000_stack_info ();
15037 if (! HAVE_epilogue
)
15039 rtx insn
= get_last_insn ();
15040 /* If the last insn was a BARRIER, we don't have to write anything except
15041 the trace table. */
15042 if (GET_CODE (insn
) == NOTE
)
15043 insn
= prev_nonnote_insn (insn
);
15044 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
15046 /* This is slightly ugly, but at least we don't have two
15047 copies of the epilogue-emitting code. */
15050 /* A NOTE_INSN_DELETED is supposed to be at the start
15051 and end of the "toplevel" insn chain. */
15052 emit_note (NOTE_INSN_DELETED
);
15053 rs6000_emit_epilogue (FALSE
);
15054 emit_note (NOTE_INSN_DELETED
);
15056 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15060 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
15062 INSN_ADDRESSES_NEW (insn
, addr
);
15067 if (TARGET_DEBUG_STACK
)
15068 debug_rtx_list (get_insns (), 100);
15069 final (get_insns (), file
, FALSE
);
15075 macho_branch_islands ();
15076 /* Mach-O doesn't support labels at the end of objects, so if
15077 it looks like we might want one, insert a NOP. */
15079 rtx insn
= get_last_insn ();
15082 && NOTE_LINE_NUMBER (insn
) != NOTE_INSN_DELETED_LABEL
)
15083 insn
= PREV_INSN (insn
);
15087 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_DELETED_LABEL
)))
15088 fputs ("\tnop\n", file
);
15092 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15095 We don't output a traceback table if -finhibit-size-directive was
15096 used. The documentation for -finhibit-size-directive reads
15097 ``don't output a @code{.size} assembler directive, or anything
15098 else that would cause trouble if the function is split in the
15099 middle, and the two halves are placed at locations far apart in
15100 memory.'' The traceback table has this property, since it
15101 includes the offset from the start of the function to the
15102 traceback table itself.
15104 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15105 different traceback table. */
15106 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
15107 && rs6000_traceback
!= traceback_none
)
15109 const char *fname
= NULL
;
15110 const char *language_string
= lang_hooks
.name
;
15111 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
15113 int optional_tbtab
;
15115 if (rs6000_traceback
== traceback_full
)
15116 optional_tbtab
= 1;
15117 else if (rs6000_traceback
== traceback_part
)
15118 optional_tbtab
= 0;
15120 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
15122 if (optional_tbtab
)
15124 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
15125 while (*fname
== '.') /* V.4 encodes . in the name */
15128 /* Need label immediately before tbtab, so we can compute
15129 its offset from the function start. */
15130 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
15131 ASM_OUTPUT_LABEL (file
, fname
);
15134 /* The .tbtab pseudo-op can only be used for the first eight
15135 expressions, since it can't handle the possibly variable
15136 length fields that follow. However, if you omit the optional
15137 fields, the assembler outputs zeros for all optional fields
15138 anyways, giving each variable length field is minimum length
15139 (as defined in sys/debug.h). Thus we can not use the .tbtab
15140 pseudo-op at all. */
15142 /* An all-zero word flags the start of the tbtab, for debuggers
15143 that have to find it by searching forward from the entry
15144 point or from the current pc. */
15145 fputs ("\t.long 0\n", file
);
15147 /* Tbtab format type. Use format type 0. */
15148 fputs ("\t.byte 0,", file
);
15150 /* Language type. Unfortunately, there does not seem to be any
15151 official way to discover the language being compiled, so we
15152 use language_string.
15153 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15154 Java is 13. Objective-C is 14. */
15155 if (! strcmp (language_string
, "GNU C"))
15157 else if (! strcmp (language_string
, "GNU F77")
15158 || ! strcmp (language_string
, "GNU F95"))
15160 else if (! strcmp (language_string
, "GNU Pascal"))
15162 else if (! strcmp (language_string
, "GNU Ada"))
15164 else if (! strcmp (language_string
, "GNU C++"))
15166 else if (! strcmp (language_string
, "GNU Java"))
15168 else if (! strcmp (language_string
, "GNU Objective-C"))
15171 gcc_unreachable ();
15172 fprintf (file
, "%d,", i
);
15174 /* 8 single bit fields: global linkage (not set for C extern linkage,
15175 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15176 from start of procedure stored in tbtab, internal function, function
15177 has controlled storage, function has no toc, function uses fp,
15178 function logs/aborts fp operations. */
15179 /* Assume that fp operations are used if any fp reg must be saved. */
15180 fprintf (file
, "%d,",
15181 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
15183 /* 6 bitfields: function is interrupt handler, name present in
15184 proc table, function calls alloca, on condition directives
15185 (controls stack walks, 3 bits), saves condition reg, saves
15187 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15188 set up as a frame pointer, even when there is no alloca call. */
15189 fprintf (file
, "%d,",
15190 ((optional_tbtab
<< 6)
15191 | ((optional_tbtab
& frame_pointer_needed
) << 5)
15192 | (info
->cr_save_p
<< 1)
15193 | (info
->lr_save_p
)));
15195 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15197 fprintf (file
, "%d,",
15198 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
15200 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15201 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
15203 if (optional_tbtab
)
15205 /* Compute the parameter info from the function decl argument
15208 int next_parm_info_bit
= 31;
15210 for (decl
= DECL_ARGUMENTS (current_function_decl
);
15211 decl
; decl
= TREE_CHAIN (decl
))
15213 rtx parameter
= DECL_INCOMING_RTL (decl
);
15214 enum machine_mode mode
= GET_MODE (parameter
);
15216 if (GET_CODE (parameter
) == REG
)
15218 if (SCALAR_FLOAT_MODE_P (mode
))
15236 gcc_unreachable ();
15239 /* If only one bit will fit, don't or in this entry. */
15240 if (next_parm_info_bit
> 0)
15241 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
15242 next_parm_info_bit
-= 2;
15246 fixed_parms
+= ((GET_MODE_SIZE (mode
)
15247 + (UNITS_PER_WORD
- 1))
15249 next_parm_info_bit
-= 1;
15255 /* Number of fixed point parameters. */
15256 /* This is actually the number of words of fixed point parameters; thus
15257 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15258 fprintf (file
, "%d,", fixed_parms
);
15260 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15262 /* This is actually the number of fp registers that hold parameters;
15263 and thus the maximum value is 13. */
15264 /* Set parameters on stack bit if parameters are not in their original
15265 registers, regardless of whether they are on the stack? Xlc
15266 seems to set the bit when not optimizing. */
15267 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
15269 if (! optional_tbtab
)
15272 /* Optional fields follow. Some are variable length. */
15274 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15275 11 double float. */
15276 /* There is an entry for each parameter in a register, in the order that
15277 they occur in the parameter list. Any intervening arguments on the
15278 stack are ignored. If the list overflows a long (max possible length
15279 34 bits) then completely leave off all elements that don't fit. */
15280 /* Only emit this long if there was at least one parameter. */
15281 if (fixed_parms
|| float_parms
)
15282 fprintf (file
, "\t.long %d\n", parm_info
);
15284 /* Offset from start of code to tb table. */
15285 fputs ("\t.long ", file
);
15286 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
15288 RS6000_OUTPUT_BASENAME (file
, fname
);
15290 assemble_name (file
, fname
);
15292 rs6000_output_function_entry (file
, fname
);
15295 /* Interrupt handler mask. */
15296 /* Omit this long, since we never set the interrupt handler bit
15299 /* Number of CTL (controlled storage) anchors. */
15300 /* Omit this long, since the has_ctl bit is never set above. */
15302 /* Displacement into stack of each CTL anchor. */
15303 /* Omit this list of longs, because there are no CTL anchors. */
15305 /* Length of function name. */
15308 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
15310 /* Function name. */
15311 assemble_string (fname
, strlen (fname
));
15313 /* Register for alloca automatic storage; this is always reg 31.
15314 Only emit this if the alloca bit was set above. */
15315 if (frame_pointer_needed
)
15316 fputs ("\t.byte 31\n", file
);
15318 fputs ("\t.align 2\n", file
);
15322 /* A C compound statement that outputs the assembler code for a thunk
15323 function, used to implement C++ virtual function calls with
15324 multiple inheritance. The thunk acts as a wrapper around a virtual
15325 function, adjusting the implicit object parameter before handing
15326 control off to the real function.
15328 First, emit code to add the integer DELTA to the location that
15329 contains the incoming first argument. Assume that this argument
15330 contains a pointer, and is the one used to pass the `this' pointer
15331 in C++. This is the incoming argument *before* the function
15332 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15333 values of all other incoming arguments.
15335 After the addition, emit code to jump to FUNCTION, which is a
15336 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15337 not touch the return address. Hence returning from FUNCTION will
15338 return to whoever called the current `thunk'.
15340 The effect must be as if FUNCTION had been called directly with the
15341 adjusted first argument. This macro is responsible for emitting
15342 all of the code for a thunk function; output_function_prologue()
15343 and output_function_epilogue() are not invoked.
15345 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15346 been extracted from it.) It might possibly be useful on some
15347 targets, but probably not.
15349 If you do not define this macro, the target-independent code in the
15350 C++ frontend will generate a less efficient heavyweight thunk that
15351 calls FUNCTION instead of jumping to it. The generic approach does
15352 not support varargs. */
15355 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
15356 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
15359 rtx
this, insn
, funexp
;
15361 reload_completed
= 1;
15362 epilogue_completed
= 1;
15363 no_new_pseudos
= 1;
15364 reset_block_changes ();
15366 /* Mark the end of the (empty) prologue. */
15367 emit_note (NOTE_INSN_PROLOGUE_END
);
15369 /* Find the "this" pointer. If the function returns a structure,
15370 the structure return pointer is in r3. */
15371 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
15372 this = gen_rtx_REG (Pmode
, 4);
15374 this = gen_rtx_REG (Pmode
, 3);
15376 /* Apply the constant offset, if required. */
15379 rtx delta_rtx
= GEN_INT (delta
);
15380 emit_insn (TARGET_32BIT
15381 ? gen_addsi3 (this, this, delta_rtx
)
15382 : gen_adddi3 (this, this, delta_rtx
));
15385 /* Apply the offset from the vtable, if required. */
15388 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
15389 rtx tmp
= gen_rtx_REG (Pmode
, 12);
15391 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
15392 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
15394 emit_insn (TARGET_32BIT
15395 ? gen_addsi3 (tmp
, tmp
, vcall_offset_rtx
)
15396 : gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
15397 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
15401 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
15403 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
15405 emit_insn (TARGET_32BIT
15406 ? gen_addsi3 (this, this, tmp
)
15407 : gen_adddi3 (this, this, tmp
));
15410 /* Generate a tail call to the target function. */
15411 if (!TREE_USED (function
))
15413 assemble_external (function
);
15414 TREE_USED (function
) = 1;
15416 funexp
= XEXP (DECL_RTL (function
), 0);
15417 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
15420 if (MACHOPIC_INDIRECT
)
15421 funexp
= machopic_indirect_call_target (funexp
);
15424 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15425 generate sibcall RTL explicitly. */
15426 insn
= emit_call_insn (
15427 gen_rtx_PARALLEL (VOIDmode
,
15429 gen_rtx_CALL (VOIDmode
,
15430 funexp
, const0_rtx
),
15431 gen_rtx_USE (VOIDmode
, const0_rtx
),
15432 gen_rtx_USE (VOIDmode
,
15433 gen_rtx_REG (SImode
,
15434 LINK_REGISTER_REGNUM
)),
15435 gen_rtx_RETURN (VOIDmode
))));
15436 SIBLING_CALL_P (insn
) = 1;
15439 /* Run just enough of rest_of_compilation to get the insns emitted.
15440 There's not really enough bulk here to make other passes such as
15441 instruction scheduling worth while. Note that use_thunk calls
15442 assemble_start_function and assemble_end_function. */
15443 insn
= get_insns ();
15444 insn_locators_initialize ();
15445 shorten_branches (insn
);
15446 final_start_function (insn
, file
, 1);
15447 final (insn
, file
, 1);
15448 final_end_function ();
15450 reload_completed
= 0;
15451 epilogue_completed
= 0;
15452 no_new_pseudos
= 0;
15455 /* A quick summary of the various types of 'constant-pool tables'
15458 Target Flags Name One table per
15459 AIX (none) AIX TOC object file
15460 AIX -mfull-toc AIX TOC object file
15461 AIX -mminimal-toc AIX minimal TOC translation unit
15462 SVR4/EABI (none) SVR4 SDATA object file
15463 SVR4/EABI -fpic SVR4 pic object file
15464 SVR4/EABI -fPIC SVR4 PIC translation unit
15465 SVR4/EABI -mrelocatable EABI TOC function
15466 SVR4/EABI -maix AIX TOC object file
15467 SVR4/EABI -maix -mminimal-toc
15468 AIX minimal TOC translation unit
15470 Name Reg. Set by entries contains:
15471 made by addrs? fp? sum?
15473 AIX TOC 2 crt0 as Y option option
15474 AIX minimal TOC 30 prolog gcc Y Y option
15475 SVR4 SDATA 13 crt0 gcc N Y N
15476 SVR4 pic 30 prolog ld Y not yet N
15477 SVR4 PIC 30 prolog gcc Y option option
15478 EABI TOC 30 prolog gcc Y option option
15482 /* Hash functions for the hash table. */
15485 rs6000_hash_constant (rtx k
)
15487 enum rtx_code code
= GET_CODE (k
);
15488 enum machine_mode mode
= GET_MODE (k
);
15489 unsigned result
= (code
<< 3) ^ mode
;
15490 const char *format
;
15493 format
= GET_RTX_FORMAT (code
);
15494 flen
= strlen (format
);
15500 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
15503 if (mode
!= VOIDmode
)
15504 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
15516 for (; fidx
< flen
; fidx
++)
15517 switch (format
[fidx
])
15522 const char *str
= XSTR (k
, fidx
);
15523 len
= strlen (str
);
15524 result
= result
* 613 + len
;
15525 for (i
= 0; i
< len
; i
++)
15526 result
= result
* 613 + (unsigned) str
[i
];
15531 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
15535 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
15538 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
15539 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
15543 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
15544 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
15551 gcc_unreachable ();
15558 toc_hash_function (const void *hash_entry
)
15560 const struct toc_hash_struct
*thc
=
15561 (const struct toc_hash_struct
*) hash_entry
;
15562 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
15565 /* Compare H1 and H2 for equivalence. */
15568 toc_hash_eq (const void *h1
, const void *h2
)
15570 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
15571 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
15573 if (((const struct toc_hash_struct
*) h1
)->key_mode
15574 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
15577 return rtx_equal_p (r1
, r2
);
15580 /* These are the names given by the C++ front-end to vtables, and
15581 vtable-like objects. Ideally, this logic should not be here;
15582 instead, there should be some programmatic way of inquiring as
15583 to whether or not an object is a vtable. */
15585 #define VTABLE_NAME_P(NAME) \
15586 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15587 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15588 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15589 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15590 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15593 rs6000_output_symbol_ref (FILE *file
, rtx x
)
15595 /* Currently C++ toc references to vtables can be emitted before it
15596 is decided whether the vtable is public or private. If this is
15597 the case, then the linker will eventually complain that there is
15598 a reference to an unknown section. Thus, for vtables only,
15599 we emit the TOC reference to reference the symbol and not the
15601 const char *name
= XSTR (x
, 0);
15603 if (VTABLE_NAME_P (name
))
15605 RS6000_OUTPUT_BASENAME (file
, name
);
15608 assemble_name (file
, name
);
15611 /* Output a TOC entry. We derive the entry name from what is being
15615 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
15618 const char *name
= buf
;
15619 const char *real_name
;
15621 HOST_WIDE_INT offset
= 0;
15623 gcc_assert (!TARGET_NO_TOC
);
15625 /* When the linker won't eliminate them, don't output duplicate
15626 TOC entries (this happens on AIX if there is any kind of TOC,
15627 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15629 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
15631 struct toc_hash_struct
*h
;
15634 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15635 time because GGC is not initialized at that point. */
15636 if (toc_hash_table
== NULL
)
15637 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
15638 toc_hash_eq
, NULL
);
15640 h
= ggc_alloc (sizeof (*h
));
15642 h
->key_mode
= mode
;
15643 h
->labelno
= labelno
;
15645 found
= htab_find_slot (toc_hash_table
, h
, 1);
15646 if (*found
== NULL
)
15648 else /* This is indeed a duplicate.
15649 Set this label equal to that label. */
15651 fputs ("\t.set ", file
);
15652 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
15653 fprintf (file
, "%d,", labelno
);
15654 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
15655 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
15661 /* If we're going to put a double constant in the TOC, make sure it's
15662 aligned properly when strict alignment is on. */
15663 if (GET_CODE (x
) == CONST_DOUBLE
15664 && STRICT_ALIGNMENT
15665 && GET_MODE_BITSIZE (mode
) >= 64
15666 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
15667 ASM_OUTPUT_ALIGN (file
, 3);
15670 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
15672 /* Handle FP constants specially. Note that if we have a minimal
15673 TOC, things we put here aren't actually in the TOC, so we can allow
15675 if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == TFmode
)
15677 REAL_VALUE_TYPE rv
;
15680 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
15681 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
15685 if (TARGET_MINIMAL_TOC
)
15686 fputs (DOUBLE_INT_ASM_OP
, file
);
15688 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15689 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15690 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15691 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
15692 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15693 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15698 if (TARGET_MINIMAL_TOC
)
15699 fputs ("\t.long ", file
);
15701 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15702 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15703 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15704 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15705 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15706 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15710 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
15712 REAL_VALUE_TYPE rv
;
15715 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
15716 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
15720 if (TARGET_MINIMAL_TOC
)
15721 fputs (DOUBLE_INT_ASM_OP
, file
);
15723 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
15724 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15725 fprintf (file
, "0x%lx%08lx\n",
15726 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15731 if (TARGET_MINIMAL_TOC
)
15732 fputs ("\t.long ", file
);
15734 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
15735 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15736 fprintf (file
, "0x%lx,0x%lx\n",
15737 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15741 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
15743 REAL_VALUE_TYPE rv
;
15746 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
15747 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
15751 if (TARGET_MINIMAL_TOC
)
15752 fputs (DOUBLE_INT_ASM_OP
, file
);
15754 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
15755 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
15760 if (TARGET_MINIMAL_TOC
)
15761 fputs ("\t.long ", file
);
15763 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
15764 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
15768 else if (GET_MODE (x
) == VOIDmode
15769 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
15771 unsigned HOST_WIDE_INT low
;
15772 HOST_WIDE_INT high
;
15774 if (GET_CODE (x
) == CONST_DOUBLE
)
15776 low
= CONST_DOUBLE_LOW (x
);
15777 high
= CONST_DOUBLE_HIGH (x
);
15780 #if HOST_BITS_PER_WIDE_INT == 32
15783 high
= (low
& 0x80000000) ? ~0 : 0;
15787 low
= INTVAL (x
) & 0xffffffff;
15788 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
15792 /* TOC entries are always Pmode-sized, but since this
15793 is a bigendian machine then if we're putting smaller
15794 integer constants in the TOC we have to pad them.
15795 (This is still a win over putting the constants in
15796 a separate constant pool, because then we'd have
15797 to have both a TOC entry _and_ the actual constant.)
15799 For a 32-bit target, CONST_INT values are loaded and shifted
15800 entirely within `low' and can be stored in one TOC entry. */
15802 /* It would be easy to make this work, but it doesn't now. */
15803 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
15805 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
15807 #if HOST_BITS_PER_WIDE_INT == 32
15808 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
15809 POINTER_SIZE
, &low
, &high
, 0);
15812 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
15813 high
= (HOST_WIDE_INT
) low
>> 32;
15820 if (TARGET_MINIMAL_TOC
)
15821 fputs (DOUBLE_INT_ASM_OP
, file
);
15823 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
15824 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15825 fprintf (file
, "0x%lx%08lx\n",
15826 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15831 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
15833 if (TARGET_MINIMAL_TOC
)
15834 fputs ("\t.long ", file
);
15836 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
15837 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15838 fprintf (file
, "0x%lx,0x%lx\n",
15839 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15843 if (TARGET_MINIMAL_TOC
)
15844 fputs ("\t.long ", file
);
15846 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
15847 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
15853 if (GET_CODE (x
) == CONST
)
15855 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
);
15857 base
= XEXP (XEXP (x
, 0), 0);
15858 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
15861 switch (GET_CODE (base
))
15864 name
= XSTR (base
, 0);
15868 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
15869 CODE_LABEL_NUMBER (XEXP (base
, 0)));
15873 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
15877 gcc_unreachable ();
15880 real_name
= (*targetm
.strip_name_encoding
) (name
);
15881 if (TARGET_MINIMAL_TOC
)
15882 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
15885 fprintf (file
, "\t.tc %s", real_name
);
15888 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
15890 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
15892 fputs ("[TC],", file
);
15895 /* Currently C++ toc references to vtables can be emitted before it
15896 is decided whether the vtable is public or private. If this is
15897 the case, then the linker will eventually complain that there is
15898 a TOC reference to an unknown section. Thus, for vtables only,
15899 we emit the TOC reference to reference the symbol and not the
15901 if (VTABLE_NAME_P (name
))
15903 RS6000_OUTPUT_BASENAME (file
, name
);
15905 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
15906 else if (offset
> 0)
15907 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
15910 output_addr_const (file
, x
);
15914 /* Output an assembler pseudo-op to write an ASCII string of N characters
15915 starting at P to FILE.
15917 On the RS/6000, we have to do this using the .byte operation and
15918 write out special characters outside the quoted string.
15919 Also, the assembler is broken; very long strings are truncated,
15920 so we must artificially break them up early. */
15923 output_ascii (FILE *file
, const char *p
, int n
)
15926 int i
, count_string
;
15927 const char *for_string
= "\t.byte \"";
15928 const char *for_decimal
= "\t.byte ";
15929 const char *to_close
= NULL
;
15932 for (i
= 0; i
< n
; i
++)
15935 if (c
>= ' ' && c
< 0177)
15938 fputs (for_string
, file
);
15941 /* Write two quotes to get one. */
15949 for_decimal
= "\"\n\t.byte ";
15953 if (count_string
>= 512)
15955 fputs (to_close
, file
);
15957 for_string
= "\t.byte \"";
15958 for_decimal
= "\t.byte ";
15966 fputs (for_decimal
, file
);
15967 fprintf (file
, "%d", c
);
15969 for_string
= "\n\t.byte \"";
15970 for_decimal
= ", ";
15976 /* Now close the string if we have written one. Then end the line. */
15978 fputs (to_close
, file
);
15981 /* Generate a unique section name for FILENAME for a section type
15982 represented by SECTION_DESC. Output goes into BUF.
15984 SECTION_DESC can be any string, as long as it is different for each
15985 possible section type.
15987 We name the section in the same manner as xlc. The name begins with an
15988 underscore followed by the filename (after stripping any leading directory
15989 names) with the last period replaced by the string SECTION_DESC. If
15990 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15994 rs6000_gen_section_name (char **buf
, const char *filename
,
15995 const char *section_desc
)
15997 const char *q
, *after_last_slash
, *last_period
= 0;
16001 after_last_slash
= filename
;
16002 for (q
= filename
; *q
; q
++)
16005 after_last_slash
= q
+ 1;
16006 else if (*q
== '.')
16010 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
16011 *buf
= (char *) xmalloc (len
);
16016 for (q
= after_last_slash
; *q
; q
++)
16018 if (q
== last_period
)
16020 strcpy (p
, section_desc
);
16021 p
+= strlen (section_desc
);
16025 else if (ISALNUM (*q
))
16029 if (last_period
== 0)
16030 strcpy (p
, section_desc
);
16035 /* Emit profile function. */
16038 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
16040 /* Non-standard profiling for kernels, which just saves LR then calls
16041 _mcount without worrying about arg saves. The idea is to change
16042 the function prologue as little as possible as it isn't easy to
16043 account for arg save/restore code added just for _mcount. */
16044 if (TARGET_PROFILE_KERNEL
)
16047 if (DEFAULT_ABI
== ABI_AIX
)
16049 #ifndef NO_PROFILE_COUNTERS
16050 # define NO_PROFILE_COUNTERS 0
16052 if (NO_PROFILE_COUNTERS
)
16053 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 0);
16057 const char *label_name
;
16060 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
16061 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
16062 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
16064 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 1,
16068 else if (DEFAULT_ABI
== ABI_DARWIN
)
16070 const char *mcount_name
= RS6000_MCOUNT
;
16071 int caller_addr_regno
= LINK_REGISTER_REGNUM
;
16073 /* Be conservative and always set this, at least for now. */
16074 current_function_uses_pic_offset_table
= 1;
16077 /* For PIC code, set up a stub and collect the caller's address
16078 from r0, which is where the prologue puts it. */
16079 if (MACHOPIC_INDIRECT
16080 && current_function_uses_pic_offset_table
)
16081 caller_addr_regno
= 0;
16083 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
16085 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
16089 /* Write function profiler code. */
16092 output_function_profiler (FILE *file
, int labelno
)
16096 switch (DEFAULT_ABI
)
16099 gcc_unreachable ();
16104 warning (0, "no profiling of 64-bit code for this ABI");
16107 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
16108 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
16109 if (NO_PROFILE_COUNTERS
)
16111 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
16112 reg_names
[0], reg_names
[1]);
16114 else if (TARGET_SECURE_PLT
&& flag_pic
)
16116 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16117 reg_names
[0], reg_names
[1]);
16118 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
16119 asm_fprintf (file
, "\t{cau|addis} %s,%s,",
16120 reg_names
[12], reg_names
[12]);
16121 assemble_name (file
, buf
);
16122 asm_fprintf (file
, "-1b@ha\n\t{cal|la} %s,", reg_names
[0]);
16123 assemble_name (file
, buf
);
16124 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
16126 else if (flag_pic
== 1)
16128 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
16129 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
16130 reg_names
[0], reg_names
[1]);
16131 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
16132 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
16133 assemble_name (file
, buf
);
16134 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
16136 else if (flag_pic
> 1)
16138 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
16139 reg_names
[0], reg_names
[1]);
16140 /* Now, we need to get the address of the label. */
16141 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
16142 assemble_name (file
, buf
);
16143 fputs ("-.\n1:", file
);
16144 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
16145 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
16146 reg_names
[0], reg_names
[11]);
16147 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
16148 reg_names
[0], reg_names
[0], reg_names
[11]);
16152 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
16153 assemble_name (file
, buf
);
16154 fputs ("@ha\n", file
);
16155 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
16156 reg_names
[0], reg_names
[1]);
16157 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
16158 assemble_name (file
, buf
);
16159 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
16162 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16163 fprintf (file
, "\tbl %s%s\n",
16164 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
16169 if (!TARGET_PROFILE_KERNEL
)
16171 /* Don't do anything, done in output_profile_hook (). */
16175 gcc_assert (!TARGET_32BIT
);
16177 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
16178 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
16180 if (cfun
->static_chain_decl
!= NULL
)
16182 asm_fprintf (file
, "\tstd %s,24(%s)\n",
16183 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
16184 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
16185 asm_fprintf (file
, "\tld %s,24(%s)\n",
16186 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
16189 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
16196 /* Power4 load update and store update instructions are cracked into a
16197 load or store and an integer insn which are executed in the same cycle.
16198 Branches have their own dispatch slot which does not count against the
16199 GCC issue rate, but it changes the program flow so there are no other
16200 instructions to issue in this cycle. */
16203 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED
,
16204 int verbose ATTRIBUTE_UNUSED
,
16205 rtx insn
, int more
)
16207 if (GET_CODE (PATTERN (insn
)) == USE
16208 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16211 if (rs6000_sched_groups
)
16213 if (is_microcoded_insn (insn
))
16215 else if (is_cracked_insn (insn
))
16216 return more
> 2 ? more
- 2 : 0;
16222 /* Adjust the cost of a scheduling dependency. Return the new cost of
16223 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16226 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
16228 if (! recog_memoized (insn
))
16231 if (REG_NOTE_KIND (link
) != 0)
16234 if (REG_NOTE_KIND (link
) == 0)
16236 /* Data dependency; DEP_INSN writes a register that INSN reads
16237 some cycles later. */
16239 /* Separate a load from a narrower, dependent store. */
16240 if (rs6000_sched_groups
16241 && GET_CODE (PATTERN (insn
)) == SET
16242 && GET_CODE (PATTERN (dep_insn
)) == SET
16243 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
16244 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
16245 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
16246 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
16249 switch (get_attr_type (insn
))
16252 /* Tell the first scheduling pass about the latency between
16253 a mtctr and bctr (and mtlr and br/blr). The first
16254 scheduling pass will not know about this latency since
16255 the mtctr instruction, which has the latency associated
16256 to it, will be generated by reload. */
16257 return TARGET_POWER
? 5 : 4;
16259 /* Leave some extra cycles between a compare and its
16260 dependent branch, to inhibit expensive mispredicts. */
16261 if ((rs6000_cpu_attr
== CPU_PPC603
16262 || rs6000_cpu_attr
== CPU_PPC604
16263 || rs6000_cpu_attr
== CPU_PPC604E
16264 || rs6000_cpu_attr
== CPU_PPC620
16265 || rs6000_cpu_attr
== CPU_PPC630
16266 || rs6000_cpu_attr
== CPU_PPC750
16267 || rs6000_cpu_attr
== CPU_PPC7400
16268 || rs6000_cpu_attr
== CPU_PPC7450
16269 || rs6000_cpu_attr
== CPU_POWER4
16270 || rs6000_cpu_attr
== CPU_POWER5
)
16271 && recog_memoized (dep_insn
)
16272 && (INSN_CODE (dep_insn
) >= 0)
16273 && (get_attr_type (dep_insn
) == TYPE_CMP
16274 || get_attr_type (dep_insn
) == TYPE_COMPARE
16275 || get_attr_type (dep_insn
) == TYPE_DELAYED_COMPARE
16276 || get_attr_type (dep_insn
) == TYPE_IMUL_COMPARE
16277 || get_attr_type (dep_insn
) == TYPE_LMUL_COMPARE
16278 || get_attr_type (dep_insn
) == TYPE_FPCOMPARE
16279 || get_attr_type (dep_insn
) == TYPE_CR_LOGICAL
16280 || get_attr_type (dep_insn
) == TYPE_DELAYED_CR
))
16285 /* Fall out to return default cost. */
16291 /* The function returns a true if INSN is microcoded.
16292 Return false otherwise. */
16295 is_microcoded_insn (rtx insn
)
16297 if (!insn
|| !INSN_P (insn
)
16298 || GET_CODE (PATTERN (insn
)) == USE
16299 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16302 if (rs6000_sched_groups
)
16304 enum attr_type type
= get_attr_type (insn
);
16305 if (type
== TYPE_LOAD_EXT_U
16306 || type
== TYPE_LOAD_EXT_UX
16307 || type
== TYPE_LOAD_UX
16308 || type
== TYPE_STORE_UX
16309 || type
== TYPE_MFCR
)
16316 /* The function returns a nonzero value if INSN can be scheduled only
16317 as the first insn in a dispatch group ("dispatch-slot restricted").
16318 In this case, the returned value indicates how many dispatch slots
16319 the insn occupies (at the beginning of the group).
16320 Return 0 otherwise. */
16323 is_dispatch_slot_restricted (rtx insn
)
16325 enum attr_type type
;
16327 if (!rs6000_sched_groups
)
16331 || insn
== NULL_RTX
16332 || GET_CODE (insn
) == NOTE
16333 || GET_CODE (PATTERN (insn
)) == USE
16334 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16337 type
= get_attr_type (insn
);
16344 case TYPE_DELAYED_CR
:
16345 case TYPE_CR_LOGICAL
:
16358 if (rs6000_cpu
== PROCESSOR_POWER5
16359 && is_cracked_insn (insn
))
16365 /* The function returns true if INSN is cracked into 2 instructions
16366 by the processor (and therefore occupies 2 issue slots). */
16369 is_cracked_insn (rtx insn
)
16371 if (!insn
|| !INSN_P (insn
)
16372 || GET_CODE (PATTERN (insn
)) == USE
16373 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16376 if (rs6000_sched_groups
)
16378 enum attr_type type
= get_attr_type (insn
);
16379 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
16380 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
16381 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
16382 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
16383 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
16384 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
16385 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
16386 || type
== TYPE_INSERT_WORD
)
16393 /* The function returns true if INSN can be issued only from
16394 the branch slot. */
16397 is_branch_slot_insn (rtx insn
)
16399 if (!insn
|| !INSN_P (insn
)
16400 || GET_CODE (PATTERN (insn
)) == USE
16401 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16404 if (rs6000_sched_groups
)
16406 enum attr_type type
= get_attr_type (insn
);
16407 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
16415 /* A C statement (sans semicolon) to update the integer scheduling
16416 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16417 INSN earlier, reduce the priority to execute INSN later. Do not
16418 define this macro if you do not need to adjust the scheduling
16419 priorities of insns. */
16422 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
16424 /* On machines (like the 750) which have asymmetric integer units,
16425 where one integer unit can do multiply and divides and the other
16426 can't, reduce the priority of multiply/divide so it is scheduled
16427 before other integer operations. */
16430 if (! INSN_P (insn
))
16433 if (GET_CODE (PATTERN (insn
)) == USE
)
16436 switch (rs6000_cpu_attr
) {
16438 switch (get_attr_type (insn
))
16445 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
16446 priority
, priority
);
16447 if (priority
>= 0 && priority
< 0x01000000)
16454 if (is_dispatch_slot_restricted (insn
)
16455 && reload_completed
16456 && current_sched_info
->sched_max_insns_priority
16457 && rs6000_sched_restricted_insns_priority
)
16460 /* Prioritize insns that can be dispatched only in the first
16462 if (rs6000_sched_restricted_insns_priority
== 1)
16463 /* Attach highest priority to insn. This means that in
16464 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16465 precede 'priority' (critical path) considerations. */
16466 return current_sched_info
->sched_max_insns_priority
;
16467 else if (rs6000_sched_restricted_insns_priority
== 2)
16468 /* Increase priority of insn by a minimal amount. This means that in
16469 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16470 considerations precede dispatch-slot restriction considerations. */
16471 return (priority
+ 1);
16477 /* Return how many instructions the machine can issue per cycle. */
16480 rs6000_issue_rate (void)
16482 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16483 if (!reload_completed
)
16486 switch (rs6000_cpu_attr
) {
16487 case CPU_RIOS1
: /* ? */
16489 case CPU_PPC601
: /* ? */
16512 /* Return how many instructions to look ahead for better insn
16516 rs6000_use_sched_lookahead (void)
16518 if (rs6000_cpu_attr
== CPU_PPC8540
)
16523 /* Determine is PAT refers to memory. */
16526 is_mem_ref (rtx pat
)
16532 if (GET_CODE (pat
) == MEM
)
16535 /* Recursively process the pattern. */
16536 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
16538 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
16541 ret
|= is_mem_ref (XEXP (pat
, i
));
16542 else if (fmt
[i
] == 'E')
16543 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
16544 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
16550 /* Determine if PAT is a PATTERN of a load insn. */
16553 is_load_insn1 (rtx pat
)
16555 if (!pat
|| pat
== NULL_RTX
)
16558 if (GET_CODE (pat
) == SET
)
16559 return is_mem_ref (SET_SRC (pat
));
16561 if (GET_CODE (pat
) == PARALLEL
)
16565 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
16566 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
16573 /* Determine if INSN loads from memory. */
16576 is_load_insn (rtx insn
)
16578 if (!insn
|| !INSN_P (insn
))
16581 if (GET_CODE (insn
) == CALL_INSN
)
16584 return is_load_insn1 (PATTERN (insn
));
16587 /* Determine if PAT is a PATTERN of a store insn. */
16590 is_store_insn1 (rtx pat
)
16592 if (!pat
|| pat
== NULL_RTX
)
16595 if (GET_CODE (pat
) == SET
)
16596 return is_mem_ref (SET_DEST (pat
));
16598 if (GET_CODE (pat
) == PARALLEL
)
16602 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
16603 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
16610 /* Determine if INSN stores to memory. */
16613 is_store_insn (rtx insn
)
16615 if (!insn
|| !INSN_P (insn
))
16618 return is_store_insn1 (PATTERN (insn
));
16621 /* Returns whether the dependence between INSN and NEXT is considered
16622 costly by the given target. */
16625 rs6000_is_costly_dependence (rtx insn
, rtx next
, rtx link
, int cost
,
16628 /* If the flag is not enabled - no dependence is considered costly;
16629 allow all dependent insns in the same group.
16630 This is the most aggressive option. */
16631 if (rs6000_sched_costly_dep
== no_dep_costly
)
16634 /* If the flag is set to 1 - a dependence is always considered costly;
16635 do not allow dependent instructions in the same group.
16636 This is the most conservative option. */
16637 if (rs6000_sched_costly_dep
== all_deps_costly
)
16640 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
16641 && is_load_insn (next
)
16642 && is_store_insn (insn
))
16643 /* Prevent load after store in the same group. */
16646 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
16647 && is_load_insn (next
)
16648 && is_store_insn (insn
)
16649 && (!link
|| (int) REG_NOTE_KIND (link
) == 0))
16650 /* Prevent load after store in the same group if it is a true
16654 /* The flag is set to X; dependences with latency >= X are considered costly,
16655 and will not be scheduled in the same group. */
16656 if (rs6000_sched_costly_dep
<= max_dep_latency
16657 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
16663 /* Return the next insn after INSN that is found before TAIL is reached,
16664 skipping any "non-active" insns - insns that will not actually occupy
16665 an issue slot. Return NULL_RTX if such an insn is not found. */
16668 get_next_active_insn (rtx insn
, rtx tail
)
16670 if (insn
== NULL_RTX
|| insn
== tail
)
16675 insn
= NEXT_INSN (insn
);
16676 if (insn
== NULL_RTX
|| insn
== tail
)
16681 || (NONJUMP_INSN_P (insn
)
16682 && GET_CODE (PATTERN (insn
)) != USE
16683 && GET_CODE (PATTERN (insn
)) != CLOBBER
16684 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
16690 /* Return whether the presence of INSN causes a dispatch group termination
16691 of group WHICH_GROUP.
16693 If WHICH_GROUP == current_group, this function will return true if INSN
16694 causes the termination of the current group (i.e, the dispatch group to
16695 which INSN belongs). This means that INSN will be the last insn in the
16696 group it belongs to.
16698 If WHICH_GROUP == previous_group, this function will return true if INSN
16699 causes the termination of the previous group (i.e, the dispatch group that
16700 precedes the group to which INSN belongs). This means that INSN will be
16701 the first insn in the group it belongs to). */
16704 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
16706 enum attr_type type
;
16711 type
= get_attr_type (insn
);
16713 if (is_microcoded_insn (insn
))
16716 if (which_group
== current_group
)
16718 if (is_branch_slot_insn (insn
))
16722 else if (which_group
== previous_group
)
16724 if (is_dispatch_slot_restricted (insn
))
16732 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16733 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16736 is_costly_group (rtx
*group_insns
, rtx next_insn
)
16741 int issue_rate
= rs6000_issue_rate ();
16743 for (i
= 0; i
< issue_rate
; i
++)
16745 rtx insn
= group_insns
[i
];
16748 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
16750 rtx next
= XEXP (link
, 0);
16751 if (next
== next_insn
)
16753 cost
= insn_cost (insn
, link
, next_insn
);
16754 if (rs6000_is_costly_dependence (insn
, next_insn
, link
, cost
, 0))
16763 /* Utility of the function redefine_groups.
16764 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16765 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16766 to keep it "far" (in a separate group) from GROUP_INSNS, following
16767 one of the following schemes, depending on the value of the flag
16768 -minsert_sched_nops = X:
16769 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16770 in order to force NEXT_INSN into a separate group.
16771 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16772 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16773 insertion (has a group just ended, how many vacant issue slots remain in the
16774 last group, and how many dispatch groups were encountered so far). */
16777 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
16778 rtx next_insn
, bool *group_end
, int can_issue_more
,
16783 int issue_rate
= rs6000_issue_rate ();
16784 bool end
= *group_end
;
16787 if (next_insn
== NULL_RTX
)
16788 return can_issue_more
;
16790 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
16791 return can_issue_more
;
16793 force
= is_costly_group (group_insns
, next_insn
);
16795 return can_issue_more
;
16797 if (sched_verbose
> 6)
16798 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
16799 *group_count
,can_issue_more
);
16801 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
16804 can_issue_more
= 0;
16806 /* Since only a branch can be issued in the last issue_slot, it is
16807 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16808 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16809 in this case the last nop will start a new group and the branch
16810 will be forced to the new group. */
16811 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
16814 while (can_issue_more
> 0)
16817 emit_insn_before (nop
, next_insn
);
16825 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
16827 int n_nops
= rs6000_sched_insert_nops
;
16829 /* Nops can't be issued from the branch slot, so the effective
16830 issue_rate for nops is 'issue_rate - 1'. */
16831 if (can_issue_more
== 0)
16832 can_issue_more
= issue_rate
;
16834 if (can_issue_more
== 0)
16836 can_issue_more
= issue_rate
- 1;
16839 for (i
= 0; i
< issue_rate
; i
++)
16841 group_insns
[i
] = 0;
16848 emit_insn_before (nop
, next_insn
);
16849 if (can_issue_more
== issue_rate
- 1) /* new group begins */
16852 if (can_issue_more
== 0)
16854 can_issue_more
= issue_rate
- 1;
16857 for (i
= 0; i
< issue_rate
; i
++)
16859 group_insns
[i
] = 0;
16865 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16868 /* Is next_insn going to start a new group? */
16871 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
16872 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
16873 || (can_issue_more
< issue_rate
&&
16874 insn_terminates_group_p (next_insn
, previous_group
)));
16875 if (*group_end
&& end
)
16878 if (sched_verbose
> 6)
16879 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
16880 *group_count
, can_issue_more
);
16881 return can_issue_more
;
16884 return can_issue_more
;
16887 /* This function tries to synch the dispatch groups that the compiler "sees"
16888 with the dispatch groups that the processor dispatcher is expected to
16889 form in practice. It tries to achieve this synchronization by forcing the
16890 estimated processor grouping on the compiler (as opposed to the function
16891 'pad_goups' which tries to force the scheduler's grouping on the processor).
16893 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16894 examines the (estimated) dispatch groups that will be formed by the processor
16895 dispatcher. It marks these group boundaries to reflect the estimated
16896 processor grouping, overriding the grouping that the scheduler had marked.
16897 Depending on the value of the flag '-minsert-sched-nops' this function can
16898 force certain insns into separate groups or force a certain distance between
16899 them by inserting nops, for example, if there exists a "costly dependence"
16902 The function estimates the group boundaries that the processor will form as
16903 follows: It keeps track of how many vacant issue slots are available after
16904 each insn. A subsequent insn will start a new group if one of the following
16906 - no more vacant issue slots remain in the current dispatch group.
16907 - only the last issue slot, which is the branch slot, is vacant, but the next
16908 insn is not a branch.
16909 - only the last 2 or less issue slots, including the branch slot, are vacant,
16910 which means that a cracked insn (which occupies two issue slots) can't be
16911 issued in this group.
16912 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16913 start a new group. */
16916 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
16918 rtx insn
, next_insn
;
16920 int can_issue_more
;
16923 int group_count
= 0;
16927 issue_rate
= rs6000_issue_rate ();
16928 group_insns
= alloca (issue_rate
* sizeof (rtx
));
16929 for (i
= 0; i
< issue_rate
; i
++)
16931 group_insns
[i
] = 0;
16933 can_issue_more
= issue_rate
;
16935 insn
= get_next_active_insn (prev_head_insn
, tail
);
16938 while (insn
!= NULL_RTX
)
16940 slot
= (issue_rate
- can_issue_more
);
16941 group_insns
[slot
] = insn
;
16943 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
16944 if (insn_terminates_group_p (insn
, current_group
))
16945 can_issue_more
= 0;
16947 next_insn
= get_next_active_insn (insn
, tail
);
16948 if (next_insn
== NULL_RTX
)
16949 return group_count
+ 1;
16951 /* Is next_insn going to start a new group? */
16953 = (can_issue_more
== 0
16954 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
16955 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
16956 || (can_issue_more
< issue_rate
&&
16957 insn_terminates_group_p (next_insn
, previous_group
)));
16959 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
16960 next_insn
, &group_end
, can_issue_more
,
16966 can_issue_more
= 0;
16967 for (i
= 0; i
< issue_rate
; i
++)
16969 group_insns
[i
] = 0;
16973 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
16974 PUT_MODE (next_insn
, VOIDmode
);
16975 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
16976 PUT_MODE (next_insn
, TImode
);
16979 if (can_issue_more
== 0)
16980 can_issue_more
= issue_rate
;
16983 return group_count
;
16986 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16987 dispatch group boundaries that the scheduler had marked. Pad with nops
16988 any dispatch groups which have vacant issue slots, in order to force the
16989 scheduler's grouping on the processor dispatcher. The function
16990 returns the number of dispatch groups found. */
16993 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
16995 rtx insn
, next_insn
;
16998 int can_issue_more
;
17000 int group_count
= 0;
17002 /* Initialize issue_rate. */
17003 issue_rate
= rs6000_issue_rate ();
17004 can_issue_more
= issue_rate
;
17006 insn
= get_next_active_insn (prev_head_insn
, tail
);
17007 next_insn
= get_next_active_insn (insn
, tail
);
17009 while (insn
!= NULL_RTX
)
17012 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
17014 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
17016 if (next_insn
== NULL_RTX
)
17021 /* If the scheduler had marked group termination at this location
17022 (between insn and next_indn), and neither insn nor next_insn will
17023 force group termination, pad the group with nops to force group
17026 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
17027 && !insn_terminates_group_p (insn
, current_group
)
17028 && !insn_terminates_group_p (next_insn
, previous_group
))
17030 if (!is_branch_slot_insn (next_insn
))
17033 while (can_issue_more
)
17036 emit_insn_before (nop
, next_insn
);
17041 can_issue_more
= issue_rate
;
17046 next_insn
= get_next_active_insn (insn
, tail
);
17049 return group_count
;
17052 /* The following function is called at the end of scheduling BB.
17053 After reload, it inserts nops at insn group bundling. */
17056 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
17061 fprintf (dump
, "=== Finishing schedule.\n");
17063 if (reload_completed
&& rs6000_sched_groups
)
17065 if (rs6000_sched_insert_nops
== sched_finish_none
)
17068 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
17069 n_groups
= pad_groups (dump
, sched_verbose
,
17070 current_sched_info
->prev_head
,
17071 current_sched_info
->next_tail
);
17073 n_groups
= redefine_groups (dump
, sched_verbose
,
17074 current_sched_info
->prev_head
,
17075 current_sched_info
->next_tail
);
17077 if (sched_verbose
>= 6)
17079 fprintf (dump
, "ngroups = %d\n", n_groups
);
17080 print_rtl (dump
, current_sched_info
->prev_head
);
17081 fprintf (dump
, "Done finish_sched\n");
17086 /* Length in units of the trampoline for entering a nested function. */
17089 rs6000_trampoline_size (void)
17093 switch (DEFAULT_ABI
)
17096 gcc_unreachable ();
17099 ret
= (TARGET_32BIT
) ? 12 : 24;
17104 ret
= (TARGET_32BIT
) ? 40 : 48;
17111 /* Emit RTL insns to initialize the variable parts of a trampoline.
17112 FNADDR is an RTX for the address of the function's pure code.
17113 CXT is an RTX for the static chain value for the function. */
17116 rs6000_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
17118 enum machine_mode pmode
= Pmode
;
17119 int regsize
= (TARGET_32BIT
) ? 4 : 8;
17120 rtx ctx_reg
= force_reg (pmode
, cxt
);
17122 switch (DEFAULT_ABI
)
17125 gcc_unreachable ();
17127 /* Macros to shorten the code expansions below. */
17128 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17129 #define MEM_PLUS(addr,offset) \
17130 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17132 /* Under AIX, just build the 3 word function descriptor */
17135 rtx fn_reg
= gen_reg_rtx (pmode
);
17136 rtx toc_reg
= gen_reg_rtx (pmode
);
17137 emit_move_insn (fn_reg
, MEM_DEREF (fnaddr
));
17138 emit_move_insn (toc_reg
, MEM_PLUS (fnaddr
, regsize
));
17139 emit_move_insn (MEM_DEREF (addr
), fn_reg
);
17140 emit_move_insn (MEM_PLUS (addr
, regsize
), toc_reg
);
17141 emit_move_insn (MEM_PLUS (addr
, 2*regsize
), ctx_reg
);
17145 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17148 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
17149 FALSE
, VOIDmode
, 4,
17151 GEN_INT (rs6000_trampoline_size ()), SImode
,
17161 /* Table of valid machine attributes. */
17163 const struct attribute_spec rs6000_attribute_table
[] =
17165 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17166 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
},
17167 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
17168 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
17169 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17170 SUBTARGET_ATTRIBUTE_TABLE
,
17172 { NULL
, 0, 0, false, false, false, NULL
}
17175 /* Handle the "altivec" attribute. The attribute may have
17176 arguments as follows:
17178 __attribute__((altivec(vector__)))
17179 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17180 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17182 and may appear more than once (e.g., 'vector bool char') in a
17183 given declaration. */
17186 rs6000_handle_altivec_attribute (tree
*node
,
17187 tree name ATTRIBUTE_UNUSED
,
17189 int flags ATTRIBUTE_UNUSED
,
17190 bool *no_add_attrs
)
17192 tree type
= *node
, result
= NULL_TREE
;
17193 enum machine_mode mode
;
17196 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
17197 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
17198 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
17201 while (POINTER_TYPE_P (type
)
17202 || TREE_CODE (type
) == FUNCTION_TYPE
17203 || TREE_CODE (type
) == METHOD_TYPE
17204 || TREE_CODE (type
) == ARRAY_TYPE
)
17205 type
= TREE_TYPE (type
);
17207 mode
= TYPE_MODE (type
);
17209 /* Check for invalid AltiVec type qualifiers. */
17210 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
17213 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17214 else if (rs6000_warn_altivec_long
)
17215 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17217 else if (type
== long_long_unsigned_type_node
17218 || type
== long_long_integer_type_node
)
17219 error ("use of %<long long%> in AltiVec types is invalid");
17220 else if (type
== double_type_node
)
17221 error ("use of %<double%> in AltiVec types is invalid");
17222 else if (type
== long_double_type_node
)
17223 error ("use of %<long double%> in AltiVec types is invalid");
17224 else if (type
== boolean_type_node
)
17225 error ("use of boolean types in AltiVec types is invalid");
17226 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
17227 error ("use of %<complex%> in AltiVec types is invalid");
17229 switch (altivec_type
)
17232 unsigned_p
= TYPE_UNSIGNED (type
);
17236 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
17239 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
17242 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
17244 case SFmode
: result
= V4SF_type_node
; break;
17245 /* If the user says 'vector int bool', we may be handed the 'bool'
17246 attribute _before_ the 'vector' attribute, and so select the
17247 proper type in the 'b' case below. */
17248 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
17256 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
17257 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
17258 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
17265 case V8HImode
: result
= pixel_V8HI_type_node
;
17271 if (result
&& result
!= type
&& TYPE_READONLY (type
))
17272 result
= build_qualified_type (result
, TYPE_QUAL_CONST
);
17274 *no_add_attrs
= true; /* No need to hang on to the attribute. */
17277 *node
= reconstruct_complex_type (*node
, result
);
17282 /* AltiVec defines four built-in scalar types that serve as vector
17283 elements; we must teach the compiler how to mangle them. */
17285 static const char *
17286 rs6000_mangle_fundamental_type (tree type
)
17288 if (type
== bool_char_type_node
) return "U6__boolc";
17289 if (type
== bool_short_type_node
) return "U6__bools";
17290 if (type
== pixel_type_node
) return "u7__pixel";
17291 if (type
== bool_int_type_node
) return "U6__booli";
17293 /* For all other types, use normal C++ mangling. */
17297 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17298 struct attribute_spec.handler. */
17301 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
17302 tree args ATTRIBUTE_UNUSED
,
17303 int flags ATTRIBUTE_UNUSED
,
17304 bool *no_add_attrs
)
17306 if (TREE_CODE (*node
) != FUNCTION_TYPE
17307 && TREE_CODE (*node
) != FIELD_DECL
17308 && TREE_CODE (*node
) != TYPE_DECL
)
17310 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
17311 IDENTIFIER_POINTER (name
));
17312 *no_add_attrs
= true;
17318 /* Set longcall attributes on all functions declared when
17319 rs6000_default_long_calls is true. */
17321 rs6000_set_default_type_attributes (tree type
)
17323 if (rs6000_default_long_calls
17324 && (TREE_CODE (type
) == FUNCTION_TYPE
17325 || TREE_CODE (type
) == METHOD_TYPE
))
17326 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
17328 TYPE_ATTRIBUTES (type
));
17331 /* Return a reference suitable for calling a function with the
17332 longcall attribute. */
17335 rs6000_longcall_ref (rtx call_ref
)
17337 const char *call_name
;
17340 if (GET_CODE (call_ref
) != SYMBOL_REF
)
17343 /* System V adds '.' to the internal name, so skip them. */
17344 call_name
= XSTR (call_ref
, 0);
17345 if (*call_name
== '.')
17347 while (*call_name
== '.')
17350 node
= get_identifier (call_name
);
17351 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
17354 return force_reg (Pmode
, call_ref
);
17357 #ifdef USING_ELFOS_H
17359 /* A get_unnamed_section callback, used for switching to toc_section. */
17362 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
17364 if (DEFAULT_ABI
== ABI_AIX
17365 && TARGET_MINIMAL_TOC
17366 && !TARGET_RELOCATABLE
)
17368 if (!toc_initialized
)
17370 toc_initialized
= 1;
17371 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
17372 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
17373 fprintf (asm_out_file
, "\t.tc ");
17374 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
17375 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
17376 fprintf (asm_out_file
, "\n");
17378 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
17379 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
17380 fprintf (asm_out_file
, " = .+32768\n");
17383 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
17385 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
17386 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
17389 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
17390 if (!toc_initialized
)
17392 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
17393 fprintf (asm_out_file
, " = .+32768\n");
17394 toc_initialized
= 1;
17399 /* Implement TARGET_ASM_INIT_SECTIONS. */
17402 rs6000_elf_asm_init_sections (void)
17405 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
17408 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
17409 SDATA2_SECTION_ASM_OP
);
17412 /* Implement TARGET_SELECT_RTX_SECTION. */
17415 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
17416 unsigned HOST_WIDE_INT align
)
17418 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
17419 return toc_section
;
17421 return default_elf_select_rtx_section (mode
, x
, align
);
17424 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
17427 rs6000_elf_select_section (tree decl
, int reloc
,
17428 unsigned HOST_WIDE_INT align
)
17430 /* Pretend that we're always building for a shared library when
17431 ABI_AIX, because otherwise we end up with dynamic relocations
17432 in read-only sections. This happens for function pointers,
17433 references to vtables in typeinfo, and probably other cases. */
17434 return default_elf_select_section_1 (decl
, reloc
, align
,
17435 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
17438 /* A C statement to build up a unique section name, expressed as a
17439 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17440 RELOC indicates whether the initial value of EXP requires
17441 link-time relocations. If you do not define this macro, GCC will use
17442 the symbol name prefixed by `.' as the section name. Note - this
17443 macro can now be called for uninitialized data items as well as
17444 initialized data and functions. */
17447 rs6000_elf_unique_section (tree decl
, int reloc
)
17449 /* As above, pretend that we're always building for a shared library
17450 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17451 default_unique_section_1 (decl
, reloc
,
17452 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
17455 /* For a SYMBOL_REF, set generic flags and then perform some
17456 target-specific processing.
17458 When the AIX ABI is requested on a non-AIX system, replace the
17459 function name with the real name (with a leading .) rather than the
17460 function descriptor name. This saves a lot of overriding code to
17461 read the prefixes. */
17464 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
17466 default_encode_section_info (decl
, rtl
, first
);
17469 && TREE_CODE (decl
) == FUNCTION_DECL
17471 && DEFAULT_ABI
== ABI_AIX
)
17473 rtx sym_ref
= XEXP (rtl
, 0);
17474 size_t len
= strlen (XSTR (sym_ref
, 0));
17475 char *str
= alloca (len
+ 2);
17477 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
17478 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
17483 rs6000_elf_in_small_data_p (tree decl
)
17485 if (rs6000_sdata
== SDATA_NONE
)
17488 /* We want to merge strings, so we never consider them small data. */
17489 if (TREE_CODE (decl
) == STRING_CST
)
17492 /* Functions are never in the small data area. */
17493 if (TREE_CODE (decl
) == FUNCTION_DECL
)
17496 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
17498 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
17499 if (strcmp (section
, ".sdata") == 0
17500 || strcmp (section
, ".sdata2") == 0
17501 || strcmp (section
, ".sbss") == 0
17502 || strcmp (section
, ".sbss2") == 0
17503 || strcmp (section
, ".PPC.EMB.sdata0") == 0
17504 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
17509 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
17512 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
17513 /* If it's not public, and we're not going to reference it there,
17514 there's no need to put it in the small data section. */
17515 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
17522 #endif /* USING_ELFOS_H */
17525 /* Return a REG that occurs in ADDR with coefficient 1.
17526 ADDR can be effectively incremented by incrementing REG.
17528 r0 is special and we must not select it as an address
17529 register by this routine since our caller will try to
17530 increment the returned register via an "la" instruction. */
17533 find_addr_reg (rtx addr
)
17535 while (GET_CODE (addr
) == PLUS
)
17537 if (GET_CODE (XEXP (addr
, 0)) == REG
17538 && REGNO (XEXP (addr
, 0)) != 0)
17539 addr
= XEXP (addr
, 0);
17540 else if (GET_CODE (XEXP (addr
, 1)) == REG
17541 && REGNO (XEXP (addr
, 1)) != 0)
17542 addr
= XEXP (addr
, 1);
17543 else if (CONSTANT_P (XEXP (addr
, 0)))
17544 addr
= XEXP (addr
, 1);
17545 else if (CONSTANT_P (XEXP (addr
, 1)))
17546 addr
= XEXP (addr
, 0);
17548 gcc_unreachable ();
17550 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
17555 rs6000_fatal_bad_address (rtx op
)
17557 fatal_insn ("bad address", op
);
17562 static tree branch_island_list
= 0;
17564 /* Remember to generate a branch island for far calls to the given
17568 add_compiler_branch_island (tree label_name
, tree function_name
,
17571 tree branch_island
= build_tree_list (function_name
, label_name
);
17572 TREE_TYPE (branch_island
) = build_int_cst (NULL_TREE
, line_number
);
17573 TREE_CHAIN (branch_island
) = branch_island_list
;
17574 branch_island_list
= branch_island
;
17577 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17578 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17579 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17580 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17582 /* Generate far-jump branch islands for everything on the
17583 branch_island_list. Invoked immediately after the last instruction
17584 of the epilogue has been emitted; the branch-islands must be
17585 appended to, and contiguous with, the function body. Mach-O stubs
17586 are generated in machopic_output_stub(). */
17589 macho_branch_islands (void)
17592 tree branch_island
;
17594 for (branch_island
= branch_island_list
;
17596 branch_island
= TREE_CHAIN (branch_island
))
17598 const char *label
=
17599 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island
));
17601 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island
));
17602 char name_buf
[512];
17603 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17604 if (name
[0] == '*' || name
[0] == '&')
17605 strcpy (name_buf
, name
+1);
17609 strcpy (name_buf
+1, name
);
17611 strcpy (tmp_buf
, "\n");
17612 strcat (tmp_buf
, label
);
17613 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17614 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
17615 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
17616 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17619 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
17620 strcat (tmp_buf
, label
);
17621 strcat (tmp_buf
, "_pic\n");
17622 strcat (tmp_buf
, label
);
17623 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
17625 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
17626 strcat (tmp_buf
, name_buf
);
17627 strcat (tmp_buf
, " - ");
17628 strcat (tmp_buf
, label
);
17629 strcat (tmp_buf
, "_pic)\n");
17631 strcat (tmp_buf
, "\tmtlr r0\n");
17633 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
17634 strcat (tmp_buf
, name_buf
);
17635 strcat (tmp_buf
, " - ");
17636 strcat (tmp_buf
, label
);
17637 strcat (tmp_buf
, "_pic)\n");
17639 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
17643 strcat (tmp_buf
, ":\nlis r12,hi16(");
17644 strcat (tmp_buf
, name_buf
);
17645 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
17646 strcat (tmp_buf
, name_buf
);
17647 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
17649 output_asm_insn (tmp_buf
, 0);
17650 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17651 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
17652 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
17653 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17656 branch_island_list
= 0;
17659 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17660 already there or not. */
17663 no_previous_def (tree function_name
)
17665 tree branch_island
;
17666 for (branch_island
= branch_island_list
;
17668 branch_island
= TREE_CHAIN (branch_island
))
17669 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
17674 /* GET_PREV_LABEL gets the label name from the previous definition of
17678 get_prev_label (tree function_name
)
17680 tree branch_island
;
17681 for (branch_island
= branch_island_list
;
17683 branch_island
= TREE_CHAIN (branch_island
))
17684 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
17685 return BRANCH_ISLAND_LABEL_NAME (branch_island
);
17689 /* INSN is either a function call or a millicode call. It may have an
17690 unconditional jump in its delay slot.
17692 CALL_DEST is the routine we are calling. */
17695 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
17696 int cookie_operand_number
)
17698 static char buf
[256];
17699 if (GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
17700 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
17703 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
17705 if (no_previous_def (funname
))
17707 int line_number
= 0;
17708 rtx label_rtx
= gen_label_rtx ();
17709 char *label_buf
, temp_buf
[256];
17710 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
17711 CODE_LABEL_NUMBER (label_rtx
));
17712 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
17713 labelname
= get_identifier (label_buf
);
17714 for (; insn
&& GET_CODE (insn
) != NOTE
; insn
= PREV_INSN (insn
));
17716 line_number
= NOTE_LINE_NUMBER (insn
);
17717 add_compiler_branch_island (labelname
, funname
, line_number
);
17720 labelname
= get_prev_label (funname
);
17722 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17723 instruction will reach 'foo', otherwise link as 'bl L42'".
17724 "L42" should be a 'branch island', that will do a far jump to
17725 'foo'. Branch islands are generated in
17726 macho_branch_islands(). */
17727 sprintf (buf
, "jbsr %%z%d,%.246s",
17728 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
17731 sprintf (buf
, "bl %%z%d", dest_operand_number
);
17735 /* Generate PIC and indirect symbol stubs. */
17738 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
17740 unsigned int length
;
17741 char *symbol_name
, *lazy_ptr_name
;
17742 char *local_label_0
;
17743 static int label
= 0;
17745 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17746 symb
= (*targetm
.strip_name_encoding
) (symb
);
17749 length
= strlen (symb
);
17750 symbol_name
= alloca (length
+ 32);
17751 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
17753 lazy_ptr_name
= alloca (length
+ 32);
17754 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
17757 switch_to_section (machopic_picsymbol_stub1_section
);
17759 switch_to_section (machopic_symbol_stub1_section
);
17763 fprintf (file
, "\t.align 5\n");
17765 fprintf (file
, "%s:\n", stub
);
17766 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
17769 local_label_0
= alloca (sizeof ("\"L00000000000$spb\""));
17770 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
17772 fprintf (file
, "\tmflr r0\n");
17773 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
17774 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
17775 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
17776 lazy_ptr_name
, local_label_0
);
17777 fprintf (file
, "\tmtlr r0\n");
17778 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
17779 (TARGET_64BIT
? "ldu" : "lwzu"),
17780 lazy_ptr_name
, local_label_0
);
17781 fprintf (file
, "\tmtctr r12\n");
17782 fprintf (file
, "\tbctr\n");
17786 fprintf (file
, "\t.align 4\n");
17788 fprintf (file
, "%s:\n", stub
);
17789 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
17791 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
17792 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
17793 (TARGET_64BIT
? "ldu" : "lwzu"),
17795 fprintf (file
, "\tmtctr r12\n");
17796 fprintf (file
, "\tbctr\n");
17799 switch_to_section (machopic_lazy_symbol_ptr_section
);
17800 fprintf (file
, "%s:\n", lazy_ptr_name
);
17801 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
17802 fprintf (file
, "%sdyld_stub_binding_helper\n",
17803 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
17806 /* Legitimize PIC addresses. If the address is already
17807 position-independent, we return ORIG. Newly generated
17808 position-independent addresses go into a reg. This is REG if non
17809 zero, otherwise we allocate register(s) as necessary. */
17811 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
17814 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
17819 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
17820 reg
= gen_reg_rtx (Pmode
);
17822 if (GET_CODE (orig
) == CONST
)
17826 if (GET_CODE (XEXP (orig
, 0)) == PLUS
17827 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
17830 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
17832 /* Use a different reg for the intermediate value, as
17833 it will be marked UNCHANGING. */
17834 reg_temp
= no_new_pseudos
? reg
: gen_reg_rtx (Pmode
);
17835 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
17838 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
17841 if (GET_CODE (offset
) == CONST_INT
)
17843 if (SMALL_INT (offset
))
17844 return plus_constant (base
, INTVAL (offset
));
17845 else if (! reload_in_progress
&& ! reload_completed
)
17846 offset
= force_reg (Pmode
, offset
);
17849 rtx mem
= force_const_mem (Pmode
, orig
);
17850 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
17853 return gen_rtx_PLUS (Pmode
, base
, offset
);
17856 /* Fall back on generic machopic code. */
17857 return machopic_legitimize_pic_address (orig
, mode
, reg
);
17860 /* Output a .machine directive for the Darwin assembler, and call
17861 the generic start_file routine. */
17864 rs6000_darwin_file_start (void)
17866 static const struct
17872 { "ppc64", "ppc64", MASK_64BIT
},
17873 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
17874 { "power4", "ppc970", 0 },
17875 { "G5", "ppc970", 0 },
17876 { "7450", "ppc7450", 0 },
17877 { "7400", "ppc7400", MASK_ALTIVEC
},
17878 { "G4", "ppc7400", 0 },
17879 { "750", "ppc750", 0 },
17880 { "740", "ppc750", 0 },
17881 { "G3", "ppc750", 0 },
17882 { "604e", "ppc604e", 0 },
17883 { "604", "ppc604", 0 },
17884 { "603e", "ppc603", 0 },
17885 { "603", "ppc603", 0 },
17886 { "601", "ppc601", 0 },
17887 { NULL
, "ppc", 0 } };
17888 const char *cpu_id
= "";
17891 rs6000_file_start ();
17893 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17894 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
17895 if (rs6000_select
[i
].set_arch_p
&& rs6000_select
[i
].string
17896 && rs6000_select
[i
].string
[0] != '\0')
17897 cpu_id
= rs6000_select
[i
].string
;
17899 /* Look through the mapping array. Pick the first name that either
17900 matches the argument, has a bit set in IF_SET that is also set
17901 in the target flags, or has a NULL name. */
17904 while (mapping
[i
].arg
!= NULL
17905 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
17906 && (mapping
[i
].if_set
& target_flags
) == 0)
17909 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
17912 #endif /* TARGET_MACHO */
17915 static unsigned int
17916 rs6000_elf_section_type_flags (tree decl
, const char *name
, int reloc
)
17918 return default_section_type_flags_1 (decl
, name
, reloc
,
17919 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
17922 /* Record an element in the table of global constructors. SYMBOL is
17923 a SYMBOL_REF of the function to be called; PRIORITY is a number
17924 between 0 and MAX_INIT_PRIORITY.
17926 This differs from default_named_section_asm_out_constructor in
17927 that we have special handling for -mrelocatable. */
17930 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
17932 const char *section
= ".ctors";
17935 if (priority
!= DEFAULT_INIT_PRIORITY
)
17937 sprintf (buf
, ".ctors.%.5u",
17938 /* Invert the numbering so the linker puts us in the proper
17939 order; constructors are run from right to left, and the
17940 linker sorts in increasing order. */
17941 MAX_INIT_PRIORITY
- priority
);
17945 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
17946 assemble_align (POINTER_SIZE
);
17948 if (TARGET_RELOCATABLE
)
17950 fputs ("\t.long (", asm_out_file
);
17951 output_addr_const (asm_out_file
, symbol
);
17952 fputs (")@fixup\n", asm_out_file
);
17955 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
17959 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
17961 const char *section
= ".dtors";
17964 if (priority
!= DEFAULT_INIT_PRIORITY
)
17966 sprintf (buf
, ".dtors.%.5u",
17967 /* Invert the numbering so the linker puts us in the proper
17968 order; constructors are run from right to left, and the
17969 linker sorts in increasing order. */
17970 MAX_INIT_PRIORITY
- priority
);
17974 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
17975 assemble_align (POINTER_SIZE
);
17977 if (TARGET_RELOCATABLE
)
17979 fputs ("\t.long (", asm_out_file
);
17980 output_addr_const (asm_out_file
, symbol
);
17981 fputs (")@fixup\n", asm_out_file
);
17984 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
17988 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
17992 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
17993 ASM_OUTPUT_LABEL (file
, name
);
17994 fputs (DOUBLE_INT_ASM_OP
, file
);
17995 rs6000_output_function_entry (file
, name
);
17996 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
17999 fputs ("\t.size\t", file
);
18000 assemble_name (file
, name
);
18001 fputs (",24\n\t.type\t.", file
);
18002 assemble_name (file
, name
);
18003 fputs (",@function\n", file
);
18004 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
18006 fputs ("\t.globl\t.", file
);
18007 assemble_name (file
, name
);
18012 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
18013 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
18014 rs6000_output_function_entry (file
, name
);
18015 fputs (":\n", file
);
18019 if (TARGET_RELOCATABLE
18020 && !TARGET_SECURE_PLT
18021 && (get_pool_size () != 0 || current_function_profile
)
18026 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
18028 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
18029 fprintf (file
, "\t.long ");
18030 assemble_name (file
, buf
);
18032 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
18033 assemble_name (file
, buf
);
18037 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
18038 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
18040 if (DEFAULT_ABI
== ABI_AIX
)
18042 const char *desc_name
, *orig_name
;
18044 orig_name
= (*targetm
.strip_name_encoding
) (name
);
18045 desc_name
= orig_name
;
18046 while (*desc_name
== '.')
18049 if (TREE_PUBLIC (decl
))
18050 fprintf (file
, "\t.globl %s\n", desc_name
);
18052 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
18053 fprintf (file
, "%s:\n", desc_name
);
18054 fprintf (file
, "\t.long %s\n", orig_name
);
18055 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
18056 if (DEFAULT_ABI
== ABI_AIX
)
18057 fputs ("\t.long 0\n", file
);
18058 fprintf (file
, "\t.previous\n");
18060 ASM_OUTPUT_LABEL (file
, name
);
18064 rs6000_elf_end_indicate_exec_stack (void)
18067 file_end_indicate_exec_stack ();
18073 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
18075 fputs (GLOBAL_ASM_OP
, stream
);
18076 RS6000_OUTPUT_BASENAME (stream
, name
);
18077 putc ('\n', stream
);
18080 /* A get_unnamed_decl callback, used for read-only sections. PTR
18081 points to the section string variable. */
18084 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
18086 fprintf (asm_out_file
, "\t.csect %s[RO],3\n",
18087 *(const char *const *) directive
);
18090 /* Likewise for read-write sections. */
18093 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
18095 fprintf (asm_out_file
, "\t.csect %s[RW],3\n",
18096 *(const char *const *) directive
);
18099 /* A get_unnamed_section callback, used for switching to toc_section. */
18102 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
18104 if (TARGET_MINIMAL_TOC
)
18106 /* toc_section is always selected at least once from
18107 rs6000_xcoff_file_start, so this is guaranteed to
18108 always be defined once and only once in each file. */
18109 if (!toc_initialized
)
18111 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
18112 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
18113 toc_initialized
= 1;
18115 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
18116 (TARGET_32BIT
? "" : ",3"));
18119 fputs ("\t.toc\n", asm_out_file
);
18122 /* Implement TARGET_ASM_INIT_SECTIONS. */
18125 rs6000_xcoff_asm_init_sections (void)
18127 read_only_data_section
18128 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
18129 &xcoff_read_only_section_name
);
18131 private_data_section
18132 = get_unnamed_section (SECTION_WRITE
,
18133 rs6000_xcoff_output_readwrite_section_asm_op
,
18134 &xcoff_private_data_section_name
);
18136 read_only_private_data_section
18137 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
18138 &xcoff_private_data_section_name
);
18141 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
18143 readonly_data_section
= read_only_data_section
;
18144 exception_section
= data_section
;
18148 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
18149 tree decl ATTRIBUTE_UNUSED
)
18152 static const char * const suffix
[3] = { "PR", "RO", "RW" };
18154 if (flags
& SECTION_CODE
)
18156 else if (flags
& SECTION_WRITE
)
18161 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
18162 (flags
& SECTION_CODE
) ? "." : "",
18163 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
18167 rs6000_xcoff_select_section (tree decl
, int reloc
,
18168 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
18170 if (decl_readonly_section_1 (decl
, reloc
, 1))
18172 if (TREE_PUBLIC (decl
))
18173 return read_only_data_section
;
18175 return read_only_private_data_section
;
18179 if (TREE_PUBLIC (decl
))
18180 return data_section
;
18182 return private_data_section
;
18187 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
18191 /* Use select_section for private and uninitialized data. */
18192 if (!TREE_PUBLIC (decl
)
18193 || DECL_COMMON (decl
)
18194 || DECL_INITIAL (decl
) == NULL_TREE
18195 || DECL_INITIAL (decl
) == error_mark_node
18196 || (flag_zero_initialized_in_bss
18197 && initializer_zerop (DECL_INITIAL (decl
))))
18200 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
18201 name
= (*targetm
.strip_name_encoding
) (name
);
18202 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
18205 /* Select section for constant in constant pool.
18207 On RS/6000, all constants are in the private read-only data area.
18208 However, if this is being placed in the TOC it must be output as a
18212 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
18213 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
18215 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
18216 return toc_section
;
18218 return read_only_private_data_section
;
18221 /* Remove any trailing [DS] or the like from the symbol name. */
18223 static const char *
18224 rs6000_xcoff_strip_name_encoding (const char *name
)
18229 len
= strlen (name
);
18230 if (name
[len
- 1] == ']')
18231 return ggc_alloc_string (name
, len
- 4);
18236 /* Section attributes. AIX is always PIC. */
18238 static unsigned int
18239 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
18241 unsigned int align
;
18242 unsigned int flags
= default_section_type_flags_1 (decl
, name
, reloc
, 1);
18244 /* Align to at least UNIT size. */
18245 if (flags
& SECTION_CODE
)
18246 align
= MIN_UNITS_PER_WORD
;
18248 /* Increase alignment of large objects if not already stricter. */
18249 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
18250 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
18251 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
18253 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
18256 /* Output at beginning of assembler file.
18258 Initialize the section names for the RS/6000 at this point.
18260 Specify filename, including full path, to assembler.
18262 We want to go into the TOC section so at least one .toc will be emitted.
18263 Also, in order to output proper .bs/.es pairs, we need at least one static
18264 [RW] section emitted.
18266 Finally, declare mcount when profiling to make the assembler happy. */
18269 rs6000_xcoff_file_start (void)
18271 rs6000_gen_section_name (&xcoff_bss_section_name
,
18272 main_input_filename
, ".bss_");
18273 rs6000_gen_section_name (&xcoff_private_data_section_name
,
18274 main_input_filename
, ".rw_");
18275 rs6000_gen_section_name (&xcoff_read_only_section_name
,
18276 main_input_filename
, ".ro_");
18278 fputs ("\t.file\t", asm_out_file
);
18279 output_quoted_string (asm_out_file
, main_input_filename
);
18280 fputc ('\n', asm_out_file
);
18281 if (write_symbols
!= NO_DEBUG
)
18282 switch_to_section (private_data_section
);
18283 switch_to_section (text_section
);
18285 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
18286 rs6000_file_start ();
18289 /* Output at end of assembler file.
18290 On the RS/6000, referencing data should automatically pull in text. */
18293 rs6000_xcoff_file_end (void)
18295 switch_to_section (text_section
);
18296 fputs ("_section_.text:\n", asm_out_file
);
18297 switch_to_section (data_section
);
18298 fputs (TARGET_32BIT
18299 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18302 #endif /* TARGET_XCOFF */
18304 /* Compute a (partial) cost for rtx X. Return true if the complete
18305 cost has been computed, and false if subexpressions should be
18306 scanned. In either case, *TOTAL contains the cost result. */
18309 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
18311 enum machine_mode mode
= GET_MODE (x
);
18315 /* On the RS/6000, if it is valid in the insn, it is free. */
18317 if (((outer_code
== SET
18318 || outer_code
== PLUS
18319 || outer_code
== MINUS
)
18320 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
18321 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')))
18322 || (outer_code
== AND
18323 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18324 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
18325 mode
== SImode
? 'L' : 'J'))
18326 || mask_operand (x
, mode
)
18328 && mask64_operand (x
, DImode
))))
18329 || ((outer_code
== IOR
|| outer_code
== XOR
)
18330 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18331 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
18332 mode
== SImode
? 'L' : 'J'))))
18333 || outer_code
== ASHIFT
18334 || outer_code
== ASHIFTRT
18335 || outer_code
== LSHIFTRT
18336 || outer_code
== ROTATE
18337 || outer_code
== ROTATERT
18338 || outer_code
== ZERO_EXTRACT
18339 || (outer_code
== MULT
18340 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I'))
18341 || ((outer_code
== DIV
|| outer_code
== UDIV
18342 || outer_code
== MOD
|| outer_code
== UMOD
)
18343 && exact_log2 (INTVAL (x
)) >= 0)
18344 || (outer_code
== COMPARE
18345 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
18346 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')))
18347 || (outer_code
== EQ
18348 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
18349 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18350 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
18351 mode
== SImode
? 'L' : 'J'))))
18352 || (outer_code
== GTU
18353 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I'))
18354 || (outer_code
== LTU
18355 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'P')))
18360 else if ((outer_code
== PLUS
18361 && reg_or_add_cint_operand (x
, VOIDmode
))
18362 || (outer_code
== MINUS
18363 && reg_or_sub_cint_operand (x
, VOIDmode
))
18364 || ((outer_code
== SET
18365 || outer_code
== IOR
18366 || outer_code
== XOR
)
18368 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
18370 *total
= COSTS_N_INSNS (1);
18377 && ((outer_code
== AND
18378 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18379 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')
18380 || mask_operand (x
, DImode
)
18381 || mask64_operand (x
, DImode
)))
18382 || ((outer_code
== IOR
|| outer_code
== XOR
)
18383 && CONST_DOUBLE_HIGH (x
) == 0
18384 && (CONST_DOUBLE_LOW (x
)
18385 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)))
18390 else if (mode
== DImode
18391 && (outer_code
== SET
18392 || outer_code
== IOR
18393 || outer_code
== XOR
)
18394 && CONST_DOUBLE_HIGH (x
) == 0)
18396 *total
= COSTS_N_INSNS (1);
18405 /* When optimizing for size, MEM should be slightly more expensive
18406 than generating address, e.g., (plus (reg) (const)).
18407 L1 cache latency is about two instructions. */
18408 *total
= optimize_size
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18416 if (mode
== DFmode
)
18418 if (GET_CODE (XEXP (x
, 0)) == MULT
)
18420 /* FNMA accounted in outer NEG. */
18421 if (outer_code
== NEG
)
18422 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
18424 *total
= rs6000_cost
->dmul
;
18427 *total
= rs6000_cost
->fp
;
18429 else if (mode
== SFmode
)
18431 /* FNMA accounted in outer NEG. */
18432 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
18435 *total
= rs6000_cost
->fp
;
18438 *total
= COSTS_N_INSNS (1);
18442 if (mode
== DFmode
)
18444 if (GET_CODE (XEXP (x
, 0)) == MULT
)
18446 /* FNMA accounted in outer NEG. */
18447 if (outer_code
== NEG
)
18450 *total
= rs6000_cost
->dmul
;
18453 *total
= rs6000_cost
->fp
;
18455 else if (mode
== SFmode
)
18457 /* FNMA accounted in outer NEG. */
18458 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
18461 *total
= rs6000_cost
->fp
;
18464 *total
= COSTS_N_INSNS (1);
18468 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
18469 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x
, 1)), 'I'))
18471 if (INTVAL (XEXP (x
, 1)) >= -256
18472 && INTVAL (XEXP (x
, 1)) <= 255)
18473 *total
= rs6000_cost
->mulsi_const9
;
18475 *total
= rs6000_cost
->mulsi_const
;
18477 /* FMA accounted in outer PLUS/MINUS. */
18478 else if ((mode
== DFmode
|| mode
== SFmode
)
18479 && (outer_code
== PLUS
|| outer_code
== MINUS
))
18481 else if (mode
== DFmode
)
18482 *total
= rs6000_cost
->dmul
;
18483 else if (mode
== SFmode
)
18484 *total
= rs6000_cost
->fp
;
18485 else if (mode
== DImode
)
18486 *total
= rs6000_cost
->muldi
;
18488 *total
= rs6000_cost
->mulsi
;
18493 if (FLOAT_MODE_P (mode
))
18495 *total
= mode
== DFmode
? rs6000_cost
->ddiv
18496 : rs6000_cost
->sdiv
;
18503 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
18504 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
18506 if (code
== DIV
|| code
== MOD
)
18508 *total
= COSTS_N_INSNS (2);
18511 *total
= COSTS_N_INSNS (1);
18515 if (GET_MODE (XEXP (x
, 1)) == DImode
)
18516 *total
= rs6000_cost
->divdi
;
18518 *total
= rs6000_cost
->divsi
;
18520 /* Add in shift and subtract for MOD. */
18521 if (code
== MOD
|| code
== UMOD
)
18522 *total
+= COSTS_N_INSNS (2);
18526 *total
= COSTS_N_INSNS (4);
18530 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
18541 *total
= COSTS_N_INSNS (1);
18549 /* Handle mul_highpart. */
18550 if (outer_code
== TRUNCATE
18551 && GET_CODE (XEXP (x
, 0)) == MULT
)
18553 if (mode
== DImode
)
18554 *total
= rs6000_cost
->muldi
;
18556 *total
= rs6000_cost
->mulsi
;
18559 else if (outer_code
== AND
)
18562 *total
= COSTS_N_INSNS (1);
18567 if (GET_CODE (XEXP (x
, 0)) == MEM
)
18570 *total
= COSTS_N_INSNS (1);
18576 if (!FLOAT_MODE_P (mode
))
18578 *total
= COSTS_N_INSNS (1);
18584 case UNSIGNED_FLOAT
:
18587 case FLOAT_TRUNCATE
:
18588 *total
= rs6000_cost
->fp
;
18592 if (mode
== DFmode
)
18595 *total
= rs6000_cost
->fp
;
18599 switch (XINT (x
, 1))
18602 *total
= rs6000_cost
->fp
;
18614 *total
= COSTS_N_INSNS (1);
18617 else if (FLOAT_MODE_P (mode
)
18618 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18620 *total
= rs6000_cost
->fp
;
18628 /* Carry bit requires mode == Pmode.
18629 NEG or PLUS already counted so only add one. */
18631 && (outer_code
== NEG
|| outer_code
== PLUS
))
18633 *total
= COSTS_N_INSNS (1);
18636 if (outer_code
== SET
)
18638 if (XEXP (x
, 1) == const0_rtx
)
18640 *total
= COSTS_N_INSNS (2);
18643 else if (mode
== Pmode
)
18645 *total
= COSTS_N_INSNS (3);
18654 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
18656 *total
= COSTS_N_INSNS (2);
18660 if (outer_code
== COMPARE
)
18674 /* A C expression returning the cost of moving data from a register of class
18675 CLASS1 to one of CLASS2. */
18678 rs6000_register_move_cost (enum machine_mode mode
,
18679 enum reg_class from
, enum reg_class to
)
18681 /* Moves from/to GENERAL_REGS. */
18682 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
18683 || reg_classes_intersect_p (from
, GENERAL_REGS
))
18685 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
18688 if (from
== FLOAT_REGS
|| from
== ALTIVEC_REGS
)
18689 return (rs6000_memory_move_cost (mode
, from
, 0)
18690 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, 0));
18692 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18694 else if (from
== CR_REGS
)
18698 /* A move will cost one instruction per GPR moved. */
18699 return 2 * hard_regno_nregs
[0][mode
];
18702 /* Moving between two similar registers is just one instruction. */
18703 else if (reg_classes_intersect_p (to
, from
))
18704 return mode
== TFmode
? 4 : 2;
18706 /* Everything else has to go through GENERAL_REGS. */
18708 return (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
18709 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
18712 /* A C expressions returning the cost of moving data of MODE from a register to
18716 rs6000_memory_move_cost (enum machine_mode mode
, enum reg_class
class,
18717 int in ATTRIBUTE_UNUSED
)
18719 if (reg_classes_intersect_p (class, GENERAL_REGS
))
18720 return 4 * hard_regno_nregs
[0][mode
];
18721 else if (reg_classes_intersect_p (class, FLOAT_REGS
))
18722 return 4 * hard_regno_nregs
[32][mode
];
18723 else if (reg_classes_intersect_p (class, ALTIVEC_REGS
))
18724 return 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
18726 return 4 + rs6000_register_move_cost (mode
, class, GENERAL_REGS
);
18729 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18730 Assumes no trapping math and finite arguments. */
18733 rs6000_emit_swdivsf (rtx res
, rtx n
, rtx d
)
18735 rtx x0
, e0
, e1
, y1
, u0
, v0
, one
;
18737 x0
= gen_reg_rtx (SFmode
);
18738 e0
= gen_reg_rtx (SFmode
);
18739 e1
= gen_reg_rtx (SFmode
);
18740 y1
= gen_reg_rtx (SFmode
);
18741 u0
= gen_reg_rtx (SFmode
);
18742 v0
= gen_reg_rtx (SFmode
);
18743 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
18745 /* x0 = 1./d estimate */
18746 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
18747 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, d
),
18749 /* e0 = 1. - d * x0 */
18750 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
18751 gen_rtx_MINUS (SFmode
, one
,
18752 gen_rtx_MULT (SFmode
, d
, x0
))));
18753 /* e1 = e0 + e0 * e0 */
18754 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
18755 gen_rtx_PLUS (SFmode
,
18756 gen_rtx_MULT (SFmode
, e0
, e0
), e0
)));
18757 /* y1 = x0 + e1 * x0 */
18758 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
18759 gen_rtx_PLUS (SFmode
,
18760 gen_rtx_MULT (SFmode
, e1
, x0
), x0
)));
18762 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
18763 gen_rtx_MULT (SFmode
, n
, y1
)));
18764 /* v0 = n - d * u0 */
18765 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
18766 gen_rtx_MINUS (SFmode
, n
,
18767 gen_rtx_MULT (SFmode
, d
, u0
))));
18768 /* res = u0 + v0 * y1 */
18769 emit_insn (gen_rtx_SET (VOIDmode
, res
,
18770 gen_rtx_PLUS (SFmode
,
18771 gen_rtx_MULT (SFmode
, v0
, y1
), u0
)));
18774 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18775 Assumes no trapping math and finite arguments. */
18778 rs6000_emit_swdivdf (rtx res
, rtx n
, rtx d
)
18780 rtx x0
, e0
, e1
, e2
, y1
, y2
, y3
, u0
, v0
, one
;
18782 x0
= gen_reg_rtx (DFmode
);
18783 e0
= gen_reg_rtx (DFmode
);
18784 e1
= gen_reg_rtx (DFmode
);
18785 e2
= gen_reg_rtx (DFmode
);
18786 y1
= gen_reg_rtx (DFmode
);
18787 y2
= gen_reg_rtx (DFmode
);
18788 y3
= gen_reg_rtx (DFmode
);
18789 u0
= gen_reg_rtx (DFmode
);
18790 v0
= gen_reg_rtx (DFmode
);
18791 one
= force_reg (DFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, DFmode
));
18793 /* x0 = 1./d estimate */
18794 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
18795 gen_rtx_UNSPEC (DFmode
, gen_rtvec (1, d
),
18797 /* e0 = 1. - d * x0 */
18798 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
18799 gen_rtx_MINUS (DFmode
, one
,
18800 gen_rtx_MULT (SFmode
, d
, x0
))));
18801 /* y1 = x0 + e0 * x0 */
18802 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
18803 gen_rtx_PLUS (DFmode
,
18804 gen_rtx_MULT (DFmode
, e0
, x0
), x0
)));
18806 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
18807 gen_rtx_MULT (DFmode
, e0
, e0
)));
18808 /* y2 = y1 + e1 * y1 */
18809 emit_insn (gen_rtx_SET (VOIDmode
, y2
,
18810 gen_rtx_PLUS (DFmode
,
18811 gen_rtx_MULT (DFmode
, e1
, y1
), y1
)));
18813 emit_insn (gen_rtx_SET (VOIDmode
, e2
,
18814 gen_rtx_MULT (DFmode
, e1
, e1
)));
18815 /* y3 = y2 + e2 * y2 */
18816 emit_insn (gen_rtx_SET (VOIDmode
, y3
,
18817 gen_rtx_PLUS (DFmode
,
18818 gen_rtx_MULT (DFmode
, e2
, y2
), y2
)));
18820 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
18821 gen_rtx_MULT (DFmode
, n
, y3
)));
18822 /* v0 = n - d * u0 */
18823 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
18824 gen_rtx_MINUS (DFmode
, n
,
18825 gen_rtx_MULT (DFmode
, d
, u0
))));
18826 /* res = u0 + v0 * y3 */
18827 emit_insn (gen_rtx_SET (VOIDmode
, res
,
18828 gen_rtx_PLUS (DFmode
,
18829 gen_rtx_MULT (DFmode
, v0
, y3
), u0
)));
18832 /* Return an RTX representing where to find the function value of a
18833 function returning MODE. */
18835 rs6000_complex_function_value (enum machine_mode mode
)
18837 unsigned int regno
;
18839 enum machine_mode inner
= GET_MODE_INNER (mode
);
18840 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
18842 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18843 regno
= FP_ARG_RETURN
;
18846 regno
= GP_ARG_RETURN
;
18848 /* 32-bit is OK since it'll go in r3/r4. */
18849 if (TARGET_32BIT
&& inner_bytes
>= 4)
18850 return gen_rtx_REG (mode
, regno
);
18853 if (inner_bytes
>= 8)
18854 return gen_rtx_REG (mode
, regno
);
18856 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
18858 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
18859 GEN_INT (inner_bytes
));
18860 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
18863 /* Define how to find the value returned by a function.
18864 VALTYPE is the data type of the value (as a tree).
18865 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18866 otherwise, FUNC is 0.
18868 On the SPE, both FPs and vectors are returned in r3.
18870 On RS/6000 an integer value is in r3 and a floating-point value is in
18871 fp1, unless -msoft-float. */
18874 rs6000_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
18876 enum machine_mode mode
;
18877 unsigned int regno
;
18879 /* Special handling for structs in darwin64. */
18880 if (rs6000_darwin64_abi
18881 && TYPE_MODE (valtype
) == BLKmode
18882 && TREE_CODE (valtype
) == RECORD_TYPE
18883 && int_size_in_bytes (valtype
) > 0)
18885 CUMULATIVE_ARGS valcum
;
18889 valcum
.fregno
= FP_ARG_MIN_REG
;
18890 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
18891 /* Do a trial code generation as if this were going to be passed as
18892 an argument; if any part goes in memory, we return NULL. */
18893 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, 1, true);
18896 /* Otherwise fall through to standard ABI rules. */
18899 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
18901 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18902 return gen_rtx_PARALLEL (DImode
,
18904 gen_rtx_EXPR_LIST (VOIDmode
,
18905 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
18907 gen_rtx_EXPR_LIST (VOIDmode
,
18908 gen_rtx_REG (SImode
,
18909 GP_ARG_RETURN
+ 1),
18912 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
18914 return gen_rtx_PARALLEL (DCmode
,
18916 gen_rtx_EXPR_LIST (VOIDmode
,
18917 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
18919 gen_rtx_EXPR_LIST (VOIDmode
,
18920 gen_rtx_REG (SImode
,
18921 GP_ARG_RETURN
+ 1),
18923 gen_rtx_EXPR_LIST (VOIDmode
,
18924 gen_rtx_REG (SImode
,
18925 GP_ARG_RETURN
+ 2),
18927 gen_rtx_EXPR_LIST (VOIDmode
,
18928 gen_rtx_REG (SImode
,
18929 GP_ARG_RETURN
+ 3),
18932 if ((INTEGRAL_TYPE_P (valtype
)
18933 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
18934 || POINTER_TYPE_P (valtype
))
18935 mode
= TARGET_32BIT
? SImode
: DImode
;
18937 mode
= TYPE_MODE (valtype
);
18939 if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18940 regno
= FP_ARG_RETURN
;
18941 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
18942 && targetm
.calls
.split_complex_arg
)
18943 return rs6000_complex_function_value (mode
);
18944 else if (TREE_CODE (valtype
) == VECTOR_TYPE
18945 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
18946 && ALTIVEC_VECTOR_MODE (mode
))
18947 regno
= ALTIVEC_ARG_RETURN
;
18948 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
18949 && (mode
== DFmode
|| mode
== DCmode
))
18950 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
18952 regno
= GP_ARG_RETURN
;
18954 return gen_rtx_REG (mode
, regno
);
18957 /* Define how to find the value returned by a library function
18958 assuming the value has mode MODE. */
18960 rs6000_libcall_value (enum machine_mode mode
)
18962 unsigned int regno
;
18964 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
18966 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18967 return gen_rtx_PARALLEL (DImode
,
18969 gen_rtx_EXPR_LIST (VOIDmode
,
18970 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
18972 gen_rtx_EXPR_LIST (VOIDmode
,
18973 gen_rtx_REG (SImode
,
18974 GP_ARG_RETURN
+ 1),
18978 if (SCALAR_FLOAT_MODE_P (mode
)
18979 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18980 regno
= FP_ARG_RETURN
;
18981 else if (ALTIVEC_VECTOR_MODE (mode
)
18982 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
18983 regno
= ALTIVEC_ARG_RETURN
;
18984 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
18985 return rs6000_complex_function_value (mode
);
18986 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
18987 && (mode
== DFmode
|| mode
== DCmode
))
18988 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
18990 regno
= GP_ARG_RETURN
;
18992 return gen_rtx_REG (mode
, regno
);
18995 /* Define the offset between two registers, FROM to be eliminated and its
18996 replacement TO, at the start of a routine. */
18998 rs6000_initial_elimination_offset (int from
, int to
)
19000 rs6000_stack_t
*info
= rs6000_stack_info ();
19001 HOST_WIDE_INT offset
;
19003 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
19004 offset
= info
->push_p
? 0 : -info
->total_size
;
19005 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
19007 offset
= info
->push_p
? 0 : -info
->total_size
;
19008 if (FRAME_GROWS_DOWNWARD
)
19009 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
19011 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
19012 offset
= FRAME_GROWS_DOWNWARD
19013 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
19015 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
19016 offset
= info
->total_size
;
19017 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
19018 offset
= info
->push_p
? info
->total_size
: 0;
19019 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
19022 gcc_unreachable ();
19027 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19030 rs6000_is_opaque_type (tree type
)
19032 return (type
== opaque_V2SI_type_node
19033 || type
== opaque_V2SF_type_node
19034 || type
== opaque_p_V2SI_type_node
19035 || type
== opaque_V4SI_type_node
);
19039 rs6000_dwarf_register_span (rtx reg
)
19044 && (SPE_VECTOR_MODE (GET_MODE (reg
))
19045 || (TARGET_E500_DOUBLE
&& GET_MODE (reg
) == DFmode
)))
19050 regno
= REGNO (reg
);
19052 /* The duality of the SPE register size wreaks all kinds of havoc.
19053 This is a way of distinguishing r0 in 32-bits from r0 in
19056 gen_rtx_PARALLEL (VOIDmode
,
19059 gen_rtx_REG (SImode
, regno
+ 1200),
19060 gen_rtx_REG (SImode
, regno
))
19062 gen_rtx_REG (SImode
, regno
),
19063 gen_rtx_REG (SImode
, regno
+ 1200)));
19066 /* Map internal gcc register numbers to DWARF2 register numbers. */
19069 rs6000_dbx_register_number (unsigned int regno
)
19071 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
19073 if (regno
== MQ_REGNO
)
19075 if (regno
== LINK_REGISTER_REGNUM
)
19077 if (regno
== COUNT_REGISTER_REGNUM
)
19079 if (CR_REGNO_P (regno
))
19080 return regno
- CR0_REGNO
+ 86;
19081 if (regno
== XER_REGNO
)
19083 if (ALTIVEC_REGNO_P (regno
))
19084 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
19085 if (regno
== VRSAVE_REGNO
)
19087 if (regno
== VSCR_REGNO
)
19089 if (regno
== SPE_ACC_REGNO
)
19091 if (regno
== SPEFSCR_REGNO
)
19093 /* SPE high reg number. We get these values of regno from
19094 rs6000_dwarf_register_span. */
19095 gcc_assert (regno
>= 1200 && regno
< 1232);
19099 /* target hook eh_return_filter_mode */
19100 static enum machine_mode
19101 rs6000_eh_return_filter_mode (void)
19103 return TARGET_32BIT
? SImode
: word_mode
;
19106 /* Target hook for vector_mode_supported_p. */
19108 rs6000_vector_mode_supported_p (enum machine_mode mode
)
19111 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
19114 else if (TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
19121 /* Target hook for invalid_arg_for_unprototyped_fn. */
19122 static const char *
19123 invalid_arg_for_unprototyped_fn (tree typelist
, tree funcdecl
, tree val
)
19125 return (!rs6000_darwin64_abi
19127 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
19128 && (funcdecl
== NULL_TREE
19129 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
19130 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
19131 ? N_("AltiVec argument passed to unprototyped function")
19135 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19136 setup by using __stack_chk_fail_local hidden function instead of
19137 calling __stack_chk_fail directly. Otherwise it is better to call
19138 __stack_chk_fail directly. */
19141 rs6000_stack_protect_fail (void)
19143 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
19144 ? default_hidden_stack_protect_fail ()
19145 : default_external_stack_protect_fail ();
19148 #include "gt-rs6000.h"