1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
21 ;; Return 1 for anything except PARALLEL.
22 (define_predicate "any_operand"
23 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
25 ;; Return 1 for any PARALLEL.
26 (define_predicate "any_parallel_operand"
27 (match_code "parallel"))
29 ;; Return 1 if op is COUNT register.
30 (define_predicate "count_register_operand"
31 (and (match_code "reg")
32 (match_test "REGNO (op) == COUNT_REGISTER_REGNUM
33 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
35 ;; Return 1 if op is an Altivec register.
36 (define_predicate "altivec_register_operand"
37 (and (match_operand 0 "register_operand")
38 (match_test "GET_CODE (op) != REG
39 || ALTIVEC_REGNO_P (REGNO (op))
40 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
42 ;; Return 1 if op is XER register.
43 (define_predicate "xer_operand"
44 (and (match_code "reg")
45 (match_test "XER_REGNO_P (REGNO (op))")))
47 ;; Return 1 if op is a signed 5-bit constant integer.
48 (define_predicate "s5bit_cint_operand"
49 (and (match_code "const_int")
50 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
52 ;; Return 1 if op is a unsigned 5-bit constant integer.
53 (define_predicate "u5bit_cint_operand"
54 (and (match_code "const_int")
55 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
57 ;; Return 1 if op is a signed 8-bit constant integer.
58 ;; Integer multiplication complete more quickly
59 (define_predicate "s8bit_cint_operand"
60 (and (match_code "const_int")
61 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
63 ;; Return 1 if op is a constant integer that can fit in a D field.
64 (define_predicate "short_cint_operand"
65 (and (match_code "const_int")
66 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')")))
68 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
69 (define_predicate "u_short_cint_operand"
70 (and (match_code "const_int")
71 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')")))
73 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
74 (define_predicate "non_short_cint_operand"
75 (and (match_code "const_int")
76 (match_test "(unsigned HOST_WIDE_INT)
77 (INTVAL (op) + 0x8000) >= 0x10000")))
79 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
80 (define_predicate "exact_log2_cint_operand"
81 (and (match_code "const_int")
82 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
84 ;; Return 1 if op is a register that is not special.
85 (define_predicate "gpc_reg_operand"
86 (and (match_operand 0 "register_operand")
87 (match_test "GET_CODE (op) != REG
88 || (REGNO (op) >= ARG_POINTER_REGNUM
89 && !XER_REGNO_P (REGNO (op)))
90 || REGNO (op) < MQ_REGNO")))
92 ;; Return 1 if op is a register that is a condition register field.
93 (define_predicate "cc_reg_operand"
94 (and (match_operand 0 "register_operand")
95 (match_test "GET_CODE (op) != REG
96 || REGNO (op) > LAST_VIRTUAL_REGISTER
97 || CR_REGNO_P (REGNO (op))")))
99 ;; Return 1 if op is a register that is a condition register field not cr0.
100 (define_predicate "cc_reg_not_cr0_operand"
101 (and (match_operand 0 "register_operand")
102 (match_test "GET_CODE (op) != REG
103 || REGNO (op) > LAST_VIRTUAL_REGISTER
104 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
106 ;; Return 1 if op is a constant integer valid for D field
107 ;; or non-special register register.
108 (define_predicate "reg_or_short_operand"
109 (if_then_else (match_code "const_int")
110 (match_operand 0 "short_cint_operand")
111 (match_operand 0 "gpc_reg_operand")))
113 ;; Return 1 if op is a constant integer valid whose negation is valid for
114 ;; D field or non-special register register.
115 ;; Do not allow a constant zero because all patterns that call this
116 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
117 ;; or equal to const, which does not work for zero.
118 (define_predicate "reg_or_neg_short_operand"
119 (if_then_else (match_code "const_int")
120 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'P')
121 && INTVAL (op) != 0")
122 (match_operand 0 "gpc_reg_operand")))
124 ;; Return 1 if op is a constant integer valid for DS field
125 ;; or non-special register.
126 (define_predicate "reg_or_aligned_short_operand"
127 (if_then_else (match_code "const_int")
128 (and (match_operand 0 "short_cint_operand")
129 (match_test "!(INTVAL (op) & 3)"))
130 (match_operand 0 "gpc_reg_operand")))
132 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
133 ;; or non-special register.
134 (define_predicate "reg_or_u_short_operand"
135 (if_then_else (match_code "const_int")
136 (match_operand 0 "u_short_cint_operand")
137 (match_operand 0 "gpc_reg_operand")))
139 ;; Return 1 if op is any constant integer
140 ;; or non-special register.
141 (define_predicate "reg_or_cint_operand"
142 (ior (match_code "const_int")
143 (match_operand 0 "gpc_reg_operand")))
145 ;; Return 1 if op is a constant integer valid for addition
146 ;; or non-special register.
147 (define_predicate "reg_or_add_cint_operand"
148 (if_then_else (match_code "const_int")
149 (match_test "(HOST_BITS_PER_WIDE_INT == 32
150 && (mode == SImode || INTVAL (op) < 0x7fff8000))
151 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
152 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
153 (match_operand 0 "gpc_reg_operand")))
155 ;; Return 1 if op is a constant integer valid for subtraction
156 ;; or non-special register.
157 (define_predicate "reg_or_sub_cint_operand"
158 (if_then_else (match_code "const_int")
159 (match_test "(HOST_BITS_PER_WIDE_INT == 32
160 && (mode == SImode || - INTVAL (op) < 0x7fff8000))
161 || ((unsigned HOST_WIDE_INT) (- INTVAL (op)
163 ? 0x80000000 : 0x80008000))
164 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
165 (match_operand 0 "gpc_reg_operand")))
167 ;; Return 1 if op is any 32-bit unsigned constant integer
168 ;; or non-special register.
169 (define_predicate "reg_or_logical_cint_operand"
170 (if_then_else (match_code "const_int")
171 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
173 || ((INTVAL (op) & GET_MODE_MASK (mode)
174 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
175 (if_then_else (match_code "const_double")
176 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
178 && CONST_DOUBLE_HIGH (op) == 0")
179 (match_operand 0 "gpc_reg_operand"))))
181 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
182 ;; with no more than one instruction per word.
183 (define_predicate "easy_fp_constant"
184 (match_code "const_double")
189 if (GET_MODE (op) != mode
190 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
193 /* Consider all constants with -msoft-float to be easy. */
194 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
198 /* If we are using V.4 style PIC, consider all constants to be hard. */
199 if (flag_pic && DEFAULT_ABI == ABI_V4)
202 #ifdef TARGET_RELOCATABLE
203 /* Similarly if we are using -mrelocatable, consider all constants
205 if (TARGET_RELOCATABLE)
212 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
213 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
215 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
216 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
217 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
218 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
221 /* Force constants to memory before reload to utilize
222 compress_float_constant.
223 Avoid this when flag_unsafe_math_optimizations is enabled
224 because RDIV division to reciprocal optimization is not able
225 to regenerate the division. */
226 if (TARGET_E500_DOUBLE
227 || (!reload_in_progress && !reload_completed
228 && !flag_unsafe_math_optimizations))
231 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
232 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
234 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
235 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
238 /* The constant 0.f is easy. */
239 if (op == CONST0_RTX (SFmode))
242 /* Force constants to memory before reload to utilize
243 compress_float_constant.
244 Avoid this when flag_unsafe_math_optimizations is enabled
245 because RDIV division to reciprocal optimization is not able
246 to regenerate the division. */
247 if (!reload_in_progress && !reload_completed
248 && !flag_unsafe_math_optimizations)
251 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
252 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
254 return num_insns_constant_wide (k[0]) == 1;
257 return ((TARGET_POWERPC64
258 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
259 || (num_insns_constant (op, DImode) <= 2));
269 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
270 ;; vector register without using memory.
271 (define_predicate "easy_vector_constant"
272 (match_code "const_vector")
274 if (ALTIVEC_VECTOR_MODE (mode))
276 if (zero_constant (op, mode))
278 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
281 return easy_altivec_constant (op, mode);
284 if (SPE_VECTOR_MODE (mode))
287 if (zero_constant (op, mode))
289 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
292 /* Limit SPE vectors to 15 bits signed. These we can generate with:
297 I don't know how efficient it would be to allow bigger constants,
298 considering we'll have an extra 'ori' for every 'li'. I doubt 5
299 instructions is better than a 64-bit memory load, but I don't
300 have the e500 timing specs. */
301 if (mode == V2SImode)
303 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
304 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
305 return cst >= -0x7fff && cst <= 0x7fff
306 && cst2 >= -0x7fff && cst2 <= 0x7fff;
313 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
314 (define_predicate "easy_vector_constant_add_self"
315 (and (match_code "const_vector")
316 (and (match_test "TARGET_ALTIVEC")
317 (match_test "easy_altivec_constant (op, mode)")))
319 rtx last = CONST_VECTOR_ELT (op, GET_MODE_NUNITS (mode) - 1);
320 HOST_WIDE_INT val = ((INTVAL (last) & 0xff) ^ 0x80) - 0x80;
321 return EASY_VECTOR_15_ADD_SELF (val);
324 ;; Return 1 if operand is constant zero (scalars and vectors).
325 (define_predicate "zero_constant"
326 (and (match_code "const_int,const_double,const_vector")
327 (match_test "op == CONST0_RTX (mode)")))
329 ;; Return 1 if operand is 0.0.
330 ;; or non-special register register field no cr0
331 (define_predicate "zero_fp_constant"
332 (and (match_code "const_double")
333 (match_test "SCALAR_FLOAT_MODE_P (mode)
334 && op == CONST0_RTX (mode)")))
336 ;; Return 1 if the operand is in volatile memory. Note that during the
337 ;; RTL generation phase, memory_operand does not return TRUE for volatile
338 ;; memory references. So this function allows us to recognize volatile
339 ;; references where it's safe.
340 (define_predicate "volatile_mem_operand"
341 (and (and (match_code "mem")
342 (match_test "MEM_VOLATILE_P (op)"))
343 (if_then_else (match_test "reload_completed")
344 (match_operand 0 "memory_operand")
345 (if_then_else (match_test "reload_in_progress")
346 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
347 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
349 ;; Return 1 if the operand is an offsettable memory operand.
350 (define_predicate "offsettable_mem_operand"
351 (and (match_code "mem")
352 (match_test "offsettable_address_p (reload_completed
353 || reload_in_progress,
354 mode, XEXP (op, 0))")))
356 ;; Return 1 if the operand is a memory operand with an address divisible by 4
357 (define_predicate "word_offset_memref_operand"
358 (and (match_operand 0 "memory_operand")
359 (match_test "GET_CODE (XEXP (op, 0)) != PLUS
360 || ! REG_P (XEXP (XEXP (op, 0), 0))
361 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT
362 || INTVAL (XEXP (XEXP (op, 0), 1)) % 4 == 0")))
364 ;; Return 1 if the operand is an indexed or indirect memory operand.
365 (define_predicate "indexed_or_indirect_operand"
370 && ALTIVEC_VECTOR_MODE (mode)
371 && GET_CODE (op) == AND
372 && GET_CODE (XEXP (op, 1)) == CONST_INT
373 && INTVAL (XEXP (op, 1)) == -16)
376 return indexed_or_indirect_address (op, mode);
379 ;; Return 1 if the operand is an indexed or indirect address.
380 (define_special_predicate "indexed_or_indirect_address"
381 (and (match_test "REG_P (op)
382 || (GET_CODE (op) == PLUS
383 /* Omit testing REG_P (XEXP (op, 0)). */
384 && REG_P (XEXP (op, 1)))")
385 (match_operand 0 "address_operand")))
387 ;; Used for the destination of the fix_truncdfsi2 expander.
388 ;; If stfiwx will be used, the result goes to memory; otherwise,
389 ;; we're going to emit a store and a load of a subreg, so the dest is a
391 (define_predicate "fix_trunc_dest_operand"
392 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
393 (match_operand 0 "memory_operand")
394 (match_operand 0 "gpc_reg_operand")))
396 ;; Return 1 if the operand is either a non-special register or can be used
397 ;; as the operand of a `mode' add insn.
398 (define_predicate "add_operand"
399 (if_then_else (match_code "const_int")
400 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
401 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')")
402 (match_operand 0 "gpc_reg_operand")))
404 ;; Return 1 if OP is a constant but not a valid add_operand.
405 (define_predicate "non_add_cint_operand"
406 (and (match_code "const_int")
407 (match_test "!CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
408 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')")))
410 ;; Return 1 if the operand is a constant that can be used as the operand
412 (define_predicate "logical_const_operand"
413 (match_code "const_int,const_double")
415 HOST_WIDE_INT opl, oph;
417 if (GET_CODE (op) == CONST_INT)
419 opl = INTVAL (op) & GET_MODE_MASK (mode);
421 if (HOST_BITS_PER_WIDE_INT <= 32
422 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
425 else if (GET_CODE (op) == CONST_DOUBLE)
427 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT);
429 opl = CONST_DOUBLE_LOW (op);
430 oph = CONST_DOUBLE_HIGH (op);
437 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
438 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
441 ;; Return 1 if the operand is a non-special register or a constant that
442 ;; can be used as the operand of an OR or XOR.
443 (define_predicate "logical_operand"
444 (ior (match_operand 0 "gpc_reg_operand")
445 (match_operand 0 "logical_const_operand")))
447 ;; Return 1 if op is a constant that is not a logical operand, but could
448 ;; be split into one.
449 (define_predicate "non_logical_cint_operand"
450 (and (match_code "const_int,const_double")
451 (and (not (match_operand 0 "logical_operand"))
452 (match_operand 0 "reg_or_logical_cint_operand"))))
454 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
455 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
456 ;; transitions). Reject all ones and all zeros, since these should have
457 ;; been optimized away and confuse the making of MB and ME.
458 (define_predicate "mask_operand"
459 (match_code "const_int")
461 HOST_WIDE_INT c, lsb;
465 if (TARGET_POWERPC64)
467 /* Fail if the mask is not 32-bit. */
468 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
471 /* Fail if the mask wraps around because the upper 32-bits of the
472 mask will all be 1s, contrary to GCC's internal view. */
473 if ((c & 0x80000001) == 0x80000001)
477 /* We don't change the number of transitions by inverting,
478 so make sure we start with the LS bit zero. */
482 /* Reject all zeros or all ones. */
486 /* Find the first transition. */
489 /* Invert to look for a second transition. */
492 /* Erase first transition. */
495 /* Find the second transition (if any). */
498 /* Match if all the bits above are 1's (or c is zero). */
502 ;; Return 1 for the PowerPC64 rlwinm corner case.
503 (define_predicate "mask_operand_wrap"
504 (match_code "const_int")
506 HOST_WIDE_INT c, lsb;
510 if ((c & 0x80000001) != 0x80000001)
524 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
525 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
526 ;; transition). Reject all zeros, since zero should have been
527 ;; optimized away and confuses the making of MB and ME.
528 (define_predicate "mask64_operand"
529 (match_code "const_int")
531 HOST_WIDE_INT c, lsb;
535 /* Reject all zeros. */
539 /* We don't change the number of transitions by inverting,
540 so make sure we start with the LS bit zero. */
544 /* Find the first transition. */
547 /* Match if all the bits above are 1's (or c is zero). */
551 ;; Like mask64_operand, but allow up to three transitions. This
552 ;; predicate is used by insn patterns that generate two rldicl or
553 ;; rldicr machine insns.
554 (define_predicate "mask64_2_operand"
555 (match_code "const_int")
557 HOST_WIDE_INT c, lsb;
561 /* Disallow all zeros. */
565 /* We don't change the number of transitions by inverting,
566 so make sure we start with the LS bit zero. */
570 /* Find the first transition. */
573 /* Invert to look for a second transition. */
576 /* Erase first transition. */
579 /* Find the second transition. */
582 /* Invert to look for a third transition. */
585 /* Erase second transition. */
588 /* Find the third transition (if any). */
591 /* Match if all the bits above are 1's (or c is zero). */
595 ;; Like and_operand, but also match constants that can be implemented
596 ;; with two rldicl or rldicr insns.
597 (define_predicate "and64_2_operand"
598 (ior (match_operand 0 "mask64_2_operand")
599 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
600 (match_operand 0 "gpc_reg_operand")
601 (match_operand 0 "logical_operand"))))
603 ;; Return 1 if the operand is either a non-special register or a
604 ;; constant that can be used as the operand of a logical AND.
605 (define_predicate "and_operand"
606 (ior (match_operand 0 "mask_operand")
607 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
608 (match_operand 0 "mask64_operand"))
609 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
610 (match_operand 0 "gpc_reg_operand")
611 (match_operand 0 "logical_operand")))))
613 ;; Return 1 if the operand is either a logical operand or a short cint operand.
614 (define_predicate "scc_eq_operand"
615 (ior (match_operand 0 "logical_operand")
616 (match_operand 0 "short_cint_operand")))
618 ;; Return 1 if the operand is a general non-special register or memory operand.
619 (define_predicate "reg_or_mem_operand"
620 (if_then_else (match_code "mem")
621 (ior (match_operand 0 "memory_operand")
622 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
623 (match_operand 0 "volatile_mem_operand")))
624 (match_operand 0 "gpc_reg_operand")))
626 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
627 (define_predicate "reg_or_none500mem_operand"
628 (if_then_else (match_code "mem")
629 (and (match_test "!TARGET_E500_DOUBLE")
630 (ior (match_operand 0 "memory_operand")
631 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
632 (match_operand 0 "volatile_mem_operand"))))
633 (match_operand 0 "gpc_reg_operand")))
635 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
636 (define_predicate "zero_reg_mem_operand"
637 (ior (match_operand 0 "zero_fp_constant")
638 (match_operand 0 "reg_or_mem_operand")))
640 ;; Return 1 if the operand is a general register or memory operand without
641 ;; pre_inc or pre_dec, which produces invalid form of PowerPC lwa
643 (define_predicate "lwa_operand"
644 (match_code "reg,subreg,mem")
648 if (reload_completed && GET_CODE (inner) == SUBREG)
649 inner = SUBREG_REG (inner);
651 return gpc_reg_operand (inner, mode)
652 || (memory_operand (inner, mode)
653 && GET_CODE (XEXP (inner, 0)) != PRE_INC
654 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
655 && (GET_CODE (XEXP (inner, 0)) != PLUS
656 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
657 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
660 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
661 (define_predicate "symbol_ref_operand"
662 (and (match_code "symbol_ref")
663 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
664 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
666 ;; Return 1 if op is an operand that can be loaded via the GOT.
667 ;; or non-special register register field no cr0
668 (define_predicate "got_operand"
669 (match_code "symbol_ref,const,label_ref"))
671 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
672 ;; excluding labels involving addition.
673 (define_predicate "got_no_const_operand"
674 (match_code "symbol_ref,label_ref"))
676 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
677 (define_predicate "rs6000_tls_symbol_ref"
678 (and (match_code "symbol_ref")
679 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
681 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
682 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
683 (define_predicate "call_operand"
684 (if_then_else (match_code "reg")
685 (match_test "REGNO (op) == LINK_REGISTER_REGNUM
686 || REGNO (op) == COUNT_REGISTER_REGNUM
687 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
688 (match_code "symbol_ref")))
690 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
692 (define_predicate "current_file_function_operand"
693 (and (match_code "symbol_ref")
694 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
695 && (SYMBOL_REF_LOCAL_P (op)
696 || (op == XEXP (DECL_RTL (current_function_decl),
699 ;; Return 1 if this operand is a valid input for a move insn.
700 (define_predicate "input_operand"
701 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
702 const_double,const_vector,const_int,plus")
704 /* Memory is always valid. */
705 if (memory_operand (op, mode))
708 /* For floating-point, easy constants are valid. */
709 if (SCALAR_FLOAT_MODE_P (mode)
711 && easy_fp_constant (op, mode))
714 /* Allow any integer constant. */
715 if (GET_MODE_CLASS (mode) == MODE_INT
716 && (GET_CODE (op) == CONST_INT
717 || GET_CODE (op) == CONST_DOUBLE))
720 /* Allow easy vector constants. */
721 if (GET_CODE (op) == CONST_VECTOR
722 && easy_vector_constant (op, mode))
725 /* For floating-point or multi-word mode, the only remaining valid type
727 if (SCALAR_FLOAT_MODE_P (mode)
728 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
729 return register_operand (op, mode);
731 /* The only cases left are integral modes one word or smaller (we
732 do not get called for MODE_CC values). These can be in any
734 if (register_operand (op, mode))
737 /* A SYMBOL_REF referring to the TOC is valid. */
738 if (legitimate_constant_pool_address_p (op))
741 /* A constant pool expression (relative to the TOC) is valid */
742 if (toc_relative_expr_p (op))
745 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
747 if (DEFAULT_ABI == ABI_V4
748 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
749 && small_data_operand (op, Pmode))
755 ;; Return true if OP is an invalid SUBREG operation on the e500.
756 (define_predicate "rs6000_nonimmediate_operand"
757 (match_code "reg,subreg,mem")
759 if (TARGET_E500_DOUBLE
760 && GET_CODE (op) == SUBREG
761 && invalid_e500_subreg (op, mode))
764 return nonimmediate_operand (op, mode);
767 ;; Return true if operand is boolean operator.
768 (define_predicate "boolean_operator"
769 (match_code "and,ior,xor"))
771 ;; Return true if operand is OR-form of boolean operator.
772 (define_predicate "boolean_or_operator"
773 (match_code "ior,xor"))
775 ;; Return true if operand is an equality operator.
776 (define_special_predicate "equality_operator"
777 (match_code "eq,ne"))
779 ;; Return true if operand is MIN or MAX operator.
780 (define_predicate "min_max_operator"
781 (match_code "smin,smax,umin,umax"))
783 ;; Return 1 if OP is a comparison operation that is valid for a branch
784 ;; instruction. We check the opcode against the mode of the CC value.
785 ;; validate_condition_mode is an assertion.
786 (define_predicate "branch_comparison_operator"
787 (and (match_operand 0 "comparison_operator")
788 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
789 (match_test "validate_condition_mode (GET_CODE (op),
790 GET_MODE (XEXP (op, 0))),
793 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
794 ;; it must be a positive comparison.
795 (define_predicate "scc_comparison_operator"
796 (and (match_operand 0 "branch_comparison_operator")
797 (match_code "eq,lt,gt,ltu,gtu,unordered")))
799 ;; Return 1 if OP is a comparison operation that is valid for a branch
800 ;; insn, which is true if the corresponding bit in the CC register is set.
801 (define_predicate "branch_positive_comparison_operator"
802 (and (match_operand 0 "branch_comparison_operator")
803 (match_code "eq,lt,gt,ltu,gtu,unordered")))
805 ;; Return 1 is OP is a comparison operation that is valid for a trap insn.
806 (define_predicate "trap_comparison_operator"
807 (and (match_operand 0 "comparison_operator")
808 (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")))
810 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
811 (define_predicate "load_multiple_operation"
812 (match_code "parallel")
814 int count = XVECLEN (op, 0);
815 unsigned int dest_regno;
819 /* Perform a quick check so we don't blow up below. */
821 || GET_CODE (XVECEXP (op, 0, 0)) != SET
822 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
823 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
826 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
827 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
829 for (i = 1; i < count; i++)
831 rtx elt = XVECEXP (op, 0, i);
833 if (GET_CODE (elt) != SET
834 || GET_CODE (SET_DEST (elt)) != REG
835 || GET_MODE (SET_DEST (elt)) != SImode
836 || REGNO (SET_DEST (elt)) != dest_regno + i
837 || GET_CODE (SET_SRC (elt)) != MEM
838 || GET_MODE (SET_SRC (elt)) != SImode
839 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
840 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
841 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
842 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
849 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
850 ;; The second vector element is a CLOBBER.
851 (define_predicate "store_multiple_operation"
852 (match_code "parallel")
854 int count = XVECLEN (op, 0) - 1;
855 unsigned int src_regno;
859 /* Perform a quick check so we don't blow up below. */
861 || GET_CODE (XVECEXP (op, 0, 0)) != SET
862 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
863 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
866 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
867 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
869 for (i = 1; i < count; i++)
871 rtx elt = XVECEXP (op, 0, i + 1);
873 if (GET_CODE (elt) != SET
874 || GET_CODE (SET_SRC (elt)) != REG
875 || GET_MODE (SET_SRC (elt)) != SImode
876 || REGNO (SET_SRC (elt)) != src_regno + i
877 || GET_CODE (SET_DEST (elt)) != MEM
878 || GET_MODE (SET_DEST (elt)) != SImode
879 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
880 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
881 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
882 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
889 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
891 (define_predicate "save_world_operation"
892 (match_code "parallel")
897 int count = XVECLEN (op, 0);
903 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
904 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
907 for (i=1; i <= 18; i++)
909 elt = XVECEXP (op, 0, index++);
910 if (GET_CODE (elt) != SET
911 || GET_CODE (SET_DEST (elt)) != MEM
912 || ! memory_operand (SET_DEST (elt), DFmode)
913 || GET_CODE (SET_SRC (elt)) != REG
914 || GET_MODE (SET_SRC (elt)) != DFmode)
918 for (i=1; i <= 12; i++)
920 elt = XVECEXP (op, 0, index++);
921 if (GET_CODE (elt) != SET
922 || GET_CODE (SET_DEST (elt)) != MEM
923 || GET_CODE (SET_SRC (elt)) != REG
924 || GET_MODE (SET_SRC (elt)) != V4SImode)
928 for (i=1; i <= 19; i++)
930 elt = XVECEXP (op, 0, index++);
931 if (GET_CODE (elt) != SET
932 || GET_CODE (SET_DEST (elt)) != MEM
933 || ! memory_operand (SET_DEST (elt), Pmode)
934 || GET_CODE (SET_SRC (elt)) != REG
935 || GET_MODE (SET_SRC (elt)) != Pmode)
939 elt = XVECEXP (op, 0, index++);
940 if (GET_CODE (elt) != SET
941 || GET_CODE (SET_DEST (elt)) != MEM
942 || ! memory_operand (SET_DEST (elt), Pmode)
943 || GET_CODE (SET_SRC (elt)) != REG
944 || REGNO (SET_SRC (elt)) != CR2_REGNO
945 || GET_MODE (SET_SRC (elt)) != Pmode)
948 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
949 || GET_CODE (XVECEXP (op, 0, index++)) != USE
950 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
955 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
957 (define_predicate "restore_world_operation"
958 (match_code "parallel")
963 int count = XVECLEN (op, 0);
969 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
970 || GET_CODE (XVECEXP (op, 0, index++)) != USE
971 || GET_CODE (XVECEXP (op, 0, index++)) != USE
972 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
975 elt = XVECEXP (op, 0, index++);
976 if (GET_CODE (elt) != SET
977 || GET_CODE (SET_SRC (elt)) != MEM
978 || ! memory_operand (SET_SRC (elt), Pmode)
979 || GET_CODE (SET_DEST (elt)) != REG
980 || REGNO (SET_DEST (elt)) != CR2_REGNO
981 || GET_MODE (SET_DEST (elt)) != Pmode)
984 for (i=1; i <= 19; i++)
986 elt = XVECEXP (op, 0, index++);
987 if (GET_CODE (elt) != SET
988 || GET_CODE (SET_SRC (elt)) != MEM
989 || ! memory_operand (SET_SRC (elt), Pmode)
990 || GET_CODE (SET_DEST (elt)) != REG
991 || GET_MODE (SET_DEST (elt)) != Pmode)
995 for (i=1; i <= 12; i++)
997 elt = XVECEXP (op, 0, index++);
998 if (GET_CODE (elt) != SET
999 || GET_CODE (SET_SRC (elt)) != MEM
1000 || GET_CODE (SET_DEST (elt)) != REG
1001 || GET_MODE (SET_DEST (elt)) != V4SImode)
1005 for (i=1; i <= 18; i++)
1007 elt = XVECEXP (op, 0, index++);
1008 if (GET_CODE (elt) != SET
1009 || GET_CODE (SET_SRC (elt)) != MEM
1010 || ! memory_operand (SET_SRC (elt), DFmode)
1011 || GET_CODE (SET_DEST (elt)) != REG
1012 || GET_MODE (SET_DEST (elt)) != DFmode)
1016 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1017 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1018 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1019 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1020 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1025 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1026 (define_predicate "vrsave_operation"
1027 (match_code "parallel")
1029 int count = XVECLEN (op, 0);
1030 unsigned int dest_regno, src_regno;
1034 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1035 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1036 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1037 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1040 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1041 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1043 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1046 for (i = 1; i < count; i++)
1048 rtx elt = XVECEXP (op, 0, i);
1050 if (GET_CODE (elt) != CLOBBER
1051 && GET_CODE (elt) != SET)
1058 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1059 (define_predicate "mfcr_operation"
1060 (match_code "parallel")
1062 int count = XVECLEN (op, 0);
1065 /* Perform a quick check so we don't blow up below. */
1067 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1068 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1069 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1072 for (i = 0; i < count; i++)
1074 rtx exp = XVECEXP (op, 0, i);
1079 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1081 if (GET_CODE (src_reg) != REG
1082 || GET_MODE (src_reg) != CCmode
1083 || ! CR_REGNO_P (REGNO (src_reg)))
1086 if (GET_CODE (exp) != SET
1087 || GET_CODE (SET_DEST (exp)) != REG
1088 || GET_MODE (SET_DEST (exp)) != SImode
1089 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1091 unspec = SET_SRC (exp);
1092 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1094 if (GET_CODE (unspec) != UNSPEC
1095 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1096 || XVECLEN (unspec, 0) != 2
1097 || XVECEXP (unspec, 0, 0) != src_reg
1098 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1099 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1105 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1106 (define_predicate "mtcrf_operation"
1107 (match_code "parallel")
1109 int count = XVECLEN (op, 0);
1113 /* Perform a quick check so we don't blow up below. */
1115 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1116 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1117 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1119 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1121 if (GET_CODE (src_reg) != REG
1122 || GET_MODE (src_reg) != SImode
1123 || ! INT_REGNO_P (REGNO (src_reg)))
1126 for (i = 0; i < count; i++)
1128 rtx exp = XVECEXP (op, 0, i);
1132 if (GET_CODE (exp) != SET
1133 || GET_CODE (SET_DEST (exp)) != REG
1134 || GET_MODE (SET_DEST (exp)) != CCmode
1135 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1137 unspec = SET_SRC (exp);
1138 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1140 if (GET_CODE (unspec) != UNSPEC
1141 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1142 || XVECLEN (unspec, 0) != 2
1143 || XVECEXP (unspec, 0, 0) != src_reg
1144 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1145 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1151 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1152 (define_predicate "lmw_operation"
1153 (match_code "parallel")
1155 int count = XVECLEN (op, 0);
1156 unsigned int dest_regno;
1158 unsigned int base_regno;
1159 HOST_WIDE_INT offset;
1162 /* Perform a quick check so we don't blow up below. */
1164 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1165 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1166 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1169 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1170 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1173 || count != 32 - (int) dest_regno)
1176 if (legitimate_indirect_address_p (src_addr, 0))
1179 base_regno = REGNO (src_addr);
1180 if (base_regno == 0)
1183 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1185 offset = INTVAL (XEXP (src_addr, 1));
1186 base_regno = REGNO (XEXP (src_addr, 0));
1191 for (i = 0; i < count; i++)
1193 rtx elt = XVECEXP (op, 0, i);
1196 HOST_WIDE_INT newoffset;
1198 if (GET_CODE (elt) != SET
1199 || GET_CODE (SET_DEST (elt)) != REG
1200 || GET_MODE (SET_DEST (elt)) != SImode
1201 || REGNO (SET_DEST (elt)) != dest_regno + i
1202 || GET_CODE (SET_SRC (elt)) != MEM
1203 || GET_MODE (SET_SRC (elt)) != SImode)
1205 newaddr = XEXP (SET_SRC (elt), 0);
1206 if (legitimate_indirect_address_p (newaddr, 0))
1211 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1213 addr_reg = XEXP (newaddr, 0);
1214 newoffset = INTVAL (XEXP (newaddr, 1));
1218 if (REGNO (addr_reg) != base_regno
1219 || newoffset != offset + 4 * i)
1226 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1227 (define_predicate "stmw_operation"
1228 (match_code "parallel")
1230 int count = XVECLEN (op, 0);
1231 unsigned int src_regno;
1233 unsigned int base_regno;
1234 HOST_WIDE_INT offset;
1237 /* Perform a quick check so we don't blow up below. */
1239 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1240 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1241 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1244 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1245 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1248 || count != 32 - (int) src_regno)
1251 if (legitimate_indirect_address_p (dest_addr, 0))
1254 base_regno = REGNO (dest_addr);
1255 if (base_regno == 0)
1258 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1260 offset = INTVAL (XEXP (dest_addr, 1));
1261 base_regno = REGNO (XEXP (dest_addr, 0));
1266 for (i = 0; i < count; i++)
1268 rtx elt = XVECEXP (op, 0, i);
1271 HOST_WIDE_INT newoffset;
1273 if (GET_CODE (elt) != SET
1274 || GET_CODE (SET_SRC (elt)) != REG
1275 || GET_MODE (SET_SRC (elt)) != SImode
1276 || REGNO (SET_SRC (elt)) != src_regno + i
1277 || GET_CODE (SET_DEST (elt)) != MEM
1278 || GET_MODE (SET_DEST (elt)) != SImode)
1280 newaddr = XEXP (SET_DEST (elt), 0);
1281 if (legitimate_indirect_address_p (newaddr, 0))
1286 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1288 addr_reg = XEXP (newaddr, 0);
1289 newoffset = INTVAL (XEXP (newaddr, 1));
1293 if (REGNO (addr_reg) != base_regno
1294 || newoffset != offset + 4 * i)