old-autovect-branch/gcc/config/m32c/m32c.c

   1 /* Target Code for R8C/M16C/M32C
   2    Copyright (C) 2005
   3    Free Software Foundation, Inc.
   4    Contributed by Red Hat.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 2, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  21    02110-1301, USA.  */
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "coretypes.h"
  26 #include "tm.h"
  27 #include "rtl.h"
  28 #include "regs.h"
  29 #include "hard-reg-set.h"
  30 #include "real.h"
  31 #include "insn-config.h"
  32 #include "conditions.h"
  33 #include "insn-flags.h"
  34 #include "output.h"
  35 #include "insn-attr.h"
  36 #include "flags.h"
  37 #include "recog.h"
  38 #include "reload.h"
  39 #include "toplev.h"
  40 #include "obstack.h"
  41 #include "tree.h"
  42 #include "expr.h"
  43 #include "optabs.h"
  44 #include "except.h"
  45 #include "function.h"
  46 #include "ggc.h"
  47 #include "target.h"
  48 #include "target-def.h"
  49 #include "tm_p.h"
  50 #include "langhooks.h"
  51 #include "tree-gimple.h"
  52
  53 /* Prototypes */
  54
  55 /* Used by m32c_pushm_popm.  */
  56 typedef enum
  57 {
  58   PP_pushm,
  59   PP_popm,
  60   PP_justcount
  61 } Push_Pop_Type;
  62
  63 static tree interrupt_handler (tree *, tree, tree, int, bool *);
  64 static int interrupt_p (tree node);
  65 static bool m32c_asm_integer (rtx, unsigned int, int);
  66 static int m32c_comp_type_attributes (tree, tree);
  67 static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
  68 static struct machine_function *m32c_init_machine_status (void);
  69 static void m32c_insert_attributes (tree, tree *);
  70 static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
  71                                     tree, bool);
  72 static bool m32c_promote_prototypes (tree);
  73 static int m32c_pushm_popm (Push_Pop_Type);
  74 static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
  75 static rtx m32c_struct_value_rtx (tree, int);
  76 static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
  77 static int need_to_save (int);
  78
  79 #define streq(a,b) (strcmp ((a), (b)) == 0)
  80
  81 /* Internal support routines */
  82
  83 /* Debugging statements are tagged with DEBUG0 only so that they can
  84    be easily enabled individually, by replacing the '0' with '1' as
  85    needed.  */
  86 #define DEBUG0 0
  87 #define DEBUG1 1
  88
  89 #if DEBUG0
  90 /* This is needed by some of the commented-out debug statements
  91    below.  */
  92 static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
  93 #endif
  94 static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
  95
  96 /* These are all to support encode_pattern().  */
  97 static char pattern[30], *patternp;
  98 static GTY(()) rtx patternr[30];
  99 #define RTX_IS(x) (streq (pattern, x))
 100
 101 /* Some macros to simplify the logic throughout this file.  */
 102 #define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
 103 #define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
 104
 105 #define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
 106 #define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
 107
 108 /* We do most RTX matching by converting the RTX into a string, and
 109    using string compares.  This vastly simplifies the logic in many of
 110    the functions in this file.
 111
 112    On exit, pattern[] has the encoded string (use RTX_IS("...") to
 113    compare it) and patternr[] has pointers to the nodes in the RTX
 114    corresponding to each character in the encoded string.  The latter
 115    is mostly used by print_operand().
 116
 117    Unrecognized patterns have '?' in them; this shows up when the
 118    assembler complains about syntax errors.
 119 */
 120
 121 static void
 122 encode_pattern_1 (rtx x)
 123 {
 124   int i;
 125
 126   if (patternp == pattern + sizeof (pattern) - 2)
 127     {
 128       patternp[-1] = '?';
 129       return;
 130     }
 131
 132   patternr[patternp - pattern] = x;
 133
 134   switch (GET_CODE (x))
 135     {
 136     case REG:
 137       *patternp++ = 'r';
 138       break;
 139     case SUBREG:
 140       if (GET_MODE_SIZE (GET_MODE (x)) !=
 141           GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
 142         *patternp++ = 'S';
 143       encode_pattern_1 (XEXP (x, 0));
 144       break;
 145     case MEM:
 146       *patternp++ = 'm';
 147     case CONST:
 148       encode_pattern_1 (XEXP (x, 0));
 149       break;
 150     case PLUS:
 151       *patternp++ = '+';
 152       encode_pattern_1 (XEXP (x, 0));
 153       encode_pattern_1 (XEXP (x, 1));
 154       break;
 155     case PRE_DEC:
 156       *patternp++ = '>';
 157       encode_pattern_1 (XEXP (x, 0));
 158       break;
 159     case POST_INC:
 160       *patternp++ = '<';
 161       encode_pattern_1 (XEXP (x, 0));
 162       break;
 163     case LO_SUM:
 164       *patternp++ = 'L';
 165       encode_pattern_1 (XEXP (x, 0));
 166       encode_pattern_1 (XEXP (x, 1));
 167       break;
 168     case HIGH:
 169       *patternp++ = 'H';
 170       encode_pattern_1 (XEXP (x, 0));
 171       break;
 172     case SYMBOL_REF:
 173       *patternp++ = 's';
 174       break;
 175     case LABEL_REF:
 176       *patternp++ = 'l';
 177       break;
 178     case CODE_LABEL:
 179       *patternp++ = 'c';
 180       break;
 181     case CONST_INT:
 182     case CONST_DOUBLE:
 183       *patternp++ = 'i';
 184       break;
 185     case UNSPEC:
 186       *patternp++ = 'u';
 187       *patternp++ = '0' + XCINT (x, 1, UNSPEC);
 188       for (i = 0; i < XVECLEN (x, 0); i++)
 189         encode_pattern_1 (XVECEXP (x, 0, i));
 190       break;
 191     case USE:
 192       *patternp++ = 'U';
 193       break;
 194     case PARALLEL:
 195       *patternp++ = '|';
 196       for (i = 0; i < XVECLEN (x, 0); i++)
 197         encode_pattern_1 (XVECEXP (x, 0, i));
 198       break;
 199     case EXPR_LIST:
 200       *patternp++ = 'E';
 201       encode_pattern_1 (XEXP (x, 0));
 202       if (XEXP (x, 1))
 203         encode_pattern_1 (XEXP (x, 1));
 204       break;
 205     default:
 206       *patternp++ = '?';
 207 #if DEBUG0
 208       fprintf (stderr, "can't encode pattern %s\n",
 209                GET_RTX_NAME (GET_CODE (x)));
 210       debug_rtx (x);
 211       gcc_unreachable ();
 212 #endif
 213       break;
 214     }
 215 }
 216
 217 static void
 218 encode_pattern (rtx x)
 219 {
 220   patternp = pattern;
 221   encode_pattern_1 (x);
 222   *patternp = 0;
 223 }
 224
 225 /* Since register names indicate the mode they're used in, we need a
 226    way to determine which name to refer to the register with.  Called
 227    by print_operand().  */
 228
 229 static const char *
 230 reg_name_with_mode (int regno, enum machine_mode mode)
 231 {
 232   int mlen = GET_MODE_SIZE (mode);
 233   if (regno == R0_REGNO && mlen == 1)
 234     return "r0l";
 235   if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
 236     return "r2r0";
 237   if (regno == R0_REGNO && mlen == 6)
 238     return "r2r1r0";
 239   if (regno == R0_REGNO && mlen == 8)
 240     return "r3r1r2r0";
 241   if (regno == R1_REGNO && mlen == 1)
 242     return "r1l";
 243   if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
 244     return "r3r1";
 245   if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
 246     return "a1a0";
 247   return reg_names[regno];
 248 }
 249
 250 /* How many bytes a register uses on stack when it's pushed.  We need
 251    to know this because the push opcode needs to explicitly indicate
 252    the size of the register, even though the name of the register
 253    already tells it that.  Used by m32c_output_reg_{push,pop}, which
 254    is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}.  */
 255
 256 static int
 257 reg_push_size (int regno)
 258 {
 259   switch (regno)
 260     {
 261     case R0_REGNO:
 262     case R1_REGNO:
 263       return 2;
 264     case R2_REGNO:
 265     case R3_REGNO:
 266     case FLG_REGNO:
 267       return 2;
 268     case A0_REGNO:
 269     case A1_REGNO:
 270     case SB_REGNO:
 271     case FB_REGNO:
 272     case SP_REGNO:
 273       if (TARGET_A16)
 274         return 2;
 275       else
 276         return 3;
 277     default:
 278       gcc_unreachable ();
 279     }
 280 }
 281
 282 static int *class_sizes = 0;
 283
 284 /* Given two register classes, find the largest intersection between
 285    them.  If there is no intersection, return RETURNED_IF_EMPTY
 286    instead.  */
 287 static int
 288 reduce_class (int original_class, int limiting_class, int returned_if_empty)
 289 {
 290   int cc = class_contents[original_class][0];
 291   int i, best = NO_REGS;
 292   int best_size = 0;
 293
 294   if (original_class == limiting_class)
 295     return original_class;
 296
 297   if (!class_sizes)
 298     {
 299       int r;
 300       class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
 301       for (i = 0; i < LIM_REG_CLASSES; i++)
 302         {
 303           class_sizes[i] = 0;
 304           for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
 305             if (class_contents[i][0] & (1 << r))
 306               class_sizes[i]++;
 307         }
 308     }
 309
 310   cc &= class_contents[limiting_class][0];
 311   for (i = 0; i < LIM_REG_CLASSES; i++)
 312     {
 313       int ic = class_contents[i][0];
 314
 315       if ((~cc & ic) == 0)
 316         if (best_size < class_sizes[i])
 317           {
 318             best = i;
 319             best_size = class_sizes[i];
 320           }
 321
 322     }
 323   if (best == NO_REGS)
 324     return returned_if_empty;
 325   return best;
 326 }
 327
 328 /* Returns TRUE If there are any registers that exist in both register
 329    classes.  */
 330 static int
 331 classes_intersect (int class1, int class2)
 332 {
 333   return class_contents[class1][0] & class_contents[class2][0];
 334 }
 335
 336 /* Used by m32c_register_move_cost to determine if a move is
 337    impossibly expensive.  */
 338 static int
 339 class_can_hold_mode (int class, enum machine_mode mode)
 340 {
 341   /* Cache the results:  0=untested  1=no  2=yes */
 342   static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
 343   if (results[class][mode] == 0)
 344     {
 345       int r, n, i;
 346       results[class][mode] = 1;
 347       for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
 348         if (class_contents[class][0] & (1 << r)
 349             && HARD_REGNO_MODE_OK (r, mode))
 350           {
 351             int ok = 1;
 352             n = HARD_REGNO_NREGS (r, mode);
 353             for (i = 1; i < n; i++)
 354               if (!(class_contents[class][0] & (1 << (r + i))))
 355                 ok = 0;
 356             if (ok)
 357               {
 358                 results[class][mode] = 2;
 359                 break;
 360               }
 361           }
 362     }
 363 #if DEBUG0
 364   fprintf (stderr, "class %s can hold %s? %s\n",
 365            class_names[class], mode_name[mode],
 366            (results[class][mode] == 2) ? "yes" : "no");
 367 #endif
 368   return results[class][mode] == 2;
 369 }
 370
 371 /* Run-time Target Specification.  */
 372
 373 /* Memregs are memory locations that gcc treats like general
 374    registers, as there are a limited number of true registers and the
 375    m32c families can use memory in most places that registers can be
 376    used.
 377
 378    However, since memory accesses are more expensive than registers,
 379    we allow the user to limit the number of memregs available, in
 380    order to try to persuade gcc to try harder to use real registers.
 381
 382    Memregs are provided by m32c-lib1.S.
 383 */
 384
 385 int target_memregs = 16;
 386 static bool target_memregs_set = FALSE;
 387 int ok_to_change_target_memregs = TRUE;
 388
 389 #undef  TARGET_HANDLE_OPTION
 390 #define TARGET_HANDLE_OPTION m32c_handle_option
 391 static bool
 392 m32c_handle_option (size_t code,
 393                     const char *arg ATTRIBUTE_UNUSED,
 394                     int value ATTRIBUTE_UNUSED)
 395 {
 396   if (code == OPT_memregs_)
 397     {
 398       target_memregs_set = TRUE;
 399       target_memregs = atoi (arg);
 400     }
 401   return TRUE;
 402 }
 403
 404 /* Implements OVERRIDE_OPTIONS.  We limit memregs to 0..16, and
 405    provide a default.  */
 406 void
 407 m32c_override_options (void)
 408 {
 409   if (target_memregs_set)
 410     {
 411       if (target_memregs < 0 || target_memregs > 16)
 412         error ("invalid target memregs value '%d'", target_memregs);
 413     }
 414   else
 415     target_memregs = "16";
 416 }
 417
 418 /* Defining data structures for per-function information */
 419
 420 /* The usual; we set up our machine_function data.  */
 421 static struct machine_function *
 422 m32c_init_machine_status (void)
 423 {
 424   struct machine_function *machine;
 425   machine =
 426     (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
 427
 428   return machine;
 429 }
 430
 431 /* Implements INIT_EXPANDERS.  We just set up to call the above
 432    function.  */
 433 void
 434 m32c_init_expanders (void)
 435 {
 436   init_machine_status = m32c_init_machine_status;
 437 }
 438
 439 /* Storage Layout */
 440
 441 #undef TARGET_PROMOTE_FUNCTION_RETURN
 442 #define TARGET_PROMOTE_FUNCTION_RETURN m32c_promote_function_return
 443 bool
 444 m32c_promote_function_return (tree fntype ATTRIBUTE_UNUSED)
 445 {
 446   return false;
 447 }
 448
 449 /* Register Basics */
 450
 451 /* Basic Characteristics of Registers */
 452
 453 /* Whether a mode fits in a register is complex enough to warrant a
 454    table.  */
 455 static struct
 456 {
 457   char qi_regs;
 458   char hi_regs;
 459   char pi_regs;
 460   char si_regs;
 461   char di_regs;
 462 } nregs_table[FIRST_PSEUDO_REGISTER] =
 463 {
 464   { 1, 1, 2, 2, 4 },            /* r0 */
 465   { 0, 1, 0, 0, 0 },            /* r2 */
 466   { 1, 1, 2, 2, 0 },            /* r1 */
 467   { 0, 1, 0, 0, 0 },            /* r3 */
 468   { 0, 1, 1, 0, 0 },            /* a0 */
 469   { 0, 1, 1, 0, 0 },            /* a1 */
 470   { 0, 1, 1, 0, 0 },            /* sb */
 471   { 0, 1, 1, 0, 0 },            /* fb */
 472   { 0, 1, 1, 0, 0 },            /* sp */
 473   { 1, 1, 1, 0, 0 },            /* pc */
 474   { 0, 0, 0, 0, 0 },            /* fl */
 475   { 1, 1, 1, 0, 0 },            /* ap */
 476   { 1, 1, 2, 2, 4 },            /* mem0 */
 477   { 1, 1, 2, 2, 4 },            /* mem1 */
 478   { 1, 1, 2, 2, 4 },            /* mem2 */
 479   { 1, 1, 2, 2, 4 },            /* mem3 */
 480   { 1, 1, 2, 2, 4 },            /* mem4 */
 481   { 1, 1, 2, 2, 0 },            /* mem5 */
 482   { 1, 1, 2, 2, 0 },            /* mem6 */
 483   { 1, 1, 0, 0, 0 },            /* mem7 */
 484 };
 485
 486 /* Implements CONDITIONAL_REGISTER_USAGE.  We adjust the number of
 487    available memregs, and select which registers need to be preserved
 488    across calls based on the chip family.  */
 489
 490 void
 491 m32c_conditional_register_usage (void)
 492 {
 493   int memregs;
 494   int i;
 495
 496   if (0 <= target_memregs && target_memregs <= 16)
 497     {
 498       /* The command line option is bytes, but our "registers" are
 499          16-bit words.  */
 500       for (i = target_memregs/2; i < 8; i++)
 501         {
 502           fixed_regs[MEM0_REGNO + i] = 1;
 503           CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
 504         }
 505     }
 506
 507   /* M32CM and M32C preserve more registers across function calls.  */
 508   if (TARGET_A24)
 509     {
 510       call_used_regs[R1_REGNO] = 0;
 511       call_used_regs[R2_REGNO] = 0;
 512       call_used_regs[R3_REGNO] = 0;
 513       call_used_regs[A0_REGNO] = 0;
 514       call_used_regs[A1_REGNO] = 0;
 515     }
 516 }
 517
 518 /* How Values Fit in Registers */
 519
 520 /* Implements HARD_REGNO_NREGS.  This is complicated by the fact that
 521    different registers are different sizes from each other, *and* may
 522    be different sizes in different chip families.  */
 523 int
 524 m32c_hard_regno_nregs (int regno, enum machine_mode mode)
 525 {
 526   if (regno == FLG_REGNO && mode == CCmode)
 527     return 1;
 528   if (regno >= FIRST_PSEUDO_REGISTER)
 529     return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
 530
 531   if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
 532     return (GET_MODE_SIZE (mode) + 1) / 2;
 533
 534   if (GET_MODE_SIZE (mode) <= 1)
 535     return nregs_table[regno].qi_regs;
 536   if (GET_MODE_SIZE (mode) <= 2)
 537     return nregs_table[regno].hi_regs;
 538   if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
 539     return 2;
 540   if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
 541     return nregs_table[regno].pi_regs;
 542   if (GET_MODE_SIZE (mode) <= 4)
 543     return nregs_table[regno].si_regs;
 544   if (GET_MODE_SIZE (mode) <= 8)
 545     return nregs_table[regno].di_regs;
 546   return 0;
 547 }
 548
 549 /* Implements HARD_REGNO_MODE_OK.  The above function does the work
 550    already; just test its return value.  */
 551 int
 552 m32c_hard_regno_ok (int regno, enum machine_mode mode)
 553 {
 554   return m32c_hard_regno_nregs (regno, mode) != 0;
 555 }
 556
 557 /* Implements MODES_TIEABLE_P.  In general, modes aren't tieable since
 558    registers are all different sizes.  However, since most modes are
 559    bigger than our registers anyway, it's easier to implement this
 560    function that way, leaving QImode as the only unique case.  */
 561 int
 562 m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
 563 {
 564   if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
 565     return 1;
 566
 567   if (m1 == QImode || m2 == QImode)
 568     return 0;
 569
 570   return 1;
 571 }
 572
 573 /* Register Classes */
 574
 575 /* Implements REGNO_REG_CLASS.  */
 576 enum machine_mode
 577 m32c_regno_reg_class (int regno)
 578 {
 579   switch (regno)
 580     {
 581     case R0_REGNO:
 582       return R0_REGS;
 583     case R1_REGNO:
 584       return R1_REGS;
 585     case R2_REGNO:
 586       return R2_REGS;
 587     case R3_REGNO:
 588       return R3_REGS;
 589     case A0_REGNO:
 590     case A1_REGNO:
 591       return A_REGS;
 592     case SB_REGNO:
 593       return SB_REGS;
 594     case FB_REGNO:
 595       return FB_REGS;
 596     case SP_REGNO:
 597       return SP_REGS;
 598     case FLG_REGNO:
 599       return FLG_REGS;
 600     default:
 601       if (IS_MEM_REGNO (regno))
 602         return MEM_REGS;
 603       return ALL_REGS;
 604     }
 605 }
 606
 607 /* Implements REG_CLASS_FROM_CONSTRAINT.  Note that some constraints only match
 608    for certain chip families.  */
 609 int
 610 m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
 611 {
 612   if (memcmp (s, "Rsp", 3) == 0)
 613     return SP_REGS;
 614   if (memcmp (s, "Rfb", 3) == 0)
 615     return FB_REGS;
 616   if (memcmp (s, "Rsb", 3) == 0)
 617     return SB_REGS;
 618   if (memcmp (s, "Rcr", 3) == 0 && TARGET_A16)
 619     return CR_REGS;
 620   if (memcmp (s, "Rcl", 3) == 0 && TARGET_A24)
 621     return CR_REGS;
 622   if (memcmp (s, "R0w", 3) == 0)
 623     return R0_REGS;
 624   if (memcmp (s, "R1w", 3) == 0)
 625     return R1_REGS;
 626   if (memcmp (s, "R2w", 3) == 0)
 627     return R2_REGS;
 628   if (memcmp (s, "R3w", 3) == 0)
 629     return R3_REGS;
 630   if (memcmp (s, "R02", 3) == 0)
 631     return R02_REGS;
 632   if (memcmp (s, "R03", 3) == 0)
 633     return R03_REGS;
 634   if (memcmp (s, "Rdi", 3) == 0)
 635     return DI_REGS;
 636   if (memcmp (s, "Rhl", 3) == 0)
 637     return HL_REGS;
 638   if (memcmp (s, "R23", 3) == 0)
 639     return R23_REGS;
 640   if (memcmp (s, "Raa", 3) == 0)
 641     return A_REGS;
 642   if (memcmp (s, "Raw", 3) == 0 && TARGET_A16)
 643     return A_REGS;
 644   if (memcmp (s, "Ral", 3) == 0 && TARGET_A24)
 645     return A_REGS;
 646   if (memcmp (s, "Rqi", 3) == 0)
 647     return QI_REGS;
 648   if (memcmp (s, "Rad", 3) == 0)
 649     return AD_REGS;
 650   if (memcmp (s, "Rsi", 3) == 0)
 651     return SI_REGS;
 652   if (memcmp (s, "Rhi", 3) == 0)
 653     return HI_REGS;
 654   if (memcmp (s, "Rhc", 3) == 0)
 655     return HC_REGS;
 656   if (memcmp (s, "Rra", 3) == 0)
 657     return RA_REGS;
 658   if (memcmp (s, "Rfl", 3) == 0)
 659     return FLG_REGS;
 660   if (memcmp (s, "Rmm", 3) == 0)
 661     {
 662       if (fixed_regs[MEM0_REGNO])
 663         return NO_REGS;
 664       return MEM_REGS;
 665     }
 666
 667   /* PSImode registers - i.e. whatever can hold a pointer.  */
 668   if (memcmp (s, "Rpi", 3) == 0)
 669     {
 670       if (TARGET_A16)
 671         return HI_REGS;
 672       else
 673         return RA_REGS; /* r2r0 and r3r1 can hold pointers.  */
 674     }
 675
 676   /* We handle this one as an EXTRA_CONSTRAINT.  */
 677   if (memcmp (s, "Rpa", 3) == 0)
 678     return NO_REGS;
 679
 680   return NO_REGS;
 681 }
 682
 683 /* Implements REGNO_OK_FOR_BASE_P.  */
 684 int
 685 m32c_regno_ok_for_base_p (int regno)
 686 {
 687   if (regno == A0_REGNO
 688       || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
 689     return 1;
 690   return 0;
 691 }
 692
 693 #define DEBUG_RELOAD 0
 694
 695 /* Implements PREFERRED_RELOAD_CLASS.  In general, prefer general
 696    registers of the appropriate size.  */
 697 int
 698 m32c_preferred_reload_class (rtx x, int rclass)
 699 {
 700   int newclass = rclass;
 701
 702 #if DEBUG_RELOAD
 703   fprintf (stderr, "\npreferred_reload_class for %s is ",
 704            class_names[rclass]);
 705 #endif
 706   if (rclass == NO_REGS)
 707     rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
 708
 709   if (classes_intersect (rclass, CR_REGS))
 710     {
 711       switch (GET_MODE (x))
 712         {
 713         case QImode:
 714           newclass = HL_REGS;
 715           break;
 716         default:
 717           /*      newclass = HI_REGS; */
 718           break;
 719         }
 720     }
 721
 722   else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
 723     newclass = SI_REGS;
 724   else if (GET_MODE_SIZE (GET_MODE (x)) > 4
 725            && ~class_contents[rclass][0] & 0x000f)
 726     newclass = DI_REGS;
 727
 728   rclass = reduce_class (rclass, newclass, rclass);
 729
 730   if (GET_MODE (x) == QImode)
 731     rclass = reduce_class (rclass, HL_REGS, rclass);
 732
 733 #if DEBUG_RELOAD
 734   fprintf (stderr, "%s\n", class_names[rclass]);
 735   debug_rtx (x);
 736
 737   if (GET_CODE (x) == MEM
 738       && GET_CODE (XEXP (x, 0)) == PLUS
 739       && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
 740     fprintf (stderr, "Glorm!\n");
 741 #endif
 742   return rclass;
 743 }
 744
 745 /* Implements PREFERRED_OUTPUT_RELOAD_CLASS.  */
 746 int
 747 m32c_preferred_output_reload_class (rtx x, int rclass)
 748 {
 749   return m32c_preferred_reload_class (x, rclass);
 750 }
 751
 752 /* Implements LIMIT_RELOAD_CLASS.  We basically want to avoid using
 753    address registers for reloads since they're needed for address
 754    reloads.  */
 755 int
 756 m32c_limit_reload_class (enum machine_mode mode, int rclass)
 757 {
 758 #if DEBUG_RELOAD
 759   fprintf (stderr, "limit_reload_class for %s: %s ->",
 760            mode_name[mode], class_names[rclass]);
 761 #endif
 762
 763   if (mode == QImode)
 764     rclass = reduce_class (rclass, HL_REGS, rclass);
 765   else if (mode == HImode)
 766     rclass = reduce_class (rclass, HI_REGS, rclass);
 767   else if (mode == SImode)
 768     rclass = reduce_class (rclass, SI_REGS, rclass);
 769
 770   if (rclass != A_REGS)
 771     rclass = reduce_class (rclass, DI_REGS, rclass);
 772
 773 #if DEBUG_RELOAD
 774   fprintf (stderr, " %s\n", class_names[rclass]);
 775 #endif
 776   return rclass;
 777 }
 778
 779 /* Implements SECONDARY_RELOAD_CLASS.  QImode have to be reloaded in
 780    r0 or r1, as those are the only real QImode registers.  CR regs get
 781    reloaded through appropriately sized general or address
 782    registers.  */
 783 int
 784 m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
 785 {
 786   int cc = class_contents[rclass][0];
 787 #if DEBUG0
 788   fprintf (stderr, "\nsecondary reload class %s %s\n",
 789            class_names[rclass], mode_name[mode]);
 790   debug_rtx (x);
 791 #endif
 792   if (mode == QImode
 793       && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
 794     return QI_REGS;
 795   if (classes_intersect (rclass, CR_REGS)
 796       && GET_CODE (x) == REG
 797       && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
 798     return TARGET_A16 ? HI_REGS : A_REGS;
 799   return NO_REGS;
 800 }
 801
 802 /* Implements CLASS_LIKELY_SPILLED_P.  A_REGS is needed for address
 803    reloads.  */
 804 int
 805 m32c_class_likely_spilled_p (int regclass)
 806 {
 807   if (regclass == A_REGS)
 808     return 1;
 809   return reg_class_size[regclass] == 1;
 810 }
 811
 812 /* Implements CLASS_MAX_NREGS.  We calculate this according to its
 813    documented meaning, to avoid potential inconsistencies with actual
 814    class definitions.  */
 815 int
 816 m32c_class_max_nregs (int regclass, enum machine_mode mode)
 817 {
 818   int rn, max = 0;
 819
 820   for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
 821     if (class_contents[regclass][0] & (1 << rn))
 822       {
 823         int n = m32c_hard_regno_nregs (rn, mode);
 824         if (max < n)
 825           max = n;
 826       }
 827   return max;
 828 }
 829
 830 /* Implements CANNOT_CHANGE_MODE_CLASS.  Only r0 and r1 can change to
 831    QI (r0l, r1l) because the chip doesn't support QI ops on other
 832    registers (well, it does on a0/a1 but if we let gcc do that, reload
 833    suffers).  Otherwise, we allow changes to larger modes.  */
 834 int
 835 m32c_cannot_change_mode_class (enum machine_mode from,
 836                                enum machine_mode to, int rclass)
 837 {
 838 #if DEBUG0
 839   fprintf (stderr, "cannot change from %s to %s in %s\n",
 840            mode_name[from], mode_name[to], class_names[rclass]);
 841 #endif
 842
 843   if (to == QImode)
 844     return (class_contents[rclass][0] & 0x1ffa);
 845
 846   if (class_contents[rclass][0] & 0x0005        /* r0, r1 */
 847       && GET_MODE_SIZE (from) > 1)
 848     return 0;
 849   if (GET_MODE_SIZE (from) > 2) /* all other regs */
 850     return 0;
 851
 852   return 1;
 853 }
 854
 855 /* Helpers for the rest of the file.  */
 856 /* TRUE if the rtx is a REG rtx for the given register.  */
 857 #define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
 858                            && REGNO (rtx) == regno)
 859 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
 860    base register in address calculations (hence the "strict"
 861    argument).  */
 862 #define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
 863                                && (REGNO (rtx) == AP_REGNO \
 864                                    || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
 865
 866 /* Implements CONST_OK_FOR_CONSTRAINT_P.  Currently, all constant
 867    constraints start with 'I', with the next two characters indicating
 868    the type and size of the range allowed.  */
 869 int
 870 m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
 871                                 char c ATTRIBUTE_UNUSED, const char *str)
 872 {
 873   /* s=signed u=unsigned n=nonzero m=minus l=log2able,
 874      [sun] bits [SUN] bytes, p=pointer size
 875      I[-0-9][0-9] matches that number */
 876   if (memcmp (str, "Is3", 3) == 0)
 877     {
 878       return (-8 <= value && value <= 7);
 879     }
 880   if (memcmp (str, "IS1", 3) == 0)
 881     {
 882       return (-128 <= value && value <= 127);
 883     }
 884   if (memcmp (str, "IS2", 3) == 0)
 885     {
 886       return (-32768 <= value && value <= 32767);
 887     }
 888   if (memcmp (str, "IU2", 3) == 0)
 889     {
 890       return (0 <= value && value <= 65535);
 891     }
 892   if (memcmp (str, "IU3", 3) == 0)
 893     {
 894       return (0 <= value && value <= 0x00ffffff);
 895     }
 896   if (memcmp (str, "In4", 3) == 0)
 897     {
 898       return (-8 <= value && value && value <= 8);
 899     }
 900   if (memcmp (str, "In5", 3) == 0)
 901     {
 902       return (-16 <= value && value && value <= 16);
 903     }
 904   if (memcmp (str, "IM2", 3) == 0)
 905     {
 906       return (-65536 <= value && value && value <= -1);
 907     }
 908   if (memcmp (str, "Ilb", 3) == 0)
 909     {
 910       int b = exact_log2 (value);
 911       return (b >= 1 && b <= 8);
 912     }
 913   if (memcmp (str, "Ilw", 3) == 0)
 914     {
 915       int b = exact_log2 (value);
 916       return (b >= 1 && b <= 16);
 917     }
 918   return 0;
 919 }
 920
 921 /* Implements EXTRA_CONSTRAINT_STR (see next function too).  'S' is
 922    for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
 923    call return values.  */
 924 int
 925 m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
 926 {
 927   encode_pattern (value);
 928   if (memcmp (str, "Sd", 2) == 0)
 929     {
 930       /* This is the common "src/dest" address */
 931       rtx r;
 932       if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
 933         return 1;
 934       if (RTX_IS ("ms") || RTX_IS ("m+si"))
 935         return 1;
 936       if (RTX_IS ("mr"))
 937         r = patternr[1];
 938       else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
 939         r = patternr[2];
 940       else
 941         return 0;
 942       if (REGNO (r) == SP_REGNO)
 943         return 0;
 944       return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
 945     }
 946   else if (memcmp (str, "Sa", 2) == 0)
 947     {
 948       rtx r;
 949       if (RTX_IS ("mr"))
 950         r = patternr[1];
 951       else if (RTX_IS ("m+ri"))
 952         r = patternr[2];
 953       else
 954         return 0;
 955       return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
 956     }
 957   else if (memcmp (str, "Si", 2) == 0)
 958     {
 959       return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
 960     }
 961   else if (memcmp (str, "Ss", 2) == 0)
 962     {
 963       return ((RTX_IS ("mr")
 964                && (IS_REG (patternr[1], SP_REGNO)))
 965               || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
 966     }
 967   else if (memcmp (str, "Sf", 2) == 0)
 968     {
 969       return ((RTX_IS ("mr")
 970                && (IS_REG (patternr[1], FB_REGNO)))
 971               || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
 972     }
 973   else if (memcmp (str, "Sb", 2) == 0)
 974     {
 975       return ((RTX_IS ("mr")
 976                && (IS_REG (patternr[1], SB_REGNO)))
 977               || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
 978     }
 979   else if (memcmp (str, "S1", 2) == 0)
 980     {
 981       return r1h_operand (value, QImode);
 982     }
 983
 984   gcc_assert (str[0] != 'S');
 985
 986   if (memcmp (str, "Rpa", 2) == 0)
 987     return GET_CODE (value) == PARALLEL;
 988
 989   return 0;
 990 }
 991
 992 /* This is for when we're debugging the above.  */
 993 int
 994 m32c_extra_constraint_p (rtx value, char c, const char *str)
 995 {
 996   int rv = m32c_extra_constraint_p2 (value, c, str);
 997 #if DEBUG0
 998   fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
 999            rv);
1000   debug_rtx (value);
1001 #endif
1002   return rv;
1003 }
1004
1005 /* Implements EXTRA_MEMORY_CONSTRAINT.  Currently, we only use strings
1006    starting with 'S'.  */
1007 int
1008 m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1009 {
1010   return c == 'S';
1011 }
1012
1013 /* Implements EXTRA_ADDRESS_CONSTRAINT.  We reserve 'A' strings for these,
1014    but don't currently define any.  */
1015 int
1016 m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1017 {
1018   return c == 'A';
1019 }
1020
1021 /* STACK AND CALLING */
1022
1023 /* Frame Layout */
1024
1025 /* Implements RETURN_ADDR_RTX.  Note that R8C and M16C push 24 bits
1026    (yes, THREE bytes) onto the stack for the return address, but we
1027    don't support pointers bigger than 16 bits on those chips.  This
1028    will likely wreak havoc with exception unwinding.  FIXME.  */
1029 rtx
1030 m32c_return_addr_rtx (int count)
1031 {
1032   enum machine_mode mode;
1033   int offset;
1034   rtx ra_mem;
1035
1036   if (count)
1037     return NULL_RTX;
1038   /* we want 2[$fb] */
1039
1040   if (TARGET_A24)
1041     {
1042       mode = SImode;
1043       offset = 4;
1044     }
1045   else
1046     {
1047       /* FIXME: it's really 3 bytes */
1048       mode = HImode;
1049       offset = 2;
1050     }
1051
1052   ra_mem =
1053     gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
1054   return copy_to_mode_reg (mode, ra_mem);
1055 }
1056
1057 /* Implements INCOMING_RETURN_ADDR_RTX.  See comment above.  */
1058 rtx
1059 m32c_incoming_return_addr_rtx (void)
1060 {
1061   /* we want [sp] */
1062   return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
1063 }
1064
1065 /* Exception Handling Support */
1066
1067 /* Implements EH_RETURN_DATA_REGNO.  Choose registers able to hold
1068    pointers.  */
1069 int
1070 m32c_eh_return_data_regno (int n)
1071 {
1072   switch (n)
1073     {
1074     case 0:
1075       return A0_REGNO;
1076     case 1:
1077       return A1_REGNO;
1078     default:
1079       return INVALID_REGNUM;
1080     }
1081 }
1082
1083 /* Implements EH_RETURN_STACKADJ_RTX.  Saved and used later in
1084    m32c_emit_eh_epilogue.  */
1085 rtx
1086 m32c_eh_return_stackadj_rtx (void)
1087 {
1088   if (!cfun->machine->eh_stack_adjust)
1089     {
1090       rtx sa;
1091
1092       sa = gen_reg_rtx (Pmode);
1093       cfun->machine->eh_stack_adjust = sa;
1094     }
1095   return cfun->machine->eh_stack_adjust;
1096 }
1097
1098 /* Registers That Address the Stack Frame */
1099
1100 /* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER.  Note that
1101    the original spec called for dwarf numbers to vary with register
1102    width as well, for example, r0l, r0, and r2r0 would each have
1103    different dwarf numbers.  GCC doesn't support this, and we don't do
1104    it, and gdb seems to like it this way anyway.  */
1105 unsigned int
1106 m32c_dwarf_frame_regnum (int n)
1107 {
1108   switch (n)
1109     {
1110     case R0_REGNO:
1111       return 5;
1112     case R1_REGNO:
1113       return 6;
1114     case R2_REGNO:
1115       return 7;
1116     case R3_REGNO:
1117       return 8;
1118     case A0_REGNO:
1119       return 9;
1120     case A1_REGNO:
1121       return 10;
1122     case FB_REGNO:
1123       return 11;
1124     case SB_REGNO:
1125       return 19;
1126
1127     case SP_REGNO:
1128       return 12;
1129     case PC_REGNO:
1130       return 13;
1131     default:
1132       return DWARF_FRAME_REGISTERS + 1;
1133     }
1134 }
1135
1136 /* The frame looks like this:
1137
1138    ap -> +------------------------------
1139          | Return address (3 or 4 bytes)
1140          | Saved FB (2 or 4 bytes)
1141    fb -> +------------------------------
1142          | local vars
1143          | register saves fb
1144          |        through r0 as needed
1145    sp -> +------------------------------
1146 */
1147
1148 /* We use this to wrap all emitted insns in the prologue.  */
1149 static rtx
1150 F (rtx x)
1151 {
1152   RTX_FRAME_RELATED_P (x) = 1;
1153   return x;
1154 }
1155
1156 /* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1157    how much the stack pointer moves for each, for each cpu family.  */
1158 static struct
1159 {
1160   int reg1;
1161   int bit;
1162   int a16_bytes;
1163   int a24_bytes;
1164 } pushm_info[] =
1165 {
1166   /* These are in push order.  */
1167   { FB_REGNO, 0x01, 2, 4 },
1168   { SB_REGNO, 0x02, 2, 4 },
1169   { A1_REGNO, 0x04, 2, 4 },
1170   { A0_REGNO, 0x08, 2, 4 },
1171   { R3_REGNO, 0x10, 2, 2 },
1172   { R2_REGNO, 0x20, 2, 2 },
1173   { R1_REGNO, 0x40, 2, 2 },
1174   { R0_REGNO, 0x80, 2, 2 }
1175 };
1176
1177 #define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1178
1179 /* Returns TRUE if we need to save/restore the given register.  We
1180    save everything for exception handlers, so that any register can be
1181    unwound.  For interrupt handlers, we save everything if the handler
1182    calls something else (because we don't know what *that* function
1183    might do), but try to be a bit smarter if the handler is a leaf
1184    function.  We always save $a0, though, because we use that in the
1185    epilog to copy $fb to $sp.  */
1186 static int
1187 need_to_save (int regno)
1188 {
1189   if (fixed_regs[regno])
1190     return 0;
1191   if (cfun->calls_eh_return)
1192     return 1;
1193   if (regno == FP_REGNO)
1194     return 0;
1195   if (cfun->machine->is_interrupt
1196       && (!cfun->machine->is_leaf || regno == A0_REGNO))
1197     return 1;
1198   if (regs_ever_live[regno]
1199       && (!call_used_regs[regno] || cfun->machine->is_interrupt))
1200     return 1;
1201   return 0;
1202 }
1203
1204 /* This function contains all the intelligence about saving and
1205    restoring registers.  It always figures out the register save set.
1206    When called with PP_justcount, it merely returns the size of the
1207    save set (for eliminating the frame pointer, for example).  When
1208    called with PP_pushm or PP_popm, it emits the appropriate
1209    instructions for saving (pushm) or restoring (popm) the
1210    registers.  */
1211 static int
1212 m32c_pushm_popm (Push_Pop_Type ppt)
1213 {
1214   int reg_mask = 0;
1215   int byte_count = 0, bytes;
1216   int i;
1217   rtx dwarf_set[PUSHM_N];
1218   int n_dwarfs = 0;
1219   int nosave_mask = 0;
1220
1221   if (cfun->return_rtx
1222       && GET_CODE (cfun->return_rtx) == PARALLEL
1223       && !(cfun->calls_eh_return || cfun->machine->is_interrupt))
1224     {
1225       rtx exp = XVECEXP (cfun->return_rtx, 0, 0);
1226       rtx rv = XEXP (exp, 0);
1227       int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
1228
1229       if (rv_bytes > 2)
1230         nosave_mask |= 0x20;    /* PSI, SI */
1231       else
1232         nosave_mask |= 0xf0;    /* DF */
1233       if (rv_bytes > 4)
1234         nosave_mask |= 0x50;    /* DI */
1235     }
1236
1237   for (i = 0; i < (int) PUSHM_N; i++)
1238     {
1239       /* Skip if neither register needs saving.  */
1240       if (!need_to_save (pushm_info[i].reg1))
1241         continue;
1242
1243       if (pushm_info[i].bit & nosave_mask)
1244         continue;
1245
1246       reg_mask |= pushm_info[i].bit;
1247       bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
1248
1249       if (ppt == PP_pushm)
1250         {
1251           enum machine_mode mode = (bytes == 2) ? HImode : SImode;
1252           rtx addr;
1253
1254           /* Always use stack_pointer_rtx instead of calling
1255              rtx_gen_REG ourselves.  Code elsewhere in GCC assumes
1256              that there is a single rtx representing the stack pointer,
1257              namely stack_pointer_rtx, and uses == to recognize it.  */
1258           addr = stack_pointer_rtx;
1259
1260           if (byte_count != 0)
1261             addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
1262
1263           dwarf_set[n_dwarfs++] =
1264             gen_rtx_SET (VOIDmode,
1265                          gen_rtx_MEM (mode, addr),
1266                          gen_rtx_REG (mode, pushm_info[i].reg1));
1267           F (dwarf_set[n_dwarfs - 1]);
1268
1269         }
1270       byte_count += bytes;
1271     }
1272
1273   if (cfun->machine->is_interrupt)
1274     {
1275       cfun->machine->intr_pushm = reg_mask & 0xfe;
1276       reg_mask = 0;
1277       byte_count = 0;
1278     }
1279
1280   if (cfun->machine->is_interrupt)
1281     for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1282       if (need_to_save (i))
1283         {
1284           byte_count += 2;
1285           cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
1286         }
1287
1288   if (ppt == PP_pushm && byte_count)
1289     {
1290       rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
1291       rtx pushm;
1292
1293       if (reg_mask)
1294         {
1295           XVECEXP (note, 0, 0)
1296             = gen_rtx_SET (VOIDmode,
1297                            stack_pointer_rtx,
1298                            gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
1299                                          stack_pointer_rtx,
1300                                          GEN_INT (-byte_count)));
1301           F (XVECEXP (note, 0, 0));
1302
1303           for (i = 0; i < n_dwarfs; i++)
1304             XVECEXP (note, 0, i + 1) = dwarf_set[i];
1305
1306           pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
1307
1308           REG_NOTES (pushm) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, note,
1309                                                  REG_NOTES (pushm));
1310         }
1311
1312       if (cfun->machine->is_interrupt)
1313         for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1314           if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1315             {
1316               if (TARGET_A16)
1317                 pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
1318               else
1319                 pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
1320               F (pushm);
1321             }
1322     }
1323   if (ppt == PP_popm && byte_count)
1324     {
1325       if (cfun->machine->is_interrupt)
1326         for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
1327           if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1328             {
1329               if (TARGET_A16)
1330                 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
1331               else
1332                 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
1333             }
1334       if (reg_mask)
1335         emit_insn (gen_popm (GEN_INT (reg_mask)));
1336     }
1337
1338   return byte_count;
1339 }
1340
1341 /* Implements INITIAL_ELIMINATION_OFFSET.  See the comment above that
1342    diagrams our call frame.  */
1343 int
1344 m32c_initial_elimination_offset (int from, int to)
1345 {
1346   int ofs = 0;
1347
1348   if (from == AP_REGNO)
1349     {
1350       if (TARGET_A16)
1351         ofs += 5;
1352       else
1353         ofs += 8;
1354     }
1355
1356   if (to == SP_REGNO)
1357     {
1358       ofs += m32c_pushm_popm (PP_justcount);
1359       ofs += get_frame_size ();
1360     }
1361
1362   /* Account for push rounding.  */
1363   if (TARGET_A24)
1364     ofs = (ofs + 1) & ~1;
1365 #if DEBUG0
1366   fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
1367            to, ofs);
1368 #endif
1369   return ofs;
1370 }
1371
1372 /* Passing Function Arguments on the Stack */
1373
1374 #undef TARGET_PROMOTE_PROTOTYPES
1375 #define TARGET_PROMOTE_PROTOTYPES m32c_promote_prototypes
1376 static bool
1377 m32c_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
1378 {
1379   return 0;
1380 }
1381
1382 /* Implements PUSH_ROUNDING.  The R8C and M16C have byte stacks, the
1383    M32C has word stacks.  */
1384 int
1385 m32c_push_rounding (int n)
1386 {
1387   if (TARGET_R8C || TARGET_M16C)
1388     return n;
1389   return (n + 1) & ~1;
1390 }
1391
1392 /* Passing Arguments in Registers */
1393
1394 /* Implements FUNCTION_ARG.  Arguments are passed partly in registers,
1395    partly on stack.  If our function returns a struct, a pointer to a
1396    buffer for it is at the top of the stack (last thing pushed).  The
1397    first few real arguments may be in registers as follows:
1398
1399    R8C/M16C:    arg1 in r1 if it's QI or HI (else it's pushed on stack)
1400                 arg2 in r2 if it's HI (else pushed on stack)
1401                 rest on stack
1402    M32C:        arg1 in r0 if it's QI or HI (else it's pushed on stack)
1403                 rest on stack
1404
1405    Structs are not passed in registers, even if they fit.  Only
1406    integer and pointer types are passed in registers.
1407
1408    Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1409    r2 if it fits.  */
1410 rtx
1411 m32c_function_arg (CUMULATIVE_ARGS * ca,
1412                    enum machine_mode mode, tree type, int named)
1413 {
1414   /* Can return a reg, parallel, or 0 for stack */
1415   rtx rv = NULL_RTX;
1416 #if DEBUG0
1417   fprintf (stderr, "func_arg %d (%s, %d)\n",
1418            ca->parm_num, mode_name[mode], named);
1419   debug_tree (type);
1420 #endif
1421
1422   if (mode == VOIDmode)
1423     return GEN_INT (0);
1424
1425   if (ca->force_mem || !named)
1426     {
1427 #if DEBUG0
1428       fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
1429                named);
1430 #endif
1431       return NULL_RTX;
1432     }
1433
1434   if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
1435     return NULL_RTX;
1436
1437   switch (ca->parm_num)
1438     {
1439     case 1:
1440       if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
1441         rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
1442       break;
1443
1444     case 2:
1445       if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
1446         rv = gen_rtx_REG (mode, R2_REGNO);
1447       break;
1448     }
1449
1450 #if DEBUG0
1451   debug_rtx (rv);
1452 #endif
1453   return rv;
1454 }
1455
1456 #undef TARGET_PASS_BY_REFERENCE
1457 #define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1458 static bool
1459 m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
1460                         enum machine_mode mode ATTRIBUTE_UNUSED,
1461                         tree type ATTRIBUTE_UNUSED,
1462                         bool named ATTRIBUTE_UNUSED)
1463 {
1464   return 0;
1465 }
1466
1467 /* Implements INIT_CUMULATIVE_ARGS.  */
1468 void
1469 m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
1470                            tree fntype ATTRIBUTE_UNUSED,
1471                            rtx libname ATTRIBUTE_UNUSED,
1472                            tree fndecl ATTRIBUTE_UNUSED,
1473                            int n_named_args ATTRIBUTE_UNUSED)
1474 {
1475   ca->force_mem = 0;
1476   ca->parm_num = 1;
1477 }
1478
1479 /* Implements FUNCTION_ARG_ADVANCE.  force_mem is set for functions
1480    returning structures, so we always reset that.  Otherwise, we only
1481    need to know the sequence number of the argument to know what to do
1482    with it.  */
1483 void
1484 m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
1485                            enum machine_mode mode ATTRIBUTE_UNUSED,
1486                            tree type ATTRIBUTE_UNUSED,
1487                            int named ATTRIBUTE_UNUSED)
1488 {
1489   if (ca->force_mem)
1490     ca->force_mem = 0;
1491   ca->parm_num++;
1492 }
1493
1494 /* Implements FUNCTION_ARG_REGNO_P.  */
1495 int
1496 m32c_function_arg_regno_p (int r)
1497 {
1498   if (TARGET_A24)
1499     return (r == R0_REGNO);
1500   return (r == R1_REGNO || r == R2_REGNO);
1501 }
1502
1503 /* HImode and PSImode are the two "native" modes as far as GCC is
1504    concerned, but the chips also support a 32 bit mode which is used
1505    for some opcodes in R8C/M16C and for reset vectors and such.  */
1506 #undef TARGET_VALID_POINTER_MODE
1507 #define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
1508 bool
1509 m32c_valid_pointer_mode (enum machine_mode mode)
1510 {
1511   if (mode == HImode
1512       || mode == PSImode
1513       || mode == SImode
1514       )
1515     return 1;
1516   return 0;
1517 }
1518
1519 /* How Scalar Function Values Are Returned */
1520
1521 /* Implements LIBCALL_VALUE.  Most values are returned in $r0, or some
1522    combination of registers starting there (r2r0 for longs, r3r1r2r0
1523    for long long, r3r2r1r0 for doubles), except that that ABI
1524    currently doesn't work because it ends up using all available
1525    general registers and gcc often can't compile it.  So, instead, we
1526    return anything bigger than 16 bits in "mem0" (effectively, a
1527    memory location).  */
1528 rtx
1529 m32c_libcall_value (enum machine_mode mode)
1530 {
1531   /* return reg or parallel */
1532 #if 0
1533   /* FIXME: GCC has difficulty returning large values in registers,
1534      because that ties up most of the general registers and gives the
1535      register allocator little to work with.  Until we can resolve
1536      this, large values are returned in memory.  */
1537   if (mode == DFmode)
1538     {
1539       rtx rv;
1540
1541       rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
1542       XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1543                                               gen_rtx_REG (HImode,
1544                                                            R0_REGNO),
1545                                               GEN_INT (0));
1546       XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
1547                                               gen_rtx_REG (HImode,
1548                                                            R1_REGNO),
1549                                               GEN_INT (2));
1550       XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
1551                                               gen_rtx_REG (HImode,
1552                                                            R2_REGNO),
1553                                               GEN_INT (4));
1554       XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
1555                                               gen_rtx_REG (HImode,
1556                                                            R3_REGNO),
1557                                               GEN_INT (6));
1558       return rv;
1559     }
1560
1561   if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
1562     {
1563       rtx rv;
1564
1565       rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
1566       XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1567                                               gen_rtx_REG (mode,
1568                                                            R0_REGNO),
1569                                               GEN_INT (0));
1570       return rv;
1571     }
1572 #endif
1573
1574   if (GET_MODE_SIZE (mode) > 2)
1575     return gen_rtx_REG (mode, MEM0_REGNO);
1576   return gen_rtx_REG (mode, R0_REGNO);
1577 }
1578
1579 /* Implements FUNCTION_VALUE.  Functions and libcalls have the same
1580    conventions.  */
1581 rtx
1582 m32c_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
1583 {
1584   /* return reg or parallel */
1585   enum machine_mode mode = TYPE_MODE (valtype);
1586   return m32c_libcall_value (mode);
1587 }
1588
1589 /* How Large Values Are Returned */
1590
1591 /* We return structures by pushing the address on the stack, even if
1592    we use registers for the first few "real" arguments.  */
1593 #undef TARGET_STRUCT_VALUE_RTX
1594 #define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1595 static rtx
1596 m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
1597                        int incoming ATTRIBUTE_UNUSED)
1598 {
1599   return 0;
1600 }
1601
1602 /* Function Entry and Exit */
1603
1604 /* Implements EPILOGUE_USES.  Interrupts restore all registers.  */
1605 int
1606 m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
1607 {
1608   if (cfun->machine->is_interrupt)
1609     return 1;
1610   return 0;
1611 }
1612
1613 /* Implementing the Varargs Macros */
1614
1615 #undef TARGET_STRICT_ARGUMENT_NAMING
1616 #define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1617 static bool
1618 m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
1619 {
1620   return 1;
1621 }
1622
1623 /* Trampolines for Nested Functions */
1624
1625 /*
1626    m16c:
1627    1 0000 75C43412              mov.w   #0x1234,a0
1628    2 0004 FC000000              jmp.a   label
1629
1630    m32c:
1631    1 0000 BC563412              mov.l:s #0x123456,a0
1632    2 0004 CC000000              jmp.a   label
1633 */
1634
1635 /* Implements TRAMPOLINE_SIZE.  */
1636 int
1637 m32c_trampoline_size (void)
1638 {
1639   /* Allocate extra space so we can avoid the messy shifts when we
1640      initialize the trampoline; we just write past the end of the
1641      opcode.  */
1642   return TARGET_A16 ? 8 : 10;
1643 }
1644
1645 /* Implements TRAMPOLINE_ALIGNMENT.  */
1646 int
1647 m32c_trampoline_alignment (void)
1648 {
1649   return 2;
1650 }
1651
1652 /* Implements INITIALIZE_TRAMPOLINE.  */
1653 void
1654 m32c_initialize_trampoline (rtx tramp, rtx function, rtx chainval)
1655 {
1656 #define A0(m,i) gen_rtx_MEM (m, plus_constant (tramp, i))
1657   if (TARGET_A16)
1658     {
1659       /* Note: we subtract a "word" because the moves want signed
1660          constants, not unsigned constants.  */
1661       emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
1662       emit_move_insn (A0 (HImode, 2), chainval);
1663       emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
1664       /* We use 16 bit addresses here, but store the zero to turn it
1665          into a 24 bit offset.  */
1666       emit_move_insn (A0 (HImode, 5), function);
1667       emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
1668     }
1669   else
1670     {
1671       /* Note that the PSI moves actually write 4 bytes.  Make sure we
1672          write stuff out in the right order, and leave room for the
1673          extra byte at the end.  */
1674       emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
1675       emit_move_insn (A0 (PSImode, 1), chainval);
1676       emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
1677       emit_move_insn (A0 (PSImode, 5), function);
1678     }
1679 #undef A0
1680 }
1681
1682 /* Addressing Modes */
1683
1684 /* Used by GO_IF_LEGITIMATE_ADDRESS.  The r8c/m32c family supports a
1685    wide range of non-orthogonal addressing modes, including the
1686    ability to double-indirect on *some* of them.  Not all insns
1687    support all modes, either, but we rely on predicates and
1688    constraints to deal with that.  */
1689 int
1690 m32c_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1691 {
1692   int mode_adjust;
1693   if (CONSTANT_P (x))
1694     return 1;
1695
1696   /* Wide references to memory will be split after reload, so we must
1697      ensure that all parts of such splits remain legitimate
1698      addresses.  */
1699   mode_adjust = GET_MODE_SIZE (mode) - 1;
1700
1701   /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1702   if (GET_CODE (x) == PRE_DEC
1703       || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
1704     {
1705       return (GET_CODE (XEXP (x, 0)) == REG
1706               && REGNO (XEXP (x, 0)) == SP_REGNO);
1707     }
1708
1709 #if 0
1710   /* This is the double indirection detection, but it currently
1711      doesn't work as cleanly as this code implies, so until we've had
1712      a chance to debug it, leave it disabled.  */
1713   if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
1714     {
1715 #if DEBUG_DOUBLE
1716       fprintf (stderr, "double indirect\n");
1717 #endif
1718       x = XEXP (x, 0);
1719     }
1720 #endif
1721
1722   encode_pattern (x);
1723   if (RTX_IS ("r"))
1724     {
1725       /* Most indexable registers can be used without displacements,
1726          although some of them will be emitted with an explicit zero
1727          to please the assembler.  */
1728       switch (REGNO (patternr[0]))
1729         {
1730         case A0_REGNO:
1731         case A1_REGNO:
1732         case SB_REGNO:
1733         case FB_REGNO:
1734         case SP_REGNO:
1735           return 1;
1736
1737         default:
1738           if (IS_PSEUDO (patternr[0], strict))
1739             return 1;
1740           return 0;
1741         }
1742     }
1743   if (RTX_IS ("+ri"))
1744     {
1745       /* This is more interesting, because different base registers
1746          allow for different displacements - both range and signedness
1747          - and it differs from chip series to chip series too.  */
1748       int rn = REGNO (patternr[1]);
1749       HOST_WIDE_INT offs = INTVAL (patternr[2]);
1750       switch (rn)
1751         {
1752         case A0_REGNO:
1753         case A1_REGNO:
1754         case SB_REGNO:
1755           /* The syntax only allows positive offsets, but when the
1756              offsets span the entire memory range, we can simulate
1757              negative offsets by wrapping.  */
1758           if (TARGET_A16)
1759             return (offs >= -65536 && offs <= 65535 - mode_adjust);
1760           if (rn == SB_REGNO)
1761             return (offs >= 0 && offs <= 65535 - mode_adjust);
1762           /* A0 or A1 */
1763           return (offs >= -16777216 && offs <= 16777215);
1764
1765         case FB_REGNO:
1766           if (TARGET_A16)
1767             return (offs >= -128 && offs <= 127 - mode_adjust);
1768           return (offs >= -65536 && offs <= 65535 - mode_adjust);
1769
1770         case SP_REGNO:
1771           return (offs >= -128 && offs <= 127 - mode_adjust);
1772
1773         default:
1774           if (IS_PSEUDO (patternr[1], strict))
1775             return 1;
1776           return 0;
1777         }
1778     }
1779   if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1780     {
1781       rtx reg = patternr[1];
1782
1783       /* We don't know where the symbol is, so only allow base
1784          registers which support displacements spanning the whole
1785          address range.  */
1786       switch (REGNO (reg))
1787         {
1788         case A0_REGNO:
1789         case A1_REGNO:
1790           /* $sb needs a secondary reload, but since it's involved in
1791              memory address reloads too, we don't deal with it very
1792              well.  */
1793           /*    case SB_REGNO: */
1794           return 1;
1795         default:
1796           if (IS_PSEUDO (reg, strict))
1797             return 1;
1798           return 0;
1799         }
1800     }
1801   return 0;
1802 }
1803
1804 /* Implements REG_OK_FOR_BASE_P.  */
1805 int
1806 m32c_reg_ok_for_base_p (rtx x, int strict)
1807 {
1808   if (GET_CODE (x) != REG)
1809     return 0;
1810   switch (REGNO (x))
1811     {
1812     case A0_REGNO:
1813     case A1_REGNO:
1814     case SB_REGNO:
1815     case FB_REGNO:
1816     case SP_REGNO:
1817       return 1;
1818     default:
1819       if (IS_PSEUDO (x, strict))
1820         return 1;
1821       return 0;
1822     }
1823 }
1824
1825 /* Implements LEGITIMIZE_ADDRESS.  The only address we really have to
1826    worry about is frame base offsets, as $fb has a limited
1827    displacement range.  We deal with this by attempting to reload $fb
1828    itself into an address register; that seems to result in the best
1829    code.  */
1830 int
1831 m32c_legitimize_address (rtx * x ATTRIBUTE_UNUSED,
1832                          rtx oldx ATTRIBUTE_UNUSED,
1833                          enum machine_mode mode ATTRIBUTE_UNUSED)
1834 {
1835 #if DEBUG0
1836   fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
1837   debug_rtx (*x);
1838   fprintf (stderr, "\n");
1839 #endif
1840
1841   if (GET_CODE (*x) == PLUS
1842       && GET_CODE (XEXP (*x, 0)) == REG
1843       && REGNO (XEXP (*x, 0)) == FB_REGNO
1844       && GET_CODE (XEXP (*x, 1)) == CONST_INT
1845       && (INTVAL (XEXP (*x, 1)) < -128
1846           || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
1847     {
1848       /* reload FB to A_REGS */
1849       rtx foo;
1850       rtx temp = gen_reg_rtx (Pmode);
1851       *x = copy_rtx (*x);
1852       foo = emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (*x, 0)));
1853       XEXP (*x, 0) = temp;
1854       return 1;
1855     }
1856
1857   return 0;
1858 }
1859
1860 /* Implements LEGITIMIZE_RELOAD_ADDRESS.  See comment above.  */
1861 int
1862 m32c_legitimize_reload_address (rtx * x,
1863                                 enum machine_mode mode,
1864                                 int opnum,
1865                                 int type, int ind_levels ATTRIBUTE_UNUSED)
1866 {
1867 #if DEBUG0
1868   fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
1869            mode_name[mode]);
1870   debug_rtx (*x);
1871 #endif
1872
1873   /* At one point, this function tried to get $fb copied to an address
1874      register, which in theory would maximize sharing, but gcc was
1875      *also* still trying to reload the whole address, and we'd run out
1876      of address registers.  So we let gcc do the naive (but safe)
1877      reload instead, when the above function doesn't handle it for
1878      us.  */
1879
1880   return 0;
1881 }
1882
1883 /* Used in GO_IF_MODE_DEPENDENT_ADDRESS.  */
1884 int
1885 m32c_mode_dependent_address (rtx addr)
1886 {
1887   if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == PRE_DEC)
1888     return 1;
1889   return 0;
1890 }
1891
1892 /* Implements LEGITIMATE_CONSTANT_P.  We split large constants anyway,
1893    so we can allow anything.  */
1894 int
1895 m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
1896 {
1897   return 1;
1898 }
1899
1900
1901 /* Condition Code Status */
1902
1903 #undef TARGET_FIXED_CONDITION_CODE_REGS
1904 #define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
1905 static bool
1906 m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
1907 {
1908   *p1 = FLG_REGNO;
1909   *p2 = INVALID_REGNUM;
1910   return true;
1911 }
1912
1913 /* Describing Relative Costs of Operations */
1914
1915 /* Implements REGISTER_MOVE_COST.  We make impossible moves
1916    prohibitively expensive, like trying to put QIs in r2/r3 (there are
1917    no opcodes to do that).  We also discourage use of mem* registers
1918    since they're really memory.  */
1919 int
1920 m32c_register_move_cost (enum machine_mode mode, int from, int to)
1921 {
1922   int cost = COSTS_N_INSNS (3);
1923   int cc = class_contents[from][0] | class_contents[to][0];
1924   /* FIXME: pick real values, but not 2 for now.  */
1925   if (mode == QImode && (cc & class_contents[R23_REGS][0]))
1926     {
1927       if (!(cc & ~class_contents[R23_REGS][0]))
1928         cost = COSTS_N_INSNS (1000);
1929       else
1930         cost = COSTS_N_INSNS (80);
1931     }
1932
1933   if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
1934     cost = COSTS_N_INSNS (1000);
1935
1936   if (classes_intersect (from, CR_REGS))
1937     cost += COSTS_N_INSNS (5);
1938
1939   if (classes_intersect (to, CR_REGS))
1940     cost += COSTS_N_INSNS (5);
1941
1942   if (from == MEM_REGS || to == MEM_REGS)
1943     cost += COSTS_N_INSNS (50);
1944   else if (classes_intersect (from, MEM_REGS)
1945            || classes_intersect (to, MEM_REGS))
1946     cost += COSTS_N_INSNS (10);
1947
1948 #if DEBUG0
1949   fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
1950            mode_name[mode], class_names[from], class_names[to], cost);
1951 #endif
1952   return cost;
1953 }
1954
1955 /*  Implements MEMORY_MOVE_COST.  */
1956 int
1957 m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1958                        int reg_class ATTRIBUTE_UNUSED,
1959                        int in ATTRIBUTE_UNUSED)
1960 {
1961   /* FIXME: pick real values.  */
1962   return COSTS_N_INSNS (10);
1963 }
1964
1965 /* Defining the Output Assembler Language */
1966
1967 /* The Overall Framework of an Assembler File */
1968
1969 #undef TARGET_HAVE_NAMED_SECTIONS
1970 #define TARGET_HAVE_NAMED_SECTIONS true
1971
1972 /* Output of Data */
1973
1974 /* We may have 24 bit sizes, which is the native address size.
1975    Currently unused, but provided for completeness.  */
1976 #undef TARGET_ASM_INTEGER
1977 #define TARGET_ASM_INTEGER m32c_asm_integer
1978 static bool
1979 m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
1980 {
1981   switch (size)
1982     {
1983     case 3:
1984       fprintf (asm_out_file, "\t.3byte\t");
1985       output_addr_const (asm_out_file, x);
1986       fputc ('\n', asm_out_file);
1987       return true;
1988     case 4:
1989       if (GET_CODE (x) == SYMBOL_REF)
1990         {
1991           fprintf (asm_out_file, "\t.long\t");
1992           output_addr_const (asm_out_file, x);
1993           fputc ('\n', asm_out_file);
1994           return true;
1995         }
1996       break;
1997     }
1998   return default_assemble_integer (x, size, aligned_p);
1999 }
2000
2001 /* Output of Assembler Instructions */
2002
2003 /* We use a lookup table because the addressing modes are non-orthogonal.  */
2004
2005 static struct
2006 {
2007   char code;
2008   char const *pattern;
2009   char const *format;
2010 }
2011 const conversions[] = {
2012   { 0, "r", "0" },
2013
2014   { 0, "mr", "z[1]" },
2015   { 0, "m+ri", "3[2]" },
2016   { 0, "m+rs", "3[2]" },
2017   { 0, "m+r+si", "4+5[2]" },
2018   { 0, "ms", "1" },
2019   { 0, "mi", "1" },
2020   { 0, "m+si", "2+3" },
2021
2022   { 0, "mmr", "[z[2]]" },
2023   { 0, "mm+ri", "[4[3]]" },
2024   { 0, "mm+rs", "[4[3]]" },
2025   { 0, "mm+r+si", "[5+6[3]]" },
2026   { 0, "mms", "[[2]]" },
2027   { 0, "mmi", "[[2]]" },
2028   { 0, "mm+si", "[4[3]]" },
2029
2030   { 0, "i", "#0" },
2031   { 0, "s", "#0" },
2032   { 0, "+si", "#1+2" },
2033   { 0, "l", "#0" },
2034
2035   { 'l', "l", "0" },
2036   { 'd', "i", "0" },
2037   { 'd', "s", "0" },
2038   { 'd', "+si", "1+2" },
2039   { 'D', "i", "0" },
2040   { 'D', "s", "0" },
2041   { 'D', "+si", "1+2" },
2042   { 'x', "i", "#0" },
2043   { 'X', "i", "#0" },
2044   { 'm', "i", "#0" },
2045   { 'b', "i", "#0" },
2046   { 'p', "i", "0" },
2047
2048   { 0, 0, 0 }
2049 };
2050
2051 /* This is in order according to the bitfield that pushm/popm use.  */
2052 static char const *pushm_regs[] = {
2053   "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2054 };
2055
2056 /* Implements PRINT_OPERAND.  */
2057 void
2058 m32c_print_operand (FILE * file, rtx x, int code)
2059 {
2060   int i, j, b;
2061   const char *comma;
2062   HOST_WIDE_INT ival;
2063   int unsigned_const = 0;
2064
2065   /* Multiplies; constants are converted to sign-extended format but
2066    we need unsigned, so 'u' and 'U' tell us what size unsigned we
2067    need.  */
2068   if (code == 'u')
2069     {
2070       unsigned_const = 2;
2071       code = 0;
2072     }
2073   if (code == 'U')
2074     {
2075       unsigned_const = 1;
2076       code = 0;
2077     }
2078   /* This one is only for debugging; you can put it in a pattern to
2079      force this error.  */
2080   if (code == '!')
2081     {
2082       fprintf (stderr, "dj: unreviewed pattern:");
2083       if (current_output_insn)
2084         debug_rtx (current_output_insn);
2085       gcc_unreachable ();
2086     }
2087   /* PSImode operations are either .w or .l depending on the target.  */
2088   if (code == '&')
2089     {
2090       if (TARGET_A16)
2091         fprintf (file, "w");
2092       else
2093         fprintf (file, "l");
2094       return;
2095     }
2096   /* Inverted conditionals.  */
2097   if (code == 'C')
2098     {
2099       switch (GET_CODE (x))
2100         {
2101         case LE:
2102           fputs ("gt", file);
2103           break;
2104         case LEU:
2105           fputs ("gtu", file);
2106           break;
2107         case LT:
2108           fputs ("ge", file);
2109           break;
2110         case LTU:
2111           fputs ("geu", file);
2112           break;
2113         case GT:
2114           fputs ("le", file);
2115           break;
2116         case GTU:
2117           fputs ("leu", file);
2118           break;
2119         case GE:
2120           fputs ("lt", file);
2121           break;
2122         case GEU:
2123           fputs ("ltu", file);
2124           break;
2125         case NE:
2126           fputs ("eq", file);
2127           break;
2128         case EQ:
2129           fputs ("ne", file);
2130           break;
2131         default:
2132           gcc_unreachable ();
2133         }
2134       return;
2135     }
2136   /* Regular conditionals.  */
2137   if (code == 'c')
2138     {
2139       switch (GET_CODE (x))
2140         {
2141         case LE:
2142           fputs ("le", file);
2143           break;
2144         case LEU:
2145           fputs ("leu", file);
2146           break;
2147         case LT:
2148           fputs ("lt", file);
2149           break;
2150         case LTU:
2151           fputs ("ltu", file);
2152           break;
2153         case GT:
2154           fputs ("gt", file);
2155           break;
2156         case GTU:
2157           fputs ("gtu", file);
2158           break;
2159         case GE:
2160           fputs ("ge", file);
2161           break;
2162         case GEU:
2163           fputs ("geu", file);
2164           break;
2165         case NE:
2166           fputs ("ne", file);
2167           break;
2168         case EQ:
2169           fputs ("eq", file);
2170           break;
2171         default:
2172           gcc_unreachable ();
2173         }
2174       return;
2175     }
2176   /* Used in negsi2 to do HImode ops on the two parts of an SImode
2177      operand.  */
2178   if (code == 'h' && GET_MODE (x) == SImode)
2179     {
2180       x = m32c_subreg (HImode, x, SImode, 0);
2181       code = 0;
2182     }
2183   if (code == 'H' && GET_MODE (x) == SImode)
2184     {
2185       x = m32c_subreg (HImode, x, SImode, 2);
2186       code = 0;
2187     }
2188   /* 'x' and 'X' need to be ignored for non-immediates.  */
2189   if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
2190     code = 0;
2191
2192   encode_pattern (x);
2193   for (i = 0; conversions[i].pattern; i++)
2194     if (conversions[i].code == code
2195         && streq (conversions[i].pattern, pattern))
2196       {
2197         for (j = 0; conversions[i].format[j]; j++)
2198           /* backslash quotes the next character in the output pattern.  */
2199           if (conversions[i].format[j] == '\\')
2200             {
2201               fputc (conversions[i].format[j + 1], file);
2202               j++;
2203             }
2204           /* Digits in the output pattern indicate that the
2205              corresponding RTX is to be output at that point.  */
2206           else if (ISDIGIT (conversions[i].format[j]))
2207             {
2208               rtx r = patternr[conversions[i].format[j] - '0'];
2209               switch (GET_CODE (r))
2210                 {
2211                 case REG:
2212                   fprintf (file, "%s",
2213                            reg_name_with_mode (REGNO (r), GET_MODE (r)));
2214                   break;
2215                 case CONST_INT:
2216                   switch (code)
2217                     {
2218                     case 'b':
2219                       /* Bit position.  */
2220                       fprintf (file, "%d", (int) exact_log2 (INTVAL (r)));
2221                       break;
2222                     case 'x':
2223                       /* Unsigned byte.  */
2224                       fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2225                                INTVAL (r) & 0xff);
2226                       break;
2227                     case 'X':
2228                       /* Unsigned word.  */
2229                       fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2230                                INTVAL (r) & 0xffff);
2231                       break;
2232                     case 'p':
2233                       /* pushm and popm encode a register set into a single byte.  */
2234                       comma = "";
2235                       for (b = 7; b >= 0; b--)
2236                         if (INTVAL (r) & (1 << b))
2237                           {
2238                             fprintf (file, "%s%s", comma, pushm_regs[b]);
2239                             comma = ",";
2240                           }
2241                       break;
2242                     case 'm':
2243                       /* "Minus".  Output -X  */
2244                       ival = (-INTVAL (r) & 0xffff);
2245                       if (ival & 0x8000)
2246                         ival = ival - 0x10000;
2247                       fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2248                       break;
2249                     default:
2250                       ival = INTVAL (r);
2251                       if (conversions[i].format[j + 1] == '[' && ival < 0)
2252                         {
2253                           /* We can simulate negative displacements by
2254                              taking advantage of address space
2255                              wrapping when the offset can span the
2256                              entire address range.  */
2257                           rtx base =
2258                             patternr[conversions[i].format[j + 2] - '0'];
2259                           if (GET_CODE (base) == REG)
2260                             switch (REGNO (base))
2261                               {
2262                               case A0_REGNO:
2263                               case A1_REGNO:
2264                                 if (TARGET_A24)
2265                                   ival = 0x1000000 + ival;
2266                                 else
2267                                   ival = 0x10000 + ival;
2268                                 break;
2269                               case SB_REGNO:
2270                                 if (TARGET_A16)
2271                                   ival = 0x10000 + ival;
2272                                 break;
2273                               }
2274                         }
2275                       else if (code == 'd' && ival < 0 && j == 0)
2276                         /* The "mova" opcode is used to do addition by
2277                            computing displacements, but again, we need
2278                            displacements to be unsigned *if* they're
2279                            the only component of the displacement
2280                            (i.e. no "symbol-4" type displacement).  */
2281                         ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
2282
2283                       if (conversions[i].format[j] == '0')
2284                         {
2285                           /* More conversions to unsigned.  */
2286                           if (unsigned_const == 2)
2287                             ival &= 0xffff;
2288                           if (unsigned_const == 1)
2289                             ival &= 0xff;
2290                         }
2291                       if (streq (conversions[i].pattern, "mi")
2292                           || streq (conversions[i].pattern, "mmi"))
2293                         {
2294                           /* Integers used as addresses are unsigned.  */
2295                           ival &= (TARGET_A24 ? 0xffffff : 0xffff);
2296                         }
2297                       fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2298                       break;
2299                     }
2300                   break;
2301                 case CONST_DOUBLE:
2302                   /* We don't have const_double constants.  If it
2303                      happens, make it obvious.  */
2304                   fprintf (file, "[const_double 0x%lx]",
2305                            (unsigned long) CONST_DOUBLE_HIGH (r));
2306                   break;
2307                 case SYMBOL_REF:
2308                   assemble_name (file, XSTR (r, 0));
2309                   break;
2310                 case LABEL_REF:
2311                   output_asm_label (r);
2312                   break;
2313                 default:
2314                   fprintf (stderr, "don't know how to print this operand:");
2315                   debug_rtx (r);
2316                   gcc_unreachable ();
2317                 }
2318             }
2319           else
2320             {
2321               if (conversions[i].format[j] == 'z')
2322                 {
2323                   /* Some addressing modes *must* have a displacement,
2324                      so insert a zero here if needed.  */
2325                   int k;
2326                   for (k = j + 1; conversions[i].format[k]; k++)
2327                     if (ISDIGIT (conversions[i].format[k]))
2328                       {
2329                         rtx reg = patternr[conversions[i].format[k] - '0'];
2330                         if (GET_CODE (reg) == REG
2331                             && (REGNO (reg) == SB_REGNO
2332                                 || REGNO (reg) == FB_REGNO
2333                                 || REGNO (reg) == SP_REGNO))
2334                           fputc ('0', file);
2335                       }
2336                   continue;
2337                 }
2338               /* Signed displacements off symbols need to have signs
2339                  blended cleanly.  */
2340               if (conversions[i].format[j] == '+'
2341                   && (!code || code == 'I')
2342                   && ISDIGIT (conversions[i].format[j + 1])
2343                   && GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
2344                   == CONST_INT
2345                   && INTVAL (patternr[conversions[i].format[j + 1] - '0']) <
2346                   0)
2347                 continue;
2348               fputc (conversions[i].format[j], file);
2349             }
2350         break;
2351       }
2352   if (!conversions[i].pattern)
2353     {
2354       fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
2355                pattern);
2356       debug_rtx (x);
2357       fprintf (file, "[%c.%s]", code ? code : '-', pattern);
2358     }
2359
2360   return;
2361 }
2362
2363 /* Implements PRINT_OPERAND_PUNCT_VALID_P.  See m32c_print_operand
2364    above for descriptions of what these do.  */
2365 int
2366 m32c_print_operand_punct_valid_p (int c)
2367 {
2368   if (c == '&' || c == '!')
2369     return 1;
2370   return 0;
2371 }
2372
2373 /* Implements PRINT_OPERAND_ADDRESS.  Nothing unusual here.  */
2374 void
2375 m32c_print_operand_address (FILE * stream, rtx address)
2376 {
2377   gcc_assert (GET_CODE (address) == MEM);
2378   m32c_print_operand (stream, XEXP (address, 0), 0);
2379 }
2380
2381 /* Implements ASM_OUTPUT_REG_PUSH.  Control registers are pushed
2382    differently than general registers.  */
2383 void
2384 m32c_output_reg_push (FILE * s, int regno)
2385 {
2386   if (regno == FLG_REGNO)
2387     fprintf (s, "\tpushc\tflg\n");
2388   else
2389     fprintf (s, "\tpush.%c\t%s",
2390              " bwll"[reg_push_size (regno)], reg_names[regno]);
2391 }
2392
2393 /* Likewise for ASM_OUTPUT_REG_POP.  */
2394 void
2395 m32c_output_reg_pop (FILE * s, int regno)
2396 {
2397   if (regno == FLG_REGNO)
2398     fprintf (s, "\tpopc\tflg\n");
2399   else
2400     fprintf (s, "\tpop.%c\t%s",
2401              " bwll"[reg_push_size (regno)], reg_names[regno]);
2402 }
2403
2404 /* Defining target-specific uses of `__attribute__' */
2405
2406 /* Used to simplify the logic below.  Find the attributes wherever
2407    they may be.  */
2408 #define M32C_ATTRIBUTES(decl) \
2409   (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2410                 : DECL_ATTRIBUTES (decl) \
2411                   ? (DECL_ATTRIBUTES (decl)) \
2412                   : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2413
2414 /* Returns TRUE if the given tree has the "interrupt" attribute.  */
2415 static int
2416 interrupt_p (tree node ATTRIBUTE_UNUSED)
2417 {
2418   tree list = M32C_ATTRIBUTES (node);
2419   while (list)
2420     {
2421       if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
2422         return 1;
2423       list = TREE_CHAIN (list);
2424     }
2425   return 0;
2426 }
2427
2428 static tree
2429 interrupt_handler (tree * node ATTRIBUTE_UNUSED,
2430                    tree name ATTRIBUTE_UNUSED,
2431                    tree args ATTRIBUTE_UNUSED,
2432                    int flags ATTRIBUTE_UNUSED,
2433                    bool * no_add_attrs ATTRIBUTE_UNUSED)
2434 {
2435   return NULL_TREE;
2436 }
2437
2438 #undef TARGET_ATTRIBUTE_TABLE
2439 #define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
2440 static const struct attribute_spec m32c_attribute_table[] = {
2441   {"interrupt", 0, 0, false, false, false, interrupt_handler},
2442   {0, 0, 0, 0, 0, 0, 0}
2443 };
2444
2445 #undef TARGET_COMP_TYPE_ATTRIBUTES
2446 #define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
2447 static int
2448 m32c_comp_type_attributes (tree type1 ATTRIBUTE_UNUSED,
2449                            tree type2 ATTRIBUTE_UNUSED)
2450 {
2451   /* 0=incompatible 1=compatible 2=warning */
2452   return 1;
2453 }
2454
2455 #undef TARGET_INSERT_ATTRIBUTES
2456 #define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
2457 static void
2458 m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
2459                         tree * attr_ptr ATTRIBUTE_UNUSED)
2460 {
2461   /* Nothing to do here.  */
2462 }
2463
2464 /* Predicates */
2465
2466 /* Returns TRUE if we support a move between the first two operands.
2467    At the moment, we just want to discourage mem to mem moves until
2468    after reload, because reload has a hard time with our limited
2469    number of address registers, and we can get into a situation where
2470    we need three of them when we only have two.  */
2471 bool
2472 m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
2473 {
2474   rtx op0 = operands[0];
2475   rtx op1 = operands[1];
2476
2477   if (TARGET_A24)
2478     return true;
2479
2480 #define DEBUG_MOV_OK 0
2481 #if DEBUG_MOV_OK
2482   fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
2483   debug_rtx (op0);
2484   debug_rtx (op1);
2485 #endif
2486
2487   if (GET_CODE (op0) == SUBREG)
2488     op0 = XEXP (op0, 0);
2489   if (GET_CODE (op1) == SUBREG)
2490     op1 = XEXP (op1, 0);
2491
2492   if (GET_CODE (op0) == MEM
2493       && GET_CODE (op1) == MEM
2494       && ! reload_completed)
2495     {
2496 #if DEBUG_MOV_OK
2497       fprintf (stderr, " - no, mem to mem\n");
2498 #endif
2499       return false;
2500     }
2501
2502 #if DEBUG_MOV_OK
2503   fprintf (stderr, " - ok\n");
2504 #endif
2505   return true;
2506 }
2507
2508 /* Expanders */
2509
2510 /* Subregs are non-orthogonal for us, because our registers are all
2511    different sizes.  */
2512 static rtx
2513 m32c_subreg (enum machine_mode outer,
2514              rtx x, enum machine_mode inner, int byte)
2515 {
2516   int r, nr = -1;
2517
2518   /* Converting MEMs to different types that are the same size, we
2519      just rewrite them.  */
2520   if (GET_CODE (x) == SUBREG
2521       && SUBREG_BYTE (x) == 0
2522       && GET_CODE (SUBREG_REG (x)) == MEM
2523       && (GET_MODE_SIZE (GET_MODE (x))
2524           == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2525     {
2526       rtx oldx = x;
2527       x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
2528       MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
2529     }
2530
2531   /* Push/pop get done as smaller push/pops.  */
2532   if (GET_CODE (x) == MEM
2533       && (GET_CODE (XEXP (x, 0)) == PRE_DEC
2534           || GET_CODE (XEXP (x, 0)) == POST_INC))
2535     return gen_rtx_MEM (outer, XEXP (x, 0));
2536   if (GET_CODE (x) == SUBREG
2537       && GET_CODE (XEXP (x, 0)) == MEM
2538       && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
2539           || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
2540     return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
2541
2542   if (GET_CODE (x) != REG)
2543     return simplify_gen_subreg (outer, x, inner, byte);
2544
2545   r = REGNO (x);
2546   if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
2547     return simplify_gen_subreg (outer, x, inner, byte);
2548
2549   if (IS_MEM_REGNO (r))
2550     return simplify_gen_subreg (outer, x, inner, byte);
2551
2552   /* This is where the complexities of our register layout are
2553      described.  */
2554   if (byte == 0)
2555     nr = r;
2556   else if (outer == HImode)
2557     {
2558       if (r == R0_REGNO && byte == 2)
2559         nr = R2_REGNO;
2560       else if (r == R0_REGNO && byte == 4)
2561         nr = R1_REGNO;
2562       else if (r == R0_REGNO && byte == 6)
2563         nr = R3_REGNO;
2564       else if (r == R1_REGNO && byte == 2)
2565         nr = R3_REGNO;
2566       else if (r == A0_REGNO && byte == 2)
2567         nr = A1_REGNO;
2568     }
2569   else if (outer == SImode)
2570     {
2571       if (r == R0_REGNO && byte == 0)
2572         nr = R0_REGNO;
2573       else if (r == R0_REGNO && byte == 4)
2574         nr = R1_REGNO;
2575     }
2576   if (nr == -1)
2577     {
2578       fprintf (stderr, "m32c_subreg %s %s %d\n",
2579                mode_name[outer], mode_name[inner], byte);
2580       debug_rtx (x);
2581       gcc_unreachable ();
2582     }
2583   return gen_rtx_REG (outer, nr);
2584 }
2585
2586 /* Used to emit move instructions.  We split some moves,
2587    and avoid mem-mem moves.  */
2588 int
2589 m32c_prepare_move (rtx * operands, enum machine_mode mode)
2590 {
2591   if (TARGET_A16 && mode == PSImode)
2592     return m32c_split_move (operands, mode, 1);
2593   if ((GET_CODE (operands[0]) == MEM)
2594       && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
2595     {
2596       rtx pmv = XEXP (operands[0], 0);
2597       rtx dest_reg = XEXP (pmv, 0);
2598       rtx dest_mod = XEXP (pmv, 1);
2599
2600       emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
2601       operands[0] = gen_rtx_MEM (mode, dest_reg);
2602     }
2603   if (!no_new_pseudos && MEM_P (operands[0]) && MEM_P (operands[1]))
2604     operands[1] = copy_to_mode_reg (mode, operands[1]);
2605   return 0;
2606 }
2607
2608 #define DEBUG_SPLIT 0
2609
2610 /* Returns TRUE if the given PSImode move should be split.  We split
2611    for all r8c/m16c moves, since it doesn't support them, and for
2612    POP.L as we can only *push* SImode.  */
2613 int
2614 m32c_split_psi_p (rtx * operands)
2615 {
2616 #if DEBUG_SPLIT
2617   fprintf (stderr, "\nm32c_split_psi_p\n");
2618   debug_rtx (operands[0]);
2619   debug_rtx (operands[1]);
2620 #endif
2621   if (TARGET_A16)
2622     {
2623 #if DEBUG_SPLIT
2624       fprintf (stderr, "yes, A16\n");
2625 #endif
2626       return 1;
2627     }
2628   if (GET_CODE (operands[1]) == MEM
2629       && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
2630     {
2631 #if DEBUG_SPLIT
2632       fprintf (stderr, "yes, pop.l\n");
2633 #endif
2634       return 1;
2635     }
2636 #if DEBUG_SPLIT
2637   fprintf (stderr, "no, default\n");
2638 #endif
2639   return 0;
2640 }
2641
2642 /* Split the given move.  SPLIT_ALL is 0 if splitting is optional
2643    (define_expand), 1 if it is not optional (define_insn_and_split),
2644    and 3 for define_split (alternate api). */
2645 int
2646 m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
2647 {
2648   rtx s[4], d[4];
2649   int parts, si, di, rev = 0;
2650   int rv = 0, opi = 2;
2651   enum machine_mode submode = HImode;
2652   rtx *ops, local_ops[10];
2653
2654   /* define_split modifies the existing operands, but the other two
2655      emit new insns.  OPS is where we store the operand pairs, which
2656      we emit later.  */
2657   if (split_all == 3)
2658     ops = operands;
2659   else
2660     ops = local_ops;
2661
2662   /* Else HImode.  */
2663   if (mode == DImode)
2664     submode = SImode;
2665
2666   /* Before splitting mem-mem moves, force one operand into a
2667      register.  */
2668   if (!no_new_pseudos && MEM_P (operands[0]) && MEM_P (operands[1]))
2669     {
2670 #if DEBUG0
2671       fprintf (stderr, "force_reg...\n");
2672       debug_rtx (operands[1]);
2673 #endif
2674       operands[1] = force_reg (mode, operands[1]);
2675 #if DEBUG0
2676       debug_rtx (operands[1]);
2677 #endif
2678     }
2679
2680   parts = 2;
2681
2682 #if DEBUG_SPLIT
2683   fprintf (stderr, "\nsplit_move %d all=%d\n", no_new_pseudos, split_all);
2684   debug_rtx (operands[0]);
2685   debug_rtx (operands[1]);
2686 #endif
2687
2688   /* Note that split_all is not used to select the api after this
2689      point, so it's safe to set it to 3 even with define_insn.  */
2690   /* None of the chips can move SI operands to sp-relative addresses,
2691      so we always split those.  */
2692   if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
2693     split_all = 3;
2694
2695   /* We don't need to split these.  */
2696   if (TARGET_A24
2697       && split_all != 3
2698       && (mode == SImode || mode == PSImode)
2699       && !(GET_CODE (operands[1]) == MEM
2700            && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2701     return 0;
2702
2703   /* First, enumerate the subregs we'll be dealing with.  */
2704   for (si = 0; si < parts; si++)
2705     {
2706       d[si] =
2707         m32c_subreg (submode, operands[0], mode,
2708                      si * GET_MODE_SIZE (submode));
2709       s[si] =
2710         m32c_subreg (submode, operands[1], mode,
2711                      si * GET_MODE_SIZE (submode));
2712     }
2713
2714   /* Split pushes by emitting a sequence of smaller pushes.  */
2715   if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
2716     {
2717       for (si = parts - 1; si >= 0; si--)
2718         {
2719           ops[opi++] = gen_rtx_MEM (submode,
2720                                     gen_rtx_PRE_DEC (Pmode,
2721                                                      gen_rtx_REG (Pmode,
2722                                                                   SP_REGNO)));
2723           ops[opi++] = s[si];
2724         }
2725
2726       rv = 1;
2727     }
2728   /* Likewise for pops.  */
2729   else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
2730     {
2731       for (di = 0; di < parts; di++)
2732         {
2733           ops[opi++] = d[di];
2734           ops[opi++] = gen_rtx_MEM (submode,
2735                                     gen_rtx_POST_INC (Pmode,
2736                                                       gen_rtx_REG (Pmode,
2737                                                                    SP_REGNO)));
2738         }
2739       rv = 1;
2740     }
2741   else if (split_all)
2742     {
2743       /* if d[di] == s[si] for any di < si, we'll early clobber. */
2744       for (di = 0; di < parts - 1; di++)
2745         for (si = di + 1; si < parts; si++)
2746           if (reg_mentioned_p (d[di], s[si]))
2747             rev = 1;
2748
2749       if (rev)
2750         for (si = 0; si < parts; si++)
2751           {
2752             ops[opi++] = d[si];
2753             ops[opi++] = s[si];
2754           }
2755       else
2756         for (si = parts - 1; si >= 0; si--)
2757           {
2758             ops[opi++] = d[si];
2759             ops[opi++] = s[si];
2760           }
2761       rv = 1;
2762     }
2763   /* Now emit any moves we may have accumulated.  */
2764   if (rv && split_all != 3)
2765     {
2766       int i;
2767       for (i = 2; i < opi; i += 2)
2768         emit_move_insn (ops[i], ops[i + 1]);
2769     }
2770   return rv;
2771 }
2772
2773 /* The m32c only has one shift, but it takes a signed count.  GCC
2774    doesn't want this, so we fake it by negating any shift count when
2775    we're pretending to shift the other way.  */
2776 int
2777 m32c_prepare_shift (rtx * operands, int scale, int bits)
2778 {
2779   rtx temp;
2780   if (GET_CODE (operands[2]) == CONST_INT
2781       && INTVAL (operands[2]) <= (1 << (bits - 1))
2782       && INTVAL (operands[2]) >= -(1 << (bits - 1)))
2783     {
2784       operands[2] = GEN_INT (scale * INTVAL (operands[2]));
2785       return 0;
2786     }
2787   if (scale < 0)
2788     {
2789       temp = gen_reg_rtx (QImode);
2790       if (GET_CODE (operands[2]) == CONST_INT)
2791         temp = GEN_INT (-INTVAL (operands[2]));
2792       else
2793         emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
2794     }
2795   else
2796     temp = operands[2];
2797   operands[2] = temp;
2798   return 0;
2799 }
2800
2801 /* The m32c has a limited range of operations that work on PSImode
2802    values; we have to expand to SI, do the math, and truncate back to
2803    PSI.  Yes, this is expensive, but hopefully gcc will learn to avoid
2804    those cases.  */
2805 void
2806 m32c_expand_neg_mulpsi3 (rtx * operands)
2807 {
2808   /* operands: a = b * i */
2809   rtx temp1; /* b as SI */
2810   rtx temp2; /* -b as SI */
2811   rtx temp3; /* -b as PSI */
2812   rtx scale;
2813
2814   temp1 = gen_reg_rtx (SImode);
2815   temp2 = gen_reg_rtx (SImode);
2816   temp3 = gen_reg_rtx (PSImode);
2817   scale = GEN_INT (- INTVAL (operands[2]));
2818
2819   emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
2820   emit_insn (gen_negsi2 (temp2, temp1));
2821   emit_insn (gen_truncsipsi2 (temp3, temp2));
2822   emit_insn (gen_mulpsi3 (operands[0], temp3, scale));
2823 }
2824
2825 /* Pattern Output Functions */
2826
2827 /* Returns TRUE if the current function is a leaf, and thus we can
2828    determine which registers an interrupt function really needs to
2829    save.  The logic below is mostly about finding the insn sequence
2830    that's the function, versus any sequence that might be open for the
2831    current insn.  */
2832 static int
2833 m32c_leaf_function_p (void)
2834 {
2835   rtx saved_first, saved_last;
2836   struct sequence_stack *seq;
2837   int rv;
2838
2839   saved_first = cfun->emit->x_first_insn;
2840   saved_last = cfun->emit->x_last_insn;
2841   for (seq = cfun->emit->sequence_stack; seq && seq->next; seq = seq->next)
2842     ;
2843   if (seq)
2844     {
2845       cfun->emit->x_first_insn = seq->first;
2846       cfun->emit->x_last_insn = seq->last;
2847     }
2848
2849   rv = leaf_function_p ();
2850
2851   cfun->emit->x_first_insn = saved_first;
2852   cfun->emit->x_last_insn = saved_last;
2853   return rv;
2854 }
2855
2856 /* Returns TRUE if the current function needs to use the ENTER/EXIT
2857    opcodes.  If the function doesn't need the frame base or stack
2858    pointer, it can use the simpler RTS opcode.  */
2859 static bool
2860 m32c_function_needs_enter (void)
2861 {
2862   rtx insn;
2863   struct sequence_stack *seq;
2864   rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
2865   rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
2866
2867   insn = get_insns ();
2868   for (seq = cfun->emit->sequence_stack;
2869        seq;
2870        insn = seq->first, seq = seq->next);
2871
2872   while (insn)
2873     {
2874       if (reg_mentioned_p (sp, insn))
2875         return true;
2876       if (reg_mentioned_p (fb, insn))
2877         return true;
2878       insn = NEXT_INSN (insn);
2879     }
2880   return false;
2881 }
2882
2883 /* Mark all the subexpressions of the PARALLEL rtx PAR as
2884    frame-related.  Return PAR.
2885
2886    dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
2887    PARALLEL rtx other than the first if they do not have the
2888    FRAME_RELATED flag set on them.  So this function is handy for
2889    marking up 'enter' instructions.  */
2890 static rtx
2891 m32c_all_frame_related (rtx par)
2892 {
2893   int len = XVECLEN (par, 0);
2894   int i;
2895
2896   for (i = 0; i < len; i++)
2897     F (XVECEXP (par, 0, i));
2898
2899   return par;
2900 }
2901
2902 /* Emits the prologue.  See the frame layout comment earlier in this
2903    file.  We can reserve up to 256 bytes with the ENTER opcode, beyond
2904    that we manually update sp.  */
2905 void
2906 m32c_emit_prologue (void)
2907 {
2908   int frame_size, extra_frame_size = 0, reg_save_size;
2909   int complex_prologue = 0;
2910
2911   cfun->machine->is_leaf = m32c_leaf_function_p ();
2912   if (interrupt_p (cfun->decl))
2913     {
2914       cfun->machine->is_interrupt = 1;
2915       complex_prologue = 1;
2916     }
2917
2918   reg_save_size = m32c_pushm_popm (PP_justcount);
2919
2920   if (interrupt_p (cfun->decl))
2921     emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
2922
2923   frame_size =
2924     m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
2925   if (frame_size == 0
2926       && !cfun->machine->is_interrupt
2927       && !m32c_function_needs_enter ())
2928     cfun->machine->use_rts = 1;
2929
2930   if (frame_size > 254)
2931     {
2932       extra_frame_size = frame_size - 254;
2933       frame_size = 254;
2934     }
2935   if (cfun->machine->use_rts == 0)
2936     F (emit_insn (m32c_all_frame_related
2937                   (TARGET_A16
2938                    ? gen_prologue_enter_16 (GEN_INT (frame_size))
2939                    : gen_prologue_enter_24 (GEN_INT (frame_size)))));
2940
2941   if (extra_frame_size)
2942     {
2943       complex_prologue = 1;
2944       if (TARGET_A16)
2945         F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
2946                                   gen_rtx_REG (HImode, SP_REGNO),
2947                                   GEN_INT (-extra_frame_size))));
2948       else
2949         F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
2950                                    gen_rtx_REG (PSImode, SP_REGNO),
2951                                    GEN_INT (-extra_frame_size))));
2952     }
2953
2954   complex_prologue += m32c_pushm_popm (PP_pushm);
2955
2956   /* This just emits a comment into the .s file for debugging.  */
2957   if (complex_prologue)
2958     emit_insn (gen_prologue_end ());
2959 }
2960
2961 /* Likewise, for the epilogue.  The only exception is that, for
2962    interrupts, we must manually unwind the frame as the REIT opcode
2963    doesn't do that.  */
2964 void
2965 m32c_emit_epilogue (void)
2966 {
2967   /* This just emits a comment into the .s file for debugging.  */
2968   if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
2969     emit_insn (gen_epilogue_start ());
2970
2971   m32c_pushm_popm (PP_popm);
2972
2973   if (cfun->machine->is_interrupt)
2974     {
2975       enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
2976
2977       emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
2978                       gen_rtx_REG (spmode, FP_REGNO));
2979       emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
2980                       gen_rtx_REG (spmode, A0_REGNO));
2981       if (TARGET_A16)
2982         emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
2983       else
2984         emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
2985       emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
2986       emit_jump_insn (gen_epilogue_reit (GEN_INT (TARGET_A16 ? 4 : 6)));
2987     }
2988   else if (cfun->machine->use_rts)
2989     emit_jump_insn (gen_epilogue_rts ());
2990   else
2991     emit_jump_insn (gen_epilogue_exitd (GEN_INT (TARGET_A16 ? 2 : 4)));
2992   emit_barrier ();
2993 }
2994
2995 void
2996 m32c_emit_eh_epilogue (rtx ret_addr)
2997 {
2998   /* R0[R2] has the stack adjustment.  R1[R3] has the address to
2999      return to.  We have to fudge the stack, pop everything, pop SP
3000      (fudged), and return (fudged).  This is actually easier to do in
3001      assembler, so punt to libgcc.  */
3002   emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
3003   /*  emit_insn (gen_rtx_CLOBBER (HImode, gen_rtx_REG (HImode, R0L_REGNO))); */
3004   emit_barrier ();
3005 }
3006
3007 /* The Global `targetm' Variable. */
3008
3009 struct gcc_target targetm = TARGET_INITIALIZER;
3010
3011 #include "gt-m32c.h"