1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "stringpool.h"
29 #include "stor-layout.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
45 #include "basic-block.h"
47 #include "diagnostic-core.h"
48 #include "sched-int.h"
51 #include "target-def.h"
52 #include "common/common-target.h"
54 #include "hash-table.h"
55 #include "langhooks.h"
56 #include "pointer-set.h"
58 #include "basic-block.h"
59 #include "tree-ssa-alias.h"
60 #include "internal-fn.h"
61 #include "gimple-fold.h"
63 #include "gimple-expr.h"
72 #include "tm-constrs.h"
73 #include "sel-sched.h"
78 /* This is used for communication between ASM_OUTPUT_LABEL and
79 ASM_OUTPUT_LABELREF. */
80 int ia64_asm_output_label
= 0;
82 /* Register names for ia64_expand_prologue. */
83 static const char * const ia64_reg_numbers
[96] =
84 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
85 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
86 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
87 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
88 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
89 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
90 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
91 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
92 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
93 "r104","r105","r106","r107","r108","r109","r110","r111",
94 "r112","r113","r114","r115","r116","r117","r118","r119",
95 "r120","r121","r122","r123","r124","r125","r126","r127"};
97 /* ??? These strings could be shared with REGISTER_NAMES. */
98 static const char * const ia64_input_reg_names
[8] =
99 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
101 /* ??? These strings could be shared with REGISTER_NAMES. */
102 static const char * const ia64_local_reg_names
[80] =
103 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
104 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
105 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
106 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
107 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
108 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
109 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
110 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
111 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
112 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
114 /* ??? These strings could be shared with REGISTER_NAMES. */
115 static const char * const ia64_output_reg_names
[8] =
116 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
118 /* Variables which are this size or smaller are put in the sdata/sbss
121 unsigned int ia64_section_threshold
;
123 /* The following variable is used by the DFA insn scheduler. The value is
124 TRUE if we do insn bundling instead of insn scheduling. */
136 number_of_ia64_frame_regs
139 /* Structure to be filled in by ia64_compute_frame_size with register
140 save masks and offsets for the current function. */
142 struct ia64_frame_info
144 HOST_WIDE_INT total_size
; /* size of the stack frame, not including
145 the caller's scratch area. */
146 HOST_WIDE_INT spill_cfa_off
; /* top of the reg spill area from the cfa. */
147 HOST_WIDE_INT spill_size
; /* size of the gr/br/fr spill area. */
148 HOST_WIDE_INT extra_spill_size
; /* size of spill area for others. */
149 HARD_REG_SET mask
; /* mask of saved registers. */
150 unsigned int gr_used_mask
; /* mask of registers in use as gr spill
151 registers or long-term scratches. */
152 int n_spilled
; /* number of spilled registers. */
153 int r
[number_of_ia64_frame_regs
]; /* Frame related registers. */
154 int n_input_regs
; /* number of input registers used. */
155 int n_local_regs
; /* number of local registers used. */
156 int n_output_regs
; /* number of output registers used. */
157 int n_rotate_regs
; /* number of rotating registers used. */
159 char need_regstk
; /* true if a .regstk directive needed. */
160 char initialized
; /* true if the data is finalized. */
163 /* Current frame information calculated by ia64_compute_frame_size. */
164 static struct ia64_frame_info current_frame_info
;
165 /* The actual registers that are emitted. */
166 static int emitted_frame_related_regs
[number_of_ia64_frame_regs
];
168 static int ia64_first_cycle_multipass_dfa_lookahead (void);
169 static void ia64_dependencies_evaluation_hook (rtx
, rtx
);
170 static void ia64_init_dfa_pre_cycle_insn (void);
171 static rtx
ia64_dfa_pre_cycle_insn (void);
172 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx
, int);
173 static int ia64_dfa_new_cycle (FILE *, int, rtx
, int, int, int *);
174 static void ia64_h_i_d_extended (void);
175 static void * ia64_alloc_sched_context (void);
176 static void ia64_init_sched_context (void *, bool);
177 static void ia64_set_sched_context (void *);
178 static void ia64_clear_sched_context (void *);
179 static void ia64_free_sched_context (void *);
180 static int ia64_mode_to_int (enum machine_mode
);
181 static void ia64_set_sched_flags (spec_info_t
);
182 static ds_t
ia64_get_insn_spec_ds (rtx
);
183 static ds_t
ia64_get_insn_checked_ds (rtx
);
184 static bool ia64_skip_rtx_p (const_rtx
);
185 static int ia64_speculate_insn (rtx
, ds_t
, rtx
*);
186 static bool ia64_needs_block_p (ds_t
);
187 static rtx
ia64_gen_spec_check (rtx
, rtx
, ds_t
);
188 static int ia64_spec_check_p (rtx
);
189 static int ia64_spec_check_src_p (rtx
);
190 static rtx
gen_tls_get_addr (void);
191 static rtx
gen_thread_pointer (void);
192 static int find_gr_spill (enum ia64_frame_regs
, int);
193 static int next_scratch_gr_reg (void);
194 static void mark_reg_gr_used_mask (rtx
, void *);
195 static void ia64_compute_frame_size (HOST_WIDE_INT
);
196 static void setup_spill_pointers (int, rtx
, HOST_WIDE_INT
);
197 static void finish_spill_pointers (void);
198 static rtx
spill_restore_mem (rtx
, HOST_WIDE_INT
);
199 static void do_spill (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
, rtx
);
200 static void do_restore (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
);
201 static rtx
gen_movdi_x (rtx
, rtx
, rtx
);
202 static rtx
gen_fr_spill_x (rtx
, rtx
, rtx
);
203 static rtx
gen_fr_restore_x (rtx
, rtx
, rtx
);
205 static void ia64_option_override (void);
206 static bool ia64_can_eliminate (const int, const int);
207 static enum machine_mode
hfa_element_mode (const_tree
, bool);
208 static void ia64_setup_incoming_varargs (cumulative_args_t
, enum machine_mode
,
210 static int ia64_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
212 static rtx
ia64_function_arg_1 (cumulative_args_t
, enum machine_mode
,
213 const_tree
, bool, bool);
214 static rtx
ia64_function_arg (cumulative_args_t
, enum machine_mode
,
216 static rtx
ia64_function_incoming_arg (cumulative_args_t
,
217 enum machine_mode
, const_tree
, bool);
218 static void ia64_function_arg_advance (cumulative_args_t
, enum machine_mode
,
220 static unsigned int ia64_function_arg_boundary (enum machine_mode
,
222 static bool ia64_function_ok_for_sibcall (tree
, tree
);
223 static bool ia64_return_in_memory (const_tree
, const_tree
);
224 static rtx
ia64_function_value (const_tree
, const_tree
, bool);
225 static rtx
ia64_libcall_value (enum machine_mode
, const_rtx
);
226 static bool ia64_function_value_regno_p (const unsigned int);
227 static int ia64_register_move_cost (enum machine_mode
, reg_class_t
,
229 static int ia64_memory_move_cost (enum machine_mode mode
, reg_class_t
,
231 static bool ia64_rtx_costs (rtx
, int, int, int, int *, bool);
232 static int ia64_unspec_may_trap_p (const_rtx
, unsigned);
233 static void fix_range (const char *);
234 static struct machine_function
* ia64_init_machine_status (void);
235 static void emit_insn_group_barriers (FILE *);
236 static void emit_all_insn_group_barriers (FILE *);
237 static void final_emit_insn_group_barriers (FILE *);
238 static void emit_predicate_relation_info (void);
239 static void ia64_reorg (void);
240 static bool ia64_in_small_data_p (const_tree
);
241 static void process_epilogue (FILE *, rtx
, bool, bool);
243 static bool ia64_assemble_integer (rtx
, unsigned int, int);
244 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT
);
245 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT
);
246 static void ia64_output_function_end_prologue (FILE *);
248 static void ia64_print_operand (FILE *, rtx
, int);
249 static void ia64_print_operand_address (FILE *, rtx
);
250 static bool ia64_print_operand_punct_valid_p (unsigned char code
);
252 static int ia64_issue_rate (void);
253 static int ia64_adjust_cost_2 (rtx
, int, rtx
, int, dw_t
);
254 static void ia64_sched_init (FILE *, int, int);
255 static void ia64_sched_init_global (FILE *, int, int);
256 static void ia64_sched_finish_global (FILE *, int);
257 static void ia64_sched_finish (FILE *, int);
258 static int ia64_dfa_sched_reorder (FILE *, int, rtx
*, int *, int, int);
259 static int ia64_sched_reorder (FILE *, int, rtx
*, int *, int);
260 static int ia64_sched_reorder2 (FILE *, int, rtx
*, int *, int);
261 static int ia64_variable_issue (FILE *, int, rtx
, int);
263 static void ia64_asm_unwind_emit (FILE *, rtx
);
264 static void ia64_asm_emit_except_personality (rtx
);
265 static void ia64_asm_init_sections (void);
267 static enum unwind_info_type
ia64_debug_unwind_info (void);
269 static struct bundle_state
*get_free_bundle_state (void);
270 static void free_bundle_state (struct bundle_state
*);
271 static void initiate_bundle_states (void);
272 static void finish_bundle_states (void);
273 static int insert_bundle_state (struct bundle_state
*);
274 static void initiate_bundle_state_table (void);
275 static void finish_bundle_state_table (void);
276 static int try_issue_nops (struct bundle_state
*, int);
277 static int try_issue_insn (struct bundle_state
*, rtx
);
278 static void issue_nops_and_insn (struct bundle_state
*, int, rtx
, int, int);
279 static int get_max_pos (state_t
);
280 static int get_template (state_t
, int);
282 static rtx
get_next_important_insn (rtx
, rtx
);
283 static bool important_for_bundling_p (rtx
);
284 static bool unknown_for_bundling_p (rtx
);
285 static void bundling (FILE *, int, rtx
, rtx
);
287 static void ia64_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
288 HOST_WIDE_INT
, tree
);
289 static void ia64_file_start (void);
290 static void ia64_globalize_decl_name (FILE *, tree
);
292 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED
;
293 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED
;
294 static section
*ia64_select_rtx_section (enum machine_mode
, rtx
,
295 unsigned HOST_WIDE_INT
);
296 static void ia64_output_dwarf_dtprel (FILE *, int, rtx
)
298 static unsigned int ia64_section_type_flags (tree
, const char *, int);
299 static void ia64_init_libfuncs (void)
301 static void ia64_hpux_init_libfuncs (void)
303 static void ia64_sysv4_init_libfuncs (void)
305 static void ia64_vms_init_libfuncs (void)
307 static void ia64_soft_fp_init_libfuncs (void)
309 static bool ia64_vms_valid_pointer_mode (enum machine_mode mode
)
311 static tree
ia64_vms_common_object_attribute (tree
*, tree
, tree
, int, bool *)
314 static tree
ia64_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
315 static tree
ia64_handle_version_id_attribute (tree
*, tree
, tree
, int, bool *);
316 static void ia64_encode_section_info (tree
, rtx
, int);
317 static rtx
ia64_struct_value_rtx (tree
, int);
318 static tree
ia64_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
319 static bool ia64_scalar_mode_supported_p (enum machine_mode mode
);
320 static bool ia64_vector_mode_supported_p (enum machine_mode mode
);
321 static bool ia64_legitimate_constant_p (enum machine_mode
, rtx
);
322 static bool ia64_legitimate_address_p (enum machine_mode
, rtx
, bool);
323 static bool ia64_cannot_force_const_mem (enum machine_mode
, rtx
);
324 static const char *ia64_mangle_type (const_tree
);
325 static const char *ia64_invalid_conversion (const_tree
, const_tree
);
326 static const char *ia64_invalid_unary_op (int, const_tree
);
327 static const char *ia64_invalid_binary_op (int, const_tree
, const_tree
);
328 static enum machine_mode
ia64_c_mode_for_suffix (char);
329 static void ia64_trampoline_init (rtx
, tree
, rtx
);
330 static void ia64_override_options_after_change (void);
331 static bool ia64_member_type_forces_blk (const_tree
, enum machine_mode
);
333 static tree
ia64_builtin_decl (unsigned, bool);
335 static reg_class_t
ia64_preferred_reload_class (rtx
, reg_class_t
);
336 static enum machine_mode
ia64_get_reg_raw_mode (int regno
);
337 static section
* ia64_hpux_function_section (tree
, enum node_frequency
,
340 static bool ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
341 const unsigned char *sel
);
343 #define MAX_VECT_LEN 8
345 struct expand_vec_perm_d
347 rtx target
, op0
, op1
;
348 unsigned char perm
[MAX_VECT_LEN
];
349 enum machine_mode vmode
;
355 static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
);
358 /* Table of valid machine attributes. */
359 static const struct attribute_spec ia64_attribute_table
[] =
361 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
362 affects_type_identity } */
363 { "syscall_linkage", 0, 0, false, true, true, NULL
, false },
364 { "model", 1, 1, true, false, false, ia64_handle_model_attribute
,
366 #if TARGET_ABI_OPEN_VMS
367 { "common_object", 1, 1, true, false, false,
368 ia64_vms_common_object_attribute
, false },
370 { "version_id", 1, 1, true, false, false,
371 ia64_handle_version_id_attribute
, false },
372 { NULL
, 0, 0, false, false, false, NULL
, false }
375 /* Initialize the GCC target structure. */
376 #undef TARGET_ATTRIBUTE_TABLE
377 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
379 #undef TARGET_INIT_BUILTINS
380 #define TARGET_INIT_BUILTINS ia64_init_builtins
382 #undef TARGET_EXPAND_BUILTIN
383 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
385 #undef TARGET_BUILTIN_DECL
386 #define TARGET_BUILTIN_DECL ia64_builtin_decl
388 #undef TARGET_ASM_BYTE_OP
389 #define TARGET_ASM_BYTE_OP "\tdata1\t"
390 #undef TARGET_ASM_ALIGNED_HI_OP
391 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
392 #undef TARGET_ASM_ALIGNED_SI_OP
393 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
394 #undef TARGET_ASM_ALIGNED_DI_OP
395 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
396 #undef TARGET_ASM_UNALIGNED_HI_OP
397 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
398 #undef TARGET_ASM_UNALIGNED_SI_OP
399 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
400 #undef TARGET_ASM_UNALIGNED_DI_OP
401 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
402 #undef TARGET_ASM_INTEGER
403 #define TARGET_ASM_INTEGER ia64_assemble_integer
405 #undef TARGET_OPTION_OVERRIDE
406 #define TARGET_OPTION_OVERRIDE ia64_option_override
408 #undef TARGET_ASM_FUNCTION_PROLOGUE
409 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
410 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
411 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
412 #undef TARGET_ASM_FUNCTION_EPILOGUE
413 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
415 #undef TARGET_PRINT_OPERAND
416 #define TARGET_PRINT_OPERAND ia64_print_operand
417 #undef TARGET_PRINT_OPERAND_ADDRESS
418 #define TARGET_PRINT_OPERAND_ADDRESS ia64_print_operand_address
419 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
420 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ia64_print_operand_punct_valid_p
422 #undef TARGET_IN_SMALL_DATA_P
423 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
425 #undef TARGET_SCHED_ADJUST_COST_2
426 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
427 #undef TARGET_SCHED_ISSUE_RATE
428 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
429 #undef TARGET_SCHED_VARIABLE_ISSUE
430 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
431 #undef TARGET_SCHED_INIT
432 #define TARGET_SCHED_INIT ia64_sched_init
433 #undef TARGET_SCHED_FINISH
434 #define TARGET_SCHED_FINISH ia64_sched_finish
435 #undef TARGET_SCHED_INIT_GLOBAL
436 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
437 #undef TARGET_SCHED_FINISH_GLOBAL
438 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
439 #undef TARGET_SCHED_REORDER
440 #define TARGET_SCHED_REORDER ia64_sched_reorder
441 #undef TARGET_SCHED_REORDER2
442 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
444 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
445 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
447 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
448 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
450 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
451 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
452 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
453 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
455 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
456 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
457 ia64_first_cycle_multipass_dfa_lookahead_guard
459 #undef TARGET_SCHED_DFA_NEW_CYCLE
460 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
462 #undef TARGET_SCHED_H_I_D_EXTENDED
463 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
465 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
466 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
468 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
469 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
471 #undef TARGET_SCHED_SET_SCHED_CONTEXT
472 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
474 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
475 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
477 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
478 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
480 #undef TARGET_SCHED_SET_SCHED_FLAGS
481 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
483 #undef TARGET_SCHED_GET_INSN_SPEC_DS
484 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
486 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
487 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
489 #undef TARGET_SCHED_SPECULATE_INSN
490 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
492 #undef TARGET_SCHED_NEEDS_BLOCK_P
493 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
495 #undef TARGET_SCHED_GEN_SPEC_CHECK
496 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
498 #undef TARGET_SCHED_SKIP_RTX_P
499 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
501 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
502 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
503 #undef TARGET_ARG_PARTIAL_BYTES
504 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
505 #undef TARGET_FUNCTION_ARG
506 #define TARGET_FUNCTION_ARG ia64_function_arg
507 #undef TARGET_FUNCTION_INCOMING_ARG
508 #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg
509 #undef TARGET_FUNCTION_ARG_ADVANCE
510 #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance
511 #undef TARGET_FUNCTION_ARG_BOUNDARY
512 #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary
514 #undef TARGET_ASM_OUTPUT_MI_THUNK
515 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
516 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
517 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
519 #undef TARGET_ASM_FILE_START
520 #define TARGET_ASM_FILE_START ia64_file_start
522 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
523 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
525 #undef TARGET_REGISTER_MOVE_COST
526 #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost
527 #undef TARGET_MEMORY_MOVE_COST
528 #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost
529 #undef TARGET_RTX_COSTS
530 #define TARGET_RTX_COSTS ia64_rtx_costs
531 #undef TARGET_ADDRESS_COST
532 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
534 #undef TARGET_UNSPEC_MAY_TRAP_P
535 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
537 #undef TARGET_MACHINE_DEPENDENT_REORG
538 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
540 #undef TARGET_ENCODE_SECTION_INFO
541 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
543 #undef TARGET_SECTION_TYPE_FLAGS
544 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
547 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
548 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
551 /* ??? Investigate. */
553 #undef TARGET_PROMOTE_PROTOTYPES
554 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
557 #undef TARGET_FUNCTION_VALUE
558 #define TARGET_FUNCTION_VALUE ia64_function_value
559 #undef TARGET_LIBCALL_VALUE
560 #define TARGET_LIBCALL_VALUE ia64_libcall_value
561 #undef TARGET_FUNCTION_VALUE_REGNO_P
562 #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p
564 #undef TARGET_STRUCT_VALUE_RTX
565 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
566 #undef TARGET_RETURN_IN_MEMORY
567 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
568 #undef TARGET_SETUP_INCOMING_VARARGS
569 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
570 #undef TARGET_STRICT_ARGUMENT_NAMING
571 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
572 #undef TARGET_MUST_PASS_IN_STACK
573 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
574 #undef TARGET_GET_RAW_RESULT_MODE
575 #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode
576 #undef TARGET_GET_RAW_ARG_MODE
577 #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode
579 #undef TARGET_MEMBER_TYPE_FORCES_BLK
580 #define TARGET_MEMBER_TYPE_FORCES_BLK ia64_member_type_forces_blk
582 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
583 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
585 #undef TARGET_ASM_UNWIND_EMIT
586 #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit
587 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
588 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality
589 #undef TARGET_ASM_INIT_SECTIONS
590 #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections
592 #undef TARGET_DEBUG_UNWIND_INFO
593 #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info
595 #undef TARGET_SCALAR_MODE_SUPPORTED_P
596 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
597 #undef TARGET_VECTOR_MODE_SUPPORTED_P
598 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
600 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
601 in an order different from the specified program order. */
602 #undef TARGET_RELAXED_ORDERING
603 #define TARGET_RELAXED_ORDERING true
605 #undef TARGET_LEGITIMATE_CONSTANT_P
606 #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p
607 #undef TARGET_LEGITIMATE_ADDRESS_P
608 #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p
610 #undef TARGET_CANNOT_FORCE_CONST_MEM
611 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
613 #undef TARGET_MANGLE_TYPE
614 #define TARGET_MANGLE_TYPE ia64_mangle_type
616 #undef TARGET_INVALID_CONVERSION
617 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
618 #undef TARGET_INVALID_UNARY_OP
619 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
620 #undef TARGET_INVALID_BINARY_OP
621 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
623 #undef TARGET_C_MODE_FOR_SUFFIX
624 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
626 #undef TARGET_CAN_ELIMINATE
627 #define TARGET_CAN_ELIMINATE ia64_can_eliminate
629 #undef TARGET_TRAMPOLINE_INIT
630 #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
632 #undef TARGET_CAN_USE_DOLOOP_P
633 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
634 #undef TARGET_INVALID_WITHIN_DOLOOP
635 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
637 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
638 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
640 #undef TARGET_PREFERRED_RELOAD_CLASS
641 #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class
643 #undef TARGET_DELAY_SCHED2
644 #define TARGET_DELAY_SCHED2 true
646 /* Variable tracking should be run after all optimizations which
647 change order of insns. It also needs a valid CFG. */
648 #undef TARGET_DELAY_VARTRACK
649 #define TARGET_DELAY_VARTRACK true
651 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
652 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK ia64_vectorize_vec_perm_const_ok
654 struct gcc_target targetm
= TARGET_INITIALIZER
;
658 ADDR_AREA_NORMAL
, /* normal address area */
659 ADDR_AREA_SMALL
/* addressable by "addl" (-2MB < addr < 2MB) */
663 static GTY(()) tree small_ident1
;
664 static GTY(()) tree small_ident2
;
669 if (small_ident1
== 0)
671 small_ident1
= get_identifier ("small");
672 small_ident2
= get_identifier ("__small__");
676 /* Retrieve the address area that has been chosen for the given decl. */
678 static ia64_addr_area
679 ia64_get_addr_area (tree decl
)
683 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
689 id
= TREE_VALUE (TREE_VALUE (model_attr
));
690 if (id
== small_ident1
|| id
== small_ident2
)
691 return ADDR_AREA_SMALL
;
693 return ADDR_AREA_NORMAL
;
697 ia64_handle_model_attribute (tree
*node
, tree name
, tree args
,
698 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
700 ia64_addr_area addr_area
= ADDR_AREA_NORMAL
;
702 tree arg
, decl
= *node
;
705 arg
= TREE_VALUE (args
);
706 if (arg
== small_ident1
|| arg
== small_ident2
)
708 addr_area
= ADDR_AREA_SMALL
;
712 warning (OPT_Wattributes
, "invalid argument of %qE attribute",
714 *no_add_attrs
= true;
717 switch (TREE_CODE (decl
))
720 if ((DECL_CONTEXT (decl
) && TREE_CODE (DECL_CONTEXT (decl
))
722 && !TREE_STATIC (decl
))
724 error_at (DECL_SOURCE_LOCATION (decl
),
725 "an address area attribute cannot be specified for "
727 *no_add_attrs
= true;
729 area
= ia64_get_addr_area (decl
);
730 if (area
!= ADDR_AREA_NORMAL
&& addr_area
!= area
)
732 error ("address area of %q+D conflicts with previous "
733 "declaration", decl
);
734 *no_add_attrs
= true;
739 error_at (DECL_SOURCE_LOCATION (decl
),
740 "address area attribute cannot be specified for "
742 *no_add_attrs
= true;
746 warning (OPT_Wattributes
, "%qE attribute ignored",
748 *no_add_attrs
= true;
755 /* Part of the low level implementation of DEC Ada pragma Common_Object which
756 enables the shared use of variables stored in overlaid linker areas
757 corresponding to the use of Fortran COMMON. */
760 ia64_vms_common_object_attribute (tree
*node
, tree name
, tree args
,
761 int flags ATTRIBUTE_UNUSED
,
767 gcc_assert (DECL_P (decl
));
769 DECL_COMMON (decl
) = 1;
770 id
= TREE_VALUE (args
);
771 if (TREE_CODE (id
) != IDENTIFIER_NODE
&& TREE_CODE (id
) != STRING_CST
)
773 error ("%qE attribute requires a string constant argument", name
);
774 *no_add_attrs
= true;
780 /* Part of the low level implementation of DEC Ada pragma Common_Object. */
783 ia64_vms_output_aligned_decl_common (FILE *file
, tree decl
, const char *name
,
784 unsigned HOST_WIDE_INT size
,
787 tree attr
= DECL_ATTRIBUTES (decl
);
790 attr
= lookup_attribute ("common_object", attr
);
793 tree id
= TREE_VALUE (TREE_VALUE (attr
));
796 if (TREE_CODE (id
) == IDENTIFIER_NODE
)
797 name
= IDENTIFIER_POINTER (id
);
798 else if (TREE_CODE (id
) == STRING_CST
)
799 name
= TREE_STRING_POINTER (id
);
803 fprintf (file
, "\t.vms_common\t\"%s\",", name
);
806 fprintf (file
, "%s", COMMON_ASM_OP
);
808 /* Code from elfos.h. */
809 assemble_name (file
, name
);
810 fprintf (file
, ","HOST_WIDE_INT_PRINT_UNSIGNED
",%u",
811 size
, align
/ BITS_PER_UNIT
);
817 ia64_encode_addr_area (tree decl
, rtx symbol
)
821 flags
= SYMBOL_REF_FLAGS (symbol
);
822 switch (ia64_get_addr_area (decl
))
824 case ADDR_AREA_NORMAL
: break;
825 case ADDR_AREA_SMALL
: flags
|= SYMBOL_FLAG_SMALL_ADDR
; break;
826 default: gcc_unreachable ();
828 SYMBOL_REF_FLAGS (symbol
) = flags
;
832 ia64_encode_section_info (tree decl
, rtx rtl
, int first
)
834 default_encode_section_info (decl
, rtl
, first
);
836 /* Careful not to prod global register variables. */
837 if (TREE_CODE (decl
) == VAR_DECL
838 && GET_CODE (DECL_RTL (decl
)) == MEM
839 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == SYMBOL_REF
840 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
841 ia64_encode_addr_area (decl
, XEXP (rtl
, 0));
844 /* Return 1 if the operands of a move are ok. */
847 ia64_move_ok (rtx dst
, rtx src
)
849 /* If we're under init_recog_no_volatile, we'll not be able to use
850 memory_operand. So check the code directly and don't worry about
851 the validity of the underlying address, which should have been
852 checked elsewhere anyway. */
853 if (GET_CODE (dst
) != MEM
)
855 if (GET_CODE (src
) == MEM
)
857 if (register_operand (src
, VOIDmode
))
860 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
861 if (INTEGRAL_MODE_P (GET_MODE (dst
)))
862 return src
== const0_rtx
;
864 return satisfies_constraint_G (src
);
867 /* Return 1 if the operands are ok for a floating point load pair. */
870 ia64_load_pair_ok (rtx dst
, rtx src
)
872 /* ??? There is a thinko in the implementation of the "x" constraint and the
873 FP_REGS class. The constraint will also reject (reg f30:TI) so we must
874 also return false for it. */
875 if (GET_CODE (dst
) != REG
876 || !(FP_REGNO_P (REGNO (dst
)) && FP_REGNO_P (REGNO (dst
) + 1)))
878 if (GET_CODE (src
) != MEM
|| MEM_VOLATILE_P (src
))
880 switch (GET_CODE (XEXP (src
, 0)))
889 rtx adjust
= XEXP (XEXP (XEXP (src
, 0), 1), 1);
891 if (GET_CODE (adjust
) != CONST_INT
892 || INTVAL (adjust
) != GET_MODE_SIZE (GET_MODE (src
)))
903 addp4_optimize_ok (rtx op1
, rtx op2
)
905 return (basereg_operand (op1
, GET_MODE(op1
)) !=
906 basereg_operand (op2
, GET_MODE(op2
)));
909 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
910 Return the length of the field, or <= 0 on failure. */
913 ia64_depz_field_mask (rtx rop
, rtx rshift
)
915 unsigned HOST_WIDE_INT op
= INTVAL (rop
);
916 unsigned HOST_WIDE_INT shift
= INTVAL (rshift
);
918 /* Get rid of the zero bits we're shifting in. */
921 /* We must now have a solid block of 1's at bit 0. */
922 return exact_log2 (op
+ 1);
925 /* Return the TLS model to use for ADDR. */
927 static enum tls_model
928 tls_symbolic_operand_type (rtx addr
)
930 enum tls_model tls_kind
= TLS_MODEL_NONE
;
932 if (GET_CODE (addr
) == CONST
)
934 if (GET_CODE (XEXP (addr
, 0)) == PLUS
935 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
936 tls_kind
= SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr
, 0), 0));
938 else if (GET_CODE (addr
) == SYMBOL_REF
)
939 tls_kind
= SYMBOL_REF_TLS_MODEL (addr
);
944 /* Returns true if REG (assumed to be a `reg' RTX) is valid for use
945 as a base register. */
948 ia64_reg_ok_for_base_p (const_rtx reg
, bool strict
)
951 && REGNO_OK_FOR_BASE_P (REGNO (reg
)))
954 && (GENERAL_REGNO_P (REGNO (reg
))
955 || !HARD_REGISTER_P (reg
)))
962 ia64_legitimate_address_reg (const_rtx reg
, bool strict
)
964 if ((REG_P (reg
) && ia64_reg_ok_for_base_p (reg
, strict
))
965 || (GET_CODE (reg
) == SUBREG
&& REG_P (XEXP (reg
, 0))
966 && ia64_reg_ok_for_base_p (XEXP (reg
, 0), strict
)))
973 ia64_legitimate_address_disp (const_rtx reg
, const_rtx disp
, bool strict
)
975 if (GET_CODE (disp
) == PLUS
976 && rtx_equal_p (reg
, XEXP (disp
, 0))
977 && (ia64_legitimate_address_reg (XEXP (disp
, 1), strict
)
978 || (CONST_INT_P (XEXP (disp
, 1))
979 && IN_RANGE (INTVAL (XEXP (disp
, 1)), -256, 255))))
985 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
988 ia64_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
991 if (ia64_legitimate_address_reg (x
, strict
))
993 else if ((GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == POST_DEC
)
994 && ia64_legitimate_address_reg (XEXP (x
, 0), strict
)
995 && XEXP (x
, 0) != arg_pointer_rtx
)
997 else if (GET_CODE (x
) == POST_MODIFY
998 && ia64_legitimate_address_reg (XEXP (x
, 0), strict
)
999 && XEXP (x
, 0) != arg_pointer_rtx
1000 && ia64_legitimate_address_disp (XEXP (x
, 0), XEXP (x
, 1), strict
))
1006 /* Return true if X is a constant that is valid for some immediate
1007 field in an instruction. */
1010 ia64_legitimate_constant_p (enum machine_mode mode
, rtx x
)
1012 switch (GET_CODE (x
))
1019 if (GET_MODE (x
) == VOIDmode
|| mode
== SFmode
|| mode
== DFmode
)
1021 return satisfies_constraint_G (x
);
1025 /* ??? Short term workaround for PR 28490. We must make the code here
1026 match the code in ia64_expand_move and move_operand, even though they
1027 are both technically wrong. */
1028 if (tls_symbolic_operand_type (x
) == 0)
1030 HOST_WIDE_INT addend
= 0;
1033 if (GET_CODE (op
) == CONST
1034 && GET_CODE (XEXP (op
, 0)) == PLUS
1035 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1037 addend
= INTVAL (XEXP (XEXP (op
, 0), 1));
1038 op
= XEXP (XEXP (op
, 0), 0);
1041 if (any_offset_symbol_operand (op
, mode
)
1042 || function_operand (op
, mode
))
1044 if (aligned_offset_symbol_operand (op
, mode
))
1045 return (addend
& 0x3fff) == 0;
1051 if (mode
== V2SFmode
)
1052 return satisfies_constraint_Y (x
);
1054 return (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
1055 && GET_MODE_SIZE (mode
) <= 8);
1062 /* Don't allow TLS addresses to get spilled to memory. */
1065 ia64_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
1069 return tls_symbolic_operand_type (x
) != 0;
1072 /* Expand a symbolic constant load. */
1075 ia64_expand_load_address (rtx dest
, rtx src
)
1077 gcc_assert (GET_CODE (dest
) == REG
);
1079 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1080 having to pointer-extend the value afterward. Other forms of address
1081 computation below are also more natural to compute as 64-bit quantities.
1082 If we've been given an SImode destination register, change it. */
1083 if (GET_MODE (dest
) != Pmode
)
1084 dest
= gen_rtx_REG_offset (dest
, Pmode
, REGNO (dest
),
1085 byte_lowpart_offset (Pmode
, GET_MODE (dest
)));
1089 if (small_addr_symbolic_operand (src
, VOIDmode
))
1092 if (TARGET_AUTO_PIC
)
1093 emit_insn (gen_load_gprel64 (dest
, src
));
1094 else if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (src
))
1095 emit_insn (gen_load_fptr (dest
, src
));
1096 else if (sdata_symbolic_operand (src
, VOIDmode
))
1097 emit_insn (gen_load_gprel (dest
, src
));
1100 HOST_WIDE_INT addend
= 0;
1103 /* We did split constant offsets in ia64_expand_move, and we did try
1104 to keep them split in move_operand, but we also allowed reload to
1105 rematerialize arbitrary constants rather than spill the value to
1106 the stack and reload it. So we have to be prepared here to split
1107 them apart again. */
1108 if (GET_CODE (src
) == CONST
)
1110 HOST_WIDE_INT hi
, lo
;
1112 hi
= INTVAL (XEXP (XEXP (src
, 0), 1));
1113 lo
= ((hi
& 0x3fff) ^ 0x2000) - 0x2000;
1119 src
= plus_constant (Pmode
, XEXP (XEXP (src
, 0), 0), hi
);
1123 tmp
= gen_rtx_HIGH (Pmode
, src
);
1124 tmp
= gen_rtx_PLUS (Pmode
, tmp
, pic_offset_table_rtx
);
1125 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1127 tmp
= gen_rtx_LO_SUM (Pmode
, gen_const_mem (Pmode
, dest
), src
);
1128 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1132 tmp
= gen_rtx_PLUS (Pmode
, dest
, GEN_INT (addend
));
1133 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1140 static GTY(()) rtx gen_tls_tga
;
1142 gen_tls_get_addr (void)
1145 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
1149 static GTY(()) rtx thread_pointer_rtx
;
1151 gen_thread_pointer (void)
1153 if (!thread_pointer_rtx
)
1154 thread_pointer_rtx
= gen_rtx_REG (Pmode
, 13);
1155 return thread_pointer_rtx
;
1159 ia64_expand_tls_address (enum tls_model tls_kind
, rtx op0
, rtx op1
,
1160 rtx orig_op1
, HOST_WIDE_INT addend
)
1162 rtx tga_op1
, tga_op2
, tga_ret
, tga_eqv
, tmp
, insns
;
1164 HOST_WIDE_INT addend_lo
, addend_hi
;
1168 case TLS_MODEL_GLOBAL_DYNAMIC
:
1171 tga_op1
= gen_reg_rtx (Pmode
);
1172 emit_insn (gen_load_dtpmod (tga_op1
, op1
));
1174 tga_op2
= gen_reg_rtx (Pmode
);
1175 emit_insn (gen_load_dtprel (tga_op2
, op1
));
1177 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1178 LCT_CONST
, Pmode
, 2, tga_op1
,
1179 Pmode
, tga_op2
, Pmode
);
1181 insns
= get_insns ();
1184 if (GET_MODE (op0
) != Pmode
)
1186 emit_libcall_block (insns
, op0
, tga_ret
, op1
);
1189 case TLS_MODEL_LOCAL_DYNAMIC
:
1190 /* ??? This isn't the completely proper way to do local-dynamic
1191 If the call to __tls_get_addr is used only by a single symbol,
1192 then we should (somehow) move the dtprel to the second arg
1193 to avoid the extra add. */
1196 tga_op1
= gen_reg_rtx (Pmode
);
1197 emit_insn (gen_load_dtpmod (tga_op1
, op1
));
1199 tga_op2
= const0_rtx
;
1201 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1202 LCT_CONST
, Pmode
, 2, tga_op1
,
1203 Pmode
, tga_op2
, Pmode
);
1205 insns
= get_insns ();
1208 tga_eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1210 tmp
= gen_reg_rtx (Pmode
);
1211 emit_libcall_block (insns
, tmp
, tga_ret
, tga_eqv
);
1213 if (!register_operand (op0
, Pmode
))
1214 op0
= gen_reg_rtx (Pmode
);
1217 emit_insn (gen_load_dtprel (op0
, op1
));
1218 emit_insn (gen_adddi3 (op0
, tmp
, op0
));
1221 emit_insn (gen_add_dtprel (op0
, op1
, tmp
));
1224 case TLS_MODEL_INITIAL_EXEC
:
1225 addend_lo
= ((addend
& 0x3fff) ^ 0x2000) - 0x2000;
1226 addend_hi
= addend
- addend_lo
;
1228 op1
= plus_constant (Pmode
, op1
, addend_hi
);
1231 tmp
= gen_reg_rtx (Pmode
);
1232 emit_insn (gen_load_tprel (tmp
, op1
));
1234 if (!register_operand (op0
, Pmode
))
1235 op0
= gen_reg_rtx (Pmode
);
1236 emit_insn (gen_adddi3 (op0
, tmp
, gen_thread_pointer ()));
1239 case TLS_MODEL_LOCAL_EXEC
:
1240 if (!register_operand (op0
, Pmode
))
1241 op0
= gen_reg_rtx (Pmode
);
1247 emit_insn (gen_load_tprel (op0
, op1
));
1248 emit_insn (gen_adddi3 (op0
, op0
, gen_thread_pointer ()));
1251 emit_insn (gen_add_tprel (op0
, op1
, gen_thread_pointer ()));
1259 op0
= expand_simple_binop (Pmode
, PLUS
, op0
, GEN_INT (addend
),
1260 orig_op0
, 1, OPTAB_DIRECT
);
1261 if (orig_op0
== op0
)
1263 if (GET_MODE (orig_op0
) == Pmode
)
1265 return gen_lowpart (GET_MODE (orig_op0
), op0
);
1269 ia64_expand_move (rtx op0
, rtx op1
)
1271 enum machine_mode mode
= GET_MODE (op0
);
1273 if (!reload_in_progress
&& !reload_completed
&& !ia64_move_ok (op0
, op1
))
1274 op1
= force_reg (mode
, op1
);
1276 if ((mode
== Pmode
|| mode
== ptr_mode
) && symbolic_operand (op1
, VOIDmode
))
1278 HOST_WIDE_INT addend
= 0;
1279 enum tls_model tls_kind
;
1282 if (GET_CODE (op1
) == CONST
1283 && GET_CODE (XEXP (op1
, 0)) == PLUS
1284 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
)
1286 addend
= INTVAL (XEXP (XEXP (op1
, 0), 1));
1287 sym
= XEXP (XEXP (op1
, 0), 0);
1290 tls_kind
= tls_symbolic_operand_type (sym
);
1292 return ia64_expand_tls_address (tls_kind
, op0
, sym
, op1
, addend
);
1294 if (any_offset_symbol_operand (sym
, mode
))
1296 else if (aligned_offset_symbol_operand (sym
, mode
))
1298 HOST_WIDE_INT addend_lo
, addend_hi
;
1300 addend_lo
= ((addend
& 0x3fff) ^ 0x2000) - 0x2000;
1301 addend_hi
= addend
- addend_lo
;
1305 op1
= plus_constant (mode
, sym
, addend_hi
);
1314 if (reload_completed
)
1316 /* We really should have taken care of this offset earlier. */
1317 gcc_assert (addend
== 0);
1318 if (ia64_expand_load_address (op0
, op1
))
1324 rtx subtarget
= !can_create_pseudo_p () ? op0
: gen_reg_rtx (mode
);
1326 emit_insn (gen_rtx_SET (VOIDmode
, subtarget
, op1
));
1328 op1
= expand_simple_binop (mode
, PLUS
, subtarget
,
1329 GEN_INT (addend
), op0
, 1, OPTAB_DIRECT
);
1338 /* Split a move from OP1 to OP0 conditional on COND. */
1341 ia64_emit_cond_move (rtx op0
, rtx op1
, rtx cond
)
1343 rtx insn
, first
= get_last_insn ();
1345 emit_move_insn (op0
, op1
);
1347 for (insn
= get_last_insn (); insn
!= first
; insn
= PREV_INSN (insn
))
1349 PATTERN (insn
) = gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
),
1353 /* Split a post-reload TImode or TFmode reference into two DImode
1354 components. This is made extra difficult by the fact that we do
1355 not get any scratch registers to work with, because reload cannot
1356 be prevented from giving us a scratch that overlaps the register
1357 pair involved. So instead, when addressing memory, we tweak the
1358 pointer register up and back down with POST_INCs. Or up and not
1359 back down when we can get away with it.
1361 REVERSED is true when the loads must be done in reversed order
1362 (high word first) for correctness. DEAD is true when the pointer
1363 dies with the second insn we generate and therefore the second
1364 address must not carry a postmodify.
1366 May return an insn which is to be emitted after the moves. */
1369 ia64_split_tmode (rtx out
[2], rtx in
, bool reversed
, bool dead
)
1373 switch (GET_CODE (in
))
1376 out
[reversed
] = gen_rtx_REG (DImode
, REGNO (in
));
1377 out
[!reversed
] = gen_rtx_REG (DImode
, REGNO (in
) + 1);
1382 /* Cannot occur reversed. */
1383 gcc_assert (!reversed
);
1385 if (GET_MODE (in
) != TFmode
)
1386 split_double (in
, &out
[0], &out
[1]);
1388 /* split_double does not understand how to split a TFmode
1389 quantity into a pair of DImode constants. */
1392 unsigned HOST_WIDE_INT p
[2];
1393 long l
[4]; /* TFmode is 128 bits */
1395 REAL_VALUE_FROM_CONST_DOUBLE (r
, in
);
1396 real_to_target (l
, &r
, TFmode
);
1398 if (FLOAT_WORDS_BIG_ENDIAN
)
1400 p
[0] = (((unsigned HOST_WIDE_INT
) l
[0]) << 32) + l
[1];
1401 p
[1] = (((unsigned HOST_WIDE_INT
) l
[2]) << 32) + l
[3];
1405 p
[0] = (((unsigned HOST_WIDE_INT
) l
[1]) << 32) + l
[0];
1406 p
[1] = (((unsigned HOST_WIDE_INT
) l
[3]) << 32) + l
[2];
1408 out
[0] = GEN_INT (p
[0]);
1409 out
[1] = GEN_INT (p
[1]);
1415 rtx base
= XEXP (in
, 0);
1418 switch (GET_CODE (base
))
1423 out
[0] = adjust_automodify_address
1424 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1425 out
[1] = adjust_automodify_address
1426 (in
, DImode
, dead
? 0 : gen_rtx_POST_DEC (Pmode
, base
), 8);
1430 /* Reversal requires a pre-increment, which can only
1431 be done as a separate insn. */
1432 emit_insn (gen_adddi3 (base
, base
, GEN_INT (8)));
1433 out
[0] = adjust_automodify_address
1434 (in
, DImode
, gen_rtx_POST_DEC (Pmode
, base
), 8);
1435 out
[1] = adjust_address (in
, DImode
, 0);
1440 gcc_assert (!reversed
&& !dead
);
1442 /* Just do the increment in two steps. */
1443 out
[0] = adjust_automodify_address (in
, DImode
, 0, 0);
1444 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1448 gcc_assert (!reversed
&& !dead
);
1450 /* Add 8, subtract 24. */
1451 base
= XEXP (base
, 0);
1452 out
[0] = adjust_automodify_address
1453 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1454 out
[1] = adjust_automodify_address
1456 gen_rtx_POST_MODIFY (Pmode
, base
,
1457 plus_constant (Pmode
, base
, -24)),
1462 gcc_assert (!reversed
&& !dead
);
1464 /* Extract and adjust the modification. This case is
1465 trickier than the others, because we might have an
1466 index register, or we might have a combined offset that
1467 doesn't fit a signed 9-bit displacement field. We can
1468 assume the incoming expression is already legitimate. */
1469 offset
= XEXP (base
, 1);
1470 base
= XEXP (base
, 0);
1472 out
[0] = adjust_automodify_address
1473 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1475 if (GET_CODE (XEXP (offset
, 1)) == REG
)
1477 /* Can't adjust the postmodify to match. Emit the
1478 original, then a separate addition insn. */
1479 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1480 fixup
= gen_adddi3 (base
, base
, GEN_INT (-8));
1484 gcc_assert (GET_CODE (XEXP (offset
, 1)) == CONST_INT
);
1485 if (INTVAL (XEXP (offset
, 1)) < -256 + 8)
1487 /* Again the postmodify cannot be made to match,
1488 but in this case it's more efficient to get rid
1489 of the postmodify entirely and fix up with an
1491 out
[1] = adjust_automodify_address (in
, DImode
, base
, 8);
1493 (base
, base
, GEN_INT (INTVAL (XEXP (offset
, 1)) - 8));
1497 /* Combined offset still fits in the displacement field.
1498 (We cannot overflow it at the high end.) */
1499 out
[1] = adjust_automodify_address
1500 (in
, DImode
, gen_rtx_POST_MODIFY
1501 (Pmode
, base
, gen_rtx_PLUS
1503 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8))),
1522 /* Split a TImode or TFmode move instruction after reload.
1523 This is used by *movtf_internal and *movti_internal. */
1525 ia64_split_tmode_move (rtx operands
[])
1527 rtx in
[2], out
[2], insn
;
1530 bool reversed
= false;
1532 /* It is possible for reload to decide to overwrite a pointer with
1533 the value it points to. In that case we have to do the loads in
1534 the appropriate order so that the pointer is not destroyed too
1535 early. Also we must not generate a postmodify for that second
1536 load, or rws_access_regno will die. And we must not generate a
1537 postmodify for the second load if the destination register
1538 overlaps with the base register. */
1539 if (GET_CODE (operands
[1]) == MEM
1540 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
1542 rtx base
= XEXP (operands
[1], 0);
1543 while (GET_CODE (base
) != REG
)
1544 base
= XEXP (base
, 0);
1546 if (REGNO (base
) == REGNO (operands
[0]))
1549 if (refers_to_regno_p (REGNO (operands
[0]),
1550 REGNO (operands
[0])+2,
1554 /* Another reason to do the moves in reversed order is if the first
1555 element of the target register pair is also the second element of
1556 the source register pair. */
1557 if (GET_CODE (operands
[0]) == REG
&& GET_CODE (operands
[1]) == REG
1558 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1561 fixup
[0] = ia64_split_tmode (in
, operands
[1], reversed
, dead
);
1562 fixup
[1] = ia64_split_tmode (out
, operands
[0], reversed
, dead
);
1564 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1565 if (GET_CODE (EXP) == MEM \
1566 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1567 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1568 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1569 add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
1571 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[0], in
[0]));
1572 MAYBE_ADD_REG_INC_NOTE (insn
, in
[0]);
1573 MAYBE_ADD_REG_INC_NOTE (insn
, out
[0]);
1575 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[1], in
[1]));
1576 MAYBE_ADD_REG_INC_NOTE (insn
, in
[1]);
1577 MAYBE_ADD_REG_INC_NOTE (insn
, out
[1]);
1580 emit_insn (fixup
[0]);
1582 emit_insn (fixup
[1]);
1584 #undef MAYBE_ADD_REG_INC_NOTE
1587 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1588 through memory plus an extra GR scratch register. Except that you can
1589 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1590 SECONDARY_RELOAD_CLASS, but not both.
1592 We got into problems in the first place by allowing a construct like
1593 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1594 This solution attempts to prevent this situation from occurring. When
1595 we see something like the above, we spill the inner register to memory. */
1598 spill_xfmode_rfmode_operand (rtx in
, int force
, enum machine_mode mode
)
1600 if (GET_CODE (in
) == SUBREG
1601 && GET_MODE (SUBREG_REG (in
)) == TImode
1602 && GET_CODE (SUBREG_REG (in
)) == REG
)
1604 rtx memt
= assign_stack_temp (TImode
, 16);
1605 emit_move_insn (memt
, SUBREG_REG (in
));
1606 return adjust_address (memt
, mode
, 0);
1608 else if (force
&& GET_CODE (in
) == REG
)
1610 rtx memx
= assign_stack_temp (mode
, 16);
1611 emit_move_insn (memx
, in
);
1618 /* Expand the movxf or movrf pattern (MODE says which) with the given
1619 OPERANDS, returning true if the pattern should then invoke
1623 ia64_expand_movxf_movrf (enum machine_mode mode
, rtx operands
[])
1625 rtx op0
= operands
[0];
1627 if (GET_CODE (op0
) == SUBREG
)
1628 op0
= SUBREG_REG (op0
);
1630 /* We must support XFmode loads into general registers for stdarg/vararg,
1631 unprototyped calls, and a rare case where a long double is passed as
1632 an argument after a float HFA fills the FP registers. We split them into
1633 DImode loads for convenience. We also need to support XFmode stores
1634 for the last case. This case does not happen for stdarg/vararg routines,
1635 because we do a block store to memory of unnamed arguments. */
1637 if (GET_CODE (op0
) == REG
&& GR_REGNO_P (REGNO (op0
)))
1641 /* We're hoping to transform everything that deals with XFmode
1642 quantities and GR registers early in the compiler. */
1643 gcc_assert (can_create_pseudo_p ());
1645 /* Struct to register can just use TImode instead. */
1646 if ((GET_CODE (operands
[1]) == SUBREG
1647 && GET_MODE (SUBREG_REG (operands
[1])) == TImode
)
1648 || (GET_CODE (operands
[1]) == REG
1649 && GR_REGNO_P (REGNO (operands
[1]))))
1651 rtx op1
= operands
[1];
1653 if (GET_CODE (op1
) == SUBREG
)
1654 op1
= SUBREG_REG (op1
);
1656 op1
= gen_rtx_REG (TImode
, REGNO (op1
));
1658 emit_move_insn (gen_rtx_REG (TImode
, REGNO (op0
)), op1
);
1662 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1664 /* Don't word-swap when reading in the constant. */
1665 emit_move_insn (gen_rtx_REG (DImode
, REGNO (op0
)),
1666 operand_subword (operands
[1], WORDS_BIG_ENDIAN
,
1668 emit_move_insn (gen_rtx_REG (DImode
, REGNO (op0
) + 1),
1669 operand_subword (operands
[1], !WORDS_BIG_ENDIAN
,
1674 /* If the quantity is in a register not known to be GR, spill it. */
1675 if (register_operand (operands
[1], mode
))
1676 operands
[1] = spill_xfmode_rfmode_operand (operands
[1], 1, mode
);
1678 gcc_assert (GET_CODE (operands
[1]) == MEM
);
1680 /* Don't word-swap when reading in the value. */
1681 out
[0] = gen_rtx_REG (DImode
, REGNO (op0
));
1682 out
[1] = gen_rtx_REG (DImode
, REGNO (op0
) + 1);
1684 emit_move_insn (out
[0], adjust_address (operands
[1], DImode
, 0));
1685 emit_move_insn (out
[1], adjust_address (operands
[1], DImode
, 8));
1689 if (GET_CODE (operands
[1]) == REG
&& GR_REGNO_P (REGNO (operands
[1])))
1691 /* We're hoping to transform everything that deals with XFmode
1692 quantities and GR registers early in the compiler. */
1693 gcc_assert (can_create_pseudo_p ());
1695 /* Op0 can't be a GR_REG here, as that case is handled above.
1696 If op0 is a register, then we spill op1, so that we now have a
1697 MEM operand. This requires creating an XFmode subreg of a TImode reg
1698 to force the spill. */
1699 if (register_operand (operands
[0], mode
))
1701 rtx op1
= gen_rtx_REG (TImode
, REGNO (operands
[1]));
1702 op1
= gen_rtx_SUBREG (mode
, op1
, 0);
1703 operands
[1] = spill_xfmode_rfmode_operand (op1
, 0, mode
);
1710 gcc_assert (GET_CODE (operands
[0]) == MEM
);
1712 /* Don't word-swap when writing out the value. */
1713 in
[0] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
1714 in
[1] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
1716 emit_move_insn (adjust_address (operands
[0], DImode
, 0), in
[0]);
1717 emit_move_insn (adjust_address (operands
[0], DImode
, 8), in
[1]);
1722 if (!reload_in_progress
&& !reload_completed
)
1724 operands
[1] = spill_xfmode_rfmode_operand (operands
[1], 0, mode
);
1726 if (GET_MODE (op0
) == TImode
&& GET_CODE (op0
) == REG
)
1728 rtx memt
, memx
, in
= operands
[1];
1729 if (CONSTANT_P (in
))
1730 in
= validize_mem (force_const_mem (mode
, in
));
1731 if (GET_CODE (in
) == MEM
)
1732 memt
= adjust_address (in
, TImode
, 0);
1735 memt
= assign_stack_temp (TImode
, 16);
1736 memx
= adjust_address (memt
, mode
, 0);
1737 emit_move_insn (memx
, in
);
1739 emit_move_insn (op0
, memt
);
1743 if (!ia64_move_ok (operands
[0], operands
[1]))
1744 operands
[1] = force_reg (mode
, operands
[1]);
1750 /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
1751 with the expression that holds the compare result (in VOIDmode). */
1753 static GTY(()) rtx cmptf_libfunc
;
1756 ia64_expand_compare (rtx
*expr
, rtx
*op0
, rtx
*op1
)
1758 enum rtx_code code
= GET_CODE (*expr
);
1761 /* If we have a BImode input, then we already have a compare result, and
1762 do not need to emit another comparison. */
1763 if (GET_MODE (*op0
) == BImode
)
1765 gcc_assert ((code
== NE
|| code
== EQ
) && *op1
== const0_rtx
);
1768 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1769 magic number as its third argument, that indicates what to do.
1770 The return value is an integer to be compared against zero. */
1771 else if (TARGET_HPUX
&& GET_MODE (*op0
) == TFmode
)
1774 QCMP_INV
= 1, /* Raise FP_INVALID on NaNs as a side effect. */
1781 enum rtx_code ncode
;
1784 gcc_assert (cmptf_libfunc
&& GET_MODE (*op1
) == TFmode
);
1787 /* 1 = equal, 0 = not equal. Equality operators do
1788 not raise FP_INVALID when given a NaN operand. */
1789 case EQ
: magic
= QCMP_EQ
; ncode
= NE
; break;
1790 case NE
: magic
= QCMP_EQ
; ncode
= EQ
; break;
1791 /* isunordered() from C99. */
1792 case UNORDERED
: magic
= QCMP_UNORD
; ncode
= NE
; break;
1793 case ORDERED
: magic
= QCMP_UNORD
; ncode
= EQ
; break;
1794 /* Relational operators raise FP_INVALID when given
1796 case LT
: magic
= QCMP_LT
|QCMP_INV
; ncode
= NE
; break;
1797 case LE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1798 case GT
: magic
= QCMP_GT
|QCMP_INV
; ncode
= NE
; break;
1799 case GE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1800 /* Unordered relational operators do not raise FP_INVALID
1801 when given a NaN operand. */
1802 case UNLT
: magic
= QCMP_LT
|QCMP_UNORD
; ncode
= NE
; break;
1803 case UNLE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_UNORD
; ncode
= NE
; break;
1804 case UNGT
: magic
= QCMP_GT
|QCMP_UNORD
; ncode
= NE
; break;
1805 case UNGE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_UNORD
; ncode
= NE
; break;
1806 /* Not supported. */
1809 default: gcc_unreachable ();
1814 ret
= emit_library_call_value (cmptf_libfunc
, 0, LCT_CONST
, DImode
, 3,
1815 *op0
, TFmode
, *op1
, TFmode
,
1816 GEN_INT (magic
), DImode
);
1817 cmp
= gen_reg_rtx (BImode
);
1818 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1819 gen_rtx_fmt_ee (ncode
, BImode
,
1822 insns
= get_insns ();
1825 emit_libcall_block (insns
, cmp
, cmp
,
1826 gen_rtx_fmt_ee (code
, BImode
, *op0
, *op1
));
1831 cmp
= gen_reg_rtx (BImode
);
1832 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1833 gen_rtx_fmt_ee (code
, BImode
, *op0
, *op1
)));
1837 *expr
= gen_rtx_fmt_ee (code
, VOIDmode
, cmp
, const0_rtx
);
1842 /* Generate an integral vector comparison. Return true if the condition has
1843 been reversed, and so the sense of the comparison should be inverted. */
1846 ia64_expand_vecint_compare (enum rtx_code code
, enum machine_mode mode
,
1847 rtx dest
, rtx op0
, rtx op1
)
1849 bool negate
= false;
1852 /* Canonicalize the comparison to EQ, GT, GTU. */
1863 code
= reverse_condition (code
);
1869 code
= reverse_condition (code
);
1875 code
= swap_condition (code
);
1876 x
= op0
, op0
= op1
, op1
= x
;
1883 /* Unsigned parallel compare is not supported by the hardware. Play some
1884 tricks to turn this into a signed comparison against 0. */
1893 /* Subtract (-(INT MAX) - 1) from both operands to make
1895 mask
= GEN_INT (0x80000000);
1896 mask
= gen_rtx_CONST_VECTOR (V2SImode
, gen_rtvec (2, mask
, mask
));
1897 mask
= force_reg (mode
, mask
);
1898 t1
= gen_reg_rtx (mode
);
1899 emit_insn (gen_subv2si3 (t1
, op0
, mask
));
1900 t2
= gen_reg_rtx (mode
);
1901 emit_insn (gen_subv2si3 (t2
, op1
, mask
));
1910 /* Perform a parallel unsigned saturating subtraction. */
1911 x
= gen_reg_rtx (mode
);
1912 emit_insn (gen_rtx_SET (VOIDmode
, x
,
1913 gen_rtx_US_MINUS (mode
, op0
, op1
)));
1917 op1
= CONST0_RTX (mode
);
1926 x
= gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
1927 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
1932 /* Emit an integral vector conditional move. */
1935 ia64_expand_vecint_cmov (rtx operands
[])
1937 enum machine_mode mode
= GET_MODE (operands
[0]);
1938 enum rtx_code code
= GET_CODE (operands
[3]);
1942 cmp
= gen_reg_rtx (mode
);
1943 negate
= ia64_expand_vecint_compare (code
, mode
, cmp
,
1944 operands
[4], operands
[5]);
1946 ot
= operands
[1+negate
];
1947 of
= operands
[2-negate
];
1949 if (ot
== CONST0_RTX (mode
))
1951 if (of
== CONST0_RTX (mode
))
1953 emit_move_insn (operands
[0], ot
);
1957 x
= gen_rtx_NOT (mode
, cmp
);
1958 x
= gen_rtx_AND (mode
, x
, of
);
1959 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1961 else if (of
== CONST0_RTX (mode
))
1963 x
= gen_rtx_AND (mode
, cmp
, ot
);
1964 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1970 t
= gen_reg_rtx (mode
);
1971 x
= gen_rtx_AND (mode
, cmp
, operands
[1+negate
]);
1972 emit_insn (gen_rtx_SET (VOIDmode
, t
, x
));
1974 f
= gen_reg_rtx (mode
);
1975 x
= gen_rtx_NOT (mode
, cmp
);
1976 x
= gen_rtx_AND (mode
, x
, operands
[2-negate
]);
1977 emit_insn (gen_rtx_SET (VOIDmode
, f
, x
));
1979 x
= gen_rtx_IOR (mode
, t
, f
);
1980 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1984 /* Emit an integral vector min or max operation. Return true if all done. */
1987 ia64_expand_vecint_minmax (enum rtx_code code
, enum machine_mode mode
,
1992 /* These four combinations are supported directly. */
1993 if (mode
== V8QImode
&& (code
== UMIN
|| code
== UMAX
))
1995 if (mode
== V4HImode
&& (code
== SMIN
|| code
== SMAX
))
1998 /* This combination can be implemented with only saturating subtraction. */
1999 if (mode
== V4HImode
&& code
== UMAX
)
2001 rtx x
, tmp
= gen_reg_rtx (mode
);
2003 x
= gen_rtx_US_MINUS (mode
, operands
[1], operands
[2]);
2004 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, x
));
2006 emit_insn (gen_addv4hi3 (operands
[0], tmp
, operands
[2]));
2010 /* Everything else implemented via vector comparisons. */
2011 xops
[0] = operands
[0];
2012 xops
[4] = xops
[1] = operands
[1];
2013 xops
[5] = xops
[2] = operands
[2];
2032 xops
[3] = gen_rtx_fmt_ee (code
, VOIDmode
, operands
[1], operands
[2]);
2034 ia64_expand_vecint_cmov (xops
);
2038 /* The vectors LO and HI each contain N halves of a double-wide vector.
2039 Reassemble either the first N/2 or the second N/2 elements. */
2042 ia64_unpack_assemble (rtx out
, rtx lo
, rtx hi
, bool highp
)
2044 enum machine_mode vmode
= GET_MODE (lo
);
2045 unsigned int i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
2046 struct expand_vec_perm_d d
;
2049 d
.target
= gen_lowpart (vmode
, out
);
2050 d
.op0
= (TARGET_BIG_ENDIAN
? hi
: lo
);
2051 d
.op1
= (TARGET_BIG_ENDIAN
? lo
: hi
);
2054 d
.one_operand_p
= false;
2055 d
.testing_p
= false;
2057 high
= (highp
? nelt
/ 2 : 0);
2058 for (i
= 0; i
< nelt
/ 2; ++i
)
2060 d
.perm
[i
* 2] = i
+ high
;
2061 d
.perm
[i
* 2 + 1] = i
+ high
+ nelt
;
2064 ok
= ia64_expand_vec_perm_const_1 (&d
);
2068 /* Return a vector of the sign-extension of VEC. */
2071 ia64_unpack_sign (rtx vec
, bool unsignedp
)
2073 enum machine_mode mode
= GET_MODE (vec
);
2074 rtx zero
= CONST0_RTX (mode
);
2080 rtx sign
= gen_reg_rtx (mode
);
2083 neg
= ia64_expand_vecint_compare (LT
, mode
, sign
, vec
, zero
);
2090 /* Emit an integral vector unpack operation. */
2093 ia64_expand_unpack (rtx operands
[3], bool unsignedp
, bool highp
)
2095 rtx sign
= ia64_unpack_sign (operands
[1], unsignedp
);
2096 ia64_unpack_assemble (operands
[0], operands
[1], sign
, highp
);
2099 /* Emit an integral vector widening sum operations. */
2102 ia64_expand_widen_sum (rtx operands
[3], bool unsignedp
)
2104 enum machine_mode wmode
;
2107 sign
= ia64_unpack_sign (operands
[1], unsignedp
);
2109 wmode
= GET_MODE (operands
[0]);
2110 l
= gen_reg_rtx (wmode
);
2111 h
= gen_reg_rtx (wmode
);
2113 ia64_unpack_assemble (l
, operands
[1], sign
, false);
2114 ia64_unpack_assemble (h
, operands
[1], sign
, true);
2116 t
= expand_binop (wmode
, add_optab
, l
, operands
[2], NULL
, 0, OPTAB_DIRECT
);
2117 t
= expand_binop (wmode
, add_optab
, h
, t
, operands
[0], 0, OPTAB_DIRECT
);
2118 if (t
!= operands
[0])
2119 emit_move_insn (operands
[0], t
);
2122 /* Emit the appropriate sequence for a call. */
2125 ia64_expand_call (rtx retval
, rtx addr
, rtx nextarg ATTRIBUTE_UNUSED
,
2130 addr
= XEXP (addr
, 0);
2131 addr
= convert_memory_address (DImode
, addr
);
2132 b0
= gen_rtx_REG (DImode
, R_BR (0));
2134 /* ??? Should do this for functions known to bind local too. */
2135 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
2138 insn
= gen_sibcall_nogp (addr
);
2140 insn
= gen_call_nogp (addr
, b0
);
2142 insn
= gen_call_value_nogp (retval
, addr
, b0
);
2143 insn
= emit_call_insn (insn
);
2148 insn
= gen_sibcall_gp (addr
);
2150 insn
= gen_call_gp (addr
, b0
);
2152 insn
= gen_call_value_gp (retval
, addr
, b0
);
2153 insn
= emit_call_insn (insn
);
2155 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2159 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), b0
);
2161 if (TARGET_ABI_OPEN_VMS
)
2162 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2163 gen_rtx_REG (DImode
, GR_REG (25)));
2167 reg_emitted (enum ia64_frame_regs r
)
2169 if (emitted_frame_related_regs
[r
] == 0)
2170 emitted_frame_related_regs
[r
] = current_frame_info
.r
[r
];
2172 gcc_assert (emitted_frame_related_regs
[r
] == current_frame_info
.r
[r
]);
2176 get_reg (enum ia64_frame_regs r
)
2179 return current_frame_info
.r
[r
];
2183 is_emitted (int regno
)
2187 for (r
= reg_fp
; r
< number_of_ia64_frame_regs
; r
++)
2188 if (emitted_frame_related_regs
[r
] == regno
)
2194 ia64_reload_gp (void)
2198 if (current_frame_info
.r
[reg_save_gp
])
2200 tmp
= gen_rtx_REG (DImode
, get_reg (reg_save_gp
));
2204 HOST_WIDE_INT offset
;
2207 offset
= (current_frame_info
.spill_cfa_off
2208 + current_frame_info
.spill_size
);
2209 if (frame_pointer_needed
)
2211 tmp
= hard_frame_pointer_rtx
;
2216 tmp
= stack_pointer_rtx
;
2217 offset
= current_frame_info
.total_size
- offset
;
2220 offset_r
= GEN_INT (offset
);
2221 if (satisfies_constraint_I (offset_r
))
2222 emit_insn (gen_adddi3 (pic_offset_table_rtx
, tmp
, offset_r
));
2225 emit_move_insn (pic_offset_table_rtx
, offset_r
);
2226 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
2227 pic_offset_table_rtx
, tmp
));
2230 tmp
= gen_rtx_MEM (DImode
, pic_offset_table_rtx
);
2233 emit_move_insn (pic_offset_table_rtx
, tmp
);
2237 ia64_split_call (rtx retval
, rtx addr
, rtx retaddr
, rtx scratch_r
,
2238 rtx scratch_b
, int noreturn_p
, int sibcall_p
)
2241 bool is_desc
= false;
2243 /* If we find we're calling through a register, then we're actually
2244 calling through a descriptor, so load up the values. */
2245 if (REG_P (addr
) && GR_REGNO_P (REGNO (addr
)))
2250 /* ??? We are currently constrained to *not* use peep2, because
2251 we can legitimately change the global lifetime of the GP
2252 (in the form of killing where previously live). This is
2253 because a call through a descriptor doesn't use the previous
2254 value of the GP, while a direct call does, and we do not
2255 commit to either form until the split here.
2257 That said, this means that we lack precise life info for
2258 whether ADDR is dead after this call. This is not terribly
2259 important, since we can fix things up essentially for free
2260 with the POST_DEC below, but it's nice to not use it when we
2261 can immediately tell it's not necessary. */
2262 addr_dead_p
= ((noreturn_p
|| sibcall_p
2263 || TEST_HARD_REG_BIT (regs_invalidated_by_call
,
2265 && !FUNCTION_ARG_REGNO_P (REGNO (addr
)));
2267 /* Load the code address into scratch_b. */
2268 tmp
= gen_rtx_POST_INC (Pmode
, addr
);
2269 tmp
= gen_rtx_MEM (Pmode
, tmp
);
2270 emit_move_insn (scratch_r
, tmp
);
2271 emit_move_insn (scratch_b
, scratch_r
);
2273 /* Load the GP address. If ADDR is not dead here, then we must
2274 revert the change made above via the POST_INCREMENT. */
2276 tmp
= gen_rtx_POST_DEC (Pmode
, addr
);
2279 tmp
= gen_rtx_MEM (Pmode
, tmp
);
2280 emit_move_insn (pic_offset_table_rtx
, tmp
);
2287 insn
= gen_sibcall_nogp (addr
);
2289 insn
= gen_call_value_nogp (retval
, addr
, retaddr
);
2291 insn
= gen_call_nogp (addr
, retaddr
);
2292 emit_call_insn (insn
);
2294 if ((!TARGET_CONST_GP
|| is_desc
) && !noreturn_p
&& !sibcall_p
)
2298 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2300 This differs from the generic code in that we know about the zero-extending
2301 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2302 also know that ld.acq+cmpxchg.rel equals a full barrier.
2304 The loop we want to generate looks like
2309 new_reg = cmp_reg op val;
2310 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2311 if (cmp_reg != old_reg)
2314 Note that we only do the plain load from memory once. Subsequent
2315 iterations use the value loaded by the compare-and-swap pattern. */
2318 ia64_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
2319 rtx old_dst
, rtx new_dst
, enum memmodel model
)
2321 enum machine_mode mode
= GET_MODE (mem
);
2322 rtx old_reg
, new_reg
, cmp_reg
, ar_ccv
, label
;
2323 enum insn_code icode
;
2325 /* Special case for using fetchadd. */
2326 if ((mode
== SImode
|| mode
== DImode
)
2327 && (code
== PLUS
|| code
== MINUS
)
2328 && fetchadd_operand (val
, mode
))
2331 val
= GEN_INT (-INTVAL (val
));
2334 old_dst
= gen_reg_rtx (mode
);
2338 case MEMMODEL_ACQ_REL
:
2339 case MEMMODEL_SEQ_CST
:
2340 emit_insn (gen_memory_barrier ());
2342 case MEMMODEL_RELAXED
:
2343 case MEMMODEL_ACQUIRE
:
2344 case MEMMODEL_CONSUME
:
2346 icode
= CODE_FOR_fetchadd_acq_si
;
2348 icode
= CODE_FOR_fetchadd_acq_di
;
2350 case MEMMODEL_RELEASE
:
2352 icode
= CODE_FOR_fetchadd_rel_si
;
2354 icode
= CODE_FOR_fetchadd_rel_di
;
2361 emit_insn (GEN_FCN (icode
) (old_dst
, mem
, val
));
2365 new_reg
= expand_simple_binop (mode
, PLUS
, old_dst
, val
, new_dst
,
2367 if (new_reg
!= new_dst
)
2368 emit_move_insn (new_dst
, new_reg
);
2373 /* Because of the volatile mem read, we get an ld.acq, which is the
2374 front half of the full barrier. The end half is the cmpxchg.rel.
2375 For relaxed and release memory models, we don't need this. But we
2376 also don't bother trying to prevent it either. */
2377 gcc_assert (model
== MEMMODEL_RELAXED
2378 || model
== MEMMODEL_RELEASE
2379 || MEM_VOLATILE_P (mem
));
2381 old_reg
= gen_reg_rtx (DImode
);
2382 cmp_reg
= gen_reg_rtx (DImode
);
2383 label
= gen_label_rtx ();
2387 val
= simplify_gen_subreg (DImode
, val
, mode
, 0);
2388 emit_insn (gen_extend_insn (cmp_reg
, mem
, DImode
, mode
, 1));
2391 emit_move_insn (cmp_reg
, mem
);
2395 ar_ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
2396 emit_move_insn (old_reg
, cmp_reg
);
2397 emit_move_insn (ar_ccv
, cmp_reg
);
2400 emit_move_insn (old_dst
, gen_lowpart (mode
, cmp_reg
));
2405 new_reg
= expand_simple_binop (DImode
, AND
, new_reg
, val
, NULL_RTX
,
2406 true, OPTAB_DIRECT
);
2407 new_reg
= expand_simple_unop (DImode
, code
, new_reg
, NULL_RTX
, true);
2410 new_reg
= expand_simple_binop (DImode
, code
, new_reg
, val
, NULL_RTX
,
2411 true, OPTAB_DIRECT
);
2414 new_reg
= gen_lowpart (mode
, new_reg
);
2416 emit_move_insn (new_dst
, new_reg
);
2420 case MEMMODEL_RELAXED
:
2421 case MEMMODEL_ACQUIRE
:
2422 case MEMMODEL_CONSUME
:
2425 case QImode
: icode
= CODE_FOR_cmpxchg_acq_qi
; break;
2426 case HImode
: icode
= CODE_FOR_cmpxchg_acq_hi
; break;
2427 case SImode
: icode
= CODE_FOR_cmpxchg_acq_si
; break;
2428 case DImode
: icode
= CODE_FOR_cmpxchg_acq_di
; break;
2434 case MEMMODEL_RELEASE
:
2435 case MEMMODEL_ACQ_REL
:
2436 case MEMMODEL_SEQ_CST
:
2439 case QImode
: icode
= CODE_FOR_cmpxchg_rel_qi
; break;
2440 case HImode
: icode
= CODE_FOR_cmpxchg_rel_hi
; break;
2441 case SImode
: icode
= CODE_FOR_cmpxchg_rel_si
; break;
2442 case DImode
: icode
= CODE_FOR_cmpxchg_rel_di
; break;
2452 emit_insn (GEN_FCN (icode
) (cmp_reg
, mem
, ar_ccv
, new_reg
));
2454 emit_cmp_and_jump_insns (cmp_reg
, old_reg
, NE
, NULL
, DImode
, true, label
);
2457 /* Begin the assembly file. */
2460 ia64_file_start (void)
2462 default_file_start ();
2463 emit_safe_across_calls ();
2467 emit_safe_across_calls (void)
2469 unsigned int rs
, re
;
2476 while (rs
< 64 && call_used_regs
[PR_REG (rs
)])
2480 for (re
= rs
+ 1; re
< 64 && ! call_used_regs
[PR_REG (re
)]; re
++)
2484 fputs ("\t.pred.safe_across_calls ", asm_out_file
);
2488 fputc (',', asm_out_file
);
2490 fprintf (asm_out_file
, "p%u", rs
);
2492 fprintf (asm_out_file
, "p%u-p%u", rs
, re
- 1);
2496 fputc ('\n', asm_out_file
);
2499 /* Globalize a declaration. */
2502 ia64_globalize_decl_name (FILE * stream
, tree decl
)
2504 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2505 tree version_attr
= lookup_attribute ("version_id", DECL_ATTRIBUTES (decl
));
2508 tree v
= TREE_VALUE (TREE_VALUE (version_attr
));
2509 const char *p
= TREE_STRING_POINTER (v
);
2510 fprintf (stream
, "\t.alias %s#, \"%s{%s}\"\n", name
, name
, p
);
2512 targetm
.asm_out
.globalize_label (stream
, name
);
2513 if (TREE_CODE (decl
) == FUNCTION_DECL
)
2514 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "function");
2517 /* Helper function for ia64_compute_frame_size: find an appropriate general
2518 register to spill some special register to. SPECIAL_SPILL_MASK contains
2519 bits in GR0 to GR31 that have already been allocated by this routine.
2520 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2523 find_gr_spill (enum ia64_frame_regs r
, int try_locals
)
2527 if (emitted_frame_related_regs
[r
] != 0)
2529 regno
= emitted_frame_related_regs
[r
];
2530 if (regno
>= LOC_REG (0) && regno
< LOC_REG (80 - frame_pointer_needed
)
2531 && current_frame_info
.n_local_regs
< regno
- LOC_REG (0) + 1)
2532 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2533 else if (crtl
->is_leaf
2534 && regno
>= GR_REG (1) && regno
<= GR_REG (31))
2535 current_frame_info
.gr_used_mask
|= 1 << regno
;
2540 /* If this is a leaf function, first try an otherwise unused
2541 call-clobbered register. */
2544 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2545 if (! df_regs_ever_live_p (regno
)
2546 && call_used_regs
[regno
]
2547 && ! fixed_regs
[regno
]
2548 && ! global_regs
[regno
]
2549 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0
2550 && ! is_emitted (regno
))
2552 current_frame_info
.gr_used_mask
|= 1 << regno
;
2559 regno
= current_frame_info
.n_local_regs
;
2560 /* If there is a frame pointer, then we can't use loc79, because
2561 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2562 reg_name switching code in ia64_expand_prologue. */
2563 while (regno
< (80 - frame_pointer_needed
))
2564 if (! is_emitted (LOC_REG (regno
++)))
2566 current_frame_info
.n_local_regs
= regno
;
2567 return LOC_REG (regno
- 1);
2571 /* Failed to find a general register to spill to. Must use stack. */
2575 /* In order to make for nice schedules, we try to allocate every temporary
2576 to a different register. We must of course stay away from call-saved,
2577 fixed, and global registers. We must also stay away from registers
2578 allocated in current_frame_info.gr_used_mask, since those include regs
2579 used all through the prologue.
2581 Any register allocated here must be used immediately. The idea is to
2582 aid scheduling, not to solve data flow problems. */
2584 static int last_scratch_gr_reg
;
2587 next_scratch_gr_reg (void)
2591 for (i
= 0; i
< 32; ++i
)
2593 regno
= (last_scratch_gr_reg
+ i
+ 1) & 31;
2594 if (call_used_regs
[regno
]
2595 && ! fixed_regs
[regno
]
2596 && ! global_regs
[regno
]
2597 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
2599 last_scratch_gr_reg
= regno
;
2604 /* There must be _something_ available. */
2608 /* Helper function for ia64_compute_frame_size, called through
2609 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2612 mark_reg_gr_used_mask (rtx reg
, void *data ATTRIBUTE_UNUSED
)
2614 unsigned int regno
= REGNO (reg
);
2617 unsigned int i
, n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2618 for (i
= 0; i
< n
; ++i
)
2619 current_frame_info
.gr_used_mask
|= 1 << (regno
+ i
);
2624 /* Returns the number of bytes offset between the frame pointer and the stack
2625 pointer for the current function. SIZE is the number of bytes of space
2626 needed for local variables. */
2629 ia64_compute_frame_size (HOST_WIDE_INT size
)
2631 HOST_WIDE_INT total_size
;
2632 HOST_WIDE_INT spill_size
= 0;
2633 HOST_WIDE_INT extra_spill_size
= 0;
2634 HOST_WIDE_INT pretend_args_size
;
2637 int spilled_gr_p
= 0;
2638 int spilled_fr_p
= 0;
2644 if (current_frame_info
.initialized
)
2647 memset (¤t_frame_info
, 0, sizeof current_frame_info
);
2648 CLEAR_HARD_REG_SET (mask
);
2650 /* Don't allocate scratches to the return register. */
2651 diddle_return_value (mark_reg_gr_used_mask
, NULL
);
2653 /* Don't allocate scratches to the EH scratch registers. */
2654 if (cfun
->machine
->ia64_eh_epilogue_sp
)
2655 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_sp
, NULL
);
2656 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
2657 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_bsp
, NULL
);
2659 /* Static stack checking uses r2 and r3. */
2660 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
2661 current_frame_info
.gr_used_mask
|= 0xc;
2663 /* Find the size of the register stack frame. We have only 80 local
2664 registers, because we reserve 8 for the inputs and 8 for the
2667 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2668 since we'll be adjusting that down later. */
2669 regno
= LOC_REG (78) + ! frame_pointer_needed
;
2670 for (; regno
>= LOC_REG (0); regno
--)
2671 if (df_regs_ever_live_p (regno
) && !is_emitted (regno
))
2673 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2675 /* For functions marked with the syscall_linkage attribute, we must mark
2676 all eight input registers as in use, so that locals aren't visible to
2679 if (cfun
->machine
->n_varargs
> 0
2680 || lookup_attribute ("syscall_linkage",
2681 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
2682 current_frame_info
.n_input_regs
= 8;
2685 for (regno
= IN_REG (7); regno
>= IN_REG (0); regno
--)
2686 if (df_regs_ever_live_p (regno
))
2688 current_frame_info
.n_input_regs
= regno
- IN_REG (0) + 1;
2691 for (regno
= OUT_REG (7); regno
>= OUT_REG (0); regno
--)
2692 if (df_regs_ever_live_p (regno
))
2694 i
= regno
- OUT_REG (0) + 1;
2696 #ifndef PROFILE_HOOK
2697 /* When -p profiling, we need one output register for the mcount argument.
2698 Likewise for -a profiling for the bb_init_func argument. For -ax
2699 profiling, we need two output registers for the two bb_init_trace_func
2704 current_frame_info
.n_output_regs
= i
;
2706 /* ??? No rotating register support yet. */
2707 current_frame_info
.n_rotate_regs
= 0;
2709 /* Discover which registers need spilling, and how much room that
2710 will take. Begin with floating point and general registers,
2711 which will always wind up on the stack. */
2713 for (regno
= FR_REG (2); regno
<= FR_REG (127); regno
++)
2714 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2716 SET_HARD_REG_BIT (mask
, regno
);
2722 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2723 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2725 SET_HARD_REG_BIT (mask
, regno
);
2731 for (regno
= BR_REG (1); regno
<= BR_REG (7); regno
++)
2732 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2734 SET_HARD_REG_BIT (mask
, regno
);
2739 /* Now come all special registers that might get saved in other
2740 general registers. */
2742 if (frame_pointer_needed
)
2744 current_frame_info
.r
[reg_fp
] = find_gr_spill (reg_fp
, 1);
2745 /* If we did not get a register, then we take LOC79. This is guaranteed
2746 to be free, even if regs_ever_live is already set, because this is
2747 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2748 as we don't count loc79 above. */
2749 if (current_frame_info
.r
[reg_fp
] == 0)
2751 current_frame_info
.r
[reg_fp
] = LOC_REG (79);
2752 current_frame_info
.n_local_regs
= LOC_REG (79) - LOC_REG (0) + 1;
2756 if (! crtl
->is_leaf
)
2758 /* Emit a save of BR0 if we call other functions. Do this even
2759 if this function doesn't return, as EH depends on this to be
2760 able to unwind the stack. */
2761 SET_HARD_REG_BIT (mask
, BR_REG (0));
2763 current_frame_info
.r
[reg_save_b0
] = find_gr_spill (reg_save_b0
, 1);
2764 if (current_frame_info
.r
[reg_save_b0
] == 0)
2766 extra_spill_size
+= 8;
2770 /* Similarly for ar.pfs. */
2771 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2772 current_frame_info
.r
[reg_save_ar_pfs
] = find_gr_spill (reg_save_ar_pfs
, 1);
2773 if (current_frame_info
.r
[reg_save_ar_pfs
] == 0)
2775 extra_spill_size
+= 8;
2779 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2780 registers are clobbered, so we fall back to the stack. */
2781 current_frame_info
.r
[reg_save_gp
]
2782 = (cfun
->calls_setjmp
? 0 : find_gr_spill (reg_save_gp
, 1));
2783 if (current_frame_info
.r
[reg_save_gp
] == 0)
2785 SET_HARD_REG_BIT (mask
, GR_REG (1));
2792 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs
[BR_REG (0)])
2794 SET_HARD_REG_BIT (mask
, BR_REG (0));
2795 extra_spill_size
+= 8;
2799 if (df_regs_ever_live_p (AR_PFS_REGNUM
))
2801 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2802 current_frame_info
.r
[reg_save_ar_pfs
]
2803 = find_gr_spill (reg_save_ar_pfs
, 1);
2804 if (current_frame_info
.r
[reg_save_ar_pfs
] == 0)
2806 extra_spill_size
+= 8;
2812 /* Unwind descriptor hackery: things are most efficient if we allocate
2813 consecutive GR save registers for RP, PFS, FP in that order. However,
2814 it is absolutely critical that FP get the only hard register that's
2815 guaranteed to be free, so we allocated it first. If all three did
2816 happen to be allocated hard regs, and are consecutive, rearrange them
2817 into the preferred order now.
2819 If we have already emitted code for any of those registers,
2820 then it's already too late to change. */
2821 min_regno
= MIN (current_frame_info
.r
[reg_fp
],
2822 MIN (current_frame_info
.r
[reg_save_b0
],
2823 current_frame_info
.r
[reg_save_ar_pfs
]));
2824 max_regno
= MAX (current_frame_info
.r
[reg_fp
],
2825 MAX (current_frame_info
.r
[reg_save_b0
],
2826 current_frame_info
.r
[reg_save_ar_pfs
]));
2828 && min_regno
+ 2 == max_regno
2829 && (current_frame_info
.r
[reg_fp
] == min_regno
+ 1
2830 || current_frame_info
.r
[reg_save_b0
] == min_regno
+ 1
2831 || current_frame_info
.r
[reg_save_ar_pfs
] == min_regno
+ 1)
2832 && (emitted_frame_related_regs
[reg_save_b0
] == 0
2833 || emitted_frame_related_regs
[reg_save_b0
] == min_regno
)
2834 && (emitted_frame_related_regs
[reg_save_ar_pfs
] == 0
2835 || emitted_frame_related_regs
[reg_save_ar_pfs
] == min_regno
+ 1)
2836 && (emitted_frame_related_regs
[reg_fp
] == 0
2837 || emitted_frame_related_regs
[reg_fp
] == min_regno
+ 2))
2839 current_frame_info
.r
[reg_save_b0
] = min_regno
;
2840 current_frame_info
.r
[reg_save_ar_pfs
] = min_regno
+ 1;
2841 current_frame_info
.r
[reg_fp
] = min_regno
+ 2;
2844 /* See if we need to store the predicate register block. */
2845 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2846 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2848 if (regno
<= PR_REG (63))
2850 SET_HARD_REG_BIT (mask
, PR_REG (0));
2851 current_frame_info
.r
[reg_save_pr
] = find_gr_spill (reg_save_pr
, 1);
2852 if (current_frame_info
.r
[reg_save_pr
] == 0)
2854 extra_spill_size
+= 8;
2858 /* ??? Mark them all as used so that register renaming and such
2859 are free to use them. */
2860 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2861 df_set_regs_ever_live (regno
, true);
2864 /* If we're forced to use st8.spill, we're forced to save and restore
2865 ar.unat as well. The check for existing liveness allows inline asm
2866 to touch ar.unat. */
2867 if (spilled_gr_p
|| cfun
->machine
->n_varargs
2868 || df_regs_ever_live_p (AR_UNAT_REGNUM
))
2870 df_set_regs_ever_live (AR_UNAT_REGNUM
, true);
2871 SET_HARD_REG_BIT (mask
, AR_UNAT_REGNUM
);
2872 current_frame_info
.r
[reg_save_ar_unat
]
2873 = find_gr_spill (reg_save_ar_unat
, spill_size
== 0);
2874 if (current_frame_info
.r
[reg_save_ar_unat
] == 0)
2876 extra_spill_size
+= 8;
2881 if (df_regs_ever_live_p (AR_LC_REGNUM
))
2883 SET_HARD_REG_BIT (mask
, AR_LC_REGNUM
);
2884 current_frame_info
.r
[reg_save_ar_lc
]
2885 = find_gr_spill (reg_save_ar_lc
, spill_size
== 0);
2886 if (current_frame_info
.r
[reg_save_ar_lc
] == 0)
2888 extra_spill_size
+= 8;
2893 /* If we have an odd number of words of pretend arguments written to
2894 the stack, then the FR save area will be unaligned. We round the
2895 size of this area up to keep things 16 byte aligned. */
2897 pretend_args_size
= IA64_STACK_ALIGN (crtl
->args
.pretend_args_size
);
2899 pretend_args_size
= crtl
->args
.pretend_args_size
;
2901 total_size
= (spill_size
+ extra_spill_size
+ size
+ pretend_args_size
2902 + crtl
->outgoing_args_size
);
2903 total_size
= IA64_STACK_ALIGN (total_size
);
2905 /* We always use the 16-byte scratch area provided by the caller, but
2906 if we are a leaf function, there's no one to which we need to provide
2907 a scratch area. However, if the function allocates dynamic stack space,
2908 the dynamic offset is computed early and contains STACK_POINTER_OFFSET,
2909 so we need to cope. */
2910 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
2911 total_size
= MAX (0, total_size
- 16);
2913 current_frame_info
.total_size
= total_size
;
2914 current_frame_info
.spill_cfa_off
= pretend_args_size
- 16;
2915 current_frame_info
.spill_size
= spill_size
;
2916 current_frame_info
.extra_spill_size
= extra_spill_size
;
2917 COPY_HARD_REG_SET (current_frame_info
.mask
, mask
);
2918 current_frame_info
.n_spilled
= n_spilled
;
2919 current_frame_info
.initialized
= reload_completed
;
2922 /* Worker function for TARGET_CAN_ELIMINATE. */
2925 ia64_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
2927 return (to
== BR_REG (0) ? crtl
->is_leaf
: true);
2930 /* Compute the initial difference between the specified pair of registers. */
2933 ia64_initial_elimination_offset (int from
, int to
)
2935 HOST_WIDE_INT offset
;
2937 ia64_compute_frame_size (get_frame_size ());
2940 case FRAME_POINTER_REGNUM
:
2943 case HARD_FRAME_POINTER_REGNUM
:
2944 offset
= -current_frame_info
.total_size
;
2945 if (!crtl
->is_leaf
|| cfun
->calls_alloca
)
2946 offset
+= 16 + crtl
->outgoing_args_size
;
2949 case STACK_POINTER_REGNUM
:
2951 if (!crtl
->is_leaf
|| cfun
->calls_alloca
)
2952 offset
+= 16 + crtl
->outgoing_args_size
;
2960 case ARG_POINTER_REGNUM
:
2961 /* Arguments start above the 16 byte save area, unless stdarg
2962 in which case we store through the 16 byte save area. */
2965 case HARD_FRAME_POINTER_REGNUM
:
2966 offset
= 16 - crtl
->args
.pretend_args_size
;
2969 case STACK_POINTER_REGNUM
:
2970 offset
= (current_frame_info
.total_size
2971 + 16 - crtl
->args
.pretend_args_size
);
2986 /* If there are more than a trivial number of register spills, we use
2987 two interleaved iterators so that we can get two memory references
2990 In order to simplify things in the prologue and epilogue expanders,
2991 we use helper functions to fix up the memory references after the
2992 fact with the appropriate offsets to a POST_MODIFY memory mode.
2993 The following data structure tracks the state of the two iterators
2994 while insns are being emitted. */
2996 struct spill_fill_data
2998 rtx init_after
; /* point at which to emit initializations */
2999 rtx init_reg
[2]; /* initial base register */
3000 rtx iter_reg
[2]; /* the iterator registers */
3001 rtx
*prev_addr
[2]; /* address of last memory use */
3002 rtx prev_insn
[2]; /* the insn corresponding to prev_addr */
3003 HOST_WIDE_INT prev_off
[2]; /* last offset */
3004 int n_iter
; /* number of iterators in use */
3005 int next_iter
; /* next iterator to use */
3006 unsigned int save_gr_used_mask
;
3009 static struct spill_fill_data spill_fill_data
;
3012 setup_spill_pointers (int n_spills
, rtx init_reg
, HOST_WIDE_INT cfa_off
)
3016 spill_fill_data
.init_after
= get_last_insn ();
3017 spill_fill_data
.init_reg
[0] = init_reg
;
3018 spill_fill_data
.init_reg
[1] = init_reg
;
3019 spill_fill_data
.prev_addr
[0] = NULL
;
3020 spill_fill_data
.prev_addr
[1] = NULL
;
3021 spill_fill_data
.prev_insn
[0] = NULL
;
3022 spill_fill_data
.prev_insn
[1] = NULL
;
3023 spill_fill_data
.prev_off
[0] = cfa_off
;
3024 spill_fill_data
.prev_off
[1] = cfa_off
;
3025 spill_fill_data
.next_iter
= 0;
3026 spill_fill_data
.save_gr_used_mask
= current_frame_info
.gr_used_mask
;
3028 spill_fill_data
.n_iter
= 1 + (n_spills
> 2);
3029 for (i
= 0; i
< spill_fill_data
.n_iter
; ++i
)
3031 int regno
= next_scratch_gr_reg ();
3032 spill_fill_data
.iter_reg
[i
] = gen_rtx_REG (DImode
, regno
);
3033 current_frame_info
.gr_used_mask
|= 1 << regno
;
3038 finish_spill_pointers (void)
3040 current_frame_info
.gr_used_mask
= spill_fill_data
.save_gr_used_mask
;
3044 spill_restore_mem (rtx reg
, HOST_WIDE_INT cfa_off
)
3046 int iter
= spill_fill_data
.next_iter
;
3047 HOST_WIDE_INT disp
= spill_fill_data
.prev_off
[iter
] - cfa_off
;
3048 rtx disp_rtx
= GEN_INT (disp
);
3051 if (spill_fill_data
.prev_addr
[iter
])
3053 if (satisfies_constraint_N (disp_rtx
))
3055 *spill_fill_data
.prev_addr
[iter
]
3056 = gen_rtx_POST_MODIFY (DImode
, spill_fill_data
.iter_reg
[iter
],
3057 gen_rtx_PLUS (DImode
,
3058 spill_fill_data
.iter_reg
[iter
],
3060 add_reg_note (spill_fill_data
.prev_insn
[iter
],
3061 REG_INC
, spill_fill_data
.iter_reg
[iter
]);
3065 /* ??? Could use register post_modify for loads. */
3066 if (!satisfies_constraint_I (disp_rtx
))
3068 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
3069 emit_move_insn (tmp
, disp_rtx
);
3072 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
3073 spill_fill_data
.iter_reg
[iter
], disp_rtx
));
3076 /* Micro-optimization: if we've created a frame pointer, it's at
3077 CFA 0, which may allow the real iterator to be initialized lower,
3078 slightly increasing parallelism. Also, if there are few saves
3079 it may eliminate the iterator entirely. */
3081 && spill_fill_data
.init_reg
[iter
] == stack_pointer_rtx
3082 && frame_pointer_needed
)
3084 mem
= gen_rtx_MEM (GET_MODE (reg
), hard_frame_pointer_rtx
);
3085 set_mem_alias_set (mem
, get_varargs_alias_set ());
3093 seq
= gen_movdi (spill_fill_data
.iter_reg
[iter
],
3094 spill_fill_data
.init_reg
[iter
]);
3099 if (!satisfies_constraint_I (disp_rtx
))
3101 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
3102 emit_move_insn (tmp
, disp_rtx
);
3106 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
3107 spill_fill_data
.init_reg
[iter
],
3114 /* Careful for being the first insn in a sequence. */
3115 if (spill_fill_data
.init_after
)
3116 insn
= emit_insn_after (seq
, spill_fill_data
.init_after
);
3119 rtx first
= get_insns ();
3121 insn
= emit_insn_before (seq
, first
);
3123 insn
= emit_insn (seq
);
3125 spill_fill_data
.init_after
= insn
;
3128 mem
= gen_rtx_MEM (GET_MODE (reg
), spill_fill_data
.iter_reg
[iter
]);
3130 /* ??? Not all of the spills are for varargs, but some of them are.
3131 The rest of the spills belong in an alias set of their own. But
3132 it doesn't actually hurt to include them here. */
3133 set_mem_alias_set (mem
, get_varargs_alias_set ());
3135 spill_fill_data
.prev_addr
[iter
] = &XEXP (mem
, 0);
3136 spill_fill_data
.prev_off
[iter
] = cfa_off
;
3138 if (++iter
>= spill_fill_data
.n_iter
)
3140 spill_fill_data
.next_iter
= iter
;
3146 do_spill (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
,
3149 int iter
= spill_fill_data
.next_iter
;
3152 mem
= spill_restore_mem (reg
, cfa_off
);
3153 insn
= emit_insn ((*move_fn
) (mem
, reg
, GEN_INT (cfa_off
)));
3154 spill_fill_data
.prev_insn
[iter
] = insn
;
3161 RTX_FRAME_RELATED_P (insn
) = 1;
3163 /* Don't even pretend that the unwind code can intuit its way
3164 through a pair of interleaved post_modify iterators. Just
3165 provide the correct answer. */
3167 if (frame_pointer_needed
)
3169 base
= hard_frame_pointer_rtx
;
3174 base
= stack_pointer_rtx
;
3175 off
= current_frame_info
.total_size
- cfa_off
;
3178 add_reg_note (insn
, REG_CFA_OFFSET
,
3179 gen_rtx_SET (VOIDmode
,
3180 gen_rtx_MEM (GET_MODE (reg
),
3181 plus_constant (Pmode
,
3188 do_restore (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
)
3190 int iter
= spill_fill_data
.next_iter
;
3193 insn
= emit_insn ((*move_fn
) (reg
, spill_restore_mem (reg
, cfa_off
),
3194 GEN_INT (cfa_off
)));
3195 spill_fill_data
.prev_insn
[iter
] = insn
;
3198 /* Wrapper functions that discards the CONST_INT spill offset. These
3199 exist so that we can give gr_spill/gr_fill the offset they need and
3200 use a consistent function interface. */
3203 gen_movdi_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3205 return gen_movdi (dest
, src
);
3209 gen_fr_spill_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3211 return gen_fr_spill (dest
, src
);
3215 gen_fr_restore_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
3217 return gen_fr_restore (dest
, src
);
3220 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3222 /* See Table 6.2 of the IA-64 Software Developer Manual, Volume 2. */
3223 #define BACKING_STORE_SIZE(N) ((N) > 0 ? ((N) + (N)/63 + 1) * 8 : 0)
3225 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
3226 inclusive. These are offsets from the current stack pointer. BS_SIZE
3227 is the size of the backing store. ??? This clobbers r2 and r3. */
3230 ia64_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
,
3233 rtx r2
= gen_rtx_REG (Pmode
, GR_REG (2));
3234 rtx r3
= gen_rtx_REG (Pmode
, GR_REG (3));
3235 rtx p6
= gen_rtx_REG (BImode
, PR_REG (6));
3237 /* On the IA-64 there is a second stack in memory, namely the Backing Store
3238 of the Register Stack Engine. We also need to probe it after checking
3239 that the 2 stacks don't overlap. */
3240 emit_insn (gen_bsp_value (r3
));
3241 emit_move_insn (r2
, GEN_INT (-(first
+ size
)));
3243 /* Compare current value of BSP and SP registers. */
3244 emit_insn (gen_rtx_SET (VOIDmode
, p6
,
3245 gen_rtx_fmt_ee (LTU
, BImode
,
3246 r3
, stack_pointer_rtx
)));
3248 /* Compute the address of the probe for the Backing Store (which grows
3249 towards higher addresses). We probe only at the first offset of
3250 the next page because some OS (eg Linux/ia64) only extend the
3251 backing store when this specific address is hit (but generate a SEGV
3252 on other address). Page size is the worst case (4KB). The reserve
3253 size is at least 4096 - (96 + 2) * 8 = 3312 bytes, which is enough.
3254 Also compute the address of the last probe for the memory stack
3255 (which grows towards lower addresses). */
3256 emit_insn (gen_rtx_SET (VOIDmode
, r3
, plus_constant (Pmode
, r3
, 4095)));
3257 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3258 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r2
)));
3260 /* Compare them and raise SEGV if the former has topped the latter. */
3261 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
3262 gen_rtx_fmt_ee (NE
, VOIDmode
, p6
, const0_rtx
),
3263 gen_rtx_SET (VOIDmode
, p6
,
3264 gen_rtx_fmt_ee (GEU
, BImode
,
3266 emit_insn (gen_rtx_SET (VOIDmode
,
3267 gen_rtx_ZERO_EXTRACT (DImode
, r3
, GEN_INT (12),
3270 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
3271 gen_rtx_fmt_ee (NE
, VOIDmode
, p6
, const0_rtx
),
3272 gen_rtx_TRAP_IF (VOIDmode
, const1_rtx
,
3275 /* Probe the Backing Store if necessary. */
3277 emit_stack_probe (r3
);
3279 /* Probe the memory stack if necessary. */
3283 /* See if we have a constant small number of probes to generate. If so,
3284 that's the easy case. */
3285 else if (size
<= PROBE_INTERVAL
)
3286 emit_stack_probe (r2
);
3288 /* The run-time loop is made up of 8 insns in the generic case while this
3289 compile-time loop is made up of 5+2*(n-2) insns for n # of intervals. */
3290 else if (size
<= 4 * PROBE_INTERVAL
)
3294 emit_move_insn (r2
, GEN_INT (-(first
+ PROBE_INTERVAL
)));
3295 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3296 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r2
)));
3297 emit_stack_probe (r2
);
3299 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3300 it exceeds SIZE. If only two probes are needed, this will not
3301 generate any code. Then probe at FIRST + SIZE. */
3302 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
3304 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3305 plus_constant (Pmode
, r2
, -PROBE_INTERVAL
)));
3306 emit_stack_probe (r2
);
3309 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3310 plus_constant (Pmode
, r2
,
3311 (i
- PROBE_INTERVAL
) - size
)));
3312 emit_stack_probe (r2
);
3315 /* Otherwise, do the same as above, but in a loop. Note that we must be
3316 extra careful with variables wrapping around because we might be at
3317 the very top (or the very bottom) of the address space and we have
3318 to be able to handle this case properly; in particular, we use an
3319 equality test for the loop condition. */
3322 HOST_WIDE_INT rounded_size
;
3324 emit_move_insn (r2
, GEN_INT (-first
));
3327 /* Step 1: round SIZE to the previous multiple of the interval. */
3329 rounded_size
= size
& -PROBE_INTERVAL
;
3332 /* Step 2: compute initial and final value of the loop counter. */
3334 /* TEST_ADDR = SP + FIRST. */
3335 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3336 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r2
)));
3338 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3339 if (rounded_size
> (1 << 21))
3341 emit_move_insn (r3
, GEN_INT (-rounded_size
));
3342 emit_insn (gen_rtx_SET (VOIDmode
, r3
, gen_rtx_PLUS (Pmode
, r2
, r3
)));
3345 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
3346 gen_rtx_PLUS (Pmode
, r2
,
3347 GEN_INT (-rounded_size
))));
3352 while (TEST_ADDR != LAST_ADDR)
3354 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3358 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3359 until it is equal to ROUNDED_SIZE. */
3361 emit_insn (gen_probe_stack_range (r2
, r2
, r3
));
3364 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3365 that SIZE is equal to ROUNDED_SIZE. */
3367 /* TEMP = SIZE - ROUNDED_SIZE. */
3368 if (size
!= rounded_size
)
3370 emit_insn (gen_rtx_SET (VOIDmode
, r2
,
3371 plus_constant (Pmode
, r2
,
3372 rounded_size
- size
)));
3373 emit_stack_probe (r2
);
3377 /* Make sure nothing is scheduled before we are done. */
3378 emit_insn (gen_blockage ());
3381 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3382 absolute addresses. */
3385 output_probe_stack_range (rtx reg1
, rtx reg2
)
3387 static int labelno
= 0;
3388 char loop_lab
[32], end_lab
[32];
3391 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
3392 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
3394 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
3396 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
3399 xops
[2] = gen_rtx_REG (BImode
, PR_REG (6));
3400 output_asm_insn ("cmp.eq %2, %I2 = %0, %1", xops
);
3401 fprintf (asm_out_file
, "\t(%s) br.cond.dpnt ", reg_names
[REGNO (xops
[2])]);
3402 assemble_name_raw (asm_out_file
, end_lab
);
3403 fputc ('\n', asm_out_file
);
3405 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3406 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
3407 output_asm_insn ("addl %0 = %1, %0", xops
);
3408 fputs ("\t;;\n", asm_out_file
);
3410 /* Probe at TEST_ADDR and branch. */
3411 output_asm_insn ("probe.w.fault %0, 0", xops
);
3412 fprintf (asm_out_file
, "\tbr ");
3413 assemble_name_raw (asm_out_file
, loop_lab
);
3414 fputc ('\n', asm_out_file
);
3416 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
3421 /* Called after register allocation to add any instructions needed for the
3422 prologue. Using a prologue insn is favored compared to putting all of the
3423 instructions in output_function_prologue(), since it allows the scheduler
3424 to intermix instructions with the saves of the caller saved registers. In
3425 some cases, it might be necessary to emit a barrier instruction as the last
3426 insn to prevent such scheduling.
3428 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
3429 so that the debug info generation code can handle them properly.
3431 The register save area is laid out like so:
3433 [ varargs spill area ]
3434 [ fr register spill area ]
3435 [ br register spill area ]
3436 [ ar register spill area ]
3437 [ pr register spill area ]
3438 [ gr register spill area ] */
3440 /* ??? Get inefficient code when the frame size is larger than can fit in an
3441 adds instruction. */
3444 ia64_expand_prologue (void)
3446 rtx insn
, ar_pfs_save_reg
, ar_unat_save_reg
;
3447 int i
, epilogue_p
, regno
, alt_regno
, cfa_off
, n_varargs
;
3450 ia64_compute_frame_size (get_frame_size ());
3451 last_scratch_gr_reg
= 15;
3453 if (flag_stack_usage_info
)
3454 current_function_static_stack_size
= current_frame_info
.total_size
;
3456 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
3458 HOST_WIDE_INT size
= current_frame_info
.total_size
;
3459 int bs_size
= BACKING_STORE_SIZE (current_frame_info
.n_input_regs
3460 + current_frame_info
.n_local_regs
);
3462 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
3464 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
3465 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT
,
3466 size
- STACK_CHECK_PROTECT
,
3468 else if (size
+ bs_size
> STACK_CHECK_PROTECT
)
3469 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT
, 0, bs_size
);
3471 else if (size
+ bs_size
> 0)
3472 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
, bs_size
);
3477 fprintf (dump_file
, "ia64 frame related registers "
3478 "recorded in current_frame_info.r[]:\n");
3479 #define PRINTREG(a) if (current_frame_info.r[a]) \
3480 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
3482 PRINTREG(reg_save_b0
);
3483 PRINTREG(reg_save_pr
);
3484 PRINTREG(reg_save_ar_pfs
);
3485 PRINTREG(reg_save_ar_unat
);
3486 PRINTREG(reg_save_ar_lc
);
3487 PRINTREG(reg_save_gp
);
3491 /* If there is no epilogue, then we don't need some prologue insns.
3492 We need to avoid emitting the dead prologue insns, because flow
3493 will complain about them. */
3499 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
)
3500 if ((e
->flags
& EDGE_FAKE
) == 0
3501 && (e
->flags
& EDGE_FALLTHRU
) != 0)
3503 epilogue_p
= (e
!= NULL
);
3508 /* Set the local, input, and output register names. We need to do this
3509 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3510 half. If we use in/loc/out register names, then we get assembler errors
3511 in crtn.S because there is no alloc insn or regstk directive in there. */
3512 if (! TARGET_REG_NAMES
)
3514 int inputs
= current_frame_info
.n_input_regs
;
3515 int locals
= current_frame_info
.n_local_regs
;
3516 int outputs
= current_frame_info
.n_output_regs
;
3518 for (i
= 0; i
< inputs
; i
++)
3519 reg_names
[IN_REG (i
)] = ia64_reg_numbers
[i
];
3520 for (i
= 0; i
< locals
; i
++)
3521 reg_names
[LOC_REG (i
)] = ia64_reg_numbers
[inputs
+ i
];
3522 for (i
= 0; i
< outputs
; i
++)
3523 reg_names
[OUT_REG (i
)] = ia64_reg_numbers
[inputs
+ locals
+ i
];
3526 /* Set the frame pointer register name. The regnum is logically loc79,
3527 but of course we'll not have allocated that many locals. Rather than
3528 worrying about renumbering the existing rtxs, we adjust the name. */
3529 /* ??? This code means that we can never use one local register when
3530 there is a frame pointer. loc79 gets wasted in this case, as it is
3531 renamed to a register that will never be used. See also the try_locals
3532 code in find_gr_spill. */
3533 if (current_frame_info
.r
[reg_fp
])
3535 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3536 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3537 = reg_names
[current_frame_info
.r
[reg_fp
]];
3538 reg_names
[current_frame_info
.r
[reg_fp
]] = tmp
;
3541 /* We don't need an alloc instruction if we've used no outputs or locals. */
3542 if (current_frame_info
.n_local_regs
== 0
3543 && current_frame_info
.n_output_regs
== 0
3544 && current_frame_info
.n_input_regs
<= crtl
->args
.info
.int_regs
3545 && !TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3547 /* If there is no alloc, but there are input registers used, then we
3548 need a .regstk directive. */
3549 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
3550 ar_pfs_save_reg
= NULL_RTX
;
3554 current_frame_info
.need_regstk
= 0;
3556 if (current_frame_info
.r
[reg_save_ar_pfs
])
3558 regno
= current_frame_info
.r
[reg_save_ar_pfs
];
3559 reg_emitted (reg_save_ar_pfs
);
3562 regno
= next_scratch_gr_reg ();
3563 ar_pfs_save_reg
= gen_rtx_REG (DImode
, regno
);
3565 insn
= emit_insn (gen_alloc (ar_pfs_save_reg
,
3566 GEN_INT (current_frame_info
.n_input_regs
),
3567 GEN_INT (current_frame_info
.n_local_regs
),
3568 GEN_INT (current_frame_info
.n_output_regs
),
3569 GEN_INT (current_frame_info
.n_rotate_regs
)));
3570 if (current_frame_info
.r
[reg_save_ar_pfs
])
3572 RTX_FRAME_RELATED_P (insn
) = 1;
3573 add_reg_note (insn
, REG_CFA_REGISTER
,
3574 gen_rtx_SET (VOIDmode
,
3576 gen_rtx_REG (DImode
, AR_PFS_REGNUM
)));
3580 /* Set up frame pointer, stack pointer, and spill iterators. */
3582 n_varargs
= cfun
->machine
->n_varargs
;
3583 setup_spill_pointers (current_frame_info
.n_spilled
+ n_varargs
,
3584 stack_pointer_rtx
, 0);
3586 if (frame_pointer_needed
)
3588 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
3589 RTX_FRAME_RELATED_P (insn
) = 1;
3591 /* Force the unwind info to recognize this as defining a new CFA,
3592 rather than some temp register setup. */
3593 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, NULL_RTX
);
3596 if (current_frame_info
.total_size
!= 0)
3598 rtx frame_size_rtx
= GEN_INT (- current_frame_info
.total_size
);
3601 if (satisfies_constraint_I (frame_size_rtx
))
3602 offset
= frame_size_rtx
;
3605 regno
= next_scratch_gr_reg ();
3606 offset
= gen_rtx_REG (DImode
, regno
);
3607 emit_move_insn (offset
, frame_size_rtx
);
3610 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
,
3611 stack_pointer_rtx
, offset
));
3613 if (! frame_pointer_needed
)
3615 RTX_FRAME_RELATED_P (insn
) = 1;
3616 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
3617 gen_rtx_SET (VOIDmode
,
3619 gen_rtx_PLUS (DImode
,
3624 /* ??? At this point we must generate a magic insn that appears to
3625 modify the stack pointer, the frame pointer, and all spill
3626 iterators. This would allow the most scheduling freedom. For
3627 now, just hard stop. */
3628 emit_insn (gen_blockage ());
3631 /* Must copy out ar.unat before doing any integer spills. */
3632 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3634 if (current_frame_info
.r
[reg_save_ar_unat
])
3637 = gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_unat
]);
3638 reg_emitted (reg_save_ar_unat
);
3642 alt_regno
= next_scratch_gr_reg ();
3643 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3644 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3647 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3648 insn
= emit_move_insn (ar_unat_save_reg
, reg
);
3649 if (current_frame_info
.r
[reg_save_ar_unat
])
3651 RTX_FRAME_RELATED_P (insn
) = 1;
3652 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3655 /* Even if we're not going to generate an epilogue, we still
3656 need to save the register so that EH works. */
3657 if (! epilogue_p
&& current_frame_info
.r
[reg_save_ar_unat
])
3658 emit_insn (gen_prologue_use (ar_unat_save_reg
));
3661 ar_unat_save_reg
= NULL_RTX
;
3663 /* Spill all varargs registers. Do this before spilling any GR registers,
3664 since we want the UNAT bits for the GR registers to override the UNAT
3665 bits from varargs, which we don't care about. */
3668 for (regno
= GR_ARG_FIRST
+ 7; n_varargs
> 0; --n_varargs
, --regno
)
3670 reg
= gen_rtx_REG (DImode
, regno
);
3671 do_spill (gen_gr_spill
, reg
, cfa_off
+= 8, NULL_RTX
);
3674 /* Locate the bottom of the register save area. */
3675 cfa_off
= (current_frame_info
.spill_cfa_off
3676 + current_frame_info
.spill_size
3677 + current_frame_info
.extra_spill_size
);
3679 /* Save the predicate register block either in a register or in memory. */
3680 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
3682 reg
= gen_rtx_REG (DImode
, PR_REG (0));
3683 if (current_frame_info
.r
[reg_save_pr
] != 0)
3685 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_pr
]);
3686 reg_emitted (reg_save_pr
);
3687 insn
= emit_move_insn (alt_reg
, reg
);
3689 /* ??? Denote pr spill/fill by a DImode move that modifies all
3690 64 hard registers. */
3691 RTX_FRAME_RELATED_P (insn
) = 1;
3692 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3694 /* Even if we're not going to generate an epilogue, we still
3695 need to save the register so that EH works. */
3697 emit_insn (gen_prologue_use (alt_reg
));
3701 alt_regno
= next_scratch_gr_reg ();
3702 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3703 insn
= emit_move_insn (alt_reg
, reg
);
3704 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3709 /* Handle AR regs in numerical order. All of them get special handling. */
3710 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
)
3711 && current_frame_info
.r
[reg_save_ar_unat
] == 0)
3713 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3714 do_spill (gen_movdi_x
, ar_unat_save_reg
, cfa_off
, reg
);
3718 /* The alloc insn already copied ar.pfs into a general register. The
3719 only thing we have to do now is copy that register to a stack slot
3720 if we'd not allocated a local register for the job. */
3721 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
)
3722 && current_frame_info
.r
[reg_save_ar_pfs
] == 0)
3724 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3725 do_spill (gen_movdi_x
, ar_pfs_save_reg
, cfa_off
, reg
);
3729 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3731 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3732 if (current_frame_info
.r
[reg_save_ar_lc
] != 0)
3734 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_lc
]);
3735 reg_emitted (reg_save_ar_lc
);
3736 insn
= emit_move_insn (alt_reg
, reg
);
3737 RTX_FRAME_RELATED_P (insn
) = 1;
3738 add_reg_note (insn
, REG_CFA_REGISTER
, NULL_RTX
);
3740 /* Even if we're not going to generate an epilogue, we still
3741 need to save the register so that EH works. */
3743 emit_insn (gen_prologue_use (alt_reg
));
3747 alt_regno
= next_scratch_gr_reg ();
3748 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3749 emit_move_insn (alt_reg
, reg
);
3750 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3755 /* Save the return pointer. */
3756 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3758 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3759 if (current_frame_info
.r
[reg_save_b0
] != 0)
3761 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
3762 reg_emitted (reg_save_b0
);
3763 insn
= emit_move_insn (alt_reg
, reg
);
3764 RTX_FRAME_RELATED_P (insn
) = 1;
3765 add_reg_note (insn
, REG_CFA_REGISTER
,
3766 gen_rtx_SET (VOIDmode
, alt_reg
, pc_rtx
));
3768 /* Even if we're not going to generate an epilogue, we still
3769 need to save the register so that EH works. */
3771 emit_insn (gen_prologue_use (alt_reg
));
3775 alt_regno
= next_scratch_gr_reg ();
3776 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3777 emit_move_insn (alt_reg
, reg
);
3778 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3783 if (current_frame_info
.r
[reg_save_gp
])
3785 reg_emitted (reg_save_gp
);
3786 insn
= emit_move_insn (gen_rtx_REG (DImode
,
3787 current_frame_info
.r
[reg_save_gp
]),
3788 pic_offset_table_rtx
);
3791 /* We should now be at the base of the gr/br/fr spill area. */
3792 gcc_assert (cfa_off
== (current_frame_info
.spill_cfa_off
3793 + current_frame_info
.spill_size
));
3795 /* Spill all general registers. */
3796 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
3797 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3799 reg
= gen_rtx_REG (DImode
, regno
);
3800 do_spill (gen_gr_spill
, reg
, cfa_off
, reg
);
3804 /* Spill the rest of the BR registers. */
3805 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
3806 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3808 alt_regno
= next_scratch_gr_reg ();
3809 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3810 reg
= gen_rtx_REG (DImode
, regno
);
3811 emit_move_insn (alt_reg
, reg
);
3812 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
3816 /* Align the frame and spill all FR registers. */
3817 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
3818 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3820 gcc_assert (!(cfa_off
& 15));
3821 reg
= gen_rtx_REG (XFmode
, regno
);
3822 do_spill (gen_fr_spill_x
, reg
, cfa_off
, reg
);
3826 gcc_assert (cfa_off
== current_frame_info
.spill_cfa_off
);
3828 finish_spill_pointers ();
3831 /* Output the textual info surrounding the prologue. */
3834 ia64_start_function (FILE *file
, const char *fnname
,
3835 tree decl ATTRIBUTE_UNUSED
)
3837 #if TARGET_ABI_OPEN_VMS
3838 vms_start_function (fnname
);
3841 fputs ("\t.proc ", file
);
3842 assemble_name (file
, fnname
);
3844 ASM_OUTPUT_LABEL (file
, fnname
);
3847 /* Called after register allocation to add any instructions needed for the
3848 epilogue. Using an epilogue insn is favored compared to putting all of the
3849 instructions in output_function_prologue(), since it allows the scheduler
3850 to intermix instructions with the saves of the caller saved registers. In
3851 some cases, it might be necessary to emit a barrier instruction as the last
3852 insn to prevent such scheduling. */
3855 ia64_expand_epilogue (int sibcall_p
)
3857 rtx insn
, reg
, alt_reg
, ar_unat_save_reg
;
3858 int regno
, alt_regno
, cfa_off
;
3860 ia64_compute_frame_size (get_frame_size ());
3862 /* If there is a frame pointer, then we use it instead of the stack
3863 pointer, so that the stack pointer does not need to be valid when
3864 the epilogue starts. See EXIT_IGNORE_STACK. */
3865 if (frame_pointer_needed
)
3866 setup_spill_pointers (current_frame_info
.n_spilled
,
3867 hard_frame_pointer_rtx
, 0);
3869 setup_spill_pointers (current_frame_info
.n_spilled
, stack_pointer_rtx
,
3870 current_frame_info
.total_size
);
3872 if (current_frame_info
.total_size
!= 0)
3874 /* ??? At this point we must generate a magic insn that appears to
3875 modify the spill iterators and the frame pointer. This would
3876 allow the most scheduling freedom. For now, just hard stop. */
3877 emit_insn (gen_blockage ());
3880 /* Locate the bottom of the register save area. */
3881 cfa_off
= (current_frame_info
.spill_cfa_off
3882 + current_frame_info
.spill_size
3883 + current_frame_info
.extra_spill_size
);
3885 /* Restore the predicate registers. */
3886 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
3888 if (current_frame_info
.r
[reg_save_pr
] != 0)
3890 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_pr
]);
3891 reg_emitted (reg_save_pr
);
3895 alt_regno
= next_scratch_gr_reg ();
3896 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3897 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3900 reg
= gen_rtx_REG (DImode
, PR_REG (0));
3901 emit_move_insn (reg
, alt_reg
);
3904 /* Restore the application registers. */
3906 /* Load the saved unat from the stack, but do not restore it until
3907 after the GRs have been restored. */
3908 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3910 if (current_frame_info
.r
[reg_save_ar_unat
] != 0)
3913 = gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_unat
]);
3914 reg_emitted (reg_save_ar_unat
);
3918 alt_regno
= next_scratch_gr_reg ();
3919 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3920 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3921 do_restore (gen_movdi_x
, ar_unat_save_reg
, cfa_off
);
3926 ar_unat_save_reg
= NULL_RTX
;
3928 if (current_frame_info
.r
[reg_save_ar_pfs
] != 0)
3930 reg_emitted (reg_save_ar_pfs
);
3931 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_pfs
]);
3932 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3933 emit_move_insn (reg
, alt_reg
);
3935 else if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3937 alt_regno
= next_scratch_gr_reg ();
3938 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3939 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3941 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3942 emit_move_insn (reg
, alt_reg
);
3945 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3947 if (current_frame_info
.r
[reg_save_ar_lc
] != 0)
3949 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_ar_lc
]);
3950 reg_emitted (reg_save_ar_lc
);
3954 alt_regno
= next_scratch_gr_reg ();
3955 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3956 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3959 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3960 emit_move_insn (reg
, alt_reg
);
3963 /* Restore the return pointer. */
3964 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3966 if (current_frame_info
.r
[reg_save_b0
] != 0)
3968 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
3969 reg_emitted (reg_save_b0
);
3973 alt_regno
= next_scratch_gr_reg ();
3974 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3975 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3978 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3979 emit_move_insn (reg
, alt_reg
);
3982 /* We should now be at the base of the gr/br/fr spill area. */
3983 gcc_assert (cfa_off
== (current_frame_info
.spill_cfa_off
3984 + current_frame_info
.spill_size
));
3986 /* The GP may be stored on the stack in the prologue, but it's
3987 never restored in the epilogue. Skip the stack slot. */
3988 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, GR_REG (1)))
3991 /* Restore all general registers. */
3992 for (regno
= GR_REG (2); regno
<= GR_REG (31); ++regno
)
3993 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3995 reg
= gen_rtx_REG (DImode
, regno
);
3996 do_restore (gen_gr_restore
, reg
, cfa_off
);
4000 /* Restore the branch registers. */
4001 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
4002 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
4004 alt_regno
= next_scratch_gr_reg ();
4005 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
4006 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
4008 reg
= gen_rtx_REG (DImode
, regno
);
4009 emit_move_insn (reg
, alt_reg
);
4012 /* Restore floating point registers. */
4013 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
4014 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
4016 gcc_assert (!(cfa_off
& 15));
4017 reg
= gen_rtx_REG (XFmode
, regno
);
4018 do_restore (gen_fr_restore_x
, reg
, cfa_off
);
4022 /* Restore ar.unat for real. */
4023 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
4025 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
4026 emit_move_insn (reg
, ar_unat_save_reg
);
4029 gcc_assert (cfa_off
== current_frame_info
.spill_cfa_off
);
4031 finish_spill_pointers ();
4033 if (current_frame_info
.total_size
4034 || cfun
->machine
->ia64_eh_epilogue_sp
4035 || frame_pointer_needed
)
4037 /* ??? At this point we must generate a magic insn that appears to
4038 modify the spill iterators, the stack pointer, and the frame
4039 pointer. This would allow the most scheduling freedom. For now,
4041 emit_insn (gen_blockage ());
4044 if (cfun
->machine
->ia64_eh_epilogue_sp
)
4045 emit_move_insn (stack_pointer_rtx
, cfun
->machine
->ia64_eh_epilogue_sp
);
4046 else if (frame_pointer_needed
)
4048 insn
= emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
4049 RTX_FRAME_RELATED_P (insn
) = 1;
4050 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, NULL
);
4052 else if (current_frame_info
.total_size
)
4054 rtx offset
, frame_size_rtx
;
4056 frame_size_rtx
= GEN_INT (current_frame_info
.total_size
);
4057 if (satisfies_constraint_I (frame_size_rtx
))
4058 offset
= frame_size_rtx
;
4061 regno
= next_scratch_gr_reg ();
4062 offset
= gen_rtx_REG (DImode
, regno
);
4063 emit_move_insn (offset
, frame_size_rtx
);
4066 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
4069 RTX_FRAME_RELATED_P (insn
) = 1;
4070 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4071 gen_rtx_SET (VOIDmode
,
4073 gen_rtx_PLUS (DImode
,
4078 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
4079 emit_insn (gen_set_bsp (cfun
->machine
->ia64_eh_epilogue_bsp
));
4082 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode
, BR_REG (0))));
4085 int fp
= GR_REG (2);
4086 /* We need a throw away register here, r0 and r1 are reserved,
4087 so r2 is the first available call clobbered register. If
4088 there was a frame_pointer register, we may have swapped the
4089 names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make
4090 sure we're using the string "r2" when emitting the register
4091 name for the assembler. */
4092 if (current_frame_info
.r
[reg_fp
]
4093 && current_frame_info
.r
[reg_fp
] == GR_REG (2))
4094 fp
= HARD_FRAME_POINTER_REGNUM
;
4096 /* We must emit an alloc to force the input registers to become output
4097 registers. Otherwise, if the callee tries to pass its parameters
4098 through to another call without an intervening alloc, then these
4100 /* ??? We don't need to preserve all input registers. We only need to
4101 preserve those input registers used as arguments to the sibling call.
4102 It is unclear how to compute that number here. */
4103 if (current_frame_info
.n_input_regs
!= 0)
4105 rtx n_inputs
= GEN_INT (current_frame_info
.n_input_regs
);
4107 insn
= emit_insn (gen_alloc (gen_rtx_REG (DImode
, fp
),
4108 const0_rtx
, const0_rtx
,
4109 n_inputs
, const0_rtx
));
4110 RTX_FRAME_RELATED_P (insn
) = 1;
4112 /* ??? We need to mark the alloc as frame-related so that it gets
4113 passed into ia64_asm_unwind_emit for ia64-specific unwinding.
4114 But there's nothing dwarf2 related to be done wrt the register
4115 windows. If we do nothing, dwarf2out will abort on the UNSPEC;
4116 the empty parallel means dwarf2out will not see anything. */
4117 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4118 gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (0)));
4123 /* Return 1 if br.ret can do all the work required to return from a
4127 ia64_direct_return (void)
4129 if (reload_completed
&& ! frame_pointer_needed
)
4131 ia64_compute_frame_size (get_frame_size ());
4133 return (current_frame_info
.total_size
== 0
4134 && current_frame_info
.n_spilled
== 0
4135 && current_frame_info
.r
[reg_save_b0
] == 0
4136 && current_frame_info
.r
[reg_save_pr
] == 0
4137 && current_frame_info
.r
[reg_save_ar_pfs
] == 0
4138 && current_frame_info
.r
[reg_save_ar_unat
] == 0
4139 && current_frame_info
.r
[reg_save_ar_lc
] == 0);
4144 /* Return the magic cookie that we use to hold the return address
4145 during early compilation. */
4148 ia64_return_addr_rtx (HOST_WIDE_INT count
, rtx frame ATTRIBUTE_UNUSED
)
4152 return gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_RET_ADDR
);
4155 /* Split this value after reload, now that we know where the return
4156 address is saved. */
4159 ia64_split_return_addr_rtx (rtx dest
)
4163 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
4165 if (current_frame_info
.r
[reg_save_b0
] != 0)
4167 src
= gen_rtx_REG (DImode
, current_frame_info
.r
[reg_save_b0
]);
4168 reg_emitted (reg_save_b0
);
4176 /* Compute offset from CFA for BR0. */
4177 /* ??? Must be kept in sync with ia64_expand_prologue. */
4178 off
= (current_frame_info
.spill_cfa_off
4179 + current_frame_info
.spill_size
);
4180 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
4181 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
4184 /* Convert CFA offset to a register based offset. */
4185 if (frame_pointer_needed
)
4186 src
= hard_frame_pointer_rtx
;
4189 src
= stack_pointer_rtx
;
4190 off
+= current_frame_info
.total_size
;
4193 /* Load address into scratch register. */
4194 off_r
= GEN_INT (off
);
4195 if (satisfies_constraint_I (off_r
))
4196 emit_insn (gen_adddi3 (dest
, src
, off_r
));
4199 emit_move_insn (dest
, off_r
);
4200 emit_insn (gen_adddi3 (dest
, src
, dest
));
4203 src
= gen_rtx_MEM (Pmode
, dest
);
4207 src
= gen_rtx_REG (DImode
, BR_REG (0));
4209 emit_move_insn (dest
, src
);
4213 ia64_hard_regno_rename_ok (int from
, int to
)
4215 /* Don't clobber any of the registers we reserved for the prologue. */
4218 for (r
= reg_fp
; r
<= reg_save_ar_lc
; r
++)
4219 if (to
== current_frame_info
.r
[r
]
4220 || from
== current_frame_info
.r
[r
]
4221 || to
== emitted_frame_related_regs
[r
]
4222 || from
== emitted_frame_related_regs
[r
])
4225 /* Don't use output registers outside the register frame. */
4226 if (OUT_REGNO_P (to
) && to
>= OUT_REG (current_frame_info
.n_output_regs
))
4229 /* Retain even/oddness on predicate register pairs. */
4230 if (PR_REGNO_P (from
) && PR_REGNO_P (to
))
4231 return (from
& 1) == (to
& 1);
4236 /* Target hook for assembling integer objects. Handle word-sized
4237 aligned objects and detect the cases when @fptr is needed. */
4240 ia64_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
4242 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
4243 && !(TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
4244 && GET_CODE (x
) == SYMBOL_REF
4245 && SYMBOL_REF_FUNCTION_P (x
))
4247 static const char * const directive
[2][2] = {
4248 /* 64-bit pointer */ /* 32-bit pointer */
4249 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
4250 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
4252 fputs (directive
[(aligned_p
!= 0)][POINTER_SIZE
== 32], asm_out_file
);
4253 output_addr_const (asm_out_file
, x
);
4254 fputs (")\n", asm_out_file
);
4257 return default_assemble_integer (x
, size
, aligned_p
);
4260 /* Emit the function prologue. */
4263 ia64_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4265 int mask
, grsave
, grsave_prev
;
4267 if (current_frame_info
.need_regstk
)
4268 fprintf (file
, "\t.regstk %d, %d, %d, %d\n",
4269 current_frame_info
.n_input_regs
,
4270 current_frame_info
.n_local_regs
,
4271 current_frame_info
.n_output_regs
,
4272 current_frame_info
.n_rotate_regs
);
4274 if (ia64_except_unwind_info (&global_options
) != UI_TARGET
)
4277 /* Emit the .prologue directive. */
4280 grsave
= grsave_prev
= 0;
4281 if (current_frame_info
.r
[reg_save_b0
] != 0)
4284 grsave
= grsave_prev
= current_frame_info
.r
[reg_save_b0
];
4286 if (current_frame_info
.r
[reg_save_ar_pfs
] != 0
4287 && (grsave_prev
== 0
4288 || current_frame_info
.r
[reg_save_ar_pfs
] == grsave_prev
+ 1))
4291 if (grsave_prev
== 0)
4292 grsave
= current_frame_info
.r
[reg_save_ar_pfs
];
4293 grsave_prev
= current_frame_info
.r
[reg_save_ar_pfs
];
4295 if (current_frame_info
.r
[reg_fp
] != 0
4296 && (grsave_prev
== 0
4297 || current_frame_info
.r
[reg_fp
] == grsave_prev
+ 1))
4300 if (grsave_prev
== 0)
4301 grsave
= HARD_FRAME_POINTER_REGNUM
;
4302 grsave_prev
= current_frame_info
.r
[reg_fp
];
4304 if (current_frame_info
.r
[reg_save_pr
] != 0
4305 && (grsave_prev
== 0
4306 || current_frame_info
.r
[reg_save_pr
] == grsave_prev
+ 1))
4309 if (grsave_prev
== 0)
4310 grsave
= current_frame_info
.r
[reg_save_pr
];
4313 if (mask
&& TARGET_GNU_AS
)
4314 fprintf (file
, "\t.prologue %d, %d\n", mask
,
4315 ia64_dbx_register_number (grsave
));
4317 fputs ("\t.prologue\n", file
);
4319 /* Emit a .spill directive, if necessary, to relocate the base of
4320 the register spill area. */
4321 if (current_frame_info
.spill_cfa_off
!= -16)
4322 fprintf (file
, "\t.spill %ld\n",
4323 (long) (current_frame_info
.spill_cfa_off
4324 + current_frame_info
.spill_size
));
4327 /* Emit the .body directive at the scheduled end of the prologue. */
4330 ia64_output_function_end_prologue (FILE *file
)
4332 if (ia64_except_unwind_info (&global_options
) != UI_TARGET
)
4335 fputs ("\t.body\n", file
);
4338 /* Emit the function epilogue. */
4341 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
4342 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4346 if (current_frame_info
.r
[reg_fp
])
4348 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
4349 reg_names
[HARD_FRAME_POINTER_REGNUM
]
4350 = reg_names
[current_frame_info
.r
[reg_fp
]];
4351 reg_names
[current_frame_info
.r
[reg_fp
]] = tmp
;
4352 reg_emitted (reg_fp
);
4354 if (! TARGET_REG_NAMES
)
4356 for (i
= 0; i
< current_frame_info
.n_input_regs
; i
++)
4357 reg_names
[IN_REG (i
)] = ia64_input_reg_names
[i
];
4358 for (i
= 0; i
< current_frame_info
.n_local_regs
; i
++)
4359 reg_names
[LOC_REG (i
)] = ia64_local_reg_names
[i
];
4360 for (i
= 0; i
< current_frame_info
.n_output_regs
; i
++)
4361 reg_names
[OUT_REG (i
)] = ia64_output_reg_names
[i
];
4364 current_frame_info
.initialized
= 0;
4368 ia64_dbx_register_number (int regno
)
4370 /* In ia64_expand_prologue we quite literally renamed the frame pointer
4371 from its home at loc79 to something inside the register frame. We
4372 must perform the same renumbering here for the debug info. */
4373 if (current_frame_info
.r
[reg_fp
])
4375 if (regno
== HARD_FRAME_POINTER_REGNUM
)
4376 regno
= current_frame_info
.r
[reg_fp
];
4377 else if (regno
== current_frame_info
.r
[reg_fp
])
4378 regno
= HARD_FRAME_POINTER_REGNUM
;
4381 if (IN_REGNO_P (regno
))
4382 return 32 + regno
- IN_REG (0);
4383 else if (LOC_REGNO_P (regno
))
4384 return 32 + current_frame_info
.n_input_regs
+ regno
- LOC_REG (0);
4385 else if (OUT_REGNO_P (regno
))
4386 return (32 + current_frame_info
.n_input_regs
4387 + current_frame_info
.n_local_regs
+ regno
- OUT_REG (0));
4392 /* Implement TARGET_TRAMPOLINE_INIT.
4394 The trampoline should set the static chain pointer to value placed
4395 into the trampoline and should branch to the specified routine.
4396 To make the normal indirect-subroutine calling convention work,
4397 the trampoline must look like a function descriptor; the first
4398 word being the target address and the second being the target's
4401 We abuse the concept of a global pointer by arranging for it
4402 to point to the data we need to load. The complete trampoline
4403 has the following form:
4405 +-------------------+ \
4406 TRAMP: | __ia64_trampoline | |
4407 +-------------------+ > fake function descriptor
4409 +-------------------+ /
4410 | target descriptor |
4411 +-------------------+
4413 +-------------------+
4417 ia64_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
4419 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4420 rtx addr
, addr_reg
, tramp
, eight
= GEN_INT (8);
4422 /* The Intel assembler requires that the global __ia64_trampoline symbol
4423 be declared explicitly */
4426 static bool declared_ia64_trampoline
= false;
4428 if (!declared_ia64_trampoline
)
4430 declared_ia64_trampoline
= true;
4431 (*targetm
.asm_out
.globalize_label
) (asm_out_file
,
4432 "__ia64_trampoline");
4436 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
4437 addr
= convert_memory_address (Pmode
, XEXP (m_tramp
, 0));
4438 fnaddr
= convert_memory_address (Pmode
, fnaddr
);
4439 static_chain
= convert_memory_address (Pmode
, static_chain
);
4441 /* Load up our iterator. */
4442 addr_reg
= copy_to_reg (addr
);
4443 m_tramp
= adjust_automodify_address (m_tramp
, Pmode
, addr_reg
, 0);
4445 /* The first two words are the fake descriptor:
4446 __ia64_trampoline, ADDR+16. */
4447 tramp
= gen_rtx_SYMBOL_REF (Pmode
, "__ia64_trampoline");
4448 if (TARGET_ABI_OPEN_VMS
)
4450 /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
4451 in the Macro-32 compiler) and changed the semantics of the LTOFF22
4452 relocation against function symbols to make it identical to the
4453 LTOFF_FPTR22 relocation. Emit the latter directly to stay within
4454 strict ELF and dereference to get the bare code address. */
4455 rtx reg
= gen_reg_rtx (Pmode
);
4456 SYMBOL_REF_FLAGS (tramp
) |= SYMBOL_FLAG_FUNCTION
;
4457 emit_move_insn (reg
, tramp
);
4458 emit_move_insn (reg
, gen_rtx_MEM (Pmode
, reg
));
4461 emit_move_insn (m_tramp
, tramp
);
4462 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4463 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4465 emit_move_insn (m_tramp
, force_reg (Pmode
, plus_constant (Pmode
, addr
, 16)));
4466 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4467 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4469 /* The third word is the target descriptor. */
4470 emit_move_insn (m_tramp
, force_reg (Pmode
, fnaddr
));
4471 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
4472 m_tramp
= adjust_automodify_address (m_tramp
, VOIDmode
, NULL
, 8);
4474 /* The fourth word is the static chain. */
4475 emit_move_insn (m_tramp
, static_chain
);
4478 /* Do any needed setup for a variadic function. CUM has not been updated
4479 for the last named argument which has type TYPE and mode MODE.
4481 We generate the actual spill instructions during prologue generation. */
4484 ia64_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
4485 tree type
, int * pretend_size
,
4486 int second_time ATTRIBUTE_UNUSED
)
4488 CUMULATIVE_ARGS next_cum
= *get_cumulative_args (cum
);
4490 /* Skip the current argument. */
4491 ia64_function_arg_advance (pack_cumulative_args (&next_cum
), mode
, type
, 1);
4493 if (next_cum
.words
< MAX_ARGUMENT_SLOTS
)
4495 int n
= MAX_ARGUMENT_SLOTS
- next_cum
.words
;
4496 *pretend_size
= n
* UNITS_PER_WORD
;
4497 cfun
->machine
->n_varargs
= n
;
4501 /* Check whether TYPE is a homogeneous floating point aggregate. If
4502 it is, return the mode of the floating point type that appears
4503 in all leafs. If it is not, return VOIDmode.
4505 An aggregate is a homogeneous floating point aggregate is if all
4506 fields/elements in it have the same floating point type (e.g,
4507 SFmode). 128-bit quad-precision floats are excluded.
4509 Variable sized aggregates should never arrive here, since we should
4510 have already decided to pass them by reference. Top-level zero-sized
4511 aggregates are excluded because our parallels crash the middle-end. */
4513 static enum machine_mode
4514 hfa_element_mode (const_tree type
, bool nested
)
4516 enum machine_mode element_mode
= VOIDmode
;
4517 enum machine_mode mode
;
4518 enum tree_code code
= TREE_CODE (type
);
4519 int know_element_mode
= 0;
4522 if (!nested
&& (!TYPE_SIZE (type
) || integer_zerop (TYPE_SIZE (type
))))
4527 case VOID_TYPE
: case INTEGER_TYPE
: case ENUMERAL_TYPE
:
4528 case BOOLEAN_TYPE
: case POINTER_TYPE
:
4529 case OFFSET_TYPE
: case REFERENCE_TYPE
: case METHOD_TYPE
:
4530 case LANG_TYPE
: case FUNCTION_TYPE
:
4533 /* Fortran complex types are supposed to be HFAs, so we need to handle
4534 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
4537 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
4538 && TYPE_MODE (type
) != TCmode
)
4539 return GET_MODE_INNER (TYPE_MODE (type
));
4544 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
4545 mode if this is contained within an aggregate. */
4546 if (nested
&& TYPE_MODE (type
) != TFmode
)
4547 return TYPE_MODE (type
);
4552 return hfa_element_mode (TREE_TYPE (type
), 1);
4556 case QUAL_UNION_TYPE
:
4557 for (t
= TYPE_FIELDS (type
); t
; t
= DECL_CHAIN (t
))
4559 if (TREE_CODE (t
) != FIELD_DECL
)
4562 mode
= hfa_element_mode (TREE_TYPE (t
), 1);
4563 if (know_element_mode
)
4565 if (mode
!= element_mode
)
4568 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
4572 know_element_mode
= 1;
4573 element_mode
= mode
;
4576 return element_mode
;
4579 /* If we reach here, we probably have some front-end specific type
4580 that the backend doesn't know about. This can happen via the
4581 aggregate_value_p call in init_function_start. All we can do is
4582 ignore unknown tree types. */
4589 /* Return the number of words required to hold a quantity of TYPE and MODE
4590 when passed as an argument. */
4592 ia64_function_arg_words (const_tree type
, enum machine_mode mode
)
4596 if (mode
== BLKmode
)
4597 words
= int_size_in_bytes (type
);
4599 words
= GET_MODE_SIZE (mode
);
4601 return (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
; /* round up */
4604 /* Return the number of registers that should be skipped so the current
4605 argument (described by TYPE and WORDS) will be properly aligned.
4607 Integer and float arguments larger than 8 bytes start at the next
4608 even boundary. Aggregates larger than 8 bytes start at the next
4609 even boundary if the aggregate has 16 byte alignment. Note that
4610 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4611 but are still to be aligned in registers.
4613 ??? The ABI does not specify how to handle aggregates with
4614 alignment from 9 to 15 bytes, or greater than 16. We handle them
4615 all as if they had 16 byte alignment. Such aggregates can occur
4616 only if gcc extensions are used. */
4618 ia64_function_arg_offset (const CUMULATIVE_ARGS
*cum
,
4619 const_tree type
, int words
)
4621 /* No registers are skipped on VMS. */
4622 if (TARGET_ABI_OPEN_VMS
|| (cum
->words
& 1) == 0)
4626 && TREE_CODE (type
) != INTEGER_TYPE
4627 && TREE_CODE (type
) != REAL_TYPE
)
4628 return TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
;
4633 /* Return rtx for register where argument is passed, or zero if it is passed
4635 /* ??? 128-bit quad-precision floats are always passed in general
4639 ia64_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
4640 const_tree type
, bool named
, bool incoming
)
4642 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4644 int basereg
= (incoming
? GR_ARG_FIRST
: AR_ARG_FIRST
);
4645 int words
= ia64_function_arg_words (type
, mode
);
4646 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4647 enum machine_mode hfa_mode
= VOIDmode
;
4649 /* For OPEN VMS, emit the instruction setting up the argument register here,
4650 when we know this will be together with the other arguments setup related
4651 insns. This is not the conceptually best place to do this, but this is
4652 the easiest as we have convenient access to cumulative args info. */
4654 if (TARGET_ABI_OPEN_VMS
&& mode
== VOIDmode
&& type
== void_type_node
4657 unsigned HOST_WIDE_INT regval
= cum
->words
;
4660 for (i
= 0; i
< 8; i
++)
4661 regval
|= ((int) cum
->atypes
[i
]) << (i
* 3 + 8);
4663 emit_move_insn (gen_rtx_REG (DImode
, GR_REG (25)),
4667 /* If all argument slots are used, then it must go on the stack. */
4668 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
4671 /* On OpenVMS argument is either in Rn or Fn. */
4672 if (TARGET_ABI_OPEN_VMS
)
4674 if (FLOAT_MODE_P (mode
))
4675 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->words
);
4677 return gen_rtx_REG (mode
, basereg
+ cum
->words
);
4680 /* Check for and handle homogeneous FP aggregates. */
4682 hfa_mode
= hfa_element_mode (type
, 0);
4684 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4685 and unprototyped hfas are passed specially. */
4686 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
4690 int fp_regs
= cum
->fp_regs
;
4691 int int_regs
= cum
->words
+ offset
;
4692 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4696 /* If prototyped, pass it in FR regs then GR regs.
4697 If not prototyped, pass it in both FR and GR regs.
4699 If this is an SFmode aggregate, then it is possible to run out of
4700 FR regs while GR regs are still left. In that case, we pass the
4701 remaining part in the GR regs. */
4703 /* Fill the FP regs. We do this always. We stop if we reach the end
4704 of the argument, the last FP register, or the last argument slot. */
4706 byte_size
= ((mode
== BLKmode
)
4707 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4708 args_byte_size
= int_regs
* UNITS_PER_WORD
;
4710 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
4711 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
)); i
++)
4713 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4714 gen_rtx_REG (hfa_mode
, (FR_ARG_FIRST
4718 args_byte_size
+= hfa_size
;
4722 /* If no prototype, then the whole thing must go in GR regs. */
4723 if (! cum
->prototype
)
4725 /* If this is an SFmode aggregate, then we might have some left over
4726 that needs to go in GR regs. */
4727 else if (byte_size
!= offset
)
4728 int_regs
+= offset
/ UNITS_PER_WORD
;
4730 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4732 for (; offset
< byte_size
&& int_regs
< MAX_ARGUMENT_SLOTS
; i
++)
4734 enum machine_mode gr_mode
= DImode
;
4735 unsigned int gr_size
;
4737 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4738 then this goes in a GR reg left adjusted/little endian, right
4739 adjusted/big endian. */
4740 /* ??? Currently this is handled wrong, because 4-byte hunks are
4741 always right adjusted/little endian. */
4744 /* If we have an even 4 byte hunk because the aggregate is a
4745 multiple of 4 bytes in size, then this goes in a GR reg right
4746 adjusted/little endian. */
4747 else if (byte_size
- offset
== 4)
4750 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4751 gen_rtx_REG (gr_mode
, (basereg
4755 gr_size
= GET_MODE_SIZE (gr_mode
);
4757 if (gr_size
== UNITS_PER_WORD
4758 || (gr_size
< UNITS_PER_WORD
&& offset
% UNITS_PER_WORD
== 0))
4760 else if (gr_size
> UNITS_PER_WORD
)
4761 int_regs
+= gr_size
/ UNITS_PER_WORD
;
4763 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4766 /* Integral and aggregates go in general registers. If we have run out of
4767 FR registers, then FP values must also go in general registers. This can
4768 happen when we have a SFmode HFA. */
4769 else if (mode
== TFmode
|| mode
== TCmode
4770 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
4772 int byte_size
= ((mode
== BLKmode
)
4773 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4774 if (BYTES_BIG_ENDIAN
4775 && (mode
== BLKmode
|| (type
&& AGGREGATE_TYPE_P (type
)))
4776 && byte_size
< UNITS_PER_WORD
4779 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4780 gen_rtx_REG (DImode
,
4781 (basereg
+ cum
->words
4784 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, gr_reg
));
4787 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
4791 /* If there is a prototype, then FP values go in a FR register when
4792 named, and in a GR register when unnamed. */
4793 else if (cum
->prototype
)
4796 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->fp_regs
);
4797 /* In big-endian mode, an anonymous SFmode value must be represented
4798 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4799 the value into the high half of the general register. */
4800 else if (BYTES_BIG_ENDIAN
&& mode
== SFmode
)
4801 return gen_rtx_PARALLEL (mode
,
4803 gen_rtx_EXPR_LIST (VOIDmode
,
4804 gen_rtx_REG (DImode
, basereg
+ cum
->words
+ offset
),
4807 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
4809 /* If there is no prototype, then FP values go in both FR and GR
4813 /* See comment above. */
4814 enum machine_mode inner_mode
=
4815 (BYTES_BIG_ENDIAN
&& mode
== SFmode
) ? DImode
: mode
;
4817 rtx fp_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4818 gen_rtx_REG (mode
, (FR_ARG_FIRST
4821 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
4822 gen_rtx_REG (inner_mode
,
4823 (basereg
+ cum
->words
4827 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, fp_reg
, gr_reg
));
4831 /* Implement TARGET_FUNCION_ARG target hook. */
4834 ia64_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
4835 const_tree type
, bool named
)
4837 return ia64_function_arg_1 (cum
, mode
, type
, named
, false);
4840 /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */
4843 ia64_function_incoming_arg (cumulative_args_t cum
,
4844 enum machine_mode mode
,
4845 const_tree type
, bool named
)
4847 return ia64_function_arg_1 (cum
, mode
, type
, named
, true);
4850 /* Return number of bytes, at the beginning of the argument, that must be
4851 put in registers. 0 is the argument is entirely in registers or entirely
4855 ia64_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
4856 tree type
, bool named ATTRIBUTE_UNUSED
)
4858 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4860 int words
= ia64_function_arg_words (type
, mode
);
4861 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4863 /* If all argument slots are used, then it must go on the stack. */
4864 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
4867 /* It doesn't matter whether the argument goes in FR or GR regs. If
4868 it fits within the 8 argument slots, then it goes entirely in
4869 registers. If it extends past the last argument slot, then the rest
4870 goes on the stack. */
4872 if (words
+ cum
->words
+ offset
<= MAX_ARGUMENT_SLOTS
)
4875 return (MAX_ARGUMENT_SLOTS
- cum
->words
- offset
) * UNITS_PER_WORD
;
4878 /* Return ivms_arg_type based on machine_mode. */
4880 static enum ivms_arg_type
4881 ia64_arg_type (enum machine_mode mode
)
4894 /* Update CUM to point after this argument. This is patterned after
4895 ia64_function_arg. */
4898 ia64_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
4899 const_tree type
, bool named
)
4901 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4902 int words
= ia64_function_arg_words (type
, mode
);
4903 int offset
= ia64_function_arg_offset (cum
, type
, words
);
4904 enum machine_mode hfa_mode
= VOIDmode
;
4906 /* If all arg slots are already full, then there is nothing to do. */
4907 if (cum
->words
>= MAX_ARGUMENT_SLOTS
)
4909 cum
->words
+= words
+ offset
;
4913 cum
->atypes
[cum
->words
] = ia64_arg_type (mode
);
4914 cum
->words
+= words
+ offset
;
4916 /* On OpenVMS argument is either in Rn or Fn. */
4917 if (TARGET_ABI_OPEN_VMS
)
4919 cum
->int_regs
= cum
->words
;
4920 cum
->fp_regs
= cum
->words
;
4924 /* Check for and handle homogeneous FP aggregates. */
4926 hfa_mode
= hfa_element_mode (type
, 0);
4928 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4929 and unprototyped hfas are passed specially. */
4930 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
4932 int fp_regs
= cum
->fp_regs
;
4933 /* This is the original value of cum->words + offset. */
4934 int int_regs
= cum
->words
- words
;
4935 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4939 /* If prototyped, pass it in FR regs then GR regs.
4940 If not prototyped, pass it in both FR and GR regs.
4942 If this is an SFmode aggregate, then it is possible to run out of
4943 FR regs while GR regs are still left. In that case, we pass the
4944 remaining part in the GR regs. */
4946 /* Fill the FP regs. We do this always. We stop if we reach the end
4947 of the argument, the last FP register, or the last argument slot. */
4949 byte_size
= ((mode
== BLKmode
)
4950 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
4951 args_byte_size
= int_regs
* UNITS_PER_WORD
;
4953 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
4954 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
));)
4957 args_byte_size
+= hfa_size
;
4961 cum
->fp_regs
= fp_regs
;
4964 /* Integral and aggregates go in general registers. So do TFmode FP values.
4965 If we have run out of FR registers, then other FP values must also go in
4966 general registers. This can happen when we have a SFmode HFA. */
4967 else if (mode
== TFmode
|| mode
== TCmode
4968 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
4969 cum
->int_regs
= cum
->words
;
4971 /* If there is a prototype, then FP values go in a FR register when
4972 named, and in a GR register when unnamed. */
4973 else if (cum
->prototype
)
4976 cum
->int_regs
= cum
->words
;
4978 /* ??? Complex types should not reach here. */
4979 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
4981 /* If there is no prototype, then FP values go in both FR and GR
4985 /* ??? Complex types should not reach here. */
4986 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
4987 cum
->int_regs
= cum
->words
;
4991 /* Arguments with alignment larger than 8 bytes start at the next even
4992 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4993 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4996 ia64_function_arg_boundary (enum machine_mode mode
, const_tree type
)
4998 if (mode
== TFmode
&& TARGET_HPUX
&& TARGET_ILP32
)
4999 return PARM_BOUNDARY
* 2;
5003 if (TYPE_ALIGN (type
) > PARM_BOUNDARY
)
5004 return PARM_BOUNDARY
* 2;
5006 return PARM_BOUNDARY
;
5009 if (GET_MODE_BITSIZE (mode
) > PARM_BOUNDARY
)
5010 return PARM_BOUNDARY
* 2;
5012 return PARM_BOUNDARY
;
5015 /* True if it is OK to do sibling call optimization for the specified
5016 call expression EXP. DECL will be the called function, or NULL if
5017 this is an indirect call. */
5019 ia64_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
5021 /* We can't perform a sibcall if the current function has the syscall_linkage
5023 if (lookup_attribute ("syscall_linkage",
5024 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
5027 /* We must always return with our current GP. This means we can
5028 only sibcall to functions defined in the current module unless
5029 TARGET_CONST_GP is set to true. */
5030 return (decl
&& (*targetm
.binds_local_p
) (decl
)) || TARGET_CONST_GP
;
5034 /* Implement va_arg. */
5037 ia64_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
5040 /* Variable sized types are passed by reference. */
5041 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
5043 tree ptrtype
= build_pointer_type (type
);
5044 tree addr
= std_gimplify_va_arg_expr (valist
, ptrtype
, pre_p
, post_p
);
5045 return build_va_arg_indirect_ref (addr
);
5048 /* Aggregate arguments with alignment larger than 8 bytes start at
5049 the next even boundary. Integer and floating point arguments
5050 do so if they are larger than 8 bytes, whether or not they are
5051 also aligned larger than 8 bytes. */
5052 if ((TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == INTEGER_TYPE
)
5053 ? int_size_in_bytes (type
) > 8 : TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
5055 tree t
= fold_build_pointer_plus_hwi (valist
, 2 * UNITS_PER_WORD
- 1);
5056 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
5057 build_int_cst (TREE_TYPE (t
), -2 * UNITS_PER_WORD
));
5058 gimplify_assign (unshare_expr (valist
), t
, pre_p
);
5061 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5064 /* Return 1 if function return value returned in memory. Return 0 if it is
5068 ia64_return_in_memory (const_tree valtype
, const_tree fntype ATTRIBUTE_UNUSED
)
5070 enum machine_mode mode
;
5071 enum machine_mode hfa_mode
;
5072 HOST_WIDE_INT byte_size
;
5074 mode
= TYPE_MODE (valtype
);
5075 byte_size
= GET_MODE_SIZE (mode
);
5076 if (mode
== BLKmode
)
5078 byte_size
= int_size_in_bytes (valtype
);
5083 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
5085 hfa_mode
= hfa_element_mode (valtype
, 0);
5086 if (hfa_mode
!= VOIDmode
)
5088 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
5090 if (byte_size
/ hfa_size
> MAX_ARGUMENT_SLOTS
)
5095 else if (byte_size
> UNITS_PER_WORD
* MAX_INT_RETURN_SLOTS
)
5101 /* Return rtx for register that holds the function return value. */
5104 ia64_function_value (const_tree valtype
,
5105 const_tree fn_decl_or_type
,
5106 bool outgoing ATTRIBUTE_UNUSED
)
5108 enum machine_mode mode
;
5109 enum machine_mode hfa_mode
;
5111 const_tree func
= fn_decl_or_type
;
5114 && !DECL_P (fn_decl_or_type
))
5117 mode
= TYPE_MODE (valtype
);
5118 hfa_mode
= hfa_element_mode (valtype
, 0);
5120 if (hfa_mode
!= VOIDmode
)
5128 hfa_size
= GET_MODE_SIZE (hfa_mode
);
5129 byte_size
= ((mode
== BLKmode
)
5130 ? int_size_in_bytes (valtype
) : GET_MODE_SIZE (mode
));
5132 for (i
= 0; offset
< byte_size
; i
++)
5134 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
5135 gen_rtx_REG (hfa_mode
, FR_ARG_FIRST
+ i
),
5139 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
5141 else if (FLOAT_TYPE_P (valtype
) && mode
!= TFmode
&& mode
!= TCmode
)
5142 return gen_rtx_REG (mode
, FR_ARG_FIRST
);
5145 bool need_parallel
= false;
5147 /* In big-endian mode, we need to manage the layout of aggregates
5148 in the registers so that we get the bits properly aligned in
5149 the highpart of the registers. */
5150 if (BYTES_BIG_ENDIAN
5151 && (mode
== BLKmode
|| (valtype
&& AGGREGATE_TYPE_P (valtype
))))
5152 need_parallel
= true;
5154 /* Something like struct S { long double x; char a[0] } is not an
5155 HFA structure, and therefore doesn't go in fp registers. But
5156 the middle-end will give it XFmode anyway, and XFmode values
5157 don't normally fit in integer registers. So we need to smuggle
5158 the value inside a parallel. */
5159 else if (mode
== XFmode
|| mode
== XCmode
|| mode
== RFmode
)
5160 need_parallel
= true;
5170 bytesize
= int_size_in_bytes (valtype
);
5171 /* An empty PARALLEL is invalid here, but the return value
5172 doesn't matter for empty structs. */
5174 return gen_rtx_REG (mode
, GR_RET_FIRST
);
5175 for (i
= 0; offset
< bytesize
; i
++)
5177 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
5178 gen_rtx_REG (DImode
,
5181 offset
+= UNITS_PER_WORD
;
5183 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
5186 mode
= promote_function_mode (valtype
, mode
, &unsignedp
,
5187 func
? TREE_TYPE (func
) : NULL_TREE
,
5190 return gen_rtx_REG (mode
, GR_RET_FIRST
);
5194 /* Worker function for TARGET_LIBCALL_VALUE. */
5197 ia64_libcall_value (enum machine_mode mode
,
5198 const_rtx fun ATTRIBUTE_UNUSED
)
5200 return gen_rtx_REG (mode
,
5201 (((GET_MODE_CLASS (mode
) == MODE_FLOAT
5202 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5203 && (mode
) != TFmode
)
5204 ? FR_RET_FIRST
: GR_RET_FIRST
));
5207 /* Worker function for FUNCTION_VALUE_REGNO_P. */
5210 ia64_function_value_regno_p (const unsigned int regno
)
5212 return ((regno
>= GR_RET_FIRST
&& regno
<= GR_RET_LAST
)
5213 || (regno
>= FR_RET_FIRST
&& regno
<= FR_RET_LAST
));
5216 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5217 We need to emit DTP-relative relocations. */
5220 ia64_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5222 gcc_assert (size
== 4 || size
== 8);
5224 fputs ("\tdata4.ua\t@dtprel(", file
);
5226 fputs ("\tdata8.ua\t@dtprel(", file
);
5227 output_addr_const (file
, x
);
5231 /* Print a memory address as an operand to reference that memory location. */
5233 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
5234 also call this from ia64_print_operand for memory addresses. */
5237 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED
,
5238 rtx address ATTRIBUTE_UNUSED
)
5242 /* Print an operand to an assembler instruction.
5243 C Swap and print a comparison operator.
5244 D Print an FP comparison operator.
5245 E Print 32 - constant, for SImode shifts as extract.
5246 e Print 64 - constant, for DImode rotates.
5247 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
5248 a floating point register emitted normally.
5249 G A floating point constant.
5250 I Invert a predicate register by adding 1.
5251 J Select the proper predicate register for a condition.
5252 j Select the inverse predicate register for a condition.
5253 O Append .acq for volatile load.
5254 P Postincrement of a MEM.
5255 Q Append .rel for volatile store.
5256 R Print .s .d or nothing for a single, double or no truncation.
5257 S Shift amount for shladd instruction.
5258 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
5259 for Intel assembler.
5260 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
5261 for Intel assembler.
5262 X A pair of floating point registers.
5263 r Print register name, or constant 0 as r0. HP compatibility for
5265 v Print vector constant value as an 8-byte integer value. */
5268 ia64_print_operand (FILE * file
, rtx x
, int code
)
5275 /* Handled below. */
5280 enum rtx_code c
= swap_condition (GET_CODE (x
));
5281 fputs (GET_RTX_NAME (c
), file
);
5286 switch (GET_CODE (x
))
5313 str
= GET_RTX_NAME (GET_CODE (x
));
5320 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
5324 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - INTVAL (x
));
5328 if (x
== CONST0_RTX (GET_MODE (x
)))
5329 str
= reg_names
[FR_REG (0)];
5330 else if (x
== CONST1_RTX (GET_MODE (x
)))
5331 str
= reg_names
[FR_REG (1)];
5334 gcc_assert (GET_CODE (x
) == REG
);
5335 str
= reg_names
[REGNO (x
)];
5344 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
5345 real_to_target (val
, &rv
, GET_MODE (x
));
5346 if (GET_MODE (x
) == SFmode
)
5347 fprintf (file
, "0x%08lx", val
[0] & 0xffffffff);
5348 else if (GET_MODE (x
) == DFmode
)
5349 fprintf (file
, "0x%08lx%08lx", (WORDS_BIG_ENDIAN
? val
[0] : val
[1])
5351 (WORDS_BIG_ENDIAN
? val
[1] : val
[0])
5354 output_operand_lossage ("invalid %%G mode");
5359 fputs (reg_names
[REGNO (x
) + 1], file
);
5365 unsigned int regno
= REGNO (XEXP (x
, 0));
5366 if (GET_CODE (x
) == EQ
)
5370 fputs (reg_names
[regno
], file
);
5375 if (MEM_VOLATILE_P (x
))
5376 fputs(".acq", file
);
5381 HOST_WIDE_INT value
;
5383 switch (GET_CODE (XEXP (x
, 0)))
5389 x
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
5390 if (GET_CODE (x
) == CONST_INT
)
5394 gcc_assert (GET_CODE (x
) == REG
);
5395 fprintf (file
, ", %s", reg_names
[REGNO (x
)]);
5401 value
= GET_MODE_SIZE (GET_MODE (x
));
5405 value
= - (HOST_WIDE_INT
) GET_MODE_SIZE (GET_MODE (x
));
5409 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
, value
);
5414 if (MEM_VOLATILE_P (x
))
5415 fputs(".rel", file
);
5419 if (x
== CONST0_RTX (GET_MODE (x
)))
5421 else if (x
== CONST1_RTX (GET_MODE (x
)))
5423 else if (x
== CONST2_RTX (GET_MODE (x
)))
5426 output_operand_lossage ("invalid %%R value");
5430 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
5434 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
5436 fprintf (file
, "0x%x", (int) INTVAL (x
) & 0xffffffff);
5442 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
5444 const char *prefix
= "0x";
5445 if (INTVAL (x
) & 0x80000000)
5447 fprintf (file
, "0xffffffff");
5450 fprintf (file
, "%s%x", prefix
, (int) INTVAL (x
) & 0xffffffff);
5457 unsigned int regno
= REGNO (x
);
5458 fprintf (file
, "%s, %s", reg_names
[regno
], reg_names
[regno
+ 1]);
5463 /* If this operand is the constant zero, write it as register zero.
5464 Any register, zero, or CONST_INT value is OK here. */
5465 if (GET_CODE (x
) == REG
)
5466 fputs (reg_names
[REGNO (x
)], file
);
5467 else if (x
== CONST0_RTX (GET_MODE (x
)))
5469 else if (GET_CODE (x
) == CONST_INT
)
5470 output_addr_const (file
, x
);
5472 output_operand_lossage ("invalid %%r value");
5476 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
5477 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
5484 /* For conditional branches, returns or calls, substitute
5485 sptk, dptk, dpnt, or spnt for %s. */
5486 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
5489 int pred_val
= XINT (x
, 0);
5491 /* Guess top and bottom 10% statically predicted. */
5492 if (pred_val
< REG_BR_PROB_BASE
/ 50
5493 && br_prob_note_reliable_p (x
))
5495 else if (pred_val
< REG_BR_PROB_BASE
/ 2)
5497 else if (pred_val
< REG_BR_PROB_BASE
/ 100 * 98
5498 || !br_prob_note_reliable_p (x
))
5503 else if (CALL_P (current_output_insn
))
5508 fputs (which
, file
);
5513 x
= current_insn_predicate
;
5516 unsigned int regno
= REGNO (XEXP (x
, 0));
5517 if (GET_CODE (x
) == EQ
)
5519 fprintf (file
, "(%s) ", reg_names
[regno
]);
5524 output_operand_lossage ("ia64_print_operand: unknown code");
5528 switch (GET_CODE (x
))
5530 /* This happens for the spill/restore instructions. */
5535 /* ... fall through ... */
5538 fputs (reg_names
[REGNO (x
)], file
);
5543 rtx addr
= XEXP (x
, 0);
5544 if (GET_RTX_CLASS (GET_CODE (addr
)) == RTX_AUTOINC
)
5545 addr
= XEXP (addr
, 0);
5546 fprintf (file
, "[%s]", reg_names
[REGNO (addr
)]);
5551 output_addr_const (file
, x
);
5558 /* Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
5561 ia64_print_operand_punct_valid_p (unsigned char code
)
5563 return (code
== '+' || code
== ',');
5566 /* Compute a (partial) cost for rtx X. Return true if the complete
5567 cost has been computed, and false if subexpressions should be
5568 scanned. In either case, *TOTAL contains the cost result. */
5569 /* ??? This is incomplete. */
5572 ia64_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
5573 int *total
, bool speed ATTRIBUTE_UNUSED
)
5581 *total
= satisfies_constraint_J (x
) ? 0 : COSTS_N_INSNS (1);
5584 if (satisfies_constraint_I (x
))
5586 else if (satisfies_constraint_J (x
))
5589 *total
= COSTS_N_INSNS (1);
5592 if (satisfies_constraint_K (x
) || satisfies_constraint_L (x
))
5595 *total
= COSTS_N_INSNS (1);
5600 *total
= COSTS_N_INSNS (1);
5606 *total
= COSTS_N_INSNS (3);
5610 *total
= COSTS_N_INSNS (4);
5614 /* For multiplies wider than HImode, we have to go to the FPU,
5615 which normally involves copies. Plus there's the latency
5616 of the multiply itself, and the latency of the instructions to
5617 transfer integer regs to FP regs. */
5618 if (FLOAT_MODE_P (GET_MODE (x
)))
5619 *total
= COSTS_N_INSNS (4);
5620 else if (GET_MODE_SIZE (GET_MODE (x
)) > 2)
5621 *total
= COSTS_N_INSNS (10);
5623 *total
= COSTS_N_INSNS (2);
5628 if (FLOAT_MODE_P (GET_MODE (x
)))
5630 *total
= COSTS_N_INSNS (4);
5638 *total
= COSTS_N_INSNS (1);
5645 /* We make divide expensive, so that divide-by-constant will be
5646 optimized to a multiply. */
5647 *total
= COSTS_N_INSNS (60);
5655 /* Calculate the cost of moving data from a register in class FROM to
5656 one in class TO, using MODE. */
5659 ia64_register_move_cost (enum machine_mode mode
, reg_class_t from
,
5662 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
5663 if (to
== ADDL_REGS
)
5665 if (from
== ADDL_REGS
)
5668 /* All costs are symmetric, so reduce cases by putting the
5669 lower number class as the destination. */
5672 reg_class_t tmp
= to
;
5673 to
= from
, from
= tmp
;
5676 /* Moving from FR<->GR in XFmode must be more expensive than 2,
5677 so that we get secondary memory reloads. Between FR_REGS,
5678 we have to make this at least as expensive as memory_move_cost
5679 to avoid spectacularly poor register class preferencing. */
5680 if (mode
== XFmode
|| mode
== RFmode
)
5682 if (to
!= GR_REGS
|| from
!= GR_REGS
)
5683 return memory_move_cost (mode
, to
, false);
5691 /* Moving between PR registers takes two insns. */
5692 if (from
== PR_REGS
)
5694 /* Moving between PR and anything but GR is impossible. */
5695 if (from
!= GR_REGS
)
5696 return memory_move_cost (mode
, to
, false);
5700 /* Moving between BR and anything but GR is impossible. */
5701 if (from
!= GR_REGS
&& from
!= GR_AND_BR_REGS
)
5702 return memory_move_cost (mode
, to
, false);
5707 /* Moving between AR and anything but GR is impossible. */
5708 if (from
!= GR_REGS
)
5709 return memory_move_cost (mode
, to
, false);
5715 case GR_AND_FR_REGS
:
5716 case GR_AND_BR_REGS
:
5727 /* Calculate the cost of moving data of MODE from a register to or from
5731 ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
5733 bool in ATTRIBUTE_UNUSED
)
5735 if (rclass
== GENERAL_REGS
5736 || rclass
== FR_REGS
5737 || rclass
== FP_REGS
5738 || rclass
== GR_AND_FR_REGS
)
5744 /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions
5745 on RCLASS to use when copying X into that class. */
5748 ia64_preferred_reload_class (rtx x
, reg_class_t rclass
)
5754 /* Don't allow volatile mem reloads into floating point registers.
5755 This is defined to force reload to choose the r/m case instead
5756 of the f/f case when reloading (set (reg fX) (mem/v)). */
5757 if (MEM_P (x
) && MEM_VOLATILE_P (x
))
5760 /* Force all unrecognized constants into the constant pool. */
5778 /* This function returns the register class required for a secondary
5779 register when copying between one of the registers in RCLASS, and X,
5780 using MODE. A return value of NO_REGS means that no secondary register
5784 ia64_secondary_reload_class (enum reg_class rclass
,
5785 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
5789 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
5790 regno
= true_regnum (x
);
5797 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5798 interaction. We end up with two pseudos with overlapping lifetimes
5799 both of which are equiv to the same constant, and both which need
5800 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5801 changes depending on the path length, which means the qty_first_reg
5802 check in make_regs_eqv can give different answers at different times.
5803 At some point I'll probably need a reload_indi pattern to handle
5806 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5807 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5808 non-general registers for good measure. */
5809 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
))
5812 /* This is needed if a pseudo used as a call_operand gets spilled to a
5814 if (GET_CODE (x
) == MEM
)
5820 /* Need to go through general registers to get to other class regs. */
5821 if (regno
>= 0 && ! (FR_REGNO_P (regno
) || GENERAL_REGNO_P (regno
)))
5824 /* This can happen when a paradoxical subreg is an operand to the
5826 /* ??? This shouldn't be necessary after instruction scheduling is
5827 enabled, because paradoxical subregs are not accepted by
5828 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5829 stop the paradoxical subreg stupidity in the *_operand functions
5831 if (GET_CODE (x
) == MEM
5832 && (GET_MODE (x
) == SImode
|| GET_MODE (x
) == HImode
5833 || GET_MODE (x
) == QImode
))
5836 /* This can happen because of the ior/and/etc patterns that accept FP
5837 registers as operands. If the third operand is a constant, then it
5838 needs to be reloaded into a FP register. */
5839 if (GET_CODE (x
) == CONST_INT
)
5842 /* This can happen because of register elimination in a muldi3 insn.
5843 E.g. `26107 * (unsigned long)&u'. */
5844 if (GET_CODE (x
) == PLUS
)
5849 /* ??? This happens if we cse/gcse a BImode value across a call,
5850 and the function has a nonlocal goto. This is because global
5851 does not allocate call crossing pseudos to hard registers when
5852 crtl->has_nonlocal_goto is true. This is relatively
5853 common for C++ programs that use exceptions. To reproduce,
5854 return NO_REGS and compile libstdc++. */
5855 if (GET_CODE (x
) == MEM
)
5858 /* This can happen when we take a BImode subreg of a DImode value,
5859 and that DImode value winds up in some non-GR register. */
5860 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
) && ! PR_REGNO_P (regno
))
5872 /* Implement targetm.unspec_may_trap_p hook. */
5874 ia64_unspec_may_trap_p (const_rtx x
, unsigned flags
)
5876 switch (XINT (x
, 1))
5882 case UNSPEC_CHKACLR
:
5884 /* These unspecs are just wrappers. */
5885 return may_trap_p_1 (XVECEXP (x
, 0, 0), flags
);
5888 return default_unspec_may_trap_p (x
, flags
);
5892 /* Parse the -mfixed-range= option string. */
5895 fix_range (const char *const_str
)
5898 char *str
, *dash
, *comma
;
5900 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5901 REG2 are either register names or register numbers. The effect
5902 of this option is to mark the registers in the range from REG1 to
5903 REG2 as ``fixed'' so they won't be used by the compiler. This is
5904 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5906 i
= strlen (const_str
);
5907 str
= (char *) alloca (i
+ 1);
5908 memcpy (str
, const_str
, i
+ 1);
5912 dash
= strchr (str
, '-');
5915 warning (0, "value of -mfixed-range must have form REG1-REG2");
5920 comma
= strchr (dash
+ 1, ',');
5924 first
= decode_reg_name (str
);
5927 warning (0, "unknown register name: %s", str
);
5931 last
= decode_reg_name (dash
+ 1);
5934 warning (0, "unknown register name: %s", dash
+ 1);
5942 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
5946 for (i
= first
; i
<= last
; ++i
)
5947 fixed_regs
[i
] = call_used_regs
[i
] = 1;
5957 /* Implement TARGET_OPTION_OVERRIDE. */
5960 ia64_option_override (void)
5963 cl_deferred_option
*opt
;
5964 vec
<cl_deferred_option
> *v
5965 = (vec
<cl_deferred_option
> *) ia64_deferred_options
;
5968 FOR_EACH_VEC_ELT (*v
, i
, opt
)
5970 switch (opt
->opt_index
)
5972 case OPT_mfixed_range_
:
5973 fix_range (opt
->arg
);
5981 if (TARGET_AUTO_PIC
)
5982 target_flags
|= MASK_CONST_GP
;
5984 /* Numerous experiment shows that IRA based loop pressure
5985 calculation works better for RTL loop invariant motion on targets
5986 with enough (>= 32) registers. It is an expensive optimization.
5987 So it is on only for peak performance. */
5989 flag_ira_loop_pressure
= 1;
5992 ia64_section_threshold
= (global_options_set
.x_g_switch_value
5994 : IA64_DEFAULT_GVALUE
);
5996 init_machine_status
= ia64_init_machine_status
;
5998 if (align_functions
<= 0)
5999 align_functions
= 64;
6000 if (align_loops
<= 0)
6002 if (TARGET_ABI_OPEN_VMS
)
6005 ia64_override_options_after_change();
6008 /* Implement targetm.override_options_after_change. */
6011 ia64_override_options_after_change (void)
6014 && !global_options_set
.x_flag_selective_scheduling
6015 && !global_options_set
.x_flag_selective_scheduling2
)
6017 flag_selective_scheduling2
= 1;
6018 flag_sel_sched_pipelining
= 1;
6020 if (mflag_sched_control_spec
== 2)
6022 /* Control speculation is on by default for the selective scheduler,
6023 but not for the Haifa scheduler. */
6024 mflag_sched_control_spec
= flag_selective_scheduling2
? 1 : 0;
6026 if (flag_sel_sched_pipelining
&& flag_auto_inc_dec
)
6028 /* FIXME: remove this when we'd implement breaking autoinsns as
6029 a transformation. */
6030 flag_auto_inc_dec
= 0;
6034 /* Initialize the record of emitted frame related registers. */
6036 void ia64_init_expanders (void)
6038 memset (&emitted_frame_related_regs
, 0, sizeof (emitted_frame_related_regs
));
6041 static struct machine_function
*
6042 ia64_init_machine_status (void)
6044 return ggc_cleared_alloc
<machine_function
> ();
6047 static enum attr_itanium_class
ia64_safe_itanium_class (rtx
);
6048 static enum attr_type
ia64_safe_type (rtx
);
6050 static enum attr_itanium_class
6051 ia64_safe_itanium_class (rtx insn
)
6053 if (recog_memoized (insn
) >= 0)
6054 return get_attr_itanium_class (insn
);
6055 else if (DEBUG_INSN_P (insn
))
6056 return ITANIUM_CLASS_IGNORE
;
6058 return ITANIUM_CLASS_UNKNOWN
;
6061 static enum attr_type
6062 ia64_safe_type (rtx insn
)
6064 if (recog_memoized (insn
) >= 0)
6065 return get_attr_type (insn
);
6067 return TYPE_UNKNOWN
;
6070 /* The following collection of routines emit instruction group stop bits as
6071 necessary to avoid dependencies. */
6073 /* Need to track some additional registers as far as serialization is
6074 concerned so we can properly handle br.call and br.ret. We could
6075 make these registers visible to gcc, but since these registers are
6076 never explicitly used in gcc generated code, it seems wasteful to
6077 do so (plus it would make the call and return patterns needlessly
6079 #define REG_RP (BR_REG (0))
6080 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
6081 /* This is used for volatile asms which may require a stop bit immediately
6082 before and after them. */
6083 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
6084 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
6085 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
6087 /* For each register, we keep track of how it has been written in the
6088 current instruction group.
6090 If a register is written unconditionally (no qualifying predicate),
6091 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
6093 If a register is written if its qualifying predicate P is true, we
6094 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
6095 may be written again by the complement of P (P^1) and when this happens,
6096 WRITE_COUNT gets set to 2.
6098 The result of this is that whenever an insn attempts to write a register
6099 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
6101 If a predicate register is written by a floating-point insn, we set
6102 WRITTEN_BY_FP to true.
6104 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
6105 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
6107 #if GCC_VERSION >= 4000
6108 #define RWS_FIELD_TYPE __extension__ unsigned short
6110 #define RWS_FIELD_TYPE unsigned int
6112 struct reg_write_state
6114 RWS_FIELD_TYPE write_count
: 2;
6115 RWS_FIELD_TYPE first_pred
: 10;
6116 RWS_FIELD_TYPE written_by_fp
: 1;
6117 RWS_FIELD_TYPE written_by_and
: 1;
6118 RWS_FIELD_TYPE written_by_or
: 1;
6121 /* Cumulative info for the current instruction group. */
6122 struct reg_write_state rws_sum
[NUM_REGS
];
6123 #ifdef ENABLE_CHECKING
6124 /* Bitmap whether a register has been written in the current insn. */
6125 HARD_REG_ELT_TYPE rws_insn
[(NUM_REGS
+ HOST_BITS_PER_WIDEST_FAST_INT
- 1)
6126 / HOST_BITS_PER_WIDEST_FAST_INT
];
6129 rws_insn_set (int regno
)
6131 gcc_assert (!TEST_HARD_REG_BIT (rws_insn
, regno
));
6132 SET_HARD_REG_BIT (rws_insn
, regno
);
6136 rws_insn_test (int regno
)
6138 return TEST_HARD_REG_BIT (rws_insn
, regno
);
6141 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
6142 unsigned char rws_insn
[2];
6145 rws_insn_set (int regno
)
6147 if (regno
== REG_AR_CFM
)
6149 else if (regno
== REG_VOLATILE
)
6154 rws_insn_test (int regno
)
6156 if (regno
== REG_AR_CFM
)
6158 if (regno
== REG_VOLATILE
)
6164 /* Indicates whether this is the first instruction after a stop bit,
6165 in which case we don't need another stop bit. Without this,
6166 ia64_variable_issue will die when scheduling an alloc. */
6167 static int first_instruction
;
6169 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
6170 RTL for one instruction. */
6173 unsigned int is_write
: 1; /* Is register being written? */
6174 unsigned int is_fp
: 1; /* Is register used as part of an fp op? */
6175 unsigned int is_branch
: 1; /* Is register used as part of a branch? */
6176 unsigned int is_and
: 1; /* Is register used as part of and.orcm? */
6177 unsigned int is_or
: 1; /* Is register used as part of or.andcm? */
6178 unsigned int is_sibcall
: 1; /* Is this a sibling or normal call? */
6181 static void rws_update (int, struct reg_flags
, int);
6182 static int rws_access_regno (int, struct reg_flags
, int);
6183 static int rws_access_reg (rtx
, struct reg_flags
, int);
6184 static void update_set_flags (rtx
, struct reg_flags
*);
6185 static int set_src_needs_barrier (rtx
, struct reg_flags
, int);
6186 static int rtx_needs_barrier (rtx
, struct reg_flags
, int);
6187 static void init_insn_group_barriers (void);
6188 static int group_barrier_needed (rtx
);
6189 static int safe_group_barrier_needed (rtx
);
6190 static int in_safe_group_barrier
;
6192 /* Update *RWS for REGNO, which is being written by the current instruction,
6193 with predicate PRED, and associated register flags in FLAGS. */
6196 rws_update (int regno
, struct reg_flags flags
, int pred
)
6199 rws_sum
[regno
].write_count
++;
6201 rws_sum
[regno
].write_count
= 2;
6202 rws_sum
[regno
].written_by_fp
|= flags
.is_fp
;
6203 /* ??? Not tracking and/or across differing predicates. */
6204 rws_sum
[regno
].written_by_and
= flags
.is_and
;
6205 rws_sum
[regno
].written_by_or
= flags
.is_or
;
6206 rws_sum
[regno
].first_pred
= pred
;
6209 /* Handle an access to register REGNO of type FLAGS using predicate register
6210 PRED. Update rws_sum array. Return 1 if this access creates
6211 a dependency with an earlier instruction in the same group. */
6214 rws_access_regno (int regno
, struct reg_flags flags
, int pred
)
6216 int need_barrier
= 0;
6218 gcc_assert (regno
< NUM_REGS
);
6220 if (! PR_REGNO_P (regno
))
6221 flags
.is_and
= flags
.is_or
= 0;
6227 rws_insn_set (regno
);
6228 write_count
= rws_sum
[regno
].write_count
;
6230 switch (write_count
)
6233 /* The register has not been written yet. */
6234 if (!in_safe_group_barrier
)
6235 rws_update (regno
, flags
, pred
);
6239 /* The register has been written via a predicate. Treat
6240 it like a unconditional write and do not try to check
6241 for complementary pred reg in earlier write. */
6242 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
6244 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
6248 if (!in_safe_group_barrier
)
6249 rws_update (regno
, flags
, pred
);
6253 /* The register has been unconditionally written already. We
6255 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
6257 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
6261 if (!in_safe_group_barrier
)
6263 rws_sum
[regno
].written_by_and
= flags
.is_and
;
6264 rws_sum
[regno
].written_by_or
= flags
.is_or
;
6274 if (flags
.is_branch
)
6276 /* Branches have several RAW exceptions that allow to avoid
6279 if (REGNO_REG_CLASS (regno
) == BR_REGS
|| regno
== AR_PFS_REGNUM
)
6280 /* RAW dependencies on branch regs are permissible as long
6281 as the writer is a non-branch instruction. Since we
6282 never generate code that uses a branch register written
6283 by a branch instruction, handling this case is
6287 if (REGNO_REG_CLASS (regno
) == PR_REGS
6288 && ! rws_sum
[regno
].written_by_fp
)
6289 /* The predicates of a branch are available within the
6290 same insn group as long as the predicate was written by
6291 something other than a floating-point instruction. */
6295 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
6297 if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
6300 switch (rws_sum
[regno
].write_count
)
6303 /* The register has not been written yet. */
6307 /* The register has been written via a predicate, assume we
6308 need a barrier (don't check for complementary regs). */
6313 /* The register has been unconditionally written already. We
6323 return need_barrier
;
6327 rws_access_reg (rtx reg
, struct reg_flags flags
, int pred
)
6329 int regno
= REGNO (reg
);
6330 int n
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
6333 return rws_access_regno (regno
, flags
, pred
);
6336 int need_barrier
= 0;
6338 need_barrier
|= rws_access_regno (regno
+ n
, flags
, pred
);
6339 return need_barrier
;
6343 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
6344 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
6347 update_set_flags (rtx x
, struct reg_flags
*pflags
)
6349 rtx src
= SET_SRC (x
);
6351 switch (GET_CODE (src
))
6357 /* There are four cases here:
6358 (1) The destination is (pc), in which case this is a branch,
6359 nothing here applies.
6360 (2) The destination is ar.lc, in which case this is a
6361 doloop_end_internal,
6362 (3) The destination is an fp register, in which case this is
6363 an fselect instruction.
6364 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
6365 this is a check load.
6366 In all cases, nothing we do in this function applies. */
6370 if (COMPARISON_P (src
)
6371 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src
, 0))))
6372 /* Set pflags->is_fp to 1 so that we know we're dealing
6373 with a floating point comparison when processing the
6374 destination of the SET. */
6377 /* Discover if this is a parallel comparison. We only handle
6378 and.orcm and or.andcm at present, since we must retain a
6379 strict inverse on the predicate pair. */
6380 else if (GET_CODE (src
) == AND
)
6382 else if (GET_CODE (src
) == IOR
)
6389 /* Subroutine of rtx_needs_barrier; this function determines whether the
6390 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
6391 are as in rtx_needs_barrier. COND is an rtx that holds the condition
6395 set_src_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
6397 int need_barrier
= 0;
6399 rtx src
= SET_SRC (x
);
6401 if (GET_CODE (src
) == CALL
)
6402 /* We don't need to worry about the result registers that
6403 get written by subroutine call. */
6404 return rtx_needs_barrier (src
, flags
, pred
);
6405 else if (SET_DEST (x
) == pc_rtx
)
6407 /* X is a conditional branch. */
6408 /* ??? This seems redundant, as the caller sets this bit for
6410 if (!ia64_spec_check_src_p (src
))
6411 flags
.is_branch
= 1;
6412 return rtx_needs_barrier (src
, flags
, pred
);
6415 if (ia64_spec_check_src_p (src
))
6416 /* Avoid checking one register twice (in condition
6417 and in 'then' section) for ldc pattern. */
6419 gcc_assert (REG_P (XEXP (src
, 2)));
6420 need_barrier
= rtx_needs_barrier (XEXP (src
, 2), flags
, pred
);
6422 /* We process MEM below. */
6423 src
= XEXP (src
, 1);
6426 need_barrier
|= rtx_needs_barrier (src
, flags
, pred
);
6429 if (GET_CODE (dst
) == ZERO_EXTRACT
)
6431 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 1), flags
, pred
);
6432 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 2), flags
, pred
);
6434 return need_barrier
;
6437 /* Handle an access to rtx X of type FLAGS using predicate register
6438 PRED. Return 1 if this access creates a dependency with an earlier
6439 instruction in the same group. */
6442 rtx_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
6445 int is_complemented
= 0;
6446 int need_barrier
= 0;
6447 const char *format_ptr
;
6448 struct reg_flags new_flags
;
6456 switch (GET_CODE (x
))
6459 update_set_flags (x
, &new_flags
);
6460 need_barrier
= set_src_needs_barrier (x
, new_flags
, pred
);
6461 if (GET_CODE (SET_SRC (x
)) != CALL
)
6463 new_flags
.is_write
= 1;
6464 need_barrier
|= rtx_needs_barrier (SET_DEST (x
), new_flags
, pred
);
6469 new_flags
.is_write
= 0;
6470 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
6472 /* Avoid multiple register writes, in case this is a pattern with
6473 multiple CALL rtx. This avoids a failure in rws_access_reg. */
6474 if (! flags
.is_sibcall
&& ! rws_insn_test (REG_AR_CFM
))
6476 new_flags
.is_write
= 1;
6477 need_barrier
|= rws_access_regno (REG_RP
, new_flags
, pred
);
6478 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, new_flags
, pred
);
6479 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6484 /* X is a predicated instruction. */
6486 cond
= COND_EXEC_TEST (x
);
6488 need_barrier
= rtx_needs_barrier (cond
, flags
, 0);
6490 if (GET_CODE (cond
) == EQ
)
6491 is_complemented
= 1;
6492 cond
= XEXP (cond
, 0);
6493 gcc_assert (GET_CODE (cond
) == REG
6494 && REGNO_REG_CLASS (REGNO (cond
)) == PR_REGS
);
6495 pred
= REGNO (cond
);
6496 if (is_complemented
)
6499 need_barrier
|= rtx_needs_barrier (COND_EXEC_CODE (x
), flags
, pred
);
6500 return need_barrier
;
6504 /* Clobber & use are for earlier compiler-phases only. */
6509 /* We always emit stop bits for traditional asms. We emit stop bits
6510 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
6511 if (GET_CODE (x
) != ASM_OPERANDS
6512 || (MEM_VOLATILE_P (x
) && TARGET_VOL_ASM_STOP
))
6514 /* Avoid writing the register multiple times if we have multiple
6515 asm outputs. This avoids a failure in rws_access_reg. */
6516 if (! rws_insn_test (REG_VOLATILE
))
6518 new_flags
.is_write
= 1;
6519 rws_access_regno (REG_VOLATILE
, new_flags
, pred
);
6524 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
6525 We cannot just fall through here since then we would be confused
6526 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6527 traditional asms unlike their normal usage. */
6529 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; --i
)
6530 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x
, i
), flags
, pred
))
6535 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
6537 rtx pat
= XVECEXP (x
, 0, i
);
6538 switch (GET_CODE (pat
))
6541 update_set_flags (pat
, &new_flags
);
6542 need_barrier
|= set_src_needs_barrier (pat
, new_flags
, pred
);
6548 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
6552 if (REG_P (XEXP (pat
, 0))
6553 && extract_asm_operands (x
) != NULL_RTX
6554 && REGNO (XEXP (pat
, 0)) != AR_UNAT_REGNUM
)
6556 new_flags
.is_write
= 1;
6557 need_barrier
|= rtx_needs_barrier (XEXP (pat
, 0),
6570 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
6572 rtx pat
= XVECEXP (x
, 0, i
);
6573 if (GET_CODE (pat
) == SET
)
6575 if (GET_CODE (SET_SRC (pat
)) != CALL
)
6577 new_flags
.is_write
= 1;
6578 need_barrier
|= rtx_needs_barrier (SET_DEST (pat
), new_flags
,
6582 else if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == RETURN
)
6583 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
6588 need_barrier
|= rtx_needs_barrier (SUBREG_REG (x
), flags
, pred
);
6591 if (REGNO (x
) == AR_UNAT_REGNUM
)
6593 for (i
= 0; i
< 64; ++i
)
6594 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ i
, flags
, pred
);
6597 need_barrier
= rws_access_reg (x
, flags
, pred
);
6601 /* Find the regs used in memory address computation. */
6602 new_flags
.is_write
= 0;
6603 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
6606 case CONST_INT
: case CONST_DOUBLE
: case CONST_VECTOR
:
6607 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
6610 /* Operators with side-effects. */
6611 case POST_INC
: case POST_DEC
:
6612 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
6614 new_flags
.is_write
= 0;
6615 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6616 new_flags
.is_write
= 1;
6617 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6621 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
6623 new_flags
.is_write
= 0;
6624 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6625 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
6626 new_flags
.is_write
= 1;
6627 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
6630 /* Handle common unary and binary ops for efficiency. */
6631 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
6632 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
6633 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
6634 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
6635 case NE
: case EQ
: case GE
: case GT
: case LE
:
6636 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
6637 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
6638 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
6641 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
6642 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
6643 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
6644 case SQRT
: case FFS
: case POPCOUNT
:
6645 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
6649 /* VEC_SELECT's second argument is a PARALLEL with integers that
6650 describe the elements selected. On ia64, those integers are
6651 always constants. Avoid walking the PARALLEL so that we don't
6652 get confused with "normal" parallels and then die. */
6653 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
6657 switch (XINT (x
, 1))
6659 case UNSPEC_LTOFF_DTPMOD
:
6660 case UNSPEC_LTOFF_DTPREL
:
6662 case UNSPEC_LTOFF_TPREL
:
6664 case UNSPEC_PRED_REL_MUTEX
:
6665 case UNSPEC_PIC_CALL
:
6667 case UNSPEC_FETCHADD_ACQ
:
6668 case UNSPEC_FETCHADD_REL
:
6669 case UNSPEC_BSP_VALUE
:
6670 case UNSPEC_FLUSHRS
:
6671 case UNSPEC_BUNDLE_SELECTOR
:
6674 case UNSPEC_GR_SPILL
:
6675 case UNSPEC_GR_RESTORE
:
6677 HOST_WIDE_INT offset
= INTVAL (XVECEXP (x
, 0, 1));
6678 HOST_WIDE_INT bit
= (offset
>> 3) & 63;
6680 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6681 new_flags
.is_write
= (XINT (x
, 1) == UNSPEC_GR_SPILL
);
6682 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ bit
,
6687 case UNSPEC_FR_SPILL
:
6688 case UNSPEC_FR_RESTORE
:
6689 case UNSPEC_GETF_EXP
:
6690 case UNSPEC_SETF_EXP
:
6692 case UNSPEC_FR_SQRT_RECIP_APPROX
:
6693 case UNSPEC_FR_SQRT_RECIP_APPROX_RES
:
6698 case UNSPEC_CHKACLR
:
6700 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6703 case UNSPEC_FR_RECIP_APPROX
:
6705 case UNSPEC_COPYSIGN
:
6706 case UNSPEC_FR_RECIP_APPROX_RES
:
6707 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6708 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
6711 case UNSPEC_CMPXCHG_ACQ
:
6712 case UNSPEC_CMPXCHG_REL
:
6713 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
6714 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 2), flags
, pred
);
6722 case UNSPEC_VOLATILE
:
6723 switch (XINT (x
, 1))
6726 /* Alloc must always be the first instruction of a group.
6727 We force this by always returning true. */
6728 /* ??? We might get better scheduling if we explicitly check for
6729 input/local/output register dependencies, and modify the
6730 scheduler so that alloc is always reordered to the start of
6731 the current group. We could then eliminate all of the
6732 first_instruction code. */
6733 rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
6735 new_flags
.is_write
= 1;
6736 rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6739 case UNSPECV_SET_BSP
:
6740 case UNSPECV_PROBE_STACK_RANGE
:
6744 case UNSPECV_BLOCKAGE
:
6745 case UNSPECV_INSN_GROUP_BARRIER
:
6747 case UNSPECV_PSAC_ALL
:
6748 case UNSPECV_PSAC_NORMAL
:
6751 case UNSPECV_PROBE_STACK_ADDRESS
:
6752 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
6761 new_flags
.is_write
= 0;
6762 need_barrier
= rws_access_regno (REG_RP
, flags
, pred
);
6763 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
6765 new_flags
.is_write
= 1;
6766 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
6767 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
6771 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
6772 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6773 switch (format_ptr
[i
])
6775 case '0': /* unused field */
6776 case 'i': /* integer */
6777 case 'n': /* note */
6778 case 'w': /* wide integer */
6779 case 's': /* pointer to string */
6780 case 'S': /* optional pointer to string */
6784 if (rtx_needs_barrier (XEXP (x
, i
), flags
, pred
))
6789 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
6790 if (rtx_needs_barrier (XVECEXP (x
, i
, j
), flags
, pred
))
6799 return need_barrier
;
6802 /* Clear out the state for group_barrier_needed at the start of a
6803 sequence of insns. */
6806 init_insn_group_barriers (void)
6808 memset (rws_sum
, 0, sizeof (rws_sum
));
6809 first_instruction
= 1;
6812 /* Given the current state, determine whether a group barrier (a stop bit) is
6813 necessary before INSN. Return nonzero if so. This modifies the state to
6814 include the effects of INSN as a side-effect. */
6817 group_barrier_needed (rtx insn
)
6820 int need_barrier
= 0;
6821 struct reg_flags flags
;
6823 memset (&flags
, 0, sizeof (flags
));
6824 switch (GET_CODE (insn
))
6831 /* A barrier doesn't imply an instruction group boundary. */
6835 memset (rws_insn
, 0, sizeof (rws_insn
));
6839 flags
.is_branch
= 1;
6840 flags
.is_sibcall
= SIBLING_CALL_P (insn
);
6841 memset (rws_insn
, 0, sizeof (rws_insn
));
6843 /* Don't bundle a call following another call. */
6844 if ((pat
= prev_active_insn (insn
)) && CALL_P (pat
))
6850 need_barrier
= rtx_needs_barrier (PATTERN (insn
), flags
, 0);
6854 if (!ia64_spec_check_p (insn
))
6855 flags
.is_branch
= 1;
6857 /* Don't bundle a jump following a call. */
6858 if ((pat
= prev_active_insn (insn
)) && CALL_P (pat
))
6866 if (GET_CODE (PATTERN (insn
)) == USE
6867 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6868 /* Don't care about USE and CLOBBER "insns"---those are used to
6869 indicate to the optimizer that it shouldn't get rid of
6870 certain operations. */
6873 pat
= PATTERN (insn
);
6875 /* Ug. Hack hacks hacked elsewhere. */
6876 switch (recog_memoized (insn
))
6878 /* We play dependency tricks with the epilogue in order
6879 to get proper schedules. Undo this for dv analysis. */
6880 case CODE_FOR_epilogue_deallocate_stack
:
6881 case CODE_FOR_prologue_allocate_stack
:
6882 pat
= XVECEXP (pat
, 0, 0);
6885 /* The pattern we use for br.cloop confuses the code above.
6886 The second element of the vector is representative. */
6887 case CODE_FOR_doloop_end_internal
:
6888 pat
= XVECEXP (pat
, 0, 1);
6891 /* Doesn't generate code. */
6892 case CODE_FOR_pred_rel_mutex
:
6893 case CODE_FOR_prologue_use
:
6900 memset (rws_insn
, 0, sizeof (rws_insn
));
6901 need_barrier
= rtx_needs_barrier (pat
, flags
, 0);
6903 /* Check to see if the previous instruction was a volatile
6906 need_barrier
= rws_access_regno (REG_VOLATILE
, flags
, 0);
6914 if (first_instruction
&& important_for_bundling_p (insn
))
6917 first_instruction
= 0;
6920 return need_barrier
;
6923 /* Like group_barrier_needed, but do not clobber the current state. */
6926 safe_group_barrier_needed (rtx insn
)
6928 int saved_first_instruction
;
6931 saved_first_instruction
= first_instruction
;
6932 in_safe_group_barrier
= 1;
6934 t
= group_barrier_needed (insn
);
6936 first_instruction
= saved_first_instruction
;
6937 in_safe_group_barrier
= 0;
6942 /* Scan the current function and insert stop bits as necessary to
6943 eliminate dependencies. This function assumes that a final
6944 instruction scheduling pass has been run which has already
6945 inserted most of the necessary stop bits. This function only
6946 inserts new ones at basic block boundaries, since these are
6947 invisible to the scheduler. */
6950 emit_insn_group_barriers (FILE *dump
)
6954 int insns_since_last_label
= 0;
6956 init_insn_group_barriers ();
6958 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6962 if (insns_since_last_label
)
6964 insns_since_last_label
= 0;
6966 else if (NOTE_P (insn
)
6967 && NOTE_KIND (insn
) == NOTE_INSN_BASIC_BLOCK
)
6969 if (insns_since_last_label
)
6971 insns_since_last_label
= 0;
6973 else if (NONJUMP_INSN_P (insn
)
6974 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
6975 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
6977 init_insn_group_barriers ();
6980 else if (NONDEBUG_INSN_P (insn
))
6982 insns_since_last_label
= 1;
6984 if (group_barrier_needed (insn
))
6989 fprintf (dump
, "Emitting stop before label %d\n",
6990 INSN_UID (last_label
));
6991 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label
);
6994 init_insn_group_barriers ();
7002 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
7003 This function has to emit all necessary group barriers. */
7006 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
7010 init_insn_group_barriers ();
7012 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7014 if (BARRIER_P (insn
))
7016 rtx last
= prev_active_insn (insn
);
7020 if (JUMP_TABLE_DATA_P (last
))
7021 last
= prev_active_insn (last
);
7022 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7023 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
7025 init_insn_group_barriers ();
7027 else if (NONDEBUG_INSN_P (insn
))
7029 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
7030 init_insn_group_barriers ();
7031 else if (group_barrier_needed (insn
))
7033 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
7034 init_insn_group_barriers ();
7035 group_barrier_needed (insn
);
7043 /* Instruction scheduling support. */
7045 #define NR_BUNDLES 10
7047 /* A list of names of all available bundles. */
7049 static const char *bundle_name
[NR_BUNDLES
] =
7055 #if NR_BUNDLES == 10
7065 /* Nonzero if we should insert stop bits into the schedule. */
7067 int ia64_final_schedule
= 0;
7069 /* Codes of the corresponding queried units: */
7071 static int _0mii_
, _0mmi_
, _0mfi_
, _0mmf_
;
7072 static int _0bbb_
, _0mbb_
, _0mib_
, _0mmb_
, _0mfb_
, _0mlx_
;
7074 static int _1mii_
, _1mmi_
, _1mfi_
, _1mmf_
;
7075 static int _1bbb_
, _1mbb_
, _1mib_
, _1mmb_
, _1mfb_
, _1mlx_
;
7077 static int pos_1
, pos_2
, pos_3
, pos_4
, pos_5
, pos_6
;
7079 /* The following variable value is an insn group barrier. */
7081 static rtx dfa_stop_insn
;
7083 /* The following variable value is the last issued insn. */
7085 static rtx last_scheduled_insn
;
7087 /* The following variable value is pointer to a DFA state used as
7088 temporary variable. */
7090 static state_t temp_dfa_state
= NULL
;
7092 /* The following variable value is DFA state after issuing the last
7095 static state_t prev_cycle_state
= NULL
;
7097 /* The following array element values are TRUE if the corresponding
7098 insn requires to add stop bits before it. */
7100 static char *stops_p
= NULL
;
7102 /* The following variable is used to set up the mentioned above array. */
7104 static int stop_before_p
= 0;
7106 /* The following variable value is length of the arrays `clocks' and
7109 static int clocks_length
;
7111 /* The following variable value is number of data speculations in progress. */
7112 static int pending_data_specs
= 0;
7114 /* Number of memory references on current and three future processor cycles. */
7115 static char mem_ops_in_group
[4];
7117 /* Number of current processor cycle (from scheduler's point of view). */
7118 static int current_cycle
;
7120 static rtx
ia64_single_set (rtx
);
7121 static void ia64_emit_insn_before (rtx
, rtx
);
7123 /* Map a bundle number to its pseudo-op. */
7126 get_bundle_name (int b
)
7128 return bundle_name
[b
];
7132 /* Return the maximum number of instructions a cpu can issue. */
7135 ia64_issue_rate (void)
7140 /* Helper function - like single_set, but look inside COND_EXEC. */
7143 ia64_single_set (rtx insn
)
7145 rtx x
= PATTERN (insn
), ret
;
7146 if (GET_CODE (x
) == COND_EXEC
)
7147 x
= COND_EXEC_CODE (x
);
7148 if (GET_CODE (x
) == SET
)
7151 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
7152 Although they are not classical single set, the second set is there just
7153 to protect it from moving past FP-relative stack accesses. */
7154 switch (recog_memoized (insn
))
7156 case CODE_FOR_prologue_allocate_stack
:
7157 case CODE_FOR_prologue_allocate_stack_pr
:
7158 case CODE_FOR_epilogue_deallocate_stack
:
7159 case CODE_FOR_epilogue_deallocate_stack_pr
:
7160 ret
= XVECEXP (x
, 0, 0);
7164 ret
= single_set_2 (insn
, x
);
7171 /* Adjust the cost of a scheduling dependency.
7172 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
7173 COST is the current cost, DW is dependency weakness. */
7175 ia64_adjust_cost_2 (rtx insn
, int dep_type1
, rtx dep_insn
, int cost
, dw_t dw
)
7177 enum reg_note dep_type
= (enum reg_note
) dep_type1
;
7178 enum attr_itanium_class dep_class
;
7179 enum attr_itanium_class insn_class
;
7181 insn_class
= ia64_safe_itanium_class (insn
);
7182 dep_class
= ia64_safe_itanium_class (dep_insn
);
7184 /* Treat true memory dependencies separately. Ignore apparent true
7185 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
7186 if (dep_type
== REG_DEP_TRUE
7187 && (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
)
7188 && (insn_class
== ITANIUM_CLASS_BR
|| insn_class
== ITANIUM_CLASS_SCALL
))
7191 if (dw
== MIN_DEP_WEAK
)
7192 /* Store and load are likely to alias, use higher cost to avoid stall. */
7193 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST
);
7194 else if (dw
> MIN_DEP_WEAK
)
7196 /* Store and load are less likely to alias. */
7197 if (mflag_sched_fp_mem_deps_zero_cost
&& dep_class
== ITANIUM_CLASS_STF
)
7198 /* Assume there will be no cache conflict for floating-point data.
7199 For integer data, L1 conflict penalty is huge (17 cycles), so we
7200 never assume it will not cause a conflict. */
7206 if (dep_type
!= REG_DEP_OUTPUT
)
7209 if (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
7210 || insn_class
== ITANIUM_CLASS_ST
|| insn_class
== ITANIUM_CLASS_STF
)
7216 /* Like emit_insn_before, but skip cycle_display notes.
7217 ??? When cycle display notes are implemented, update this. */
7220 ia64_emit_insn_before (rtx insn
, rtx before
)
7222 emit_insn_before (insn
, before
);
7225 /* The following function marks insns who produce addresses for load
7226 and store insns. Such insns will be placed into M slots because it
7227 decrease latency time for Itanium1 (see function
7228 `ia64_produce_address_p' and the DFA descriptions). */
7231 ia64_dependencies_evaluation_hook (rtx head
, rtx tail
)
7233 rtx insn
, next
, next_tail
;
7235 /* Before reload, which_alternative is not set, which means that
7236 ia64_safe_itanium_class will produce wrong results for (at least)
7237 move instructions. */
7238 if (!reload_completed
)
7241 next_tail
= NEXT_INSN (tail
);
7242 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
7245 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
7247 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IALU
)
7249 sd_iterator_def sd_it
;
7251 bool has_mem_op_consumer_p
= false;
7253 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
7255 enum attr_itanium_class c
;
7257 if (DEP_TYPE (dep
) != REG_DEP_TRUE
)
7260 next
= DEP_CON (dep
);
7261 c
= ia64_safe_itanium_class (next
);
7262 if ((c
== ITANIUM_CLASS_ST
7263 || c
== ITANIUM_CLASS_STF
)
7264 && ia64_st_address_bypass_p (insn
, next
))
7266 has_mem_op_consumer_p
= true;
7269 else if ((c
== ITANIUM_CLASS_LD
7270 || c
== ITANIUM_CLASS_FLD
7271 || c
== ITANIUM_CLASS_FLDP
)
7272 && ia64_ld_address_bypass_p (insn
, next
))
7274 has_mem_op_consumer_p
= true;
7279 insn
->call
= has_mem_op_consumer_p
;
7283 /* We're beginning a new block. Initialize data structures as necessary. */
7286 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
7287 int sched_verbose ATTRIBUTE_UNUSED
,
7288 int max_ready ATTRIBUTE_UNUSED
)
7290 #ifdef ENABLE_CHECKING
7293 if (!sel_sched_p () && reload_completed
)
7294 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
7295 insn
!= current_sched_info
->next_tail
;
7296 insn
= NEXT_INSN (insn
))
7297 gcc_assert (!SCHED_GROUP_P (insn
));
7299 last_scheduled_insn
= NULL_RTX
;
7300 init_insn_group_barriers ();
7303 memset (mem_ops_in_group
, 0, sizeof (mem_ops_in_group
));
7306 /* We're beginning a scheduling pass. Check assertion. */
7309 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED
,
7310 int sched_verbose ATTRIBUTE_UNUSED
,
7311 int max_ready ATTRIBUTE_UNUSED
)
7313 gcc_assert (pending_data_specs
== 0);
7316 /* Scheduling pass is now finished. Free/reset static variable. */
7318 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
7319 int sched_verbose ATTRIBUTE_UNUSED
)
7321 gcc_assert (pending_data_specs
== 0);
7324 /* Return TRUE if INSN is a load (either normal or speculative, but not a
7325 speculation check), FALSE otherwise. */
7327 is_load_p (rtx insn
)
7329 enum attr_itanium_class insn_class
= ia64_safe_itanium_class (insn
);
7332 ((insn_class
== ITANIUM_CLASS_LD
|| insn_class
== ITANIUM_CLASS_FLD
)
7333 && get_attr_check_load (insn
) == CHECK_LOAD_NO
);
7336 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
7337 (taking account for 3-cycle cache reference postponing for stores: Intel
7338 Itanium 2 Reference Manual for Software Development and Optimization,
7341 record_memory_reference (rtx insn
)
7343 enum attr_itanium_class insn_class
= ia64_safe_itanium_class (insn
);
7345 switch (insn_class
) {
7346 case ITANIUM_CLASS_FLD
:
7347 case ITANIUM_CLASS_LD
:
7348 mem_ops_in_group
[current_cycle
% 4]++;
7350 case ITANIUM_CLASS_STF
:
7351 case ITANIUM_CLASS_ST
:
7352 mem_ops_in_group
[(current_cycle
+ 3) % 4]++;
7358 /* We are about to being issuing insns for this clock cycle.
7359 Override the default sort algorithm to better slot instructions. */
7362 ia64_dfa_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
,
7363 int *pn_ready
, int clock_var
,
7367 int n_ready
= *pn_ready
;
7368 rtx
*e_ready
= ready
+ n_ready
;
7372 fprintf (dump
, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type
);
7374 if (reorder_type
== 0)
7376 /* First, move all USEs, CLOBBERs and other crud out of the way. */
7378 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
7379 if (insnp
< e_ready
)
7382 enum attr_type t
= ia64_safe_type (insn
);
7383 if (t
== TYPE_UNKNOWN
)
7385 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
7386 || asm_noperands (PATTERN (insn
)) >= 0)
7388 rtx lowest
= ready
[n_asms
];
7389 ready
[n_asms
] = insn
;
7395 rtx highest
= ready
[n_ready
- 1];
7396 ready
[n_ready
- 1] = insn
;
7403 if (n_asms
< n_ready
)
7405 /* Some normal insns to process. Skip the asms. */
7409 else if (n_ready
> 0)
7413 if (ia64_final_schedule
)
7416 int nr_need_stop
= 0;
7418 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
7419 if (safe_group_barrier_needed (*insnp
))
7422 if (reorder_type
== 1 && n_ready
== nr_need_stop
)
7424 if (reorder_type
== 0)
7427 /* Move down everything that needs a stop bit, preserving
7429 while (insnp
-- > ready
+ deleted
)
7430 while (insnp
>= ready
+ deleted
)
7433 if (! safe_group_barrier_needed (insn
))
7435 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
7443 current_cycle
= clock_var
;
7444 if (reload_completed
&& mem_ops_in_group
[clock_var
% 4] >= ia64_max_memory_insns
)
7449 /* Move down loads/stores, preserving relative order. */
7450 while (insnp
-- > ready
+ moved
)
7451 while (insnp
>= ready
+ moved
)
7454 if (! is_load_p (insn
))
7456 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
7467 /* We are about to being issuing insns for this clock cycle. Override
7468 the default sort algorithm to better slot instructions. */
7471 ia64_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
, int *pn_ready
,
7474 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
,
7475 pn_ready
, clock_var
, 0);
7478 /* Like ia64_sched_reorder, but called after issuing each insn.
7479 Override the default sort algorithm to better slot instructions. */
7482 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
7483 int sched_verbose ATTRIBUTE_UNUSED
, rtx
*ready
,
7484 int *pn_ready
, int clock_var
)
7486 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
7490 /* We are about to issue INSN. Return the number of insns left on the
7491 ready queue that can be issued this cycle. */
7494 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
7495 int sched_verbose ATTRIBUTE_UNUSED
,
7496 rtx insn ATTRIBUTE_UNUSED
,
7497 int can_issue_more ATTRIBUTE_UNUSED
)
7499 if (sched_deps_info
->generate_spec_deps
&& !sel_sched_p ())
7500 /* Modulo scheduling does not extend h_i_d when emitting
7501 new instructions. Don't use h_i_d, if we don't have to. */
7503 if (DONE_SPEC (insn
) & BEGIN_DATA
)
7504 pending_data_specs
++;
7505 if (CHECK_SPEC (insn
) & BEGIN_DATA
)
7506 pending_data_specs
--;
7509 if (DEBUG_INSN_P (insn
))
7512 last_scheduled_insn
= insn
;
7513 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
7514 if (reload_completed
)
7516 int needed
= group_barrier_needed (insn
);
7518 gcc_assert (!needed
);
7520 init_insn_group_barriers ();
7521 stops_p
[INSN_UID (insn
)] = stop_before_p
;
7524 record_memory_reference (insn
);
7529 /* We are choosing insn from the ready queue. Return zero if INSN
7533 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn
, int ready_index
)
7535 gcc_assert (insn
&& INSN_P (insn
));
7537 /* Size of ALAT is 32. As far as we perform conservative
7538 data speculation, we keep ALAT half-empty. */
7539 if (pending_data_specs
>= 16 && (TODO_SPEC (insn
) & BEGIN_DATA
))
7540 return ready_index
== 0 ? -1 : 1;
7542 if (ready_index
== 0)
7545 if ((!reload_completed
7546 || !safe_group_barrier_needed (insn
))
7547 && (!mflag_sched_mem_insns_hard_limit
7548 || !is_load_p (insn
)
7549 || mem_ops_in_group
[current_cycle
% 4] < ia64_max_memory_insns
))
7555 /* The following variable value is pseudo-insn used by the DFA insn
7556 scheduler to change the DFA state when the simulated clock is
7559 static rtx dfa_pre_cycle_insn
;
7561 /* Returns 1 when a meaningful insn was scheduled between the last group
7562 barrier and LAST. */
7564 scheduled_good_insn (rtx last
)
7566 if (last
&& recog_memoized (last
) >= 0)
7570 last
!= NULL
&& !NOTE_INSN_BASIC_BLOCK_P (last
)
7571 && !stops_p
[INSN_UID (last
)];
7572 last
= PREV_INSN (last
))
7573 /* We could hit a NOTE_INSN_DELETED here which is actually outside
7574 the ebb we're scheduling. */
7575 if (INSN_P (last
) && recog_memoized (last
) >= 0)
7581 /* We are about to being issuing INSN. Return nonzero if we cannot
7582 issue it on given cycle CLOCK and return zero if we should not sort
7583 the ready queue on the next clock start. */
7586 ia64_dfa_new_cycle (FILE *dump
, int verbose
, rtx insn
, int last_clock
,
7587 int clock
, int *sort_p
)
7589 gcc_assert (insn
&& INSN_P (insn
));
7591 if (DEBUG_INSN_P (insn
))
7594 /* When a group barrier is needed for insn, last_scheduled_insn
7596 gcc_assert (!(reload_completed
&& safe_group_barrier_needed (insn
))
7597 || last_scheduled_insn
);
7599 if ((reload_completed
7600 && (safe_group_barrier_needed (insn
)
7601 || (mflag_sched_stop_bits_after_every_cycle
7602 && last_clock
!= clock
7603 && last_scheduled_insn
7604 && scheduled_good_insn (last_scheduled_insn
))))
7605 || (last_scheduled_insn
7606 && (CALL_P (last_scheduled_insn
)
7607 || unknown_for_bundling_p (last_scheduled_insn
))))
7609 init_insn_group_barriers ();
7611 if (verbose
&& dump
)
7612 fprintf (dump
, "// Stop should be before %d%s\n", INSN_UID (insn
),
7613 last_clock
== clock
? " + cycle advance" : "");
7616 current_cycle
= clock
;
7617 mem_ops_in_group
[current_cycle
% 4] = 0;
7619 if (last_clock
== clock
)
7621 state_transition (curr_state
, dfa_stop_insn
);
7622 if (TARGET_EARLY_STOP_BITS
)
7623 *sort_p
= (last_scheduled_insn
== NULL_RTX
7624 || ! CALL_P (last_scheduled_insn
));
7630 if (last_scheduled_insn
)
7632 if (unknown_for_bundling_p (last_scheduled_insn
))
7633 state_reset (curr_state
);
7636 memcpy (curr_state
, prev_cycle_state
, dfa_state_size
);
7637 state_transition (curr_state
, dfa_stop_insn
);
7638 state_transition (curr_state
, dfa_pre_cycle_insn
);
7639 state_transition (curr_state
, NULL
);
7646 /* Implement targetm.sched.h_i_d_extended hook.
7647 Extend internal data structures. */
7649 ia64_h_i_d_extended (void)
7651 if (stops_p
!= NULL
)
7653 int new_clocks_length
= get_max_uid () * 3 / 2;
7654 stops_p
= (char *) xrecalloc (stops_p
, new_clocks_length
, clocks_length
, 1);
7655 clocks_length
= new_clocks_length
;
7660 /* This structure describes the data used by the backend to guide scheduling.
7661 When the current scheduling point is switched, this data should be saved
7662 and restored later, if the scheduler returns to this point. */
7663 struct _ia64_sched_context
7665 state_t prev_cycle_state
;
7666 rtx last_scheduled_insn
;
7667 struct reg_write_state rws_sum
[NUM_REGS
];
7668 struct reg_write_state rws_insn
[NUM_REGS
];
7669 int first_instruction
;
7670 int pending_data_specs
;
7672 char mem_ops_in_group
[4];
7674 typedef struct _ia64_sched_context
*ia64_sched_context_t
;
7676 /* Allocates a scheduling context. */
7678 ia64_alloc_sched_context (void)
7680 return xmalloc (sizeof (struct _ia64_sched_context
));
7683 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7684 the global context otherwise. */
7686 ia64_init_sched_context (void *_sc
, bool clean_p
)
7688 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7690 sc
->prev_cycle_state
= xmalloc (dfa_state_size
);
7693 state_reset (sc
->prev_cycle_state
);
7694 sc
->last_scheduled_insn
= NULL_RTX
;
7695 memset (sc
->rws_sum
, 0, sizeof (rws_sum
));
7696 memset (sc
->rws_insn
, 0, sizeof (rws_insn
));
7697 sc
->first_instruction
= 1;
7698 sc
->pending_data_specs
= 0;
7699 sc
->current_cycle
= 0;
7700 memset (sc
->mem_ops_in_group
, 0, sizeof (mem_ops_in_group
));
7704 memcpy (sc
->prev_cycle_state
, prev_cycle_state
, dfa_state_size
);
7705 sc
->last_scheduled_insn
= last_scheduled_insn
;
7706 memcpy (sc
->rws_sum
, rws_sum
, sizeof (rws_sum
));
7707 memcpy (sc
->rws_insn
, rws_insn
, sizeof (rws_insn
));
7708 sc
->first_instruction
= first_instruction
;
7709 sc
->pending_data_specs
= pending_data_specs
;
7710 sc
->current_cycle
= current_cycle
;
7711 memcpy (sc
->mem_ops_in_group
, mem_ops_in_group
, sizeof (mem_ops_in_group
));
7715 /* Sets the global scheduling context to the one pointed to by _SC. */
7717 ia64_set_sched_context (void *_sc
)
7719 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7721 gcc_assert (sc
!= NULL
);
7723 memcpy (prev_cycle_state
, sc
->prev_cycle_state
, dfa_state_size
);
7724 last_scheduled_insn
= sc
->last_scheduled_insn
;
7725 memcpy (rws_sum
, sc
->rws_sum
, sizeof (rws_sum
));
7726 memcpy (rws_insn
, sc
->rws_insn
, sizeof (rws_insn
));
7727 first_instruction
= sc
->first_instruction
;
7728 pending_data_specs
= sc
->pending_data_specs
;
7729 current_cycle
= sc
->current_cycle
;
7730 memcpy (mem_ops_in_group
, sc
->mem_ops_in_group
, sizeof (mem_ops_in_group
));
7733 /* Clears the data in the _SC scheduling context. */
7735 ia64_clear_sched_context (void *_sc
)
7737 ia64_sched_context_t sc
= (ia64_sched_context_t
) _sc
;
7739 free (sc
->prev_cycle_state
);
7740 sc
->prev_cycle_state
= NULL
;
7743 /* Frees the _SC scheduling context. */
7745 ia64_free_sched_context (void *_sc
)
7747 gcc_assert (_sc
!= NULL
);
7752 typedef rtx (* gen_func_t
) (rtx
, rtx
);
7754 /* Return a function that will generate a load of mode MODE_NO
7755 with speculation types TS. */
7757 get_spec_load_gen_function (ds_t ts
, int mode_no
)
7759 static gen_func_t gen_ld_
[] = {
7769 gen_zero_extendqidi2
,
7770 gen_zero_extendhidi2
,
7771 gen_zero_extendsidi2
,
7774 static gen_func_t gen_ld_a
[] = {
7784 gen_zero_extendqidi2_advanced
,
7785 gen_zero_extendhidi2_advanced
,
7786 gen_zero_extendsidi2_advanced
,
7788 static gen_func_t gen_ld_s
[] = {
7789 gen_movbi_speculative
,
7790 gen_movqi_speculative
,
7791 gen_movhi_speculative
,
7792 gen_movsi_speculative
,
7793 gen_movdi_speculative
,
7794 gen_movsf_speculative
,
7795 gen_movdf_speculative
,
7796 gen_movxf_speculative
,
7797 gen_movti_speculative
,
7798 gen_zero_extendqidi2_speculative
,
7799 gen_zero_extendhidi2_speculative
,
7800 gen_zero_extendsidi2_speculative
,
7802 static gen_func_t gen_ld_sa
[] = {
7803 gen_movbi_speculative_advanced
,
7804 gen_movqi_speculative_advanced
,
7805 gen_movhi_speculative_advanced
,
7806 gen_movsi_speculative_advanced
,
7807 gen_movdi_speculative_advanced
,
7808 gen_movsf_speculative_advanced
,
7809 gen_movdf_speculative_advanced
,
7810 gen_movxf_speculative_advanced
,
7811 gen_movti_speculative_advanced
,
7812 gen_zero_extendqidi2_speculative_advanced
,
7813 gen_zero_extendhidi2_speculative_advanced
,
7814 gen_zero_extendsidi2_speculative_advanced
,
7816 static gen_func_t gen_ld_s_a
[] = {
7817 gen_movbi_speculative_a
,
7818 gen_movqi_speculative_a
,
7819 gen_movhi_speculative_a
,
7820 gen_movsi_speculative_a
,
7821 gen_movdi_speculative_a
,
7822 gen_movsf_speculative_a
,
7823 gen_movdf_speculative_a
,
7824 gen_movxf_speculative_a
,
7825 gen_movti_speculative_a
,
7826 gen_zero_extendqidi2_speculative_a
,
7827 gen_zero_extendhidi2_speculative_a
,
7828 gen_zero_extendsidi2_speculative_a
,
7833 if (ts
& BEGIN_DATA
)
7835 if (ts
& BEGIN_CONTROL
)
7840 else if (ts
& BEGIN_CONTROL
)
7842 if ((spec_info
->flags
& SEL_SCHED_SPEC_DONT_CHECK_CONTROL
)
7843 || ia64_needs_block_p (ts
))
7846 gen_ld
= gen_ld_s_a
;
7853 return gen_ld
[mode_no
];
7856 /* Constants that help mapping 'enum machine_mode' to int. */
7859 SPEC_MODE_INVALID
= -1,
7860 SPEC_MODE_FIRST
= 0,
7861 SPEC_MODE_FOR_EXTEND_FIRST
= 1,
7862 SPEC_MODE_FOR_EXTEND_LAST
= 3,
7868 /* Offset to reach ZERO_EXTEND patterns. */
7869 SPEC_GEN_EXTEND_OFFSET
= SPEC_MODE_LAST
- SPEC_MODE_FOR_EXTEND_FIRST
+ 1
7872 /* Return index of the MODE. */
7874 ia64_mode_to_int (enum machine_mode mode
)
7878 case BImode
: return 0; /* SPEC_MODE_FIRST */
7879 case QImode
: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7880 case HImode
: return 2;
7881 case SImode
: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7882 case DImode
: return 4;
7883 case SFmode
: return 5;
7884 case DFmode
: return 6;
7885 case XFmode
: return 7;
7887 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7888 mentioned in itanium[12].md. Predicate fp_register_operand also
7889 needs to be defined. Bottom line: better disable for now. */
7890 return SPEC_MODE_INVALID
;
7891 default: return SPEC_MODE_INVALID
;
7895 /* Provide information about speculation capabilities. */
7897 ia64_set_sched_flags (spec_info_t spec_info
)
7899 unsigned int *flags
= &(current_sched_info
->flags
);
7901 if (*flags
& SCHED_RGN
7902 || *flags
& SCHED_EBB
7903 || *flags
& SEL_SCHED
)
7907 if ((mflag_sched_br_data_spec
&& !reload_completed
&& optimize
> 0)
7908 || (mflag_sched_ar_data_spec
&& reload_completed
))
7913 && ((mflag_sched_br_in_data_spec
&& !reload_completed
)
7914 || (mflag_sched_ar_in_data_spec
&& reload_completed
)))
7918 if (mflag_sched_control_spec
7920 || reload_completed
))
7922 mask
|= BEGIN_CONTROL
;
7924 if (!sel_sched_p () && mflag_sched_in_control_spec
)
7925 mask
|= BE_IN_CONTROL
;
7928 spec_info
->mask
= mask
;
7932 *flags
|= USE_DEPS_LIST
| DO_SPECULATION
;
7934 if (mask
& BE_IN_SPEC
)
7937 spec_info
->flags
= 0;
7939 if ((mask
& CONTROL_SPEC
)
7940 && sel_sched_p () && mflag_sel_sched_dont_check_control_spec
)
7941 spec_info
->flags
|= SEL_SCHED_SPEC_DONT_CHECK_CONTROL
;
7943 if (sched_verbose
>= 1)
7944 spec_info
->dump
= sched_dump
;
7946 spec_info
->dump
= 0;
7948 if (mflag_sched_count_spec_in_critical_path
)
7949 spec_info
->flags
|= COUNT_SPEC_IN_CRITICAL_PATH
;
7953 spec_info
->mask
= 0;
7956 /* If INSN is an appropriate load return its mode.
7957 Return -1 otherwise. */
7959 get_mode_no_for_insn (rtx insn
)
7961 rtx reg
, mem
, mode_rtx
;
7965 extract_insn_cached (insn
);
7967 /* We use WHICH_ALTERNATIVE only after reload. This will
7968 guarantee that reload won't touch a speculative insn. */
7970 if (recog_data
.n_operands
!= 2)
7973 reg
= recog_data
.operand
[0];
7974 mem
= recog_data
.operand
[1];
7976 /* We should use MEM's mode since REG's mode in presence of
7977 ZERO_EXTEND will always be DImode. */
7978 if (get_attr_speculable1 (insn
) == SPECULABLE1_YES
)
7979 /* Process non-speculative ld. */
7981 if (!reload_completed
)
7983 /* Do not speculate into regs like ar.lc. */
7984 if (!REG_P (reg
) || AR_REGNO_P (REGNO (reg
)))
7991 rtx mem_reg
= XEXP (mem
, 0);
7993 if (!REG_P (mem_reg
))
7999 else if (get_attr_speculable2 (insn
) == SPECULABLE2_YES
)
8001 gcc_assert (REG_P (reg
) && MEM_P (mem
));
8007 else if (get_attr_data_speculative (insn
) == DATA_SPECULATIVE_YES
8008 || get_attr_control_speculative (insn
) == CONTROL_SPECULATIVE_YES
8009 || get_attr_check_load (insn
) == CHECK_LOAD_YES
)
8010 /* Process speculative ld or ld.c. */
8012 gcc_assert (REG_P (reg
) && MEM_P (mem
));
8017 enum attr_itanium_class attr_class
= get_attr_itanium_class (insn
);
8019 if (attr_class
== ITANIUM_CLASS_CHK_A
8020 || attr_class
== ITANIUM_CLASS_CHK_S_I
8021 || attr_class
== ITANIUM_CLASS_CHK_S_F
)
8028 mode_no
= ia64_mode_to_int (GET_MODE (mode_rtx
));
8030 if (mode_no
== SPEC_MODE_INVALID
)
8033 extend_p
= (GET_MODE (reg
) != GET_MODE (mode_rtx
));
8037 if (!(SPEC_MODE_FOR_EXTEND_FIRST
<= mode_no
8038 && mode_no
<= SPEC_MODE_FOR_EXTEND_LAST
))
8041 mode_no
+= SPEC_GEN_EXTEND_OFFSET
;
8047 /* If X is an unspec part of a speculative load, return its code.
8048 Return -1 otherwise. */
8050 get_spec_unspec_code (const_rtx x
)
8052 if (GET_CODE (x
) != UNSPEC
)
8074 /* Implement skip_rtx_p hook. */
8076 ia64_skip_rtx_p (const_rtx x
)
8078 return get_spec_unspec_code (x
) != -1;
8081 /* If INSN is a speculative load, return its UNSPEC code.
8082 Return -1 otherwise. */
8084 get_insn_spec_code (const_rtx insn
)
8088 pat
= PATTERN (insn
);
8090 if (GET_CODE (pat
) == COND_EXEC
)
8091 pat
= COND_EXEC_CODE (pat
);
8093 if (GET_CODE (pat
) != SET
)
8096 reg
= SET_DEST (pat
);
8100 mem
= SET_SRC (pat
);
8101 if (GET_CODE (mem
) == ZERO_EXTEND
)
8102 mem
= XEXP (mem
, 0);
8104 return get_spec_unspec_code (mem
);
8107 /* If INSN is a speculative load, return a ds with the speculation types.
8108 Otherwise [if INSN is a normal instruction] return 0. */
8110 ia64_get_insn_spec_ds (rtx insn
)
8112 int code
= get_insn_spec_code (insn
);
8121 return BEGIN_CONTROL
;
8124 return BEGIN_DATA
| BEGIN_CONTROL
;
8131 /* If INSN is a speculative load return a ds with the speculation types that
8133 Otherwise [if INSN is a normal instruction] return 0. */
8135 ia64_get_insn_checked_ds (rtx insn
)
8137 int code
= get_insn_spec_code (insn
);
8142 return BEGIN_DATA
| BEGIN_CONTROL
;
8145 return BEGIN_CONTROL
;
8149 return BEGIN_DATA
| BEGIN_CONTROL
;
8156 /* If GEN_P is true, calculate the index of needed speculation check and return
8157 speculative pattern for INSN with speculative mode TS, machine mode
8158 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
8159 If GEN_P is false, just calculate the index of needed speculation check. */
8161 ia64_gen_spec_load (rtx insn
, ds_t ts
, int mode_no
)
8164 gen_func_t gen_load
;
8166 gen_load
= get_spec_load_gen_function (ts
, mode_no
);
8168 new_pat
= gen_load (copy_rtx (recog_data
.operand
[0]),
8169 copy_rtx (recog_data
.operand
[1]));
8171 pat
= PATTERN (insn
);
8172 if (GET_CODE (pat
) == COND_EXEC
)
8173 new_pat
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (COND_EXEC_TEST (pat
)),
8180 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED
,
8181 ds_t ds ATTRIBUTE_UNUSED
)
8186 /* Implement targetm.sched.speculate_insn hook.
8187 Check if the INSN can be TS speculative.
8188 If 'no' - return -1.
8189 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
8190 If current pattern of the INSN already provides TS speculation,
8193 ia64_speculate_insn (rtx insn
, ds_t ts
, rtx
*new_pat
)
8198 gcc_assert (!(ts
& ~SPECULATIVE
));
8200 if (ia64_spec_check_p (insn
))
8203 if ((ts
& BE_IN_SPEC
)
8204 && !insn_can_be_in_speculative_p (insn
, ts
))
8207 mode_no
= get_mode_no_for_insn (insn
);
8209 if (mode_no
!= SPEC_MODE_INVALID
)
8211 if (ia64_get_insn_spec_ds (insn
) == ds_get_speculation_types (ts
))
8216 *new_pat
= ia64_gen_spec_load (insn
, ts
, mode_no
);
8225 /* Return a function that will generate a check for speculation TS with mode
8227 If simple check is needed, pass true for SIMPLE_CHECK_P.
8228 If clearing check is needed, pass true for CLEARING_CHECK_P. */
8230 get_spec_check_gen_function (ds_t ts
, int mode_no
,
8231 bool simple_check_p
, bool clearing_check_p
)
8233 static gen_func_t gen_ld_c_clr
[] = {
8243 gen_zero_extendqidi2_clr
,
8244 gen_zero_extendhidi2_clr
,
8245 gen_zero_extendsidi2_clr
,
8247 static gen_func_t gen_ld_c_nc
[] = {
8257 gen_zero_extendqidi2_nc
,
8258 gen_zero_extendhidi2_nc
,
8259 gen_zero_extendsidi2_nc
,
8261 static gen_func_t gen_chk_a_clr
[] = {
8262 gen_advanced_load_check_clr_bi
,
8263 gen_advanced_load_check_clr_qi
,
8264 gen_advanced_load_check_clr_hi
,
8265 gen_advanced_load_check_clr_si
,
8266 gen_advanced_load_check_clr_di
,
8267 gen_advanced_load_check_clr_sf
,
8268 gen_advanced_load_check_clr_df
,
8269 gen_advanced_load_check_clr_xf
,
8270 gen_advanced_load_check_clr_ti
,
8271 gen_advanced_load_check_clr_di
,
8272 gen_advanced_load_check_clr_di
,
8273 gen_advanced_load_check_clr_di
,
8275 static gen_func_t gen_chk_a_nc
[] = {
8276 gen_advanced_load_check_nc_bi
,
8277 gen_advanced_load_check_nc_qi
,
8278 gen_advanced_load_check_nc_hi
,
8279 gen_advanced_load_check_nc_si
,
8280 gen_advanced_load_check_nc_di
,
8281 gen_advanced_load_check_nc_sf
,
8282 gen_advanced_load_check_nc_df
,
8283 gen_advanced_load_check_nc_xf
,
8284 gen_advanced_load_check_nc_ti
,
8285 gen_advanced_load_check_nc_di
,
8286 gen_advanced_load_check_nc_di
,
8287 gen_advanced_load_check_nc_di
,
8289 static gen_func_t gen_chk_s
[] = {
8290 gen_speculation_check_bi
,
8291 gen_speculation_check_qi
,
8292 gen_speculation_check_hi
,
8293 gen_speculation_check_si
,
8294 gen_speculation_check_di
,
8295 gen_speculation_check_sf
,
8296 gen_speculation_check_df
,
8297 gen_speculation_check_xf
,
8298 gen_speculation_check_ti
,
8299 gen_speculation_check_di
,
8300 gen_speculation_check_di
,
8301 gen_speculation_check_di
,
8304 gen_func_t
*gen_check
;
8306 if (ts
& BEGIN_DATA
)
8308 /* We don't need recovery because even if this is ld.sa
8309 ALAT entry will be allocated only if NAT bit is set to zero.
8310 So it is enough to use ld.c here. */
8314 gcc_assert (mflag_sched_spec_ldc
);
8316 if (clearing_check_p
)
8317 gen_check
= gen_ld_c_clr
;
8319 gen_check
= gen_ld_c_nc
;
8323 if (clearing_check_p
)
8324 gen_check
= gen_chk_a_clr
;
8326 gen_check
= gen_chk_a_nc
;
8329 else if (ts
& BEGIN_CONTROL
)
8332 /* We might want to use ld.sa -> ld.c instead of
8335 gcc_assert (!ia64_needs_block_p (ts
));
8337 if (clearing_check_p
)
8338 gen_check
= gen_ld_c_clr
;
8340 gen_check
= gen_ld_c_nc
;
8344 gen_check
= gen_chk_s
;
8350 gcc_assert (mode_no
>= 0);
8351 return gen_check
[mode_no
];
8354 /* Return nonzero, if INSN needs branchy recovery check. */
8356 ia64_needs_block_p (ds_t ts
)
8358 if (ts
& BEGIN_DATA
)
8359 return !mflag_sched_spec_ldc
;
8361 gcc_assert ((ts
& BEGIN_CONTROL
) != 0);
8363 return !(mflag_sched_spec_control_ldc
&& mflag_sched_spec_ldc
);
8366 /* Generate (or regenerate) a recovery check for INSN. */
8368 ia64_gen_spec_check (rtx insn
, rtx label
, ds_t ds
)
8370 rtx op1
, pat
, check_pat
;
8371 gen_func_t gen_check
;
8374 mode_no
= get_mode_no_for_insn (insn
);
8375 gcc_assert (mode_no
>= 0);
8381 gcc_assert (!ia64_needs_block_p (ds
));
8382 op1
= copy_rtx (recog_data
.operand
[1]);
8385 gen_check
= get_spec_check_gen_function (ds
, mode_no
, label
== NULL_RTX
,
8388 check_pat
= gen_check (copy_rtx (recog_data
.operand
[0]), op1
);
8390 pat
= PATTERN (insn
);
8391 if (GET_CODE (pat
) == COND_EXEC
)
8392 check_pat
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (COND_EXEC_TEST (pat
)),
8398 /* Return nonzero, if X is branchy recovery check. */
8400 ia64_spec_check_p (rtx x
)
8403 if (GET_CODE (x
) == COND_EXEC
)
8404 x
= COND_EXEC_CODE (x
);
8405 if (GET_CODE (x
) == SET
)
8406 return ia64_spec_check_src_p (SET_SRC (x
));
8410 /* Return nonzero, if SRC belongs to recovery check. */
8412 ia64_spec_check_src_p (rtx src
)
8414 if (GET_CODE (src
) == IF_THEN_ELSE
)
8419 if (GET_CODE (t
) == NE
)
8423 if (GET_CODE (t
) == UNSPEC
)
8429 if (code
== UNSPEC_LDCCLR
8430 || code
== UNSPEC_LDCNC
8431 || code
== UNSPEC_CHKACLR
8432 || code
== UNSPEC_CHKANC
8433 || code
== UNSPEC_CHKS
)
8435 gcc_assert (code
!= 0);
8445 /* The following page contains abstract data `bundle states' which are
8446 used for bundling insns (inserting nops and template generation). */
8448 /* The following describes state of insn bundling. */
8452 /* Unique bundle state number to identify them in the debugging
8455 rtx insn
; /* corresponding insn, NULL for the 1st and the last state */
8456 /* number nops before and after the insn */
8457 short before_nops_num
, after_nops_num
;
8458 int insn_num
; /* insn number (0 - for initial state, 1 - for the 1st
8460 int cost
; /* cost of the state in cycles */
8461 int accumulated_insns_num
; /* number of all previous insns including
8462 nops. L is considered as 2 insns */
8463 int branch_deviation
; /* deviation of previous branches from 3rd slots */
8464 int middle_bundle_stops
; /* number of stop bits in the middle of bundles */
8465 struct bundle_state
*next
; /* next state with the same insn_num */
8466 struct bundle_state
*originator
; /* originator (previous insn state) */
8467 /* All bundle states are in the following chain. */
8468 struct bundle_state
*allocated_states_chain
;
8469 /* The DFA State after issuing the insn and the nops. */
8473 /* The following is map insn number to the corresponding bundle state. */
8475 static struct bundle_state
**index_to_bundle_states
;
8477 /* The unique number of next bundle state. */
8479 static int bundle_states_num
;
8481 /* All allocated bundle states are in the following chain. */
8483 static struct bundle_state
*allocated_bundle_states_chain
;
8485 /* All allocated but not used bundle states are in the following
8488 static struct bundle_state
*free_bundle_state_chain
;
8491 /* The following function returns a free bundle state. */
8493 static struct bundle_state
*
8494 get_free_bundle_state (void)
8496 struct bundle_state
*result
;
8498 if (free_bundle_state_chain
!= NULL
)
8500 result
= free_bundle_state_chain
;
8501 free_bundle_state_chain
= result
->next
;
8505 result
= XNEW (struct bundle_state
);
8506 result
->dfa_state
= xmalloc (dfa_state_size
);
8507 result
->allocated_states_chain
= allocated_bundle_states_chain
;
8508 allocated_bundle_states_chain
= result
;
8510 result
->unique_num
= bundle_states_num
++;
8515 /* The following function frees given bundle state. */
8518 free_bundle_state (struct bundle_state
*state
)
8520 state
->next
= free_bundle_state_chain
;
8521 free_bundle_state_chain
= state
;
8524 /* Start work with abstract data `bundle states'. */
8527 initiate_bundle_states (void)
8529 bundle_states_num
= 0;
8530 free_bundle_state_chain
= NULL
;
8531 allocated_bundle_states_chain
= NULL
;
8534 /* Finish work with abstract data `bundle states'. */
8537 finish_bundle_states (void)
8539 struct bundle_state
*curr_state
, *next_state
;
8541 for (curr_state
= allocated_bundle_states_chain
;
8543 curr_state
= next_state
)
8545 next_state
= curr_state
->allocated_states_chain
;
8546 free (curr_state
->dfa_state
);
8551 /* Hashtable helpers. */
8553 struct bundle_state_hasher
: typed_noop_remove
<bundle_state
>
8555 typedef bundle_state value_type
;
8556 typedef bundle_state compare_type
;
8557 static inline hashval_t
hash (const value_type
*);
8558 static inline bool equal (const value_type
*, const compare_type
*);
8561 /* The function returns hash of BUNDLE_STATE. */
8564 bundle_state_hasher::hash (const value_type
*state
)
8568 for (result
= i
= 0; i
< dfa_state_size
; i
++)
8569 result
+= (((unsigned char *) state
->dfa_state
) [i
]
8570 << ((i
% CHAR_BIT
) * 3 + CHAR_BIT
));
8571 return result
+ state
->insn_num
;
8574 /* The function returns nonzero if the bundle state keys are equal. */
8577 bundle_state_hasher::equal (const value_type
*state1
,
8578 const compare_type
*state2
)
8580 return (state1
->insn_num
== state2
->insn_num
8581 && memcmp (state1
->dfa_state
, state2
->dfa_state
,
8582 dfa_state_size
) == 0);
8585 /* Hash table of the bundle states. The key is dfa_state and insn_num
8586 of the bundle states. */
8588 static hash_table
<bundle_state_hasher
> bundle_state_table
;
8590 /* The function inserts the BUNDLE_STATE into the hash table. The
8591 function returns nonzero if the bundle has been inserted into the
8592 table. The table contains the best bundle state with given key. */
8595 insert_bundle_state (struct bundle_state
*bundle_state
)
8597 struct bundle_state
**entry_ptr
;
8599 entry_ptr
= bundle_state_table
.find_slot (bundle_state
, INSERT
);
8600 if (*entry_ptr
== NULL
)
8602 bundle_state
->next
= index_to_bundle_states
[bundle_state
->insn_num
];
8603 index_to_bundle_states
[bundle_state
->insn_num
] = bundle_state
;
8604 *entry_ptr
= bundle_state
;
8607 else if (bundle_state
->cost
< (*entry_ptr
)->cost
8608 || (bundle_state
->cost
== (*entry_ptr
)->cost
8609 && ((*entry_ptr
)->accumulated_insns_num
8610 > bundle_state
->accumulated_insns_num
8611 || ((*entry_ptr
)->accumulated_insns_num
8612 == bundle_state
->accumulated_insns_num
8613 && ((*entry_ptr
)->branch_deviation
8614 > bundle_state
->branch_deviation
8615 || ((*entry_ptr
)->branch_deviation
8616 == bundle_state
->branch_deviation
8617 && (*entry_ptr
)->middle_bundle_stops
8618 > bundle_state
->middle_bundle_stops
))))))
8621 struct bundle_state temp
;
8624 **entry_ptr
= *bundle_state
;
8625 (*entry_ptr
)->next
= temp
.next
;
8626 *bundle_state
= temp
;
8631 /* Start work with the hash table. */
8634 initiate_bundle_state_table (void)
8636 bundle_state_table
.create (50);
8639 /* Finish work with the hash table. */
8642 finish_bundle_state_table (void)
8644 bundle_state_table
.dispose ();
8649 /* The following variable is a insn `nop' used to check bundle states
8650 with different number of inserted nops. */
8652 static rtx ia64_nop
;
8654 /* The following function tries to issue NOPS_NUM nops for the current
8655 state without advancing processor cycle. If it failed, the
8656 function returns FALSE and frees the current state. */
8659 try_issue_nops (struct bundle_state
*curr_state
, int nops_num
)
8663 for (i
= 0; i
< nops_num
; i
++)
8664 if (state_transition (curr_state
->dfa_state
, ia64_nop
) >= 0)
8666 free_bundle_state (curr_state
);
8672 /* The following function tries to issue INSN for the current
8673 state without advancing processor cycle. If it failed, the
8674 function returns FALSE and frees the current state. */
8677 try_issue_insn (struct bundle_state
*curr_state
, rtx insn
)
8679 if (insn
&& state_transition (curr_state
->dfa_state
, insn
) >= 0)
8681 free_bundle_state (curr_state
);
8687 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8688 starting with ORIGINATOR without advancing processor cycle. If
8689 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8690 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8691 If it was successful, the function creates new bundle state and
8692 insert into the hash table and into `index_to_bundle_states'. */
8695 issue_nops_and_insn (struct bundle_state
*originator
, int before_nops_num
,
8696 rtx insn
, int try_bundle_end_p
, int only_bundle_end_p
)
8698 struct bundle_state
*curr_state
;
8700 curr_state
= get_free_bundle_state ();
8701 memcpy (curr_state
->dfa_state
, originator
->dfa_state
, dfa_state_size
);
8702 curr_state
->insn
= insn
;
8703 curr_state
->insn_num
= originator
->insn_num
+ 1;
8704 curr_state
->cost
= originator
->cost
;
8705 curr_state
->originator
= originator
;
8706 curr_state
->before_nops_num
= before_nops_num
;
8707 curr_state
->after_nops_num
= 0;
8708 curr_state
->accumulated_insns_num
8709 = originator
->accumulated_insns_num
+ before_nops_num
;
8710 curr_state
->branch_deviation
= originator
->branch_deviation
;
8711 curr_state
->middle_bundle_stops
= originator
->middle_bundle_stops
;
8713 if (INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
)
8715 gcc_assert (GET_MODE (insn
) != TImode
);
8716 if (!try_issue_nops (curr_state
, before_nops_num
))
8718 if (!try_issue_insn (curr_state
, insn
))
8720 memcpy (temp_dfa_state
, curr_state
->dfa_state
, dfa_state_size
);
8721 if (curr_state
->accumulated_insns_num
% 3 != 0)
8722 curr_state
->middle_bundle_stops
++;
8723 if (state_transition (temp_dfa_state
, dfa_pre_cycle_insn
) >= 0
8724 && curr_state
->accumulated_insns_num
% 3 != 0)
8726 free_bundle_state (curr_state
);
8730 else if (GET_MODE (insn
) != TImode
)
8732 if (!try_issue_nops (curr_state
, before_nops_num
))
8734 if (!try_issue_insn (curr_state
, insn
))
8736 curr_state
->accumulated_insns_num
++;
8737 gcc_assert (!unknown_for_bundling_p (insn
));
8739 if (ia64_safe_type (insn
) == TYPE_L
)
8740 curr_state
->accumulated_insns_num
++;
8744 /* If this is an insn that must be first in a group, then don't allow
8745 nops to be emitted before it. Currently, alloc is the only such
8746 supported instruction. */
8747 /* ??? The bundling automatons should handle this for us, but they do
8748 not yet have support for the first_insn attribute. */
8749 if (before_nops_num
> 0 && get_attr_first_insn (insn
) == FIRST_INSN_YES
)
8751 free_bundle_state (curr_state
);
8755 state_transition (curr_state
->dfa_state
, dfa_pre_cycle_insn
);
8756 state_transition (curr_state
->dfa_state
, NULL
);
8758 if (!try_issue_nops (curr_state
, before_nops_num
))
8760 if (!try_issue_insn (curr_state
, insn
))
8762 curr_state
->accumulated_insns_num
++;
8763 if (unknown_for_bundling_p (insn
))
8765 /* Finish bundle containing asm insn. */
8766 curr_state
->after_nops_num
8767 = 3 - curr_state
->accumulated_insns_num
% 3;
8768 curr_state
->accumulated_insns_num
8769 += 3 - curr_state
->accumulated_insns_num
% 3;
8771 else if (ia64_safe_type (insn
) == TYPE_L
)
8772 curr_state
->accumulated_insns_num
++;
8774 if (ia64_safe_type (insn
) == TYPE_B
)
8775 curr_state
->branch_deviation
8776 += 2 - (curr_state
->accumulated_insns_num
- 1) % 3;
8777 if (try_bundle_end_p
&& curr_state
->accumulated_insns_num
% 3 != 0)
8779 if (!only_bundle_end_p
&& insert_bundle_state (curr_state
))
8782 struct bundle_state
*curr_state1
;
8783 struct bundle_state
*allocated_states_chain
;
8785 curr_state1
= get_free_bundle_state ();
8786 dfa_state
= curr_state1
->dfa_state
;
8787 allocated_states_chain
= curr_state1
->allocated_states_chain
;
8788 *curr_state1
= *curr_state
;
8789 curr_state1
->dfa_state
= dfa_state
;
8790 curr_state1
->allocated_states_chain
= allocated_states_chain
;
8791 memcpy (curr_state1
->dfa_state
, curr_state
->dfa_state
,
8793 curr_state
= curr_state1
;
8795 if (!try_issue_nops (curr_state
,
8796 3 - curr_state
->accumulated_insns_num
% 3))
8798 curr_state
->after_nops_num
8799 = 3 - curr_state
->accumulated_insns_num
% 3;
8800 curr_state
->accumulated_insns_num
8801 += 3 - curr_state
->accumulated_insns_num
% 3;
8803 if (!insert_bundle_state (curr_state
))
8804 free_bundle_state (curr_state
);
8808 /* The following function returns position in the two window bundle
8812 get_max_pos (state_t state
)
8814 if (cpu_unit_reservation_p (state
, pos_6
))
8816 else if (cpu_unit_reservation_p (state
, pos_5
))
8818 else if (cpu_unit_reservation_p (state
, pos_4
))
8820 else if (cpu_unit_reservation_p (state
, pos_3
))
8822 else if (cpu_unit_reservation_p (state
, pos_2
))
8824 else if (cpu_unit_reservation_p (state
, pos_1
))
8830 /* The function returns code of a possible template for given position
8831 and state. The function should be called only with 2 values of
8832 position equal to 3 or 6. We avoid generating F NOPs by putting
8833 templates containing F insns at the end of the template search
8834 because undocumented anomaly in McKinley derived cores which can
8835 cause stalls if an F-unit insn (including a NOP) is issued within a
8836 six-cycle window after reading certain application registers (such
8837 as ar.bsp). Furthermore, power-considerations also argue against
8838 the use of F-unit instructions unless they're really needed. */
8841 get_template (state_t state
, int pos
)
8846 if (cpu_unit_reservation_p (state
, _0mmi_
))
8848 else if (cpu_unit_reservation_p (state
, _0mii_
))
8850 else if (cpu_unit_reservation_p (state
, _0mmb_
))
8852 else if (cpu_unit_reservation_p (state
, _0mib_
))
8854 else if (cpu_unit_reservation_p (state
, _0mbb_
))
8856 else if (cpu_unit_reservation_p (state
, _0bbb_
))
8858 else if (cpu_unit_reservation_p (state
, _0mmf_
))
8860 else if (cpu_unit_reservation_p (state
, _0mfi_
))
8862 else if (cpu_unit_reservation_p (state
, _0mfb_
))
8864 else if (cpu_unit_reservation_p (state
, _0mlx_
))
8869 if (cpu_unit_reservation_p (state
, _1mmi_
))
8871 else if (cpu_unit_reservation_p (state
, _1mii_
))
8873 else if (cpu_unit_reservation_p (state
, _1mmb_
))
8875 else if (cpu_unit_reservation_p (state
, _1mib_
))
8877 else if (cpu_unit_reservation_p (state
, _1mbb_
))
8879 else if (cpu_unit_reservation_p (state
, _1bbb_
))
8881 else if (_1mmf_
>= 0 && cpu_unit_reservation_p (state
, _1mmf_
))
8883 else if (cpu_unit_reservation_p (state
, _1mfi_
))
8885 else if (cpu_unit_reservation_p (state
, _1mfb_
))
8887 else if (cpu_unit_reservation_p (state
, _1mlx_
))
8896 /* True when INSN is important for bundling. */
8899 important_for_bundling_p (rtx insn
)
8901 return (INSN_P (insn
)
8902 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
8903 && GET_CODE (PATTERN (insn
)) != USE
8904 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
8907 /* The following function returns an insn important for insn bundling
8908 followed by INSN and before TAIL. */
8911 get_next_important_insn (rtx insn
, rtx tail
)
8913 for (; insn
&& insn
!= tail
; insn
= NEXT_INSN (insn
))
8914 if (important_for_bundling_p (insn
))
8919 /* True when INSN is unknown, but important, for bundling. */
8922 unknown_for_bundling_p (rtx insn
)
8924 return (INSN_P (insn
)
8925 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_UNKNOWN
8926 && GET_CODE (PATTERN (insn
)) != USE
8927 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
8930 /* Add a bundle selector TEMPLATE0 before INSN. */
8933 ia64_add_bundle_selector_before (int template0
, rtx insn
)
8935 rtx b
= gen_bundle_selector (GEN_INT (template0
));
8937 ia64_emit_insn_before (b
, insn
);
8938 #if NR_BUNDLES == 10
8939 if ((template0
== 4 || template0
== 5)
8940 && ia64_except_unwind_info (&global_options
) == UI_TARGET
)
8943 rtx note
= NULL_RTX
;
8945 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8946 first or second slot. If it is and has REG_EH_NOTE set, copy it
8947 to following nops, as br.call sets rp to the address of following
8948 bundle and therefore an EH region end must be on a bundle
8950 insn
= PREV_INSN (insn
);
8951 for (i
= 0; i
< 3; i
++)
8954 insn
= next_active_insn (insn
);
8955 while (NONJUMP_INSN_P (insn
)
8956 && get_attr_empty (insn
) == EMPTY_YES
);
8958 note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
8963 gcc_assert ((code
= recog_memoized (insn
)) == CODE_FOR_nop
8964 || code
== CODE_FOR_nop_b
);
8965 if (find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
8968 add_reg_note (insn
, REG_EH_REGION
, XEXP (note
, 0));
8975 /* The following function does insn bundling. Bundling means
8976 inserting templates and nop insns to fit insn groups into permitted
8977 templates. Instruction scheduling uses NDFA (non-deterministic
8978 finite automata) encoding informations about the templates and the
8979 inserted nops. Nondeterminism of the automata permits follows
8980 all possible insn sequences very fast.
8982 Unfortunately it is not possible to get information about inserting
8983 nop insns and used templates from the automata states. The
8984 automata only says that we can issue an insn possibly inserting
8985 some nops before it and using some template. Therefore insn
8986 bundling in this function is implemented by using DFA
8987 (deterministic finite automata). We follow all possible insn
8988 sequences by inserting 0-2 nops (that is what the NDFA describe for
8989 insn scheduling) before/after each insn being bundled. We know the
8990 start of simulated processor cycle from insn scheduling (insn
8991 starting a new cycle has TImode).
8993 Simple implementation of insn bundling would create enormous
8994 number of possible insn sequences satisfying information about new
8995 cycle ticks taken from the insn scheduling. To make the algorithm
8996 practical we use dynamic programming. Each decision (about
8997 inserting nops and implicitly about previous decisions) is described
8998 by structure bundle_state (see above). If we generate the same
8999 bundle state (key is automaton state after issuing the insns and
9000 nops for it), we reuse already generated one. As consequence we
9001 reject some decisions which cannot improve the solution and
9002 reduce memory for the algorithm.
9004 When we reach the end of EBB (extended basic block), we choose the
9005 best sequence and then, moving back in EBB, insert templates for
9006 the best alternative. The templates are taken from querying
9007 automaton state for each insn in chosen bundle states.
9009 So the algorithm makes two (forward and backward) passes through
9013 bundling (FILE *dump
, int verbose
, rtx prev_head_insn
, rtx tail
)
9015 struct bundle_state
*curr_state
, *next_state
, *best_state
;
9016 rtx insn
, next_insn
;
9018 int i
, bundle_end_p
, only_bundle_end_p
, asm_p
;
9019 int pos
= 0, max_pos
, template0
, template1
;
9022 enum attr_type type
;
9025 /* Count insns in the EBB. */
9026 for (insn
= NEXT_INSN (prev_head_insn
);
9027 insn
&& insn
!= tail
;
9028 insn
= NEXT_INSN (insn
))
9034 dfa_clean_insn_cache ();
9035 initiate_bundle_state_table ();
9036 index_to_bundle_states
= XNEWVEC (struct bundle_state
*, insn_num
+ 2);
9037 /* First (forward) pass -- generation of bundle states. */
9038 curr_state
= get_free_bundle_state ();
9039 curr_state
->insn
= NULL
;
9040 curr_state
->before_nops_num
= 0;
9041 curr_state
->after_nops_num
= 0;
9042 curr_state
->insn_num
= 0;
9043 curr_state
->cost
= 0;
9044 curr_state
->accumulated_insns_num
= 0;
9045 curr_state
->branch_deviation
= 0;
9046 curr_state
->middle_bundle_stops
= 0;
9047 curr_state
->next
= NULL
;
9048 curr_state
->originator
= NULL
;
9049 state_reset (curr_state
->dfa_state
);
9050 index_to_bundle_states
[0] = curr_state
;
9052 /* Shift cycle mark if it is put on insn which could be ignored. */
9053 for (insn
= NEXT_INSN (prev_head_insn
);
9055 insn
= NEXT_INSN (insn
))
9057 && !important_for_bundling_p (insn
)
9058 && GET_MODE (insn
) == TImode
)
9060 PUT_MODE (insn
, VOIDmode
);
9061 for (next_insn
= NEXT_INSN (insn
);
9063 next_insn
= NEXT_INSN (next_insn
))
9064 if (important_for_bundling_p (next_insn
)
9065 && INSN_CODE (next_insn
) != CODE_FOR_insn_group_barrier
)
9067 PUT_MODE (next_insn
, TImode
);
9071 /* Forward pass: generation of bundle states. */
9072 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
9076 gcc_assert (important_for_bundling_p (insn
));
9077 type
= ia64_safe_type (insn
);
9078 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
9080 index_to_bundle_states
[insn_num
] = NULL
;
9081 for (curr_state
= index_to_bundle_states
[insn_num
- 1];
9083 curr_state
= next_state
)
9085 pos
= curr_state
->accumulated_insns_num
% 3;
9086 next_state
= curr_state
->next
;
9087 /* We must fill up the current bundle in order to start a
9088 subsequent asm insn in a new bundle. Asm insn is always
9089 placed in a separate bundle. */
9091 = (next_insn
!= NULL_RTX
9092 && INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
9093 && unknown_for_bundling_p (next_insn
));
9094 /* We may fill up the current bundle if it is the cycle end
9095 without a group barrier. */
9097 = (only_bundle_end_p
|| next_insn
== NULL_RTX
9098 || (GET_MODE (next_insn
) == TImode
9099 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
));
9100 if (type
== TYPE_F
|| type
== TYPE_B
|| type
== TYPE_L
9102 issue_nops_and_insn (curr_state
, 2, insn
, bundle_end_p
,
9104 issue_nops_and_insn (curr_state
, 1, insn
, bundle_end_p
,
9106 issue_nops_and_insn (curr_state
, 0, insn
, bundle_end_p
,
9109 gcc_assert (index_to_bundle_states
[insn_num
]);
9110 for (curr_state
= index_to_bundle_states
[insn_num
];
9112 curr_state
= curr_state
->next
)
9113 if (verbose
>= 2 && dump
)
9115 /* This structure is taken from generated code of the
9116 pipeline hazard recognizer (see file insn-attrtab.c).
9117 Please don't forget to change the structure if a new
9118 automaton is added to .md file. */
9121 unsigned short one_automaton_state
;
9122 unsigned short oneb_automaton_state
;
9123 unsigned short two_automaton_state
;
9124 unsigned short twob_automaton_state
;
9129 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
9130 curr_state
->unique_num
,
9131 (curr_state
->originator
== NULL
9132 ? -1 : curr_state
->originator
->unique_num
),
9134 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
9135 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
9136 curr_state
->middle_bundle_stops
,
9137 ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
,
9142 /* We should find a solution because the 2nd insn scheduling has
9144 gcc_assert (index_to_bundle_states
[insn_num
]);
9145 /* Find a state corresponding to the best insn sequence. */
9147 for (curr_state
= index_to_bundle_states
[insn_num
];
9149 curr_state
= curr_state
->next
)
9150 /* We are just looking at the states with fully filled up last
9151 bundle. The first we prefer insn sequences with minimal cost
9152 then with minimal inserted nops and finally with branch insns
9153 placed in the 3rd slots. */
9154 if (curr_state
->accumulated_insns_num
% 3 == 0
9155 && (best_state
== NULL
|| best_state
->cost
> curr_state
->cost
9156 || (best_state
->cost
== curr_state
->cost
9157 && (curr_state
->accumulated_insns_num
9158 < best_state
->accumulated_insns_num
9159 || (curr_state
->accumulated_insns_num
9160 == best_state
->accumulated_insns_num
9161 && (curr_state
->branch_deviation
9162 < best_state
->branch_deviation
9163 || (curr_state
->branch_deviation
9164 == best_state
->branch_deviation
9165 && curr_state
->middle_bundle_stops
9166 < best_state
->middle_bundle_stops
)))))))
9167 best_state
= curr_state
;
9168 /* Second (backward) pass: adding nops and templates. */
9169 gcc_assert (best_state
);
9170 insn_num
= best_state
->before_nops_num
;
9171 template0
= template1
= -1;
9172 for (curr_state
= best_state
;
9173 curr_state
->originator
!= NULL
;
9174 curr_state
= curr_state
->originator
)
9176 insn
= curr_state
->insn
;
9177 asm_p
= unknown_for_bundling_p (insn
);
9179 if (verbose
>= 2 && dump
)
9183 unsigned short one_automaton_state
;
9184 unsigned short oneb_automaton_state
;
9185 unsigned short two_automaton_state
;
9186 unsigned short twob_automaton_state
;
9191 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
9192 curr_state
->unique_num
,
9193 (curr_state
->originator
== NULL
9194 ? -1 : curr_state
->originator
->unique_num
),
9196 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
9197 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
9198 curr_state
->middle_bundle_stops
,
9199 ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
,
9202 /* Find the position in the current bundle window. The window can
9203 contain at most two bundles. Two bundle window means that
9204 the processor will make two bundle rotation. */
9205 max_pos
= get_max_pos (curr_state
->dfa_state
);
9207 /* The following (negative template number) means that the
9208 processor did one bundle rotation. */
9209 || (max_pos
== 3 && template0
< 0))
9211 /* We are at the end of the window -- find template(s) for
9215 template0
= get_template (curr_state
->dfa_state
, 3);
9218 template1
= get_template (curr_state
->dfa_state
, 3);
9219 template0
= get_template (curr_state
->dfa_state
, 6);
9222 if (max_pos
> 3 && template1
< 0)
9223 /* It may happen when we have the stop inside a bundle. */
9225 gcc_assert (pos
<= 3);
9226 template1
= get_template (curr_state
->dfa_state
, 3);
9230 /* Emit nops after the current insn. */
9231 for (i
= 0; i
< curr_state
->after_nops_num
; i
++)
9234 emit_insn_after (nop
, insn
);
9236 gcc_assert (pos
>= 0);
9239 /* We are at the start of a bundle: emit the template
9240 (it should be defined). */
9241 gcc_assert (template0
>= 0);
9242 ia64_add_bundle_selector_before (template0
, nop
);
9243 /* If we have two bundle window, we make one bundle
9244 rotation. Otherwise template0 will be undefined
9245 (negative value). */
9246 template0
= template1
;
9250 /* Move the position backward in the window. Group barrier has
9251 no slot. Asm insn takes all bundle. */
9252 if (INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
9253 && !unknown_for_bundling_p (insn
))
9255 /* Long insn takes 2 slots. */
9256 if (ia64_safe_type (insn
) == TYPE_L
)
9258 gcc_assert (pos
>= 0);
9260 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
9261 && !unknown_for_bundling_p (insn
))
9263 /* The current insn is at the bundle start: emit the
9265 gcc_assert (template0
>= 0);
9266 ia64_add_bundle_selector_before (template0
, insn
);
9267 b
= PREV_INSN (insn
);
9269 /* See comment above in analogous place for emitting nops
9271 template0
= template1
;
9274 /* Emit nops after the current insn. */
9275 for (i
= 0; i
< curr_state
->before_nops_num
; i
++)
9278 ia64_emit_insn_before (nop
, insn
);
9279 nop
= PREV_INSN (insn
);
9282 gcc_assert (pos
>= 0);
9285 /* See comment above in analogous place for emitting nops
9287 gcc_assert (template0
>= 0);
9288 ia64_add_bundle_selector_before (template0
, insn
);
9289 b
= PREV_INSN (insn
);
9291 template0
= template1
;
9297 #ifdef ENABLE_CHECKING
9299 /* Assert right calculation of middle_bundle_stops. */
9300 int num
= best_state
->middle_bundle_stops
;
9301 bool start_bundle
= true, end_bundle
= false;
9303 for (insn
= NEXT_INSN (prev_head_insn
);
9304 insn
&& insn
!= tail
;
9305 insn
= NEXT_INSN (insn
))
9309 if (recog_memoized (insn
) == CODE_FOR_bundle_selector
)
9310 start_bundle
= true;
9315 for (next_insn
= NEXT_INSN (insn
);
9316 next_insn
&& next_insn
!= tail
;
9317 next_insn
= NEXT_INSN (next_insn
))
9318 if (INSN_P (next_insn
)
9319 && (ia64_safe_itanium_class (next_insn
)
9320 != ITANIUM_CLASS_IGNORE
9321 || recog_memoized (next_insn
)
9322 == CODE_FOR_bundle_selector
)
9323 && GET_CODE (PATTERN (next_insn
)) != USE
9324 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
)
9327 end_bundle
= next_insn
== NULL_RTX
9328 || next_insn
== tail
9329 || (INSN_P (next_insn
)
9330 && recog_memoized (next_insn
)
9331 == CODE_FOR_bundle_selector
);
9332 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
9333 && !start_bundle
&& !end_bundle
9335 && !unknown_for_bundling_p (next_insn
))
9338 start_bundle
= false;
9342 gcc_assert (num
== 0);
9346 free (index_to_bundle_states
);
9347 finish_bundle_state_table ();
9349 dfa_clean_insn_cache ();
9352 /* The following function is called at the end of scheduling BB or
9353 EBB. After reload, it inserts stop bits and does insn bundling. */
9356 ia64_sched_finish (FILE *dump
, int sched_verbose
)
9359 fprintf (dump
, "// Finishing schedule.\n");
9360 if (!reload_completed
)
9362 if (reload_completed
)
9364 final_emit_insn_group_barriers (dump
);
9365 bundling (dump
, sched_verbose
, current_sched_info
->prev_head
,
9366 current_sched_info
->next_tail
);
9367 if (sched_verbose
&& dump
)
9368 fprintf (dump
, "// finishing %d-%d\n",
9369 INSN_UID (NEXT_INSN (current_sched_info
->prev_head
)),
9370 INSN_UID (PREV_INSN (current_sched_info
->next_tail
)));
9376 /* The following function inserts stop bits in scheduled BB or EBB. */
9379 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
9382 int need_barrier_p
= 0;
9383 int seen_good_insn
= 0;
9385 init_insn_group_barriers ();
9387 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
9388 insn
!= current_sched_info
->next_tail
;
9389 insn
= NEXT_INSN (insn
))
9391 if (BARRIER_P (insn
))
9393 rtx last
= prev_active_insn (insn
);
9397 if (JUMP_TABLE_DATA_P (last
))
9398 last
= prev_active_insn (last
);
9399 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
9400 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
9402 init_insn_group_barriers ();
9406 else if (NONDEBUG_INSN_P (insn
))
9408 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
9410 init_insn_group_barriers ();
9414 else if (need_barrier_p
|| group_barrier_needed (insn
)
9415 || (mflag_sched_stop_bits_after_every_cycle
9416 && GET_MODE (insn
) == TImode
9419 if (TARGET_EARLY_STOP_BITS
)
9424 last
!= current_sched_info
->prev_head
;
9425 last
= PREV_INSN (last
))
9426 if (INSN_P (last
) && GET_MODE (last
) == TImode
9427 && stops_p
[INSN_UID (last
)])
9429 if (last
== current_sched_info
->prev_head
)
9431 last
= prev_active_insn (last
);
9433 && recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
9434 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
9436 init_insn_group_barriers ();
9437 for (last
= NEXT_INSN (last
);
9439 last
= NEXT_INSN (last
))
9442 group_barrier_needed (last
);
9443 if (recog_memoized (last
) >= 0
9444 && important_for_bundling_p (last
))
9450 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
9452 init_insn_group_barriers ();
9455 group_barrier_needed (insn
);
9456 if (recog_memoized (insn
) >= 0
9457 && important_for_bundling_p (insn
))
9460 else if (recog_memoized (insn
) >= 0
9461 && important_for_bundling_p (insn
))
9463 need_barrier_p
= (CALL_P (insn
) || unknown_for_bundling_p (insn
));
9470 /* If the following function returns TRUE, we will use the DFA
9474 ia64_first_cycle_multipass_dfa_lookahead (void)
9476 return (reload_completed
? 6 : 4);
9479 /* The following function initiates variable `dfa_pre_cycle_insn'. */
9482 ia64_init_dfa_pre_cycle_insn (void)
9484 if (temp_dfa_state
== NULL
)
9486 dfa_state_size
= state_size ();
9487 temp_dfa_state
= xmalloc (dfa_state_size
);
9488 prev_cycle_state
= xmalloc (dfa_state_size
);
9490 dfa_pre_cycle_insn
= make_insn_raw (gen_pre_cycle ());
9491 PREV_INSN (dfa_pre_cycle_insn
) = NEXT_INSN (dfa_pre_cycle_insn
) = NULL_RTX
;
9492 recog_memoized (dfa_pre_cycle_insn
);
9493 dfa_stop_insn
= make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
9494 PREV_INSN (dfa_stop_insn
) = NEXT_INSN (dfa_stop_insn
) = NULL_RTX
;
9495 recog_memoized (dfa_stop_insn
);
9498 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
9499 used by the DFA insn scheduler. */
9502 ia64_dfa_pre_cycle_insn (void)
9504 return dfa_pre_cycle_insn
;
9507 /* The following function returns TRUE if PRODUCER (of type ilog or
9508 ld) produces address for CONSUMER (of type st or stf). */
9511 ia64_st_address_bypass_p (rtx producer
, rtx consumer
)
9515 gcc_assert (producer
&& consumer
);
9516 dest
= ia64_single_set (producer
);
9518 reg
= SET_DEST (dest
);
9520 if (GET_CODE (reg
) == SUBREG
)
9521 reg
= SUBREG_REG (reg
);
9522 gcc_assert (GET_CODE (reg
) == REG
);
9524 dest
= ia64_single_set (consumer
);
9526 mem
= SET_DEST (dest
);
9527 gcc_assert (mem
&& GET_CODE (mem
) == MEM
);
9528 return reg_mentioned_p (reg
, mem
);
9531 /* The following function returns TRUE if PRODUCER (of type ilog or
9532 ld) produces address for CONSUMER (of type ld or fld). */
9535 ia64_ld_address_bypass_p (rtx producer
, rtx consumer
)
9537 rtx dest
, src
, reg
, mem
;
9539 gcc_assert (producer
&& consumer
);
9540 dest
= ia64_single_set (producer
);
9542 reg
= SET_DEST (dest
);
9544 if (GET_CODE (reg
) == SUBREG
)
9545 reg
= SUBREG_REG (reg
);
9546 gcc_assert (GET_CODE (reg
) == REG
);
9548 src
= ia64_single_set (consumer
);
9550 mem
= SET_SRC (src
);
9553 if (GET_CODE (mem
) == UNSPEC
&& XVECLEN (mem
, 0) > 0)
9554 mem
= XVECEXP (mem
, 0, 0);
9555 else if (GET_CODE (mem
) == IF_THEN_ELSE
)
9556 /* ??? Is this bypass necessary for ld.c? */
9558 gcc_assert (XINT (XEXP (XEXP (mem
, 0), 0), 1) == UNSPEC_LDCCLR
);
9559 mem
= XEXP (mem
, 1);
9562 while (GET_CODE (mem
) == SUBREG
|| GET_CODE (mem
) == ZERO_EXTEND
)
9563 mem
= XEXP (mem
, 0);
9565 if (GET_CODE (mem
) == UNSPEC
)
9567 int c
= XINT (mem
, 1);
9569 gcc_assert (c
== UNSPEC_LDA
|| c
== UNSPEC_LDS
|| c
== UNSPEC_LDS_A
9570 || c
== UNSPEC_LDSA
);
9571 mem
= XVECEXP (mem
, 0, 0);
9574 /* Note that LO_SUM is used for GOT loads. */
9575 gcc_assert (GET_CODE (mem
) == LO_SUM
|| GET_CODE (mem
) == MEM
);
9577 return reg_mentioned_p (reg
, mem
);
9580 /* The following function returns TRUE if INSN produces address for a
9581 load/store insn. We will place such insns into M slot because it
9582 decreases its latency time. */
9585 ia64_produce_address_p (rtx insn
)
9591 /* Emit pseudo-ops for the assembler to describe predicate relations.
9592 At present this assumes that we only consider predicate pairs to
9593 be mutex, and that the assembler can deduce proper values from
9594 straight-line code. */
9597 emit_predicate_relation_info (void)
9601 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
9604 rtx head
= BB_HEAD (bb
);
9606 /* We only need such notes at code labels. */
9607 if (! LABEL_P (head
))
9609 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head
)))
9610 head
= NEXT_INSN (head
);
9612 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9613 grabbing the entire block of predicate registers. */
9614 for (r
= PR_REG (2); r
< PR_REG (64); r
+= 2)
9615 if (REGNO_REG_SET_P (df_get_live_in (bb
), r
))
9617 rtx p
= gen_rtx_REG (BImode
, r
);
9618 rtx n
= emit_insn_after (gen_pred_rel_mutex (p
), head
);
9619 if (head
== BB_END (bb
))
9625 /* Look for conditional calls that do not return, and protect predicate
9626 relations around them. Otherwise the assembler will assume the call
9627 returns, and complain about uses of call-clobbered predicates after
9629 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
9631 rtx insn
= BB_HEAD (bb
);
9636 && GET_CODE (PATTERN (insn
)) == COND_EXEC
9637 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
9639 rtx b
= emit_insn_before (gen_safe_across_calls_all (), insn
);
9640 rtx a
= emit_insn_after (gen_safe_across_calls_normal (), insn
);
9641 if (BB_HEAD (bb
) == insn
)
9643 if (BB_END (bb
) == insn
)
9647 if (insn
== BB_END (bb
))
9649 insn
= NEXT_INSN (insn
);
9654 /* Perform machine dependent operations on the rtl chain INSNS. */
9659 /* We are freeing block_for_insn in the toplev to keep compatibility
9660 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9661 compute_bb_for_insn ();
9663 /* If optimizing, we'll have split before scheduling. */
9667 if (optimize
&& flag_schedule_insns_after_reload
9668 && dbg_cnt (ia64_sched2
))
9671 timevar_push (TV_SCHED2
);
9672 ia64_final_schedule
= 1;
9674 /* We can't let modulo-sched prevent us from scheduling any bbs,
9675 since we need the final schedule to produce bundle information. */
9676 FOR_EACH_BB_FN (bb
, cfun
)
9677 bb
->flags
&= ~BB_DISABLE_SCHEDULE
;
9679 initiate_bundle_states ();
9680 ia64_nop
= make_insn_raw (gen_nop ());
9681 PREV_INSN (ia64_nop
) = NEXT_INSN (ia64_nop
) = NULL_RTX
;
9682 recog_memoized (ia64_nop
);
9683 clocks_length
= get_max_uid () + 1;
9684 stops_p
= XCNEWVEC (char, clocks_length
);
9686 if (ia64_tune
== PROCESSOR_ITANIUM2
)
9688 pos_1
= get_cpu_unit_code ("2_1");
9689 pos_2
= get_cpu_unit_code ("2_2");
9690 pos_3
= get_cpu_unit_code ("2_3");
9691 pos_4
= get_cpu_unit_code ("2_4");
9692 pos_5
= get_cpu_unit_code ("2_5");
9693 pos_6
= get_cpu_unit_code ("2_6");
9694 _0mii_
= get_cpu_unit_code ("2b_0mii.");
9695 _0mmi_
= get_cpu_unit_code ("2b_0mmi.");
9696 _0mfi_
= get_cpu_unit_code ("2b_0mfi.");
9697 _0mmf_
= get_cpu_unit_code ("2b_0mmf.");
9698 _0bbb_
= get_cpu_unit_code ("2b_0bbb.");
9699 _0mbb_
= get_cpu_unit_code ("2b_0mbb.");
9700 _0mib_
= get_cpu_unit_code ("2b_0mib.");
9701 _0mmb_
= get_cpu_unit_code ("2b_0mmb.");
9702 _0mfb_
= get_cpu_unit_code ("2b_0mfb.");
9703 _0mlx_
= get_cpu_unit_code ("2b_0mlx.");
9704 _1mii_
= get_cpu_unit_code ("2b_1mii.");
9705 _1mmi_
= get_cpu_unit_code ("2b_1mmi.");
9706 _1mfi_
= get_cpu_unit_code ("2b_1mfi.");
9707 _1mmf_
= get_cpu_unit_code ("2b_1mmf.");
9708 _1bbb_
= get_cpu_unit_code ("2b_1bbb.");
9709 _1mbb_
= get_cpu_unit_code ("2b_1mbb.");
9710 _1mib_
= get_cpu_unit_code ("2b_1mib.");
9711 _1mmb_
= get_cpu_unit_code ("2b_1mmb.");
9712 _1mfb_
= get_cpu_unit_code ("2b_1mfb.");
9713 _1mlx_
= get_cpu_unit_code ("2b_1mlx.");
9717 pos_1
= get_cpu_unit_code ("1_1");
9718 pos_2
= get_cpu_unit_code ("1_2");
9719 pos_3
= get_cpu_unit_code ("1_3");
9720 pos_4
= get_cpu_unit_code ("1_4");
9721 pos_5
= get_cpu_unit_code ("1_5");
9722 pos_6
= get_cpu_unit_code ("1_6");
9723 _0mii_
= get_cpu_unit_code ("1b_0mii.");
9724 _0mmi_
= get_cpu_unit_code ("1b_0mmi.");
9725 _0mfi_
= get_cpu_unit_code ("1b_0mfi.");
9726 _0mmf_
= get_cpu_unit_code ("1b_0mmf.");
9727 _0bbb_
= get_cpu_unit_code ("1b_0bbb.");
9728 _0mbb_
= get_cpu_unit_code ("1b_0mbb.");
9729 _0mib_
= get_cpu_unit_code ("1b_0mib.");
9730 _0mmb_
= get_cpu_unit_code ("1b_0mmb.");
9731 _0mfb_
= get_cpu_unit_code ("1b_0mfb.");
9732 _0mlx_
= get_cpu_unit_code ("1b_0mlx.");
9733 _1mii_
= get_cpu_unit_code ("1b_1mii.");
9734 _1mmi_
= get_cpu_unit_code ("1b_1mmi.");
9735 _1mfi_
= get_cpu_unit_code ("1b_1mfi.");
9736 _1mmf_
= get_cpu_unit_code ("1b_1mmf.");
9737 _1bbb_
= get_cpu_unit_code ("1b_1bbb.");
9738 _1mbb_
= get_cpu_unit_code ("1b_1mbb.");
9739 _1mib_
= get_cpu_unit_code ("1b_1mib.");
9740 _1mmb_
= get_cpu_unit_code ("1b_1mmb.");
9741 _1mfb_
= get_cpu_unit_code ("1b_1mfb.");
9742 _1mlx_
= get_cpu_unit_code ("1b_1mlx.");
9745 if (flag_selective_scheduling2
9746 && !maybe_skip_selective_scheduling ())
9747 run_selective_scheduling ();
9751 /* Redo alignment computation, as it might gone wrong. */
9752 compute_alignments ();
9754 /* We cannot reuse this one because it has been corrupted by the
9756 finish_bundle_states ();
9759 emit_insn_group_barriers (dump_file
);
9761 ia64_final_schedule
= 0;
9762 timevar_pop (TV_SCHED2
);
9765 emit_all_insn_group_barriers (dump_file
);
9769 /* A call must not be the last instruction in a function, so that the
9770 return address is still within the function, so that unwinding works
9771 properly. Note that IA-64 differs from dwarf2 on this point. */
9772 if (ia64_except_unwind_info (&global_options
) == UI_TARGET
)
9777 insn
= get_last_insn ();
9778 if (! INSN_P (insn
))
9779 insn
= prev_active_insn (insn
);
9782 /* Skip over insns that expand to nothing. */
9783 while (NONJUMP_INSN_P (insn
)
9784 && get_attr_empty (insn
) == EMPTY_YES
)
9786 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
9787 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
9789 insn
= prev_active_insn (insn
);
9794 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9795 emit_insn (gen_break_f ());
9796 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9801 emit_predicate_relation_info ();
9803 if (flag_var_tracking
)
9805 timevar_push (TV_VAR_TRACKING
);
9806 variable_tracking_main ();
9807 timevar_pop (TV_VAR_TRACKING
);
9809 df_finish_pass (false);
9812 /* Return true if REGNO is used by the epilogue. */
9815 ia64_epilogue_uses (int regno
)
9820 /* With a call to a function in another module, we will write a new
9821 value to "gp". After returning from such a call, we need to make
9822 sure the function restores the original gp-value, even if the
9823 function itself does not use the gp anymore. */
9824 return !(TARGET_AUTO_PIC
|| TARGET_NO_PIC
);
9826 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9827 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9828 /* For functions defined with the syscall_linkage attribute, all
9829 input registers are marked as live at all function exits. This
9830 prevents the register allocator from using the input registers,
9831 which in turn makes it possible to restart a system call after
9832 an interrupt without having to save/restore the input registers.
9833 This also prevents kernel data from leaking to application code. */
9834 return lookup_attribute ("syscall_linkage",
9835 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))) != NULL
;
9838 /* Conditional return patterns can't represent the use of `b0' as
9839 the return address, so we force the value live this way. */
9843 /* Likewise for ar.pfs, which is used by br.ret. */
9851 /* Return true if REGNO is used by the frame unwinder. */
9854 ia64_eh_uses (int regno
)
9858 if (! reload_completed
)
9864 for (r
= reg_save_b0
; r
<= reg_save_ar_lc
; r
++)
9865 if (regno
== current_frame_info
.r
[r
]
9866 || regno
== emitted_frame_related_regs
[r
])
9872 /* Return true if this goes in small data/bss. */
9874 /* ??? We could also support own long data here. Generating movl/add/ld8
9875 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9876 code faster because there is one less load. This also includes incomplete
9877 types which can't go in sdata/sbss. */
9880 ia64_in_small_data_p (const_tree exp
)
9882 if (TARGET_NO_SDATA
)
9885 /* We want to merge strings, so we never consider them small data. */
9886 if (TREE_CODE (exp
) == STRING_CST
)
9889 /* Functions are never small data. */
9890 if (TREE_CODE (exp
) == FUNCTION_DECL
)
9893 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
9895 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
9897 if (strcmp (section
, ".sdata") == 0
9898 || strncmp (section
, ".sdata.", 7) == 0
9899 || strncmp (section
, ".gnu.linkonce.s.", 16) == 0
9900 || strcmp (section
, ".sbss") == 0
9901 || strncmp (section
, ".sbss.", 6) == 0
9902 || strncmp (section
, ".gnu.linkonce.sb.", 17) == 0)
9907 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
9909 /* If this is an incomplete type with size 0, then we can't put it
9910 in sdata because it might be too big when completed. */
9911 if (size
> 0 && size
<= ia64_section_threshold
)
9918 /* Output assembly directives for prologue regions. */
9920 /* The current basic block number. */
9922 static bool last_block
;
9924 /* True if we need a copy_state command at the start of the next block. */
9926 static bool need_copy_state
;
9928 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9929 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9932 /* The function emits unwind directives for the start of an epilogue. */
9935 process_epilogue (FILE *asm_out_file
, rtx insn ATTRIBUTE_UNUSED
,
9936 bool unwind
, bool frame ATTRIBUTE_UNUSED
)
9938 /* If this isn't the last block of the function, then we need to label the
9939 current state, and copy it back in at the start of the next block. */
9944 fprintf (asm_out_file
, "\t.label_state %d\n",
9945 ++cfun
->machine
->state_num
);
9946 need_copy_state
= true;
9950 fprintf (asm_out_file
, "\t.restore sp\n");
9953 /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */
9956 process_cfa_adjust_cfa (FILE *asm_out_file
, rtx pat
, rtx insn
,
9957 bool unwind
, bool frame
)
9959 rtx dest
= SET_DEST (pat
);
9960 rtx src
= SET_SRC (pat
);
9962 if (dest
== stack_pointer_rtx
)
9964 if (GET_CODE (src
) == PLUS
)
9966 rtx op0
= XEXP (src
, 0);
9967 rtx op1
= XEXP (src
, 1);
9969 gcc_assert (op0
== dest
&& GET_CODE (op1
) == CONST_INT
);
9971 if (INTVAL (op1
) < 0)
9973 gcc_assert (!frame_pointer_needed
);
9975 fprintf (asm_out_file
,
9976 "\t.fframe "HOST_WIDE_INT_PRINT_DEC
"\n",
9980 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
9984 gcc_assert (src
== hard_frame_pointer_rtx
);
9985 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
9988 else if (dest
== hard_frame_pointer_rtx
)
9990 gcc_assert (src
== stack_pointer_rtx
);
9991 gcc_assert (frame_pointer_needed
);
9994 fprintf (asm_out_file
, "\t.vframe r%d\n",
9995 ia64_dbx_register_number (REGNO (dest
)));
10001 /* This function processes a SET pattern for REG_CFA_REGISTER. */
10004 process_cfa_register (FILE *asm_out_file
, rtx pat
, bool unwind
)
10006 rtx dest
= SET_DEST (pat
);
10007 rtx src
= SET_SRC (pat
);
10008 int dest_regno
= REGNO (dest
);
10013 /* Saving return address pointer. */
10015 fprintf (asm_out_file
, "\t.save rp, r%d\n",
10016 ia64_dbx_register_number (dest_regno
));
10020 src_regno
= REGNO (src
);
10025 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_pr
]);
10027 fprintf (asm_out_file
, "\t.save pr, r%d\n",
10028 ia64_dbx_register_number (dest_regno
));
10031 case AR_UNAT_REGNUM
:
10032 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_ar_unat
]);
10034 fprintf (asm_out_file
, "\t.save ar.unat, r%d\n",
10035 ia64_dbx_register_number (dest_regno
));
10039 gcc_assert (dest_regno
== current_frame_info
.r
[reg_save_ar_lc
]);
10041 fprintf (asm_out_file
, "\t.save ar.lc, r%d\n",
10042 ia64_dbx_register_number (dest_regno
));
10046 /* Everything else should indicate being stored to memory. */
10047 gcc_unreachable ();
10051 /* This function processes a SET pattern for REG_CFA_OFFSET. */
10054 process_cfa_offset (FILE *asm_out_file
, rtx pat
, bool unwind
)
10056 rtx dest
= SET_DEST (pat
);
10057 rtx src
= SET_SRC (pat
);
10058 int src_regno
= REGNO (src
);
10059 const char *saveop
;
10063 gcc_assert (MEM_P (dest
));
10064 if (GET_CODE (XEXP (dest
, 0)) == REG
)
10066 base
= XEXP (dest
, 0);
10071 gcc_assert (GET_CODE (XEXP (dest
, 0)) == PLUS
10072 && GET_CODE (XEXP (XEXP (dest
, 0), 1)) == CONST_INT
);
10073 base
= XEXP (XEXP (dest
, 0), 0);
10074 off
= INTVAL (XEXP (XEXP (dest
, 0), 1));
10077 if (base
== hard_frame_pointer_rtx
)
10079 saveop
= ".savepsp";
10084 gcc_assert (base
== stack_pointer_rtx
);
10085 saveop
= ".savesp";
10088 src_regno
= REGNO (src
);
10092 gcc_assert (!current_frame_info
.r
[reg_save_b0
]);
10094 fprintf (asm_out_file
, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC
"\n",
10099 gcc_assert (!current_frame_info
.r
[reg_save_pr
]);
10101 fprintf (asm_out_file
, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC
"\n",
10106 gcc_assert (!current_frame_info
.r
[reg_save_ar_lc
]);
10108 fprintf (asm_out_file
, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC
"\n",
10112 case AR_PFS_REGNUM
:
10113 gcc_assert (!current_frame_info
.r
[reg_save_ar_pfs
]);
10115 fprintf (asm_out_file
, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC
"\n",
10119 case AR_UNAT_REGNUM
:
10120 gcc_assert (!current_frame_info
.r
[reg_save_ar_unat
]);
10122 fprintf (asm_out_file
, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC
"\n",
10131 fprintf (asm_out_file
, "\t.save.g 0x%x\n",
10132 1 << (src_regno
- GR_REG (4)));
10141 fprintf (asm_out_file
, "\t.save.b 0x%x\n",
10142 1 << (src_regno
- BR_REG (1)));
10150 fprintf (asm_out_file
, "\t.save.f 0x%x\n",
10151 1 << (src_regno
- FR_REG (2)));
10154 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
10155 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
10156 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
10157 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
10159 fprintf (asm_out_file
, "\t.save.gf 0x0, 0x%x\n",
10160 1 << (src_regno
- FR_REG (12)));
10164 /* ??? For some reason we mark other general registers, even those
10165 we can't represent in the unwind info. Ignore them. */
10170 /* This function looks at a single insn and emits any directives
10171 required to unwind this insn. */
10174 ia64_asm_unwind_emit (FILE *asm_out_file
, rtx insn
)
10176 bool unwind
= ia64_except_unwind_info (&global_options
) == UI_TARGET
;
10177 bool frame
= dwarf2out_do_frame ();
10181 if (!unwind
&& !frame
)
10184 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
10186 last_block
= NOTE_BASIC_BLOCK (insn
)->next_bb
10187 == EXIT_BLOCK_PTR_FOR_FN (cfun
);
10189 /* Restore unwind state from immediately before the epilogue. */
10190 if (need_copy_state
)
10194 fprintf (asm_out_file
, "\t.body\n");
10195 fprintf (asm_out_file
, "\t.copy_state %d\n",
10196 cfun
->machine
->state_num
);
10198 need_copy_state
= false;
10202 if (NOTE_P (insn
) || ! RTX_FRAME_RELATED_P (insn
))
10205 /* Look for the ALLOC insn. */
10206 if (INSN_CODE (insn
) == CODE_FOR_alloc
)
10208 rtx dest
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 0));
10209 int dest_regno
= REGNO (dest
);
10211 /* If this is the final destination for ar.pfs, then this must
10212 be the alloc in the prologue. */
10213 if (dest_regno
== current_frame_info
.r
[reg_save_ar_pfs
])
10216 fprintf (asm_out_file
, "\t.save ar.pfs, r%d\n",
10217 ia64_dbx_register_number (dest_regno
));
10221 /* This must be an alloc before a sibcall. We must drop the
10222 old frame info. The easiest way to drop the old frame
10223 info is to ensure we had a ".restore sp" directive
10224 followed by a new prologue. If the procedure doesn't
10225 have a memory-stack frame, we'll issue a dummy ".restore
10227 if (current_frame_info
.total_size
== 0 && !frame_pointer_needed
)
10228 /* if haven't done process_epilogue() yet, do it now */
10229 process_epilogue (asm_out_file
, insn
, unwind
, frame
);
10231 fprintf (asm_out_file
, "\t.prologue\n");
10236 handled_one
= false;
10237 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
10238 switch (REG_NOTE_KIND (note
))
10240 case REG_CFA_ADJUST_CFA
:
10241 pat
= XEXP (note
, 0);
10243 pat
= PATTERN (insn
);
10244 process_cfa_adjust_cfa (asm_out_file
, pat
, insn
, unwind
, frame
);
10245 handled_one
= true;
10248 case REG_CFA_OFFSET
:
10249 pat
= XEXP (note
, 0);
10251 pat
= PATTERN (insn
);
10252 process_cfa_offset (asm_out_file
, pat
, unwind
);
10253 handled_one
= true;
10256 case REG_CFA_REGISTER
:
10257 pat
= XEXP (note
, 0);
10259 pat
= PATTERN (insn
);
10260 process_cfa_register (asm_out_file
, pat
, unwind
);
10261 handled_one
= true;
10264 case REG_FRAME_RELATED_EXPR
:
10265 case REG_CFA_DEF_CFA
:
10266 case REG_CFA_EXPRESSION
:
10267 case REG_CFA_RESTORE
:
10268 case REG_CFA_SET_VDRAP
:
10269 /* Not used in the ia64 port. */
10270 gcc_unreachable ();
10273 /* Not a frame-related note. */
10277 /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the
10278 explicit action to take. No guessing required. */
10279 gcc_assert (handled_one
);
10282 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
10285 ia64_asm_emit_except_personality (rtx personality
)
10287 fputs ("\t.personality\t", asm_out_file
);
10288 output_addr_const (asm_out_file
, personality
);
10289 fputc ('\n', asm_out_file
);
10292 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
10295 ia64_asm_init_sections (void)
10297 exception_section
= get_unnamed_section (0, output_section_asm_op
,
10301 /* Implement TARGET_DEBUG_UNWIND_INFO. */
10303 static enum unwind_info_type
10304 ia64_debug_unwind_info (void)
10312 IA64_BUILTIN_COPYSIGNQ
,
10313 IA64_BUILTIN_FABSQ
,
10314 IA64_BUILTIN_FLUSHRS
,
10316 IA64_BUILTIN_HUGE_VALQ
,
10320 static GTY(()) tree ia64_builtins
[(int) IA64_BUILTIN_max
];
10323 ia64_init_builtins (void)
10329 /* The __fpreg type. */
10330 fpreg_type
= make_node (REAL_TYPE
);
10331 TYPE_PRECISION (fpreg_type
) = 82;
10332 layout_type (fpreg_type
);
10333 (*lang_hooks
.types
.register_builtin_type
) (fpreg_type
, "__fpreg");
10335 /* The __float80 type. */
10336 float80_type
= make_node (REAL_TYPE
);
10337 TYPE_PRECISION (float80_type
) = 80;
10338 layout_type (float80_type
);
10339 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
10341 /* The __float128 type. */
10345 tree float128_type
= make_node (REAL_TYPE
);
10347 TYPE_PRECISION (float128_type
) = 128;
10348 layout_type (float128_type
);
10349 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
10351 /* TFmode support builtins. */
10352 ftype
= build_function_type_list (float128_type
, NULL_TREE
);
10353 decl
= add_builtin_function ("__builtin_infq", ftype
,
10354 IA64_BUILTIN_INFQ
, BUILT_IN_MD
,
10356 ia64_builtins
[IA64_BUILTIN_INFQ
] = decl
;
10358 decl
= add_builtin_function ("__builtin_huge_valq", ftype
,
10359 IA64_BUILTIN_HUGE_VALQ
, BUILT_IN_MD
,
10361 ia64_builtins
[IA64_BUILTIN_HUGE_VALQ
] = decl
;
10363 ftype
= build_function_type_list (float128_type
,
10366 decl
= add_builtin_function ("__builtin_fabsq", ftype
,
10367 IA64_BUILTIN_FABSQ
, BUILT_IN_MD
,
10368 "__fabstf2", NULL_TREE
);
10369 TREE_READONLY (decl
) = 1;
10370 ia64_builtins
[IA64_BUILTIN_FABSQ
] = decl
;
10372 ftype
= build_function_type_list (float128_type
,
10376 decl
= add_builtin_function ("__builtin_copysignq", ftype
,
10377 IA64_BUILTIN_COPYSIGNQ
, BUILT_IN_MD
,
10378 "__copysigntf3", NULL_TREE
);
10379 TREE_READONLY (decl
) = 1;
10380 ia64_builtins
[IA64_BUILTIN_COPYSIGNQ
] = decl
;
10383 /* Under HPUX, this is a synonym for "long double". */
10384 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
10387 /* Fwrite on VMS is non-standard. */
10388 #if TARGET_ABI_OPEN_VMS
10389 vms_patch_builtins ();
10392 #define def_builtin(name, type, code) \
10393 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
10396 decl
= def_builtin ("__builtin_ia64_bsp",
10397 build_function_type_list (ptr_type_node
, NULL_TREE
),
10399 ia64_builtins
[IA64_BUILTIN_BSP
] = decl
;
10401 decl
= def_builtin ("__builtin_ia64_flushrs",
10402 build_function_type_list (void_type_node
, NULL_TREE
),
10403 IA64_BUILTIN_FLUSHRS
);
10404 ia64_builtins
[IA64_BUILTIN_FLUSHRS
] = decl
;
10410 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITE
)) != NULL_TREE
)
10411 set_user_assembler_name (decl
, "_Isfinite");
10412 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITEF
)) != NULL_TREE
)
10413 set_user_assembler_name (decl
, "_Isfinitef");
10414 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITEL
)) != NULL_TREE
)
10415 set_user_assembler_name (decl
, "_Isfinitef128");
10420 ia64_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10421 enum machine_mode mode ATTRIBUTE_UNUSED
,
10422 int ignore ATTRIBUTE_UNUSED
)
10424 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10425 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10429 case IA64_BUILTIN_BSP
:
10430 if (! target
|| ! register_operand (target
, DImode
))
10431 target
= gen_reg_rtx (DImode
);
10432 emit_insn (gen_bsp_value (target
));
10433 #ifdef POINTERS_EXTEND_UNSIGNED
10434 target
= convert_memory_address (ptr_mode
, target
);
10438 case IA64_BUILTIN_FLUSHRS
:
10439 emit_insn (gen_flushrs ());
10442 case IA64_BUILTIN_INFQ
:
10443 case IA64_BUILTIN_HUGE_VALQ
:
10445 enum machine_mode target_mode
= TYPE_MODE (TREE_TYPE (exp
));
10446 REAL_VALUE_TYPE inf
;
10450 tmp
= CONST_DOUBLE_FROM_REAL_VALUE (inf
, target_mode
);
10452 tmp
= validize_mem (force_const_mem (target_mode
, tmp
));
10455 target
= gen_reg_rtx (target_mode
);
10457 emit_move_insn (target
, tmp
);
10461 case IA64_BUILTIN_FABSQ
:
10462 case IA64_BUILTIN_COPYSIGNQ
:
10463 return expand_call (exp
, target
, ignore
);
10466 gcc_unreachable ();
10472 /* Return the ia64 builtin for CODE. */
10475 ia64_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
10477 if (code
>= IA64_BUILTIN_max
)
10478 return error_mark_node
;
10480 return ia64_builtins
[code
];
10483 /* For the HP-UX IA64 aggregate parameters are passed stored in the
10484 most significant bits of the stack slot. */
10487 ia64_hpux_function_arg_padding (enum machine_mode mode
, const_tree type
)
10489 /* Exception to normal case for structures/unions/etc. */
10491 if (type
&& AGGREGATE_TYPE_P (type
)
10492 && int_size_in_bytes (type
) < UNITS_PER_WORD
)
10495 /* Fall back to the default. */
10496 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
10499 /* Emit text to declare externally defined variables and functions, because
10500 the Intel assembler does not support undefined externals. */
10503 ia64_asm_output_external (FILE *file
, tree decl
, const char *name
)
10505 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
10506 set in order to avoid putting out names that are never really
10508 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
10510 /* maybe_assemble_visibility will return 1 if the assembler
10511 visibility directive is output. */
10512 int need_visibility
= ((*targetm
.binds_local_p
) (decl
)
10513 && maybe_assemble_visibility (decl
));
10515 /* GNU as does not need anything here, but the HP linker does
10516 need something for external functions. */
10517 if ((TARGET_HPUX_LD
|| !TARGET_GNU_AS
)
10518 && TREE_CODE (decl
) == FUNCTION_DECL
)
10519 (*targetm
.asm_out
.globalize_decl_name
) (file
, decl
);
10520 else if (need_visibility
&& !TARGET_GNU_AS
)
10521 (*targetm
.asm_out
.globalize_label
) (file
, name
);
10525 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
10526 modes of word_mode and larger. Rename the TFmode libfuncs using the
10527 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
10528 backward compatibility. */
10531 ia64_init_libfuncs (void)
10533 set_optab_libfunc (sdiv_optab
, SImode
, "__divsi3");
10534 set_optab_libfunc (udiv_optab
, SImode
, "__udivsi3");
10535 set_optab_libfunc (smod_optab
, SImode
, "__modsi3");
10536 set_optab_libfunc (umod_optab
, SImode
, "__umodsi3");
10538 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
10539 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
10540 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
10541 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
10542 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
10544 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
10545 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
10546 set_conv_libfunc (sext_optab
, TFmode
, XFmode
, "_U_Qfcnvff_f80_to_quad");
10547 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
10548 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
10549 set_conv_libfunc (trunc_optab
, XFmode
, TFmode
, "_U_Qfcnvff_quad_to_f80");
10551 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_U_Qfcnvfxt_quad_to_sgl");
10552 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_U_Qfcnvfxt_quad_to_dbl");
10553 set_conv_libfunc (sfix_optab
, TImode
, TFmode
, "_U_Qfcnvfxt_quad_to_quad");
10554 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_U_Qfcnvfxut_quad_to_sgl");
10555 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_U_Qfcnvfxut_quad_to_dbl");
10557 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_U_Qfcnvxf_sgl_to_quad");
10558 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_U_Qfcnvxf_dbl_to_quad");
10559 set_conv_libfunc (sfloat_optab
, TFmode
, TImode
, "_U_Qfcnvxf_quad_to_quad");
10560 /* HP-UX 11.23 libc does not have a function for unsigned
10561 SImode-to-TFmode conversion. */
10562 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_U_Qfcnvxuf_dbl_to_quad");
10565 /* Rename all the TFmode libfuncs using the HPUX conventions. */
10568 ia64_hpux_init_libfuncs (void)
10570 ia64_init_libfuncs ();
10572 /* The HP SI millicode division and mod functions expect DI arguments.
10573 By turning them off completely we avoid using both libgcc and the
10574 non-standard millicode routines and use the HP DI millicode routines
10577 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10578 set_optab_libfunc (udiv_optab
, SImode
, 0);
10579 set_optab_libfunc (smod_optab
, SImode
, 0);
10580 set_optab_libfunc (umod_optab
, SImode
, 0);
10582 set_optab_libfunc (sdiv_optab
, DImode
, "__milli_divI");
10583 set_optab_libfunc (udiv_optab
, DImode
, "__milli_divU");
10584 set_optab_libfunc (smod_optab
, DImode
, "__milli_remI");
10585 set_optab_libfunc (umod_optab
, DImode
, "__milli_remU");
10587 /* HP-UX libc has TF min/max/abs routines in it. */
10588 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qfmin");
10589 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
10590 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
10592 /* ia64_expand_compare uses this. */
10593 cmptf_libfunc
= init_one_libfunc ("_U_Qfcmp");
10595 /* These should never be used. */
10596 set_optab_libfunc (eq_optab
, TFmode
, 0);
10597 set_optab_libfunc (ne_optab
, TFmode
, 0);
10598 set_optab_libfunc (gt_optab
, TFmode
, 0);
10599 set_optab_libfunc (ge_optab
, TFmode
, 0);
10600 set_optab_libfunc (lt_optab
, TFmode
, 0);
10601 set_optab_libfunc (le_optab
, TFmode
, 0);
10604 /* Rename the division and modulus functions in VMS. */
10607 ia64_vms_init_libfuncs (void)
10609 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10610 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10611 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10612 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10613 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10614 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10615 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10616 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10617 abort_libfunc
= init_one_libfunc ("decc$abort");
10618 memcmp_libfunc
= init_one_libfunc ("decc$memcmp");
10619 #ifdef MEM_LIBFUNCS_INIT
10624 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10625 the HPUX conventions. */
10628 ia64_sysv4_init_libfuncs (void)
10630 ia64_init_libfuncs ();
10632 /* These functions are not part of the HPUX TFmode interface. We
10633 use them instead of _U_Qfcmp, which doesn't work the way we
10635 set_optab_libfunc (eq_optab
, TFmode
, "_U_Qfeq");
10636 set_optab_libfunc (ne_optab
, TFmode
, "_U_Qfne");
10637 set_optab_libfunc (gt_optab
, TFmode
, "_U_Qfgt");
10638 set_optab_libfunc (ge_optab
, TFmode
, "_U_Qfge");
10639 set_optab_libfunc (lt_optab
, TFmode
, "_U_Qflt");
10640 set_optab_libfunc (le_optab
, TFmode
, "_U_Qfle");
10642 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10643 glibc doesn't have them. */
10649 ia64_soft_fp_init_libfuncs (void)
10654 ia64_vms_valid_pointer_mode (enum machine_mode mode
)
10656 return (mode
== SImode
|| mode
== DImode
);
10659 /* For HPUX, it is illegal to have relocations in shared segments. */
10662 ia64_hpux_reloc_rw_mask (void)
10667 /* For others, relax this so that relocations to local data goes in
10668 read-only segments, but we still cannot allow global relocations
10669 in read-only segments. */
10672 ia64_reloc_rw_mask (void)
10674 return flag_pic
? 3 : 2;
10677 /* Return the section to use for X. The only special thing we do here
10678 is to honor small data. */
10681 ia64_select_rtx_section (enum machine_mode mode
, rtx x
,
10682 unsigned HOST_WIDE_INT align
)
10684 if (GET_MODE_SIZE (mode
) > 0
10685 && GET_MODE_SIZE (mode
) <= ia64_section_threshold
10686 && !TARGET_NO_SDATA
)
10687 return sdata_section
;
10689 return default_elf_select_rtx_section (mode
, x
, align
);
10692 static unsigned int
10693 ia64_section_type_flags (tree decl
, const char *name
, int reloc
)
10695 unsigned int flags
= 0;
10697 if (strcmp (name
, ".sdata") == 0
10698 || strncmp (name
, ".sdata.", 7) == 0
10699 || strncmp (name
, ".gnu.linkonce.s.", 16) == 0
10700 || strncmp (name
, ".sdata2.", 8) == 0
10701 || strncmp (name
, ".gnu.linkonce.s2.", 17) == 0
10702 || strcmp (name
, ".sbss") == 0
10703 || strncmp (name
, ".sbss.", 6) == 0
10704 || strncmp (name
, ".gnu.linkonce.sb.", 17) == 0)
10705 flags
= SECTION_SMALL
;
10707 flags
|= default_section_type_flags (decl
, name
, reloc
);
10711 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10712 structure type and that the address of that type should be passed
10713 in out0, rather than in r8. */
10716 ia64_struct_retval_addr_is_first_parm_p (tree fntype
)
10718 tree ret_type
= TREE_TYPE (fntype
);
10720 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10721 as the structure return address parameter, if the return value
10722 type has a non-trivial copy constructor or destructor. It is not
10723 clear if this same convention should be used for other
10724 programming languages. Until G++ 3.4, we incorrectly used r8 for
10725 these return values. */
10726 return (abi_version_at_least (2)
10728 && TYPE_MODE (ret_type
) == BLKmode
10729 && TREE_ADDRESSABLE (ret_type
)
10730 && strcmp (lang_hooks
.name
, "GNU C++") == 0);
10733 /* Output the assembler code for a thunk function. THUNK_DECL is the
10734 declaration for the thunk function itself, FUNCTION is the decl for
10735 the target function. DELTA is an immediate constant offset to be
10736 added to THIS. If VCALL_OFFSET is nonzero, the word at
10737 *(*this + vcall_offset) should be added to THIS. */
10740 ia64_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
10741 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10744 rtx this_rtx
, insn
, funexp
;
10745 unsigned int this_parmno
;
10746 unsigned int this_regno
;
10749 reload_completed
= 1;
10750 epilogue_completed
= 1;
10752 /* Set things up as ia64_expand_prologue might. */
10753 last_scratch_gr_reg
= 15;
10755 memset (¤t_frame_info
, 0, sizeof (current_frame_info
));
10756 current_frame_info
.spill_cfa_off
= -16;
10757 current_frame_info
.n_input_regs
= 1;
10758 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
10760 /* Mark the end of the (empty) prologue. */
10761 emit_note (NOTE_INSN_PROLOGUE_END
);
10763 /* Figure out whether "this" will be the first parameter (the
10764 typical case) or the second parameter (as happens when the
10765 virtual function returns certain class objects). */
10767 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk
))
10769 this_regno
= IN_REG (this_parmno
);
10770 if (!TARGET_REG_NAMES
)
10771 reg_names
[this_regno
] = ia64_reg_numbers
[this_parmno
];
10773 this_rtx
= gen_rtx_REG (Pmode
, this_regno
);
10775 /* Apply the constant offset, if required. */
10776 delta_rtx
= GEN_INT (delta
);
10779 rtx tmp
= gen_rtx_REG (ptr_mode
, this_regno
);
10780 REG_POINTER (tmp
) = 1;
10781 if (delta
&& satisfies_constraint_I (delta_rtx
))
10783 emit_insn (gen_ptr_extend_plus_imm (this_rtx
, tmp
, delta_rtx
));
10787 emit_insn (gen_ptr_extend (this_rtx
, tmp
));
10791 if (!satisfies_constraint_I (delta_rtx
))
10793 rtx tmp
= gen_rtx_REG (Pmode
, 2);
10794 emit_move_insn (tmp
, delta_rtx
);
10797 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, delta_rtx
));
10800 /* Apply the offset from the vtable, if required. */
10803 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
10804 rtx tmp
= gen_rtx_REG (Pmode
, 2);
10808 rtx t
= gen_rtx_REG (ptr_mode
, 2);
10809 REG_POINTER (t
) = 1;
10810 emit_move_insn (t
, gen_rtx_MEM (ptr_mode
, this_rtx
));
10811 if (satisfies_constraint_I (vcall_offset_rtx
))
10813 emit_insn (gen_ptr_extend_plus_imm (tmp
, t
, vcall_offset_rtx
));
10817 emit_insn (gen_ptr_extend (tmp
, t
));
10820 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
10824 if (!satisfies_constraint_J (vcall_offset_rtx
))
10826 rtx tmp2
= gen_rtx_REG (Pmode
, next_scratch_gr_reg ());
10827 emit_move_insn (tmp2
, vcall_offset_rtx
);
10828 vcall_offset_rtx
= tmp2
;
10830 emit_insn (gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
10834 emit_insn (gen_zero_extendsidi2 (tmp
, gen_rtx_MEM (ptr_mode
, tmp
)));
10836 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
10838 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, tmp
));
10841 /* Generate a tail call to the target function. */
10842 if (! TREE_USED (function
))
10844 assemble_external (function
);
10845 TREE_USED (function
) = 1;
10847 funexp
= XEXP (DECL_RTL (function
), 0);
10848 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
10849 ia64_expand_call (NULL_RTX
, funexp
, NULL_RTX
, 1);
10850 insn
= get_last_insn ();
10851 SIBLING_CALL_P (insn
) = 1;
10853 /* Code generation for calls relies on splitting. */
10854 reload_completed
= 1;
10855 epilogue_completed
= 1;
10856 try_split (PATTERN (insn
), insn
, 0);
10860 /* Run just enough of rest_of_compilation to get the insns emitted.
10861 There's not really enough bulk here to make other passes such as
10862 instruction scheduling worth while. Note that use_thunk calls
10863 assemble_start_function and assemble_end_function. */
10865 emit_all_insn_group_barriers (NULL
);
10866 insn
= get_insns ();
10867 shorten_branches (insn
);
10868 final_start_function (insn
, file
, 1);
10869 final (insn
, file
, 1);
10870 final_end_function ();
10872 reload_completed
= 0;
10873 epilogue_completed
= 0;
10876 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10879 ia64_struct_value_rtx (tree fntype
,
10880 int incoming ATTRIBUTE_UNUSED
)
10882 if (TARGET_ABI_OPEN_VMS
||
10883 (fntype
&& ia64_struct_retval_addr_is_first_parm_p (fntype
)))
10885 return gen_rtx_REG (Pmode
, GR_REG (8));
10889 ia64_scalar_mode_supported_p (enum machine_mode mode
)
10915 ia64_vector_mode_supported_p (enum machine_mode mode
)
10932 /* Implement the FUNCTION_PROFILER macro. */
10935 ia64_output_function_profiler (FILE *file
, int labelno
)
10937 bool indirect_call
;
10939 /* If the function needs a static chain and the static chain
10940 register is r15, we use an indirect call so as to bypass
10941 the PLT stub in case the executable is dynamically linked,
10942 because the stub clobbers r15 as per 5.3.6 of the psABI.
10943 We don't need to do that in non canonical PIC mode. */
10945 if (cfun
->static_chain_decl
&& !TARGET_NO_PIC
&& !TARGET_AUTO_PIC
)
10947 gcc_assert (STATIC_CHAIN_REGNUM
== 15);
10948 indirect_call
= true;
10951 indirect_call
= false;
10954 fputs ("\t.prologue 4, r40\n", file
);
10956 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file
);
10957 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file
);
10959 if (NO_PROFILE_COUNTERS
)
10960 fputs ("\tmov out3 = r0\n", file
);
10964 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10966 if (TARGET_AUTO_PIC
)
10967 fputs ("\tmovl out3 = @gprel(", file
);
10969 fputs ("\taddl out3 = @ltoff(", file
);
10970 assemble_name (file
, buf
);
10971 if (TARGET_AUTO_PIC
)
10972 fputs (")\n", file
);
10974 fputs ("), r1\n", file
);
10978 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file
);
10979 fputs ("\t;;\n", file
);
10981 fputs ("\t.save rp, r42\n", file
);
10982 fputs ("\tmov out2 = b0\n", file
);
10984 fputs ("\tld8 r14 = [r14]\n\t;;\n", file
);
10985 fputs ("\t.body\n", file
);
10986 fputs ("\tmov out1 = r1\n", file
);
10989 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file
);
10990 fputs ("\tmov b6 = r16\n", file
);
10991 fputs ("\tld8 r1 = [r14]\n", file
);
10992 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file
);
10995 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file
);
10998 static GTY(()) rtx mcount_func_rtx
;
11000 gen_mcount_func_rtx (void)
11002 if (!mcount_func_rtx
)
11003 mcount_func_rtx
= init_one_libfunc ("_mcount");
11004 return mcount_func_rtx
;
11008 ia64_profile_hook (int labelno
)
11012 if (NO_PROFILE_COUNTERS
)
11013 label
= const0_rtx
;
11017 const char *label_name
;
11018 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
11019 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
11020 label
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
11021 SYMBOL_REF_FLAGS (label
) = SYMBOL_FLAG_LOCAL
;
11023 ip
= gen_reg_rtx (Pmode
);
11024 emit_insn (gen_ip_value (ip
));
11025 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL
,
11027 gen_rtx_REG (Pmode
, BR_REG (0)), Pmode
,
11032 /* Return the mangling of TYPE if it is an extended fundamental type. */
11034 static const char *
11035 ia64_mangle_type (const_tree type
)
11037 type
= TYPE_MAIN_VARIANT (type
);
11039 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
11040 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
11043 /* On HP-UX, "long double" is mangled as "e" so __float128 is
11045 if (!TARGET_HPUX
&& TYPE_MODE (type
) == TFmode
)
11047 /* On HP-UX, "e" is not available as a mangling of __float80 so use
11048 an extended mangling. Elsewhere, "e" is available since long
11049 double is 80 bits. */
11050 if (TYPE_MODE (type
) == XFmode
)
11051 return TARGET_HPUX
? "u9__float80" : "e";
11052 if (TYPE_MODE (type
) == RFmode
)
11053 return "u7__fpreg";
11057 /* Return the diagnostic message string if conversion from FROMTYPE to
11058 TOTYPE is not allowed, NULL otherwise. */
11059 static const char *
11060 ia64_invalid_conversion (const_tree fromtype
, const_tree totype
)
11062 /* Reject nontrivial conversion to or from __fpreg. */
11063 if (TYPE_MODE (fromtype
) == RFmode
11064 && TYPE_MODE (totype
) != RFmode
11065 && TYPE_MODE (totype
) != VOIDmode
)
11066 return N_("invalid conversion from %<__fpreg%>");
11067 if (TYPE_MODE (totype
) == RFmode
11068 && TYPE_MODE (fromtype
) != RFmode
)
11069 return N_("invalid conversion to %<__fpreg%>");
11073 /* Return the diagnostic message string if the unary operation OP is
11074 not permitted on TYPE, NULL otherwise. */
11075 static const char *
11076 ia64_invalid_unary_op (int op
, const_tree type
)
11078 /* Reject operations on __fpreg other than unary + or &. */
11079 if (TYPE_MODE (type
) == RFmode
11080 && op
!= CONVERT_EXPR
11081 && op
!= ADDR_EXPR
)
11082 return N_("invalid operation on %<__fpreg%>");
11086 /* Return the diagnostic message string if the binary operation OP is
11087 not permitted on TYPE1 and TYPE2, NULL otherwise. */
11088 static const char *
11089 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED
, const_tree type1
, const_tree type2
)
11091 /* Reject operations on __fpreg. */
11092 if (TYPE_MODE (type1
) == RFmode
|| TYPE_MODE (type2
) == RFmode
)
11093 return N_("invalid operation on %<__fpreg%>");
11097 /* HP-UX version_id attribute.
11098 For object foo, if the version_id is set to 1234 put out an alias
11099 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
11100 other than an alias statement because it is an illegal symbol name. */
11103 ia64_handle_version_id_attribute (tree
*node ATTRIBUTE_UNUSED
,
11104 tree name ATTRIBUTE_UNUSED
,
11106 int flags ATTRIBUTE_UNUSED
,
11107 bool *no_add_attrs
)
11109 tree arg
= TREE_VALUE (args
);
11111 if (TREE_CODE (arg
) != STRING_CST
)
11113 error("version attribute is not a string");
11114 *no_add_attrs
= true;
11120 /* Target hook for c_mode_for_suffix. */
11122 static enum machine_mode
11123 ia64_c_mode_for_suffix (char suffix
)
11133 static GTY(()) rtx ia64_dconst_0_5_rtx
;
11136 ia64_dconst_0_5 (void)
11138 if (! ia64_dconst_0_5_rtx
)
11140 REAL_VALUE_TYPE rv
;
11141 real_from_string (&rv
, "0.5");
11142 ia64_dconst_0_5_rtx
= const_double_from_real_value (rv
, DFmode
);
11144 return ia64_dconst_0_5_rtx
;
11147 static GTY(()) rtx ia64_dconst_0_375_rtx
;
11150 ia64_dconst_0_375 (void)
11152 if (! ia64_dconst_0_375_rtx
)
11154 REAL_VALUE_TYPE rv
;
11155 real_from_string (&rv
, "0.375");
11156 ia64_dconst_0_375_rtx
= const_double_from_real_value (rv
, DFmode
);
11158 return ia64_dconst_0_375_rtx
;
11161 static enum machine_mode
11162 ia64_get_reg_raw_mode (int regno
)
11164 if (FR_REGNO_P (regno
))
11166 return default_get_reg_raw_mode(regno
);
11169 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. ??? Might not be needed
11173 ia64_member_type_forces_blk (const_tree
, enum machine_mode mode
)
11175 return TARGET_HPUX
&& mode
== TFmode
;
11178 /* Always default to .text section until HP-UX linker is fixed. */
11180 ATTRIBUTE_UNUSED
static section
*
11181 ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED
,
11182 enum node_frequency freq ATTRIBUTE_UNUSED
,
11183 bool startup ATTRIBUTE_UNUSED
,
11184 bool exit ATTRIBUTE_UNUSED
)
11189 /* Construct (set target (vec_select op0 (parallel perm))) and
11190 return true if that's a valid instruction in the active ISA. */
11193 expand_vselect (rtx target
, rtx op0
, const unsigned char *perm
, unsigned nelt
)
11195 rtx rperm
[MAX_VECT_LEN
], x
;
11198 for (i
= 0; i
< nelt
; ++i
)
11199 rperm
[i
] = GEN_INT (perm
[i
]);
11201 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
11202 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
11203 x
= gen_rtx_SET (VOIDmode
, target
, x
);
11206 if (recog_memoized (x
) < 0)
11214 /* Similar, but generate a vec_concat from op0 and op1 as well. */
11217 expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
11218 const unsigned char *perm
, unsigned nelt
)
11220 enum machine_mode v2mode
;
11223 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
11224 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
11225 return expand_vselect (target
, x
, perm
, nelt
);
11228 /* Try to expand a no-op permutation. */
11231 expand_vec_perm_identity (struct expand_vec_perm_d
*d
)
11233 unsigned i
, nelt
= d
->nelt
;
11235 for (i
= 0; i
< nelt
; ++i
)
11236 if (d
->perm
[i
] != i
)
11240 emit_move_insn (d
->target
, d
->op0
);
11245 /* Try to expand D via a shrp instruction. */
11248 expand_vec_perm_shrp (struct expand_vec_perm_d
*d
)
11250 unsigned i
, nelt
= d
->nelt
, shift
, mask
;
11253 /* ??? Don't force V2SFmode into the integer registers. */
11254 if (d
->vmode
== V2SFmode
)
11257 mask
= (d
->one_operand_p
? nelt
- 1 : 2 * nelt
- 1);
11259 shift
= d
->perm
[0];
11260 if (BYTES_BIG_ENDIAN
&& shift
> nelt
)
11263 for (i
= 1; i
< nelt
; ++i
)
11264 if (d
->perm
[i
] != ((shift
+ i
) & mask
))
11270 hi
= shift
< nelt
? d
->op1
: d
->op0
;
11271 lo
= shift
< nelt
? d
->op0
: d
->op1
;
11275 shift
*= GET_MODE_UNIT_SIZE (d
->vmode
) * BITS_PER_UNIT
;
11277 /* We've eliminated the shift 0 case via expand_vec_perm_identity. */
11278 gcc_assert (IN_RANGE (shift
, 1, 63));
11280 /* Recall that big-endian elements are numbered starting at the top of
11281 the register. Ideally we'd have a shift-left-pair. But since we
11282 don't, convert to a shift the other direction. */
11283 if (BYTES_BIG_ENDIAN
)
11284 shift
= 64 - shift
;
11286 tmp
= gen_reg_rtx (DImode
);
11287 hi
= gen_lowpart (DImode
, hi
);
11288 lo
= gen_lowpart (DImode
, lo
);
11289 emit_insn (gen_shrp (tmp
, hi
, lo
, GEN_INT (shift
)));
11291 emit_move_insn (d
->target
, gen_lowpart (d
->vmode
, tmp
));
11295 /* Try to instantiate D in a single instruction. */
11298 expand_vec_perm_1 (struct expand_vec_perm_d
*d
)
11300 unsigned i
, nelt
= d
->nelt
;
11301 unsigned char perm2
[MAX_VECT_LEN
];
11303 /* Try single-operand selections. */
11304 if (d
->one_operand_p
)
11306 if (expand_vec_perm_identity (d
))
11308 if (expand_vselect (d
->target
, d
->op0
, d
->perm
, nelt
))
11312 /* Try two operand selections. */
11313 if (expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, d
->perm
, nelt
))
11316 /* Recognize interleave style patterns with reversed operands. */
11317 if (!d
->one_operand_p
)
11319 for (i
= 0; i
< nelt
; ++i
)
11321 unsigned e
= d
->perm
[i
];
11329 if (expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
11333 if (expand_vec_perm_shrp (d
))
11336 /* ??? Look for deposit-like permutations where most of the result
11337 comes from one vector unchanged and the rest comes from a
11338 sequential hunk of the other vector. */
11343 /* Pattern match broadcast permutations. */
11346 expand_vec_perm_broadcast (struct expand_vec_perm_d
*d
)
11348 unsigned i
, elt
, nelt
= d
->nelt
;
11349 unsigned char perm2
[2];
11353 if (!d
->one_operand_p
)
11357 for (i
= 1; i
< nelt
; ++i
)
11358 if (d
->perm
[i
] != elt
)
11365 /* Implementable by interleave. */
11367 perm2
[1] = elt
+ 2;
11368 ok
= expand_vselect_vconcat (d
->target
, d
->op0
, d
->op0
, perm2
, 2);
11373 /* Implementable by extract + broadcast. */
11374 if (BYTES_BIG_ENDIAN
)
11376 elt
*= BITS_PER_UNIT
;
11377 temp
= gen_reg_rtx (DImode
);
11378 emit_insn (gen_extzv (temp
, gen_lowpart (DImode
, d
->op0
),
11379 GEN_INT (8), GEN_INT (elt
)));
11380 emit_insn (gen_mux1_brcst_qi (d
->target
, gen_lowpart (QImode
, temp
)));
11384 /* Should have been matched directly by vec_select. */
11386 gcc_unreachable ();
11392 /* A subroutine of ia64_expand_vec_perm_const_1. Try to simplify a
11393 two vector permutation into a single vector permutation by using
11394 an interleave operation to merge the vectors. */
11397 expand_vec_perm_interleave_2 (struct expand_vec_perm_d
*d
)
11399 struct expand_vec_perm_d dremap
, dfinal
;
11400 unsigned char remap
[2 * MAX_VECT_LEN
];
11401 unsigned contents
, i
, nelt
, nelt2
;
11402 unsigned h0
, h1
, h2
, h3
;
11406 if (d
->one_operand_p
)
11412 /* Examine from whence the elements come. */
11414 for (i
= 0; i
< nelt
; ++i
)
11415 contents
|= 1u << d
->perm
[i
];
11417 memset (remap
, 0xff, sizeof (remap
));
11420 h0
= (1u << nelt2
) - 1;
11423 h3
= h0
<< (nelt
+ nelt2
);
11425 if ((contents
& (h0
| h2
)) == contents
) /* punpck even halves */
11427 for (i
= 0; i
< nelt
; ++i
)
11429 unsigned which
= i
/ 2 + (i
& 1 ? nelt
: 0);
11431 dremap
.perm
[i
] = which
;
11434 else if ((contents
& (h1
| h3
)) == contents
) /* punpck odd halves */
11436 for (i
= 0; i
< nelt
; ++i
)
11438 unsigned which
= i
/ 2 + nelt2
+ (i
& 1 ? nelt
: 0);
11440 dremap
.perm
[i
] = which
;
11443 else if ((contents
& 0x5555) == contents
) /* mix even elements */
11445 for (i
= 0; i
< nelt
; ++i
)
11447 unsigned which
= (i
& ~1) + (i
& 1 ? nelt
: 0);
11449 dremap
.perm
[i
] = which
;
11452 else if ((contents
& 0xaaaa) == contents
) /* mix odd elements */
11454 for (i
= 0; i
< nelt
; ++i
)
11456 unsigned which
= (i
| 1) + (i
& 1 ? nelt
: 0);
11458 dremap
.perm
[i
] = which
;
11461 else if (floor_log2 (contents
) - ctz_hwi (contents
) < (int)nelt
) /* shrp */
11463 unsigned shift
= ctz_hwi (contents
);
11464 for (i
= 0; i
< nelt
; ++i
)
11466 unsigned which
= (i
+ shift
) & (2 * nelt
- 1);
11468 dremap
.perm
[i
] = which
;
11474 /* Use the remapping array set up above to move the elements from their
11475 swizzled locations into their final destinations. */
11477 for (i
= 0; i
< nelt
; ++i
)
11479 unsigned e
= remap
[d
->perm
[i
]];
11480 gcc_assert (e
< nelt
);
11481 dfinal
.perm
[i
] = e
;
11483 dfinal
.op0
= gen_reg_rtx (dfinal
.vmode
);
11484 dfinal
.op1
= dfinal
.op0
;
11485 dfinal
.one_operand_p
= true;
11486 dremap
.target
= dfinal
.op0
;
11488 /* Test if the final remap can be done with a single insn. For V4HImode
11489 this *will* succeed. For V8QImode or V2SImode it may not. */
11491 ok
= expand_vec_perm_1 (&dfinal
);
11492 seq
= get_insns ();
11499 ok
= expand_vec_perm_1 (&dremap
);
11506 /* A subroutine of ia64_expand_vec_perm_const_1. Emit a full V4HImode
11507 constant permutation via two mux2 and a merge. */
11510 expand_vec_perm_v4hi_5 (struct expand_vec_perm_d
*d
)
11512 unsigned char perm2
[4];
11515 rtx t0
, t1
, mask
, x
;
11518 if (d
->vmode
!= V4HImode
|| d
->one_operand_p
)
11523 for (i
= 0; i
< 4; ++i
)
11525 perm2
[i
] = d
->perm
[i
] & 3;
11526 rmask
[i
] = (d
->perm
[i
] & 4 ? const0_rtx
: constm1_rtx
);
11528 mask
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmask
));
11529 mask
= force_reg (V4HImode
, mask
);
11531 t0
= gen_reg_rtx (V4HImode
);
11532 t1
= gen_reg_rtx (V4HImode
);
11534 ok
= expand_vselect (t0
, d
->op0
, perm2
, 4);
11536 ok
= expand_vselect (t1
, d
->op1
, perm2
, 4);
11539 x
= gen_rtx_AND (V4HImode
, mask
, t0
);
11540 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
11542 x
= gen_rtx_NOT (V4HImode
, mask
);
11543 x
= gen_rtx_AND (V4HImode
, x
, t1
);
11544 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
11546 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
11547 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
11552 /* The guts of ia64_expand_vec_perm_const, also used by the ok hook.
11553 With all of the interface bits taken care of, perform the expansion
11554 in D and return true on success. */
11557 ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
11559 if (expand_vec_perm_1 (d
))
11561 if (expand_vec_perm_broadcast (d
))
11563 if (expand_vec_perm_interleave_2 (d
))
11565 if (expand_vec_perm_v4hi_5 (d
))
11571 ia64_expand_vec_perm_const (rtx operands
[4])
11573 struct expand_vec_perm_d d
;
11574 unsigned char perm
[MAX_VECT_LEN
];
11575 int i
, nelt
, which
;
11578 d
.target
= operands
[0];
11579 d
.op0
= operands
[1];
11580 d
.op1
= operands
[2];
11583 d
.vmode
= GET_MODE (d
.target
);
11584 gcc_assert (VECTOR_MODE_P (d
.vmode
));
11585 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
11586 d
.testing_p
= false;
11588 gcc_assert (GET_CODE (sel
) == CONST_VECTOR
);
11589 gcc_assert (XVECLEN (sel
, 0) == nelt
);
11590 gcc_checking_assert (sizeof (d
.perm
) == sizeof (perm
));
11592 for (i
= which
= 0; i
< nelt
; ++i
)
11594 rtx e
= XVECEXP (sel
, 0, i
);
11595 int ei
= INTVAL (e
) & (2 * nelt
- 1);
11597 which
|= (ei
< nelt
? 1 : 2);
11608 if (!rtx_equal_p (d
.op0
, d
.op1
))
11610 d
.one_operand_p
= false;
11614 /* The elements of PERM do not suggest that only the first operand
11615 is used, but both operands are identical. Allow easier matching
11616 of the permutation by folding the permutation into the single
11618 for (i
= 0; i
< nelt
; ++i
)
11619 if (d
.perm
[i
] >= nelt
)
11625 d
.one_operand_p
= true;
11629 for (i
= 0; i
< nelt
; ++i
)
11632 d
.one_operand_p
= true;
11636 if (ia64_expand_vec_perm_const_1 (&d
))
11639 /* If the mask says both arguments are needed, but they are the same,
11640 the above tried to expand with one_operand_p true. If that didn't
11641 work, retry with one_operand_p false, as that's what we used in _ok. */
11642 if (which
== 3 && d
.one_operand_p
)
11644 memcpy (d
.perm
, perm
, sizeof (perm
));
11645 d
.one_operand_p
= false;
11646 return ia64_expand_vec_perm_const_1 (&d
);
11652 /* Implement targetm.vectorize.vec_perm_const_ok. */
11655 ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
11656 const unsigned char *sel
)
11658 struct expand_vec_perm_d d
;
11659 unsigned int i
, nelt
, which
;
11663 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
11664 d
.testing_p
= true;
11666 /* Extract the values from the vector CST into the permutation
11668 memcpy (d
.perm
, sel
, nelt
);
11669 for (i
= which
= 0; i
< nelt
; ++i
)
11671 unsigned char e
= d
.perm
[i
];
11672 gcc_assert (e
< 2 * nelt
);
11673 which
|= (e
< nelt
? 1 : 2);
11676 /* For all elements from second vector, fold the elements to first. */
11678 for (i
= 0; i
< nelt
; ++i
)
11681 /* Check whether the mask can be applied to the vector type. */
11682 d
.one_operand_p
= (which
!= 3);
11684 /* Otherwise we have to go through the motions and see if we can
11685 figure out how to generate the requested permutation. */
11686 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
11687 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
11688 if (!d
.one_operand_p
)
11689 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
11692 ret
= ia64_expand_vec_perm_const_1 (&d
);
11699 ia64_expand_vec_setv2sf (rtx operands
[3])
11701 struct expand_vec_perm_d d
;
11702 unsigned int which
;
11705 d
.target
= operands
[0];
11706 d
.op0
= operands
[0];
11707 d
.op1
= gen_reg_rtx (V2SFmode
);
11708 d
.vmode
= V2SFmode
;
11710 d
.one_operand_p
= false;
11711 d
.testing_p
= false;
11713 which
= INTVAL (operands
[2]);
11714 gcc_assert (which
<= 1);
11715 d
.perm
[0] = 1 - which
;
11716 d
.perm
[1] = which
+ 2;
11718 emit_insn (gen_fpack (d
.op1
, operands
[1], CONST0_RTX (SFmode
)));
11720 ok
= ia64_expand_vec_perm_const_1 (&d
);
11725 ia64_expand_vec_perm_even_odd (rtx target
, rtx op0
, rtx op1
, int odd
)
11727 struct expand_vec_perm_d d
;
11728 enum machine_mode vmode
= GET_MODE (target
);
11729 unsigned int i
, nelt
= GET_MODE_NUNITS (vmode
);
11737 d
.one_operand_p
= false;
11738 d
.testing_p
= false;
11740 for (i
= 0; i
< nelt
; ++i
)
11741 d
.perm
[i
] = i
* 2 + odd
;
11743 ok
= ia64_expand_vec_perm_const_1 (&d
);
11747 #include "gt-ia64.h"