| blob | b75a588eb9aa49b1796161d34494d452a6742e4d |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
75 /* This file should be included last. */
78 /* Defined for convenience. */
79 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
81 /* Classifies an address.
83 ADDRESS_REG_IMM
84 A simple base register plus immediate offset.
86 ADDRESS_REG_WB
87 A base register indexed by immediate offset with writeback.
89 ADDRESS_REG_REG
90 A base register indexed by (optionally scaled) register.
92 ADDRESS_REG_UXTW
93 A base register indexed by (optionally scaled) zero-extended register.
95 ADDRESS_REG_SXTW
96 A base register indexed by (optionally scaled) sign-extended register.
98 ADDRESS_LO_SUM
99 A LO_SUM rtx with a base register and "LO12" symbol relocation.
101 ADDRESS_SYMBOLIC:
102 A constant symbolic address, in pc-relative literal pool. */
105 ADDRESS_REG_IMM,
106 ADDRESS_REG_WB,
107 ADDRESS_REG_REG,
108 ADDRESS_REG_UXTW,
109 ADDRESS_REG_SXTW,
110 ADDRESS_LO_SUM,
111 ADDRESS_SYMBOLIC
112 };
116 rtx base;
117 rtx offset;
118 poly_int64 const_offset;
121 };
123 /* Information about a legitimate vector immediate operand. */
124 struct simd_immediate_info
125 {
136 /* The mode of the elements. */
137 scalar_mode elt_mode;
139 /* The value of each element if all elements are the same, or the
140 first value if the constant is a series. */
141 rtx value;
143 /* The value of the step if the constant is a series, null otherwise. */
144 rtx step;
146 /* The instruction to use to move the immediate into a vector. */
147 insn_type insn;
149 /* The kind of shift modifier to use, and the number of bits to shift.
150 This is (LSL, 0) if no shift is needed. */
151 modifier_type modifier;
153 };
155 /* Construct a floating-point immediate in which each element has mode
156 ELT_MODE_IN and value VALUE_IN. */
157 inline simd_immediate_info
161 {}
163 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
164 and value VALUE_IN. The other parameters are as for the structure
165 fields. */
166 inline simd_immediate_info
173 {}
175 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
176 and where element I is equal to VALUE_IN + I * STEP_IN. */
177 inline simd_immediate_info
181 {}
183 /* The current code model. */
186 /* The number of 64-bit elements in an SVE vector. */
187 poly_uint16 aarch64_sve_vg;
189 #ifdef HAVE_AS_TLS
190 #undef TARGET_HAVE_TLS
191 #define TARGET_HAVE_TLS 1
192 #endif
196 const_tree,
205 const_tree type,
211 /* Major revision number of the ARM Architecture implemented by the target. */
214 /* The processor for which instructions should be scheduled. */
217 /* Mask to specify which instruction scheduling options should be used. */
220 /* Global flag for PC relative loads. */
223 /* Support for command line parsing of boolean flags in the tuning
224 structures. */
225 struct aarch64_flag_desc
226 {
229 };
231 #define AARCH64_FUSION_PAIR(name, internal_name) \
232 { name, AARCH64_FUSE_##internal_name },
234 {
239 };
241 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
242 { name, AARCH64_EXTRA_TUNE_##internal_name },
244 {
249 };
251 /* Tuning parameters. */
254 {
255 {
260 },
267 };
270 {
271 {
276 },
283 };
286 {
287 {
292 },
299 };
302 {
303 {
308 },
315 };
318 {
320 /* Avoid the use of slow int<->fp moves for spilling by setting
321 their cost higher than memmov_cost. */
325 };
328 {
330 /* Avoid the use of slow int<->fp moves for spilling by setting
331 their cost higher than memmov_cost. */
335 };
338 {
340 /* Avoid the use of slow int<->fp moves for spilling by setting
341 their cost higher than memmov_cost. */
345 };
348 {
350 /* Avoid the use of slow int<->fp moves for spilling by setting
351 their cost higher than memmov_cost (actual, 4 and 9). */
355 };
358 {
363 };
366 {
368 /* Avoid the use of slow int<->fp moves for spilling by setting
369 their cost higher than memmov_cost. */
373 };
376 {
378 /* Avoid the use of int<->fp moves for spilling. */
382 };
385 {
387 /* Avoid the use of int<->fp moves for spilling. */
391 };
393 /* Generic costs for vector insn classes. */
395 {
411 };
413 /* ThunderX costs for vector insn classes. */
415 {
431 };
433 /* Generic costs for vector insn classes. */
435 {
451 };
454 {
470 };
472 /* Generic costs for vector insn classes. */
474 {
490 };
492 /* Costs for vector insn classes for Vulcan. */
494 {
510 };
512 /* Generic costs for branch instructions. */
514 {
517 };
519 /* Generic approximation modes. */
521 {
524 AARCH64_APPROX_NONE /* recip_sqrt */
525 };
527 /* Approximation modes for Exynos M1. */
529 {
532 AARCH64_APPROX_ALL /* recip_sqrt */
533 };
535 /* Approximation modes for X-Gene 1. */
537 {
540 AARCH64_APPROX_ALL /* recip_sqrt */
541 };
543 /* Generic prefetch settings (which disable prefetch). */
545 {
551 };
554 {
560 };
563 {
569 };
572 {
578 };
581 {
587 };
590 {
596 };
599 {
620 &generic_prefetch_tune
621 };
624 {
646 &generic_prefetch_tune
647 };
650 {
672 &generic_prefetch_tune
673 };
676 {
698 &generic_prefetch_tune
699 };
702 {
724 &generic_prefetch_tune
725 };
728 {
750 &generic_prefetch_tune
751 };
756 {
777 &exynosm1_prefetch_tune
778 };
781 {
802 &thunderxt88_prefetch_tune
803 };
806 {
826 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
828 &thunderx_prefetch_tune
829 };
832 {
853 &generic_prefetch_tune
854 };
857 {
879 &qdf24xx_prefetch_tune
880 };
882 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
883 for now. */
885 {
907 &generic_prefetch_tune
908 };
911 {
933 &thunderx2t99_prefetch_tune
934 };
936 /* Support for fine-grained override of the tuning structures. */
937 struct aarch64_tuning_override_function
938 {
941 };
946 static const struct aarch64_tuning_override_function
947 aarch64_tuning_override_functions[] =
948 {
952 };
954 /* A processor implementing AArch64. */
955 struct processor
956 {
964 };
966 /* Architectures implementing AArch64. */
968 {
969 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
970 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
973 };
975 /* Processor cores implementing AArch64. */
977 {
978 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
979 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
980 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
981 FLAGS, &COSTS##_tunings},
986 };
989 /* Target specification. These are populated by the -march, -mtune, -mcpu
990 handling code or by target attributes. */
995 /* The current tuning set. */
998 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
1000 /* An ISA extension in the co-processor and main instruction set space. */
1001 struct aarch64_option_extension
1002 {
1006 };
1009 {
1013 }
1014 aarch64_cc;
1016 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
1018 /* The condition codes of the processor, and the inverse function. */
1020 {
1023 };
1025 /* Generate code to enable conditional branches in functions over 1 MiB. */
1029 {
1046 }
1048 void
1050 {
1054 else
1056 }
1058 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
1059 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
1060 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
1061 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
1062 cost (in this case the best class is the lowest cost one). Using ALL_REGS
1063 irrespectively of its cost results in bad allocations with many redundant
1064 int<->FP moves which are expensive on various cores.
1065 To avoid this we don't allow ALL_REGS as the allocno class, but force a
1066 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
1067 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
1068 Otherwise set the allocno class depending on the mode.
1069 The result of this is that it is no longer inefficient to have a higher
1070 memory move cost than the register move cost.
1071 */
1073 static reg_class_t
1075 reg_class_t best_class)
1076 {
1077 machine_mode mode;
1087 }
1089 static unsigned int
1091 {
1095 }
1097 /* Return the reassociation width of treeop OPC with mode MODE. */
1098 static int
1100 {
1105 /* Avoid reassociating floating point addition so we emit more FMAs. */
1109 }
1111 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1112 unsigned
1114 {
1126 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1127 equivalent DWARF register. */
1129 }
1131 /* Return true if MODE is any of the Advanced SIMD structure modes. */
1132 static bool
1134 {
1137 }
1139 /* Return true if MODE is an SVE predicate mode. */
1140 static bool
1142 {
1148 }
1150 /* Three mutually-exclusive flags describing a vector or predicate type. */
1154 /* Can be used in combination with VEC_ADVSIMD or VEC_SVE_DATA to indicate
1155 a structure of 2, 3 or 4 vectors. */
1157 /* Useful combinations of the above. */
1161 /* Return a set of flags describing the vector properties of mode MODE.
1162 Ignore modes that are not supported by the current target. */
1163 static unsigned int
1165 {
1181 {
1183 {
1190 }
1192 /* This includes V1DF but not V1DI (which doesn't exist). */
1197 }
1200 }
1202 /* Return true if MODE is any of the data vector modes, including
1203 structure modes. */
1204 static bool
1206 {
1208 }
1210 /* Return true if MODE is an SVE data vector mode; either a single vector
1211 or a structure of vectors. */
1212 static bool
1214 {
1216 }
1218 /* Implement target hook TARGET_ARRAY_MODE. */
1219 static opt_machine_mode
1221 {
1228 }
1230 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1231 static bool
1234 {
1242 }
1244 /* Return the SVE predicate mode to use for elements that have
1245 ELEM_NBYTES bytes, if such a mode exists. */
1247 opt_machine_mode
1249 {
1251 {
1260 }
1262 }
1264 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
1266 static opt_machine_mode
1268 {
1270 {
1272 machine_mode pred_mode;
1275 }
1278 }
1280 /* Implement TARGET_HARD_REGNO_NREGS. */
1282 static unsigned int
1284 {
1285 /* ??? Logically we should only need to provide a value when
1286 HARD_REGNO_MODE_OK says that the combination is valid,
1287 but at the moment we need to handle all modes. Just ignore
1288 any runtime parts for registers that can't store them. */
1291 {
1304 }
1306 }
1308 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1310 static bool
1312 {
1317 /* This must have the same size as _Unwind_Word. */
1328 /* The purpose of comparing with ptr_mode is to support the
1329 global register variable associated with the stack pointer
1330 register via the syntax of asm ("wsp") in ILP32. */
1340 {
1343 else
1345 }
1348 }
1350 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1351 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1352 clobbers the top 64 bits when restoring the bottom 64 bits. */
1354 static bool
1356 {
1358 }
1360 /* Implement REGMODE_NATURAL_SIZE. */
1361 poly_uint64
1363 {
1364 /* The natural size for SVE data modes is one SVE data vector,
1365 and similarly for predicates. We can't independently modify
1366 anything smaller than that. */
1367 /* ??? For now, only do this for variable-width SVE registers.
1368 Doing it for constant-sized registers breaks lower-subreg.c. */
1369 /* ??? And once that's fixed, we should probably have similar
1370 code for Advanced SIMD. */
1372 {
1378 }
1380 }
1382 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1383 machine_mode
1385 machine_mode mode)
1386 {
1387 /* The predicate mode determines which bits are significant and
1388 which are "don't care". Decreasing the number of lanes would
1389 lose data while increasing the number of lanes would make bits
1390 unnecessarily significant. */
1395 else
1397 }
1399 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
1400 that strcpy from constants will be faster. */
1402 static HOST_WIDE_INT
1404 {
1408 }
1410 /* Return true if calls to DECL should be treated as
1411 long-calls (ie called via a register). */
1412 static bool
1414 {
1416 }
1418 /* Return true if calls to symbol-ref SYM should be treated as
1419 long-calls (ie called via a register). */
1420 bool
1422 {
1424 }
1426 /* Return true if calls to symbol-ref SYM should not go through
1427 plt stubs. */
1429 bool
1431 {
1435 && decl
1436 && (!flag_plt
1442 }
1444 /* Return true if the offsets to a zero/sign-extract operation
1445 represent an expression that matches an extend operation. The
1446 operands represent the paramters from
1448 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1449 bool
1451 rtx extract_imm)
1452 {
1469 }
1471 /* Emit an insn that's a simple single-set. Both the operands must be
1472 known to be valid. */
1475 {
1477 }
1479 /* X and Y are two things to compare using CODE. Emit the compare insn and
1480 return the rtx for register 0 in the proper mode. */
1481 rtx
1483 {
1489 }
1491 /* Build the SYMBOL_REF for __tls_get_addr. */
1495 rtx
1497 {
1501 }
1503 /* Return the TLS model to use for ADDR. */
1505 static enum tls_model
1507 {
1510 {
1511 poly_int64 addend;
1515 }
1520 }
1522 /* We'll allow lo_sum's in addresses in our legitimate addresses
1523 so that combine would take care of combining addresses where
1524 necessary, but for generation purposes, we'll generate the address
1525 as :
1526 RTL Absolute
1527 tmp = hi (symbol_ref); adrp x1, foo
1528 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1529 nop
1531 PIC TLS
1532 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1533 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1534 bl __tls_get_addr
1535 nop
1537 Load TLS symbol, depending on TLS mechanism and TLS access model.
1539 Global Dynamic - Traditional TLS:
1540 adrp tmp, :tlsgd:imm
1541 add dest, tmp, #:tlsgd_lo12:imm
1542 bl __tls_get_addr
1544 Global Dynamic - TLS Descriptors:
1545 adrp dest, :tlsdesc:imm
1546 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1547 add dest, dest, #:tlsdesc_lo12:imm
1548 blr tmp
1549 mrs tp, tpidr_el0
1550 add dest, dest, tp
1552 Initial Exec:
1553 mrs tp, tpidr_el0
1554 adrp tmp, :gottprel:imm
1555 ldr dest, [tmp, #:gottprel_lo12:imm]
1556 add dest, dest, tp
1558 Local Exec:
1559 mrs tp, tpidr_el0
1560 add t0, tp, #:tprel_hi12:imm, lsl #12
1561 add t0, t0, #:tprel_lo12_nc:imm
1562 */
1564 static void
1567 {
1569 {
1571 {
1572 /* In ILP32, the mode of dest can be either SImode or DImode. */
1584 }
1591 {
1594 rtx insn;
1595 rtx mem;
1597 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1598 here before rtl expand. Tree IVOPT will generate rtl pattern to
1599 decide rtx costs, in which case pic_offset_table_rtx is not
1600 initialized. For that case no need to generate the first adrp
1601 instruction as the final cost for global variable access is
1602 one instruction. */
1604 {
1605 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1606 using the page base as GOT base, the first page may be wasted,
1607 in the worst scenario, there is only 28K space for GOT).
1609 The generate instruction sequence for accessing global variable
1610 is:
1612 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1614 Only one instruction needed. But we must initialize
1615 pic_offset_table_rtx properly. We generate initialize insn for
1616 every global access, and allow CSE to remove all redundant.
1618 The final instruction sequences will look like the following
1619 for multiply global variables access.
1621 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1623 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1624 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1625 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1626 ... */
1635 }
1638 {
1641 else
1645 }
1646 else
1647 {
1652 }
1654 /* The operand is expected to be MEM. Whenever the related insn
1655 pattern changed, above code which calculate mem should be
1656 updated. */
1662 }
1665 {
1666 /* In ILP32, the mode of dest can be either SImode or DImode,
1667 while the got entry is always of SImode size. The mode of
1668 dest depends on how dest is used: if dest is assigned to a
1669 pointer (e.g. in the memory), it has SImode; it may have
1670 DImode if dest is dereferenced to access the memeory.
1671 This is why we have to handle three different ldr_got_small
1672 patterns here (two patterns for ILP32). */
1674 rtx insn;
1675 rtx mem;
1684 {
1687 else
1691 }
1692 else
1693 {
1698 }
1705 }
1708 {
1716 else
1724 }
1727 {
1730 rtx tp;
1734 /* In ILP32, the got entry is always of SImode size. Unlike
1735 small GOT, the dest is fixed at reg 0. */
1738 else
1749 }
1752 {
1753 /* In ILP32, the mode of dest can be either SImode or DImode,
1754 while the got entry is always of SImode size. The mode of
1755 dest depends on how dest is used: if dest is assigned to a
1756 pointer (e.g. in the memory), it has SImode; it may have
1757 DImode if dest is dereferenced to access the memeory.
1758 This is why we have to handle three different tlsie_small
1759 patterns here (two patterns for ILP32). */
1765 {
1768 else
1769 {
1772 }
1773 }
1774 else
1775 {
1778 }
1784 }
1790 {
1798 {
1821 }
1826 }
1833 {
1838 {
1841 else
1842 {
1845 }
1846 }
1847 else
1848 {
1851 }
1856 }
1860 }
1861 }
1863 /* Emit a move from SRC to DEST. Assume that the move expanders can
1864 handle all moves if !can_create_pseudo_p (). The distinction is
1865 important because, unlike emit_move_insn, the move expanders know
1866 how to force Pmode objects into the constant pool even when the
1867 constant pool address is not itself legitimate. */
1868 static rtx
1870 {
1874 }
1876 /* Apply UNOPTAB to OP and store the result in DEST. */
1878 static void
1880 {
1884 }
1886 /* Apply BINOPTAB to OP0 and OP1 and store the result in DEST. */
1888 static void
1890 {
1892 OPTAB_DIRECT);
1895 }
1897 /* Split a 128-bit move operation into two 64-bit move operations,
1898 taking care to handle partial overlap of register to register
1899 copies. Special cases are needed when moving between GP regs and
1900 FP regs. SRC can be a register, constant or memory; DST a register
1901 or memory. If either operand is memory it must not have any side
1902 effects. */
1903 void
1905 {
1916 {
1920 /* Handle FP <-> GP regs. */
1922 {
1927 {
1930 }
1931 else
1932 {
1935 }
1937 }
1939 {
1944 {
1947 }
1948 else
1949 {
1952 }
1954 }
1955 }
1962 /* At most one pairing may overlap. */
1964 {
1967 }
1968 else
1969 {
1972 }
1973 }
1975 bool
1977 {
1980 }
1982 /* Split a complex SIMD combine. */
1984 void
1986 {
1998 {
2022 }
2026 }
2028 /* Split a complex SIMD move. */
2030 void
2032 {
2039 {
2045 {
2069 }
2073 }
2074 }
2076 bool
2079 {
2083 }
2086 static rtx
2088 {
2091 else
2092 {
2096 }
2097 }
2099 /* Return true if we can move VALUE into a register using a single
2100 CNT[BHWD] instruction. */
2102 static bool
2104 {
2106 /* The coefficient must be [1, 16] * {2, 4, 8, 16}. */
2111 }
2113 /* Likewise for rtx X. */
2115 bool
2117 {
2118 poly_int64 value;
2120 }
2122 /* Return the asm string for an instruction with a CNT-like vector size
2123 operand (a vector pattern followed by a multiplier in the range [1, 16]).
2124 PREFIX is the mnemonic without the size suffix and OPERANDS is the
2125 first part of the operands template (the part that comes before the
2126 vector size itself). FACTOR is the number of quadwords.
2127 NELTS_PER_VQ, if nonzero, is the number of elements in each quadword.
2128 If it is zero, we can use any element size. */
2134 {
2138 /* There is some overlap in the ranges of the four CNT instructions.
2139 Here we always use the smallest possible element size, so that the
2140 multiplier is 1 whereever possible. */
2151 else
2156 }
2158 /* Return the asm string for an instruction with a CNT-like vector size
2159 operand (a vector pattern followed by a multiplier in the range [1, 16]).
2160 PREFIX is the mnemonic without the size suffix and OPERANDS is the
2161 first part of the operands template (the part that comes before the
2162 vector size itself). X is the value of the vector size operand,
2163 as a polynomial integer rtx. */
2167 rtx x)
2168 {
2173 }
2175 /* Return true if we can add VALUE to a register using a single ADDVL
2176 or ADDPL instruction. */
2178 static bool
2180 {
2184 /* FACTOR counts VG / 2, so a value of 2 is one predicate width
2185 and a value of 16 is one vector width. */
2188 }
2190 /* Likewise for rtx X. */
2192 bool
2194 {
2195 poly_int64 value;
2198 }
2200 /* Return the asm string for adding ADDVL or ADDPL immediate X to operand 1
2201 and storing the result in operand 0. */
2205 {
2210 /* Use INC or DEC if possible. */
2212 {
2219 }
2224 else
2227 }
2229 /* Return true if X is a valid immediate for an SVE vector INC or DEC
2230 instruction. If it is, store the number of elements in each vector
2231 quadword in *NELTS_PER_VQ_OUT (if nonnull) and store the multiplication
2232 factor in *FACTOR_OUT (if nonnull). */
2234 bool
2237 {
2238 rtx elt;
2239 poly_int64 value;
2247 /* There's no vector INCB. */
2254 /* The coefficient must be [1, 16] * NELTS_PER_VQ. */
2264 }
2266 /* Return true if X is a valid immediate for an SVE vector INC or DEC
2267 instruction. */
2269 bool
2271 {
2273 }
2275 /* Return the asm template for an SVE vector INC or DEC instruction.
2276 OPERANDS gives the operands before the vector count and X is the
2277 value of the vector count operand itself. */
2281 {
2288 nelts_per_vq);
2289 else
2291 nelts_per_vq);
2292 }
2294 static int
2296 scalar_int_mode mode)
2297 {
2306 {
2310 }
2312 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
2313 (with XXXX non-zero). In that case check to see if the move can be done in
2314 a smaller mode. */
2319 {
2323 /* Check if we have to emit a second instruction by checking to see
2324 if any of the upper 32 bits of the original DI mode value is set. */
2335 }
2338 {
2340 {
2345 else
2348 }
2350 }
2352 /* Remaining cases are all for DImode. */
2361 {
2362 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
2363 For a 64-bit bitmask try whether changing 16 bits to all ones or
2364 zeroes creates a valid bitmask. To check any repeated bitmask,
2365 try using 16 bits from the other 32-bit half of val. */
2368 {
2379 }
2381 {
2383 {
2387 }
2389 }
2390 }
2392 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
2393 are emitted by the initial mov. If one_match > zero_match, skip set bits,
2394 otherwise skip zero bits. */
2406 {
2412 num_insns ++;
2413 }
2416 }
2418 /* Return whether imm is a 128-bit immediate which is simple enough to
2419 expand inline. */
2420 bool
2422 {
2433 }
2436 /* Return the number of temporary registers that aarch64_add_offset_1
2437 would need to add OFFSET to a register. */
2439 static unsigned int
2441 {
2443 }
2445 /* A subroutine of aarch64_add_offset. Set DEST to SRC + OFFSET for
2446 a non-polynomial OFFSET. MODE is the mode of the addition.
2447 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
2448 be set and CFA adjustments added to the generated instructions.
2450 TEMP1, if nonnull, is a register of mode MODE that can be used as a
2451 temporary if register allocation is already complete. This temporary
2452 register may overlap DEST but must not overlap SRC. If TEMP1 is known
2453 to hold abs (OFFSET), EMIT_MOVE_IMM can be set to false to avoid emitting
2454 the immediate again.
2456 Since this function may be used to adjust the stack pointer, we must
2457 ensure that it cannot cause transient stack deallocation (for example
2458 by first incrementing SP and then decrementing when adjusting by a
2459 large immediate). */
2461 static void
2465 {
2473 {
2475 {
2478 }
2480 }
2482 /* Single instruction adjustment. */
2484 {
2488 }
2490 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits
2491 and either:
2493 a) the offset cannot be loaded by a 16-bit move or
2494 b) there is no spare register into which we can move it. */
2498 {
2507 }
2509 /* Emit a move immediate if required and an addition/subtraction. */
2511 {
2514 }
2519 {
2523 }
2524 }
2526 /* Return the number of temporary registers that aarch64_add_offset
2527 would need to move OFFSET into a register or add OFFSET to a register;
2528 ADD_P is true if we want the latter rather than the former. */
2530 static unsigned int
2532 {
2533 /* This follows the same structure as aarch64_add_offset. */
2542 /* Need one register for the ADDVL/ADDPL result. */
2545 {
2548 /* Need one register for the CNT result and one for the multiplication
2549 factor. If necessary, the second temporary can be reused for the
2550 constant part of the offset. */
2552 /* Need one register for the CNT result (which might then
2553 be shifted). */
2555 }
2557 }
2559 /* If X can be represented as a poly_int64, return the number
2560 of temporaries that are required to add it to a register.
2561 Return -1 otherwise. */
2563 int
2565 {
2566 poly_int64 offset;
2570 }
2572 /* Set DEST to SRC + OFFSET. MODE is the mode of the addition.
2573 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
2574 be set and CFA adjustments added to the generated instructions.
2576 TEMP1, if nonnull, is a register of mode MODE that can be used as a
2577 temporary if register allocation is already complete. This temporary
2578 register may overlap DEST if !FRAME_RELATED_P but must not overlap SRC.
2579 If TEMP1 is known to hold abs (OFFSET), EMIT_MOVE_IMM can be set to
2580 false to avoid emitting the immediate again.
2582 TEMP2, if nonnull, is a second temporary register that doesn't
2583 overlap either DEST or REG.
2585 Since this function may be used to adjust the stack pointer, we must
2586 ensure that it cannot cause transient stack deallocation (for example
2587 by first incrementing SP and then decrementing when adjusting by a
2588 large immediate). */
2590 static void
2594 {
2598 || !frame_related_p
2602 /* Try using ADDVL or ADDPL to add the whole value. */
2604 {
2609 }
2611 /* Coefficient 1 is multiplied by the number of 128-bit blocks in an
2612 SVE vector register, over and above the minimum size of 128 bits.
2613 This is equivalent to half the value returned by CNTD with a
2614 vector shape of ALL. */
2618 /* Try using ADDVL or ADDPL to add the VG-based part. */
2622 {
2625 {
2629 }
2630 else
2631 {
2636 }
2637 }
2638 /* Otherwise use a CNT-based sequence. */
2640 {
2641 /* Use a subtraction if we have a negative factor. */
2644 {
2647 }
2649 /* Calculate CNTD * FACTOR / 2. First try to fold the division
2650 into the multiplication. */
2651 rtx val;
2654 /* Use a right shift by 1. */
2656 else
2660 {
2662 {
2663 /* "CNTB Xn, ALL, MUL #FACTOR" is out of range, so calculate
2664 the value with the minimum multiplier and shift it into
2665 position. */
2669 }
2671 }
2672 else
2673 {
2674 /* Use CNTD, then multiply it by FACTOR. */
2678 /* Go back to using a negative multiplication factor if we have
2679 no register from which to subtract. */
2681 {
2684 }
2688 }
2691 {
2692 /* Multiply by 1 << SHIFT. */
2695 }
2697 {
2698 /* Divide by 2. */
2701 }
2703 /* Calculate SRC +/- CNTD * FACTOR / 2. */
2705 {
2708 }
2710 {
2713 }
2716 {
2719 {
2723 poly_offset)));
2724 }
2728 }
2729 else
2730 {
2734 }
2737 }
2741 }
2743 /* Like aarch64_add_offset, but the offset is given as an rtx rather
2744 than a poly_int64. */
2746 void
2749 {
2752 }
2754 /* Add DELTA to the stack pointer, marking the instructions frame-related.
2755 TEMP1 is available as a temporary if nonnull. EMIT_MOVE_IMM is false
2756 if TEMP1 already contains abs (DELTA). */
2760 {
2763 }
2765 /* Subtract DELTA from the stack pointer, marking the instructions
2766 frame-related if FRAME_RELATED_P. TEMP1 is available as a temporary
2767 if nonnull. */
2771 {
2774 }
2776 /* Set DEST to (vec_series BASE STEP). */
2778 static void
2780 {
2784 /* Each operand can be a register or an immediate in the range [-16, 15]. */
2791 }
2793 /* Try to duplicate SRC into SVE register DEST, given that SRC is an
2794 integer of mode INT_MODE. Return true on success. */
2796 static bool
2798 rtx src)
2799 {
2800 /* If the constant is smaller than 128 bits, we can do the move
2801 using a vector of SRC_MODEs. */
2803 {
2810 }
2812 /* Use LD1RQ[BHWD] to load the 128 bits from memory. */
2817 /* Make sure that the address is legitimate. */
2819 {
2822 }
2831 }
2833 /* Expand a move of general CONST_VECTOR SRC into DEST, given that it
2834 isn't a simple duplicate or series. */
2836 static void
2838 {
2845 {
2846 /* The constant is a repeating seqeuence of at least two elements,
2847 where the repeating elements occupy no more than 128 bits.
2848 Get an integer representation of the replicated value. */
2849 scalar_int_mode int_mode;
2851 /* For now, always use LD1RQ to load the value on big-endian
2852 targets, since the handling of smaller integers includes a
2853 subreg that is semantically an element reverse. */
2855 else
2856 {
2860 }
2865 }
2867 /* Expand each pattern individually. */
2868 rtx_vector_builder builder;
2871 {
2876 }
2878 /* Use permutes to interleave the separate vectors. */
2880 {
2883 {
2888 }
2889 }
2891 }
2893 /* Set DEST to immediate IMM. For SVE vector modes, GEN_VEC_DUPLICATE
2894 is a pattern that can be used to set DEST to a replicated scalar
2895 element. */
2897 void
2900 {
2903 /* Check on what type of symbol it is. */
2904 scalar_int_mode int_mode;
2910 {
2911 rtx mem;
2912 poly_int64 offset;
2913 HOST_WIDE_INT const_offset;
2916 /* If we have (const (plus symbol offset)), separate out the offset
2917 before we start classifying the symbol. */
2920 /* We must always add an offset involving VL separately, rather than
2921 folding it into the relocation. */
2923 {
2926 else
2927 {
2928 /* Do arithmetic on 32-bit values if the result is smaller
2929 than that. */
2931 {
2932 /* It is invalid to do symbol calculations in modes
2933 narrower than SImode. */
2937 }
2939 {
2943 }
2944 else
2947 }
2949 }
2953 {
2957 {
2963 }
2968 /* If we aren't generating PC relative literals, then
2969 we need to expand the literal pool access carefully.
2970 This is something that needs to be done in a number
2971 of places, so could well live as a separate function. */
2973 {
2980 }
2997 {
3003 }
3004 /* FALLTHRU */
3017 }
3018 }
3021 {
3029 {
3030 /* If the constant is out of range of an SVE vector move,
3031 load it from memory if we can, otherwise move it into
3032 a register and use a DUP. */
3038 {
3041 }
3043 }
3047 else
3048 {
3052 }
3055 }
3059 }
3061 /* Emit an SVE predicated move from SRC to DEST. PRED is a predicate
3062 that is known to contain PTRUE. */
3064 void
3066 {
3069 UNSPEC_MERGE_PTRUE)));
3070 }
3072 /* Expand a pre-RA SVE data move from SRC to DEST in which at least one
3073 operand is in memory. In this case we need to use the predicated LD1
3074 and ST1 instead of LDR and STR, both for correctness on big-endian
3075 targets and because LD1 and ST1 support a wider range of addressing modes.
3076 PRED_MODE is the mode of the predicate.
3078 See the comment at the head of aarch64-sve.md for details about the
3079 big-endian handling. */
3081 void
3083 {
3088 {
3092 else
3095 }
3097 }
3099 /* Called only on big-endian targets. See whether an SVE vector move
3100 from SRC to DEST is effectively a REV[BHW] instruction, because at
3101 least one operand is a subreg of an SVE vector that has wider or
3102 narrower elements. Return true and emit the instruction if so.
3104 For example:
3106 (set (reg:VNx8HI R1) (subreg:VNx8HI (reg:VNx16QI R2) 0))
3108 represents a VIEW_CONVERT between the following vectors, viewed
3109 in memory order:
3111 R2: { [0].high, [0].low, [1].high, [1].low, ... }
3112 R1: { [0], [1], [2], [3], ... }
3114 The high part of lane X in R2 should therefore correspond to lane X*2
3115 of R1, but the register representations are:
3117 msb lsb
3118 R2: ...... [1].high [1].low [0].high [0].low
3119 R1: ...... [3] [2] [1] [0]
3121 where the low part of lane X in R2 corresponds to lane X*2 in R1.
3122 We therefore need a reverse operation to swap the high and low values
3123 around.
3125 This is purely an optimization. Without it we would spill the
3126 subreg operand to the stack in one mode and reload it in the
3127 other mode, which has the same effect as the REV. */
3129 bool
3131 {
3138 /* The optimization handles two single SVE REGs with different element
3139 sizes. */
3148 /* Generate *aarch64_sve_mov<mode>_subreg_be. */
3151 UNSPEC_REV_SUBREG);
3154 }
3156 /* Return a copy of X with mode MODE, without changing its other
3157 attributes. Unlike gen_lowpart, this doesn't care whether the
3158 mode change is valid. */
3160 static rtx
3162 {
3169 }
3171 /* Split a *aarch64_sve_mov<mode>_subreg_be pattern with the given
3172 operands. */
3174 void
3176 {
3177 /* Decide which REV operation we need. The mode with narrower elements
3178 determines the mode of the operands and the mode with the wider
3179 elements determines the reverse width. */
3194 else
3198 /* Emit:
3200 (set DEST (unspec [PTRUE (unspec [SRC] UNSPEC_REV<nn>)]
3201 UNSPEC_MERGE_PTRUE))
3203 with the appropriate modes. */
3209 UNSPEC_MERGE_PTRUE);
3211 }
3213 static bool
3215 tree exp ATTRIBUTE_UNUSED)
3216 {
3217 /* Currently, always true. */
3219 }
3221 /* Implement TARGET_PASS_BY_REFERENCE. */
3223 static bool
3225 machine_mode mode,
3226 const_tree type,
3228 {
3229 HOST_WIDE_INT size;
3230 machine_mode dummymode;
3233 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
3236 else
3237 /* No frontends can create types with variable-sized modes, so we
3238 shouldn't be asked to pass or return them. */
3241 /* Aggregates are passed by reference based on their size. */
3243 {
3245 }
3247 /* Variable sized arguments are always returned by reference. */
3251 /* Can this be a candidate to be passed in fp/simd register(s)? */
3254 NULL))
3257 /* Arguments which are variable sized or larger than 2 registers are
3258 passed by reference unless they are a homogenous floating point
3259 aggregate. */
3261 }
3263 /* Return TRUE if VALTYPE is padded to its least significant bits. */
3264 static bool
3266 {
3267 machine_mode dummy_mode;
3270 /* Never happens in little-endian mode. */
3274 /* Only composite types smaller than or equal to 16 bytes can
3275 be potentially returned in registers. */
3281 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
3282 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
3283 is always passed/returned in the least significant bits of fp/simd
3284 register(s). */
3290 }
3292 /* Implement TARGET_FUNCTION_VALUE.
3293 Define how to find the value returned by a function. */
3295 static rtx
3298 {
3299 machine_mode mode;
3302 machine_mode ag_mode;
3309 {
3313 {
3316 }
3317 }
3321 {
3323 {
3326 }
3327 else
3328 {
3330 rtx par;
3334 {
3339 }
3341 }
3342 }
3343 else
3345 }
3347 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
3348 Return true if REGNO is the number of a hard register in which the values
3349 of called function may come back. */
3351 static bool
3353 {
3354 /* Maximum of 16 bytes can be returned in the general registers. Examples
3355 of 16-byte return values are: 128-bit integers and 16-byte small
3356 structures (excluding homogeneous floating-point aggregates). */
3360 /* Up to four fp/simd registers can return a function value, e.g. a
3361 homogeneous floating-point aggregate having four members. */
3366 }
3368 /* Implement TARGET_RETURN_IN_MEMORY.
3370 If the type T of the result of a function is such that
3371 void func (T arg)
3372 would require that arg be passed as a value in a register (or set of
3373 registers) according to the parameter passing rules, then the result
3374 is returned in the same registers as would be used for such an
3375 argument. */
3377 static bool
3379 {
3380 HOST_WIDE_INT size;
3381 machine_mode ag_mode;
3387 /* Simple scalar types always returned in registers. */
3391 type,
3394 NULL))
3397 /* Types larger than 2 registers returned in memory. */
3400 }
3402 static bool
3405 {
3408 type,
3410 nregs,
3411 NULL);
3412 }
3414 /* Given MODE and TYPE of a function argument, return the alignment in
3415 bits. The idea is to suppress any stronger alignment requested by
3416 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
3417 This is a helper function for local use only. */
3419 static unsigned int
3421 {
3442 }
3444 /* Layout a function argument according to the AAPCS64 rules. The rule
3445 numbers refer to the rule numbers in the AAPCS64. */
3447 static void
3449 const_tree type,
3451 {
3455 HOST_WIDE_INT size;
3457 /* We need to do this once per argument. */
3463 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
3466 else
3467 /* No frontends can create types with variable-sized modes, so we
3468 shouldn't be asked to pass or return them. */
3474 mode,
3475 type,
3478 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
3479 The following code thus handles passing by SIMD/FP registers first. */
3483 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
3484 and homogenous short-vector aggregates (HVA). */
3486 {
3491 {
3494 {
3497 }
3498 else
3499 {
3500 rtx par;
3504 {
3507 rtx offset = gen_int_mode
3511 }
3513 }
3515 }
3516 else
3517 {
3518 /* C.3 NSRN is set to 8. */
3521 }
3522 }
3527 /* C6 - C9. though the sign and zero extension semantics are
3528 handled elsewhere. This is the case where the argument fits
3529 entirely general registers. */
3531 {
3535 /* C.8 if the argument has an alignment of 16 then the NGRN is
3536 rounded up to the next even number. */
3539 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
3540 comparison is there because for > 16 * BITS_PER_UNIT
3541 alignment nregs should be > 2 and therefore it should be
3542 passed by reference rather than value. */
3544 {
3547 }
3549 /* NREGS can be 0 when e.g. an empty structure is to be passed.
3550 A reg is still generated for it, but the caller should be smart
3551 enough not to use it. */
3554 else
3555 {
3556 rtx par;
3561 {
3566 }
3568 }
3572 }
3574 /* C.11 */
3577 /* The argument is passed on stack; record the needed number of words for
3578 this argument and align the total size if necessary. */
3579 on_stack:
3586 }
3588 /* Implement TARGET_FUNCTION_ARG. */
3590 static rtx
3593 {
3602 }
3604 void
3606 const_tree fntype ATTRIBUTE_UNUSED,
3607 rtx libname ATTRIBUTE_UNUSED,
3608 const_tree fndecl ATTRIBUTE_UNUSED,
3610 {
3624 {
3631 }
3633 }
3635 static void
3637 machine_mode mode,
3638 const_tree type,
3640 {
3643 {
3653 }
3654 }
3656 bool
3658 {
3661 }
3663 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3664 PARM_BOUNDARY bits of alignment, but will be given anything up
3665 to STACK_BOUNDARY bits if the type requires it. This makes sure
3666 that both before and after the layout of each argument, the Next
3667 Stacked Argument Address (NSAA) will have a minimum alignment of
3668 8 bytes. */
3670 static unsigned int
3672 {
3675 }
3677 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
3679 static fixed_size_mode
3681 {
3683 /* Don't use the SVE part of the register for __builtin_apply and
3684 __builtin_return. The SVE registers aren't used by the normal PCS,
3685 so using them there would be a waste of time. The PCS extensions
3686 for SVE types are fundamentally incompatible with the
3687 __builtin_return/__builtin_apply interface. */
3690 }
3692 /* Implement TARGET_FUNCTION_ARG_PADDING.
3694 Small aggregate types are placed in the lowest memory address.
3696 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
3698 static pad_direction
3700 {
3701 /* On little-endian targets, the least significant byte of every stack
3702 argument is passed at the lowest byte address of the stack slot. */
3706 /* Otherwise, integral, floating-point and pointer types are padded downward:
3707 the least significant byte of a stack argument is passed at the highest
3708 byte address of the stack slot. */
3715 /* Everything else padded upward, i.e. data in first byte of stack slot. */
3717 }
3719 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
3721 It specifies padding for the last (may also be the only)
3722 element of a block move between registers and memory. If
3723 assuming the block is in the memory, padding upward means that
3724 the last element is padded after its highest significant byte,
3725 while in downward padding, the last element is padded at the
3726 its least significant byte side.
3728 Small aggregates and small complex types are always padded
3729 upwards.
3731 We don't need to worry about homogeneous floating-point or
3732 short-vector aggregates; their move is not affected by the
3733 padding direction determined here. Regardless of endianness,
3734 each element of such an aggregate is put in the least
3735 significant bits of a fp/simd register.
3737 Return !BYTES_BIG_ENDIAN if the least significant byte of the
3738 register has useful data, and return the opposite if the most
3739 significant byte does. */
3741 bool
3744 {
3746 /* Small composite types are always padded upward. */
3748 {
3749 HOST_WIDE_INT size;
3752 else
3753 /* No frontends can create types with variable-sized modes, so we
3754 shouldn't be asked to pass or return them. */
3758 }
3760 /* Otherwise, use the default padding. */
3762 }
3764 static scalar_int_mode
3766 {
3768 }
3770 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3772 /* We use the 12-bit shifted immediate arithmetic instructions so values
3773 must be multiple of (1 << 12), i.e. 4096. */
3774 #define ARITH_FACTOR 4096
3776 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
3777 #error Cannot use simple address calculation for stack probing
3778 #endif
3780 /* The pair of scratch registers used for stack probing. */
3781 #define PROBE_STACK_FIRST_REG 9
3782 #define PROBE_STACK_SECOND_REG 10
3784 /* Emit code to probe a range of stack addresses from FIRST to FIRST+POLY_SIZE,
3785 inclusive. These are offsets from the current stack pointer. */
3787 static void
3789 {
3790 HOST_WIDE_INT size;
3792 {
3795 }
3799 /* See the same assertion on PROBE_INTERVAL above. */
3802 /* See if we have a constant small number of probes to generate. If so,
3803 that's the easy case. */
3805 {
3812 }
3814 /* The run-time loop is made up of 8 insns in the generic case while the
3815 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
3817 {
3822 stack_pointer_rtx,
3826 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3827 it exceeds SIZE. If only two probes are needed, this will not
3828 generate any code. Then probe at FIRST + SIZE. */
3830 {
3834 }
3838 {
3843 }
3844 else
3846 }
3848 /* Otherwise, do the same as above, but in a loop. Note that we must be
3849 extra careful with variables wrapping around because we might be at
3850 the very top (or the very bottom) of the address space and we have
3851 to be able to handle this case properly; in particular, we use an
3852 equality test for the loop condition. */
3853 else
3854 {
3857 /* Step 1: round SIZE to the previous multiple of the interval. */
3862 /* Step 2: compute initial and final value of the loop counter. */
3864 /* TEST_ADDR = SP + FIRST. */
3868 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3871 {
3875 }
3876 else
3880 /* Step 3: the loop
3882 do
3883 {
3884 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3885 probe at TEST_ADDR
3886 }
3887 while (TEST_ADDR != LAST_ADDR)
3889 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3890 until it is equal to ROUNDED_SIZE. */
3895 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3896 that SIZE is equal to ROUNDED_SIZE. */
3899 {
3903 {
3908 }
3909 else
3911 }
3912 }
3914 /* Make sure nothing is scheduled before we are done. */
3916 }
3918 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3919 absolute addresses. */
3923 {
3930 /* Loop. */
3933 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3938 /* Probe at TEST_ADDR. */
3941 /* Test if TEST_ADDR == LAST_ADDR. */
3945 /* Branch. */
3951 }
3953 /* Mark the registers that need to be saved by the callee and calculate
3954 the size of the callee-saved registers area and frame record (both FP
3955 and LR may be omitted). */
3956 static void
3958 {
3965 /* Force a frame chain for EH returns so the return address is at FP+8. */
3969 /* Emit a frame chain if the frame pointer is enabled.
3970 If -momit-leaf-frame-pointer is used, do not use a frame chain
3971 in leaf functions which do not use LR. */
3977 #define SLOT_NOT_REQUIRED (-2)
3978 #define SLOT_REQUIRED (-1)
3983 /* First mark all the registers that really need to be saved... */
3990 /* ... that includes the eh data registers (if needed)... */
3996 /* ... and any callee saved register that dataflow says is live. */
4006 {
4009 }
4012 {
4013 /* FP and LR are placed in the linkage record. */
4019 }
4021 /* Now assign stack slots for them. */
4024 {
4031 }
4039 {
4040 /* If there is an alignment gap between integer and fp callee-saves,
4041 allocate the last fp register to it if possible. */
4043 {
4046 }
4055 }
4061 HOST_WIDE_INT varargs_and_saved_regs_size
4069 /* Both these values are already aligned. */
4093 {
4094 /* Simple, small frame with no outgoing arguments:
4095 stp reg1, reg2, [sp, -frame_size]!
4096 stp reg3, reg4, [sp, 16] */
4098 }
4103 max_push_offset)))
4104 {
4105 /* Frame with small outgoing arguments:
4106 sub sp, sp, frame_size
4107 stp reg1, reg2, [sp, outgoing_args_size]
4108 stp reg3, reg4, [sp, outgoing_args_size + 16] */
4112 }
4115 {
4116 /* Frame with large outgoing arguments but a small local area:
4117 stp reg1, reg2, [sp, -hard_fp_offset]!
4118 stp reg3, reg4, [sp, 16]
4119 sub sp, sp, outgoing_args_size */
4123 }
4124 else
4125 {
4126 /* Frame with large local area and outgoing arguments using frame pointer:
4127 sub sp, sp, hard_fp_offset
4128 stp x29, x30, [sp, 0]
4129 add x29, sp, 0
4130 stp reg3, reg4, [sp, 16]
4131 sub sp, sp, outgoing_args_size */
4135 }
4138 }
4140 /* Return true if the register REGNO is saved on entry to
4141 the current function. */
4143 static bool
4145 {
4147 }
4149 /* Return the next register up from REGNO up to LIMIT for the callee
4150 to save. */
4152 static unsigned
4154 {
4156 regno ++;
4158 }
4160 /* Push the register number REGNO of mode MODE to the stack with write-back
4161 adjusting the stack by ADJUSTMENT. */
4163 static void
4165 HOST_WIDE_INT adjustment)
4166 {
4177 }
4179 /* Generate and return an instruction to store the pair of registers
4180 REG and REG2 of mode MODE to location BASE with write-back adjusting
4181 the stack location BASE by ADJUSTMENT. */
4183 static rtx
4185 HOST_WIDE_INT adjustment)
4186 {
4188 {
4199 }
4200 }
4202 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
4203 stack pointer by ADJUSTMENT. */
4205 static void
4207 {
4222 }
4224 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
4225 adjusting it by ADJUSTMENT afterwards. */
4227 static rtx
4229 HOST_WIDE_INT adjustment)
4230 {
4232 {
4241 }
4242 }
4244 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
4245 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
4246 into CFI_OPS. */
4248 static void
4251 {
4258 {
4262 }
4263 else
4264 {
4269 }
4270 }
4272 /* Generate and return a store pair instruction of mode MODE to store
4273 register REG1 to MEM1 and register REG2 to MEM2. */
4275 static rtx
4277 rtx reg2)
4278 {
4280 {
4289 }
4290 }
4292 /* Generate and regurn a load pair isntruction of mode MODE to load register
4293 REG1 from MEM1 and register REG2 from MEM2. */
4295 static rtx
4297 rtx mem2)
4298 {
4300 {
4309 }
4310 }
4312 /* Return TRUE if return address signing should be enabled for the current
4313 function, otherwise return FALSE. */
4315 bool
4317 {
4318 /* This function should only be called after frame laid out. */
4321 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
4322 if it's LR is pushed onto stack. */
4326 }
4328 /* Emit code to save the callee-saved registers from register number START
4329 to LIMIT to the stack at the location starting at offset START_OFFSET,
4330 skipping any write-back candidates if SKIP_WB is true. */
4332 static void
4335 {
4343 {
4345 poly_int64 offset;
4358 offset));
4367 {
4369 rtx mem2;
4373 offset));
4375 reg2));
4377 /* The first part of a frame-related parallel insn is
4378 always assumed to be relevant to the frame
4379 calculations; subsequent parts, are only
4380 frame-related if explicitly marked. */
4383 }
4384 else
4388 }
4389 }
4391 /* Emit code to restore the callee registers of mode MODE from register
4392 number START up to and including LIMIT. Restore from the stack offset
4393 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
4394 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
4396 static void
4400 {
4404 poly_int64 offset;
4409 {
4430 {
4432 rtx mem2;
4440 }
4441 else
4444 }
4445 }
4447 /* Return true if OFFSET is a signed 4-bit value multiplied by the size
4448 of MODE. */
4452 {
4453 HOST_WIDE_INT multiple;
4456 }
4458 /* Return true if OFFSET is a unsigned 6-bit value multiplied by the size
4459 of MODE. */
4463 {
4464 HOST_WIDE_INT multiple;
4467 }
4469 /* Return true if OFFSET is a signed 7-bit value multiplied by the size
4470 of MODE. */
4472 bool
4474 {
4475 HOST_WIDE_INT multiple;
4478 }
4480 /* Return true if OFFSET is a signed 9-bit value. */
4484 poly_int64 offset)
4485 {
4486 HOST_WIDE_INT const_offset;
4489 }
4491 /* Return true if OFFSET is a signed 9-bit value multiplied by the size
4492 of MODE. */
4496 {
4497 HOST_WIDE_INT multiple;
4500 }
4502 /* Return true if OFFSET is an unsigned 12-bit value multiplied by the size
4503 of MODE. */
4507 {
4508 HOST_WIDE_INT multiple;
4511 }
4513 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
4515 static sbitmap
4517 {
4523 /* The registers we need saved to the frame. */
4526 {
4531 /* Check that we can access the stack slot of the register with one
4532 direct load with no adjustments needed. */
4535 }
4537 /* Don't mess with the hard frame pointer. */
4543 /* If aarch64_layout_frame has chosen registers to store/restore with
4544 writeback don't interfere with them to avoid having to output explicit
4545 stack adjustment instructions. */
4555 }
4557 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
4559 static sbitmap
4561 {
4569 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
4575 {
4579 /* If there is a callee-save at an adjacent offset, add it too
4580 to increase the use of LDP/STP. */
4585 {
4589 }
4590 }
4593 }
4595 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
4596 Nothing to do for aarch64. */
4598 static void
4600 {
4601 }
4603 /* Return the next set bit in BMP from START onwards. Return the total number
4604 of bits in BMP if no set bit is found at or after START. */
4606 static unsigned int
4608 {
4619 }
4621 /* Do the work for aarch64_emit_prologue_components and
4622 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
4623 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
4624 for these components or the epilogue sequence. That is, it determines
4625 whether we should emit stores or loads and what kind of CFA notes to attach
4626 to the insns. Otherwise the logic for the two sequences is very
4627 similar. */
4629 static void
4631 {
4633 ? HARD_FRAME_POINTER_REGNUM
4641 {
4642 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
4643 so DFmode for the vector registers is enough. */
4655 /* No more registers to handle after REGNO.
4656 Emit a single save/restore and exit. */
4658 {
4663 else
4666 }
4669 /* The next register is not of the same class or its offset is not
4670 mergeable with the current one into a pair. */
4675 {
4680 else
4685 }
4687 /* REGNO2 can be saved/restored in a pair with REGNO. */
4699 else
4704 {
4707 }
4708 else
4709 {
4712 }
4715 }
4716 }
4718 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
4720 static void
4722 {
4724 }
4726 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
4728 static void
4730 {
4732 }
4734 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
4736 static void
4738 {
4742 }
4744 /* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
4745 is saved at BASE + OFFSET. */
4747 static void
4750 {
4754 }
4756 /* AArch64 stack frames generated by this compiler look like:
4758 +-------------------------------+
4759 | |
4760 | incoming stack arguments |
4761 | |
4762 +-------------------------------+
4763 | | <-- incoming stack pointer (aligned)
4764 | callee-allocated save area |
4765 | for register varargs |
4766 | |
4767 +-------------------------------+
4768 | local variables | <-- frame_pointer_rtx
4769 | |
4770 +-------------------------------+
4771 | padding0 | \
4772 +-------------------------------+ |
4773 | callee-saved registers | | frame.saved_regs_size
4774 +-------------------------------+ |
4775 | LR' | |
4776 +-------------------------------+ |
4777 | FP' | / <- hard_frame_pointer_rtx (aligned)
4778 +-------------------------------+
4779 | dynamic allocation |
4780 +-------------------------------+
4781 | padding |
4782 +-------------------------------+
4783 | outgoing stack arguments | <-- arg_pointer
4784 | |
4785 +-------------------------------+
4786 | | <-- stack_pointer_rtx (aligned)
4788 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
4789 but leave frame_pointer_rtx and hard_frame_pointer_rtx
4790 unchanged. */
4792 /* Generate the prologue instructions for entry into a function.
4793 Establish the stack frame by decreasing the stack pointer with a
4794 properly calculated size and, if necessary, create a frame record
4795 filled with the values of LR and previous frame pointer. The
4796 current FP is also set up if it is in use. */
4798 void
4800 {
4813 /* Sign return address for functions. */
4815 {
4819 }
4825 {
4827 {
4831 (frame_size
4833 }
4836 }
4847 {
4850 {
4855 }
4860 {
4861 /* Variable-sized frames need to describe the save slot
4862 address using DW_CFA_expression rather than DW_CFA_offset.
4863 This means that, without taking further action, the
4864 locations of the registers that we've already saved would
4865 remain based on the stack pointer even after we redefine
4866 the CFA based on the frame pointer. We therefore need new
4867 DW_CFA_expressions to re-express the save slots with addresses
4868 based on the frame pointer. */
4872 /* Add an explicit CFA definition if this was previously
4873 implicit. */
4875 {
4877 callee_offset);
4880 }
4882 /* Change the save slot expressions for the registers that
4883 we've already saved. */
4888 reg_offset);
4889 }
4891 }
4898 }
4900 /* Return TRUE if we can use a simple_return insn.
4902 This function checks whether the callee saved stack is empty, which
4903 means no restore actions are need. The pro_and_epilogue will use
4904 this to check whether shrink-wrapping opt is feasible. */
4906 bool
4908 {
4918 }
4920 /* Generate the epilogue instructions for returning from a function.
4921 This is almost exactly the reverse of the prolog sequence, except
4922 that we need to insert barriers to avoid scheduling loads that read
4923 from a deallocated stack, and we optimize the unwind records by
4924 emitting them all together if possible. */
4925 void
4927 {
4938 /* A stack clash protection prologue may not have left IP0_REGNUM or
4939 IP1_REGNUM in a usable state. The same is true for allocations
4940 with an SVE component, since we then need both temporary registers
4941 for each allocation. */
4946 /* We need to add memory barrier to prevent read from deallocated stack. */
4947 bool need_barrier_p
4951 /* Emit a barrier to prevent loads from a deallocated stack. */
4955 {
4958 }
4960 /* Restore the stack pointer from the frame pointer if it may not
4961 be the same as the stack pointer. */
4966 /* If writeback is used when restoring callee-saves, the CFA
4967 is restored on the instruction doing the writeback. */
4971 else
4987 {
4988 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
4994 }
5000 {
5001 /* Emit delayed restores and reset the CFA to be SP. */
5006 }
5008 /* We prefer to emit the combined return/authenticate instruction RETAA,
5009 however there are three cases in which we must instead emit an explicit
5010 authentication instruction.
5012 1) Sibcalls don't return in a normal way, so if we're about to call one
5013 we must authenticate.
5015 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
5016 generating code for !TARGET_ARMV8_3 we can't use it and must
5017 explicitly authenticate.
5019 3) On an eh_return path we make extra stack adjustments to update the
5020 canonical frame address to be the exception handler's CFA. We want
5021 to authenticate using the CFA of the function which calls eh_return.
5022 */
5025 {
5029 }
5031 /* Stack adjustment for exception handler. */
5033 {
5034 /* We need to unwind the stack by the offset computed by
5035 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
5036 to be SP; letting the CFA move during this adjustment
5037 is just as correct as retaining the CFA from the body
5038 of the function. Therefore, do nothing special. */
5040 }
5045 }
5047 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
5048 normally or return to a previous frame after unwinding.
5050 An EH return uses a single shared return sequence. The epilogue is
5051 exactly like a normal epilogue except that it has an extra input
5052 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
5053 that must be applied after the frame has been destroyed. An extra label
5054 is inserted before the epilogue which initializes this register to zero,
5055 and this is the entry point for a normal return.
5057 An actual EH return updates the return address, initializes the stack
5058 adjustment and jumps directly into the epilogue (bypassing the zeroing
5059 of the adjustment). Since the return address is typically saved on the
5060 stack when a function makes a call, the saved LR must be updated outside
5061 the epilogue.
5063 This poses problems as the store is generated well before the epilogue,
5064 so the offset of LR is not known yet. Also optimizations will remove the
5065 store as it appears dead, even after the epilogue is generated (as the
5066 base or offset for loading LR is different in many cases).
5068 To avoid these problems this implementation forces the frame pointer
5069 in eh_return functions so that the location of LR is fixed and known early.
5070 It also marks the store volatile, so no optimization is permitted to
5071 remove the store. */
5072 rtx
5074 {
5078 /* Mark the store volatile, so no optimization is permitted to remove it. */
5081 }
5083 /* Output code to add DELTA to the first argument, and then jump
5084 to FUNCTION. Used for C++ multiple inheritance. */
5085 static void
5087 HOST_WIDE_INT delta,
5088 HOST_WIDE_INT vcall_offset,
5089 tree function)
5090 {
5091 /* The this pointer is always in x0. Note that this differs from
5092 Arm where the this pointer maybe bumped to r1 if r0 is required
5093 to return a pointer to an aggregate. On AArch64 a result value
5094 pointer will be in x8. */
5108 else
5109 {
5114 {
5118 else
5121 }
5125 else
5132 else
5133 {
5135 Pmode);
5137 }
5141 else
5147 }
5149 /* Generate a tail call to the target function. */
5151 {
5154 }
5166 /* Stop pretending to be a post-reload pass. */
5168 }
5170 static bool
5172 {
5177 {
5181 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
5182 TLS offsets, not real symbol references. */
5185 }
5187 }
5190 /* Return true if val can be encoded as a 12-bit unsigned immediate with
5191 a left shift of 0 or 12 bits. */
5192 bool
5194 {
5197 );
5198 }
5201 /* Return true if val is an immediate that can be loaded into a
5202 register by a MOVZ instruction. */
5203 static bool
5205 {
5207 {
5211 }
5212 else
5213 {
5214 /* Ignore sign extension. */
5216 }
5219 }
5221 /* VAL is a value with the inner mode of MODE. Replicate it to fill a
5222 64-bit (DImode) integer. */
5224 static unsigned HOST_WIDE_INT
5226 {
5229 {
5233 }
5235 }
5237 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
5240 {
5246 };
5249 /* Return true if val is a valid bitmask immediate. */
5251 bool
5253 {
5257 /* Check for a single sequence of one bits and return quickly if so.
5258 The special cases of all ones and all zeroes returns false. */
5265 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
5269 /* Invert if the immediate doesn't start with a zero bit - this means we
5270 only need to search for sequences of one bits. */
5274 /* Find the first set bit and set tmp to val with the first sequence of one
5275 bits removed. Return success if there is a single sequence of ones. */
5282 /* Find the next set bit and compute the difference in bit position. */
5287 /* Check the bit position difference is a power of 2, and that the first
5288 sequence of one bits fits within 'bits' bits. */
5292 /* Check the sequence of one bits is repeated 64/bits times. */
5294 }
5296 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
5297 Assumed precondition: VAL_IN Is not zero. */
5299 unsigned HOST_WIDE_INT
5301 {
5308 }
5310 /* Create constant where bits outside of lowest bit set to highest bit set
5311 are set to 1. */
5313 unsigned HOST_WIDE_INT
5315 {
5317 }
5319 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
5321 bool
5323 {
5324 scalar_int_mode int_mode;
5337 }
5339 /* Return true if val is an immediate that can be loaded into a
5340 register in a single instruction. */
5341 bool
5343 {
5344 scalar_int_mode int_mode;
5351 }
5353 static bool
5355 {
5361 /* There's no way to calculate VL-based values using relocations. */
5369 {
5373 else
5374 /* Avoid generating a 64-bit relocation in ILP32; leave
5375 to aarch64_expand_mov_immediate to handle it properly. */
5377 }
5380 }
5382 /* Implement TARGET_CASE_VALUES_THRESHOLD.
5383 The expansion for a table switch is quite expensive due to the number
5384 of instructions, the table lookup and hard to predict indirect jump.
5385 When optimizing for speed, and -O3 enabled, use the per-core tuning if
5386 set, otherwise use tables for > 16 cases as a tradeoff between size and
5387 performance. When optimizing for size, use the default setting. */
5389 static unsigned int
5391 {
5392 /* Use the specified limit for the number of cases before using jump
5393 tables at higher optimization levels. */
5397 else
5399 }
5401 /* Return true if register REGNO is a valid index register.
5402 STRICT_P is true if REG_OK_STRICT is in effect. */
5404 bool
5406 {
5408 {
5416 }
5418 }
5420 /* Return true if register REGNO is a valid base register for mode MODE.
5421 STRICT_P is true if REG_OK_STRICT is in effect. */
5423 bool
5425 {
5427 {
5435 }
5437 /* The fake registers will be eliminated to either the stack or
5438 hard frame pointer, both of which are usually valid base registers.
5439 Reload deals with the cases where the eliminated form isn't valid. */
5444 }
5446 /* Return true if X is a valid base register for mode MODE.
5447 STRICT_P is true if REG_OK_STRICT is in effect. */
5449 static bool
5451 {
5458 }
5460 /* Return true if address offset is a valid index. If it is, fill in INFO
5461 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
5463 static bool
5466 {
5468 rtx index;
5471 /* (reg:P) */
5474 {
5478 }
5479 /* (sign_extend:DI (reg:SI)) */
5484 {
5489 }
5490 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
5497 {
5502 }
5503 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
5510 {
5515 }
5516 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
5523 {
5531 }
5532 /* (and:DI (mult:DI (reg:DI) (const_int scale))
5533 (const_int 0xffffffff<<shift)) */
5540 {
5546 }
5547 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
5554 {
5562 }
5563 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
5564 (const_int 0xffffffff<<shift)) */
5571 {
5577 }
5578 /* (mult:P (reg:P) (const_int scale)) */
5583 {
5587 }
5588 /* (ashift:P (reg:P) (const_int shift)) */
5593 {
5597 }
5598 else
5607 {
5611 }
5612 else
5613 {
5618 }
5622 {
5627 }
5630 }
5632 /* Return true if MODE is one of the modes for which we
5633 support LDP/STP operations. */
5635 static bool
5637 {
5642 }
5644 /* Return true if REGNO is a virtual pointer register, or an eliminable
5645 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
5646 include stack_pointer or hard_frame_pointer. */
5647 static bool
5649 {
5654 }
5656 /* Return true if X is a valid address of type TYPE for machine mode MODE.
5657 If it is, fill in INFO appropriately. STRICT_P is true if
5658 REG_OK_STRICT is in effect. */
5660 static bool
5664 {
5667 poly_int64 offset;
5669 HOST_WIDE_INT const_size;
5671 /* On BE, we use load/store pair for all large int mode load/stores.
5672 TI/TFmode may also use a load/store pair. */
5685 /* For SVE, only accept [Rn], [Rn, Rm, LSL #shift] and
5686 [Rn, #offset, MUL VL]. */
5691 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
5692 REG addressing. */
5694 && !BYTES_BIG_ENDIAN
5702 {
5719 {
5726 }
5731 {
5737 /* TImode and TFmode values are allowed in both pairs of X
5738 registers and individual Q registers. The available
5739 address modes are:
5740 X,X: 7-bit signed scaled offset
5741 Q: 9-bit signed offset
5742 We conservatively require an offset representable in either mode.
5743 When performing the check for pairs of X registers i.e. LDP/STP
5744 pass down DImode since that is the natural size of the LDP/STP
5745 instruction memory accesses. */
5751 /* A 7bit offset check because OImode will emit a ldp/stp
5752 instruction (only big endian will get here).
5753 For ldp/stp instructions, the offset is scaled for the size of a
5754 single element of the pair. */
5758 /* Three 9/12 bit offsets checks because CImode will emit three
5759 ldr/str instructions (only big endian will get here). */
5766 /* Two 7bit offsets checks because XImode will emit two ldp/stp
5767 instructions (only big endian will get here). */
5773 /* Make "m" use the LD1 offset range for SVE data modes, so
5774 that pre-RTL optimizers like ivopts will work to that
5775 instead of the wider LDR/STR range. */
5782 {
5783 poly_int64 end_offset = (offset
5790 end_offset)));
5791 }
5800 else
5803 }
5806 {
5807 /* Look for base + (scaled/extended) index register. */
5810 {
5813 }
5816 {
5819 }
5820 }
5841 {
5845 /* TImode and TFmode values are allowed in both pairs of X
5846 registers and individual Q registers. The available
5847 address modes are:
5848 X,X: 7-bit signed scaled offset
5849 Q: 9-bit signed offset
5850 We conservatively require an offset representable in either mode.
5851 */
5860 else
5862 }
5868 /* load literal: pc-relative constant pool entry. Only supported
5869 for SI mode or larger. */
5875 {
5883 }
5892 {
5898 {
5899 /* The symbol and offset must be aligned to the access size. */
5905 {
5909 }
5915 else
5924 }
5925 }
5930 }
5931 }
5933 /* Return true if the address X is valid for a PRFM instruction.
5934 STRICT_P is true if we should do strict checking with
5935 aarch64_classify_address. */
5937 bool
5939 {
5942 /* PRFM accepts the same addresses as DImode... */
5947 /* ... except writeback forms. */
5949 }
5951 bool
5953 {
5954 rtx offset;
5958 }
5960 /* Classify the base of symbolic expression X. */
5962 enum aarch64_symbol_type
5964 {
5965 rtx offset;
5969 }
5972 /* Return TRUE if X is a legitimate address for accessing memory in
5973 mode MODE. */
5974 static bool
5976 {
5980 }
5982 /* Return TRUE if X is a legitimate address of type TYPE for accessing
5983 memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
5984 bool
5986 aarch64_addr_query_type type)
5987 {
5991 }
5993 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
5995 static bool
5997 poly_int64 orig_offset,
5998 machine_mode mode)
5999 {
6000 HOST_WIDE_INT size;
6002 {
6005 /* A general SVE offset is A * VQ + B. Remove the A component from
6006 coefficient 0 in order to get the constant B. */
6009 /* Split an out-of-range address displacement into a base and
6010 offset. Use 4KB range for 1- and 2-byte accesses and a 16KB
6011 range otherwise to increase opportunities for sharing the base
6012 address of different sizes. Unaligned accesses use the signed
6013 9-bit range, TImode/TFmode use the intersection of signed
6014 scaled 7-bit and signed 9-bit offset. */
6019 else
6025 /* Split the offset into second_offset and the rest. */
6029 }
6030 else
6031 {
6032 /* Get the mode we should use as the basis of the range. For structure
6033 modes this is the mode of one vector. */
6035 machine_mode step_mode
6038 /* Get the "mul vl" multiplier we'd like to use. */
6042 /* LDR supports a 9-bit range, but the move patterns for
6043 structure modes require all vectors to be in range of the
6044 same base. The simplest way of accomodating that while still
6045 promoting reuse of anchor points between different modes is
6046 to use an 8-bit range unconditionally. */
6048 else
6049 /* Predicates are only handled singly, so we might as well use
6050 the full range. */
6055 /* Convert the "mul vl" multiplier into a byte offset. */
6060 /* Split the offset into second_offset and the rest. */
6064 }
6065 }
6067 /* Return the binary representation of floating point constant VALUE in INTVAL.
6068 If the value cannot be converted, return false without setting INTVAL.
6069 The conversion is done in the given MODE. */
6070 bool
6072 {
6074 /* We make a general exception for 0. */
6076 {
6079 }
6081 scalar_float_mode mode;
6085 /* Only support up to DF mode. */
6097 {
6101 }
6102 else
6107 }
6109 /* Return TRUE if rtx X is an immediate constant that can be moved using a
6110 single MOV(+MOVK) followed by an FMOV. */
6111 bool
6113 {
6118 /* Determine whether it's cheaper to write float constants as
6119 mov/movk pairs over ldr/adrp pairs. */
6125 {
6127 ? SImode
6132 }
6135 }
6137 /* Return TRUE if rtx X is immediate constant 0.0 */
6138 bool
6140 {
6147 }
6149 /* Return TRUE if rtx X is immediate constant that fits in a single
6150 MOVI immediate operation. */
6151 bool
6153 {
6157 machine_mode vmode;
6158 scalar_int_mode imode;
6163 {
6167 /* We make a general exception for 0. */
6172 }
6176 else
6179 /* use a 64 bit mode for everything except for DI/DF mode, where we use
6180 a 128 bit vector mode. */
6187 }
6190 /* Return the fixed registers used for condition codes. */
6192 static bool
6194 {
6198 }
6200 /* This function is used by the call expanders of the machine description.
6201 RESULT is the register in which the result is returned. It's NULL for
6202 "call" and "sibcall".
6203 MEM is the location of the function call.
6204 SIBCALL indicates whether this function call is normal call or sibling call.
6205 It will generate different pattern accordingly. */
6207 void
6209 {
6211 rtvec vec;
6212 machine_mode mode;
6219 /* Decide if we should generate indirect calls by loading the
6220 address of the callee into a register before performing
6221 the branch-and-link. */
6235 else
6242 }
6244 /* Emit call insn with PAT and do aarch64-specific handling. */
6246 void
6248 {
6254 }
6256 machine_mode
6258 {
6259 /* All floating point compares return CCFP if it is an equality
6260 comparison, and CCFPE otherwise. */
6262 {
6264 {
6285 }
6286 }
6288 /* Equality comparisons of short modes against zero can be performed
6289 using the TST instruction with the appropriate bitmask. */
6295 /* Similarly, comparisons of zero_extends from shorter modes can
6296 be performed using an ANDS with an immediate mask. */
6312 /* A compare with a shifted operand. Because of canonicalization,
6313 the comparison will have to be swapped when we emit the assembly
6314 code. */
6322 /* Similarly for a negated operand, but we can only do this for
6323 equalities. */
6330 /* A test for unsigned overflow. */
6337 /* For everything else, return CCmode. */
6339 }
6341 static int
6344 int
6346 {
6353 }
6355 static int
6357 {
6359 {
6363 {
6377 }
6382 {
6394 }
6399 {
6411 }
6416 {
6422 }
6427 {
6431 }
6436 {
6440 }
6445 }
6448 }
6450 bool
6452 HOST_WIDE_INT minval,
6453 HOST_WIDE_INT maxval)
6454 {
6455 rtx elt;
6459 }
6461 bool
6463 {
6465 }
6467 /* Return true if VEC is a constant in which every element is in the range
6468 [MINVAL, MAXVAL]. The elements do not need to have the same value. */
6470 static bool
6472 HOST_WIDE_INT minval,
6473 HOST_WIDE_INT maxval)
6474 {
6486 {
6491 }
6493 }
6495 /* N Z C V. */
6496 #define AARCH64_CC_V 1
6497 #define AARCH64_CC_C (1 << 1)
6498 #define AARCH64_CC_Z (1 << 2)
6499 #define AARCH64_CC_N (1 << 3)
6501 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
6503 {
6520 };
6522 /* Print floating-point vector immediate operand X to F, negating it
6523 first if NEGATE is true. Return true on success, false if it isn't
6524 a constant we can handle. */
6526 static bool
6528 {
6529 rtx elt;
6538 /* We only handle the SVE single-bit immediates here. */
6545 else
6549 }
6551 /* Return the equivalent letter for size. */
6552 static char
6554 {
6556 {
6562 }
6563 }
6565 /* Print operand X to file F in a target specific manner according to CODE.
6566 The acceptable formatting commands given by CODE are:
6567 'c': An integer or symbol address without a preceding #
6568 sign.
6569 'C': Take the duplicated element in a vector constant
6570 and print it in hex.
6571 'D': Take the duplicated element in a vector constant
6572 and print it as an unsigned integer, in decimal.
6573 'e': Print the sign/zero-extend size as a character 8->b,
6574 16->h, 32->w.
6575 'p': Prints N such that 2^N == X (X must be power of 2 and
6576 const int).
6577 'P': Print the number of non-zero bits in X (a const_int).
6578 'H': Print the higher numbered register of a pair (TImode)
6579 of regs.
6580 'm': Print a condition (eq, ne, etc).
6581 'M': Same as 'm', but invert condition.
6582 'N': Take the duplicated element in a vector constant
6583 and print the negative of it in decimal.
6584 'b/h/s/d/q': Print a scalar FP/SIMD register name.
6585 'S/T/U/V': Print a FP/SIMD register name for a register list.
6586 The register printed is the FP/SIMD register name
6587 of X + 0/1/2/3 for S/T/U/V.
6588 'R': Print a scalar FP/SIMD register name + 1.
6589 'X': Print bottom 16 bits of integer constant in hex.
6590 'w/x': Print a general register name or the zero register
6591 (32-bit or 64-bit).
6592 '0': Print a normal operand, if it's a general register,
6593 then we assume DImode.
6594 'k': Print NZCV for conditional compare instructions.
6595 'A': Output address constant representing the first
6596 argument of X, specifying a relocation offset
6597 if appropriate.
6598 'L': Output constant address specified by X
6599 with a relocation offset if appropriate.
6600 'G': Prints address of X, specifying a PC relative
6601 relocation mode if appropriate.
6602 'y': Output address of LDP or STP - this is used for
6603 some LDP/STPs which don't use a PARALLEL in their
6604 pattern (so the mode needs to be adjusted).
6605 'z': Output address of a typical LDP or STP. */
6607 static void
6609 {
6610 rtx elt;
6612 {
6615 {
6627 {
6630 }
6631 /* Fall through. */
6635 }
6639 {
6644 {
6647 }
6650 {
6663 }
6664 }
6668 {
6672 {
6675 }
6678 }
6683 {
6686 }
6693 {
6696 }
6703 {
6705 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
6707 {
6711 }
6714 {
6717 }
6724 }
6729 {
6732 }
6738 ;
6739 else
6740 {
6743 }
6752 {
6753 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6755 }
6764 {
6765 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6767 }
6775 {
6776 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6778 }
6784 {
6787 }
6792 {
6793 /* Print a replicated constant in hex. */
6795 {
6798 }
6801 }
6805 {
6806 /* Print a replicated constant in decimal, treating it as
6807 unsigned. */
6809 {
6812 }
6815 }
6822 {
6825 }
6828 {
6831 }
6834 {
6837 }
6839 /* Fall through */
6843 {
6846 }
6849 {
6852 {
6855 else
6856 {
6857 char suffix
6862 }
6863 }
6864 else
6883 {
6886 }
6887 /* fall through */
6891 {
6894 }
6900 ;
6901 else
6902 {
6905 }
6909 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
6910 be getting CONST_DOUBLEs holding integers. */
6913 {
6916 }
6918 {
6919 #define buf_size 20
6927 #undef buf_size
6928 }
6934 }
6942 {
6969 }
6975 {
7010 }
7016 {
7022 }
7027 {
7028 HOST_WIDE_INT cond_code;
7031 {
7034 }
7039 }
7044 {
7049 {
7052 }
7055 /* LDP/STP which uses a single double-width memory operand.
7056 Adjust the mode to appear like a typical LDP/STP.
7057 Currently this is supported for 16-byte accesses only. */
7062 }
7068 }
7069 }
7071 /* Print address 'x' of a memory access with mode 'mode'.
7072 'op' is the context required by aarch64_classify_address. It can either be
7073 MEM for a normal memory access or PARALLEL for LDP/STP. */
7074 static bool
7076 aarch64_addr_query_type type)
7077 {
7081 /* Check all addresses are Pmode - including ILP32. */
7087 {
7092 {
7093 HOST_WIDE_INT vnum
7098 }
7100 {
7101 HOST_WIDE_INT vnum
7106 }
7107 else
7116 else
7125 else
7134 else
7140 /* Writeback is only supported for fixed-width modes. */
7143 {
7166 }
7178 }
7181 }
7183 /* Print address 'x' of a LDP/STP with mode 'mode'. */
7184 static bool
7186 {
7188 }
7190 /* Print address 'x' of a memory access with mode 'mode'. */
7191 static void
7193 {
7196 }
7198 bool
7200 {
7207 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
7208 referencing instruction, but they are constant offsets, not
7209 symbols. */
7215 {
7217 {
7223 }
7226 }
7229 }
7231 /* Implement REGNO_REG_CLASS. */
7233 enum reg_class
7235 {
7253 }
7255 /* OFFSET is an address offset for mode MODE, which has SIZE bytes.
7256 If OFFSET is out of range, return an offset of an anchor point
7257 that is in range. Return 0 otherwise. */
7259 static HOST_WIDE_INT
7261 machine_mode mode)
7262 {
7263 /* Does it look like we'll need a 16-byte load/store-pair operation? */
7267 /* For offsets that aren't a multiple of the access size, the limit is
7268 -256...255. */
7270 {
7271 /* BLKmode typically uses LDP of X-registers. */
7275 }
7277 /* Small negative offsets are supported. */
7284 /* Use 12-bit offset by access size. */
7286 }
7288 static rtx
7290 {
7291 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
7292 where mask is selected by alignment and size of the offset.
7293 We try to pick as large a range for the offset as possible to
7294 maximize the chance of a CSE. However, for aligned addresses
7295 we limit the range to 4k so that structures with different sized
7296 elements are likely to use the same base. We need to be careful
7297 not to split a CONST for some forms of address expression, otherwise
7298 it will generate sub-optimal code. */
7301 {
7307 {
7311 /* Force any scaling into a temp for CSE. */
7315 /* Let the pointer register be in op0. */
7319 /* If the pointer is virtual or frame related, then we know that
7320 virtual register instantiation or register elimination is going
7321 to apply a second constant. We want the two constants folded
7322 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
7324 {
7328 }
7330 /* Otherwise, in order to encourage CSE (and thence loop strength
7331 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
7335 }
7337 HOST_WIDE_INT size;
7339 {
7341 mode);
7343 {
7347 }
7348 }
7349 }
7352 }
7354 /* Return the reload icode required for a constant pool in mode. */
7355 static enum insn_code
7357 {
7359 {
7395 }
7398 }
7399 static reg_class_t
7401 reg_class_t rclass,
7402 machine_mode mode,
7404 {
7405 /* Use aarch64_sve_reload_be for SVE reloads that cannot be handled
7406 directly by the *aarch64_sve_mov<mode>_be move pattern. See the
7407 comment at the head of aarch64-sve.md for more details about the
7408 big-endian handling. */
7414 {
7417 }
7419 /* If we have to disable direct literal pool loads and stores because the
7420 function is too big, then we need a scratch register. */
7425 {
7428 }
7430 /* Without the TARGET_SIMD instructions we cannot move a Q register
7431 to a Q register directly. We need a scratch. */
7435 {
7441 }
7443 /* A TFmode or TImode memory access should be handled via an FP_REGS
7444 because AArch64 has richer addressing modes for LDR/STR instructions
7445 than LDP/STP instructions. */
7454 }
7456 static bool
7458 {
7461 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
7462 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
7466 }
7468 poly_int64
7470 {
7474 {
7481 }
7484 {
7488 }
7491 }
7493 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
7494 previous frame. */
7496 rtx
7498 {
7502 }
7505 static void
7507 {
7509 {
7512 }
7513 else
7514 {
7517 }
7522 }
7524 static void
7526 {
7530 /* Don't need to copy the trailing D-words, we fill those in below. */
7542 /* XXX We should really define a "clear_cache" pattern and use
7543 gen_clear_cache(). */
7548 ptr_mode);
7549 }
7551 static unsigned char
7553 {
7554 /* ??? Logically we should only need to provide a value when
7555 HARD_REGNO_MODE_OK says that at least one register in REGCLASS
7556 can hold MODE, but at the moment we need to handle all modes.
7557 Just ignore any runtime parts for registers that can't store them. */
7561 {
7587 }
7589 }
7591 static reg_class_t
7593 {
7598 {
7604 }
7606 /* Register eliminiation can result in a request for
7607 SP+constant->FP_REGS. We cannot support such operations which
7608 use SP as source and an FP_REG as destination, so reject out
7609 right now. */
7611 {
7614 /* Look through a possible SUBREG introduced by ILP32. */
7620 POINTER_REGS));
7622 }
7625 }
7627 void
7629 {
7631 }
7633 static void
7635 {
7638 else
7639 {
7641 /* While priority is known to be in range [0, 65535], so 18 bytes
7642 would be enough, the compiler might not know that. To avoid
7643 -Wformat-truncation false positive, use a larger size. */
7650 }
7651 }
7653 static void
7655 {
7658 else
7659 {
7661 /* While priority is known to be in range [0, 65535], so 18 bytes
7662 would be enough, the compiler might not know that. To avoid
7663 -Wformat-truncation false positive, use a larger size. */
7670 }
7671 }
7675 {
7681 {
7682 {
7685 },
7686 {
7689 },
7690 {
7693 },
7694 /* We assume that DImode is only generated when not optimizing and
7695 that we don't really need 64-bit address offsets. That would
7696 imply an object file with 8GB of code in a single function! */
7697 {
7700 }
7701 };
7710 /* Need to implement table size reduction, by chaning the code below. */
7720 }
7723 /* Return size in bits of an arithmetic operand which is shifted/scaled and
7724 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
7725 operator. */
7727 int
7729 {
7731 {
7734 {
7738 }
7739 }
7741 }
7743 /* Constant pools are per function only when PC relative
7744 literal loads are true or we are in the large memory
7745 model. */
7749 {
7752 }
7754 static bool
7756 {
7757 /* We can't use blocks for constants when we're using a per-function
7758 constant pool. */
7760 }
7762 /* Select appropriate section for constants depending
7763 on where we place literal pools. */
7767 rtx x,
7769 {
7774 }
7776 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
7777 void
7779 HOST_WIDE_INT offset)
7780 {
7781 /* When using per-function literal pools, we must ensure that any code
7782 section is aligned to the minimal instruction length, lest we get
7783 errors from the assembler re "unaligned instructions". */
7786 }
7788 /* Costs. */
7790 /* Helper function for rtx cost calculation. Strip a shift expression
7791 from X. Returns the inner operand if successful, or the original
7792 expression on failure. */
7793 static rtx
7795 {
7798 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
7799 we can convert both to ROR during final output. */
7814 }
7816 /* Helper function for rtx cost calculation. Strip an extend
7817 expression from X. Returns the inner operand if successful, or the
7818 original expression on failure. We deal with a number of possible
7819 canonicalization variations here. If STRIP_SHIFT is true, then
7820 we can strip off a shift also. */
7821 static rtx
7823 {
7824 scalar_int_mode mode;
7830 /* Zero and sign extraction of a widened value. */
7838 /* It can also be represented (for zero-extend) as an AND with an
7839 immediate. */
7848 /* Now handle extended register, as this may also have an optional
7849 left shift by 1..4. */
7864 }
7866 /* Return true iff CODE is a shift supported in combination
7867 with arithmetic instructions. */
7869 static bool
7871 {
7873 }
7876 /* Return true iff X is a cheap shift without a sign extend. */
7878 static bool
7880 {
7906 }
7908 /* Helper function for rtx cost calculation. Calculate the cost of
7909 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
7910 Return the calculated cost of the expression, recursing manually in to
7911 operands where needed. */
7913 static int
7915 {
7931 /* Integer multiply/fma. */
7933 {
7934 /* The multiply will be canonicalized as a shift, cost it as such. */
7938 {
7942 {
7944 {
7945 /* If the shift is considered cheap,
7946 then don't add any cost. */
7948 ;
7950 /* ARITH + shift-by-register. */
7953 /* ARITH + extended register. We don't have a cost field
7954 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
7956 else
7957 /* ARITH + shift-by-immediate. */
7959 }
7960 else
7961 /* LSL (immediate). */
7964 }
7965 /* Strip extends as we will have costed them in the case above. */
7972 }
7974 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
7975 compound and let the below cases handle it. After all, MNEG is a
7976 special-case alias of MSUB. */
7978 {
7981 }
7983 /* Integer multiplies or FMAs have zero/sign extending variants. */
7988 {
7993 {
7995 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
7997 else
7998 /* MUL/SMULL/UMULL. */
8000 }
8003 }
8005 /* This is either an integer multiply or a MADD. In both cases
8006 we want to recurse and cost the operands. */
8011 {
8013 /* MADD/MSUB. */
8015 else
8016 /* MUL. */
8018 }
8021 }
8022 else
8023 {
8025 {
8026 /* Floating-point FMA/FMUL can also support negations of the
8027 operands, unless the rounding mode is upward or downward in
8028 which case FNMUL is different than FMUL with operand negation. */
8032 {
8037 }
8040 /* FMADD/FNMADD/FNMSUB/FMSUB. */
8042 else
8043 /* FMUL/FNMUL. */
8045 }
8050 }
8051 }
8053 static int
8055 machine_mode mode,
8056 addr_space_t as ATTRIBUTE_UNUSED,
8058 {
8066 {
8068 {
8069 /* This is a CONST or SYMBOL ref which will be split
8070 in a different way depending on the code model in use.
8071 Cost it through the generic infrastructure. */
8073 /* Divide through by the cost of one instruction to
8074 bring it to the same units as the address costs. */
8076 /* The cost is then the cost of preparing the address,
8077 followed by an immediate (possibly 0) offset. */
8079 }
8080 else
8081 {
8082 /* This is most likely a jump table from a case
8083 statement. */
8085 }
8086 }
8089 {
8101 else
8120 }
8124 {
8125 /* For the sake of calculating the cost of the shifted register
8126 component, we can treat same sized modes in the same way. */
8133 else
8134 /* We can't tell, or this is a 128-bit vector. */
8136 }
8139 }
8141 /* Return the cost of a branch. If SPEED_P is true then the compiler is
8142 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
8143 to be taken. */
8145 int
8147 {
8148 /* When optimizing for speed, use the cost of unpredictable branches. */
8154 else
8156 }
8158 /* Return true if the RTX X in mode MODE is a zero or sign extract
8159 usable in an ADD or SUB (extended register) instruction. */
8160 static bool
8162 {
8163 /* Catch add with a sign extract.
8164 This is add_<optab><mode>_multp2. */
8167 {
8178 op1))
8179 {
8181 }
8182 }
8183 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
8184 No shift. */
8190 }
8192 static bool
8194 {
8196 {
8208 }
8209 }
8211 /* Return true iff X is an rtx that will match an extr instruction
8212 i.e. as described in the *extr<mode>5_insn family of patterns.
8213 OP0 and OP1 will be set to the operands of the shifts involved
8214 on success and will be NULL_RTX otherwise. */
8216 static bool
8218 {
8220 scalar_int_mode mode;
8235 {
8236 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
8248 {
8252 }
8253 }
8256 }
8258 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
8259 storing it in *COST. Result is true if the total cost of the operation
8260 has now been calculated. */
8261 static bool
8263 {
8264 rtx inner;
8265 rtx comparator;
8269 {
8273 }
8274 else
8275 {
8279 }
8282 {
8283 /* Conditional branch. */
8286 else
8287 {
8289 {
8291 {
8292 /* TBZ/TBNZ/CBZ/CBNZ. */
8294 /* TBZ/TBNZ. */
8297 else
8298 /* CBZ/CBNZ. */
8302 }
8303 }
8305 {
8306 /* TBZ/TBNZ. */
8309 }
8310 }
8311 }
8313 {
8314 /* CCMP. */
8316 {
8317 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
8321 {
8328 else
8330 }
8332 }
8334 /* It's a conditional operation based on the status flags,
8335 so it must be some flavor of CSEL. */
8337 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
8343 {
8344 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
8347 }
8352 }
8354 /* We don't know what this is, cost all operands. */
8356 }
8358 /* Check whether X is a bitfield operation of the form shift + extend that
8359 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
8360 operand to which the bitfield operation is applied. Otherwise return
8361 NULL_RTX. */
8363 static rtx
8365 {
8379 {
8397 }
8400 }
8402 /* Return true if the mask and a shift amount from an RTX of the form
8403 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
8404 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
8406 bool
8408 rtx shft_amnt)
8409 {
8414 }
8416 /* Calculate the cost of calculating X, storing it in *COST. Result
8417 is true if the total cost of the operation has now been calculated. */
8418 static bool
8421 {
8426 scalar_int_mode int_mode;
8428 /* By default, assume that everything has equivalent cost to the
8429 cheapest instruction. Any additional costs are applied as a delta
8430 above this default. */
8434 {
8436 /* The cost depends entirely on the operands to SET. */
8442 {
8445 {
8459 }
8468 /* Fall through. */
8470 /* The cost is one per vector-register copied. */
8472 {
8475 }
8476 /* const0_rtx is in general free, but we will use an
8477 instruction to set a register to 0. */
8479 {
8480 /* The cost is 1 per register copied. */
8483 }
8484 else
8485 /* Cost is just the cost of the RHS of the set. */
8491 /* Bit-field insertion. Strip any redundant widening of
8492 the RHS to meet the width of the target. */
8503 {
8504 /* MOV immediate is assumed to always be cheap. */
8506 }
8507 else
8508 {
8509 /* BFM. */
8513 }
8518 /* We can't make sense of this, assume default cost. */
8521 }
8525 /* If an instruction can incorporate a constant within the
8526 instruction, the instruction's expression avoids calling
8527 rtx_cost() on the constant. If rtx_cost() is called on a
8528 constant, then it is usually because the constant must be
8529 moved into a register by one or more instructions.
8531 The exception is constant 0, which can be expressed
8532 as XZR/WZR and is therefore free. The exception to this is
8533 if we have (set (reg) (const0_rtx)) in which case we must cost
8534 the move. However, we can catch that when we cost the SET, so
8535 we don't need to consider that here. */
8538 else
8539 {
8540 /* To an approximation, building any other constant is
8541 proportionally expensive to the number of instructions
8542 required to build that constant. This is true whether we
8543 are compiling for SPEED or otherwise. */
8548 }
8553 /* First determine number of instructions to do the move
8554 as an integer constant. */
8558 {
8564 ? SImode
8570 }
8573 {
8574 /* mov[df,sf]_aarch64. */
8576 /* FMOV (scalar immediate). */
8579 {
8580 /* This will be a load from memory. */
8583 else
8585 }
8586 else
8587 /* Otherwise this is +0.0. We get this using MOVI d0, #0
8588 or MOV v0.s[0], wzr - neither of which are modeled by the
8589 cost tables. Just use the default cost. */
8590 {
8591 }
8592 }
8598 {
8599 /* For loads we want the base cost of a load, plus an
8600 approximation for the additional cost of the addressing
8601 mode. */
8615 }
8623 {
8625 {
8626 /* FNEG. */
8628 }
8630 }
8633 {
8636 {
8637 /* CSETM. */
8640 }
8642 /* Cost this as SUB wzr, X. */
8646 }
8649 {
8650 /* Support (neg(fma...)) as a single instruction only if
8651 sign of zeros is unimportant. This matches the decision
8652 making in aarch64.md. */
8654 {
8655 /* FNMADD. */
8658 }
8660 {
8661 /* FNMUL. */
8664 }
8666 /* FNEG. */
8669 }
8676 {
8679 else
8681 }
8691 {
8695 }
8698 {
8699 /* TODO: A write to the CC flags possibly costs extra, this
8700 needs encoding in the cost tables. */
8703 /* ANDS. */
8705 {
8708 }
8711 {
8712 /* ADDS (and CMN alias). */
8715 }
8718 {
8719 /* SUBS. */
8722 }
8727 {
8728 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
8729 Handle it here directly rather than going to cost_logic
8730 since we know the immediate generated for the TST is valid
8731 so we can avoid creating an intermediate rtx for it only
8732 for costing purposes. */
8739 }
8742 {
8743 /* CMN. */
8750 }
8752 /* CMP.
8754 Compare can freely swap the order of operands, and
8755 canonicalization puts the more complex operation first.
8756 But the integer MINUS logic expects the shift/extend
8757 operation in op1. */
8760 {
8763 }
8765 }
8768 {
8769 /* FCMP. */
8774 {
8776 /* FCMP supports constant 0.0 for no extra cost. */
8778 }
8780 }
8783 {
8784 /* Vector compare. */
8789 {
8790 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
8791 cost. */
8793 }
8795 }
8799 {
8803 cost_minus:
8806 /* Detect valid immediates. */
8812 {
8814 /* SUB(S) (immediate). */
8817 }
8819 /* Look for SUB (extended register). */
8822 {
8830 }
8834 /* Cost this as an FMA-alike operation. */
8838 {
8841 speed);
8843 }
8848 {
8850 {
8851 /* Vector SUB. */
8853 }
8855 {
8856 /* SUB(S). */
8858 }
8860 {
8861 /* FSUB. */
8863 }
8864 }
8866 }
8869 {
8870 rtx new_op0;
8875 cost_plus:
8878 {
8879 /* CSINC. */
8883 }
8888 {
8892 /* ADD (immediate). */
8895 }
8899 /* Look for ADD (extended register). */
8902 {
8910 }
8912 /* Strip any extend, leave shifts behind as we will
8913 cost them through mult_cost. */
8918 {
8920 speed);
8922 }
8927 {
8929 {
8930 /* Vector ADD. */
8932 }
8934 {
8935 /* ADD. */
8937 }
8939 {
8940 /* FADD. */
8942 }
8943 }
8945 }
8951 {
8954 else
8956 }
8961 {
8965 {
8968 else
8970 }
8972 }
8975 {
8982 }
8983 /* Fall through. */
8986 cost_logic:
8991 {
8995 }
9003 {
9004 /* This is a UBFM/SBFM. */
9009 }
9012 {
9014 {
9015 /* We have a mask + shift version of a UBFIZ
9016 i.e. the *andim_ashift<mode>_bfiz pattern. */
9020 {
9027 }
9029 {
9030 /* We possibly get the immediate for free, this is not
9031 modelled. */
9038 }
9039 }
9040 else
9041 {
9044 /* Handle ORN, EON, or BIC. */
9050 /* If we had a shift on op0 then this is a logical-shift-
9051 by-register/immediate operation. Otherwise, this is just
9052 a logical operation. */
9054 {
9056 {
9057 /* Shift by immediate. */
9060 else
9062 }
9063 else
9065 }
9067 /* In both cases we want to cost both operands. */
9074 }
9075 }
9083 {
9084 /* Vector NOT. */
9087 }
9089 /* MVN-shifted-reg. */
9091 {
9098 }
9099 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
9100 Handle the second form here taking care that 'a' in the above can
9101 be a shift. */
9103 {
9112 {
9115 else
9117 }
9120 }
9121 /* MVN. */
9130 /* If a value is written in SI mode, then zero extended to DI
9131 mode, the operation will in general be free as a write to
9132 a 'w' register implicitly zeroes the upper bits of an 'x'
9133 register. However, if this is
9135 (set (reg) (zero_extend (reg)))
9137 we must cost the explicit register move. */
9141 {
9144 /* If OP_COST is non-zero, then the cost of the zero extend
9145 is effectively the cost of the inner operation. Otherwise
9146 we have a MOV instruction and we take the cost from the MOV
9147 itself. This is true independently of whether we are
9148 optimizing for space or time. */
9153 }
9155 {
9156 /* All loads can zero extend to any size for free. */
9159 }
9163 {
9168 }
9171 {
9173 {
9174 /* UMOV. */
9176 }
9177 else
9178 {
9179 /* We generate an AND instead of UXTB/UXTH. */
9181 }
9182 }
9187 {
9188 /* LDRSH. */
9190 {
9197 }
9199 }
9203 {
9208 }
9211 {
9214 else
9216 }
9224 {
9226 {
9228 {
9229 /* Vector shift (immediate). */
9231 }
9232 else
9233 {
9234 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
9235 aliases. */
9237 }
9238 }
9240 /* We can incorporate zero/sign extend for free. */
9247 }
9248 else
9249 {
9251 {
9253 /* Vector shift (register). */
9255 }
9256 else
9257 {
9259 /* LSLV. */
9266 {
9268 /* We already demanded XEXP (op1, 0) to be REG_P, so
9269 don't recurse into it. */
9271 }
9272 }
9274 }
9284 {
9285 /* ASR (immediate) and friends. */
9287 {
9290 else
9292 }
9296 }
9297 else
9298 {
9300 {
9302 /* Vector shift (register). */
9304 }
9305 else
9306 {
9308 /* ASR (register) and friends. */
9315 {
9317 /* We already demanded XEXP (op1, 0) to be REG_P, so
9318 don't recurse into it. */
9320 }
9321 }
9323 }
9329 {
9330 /* LDR. */
9333 }
9336 {
9337 /* ADRP, followed by ADD. */
9341 }
9344 {
9345 /* ADR. */
9348 }
9351 {
9352 /* One extra load instruction, after accessing the GOT. */
9356 }
9361 /* ADRP/ADD (immediate). */
9368 /* UBFX/SBFX. */
9370 {
9373 else
9375 }
9377 /* We can trust that the immediates used will be correct (there
9378 are no by-register forms), so we need only cost op0. */
9384 /* aarch64_rtx_mult_cost always handles recursion to its
9385 operands. */
9389 /* We can expand signed mod by power of 2 using a NEGS, two parallel
9390 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
9391 an unconditional negate. This case should only ever be reached through
9392 the set_smod_pow2_cheap check in expmed.c. */
9396 {
9397 /* We expand to 4 instructions. Reset the baseline. */
9405 }
9407 /* Fall-through. */
9410 {
9411 /* Slighly prefer UMOD over SMOD. */
9418 }
9425 {
9429 /* There is no integer SQRT, so only DIV and UDIV can get
9430 here. */
9432 /* Slighly prefer UDIV over SDIV. */
9434 else
9436 }
9462 {
9465 else
9467 }
9469 /* FMSUB, FNMADD, and FNMSUB are free. */
9476 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
9477 and the by-element operand as operand 0. */
9481 /* Catch vector-by-element operations. The by-element operand can
9482 either be (vec_duplicate (vec_select (x))) or just
9483 (vec_select (x)), depending on whether we are multiplying by
9484 a vector or a scalar.
9486 Canonicalization is not very good in these cases, FMA4 will put the
9487 by-element operand as operand 0, FNMA4 will have it as operand 1. */
9498 /* If the remaining parameters are not registers,
9499 get the cost to put them into registers. */
9513 {
9515 {
9516 /*Vector truncate. */
9518 }
9519 else
9521 }
9526 {
9528 {
9529 /*Vector conversion. */
9531 }
9532 else
9534 }
9540 /* Strip the rounding part. They will all be implemented
9541 by the fcvt* family of instructions anyway. */
9543 {
9552 }
9555 {
9558 else
9560 }
9562 /* We can combine fmul by a power of 2 followed by a fcvt into a single
9563 fixed-point fcvt. */
9568 {
9572 }
9579 {
9580 /* ABS (vector). */
9583 }
9585 {
9588 /* FABD, which is analogous to FADD. */
9590 {
9597 }
9598 /* Simple FABS is analogous to FNEG. */
9601 }
9602 else
9603 {
9604 /* Integer ABS will either be split to
9605 two arithmetic instructions, or will be an ABS
9606 (scalar), which we don't model. */
9610 }
9616 {
9619 else
9620 {
9621 /* FMAXNM/FMINNM/FMAX/FMIN.
9622 TODO: This may not be accurate for all implementations, but
9623 we do not model this in the cost tables. */
9625 }
9626 }
9630 /* The floating point round to integer frint* instructions. */
9632 {
9637 }
9640 {
9645 }
9650 /* Decompose <su>muldi3_highpart. */
9652 mode == DImode
9653 /* (lshiftrt:TI */
9656 /* (mult:TI */
9658 /* (ANY_EXTEND:TI (reg:DI))
9659 (ANY_EXTEND:TI (reg:DI))) */
9666 /* (const_int 64) */
9669 {
9670 /* UMULH/SMULH. */
9678 }
9680 /* Fall through. */
9683 }
9691 }
9693 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
9694 calculated for X. This cost is stored in *COST. Returns true
9695 if the total cost of X was calculated. */
9696 static bool
9699 {
9704 {
9709 }
9712 }
9714 static int
9717 {
9723 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
9730 /* Moving between GPR and stack cost is the same as GP2GP. */
9735 /* To/From the stack register, we move via the gprs. */
9741 {
9742 /* 128-bit operations on general registers require 2 instructions. */
9750 /* When AdvSIMD instructions are disabled it is not possible to move
9751 a 128-bit value directly between Q registers. This is handled in
9752 secondary reload. A general register is used as a scratch to move
9753 the upper DI value and the lower DI value is moved directly,
9754 hence the cost is the sum of three moves. */
9759 }
9769 }
9771 static int
9773 reg_class_t rclass ATTRIBUTE_UNUSED,
9775 {
9777 }
9779 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
9780 to optimize 1.0/sqrt. */
9782 static bool
9784 {
9786 && flag_unsafe_math_optimizations
9790 }
9792 /* Function to decide when to use the approximate reciprocal square root
9793 builtin. */
9795 static tree
9797 {
9803 }
9807 /* Select reciprocal square root initial estimate insn depending on machine
9808 mode. */
9810 static rsqrte_type
9812 {
9814 {
9821 }
9822 }
9826 /* Select reciprocal square root series step insn depending on machine mode. */
9828 static rsqrts_type
9830 {
9832 {
9839 }
9840 }
9842 /* Emit instruction sequence to compute either the approximate square root
9843 or its approximate reciprocal, depending on the flag RECP, and return
9844 whether the sequence was emitted or not. */
9846 bool
9848 {
9852 {
9855 }
9858 {
9865 || flag_trapping_math
9866 || !flag_unsafe_math_optimizations
9869 }
9870 else
9871 /* Caller assumes we cannot fail. */
9877 /* When calculating the approximate square root, compare the
9878 argument with 0.0 and create a mask. */
9884 /* Estimate the approximate reciprocal square root. */
9888 /* Iterate over the series twice for SF and thrice for DF. */
9891 /* Optionally iterate over the series once less for faster performance
9892 while sacrificing the accuracy. */
9895 iterations--;
9897 /* Iterate over the series to calculate the approximate reciprocal square
9898 root. */
9901 {
9909 }
9912 {
9913 /* Qualify the approximate reciprocal square root when the argument is
9914 0.0 by squashing the intermediary result to 0.0. */
9920 /* Calculate the approximate square root. */
9922 }
9924 /* Finalize the approximation. */
9928 }
9932 /* Select reciprocal initial estimate insn depending on machine mode. */
9934 static recpe_type
9936 {
9938 {
9945 }
9946 }
9950 /* Select reciprocal series step insn depending on machine mode. */
9952 static recps_type
9954 {
9956 {
9963 }
9964 }
9966 /* Emit the instruction sequence to compute the approximation for the division
9967 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
9969 bool
9971 {
9982 || flag_trapping_math
9983 || !flag_unsafe_math_optimizations
9991 /* Estimate the approximate reciprocal. */
9995 /* Iterate over the series twice for SF and thrice for DF. */
9998 /* Optionally iterate over the series once less for faster performance,
9999 while sacrificing the accuracy. */
10001 iterations--;
10003 /* Iterate over the series to calculate the approximate reciprocal. */
10006 {
10011 }
10014 {
10015 /* As the approximate reciprocal of DEN is already calculated, only
10016 calculate the approximate division when NUM is not 1.0. */
10019 }
10021 /* Finalize the approximation. */
10024 }
10026 /* Return the number of instructions that can be issued per cycle. */
10027 static int
10029 {
10031 }
10033 static int
10035 {
10039 }
10042 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
10043 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
10044 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
10046 static int
10049 {
10051 }
10054 /* Vectorizer cost model target hooks. */
10056 /* Implement targetm.vectorize.builtin_vectorization_cost. */
10057 static int
10059 tree vectype,
10061 {
10070 {
10121 }
10122 }
10124 /* Implement targetm.vectorize.add_stmt_cost. */
10125 static unsigned
10129 {
10134 {
10139 /* Statements in an inner loop relative to the loop being
10140 vectorized are weighted more heavily. The value here is
10141 arbitrary and could potentially be improved with analysis. */
10147 }
10150 }
10154 /* Parse the TO_PARSE string and put the architecture struct that it
10155 selects into RES and the architectural features into ISA_FLAGS.
10156 Return an aarch64_parse_opt_result describing the parse result.
10157 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
10159 static enum aarch64_parse_opt_result
10162 {
10174 else
10181 /* Loop through the list of supported ARCHes to find a match. */
10183 {
10185 {
10189 {
10190 /* TO_PARSE string contains at least one extension. */
10191 enum aarch64_parse_opt_result ext_res
10196 }
10197 /* Extension parsing was successful. Confirm the result
10198 arch and ISA flags. */
10202 }
10203 }
10205 /* ARCH name not found in list. */
10207 }
10209 /* Parse the TO_PARSE string and put the result tuning in RES and the
10210 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
10211 describing the parse result. If there is an error parsing, RES and
10212 ISA_FLAGS are left unchanged. */
10214 static enum aarch64_parse_opt_result
10217 {
10229 else
10236 /* Loop through the list of supported CPUs to find a match. */
10238 {
10240 {
10245 {
10246 /* TO_PARSE string contains at least one extension. */
10247 enum aarch64_parse_opt_result ext_res
10252 }
10253 /* Extension parsing was successfull. Confirm the result
10254 cpu and ISA flags. */
10258 }
10259 }
10261 /* CPU name not found in list. */
10263 }
10265 /* Parse the TO_PARSE string and put the cpu it selects into RES.
10266 Return an aarch64_parse_opt_result describing the parse result.
10267 If the parsing fails the RES does not change. */
10269 static enum aarch64_parse_opt_result
10271 {
10277 /* Loop through the list of supported CPUs to find a match. */
10279 {
10281 {
10284 }
10285 }
10287 /* CPU name not found in list. */
10289 }
10291 /* Parse TOKEN, which has length LENGTH to see if it is an option
10292 described in FLAG. If it is, return the index bit for that fusion type.
10293 If not, error (printing OPTION_NAME) and return zero. */
10295 static unsigned int
10300 {
10302 {
10306 }
10310 }
10312 /* Parse OPTION which is a comma-separated list of flags to enable.
10313 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
10314 default state we inherit from the CPU tuning structures. OPTION_NAME
10315 gives the top-level option we are parsing in the -moverride string,
10316 for use in error messages. */
10318 static unsigned int
10323 {
10330 {
10333 token_length,
10334 flags,
10335 option_name);
10336 /* If we find "none" (or, for simplicity's sake, an error) anywhere
10337 in the token stream, reset the supported operations. So:
10339 adrp+add.cmp+branch.none.adrp+add
10341 would have the result of turning on only adrp+add fusion. */
10347 }
10349 /* We ended with a comma, print something. */
10351 {
10354 }
10356 /* We still have one more token to parse. */
10359 token_length,
10360 flags,
10361 option_name);
10367 }
10369 /* Support for overriding instruction fusion. */
10371 static void
10374 {
10376 aarch64_fusible_pairs,
10379 }
10381 /* Support for overriding other tuning flags. */
10383 static void
10386 {
10387 tune->extra_tuning_flags
10389 aarch64_tuning_flags,
10392 }
10394 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
10395 we understand. If it is, extract the option string and handoff to
10396 the appropriate function. */
10398 void
10402 {
10408 {
10411 }
10413 /* Get the length of the option name. */
10415 /* Skip the '=' to get to the option string. */
10416 option_part++;
10419 {
10421 {
10424 }
10425 }
10429 }
10431 /* A checking mechanism for the implementation of the tls size. */
10433 static void
10435 {
10440 {
10442 /* Both the default and maximum TLS size allowed under tiny is 1M which
10443 needs two instructions to address, so we clamp the size to 24. */
10448 /* The maximum TLS size allowed under small is 4G. */
10453 /* The maximum TLS size allowed under large is 16E.
10454 FIXME: 16E should be 64bit, we only support 48bit offset now. */
10460 }
10463 }
10465 /* Parse STRING looking for options in the format:
10466 string :: option:string
10467 option :: name=substring
10468 name :: {a-z}
10469 substring :: defined by option. */
10471 static void
10474 {
10485 {
10487 /* Make this substring look like a string. */
10491 }
10493 /* One last option to parse. */
10496 }
10499 static void
10501 {
10502 /* PR 70044: We have to be careful about being called multiple times for the
10503 same function. This means all changes should be repeatable. */
10505 /* If the frame pointer is enabled, set it to a special value that behaves
10506 similar to frame pointer omission. If we don't do this all leaf functions
10507 will get a frame pointer even if flag_omit_leaf_frame_pointer is set.
10508 If flag_omit_frame_pointer has this special value, we must force the
10509 frame pointer if not in a leaf function. We also need to force it in a
10510 leaf function if flag_omit_frame_pointer is not set or if LR is used. */
10514 /* If not optimizing for size, set the default
10515 alignment to what the target wants. */
10517 {
10524 }
10526 /* We default to no pc-relative literal loads. */
10530 /* If -mpc-relative-literal-loads is set on the command line, this
10531 implies that the user asked for PC relative literal loads. */
10535 /* In the tiny memory model it makes no sense to disallow PC relative
10536 literal pool loads. */
10541 /* When enabling the lower precision Newton series for the square root, also
10542 enable it for the reciprocal square root, since the latter is an
10543 intermediary step for the former. */
10546 }
10548 /* 'Unpack' up the internal tuning structs and update the options
10549 in OPTS. The caller must have set up selected_tune and selected_arch
10550 as all the other target-specific codegen decisions are
10551 derived from them. */
10553 void
10555 {
10558 /* Make a copy of the tuning parameters attached to the core, which
10559 we may later overwrite. */
10567 /* This target defaults to strict volatile bitfields. */
10576 {
10588 }
10590 /* We don't mind passing in global_options_set here as we don't use
10591 the *options_set structs anyway. */
10593 queue_depth,
10597 /* Set up parameters to be used in prefetching algorithm. Do not
10598 override the defaults unless we are tuning for a core we have
10599 researched values for. */
10621 /* Use the alternative scheduling-pressure algorithm by default. */
10626 /* Enable sw prefetching at specified optimization level for
10627 CPUS that have prefetch. Lower optimization level threshold by 1
10628 when profiling is enabled. */
10636 }
10638 /* Print a hint with a suggestion for a core or architecture name that
10639 most closely resembles what the user passed in STR. ARCH is true if
10640 the user is asking for an architecture name. ARCH is false if the user
10641 is asking for a core name. */
10643 static void
10645 {
10651 #ifdef HAVE_LOCAL_CPU_DETECT
10652 /* Add also "native" as possible value. */
10655 #endif
10662 else
10666 }
10668 /* Print a hint with a suggestion for a core name that most closely resembles
10669 what the user passed in STR. */
10673 {
10675 }
10677 /* Print a hint with a suggestion for an architecture name that most closely
10678 resembles what the user passed in STR. */
10682 {
10684 }
10686 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
10687 specified in STR and throw errors if appropriate. Put the results if
10688 they are valid in RES and ISA_FLAGS. Return whether the option is
10689 valid. */
10691 static bool
10694 {
10695 enum aarch64_parse_opt_result parse_res
10702 {
10715 }
10718 }
10720 /* Validate a command-line -march option. Parse the arch and extensions
10721 (if any) specified in STR and throw errors if appropriate. Put the
10722 results, if they are valid, in RES and ISA_FLAGS. Return whether the
10723 option is valid. */
10725 static bool
10728 {
10729 enum aarch64_parse_opt_result parse_res
10736 {
10749 }
10752 }
10754 /* Validate a command-line -mtune option. Parse the cpu
10755 specified in STR and throw errors if appropriate. Put the
10756 result, if it is valid, in RES. Return whether the option is
10757 valid. */
10759 static bool
10761 {
10762 enum aarch64_parse_opt_result parse_res
10769 {
10779 }
10781 }
10783 /* Return the CPU corresponding to the enum CPU.
10784 If it doesn't specify a cpu, return the default. */
10788 {
10792 /* The & 0x3f is to extract the bottom 6 bits that encode the
10793 default cpu as selected by the --with-cpu GCC configure option
10794 in config.gcc.
10795 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
10796 flags mechanism should be reworked to make it more sane. */
10798 }
10800 /* Return the architecture corresponding to the enum ARCH.
10801 If it doesn't specify a valid architecture, return the default. */
10805 {
10812 }
10814 /* Return the VG value associated with -msve-vector-bits= value VALUE. */
10816 static poly_uint16
10818 {
10819 /* For now generate vector-length agnostic code for -msve-vector-bits=128.
10820 This ensures we can clearly distinguish SVE and Advanced SIMD modes when
10821 deciding which .md file patterns to use and when deciding whether
10822 something is a legitimate address or constant. */
10825 else
10827 }
10829 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
10830 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
10831 tuning structs. In particular it must set selected_tune and
10832 aarch64_isa_flags that define the available ISA features and tuning
10833 decisions. It must also set selected_arch as this will be used to
10834 output the .arch asm tags for each function. */
10836 static void
10838 {
10851 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
10852 If either of -march or -mtune is given, they override their
10853 respective component of -mcpu. */
10865 /* If the user did not specify a processor, choose the default
10866 one for them. This will be the CPU set during configuration using
10867 --with-cpu, otherwise it is "generic". */
10869 {
10871 {
10875 }
10876 else
10877 {
10878 /* Get default configure-time CPU. */
10881 }
10885 }
10886 /* If both -mcpu and -march are specified check that they are architecturally
10887 compatible, warn if they're not and prefer the -march ISA flags. */
10889 {
10891 {
10895 }
10900 }
10901 else
10902 {
10903 /* -mcpu but no -march. */
10910 }
10912 /* Set the arch as well as we will need it when outputing
10913 the .arch directive in assembly. */
10915 {
10918 }
10923 #ifndef HAVE_AS_MABI_OPTION
10924 /* The compiler may have been configured with 2.23.* binutils, which does
10925 not have support for ILP32. */
10928 #endif
10930 /* Convert -msve-vector-bits to a VG count. */
10936 /* Make sure we properly set up the explicit options. */
10947 /* Save these options as the default ones in case we push and pop them later
10948 while processing functions with potential target attributes. */
10949 target_option_default_node = target_option_current_node
10951 }
10953 /* Implement targetm.override_options_after_change. */
10955 static void
10957 {
10959 }
10963 {
10967 }
10969 void
10971 {
10973 }
10975 /* A checking mechanism for the implementation of the various code models. */
10976 static void
10978 {
10980 {
10982 {
10987 #ifdef HAVE_AS_SMALL_PIC_RELOCS
10989 ? AARCH64_CMODEL_SMALL_PIC
10991 #else
10993 #endif
11001 }
11002 }
11003 else
11005 }
11007 /* Implement TARGET_OPTION_SAVE. */
11009 static void
11011 {
11013 }
11015 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
11016 using the information saved in PTR. */
11018 static void
11020 {
11028 }
11030 /* Implement TARGET_OPTION_PRINT. */
11032 static void
11034 {
11045 }
11049 void
11051 {
11053 }
11055 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
11056 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
11057 make sure optab availability predicates are recomputed when necessary. */
11059 void
11061 {
11066 else
11068 }
11070 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
11071 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
11072 of the function, if such exists. This function may be called multiple
11073 times on a single function so use aarch64_previous_fndecl to avoid
11074 setting up identical state. */
11076 static void
11078 {
11082 tree old_tree = (aarch64_previous_fndecl
11088 /* If current function has no attributes but the previous one did,
11089 use the default node. */
11093 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
11094 the default have been handled by aarch64_save_restore_target_globals from
11095 aarch64_pragma_target_parse. */
11101 /* First set the target options. */
11105 }
11107 /* Enum describing the various ways we can handle attributes.
11108 In many cases we can reuse the generic option handling machinery. */
11110 enum aarch64_attr_opt_type
11111 {
11115 aarch64_attr_custom /* Attribute requires a custom handling function. */
11116 };
11118 /* All the information needed to handle a target attribute.
11119 NAME is the name of the attribute.
11120 ATTR_TYPE specifies the type of behavior of the attribute as described
11121 in the definition of enum aarch64_attr_opt_type.
11122 ALLOW_NEG is true if the attribute supports a "no-" form.
11123 HANDLER is the function that takes the attribute string as an argument
11124 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
11125 OPT_NUM is the enum specifying the option that the attribute modifies.
11126 This is needed for attributes that mirror the behavior of a command-line
11127 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
11128 aarch64_attr_enum. */
11130 struct aarch64_attribute_info
11131 {
11137 };
11139 /* Handle the ARCH_STR argument to the arch= target attribute. */
11141 static bool
11143 {
11145 enum aarch64_parse_opt_result parse_res
11149 {
11154 }
11157 {
11170 }
11173 }
11175 /* Handle the argument CPU_STR to the cpu= target attribute. */
11177 static bool
11179 {
11181 enum aarch64_parse_opt_result parse_res
11185 {
11193 }
11196 {
11209 }
11212 }
11214 /* Handle the argument STR to the tune= target attribute. */
11216 static bool
11218 {
11220 enum aarch64_parse_opt_result parse_res
11224 {
11229 }
11232 {
11239 }
11242 }
11244 /* Parse an architecture extensions target attribute string specified in STR.
11245 For example "+fp+nosimd". Show any errors if needed. Return TRUE
11246 if successful. Update aarch64_isa_flags to reflect the ISA features
11247 modified. */
11249 static bool
11251 {
11255 /* We allow "+nothing" in the beginning to clear out all architectural
11256 features if the user wants to handpick specific features. */
11258 {
11261 }
11266 {
11269 }
11272 {
11283 }
11286 }
11288 /* The target attributes that we support. On top of these we also support just
11289 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
11290 handled explicitly in aarch64_process_one_target_attr. */
11293 {
11295 OPT_mgeneral_regs_only },
11297 OPT_mfix_cortex_a53_835769 },
11299 OPT_mfix_cortex_a53_843419 },
11303 OPT_momit_leaf_frame_pointer },
11306 OPT_march_ },
11309 OPT_mtune_ },
11311 OPT_msign_return_address_ },
11313 };
11315 /* Parse ARG_STR which contains the definition of one target attribute.
11316 Show appropriate errors if any or return true if the attribute is valid. */
11318 static bool
11320 {
11326 {
11329 }
11334 /* Skip leading whitespace. */
11336 str_to_check++;
11338 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
11339 It is easier to detect and handle it explicitly here rather than going
11340 through the machinery for the rest of the target attributes in this
11341 function. */
11346 {
11349 }
11352 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
11353 and point ARG to "foo". */
11355 {
11357 arg++;
11358 }
11362 {
11363 /* If the names don't match up, or the user has given an argument
11364 to an attribute that doesn't accept one, or didn't give an argument
11365 to an attribute that expects one, fail to match. */
11374 {
11377 }
11379 /* If the name matches but the attribute does not allow "no-" versions
11380 then we can't match. */
11382 {
11385 }
11388 {
11389 /* Has a custom handler registered.
11390 For example, cpu=, arch=, tune=. */
11397 /* Either set or unset a boolean option. */
11399 {
11407 }
11408 /* Set or unset a bit in the target_flags. aarch64_handle_option
11409 should know what mask to apply given the option number. */
11411 {
11413 /* We only need to specify the option number.
11414 aarch64_handle_option will know which mask to apply. */
11420 }
11421 /* Use the option setting machinery to set an option to an enum. */
11423 {
11430 {
11433 global_dc);
11434 }
11435 else
11436 {
11438 }
11440 }
11443 }
11444 }
11446 /* If we reached here we either have found an attribute and validated
11447 it or didn't match any. If we matched an attribute but its arguments
11448 were malformed we will have returned false already. */
11450 }
11452 /* Count how many times the character C appears in
11453 NULL-terminated string STR. */
11455 static unsigned int
11457 {
11460 {
11462 res++;
11464 str++;
11465 }
11468 }
11470 /* Parse the tree in ARGS that contains the target attribute information
11471 and update the global target options space. */
11473 bool
11475 {
11477 {
11478 do
11479 {
11482 {
11485 }
11490 }
11493 {
11496 }
11503 {
11506 }
11508 /* Used to catch empty spaces between commas i.e.
11509 attribute ((target ("attr1,,attr2"))). */
11512 /* Handle multiple target attributes separated by ','. */
11517 {
11518 num_attrs++;
11520 {
11523 }
11526 }
11529 {
11532 }
11535 }
11537 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
11538 process attribute ((target ("..."))). */
11540 static bool
11542 {
11545 tree old_optimize;
11549 /* If what we're processing is the current pragma string then the
11550 target option node is already stored in target_option_current_node
11551 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
11552 having to re-parse the string. This is especially useful to keep
11553 arm_neon.h compile times down since that header contains a lot
11554 of intrinsics enclosed in pragmas. */
11556 {
11559 }
11565 /* If the function changed the optimization levels as well as setting
11566 target options, start with the optimizations specified. */
11571 /* Save the current target options to restore at the end. */
11574 /* If fndecl already has some target attributes applied to it, unpack
11575 them so that we add this attribute on top of them, rather than
11576 overwriting them. */
11578 {
11584 }
11585 else
11591 /* Set up any additional state. */
11593 {
11595 /* Initialize SIMD builtins if we haven't already.
11596 Set current_target_pragma to NULL for the duration so that
11597 the builtin initialization code doesn't try to tag the functions
11598 being built with the attributes specified by any current pragma, thus
11599 going into an infinite recursion. */
11601 {
11606 }
11608 }
11609 else
11615 {
11620 }
11628 }
11630 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
11631 tri-bool options (yes, no, don't care) and the default value is
11632 DEF, determine whether to reject inlining. */
11634 static bool
11637 {
11638 /* If the callee doesn't care, always allow inlining. */
11642 /* If the caller doesn't care, always allow inlining. */
11646 /* Otherwise, allow inlining if either the callee and caller values
11647 agree, or if the callee is using the default value. */
11649 }
11651 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
11652 to inline CALLEE into CALLER based on target-specific info.
11653 Make sure that the caller and callee have compatible architectural
11654 features. Then go through the other possible target attributes
11655 and see if they can block inlining. Try not to reject always_inline
11656 callees unless they are incompatible architecturally. */
11658 static bool
11660 {
11664 /* If callee has no option attributes, then it is ok to inline. */
11675 /* Callee's ISA flags should be a subset of the caller's. */
11680 /* Allow non-strict aligned functions inlining into strict
11681 aligned ones. */
11691 /* If the architectural features match up and the callee is always_inline
11692 then the other attributes don't matter. */
11704 /* Honour explicit requests to workaround errata. */
11717 /* If the user explicitly specified -momit-leaf-frame-pointer for the
11718 caller and calle and they don't match up, reject inlining. */
11725 /* If the callee has specific tuning overrides, respect them. */
11730 /* If the user specified tuning override strings for the
11731 caller and callee and they don't match up, reject inlining.
11732 We just do a string compare here, we don't analyze the meaning
11733 of the string, as it would be too costly for little gain. */
11741 }
11743 /* Return true if SYMBOL_REF X binds locally. */
11745 static bool
11747 {
11751 }
11753 /* Return true if SYMBOL_REF X is thread local */
11754 static bool
11756 {
11764 }
11766 /* Classify a TLS symbol into one of the TLS kinds. */
11767 enum aarch64_symbol_type
11769 {
11773 {
11780 {
11786 }
11797 else
11806 }
11807 }
11809 /* Return the correct method for accessing X + OFFSET, where X is either
11810 a SYMBOL_REF or LABEL_REF. */
11812 enum aarch64_symbol_type
11814 {
11816 {
11818 {
11833 }
11834 }
11837 {
11842 {
11844 /* When we retrieve symbol + offset address, we have to make sure
11845 the offset does not cause overflow of the final address. But
11846 we have no way of knowing the address of symbol at compile time
11847 so we can't accurately say if the distance between the PC and
11848 symbol + offset is outside the addressible range of +/-1M in the
11849 TINY code model. So we rely on images not being greater than
11850 1M and cap the offset at 1M and anything beyond 1M will have to
11851 be loaded using an alternative mechanism. Furthermore if the
11852 symbol is a weak reference to something that isn't known to
11853 resolve to a symbol in this module, then force to memory. */
11861 /* Same reasoning as the tiny code model, but the offset cap here is
11862 4G. */
11883 /* This is alright even in PIC code as the constant
11884 pool reference is always PC relative and within
11885 the same translation unit. */
11888 else
11893 }
11894 }
11896 /* By default push everything into the constant pool. */
11898 }
11900 bool
11902 {
11904 }
11906 bool
11908 {
11916 }
11918 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
11919 that should be rematerialized rather than spilled. */
11921 static bool
11923 {
11924 /* Support CSE and rematerialization of common constants. */
11930 /* Do not allow vector struct mode constants for Advanced SIMD.
11931 We could support 0 and -1 easily, but they need support in
11932 aarch64-simd.md. */
11937 /* Only accept variable-length vector constants if they can be
11938 handled directly.
11940 ??? It would be possible to handle rematerialization of other
11941 constants via secondary reloads. */
11948 /* Accept polynomial constants that can be calculated by using the
11949 destination of a move as the sole temporary. Constants that
11950 require a second temporary cannot be rematerialized (they can't be
11951 forced to memory and also aren't legitimate constants). */
11952 poly_int64 offset;
11956 /* If an offset is being added to something else, we need to allow the
11957 base to be moved into the destination register, meaning that there
11958 are no free temporaries for the offset. */
11963 /* Do not allow const (plus (anchor_symbol, const_int)). */
11967 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
11968 so spilling them is better than rematerialization. */
11972 /* Label references are always constant. */
11977 }
11979 rtx
11981 {
11987 /* Can return in any reg. */
11990 }
11992 /* On AAPCS systems, this is the "struct __va_list". */
11995 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
11996 Return the type to use as __builtin_va_list.
11998 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
12000 struct __va_list
12001 {
12002 void *__stack;
12003 void *__gr_top;
12004 void *__vr_top;
12005 int __gr_offs;
12006 int __vr_offs;
12007 }; */
12009 static tree
12011 {
12012 tree va_list_name;
12015 /* Create the type. */
12017 /* Give it the required name. */
12019 TYPE_DECL,
12021 va_list_type);
12026 /* Create the fields. */
12029 ptr_type_node);
12032 ptr_type_node);
12035 ptr_type_node);
12038 integer_type_node);
12041 integer_type_node);
12043 /* Tell tree-stdarg pass about our internal offset fields.
12044 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
12045 purpose to identify whether the code is updating va_list internal
12046 offset fields through irregular way. */
12068 /* Compute its layout. */
12072 }
12074 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
12075 static void
12077 {
12081 tree t;
12095 {
12098 }
12107 NULL_TREE);
12109 NULL_TREE);
12111 NULL_TREE);
12113 NULL_TREE);
12115 NULL_TREE);
12117 /* Emit code to initialize STACK, which points to the next varargs stack
12118 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
12119 by named arguments. STACK is 8-byte aligned. */
12126 /* Emit code to initialize GRTOP, the top of the GR save area.
12127 virtual_incoming_args_rtx should have been 16 byte aligned. */
12132 /* Emit code to initialize VRTOP, the top of the VR save area.
12133 This address is gr_save_area_bytes below GRTOP, rounded
12134 down to the next 16-byte boundary. */
12144 /* Emit code to initialize GROFF, the offset from GRTOP of the
12145 next GPR argument. */
12150 /* Likewise emit code to initialize VROFF, the offset from FTOP
12151 of the next VR argument. */
12155 }
12157 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
12159 static tree
12162 {
12163 tree addr;
12169 machine_mode mode;
12196 type,
12200 {
12201 /* No frontends can create types with variable-sized modes, so we
12202 shouldn't be asked to pass or return them. */
12205 /* TYPE passed in fp/simd registers. */
12217 {
12220 }
12223 {
12225 }
12226 }
12227 else
12228 {
12229 /* TYPE passed in general registers. */
12242 {
12244 }
12245 }
12247 /* Get a local temporary for the field value. */
12250 /* Emit code to branch if off >= 0. */
12256 {
12257 /* Emit: offs = (offs + 15) & -16. */
12263 }
12264 else
12267 /* Update ap.__[g|v]r_offs */
12272 /* String up. */
12276 /* [cond2] if (ap.__[g|v]r_offs > 0) */
12281 /* String up: make sure the assignment happens before the use. */
12285 /* Prepare the trees handling the argument that is passed on the stack;
12286 the top level node will store in ON_STACK. */
12289 {
12290 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
12295 }
12296 else
12298 /* Advance ap.__stack */
12303 /* String up roundup and advance. */
12306 /* String up with arg */
12308 /* Big-endianness related address adjustment. */
12311 {
12315 }
12320 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
12330 {
12331 /* type ha; // treat as "struct {ftype field[n];}"
12332 ... [computing offs]
12333 for (i = 0; i <nregs; ++i, offs += 16)
12334 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
12335 return ha; */
12339 /* Declare a local variable. */
12343 /* Establish the base type. */
12345 {
12364 {
12368 }
12372 }
12374 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
12382 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
12384 {
12394 }
12398 }
12408 }
12410 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
12412 static void
12416 {
12418 CUMULATIVE_ARGS local_cum;
12422 /* The caller has advanced CUM up to, but not beyond, the last named
12423 argument. Advance a local copy of CUM past the last "real" named
12424 argument, to find out how many registers are left over. */
12428 /* Found out how many registers we need to save.
12429 Honor tree-stdvar analysis results. */
12438 {
12441 }
12444 {
12446 {
12449 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
12457 }
12459 {
12460 /* We can't use move_block_from_reg, because it will use
12461 the wrong mode, storing D regs only. */
12465 /* Set OFF to the offset from virtual_incoming_args_rtx of
12466 the first vector register. The VR save area lies below
12467 the GR one, and is aligned to 16 bytes. */
12474 {
12482 }
12483 }
12484 }
12486 /* We don't save the size into *PRETEND_SIZE because we want to avoid
12487 any complication of having crtl->args.pretend_args_size changed. */
12492 }
12494 static void
12496 {
12499 {
12501 {
12504 }
12505 }
12508 {
12511 }
12512 }
12514 /* Walk down the type tree of TYPE counting consecutive base elements.
12515 If *MODEP is VOIDmode, then set it to the first valid floating point
12516 type. If a non-floating point type is found, or if a floating point
12517 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
12518 otherwise return the count in the sub-tree. */
12519 static int
12521 {
12522 machine_mode mode;
12523 HOST_WIDE_INT size;
12526 {
12556 /* Use V2SImode and V4SImode as representatives of all 64-bit
12557 and 128-bit vector types. */
12560 {
12569 }
12574 /* Vector modes are considered to be opaque: two vectors are
12575 equivalent for the purposes of being homogeneous aggregates
12576 if they are the same size. */
12583 {
12587 /* Can't handle incomplete types nor sizes that are not
12588 fixed. */
12595 || !index
12606 /* There must be no padding. */
12612 }
12615 {
12618 tree field;
12620 /* Can't handle incomplete types nor sizes that are not
12621 fixed. */
12627 {
12635 }
12637 /* There must be no padding. */
12643 }
12647 {
12648 /* These aren't very interesting except in a degenerate case. */
12651 tree field;
12653 /* Can't handle incomplete types nor sizes that are not
12654 fixed. */
12660 {
12668 }
12670 /* There must be no padding. */
12676 }
12680 }
12683 }
12685 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
12686 type as described in AAPCS64 \S 4.1.2.
12688 See the comment above aarch64_composite_type_p for the notes on MODE. */
12690 static bool
12692 machine_mode mode)
12693 {
12703 }
12705 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
12706 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
12707 array types. The C99 floating-point complex types are also considered
12708 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
12709 types, which are GCC extensions and out of the scope of AAPCS64, are
12710 treated as composite types here as well.
12712 Note that MODE itself is not sufficient in determining whether a type
12713 is such a composite type or not. This is because
12714 stor-layout.c:compute_record_mode may have already changed the MODE
12715 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
12716 structure with only one field may have its MODE set to the mode of the
12717 field. Also an integer mode whose size matches the size of the
12718 RECORD_TYPE type may be used to substitute the original mode
12719 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
12720 solely relied on. */
12722 static bool
12724 machine_mode mode)
12725 {
12738 }
12740 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
12741 shall be passed or returned in simd/fp register(s) (providing these
12742 parameter passing registers are available).
12744 Upon successful return, *COUNT returns the number of needed registers,
12745 *BASE_MODE returns the mode of the individual register and when IS_HAF
12746 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
12747 floating-point aggregate or a homogeneous short-vector aggregate. */
12749 static bool
12751 const_tree type,
12755 {
12763 {
12766 }
12768 {
12772 }
12774 {
12778 {
12781 }
12782 else
12784 }
12785 else
12790 }
12792 /* Implement TARGET_STRUCT_VALUE_RTX. */
12794 static rtx
12797 {
12799 }
12801 /* Implements target hook vector_mode_supported_p. */
12802 static bool
12804 {
12807 }
12809 /* Return appropriate SIMD container
12810 for MODE within a vector of WIDTH bits. */
12811 static machine_mode
12813 {
12816 {
12833 }
12837 {
12840 {
12857 }
12858 else
12860 {
12873 }
12874 }
12876 }
12878 /* Return 128-bit container as the preferred SIMD mode for MODE. */
12879 static machine_mode
12881 {
12884 }
12886 /* Return a list of possible vector sizes for the vectorizer
12887 to iterate over. */
12888 static void
12890 {
12895 }
12897 /* Implement TARGET_MANGLE_TYPE. */
12901 {
12902 /* The AArch64 ABI documents say that "__va_list" has to be
12903 managled as if it is in the "std" namespace. */
12907 /* Half-precision float. */
12911 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
12912 builtin types. */
12916 /* Use the default mangling. */
12918 }
12920 /* Find the first rtx_insn before insn that will generate an assembly
12921 instruction. */
12925 {
12929 do
12930 {
12932 }
12936 }
12938 static bool
12940 {
12942 /* A number of these may be AArch32 only. */
12947 };
12950 {
12953 }
12956 }
12958 /* Check if there is a register dependency between a load and the insn
12959 for which we hold recog_data. */
12961 static bool
12963 {
12964 rtx load_reg;
12974 {
12980 }
12982 }
12985 /* When working around the Cortex-A53 erratum 835769,
12986 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
12987 instruction and has a preceding memory instruction such that a NOP
12988 should be inserted between them. */
12990 bool
12992 {
12995 rtx body;
13008 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
13009 Restore recog state to INSN to avoid state corruption. */
13017 /* If the previous insn is a memory op and there is no dependency between
13018 it and the DImode madd, emit a NOP between them. If body is NULL then we
13019 have a complex memory operation, probably a load/store pair.
13020 Be conservative for now and emit a NOP. */
13027 }
13030 /* Implement FINAL_PRESCAN_INSN. */
13032 void
13034 {
13037 }
13040 /* Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX
13041 instruction. */
13043 bool
13045 {
13048 }
13050 /* Return true if X is a valid immediate for the SVE ADD and SUB
13051 instructions. Negate X first if NEGATE_P is true. */
13053 bool
13055 {
13056 rtx elt;
13070 }
13072 /* Return true if X is a valid immediate operand for an SVE logical
13073 instruction such as AND. */
13075 bool
13077 {
13078 rtx elt;
13084 }
13086 /* Return true if X is a valid immediate for the SVE DUP and CPY
13087 instructions. */
13089 bool
13091 {
13092 rtx elt;
13102 }
13104 /* Return true if X is a valid immediate operand for an SVE CMP instruction.
13105 SIGNED_P says whether the operand is signed rather than unsigned. */
13107 bool
13109 {
13110 rtx elt;
13114 && (signed_p
13117 }
13119 /* Return true if X is a valid immediate operand for an SVE FADD or FSUB
13120 instruction. Negate X first if NEGATE_P is true. */
13122 bool
13124 {
13125 rtx elt;
13126 REAL_VALUE_TYPE r;
13142 }
13144 /* Return true if X is a valid immediate operand for an SVE FMUL
13145 instruction. */
13147 bool
13149 {
13150 rtx elt;
13152 /* GCC will never generate a multiply with an immediate of 2, so there is no
13153 point testing for it (even though it is a valid constant). */
13157 }
13159 /* Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate
13160 for the Advanced SIMD operation described by WHICH and INSN. If INFO
13161 is nonnull, use it to describe valid immediates. */
13162 static bool
13167 {
13168 /* Try a 4-byte immediate with LSL. */
13171 {
13176 }
13178 /* Try a 2-byte immediate with LSL. */
13183 {
13188 }
13190 /* Try a 4-byte immediate with MSL, except for cases that MVN
13191 can handle. */
13194 {
13197 {
13202 }
13203 }
13206 }
13208 /* Return true if replicating VAL64 is a valid immediate for the
13209 Advanced SIMD operation described by WHICH. If INFO is nonnull,
13210 use it to describe valid immediates. */
13211 static bool
13215 {
13221 {
13232 /* Try using a replicated byte. */
13236 {
13240 }
13241 }
13243 /* Try using a bit-to-bytemask. */
13245 {
13248 {
13252 }
13254 {
13258 }
13259 }
13261 }
13263 /* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
13264 instruction. If INFO is nonnull, use it to describe valid immediates. */
13266 static bool
13269 {
13273 {
13277 {
13282 }
13283 }
13286 {
13287 /* DUP with no shift. */
13291 }
13293 {
13294 /* DUP with LSL #8. */
13298 }
13300 {
13301 /* DUPM. */
13305 }
13307 }
13309 /* Return true if OP is a valid SIMD immediate for the operation
13310 described by WHICH. If INFO is nonnull, use it to describe valid
13311 immediates. */
13312 bool
13315 {
13329 {
13338 }
13342 else
13345 /* Handle PFALSE and PTRUE. */
13350 scalar_float_mode elt_float_mode;
13353 {
13357 {
13361 }
13362 }
13370 /* Expand the vector constant out into a byte vector, with the least
13371 significant byte of the register first. */
13375 {
13376 /* The vector is provided in gcc endian-neutral fashion.
13377 For aarch64_be Advanced SIMD, it must be laid out in the vector
13378 register in reverse order. */
13390 {
13393 }
13394 }
13396 /* The immediate must repeat every eight bytes. */
13402 /* Get the repeating 8-byte value as an integer. No endian correction
13403 is needed here because bytes is already in lsb-first order. */
13411 else
13413 }
13415 /* Check whether X is a VEC_SERIES-like constant that starts at 0 and
13416 has a step in the range of INDEX. Return the index expression if so,
13417 otherwise return null. */
13418 rtx
13420 {
13427 }
13429 /* Check of immediate shift constants are within range. */
13430 bool
13432 {
13436 else
13438 }
13440 /* Return the bitmask CONST_INT to select the bits required by a zero extract
13441 operation of width WIDTH at bit position POS. */
13443 rtx
13445 {
13449 unsigned HOST_WIDE_INT mask
13452 }
13454 bool
13456 {
13475 }
13477 /* Return a const_int vector of VAL. */
13478 rtx
13480 {
13483 }
13485 /* Check OP is a legal scalar immediate for the MOVI instruction. */
13487 bool
13489 {
13490 machine_mode vmode;
13495 }
13497 /* Construct and return a PARALLEL RTX vector with elements numbering the
13498 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
13499 the vector - from the perspective of the architecture. This does not
13500 line up with GCC's perspective on lane numbers, so we end up with
13501 different masks depending on our target endian-ness. The diagram
13502 below may help. We must draw the distinction when building masks
13503 which select one half of the vector. An instruction selecting
13504 architectural low-lanes for a big-endian target, must be described using
13505 a mask selecting GCC high-lanes.
13507 Big-Endian Little-Endian
13509 GCC 0 1 2 3 3 2 1 0
13510 | x | x | x | x | | x | x | x | x |
13511 Architecture 3 2 1 0 3 2 1 0
13513 Low Mask: { 2, 3 } { 0, 1 }
13514 High Mask: { 0, 1 } { 2, 3 }
13516 MODE Is the mode of the vector and NUNITS is the number of units in it. */
13518 rtx
13520 {
13525 rtx t1;
13530 else
13538 }
13540 /* Check OP for validity as a PARALLEL RTX vector with elements
13541 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
13542 from the perspective of the architecture. See the diagram above
13543 aarch64_simd_vect_par_cnst_half for more details. */
13545 bool
13548 {
13562 {
13569 }
13571 }
13573 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
13574 HIGH (exclusive). */
13575 void
13577 const_tree exp)
13578 {
13579 HOST_WIDE_INT lane;
13584 {
13587 else
13589 }
13590 }
13592 /* Peform endian correction on lane number N, which indexes a vector
13593 of mode MODE, and return the result as an SImode rtx. */
13595 rtx
13597 {
13599 }
13601 /* Return TRUE if OP is a valid vector addressing mode. */
13603 bool
13605 {
13608 }
13610 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */
13612 bool
13614 {
13616 scalar_mode mode;
13623 }
13625 /* Return true if OP is a valid MEM operand for an SVE LDR instruction.
13626 The conditions for STR are the same. */
13627 bool
13629 {
13636 }
13638 /* Return true if OP is a valid MEM operand for an SVE_STRUCT mode.
13639 We need to be able to access the individual pieces, so the range
13640 is different from LD[234] and ST[234]. */
13641 bool
13643 {
13650 ADDR_QUERY_ANY)
13658 }
13660 /* Emit a register copy from operand to operand, taking care not to
13661 early-clobber source registers in the process.
13663 COUNT is the number of components into which the copy needs to be
13664 decomposed. */
13665 void
13668 {
13678 else
13682 }
13684 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
13685 one of VSTRUCT modes: OI, CI, or XI. */
13686 int
13688 {
13689 /* This is only used (and only meaningful) for Advanced SIMD, not SVE. */
13691 }
13693 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
13694 alignment of a vector to 128 bits. SVE predicates have an alignment of
13695 16 bits. */
13696 static HOST_WIDE_INT
13698 {
13700 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
13701 be set for non-predicate vectors of booleans. Modes are the most
13702 direct way we have of identifying real SVE predicate types. */
13706 }
13708 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
13709 static HOST_WIDE_INT
13711 {
13713 {
13714 /* If the length of the vector is fixed, try to align to that length,
13715 otherwise don't try to align at all. */
13716 HOST_WIDE_INT result;
13720 }
13722 }
13724 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
13725 static bool
13727 {
13731 /* For fixed-length vectors, check that the vectorizer will aim for
13732 full-vector alignment. This isn't true for generic GCC vectors
13733 that are wider than the ABI maximum of 128 bits. */
13739 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
13741 }
13743 /* Return true if the vector misalignment factor is supported by the
13744 target. */
13745 static bool
13749 {
13751 {
13752 /* Return if movmisalign pattern is not supported for this mode. */
13756 /* Misalignment factor is unknown at compile time. */
13759 }
13761 is_packed);
13762 }
13764 /* If VALS is a vector constant that can be loaded into a register
13765 using DUP, generate instructions to do so and return an RTX to
13766 assign to the register. Otherwise return NULL_RTX. */
13767 static rtx
13769 {
13772 rtx x;
13777 /* We can load this constant by using DUP and a constant in a
13778 single ARM register. This will be cheaper than a vector
13779 load. */
13782 }
13785 /* Generate code to load VALS, which is a PARALLEL containing only
13786 constants (for vec_init) or CONST_VECTOR, efficiently into a
13787 register. Returns an RTX to copy into the register, or NULL_RTX
13788 for a PARALLEL that can not be converted into a CONST_VECTOR. */
13789 static rtx
13791 {
13793 rtx const_dup;
13801 {
13802 /* A CONST_VECTOR must contain only CONST_INTs and
13803 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
13804 Only store valid constants in a CONST_VECTOR. */
13807 {
13810 n_const++;
13811 }
13814 }
13815 else
13820 /* Load using MOVI/MVNI. */
13823 /* Loaded using DUP. */
13826 /* Load from constant pool. We can not take advantage of single-cycle
13827 LD1 because we need a PC-relative addressing mode. */
13829 else
13830 /* A PARALLEL containing something not valid inside CONST_VECTOR.
13831 We can not construct an initializer. */
13833 }
13835 /* Expand a vector initialisation sequence, such that TARGET is
13836 initialised to contain VALS. */
13838 void
13840 {
13843 /* The number of vector elements. */
13845 /* The number of vector elements which are not constant. */
13848 /* The first element of vals. */
13852 /* Count the number of variable elements to initialise. */
13854 {
13858 else
13862 }
13864 /* No variable elements, hand off to aarch64_simd_make_constant which knows
13865 how best to handle this. */
13867 {
13870 {
13873 }
13874 }
13876 /* Splat a single non-constant element if we can. */
13878 {
13882 }
13887 /* If there are only variable elements, try to optimize
13888 the insertion using dup for the most common element
13889 followed by insertions. */
13891 /* The algorithm will fill matches[*][0] with the earliest matching element,
13892 and matches[X][1] with the count of duplicate elements (if X is the
13893 earliest element which has duplicates). */
13896 {
13899 {
13901 {
13903 {
13907 }
13908 }
13909 }
13914 {
13917 }
13919 /* Create a duplicate of the most common element, unless all elements
13920 are equally useless to us, in which case just immediately set the
13921 vector register using the first element. */
13924 {
13925 /* For vectors of two 64-bit elements, we can do even better. */
13930 {
13933 /* Combine can pick up this case, but handling it directly
13934 here leaves clearer RTL.
13936 This is load_pair_lanes<mode>, and also gives us a clean-up
13937 for store_pair_lanes<mode>. */
13940 && !STRICT_ALIGNMENT
13945 {
13946 rtx t;
13949 else
13953 }
13954 }
13955 /* The subreg-move sequence below will move into lane zero of the
13956 vector register. For big-endian we want that position to hold
13957 the last element of VALS. */
13961 }
13962 else
13963 {
13966 }
13968 /* Insert the rest. */
13970 {
13976 }
13978 }
13980 /* Initialise a vector which is part-variable. We want to first try
13981 to build those lanes which are constant in the most efficient way we
13982 can. */
13984 {
13987 /* Load constant part of vector. We really don't care what goes into the
13988 parts we will overwrite, but we're more likely to be able to load the
13989 constant efficiently if it has fewer, larger, repeating parts
13990 (see aarch64_simd_valid_immediate). */
13992 {
13998 {
13999 /* Look in the copied vector, as more elements are const. */
14002 {
14005 }
14006 }
14008 }
14010 }
14012 /* Insert the variable lanes directly. */
14014 {
14020 }
14021 }
14023 static unsigned HOST_WIDE_INT
14025 {
14029 }
14031 /* Select a format to encode pointers in exception handling data. */
14032 int
14034 {
14037 {
14043 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
14044 for everything. */
14048 /* No assumptions here. 8-byte relocs required. */
14051 }
14053 }
14055 /* The last .arch and .tune assembly strings that we printed. */
14059 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
14060 by the function fndecl. */
14062 void
14064 tree fndecl)
14065 {
14071 else
14082 /* Only update the assembler .arch string if it is distinct from the last
14083 such string we printed. */
14086 {
14089 }
14091 /* Print the cpu name we're tuning for in the comments, might be
14092 useful to readers of the generated asm. Do it only when it changes
14093 from function to function and verbose assembly is requested. */
14098 {
14102 }
14104 /* Don't forget the type directive for ELF. */
14107 }
14109 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
14111 static void
14113 {
14130 }
14132 /* Emit load exclusive. */
14134 static void
14137 {
14141 {
14148 }
14151 }
14153 /* Emit store exclusive. */
14155 static void
14158 {
14162 {
14169 }
14172 }
14174 /* Mark the previous jump instruction as unlikely. */
14176 static void
14178 {
14181 }
14183 /* Expand a compare and swap pattern. */
14185 void
14187 {
14192 gen_cas_fn gen;
14194 {
14195 gen_aarch64_compare_and_swapqi,
14196 gen_aarch64_compare_and_swaphi,
14197 gen_aarch64_compare_and_swapsi,
14198 gen_aarch64_compare_and_swapdi
14199 };
14201 {
14202 gen_aarch64_compare_and_swapqi_lse,
14203 gen_aarch64_compare_and_swaphi_lse,
14204 gen_aarch64_compare_and_swapsi_lse,
14205 gen_aarch64_compare_and_swapdi_lse
14206 };
14219 /* Normally the succ memory model must be stronger than fail, but in the
14220 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
14221 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
14228 {
14231 /* For short modes, we're going to perform the comparison in SImode,
14232 so do the zero-extension now. */
14236 /* Fall through. */
14240 /* Force the value into a register if needed. */
14247 }
14250 {
14257 }
14260 else
14271 }
14273 /* Test whether the target supports using a atomic load-operate instruction.
14274 CODE is the operation and AFTER is TRUE if the data in memory after the
14275 operation should be returned and FALSE if the data before the operation
14276 should be returned. Returns FALSE if the operation isn't supported by the
14277 architecture. */
14279 bool
14281 {
14286 {
14296 }
14297 }
14299 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
14300 sequence implementing an atomic operation. */
14302 static void
14304 {
14311 {
14313 }
14314 }
14316 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
14317 for the data in memory. EXPECTED is the value expected to be in memory.
14318 DESIRED is the value to store to memory. MEM is the memory location. MODEL
14319 is the memory ordering to use. */
14321 void
14324 rtx model)
14325 {
14327 machine_mode mode;
14332 {
14339 }
14341 /* Move the expected value into the CAS destination register. */
14344 /* Emit the CAS. */
14347 /* Compare the expected value with the value loaded by the CAS, to establish
14348 whether the swap was made. */
14350 }
14352 /* Split a compare and swap pattern. */
14354 void
14356 {
14358 machine_mode mode;
14363 rtx model_rtx;
14375 /* When OLDVAL is zero and we want the strong version we can emit a tighter
14376 loop:
14377 .label1:
14378 LD[A]XR rval, [mem]
14379 CBNZ rval, .label2
14380 ST[L]XR scratch, newval, [mem]
14381 CBNZ scratch, .label1
14382 .label2:
14383 CMP rval, 0. */
14388 {
14391 }
14394 /* The initial load can be relaxed for a __sync operation since a final
14395 barrier will be emitted to stop code hoisting. */
14399 else
14403 {
14408 }
14409 else
14410 {
14416 }
14421 {
14426 }
14427 else
14428 {
14432 }
14435 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
14436 to set the condition flags. If this is not used it will be removed by
14437 later passes. */
14439 {
14443 }
14444 /* Emit any final barrier needed for a __sync operation. */
14447 }
14449 /* Emit a BIC instruction. */
14451 static void
14453 {
14458 {
14463 }
14466 }
14468 /* Emit an atomic swap. */
14470 static void
14473 {
14477 {
14484 }
14487 }
14489 /* Operations supported by aarch64_emit_atomic_load_op. */
14491 enum aarch64_atomic_load_op_code
14492 {
14496 AARCH64_LDOP_BIC /* A & ~B */
14497 };
14499 /* Emit an atomic load-operate. */
14501 static void
14505 {
14508 {
14509 gen_aarch64_atomic_loadaddqi,
14510 gen_aarch64_atomic_loadaddhi,
14511 gen_aarch64_atomic_loadaddsi,
14512 gen_aarch64_atomic_loadadddi
14513 };
14515 {
14516 gen_aarch64_atomic_loadeorqi,
14517 gen_aarch64_atomic_loadeorhi,
14518 gen_aarch64_atomic_loadeorsi,
14519 gen_aarch64_atomic_loadeordi
14520 };
14522 {
14523 gen_aarch64_atomic_loadsetqi,
14524 gen_aarch64_atomic_loadsethi,
14525 gen_aarch64_atomic_loadsetsi,
14526 gen_aarch64_atomic_loadsetdi
14527 };
14529 {
14530 gen_aarch64_atomic_loadclrqi,
14531 gen_aarch64_atomic_loadclrhi,
14532 gen_aarch64_atomic_loadclrsi,
14533 gen_aarch64_atomic_loadclrdi
14534 };
14535 aarch64_atomic_load_op_fn gen;
14539 {
14546 }
14549 {
14556 }
14559 }
14561 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
14562 location to store the data read from memory. OUT_RESULT is the location to
14563 store the result of the operation. MEM is the memory location to read and
14564 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
14565 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
14566 be NULL. */
14568 void
14571 {
14575 aarch64_atomic_load_op_code ldop_code;
14576 rtx src;
14577 rtx x;
14585 /* Make sure the value is in a register, putting it into a destination
14586 register if it needs to be manipulated. */
14589 {
14592 }
14593 else
14597 /* Preprocess the data for the operation as necessary. If the operation is
14598 a SET then emit a swap instruction and finish. */
14600 {
14606 /* Negate the value and treat it as a PLUS. */
14607 {
14608 rtx neg_src;
14610 /* Resize the value if necessary. */
14619 }
14620 /* Fall-through. */
14634 {
14635 rtx not_src;
14637 /* Resize the value if necessary. */
14646 }
14651 /* The operation can't be done with atomic instructions. */
14653 }
14657 /* If necessary, calculate the data in memory after the update by redoing the
14658 operation from values in registers. */
14663 {
14667 }
14672 {
14688 }
14693 }
14695 /* Split an atomic operation. */
14697 void
14700 {
14706 rtx x;
14708 /* Split the atomic operation into a sequence. */
14716 else
14720 /* The initial load can be relaxed for a __sync operation since a final
14721 barrier will be emitted to stop code hoisting. */
14725 else
14729 {
14743 {
14746 }
14747 /* Fall through. */
14753 }
14763 /* Emit any final barrier needed for a __sync operation. */
14766 }
14768 static void
14770 {
14771 /* Half-precision float operations. The compiler handles all operations
14772 with NULL libfuncs by converting to SFmode. */
14774 /* Conversions. */
14778 /* Arithmetic. */
14785 /* Comparisons. */
14793 }
14795 /* Target hook for c_mode_for_suffix. */
14796 static machine_mode
14798 {
14803 }
14805 /* We can only represent floating point constants which will fit in
14806 "quarter-precision" values. These values are characterised by
14807 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
14808 by:
14810 (-1)^s * (n/16) * 2^r
14812 Where:
14813 's' is the sign bit.
14814 'n' is an integer in the range 16 <= n <= 31.
14815 'r' is an integer in the range -3 <= r <= 4. */
14817 /* Return true iff X can be represented by a quarter-precision
14818 floating point immediate operand X. Note, we cannot represent 0.0. */
14819 bool
14821 {
14822 /* This represents our current view of how many bits
14823 make up the mantissa. */
14833 /* We don't support HFmode constants yet. */
14839 /* We cannot represent infinities, NaNs or +/-zero. We won't
14840 know if we have +zero until we analyse the mantissa, but we
14841 can reject the other invalid values. */
14846 /* Extract exponent. */
14850 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
14851 highest (sign) bit, with a fixed binary point at bit point_pos.
14852 m1 holds the low part of the mantissa, m2 the high part.
14853 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
14854 bits for the mantissa, this can fail (low bits will be lost). */
14858 /* If the low part of the mantissa has bits set we cannot represent
14859 the value. */
14862 /* We have rejected the lower HOST_WIDE_INT, so update our
14863 understanding of how many bits lie in the mantissa and
14864 look only at the high HOST_WIDE_INT. */
14868 /* We can only represent values with a mantissa of the form 1.xxxx. */
14873 /* Having filtered unrepresentable values, we may now remove all
14874 but the highest 5 bits. */
14877 /* We cannot represent the value 0.0, so reject it. This is handled
14878 elsewhere. */
14882 /* Then, as bit 4 is always set, we can mask it off, leaving
14883 the mantissa in the range [0, 15]. */
14887 /* GCC internally does not use IEEE754-like encoding (where normalized
14888 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
14889 Our mantissa values are shifted 4 places to the left relative to
14890 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
14891 by 5 places to correct for GCC's representation. */
14895 }
14897 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
14898 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
14899 output MOVI/MVNI, ORR or BIC immediate. */
14903 {
14913 /* This will return true to show const_vector is legal for use as either
14914 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
14915 It will also update INFO to show how the immediate should be generated.
14916 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
14924 {
14926 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
14927 move immediate path. */
14930 else
14931 {
14940 else
14944 }
14945 }
14950 {
14960 else
14964 }
14965 else
14966 {
14967 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
14973 else
14977 }
14979 }
14983 {
14985 /* If a floating point number was passed and we desire to use it in an
14986 integer mode do the conversion to integer. */
14988 {
14993 }
14995 machine_mode vmode;
14996 /* use a 64 bit mode for everything except for DI/DF mode, where we use
14997 a 128 bit vector mode. */
15003 }
15005 /* Return the output string to use for moving immediate CONST_VECTOR
15006 into an SVE register. */
15010 {
15021 {
15026 }
15029 {
15032 else
15033 {
15043 }
15044 }
15049 }
15051 /* Return the asm format for a PTRUE instruction whose destination has
15052 mode MODE. SUFFIX is the element size suffix. */
15056 {
15061 else
15064 }
15066 /* Split operands into moves from op[1] + op[2] into op[0]. */
15068 void
15070 {
15081 {
15082 /* No-op move. Can't split to nothing; emit something. */
15085 }
15087 /* Preserve register attributes for variable tracking. */
15092 /* Special case of reversed high/low parts. */
15095 {
15099 }
15101 {
15102 /* Try to avoid unnecessary moves if part of the result
15103 is in the right place already. */
15108 }
15109 else
15110 {
15115 }
15116 }
15118 /* vec_perm support. */
15120 struct expand_vec_perm_d
15121 {
15123 vec_perm_indices perm;
15124 machine_mode vmode;
15128 };
15130 /* Generate a variable permutation. */
15132 static void
15134 {
15145 {
15147 {
15148 /* Expand the argument to a V16QI mode by duplicating it. */
15152 }
15153 else
15154 {
15156 }
15157 }
15158 else
15159 {
15160 rtx pair;
15163 {
15167 }
15168 else
15169 {
15173 }
15174 }
15175 }
15177 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
15178 NELT is the number of elements in the vector. */
15180 void
15183 {
15186 rtx mask;
15188 /* The TBL instruction does not use a modulo index, so we must take care
15189 of that ourselves. */
15194 /* For big-endian, we also need to reverse the index within the vector
15195 (but not which vector). */
15197 {
15198 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
15203 }
15205 }
15207 /* Generate (set TARGET (unspec [OP0 OP1] CODE)). */
15209 static void
15211 {
15215 }
15217 /* Expand an SVE vec_perm with the given operands. */
15219 void
15221 {
15224 /* Enforced by the pattern condition. */
15227 /* Note: vec_perm indices are supposed to wrap when they go beyond the
15228 size of the two value vectors, i.e. the upper bits of the indices
15229 are effectively ignored. SVE TBL instead produces 0 for any
15230 out-of-range indices, so we need to modulo all the vec_perm indices
15231 to ensure they are all in range. */
15234 /* Check if the sel only references the first values vector. */
15237 {
15240 }
15242 /* Check if the two values vectors are the same. */
15244 {
15250 }
15252 /* Run TBL on for each value vector and combine the results. */
15259 {
15264 }
15271 else
15273 }
15275 /* Recognize patterns suitable for the TRN instructions. */
15276 static bool
15278 {
15279 HOST_WIDE_INT odd;
15287 /* Note that these are little-endian tests.
15288 We correct for big-endian later. */
15295 /* Success! */
15301 /* We don't need a big-endian lane correction for SVE; see the comment
15302 at the head of aarch64-sve.md for details. */
15304 {
15307 }
15313 }
15315 /* Recognize patterns suitable for the UZP instructions. */
15316 static bool
15318 {
15319 HOST_WIDE_INT odd;
15326 /* Note that these are little-endian tests.
15327 We correct for big-endian later. */
15333 /* Success! */
15339 /* We don't need a big-endian lane correction for SVE; see the comment
15340 at the head of aarch64-sve.md for details. */
15342 {
15345 }
15351 }
15353 /* Recognize patterns suitable for the ZIP instructions. */
15354 static bool
15356 {
15365 /* Note that these are little-endian tests.
15366 We correct for big-endian later. */
15374 /* Success! */
15380 /* We don't need a big-endian lane correction for SVE; see the comment
15381 at the head of aarch64-sve.md for details. */
15383 {
15386 }
15392 }
15394 /* Recognize patterns for the EXT insn. */
15396 static bool
15398 {
15399 HOST_WIDE_INT location;
15400 rtx offset;
15402 /* The first element always refers to the first vector.
15403 Check if the extracted indices are increasing by one. */
15409 /* Success! */
15413 /* The case where (location == 0) is a no-op for both big- and little-endian,
15414 and is removed by the mid-end at optimization levels -O1 and higher.
15416 We don't need a big-endian lane correction for SVE; see the comment
15417 at the head of aarch64-sve.md for details. */
15419 {
15420 /* After setup, we want the high elements of the first vector (stored
15421 at the LSB end of the register), and the low elements of the second
15422 vector (stored at the MSB end of the register). So swap. */
15424 /* location != 0 (above), so safe to assume (nelt - location) < nelt.
15425 to_constant () is safe since this is restricted to Advanced SIMD
15426 vectors. */
15428 }
15434 UNSPEC_EXT));
15436 }
15438 /* Recognize patterns for the REV{64,32,16} insns, which reverse elements
15439 within each 64-bit, 32-bit or 16-bit granule. */
15441 static bool
15443 {
15444 HOST_WIDE_INT diff;
15446 machine_mode pred_mode;
15455 {
15458 }
15460 {
15463 }
15465 {
15468 }
15469 else
15477 /* Success! */
15483 {
15486 UNSPEC_MERGE_PTRUE);
15487 }
15490 }
15492 /* Recognize patterns for the REV insn, which reverses elements within
15493 a full vector. */
15495 static bool
15497 {
15506 /* Success! */
15513 }
15515 static bool
15517 {
15519 rtx in0;
15520 HOST_WIDE_INT elt;
15522 rtx lane;
15532 /* Success! */
15536 /* The generic preparation in aarch64_expand_vec_perm_const_1
15537 swaps the operand order and the permute indices if it finds
15538 d->perm[0] to be in the second operand. Thus, we can always
15539 use d->op0 and need not do any extra arithmetic to get the
15540 correct lane number. */
15548 }
15550 static bool
15552 {
15556 /* Make sure that the indices are constant. */
15565 /* Generic code will try constant permutation twice. Once with the
15566 original mode and again with the elements lowered to QImode.
15567 So wait and don't do the selector expansion ourselves. */
15571 /* to_constant is safe since this routine is specific to Advanced SIMD
15572 vectors. */
15575 /* If big-endian and two vectors we end up with a weird mixed-endian
15576 mode on NEON. Reverse the index within each word but not the word
15577 itself. to_constant is safe because we checked is_constant above. */
15587 }
15589 /* Try to implement D using an SVE TBL instruction. */
15591 static bool
15593 {
15596 /* Permuting two variable-length vectors could overflow the
15597 index range. */
15608 }
15610 static bool
15612 {
15613 /* The pattern matching functions above are written to look for a small
15614 number to begin the sequence (0, 1, N/2). If we begin with an index
15615 from the second operand, we can swap the operands. */
15618 {
15621 }
15627 {
15646 }
15648 }
15650 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
15652 static bool
15655 {
15658 /* Check whether the mask can be applied to a single vector. */
15662 {
15665 }
15667 {
15670 }
15671 else
15691 }
15693 /* Generate a byte permute mask for a register of mode MODE,
15694 which has NUNITS units. */
15696 rtx
15698 {
15699 /* We have to reverse each vector because we dont have
15700 a permuted load that can reverse-load according to ABI rules. */
15701 rtx mask;
15714 }
15716 /* Return true if X is a valid second operand for the SVE instruction
15717 that implements integer comparison OP_CODE. */
15719 static bool
15721 {
15726 {
15741 }
15742 }
15744 /* Use predicated SVE instructions to implement the equivalent of:
15746 (set TARGET OP)
15748 given that PTRUE is an all-true predicate of the appropriate mode. */
15750 static void
15752 {
15755 UNSPEC_MERGE_PTRUE);
15758 }
15760 /* Likewise, but also clobber the condition codes. */
15762 static void
15764 {
15767 UNSPEC_MERGE_PTRUE);
15770 }
15772 /* Return the UNSPEC_COND_* code for comparison CODE. */
15774 static unsigned int
15776 {
15778 {
15793 }
15794 }
15796 /* Emit:
15798 (set TARGET (unspec [PRED OP0 OP1] UNSPEC_COND_<X>))
15800 where <X> is the operation associated with comparison CODE. This form
15801 of instruction is used when (and (CODE OP0 OP1) PRED) would have different
15802 semantics, such as when PRED might not be all-true and when comparing
15803 inactive lanes could have side effects. */
15805 static void
15808 {
15813 }
15815 /* Expand an SVE integer comparison using the SVE equivalent of:
15817 (set TARGET (CODE OP0 OP1)). */
15819 void
15821 {
15831 }
15833 /* Emit the SVE equivalent of:
15835 (set TMP1 (CODE1 OP0 OP1))
15836 (set TMP2 (CODE2 OP0 OP1))
15837 (set TARGET (ior:PRED_MODE TMP1 TMP2))
15839 PTRUE is an all-true predicate with the same mode as TARGET. */
15841 static void
15844 {
15853 }
15855 /* Emit the SVE equivalent of:
15857 (set TMP (CODE OP0 OP1))
15858 (set TARGET (not TMP))
15860 PTRUE is an all-true predicate with the same mode as TARGET. */
15862 static void
15865 {
15871 }
15873 /* Expand an SVE floating-point comparison using the SVE equivalent of:
15875 (set TARGET (CODE OP0 OP1))
15877 If CAN_INVERT_P is true, the caller can also handle inverted results;
15878 return true if the result is in fact inverted. */
15880 bool
15883 {
15889 {
15891 /* UNORDERED has no immediate form. */
15893 /* fall through */
15900 {
15901 /* There is native support for the comparison. */
15905 }
15908 /* This is a trapping operation (LT or GT). */
15914 {
15915 /* This would trap for signaling NaNs. */
15919 }
15920 /* fall through */
15926 {
15927 /* Work out which elements are ordered. */
15932 /* Test the opposite condition for the ordered elements,
15933 then invert the result. */
15936 else
15939 {
15943 }
15948 }
15952 /* ORDERED has no immediate form. */
15958 }
15960 /* There is native support for the inverse comparison. */
15963 {
15967 }
15970 }
15972 /* Expand an SVE vcond pattern with operands OPS. DATA_MODE is the mode
15973 of the data being selected and CMP_MODE is the mode of the values being
15974 compared. */
15976 void
15979 {
15980 machine_mode pred_mode
15985 {
15989 }
15990 else
15995 }
15997 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
15998 true. However due to issues with register allocation it is preferable
15999 to avoid tieing integer scalar and FP scalar modes. Executing integer
16000 operations in general registers is better than treating them as scalar
16001 vector operations. This reduces latency and avoids redundant int<->FP
16002 moves. So tie modes if they are either the same class, or vector modes
16003 with other vector modes, vector structs or any scalar mode. */
16005 static bool
16007 {
16011 /* We specifically want to allow elements of "structure" modes to
16012 be tieable to the structure. This more general condition allows
16013 other rarer situations too. The reason we don't extend this to
16014 predicate modes is that there are no predicate structure modes
16015 nor any specific instructions for extracting part of a predicate
16016 register. */
16021 /* Also allow any scalar modes with vectors. */
16027 }
16029 /* Return a new RTX holding the result of moving POINTER forward by
16030 AMOUNT bytes. */
16032 static rtx
16034 {
16039 }
16041 /* Return a new RTX holding the result of moving POINTER forward by the
16042 size of the mode it points to. */
16044 static rtx
16046 {
16048 }
16050 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
16051 MODE bytes. */
16053 static void
16055 machine_mode mode)
16056 {
16059 /* "Cast" the pointers to the correct mode. */
16062 /* Emit the memcpy. */
16065 /* Move the pointers forward. */
16068 }
16070 /* Expand movmem, as if from a __builtin_memcpy. Return true if
16071 we succeed, otherwise return false. */
16073 bool
16075 {
16079 rtx base;
16082 /* When optimizing for size, give a better estimate of the length of a
16083 memcpy call, but use the default otherwise. */
16086 /* We can't do anything smart if the amount to copy is not constant. */
16092 /* Try to keep the number of instructions low. For cases below 16 bytes we
16093 need to make at most two moves. For cases above 16 bytes it will be one
16094 move for each 16 byte chunk, then at most two additional moves. */
16104 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
16105 1-byte chunk. */
16107 {
16109 {
16112 }
16118 }
16120 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
16121 4-byte chunk, partially overlapping with the previously copied chunk. */
16123 {
16127 {
16133 }
16135 }
16137 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
16138 them, then (if applicable) an 8-byte chunk. */
16140 {
16142 {
16145 }
16146 else
16147 {
16150 }
16151 }
16153 /* Finish the final bytes of the copy. We can always do this in one
16154 instruction. We either copy the exact amount we need, or partially
16155 overlap with the previous chunk we copied and copy 8-bytes. */
16164 else
16165 {
16167 {
16171 }
16172 else
16173 {
16179 }
16180 }
16183 }
16185 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
16186 SImode stores. Handle the case when the constant has identical
16187 bottom and top halves. This is beneficial when the two stores can be
16188 merged into an STP and we avoid synthesising potentially expensive
16189 immediates twice. Return true if such a split is possible. */
16191 bool
16193 {
16202 unsigned int orig_cost
16204 unsigned int lo_cost
16207 /* We want to transform:
16208 MOV x1, 49370
16209 MOVK x1, 0x140, lsl 16
16210 MOVK x1, 0xc0da, lsl 32
16211 MOVK x1, 0x140, lsl 48
16212 STR x1, [x0]
16213 into:
16214 MOV w1, 49370
16215 MOVK w1, 0x140, lsl 16
16216 STP w1, w1, [x0]
16217 So we want to perform this only when we save two instructions
16218 or more. When optimizing for size, however, accept any code size
16219 savings we can. */
16234 /* Don't emit an explicit store pair as this may not be always profitable.
16235 Let the sched-fusion logic decide whether to merge them. */
16240 }
16242 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
16244 static unsigned HOST_WIDE_INT
16246 {
16248 }
16250 static rtx
16253 {
16257 insn_code icode;
16268 {
16296 }
16301 {
16304 }
16313 {
16316 }
16322 }
16324 static rtx
16327 {
16331 insn_code icode;
16343 {
16371 }
16376 {
16379 }
16387 {
16392 }
16403 {
16406 }
16412 }
16414 #undef TARGET_GEN_CCMP_FIRST
16415 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
16417 #undef TARGET_GEN_CCMP_NEXT
16418 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
16420 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
16421 instruction fusion of some sort. */
16423 static bool
16425 {
16427 }
16430 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
16431 should be kept together during scheduling. */
16433 static bool
16435 {
16436 rtx set_dest;
16439 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
16446 {
16447 /* We are trying to match:
16448 prev (mov) == (set (reg r0) (const_int imm16))
16449 curr (movk) == (set (zero_extract (reg r0)
16450 (const_int 16)
16451 (const_int 16))
16452 (const_int imm16_1)) */
16464 {
16466 }
16467 }
16470 {
16472 /* We're trying to match:
16473 prev (adrp) == (set (reg r1)
16474 (high (symbol_ref ("SYM"))))
16475 curr (add) == (set (reg r0)
16476 (lo_sum (reg r1)
16477 (symbol_ref ("SYM"))))
16478 Note that r0 need not necessarily be the same as r1, especially
16479 during pre-regalloc scheduling. */
16483 {
16491 }
16492 }
16495 {
16497 /* We're trying to match:
16498 prev (movk) == (set (zero_extract (reg r0)
16499 (const_int 16)
16500 (const_int 32))
16501 (const_int imm16_1))
16502 curr (movk) == (set (zero_extract (reg r0)
16503 (const_int 16)
16504 (const_int 48))
16505 (const_int imm16_2)) */
16521 }
16523 {
16524 /* We're trying to match:
16525 prev (adrp) == (set (reg r0)
16526 (high (symbol_ref ("SYM"))))
16527 curr (ldr) == (set (reg r1)
16528 (mem (lo_sum (reg r0)
16529 (symbol_ref ("SYM")))))
16530 or
16531 curr (ldr) == (set (reg r1)
16532 (zero_extend (mem
16533 (lo_sum (reg r0)
16534 (symbol_ref ("SYM")))))) */
16537 {
16550 }
16551 }
16559 {
16563 rtx cc_reg_1;
16568 && prev
16570 {
16571 /* FIXME: this misses some which is considered simple arthematic
16572 instructions for ThunderX. Simple shifts are missed here. */
16578 }
16579 }
16582 && curr_set
16585 {
16586 /* We're trying to match:
16587 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
16588 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
16589 (const_int 0))
16590 (label_ref ("SYM"))
16591 (pc)) */
16598 {
16599 /* Fuse ALU operations followed by conditional branch instruction. */
16601 {
16622 }
16623 }
16624 }
16627 }
16629 /* Return true iff the instruction fusion described by OP is enabled. */
16631 bool
16633 {
16635 }
16637 /* If MEM is in the form of [base+offset], extract the two parts
16638 of address and set to BASE and OFFSET, otherwise return false
16639 after clearing BASE and OFFSET. */
16641 bool
16643 {
16644 rtx addr;
16651 {
16655 }
16659 {
16663 }
16669 }
16671 /* Types for scheduling fusion. */
16672 enum sched_fusion_type
16673 {
16675 SCHED_FUSION_LD_SIGN_EXTEND,
16676 SCHED_FUSION_LD_ZERO_EXTEND,
16677 SCHED_FUSION_LD,
16678 SCHED_FUSION_ST,
16679 SCHED_FUSION_NUM
16680 };
16682 /* If INSN is a load or store of address in the form of [base+offset],
16683 extract the two parts and set to BASE and OFFSET. Return scheduling
16684 fusion type this INSN is. */
16686 static enum sched_fusion_type
16688 {
16706 {
16711 }
16713 {
16718 }
16723 {
16726 }
16727 else
16734 }
16736 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
16738 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
16739 and PRI are only calculated for these instructions. For other instruction,
16740 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
16741 type instruction fusion can be added by returning different priorities.
16743 It's important that irrelevant instructions get the largest FUSION_PRI. */
16745 static void
16748 {
16758 {
16762 }
16764 /* Set FUSION_PRI according to fusion type and base register. */
16767 /* Calculate PRI. */
16770 /* INSN with smaller offset goes first. */
16774 else
16779 }
16781 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
16782 Adjust priority of sha1h instructions so they are scheduled before
16783 other SHA1 instructions. */
16785 static int
16787 {
16791 {
16796 }
16799 }
16801 /* Given OPERANDS of consecutive load/store, check if we can merge
16802 them into ldp/stp. LOAD is true if they are load instructions.
16803 MODE is the mode of memory operands. */
16805 bool
16807 machine_mode mode)
16808 {
16814 {
16822 }
16823 else
16824 {
16829 }
16831 /* The mems cannot be volatile. */
16835 /* If we have SImode and slow unaligned ldp,
16836 check the alignment to be at least 8 byte. */
16840 && !optimize_size
16844 /* Check if the addresses are in the form of [base+offset]. */
16852 /* Check if the bases are same. */
16856 /* The operands must be of the same size. */
16862 /* We should only be trying this for fixed-sized modes. There is no
16863 SVE LDP/STP instruction. */
16865 /* Check if the offsets are consecutive. */
16869 /* Check if the addresses are clobbered by load. */
16871 {
16875 /* In increasing order, the last load can clobber the address. */
16878 }
16882 else
16887 else
16890 /* Check if the registers are of same class. */
16895 }
16897 /* Given OPERANDS of consecutive load/store, check if we can merge
16898 them into ldp/stp by adjusting the offset. LOAD is true if they
16899 are load instructions. MODE is the mode of memory operands.
16901 Given below consecutive stores:
16903 str w1, [xb, 0x100]
16904 str w1, [xb, 0x104]
16905 str w1, [xb, 0x108]
16906 str w1, [xb, 0x10c]
16908 Though the offsets are out of the range supported by stp, we can
16909 still pair them after adjusting the offset, like:
16911 add scratch, xb, 0x100
16912 stp w1, w1, [scratch]
16913 stp w1, w1, [scratch, 0x8]
16915 The peephole patterns detecting this opportunity should guarantee
16916 the scratch register is avaliable. */
16918 bool
16920 scalar_mode mode)
16921 {
16928 {
16941 }
16942 else
16943 {
16952 }
16953 /* Skip if memory operand is by itslef valid for ldp/stp. */
16957 /* The mems cannot be volatile. */
16962 /* Check if the addresses are in the form of [base+offset]. */
16976 /* Check if the bases are same. */
16987 /* Check if the offsets are consecutive. */
16996 /* Check if the addresses are clobbered by load. */
16998 {
17004 /* In increasing order, the last load can clobber the address. */
17007 }
17009 /* If we have SImode and slow unaligned ldp,
17010 check the alignment to be at least 8 byte. */
17014 && !optimize_size
17020 else
17025 else
17030 else
17035 else
17038 /* Check if the registers are of same class. */
17043 }
17045 /* Given OPERANDS of consecutive load/store, this function pairs them
17046 into ldp/stp after adjusting the offset. It depends on the fact
17047 that addresses of load/store instructions are in increasing order.
17048 MODE is the mode of memory operands. CODE is the rtl operator
17049 which should be applied to all memory operands, it's SIGN_EXTEND,
17050 ZERO_EXTEND or UNKNOWN. */
17052 bool
17055 {
17061 {
17066 }
17067 else
17068 {
17074 }
17079 /* Adjust offset thus it can fit in ldp/stp instruction. */
17087 /* Further adjust to make sure all offsets are OK. */
17089 {
17092 }
17094 /* Make sure the adjustment can be done with ADD/SUB instructions. */
17099 {
17102 }
17104 /* Create new memory references. */
17108 /* Check if the adjusted address is OK for ldp/stp. */
17127 {
17132 }
17134 {
17139 }
17142 {
17147 }
17148 else
17149 {
17154 }
17156 /* Emit adjusting instruction. */
17158 /* Emit ldp/stp instructions. */
17166 }
17168 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
17169 it isn't worth branching around empty masked ops (including masked
17170 stores). */
17172 static bool
17174 {
17176 }
17178 /* Return 1 if pseudo register should be created and used to hold
17179 GOT address for PIC code. */
17181 bool
17183 {
17185 }
17187 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
17189 static int
17191 {
17193 {
17200 }
17203 }
17206 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
17207 return the log2 of that value. Otherwise return -1. */
17209 int
17211 {
17226 }
17228 /* If X is a vector of equal CONST_DOUBLE values and that value is
17229 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
17231 int
17233 {
17251 }
17253 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
17254 to float.
17256 __fp16 always promotes through this hook.
17257 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
17258 through the generic excess precision logic rather than here. */
17260 static tree
17262 {
17268 }
17270 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
17272 static bool
17274 optimization_type opt_type)
17275 {
17277 {
17283 }
17284 }
17286 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
17288 static unsigned int
17291 {
17292 /* Polynomial invariant 1 == (VG / 2) - 1. */
17297 }
17299 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
17300 if MODE is HFmode, and punt to the generic implementation otherwise. */
17302 static bool
17304 {
17308 }
17310 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
17311 if MODE is HFmode, and punt to the generic implementation otherwise. */
17313 static bool
17315 {
17319 }
17321 /* Set the value of FLT_EVAL_METHOD.
17322 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
17324 0: evaluate all operations and constants, whose semantic type has at
17325 most the range and precision of type float, to the range and
17326 precision of float; evaluate all other operations and constants to
17327 the range and precision of the semantic type;
17329 N, where _FloatN is a supported interchange floating type
17330 evaluate all operations and constants, whose semantic type has at
17331 most the range and precision of _FloatN type, to the range and
17332 precision of the _FloatN type; evaluate all other operations and
17333 constants to the range and precision of the semantic type;
17335 If we have the ARMv8.2-A extensions then we support _Float16 in native
17336 precision, so we should set this to 16. Otherwise, we support the type,
17337 but want to evaluate expressions in float precision, so set this to
17338 0. */
17340 static enum flt_eval_method
17342 {
17344 {
17347 /* We can calculate either in 16-bit range and precision or
17348 32-bit range and precision. Make that decision based on whether
17349 we have native support for the ARMv8.2-A 16-bit floating-point
17350 instructions or not. */
17352 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
17358 }
17360 }
17362 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
17363 scheduled for speculative execution. Reject the long-running division
17364 and square-root instructions. */
17366 static bool
17368 {
17370 {
17388 }
17389 }
17391 /* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */
17393 static int
17395 {
17399 /* PR_REGS isn't a useful pressure class because many predicate pseudo
17400 registers need to go in PR_LO_REGS at some point during their
17401 lifetime. Splitting it into two halves has the effect of making
17402 all predicates count against PR_LO_REGS, so that we try whenever
17403 possible to restrict the number of live predicates to 8. This
17404 greatly reduces the amount of spilling in certain loops. */
17408 }
17410 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
17412 static bool
17415 {
17417 {
17421 /* Don't allow changes between SVE data modes and non-SVE modes.
17422 See the comment at the head of aarch64-sve.md for details. */
17426 /* Don't allow changes in element size: lane 0 of the new vector
17427 would not then be lane 0 of the old vector. See the comment
17428 above aarch64_maybe_expand_sve_subreg_move for a more detailed
17429 description.
17431 In the worst case, this forces a register to be spilled in
17432 one mode and reloaded in the other, which handles the
17433 endianness correctly. */
17436 }
17438 }
17440 /* Implement TARGET_EARLY_REMAT_MODES. */
17442 static void
17444 {
17445 /* SVE values are not normally live across a call, so it should be
17446 worth doing early rematerialization even in VL-specific mode. */
17448 {
17453 }
17454 }
17456 /* Target-specific selftests. */
17458 #if CHECKING_P
17462 /* Selftest for the RTL loader.
17463 Verify that the RTL loader copes with a dump from
17464 print_rtx_function. This is essentially just a test that class
17465 function_reader can handle a real dump, but it also verifies
17466 that lookup_reg_by_dump_name correctly handles hard regs.
17467 The presence of hard reg names in the dump means that the test is
17468 target-specific, hence it is in this file. */
17470 static void
17472 {
17484 /* Verify crtl->return_rtx. */
17488 }
17490 /* Run all target-specific selftests. */
17492 static void
17494 {
17496 }
17502 #undef TARGET_ADDRESS_COST
17503 #define TARGET_ADDRESS_COST aarch64_address_cost
17505 /* This hook will determines whether unnamed bitfields affect the alignment
17506 of the containing structure. The hook returns true if the structure
17507 should inherit the alignment requirements of an unnamed bitfield's
17508 type. */
17509 #undef TARGET_ALIGN_ANON_BITFIELD
17510 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
17512 #undef TARGET_ASM_ALIGNED_DI_OP
17515 #undef TARGET_ASM_ALIGNED_HI_OP
17518 #undef TARGET_ASM_ALIGNED_SI_OP
17521 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17522 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
17523 hook_bool_const_tree_hwi_hwi_const_tree_true
17525 #undef TARGET_ASM_FILE_START
17526 #define TARGET_ASM_FILE_START aarch64_start_file
17528 #undef TARGET_ASM_OUTPUT_MI_THUNK
17529 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
17531 #undef TARGET_ASM_SELECT_RTX_SECTION
17532 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
17534 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
17535 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
17537 #undef TARGET_BUILD_BUILTIN_VA_LIST
17538 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
17540 #undef TARGET_CALLEE_COPIES
17541 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
17543 #undef TARGET_CAN_ELIMINATE
17544 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
17546 #undef TARGET_CAN_INLINE_P
17547 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
17549 #undef TARGET_CANNOT_FORCE_CONST_MEM
17550 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
17552 #undef TARGET_CASE_VALUES_THRESHOLD
17553 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
17555 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17556 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
17558 /* Only the least significant bit is used for initialization guard
17559 variables. */
17560 #undef TARGET_CXX_GUARD_MASK_BIT
17561 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
17563 #undef TARGET_C_MODE_FOR_SUFFIX
17564 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
17566 #ifdef TARGET_BIG_ENDIAN_DEFAULT
17567 #undef TARGET_DEFAULT_TARGET_FLAGS
17568 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
17569 #endif
17571 #undef TARGET_CLASS_MAX_NREGS
17572 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
17574 #undef TARGET_BUILTIN_DECL
17575 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
17577 #undef TARGET_BUILTIN_RECIPROCAL
17578 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
17580 #undef TARGET_C_EXCESS_PRECISION
17581 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
17583 #undef TARGET_EXPAND_BUILTIN
17584 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
17586 #undef TARGET_EXPAND_BUILTIN_VA_START
17587 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
17589 #undef TARGET_FOLD_BUILTIN
17590 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
17592 #undef TARGET_FUNCTION_ARG
17593 #define TARGET_FUNCTION_ARG aarch64_function_arg
17595 #undef TARGET_FUNCTION_ARG_ADVANCE
17596 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
17598 #undef TARGET_FUNCTION_ARG_BOUNDARY
17599 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
17601 #undef TARGET_FUNCTION_ARG_PADDING
17602 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
17604 #undef TARGET_GET_RAW_RESULT_MODE
17605 #define TARGET_GET_RAW_RESULT_MODE aarch64_get_reg_raw_mode
17606 #undef TARGET_GET_RAW_ARG_MODE
17607 #define TARGET_GET_RAW_ARG_MODE aarch64_get_reg_raw_mode
17609 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17610 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
17612 #undef TARGET_FUNCTION_VALUE
17613 #define TARGET_FUNCTION_VALUE aarch64_function_value
17615 #undef TARGET_FUNCTION_VALUE_REGNO_P
17616 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
17618 #undef TARGET_GIMPLE_FOLD_BUILTIN
17619 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
17621 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17622 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
17624 #undef TARGET_INIT_BUILTINS
17625 #define TARGET_INIT_BUILTINS aarch64_init_builtins
17627 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
17628 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
17629 aarch64_ira_change_pseudo_allocno_class
17631 #undef TARGET_LEGITIMATE_ADDRESS_P
17632 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
17634 #undef TARGET_LEGITIMATE_CONSTANT_P
17635 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
17637 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
17638 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
17639 aarch64_legitimize_address_displacement
17641 #undef TARGET_LIBGCC_CMP_RETURN_MODE
17642 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
17644 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
17645 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
17646 aarch64_libgcc_floating_mode_supported_p
17648 #undef TARGET_MANGLE_TYPE
17649 #define TARGET_MANGLE_TYPE aarch64_mangle_type
17651 #undef TARGET_MEMORY_MOVE_COST
17652 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
17654 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
17655 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
17657 #undef TARGET_MUST_PASS_IN_STACK
17658 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17660 /* This target hook should return true if accesses to volatile bitfields
17661 should use the narrowest mode possible. It should return false if these
17662 accesses should use the bitfield container type. */
17663 #undef TARGET_NARROW_VOLATILE_BITFIELD
17664 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
17666 #undef TARGET_OPTION_OVERRIDE
17667 #define TARGET_OPTION_OVERRIDE aarch64_override_options
17669 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
17670 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
17671 aarch64_override_options_after_change
17673 #undef TARGET_OPTION_SAVE
17674 #define TARGET_OPTION_SAVE aarch64_option_save
17676 #undef TARGET_OPTION_RESTORE
17677 #define TARGET_OPTION_RESTORE aarch64_option_restore
17679 #undef TARGET_OPTION_PRINT
17680 #define TARGET_OPTION_PRINT aarch64_option_print
17682 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
17683 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
17685 #undef TARGET_SET_CURRENT_FUNCTION
17686 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
17688 #undef TARGET_PASS_BY_REFERENCE
17689 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
17691 #undef TARGET_PREFERRED_RELOAD_CLASS
17692 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
17694 #undef TARGET_SCHED_REASSOCIATION_WIDTH
17695 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
17697 #undef TARGET_PROMOTED_TYPE
17698 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
17700 #undef TARGET_SECONDARY_RELOAD
17701 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
17703 #undef TARGET_SHIFT_TRUNCATION_MASK
17704 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
17706 #undef TARGET_SETUP_INCOMING_VARARGS
17707 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
17709 #undef TARGET_STRUCT_VALUE_RTX
17710 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
17712 #undef TARGET_REGISTER_MOVE_COST
17713 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
17715 #undef TARGET_RETURN_IN_MEMORY
17716 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
17718 #undef TARGET_RETURN_IN_MSB
17719 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
17721 #undef TARGET_RTX_COSTS
17722 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
17724 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17725 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
17727 #undef TARGET_SCHED_ISSUE_RATE
17728 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
17730 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17731 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17732 aarch64_sched_first_cycle_multipass_dfa_lookahead
17734 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
17735 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
17736 aarch64_first_cycle_multipass_dfa_lookahead_guard
17738 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
17739 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
17740 aarch64_get_separate_components
17742 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
17743 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
17744 aarch64_components_for_bb
17746 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
17747 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
17748 aarch64_disqualify_components
17750 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
17751 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
17752 aarch64_emit_prologue_components
17754 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
17755 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
17756 aarch64_emit_epilogue_components
17758 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
17759 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
17760 aarch64_set_handled_components
17762 #undef TARGET_TRAMPOLINE_INIT
17763 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
17765 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17766 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
17768 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17769 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
17771 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
17772 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
17773 aarch64_builtin_support_vector_misalignment
17775 #undef TARGET_ARRAY_MODE
17776 #define TARGET_ARRAY_MODE aarch64_array_mode
17778 #undef TARGET_ARRAY_MODE_SUPPORTED_P
17779 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
17781 #undef TARGET_VECTORIZE_ADD_STMT_COST
17782 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
17784 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
17785 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
17786 aarch64_builtin_vectorization_cost
17788 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17789 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
17791 #undef TARGET_VECTORIZE_BUILTINS
17792 #define TARGET_VECTORIZE_BUILTINS
17794 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
17795 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
17796 aarch64_builtin_vectorized_function
17798 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
17799 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
17800 aarch64_autovectorize_vector_sizes
17802 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
17803 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
17804 aarch64_atomic_assign_expand_fenv
17806 /* Section anchor support. */
17808 #undef TARGET_MIN_ANCHOR_OFFSET
17809 #define TARGET_MIN_ANCHOR_OFFSET -256
17811 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
17812 byte offset; we can do much more for larger data types, but have no way
17813 to determine the size of the access. We assume accesses are aligned. */
17814 #undef TARGET_MAX_ANCHOR_OFFSET
17815 #define TARGET_MAX_ANCHOR_OFFSET 4095
17817 #undef TARGET_VECTOR_ALIGNMENT
17818 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
17820 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
17821 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
17822 aarch64_vectorize_preferred_vector_alignment
17823 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
17824 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
17825 aarch64_simd_vector_alignment_reachable
17827 /* vec_perm support. */
17829 #undef TARGET_VECTORIZE_VEC_PERM_CONST
17830 #define TARGET_VECTORIZE_VEC_PERM_CONST \
17831 aarch64_vectorize_vec_perm_const
17833 #undef TARGET_VECTORIZE_GET_MASK_MODE
17834 #define TARGET_VECTORIZE_GET_MASK_MODE aarch64_get_mask_mode
17835 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
17836 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE \
17837 aarch64_empty_mask_is_expensive
17839 #undef TARGET_INIT_LIBFUNCS
17840 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
17842 #undef TARGET_FIXED_CONDITION_CODE_REGS
17843 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
17845 #undef TARGET_FLAGS_REGNUM
17846 #define TARGET_FLAGS_REGNUM CC_REGNUM
17848 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
17849 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
17851 #undef TARGET_ASAN_SHADOW_OFFSET
17852 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
17854 #undef TARGET_LEGITIMIZE_ADDRESS
17855 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
17857 #undef TARGET_SCHED_CAN_SPECULATE_INSN
17858 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
17860 #undef TARGET_CAN_USE_DOLOOP_P
17861 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
17863 #undef TARGET_SCHED_ADJUST_PRIORITY
17864 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
17866 #undef TARGET_SCHED_MACRO_FUSION_P
17867 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
17869 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
17870 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
17872 #undef TARGET_SCHED_FUSION_PRIORITY
17873 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
17875 #undef TARGET_UNSPEC_MAY_TRAP_P
17876 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
17878 #undef TARGET_USE_PSEUDO_PIC_REG
17879 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
17881 #undef TARGET_PRINT_OPERAND
17882 #define TARGET_PRINT_OPERAND aarch64_print_operand
17884 #undef TARGET_PRINT_OPERAND_ADDRESS
17885 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
17887 #undef TARGET_OPTAB_SUPPORTED_P
17888 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
17890 #undef TARGET_OMIT_STRUCT_RETURN_REG
17891 #define TARGET_OMIT_STRUCT_RETURN_REG true
17893 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
17894 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE \
17895 aarch64_dwarf_poly_indeterminate_value
17897 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
17898 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
17899 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
17901 #undef TARGET_HARD_REGNO_NREGS
17902 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
17903 #undef TARGET_HARD_REGNO_MODE_OK
17904 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
17906 #undef TARGET_MODES_TIEABLE_P
17907 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
17909 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
17910 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
17911 aarch64_hard_regno_call_part_clobbered
17913 #undef TARGET_CONSTANT_ALIGNMENT
17914 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
17916 #undef TARGET_COMPUTE_PRESSURE_CLASSES
17917 #define TARGET_COMPUTE_PRESSURE_CLASSES aarch64_compute_pressure_classes
17919 #undef TARGET_CAN_CHANGE_MODE_CLASS
17920 #define TARGET_CAN_CHANGE_MODE_CLASS aarch64_can_change_mode_class
17922 #undef TARGET_SELECT_EARLY_REMAT_MODES
17923 #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes
17925 #if CHECKING_P
17926 #undef TARGET_RUN_TARGET_SELFTESTS
17927 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests