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1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
94 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
116 #ifndef LOAD_EXTEND_OP
117 #define LOAD_EXTEND_OP(M) UNKNOWN
118 #endif
120 /* Number of attempts to combine instructions in this function. */
124 /* Number of attempts that got as far as substitution in this function. */
128 /* Number of instructions combined with added SETs in this function. */
132 /* Number of instructions combined in this function. */
136 /* Totals over entire compilation. */
140 /* combine_instructions may try to replace the right hand side of the
141 second instruction with the value of an associated REG_EQUAL note
142 before throwing it at try_combine. That is problematic when there
143 is a REG_DEAD note for a register used in the old right hand side
144 and can cause distribute_notes to do wrong things. This is the
145 second instruction if it has been so modified, null otherwise. */
149 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
153 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
156 \f
158 /* Record last point of death of (hard or pseudo) register n. */
161 /* Record last point of modification of (hard or pseudo) register n. */
164 /* The next group of fields allows the recording of the last value assigned
165 to (hard or pseudo) register n. We use this information to see if an
166 operation being processed is redundant given a prior operation performed
167 on the register. For example, an `and' with a constant is redundant if
168 all the zero bits are already known to be turned off.
170 We use an approach similar to that used by cse, but change it in the
171 following ways:
173 (1) We do not want to reinitialize at each label.
174 (2) It is useful, but not critical, to know the actual value assigned
175 to a register. Often just its form is helpful.
177 Therefore, we maintain the following fields:
179 last_set_value the last value assigned
180 last_set_label records the value of label_tick when the
181 register was assigned
182 last_set_table_tick records the value of label_tick when a
183 value using the register is assigned
184 last_set_invalid set to nonzero when it is not valid
185 to use the value of this register in some
186 register's value
188 To understand the usage of these tables, it is important to understand
189 the distinction between the value in last_set_value being valid and
190 the register being validly contained in some other expression in the
191 table.
193 (The next two parameters are out of date).
195 reg_stat[i].last_set_value is valid if it is nonzero, and either
196 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
198 Register I may validly appear in any expression returned for the value
199 of another register if reg_n_sets[i] is 1. It may also appear in the
200 value for register J if reg_stat[j].last_set_invalid is zero, or
201 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
203 If an expression is found in the table containing a register which may
204 not validly appear in an expression, the register is replaced by
205 something that won't match, (clobber (const_int 0)). */
207 /* Record last value assigned to (hard or pseudo) register n. */
209 rtx last_set_value;
211 /* Record the value of label_tick when an expression involving register n
212 is placed in last_set_value. */
216 /* Record the value of label_tick when the value for register n is placed in
217 last_set_value. */
221 /* These fields are maintained in parallel with last_set_value and are
222 used to store the mode in which the register was last set, the bits
223 that were known to be zero when it was last set, and the number of
224 sign bits copies it was known to have when it was last set. */
230 /* Set nonzero if references to register n in expressions should not be
231 used. last_set_invalid is set nonzero when this register is being
232 assigned to and last_set_table_tick == label_tick. */
236 /* Some registers that are set more than once and used in more than one
237 basic block are nevertheless always set in similar ways. For example,
238 a QImode register may be loaded from memory in two places on a machine
239 where byte loads zero extend.
241 We record in the following fields if a register has some leading bits
242 that are always equal to the sign bit, and what we know about the
243 nonzero bits of a register, specifically which bits are known to be
244 zero.
246 If an entry is zero, it means that we don't know anything special. */
252 /* Record the value of the label_tick when the last truncation
253 happened. The field truncated_to_mode is only valid if
254 truncation_label == label_tick. */
258 /* Record the last truncation seen for this register. If truncation
259 is not a nop to this mode we might be able to save an explicit
260 truncation if we know that value already contains a truncated
261 value. */
269 /* One plus the highest pseudo for which we track REG_N_SETS.
270 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
271 but during combine_split_insns new pseudos can be created. As we don't have
272 updated DF information in that case, it is hard to initialize the array
273 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
274 so instead of growing the arrays, just assume all newly created pseudos
275 during combine might be set multiple times. */
279 /* Record the luid of the last insn that invalidated memory
280 (anything that writes memory, and subroutine calls, but not pushes). */
284 /* Record the luid of the last CALL_INSN
285 so we can tell whether a potential combination crosses any calls. */
289 /* When `subst' is called, this is the insn that is being modified
290 (by combining in a previous insn). The PATTERN of this insn
291 is still the old pattern partially modified and it should not be
292 looked at, but this may be used to examine the successors of the insn
293 to judge whether a simplification is valid. */
297 /* This is the lowest LUID that `subst' is currently dealing with.
298 get_last_value will not return a value if the register was set at or
299 after this LUID. If not for this mechanism, we could get confused if
300 I2 or I1 in try_combine were an insn that used the old value of a register
301 to obtain a new value. In that case, we might erroneously get the
302 new value of the register when we wanted the old one. */
306 /* This contains any hard registers that are used in newpat; reg_dead_at_p
307 must consider all these registers to be always live. */
311 /* This is an insn to which a LOG_LINKS entry has been added. If this
312 insn is the earlier than I2 or I3, combine should rescan starting at
313 that location. */
317 /* Basic block in which we are performing combines. */
321 \f
322 /* Length of the currently allocated uid_insn_cost array. */
326 /* The following array records the insn_rtx_cost for every insn
327 in the instruction stream. */
331 /* The following array records the LOG_LINKS for every insn in the
332 instruction stream as struct insn_link pointers. */
338 };
342 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
343 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
345 #define FOR_EACH_LOG_LINK(L, INSN) \
346 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
348 /* Links for LOG_LINKS are allocated from this obstack. */
352 /* Allocate a link. */
356 {
364 }
366 /* Incremented for each basic block. */
370 /* Reset to label_tick for each extended basic block in scanning order. */
374 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
375 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
379 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
380 be safely used. It is zero while computing them and after combine has
381 completed. This former test prevents propagating values based on
382 previously set values, which can be incorrect if a variable is modified
383 in a loop. */
387 \f
388 /* Record one modification to rtl structure
389 to be undone by storing old_contents into *where. */
393 struct undo
394 {
399 };
401 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
402 num_undo says how many are currently recorded.
404 other_insn is nonzero if we have modified some other insn in the process
405 of working on subst_insn. It must be verified too. */
407 struct undobuf
408 {
412 };
416 /* Number of times the pseudo being substituted for
417 was found and replaced. */
422 machine_mode,
426 machine_mode,
498 \f
500 /* It is not safe to use ordinary gen_lowpart in combine.
501 See comments in gen_lowpart_for_combine. */
502 #undef RTL_HOOKS_GEN_LOWPART
503 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
505 /* Our implementation of gen_lowpart never emits a new pseudo. */
506 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
507 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
509 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
510 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
512 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
513 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
515 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
516 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
520 \f
521 /* Convenience wrapper for the canonicalize_comparison target hook.
522 Target hooks cannot use enum rtx_code. */
526 {
530 }
532 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
533 PATTERN can not be split. Otherwise, it returns an insn sequence.
534 This is a wrapper around split_insns which ensures that the
535 reg_stat vector is made larger if the splitter creates a new
536 register. */
540 {
549 }
551 /* This is used by find_single_use to locate an rtx in LOC that
552 contains exactly one use of DEST, which is typically either a REG
553 or CC0. It returns a pointer to the innermost rtx expression
554 containing DEST. Appearances of DEST that are being used to
555 totally replace it are not counted. */
559 {
568 {
572 CASE_CONST_ANY:
577 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
578 of a REG that occupies all of the REG, the insn uses DEST if
579 it is mentioned in the destination or the source. Otherwise, we
580 need just check the source. */
600 }
602 /* If it wasn't one of the common cases above, check each expression and
603 vector of this code. Look for a unique usage of DEST. */
607 {
609 {
614 else
620 /* Duplicate usage. */
622 }
624 {
628 {
634 else
641 }
642 }
643 }
646 }
649 /* See if DEST, produced in INSN, is used only a single time in the
650 sequel. If so, return a pointer to the innermost rtx expression in which
651 it is used.
653 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
655 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
656 care about REG_DEAD notes or LOG_LINKS.
658 Otherwise, we find the single use by finding an insn that has a
659 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
660 only referenced once in that insn, we know that it must be the first
661 and last insn referencing DEST. */
665 {
666 basic_block bb;
672 {
682 }
692 {
698 {
703 }
704 }
707 }
708 \f
709 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
710 insn. The substitution can be undone by undo_all. If INTO is already
711 set to NEWVAL, do not record this change. Because computing NEWVAL might
712 also call SUBST, we have to compute it before we put anything into
713 the undo table. */
715 static void
717 {
724 /* We'd like to catch as many invalid transformations here as
725 possible. Unfortunately, there are way too many mode changes
726 that are perfectly valid, so we'd waste too much effort for
727 little gain doing the checks here. Focus on catching invalid
728 transformations involving integer constants. */
731 {
732 /* Sanity check that we're replacing oldval with a CONST_INT
733 that is a valid sign-extension for the original mode. */
737 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
738 CONST_INT is not valid, because after the replacement, the
739 original mode would be gone. Unfortunately, we can't tell
740 when do_SUBST is called to replace the operand thereof, so we
741 perform this test on oldval instead, checking whether an
742 invalid replacement took place before we got here. */
747 }
751 else
760 }
762 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
764 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
765 for the value of a HOST_WIDE_INT value (including CONST_INT) is
766 not safe. */
768 static void
770 {
779 else
788 }
790 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
792 /* Similar to SUBST, but just substitute the mode. This is used when
793 changing the mode of a pseudo-register, so that any other
794 references to the entry in the regno_reg_rtx array will change as
795 well. */
797 static void
799 {
808 else
817 }
819 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
821 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
823 static void
825 {
834 else
843 }
845 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
846 \f
847 /* Subroutine of try_combine. Determine whether the replacement patterns
848 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
849 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
850 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
851 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
852 of all the instructions can be estimated and the replacements are more
853 expensive than the original sequence. */
855 static bool
858 {
863 /* Lookup the original insn_rtx_costs. */
868 {
871 {
875 }
876 else
877 {
881 }
882 }
883 else
884 {
887 }
889 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
890 correct that. */
895 /* Calculate the replacement insn_rtx_costs. */
898 {
902 }
903 else
904 {
907 }
910 {
916 {
919 }
920 else
922 }
924 /* Disallow this combination if both new_cost and old_cost are greater than
925 zero, and new_cost is greater than old cost. */
929 {
948 else
950 }
955 /* Update the uid_insn_cost array with the replacement costs. */
959 {
963 }
966 }
969 /* Delete any insns that copy a register to itself. */
971 static void
973 {
975 basic_block bb;
978 {
980 {
983 {
988 }
989 }
990 }
991 }
993 \f
994 /* Return false if we do not want to (or cannot) combine DEF. */
995 static bool
997 {
998 /* Do not consider if it is pre/post modification in MEM. */
1004 /* Do not combine frame pointer adjustments. */
1007 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1015 }
1017 /* Return false if we do not want to (or cannot) combine USE. */
1018 static bool
1020 {
1021 /* Do not consider the usage of the stack pointer by function call. */
1026 }
1028 /* Fill in log links field for all insns. */
1030 static void
1032 {
1033 basic_block bb;
1040 /* Pass through each block from the end, recording the uses of each
1041 register and establishing log links when def is encountered.
1042 Note that we do not clear next_use array in order to save time,
1043 so we have to test whether the use is in the same basic block as def.
1045 There are a few cases below when we do not consider the definition or
1046 usage -- these are taken from original flow.c did. Don't ask me why it is
1047 done this way; I don't know and if it works, I don't want to know. */
1050 {
1052 {
1056 /* Log links are created only once. */
1060 {
1076 /* flow.c claimed:
1078 We don't build a LOG_LINK for hard registers contained
1079 in ASM_OPERANDs. If these registers get replaced,
1080 we might wind up changing the semantics of the insn,
1081 even if reload can make what appear to be valid
1082 assignments later. */
1087 /* Don't add duplicate links between instructions. */
1096 }
1101 }
1102 }
1105 }
1107 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1108 true if we found a LOG_LINK that proves that A feeds B. This only works
1109 if there are no instructions between A and B which could have a link
1110 depending on A, since in that case we would not record a link for B.
1111 We also check the implicit dependency created by a cc0 setter/user
1112 pair. */
1114 static bool
1116 {
1124 }
1125 \f
1126 /* Main entry point for combiner. F is the first insn of the function.
1127 NREGS is the first unused pseudo-reg number.
1129 Return nonzero if the combiner has turned an indirect jump
1130 instruction into a direct jump. */
1131 static int
1133 {
1138 basic_block last_bb;
1158 /* Allocate array for insn info. */
1166 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1167 problems when, for example, we have j <<= 1 in a loop. */
1172 /* Scan all SETs and see if we can deduce anything about what
1173 bits are known to be zero for some registers and how many copies
1174 of the sign bit are known to exist for those registers.
1176 Also set any known values so that we can use it while searching
1177 for what bits are known to be set. */
1180 /* Allow the entry block and the first block to fall into the same EBB.
1181 Conceptually the incoming promotions are assigned to the entry block. */
1186 {
1191 label_tick++;
1199 {
1200 rtx links;
1206 insn);
1213 insn);
1215 /* Record the current insn_rtx_cost of this instruction. */
1218 optimize_this_for_speed_p);
1222 }
1223 }
1227 /* Now scan all the insns in forward order. */
1235 {
1241 label_tick++;
1251 {
1265 /* See if we know about function return values before this
1266 insn based upon SUBREG flags. */
1269 /* See if we can find hardregs and subreg of pseudos in
1270 narrower modes. This could help turning TRUNCATEs
1271 into SUBREGs. */
1274 /* Try this insn with each insn it links back to. */
1280 {
1283 }
1285 /* Try each sequence of three linked insns ending with this one. */
1289 {
1292 /* If the linked insn has been replaced by a note, then there
1293 is no point in pursuing this chain any further. */
1301 {
1304 }
1305 }
1307 /* Try to combine a jump insn that uses CC0
1308 with a preceding insn that sets CC0, and maybe with its
1309 logical predecessor as well.
1310 This is how we make decrement-and-branch insns.
1311 We need this special code because data flow connections
1312 via CC0 do not get entered in LOG_LINKS. */
1319 {
1330 }
1332 /* Do the same for an insn that explicitly references CC0. */
1339 {
1350 }
1352 /* Finally, see if any of the insns that this insn links to
1353 explicitly references CC0. If so, try this insn, that insn,
1354 and its predecessor if it sets CC0. */
1356 {
1368 }
1370 /* Try combining an insn with two different insns whose results it
1371 uses. */
1381 {
1384 }
1386 /* Try four-instruction combinations. */
1389 {
1393 /* If the linked insn has been replaced by a note, then there
1394 is no point in pursuing this chain any further. */
1399 {
1403 /* I0 -> I1 -> I2 -> I3. */
1409 {
1412 }
1413 /* I0, I1 -> I2, I2 -> I3. */
1420 {
1423 }
1424 }
1427 {
1431 /* I0 -> I2; I1, I2 -> I3. */
1437 {
1440 }
1441 /* I0 -> I1; I1, I2 -> I3. */
1447 {
1450 }
1451 }
1452 }
1454 /* Try this insn with each REG_EQUAL note it links back to. */
1456 {
1462 /* Avoid using a register that may already been marked
1463 dead by an earlier instruction. */
1468 {
1469 /* Temporarily replace the set's source with the
1470 contents of the REG_EQUAL note. The insn will
1471 be deleted or recognized by try_combine. */
1479 last_combined_insn);
1482 {
1485 }
1487 }
1488 }
1493 retry:
1494 ;
1495 }
1496 }
1503 /* Clean up. */
1509 {
1512 {
1515 }
1517 }
1527 /* Make recognizer allow volatile MEMs again. */
1531 }
1533 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1535 static void
1537 {
1543 }
1544 \f
1545 /* Set up any promoted values for incoming argument registers. */
1547 static void
1549 {
1550 tree arg;
1555 {
1560 /* Only continue if the incoming argument is in a register. */
1564 /* Determine, if possible, whether all call sites of the current
1565 function lie within the current compilation unit. (This does
1566 take into account the exporting of a function via taking its
1567 address, and so forth.) */
1570 /* The mode and signedness of the argument before any promotions happen
1571 (equal to the mode of the pseudo holding it at that stage). */
1575 /* The mode and signedness of the argument after any source language and
1576 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1580 /* The mode and signedness of the argument as it is actually passed,
1581 see assign_parm_setup_reg in function.c. */
1585 /* The mode of the register in which the argument is being passed. */
1588 /* Eliminate sign extensions in the callee when:
1589 (a) A mode promotion has occurred; */
1592 /* (b) The mode of the register is the same as the mode of
1593 the argument as it is passed; */
1596 /* (c) There's no language level extension; */
1598 ;
1599 /* (c.1) All callers are from the current compilation unit. If that's
1600 the case we don't have to rely on an ABI, we only have to know
1601 what we're generating right now, and we know that we will do the
1602 mode1 to mode2 promotion with the given sign. */
1605 /* (c.2) The combination of the two promotions is useful. This is
1606 true when the signs match, or if the first promotion is unsigned.
1607 In the later case, (sign_extend (zero_extend x)) is the same as
1608 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1614 /* Record that the value was promoted from mode1 to mode3,
1615 so that any sign extension at the head of the current
1616 function may be eliminated. */
1620 }
1621 }
1623 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1624 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1625 because some machines (maybe most) will actually do the sign-extension and
1626 this is the conservative approach.
1628 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1629 kludge. */
1631 static rtx
1633 {
1641 }
1643 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1644 and SET. */
1646 static void
1648 rtx x)
1649 {
1659 {
1663 }
1665 /* Don't call nonzero_bits if it cannot change anything. */
1667 {
1672 }
1674 /* Don't call num_sign_bit_copies if it cannot change anything. */
1676 {
1679 {
1683 }
1686 }
1687 }
1689 /* Called via note_stores. If X is a pseudo that is narrower than
1690 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1692 If we are setting only a portion of X and we can't figure out what
1693 portion, assume all bits will be used since we don't know what will
1694 be happening.
1696 Similarly, set how many bits of X are known to be copies of the sign bit
1697 at all locations in the function. This is the smallest number implied
1698 by any set of X. */
1700 static void
1702 {
1707 /* If this register is undefined at the start of the file, we can't
1708 say what its contents were. */
1709 && ! REGNO_REG_SET_P
1712 {
1716 {
1720 }
1722 /* If this register is being initialized using itself, and the
1723 register is uninitialized in this basic block, and there are
1724 no LOG_LINKS which set the register, then part of the
1725 register is uninitialized. In that case we can't assume
1726 anything about the number of nonzero bits.
1728 ??? We could do better if we checked this in
1729 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1730 could avoid making assumptions about the insn which initially
1731 sets the register, while still using the information in other
1732 insns. We would have to be careful to check every insn
1733 involved in the combination. */
1739 {
1746 {
1750 }
1751 }
1753 /* If this is a complex assignment, see if we can convert it into a
1754 simple assignment. */
1757 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1758 set what we know about X. */
1764 else
1765 {
1768 }
1769 }
1770 }
1771 \f
1772 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1773 optionally insns that were previously combined into I3 or that will be
1774 combined into the merger of INSN and I3. The order is PRED, PRED2,
1775 INSN, SUCC, SUCC2, I3.
1777 Return 0 if the combination is not allowed for any reason.
1779 If the combination is allowed, *PDEST will be set to the single
1780 destination of INSN and *PSRC to the single source, and this function
1781 will return 1. */
1783 static int
1787 {
1792 rtx link;
1797 {
1799 {
1804 }
1809 }
1813 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1814 or a PARALLEL consisting of such a SET and CLOBBERs.
1816 If INSN has CLOBBER parallel parts, ignore them for our processing.
1817 By definition, these happen during the execution of the insn. When it
1818 is merged with another insn, all bets are off. If they are, in fact,
1819 needed and aren't also supplied in I3, they may be added by
1820 recog_for_combine. Otherwise, it won't match.
1822 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1823 note.
1825 Get the source and destination of INSN. If more than one, can't
1826 combine. */
1832 {
1834 {
1838 {
1839 /* This is important to combine floating point insns
1840 for the SH4 port. */
1842 /* Combining an isolated USE doesn't make sense.
1843 We depend here on combinable_i3pat to reject them. */
1844 /* The code below this loop only verifies that the inputs of
1845 the SET in INSN do not change. We call reg_set_between_p
1846 to verify that the REG in the USE does not change between
1847 I3 and INSN.
1848 If the USE in INSN was for a pseudo register, the matching
1849 insn pattern will likely match any register; combining this
1850 with any other USE would only be safe if we knew that the
1851 used registers have identical values, or if there was
1852 something to tell them apart, e.g. different modes. For
1853 now, we forgo such complicated tests and simply disallow
1854 combining of USES of pseudo registers with any other USE. */
1857 {
1862 do
1863 {
1873 }
1875 }
1878 /* We can ignore CLOBBERs. */
1883 /* Ignore SETs whose result isn't used but not those that
1884 have side-effects. */
1890 /* If we have already found a SET, this is a second one and
1891 so we cannot combine with this insn. */
1899 /* Anything else means we can't combine. */
1901 }
1902 }
1905 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1906 so don't do anything with it. */
1909 }
1910 else
1916 /* The simplification in expand_field_assignment may call back to
1917 get_last_value, so set safe guard here. */
1923 /* Do not eliminate user-specified register if it is in an
1924 asm input because we may break the register asm usage defined
1925 in GCC manual if allow to do so.
1926 Be aware that this may cover more cases than we expect but this
1927 should be harmless. */
1932 /* Don't eliminate a store in the stack pointer. */
1934 /* Don't combine with an insn that sets a register to itself if it has
1935 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1937 /* Can't merge an ASM_OPERANDS. */
1939 /* Can't merge a function call. */
1941 /* Don't eliminate a function call argument. */
1947 /* Don't substitute into an incremented register. */
1951 /* Don't substitute into a non-local goto, this confuses CFG. */
1953 /* Make sure that DEST is not used after SUCC but before I3. */
1954 || (!all_adjacent
1955 && ((succ2
1959 /* Make sure that the value that is to be substituted for the register
1960 does not use any registers whose values alter in between. However,
1961 If the insns are adjacent, a use can't cross a set even though we
1962 think it might (this can happen for a sequence of insns each setting
1963 the same destination; last_set of that register might point to
1964 a NOTE). If INSN has a REG_EQUIV note, the register is always
1965 equivalent to the memory so the substitution is valid even if there
1966 are intervening stores. Also, don't move a volatile asm or
1967 UNSPEC_VOLATILE across any other insns. */
1968 || (! all_adjacent
1974 /* Don't combine across a CALL_INSN, because that would possibly
1975 change whether the life span of some REGs crosses calls or not,
1976 and it is a pain to update that information.
1977 Exception: if source is a constant, moving it later can't hurt.
1978 Accept that as a special case. */
1982 /* DEST must either be a REG or CC0. */
1984 {
1985 /* If register alignment is being enforced for multi-word items in all
1986 cases except for parameters, it is possible to have a register copy
1987 insn referencing a hard register that is not allowed to contain the
1988 mode being copied and which would not be valid as an operand of most
1989 insns. Eliminate this problem by not combining with such an insn.
1991 Also, on some machines we don't want to extend the life of a hard
1992 register. */
1997 /* Don't extend the life of a hard register unless it is
1998 user variable (if we have few registers) or it can't
1999 fit into the desired register (meaning something special
2000 is going on).
2001 Also avoid substituting a return register into I3, because
2002 reload can't handle a conflict with constraints of other
2003 inputs. */
2007 }
2015 {
2018 /* If the clobber represents an earlyclobber operand, we must not
2019 substitute an expression containing the clobbered register.
2020 As we do not analyze the constraint strings here, we have to
2021 make the conservative assumption. However, if the register is
2022 a fixed hard reg, the clobber cannot represent any operand;
2023 we leave it up to the machine description to either accept or
2024 reject use-and-clobber patterns. */
2030 }
2032 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2033 or not), reject, unless nothing volatile comes between it and I3 */
2036 {
2037 /* Make sure neither succ nor succ2 contains a volatile reference. */
2042 /* We'll check insns between INSN and I3 below. */
2043 }
2045 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2046 to be an explicit register variable, and was chosen for a reason. */
2052 /* If INSN contains volatile references (specifically volatile MEMs),
2053 we cannot combine across any other volatile references.
2054 Even if INSN doesn't contain volatile references, any intervening
2055 volatile insn might affect machine state. */
2058 ? volatile_refs_p
2065 /* If INSN contains an autoincrement or autodecrement, make sure that
2066 register is not used between there and I3, and not already used in
2067 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2068 Also insist that I3 not be a jump; if it were one
2069 and the incremented register were spilled, we would lose. */
2087 /* Don't combine an insn that follows a CC0-setting insn.
2088 An insn that uses CC0 must not be separated from the one that sets it.
2089 We do, however, allow I2 to follow a CC0-setting insn if that insn
2090 is passed as I1; in that case it will be deleted also.
2091 We also allow combining in this case if all the insns are adjacent
2092 because that would leave the two CC0 insns adjacent as well.
2093 It would be more logical to test whether CC0 occurs inside I1 or I2,
2094 but that would be much slower, and this ought to be equivalent. */
2097 {
2102 }
2104 /* If we get here, we have passed all the tests and the combination is
2105 to be allowed. */
2111 }
2112 \f
2113 /* LOC is the location within I3 that contains its pattern or the component
2114 of a PARALLEL of the pattern. We validate that it is valid for combining.
2116 One problem is if I3 modifies its output, as opposed to replacing it
2117 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2118 doing so would produce an insn that is not equivalent to the original insns.
2120 Consider:
2122 (set (reg:DI 101) (reg:DI 100))
2123 (set (subreg:SI (reg:DI 101) 0) <foo>)
2125 This is NOT equivalent to:
2127 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2128 (set (reg:DI 101) (reg:DI 100))])
2130 Not only does this modify 100 (in which case it might still be valid
2131 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2133 We can also run into a problem if I2 sets a register that I1
2134 uses and I1 gets directly substituted into I3 (not via I2). In that
2135 case, we would be getting the wrong value of I2DEST into I3, so we
2136 must reject the combination. This case occurs when I2 and I1 both
2137 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2138 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2139 of a SET must prevent combination from occurring. The same situation
2140 can occur for I0, in which case I0_NOT_IN_SRC is set.
2142 Before doing the above check, we first try to expand a field assignment
2143 into a set of logical operations.
2145 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2146 we place a register that is both set and used within I3. If more than one
2147 such register is detected, we fail.
2149 Return 1 if the combination is valid, zero otherwise. */
2151 static int
2154 {
2158 {
2163 rtx subdest;
2170 /* Check for the case where I3 modifies its output, as discussed
2171 above. We don't want to prevent pseudos from being combined
2172 into the address of a MEM, so only prevent the combination if
2173 i1 or i2 set the same MEM. */
2183 /* This is the same test done in can_combine_p except we can't test
2184 all_adjacent; we don't have to, since this instruction will stay
2185 in place, thus we are not considering increasing the lifetime of
2186 INNER_DEST.
2188 Also, if this insn sets a function argument, combining it with
2189 something that might need a spill could clobber a previous
2190 function argument; the all_adjacent test in can_combine_p also
2191 checks this; here, we do a more specific test for this case. */
2201 /* If DEST is used in I3, it is being killed in this insn, so
2202 record that for later. We have to consider paradoxical
2203 subregs here, since they kill the whole register, but we
2204 ignore partial subregs, STRICT_LOW_PART, etc.
2205 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2206 STACK_POINTER_REGNUM, since these are always considered to be
2207 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2217 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2223 {
2228 }
2229 }
2232 {
2239 }
2242 }
2243 \f
2244 /* Return 1 if X is an arithmetic expression that contains a multiplication
2245 and division. We don't count multiplications by powers of two here. */
2247 static int
2249 {
2251 {
2267 }
2268 }
2269 \f
2270 /* Determine whether INSN can be used in a combination. Return nonzero if
2271 not. This is used in try_combine to detect early some cases where we
2272 can't perform combinations. */
2274 static int
2276 {
2277 rtx set;
2280 /* If this isn't really an insn, we can't do anything.
2281 This can occur when flow deletes an insn that it has merged into an
2282 auto-increment address. */
2286 /* Never combine loads and stores involving hard regs that are likely
2287 to be spilled. The register allocator can usually handle such
2288 reg-reg moves by tying. If we allow the combiner to make
2289 substitutions of likely-spilled regs, reload might die.
2290 As an exception, we allow combinations involving fixed regs; these are
2291 not available to the register allocator so there's no risk involved. */
2312 }
2314 struct likely_spilled_retval_info
2315 {
2318 };
2320 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2321 hard registers that are known to be written to / clobbered in full. */
2322 static void
2324 {
2341 else
2344 }
2346 /* Return nonzero iff part of the return value is live during INSN, and
2347 it is likely spilled. This can happen when more than one insn is needed
2348 to copy the return value, e.g. when we consider to combine into the
2349 second copy insn for a complex value. */
2351 static int
2353 {
2355 rtx reg;
2358 /* We assume here that no machine mode needs more than
2359 32 hard registers when the value overlaps with a register
2360 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2375 /* Disregard parts of the return value that are set later. */
2384 /* Check if any of the (probably) live return value registers is
2385 likely spilled. */
2386 nregs --;
2387 do
2388 {
2394 }
2396 /* Adjust INSN after we made a change to its destination.
2398 Changing the destination can invalidate notes that say something about
2399 the results of the insn and a LOG_LINK pointing to the insn. */
2401 static void
2403 {
2404 /* For notes, be conservative and simply remove them. */
2407 /* The new insn will have a destination that was previously the destination
2408 of an insn just above it. Call distribute_links to make a LOG_LINK from
2409 the next use of that destination. */
2425 }
2427 /* Return TRUE if combine can reuse reg X in mode MODE.
2428 ADDED_SETS is nonzero if the original set is still required. */
2429 static bool
2431 {
2438 /* Allow hard registers if the new mode is legal, and occupies no more
2439 registers than the old mode. */
2444 /* Or a pseudo that is only used once. */
2447 && !added_sets
2449 }
2452 /* Check whether X, the destination of a set, refers to part of
2453 the register specified by REG. */
2455 static bool
2457 {
2458 /* Check that reg is an integer mode register. */
2469 }
2471 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2472 Note that the INSN should be deleted *after* removing dead edges, so
2473 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2474 but not for a (set (pc) (label_ref FOO)). */
2476 static void
2478 {
2486 {
2491 /* Remove barriers from the footer if there are any. */
2494 {
2497 else
2501 }
2504 }
2505 }
2507 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2508 by an arbitrary number of CLOBBERs. */
2509 static bool
2511 {
2529 }
2531 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2532 CLOBBERs), can be split into individual SETs in that order, without
2533 changing semantics. */
2534 static bool
2536 {
2544 {
2553 }
2556 }
2558 /* Try to combine the insns I0, I1 and I2 into I3.
2559 Here I0, I1 and I2 appear earlier than I3.
2560 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2561 I3.
2563 If we are combining more than two insns and the resulting insn is not
2564 recognized, try splitting it into two insns. If that happens, I2 and I3
2565 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2566 Otherwise, I0, I1 and I2 are pseudo-deleted.
2568 Return 0 if the combination does not work. Then nothing is changed.
2569 If we did the combination, return the insn at which combine should
2570 resume scanning.
2572 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2573 new direct jump instruction.
2575 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2576 been I3 passed to an earlier try_combine within the same basic
2577 block. */
2582 {
2583 /* New patterns for I3 and I2, respectively. */
2587 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2588 dead. */
2590 /* Total number of SETs to put into I3. */
2592 /* Nonzero if I2's or I1's body now appears in I3. */
2594 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2596 /* Contains I3 if the destination of I3 is used in its source, which means
2597 that the old life of I3 is being killed. If that usage is placed into
2598 I2 and not in I3, a REG_DEAD note must be made. */
2600 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2602 /* Copy of SET_SRC of I1 and I0, if needed. */
2604 /* Set if I2DEST was reused as a scratch register. */
2606 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2608 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2613 /* Notes that must be added to REG_NOTES in I3 and I2. */
2615 /* Notes that we substituted I3 into I2 instead of the normal case. */
2617 /* Notes that I1, I2 or I3 is a MULT operation. */
2624 rtx temp_expr;
2627 rtx new_other_notes;
2630 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2631 never be). */
2635 /* Only try four-insn combinations when there's high likelihood of
2636 success. Look for simple insns, such as loads of constants or
2637 binary operations involving a constant. */
2639 {
2649 {
2652 rtx src;
2657 {
2660 }
2662 ngood++;
2665 nshift++;
2666 }
2668 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2669 are likely manipulating its value. Ideally we'll be able to combine
2670 all four insns into a bitfield insertion of some kind.
2672 Note the source in I0 might be inside a sign/zero extension and the
2673 memory modes in I0 and I3 might be different. So extract the address
2674 from the destination of I3 and search for it in the source of I0.
2676 In the event that there's a match but the source/dest do not actually
2677 refer to the same memory, the worst that happens is we try some
2678 combinations that we wouldn't have otherwise. */
2680 /* Ensure the source of SET0 is a MEM, possibly buried inside
2681 an extension. */
2687 /* Ensure the destination of SET3 is a MEM. */
2689 /* Would it be better to extract the base address for the MEM
2690 in SET3 and look for that? I don't have cases where it matters
2691 but I could envision such cases. */
2697 }
2699 /* Exit early if one of the insns involved can't be used for
2700 combinations. */
2711 combine_attempts++;
2714 /* Reset the hard register usage information. */
2718 {
2725 else
2728 }
2730 /* If multiple insns feed into one of I2 or I3, they can be in any
2731 order. To simplify the code below, reorder them in sequence. */
2741 /* First check for one important special case that the code below will
2742 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2743 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2744 we may be able to replace that destination with the destination of I3.
2745 This occurs in the common code where we compute both a quotient and
2746 remainder into a structure, in which case we want to do the computation
2747 directly into the structure to avoid register-register copies.
2749 Note that this case handles both multiple sets in I2 and also cases
2750 where I2 has a number of CLOBBERs inside the PARALLEL.
2752 We make very conservative checks below and only try to handle the
2753 most common cases of this. For example, we only handle the case
2754 where I2 and I3 are adjacent to avoid making difficult register
2755 usage tests. */
2763 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2764 below would need to check what is inside (and reg_overlap_mentioned_p
2765 doesn't support those codes anyway). Don't allow those destinations;
2766 the resulting insn isn't likely to be recognized anyway. */
2772 {
2775 /* Make sure that the destination of I3,
2776 which we are going to substitute into one output of I2,
2777 is not used within another output of I2. We must avoid making this:
2778 (parallel [(set (mem (reg 69)) ...)
2779 (set (reg 69) ...)])
2780 which is not well-defined as to order of actions.
2781 (Besides, reload can't handle output reloads for this.)
2783 The problem can also happen if the dest of I3 is a memory ref,
2784 if another dest in I2 is an indirect memory ref. */
2792 /* Make sure this PARALLEL is not an asm. We do not allow combining
2793 that usually (see can_combine_p), so do not here either. */
2803 {
2804 combine_merges++;
2814 /* Replace the dest in I2 with our dest and make the resulting
2815 insn the new pattern for I3. Then skip to where we validate
2816 the pattern. Everything was set up above. */
2821 }
2822 }
2824 /* If I2 is setting a pseudo to a constant and I3 is setting some
2825 sub-part of it to another constant, merge them by making a new
2826 constant. */
2833 {
2839 {
2842 {
2848 }
2849 }
2850 else
2851 {
2856 }
2859 {
2860 /* If this is the low part, we're done. */
2862 ;
2863 /* Handle the case where inner is twice the size of outer. */
2867 /* Otherwise give up for now. */
2868 else
2870 }
2873 {
2877 wide_int o
2882 combine_merges++;
2889 /* Replace the source in I2 with the new constant and make the
2890 resulting insn the new pattern for I3. Then skip to where we
2891 validate the pattern. Everything was set up above. */
2897 /* The dest of I3 has been replaced with the dest of I2. */
2900 }
2901 }
2903 /* If we have no I1 and I2 looks like:
2904 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2905 (set Y OP)])
2906 make up a dummy I1 that is
2907 (set Y OP)
2908 and change I2 to be
2909 (set (reg:CC X) (compare:CC Y (const_int 0)))
2911 (We can ignore any trailing CLOBBERs.)
2913 This undoes a previous combination and allows us to match a branch-and-
2914 decrement insn. */
2926 {
2927 /* We make I1 with the same INSN_UID as I2. This gives it
2928 the same DF_INSN_LUID for value tracking. Our fake I1 will
2929 never appear in the insn stream so giving it the same INSN_UID
2930 as I2 will not cause a problem. */
2943 }
2945 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2946 make those two SETs separate I1 and I2 insns, and make an I0 that is
2947 the original I1. */
2953 {
2954 /* If there is no I1, there is no I0 either. */
2957 /* We make I1 with the same INSN_UID as I2. This gives it
2958 the same DF_INSN_LUID for value tracking. Our fake I1 will
2959 never appear in the insn stream so giving it the same INSN_UID
2960 as I2 will not cause a problem. */
2968 }
2970 /* Verify that I2 and I1 are valid for combining. */
2976 {
2979 }
2981 /* Record whether I2DEST is used in I2SRC and similarly for the other
2982 cases. Knowing this will help in register status updating below. */
2993 /* For the earlier insns, determine which of the subsequent ones they
2994 feed. */
3001 /* Ensure that I3's pattern can be the destination of combines. */
3007 {
3010 }
3012 /* See if any of the insns is a MULT operation. Unless one is, we will
3013 reject a combination that is, since it must be slower. Be conservative
3014 here. */
3022 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3023 We used to do this EXCEPT in one case: I3 has a post-inc in an
3024 output operand. However, that exception can give rise to insns like
3025 mov r3,(r3)+
3026 which is a famous insn on the PDP-11 where the value of r3 used as the
3027 source was model-dependent. Avoid this sort of thing. */
3029 #if 0
3035 /* It's not the exception. */
3036 #endif
3038 {
3039 rtx link;
3045 {
3048 }
3049 }
3051 /* See if the SETs in I1 or I2 need to be kept around in the merged
3052 instruction: whenever the value set there is still needed past I3.
3053 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3055 For the SET in I1, we have two cases: if I1 and I2 independently feed
3056 into I3, the set in I1 needs to be kept around unless I1DEST dies
3057 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3058 in I1 needs to be kept around unless I1DEST dies or is set in either
3059 I2 or I3. The same considerations apply to I0. */
3066 else
3074 else
3077 /* We are about to copy insns for the case where they need to be kept
3078 around. Check that they can be copied in the merged instruction. */
3084 {
3087 }
3089 /* If the set in I2 needs to be kept around, we must make a copy of
3090 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3091 PATTERN (I2), we are only substituting for the original I1DEST, not into
3092 an already-substituted copy. This also prevents making self-referential
3093 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3094 I2DEST. */
3097 {
3100 else
3102 }
3105 {
3108 else
3110 }
3113 {
3116 else
3118 }
3120 combine_merges++;
3122 /* Substitute in the latest insn for the regs set by the earlier ones. */
3128 /* Many machines that don't use CC0 have insns that can both perform an
3129 arithmetic operation and set the condition code. These operations will
3130 be represented as a PARALLEL with the first element of the vector
3131 being a COMPARE of an arithmetic operation with the constant zero.
3132 The second element of the vector will set some pseudo to the result
3133 of the same arithmetic operation. If we simplify the COMPARE, we won't
3134 match such a pattern and so will generate an extra insn. Here we test
3135 for this case, where both the comparison and the operation result are
3136 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3137 I2SRC. Later we will make the PARALLEL that contains I2. */
3143 {
3144 rtx newpat_dest;
3158 {
3163 }
3165 /* Do the rest only if op1 is const0_rtx, which may be the
3166 result of simplification. */
3168 {
3169 /* If a single use of the CC is found, prepare to modify it
3170 when SELECT_CC_MODE returns a new CC-class mode, or when
3171 the above simplify_compare_const() returned a new comparison
3172 operator. undobuf.other_insn is assigned the CC use insn
3173 when modifying it. */
3175 {
3176 #ifdef SELECT_CC_MODE
3177 machine_mode new_mode
3182 {
3187 else
3188 {
3191 }
3192 }
3193 #endif
3194 /* Cases for modifying the CC-using comparison. */
3196 /* ??? Do we need to verify the zero rtx? */
3198 {
3199 /* Replace cc_use_loc with entire new RTX. */
3204 }
3206 {
3207 /* Just replace the CC reg with a new mode. */
3210 }
3211 }
3213 /* Now we modify the current newpat:
3214 First, SET_DEST(newpat) is updated if the CC mode has been
3215 altered. For targets without SELECT_CC_MODE, this should be
3216 optimized away. */
3219 /* This is always done to propagate i2src into newpat. */
3222 /* Create new version of i2pat if needed; the below PARALLEL
3223 creation needs this to work correctly. */
3227 }
3228 }
3231 {
3232 /* It is possible that the source of I2 or I1 may be performing
3233 an unneeded operation, such as a ZERO_EXTEND of something
3234 that is known to have the high part zero. Handle that case
3235 by letting subst look at the inner insns.
3237 Another way to do this would be to have a function that tries
3238 to simplify a single insn instead of merging two or more
3239 insns. We don't do this because of the potential of infinite
3240 loops and because of the potential extra memory required.
3241 However, doing it the way we are is a bit of a kludge and
3242 doesn't catch all cases.
3244 But only do this if -fexpensive-optimizations since it slows
3245 things down and doesn't usually win.
3247 This is not done in the COMPARE case above because the
3248 unmodified I2PAT is used in the PARALLEL and so a pattern
3249 with a modified I2SRC would not match. */
3252 {
3253 /* Pass pc_rtx so no substitutions are done, just
3254 simplifications. */
3256 {
3259 }
3263 }
3268 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3269 copy of I2SRC each time we substitute it, in order to avoid creating
3270 self-referential RTL when we will be substituting I1SRC for I1DEST
3271 later. Likewise if I0 feeds into I2, either directly or indirectly
3272 through I1, and I0DEST is in I0SRC. */
3279 /* Record whether I2's body now appears within I3's body. */
3281 }
3283 /* If we already got a failure, don't try to do more. Otherwise, try to
3284 substitute I1 if we have it. */
3287 {
3288 /* Check that an autoincrement side-effect on I1 has not been lost.
3289 This happens if I1DEST is mentioned in I2 and dies there, and
3290 has disappeared from the new pattern. */
3292 && i1_feeds_i2_n
3295 /* Before we can do this substitution, we must redo the test done
3296 above (see detailed comments there) that ensures I1DEST isn't
3297 mentioned in any SETs in NEWPAT that are field assignments. */
3300 {
3303 }
3308 /* If the following substitution will modify I1SRC, make a copy of it
3309 for the case where it is substituted for I1DEST in I2PAT later. */
3313 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3314 copy of I1SRC each time we substitute it, in order to avoid creating
3315 self-referential RTL when we will be substituting I0SRC for I0DEST
3316 later. */
3321 /* Record whether I1's body now appears within I3's body. */
3323 }
3325 /* Likewise for I0 if we have it. */
3328 {
3335 {
3338 }
3340 /* If the following substitution will modify I0SRC, make a copy of it
3341 for the case where it is substituted for I0DEST in I1PAT later. */
3344 /* And a copy for I0DEST in I2PAT substitution. */
3353 }
3355 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3356 to count all the ways that I2SRC and I1SRC can be used. */
3367 /* Fail if we tried to make a new register. */
3369 /* Fail if we couldn't do something and have a CLOBBER. */
3371 /* Fail if this new pattern is a MULT and we didn't have one before
3372 at the outer level. */
3375 {
3378 }
3380 /* If the actions of the earlier insns must be kept
3381 in addition to substituting them into the latest one,
3382 we must make a new PARALLEL for the latest insn
3383 to hold additional the SETs. */
3386 {
3388 combine_extras++;
3391 {
3397 }
3398 else
3399 {
3404 }
3410 {
3416 }
3418 {
3427 }
3428 }
3430 validate_replacement:
3432 /* Note which hard regs this insn has as inputs. */
3435 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3436 consider splitting this pattern, we might need these clobbers. */
3439 {
3445 }
3447 /* We have recognized nothing yet. */
3450 /* See if this is a PARALLEL of two SETs where one SET's destination is
3451 a register that is unused and this isn't marked as an instruction that
3452 might trap in an EH region. In that case, we just need the other SET.
3453 We prefer this over the PARALLEL.
3455 This can occur when simplifying a divmod insn. We *must* test for this
3456 case here because the code below that splits two independent SETs doesn't
3457 handle this case correctly when it updates the register status.
3459 It's pointless doing this if we originally had two sets, one from
3460 i3, and one from i2. Combining then splitting the parallel results
3461 in the original i2 again plus an invalid insn (which we delete).
3462 The net effect is only to move instructions around, which makes
3463 debug info less accurate. */
3468 {
3479 {
3482 }
3491 {
3497 }
3501 }
3503 /* Is the result of combination a valid instruction? */
3507 /* If we were combining three insns and the result is a simple SET
3508 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3509 insns. There are two ways to do this. It can be split using a
3510 machine-specific method (like when you have an addition of a large
3511 constant) or by combine in the function find_split_point. */
3515 {
3519 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3520 use I2DEST as a scratch register will help. In the latter case,
3521 convert I2DEST to the mode of the source of NEWPAT if we can. */
3525 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3526 inputs of NEWPAT. */
3528 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3529 possible to try that as a scratch reg. This would require adding
3530 more code to make it work though. */
3533 {
3536 /* First try to split using the original register as a
3537 scratch register. */
3541 i2dest)));
3544 /* If that didn't work, try changing the mode of I2DEST if
3545 we can. */
3550 {
3552 rtx ni2dest;
3556 else
3557 {
3560 }
3562 parallel = (gen_rtx_PARALLEL
3566 ni2dest))));
3571 {
3579 }
3580 }
3583 }
3585 /* If recog_for_combine has discarded clobbers, try to use them
3586 again for the split. */
3588 {
3591 }
3594 {
3599 }
3603 {
3613 /* If I2 or I3 has multiple SETs, we won't know how to track
3614 register status, so don't use these insns. If I2's destination
3615 is used between I2 and I3, we also can't use these insns. */
3625 /* It is possible that both insns now set the destination of I3.
3626 If so, we must show an extra use of it. */
3629 {
3648 }
3649 }
3651 /* If we can split it and use I2DEST, go ahead and see if that
3652 helps things be recognized. Verify that none of the registers
3653 are set between I2 and I3. */
3657 /* We need I2DEST in the proper mode. If it is a hard register
3658 or the only use of a pseudo, we can change its mode.
3659 Make sure we don't change a hard register to have a mode that
3660 isn't valid for it, or change the number of registers. */
3667 /* We can't overwrite I2DEST if its value is still used by
3668 NEWPAT. */
3670 {
3679 /* *SPLIT may be part of I2SRC, so make sure we have the
3680 original expression around for later debug processing.
3681 We should not need I2SRC any more in other cases. */
3684 else
3687 /* Get NEWDEST as a register in the proper mode. We have already
3688 validated that we can do this. */
3690 {
3693 else
3694 {
3697 }
3698 }
3700 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3701 an ASHIFT. This can occur if it was inside a PLUS and hence
3702 appeared to be a memory address. This is a kludge. */
3707 {
3710 /* Update split_code because we may not have a multiply
3711 anymore. */
3713 }
3715 /* Similarly for (plus (mult FOO (const_int pow2))). */
3721 {
3725 /* Update split_code because we may not have a multiply
3726 anymore. */
3728 }
3730 #ifdef INSN_SCHEDULING
3731 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3732 be written as a ZERO_EXTEND. */
3734 {
3735 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3736 what it really is. */
3741 else
3744 }
3745 #endif
3747 /* Attempt to split binary operators using arithmetic identities. */
3751 {
3758 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3760 {
3765 }
3766 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3773 {
3779 /* Split both "((X op Y) op X) op Y" and
3780 "((X op Y) op Y) op X" as "T op T" where T is
3781 "X op Y". */
3784 {
3789 }
3790 /* Split "((X op X) op Y) op Y)" as "T op T" where
3791 T is "X op Y". */
3793 {
3799 }
3800 }
3801 }
3804 {
3807 }
3811 /* recog_for_combine might have added CLOBBERs to newi2pat.
3812 Make sure NEWPAT does not depend on the clobbered regs. */
3816 {
3819 {
3822 }
3823 }
3825 /* If the split point was a MULT and we didn't have one before,
3826 don't use one now. */
3829 }
3830 }
3832 /* Check for a case where we loaded from memory in a narrow mode and
3833 then sign extended it, but we need both registers. In that case,
3834 we have a PARALLEL with both loads from the same memory location.
3835 We can split this into a load from memory followed by a register-register
3836 copy. This saves at least one insn, more if register allocation can
3837 eliminate the copy.
3839 We cannot do this if the destination of the first assignment is a
3840 condition code register or cc0. We eliminate this case by making sure
3841 the SET_DEST and SET_SRC have the same mode.
3843 We cannot do this if the destination of the second assignment is
3844 a register that we have already assumed is zero-extended. Similarly
3845 for a SUBREG of such a register. */
3880 {
3881 rtx ni2dest;
3895 }
3897 /* Similarly, check for a case where we have a PARALLEL of two independent
3898 SETs but we started with three insns. In this case, we can do the sets
3899 as two separate insns. This case occurs when some SET allows two
3900 other insns to combine, but the destination of that SET is still live.
3902 Also do this if we started with two insns and (at least) one of the
3903 resulting sets is a noop; this noop will be deleted later. */
3922 {
3926 /* Normally, it doesn't matter which of the two is done first,
3927 but the one that references cc0 can't be the second, and
3928 one which uses any regs/memory set in between i2 and i3 can't
3929 be first. The PARALLEL might also have been pre-existing in i3,
3930 so we need to make sure that we won't wrongly hoist a SET to i2
3931 that would conflict with a death note present in there. */
3939 /* If I3 is a jump, ensure that set0 is a jump so that
3940 we do not create invalid RTL. */
3942 )
3943 {
3946 }
3954 /* If I3 is a jump, ensure that set1 is a jump so that
3955 we do not create invalid RTL. */
3957 )
3958 {
3961 }
3962 else
3963 {
3966 }
3971 {
3972 /* recog_for_combine might have added CLOBBERs to newi2pat.
3973 Make sure NEWPAT does not depend on the clobbered regs. */
3975 {
3978 {
3981 {
3984 }
3985 }
3986 }
3989 }
3990 }
3992 /* If it still isn't recognized, fail and change things back the way they
3993 were. */
3995 /* Is the result a reasonable ASM_OPERANDS? */
3997 {
4000 }
4002 /* If we had to change another insn, make sure it is valid also. */
4004 {
4012 {
4015 }
4016 }
4018 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4019 they are adjacent to each other or not. */
4021 {
4025 {
4028 }
4029 }
4031 /* Only allow this combination if insn_rtx_costs reports that the
4032 replacement instructions are cheaper than the originals. */
4034 {
4037 }
4040 {
4045 {
4050 /* Temporarily revert mode back. */
4054 {
4055 /* If we used i2dest as a scratch register with a
4056 different mode, substitute it for the original
4057 i2src while its original mode is temporarily
4058 restored, and then clear i2scratch so that we don't
4059 do it again later. */
4061 this_basic_block);
4063 /* Put back the new mode. */
4065 }
4066 else
4067 {
4072 {
4075 }
4076 else
4077 {
4084 }
4086 /* We're dealing with a reg that changed mode but not
4087 meaning, so we want to turn it into a subreg for
4088 the new mode. However, because of REG sharing and
4089 because its mode had already changed, we have to do
4090 it in two steps. First, replace any debug uses of
4091 reg, with its original mode temporarily restored,
4092 with this copy we have created; then, replace the
4093 copy with the SUBREG of the original shared reg,
4094 once again changed to the new mode. */
4096 this_basic_block);
4100 this_basic_block);
4101 }
4102 }
4103 }
4105 /* If we will be able to accept this, we have made a
4106 change to the destination of I3. This requires us to
4107 do a few adjustments. */
4110 {
4113 }
4115 /* We now know that we can do this combination. Merge the insns and
4116 update the status of registers and LOG_LINKS. */
4119 {
4124 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4125 ensure that they are still valid. Then add any non-duplicate
4126 notes added by recog_for_combine. */
4128 {
4138 }
4142 NULL_RTX);
4143 }
4146 {
4149 rtx ni2dest;
4151 /* I3 now uses what used to be its destination and which is now
4152 I2's destination. This requires us to do a few adjustments. */
4156 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4157 so we still will.
4159 However, some later insn might be using I2's dest and have
4160 a LOG_LINK pointing at I3. We must remove this link.
4161 The simplest way to remove the link is to point it at I1,
4162 which we know will be a NOTE. */
4164 /* newi2pat is usually a SET here; however, recog_for_combine might
4165 have added some clobbers. */
4168 else
4175 {
4177 {
4183 }
4184 }
4185 }
4187 {
4192 /* Compute which registers we expect to eliminate. newi2pat may be setting
4193 either i3dest or i2dest, so we must check it. */
4196 || !i2dest_killed
4198 /* For i1, we need to compute both local elimination and global
4199 elimination information with respect to newi2pat because i1dest
4200 may be the same as i3dest, in which case newi2pat may be setting
4201 i1dest. Global information is used when distributing REG_DEAD
4202 note for i2 and i3, in which case it does matter if newi2pat sets
4203 i1dest or not.
4205 Local information is used when distributing REG_DEAD note for i1,
4206 in which case it doesn't matter if newi2pat sets i1dest or not.
4207 See PR62151, if we have four insns combination:
4208 i0: r0 <- i0src
4209 i1: r1 <- i1src (using r0)
4210 REG_DEAD (r0)
4211 i2: r0 <- i2src (using r1)
4212 i3: r3 <- i3src (using r0)
4213 ix: using r0
4214 From i1's point of view, r0 is eliminated, no matter if it is set
4215 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4216 should be discarded.
4218 Note local information only affects cases in forms like "I1->I2->I3",
4219 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4220 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4221 i0dest anyway. */
4223 || !i1dest_killed
4228 /* Same case as i1. */
4235 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4236 clear them. */
4244 /* Ensure that we do not have something that should not be shared but
4245 occurs multiple times in the new insns. Check this by first
4246 resetting all the `used' flags and then copying anything is shared. */
4270 {
4277 {
4278 /* I2SRC must still be meaningful at this point. Some splitting
4279 operations can invalidate I2SRC, but those operations do not
4280 apply to calls. */
4283 }
4291 }
4296 /* We had one special case above where I2 had more than one set and
4297 we replaced a destination of one of those sets with the destination
4298 of I3. In that case, we have to update LOG_LINKS of insns later
4299 in this basic block. Note that this (expensive) case is rare.
4301 Also, in this case, we must pretend that all REG_NOTEs for I2
4302 actually came from I3, so that REG_UNUSED notes from I2 will be
4303 properly handled. */
4306 {
4315 temp_insn
4325 {
4330 }
4331 else
4334 }
4342 {
4345 this_basic_block);
4348 }
4349 else
4350 {
4353 this_basic_block);
4355 }
4358 {
4363 this_basic_block);
4365 }
4368 {
4373 this_basic_block);
4375 }
4377 /* Get death notes for everything that is now used in either I3 or
4378 I2 and used to die in a previous insn. If we built two new
4379 patterns, move from I1 to I2 then I2 to I3 so that we get the
4380 proper movement on registers that I2 modifies. */
4386 else
4392 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4409 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4410 know these are REG_UNUSED and want them to go to the desired insn,
4411 so we always pass it as i3. */
4415 NULL_RTX);
4419 NULL_RTX);
4421 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4422 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4423 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4424 in that case, it might delete I2. Similarly for I2 and I1.
4425 Show an additional death due to the REG_DEAD note we make here. If
4426 we discard it in distribute_notes, we will decrement it again. */
4429 {
4434 else
4437 }
4440 {
4445 else
4448 }
4451 {
4456 else
4459 }
4462 {
4467 else
4470 }
4478 {
4483 /* The insn that used to set this register doesn't exist, and
4484 this life of the register may not exist either. See if one of
4485 I3's links points to an insn that sets I2DEST. If it does,
4486 that is now the last known value for I2DEST. If we don't update
4487 this and I2 set the register to a value that depended on its old
4488 contents, we will get confused. If this insn is used, thing
4489 will be set correctly in combine_instructions. */
4497 /* If the reg formerly set in I2 died only once and that was in I3,
4498 zero its use count so it won't make `reload' do any work. */
4501 && ! i2dest_in_i2src
4504 }
4507 {
4520 && ! i1dest_in_i1src
4523 }
4526 {
4539 && ! i0dest_in_i0src
4542 }
4544 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4545 been made to this insn. The order is important, because newi2pat
4546 can affect nonzero_bits of newpat. */
4550 }
4553 {
4555 {
4558 }
4560 }
4563 {
4565 {
4568 }
4570 }
4573 {
4575 {
4578 }
4580 }
4583 {
4585 {
4588 }
4590 }
4593 {
4595 {
4598 }
4600 }
4602 /* Set new_direct_jump_p if a new return or simple jump instruction
4603 has been created. Adjust the CFG accordingly. */
4605 {
4609 }
4614 {
4617 }
4619 /* A noop might also need cleaning up of CFG, if it comes from the
4620 simplification of a jump. */
4625 {
4628 }
4635 {
4638 }
4640 combine_successes++;
4647 else
4649 }
4650 \f
4651 /* Get a marker for undoing to the current state. */
4655 {
4657 }
4659 /* Undo the modifications up to the marker. */
4661 static void
4663 {
4667 {
4672 {
4687 }
4691 }
4694 }
4696 /* Undo all the modifications recorded in undobuf. */
4698 static void
4700 {
4702 }
4704 /* We've committed to accepting the changes we made. Move all
4705 of the undos to the free list. */
4707 static void
4709 {
4713 {
4717 }
4719 }
4720 \f
4721 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4722 where we have an arithmetic expression and return that point. LOC will
4723 be inside INSN.
4725 try_combine will call this function to see if an insn can be split into
4726 two insns. */
4730 {
4739 /* First special-case some codes. */
4741 {
4743 #ifdef INSN_SCHEDULING
4744 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4745 point. */
4748 #endif
4752 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4753 using LO_SUM and HIGH. */
4756 {
4764 }
4766 /* If we have a PLUS whose second operand is a constant and the
4767 address is not valid, perhaps will can split it up using
4768 the machine-specific way to split large constants. We use
4769 the first pseudo-reg (one of the virtual regs) as a placeholder;
4770 it will not remain in the result. */
4775 {
4778 subst_insn);
4780 /* This should have produced two insns, each of which sets our
4781 placeholder. If the source of the second is a valid address,
4782 we can make put both sources together and make a split point
4783 in the middle. */
4796 && memory_address_addr_space_p
4799 {
4803 /* Replace the placeholder in SRC2 with SRC1. If we can
4804 find where in SRC2 it was placed, that can become our
4805 split point and we can replace this address with SRC2.
4806 Just try two obvious places. */
4817 {
4820 }
4821 }
4823 /* If that didn't work, perhaps the first operand is complex and
4824 needs to be computed separately, so make a split point there.
4825 This will occur on machines that just support REG + CONST
4826 and have a constant moved through some previous computation. */
4832 }
4834 /* If we have a PLUS whose first operand is complex, try computing it
4835 separately by making a split there. */
4846 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4847 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4848 we need to put the operand into a register. So split at that
4849 point. */
4859 /* See if we can split SET_SRC as it stands. */
4864 /* See if we can split SET_DEST as it stands. */
4869 /* See if this is a bitfield assignment with everything constant. If
4870 so, this is an IOR of an AND, so split it into that. */
4880 {
4886 unsigned HOST_WIDE_INT mask
4888 rtx or_mask;
4897 else
4898 {
4904 or_mask));
4905 }
4912 }
4914 /* Otherwise, see if this is an operation that we can split into two.
4915 If so, try to split that. */
4919 {
4921 /* If we are AND'ing with a large constant that is only a single
4922 bit and the result is only being used in a context where we
4923 need to know if it is zero or nonzero, replace it with a bit
4924 extraction. This will avoid the large constant, which might
4925 have taken more than one insn to make. If the constant were
4926 not a valid argument to the AND but took only one insn to make,
4927 this is no worse, but if it took more than one insn, it will
4928 be better. */
4938 {
4943 {
4946 }
4947 }
4951 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4952 is known to be on, this can be converted into a NEG of a shift. */
4958 {
4970 }
4976 /* We can't optimize if either mode is a partial integer
4977 mode as we don't know how many bits are significant
4978 in those modes. */
4992 {
5000 }
5005 }
5009 {
5012 /* For unsigned, we have a choice of a shift followed by an
5013 AND or two shifts. Use two shifts for field sizes where the
5014 constant might be too large. We assume here that we can
5015 always at least get 8-bit constants in an AND insn, which is
5016 true for every current RISC. */
5019 {
5020 unsigned HOST_WIDE_INT mask
5024 gen_rtx_LSHIFTRT
5032 }
5033 else
5034 {
5036 gen_rtx_fmt_ee
5047 }
5048 }
5050 /* See if this is a simple operation with a constant as the second
5051 operand. It might be that this constant is out of range and hence
5052 could be used as a split point. */
5060 /* Finally, see if this is a simple operation with its first operand
5061 not in a register. The operation might require this operand in a
5062 register, so return it as a split point. We can always do this
5063 because if the first operand were another operation, we would have
5064 already found it as a split point. */
5073 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5074 it is better to write this as (not (ior A B)) so we can split it.
5075 Similarly for IOR. */
5077 {
5085 }
5087 /* Many RISC machines have a large set of logical insns. If the
5088 second operand is a NOT, put it first so we will try to split the
5089 other operand first. */
5091 {
5095 }
5100 /* Canonicalization can produce (minus A (mult B C)), where C is a
5101 constant. It may be better to try splitting (plus (mult B -C) A)
5102 instead if this isn't a multiply by a power of two. */
5106 {
5114 mode)),
5117 }
5119 /* Split at a multiply-accumulate instruction. However if this is
5120 the SET_SRC, we likely do not have such an instruction and it's
5121 worthless to try this split. */
5130 }
5132 /* Otherwise, select our actions depending on our rtx class. */
5134 {
5140 /* ... fall through ... */
5148 /* ... fall through ... */
5150 /* Some machines have (and (shift ...) ...) insns. If X is not
5151 an AND, but XEXP (X, 0) is, use it as our split point. */
5161 /* Otherwise, we don't have a split point. */
5163 }
5164 }
5165 \f
5166 /* Throughout X, replace FROM with TO, and return the result.
5167 The result is TO if X is FROM;
5168 otherwise the result is X, but its contents may have been modified.
5169 If they were modified, a record was made in undobuf so that
5170 undo_all will (among other things) return X to its original state.
5172 If the number of changes necessary is too much to record to undo,
5173 the excess changes are not made, so the result is invalid.
5174 The changes already made can still be undone.
5175 undobuf.num_undo is incremented for such changes, so by testing that
5176 the caller can tell whether the result is valid.
5178 `n_occurrences' is incremented each time FROM is replaced.
5180 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5182 IN_COND is nonzero if we are at the top level of a condition.
5184 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5185 by copying if `n_occurrences' is nonzero. */
5187 static rtx
5189 {
5194 rtx new_rtx;
5196 /* Two expressions are equal if they are identical copies of a shared
5197 RTX or if they are both registers with the same register number
5198 and mode. */
5200 #define COMBINE_RTX_EQUAL_P(X,Y) \
5201 ((X) == (Y) \
5202 || (REG_P (X) && REG_P (Y) \
5203 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5205 /* Do not substitute into clobbers of regs -- this will never result in
5206 valid RTL. */
5211 {
5212 n_occurrences++;
5214 }
5216 /* If X and FROM are the same register but different modes, they
5217 will not have been seen as equal above. However, the log links code
5218 will make a LOG_LINKS entry for that case. If we do nothing, we
5219 will try to rerecognize our original insn and, when it succeeds,
5220 we will delete the feeding insn, which is incorrect.
5222 So force this insn not to match in this (rare) case. */
5227 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5228 of which may contain things that can be combined. */
5232 /* It is possible to have a subexpression appear twice in the insn.
5233 Suppose that FROM is a register that appears within TO.
5234 Then, after that subexpression has been scanned once by `subst',
5235 the second time it is scanned, TO may be found. If we were
5236 to scan TO here, we would find FROM within it and create a
5237 self-referent rtl structure which is completely wrong. */
5241 /* Parallel asm_operands need special attention because all of the
5242 inputs are shared across the arms. Furthermore, unsharing the
5243 rtl results in recognition failures. Failure to handle this case
5244 specially can result in circular rtl.
5246 Solve this by doing a normal pass across the first entry of the
5247 parallel, and only processing the SET_DESTs of the subsequent
5248 entries. Ug. */
5253 {
5256 /* If this substitution failed, this whole thing fails. */
5264 {
5270 {
5273 /* If this substitution failed, this whole thing fails. */
5279 }
5280 }
5281 }
5282 else
5283 {
5287 /* We don't need to process a SET_DEST that is a register, CC0,
5288 or PC, so set up to skip this common case. All other cases
5289 where we want to suppress replacing something inside a
5290 SET_SRC are handled via the IN_DEST operand. */
5297 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5298 constant. */
5303 {
5305 {
5308 {
5310 {
5313 n_occurrences++;
5314 }
5315 else
5316 {
5318 unique_copy);
5320 /* If this substitution failed, this whole thing
5321 fails. */
5325 }
5328 }
5329 }
5331 {
5332 /* If this is a register being set, ignore it. */
5339 ;
5342 {
5343 /* In general, don't install a subreg involving two
5344 modes not tieable. It can worsen register
5345 allocation, and can even make invalid reload
5346 insns, since the reg inside may need to be copied
5347 from in the outside mode, and that may be invalid
5348 if it is an fp reg copied in integer mode.
5350 We allow two exceptions to this: It is valid if
5351 it is inside another SUBREG and the mode of that
5352 SUBREG and the mode of the inside of TO is
5353 tieable and it is valid if X is a SET that copies
5354 FROM to CC0. */
5362 && (!HAVE_cc0
5377 n_occurrences++;
5378 }
5379 else
5380 /* If we are in a SET_DEST, suppress most cases unless we
5381 have gone inside a MEM, in which case we want to
5382 simplify the address. We assume here that things that
5383 are actually part of the destination have their inner
5384 parts in the first expression. This is true for SUBREG,
5385 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5386 things aside from REG and MEM that should appear in a
5387 SET_DEST. */
5389 (((in_dest
5395 unique_copy);
5397 /* If we found that we will have to reject this combination,
5398 indicate that by returning the CLOBBER ourselves, rather than
5399 an expression containing it. This will speed things up as
5400 well as prevent accidents where two CLOBBERs are considered
5401 to be equal, thus producing an incorrect simplification. */
5407 {
5415 }
5418 {
5422 }
5423 else
5425 }
5426 }
5427 }
5429 /* Check if we are loading something from the constant pool via float
5430 extension; in this case we would undo compress_float_constant
5431 optimization and degenerate constant load to an immediate value. */
5435 {
5439 }
5441 /* Try to simplify X. If the simplification changed the code, it is likely
5442 that further simplification will help, so loop, but limit the number
5443 of repetitions that will be performed. */
5446 {
5447 /* If X is sufficiently simple, don't bother trying to do anything
5448 with it. */
5457 /* We no longer know the original mode of operand 0 since we
5458 have changed the form of X) */
5460 }
5463 }
5464 \f
5465 /* Simplify X, a piece of RTL. We just operate on the expression at the
5466 outer level; call `subst' to simplify recursively. Return the new
5467 expression.
5469 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5470 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5471 of a condition. */
5473 static rtx
5476 {
5479 rtx temp;
5482 /* If this is a commutative operation, put a constant last and a complex
5483 expression first. We don't need to do this for comparisons here. */
5486 {
5490 }
5492 /* Try to fold this expression in case we have constants that weren't
5493 present before. */
5496 {
5504 {
5507 {
5511 }
5514 }
5527 }
5530 {
5535 }
5537 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5538 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5539 things. Check for cases where both arms are testing the same
5540 condition.
5542 Don't do anything if all operands are very simple. */
5555 {
5560 /* If everything is a comparison, what we have is highly unlikely
5561 to be simpler, so don't use it. */
5564 {
5571 /* Simplify the alternative arms; this may collapse the true and
5572 false arms to store-flag values. Be careful to use copy_rtx
5573 here since true_rtx or false_rtx might share RTL with x as a
5574 result of the if_then_else_cond call above. */
5578 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5579 is unlikely to be simpler. */
5582 {
5585 /* Restarting if we generate a store-flag expression will cause
5586 us to loop. Just drop through in this case. */
5588 /* If the result values are STORE_FLAG_VALUE and zero, we can
5589 just make the comparison operation. */
5600 /* Likewise, we can make the negate of a comparison operation
5601 if the result values are - STORE_FLAG_VALUE and zero. */
5609 mode);
5620 mode);
5621 else
5624 mode,
5625 VOIDmode,
5626 cond,
5627 cop1),
5632 }
5633 }
5634 }
5636 /* First see if we can apply the inverse distributive law. */
5639 {
5643 }
5645 /* If CODE is an associative operation not otherwise handled, see if we
5646 can associate some operands. This can win if they are constants or
5647 if they are logically related (i.e. (a & b) & a). */
5653 {
5655 {
5659 rtx inner;
5661 /* Make sure we pass the constant operand if any as the second
5662 one if this is a commutative operation. */
5670 /* For commutative operations, try the other pair if that one
5671 didn't simplify. */
5673 {
5678 }
5682 }
5683 }
5685 /* A little bit of algebraic simplification here. */
5687 {
5689 /* Ensure that our address has any ASHIFTs converted to MULT in case
5690 address-recognizing predicates are called later. */
5699 /* See if this can be moved to simplify_subreg. */
5702 /* Don't call gen_lowpart if the inner mode
5703 is VOIDmode and we cannot simplify it, as SUBREG without
5704 inner mode is invalid. */
5711 {
5712 rtx temp;
5718 /* If op is known to have all lower bits zero, the result is zero. */
5728 }
5730 /* Don't change the mode of the MEM if that would change the meaning
5731 of the address. */
5738 /* Note that we cannot do any narrowing for non-constants since
5739 we might have been counting on using the fact that some bits were
5740 zero. We now do this in the SET. */
5747 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5748 replaced by (lshiftrt X C). This will convert
5749 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5757 /* If X has only a single bit that might be nonzero, say, bit I, convert
5758 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5759 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5760 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5761 or a SUBREG of one since we'd be making the expression more
5762 complex if it was just a register. */
5768 {
5769 rtx temp1 = simplify_shift_const
5775 /* If all we did was surround TEMP with the two shifts, we
5776 haven't improved anything, so don't use it. Otherwise,
5777 we are better off with TEMP1. */
5782 }
5786 /* We can't handle truncation to a partial integer mode here
5787 because we don't know the real bitsize of the partial
5788 integer mode. */
5797 /* We can truncate a constant value and return it. */
5801 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5802 whose value is a comparison can be replaced with a subreg if
5803 STORE_FLAG_VALUE permits. */
5812 /* (const (const X)) can become (const X). Do it this way rather than
5813 returning the inner CONST since CONST can be shared with a
5814 REG_EQUAL note. */
5820 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5821 can add in an offset. find_split_point will split this address up
5822 again if it doesn't match. */
5829 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5830 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5831 bit-field and can be replaced by either a sign_extend or a
5832 sign_extract. The `and' may be a zero_extend and the two
5833 <c>, -<c> constants may be reversed. */
5848 return simplify_shift_const
5855 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5856 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5857 the bitsize of the mode - 1. This allows simplification of
5858 "a = (b & 8) == 0;" */
5870 /* If we are adding two things that have no bits in common, convert
5871 the addition into an IOR. This will often be further simplified,
5872 for example in cases like ((a & 1) + (a & 2)), which can
5873 become a & 3. */
5878 {
5879 /* Try to simplify the expression further. */
5883 /* If we could, great. If not, do not go ahead with the IOR
5884 replacement, since PLUS appears in many special purpose
5885 address arithmetic instructions. */
5893 }
5897 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5898 (and <foo> (const_int pow2-1)) */
5908 /* If we have (mult (plus A B) C), apply the distributive law and then
5909 the inverse distributive law to see if things simplify. This
5910 occurs mostly in addresses, often when unrolling loops. */
5913 {
5917 }
5919 /* Try simplify a*(b/c) as (a*b)/c. */
5922 {
5928 }
5932 /* If this is a divide by a power of two, treat it as a shift if
5933 its first operand is a shift. */
5951 /* If the first operand is a condition code, we can't do anything
5952 with it. */
5956 {
5964 /* Simplify our comparison, if possible. */
5967 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5968 if only the low-order bit is possibly nonzero in X (such as when
5969 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5970 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5971 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5972 (plus X 1).
5974 Remove any ZERO_EXTRACT we made when thinking this was a
5975 comparison. It may now be simpler to use, e.g., an AND. If a
5976 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5977 the call to make_compound_operation in the SET case.
5979 Don't apply these optimizations if the caller would
5980 prefer a comparison rather than a value.
5981 E.g., for the condition in an IF_THEN_ELSE most targets need
5982 an explicit comparison. */
5985 ;
6001 {
6005 mode);
6006 }
6013 {
6017 const1_rtx);
6018 }
6026 {
6029 }
6031 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6032 those above. */
6034 ;
6050 {
6054 mode);
6055 }
6063 {
6067 mode);
6068 }
6070 /* If X is 0/1, (eq X 0) is X-1. */
6076 {
6079 }
6081 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6082 one bit that might be nonzero, we can convert (ne x 0) to
6083 (ashift x c) where C puts the bit in the sign bit. Remove any
6084 AND with STORE_FLAG_VALUE when we are done, since we are only
6085 going to test the sign bit. */
6092 {
6098 else
6100 }
6102 /* If the code changed, return a whole new comparison.
6103 We also need to avoid using SUBST in cases where
6104 simplify_comparison has widened a comparison with a CONST_INT,
6105 since in that case the wider CONST_INT may fail the sanity
6106 checks in do_SUBST. */
6113 /* Otherwise, keep this operation, but maybe change its operands.
6114 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6117 }
6127 /* If we are processing SET_DEST, we are done. */
6145 /* If this is a shift by a constant amount, simplify it. */
6161 }
6164 }
6165 \f
6166 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6168 static rtx
6170 {
6177 rtx temp;
6180 rtx reversed;
6182 /* Simplify storing of the truth value. */
6187 /* Also when the truth value has to be reversed. */
6193 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6194 in it is being compared against certain values. Get the true and false
6195 comparisons and see if that says anything about the value of each arm. */
6201 {
6202 HOST_WIDE_INT nzb;
6208 /* If FALSE_CODE is EQ, swap the codes and arms. */
6211 {
6214 }
6216 /* If we are comparing against zero and the expression being tested has
6217 only a single bit that might be nonzero, that is its value when it is
6218 not equal to zero. Similarly if it is known to be -1 or 0. */
6222 {
6225 }
6229 {
6232 }
6234 /* Now simplify an arm if we know the value of the register in the
6235 branch and it is used in the arm. Be careful due to the potential
6236 of locally-shared RTL. */
6253 }
6255 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6256 reversed, do so to avoid needing two sets of patterns for
6257 subtract-and-branch insns. Similarly if we have a constant in the true
6258 arm, the false arm is the same as the first operand of the comparison, or
6259 the false arm is more complicated than the true arm. */
6272 {
6281 /* It is possible that the conditional has been simplified out. */
6284 }
6286 /* If the two arms are identical, we don't need the comparison. */
6291 /* Convert a == b ? b : a to "a". */
6303 /* Look for cases where we have (abs x) or (neg (abs X)). */
6306 && comparison_p
6313 {
6319 return
6322 mode);
6325 }
6327 /* Look for MIN or MAX. */
6330 && comparison_p
6335 {
6350 }
6352 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6353 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6354 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6355 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6356 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6357 neither 1 or -1, but it isn't worth checking for. */
6360 && comparison_p
6363 {
6379 /* If an identity-zero op is commutative, check whether there
6380 would be a match if we swapped the operands. */
6400 {
6404 }
6416 {
6420 }
6436 {
6440 }
6452 {
6456 }
6459 {
6465 const_true_rtx));
6473 }
6474 }
6476 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6477 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6478 negation of a single bit, we can convert this operation to a shift. We
6479 can actually do this more generally, but it doesn't seem worth it. */
6488 return
6492 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6502 }
6503 \f
6504 /* Simplify X, a SET expression. Return the new expression. */
6506 static rtx
6508 {
6511 machine_mode mode
6516 /* (set (pc) (return)) gets written as (return). */
6520 /* Now that we know for sure which bits of SRC we are using, see if we can
6521 simplify the expression for the object knowing that we only need the
6522 low-order bits. */
6525 {
6528 }
6530 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6531 the comparison result and try to simplify it unless we already have used
6532 undobuf.other_insn. */
6540 {
6549 {
6552 {
6555 }
6556 }
6557 else
6565 {
6569 }
6570 else
6571 {
6576 /* Attempt to simplify CC user. */
6578 {
6582 }
6584 /* Convert X into a no-op move. */
6588 }
6590 /* Simplify our comparison, if possible. */
6593 #ifdef SELECT_CC_MODE
6594 /* If this machine has CC modes other than CCmode, check to see if we
6595 need to use a different CC mode here. */
6604 else
6607 /* If the mode changed, we have to change SET_DEST, the mode in the
6608 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6609 a hard register, just build new versions with the proper mode. If it
6610 is a pseudo, we lose unless it is only time we set the pseudo, in
6611 which case we can safely change its mode. */
6613 {
6615 {
6617 rtx new_dest;
6621 else
6622 {
6625 }
6632 }
6633 }
6636 /* If the code changed, we have to build a new comparison in
6637 undobuf.other_insn. */
6639 {
6648 /* If the only change we made was to change an EQ into an NE or
6649 vice versa, OP0 has only one bit that might be nonzero, and OP1
6650 is zero, check if changing the user of the condition code will
6651 produce a valid insn. If it won't, we can keep the original code
6652 in that insn by surrounding our operation with an XOR. */
6659 {
6664 {
6671 }
6672 }
6673 }
6678 /* Don't generate a compare of a CC with 0, just use that CC. */
6680 {
6683 }
6684 /* Otherwise, if we didn't previously have the same COMPARE we
6685 want, create it from scratch. */
6688 {
6691 }
6692 }
6693 else
6694 {
6695 /* Get SET_SRC in a form where we have placed back any
6696 compound expressions. Then do the checks below. */
6699 }
6701 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6702 and X being a REG or (subreg (reg)), we may be able to convert this to
6703 (set (subreg:m2 x) (op)).
6705 We can always do this if M1 is narrower than M2 because that means that
6706 we only care about the low bits of the result.
6708 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6709 perform a narrower operation than requested since the high-order bits will
6710 be undefined. On machine where it is defined, this transformation is safe
6711 as long as M1 and M2 have the same number of words. */
6719 && (WORD_REGISTER_OPERATIONS
6722 #ifdef CANNOT_CHANGE_MODE_CLASS
6727 #endif
6731 {
6734 dest));
6738 }
6740 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6741 in SRC. */
6747 {
6751 /* Here we make sure that we don't have a sign bit on. */
6754 {
6757 }
6758 }
6760 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6761 would require a paradoxical subreg. Replace the subreg with a
6762 zero_extend to avoid the reload that would otherwise be required. */
6770 {
6776 }
6778 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6779 are comparing an item known to be 0 or -1 against 0, use a logical
6780 operation instead. Check for one of the arms being an IOR of the other
6781 arm with some value. We compute three terms to be IOR'ed together. In
6782 practice, at most two will be nonzero. Then we do the IOR's. */
6790 && (!HAVE_conditional_move
6796 {
6822 false_rtx);
6828 term3));
6831 }
6833 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6834 whole thing fail. */
6839 else
6840 /* Convert this into a field assignment operation, if possible. */
6842 }
6843 \f
6844 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6845 result. */
6847 static rtx
6849 {
6855 {
6857 /* We can call simplify_and_const_int only if we don't lose
6858 any (sign) bits when converting INTVAL (op1) to
6859 "unsigned HOST_WIDE_INT". */
6863 {
6870 }
6872 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6873 apply the distributive law and then the inverse distributive
6874 law to see if things simplify. */
6876 {
6880 }
6882 {
6886 }
6890 /* If we have (ior (and A B) C), apply the distributive law and then
6891 the inverse distributive law to see if things simplify. */
6894 {
6898 }
6901 {
6905 }
6910 }
6913 }
6914 \f
6915 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6916 operations" because they can be replaced with two more basic operations.
6917 ZERO_EXTEND is also considered "compound" because it can be replaced with
6918 an AND operation, which is simpler, though only one operation.
6920 The function expand_compound_operation is called with an rtx expression
6921 and will convert it to the appropriate shifts and AND operations,
6922 simplifying at each stage.
6924 The function make_compound_operation is called to convert an expression
6925 consisting of shifts and ANDs into the equivalent compound expression.
6926 It is the inverse of this function, loosely speaking. */
6928 static rtx
6930 {
6934 rtx tem;
6937 {
6941 /* We can't necessarily use a const_int for a multiword mode;
6942 it depends on implicitly extending the value.
6943 Since we don't know the right way to extend it,
6944 we can't tell whether the implicit way is right.
6946 Even for a mode that is no wider than a const_int,
6947 we can't win, because we need to sign extend one of its bits through
6948 the rest of it, and we don't know which bit. */
6952 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6953 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6954 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6955 reloaded. If not for that, MEM's would very rarely be safe.
6957 Reject MODEs bigger than a word, because we might not be able
6958 to reference a two-register group starting with an arbitrary register
6959 (and currently gen_lowpart might crash for a SUBREG). */
6964 /* Reject MODEs that aren't scalar integers because turning vector
6965 or complex modes into shifts causes problems. */
6971 /* If the inner object has VOIDmode (the only way this can happen
6972 is if it is an ASM_OPERANDS), we can't do anything since we don't
6973 know how much masking to do. */
6982 /* ... fall through ... */
6985 /* If the operand is a CLOBBER, just return it. */
6994 /* Reject MODEs that aren't scalar integers because turning vector
6995 or complex modes into shifts causes problems. */
7003 /* This should stay within the object being extracted, fail otherwise. */
7014 }
7015 /* Convert sign extension to zero extension, if we know that the high
7016 bit is not set, as this is easier to optimize. It will be converted
7017 back to cheaper alternative in make_extraction. */
7025 {
7030 /* Make sure this is a profitable operation. */
7037 else
7039 }
7041 /* We can optimize some special cases of ZERO_EXTEND. */
7043 {
7044 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7045 know that the last value didn't have any inappropriate bits
7046 set. */
7054 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7063 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7064 is a comparison and STORE_FLAG_VALUE permits. This is like
7065 the first case, but it works even when GET_MODE (x) is larger
7066 than HOST_WIDE_INT. */
7075 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7085 }
7087 /* If we reach here, we want to return a pair of shifts. The inner
7088 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7089 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7090 logical depending on the value of UNSIGNEDP.
7092 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7093 converted into an AND of a shift.
7095 We must check for the case where the left shift would have a negative
7096 count. This can happen in a case like (x >> 31) & 255 on machines
7097 that can't shift by a constant. On those machines, we would first
7098 combine the shift with the AND to produce a variable-position
7099 extraction. Then the constant of 31 would be substituted in
7100 to produce such a position. */
7104 {
7113 }
7120 else
7121 /* Any other cases we can't handle. */
7124 /* If we couldn't do this for some reason, return the original
7125 expression. */
7130 }
7131 \f
7132 /* X is a SET which contains an assignment of one object into
7133 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7134 or certain SUBREGS). If possible, convert it into a series of
7135 logical operations.
7137 We half-heartedly support variable positions, but do not at all
7138 support variable lengths. */
7140 static const_rtx
7142 {
7143 rtx inner;
7147 machine_mode compute_mode;
7149 /* Loop until we find something we can't simplify. */
7151 {
7154 {
7158 }
7161 {
7166 /* A constant position should stay within the width of INNER. */
7172 {
7180 /* If position is ADJUST - X, new position is X. */
7182 else
7183 {
7188 pos);
7189 }
7190 }
7191 }
7193 /* A SUBREG between two modes that occupy the same numbers of words
7194 can be done by moving the SUBREG to the source. */
7196 /* We need SUBREGs to compute nonzero_bits properly. */
7197 && nonzero_sign_valid
7202 {
7204 gen_lowpart
7208 }
7209 else
7217 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7219 {
7220 machine_mode imode;
7222 /* Don't do anything for vector or complex integral types. */
7226 /* Try to find an integral mode to pun with. */
7233 }
7235 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7239 /* Now compute the equivalent expression. Make a copy of INNER
7240 for the SET_DEST in case it is a MEM into which we will substitute;
7241 we don't want shared RTL in that case. */
7243 compute_mode);
7247 compute_mode,
7249 compute_mode),
7250 inner);
7255 mask),
7256 pos);
7261 }
7264 }
7265 \f
7266 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7267 it is an RTX that represents the (variable) starting position; otherwise,
7268 POS is the (constant) starting bit position. Both are counted from the LSB.
7270 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7272 IN_DEST is nonzero if this is a reference in the destination of a SET.
7273 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7274 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7275 be used.
7277 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7278 ZERO_EXTRACT should be built even for bits starting at bit 0.
7280 MODE is the desired mode of the result (if IN_DEST == 0).
7282 The result is an RTX for the extraction or NULL_RTX if the target
7283 can't handle it. */
7285 static rtx
7289 {
7290 /* This mode describes the size of the storage area
7291 to fetch the overall value from. Within that, we
7292 ignore the POS lowest bits, etc. */
7294 machine_mode inner_mode;
7295 machine_mode wanted_inner_mode;
7302 HOST_WIDE_INT orig_pos;
7308 {
7309 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7310 consider just the QI as the memory to extract from.
7311 The subreg adds or removes high bits; its mode is
7312 irrelevant to the meaning of this extraction,
7313 since POS and LEN count from the lsb. */
7317 }
7322 {
7323 /* We're extracting the least significant bits of an rtx
7324 (ashift X (const_int C)), where LEN > C. Extract the
7325 least significant (LEN - C) bits of X, giving an rtx
7326 whose mode is MODE, then shift it left C times. */
7332 }
7338 /* See if this can be done without an extraction. We never can if the
7339 width of the field is not the same as that of some integer mode. For
7340 registers, we can only avoid the extraction if the position is at the
7341 low-order bit and this is either not in the destination or we have the
7342 appropriate STRICT_LOW_PART operation available.
7344 For MEM, we can avoid an extract if the field starts on an appropriate
7345 boundary and we can change the mode of the memory reference. */
7354 && (! in_dest
7358 && (pos
7361 /* We can't do this if we are widening INNER_MODE (it
7362 may not be aligned, for one thing). */
7368 {
7369 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7370 field. If the original and current mode are the same, we need not
7371 adjust the offset. Otherwise, we do if bytes big endian.
7373 If INNER is not a MEM, get a piece consisting of just the field
7374 of interest (in this case POS % BITS_PER_WORD must be 0). */
7377 {
7378 HOST_WIDE_INT offset;
7380 /* POS counts from lsb, but make OFFSET count in memory order. */
7383 else
7387 }
7389 {
7391 {
7392 /* We can't call gen_lowpart in a DEST since we
7393 always want a SUBREG (see below) and it would sometimes
7394 return a new hard register. */
7396 {
7411 /* Avoid creating invalid subregs, for example when
7412 simplifying (x>>32)&255. */
7417 }
7418 else
7420 }
7421 else
7423 }
7424 else
7426 len >= HOST_BITS_PER_WIDE_INT
7431 /* If this extraction is going into the destination of a SET,
7432 make a STRICT_LOW_PART unless we made a MEM. */
7447 /* If we know that no extraneous bits are set, and that the high
7448 bit is not set, convert the extraction to the cheaper of
7449 sign and zero extension, that are equivalent in these cases. */
7455 {
7459 /* Prefer ZERO_EXTENSION, since it gives more information to
7460 backends. */
7465 }
7467 /* Otherwise, sign- or zero-extend unless we already are in the
7468 proper mode. */
7472 }
7474 /* Unless this is a COMPARE or we have a funny memory reference,
7475 don't do anything with zero-extending field extracts starting at
7476 the low-order bit since they are simple AND operations. */
7481 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7482 if the position is not a constant and the length is not 1. In all
7483 other cases, we would only be going outside our object in cases when
7484 an original shift would have been undefined. */
7493 /* If INNER is not from memory, we want it to have the mode of a register
7494 extraction pattern's structure operand, or word_mode if there is no
7495 such pattern. The same applies to extraction_mode and pos_mode
7496 and their respective operands.
7498 For memory, assume that the desired extraction_mode and pos_mode
7499 are the same as for a register operation, since at present we don't
7500 have named patterns for aligned memory structures. */
7504 {
7508 }
7510 /* Never narrow an object, since that might not be safe. */
7518 else
7519 {
7520 /* Be careful not to go beyond the extracted object and maintain the
7521 natural alignment of the memory. */
7525 {
7528 }
7529 }
7534 {
7535 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7536 BITS_BIG_ENDIAN style. If position is constant, compute new
7537 position. Otherwise, build subtraction.
7538 Note that POS is relative to the mode of the original argument.
7539 If it's a MEM we need to recompute POS relative to that.
7540 However, if we're extracting from (or inserting into) a register,
7541 we want to recompute POS relative to wanted_inner_mode. */
7548 else
7549 pos_rtx
7552 pos_rtx);
7553 /* POS may be less than 0 now, but we check for that below.
7554 Note that it can only be less than 0 if !MEM_P (inner). */
7555 }
7557 /* If INNER has a wider mode, and this is a constant extraction, try to
7558 make it smaller and adjust the byte to point to the byte containing
7559 the value. */
7562 && ! pos_rtx
7567 {
7570 /* The computations below will be correct if the machine is big
7571 endian in both bits and bytes or little endian in bits and bytes.
7572 If it is mixed, we must adjust. */
7574 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7575 adjust OFFSET to compensate. */
7580 /* We can now move to the desired byte. */
7591 }
7593 /* If INNER is not memory, get it into the proper mode. If we are changing
7594 its mode, POS must be a constant and smaller than the size of the new
7595 mode. */
7597 {
7598 /* On the LHS, don't create paradoxical subregs implicitely truncating
7599 the register unless TRULY_NOOP_TRUNCATION. */
7602 wanted_inner_mode))
7614 pos_rtx
7620 }
7622 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7623 have to zero extend. Otherwise, we can just use a SUBREG. */
7626 {
7630 /* If we know that no extraneous bits are set, and that the high
7631 bit is not set, convert extraction to cheaper one - either
7632 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7633 cases. */
7641 {
7645 /* Prefer ZERO_EXTENSION, since it gives more information to
7646 backends. */
7650 }
7652 }
7654 /* Make POS_RTX unless we already have it and it is correct. If we don't
7655 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7656 be a CONST_INT. */
7663 /* Make the required operation. See if we can use existing rtx. */
7670 }
7671 \f
7672 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7673 with any other operations in X. Return X without that shift if so. */
7675 static rtx
7677 {
7680 rtx tem;
7683 {
7685 /* This is the shift itself. If it is wide enough, we will return
7686 either the value being shifted if the shift count is equal to
7687 COUNT or a shift for the difference. */
7701 /* If we can safely shift this constant and we find the inner shift,
7702 make a new operation. */
7707 {
7711 }
7716 }
7719 }
7720 \f
7721 /* Look at the expression rooted at X. Look for expressions
7722 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7723 Form these expressions.
7725 Return the new rtx, usually just X.
7727 Also, for machines like the VAX that don't have logical shift insns,
7728 try to convert logical to arithmetic shift operations in cases where
7729 they are equivalent. This undoes the canonicalizations to logical
7730 shifts done elsewhere.
7732 We try, as much as possible, to re-use rtl expressions to save memory.
7734 IN_CODE says what kind of expression we are processing. Normally, it is
7735 SET. In a memory address it is MEM. When processing the arguments of
7736 a comparison or a COMPARE against zero, it is COMPARE. */
7738 rtx
7740 {
7748 rtx tem;
7751 /* Select the code to be used in recursive calls. Once we are inside an
7752 address, we stay there. If we have a comparison, set to COMPARE,
7753 but once inside, go back to our default of SET. */
7760 /* Process depending on the code of this operation. If NEW is set
7761 nonzero, it will be returned. */
7764 {
7766 /* Convert shifts by constants into multiplications if inside
7767 an address. */
7772 {
7778 {
7781 }
7784 }
7794 {
7798 }
7801 {
7805 mode));
7807 }
7808 else
7809 {
7813 }
7824 {
7828 }
7831 {
7835 mode));
7837 }
7838 else
7839 {
7843 }
7847 /* If the second operand is not a constant, we can't do anything
7848 with it. */
7852 /* If the constant is a power of two minus one and the first operand
7853 is a logical right shift, make an extraction. */
7856 {
7860 }
7862 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7867 {
7869 next_code);
7874 /* If that didn't give anything, see if the AND simplifies on
7875 its own. */
7877 {
7881 }
7882 }
7883 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7889 {
7890 /* Apply the distributive law, and then try to make extractions. */
7897 }
7899 /* If we are have (and (rotate X C) M) and C is larger than the number
7900 of bits in M, this is an extraction. */
7906 {
7912 }
7914 /* On machines without logical shifts, if the operand of the AND is
7915 a logical shift and our mask turns off all the propagated sign
7916 bits, we can replace the logical shift with an arithmetic shift. */
7924 {
7931 make_compound_operation
7934 }
7936 /* If the constant is one less than a power of two, this might be
7937 representable by an extraction even if no shift is present.
7938 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7939 we are in a COMPARE. */
7943 next_code),
7946 /* If we are in a comparison and this is an AND with a power of two,
7947 convert this into the appropriate bit extract. */
7952 next_code),
7958 /* If the sign bit is known to be zero, replace this with an
7959 arithmetic shift. */
7964 {
7967 next_code),
7970 }
7972 /* ... fall through ... */
7978 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7979 this is a SIGN_EXTRACT. */
7986 {
7993 }
7995 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7996 If so, try to merge the shifts into a SIGN_EXTEND. We could
7997 also do this for some cases of SIGN_EXTRACT, but it doesn't
7998 seem worth the effort; the case checked for occurs on Alpha. */
8014 /* Call ourselves recursively on the inner expression. If we are
8015 narrowing the object and it has a different RTL code from
8016 what it originally did, do this SUBREG as a force_to_mode. */
8017 {
8021 /* If in_code is COMPARE, it isn't always safe to pass it through
8022 to the recursive make_compound_operation call. */
8026 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8027 is (const_int 0), rather than
8028 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8038 simplified
8046 {
8047 rtx newer
8050 /* If we have something other than a SUBREG, we might have
8051 done an expansion, so rerun ourselves. */
8055 /* force_to_mode can expand compounds. If it just re-expanded the
8056 compound, use gen_lowpart to convert to the desired mode. */
8058 /* Likewise if it re-expanded the compound only partially.
8059 This happens for SUBREG of ZERO_EXTRACT if they extract
8060 the same number of bits. */
8069 }
8073 }
8078 }
8081 {
8084 }
8086 /* Now recursively process each operand of this operation. We need to
8087 handle ZERO_EXTEND specially so that we don't lose track of the
8088 inner mode. */
8090 {
8098 }
8103 {
8106 }
8109 {
8112 }
8114 maybe_swap:
8115 /* If this is a commutative operation, the changes to the operands
8116 may have made it noncanonical. */
8119 {
8123 }
8126 }
8127 \f
8128 /* Given M see if it is a value that would select a field of bits
8129 within an item, but not the entire word. Return -1 if not.
8130 Otherwise, return the starting position of the field, where 0 is the
8131 low-order bit.
8133 *PLEN is set to the length of the field. */
8135 static int
8137 {
8138 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8143 /* Now shift off the low-order zero bits and see if we have a
8144 power of two minus 1. */
8152 }
8153 \f
8154 /* If X refers to a register that equals REG in value, replace these
8155 references with REG. */
8156 static rtx
8158 {
8166 {
8202 {
8206 else
8208 }
8210 /* fall through */
8217 {
8220 {
8222 {
8225 }
8227 }
8228 }
8230 {
8233 {
8236 {
8238 {
8241 }
8243 }
8244 }
8245 }
8248 }
8251 }
8253 /* Return X converted to MODE. If the value is already truncated to
8254 MODE we can just return a subreg even though in the general case we
8255 would need an explicit truncation. */
8257 static rtx
8259 {
8264 {
8265 /* Bit-cast X into an integer mode. */
8270 }
8273 }
8275 /* See if X can be simplified knowing that we will only refer to it in
8276 MODE and will only refer to those bits that are nonzero in MASK.
8277 If other bits are being computed or if masking operations are done
8278 that select a superset of the bits in MASK, they can sometimes be
8279 ignored.
8281 Return a possibly simplified expression, but always convert X to
8282 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8284 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8285 are all off in X. This is used when X will be complemented, by either
8286 NOT, NEG, or XOR. */
8288 static rtx
8291 {
8294 machine_mode op_mode;
8298 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8299 code below will do the wrong thing since the mode of such an
8300 expression is VOIDmode.
8302 Also do nothing if X is a CLOBBER; this can happen if X was
8303 the return value from a call to gen_lowpart. */
8307 /* We want to perform the operation in its present mode unless we know
8308 that the operation is valid in MODE, in which case we do the operation
8309 in MODE. */
8314 /* It is not valid to do a right-shift in a narrower mode
8315 than the one it came in with. */
8320 /* Truncate MASK to fit OP_MODE. */
8324 /* When we have an arithmetic operation, or a shift whose count we
8325 do not know, we need to assume that all bits up to the highest-order
8326 bit in MASK will be needed. This is how we form such a mask. */
8329 else
8333 /* Determine what bits of X are guaranteed to be (non)zero. */
8336 /* If none of the bits in X are needed, return a zero. */
8340 /* If X is a CONST_INT, return a new one. Do this here since the
8341 test below will fail. */
8343 {
8346 else
8347 {
8350 }
8351 }
8353 /* If X is narrower than MODE and we want all the bits in X's mode, just
8354 get X in the proper mode. */
8359 /* We can ignore the effect of a SUBREG if it narrows the mode or
8360 if the constant masks to zero all the bits the mode doesn't have. */
8370 /* The arithmetic simplifications here only work for scalar integer modes. */
8375 {
8377 /* If X is a (clobber (const_int)), return it since we know we are
8378 generating something that won't match. */
8391 /* Similarly for a truncate. */
8395 /* If this is an AND with a constant, convert it into an AND
8396 whose constant is the AND of that constant with MASK. If it
8397 remains an AND of MASK, delete it since it is redundant. */
8400 {
8404 /* If X is still an AND, see if it is an AND with a mask that
8405 is just some low-order bits. If so, and it is MASK, we don't
8406 need it. */
8413 /* If it remains an AND, try making another AND with the bits
8414 in the mode mask that aren't in MASK turned on. If the
8415 constant in the AND is wide enough, this might make a
8416 cheaper constant. */
8421 {
8422 unsigned HOST_WIDE_INT cval
8425 rtx y;
8432 }
8435 }
8440 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8441 low-order bits (as in an alignment operation) and FOO is already
8442 aligned to that boundary, mask C1 to that boundary as well.
8443 This may eliminate that PLUS and, later, the AND. */
8445 {
8449 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8450 number, sign extend it. */
8463 }
8465 /* ... fall through ... */
8468 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8469 most significant bit in MASK since carries from those bits will
8470 affect the bits we are interested in. */
8475 /* If X is (minus C Y) where C's least set bit is larger than any bit
8476 in the mask, then we may replace with (neg Y). */
8479 {
8483 }
8485 /* Similarly, if C contains every bit in the fuller_mask, then we may
8486 replace with (not Y). */
8489 {
8493 }
8500 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8501 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8502 operation which may be a bitfield extraction. Ensure that the
8503 constant we form is not wider than the mode of X. */
8515 {
8524 }
8526 binop:
8527 /* For most binary operations, just propagate into the operation and
8528 change the mode if we have an operation of that mode. */
8533 /* If we ended up truncating both operands, truncate the result of the
8534 operation instead. */
8537 {
8540 }
8550 /* For left shifts, do the same, but just for the first operand.
8551 However, we cannot do anything with shifts where we cannot
8552 guarantee that the counts are smaller than the size of the mode
8553 because such a count will have a different meaning in a
8554 wider mode. */
8564 /* If the shift count is a constant and we can do arithmetic in
8565 the mode of the shift, refine which bits we need. Otherwise, use the
8566 conservative form of the mask. */
8572 else
8584 /* Here we can only do something if the shift count is a constant,
8585 this shift constant is valid for the host, and we can do arithmetic
8586 in OP_MODE. */
8592 {
8596 /* Select the mask of the bits we need for the shift operand. */
8599 /* We can only change the mode of the shift if we can do arithmetic
8600 in the mode of the shift and INNER_MASK is no wider than the
8601 width of X's mode. */
8609 }
8611 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8612 shift and AND produces only copies of the sign bit (C2 is one less
8613 than a power of two), we can do this with just a shift. */
8617 /* The shift puts one of the sign bit copies in the least significant
8618 bit. */
8623 /* Number of bits left after the shift must be more than the mask
8624 needs. */
8627 /* Must be more sign bit copies than the mask needs. */
8637 /* If we are just looking for the sign bit, we don't need this shift at
8638 all, even if it has a variable count. */
8642 /* If this is a shift by a constant, get a mask that contains those bits
8643 that are not copies of the sign bit. We then have two cases: If
8644 MASK only includes those bits, this can be a logical shift, which may
8645 allow simplifications. If MASK is a single-bit field not within
8646 those bits, we are requesting a copy of the sign bit and hence can
8647 shift the sign bit to the appropriate location. */
8651 {
8654 /* If the considered data is wider than HOST_WIDE_INT, we can't
8655 represent a mask for all its bits in a single scalar.
8656 But we only care about the lower bits, so calculate these. */
8659 {
8662 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8663 is the number of bits a full-width mask would have set.
8664 We need only shift if these are fewer than nonzero can
8665 hold. If not, we must keep all bits set in nonzero. */
8670 + HOST_BITS_PER_WIDE_INT
8672 }
8673 else
8674 {
8677 }
8680 {
8685 }
8688 {
8689 x = simplify_shift_const
8695 }
8696 }
8698 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8699 even if the shift count isn't a constant. */
8704 shiftrt:
8706 /* If this is a zero- or sign-extension operation that just affects bits
8707 we don't care about, remove it. Be sure the call above returned
8708 something that is still a shift. */
8718 next_select);
8724 /* If the shift count is constant and we can do computations
8725 in the mode of X, compute where the bits we care about are.
8726 Otherwise, we can't do anything. Don't change the mode of
8727 the shift or propagate MODE into the shift, though. */
8730 {
8740 }
8744 /* If we just want the low-order bit, the NEG isn't needed since it
8745 won't change the low-order bit. */
8749 /* We need any bits less significant than the most significant bit in
8750 MASK since carries from those bits will affect the bits we are
8751 interested in. */
8756 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8757 same as the XOR case above. Ensure that the constant we form is not
8758 wider than the mode of X. */
8766 {
8775 }
8777 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8778 use the full mask inside the NOT. */
8781 unop:
8784 next_select));
8790 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8791 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8792 which is equal to STORE_FLAG_VALUE. */
8804 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8805 written in a narrower mode. We play it safe and do not do so. */
8821 }
8823 /* Ensure we return a value of the proper mode. */
8825 }
8826 \f
8827 /* Return nonzero if X is an expression that has one of two values depending on
8828 whether some other value is zero or nonzero. In that case, we return the
8829 value that is being tested, *PTRUE is set to the value if the rtx being
8830 returned has a nonzero value, and *PFALSE is set to the other alternative.
8832 If we return zero, we set *PTRUE and *PFALSE to X. */
8834 static rtx
8836 {
8842 /* If we are comparing a value against zero, we are done. */
8845 {
8849 }
8851 /* If this is a unary operation whose operand has one of two values, apply
8852 our opcode to compute those values. */
8855 {
8860 }
8862 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8863 make can't possibly match and would suppress other optimizations. */
8865 ;
8867 /* If this is a binary operation, see if either side has only one of two
8868 values. If either one does or if both do and they are conditional on
8869 the same value, compute the new true and false values. */
8871 {
8877 {
8878 /* If if_then_else_cond returned zero, then true/false are the
8879 same rtl. We must copy one of them to prevent invalid rtl
8880 sharing. */
8887 {
8892 }
8893 else
8894 {
8897 }
8900 }
8902 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8903 operands is zero when the other is nonzero, and vice-versa,
8904 and STORE_FLAG_VALUE is 1 or -1. */
8910 {
8927 {
8934 const_true_rtx);
8936 }
8937 }
8939 /* Similarly for MULT, AND and UMIN, except that for these the result
8940 is always zero. */
8944 {
8958 {
8961 }
8962 }
8963 }
8966 {
8967 /* If we have IF_THEN_ELSE already, extract the condition and
8968 canonicalize it if it is NE or EQ. */
8974 {
8977 }
8978 else
8980 }
8982 /* If X is a SUBREG, we can narrow both the true and false values
8983 if the inner expression, if there is a condition. */
8987 {
8993 {
8997 }
8998 }
9000 /* If X is a constant, this isn't special and will cause confusions
9001 if we treat it as such. Likewise if it is equivalent to a constant. */
9004 ;
9006 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9007 will be least confusing to the rest of the compiler. */
9009 {
9012 }
9014 /* If X is known to be either 0 or -1, those are the true and
9015 false values when testing X. */
9019 {
9022 }
9024 /* Likewise for 0 or a single bit. */
9027 {
9030 }
9032 /* Otherwise fail; show no condition with true and false values the same. */
9035 }
9036 \f
9037 /* Return the value of expression X given the fact that condition COND
9038 is known to be true when applied to REG as its first operand and VAL
9039 as its second. X is known to not be shared and so can be modified in
9040 place.
9042 We only handle the simplest cases, and specifically those cases that
9043 arise with IF_THEN_ELSE expressions. */
9045 static rtx
9047 {
9055 /* If either operand of the condition is a floating point value,
9056 then we have to avoid collapsing an EQ comparison. */
9066 /* If X is (abs REG) and we know something about REG's relationship
9067 with zero, we may be able to simplify this. */
9071 {
9080 }
9082 /* The only other cases we handle are MIN, MAX, and comparisons if the
9083 operands are the same as REG and VAL. */
9086 {
9088 {
9091 }
9094 {
9096 {
9104 else
9106 }
9109 {
9112 /* Do not reverse the condition when it is NE or EQ.
9113 This is because we cannot conclude anything about
9114 the value of 'SMAX (x, y)' when x is not equal to y,
9115 but we can when x equals y. */
9121 {
9132 }
9133 }
9134 }
9135 }
9137 {
9142 {
9143 /* We must simplify subreg here, before we lose track of the
9144 original inner_mode. */
9149 else
9151 }
9154 }
9155 /* We don't have to handle SIGN_EXTEND here, because even in the
9156 case of replacing something with a modeless CONST_INT, a
9157 CONST_INT is already (supposed to be) a valid sign extension for
9158 its narrower mode, which implies it's already properly
9159 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9160 story is different. */
9162 {
9167 {
9168 /* We must simplify the zero_extend here, before we lose
9169 track of the original inner_mode. */
9174 else
9176 }
9179 }
9183 {
9190 }
9193 }
9194 \f
9195 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9196 assignment as a field assignment. */
9198 static int
9200 {
9202 {
9207 /* For big endian, adjust the memory offset. */
9212 else
9214 }
9222 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9223 Note that all SUBREGs of MEM are paradoxical; otherwise they
9224 would have been rewritten. */
9237 /* We used to see if get_last_value of X and Y were the same but that's
9238 not correct. In one direction, we'll cause the assignment to have
9239 the wrong destination and in the case, we'll import a register into this
9240 insn that might have already have been dead. So fail if none of the
9241 above cases are true. */
9243 }
9244 \f
9245 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9246 Return that assignment if so.
9248 We only handle the most common cases. */
9250 static rtx
9252 {
9255 rtx assign;
9257 HOST_WIDE_INT c1;
9258 HOST_WIDE_INT pos;
9260 rtx other;
9261 machine_mode mode;
9263 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9264 a clear of a one-bit field. We will have changed it to
9265 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9266 for a SUBREG. */
9272 {
9278 }
9288 {
9295 }
9297 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9298 one-bit field. */
9302 {
9308 }
9310 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9311 SRC is an AND with all bits of that field set, then we can discard
9312 the AND. */
9317 {
9324 else
9327 /* Complete overlap. We can remove the source AND. */
9331 /* Partial overlap. We can reduce the source AND. */
9333 {
9338 }
9339 }
9341 /* The other case we handle is assignments into a constant-position
9342 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9343 a mask that has all one bits except for a group of zero bits and
9344 OTHER is known to have zeros where C1 has ones, this is such an
9345 assignment. Compute the position and length from C1. Shift OTHER
9346 to the appropriate position, force it to the required mode, and
9347 make the extraction. Check for the AND in both operands. */
9349 /* One or more SUBREGs might obscure the constant-position field
9350 assignment. The first one we are likely to encounter is an outer
9351 narrowing SUBREG, which we can just strip for the purposes of
9352 identifying the constant-field assignment. */
9366 /* The second SUBREG that might get in the way is a paradoxical
9367 SUBREG around the first operand of the AND. We want to
9368 pretend the operand is as wide as the destination here. We
9369 do this by adjusting the MEM to wider mode for the sole
9370 purpose of the call to rtx_equal_for_field_assignment_p. Also
9371 note this trick only works for MEMs. */
9383 /* The second SUBREG that might get in the way is a paradoxical
9384 SUBREG around the first operand of the AND. We want to
9385 pretend the operand is as wide as the destination here. We
9386 do this by adjusting the MEM to wider mode for the sole
9387 purpose of the call to rtx_equal_for_field_assignment_p. Also
9388 note this trick only works for MEMs. */
9396 else
9409 /* The mode to use for the source is the mode of the assignment, or of
9410 what is inside a possible STRICT_LOW_PART. */
9414 /* Shift OTHER right POS places and make it the source, restricting it
9415 to the proper length and mode. */
9420 dest);
9427 /* If SRC is masked by an AND that does not make a difference in
9428 the value being stored, strip it. */
9439 }
9440 \f
9441 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9442 if so. */
9444 static rtx
9446 {
9450 rtx tem;
9452 /* Distributivity is not true for floating point as it can change the
9453 value. So we don't do it unless -funsafe-math-optimizations. */
9458 /* The outer operation can only be one of the following: */
9466 /* If either operand is a primitive we can't do anything, so get out
9467 fast. */
9477 /* See if the inner and outer operations distribute. */
9479 {
9484 /* These all distribute except over PLUS. */
9495 /* This is also a multiply, so it distributes over everything. */
9498 /* This used to handle SUBREG, but this turned out to be counter-
9499 productive, since (subreg (op ...)) usually is not handled by
9500 insn patterns, and this "optimization" therefore transformed
9501 recognizable patterns into unrecognizable ones. Therefore the
9502 SUBREG case was removed from here.
9504 It is possible that distributing SUBREG over arithmetic operations
9505 leads to an intermediate result than can then be optimized further,
9506 e.g. by moving the outer SUBREG to the other side of a SET as done
9507 in simplify_set. This seems to have been the original intent of
9508 handling SUBREGs here.
9510 However, with current GCC this does not appear to actually happen,
9511 at least on major platforms. If some case is found where removing
9512 the SUBREG case here prevents follow-on optimizations, distributing
9513 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9517 }
9519 /* Set LHS and RHS to the inner operands (A and B in the example
9520 above) and set OTHER to the common operand (C in the example).
9521 There is only one way to do this unless the inner operation is
9522 commutative. */
9534 else
9537 /* Form the new inner operation, seeing if it simplifies first. */
9540 /* There is one exception to the general way of distributing:
9541 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9543 {
9546 }
9548 /* We may be able to continuing distributing the result, so call
9549 ourselves recursively on the inner operation before forming the
9550 outer operation, which we return. */
9553 }
9555 /* See if X is of the form (* (+ A B) C), and if so convert to
9556 (+ (* A C) (* B C)) and try to simplify.
9558 Most of the time, this results in no change. However, if some of
9559 the operands are the same or inverses of each other, simplifications
9560 will result.
9562 For example, (and (ior A B) (not B)) can occur as the result of
9563 expanding a bit field assignment. When we apply the distributive
9564 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9565 which then simplifies to (and (A (not B))).
9567 Note that no checks happen on the validity of applying the inverse
9568 distributive law. This is pointless since we can do it in the
9569 few places where this routine is called.
9571 N is the index of the term that is decomposed (the arithmetic operation,
9572 i.e. (+ A B) in the first example above). !N is the index of the term that
9573 is distributed, i.e. of C in the first example above. */
9574 static rtx
9576 {
9577 machine_mode mode;
9581 /* Distributivity is not true for floating point as it can change the
9582 value. So we don't do it unless -funsafe-math-optimizations. */
9599 /* Special case (and (xor B C) (not A)), which is equivalent to
9600 (xor (ior A B) (ior A C)) */
9602 {
9605 }
9608 {
9609 /* Distribute the second term. */
9612 }
9613 else
9614 {
9615 /* Distribute the first term. */
9618 }
9628 }
9629 \f
9630 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9631 in MODE. Return an equivalent form, if different from (and VAROP
9632 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9634 static rtx
9637 {
9640 rtx orig_varop;
9648 /* Simplify VAROP knowing that we will be only looking at some of the
9649 bits in it.
9651 Note by passing in CONSTOP, we guarantee that the bits not set in
9652 CONSTOP are not significant and will never be examined. We must
9653 ensure that is the case by explicitly masking out those bits
9654 before returning. */
9657 /* If VAROP is a CLOBBER, we will fail so return it. */
9661 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9662 to VAROP and return the new constant. */
9666 /* See what bits may be nonzero in VAROP. Unlike the general case of
9667 a call to nonzero_bits, here we don't care about bits outside
9668 MODE. */
9672 /* Turn off all bits in the constant that are known to already be zero.
9673 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9674 which is tested below. */
9678 /* If we don't have any bits left, return zero. */
9682 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9683 a power of two, we can replace this with an ASHIFT. */
9688 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9689 or XOR, then try to apply the distributive law. This may eliminate
9690 operations if either branch can be simplified because of the AND.
9691 It may also make some cases more complex, but those cases probably
9692 won't match a pattern either with or without this. */
9695 return
9696 gen_lowpart
9698 apply_distributive_law
9703 constop),
9707 constop))));
9709 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9710 the AND and see if one of the operands simplifies to zero. If so, we
9711 may eliminate it. */
9715 {
9724 }
9726 /* Make a SUBREG if necessary. If we can't make it, fail. */
9731 /* If we are only masking insignificant bits, return VAROP. */
9738 /* Otherwise, return an AND. */
9740 }
9743 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9744 in MODE.
9746 Return an equivalent form, if different from X. Otherwise, return X. If
9747 X is zero, we are to always construct the equivalent form. */
9749 static rtx
9752 {
9763 }
9764 \f
9765 /* Given a REG, X, compute which bits in X can be nonzero.
9766 We don't care about bits outside of those defined in MODE.
9768 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9769 a shift, AND, or zero_extract, we can do better. */
9771 static rtx
9773 const_rtx known_x ATTRIBUTE_UNUSED,
9774 machine_mode known_mode ATTRIBUTE_UNUSED,
9777 {
9778 rtx tem;
9781 /* If X is a register whose nonzero bits value is current, use it.
9782 Otherwise, if X is a register whose value we can find, use that
9783 value. Otherwise, use the previously-computed global nonzero bits
9784 for this register. */
9798 && !REGNO_REG_SET_P
9801 {
9805 /* We don't know anything about the upper bits. */
9810 }
9815 {
9821 }
9823 {
9827 /* We don't know anything about the upper bits. */
9831 }
9834 }
9836 /* Return the number of bits at the high-order end of X that are known to
9837 be equal to the sign bit. X will be used in mode MODE; if MODE is
9838 VOIDmode, X will be used in its own mode. The returned value will always
9839 be between 1 and the number of bits in MODE. */
9841 static rtx
9843 const_rtx known_x ATTRIBUTE_UNUSED,
9844 machine_mode known_mode
9845 ATTRIBUTE_UNUSED,
9848 {
9849 rtx tem;
9862 && !REGNO_REG_SET_P
9865 {
9868 }
9879 }
9880 \f
9881 /* Return the number of "extended" bits there are in X, when interpreted
9882 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9883 unsigned quantities, this is the number of high-order zero bits.
9884 For signed quantities, this is the number of copies of the sign bit
9885 minus 1. In both case, this function returns the number of "spare"
9886 bits. For example, if two quantities for which this function returns
9887 at least 1 are added, the addition is known not to overflow.
9889 This function will always return 0 unless called during combine, which
9890 implies that it must be called from a define_split. */
9892 unsigned int
9894 {
9904 }
9906 /* This function is called from `simplify_shift_const' to merge two
9907 outer operations. Specifically, we have already found that we need
9908 to perform operation *POP0 with constant *PCONST0 at the outermost
9909 position. We would now like to also perform OP1 with constant CONST1
9910 (with *POP0 being done last).
9912 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9913 the resulting operation. *PCOMP_P is set to 1 if we would need to
9914 complement the innermost operand, otherwise it is unchanged.
9916 MODE is the mode in which the operation will be done. No bits outside
9917 the width of this mode matter. It is assumed that the width of this mode
9918 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9920 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9921 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9922 result is simply *PCONST0.
9924 If the resulting operation cannot be expressed as one operation, we
9925 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9927 static int
9928 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9929 {
9936 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9940 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9941 if OP0 is SET. */
9950 {
9952 {
9970 }
9971 }
9973 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9977 /* If the two constants aren't the same, we can't do anything. The
9978 remaining six cases can all be done. */
9982 else
9984 {
9987 /* (a & b) | b == b */
9990 /* (a ^ b) | b == a | b */
9991 {;}
9996 /* (a & b) ^ b == (~a) & b */
9999 /* (a | b) ^ b == a & ~b */
10005 /* (a | b) & b == b */
10008 /* (a ^ b) & b) == (~a) & b */
10013 }
10015 /* Check for NO-OP cases. */
10028 /* ??? Slightly redundant with the above mask, but not entirely.
10029 Moving this above means we'd have to sign-extend the mode mask
10030 for the final test. */
10035 }
10036 \f
10037 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10038 the shift in. The original shift operation CODE is performed on OP in
10039 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10040 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10041 result of the shift is subject to operation OUTER_CODE with operand
10042 OUTER_CONST. */
10044 static machine_mode
10048 {
10053 /* In general we can't perform in wider mode for right shift and rotate. */
10055 {
10057 /* We can still widen if the bits brought in from the left are identical
10058 to the sign bit of ORIG_MODE. */
10066 /* Similarly here but with zero bits. */
10071 /* We can also widen if the bits brought in will be masked off. This
10072 operation is performed in ORIG_MODE. */
10074 {
10080 }
10081 /* fall through */
10091 }
10092 }
10094 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10095 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10096 if we cannot simplify it. Otherwise, return a simplified value.
10098 The shift is normally computed in the widest mode we find in VAROP, as
10099 long as it isn't a different number of words than RESULT_MODE. Exceptions
10100 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10102 static rtx
10105 {
10111 unsigned int mode_words
10113 /* We form (outer_op (code varop count) (outer_const)). */
10119 /* Make sure and truncate the "natural" shift on the way in. We don't
10120 want to do this inside the loop as it makes it more difficult to
10121 combine shifts. */
10125 /* If we were given an invalid count, don't do anything except exactly
10126 what was requested. */
10133 /* Unless one of the branches of the `if' in this loop does a `continue',
10134 we will `break' the loop after the `if'. */
10137 {
10138 /* If we have an operand of (clobber (const_int 0)), fail. */
10142 /* Convert ROTATERT to ROTATE. */
10144 {
10149 else
10151 }
10156 /* Handle cases where the count is greater than the size of the mode
10157 minus 1. For ASHIFT, use the size minus one as the count (this can
10158 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10159 take the count modulo the size. For other shifts, the result is
10160 zero.
10162 Since these shifts are being produced by the compiler by combining
10163 multiple operations, each of which are defined, we know what the
10164 result is supposed to be. */
10167 {
10172 else
10173 {
10174 /* We can't simply return zero because there may be an
10175 outer op. */
10179 }
10180 }
10182 /* If we discovered we had to complement VAROP, leave. Making a NOT
10183 here would cause an infinite loop. */
10187 /* An arithmetic right shift of a quantity known to be -1 or 0
10188 is a no-op. */
10192 {
10195 }
10197 /* If we are doing an arithmetic right shift and discarding all but
10198 the sign bit copies, this is equivalent to doing a shift by the
10199 bitsize minus one. Convert it into that shift because it will often
10200 allow other simplifications. */
10207 /* We simplify the tests below and elsewhere by converting
10208 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10209 `make_compound_operation' will convert it to an ASHIFTRT for
10210 those machines (such as VAX) that don't have an LSHIFTRT. */
10227 {
10234 {
10237 }
10241 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10242 minus the width of a smaller mode, we can do this with a
10243 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10250 {
10259 }
10263 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10264 the same number of words as what we've seen so far. Then store
10265 the widest mode in MODE. */
10271 == mode_words
10274 {
10279 }
10283 /* Some machines use MULT instead of ASHIFT because MULT
10284 is cheaper. But it is still better on those machines to
10285 merge two shifts into one. */
10288 {
10289 varop
10295 }
10299 /* Similar, for when divides are cheaper. */
10302 {
10303 varop
10309 }
10313 /* If we are extracting just the sign bit of an arithmetic
10314 right shift, that shift is not needed. However, the sign
10315 bit of a wider mode may be different from what would be
10316 interpreted as the sign bit in a narrower mode, so, if
10317 the result is narrower, don't discard the shift. */
10322 {
10325 }
10327 /* ... fall through ... */
10332 /* Here we have two nested shifts. The result is usually the
10333 AND of a new shift with a mask. We compute the result below. */
10340 {
10344 rtx mask_rtx;
10346 /* We have one common special case. We can't do any merging if
10347 the inner code is an ASHIFTRT of a smaller mode. However, if
10348 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10349 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10350 we can convert it to
10351 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10352 This simplifies certain SIGN_EXTEND operations. */
10356 {
10357 /* C3 has the low-order C1 bits zero. */
10369 }
10371 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10372 than C1 high-order bits equal to the sign bit, we can convert
10373 this to either an ASHIFT or an ASHIFTRT depending on the
10374 two counts.
10376 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10382 {
10386 {
10389 }
10392 }
10394 /* There are some cases we can't do. If CODE is ASHIFTRT,
10395 we can only do this if FIRST_CODE is also ASHIFTRT.
10397 We can't do the case when CODE is ROTATE and FIRST_CODE is
10398 ASHIFTRT.
10400 If the mode of this shift is not the mode of the outer shift,
10401 we can't do this if either shift is a right shift or ROTATE.
10403 Finally, we can't do any of these if the mode is too wide
10404 unless the codes are the same.
10406 Handle the case where the shift codes are the same
10407 first. */
10410 {
10419 }
10430 /* To compute the mask to apply after the shift, shift the
10431 nonzero bits of the inner shift the same way the
10432 outer shift will. */
10435 result_mode);
10437 mask_rtx
10441 /* Give up if we can't compute an outer operation to use. */
10449 /* If the shifts are in the same direction, we add the
10450 counts. Otherwise, we subtract them. */
10454 else
10457 /* If COUNT is positive, the new shift is usually CODE,
10458 except for the two exceptions below, in which case it is
10459 FIRST_CODE. If the count is negative, FIRST_CODE should
10460 always be used */
10470 }
10472 /* If we have (A << B << C) for any shift, we can convert this to
10473 (A << C << B). This wins if A is a constant. Only try this if
10474 B is not a constant. */
10479 {
10486 }
10493 /* Make this fit the case below. */
10500 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10501 with C the size of VAROP - 1 and the shift is logical if
10502 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10503 we have an (le X 0) operation. If we have an arithmetic shift
10504 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10505 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10513 {
10516 const0_rtx);
10522 }
10524 /* If we have (shift (logical)), move the logical to the outside
10525 to allow it to possibly combine with another logical and the
10526 shift to combine with another shift. This also canonicalizes to
10527 what a ZERO_EXTRACT looks like. Also, some machines have
10528 (and (shift)) insns. */
10531 /* We can't do this if we have (ashiftrt (xor)) and the
10532 constant has its sign bit set in shift_mode with shift_mode
10533 wider than result_mode. */
10537 shift_mode))
10545 {
10548 }
10550 /* If we can't do that, try to simplify the shift in each arm of the
10551 logical expression, make a new logical expression, and apply
10552 the inverse distributive law. This also can't be done for
10553 (ashiftrt (xor)) where we've widened the shift and the constant
10554 changes the sign bit. */
10559 shift_mode)))
10560 {
10572 }
10576 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10577 says that the sign bit can be tested, FOO has mode MODE, C is
10578 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10579 that may be nonzero. */
10589 {
10593 }
10597 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10598 than the number of bits in the mode is equivalent to A. */
10602 {
10606 }
10608 /* NEG commutes with ASHIFT since it is multiplication. Move the
10609 NEG outside to allow shifts to combine. */
10613 {
10616 }
10620 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10621 is one less than the number of bits in the mode is
10622 equivalent to (xor A 1). */
10629 {
10633 }
10635 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10636 that might be nonzero in BAR are those being shifted out and those
10637 bits are known zero in FOO, we can replace the PLUS with FOO.
10638 Similarly in the other operand order. This code occurs when
10639 we are computing the size of a variable-size array. */
10646 {
10649 }
10657 result_mode)))
10658 {
10661 }
10663 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10673 {
10676 }
10678 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10679 signbit', and attempt to change the PLUS to an XOR and move it to
10680 the outer operation as is done above in the AND/IOR/XOR case
10681 leg for shift(logical). See details in logical handling above
10682 for reasoning in doing so. */
10693 {
10696 }
10701 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10702 with C the size of VAROP - 1 and the shift is logical if
10703 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10704 we have a (gt X 0) operation. If the shift is arithmetic with
10705 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10706 we have a (neg (gt X 0)) operation. */
10715 {
10718 const0_rtx);
10724 }
10728 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10729 if the truncate does not affect the value. */
10736 {
10739 varop_inner
10742 GEN_INT
10747 }
10752 }
10755 }
10760 /* We have now finished analyzing the shift. The result should be
10761 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10762 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10763 to the result of the shift. OUTER_CONST is the relevant constant,
10764 but we must turn off all bits turned off in the shift. */
10772 /* Make a SUBREG if necessary. If we can't make it, fail. */
10777 /* If we have an outer operation and we just made a shift, it is
10778 possible that we could have simplified the shift were it not
10779 for the outer operation. So try to do the simplification
10780 recursively. */
10784 else
10790 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10791 turn off all the bits that the shift would have turned off. */
10796 /* Do the remainder of the processing in RESULT_MODE. */
10799 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10800 operation. */
10805 {
10813 {
10814 /* This means that we have determined that the result is
10815 equivalent to a constant. This should be rare. */
10818 }
10821 else
10824 }
10827 }
10829 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10830 The result of the shift is RESULT_MODE. If we cannot simplify it,
10831 return X or, if it is NULL, synthesize the expression with
10832 simplify_gen_binary. Otherwise, return a simplified value.
10834 The shift is normally computed in the widest mode we find in VAROP, as
10835 long as it isn't a different number of words than RESULT_MODE. Exceptions
10836 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10838 static rtx
10841 {
10851 }
10853 \f
10854 /* A subroutine of recog_for_combine. See there for arguments and
10855 return value. */
10857 static int
10859 {
10861 rtx pat_without_clobbers;
10869 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10870 we use to indicate that something didn't match. If we find such a
10871 thing, force rejection. */
10885 {
10888 else
10891 }
10893 /* If it isn't, there is the possibility that we previously had an insn
10894 that clobbered some register as a side effect, but the combined
10895 insn doesn't need to do that. So try once more without the clobbers
10896 unless this represents an ASM insn. */
10900 {
10905 {
10908 pos++;
10909 }
10919 {
10922 else
10925 }
10926 }
10933 /* Recognize all noop sets, these will be killed by followup pass. */
10937 /* If we had any clobbers to add, make a new pattern than contains
10938 them. Then check to make sure that all of them are dead. */
10940 {
10950 else
10957 {
10962 {
10966 }
10967 }
10969 }
10973 {
10980 /* Allow targets to reject combined insn. */
10982 {
10985 dump_file);
10987 /* Callers expect recog_for_combine to strip
10988 clobbers from the pattern on failure. */
10993 }
10998 }
11004 }
11006 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11007 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11008 Return whether anything was so changed. */
11010 static bool
11012 {
11017 {
11026 {
11034 }
11039 {
11042 }
11043 else
11048 mask--;
11054 }
11057 }
11059 /* Like recog, but we receive the address of a pointer to a new pattern.
11060 We try to match the rtx that the pointer points to.
11061 If that fails, we may try to modify or replace the pattern,
11062 storing the replacement into the same pointer object.
11064 Modifications include deletion or addition of CLOBBERs. If the
11065 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11066 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11067 (and undo if that fails).
11069 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11070 the CLOBBERs are placed.
11072 The value is the final insn code from the pattern ultimately matched,
11073 or -1. */
11075 static int
11077 {
11089 {
11092 {
11096 }
11097 }
11100 {
11105 }
11108 }
11109 \f
11110 /* Like gen_lowpart_general but for use by combine. In combine it
11111 is not possible to create any new pseudoregs. However, it is
11112 safe to create invalid memory addresses, because combine will
11113 try to recognize them and all they will do is make the combine
11114 attempt fail.
11116 If for some reason this cannot do its job, an rtx
11117 (clobber (const_int 0)) is returned.
11118 An insn containing that will not be recognized. */
11120 static rtx
11122 {
11126 rtx result;
11131 /* We can only support MODE being wider than a word if X is a
11132 constant integer or has a mode the same size. */
11137 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11138 won't know what to do. So we will strip off the SUBREG here and
11139 process normally. */
11141 {
11144 /* For use in case we fall down into the address adjustments
11145 further below, we need to adjust the known mode and size of
11146 x; imode and isize, since we just adjusted x. */
11153 }
11161 {
11164 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11165 address. */
11170 /* If we want to refer to something bigger than the original memref,
11171 generate a paradoxical subreg instead. That will force a reload
11172 of the original memref X. */
11179 /* Adjust the address so that the address-after-the-data is
11180 unchanged. */
11185 }
11187 /* If X is a comparison operator, rewrite it in a new mode. This
11188 probably won't match, but may allow further simplifications. */
11192 /* If we couldn't simplify X any other way, just enclose it in a
11193 SUBREG. Normally, this SUBREG won't match, but some patterns may
11194 include an explicit SUBREG or we may simplify it further in combine. */
11195 else
11196 {
11197 rtx res;
11200 {
11205 }
11209 }
11211 fail:
11213 }
11214 \f
11215 /* Try to simplify a comparison between OP0 and a constant OP1,
11216 where CODE is the comparison code that will be tested, into a
11217 (CODE OP0 const0_rtx) form.
11219 The result is a possibly different comparison code to use.
11220 *POP1 may be updated. */
11222 static enum rtx_code
11225 {
11229 /* Get the constant we are comparing against and turn off all bits
11230 not on in our mode. */
11234 /* If we are comparing against a constant power of two and the value
11235 being compared can only have that single bit nonzero (e.g., it was
11236 `and'ed with that bit), we can replace this with a comparison
11237 with zero. */
11245 {
11248 }
11250 /* Similarly, if we are comparing a value known to be either -1 or
11251 0 with -1, change it to the opposite comparison against zero. */
11256 {
11259 }
11261 /* Do some canonicalizations based on the comparison code. We prefer
11262 comparisons against zero and then prefer equality comparisons.
11263 If we can reduce the size of a constant, we will do that too. */
11265 {
11267 /* < C is equivalent to <= (C - 1) */
11269 {
11272 /* ... fall through to LE case below. */
11273 }
11274 else
11278 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11280 {
11283 }
11285 /* If we are doing a <= 0 comparison on a value known to have
11286 a zero sign bit, we can replace this with == 0. */
11296 /* >= C is equivalent to > (C - 1). */
11298 {
11301 /* ... fall through to GT below. */
11302 }
11303 else
11307 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11309 {
11312 }
11314 /* If we are doing a > 0 comparison on a value known to have
11315 a zero sign bit, we can replace this with != 0. */
11325 /* < C is equivalent to <= (C - 1). */
11327 {
11330 /* ... fall through ... */
11331 }
11332 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11336 {
11340 }
11341 else
11345 /* unsigned <= 0 is equivalent to == 0 */
11348 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11352 {
11355 }
11359 /* >= C is equivalent to > (C - 1). */
11361 {
11364 /* ... fall through ... */
11365 }
11367 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11371 {
11375 }
11376 else
11380 /* unsigned > 0 is equivalent to != 0 */
11383 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11387 {
11390 }
11395 }
11399 }
11400 \f
11401 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11402 comparison code that will be tested.
11404 The result is a possibly different comparison code to use. *POP0 and
11405 *POP1 may be updated.
11407 It is possible that we might detect that a comparison is either always
11408 true or always false. However, we do not perform general constant
11409 folding in combine, so this knowledge isn't useful. Such tautologies
11410 should have been detected earlier. Hence we ignore all such cases. */
11412 static enum rtx_code
11414 {
11421 /* Try a few ways of applying the same transformation to both operands. */
11423 {
11424 #if !WORD_REGISTER_OPERATIONS
11425 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11426 so check specially. */
11441 - (GET_MODE_PRECISION
11443 {
11446 }
11447 #endif
11449 /* If both operands are the same constant shift, see if we can ignore the
11450 shift. We can if the shift is a rotate or if the bits shifted out of
11451 this shift are known to be zero for both inputs and if the type of
11452 comparison is compatible with the shift. */
11465 {
11478 else
11480 }
11482 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11483 SUBREGs are of the same mode, and, in both cases, the AND would
11484 be redundant if the comparison was done in the narrower mode,
11485 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11486 and the operand's possibly nonzero bits are 0xffffff01; in that case
11487 if we only care about QImode, we don't need the AND). This case
11488 occurs if the output mode of an scc insn is not SImode and
11489 STORE_FLAG_VALUE == 1 (e.g., the 386).
11491 Similarly, check for a case where the AND's are ZERO_EXTEND
11492 operations from some narrower mode even though a SUBREG is not
11493 present. */
11498 {
11515 {
11519 /* The resulting comparison is always unsigned since we masked
11520 off the original sign bit. */
11524 }
11531 {
11537 }
11541 }
11543 /* If both operands are NOT, we can strip off the outer operation
11544 and adjust the comparison code for swapped operands; similarly for
11545 NEG, except that this must be an equality comparison. */
11551 else
11553 }
11555 /* If the first operand is a constant, swap the operands and adjust the
11556 comparison code appropriately, but don't do this if the second operand
11557 is already a constant integer. */
11559 {
11562 }
11564 /* We now enter a loop during which we will try to simplify the comparison.
11565 For the most part, we only are concerned with comparisons with zero,
11566 but some things may really be comparisons with zero but not start
11567 out looking that way. */
11570 {
11577 HOST_WIDE_INT const_op;
11579 /* We only want to handle integral modes. This catches VOIDmode,
11580 CCmode, and the floating-point modes. An exception is that we
11581 can handle VOIDmode if OP0 is a COMPARE or a comparison
11582 operation. */
11589 /* Try to simplify the compare to constant, possibly changing the
11590 comparison op, and/or changing op1 to zero. */
11594 /* Compute some predicates to simplify code below. */
11601 /* If this is a sign bit comparison and we can do arithmetic in
11602 MODE, say that we will only be needing the sign bit of OP0. */
11609 /* Now try cases based on the opcode of OP0. If none of the cases
11610 does a "continue", we exit this loop immediately after the
11611 switch. */
11614 {
11616 /* If we are extracting a single bit from a variable position in
11617 a constant that has only a single bit set and are comparing it
11618 with zero, we can convert this into an equality comparison
11619 between the position and the location of the single bit. */
11620 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11621 have already reduced the shift count modulo the word size. */
11627 {
11635 /* Result is nonzero iff shift count is equal to I. */
11638 }
11640 /* ... fall through ... */
11645 {
11648 }
11652 /* If testing for equality, we can take the NOT of the constant. */
11655 {
11659 }
11661 /* If just looking at the sign bit, reverse the sense of the
11662 comparison. */
11664 {
11668 }
11672 /* If testing for equality, we can take the NEG of the constant. */
11675 {
11679 }
11681 /* The remaining cases only apply to comparisons with zero. */
11685 /* When X is ABS or is known positive,
11686 (neg X) is < 0 if and only if X != 0. */
11694 {
11698 }
11700 /* If we have NEG of something whose two high-order bits are the
11701 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11703 {
11707 }
11711 /* If we are testing equality and our count is a constant, we
11712 can perform the inverse operation on our RHS. */
11716 {
11720 }
11722 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11723 a particular bit. Convert it to an AND of a constant of that
11724 bit. This will be converted into a ZERO_EXTRACT. */
11728 {
11735 }
11737 /* Fall through. */
11740 /* ABS is ignorable inside an equality comparison with zero. */
11742 {
11745 }
11749 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11750 (compare FOO CONST) if CONST fits in FOO's mode and we
11751 are either testing inequality or have an unsigned
11752 comparison with ZERO_EXTEND or a signed comparison with
11753 SIGN_EXTEND. But don't do it if we don't have a compare
11754 insn of the given mode, since we'd have to revert it
11755 later on, and then we wouldn't know whether to sign- or
11756 zero-extend. */
11759 && ! unsigned_comparison_p
11763 {
11766 }
11770 /* Check for the case where we are comparing A - C1 with C2, that is
11772 (subreg:MODE (plus (A) (-C1))) op (C2)
11774 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11775 comparison in the wider mode. One of the following two conditions
11776 must be true in order for this to be valid:
11778 1. The mode extension results in the same bit pattern being added
11779 on both sides and the comparison is equality or unsigned. As
11780 C2 has been truncated to fit in MODE, the pattern can only be
11781 all 0s or all 1s.
11783 2. The mode extension results in the sign bit being copied on
11784 each side.
11786 The difficulty here is that we have predicates for A but not for
11787 (A - C1) so we need to check that C1 is within proper bounds so
11788 as to perturbate A as little as possible. */
11795 {
11804 /* (A - C1) zero-extends if it is positive and sign-extends
11805 if it is negative, C2 both zero- and sign-extends. */
11809 /* (A - C1) sign-extends if it is positive and 1-extends
11810 if it is negative, C2 both sign- and 1-extends. */
11817 /* (A - C1) always sign-extends, like C2. */
11821 {
11824 }
11825 }
11827 /* If the inner mode is narrower and we are extracting the low part,
11828 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11832 else
11835 /* ... fall through ... */
11845 {
11848 }
11852 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11853 this for equality comparisons due to pathological cases involving
11854 overflows. */
11858 {
11862 }
11864 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11867 {
11871 }
11875 /* We used to optimize signed comparisons against zero, but that
11876 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11877 arrive here as equality comparisons, or (GEU, LTU) are
11878 optimized away. No need to special-case them. */
11880 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11881 (eq B (minus A C)), whichever simplifies. We can only do
11882 this for equality comparisons due to pathological cases involving
11883 overflows. */
11887 {
11891 }
11896 {
11900 }
11902 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11903 of bits in X minus 1, is one iff X > 0. */
11908 {
11912 }
11916 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11917 if C is zero or B is a constant. */
11921 {
11925 }
11933 /* We can't do anything if OP0 is a condition code value, rather
11934 than an actual data value. */
11940 /* Get the two operands being compared. */
11943 else
11946 /* Check for the cases where we simply want the result of the
11947 earlier test or the opposite of that result. */
11951 {
11955 else
11959 {
11964 }
11965 }
11969 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11970 iff X <= 0. */
11974 {
11978 }
11982 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11983 will be converted to a ZERO_EXTRACT later. */
11987 {
11992 }
11994 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11995 zero and X is a comparison and C1 and C2 describe only bits set
11996 in STORE_FLAG_VALUE, we can compare with X. */
12004 {
12011 {
12014 }
12015 }
12017 /* If we are doing an equality comparison of an AND of a bit equal
12018 to the sign bit, replace this with a LT or GE comparison of
12019 the underlying value. */
12026 {
12030 }
12032 /* If this AND operation is really a ZERO_EXTEND from a narrower
12033 mode, the constant fits within that mode, and this is either an
12034 equality or unsigned comparison, try to do this comparison in
12035 the narrower mode.
12037 Note that in:
12039 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12040 -> (ne:DI (reg:SI 4) (const_int 0))
12042 unless TRULY_NOOP_TRUNCATION allows it or the register is
12043 known to hold a value of the required mode the
12044 transformation is invalid. */
12055 {
12058 }
12060 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
12061 fits in both M1 and M2 and the SUBREG is either paradoxical
12062 or represents the low part, permute the SUBREG and the AND
12063 and try again. */
12065 {
12068 /* Require an integral mode, to avoid creating something like
12069 (AND:SF ...). */
12071 /* It is unsafe to commute the AND into the SUBREG if the
12072 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12073 not defined. As originally written the upper bits
12074 have a defined value due to the AND operation.
12075 However, if we commute the AND inside the SUBREG then
12076 they no longer have defined values and the meaning of
12077 the code has been changed. */
12078 && ((WORD_REGISTER_OPERATIONS
12090 {
12096 }
12097 }
12099 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12103 {
12108 }
12110 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12111 (eq (and (lshiftrt X) 1) 0).
12112 Also handle the case where (not X) is expressed using xor. */
12116 {
12128 {
12129 op0
12134 }
12135 }
12139 /* If we have (compare (ashift FOO N) (const_int C)) and
12140 the high order N bits of FOO (N+1 if an inequality comparison)
12141 are known to be zero, we can do this by comparing FOO with C
12142 shifted right N bits so long as the low-order N bits of C are
12143 zero. */
12155 {
12156 /* We must perform a logical shift, not an arithmetic one,
12157 as we want the top N bits of C to be zero. */
12164 }
12166 /* If we are doing a sign bit comparison, it means we are testing
12167 a particular bit. Convert it to the appropriate AND. */
12170 {
12177 }
12179 /* If this an equality comparison with zero and we are shifting
12180 the low bit to the sign bit, we can convert this to an AND of the
12181 low-order bit. */
12185 {
12188 }
12192 /* If this is an equality comparison with zero, we can do this
12193 as a logical shift, which might be much simpler. */
12196 {
12201 }
12203 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12204 do the comparison in a narrower mode. */
12214 {
12217 }
12219 /* Likewise if OP0 is a PLUS of a sign extension with a
12220 constant, which is usually represented with the PLUS
12221 between the shifts. */
12233 {
12241 new_const);
12243 }
12245 /* ... fall through ... */
12247 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12248 the low order N bits of FOO are known to be zero, we can do this
12249 by comparing FOO with C shifted left N bits so long as no
12250 overflow occurs. Even if the low order N bits of FOO aren't known
12251 to be zero, if the comparison is >= or < we can use the same
12252 optimization and for > or <= by setting all the low
12253 order N bits in the comparison constant. */
12264 {
12265 unsigned HOST_WIDE_INT low_bits
12270 {
12271 /* If the shift was logical, then we must make the condition
12272 unsigned. */
12280 const_op
12285 }
12286 }
12288 /* If we are using this shift to extract just the sign bit, we
12289 can replace this with an LT or GE comparison. */
12294 {
12298 }
12303 }
12306 }
12308 /* Now make any compound operations involved in this comparison. Then,
12309 check for an outmost SUBREG on OP0 that is not doing anything or is
12310 paradoxical. The latter transformation must only be performed when
12311 it is known that the "extra" bits will be the same in op0 and op1 or
12312 that they don't matter. There are three cases to consider:
12314 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12315 care bits and we can assume they have any convenient value. So
12316 making the transformation is safe.
12318 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12319 In this case the upper bits of op0 are undefined. We should not make
12320 the simplification in that case as we do not know the contents of
12321 those bits.
12323 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12324 UNKNOWN. In that case we know those bits are zeros or ones. We must
12325 also be sure that they are the same as the upper bits of op1.
12327 We can never remove a SUBREG for a non-equality comparison because
12328 the sign bit is in a different place in the underlying object. */
12337 {
12339 {
12340 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12341 implemented. */
12343 {
12346 }
12347 }
12353 {
12359 }
12360 }
12362 /* We now do the opposite procedure: Some machines don't have compare
12363 insns in all modes. If OP0's mode is an integer mode smaller than a
12364 word and we can't do a compare in that mode, see if there is a larger
12365 mode for which we can do the compare. There are a number of cases in
12366 which we can use the wider mode. */
12376 {
12379 /* If this is a test for negative, we can make an explicit
12380 test of the sign bit. Test this first so we can use
12381 a paradoxical subreg to extend OP0. */
12385 {
12386 unsigned HOST_WIDE_INT sign
12393 }
12395 /* If the only nonzero bits in OP0 and OP1 are those in the
12396 narrower mode and this is an equality or unsigned comparison,
12397 we can use the wider mode. Similarly for sign-extended
12398 values, in which case it is true for all comparisons. */
12415 {
12416 /* If OP0 is an AND and we don't have an AND in MODE either,
12417 make a new AND in the proper mode. */
12425 else
12426 {
12428 {
12431 }
12432 else
12433 {
12436 }
12438 }
12439 }
12440 }
12442 /* We may have changed the comparison operands. Re-canonicalize. */
12444 {
12447 }
12449 /* If this machine only supports a subset of valid comparisons, see if we
12450 can convert an unsupported one into a supported one. */
12457 }
12458 \f
12459 /* Utility function for record_value_for_reg. Count number of
12460 rtxs in X. */
12461 static int
12463 {
12470 {
12490 }
12501 }
12502 \f
12503 /* Utility function for following routine. Called when X is part of a value
12504 being stored into last_set_value. Sets last_set_table_tick
12505 for each register mentioned. Similar to mention_regs in cse.c */
12507 static void
12509 {
12515 {
12521 {
12524 }
12527 }
12531 {
12532 /* Check for identical subexpressions. If x contains
12533 identical subexpression we only have to traverse one of
12534 them. */
12536 {
12537 /* Note that at this point x1 has already been
12538 processed. */
12542 /* If x0 and x1 are identical then there is no need to
12543 process x0. */
12547 /* If x0 is identical to a subexpression of x1 then while
12548 processing x1, x0 has already been processed. Thus we
12549 are done with x. */
12554 /* If x1 is identical to a subexpression of x0 then we
12555 still have to process the rest of x0. */
12558 {
12561 }
12562 }
12565 }
12569 }
12571 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12572 are saying that the register is clobbered and we no longer know its
12573 value. If INSN is zero, don't update reg_stat[].last_set; this is
12574 only permitted with VALUE also zero and is used to invalidate the
12575 register. */
12577 static void
12579 {
12585 /* If VALUE contains REG and we have a previous value for REG, substitute
12586 the previous value. */
12588 {
12589 rtx tem;
12591 /* Set things up so get_last_value is allowed to see anything set up to
12592 our insn. */
12596 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12597 it isn't going to be useful and will take a lot of time to process,
12598 so just use the CLOBBER. */
12601 {
12607 {
12608 /* If there are two or more occurrences of REG in VALUE,
12609 prevent the value from growing too much. */
12612 }
12615 }
12616 }
12618 /* For each register modified, show we don't know its value, that
12619 we don't know about its bitwise content, that its value has been
12620 updated, and that we don't know the location of the death of the
12621 register. */
12623 {
12635 }
12637 /* Mark registers that are being referenced in this value. */
12641 /* Now update the status of each register being set.
12642 If someone is using this register in this block, set this register
12643 to invalid since we will get confused between the two lives in this
12644 basic block. This makes using this register always invalid. In cse, we
12645 scan the table to invalidate all entries using this register, but this
12646 is too much work for us. */
12649 {
12655 else
12657 }
12659 /* The value being assigned might refer to X (like in "x++;"). In that
12660 case, we must replace it with (clobber (const_int 0)) to prevent
12661 infinite loops. */
12664 {
12668 }
12670 /* For the main register being modified, update the value, the mode, the
12671 nonzero bits, and the number of sign bit copies. */
12676 {
12684 rsp->last_set_sign_bit_copies
12686 }
12687 }
12689 /* Called via note_stores from record_dead_and_set_regs to handle one
12690 SET or CLOBBER in an insn. DATA is the instruction in which the
12691 set is occurring. */
12693 static void
12695 {
12702 {
12706 }
12709 {
12710 /* If we are setting the whole register, we know its value. Otherwise
12711 show that we don't know the value. We can handle SUBREG in
12712 some cases. */
12723 else
12725 }
12727 /* Ignore pushes, they clobber nothing. */
12730 }
12732 /* Update the records of when each REG was most recently set or killed
12733 for the things done by INSN. This is the last thing done in processing
12734 INSN in the combiner loop.
12736 We update reg_stat[], in particular fields last_set, last_set_value,
12737 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12738 last_death, and also the similar information mem_last_set (which insn
12739 most recently modified memory) and last_call_luid (which insn was the
12740 most recent subroutine call). */
12742 static void
12744 {
12745 rtx link;
12749 {
12752 {
12757 {
12762 }
12763 }
12766 }
12769 {
12770 hard_reg_set_iterator hrsi;
12772 {
12784 }
12788 /* We can't combine into a call pattern. Remember, though, that
12789 the return value register is set at this LUID. We could
12790 still replace a register with the return value from the
12791 wrong subroutine call! */
12793 }
12794 else
12796 }
12798 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12799 register present in the SUBREG, so for each such SUBREG go back and
12800 adjust nonzero and sign bit information of the registers that are
12801 known to have some zero/sign bits set.
12803 This is needed because when combine blows the SUBREGs away, the
12804 information on zero/sign bits is lost and further combines can be
12805 missed because of that. */
12807 static void
12809 {
12811 rtx set;
12819 {
12828 {
12831 }
12835 {
12838 }
12841 {
12844 }
12845 else
12847 }
12848 }
12850 /* Check if X, a register, is known to contain a value already
12851 truncated to MODE. In this case we can use a subreg to refer to
12852 the truncated value even though in the generic case we would need
12853 an explicit truncation. */
12855 static bool
12857 {
12869 }
12871 /* If X is a hard reg or a subreg record the mode that the register is
12872 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12873 to turn a truncate into a subreg using this information. Return true
12874 if traversing X is complete. */
12876 static bool
12878 {
12879 machine_mode truncated_mode;
12883 {
12894 }
12895 /* ??? For hard-regs we now record everything. We might be able to
12896 optimize this using last_set_mode. */
12899 else
12907 {
12910 }
12913 }
12915 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12916 the modes they are used in. This can help truning TRUNCATEs into
12917 SUBREGs. */
12919 static void
12921 {
12926 }
12928 /* Scan X for promoted SUBREGs. For each one found,
12929 note what it implies to the registers used in it. */
12931 static void
12933 {
12938 else
12939 {
12945 {
12955 }
12956 }
12957 }
12958 \f
12959 /* Verify that all the registers and memory references mentioned in *LOC are
12960 still valid. *LOC was part of a value set in INSN when label_tick was
12961 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12962 the invalid references with (clobber (const_int 0)) and return 1. This
12963 replacement is useful because we often can get useful information about
12964 the form of a value (e.g., if it was produced by a shift that always
12965 produces -1 or 0) even though we don't know exactly what registers it
12966 was produced from. */
12968 static int
12970 {
12977 {
12983 {
12986 /* If this is a pseudo-register that was only set once and not
12987 live at the beginning of the function, it is always valid. */
12991 && (!REGNO_REG_SET_P
12993 regno)))
12995 {
12999 }
13000 }
13003 }
13004 /* If this is a memory reference, make sure that there were no stores after
13005 it that might have clobbered the value. We don't have alias info, so we
13006 assume any store invalidates it. Moreover, we only have local UIDs, so
13007 we also assume that there were stores in the intervening basic blocks. */
13010 {
13014 }
13017 {
13019 {
13020 /* Check for identical subexpressions. If x contains
13021 identical subexpression we only have to traverse one of
13022 them. */
13024 {
13025 /* Note that at this point x0 has already been checked
13026 and found valid. */
13030 /* If x0 and x1 are identical then x is also valid. */
13034 /* If x1 is identical to a subexpression of x0 then
13035 while checking x0, x1 has already been checked. Thus
13036 it is valid and so as x. */
13041 /* If x0 is identical to a subexpression of x1 then x is
13042 valid iff the rest of x1 is valid. */
13045 return
13049 }
13054 }
13060 }
13062 /* If we haven't found a reason for it to be invalid, it is valid. */
13064 }
13066 /* Get the last value assigned to X, if known. Some registers
13067 in the value may be replaced with (clobber (const_int 0)) if their value
13068 is known longer known reliably. */
13070 static rtx
13072 {
13074 rtx value;
13077 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13078 then convert it to the desired mode. If this is a paradoxical SUBREG,
13079 we cannot predict what values the "extra" bits might have. */
13093 /* If we don't have a value, or if it isn't for this basic block and
13094 it's either a hard register, set more than once, or it's a live
13095 at the beginning of the function, return 0.
13097 Because if it's not live at the beginning of the function then the reg
13098 is always set before being used (is never used without being set).
13099 And, if it's set only once, and it's always set before use, then all
13100 uses must have the same last value, even if it's not from this basic
13101 block. */
13108 || REGNO_REG_SET_P
13112 /* If the value was set in a later insn than the ones we are processing,
13113 we can't use it even if the register was only set once. */
13118 /* If the value has all its registers valid, return it. */
13122 /* Otherwise, make a copy and replace any invalid register with
13123 (clobber (const_int 0)). If that fails for some reason, return 0. */
13130 }
13131 \f
13132 /* Return nonzero if expression X refers to a REG or to memory
13133 that is set in an instruction more recent than FROM_LUID. */
13135 static int
13137 {
13143 {
13147 #ifdef PUSH_ROUNDING
13148 /* Don't allow uses of the stack pointer to be moved,
13149 because we don't know whether the move crosses a push insn. */
13152 #endif
13154 {
13160 }
13162 }
13170 {
13172 {
13177 }
13181 }
13183 }
13184 \f
13185 /* Define three variables used for communication between the following
13186 routines. */
13191 /* Function called via note_stores from reg_dead_at_p.
13193 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13194 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13196 static void
13198 {
13208 }
13210 /* Return nonzero if REG is known to be dead at INSN.
13212 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13213 referencing REG, it is dead. If we hit a SET referencing REG, it is
13214 live. Otherwise, see if it is live or dead at the start of the basic
13215 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13216 must be assumed to be always live. */
13218 static int
13220 {
13221 basic_block block;
13224 /* Set variables for reg_dead_at_p_1. */
13230 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13231 we allow the machine description to decide whether use-and-clobber
13232 patterns are OK. */
13234 {
13238 }
13240 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13241 beginning of basic block. */
13244 {
13246 {
13256 }
13262 }
13264 /* Look at live-in sets for the basic block that we were in. */
13270 }
13271 \f
13272 /* Note hard registers in X that are used. */
13274 static void
13276 {
13282 {
13286 CASE_CONST_ANY:
13291 /* CC0 must die in the insn after it is set, so we don't need to take
13292 special note of it here. */
13297 /* If we are clobbering a MEM, mark any hard registers inside the
13298 address as used. */
13305 /* A hard reg in a wide mode may really be multiple registers.
13306 If so, mark all of them just like the first. */
13308 {
13309 /* None of this applies to the stack, frame or arg pointers. */
13311 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13319 }
13323 {
13324 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13325 the address. */
13337 }
13342 }
13344 /* Recursively scan the operands of this expression. */
13346 {
13350 {
13354 {
13359 }
13360 }
13361 }
13362 }
13363 \f
13364 /* Remove register number REGNO from the dead registers list of INSN.
13366 Return the note used to record the death, if there was one. */
13368 rtx
13370 {
13377 }
13379 /* For each register (hardware or pseudo) used within expression X, if its
13380 death is in an instruction with luid between FROM_LUID (inclusive) and
13381 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13382 list headed by PNOTES.
13384 That said, don't move registers killed by maybe_kill_insn.
13386 This is done when X is being merged by combination into TO_INSN. These
13387 notes will then be distributed as needed. */
13389 static void
13392 {
13398 {
13402 /* Don't move the register if it gets killed in between from and to. */
13411 {
13414 /* It is possible for the call above to return 0. This can occur
13415 when last_death points to I2 or I1 that we combined with.
13416 In that case make a new note.
13418 We must also check for the case where X is a hard register
13419 and NOTE is a death note for a range of hard registers
13420 including X. In that case, we must put REG_DEAD notes for
13421 the remaining registers in place of NOTE. */
13426 {
13435 }
13437 /* If we didn't find any note, or if we found a REG_DEAD note that
13438 covers only part of the given reg, and we have a multi-reg hard
13439 register, then to be safe we must check for REG_DEAD notes
13440 for each register other than the first. They could have
13441 their own REG_DEAD notes lying around. */
13448 {
13455 else
13461 }
13464 {
13467 }
13468 else
13470 }
13473 }
13476 {
13481 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13482 that accesses one word of a multi-word item, some
13483 piece of everything register in the expression is used by
13484 this insn, so remove any old death. */
13485 /* ??? So why do we test for equality of the sizes? */
13494 {
13497 }
13499 /* If this is some other SUBREG, we know it replaces the entire
13500 value, so use that as the destination. */
13504 /* If this is a MEM, adjust deaths of anything used in the address.
13505 For a REG (the only other possibility), the entire value is
13506 being replaced so the old value is not used in this insn. */
13512 }
13521 {
13523 {
13528 }
13531 }
13532 }
13533 \f
13534 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13535 pattern of an insn. X must be a REG. */
13537 static int
13539 {
13543 {
13545 rtx target;
13552 else
13569 }
13577 }
13578 \f
13579 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13580 as appropriate. I3 and I2 are the insns resulting from the combination
13581 insns including FROM (I2 may be zero).
13583 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13584 not need REG_DEAD notes because they are being substituted for. This
13585 saves searching in the most common cases.
13587 Each note in the list is either ignored or placed on some insns, depending
13588 on the type of note. */
13590 static void
13593 {
13595 rtx tem_note;
13599 {
13604 {
13607 /* Doesn't matter much where we put this, as long as it's somewhere.
13608 It is preferable to keep these notes on branches, which is most
13609 likely to be i3. */
13616 else
13617 {
13620 }
13624 /* These notes must remain with the call or trapping instruction. */
13629 else
13630 {
13636 /* ??? Otherwise assume we've combined things such that we
13637 can now prove that the instructions can't trap. Drop the
13638 note in this case. */
13639 }
13643 /* ??? How to distribute between i3-i1. Assume i3 contains the
13644 entire adjustment. Assert i3 contains at least some adjust. */
13646 {
13648 /* fixup_args_size_notes looks at REG_NORETURN note,
13649 so ensure the note is placed there first. */
13651 {
13655 {
13661 }
13662 }
13664 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13665 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13668 && !ACCUMULATE_OUTGOING_ARGS
13670 }
13677 /* These notes must remain with the call. It should not be
13678 possible for both I2 and I3 to be a call. */
13681 else
13682 {
13685 }
13689 /* Any clobbers for i3 may still exist, and so we must process
13690 REG_UNUSED notes from that insn.
13692 Any clobbers from i2 or i1 can only exist if they were added by
13693 recog_for_combine. In that case, recog_for_combine created the
13694 necessary REG_UNUSED notes. Trying to keep any original
13695 REG_UNUSED notes from these insns can cause incorrect output
13696 if it is for the same register as the original i3 dest.
13697 In that case, we will notice that the register is set in i3,
13698 and then add a REG_UNUSED note for the destination of i3, which
13699 is wrong. However, it is possible to have REG_UNUSED notes from
13700 i2 or i1 for register which were both used and clobbered, so
13701 we keep notes from i2 or i1 if they will turn into REG_DEAD
13702 notes. */
13704 /* If this register is set or clobbered in I3, put the note there
13705 unless there is one already. */
13707 {
13715 }
13716 /* Otherwise, if this register is used by I3, then this register
13717 now dies here, so we must put a REG_DEAD note here unless there
13718 is one already. */
13724 {
13727 }
13733 /* These notes say something about results of an insn. We can
13734 only support them if they used to be on I3 in which case they
13735 remain on I3. Otherwise they are ignored.
13737 If the note refers to an expression that is not a constant, we
13738 must also ignore the note since we cannot tell whether the
13739 equivalence is still true. It might be possible to do
13740 slightly better than this (we only have a problem if I2DEST
13741 or I1DEST is present in the expression), but it doesn't
13742 seem worth the trouble. */
13750 /* These notes say something about how a register is used. They must
13751 be present on any use of the register in I2 or I3. */
13756 {
13759 else
13761 }
13766 /* This can show up in several ways -- either directly in the
13767 pattern, or hidden off in the constant pool with (or without?)
13768 a REG_EQUAL note. */
13769 /* ??? Ignore the without-reg_equal-note problem for now. */
13781 {
13784 else
13786 }
13788 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13789 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13790 there. */
13795 {
13802 }
13808 {
13816 }
13820 /* This note says something about the value of a register prior
13821 to the execution of an insn. It is too much trouble to see
13822 if the note is still correct in all situations. It is better
13823 to simply delete it. */
13827 /* If we replaced the right hand side of FROM_INSN with a
13828 REG_EQUAL note, the original use of the dying register
13829 will not have been combined into I3 and I2. In such cases,
13830 FROM_INSN is guaranteed to be the first of the combined
13831 instructions, so we simply need to search back before
13832 FROM_INSN for the previous use or set of this register,
13833 then alter the notes there appropriately.
13835 If the register is used as an input in I3, it dies there.
13836 Similarly for I2, if it is nonzero and adjacent to I3.
13838 If the register is not used as an input in either I3 or I2
13839 and it is not one of the registers we were supposed to eliminate,
13840 there are two possibilities. We might have a non-adjacent I2
13841 or we might have somehow eliminated an additional register
13842 from a computation. For example, we might have had A & B where
13843 we discover that B will always be zero. In this case we will
13844 eliminate the reference to A.
13846 In both cases, we must search to see if we can find a previous
13847 use of A and put the death note there. */
13853 else
13854 {
13865 && !(i2mod
13867 i2mod_old_rhs)))
13872 /* If the new I2 sets the same register that is marked dead
13873 in the note, the note now should not be put on I2, as the
13874 note refers to a previous incarnation of the reg. */
13877 }
13880 {
13884 {
13886 {
13890 }
13892 /* If the register is being set at TEM_INSN, see if that is all
13893 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13894 into a REG_UNUSED note instead. Don't delete sets to
13895 global register vars. */
13899 {
13910 ;
13912 /* Verify that it was the set, and not a clobber that
13913 modified the register.
13915 CC0 targets must be careful to maintain setter/user
13916 pairs. If we cannot delete the setter due to side
13917 effects, mark the user with an UNUSED note instead
13918 of deleting it. */
13922 && (!HAVE_cc0
13926 {
13927 /* Move the notes and links of TEM_INSN elsewhere.
13928 This might delete other dead insns recursively.
13929 First set the pattern to something that won't use
13930 any register. */
13944 /* Delete the setter too. */
13946 {
13959 }
13960 }
13961 else
13962 {
13965 /* If there isn't already a REG_UNUSED note, put one
13966 here. Do not place a REG_DEAD note, even if
13967 the register is also used here; that would not
13968 match the algorithm used in lifetime analysis
13969 and can cause the consistency check in the
13970 scheduler to fail. */
13975 }
13976 }
13980 {
13983 /* If we are doing a 3->2 combination, and we have a
13984 register which formerly died in i3 and was not used
13985 by i2, which now no longer dies in i3 and is used in
13986 i2 but does not die in i2, and place is between i2
13987 and i3, then we may need to move a link from place to
13988 i2. */
13990 && from_insn
13993 {
13997 }
13999 }
14003 }
14005 }
14007 /* If the register is set or already dead at PLACE, we needn't do
14008 anything with this note if it is still a REG_DEAD note.
14009 We check here if it is set at all, not if is it totally replaced,
14010 which is what `dead_or_set_p' checks, so also check for it being
14011 set partially. */
14014 {
14020 {
14021 /* Unless the register previously died in PLACE, clear
14022 last_death. [I no longer understand why this is
14023 being done.] */
14027 }
14028 else
14031 /* If this is a death note for a hard reg that is occupying
14032 multiple registers, ensure that we are still using all
14033 parts of the object. If we find a piece of the object
14034 that is unused, we must arrange for an appropriate REG_DEAD
14035 note to be added for it. However, we can't just emit a USE
14036 and tag the note to it, since the register might actually
14037 be dead; so we recourse, and the recursive call then finds
14038 the previous insn that used this register. */
14041 {
14050 {
14053 }
14056 {
14057 /* Put only REG_DEAD notes for pieces that are
14058 not already dead or set. */
14062 {
14069 {
14071 NULL_RTX);
14075 NULL_RTX);
14076 }
14081 {
14083 {
14087 }
14091 {
14094 }
14095 }
14096 }
14099 }
14100 }
14101 }
14105 /* Any other notes should not be present at this point in the
14106 compilation. */
14108 }
14111 {
14114 }
14118 }
14119 }
14120 \f
14121 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14122 I3, I2, and I1 to new locations. This is also called to add a link
14123 pointing at I3 when I3's destination is changed. */
14125 static void
14127 {
14131 {
14138 /* If the insn that this link points to is a NOTE, ignore it. */
14147 {
14150 {
14166 }
14169 }
14170 else
14180 /* A LOG_LINK is defined as being placed on the first insn that uses
14181 a register and points to the insn that sets the register. Start
14182 searching at the next insn after the target of the link and stop
14183 when we reach a set of the register or the end of the basic block.
14185 Note that this correctly handles the link that used to point from
14186 I3 to I2. Also note that not much searching is typically done here
14187 since most links don't point very far away. */
14196 {
14200 }
14203 {
14206 }
14210 /* If we found a place to put the link, place it there unless there
14211 is already a link to the same insn as LINK at that point. */
14214 {
14222 {
14226 /* Set added_links_insn to the earliest insn we added a
14227 link to. */
14231 }
14232 }
14233 }
14234 }
14235 \f
14236 /* Check for any register or memory mentioned in EQUIV that is not
14237 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14238 of EXPR where some registers may have been replaced by constants. */
14240 static bool
14242 {
14245 {
14250 }
14252 }
14253 \f
14254 DEBUG_FUNCTION void
14256 {
14257 fprintf
14259 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14261 }
14263 void
14265 {
14266 fprintf
14268 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14270 }
14271 \f
14272 /* Try combining insns through substitution. */
14273 static unsigned int
14275 {
14285 rebuild_jump_labels_after_combine
14288 /* Combining insns may have turned an indirect jump into a
14289 direct jump. Rebuild the JUMP_LABEL fields of jumping
14290 instructions. */
14292 {
14297 }
14301 }
14306 {
14316 };
14319 {
14323 {}
14325 /* opt_pass methods: */
14328 {
14330 }
14336 rtl_opt_pass *
14338 {
14340 }