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* config/sh/divtab.c, config/sh/sh.c, config/sh/sh.h,
[official-gcc.git] / gcc / config / sh / sh.h
blobd76f97b764bb8772f2aa26b6a0da023c35047367
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
29
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
34
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
43 builtin_define ("__sh1__"); \
44 break; \
45 case PROCESSOR_SH2: \
46 builtin_define ("__sh2__"); \
47 break; \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
50 break; \
51 case PROCESSOR_SH2A: \
52 builtin_define ("__SH2A__"); \
53 builtin_define (TARGET_SH2A_DOUBLE \
54 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
55 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
56 : "__SH2A_NOFPU__"); \
57 break; \
58 case PROCESSOR_SH3: \
59 builtin_define ("__sh3__"); \
60 builtin_define ("__SH3__"); \
61 if (TARGET_HARD_SH4) \
62 builtin_define ("__SH4_NOFPU__"); \
63 break; \
64 case PROCESSOR_SH3E: \
65 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
66 break; \
67 case PROCESSOR_SH4: \
68 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
69 break; \
70 case PROCESSOR_SH4A: \
71 builtin_define ("__SH4A__"); \
72 builtin_define (TARGET_SH4 \
73 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
74 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
75 : "__SH4_NOFPU__"); \
76 break; \
77 case PROCESSOR_SH5: \
78 { \
79 builtin_define_with_value ("__SH5__", \
80 TARGET_SHMEDIA64 ? "64" : "32", 0); \
81 builtin_define_with_value ("__SHMEDIA__", \
82 TARGET_SHMEDIA ? "1" : "0", 0); \
83 if (! TARGET_FPU_DOUBLE) \
84 builtin_define ("__SH4_NOFPU__"); \
85 } \
86 } \
87 if (TARGET_FPU_ANY) \
88 builtin_define ("__SH_FPU_ANY__"); \
89 if (TARGET_FPU_DOUBLE) \
90 builtin_define ("__SH_FPU_DOUBLE__"); \
91 if (TARGET_HITACHI) \
92 builtin_define ("__HITACHI__"); \
93 builtin_define (TARGET_LITTLE_ENDIAN \
94 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
95 } while (0)
96
97 /* We can not debug without a frame pointer. */
98 /* #define CAN_DEBUG_WITHOUT_FP */
99
100 #define CONDITIONAL_REGISTER_USAGE do \
101 { \
102 int regno; \
103 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
104 if (! VALID_REGISTER_P (regno)) \
105 fixed_regs[regno] = call_used_regs[regno] = 1; \
106 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
107 if (TARGET_SH5) \
108 { \
109 call_used_regs[FIRST_GENERAL_REG + 8] \
110 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
111 call_really_used_regs[FIRST_GENERAL_REG + 8] \
112 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
113 } \
114 if (TARGET_SHMEDIA) \
115 { \
116 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
117 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
118 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
119 } \
120 if (flag_pic) \
121 { \
122 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
123 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 } \
125 /* Renesas saves and restores mac registers on call. */ \
126 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
127 { \
128 call_really_used_regs[MACH_REG] = 0; \
129 call_really_used_regs[MACL_REG] = 0; \
130 } \
131 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
132 regno <= LAST_FP_REG; regno += 2) \
133 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
134 if (TARGET_SHMEDIA) \
135 { \
136 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
137 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
138 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
139 } \
140 else \
141 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
142 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
143 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
144 } while (0)
145 \f
146 /* Nonzero if this is an ELF target - compile time only */
147 #define TARGET_ELF 0
148
149 /* Nonzero if we should generate code using type 2E insns. */
150 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
151
152 /* Nonzero if we should generate code using type 2A insns. */
153 #define TARGET_SH2A TARGET_HARD_SH2A
154 /* Nonzero if we should generate code using type 2A SF insns. */
155 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
156 /* Nonzero if we should generate code using type 2A DF insns. */
157 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
158
159 /* Nonzero if we should generate code using type 3E insns. */
160 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
161
162 /* Nonzero if the cache line size is 32. */
163 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
164
165 /* Nonzero if we schedule for a superscalar implementation. */
166 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
167
168 /* Nonzero if the target has separate instruction and data caches. */
169 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
170
171 /* Nonzero if a double-precision FPU is available. */
172 #define TARGET_FPU_DOUBLE \
173 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
174
175 /* Nonzero if an FPU is available. */
176 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
177
178 /* Nonzero if we should generate code using type 4 insns. */
179 #undef TARGET_SH4
180 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
181
182 /* Nonzero if we're generating code for the common subset of
183 instructions present on both SH4a and SH4al-dsp. */
184 #define TARGET_SH4A_ARCH TARGET_SH4A
185
186 /* Nonzero if we're generating code for SH4a, unless the use of the
187 FPU is disabled (which makes it compatible with SH4al-dsp). */
188 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
189
190 /* Nonzero if we should generate code using the SHcompact instruction
191 set and 32-bit ABI. */
192 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
193
194 /* Nonzero if we should generate code using the SHmedia instruction
195 set and ABI. */
196 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
197
198 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
199 ABI. */
200 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
201
202 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
203 ABI. */
204 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
205
206 /* Nonzero if we should generate code using SHmedia FPU instructions. */
207 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
208
209 /* This is not used by the SH2E calling convention */
210 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
211 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
212 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
213
214 #ifndef TARGET_CPU_DEFAULT
215 #define TARGET_CPU_DEFAULT SELECT_SH1
216 #define SUPPORT_SH1 1
217 #define SUPPORT_SH2E 1
218 #define SUPPORT_SH4 1
219 #define SUPPORT_SH4_SINGLE 1
220 #define SUPPORT_SH2A 1
221 #define SUPPORT_SH2A_SINGLE 1
222 #endif
223
224 #define TARGET_DIVIDE_INV \
225 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
226 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
227 || sh_div_strategy == SH_DIV_INV_CALL \
228 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
229 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
230 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
231 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
232 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
233 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
234 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
235 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
236 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
237 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
238 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
239 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
240
241 #define SELECT_SH1 (MASK_SH1)
242 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
243 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
244 | MASK_FPU_SINGLE)
245 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
246 | MASK_HARD_SH2A_DOUBLE \
247 | MASK_SH2 | MASK_SH1)
248 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
249 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
250 | MASK_SH1 | MASK_FPU_SINGLE)
251 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
252 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
253 | MASK_SH2 | MASK_SH1)
254 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
255 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
256 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
257 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
258 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
259 | SELECT_SH3)
260 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
261 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
262 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
263 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
264 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
265 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
266 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
267 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
268 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
269 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
270 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
271
272 #if SUPPORT_SH1
273 #define SUPPORT_SH2 1
274 #endif
275 #if SUPPORT_SH2
276 #define SUPPORT_SH3 1
277 #define SUPPORT_SH2A_NOFPU 1
278 #endif
279 #if SUPPORT_SH3
280 #define SUPPORT_SH4_NOFPU 1
281 #endif
282 #if SUPPORT_SH4_NOFPU
283 #define SUPPORT_SH4A_NOFPU 1
284 #define SUPPORT_SH4AL 1
285 #endif
286
287 #if SUPPORT_SH2E
288 #define SUPPORT_SH3E 1
289 #define SUPPORT_SH2A_SINGLE_ONLY 1
290 #endif
291 #if SUPPORT_SH3E
292 #define SUPPORT_SH4_SINGLE_ONLY 1
293 #endif
294 #if SUPPORT_SH4_SINGLE_ONLY
295 #define SUPPORT_SH4A_SINGLE_ONLY 1
296 #endif
297
298 #if SUPPORT_SH4
299 #define SUPPORT_SH4A 1
300 #endif
301
302 #if SUPPORT_SH4_SINGLE
303 #define SUPPORT_SH4A_SINGLE 1
304 #endif
305
306 #if SUPPORT_SH5_COMPAT
307 #define SUPPORT_SH5_32MEDIA 1
308 #endif
309
310 #if SUPPORT_SH5_COMPACT_NOFPU
311 #define SUPPORT_SH5_32MEDIA_NOFPU 1
312 #endif
313
314 #define SUPPORT_ANY_SH5_32MEDIA \
315 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
316 #define SUPPORT_ANY_SH5_64MEDIA \
317 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
318 #define SUPPORT_ANY_SH5 \
319 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
320
321 /* Reset all target-selection flags. */
322 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
323 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
324 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
325
326 /* This defaults us to big-endian. */
327 #ifndef TARGET_ENDIAN_DEFAULT
328 #define TARGET_ENDIAN_DEFAULT 0
329 #endif
330
331 #ifndef TARGET_OPT_DEFAULT
332 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
333 #endif
334
335 #define TARGET_DEFAULT \
336 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
337
338 #ifndef SH_MULTILIB_CPU_DEFAULT
339 #define SH_MULTILIB_CPU_DEFAULT "m1"
340 #endif
341
342 #if TARGET_ENDIAN_DEFAULT
343 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
344 #else
345 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
346 #endif
347
348 #define CPP_SPEC " %(subtarget_cpp_spec) "
349
350 #ifndef SUBTARGET_CPP_SPEC
351 #define SUBTARGET_CPP_SPEC ""
352 #endif
353
354 #ifndef SUBTARGET_EXTRA_SPECS
355 #define SUBTARGET_EXTRA_SPECS
356 #endif
357
358 #define EXTRA_SPECS \
359 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
360 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
361 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
362 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
363 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
364 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
365 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
366 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
367 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
368 SUBTARGET_EXTRA_SPECS
369
370 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
371 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
372 #else
373 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
374 #endif
375
376 #define SH_ASM_SPEC \
377 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
378 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
379 %{m2a:--isa=sh2a} \
380 %{m2a-single:--isa=sh2a} \
381 %{m2a-single-only:--isa=sh2a} \
382 %{m2a-nofpu:--isa=sh2a-nofpu} \
383 %{m5-compact*:--isa=SHcompact} \
384 %{m5-32media*:--isa=SHmedia --abi=32} \
385 %{m5-64media*:--isa=SHmedia --abi=64} \
386 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
387
388 #define ASM_SPEC SH_ASM_SPEC
389
390 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
391 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
392 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
393 #else
394 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
395 #endif
396 #endif
397
398 #if STRICT_NOFPU == 1
399 /* Strict nofpu means that the compiler should tell the assembler
400 to reject FPU instructions. E.g. from ASM inserts. */
401 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
402 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
403 #else
404 /* If there were an -isa option for sh5-nofpu then it would also go here. */
405 #define SUBTARGET_ASM_ISA_SPEC \
406 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
407 #endif
408 #else /* ! STRICT_NOFPU */
409 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
410 #endif
411
412 #ifndef SUBTARGET_ASM_SPEC
413 #define SUBTARGET_ASM_SPEC ""
414 #endif
415
416 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
417 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
418 #else
419 #define LINK_EMUL_PREFIX "sh%{ml:l}"
420 #endif
421
422 #if TARGET_CPU_DEFAULT & MASK_SH5
423 #if TARGET_CPU_DEFAULT & MASK_SH_E
424 #define LINK_DEFAULT_CPU_EMUL "32"
425 #if TARGET_CPU_DEFAULT & MASK_SH1
426 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
427 #else
428 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
429 #endif /* MASK_SH1 */
430 #else /* !MASK_SH_E */
431 #define LINK_DEFAULT_CPU_EMUL "64"
432 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
433 #endif /* MASK_SH_E */
434 #define ASM_ISA_DEFAULT_SPEC \
435 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
436 #else /* !MASK_SH5 */
437 #define LINK_DEFAULT_CPU_EMUL ""
438 #define ASM_ISA_DEFAULT_SPEC ""
439 #endif /* MASK_SH5 */
440
441 #define SUBTARGET_LINK_EMUL_SUFFIX ""
442 #define SUBTARGET_LINK_SPEC ""
443
444 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
445 so that we can undo the damage without code replication. */
446 #define LINK_SPEC SH_LINK_SPEC
447
448 #define SH_LINK_SPEC "\
449 -m %(link_emul_prefix)\
450 %{m5-compact*|m5-32media*:32}\
451 %{m5-64media*:64}\
452 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
453 %(subtarget_link_emul_suffix) \
454 %{mrelax:-relax} %(subtarget_link_spec)"
455
456 #ifndef SH_DIV_STR_FOR_SIZE
457 #define SH_DIV_STR_FOR_SIZE "call"
458 #endif
459
460 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
461 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
462 do { \
463 if (LEVEL) \
464 { \
465 flag_omit_frame_pointer = -1; \
466 if (! SIZE) \
467 sh_div_str = "inv:minlat"; \
468 } \
469 if (SIZE) \
470 { \
471 target_flags |= MASK_SMALLCODE; \
472 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
473 } \
474 else \
475 { \
476 TARGET_CBRANCHDI4 = 1; \
477 TARGET_EXPAND_CBRANCHDI4 = 1; \
478 } \
479 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
480 haven't been parsed yet, hence we'd read only the default. \
481 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
482 it's OK to always set flag_branch_target_load_optimize. */ \
483 if (LEVEL > 1) \
484 { \
485 flag_branch_target_load_optimize = 1; \
486 if (! (SIZE)) \
487 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
488 } \
489 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
490 here, so leave it to OVERRIDE_OPTIONS to set \
491 flag_finite_math_only. We set it to 2 here so we know if the user \
492 explicitly requested this to be on or off. */ \
493 flag_finite_math_only = 2; \
494 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
495 the user explicitly requested this to be on or off. */ \
496 if (flag_schedule_insns > 0) \
497 flag_schedule_insns = 2; \
498 \
499 set_param_value ("simultaneous-prefetches", 2); \
500 } while (0)
501
502 #define ASSEMBLER_DIALECT assembler_dialect
503
504 extern int assembler_dialect;
505
506 enum sh_divide_strategy_e {
507 /* SH5 strategies. */
508 SH_DIV_CALL,
509 SH_DIV_CALL2,
510 SH_DIV_FP, /* We could do this also for SH4. */
511 SH_DIV_INV,
512 SH_DIV_INV_MINLAT,
513 SH_DIV_INV20U,
514 SH_DIV_INV20L,
515 SH_DIV_INV_CALL,
516 SH_DIV_INV_CALL2,
517 SH_DIV_INV_FP,
518 /* SH1 .. SH4 strategies. Because of the small number of registers
519 available, the compiler uses knowledge of the actual set of registers
520 being clobbered by the different functions called. */
521 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
522 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
523 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
524 SH_DIV_INTRINSIC
525 };
526
527 extern enum sh_divide_strategy_e sh_div_strategy;
528
529 #ifndef SH_DIV_STRATEGY_DEFAULT
530 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
531 #endif
532
533 #define OVERRIDE_OPTIONS \
534 do { \
535 int regno; \
536 \
537 if (flag_finite_math_only == 2) \
538 flag_finite_math_only \
539 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
540 if (TARGET_SH2E && !flag_finite_math_only) \
541 target_flags |= MASK_IEEE; \
542 sh_cpu = CPU_SH1; \
543 assembler_dialect = 0; \
544 if (TARGET_SH2) \
545 sh_cpu = CPU_SH2; \
546 if (TARGET_SH2E) \
547 sh_cpu = CPU_SH2E; \
548 if (TARGET_SH2A) \
549 { \
550 sh_cpu = CPU_SH2A; \
551 if (TARGET_SH2A_DOUBLE) \
552 target_flags |= MASK_FMOVD; \
553 } \
554 if (TARGET_SH3) \
555 sh_cpu = CPU_SH3; \
556 if (TARGET_SH3E) \
557 sh_cpu = CPU_SH3E; \
558 if (TARGET_SH4) \
559 { \
560 assembler_dialect = 1; \
561 sh_cpu = CPU_SH4; \
562 } \
563 if (TARGET_SH4A_ARCH) \
564 { \
565 assembler_dialect = 1; \
566 sh_cpu = CPU_SH4A; \
567 } \
568 if (TARGET_SH5) \
569 { \
570 sh_cpu = CPU_SH5; \
571 target_flags |= MASK_ALIGN_DOUBLE; \
572 if (TARGET_SHMEDIA_FPU) \
573 target_flags |= MASK_FMOVD; \
574 if (TARGET_SHMEDIA) \
575 { \
576 /* There are no delay slots on SHmedia. */ \
577 flag_delayed_branch = 0; \
578 /* Relaxation isn't yet supported for SHmedia */ \
579 target_flags &= ~MASK_RELAX; \
580 /* After reload, if conversion does little good but can cause \
581 ICEs: \
582 - find_if_block doesn't do anything for SH because we don't\
583 have conditional execution patterns. (We use conditional\
584 move patterns, which are handled differently, and only \
585 before reload). \
586 - find_cond_trap doesn't do anything for the SH because we \
587 don't have conditional traps. \
588 - find_if_case_1 uses redirect_edge_and_branch_force in \
589 the only path that does an optimization, and this causes \
590 an ICE when branch targets are in registers. \
591 - find_if_case_2 doesn't do anything for the SHmedia after \
592 reload except when it can redirect a tablejump - and \
593 that's rather rare. */ \
594 flag_if_conversion2 = 0; \
595 if (! strcmp (sh_div_str, "call")) \
596 sh_div_strategy = SH_DIV_CALL; \
597 else if (! strcmp (sh_div_str, "call2")) \
598 sh_div_strategy = SH_DIV_CALL2; \
599 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
600 sh_div_strategy = SH_DIV_FP; \
601 else if (! strcmp (sh_div_str, "inv")) \
602 sh_div_strategy = SH_DIV_INV; \
603 else if (! strcmp (sh_div_str, "inv:minlat")) \
604 sh_div_strategy = SH_DIV_INV_MINLAT; \
605 else if (! strcmp (sh_div_str, "inv20u")) \
606 sh_div_strategy = SH_DIV_INV20U; \
607 else if (! strcmp (sh_div_str, "inv20l")) \
608 sh_div_strategy = SH_DIV_INV20L; \
609 else if (! strcmp (sh_div_str, "inv:call2")) \
610 sh_div_strategy = SH_DIV_INV_CALL2; \
611 else if (! strcmp (sh_div_str, "inv:call")) \
612 sh_div_strategy = SH_DIV_INV_CALL; \
613 else if (! strcmp (sh_div_str, "inv:fp")) \
614 { \
615 if (TARGET_FPU_ANY) \
616 sh_div_strategy = SH_DIV_INV_FP; \
617 else \
618 sh_div_strategy = SH_DIV_INV; \
619 } \
620 TARGET_CBRANCHDI4 = 0; \
621 } \
622 /* -fprofile-arcs needs a working libgcov . In unified tree \
623 configurations with newlib, this requires to configure with \
624 --with-newlib --with-headers. But there is no way to check \
625 here we have a working libgcov, so just assume that we have. */\
626 if (profile_flag) \
627 warning (0, "profiling is still experimental for this target");\
628 } \
629 else \
630 { \
631 /* Only the sh64-elf assembler fully supports .quad properly. */\
632 targetm.asm_out.aligned_op.di = NULL; \
633 targetm.asm_out.unaligned_op.di = NULL; \
634 } \
635 if (TARGET_SH1) \
636 { \
637 if (! strcmp (sh_div_str, "call-div1")) \
638 sh_div_strategy = SH_DIV_CALL_DIV1; \
639 else if (! strcmp (sh_div_str, "call-fp") \
640 && (TARGET_FPU_DOUBLE \
641 || (TARGET_HARD_SH4 && TARGET_SH2E) \
642 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
643 sh_div_strategy = SH_DIV_CALL_FP; \
644 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2) \
645 sh_div_strategy = SH_DIV_CALL_TABLE; \
646 else \
647 /* Pick one that makes most sense for the target in general. \
648 It is not much good to use different functions depending \
649 on -Os, since then we'll end up with two different functions \
650 when some of the code is compiled for size, and some for \
651 speed. */ \
652 \
653 /* SH4 tends to emphasize speed. */ \
654 if (TARGET_HARD_SH4) \
655 sh_div_strategy = SH_DIV_CALL_TABLE; \
656 /* These have their own way of doing things. */ \
657 else if (TARGET_SH2A) \
658 sh_div_strategy = SH_DIV_INTRINSIC; \
659 /* ??? Should we use the integer SHmedia function instead? */ \
660 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
661 sh_div_strategy = SH_DIV_CALL_FP; \
662 /* SH1 .. SH3 cores often go into small-footprint systems, so \
663 default to the smallest implementation available. */ \
664 else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
665 sh_div_strategy = SH_DIV_CALL_TABLE; \
666 else \
667 sh_div_strategy = SH_DIV_CALL_DIV1; \
668 } \
669 if (!TARGET_SH1) \
670 TARGET_PRETEND_CMOVE = 0; \
671 if (sh_divsi3_libfunc[0]) \
672 ; /* User supplied - leave it alone. */ \
673 else if (TARGET_DIVIDE_CALL_FP) \
674 sh_divsi3_libfunc = "__sdivsi3_i4"; \
675 else if (TARGET_DIVIDE_CALL_TABLE) \
676 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
677 else if (TARGET_SH5) \
678 sh_divsi3_libfunc = "__sdivsi3_1"; \
679 else \
680 sh_divsi3_libfunc = "__sdivsi3"; \
681 if (sh_branch_cost == -1) \
682 sh_branch_cost \
683 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1; \
684 if (TARGET_FMOVD) \
685 reg_class_from_letter['e' - 'a'] = NO_REGS; \
686 \
687 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
688 if (! VALID_REGISTER_P (regno)) \
689 sh_register_names[regno][0] = '\0'; \
690 \
691 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
692 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
693 sh_additional_register_names[regno][0] = '\0'; \
694 \
695 if (flag_omit_frame_pointer < 0) \
696 { \
697 /* The debugging information is sufficient, \
698 but gdb doesn't implement this yet */ \
699 if (0) \
700 flag_omit_frame_pointer \
701 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
702 else \
703 flag_omit_frame_pointer = 0; \
704 } \
705 \
706 if ((flag_pic && ! TARGET_PREFERGOT) \
707 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
708 flag_no_function_cse = 1; \
709 \
710 if (SMALL_REGISTER_CLASSES) \
711 { \
712 /* Never run scheduling before reload, since that can \
713 break global alloc, and generates slower code anyway due \
714 to the pressure on R0. */ \
715 /* Enable sched1 for SH4; ready queue will be reordered by \
716 the target hooks when pressure is high. We can not do this for \
717 SH3 and lower as they give spill failures for R0. */ \
718 if (!TARGET_HARD_SH4) \
719 flag_schedule_insns = 0; \
720 /* ??? Current exception handling places basic block boundaries \
721 after call_insns. It causes the high pressure on R0 and gives \
722 spill failures for R0 in reload. See PR 22553 and the thread \
723 on gcc-patches \
724 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
725 else if (flag_exceptions) \
726 { \
727 if (flag_schedule_insns == 1) \
728 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
729 flag_schedule_insns = 0; \
730 } \
731 } \
732 \
733 if (align_loops == 0) \
734 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
735 if (align_jumps == 0) \
736 align_jumps = 1 << CACHE_LOG; \
737 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
738 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
739 \
740 /* Allocation boundary (in *bytes*) for the code of a function. \
741 SH1: 32 bit alignment is faster, because instructions are always \
742 fetched as a pair from a longword boundary. \
743 SH2 .. SH5 : align to cache line start. */ \
744 if (align_functions == 0) \
745 align_functions \
746 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
747 /* The linker relaxation code breaks when a function contains \
748 alignments that are larger than that at the start of a \
749 compilation unit. */ \
750 if (TARGET_RELAX) \
751 { \
752 int min_align \
753 = align_loops > align_jumps ? align_loops : align_jumps; \
754 \
755 /* Also take possible .long constants / mova tables int account. */\
756 if (min_align < 4) \
757 min_align = 4; \
758 if (align_functions < min_align) \
759 align_functions = min_align; \
760 } \
761 } while (0)
762 \f
763 /* Target machine storage layout. */
764
765 /* Define this if most significant bit is lowest numbered
766 in instructions that operate on numbered bit-fields. */
767
768 #define BITS_BIG_ENDIAN 0
769
770 /* Define this if most significant byte of a word is the lowest numbered. */
771 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
772
773 /* Define this if most significant word of a multiword number is the lowest
774 numbered. */
775 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
776
777 /* Define this to set the endianness to use in libgcc2.c, which can
778 not depend on target_flags. */
779 #if defined(__LITTLE_ENDIAN__)
780 #define LIBGCC2_WORDS_BIG_ENDIAN 0
781 #else
782 #define LIBGCC2_WORDS_BIG_ENDIAN 1
783 #endif
784
785 #define MAX_BITS_PER_WORD 64
786
787 /* Width in bits of an `int'. We want just 32-bits, even if words are
788 longer. */
789 #define INT_TYPE_SIZE 32
790
791 /* Width in bits of a `long'. */
792 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
793
794 /* Width in bits of a `long long'. */
795 #define LONG_LONG_TYPE_SIZE 64
796
797 /* Width in bits of a `long double'. */
798 #define LONG_DOUBLE_TYPE_SIZE 64
799
800 /* Width of a word, in units (bytes). */
801 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
802 #define MIN_UNITS_PER_WORD 4
803
804 /* Scaling factor for Dwarf data offsets for CFI information.
805 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
806 SHmedia; however, since we do partial register saves for the registers
807 visible to SHcompact, and for target registers for SHMEDIA32, we have
808 to allow saves that are only 4-byte aligned. */
809 #define DWARF_CIE_DATA_ALIGNMENT -4
810
811 /* Width in bits of a pointer.
812 See also the macro `Pmode' defined below. */
813 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
814
815 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
816 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
817
818 /* Boundary (in *bits*) on which stack pointer should be aligned. */
819 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
820
821 /* The log (base 2) of the cache line size, in bytes. Processors prior to
822 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
823 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
824 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
825
826 /* ABI given & required minimum allocation boundary (in *bits*) for the
827 code of a function. */
828 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
829
830 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
831 the vbit must go into the delta field of
832 pointers-to-member-functions. */
833 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
834 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
835
836 /* Alignment of field after `int : 0' in a structure. */
837 #define EMPTY_FIELD_BOUNDARY 32
838
839 /* No data type wants to be aligned rounder than this. */
840 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
841
842 /* The best alignment to use in cases where we have a choice. */
843 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
844
845 /* Make strings word-aligned so strcpy from constants will be faster. */
846 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
847 ((TREE_CODE (EXP) == STRING_CST \
848 && (ALIGN) < FASTEST_ALIGNMENT) \
849 ? FASTEST_ALIGNMENT : (ALIGN))
850
851 /* get_mode_alignment assumes complex values are always held in multiple
852 registers, but that is not the case on the SH; CQImode and CHImode are
853 held in a single integer register. SH5 also holds CSImode and SCmode
854 values in integer registers. This is relevant for argument passing on
855 SHcompact as we use a stack temp in order to pass CSImode by reference. */
856 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
857 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
858 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
859 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
860 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
861
862 /* Make arrays of chars word-aligned for the same reasons. */
863 #define DATA_ALIGNMENT(TYPE, ALIGN) \
864 (TREE_CODE (TYPE) == ARRAY_TYPE \
865 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
866 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
867
868 /* Number of bits which any structure or union's size must be a
869 multiple of. Each structure or union's size is rounded up to a
870 multiple of this. */
871 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
872
873 /* Set this nonzero if move instructions will actually fail to work
874 when given unaligned data. */
875 #define STRICT_ALIGNMENT 1
876
877 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
878 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
879 barrier_align (LABEL_AFTER_BARRIER)
880
881 #define LOOP_ALIGN(A_LABEL) \
882 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
883 ? 0 : sh_loop_align (A_LABEL))
884
885 #define LABEL_ALIGN(A_LABEL) \
886 ( \
887 (PREV_INSN (A_LABEL) \
888 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
889 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
890 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
891 /* explicit alignment insn in constant tables. */ \
892 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
893 : 0)
894
895 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
896 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
897
898 /* The base two logarithm of the known minimum alignment of an insn length. */
899 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
900 (GET_CODE (A_INSN) == INSN \
901 ? 1 << TARGET_SHMEDIA \
902 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
903 ? 1 << TARGET_SHMEDIA \
904 : CACHE_LOG)
905 \f
906 /* Standard register usage. */
907
908 /* Register allocation for the Renesas calling convention:
909
910 r0 arg return
911 r1..r3 scratch
912 r4..r7 args in
913 r8..r13 call saved
914 r14 frame pointer/call saved
915 r15 stack pointer
916 ap arg pointer (doesn't really exist, always eliminated)
917 pr subroutine return address
918 t t bit
919 mach multiply/accumulate result, high part
920 macl multiply/accumulate result, low part.
921 fpul fp/int communication register
922 rap return address pointer register
923 fr0 fp arg return
924 fr1..fr3 scratch floating point registers
925 fr4..fr11 fp args in
926 fr12..fr15 call saved floating point registers */
927
928 #define MAX_REGISTER_NAME_LENGTH 5
929 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
930
931 #define SH_REGISTER_NAMES_INITIALIZER \
932 { \
933 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
934 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
935 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
936 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
937 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
938 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
939 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
940 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
941 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
942 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
943 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
944 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
945 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
946 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
947 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
948 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
949 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
950 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
951 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
952 "rap", "sfp" \
953 }
954
955 #define REGNAMES_ARR_INDEX_1(index) \
956 (sh_register_names[index])
957 #define REGNAMES_ARR_INDEX_2(index) \
958 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
959 #define REGNAMES_ARR_INDEX_4(index) \
960 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
961 #define REGNAMES_ARR_INDEX_8(index) \
962 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
963 #define REGNAMES_ARR_INDEX_16(index) \
964 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
965 #define REGNAMES_ARR_INDEX_32(index) \
966 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
967 #define REGNAMES_ARR_INDEX_64(index) \
968 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
969
970 #define REGISTER_NAMES \
971 { \
972 REGNAMES_ARR_INDEX_64 (0), \
973 REGNAMES_ARR_INDEX_64 (64), \
974 REGNAMES_ARR_INDEX_8 (128), \
975 REGNAMES_ARR_INDEX_8 (136), \
976 REGNAMES_ARR_INDEX_8 (144), \
977 REGNAMES_ARR_INDEX_2 (152) \
978 }
979
980 #define ADDREGNAMES_SIZE 32
981 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
982 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
983 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
984
985 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
986 { \
987 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
988 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
989 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
990 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
991 }
992
993 #define ADDREGNAMES_REGNO(index) \
994 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
995 : (-1))
996
997 #define ADDREGNAMES_ARR_INDEX_1(index) \
998 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
999 #define ADDREGNAMES_ARR_INDEX_2(index) \
1000 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
1001 #define ADDREGNAMES_ARR_INDEX_4(index) \
1002 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
1003 #define ADDREGNAMES_ARR_INDEX_8(index) \
1004 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1005 #define ADDREGNAMES_ARR_INDEX_16(index) \
1006 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1007 #define ADDREGNAMES_ARR_INDEX_32(index) \
1008 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1009
1010 #define ADDITIONAL_REGISTER_NAMES \
1011 { \
1012 ADDREGNAMES_ARR_INDEX_32 (0) \
1013 }
1014
1015 /* Number of actual hardware registers.
1016 The hardware registers are assigned numbers for the compiler
1017 from 0 to just below FIRST_PSEUDO_REGISTER.
1018 All registers that the compiler knows about must be given numbers,
1019 even those that are not normally considered general registers. */
1020
1021 /* There are many other relevant definitions in sh.md's md_constants. */
1022
1023 #define FIRST_GENERAL_REG R0_REG
1024 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1025 #define FIRST_FP_REG DR0_REG
1026 #define LAST_FP_REG (FIRST_FP_REG + \
1027 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1028 #define FIRST_XD_REG XD0_REG
1029 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1030 #define FIRST_TARGET_REG TR0_REG
1031 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1032
1033 #define GENERAL_REGISTER_P(REGNO) \
1034 IN_RANGE ((REGNO), \
1035 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1036 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1037
1038 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1039 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
1040 || ((REGNO) == FRAME_POINTER_REGNUM))
1041
1042 #define FP_REGISTER_P(REGNO) \
1043 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1044
1045 #define XD_REGISTER_P(REGNO) \
1046 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1047
1048 #define FP_OR_XD_REGISTER_P(REGNO) \
1049 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1050
1051 #define FP_ANY_REGISTER_P(REGNO) \
1052 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1053
1054 #define SPECIAL_REGISTER_P(REGNO) \
1055 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1056 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1057
1058 #define TARGET_REGISTER_P(REGNO) \
1059 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1060
1061 #define SHMEDIA_REGISTER_P(REGNO) \
1062 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1063 || TARGET_REGISTER_P (REGNO))
1064
1065 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1066 that should be fixed. */
1067 #define VALID_REGISTER_P(REGNO) \
1068 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1069 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1070 || (REGNO) == FRAME_POINTER_REGNUM \
1071 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1072 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1073
1074 /* The mode that should be generally used to store a register by
1075 itself in the stack, or to load it back. */
1076 #define REGISTER_NATURAL_MODE(REGNO) \
1077 (FP_REGISTER_P (REGNO) ? SFmode \
1078 : XD_REGISTER_P (REGNO) ? DFmode \
1079 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1080 ? DImode \
1081 : SImode)
1082
1083 #define FIRST_PSEUDO_REGISTER 154
1084
1085 /* Don't count soft frame pointer. */
1086 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1087
1088 /* 1 for registers that have pervasive standard uses
1089 and are not available for the register allocator.
1090
1091 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1092 It is 32 bits wide for SH2. */
1093
1094 #define FIXED_REGISTERS \
1095 { \
1096 /* Regular registers. */ \
1097 0, 0, 0, 0, 0, 0, 0, 0, \
1098 0, 0, 0, 0, 0, 0, 0, 1, \
1099 /* r16 is reserved, r18 is the former pr. */ \
1100 1, 0, 0, 0, 0, 0, 0, 0, \
1101 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1102 /* r26 is a global variable data pointer; r27 is for constants. */ \
1103 1, 1, 1, 1, 0, 0, 0, 0, \
1104 0, 0, 0, 0, 0, 0, 0, 0, \
1105 0, 0, 0, 0, 0, 0, 0, 0, \
1106 0, 0, 0, 0, 0, 0, 0, 0, \
1107 0, 0, 0, 0, 0, 0, 0, 1, \
1108 /* FP registers. */ \
1109 0, 0, 0, 0, 0, 0, 0, 0, \
1110 0, 0, 0, 0, 0, 0, 0, 0, \
1111 0, 0, 0, 0, 0, 0, 0, 0, \
1112 0, 0, 0, 0, 0, 0, 0, 0, \
1113 0, 0, 0, 0, 0, 0, 0, 0, \
1114 0, 0, 0, 0, 0, 0, 0, 0, \
1115 0, 0, 0, 0, 0, 0, 0, 0, \
1116 0, 0, 0, 0, 0, 0, 0, 0, \
1117 /* Branch target registers. */ \
1118 0, 0, 0, 0, 0, 0, 0, 0, \
1119 /* XD registers. */ \
1120 0, 0, 0, 0, 0, 0, 0, 0, \
1121 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1122 1, 1, 1, 1, 1, 1, 0, 1, \
1123 /*"rap", "sfp" */ \
1124 1, 1, \
1125 }
1126
1127 /* 1 for registers not available across function calls.
1128 These must include the FIXED_REGISTERS and also any
1129 registers that can be used without being saved.
1130 The latter must include the registers where values are returned
1131 and the register where structure-value addresses are passed.
1132 Aside from that, you can include as many other registers as you like. */
1133
1134 #define CALL_USED_REGISTERS \
1135 { \
1136 /* Regular registers. */ \
1137 1, 1, 1, 1, 1, 1, 1, 1, \
1138 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1139 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1140 across SH5 function calls. */ \
1141 0, 0, 0, 0, 0, 0, 0, 1, \
1142 1, 1, 1, 1, 1, 1, 1, 1, \
1143 1, 1, 1, 1, 0, 0, 0, 0, \
1144 0, 0, 0, 0, 1, 1, 1, 1, \
1145 1, 1, 1, 1, 0, 0, 0, 0, \
1146 0, 0, 0, 0, 0, 0, 0, 0, \
1147 0, 0, 0, 0, 1, 1, 1, 1, \
1148 /* FP registers. */ \
1149 1, 1, 1, 1, 1, 1, 1, 1, \
1150 1, 1, 1, 1, 0, 0, 0, 0, \
1151 1, 1, 1, 1, 1, 1, 1, 1, \
1152 1, 1, 1, 1, 1, 1, 1, 1, \
1153 1, 1, 1, 1, 0, 0, 0, 0, \
1154 0, 0, 0, 0, 0, 0, 0, 0, \
1155 0, 0, 0, 0, 0, 0, 0, 0, \
1156 0, 0, 0, 0, 0, 0, 0, 0, \
1157 /* Branch target registers. */ \
1158 1, 1, 1, 1, 1, 0, 0, 0, \
1159 /* XD registers. */ \
1160 1, 1, 1, 1, 1, 1, 0, 0, \
1161 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1162 1, 1, 1, 1, 1, 1, 1, 1, \
1163 /*"rap", "sfp" */ \
1164 1, 1, \
1165 }
1166
1167 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1168 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1169 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1170
1171 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1172 across SHcompact function calls. We can't tell whether a called
1173 function is SHmedia or SHcompact, so we assume it may be when
1174 compiling SHmedia code with the 32-bit ABI, since that's the only
1175 ABI that can be linked with SHcompact code. */
1176 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1177 (TARGET_SHMEDIA32 \
1178 && GET_MODE_SIZE (MODE) > 4 \
1179 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1180 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1181 || TARGET_REGISTER_P (REGNO) \
1182 || (REGNO) == PR_MEDIA_REG))
1183
1184 /* Return number of consecutive hard regs needed starting at reg REGNO
1185 to hold something of mode MODE.
1186 This is ordinarily the length in words of a value of mode MODE
1187 but can be less for certain modes in special long registers.
1188
1189 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1190
1191 #define HARD_REGNO_NREGS(REGNO, MODE) \
1192 (XD_REGISTER_P (REGNO) \
1193 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1194 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1195 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1196 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1197
1198 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1199 We can allow any mode in any general register. The special registers
1200 only allow SImode. Don't allow any mode in the PR. */
1201
1202 /* We cannot hold DCmode values in the XD registers because alter_reg
1203 handles subregs of them incorrectly. We could work around this by
1204 spacing the XD registers like the DR registers, but this would require
1205 additional memory in every compilation to hold larger register vectors.
1206 We could hold SFmode / SCmode values in XD registers, but that
1207 would require a tertiary reload when reloading from / to memory,
1208 and a secondary reload to reload from / to general regs; that
1209 seems to be a loosing proposition. */
1210 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1211 it won't be ferried through GP registers first. */
1212 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1213 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1214 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1215 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1216 ? 1 \
1217 : (MODE) == V2SFmode \
1218 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1219 || GENERAL_REGISTER_P (REGNO)) \
1220 : (MODE) == V4SFmode \
1221 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1222 || GENERAL_REGISTER_P (REGNO)) \
1223 : (MODE) == V16SFmode \
1224 ? (TARGET_SHMEDIA \
1225 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1226 : (REGNO) == FIRST_XD_REG) \
1227 : FP_REGISTER_P (REGNO) \
1228 ? ((MODE) == SFmode || (MODE) == SImode \
1229 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1230 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1231 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1232 || (MODE) == V2SFmode || (MODE) == TImode))) \
1233 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1234 || ((TARGET_SH4 || TARGET_SHMEDIA) \
1235 && (MODE) == TImode \
1236 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1237 : XD_REGISTER_P (REGNO) \
1238 ? (MODE) == DFmode \
1239 : TARGET_REGISTER_P (REGNO) \
1240 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1241 : (REGNO) == PR_REG ? (MODE) == SImode \
1242 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1243 : 1)
1244
1245 /* Value is 1 if it is a good idea to tie two pseudo registers
1246 when one has mode MODE1 and one has mode MODE2.
1247 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1248 for any hard reg, then this must be 0 for correct output.
1249 That's the case for xd registers: we don't hold SFmode values in
1250 them, so we can't tie an SFmode pseudos with one in another
1251 floating-point mode. */
1252
1253 #define MODES_TIEABLE_P(MODE1, MODE2) \
1254 ((MODE1) == (MODE2) \
1255 || (TARGET_SHMEDIA \
1256 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1257 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1258 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1259 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1260 && (GET_MODE_SIZE (MODE2) <= 4)) \
1261 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1262
1263 /* A C expression that is nonzero if hard register NEW_REG can be
1264 considered for use as a rename register for OLD_REG register */
1265
1266 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1267 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1268
1269 /* Specify the registers used for certain standard purposes.
1270 The values of these macros are register numbers. */
1271
1272 /* Define this if the program counter is overloaded on a register. */
1273 /* #define PC_REGNUM 15*/
1274
1275 /* Register to use for pushing function arguments. */
1276 #define STACK_POINTER_REGNUM SP_REG
1277
1278 /* Base register for access to local variables of the function. */
1279 #define HARD_FRAME_POINTER_REGNUM FP_REG
1280
1281 /* Base register for access to local variables of the function. */
1282 #define FRAME_POINTER_REGNUM 153
1283
1284 /* Fake register that holds the address on the stack of the
1285 current function's return address. */
1286 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1287
1288 /* Register to hold the addressing base for position independent
1289 code access to data items. */
1290 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1291
1292 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1293
1294 /* Value should be nonzero if functions must have frame pointers.
1295 Zero means the frame pointer need not be set up (and parms may be accessed
1296 via the stack pointer) in functions that seem suitable. */
1297
1298 #define FRAME_POINTER_REQUIRED 0
1299
1300 /* Definitions for register eliminations.
1301
1302 We have three registers that can be eliminated on the SH. First, the
1303 frame pointer register can often be eliminated in favor of the stack
1304 pointer register. Secondly, the argument pointer register can always be
1305 eliminated; it is replaced with either the stack or frame pointer.
1306 Third, there is the return address pointer, which can also be replaced
1307 with either the stack or the frame pointer. */
1308
1309 /* This is an array of structures. Each structure initializes one pair
1310 of eliminable registers. The "from" register number is given first,
1311 followed by "to". Eliminations of the same "from" register are listed
1312 in order of preference. */
1313
1314 /* If you add any registers here that are not actually hard registers,
1315 and that have any alternative of elimination that doesn't always
1316 apply, you need to amend calc_live_regs to exclude it, because
1317 reload spills all eliminable registers where it sees an
1318 can_eliminate == 0 entry, thus making them 'live' .
1319 If you add any hard registers that can be eliminated in different
1320 ways, you have to patch reload to spill them only when all alternatives
1321 of elimination fail. */
1322
1323 #define ELIMINABLE_REGS \
1324 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1325 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1326 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1327 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1328 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1329 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1330 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1331
1332 /* Given FROM and TO register numbers, say whether this elimination
1333 is allowed. */
1334 #define CAN_ELIMINATE(FROM, TO) \
1335 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1336
1337 /* Define the offset between two registers, one to be eliminated, and the other
1338 its replacement, at the start of a routine. */
1339
1340 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1341 OFFSET = initial_elimination_offset ((FROM), (TO))
1342
1343 /* Base register for access to arguments of the function. */
1344 #define ARG_POINTER_REGNUM AP_REG
1345
1346 /* Register in which the static-chain is passed to a function. */
1347 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1348
1349 /* Don't default to pcc-struct-return, because we have already specified
1350 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1351 target hook. */
1352
1353 #define DEFAULT_PCC_STRUCT_RETURN 0
1354
1355 #define SHMEDIA_REGS_STACK_ADJUST() \
1356 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1357 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1358 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1359 : 0)
1360
1361 \f
1362 /* Define the classes of registers for register constraints in the
1363 machine description. Also define ranges of constants.
1364
1365 One of the classes must always be named ALL_REGS and include all hard regs.
1366 If there is more than one class, another class must be named NO_REGS
1367 and contain no registers.
1368
1369 The name GENERAL_REGS must be the name of a class (or an alias for
1370 another name such as ALL_REGS). This is the class of registers
1371 that is allowed by "g" or "r" in a register constraint.
1372 Also, registers outside this class are allocated only when
1373 instructions express preferences for them.
1374
1375 The classes must be numbered in nondecreasing order; that is,
1376 a larger-numbered class must never be contained completely
1377 in a smaller-numbered class.
1378
1379 For any two classes, it is very desirable that there be another
1380 class that represents their union. */
1381
1382 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1383 be used as the destination of some of the arithmetic ops. There are
1384 also some special purpose registers; the T bit register, the
1385 Procedure Return Register and the Multiply Accumulate Registers. */
1386 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1387 reg_class_subunion. We don't want to have an actual union class
1388 of these, because it would only be used when both classes are calculated
1389 to give the same cost, but there is only one FPUL register.
1390 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1391 applying to the actual instruction alternative considered. E.g., the
1392 y/r alternative of movsi_ie is considered to have no more cost that
1393 the r/r alternative, which is patently untrue. */
1394
1395 enum reg_class
1396 {
1397 NO_REGS,
1398 R0_REGS,
1399 PR_REGS,
1400 T_REGS,
1401 MAC_REGS,
1402 FPUL_REGS,
1403 SIBCALL_REGS,
1404 GENERAL_REGS,
1405 FP0_REGS,
1406 FP_REGS,
1407 DF_HI_REGS,
1408 DF_REGS,
1409 FPSCR_REGS,
1410 GENERAL_FP_REGS,
1411 GENERAL_DF_REGS,
1412 TARGET_REGS,
1413 ALL_REGS,
1414 LIM_REG_CLASSES
1415 };
1416
1417 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1418
1419 /* Give names of register classes as strings for dump file. */
1420 #define REG_CLASS_NAMES \
1421 { \
1422 "NO_REGS", \
1423 "R0_REGS", \
1424 "PR_REGS", \
1425 "T_REGS", \
1426 "MAC_REGS", \
1427 "FPUL_REGS", \
1428 "SIBCALL_REGS", \
1429 "GENERAL_REGS", \
1430 "FP0_REGS", \
1431 "FP_REGS", \
1432 "DF_HI_REGS", \
1433 "DF_REGS", \
1434 "FPSCR_REGS", \
1435 "GENERAL_FP_REGS", \
1436 "GENERAL_DF_REGS", \
1437 "TARGET_REGS", \
1438 "ALL_REGS", \
1439 }
1440
1441 /* Define which registers fit in which classes.
1442 This is an initializer for a vector of HARD_REG_SET
1443 of length N_REG_CLASSES. */
1444
1445 #define REG_CLASS_CONTENTS \
1446 { \
1447 /* NO_REGS: */ \
1448 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1449 /* R0_REGS: */ \
1450 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1451 /* PR_REGS: */ \
1452 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1453 /* T_REGS: */ \
1454 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1455 /* MAC_REGS: */ \
1456 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1457 /* FPUL_REGS: */ \
1458 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1459 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1460 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1461 /* GENERAL_REGS: */ \
1462 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1463 /* FP0_REGS: */ \
1464 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1465 /* FP_REGS: */ \
1466 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1467 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1468 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1469 /* DF_REGS: */ \
1470 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1471 /* FPSCR_REGS: */ \
1472 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1473 /* GENERAL_FP_REGS: */ \
1474 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1475 /* GENERAL_DF_REGS: */ \
1476 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1477 /* TARGET_REGS: */ \
1478 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1479 /* ALL_REGS: */ \
1480 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1481 }
1482
1483 /* The same information, inverted:
1484 Return the class number of the smallest class containing
1485 reg number REGNO. This could be a conditional expression
1486 or could index an array. */
1487
1488 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1489 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1490
1491 /* When defined, the compiler allows registers explicitly used in the
1492 rtl to be used as spill registers but prevents the compiler from
1493 extending the lifetime of these registers. */
1494
1495 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1496
1497 /* The order in which register should be allocated. */
1498 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1499 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1500 spilled or used otherwise, we better have the FP_REGS allocated first. */
1501 #define REG_ALLOC_ORDER \
1502 {/* Caller-saved FPRs */ \
1503 65, 66, 67, 68, 69, 70, 71, 64, \
1504 72, 73, 74, 75, 80, 81, 82, 83, \
1505 84, 85, 86, 87, 88, 89, 90, 91, \
1506 92, 93, 94, 95, 96, 97, 98, 99, \
1507 /* Callee-saved FPRs */ \
1508 76, 77, 78, 79,100,101,102,103, \
1509 104,105,106,107,108,109,110,111, \
1510 112,113,114,115,116,117,118,119, \
1511 120,121,122,123,124,125,126,127, \
1512 136,137,138,139,140,141,142,143, \
1513 /* FPSCR */ 151, \
1514 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1515 1, 2, 3, 7, 6, 5, 4, 0, \
1516 8, 9, 17, 19, 20, 21, 22, 23, \
1517 36, 37, 38, 39, 40, 41, 42, 43, \
1518 60, 61, 62, \
1519 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1520 10, 11, 12, 13, 14, 18, \
1521 /* SH5 callee-saved GPRs */ \
1522 28, 29, 30, 31, 32, 33, 34, 35, \
1523 44, 45, 46, 47, 48, 49, 50, 51, \
1524 52, 53, 54, 55, 56, 57, 58, 59, \
1525 /* FPUL */ 150, \
1526 /* SH5 branch target registers */ \
1527 128,129,130,131,132,133,134,135, \
1528 /* Fixed registers */ \
1529 15, 16, 24, 25, 26, 27, 63,144, \
1530 145,146,147,148,149,152,153 }
1531
1532 /* The class value for index registers, and the one for base regs. */
1533 #define INDEX_REG_CLASS \
1534 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1535 #define BASE_REG_CLASS GENERAL_REGS
1536
1537 /* Get reg_class from a letter such as appears in the machine
1538 description. */
1539 extern enum reg_class reg_class_from_letter[];
1540
1541 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1542 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1543 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1544 \f
1545 /* Overview of uppercase letter constraints:
1546 A: Addresses (constraint len == 3)
1547 Ac4: sh4 cache operations
1548 Ac5: sh5 cache operations
1549 Bxx: miscellaneous constraints
1550 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1551 fldi0 / fldi0 cases
1552 C: Constants other than only CONST_INT (constraint len == 3)
1553 Css: signed 16-bit constant, literal or symbolic
1554 Csu: unsigned 16-bit constant, literal or symbolic
1555 Csy: label or symbol
1556 Cpg: non-explicit constants that can be directly loaded into a general
1557 purpose register in PIC code. like 's' except we don't allow
1558 PIC_DIRECT_ADDR_P
1559 IJKLMNOP: CONT_INT constants
1560 Ixx: signed xx bit
1561 J16: 0xffffffff00000000 | 0x00000000ffffffff
1562 Kxx: unsigned xx bit
1563 M: 1
1564 N: 0
1565 P27: 1 | 2 | 8 | 16
1566 Q: pc relative load operand
1567 Rxx: reserved for exotic register classes.
1568 S: extra memory (storage) constraints (constraint len == 3)
1569 Sua: unaligned memory operations
1570 W: vector
1571 Z: zero in any mode
1572
1573 unused CONST_INT constraint letters: LO
1574 unused EXTRA_CONSTRAINT letters: D T U Y */
1575
1576 #define CONSTRAINT_LEN(C,STR) \
1577 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1578 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1579 || (C) == 'R' || (C) == 'S') \
1580 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1581
1582 /* The letters I, J, K, L and M in a register constraint string
1583 can be used to stand for particular ranges of immediate operands.
1584 This macro defines what the ranges are.
1585 C is the letter, and VALUE is a constant value.
1586 Return 1 if VALUE is in the range specified by C.
1587 I08: arithmetic operand -127..128, as used in add, sub, etc
1588 I16: arithmetic operand -32768..32767, as used in SHmedia movi
1589 K16: arithmetic operand 0..65535, as used in SHmedia shori
1590 P27: shift operand 1,2,8 or 16
1591 K08: logical operand 0..255, as used in and, or, etc.
1592 M: constant 1
1593 N: constant 0
1594 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1595 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1596 */
1597
1598 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1599 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1600 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1601 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1602 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1603 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1604 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1605 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1606 #define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
1607 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
1608 && TARGET_SH2A)
1609 #define CONST_OK_FOR_I(VALUE, STR) \
1610 ((STR)[1] == '0' && (STR)[2] == '6' ? CONST_OK_FOR_I06 (VALUE) \
1611 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1612 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1613 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1614 : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
1615 : 0)
1616
1617 #define CONST_OK_FOR_J16(VALUE) \
1618 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1619 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1620 #define CONST_OK_FOR_J(VALUE, STR) \
1621 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1622 : 0)
1623
1624 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1625 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1626 #define CONST_OK_FOR_K16(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1627 && ((HOST_WIDE_INT)(VALUE)) <= 65535)
1628 #define CONST_OK_FOR_K(VALUE, STR) \
1629 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1630 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_K16 (VALUE) \
1631 : 0)
1632 #define CONST_OK_FOR_P27(VALUE) \
1633 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1634 #define CONST_OK_FOR_P(VALUE, STR) \
1635 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1636 : 0)
1637 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1638 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1639 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1640 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1641 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1642 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1643 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1644 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1645 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1646 : 0)
1647
1648 /* Similar, but for floating constants, and defining letters G and H.
1649 Here VALUE is the CONST_DOUBLE rtx itself. */
1650
1651 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1652 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1653 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1654 : (C) == 'F')
1655
1656 /* Given an rtx X being reloaded into a reg required to be
1657 in class CLASS, return the class of reg to actually use.
1658 In general this is just CLASS; but on some machines
1659 in some cases it is preferable to use a more restrictive class. */
1660
1661 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1662 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1663 && (GET_CODE (X) == CONST_DOUBLE \
1664 || GET_CODE (X) == SYMBOL_REF \
1665 || PIC_DIRECT_ADDR_P (X)) \
1666 ? GENERAL_REGS \
1667 : (CLASS)) \
1668
1669 #if 0
1670 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1671 ((((REGCLASS_HAS_FP_REG (CLASS) \
1672 && (GET_CODE (X) == REG \
1673 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1674 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1675 && TARGET_FMOVD)))) \
1676 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1677 && GET_CODE (X) == REG \
1678 && FP_REGISTER_P (REGNO (X)))) \
1679 && ! TARGET_SHMEDIA \
1680 && ((MODE) == SFmode || (MODE) == SImode)) \
1681 ? FPUL_REGS \
1682 : (((CLASS) == FPUL_REGS \
1683 || (REGCLASS_HAS_FP_REG (CLASS) \
1684 && ! TARGET_SHMEDIA && MODE == SImode)) \
1685 && (GET_CODE (X) == MEM \
1686 || (GET_CODE (X) == REG \
1687 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1688 || REGNO (X) == T_REG \
1689 || system_reg_operand (X, VOIDmode))))) \
1690 ? GENERAL_REGS \
1691 : (((CLASS) == TARGET_REGS \
1692 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1693 && !EXTRA_CONSTRAINT_Csy (X) \
1694 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1695 ? GENERAL_REGS \
1696 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1697 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1698 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1699 ? GENERAL_REGS \
1700 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1701 && TARGET_REGISTER_P (REGNO (X))) \
1702 ? GENERAL_REGS : (ELSE))
1703
1704 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1705 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1706
1707 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1708 ((REGCLASS_HAS_FP_REG (CLASS) \
1709 && ! TARGET_SHMEDIA \
1710 && immediate_operand ((X), (MODE)) \
1711 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1712 && (MODE) == SFmode && fldi_ok ())) \
1713 ? R0_REGS \
1714 : ((CLASS) == FPUL_REGS \
1715 && ((GET_CODE (X) == REG \
1716 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1717 || REGNO (X) == T_REG)) \
1718 || GET_CODE (X) == PLUS)) \
1719 ? GENERAL_REGS \
1720 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1721 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1722 ? GENERAL_REGS \
1723 : R0_REGS) \
1724 : ((CLASS) == FPSCR_REGS \
1725 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1726 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1727 ? GENERAL_REGS \
1728 : (REGCLASS_HAS_FP_REG (CLASS) \
1729 && TARGET_SHMEDIA \
1730 && immediate_operand ((X), (MODE)) \
1731 && (X) != CONST0_RTX (GET_MODE (X)) \
1732 && GET_MODE (X) != V4SFmode) \
1733 ? GENERAL_REGS \
1734 : (((MODE) == QImode || (MODE) == HImode) \
1735 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1736 ? GENERAL_REGS \
1737 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1738 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
1739 ? TARGET_REGS \
1740 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1741 #endif
1742
1743 /* Return the maximum number of consecutive registers
1744 needed to represent mode MODE in a register of class CLASS.
1745
1746 If TARGET_SHMEDIA, we need two FP registers per word.
1747 Otherwise we will need at most one register per word. */
1748 #define CLASS_MAX_NREGS(CLASS, MODE) \
1749 (TARGET_SHMEDIA \
1750 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1751 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1752 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1753
1754 /* If defined, gives a class of registers that cannot be used as the
1755 operand of a SUBREG that changes the mode of the object illegally. */
1756 /* ??? We need to renumber the internal numbers for the frnn registers
1757 when in little endian in order to allow mode size changes. */
1758
1759 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1760 sh_cannot_change_mode_class (FROM, TO, CLASS)
1761 \f
1762 /* Stack layout; function entry, exit and calling. */
1763
1764 /* Define the number of registers that can hold parameters.
1765 These macros are used only in other macro definitions below. */
1766
1767 #define NPARM_REGS(MODE) \
1768 (TARGET_FPU_ANY && (MODE) == SFmode \
1769 ? (TARGET_SH5 ? 12 : 8) \
1770 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1771 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1772 ? (TARGET_SH5 ? 12 : 8) \
1773 : (TARGET_SH5 ? 8 : 4))
1774
1775 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1776 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1777
1778 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1779 #define FIRST_FP_RET_REG FIRST_FP_REG
1780
1781 /* Define this if pushing a word on the stack
1782 makes the stack pointer a smaller address. */
1783 #define STACK_GROWS_DOWNWARD
1784
1785 /* Define this macro to nonzero if the addresses of local variable slots
1786 are at negative offsets from the frame pointer. */
1787 #define FRAME_GROWS_DOWNWARD 1
1788
1789 /* Offset from the frame pointer to the first local variable slot to
1790 be allocated. */
1791 #define STARTING_FRAME_OFFSET 0
1792
1793 /* If we generate an insn to push BYTES bytes,
1794 this says how many the stack pointer really advances by. */
1795 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1796 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1797 do correct alignment. */
1798 #if 0
1799 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1800 #endif
1801
1802 /* Offset of first parameter from the argument pointer register value. */
1803 #define FIRST_PARM_OFFSET(FNDECL) 0
1804
1805 /* Value is the number of byte of arguments automatically
1806 popped when returning from a subroutine call.
1807 FUNDECL is the declaration node of the function (as a tree),
1808 FUNTYPE is the data type of the function (as a tree),
1809 or for a library call it is an identifier node for the subroutine name.
1810 SIZE is the number of bytes of arguments passed on the stack.
1811
1812 On the SH, the caller does not pop any of its arguments that were passed
1813 on the stack. */
1814 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1815
1816 /* Value is the number of bytes of arguments automatically popped when
1817 calling a subroutine.
1818 CUM is the accumulated argument list.
1819
1820 On SHcompact, the call trampoline pops arguments off the stack. */
1821 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1822
1823 /* Some subroutine macros specific to this machine. */
1824
1825 #define BASE_RETURN_VALUE_REG(MODE) \
1826 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1827 ? FIRST_FP_RET_REG \
1828 : TARGET_FPU_ANY && (MODE) == SCmode \
1829 ? FIRST_FP_RET_REG \
1830 : (TARGET_FPU_DOUBLE \
1831 && ((MODE) == DFmode || (MODE) == SFmode \
1832 || (MODE) == DCmode || (MODE) == SCmode )) \
1833 ? FIRST_FP_RET_REG \
1834 : FIRST_RET_REG)
1835
1836 #define BASE_ARG_REG(MODE) \
1837 ((TARGET_SH2E && ((MODE) == SFmode)) \
1838 ? FIRST_FP_PARM_REG \
1839 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1840 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1841 ? FIRST_FP_PARM_REG \
1842 : FIRST_PARM_REG)
1843
1844 /* Define how to find the value returned by a function.
1845 VALTYPE is the data type of the value (as a tree).
1846 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1847 otherwise, FUNC is 0.
1848 For the SH, this is like LIBCALL_VALUE, except that we must change the
1849 mode like PROMOTE_MODE does.
1850 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1851 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1852
1853 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1854 gen_rtx_REG ( \
1855 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1856 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1857 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1858 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1859 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1860 || TREE_CODE (VALTYPE) == REAL_TYPE \
1861 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1862 && sh_promote_prototypes (VALTYPE) \
1863 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1864 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1865
1866 /* Define how to find the value returned by a library function
1867 assuming the value has mode MODE. */
1868 #define LIBCALL_VALUE(MODE) \
1869 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1870
1871 /* 1 if N is a possible register number for a function value. */
1872 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1873 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1874 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1875
1876 /* 1 if N is a possible register number for function argument passing. */
1877 /* ??? There are some callers that pass REGNO as int, and others that pass
1878 it as unsigned. We get warnings unless we do casts everywhere. */
1879 #define FUNCTION_ARG_REGNO_P(REGNO) \
1880 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1881 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1882 || (TARGET_FPU_ANY \
1883 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1884 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1885 + NPARM_REGS (SFmode))))
1886 \f
1887 /* Define a data type for recording info about an argument list
1888 during the scan of that argument list. This data type should
1889 hold all necessary information about the function itself
1890 and about the args processed so far, enough to enable macros
1891 such as FUNCTION_ARG to determine where the next arg should go.
1892
1893 On SH, this is a single integer, which is a number of words
1894 of arguments scanned so far (including the invisible argument,
1895 if any, which holds the structure-value-address).
1896 Thus NARGREGS or more means all following args should go on the stack. */
1897
1898 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1899 struct sh_args {
1900 int arg_count[2];
1901 int force_mem;
1902 /* Nonzero if a prototype is available for the function. */
1903 int prototype_p;
1904 /* The number of an odd floating-point register, that should be used
1905 for the next argument of type float. */
1906 int free_single_fp_reg;
1907 /* Whether we're processing an outgoing function call. */
1908 int outgoing;
1909 /* The number of general-purpose registers that should have been
1910 used to pass partial arguments, that are passed totally on the
1911 stack. On SHcompact, a call trampoline will pop them off the
1912 stack before calling the actual function, and, if the called
1913 function is implemented in SHcompact mode, the incoming arguments
1914 decoder will push such arguments back onto the stack. For
1915 incoming arguments, STACK_REGS also takes into account other
1916 arguments passed by reference, that the decoder will also push
1917 onto the stack. */
1918 int stack_regs;
1919 /* The number of general-purpose registers that should have been
1920 used to pass arguments, if the arguments didn't have to be passed
1921 by reference. */
1922 int byref_regs;
1923 /* Set as by shcompact_byref if the current argument is to be passed
1924 by reference. */
1925 int byref;
1926
1927 /* call_cookie is a bitmask used by call expanders, as well as
1928 function prologue and epilogues, to allow SHcompact to comply
1929 with the SH5 32-bit ABI, that requires 64-bit registers to be
1930 used even though only the lower 32-bit half is visible in
1931 SHcompact mode. The strategy is to call SHmedia trampolines.
1932
1933 The alternatives for each of the argument-passing registers are
1934 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1935 contents from the address in it; (d) add 8 to it, storing the
1936 result in the next register, then (c); (e) copy it from some
1937 floating-point register,
1938
1939 Regarding copies from floating-point registers, r2 may only be
1940 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1941 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1942 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1943 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1944 dr10.
1945
1946 The bit mask is structured as follows:
1947
1948 - 1 bit to tell whether to set up a return trampoline.
1949
1950 - 3 bits to count the number consecutive registers to pop off the
1951 stack.
1952
1953 - 4 bits for each of r9, r8, r7 and r6.
1954
1955 - 3 bits for each of r5, r4, r3 and r2.
1956
1957 - 3 bits set to 0 (the most significant ones)
1958
1959 3 2 1 0
1960 1098 7654 3210 9876 5432 1098 7654 3210
1961 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1962 2223 3344 4555 6666 7777 8888 9999 SSS-
1963
1964 - If F is set, the register must be copied from an FP register,
1965 whose number is encoded in the remaining bits.
1966
1967 - Else, if L is set, the register must be loaded from the address
1968 contained in it. If the P bit is *not* set, the address of the
1969 following dword should be computed first, and stored in the
1970 following register.
1971
1972 - Else, if P is set, the register alone should be popped off the
1973 stack.
1974
1975 - After all this processing, the number of registers represented
1976 in SSS will be popped off the stack. This is an optimization
1977 for pushing/popping consecutive registers, typically used for
1978 varargs and large arguments partially passed in registers.
1979
1980 - If T is set, a return trampoline will be set up for 64-bit
1981 return values to be split into 2 32-bit registers. */
1982 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1983 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1984 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1985 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1986 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1987 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1988 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1989 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1990 #define CALL_COOKIE_INT_REG(REG, VAL) \
1991 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1992 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1993 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1994 long call_cookie;
1995
1996 /* This is set to nonzero when the call in question must use the Renesas ABI,
1997 even without the -mrenesas option. */
1998 int renesas_abi;
1999 };
2000
2001 #define CUMULATIVE_ARGS struct sh_args
2002
2003 #define GET_SH_ARG_CLASS(MODE) \
2004 ((TARGET_FPU_ANY && (MODE) == SFmode) \
2005 ? SH_ARG_FLOAT \
2006 /* There's no mention of complex float types in the SH5 ABI, so we
2007 should presumably handle them as aggregate types. */ \
2008 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
2009 ? SH_ARG_INT \
2010 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2011 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
2012 ? SH_ARG_FLOAT : SH_ARG_INT)
2013
2014 #define ROUND_ADVANCE(SIZE) \
2015 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2016
2017 /* Round a register number up to a proper boundary for an arg of mode
2018 MODE.
2019
2020 The SH doesn't care about double alignment, so we only
2021 round doubles to even regs when asked to explicitly. */
2022
2023 #define ROUND_REG(CUM, MODE) \
2024 (((TARGET_ALIGN_DOUBLE \
2025 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
2026 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
2027 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
2028 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
2029 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
2030 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
2031
2032 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2033 for a call to a function whose data type is FNTYPE.
2034 For a library call, FNTYPE is 0.
2035
2036 On SH, the offset always starts at 0: the first parm reg is always
2037 the same reg for a given argument class.
2038
2039 For TARGET_HITACHI, the structure value pointer is passed in memory. */
2040
2041 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
2042 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
2043
2044 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
2045 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
2046
2047 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2048 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
2049 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2050 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
2051
2052 /* Return boolean indicating arg of mode MODE will be passed in a reg.
2053 This macro is only used in this file. */
2054
2055 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2056 (((TYPE) == 0 \
2057 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2058 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2059 || ! (AGGREGATE_TYPE_P (TYPE) \
2060 || (!TARGET_FPU_ANY \
2061 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2062 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2063 && ! (CUM).force_mem \
2064 && (TARGET_SH2E \
2065 ? ((MODE) == BLKmode \
2066 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2067 + int_size_in_bytes (TYPE)) \
2068 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2069 : ((ROUND_REG((CUM), (MODE)) \
2070 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2071 <= NPARM_REGS (MODE))) \
2072 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2073
2074 /* By accident we got stuck with passing SCmode on SH4 little endian
2075 in two registers that are nominally successive - which is different from
2076 two single SFmode values, where we take endianness translation into
2077 account. That does not work at all if an odd number of registers is
2078 already in use, so that got fixed, but library functions are still more
2079 likely to use complex numbers without mixing them with SFmode arguments
2080 (which in C would have to be structures), so for the sake of ABI
2081 compatibility the way SCmode values are passed when an even number of
2082 FP registers is in use remains different from a pair of SFmode values for
2083 now.
2084 I.e.:
2085 foo (double); a: fr5,fr4
2086 foo (float a, float b); a: fr5 b: fr4
2087 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2088 this should be the other way round...
2089 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2090 #define FUNCTION_ARG_SCmode_WART 1
2091
2092 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2093 register in SHcompact mode, it must be padded in the most
2094 significant end. This means that passing it by reference wouldn't
2095 pad properly on a big-endian machine. In this particular case, we
2096 pass this argument on the stack, in a way that the call trampoline
2097 will load its value into the appropriate register. */
2098 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2099 ((MODE) == BLKmode \
2100 && TARGET_SHCOMPACT \
2101 && ! TARGET_LITTLE_ENDIAN \
2102 && int_size_in_bytes (TYPE) > 4 \
2103 && int_size_in_bytes (TYPE) < 8)
2104
2105 /* Minimum alignment for an argument to be passed by callee-copy
2106 reference. We need such arguments to be aligned to 8 byte
2107 boundaries, because they'll be loaded using quad loads. */
2108 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2109
2110 /* The SH5 ABI requires floating-point arguments to be passed to
2111 functions without a prototype in both an FP register and a regular
2112 register or the stack. When passing the argument in both FP and
2113 general-purpose registers, list the FP register first. */
2114 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2115 (gen_rtx_PARALLEL \
2116 ((MODE), \
2117 gen_rtvec (2, \
2118 gen_rtx_EXPR_LIST \
2119 (VOIDmode, \
2120 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2121 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2122 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2123 : NULL_RTX), \
2124 const0_rtx), \
2125 gen_rtx_EXPR_LIST \
2126 (VOIDmode, \
2127 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2128 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2129 + (CUM).arg_count[(int) SH_ARG_INT]) \
2130 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2131 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2132 const0_rtx))))
2133
2134 /* The SH5 ABI requires regular registers or stack slots to be
2135 reserved for floating-point arguments. Registers are taken care of
2136 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2137 Unfortunately, there's no way to just reserve a stack slot, so
2138 we'll end up needlessly storing a copy of the argument in the
2139 stack. For incoming arguments, however, the PARALLEL will be
2140 optimized to the register-only form, and the value in the stack
2141 slot won't be used at all. */
2142 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2143 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2144 ? gen_rtx_REG ((MODE), (REG)) \
2145 : gen_rtx_PARALLEL ((MODE), \
2146 gen_rtvec (2, \
2147 gen_rtx_EXPR_LIST \
2148 (VOIDmode, NULL_RTX, \
2149 const0_rtx), \
2150 gen_rtx_EXPR_LIST \
2151 (VOIDmode, gen_rtx_REG ((MODE), \
2152 (REG)), \
2153 const0_rtx))))
2154
2155 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2156 (TARGET_SH5 \
2157 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2158 || (MODE) == DCmode) \
2159 && ((CUM).arg_count[(int) SH_ARG_INT] \
2160 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2161 : GET_MODE_SIZE (MODE)) \
2162 + 7) / 8) > NPARM_REGS (SImode))
2163
2164 /* Perform any needed actions needed for a function that is receiving a
2165 variable number of arguments. */
2166
2167 /* Implement `va_start' for varargs and stdarg. */
2168 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2169 sh_va_start (valist, nextarg)
2170
2171 /* Call the function profiler with a given profile label.
2172 We use two .aligns, so as to make sure that both the .long is aligned
2173 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2174 from the trapa instruction. */
2175
2176 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2177 { \
2178 if (TARGET_SHMEDIA) \
2179 { \
2180 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2181 fprintf((STREAM), "\ttrapa\tr0\n"); \
2182 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2183 } \
2184 else \
2185 { \
2186 fprintf((STREAM), "\t.align\t2\n"); \
2187 fprintf((STREAM), "\ttrapa\t#33\n"); \
2188 fprintf((STREAM), "\t.align\t2\n"); \
2189 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2190 } \
2191 }
2192
2193 /* Define this macro if the code for function profiling should come
2194 before the function prologue. Normally, the profiling code comes
2195 after. */
2196
2197 #define PROFILE_BEFORE_PROLOGUE
2198
2199 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2200 the stack pointer does not matter. The value is tested only in
2201 functions that have frame pointers.
2202 No definition is equivalent to always zero. */
2203
2204 #define EXIT_IGNORE_STACK 1
2205
2206 /*
2207 On the SH, the trampoline looks like
2208 2 0002 D202 mov.l l2,r2
2209 1 0000 D301 mov.l l1,r3
2210 3 0004 422B jmp @r2
2211 4 0006 0009 nop
2212 5 0008 00000000 l1: .long area
2213 6 000c 00000000 l2: .long function */
2214
2215 /* Length in units of the trampoline for entering a nested function. */
2216 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2217
2218 /* Alignment required for a trampoline in bits . */
2219 #define TRAMPOLINE_ALIGNMENT \
2220 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2221 : TARGET_SHMEDIA ? 256 : 64)
2222
2223 /* Emit RTL insns to initialize the variable parts of a trampoline.
2224 FNADDR is an RTX for the address of the function's pure code.
2225 CXT is an RTX for the static chain value for the function. */
2226
2227 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2228 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2229
2230 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2231
2232 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2233 { \
2234 if (TARGET_SHMEDIA) \
2235 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2236 gen_reg_rtx (Pmode), 0, \
2237 OPTAB_LIB_WIDEN); \
2238 } while (0)
2239
2240 /* A C expression whose value is RTL representing the value of the return
2241 address for the frame COUNT steps up from the current frame.
2242 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2243 can ignore COUNT. */
2244
2245 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2246 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2247
2248 /* A C expression whose value is RTL representing the location of the
2249 incoming return address at the beginning of any function, before the
2250 prologue. This RTL is either a REG, indicating that the return
2251 value is saved in REG, or a MEM representing a location in
2252 the stack. */
2253 #define INCOMING_RETURN_ADDR_RTX \
2254 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2255 \f
2256 /* Addressing modes, and classification of registers for them. */
2257 #define HAVE_POST_INCREMENT TARGET_SH1
2258 #define HAVE_PRE_DECREMENT TARGET_SH1
2259
2260 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2261 ? 0 : TARGET_SH1)
2262 #define USE_LOAD_PRE_DECREMENT(mode) 0
2263 #define USE_STORE_POST_INCREMENT(mode) 0
2264 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2265 ? 0 : TARGET_SH1)
2266
2267 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2268 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2269 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2270
2271 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2272 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2273 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2274
2275 /* Macros to check register numbers against specific register classes. */
2276
2277 /* These assume that REGNO is a hard or pseudo reg number.
2278 They give nonzero only if REGNO is a hard reg of the suitable class
2279 or a pseudo reg currently allocated to a suitable hard reg.
2280 Since they use reg_renumber, they are safe only once reg_renumber
2281 has been allocated, which happens in local-alloc.c. */
2282
2283 #define REGNO_OK_FOR_BASE_P(REGNO) \
2284 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2285 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2286 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2287 (TARGET_SHMEDIA \
2288 ? (GENERAL_REGISTER_P (REGNO) \
2289 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2290 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2291
2292 /* Maximum number of registers that can appear in a valid memory
2293 address. */
2294
2295 #define MAX_REGS_PER_ADDRESS 2
2296
2297 /* Recognize any constant value that is a valid address. */
2298
2299 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2300
2301 /* Nonzero if the constant value X is a legitimate general operand. */
2302 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
2303
2304 #define LEGITIMATE_CONSTANT_P(X) \
2305 (TARGET_SHMEDIA \
2306 ? ((GET_MODE (X) != DFmode \
2307 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2308 || (X) == CONST0_RTX (GET_MODE (X)) \
2309 || ! TARGET_SHMEDIA_FPU \
2310 || TARGET_SHMEDIA64) \
2311 : (GET_CODE (X) != CONST_DOUBLE \
2312 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2313 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
2314
2315 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2316 and check its validity for a certain class.
2317 We have two alternate definitions for each of them.
2318 The usual definition accepts all pseudo regs; the other rejects
2319 them unless they have been allocated suitable hard regs.
2320 The symbol REG_OK_STRICT causes the latter definition to be used. */
2321
2322 #ifndef REG_OK_STRICT
2323
2324 /* Nonzero if X is a hard reg that can be used as a base reg
2325 or if it is a pseudo reg. */
2326 #define REG_OK_FOR_BASE_P(X) \
2327 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2328
2329 /* Nonzero if X is a hard reg that can be used as an index
2330 or if it is a pseudo reg. */
2331 #define REG_OK_FOR_INDEX_P(X) \
2332 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2333 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2334
2335 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2336 or if X is a pseudo reg. */
2337 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2338 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2339 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2340
2341 #else
2342
2343 /* Nonzero if X is a hard reg that can be used as a base reg. */
2344 #define REG_OK_FOR_BASE_P(X) \
2345 REGNO_OK_FOR_BASE_P (REGNO (X))
2346
2347 /* Nonzero if X is a hard reg that can be used as an index. */
2348 #define REG_OK_FOR_INDEX_P(X) \
2349 REGNO_OK_FOR_INDEX_P (REGNO (X))
2350
2351 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2352 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2353 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2354
2355 #endif
2356
2357 /* The 'Q' constraint is a pc relative load operand. */
2358 #define EXTRA_CONSTRAINT_Q(OP) \
2359 (GET_CODE (OP) == MEM \
2360 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2361 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2362 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2363 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2364 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2365
2366 /* Extra address constraints. */
2367 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2368
2369 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2370 operand is not SCRATCH (i.e. REG) then R0 is probably being
2371 used, hence mova is being used, hence do not select this pattern */
2372 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2373 #define EXTRA_CONSTRAINT_B(OP, STR) \
2374 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2375 : 0)
2376
2377 /* The `Css' constraint is a signed 16-bit constant, literal or symbolic. */
2378 #define EXTRA_CONSTRAINT_Css(OP) \
2379 (GET_CODE (OP) == CONST \
2380 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2381 && (GET_MODE (XEXP ((OP), 0)) == DImode \
2382 || GET_MODE (XEXP ((OP), 0)) == SImode) \
2383 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2384 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2385 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2386 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2387 && (MOVI_SHORI_BASE_OPERAND_P \
2388 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2389 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2390 1)) == CONST_INT)))
2391
2392 /* The `Csu' constraint is an unsigned 16-bit constant, literal or symbolic. */
2393 #define EXTRA_CONSTRAINT_Csu(OP) \
2394 (GET_CODE (OP) == CONST \
2395 && GET_CODE (XEXP ((OP), 0)) == ZERO_EXTEND \
2396 && (GET_MODE (XEXP ((OP), 0)) == DImode \
2397 || GET_MODE (XEXP ((OP), 0)) == SImode) \
2398 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2399 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2400 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2401 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2402 && (MOVI_SHORI_BASE_OPERAND_P \
2403 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2404 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2405 1)) == CONST_INT)))
2406
2407 /* Check whether OP is a datalabel unspec. */
2408 #define DATALABEL_REF_NO_CONST_P(OP) \
2409 (GET_CODE (OP) == UNSPEC \
2410 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2411 && XVECLEN ((OP), 0) == 1 \
2412 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2413
2414 #define GOT_ENTRY_P(OP) \
2415 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2416 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2417
2418 #define GOTPLT_ENTRY_P(OP) \
2419 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2420 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2421
2422 #define UNSPEC_GOTOFF_P(OP) \
2423 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2424
2425 #define GOTOFF_P(OP) \
2426 (GET_CODE (OP) == CONST \
2427 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2428 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2429 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2430 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2431
2432 #define PIC_ADDR_P(OP) \
2433 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2434 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2435
2436 #define PIC_OFFSET_P(OP) \
2437 (PIC_ADDR_P (OP) \
2438 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2439 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2440
2441 #define PIC_DIRECT_ADDR_P(OP) \
2442 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2443
2444 #define NON_PIC_REFERENCE_P(OP) \
2445 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2446 || (GET_CODE (OP) == CONST \
2447 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2448 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2449 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2450 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2451 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2452 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2453 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2454 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2455
2456 #define PIC_REFERENCE_P(OP) \
2457 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2458 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2459
2460 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2461 (flag_pic \
2462 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2463 || PIC_OFFSET_P (OP)) \
2464 : NON_PIC_REFERENCE_P (OP))
2465
2466 /* The `Csy' constraint is a label or a symbol. */
2467 #define EXTRA_CONSTRAINT_Csy(OP) \
2468 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2469
2470 /* A zero in any shape or form. */
2471 #define EXTRA_CONSTRAINT_Z(OP) \
2472 ((OP) == CONST0_RTX (GET_MODE (OP)))
2473
2474 /* Any vector constant we can handle. */
2475 #define EXTRA_CONSTRAINT_W(OP) \
2476 (GET_CODE (OP) == CONST_VECTOR \
2477 && (sh_rep_vec ((OP), VOIDmode) \
2478 || (HOST_BITS_PER_WIDE_INT >= 64 \
2479 ? sh_const_vec ((OP), VOIDmode) \
2480 : sh_1el_vec ((OP), VOIDmode))))
2481
2482 /* A non-explicit constant that can be loaded directly into a general purpose
2483 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2484 #define EXTRA_CONSTRAINT_Cpg(OP) \
2485 (CONSTANT_P (OP) \
2486 && GET_CODE (OP) != CONST_INT \
2487 && GET_CODE (OP) != CONST_DOUBLE \
2488 && (!flag_pic \
2489 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2490 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2491 && GET_CODE (OP) != LABEL_REF)))
2492 #define EXTRA_CONSTRAINT_C(OP, STR) \
2493 ((STR)[1] == 's' && (STR)[2] == 's' ? EXTRA_CONSTRAINT_Css (OP) \
2494 : (STR)[1] == 's' && (STR)[2] == 'u' ? EXTRA_CONSTRAINT_Csu (OP) \
2495 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2496 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2497 : 0)
2498
2499 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2500 #define EXTRA_CONSTRAINT_Sr0(OP) \
2501 (memory_operand((OP), GET_MODE (OP)) \
2502 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2503 #define EXTRA_CONSTRAINT_Sua(OP) \
2504 (memory_operand((OP), GET_MODE (OP)) \
2505 && GET_CODE (XEXP (OP, 0)) != PLUS)
2506 #define EXTRA_CONSTRAINT_S(OP, STR) \
2507 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2508 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2509 : 0)
2510
2511 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2512 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2513 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2514 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2515 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2516 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2517 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2518 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2519 : 0)
2520 \f
2521 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2522 that is a valid memory address for an instruction.
2523 The MODE argument is the machine mode for the MEM expression
2524 that wants to use this address. */
2525
2526 #define MODE_DISP_OK_4(X,MODE) \
2527 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2528 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2529
2530 #define MODE_DISP_OK_8(X,MODE) \
2531 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2532 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2533
2534 #undef MODE_DISP_OK_4
2535 #define MODE_DISP_OK_4(X,MODE) \
2536 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2537 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2538 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2539 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2540
2541 #undef MODE_DISP_OK_8
2542 #define MODE_DISP_OK_8(X,MODE) \
2543 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2544 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2545 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2546 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2547
2548 #define BASE_REGISTER_RTX_P(X) \
2549 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2550 || (GET_CODE (X) == SUBREG \
2551 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2552 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2553 && GET_CODE (SUBREG_REG (X)) == REG \
2554 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2555
2556 /* Since this must be r0, which is a single register class, we must check
2557 SUBREGs more carefully, to be sure that we don't accept one that extends
2558 outside the class. */
2559 #define INDEX_REGISTER_RTX_P(X) \
2560 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2561 || (GET_CODE (X) == SUBREG \
2562 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2563 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2564 && GET_CODE (SUBREG_REG (X)) == REG \
2565 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2566
2567 /* Jump to LABEL if X is a valid address RTX. This must also take
2568 REG_OK_STRICT into account when deciding about valid registers, but it uses
2569 the above macros so we are in luck.
2570
2571 Allow REG
2572 REG+disp
2573 REG+r0
2574 REG++
2575 --REG */
2576
2577 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2578 into the FRx registers. We implement this by setting the maximum offset
2579 to zero when the value is SFmode. This also restricts loading of SFmode
2580 values into the integer registers, but that can't be helped. */
2581
2582 /* The SH allows a displacement in a QI or HI amode, but only when the
2583 other operand is R0. GCC doesn't handle this very well, so we forgo
2584 all of that.
2585
2586 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2587 DI can be any number 0..60. */
2588
2589 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2590 do { \
2591 if (GET_CODE (OP) == CONST_INT) \
2592 { \
2593 if (TARGET_SHMEDIA) \
2594 { \
2595 int MODE_SIZE; \
2596 /* Check if this the address of an unaligned load / store. */\
2597 if ((MODE) == VOIDmode) \
2598 { \
2599 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2600 goto LABEL; \
2601 break; \
2602 } \
2603 MODE_SIZE = GET_MODE_SIZE (MODE); \
2604 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2605 && INTVAL (OP) >= -512 * MODE_SIZE \
2606 && INTVAL (OP) < 512 * MODE_SIZE) \
2607 goto LABEL; \
2608 else \
2609 break; \
2610 } \
2611 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2612 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2613 } \
2614 } while(0)
2615
2616 #define ALLOW_INDEXED_ADDRESS \
2617 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2618
2619 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2620 { \
2621 if (BASE_REGISTER_RTX_P (X)) \
2622 goto LABEL; \
2623 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2624 && ! TARGET_SHMEDIA \
2625 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2626 goto LABEL; \
2627 else if (GET_CODE (X) == PLUS \
2628 && ((MODE) != PSImode || reload_completed)) \
2629 { \
2630 rtx xop0 = XEXP ((X), 0); \
2631 rtx xop1 = XEXP ((X), 1); \
2632 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2633 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2634 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2635 || ((xop0 == stack_pointer_rtx \
2636 || xop0 == hard_frame_pointer_rtx) \
2637 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2638 || ((xop1 == stack_pointer_rtx \
2639 || xop1 == hard_frame_pointer_rtx) \
2640 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2641 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2642 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2643 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2644 && TARGET_FMOVD && MODE == DFmode))) \
2645 { \
2646 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2647 goto LABEL; \
2648 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2649 goto LABEL; \
2650 } \
2651 } \
2652 }
2653 \f
2654 /* Try machine-dependent ways of modifying an illegitimate address
2655 to be legitimate. If we find one, return the new, valid address.
2656 This macro is used in only one place: `memory_address' in explow.c.
2657
2658 OLDX is the address as it was before break_out_memory_refs was called.
2659 In some cases it is useful to look at this to decide what needs to be done.
2660
2661 MODE and WIN are passed so that this macro can use
2662 GO_IF_LEGITIMATE_ADDRESS.
2663
2664 It is always safe for this macro to do nothing. It exists to recognize
2665 opportunities to optimize the output.
2666
2667 For the SH, if X is almost suitable for indexing, but the offset is
2668 out of range, convert it into a normal form so that cse has a chance
2669 of reducing the number of address registers used. */
2670
2671 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2672 { \
2673 if (flag_pic) \
2674 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2675 if (GET_CODE (X) == PLUS \
2676 && (GET_MODE_SIZE (MODE) == 4 \
2677 || GET_MODE_SIZE (MODE) == 8) \
2678 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2679 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2680 && ! TARGET_SHMEDIA \
2681 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2682 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2683 { \
2684 rtx index_rtx = XEXP ((X), 1); \
2685 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2686 rtx sum; \
2687 \
2688 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2689 /* On rare occasions, we might get an unaligned pointer \
2690 that is indexed in a way to give an aligned address. \
2691 Therefore, keep the lower two bits in offset_base. */ \
2692 /* Instead of offset_base 128..131 use 124..127, so that \
2693 simple add suffices. */ \
2694 if (offset > 127) \
2695 { \
2696 offset_base = ((offset + 4) & ~60) - 4; \
2697 } \
2698 else \
2699 offset_base = offset & ~60; \
2700 /* Sometimes the normal form does not suit DImode. We \
2701 could avoid that by using smaller ranges, but that \
2702 would give less optimized code when SImode is \
2703 prevalent. */ \
2704 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2705 { \
2706 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2707 GEN_INT (offset_base), NULL_RTX, 0, \
2708 OPTAB_LIB_WIDEN); \
2709 \
2710 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2711 goto WIN; \
2712 } \
2713 } \
2714 }
2715
2716 /* A C compound statement that attempts to replace X, which is an address
2717 that needs reloading, with a valid memory address for an operand of
2718 mode MODE. WIN is a C statement label elsewhere in the code.
2719
2720 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2721 of the address. That will allow inheritance of the address reloads. */
2722
2723 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2724 { \
2725 if (GET_CODE (X) == PLUS \
2726 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2727 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2728 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2729 && ! TARGET_SHMEDIA \
2730 && ! (TARGET_SH4 && (MODE) == DFmode) \
2731 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2732 && (ALLOW_INDEXED_ADDRESS \
2733 || XEXP ((X), 0) == stack_pointer_rtx \
2734 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2735 { \
2736 rtx index_rtx = XEXP (X, 1); \
2737 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2738 rtx sum; \
2739 \
2740 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2741 { \
2742 push_reload (X, NULL_RTX, &X, NULL, \
2743 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2744 (TYPE)); \
2745 goto WIN; \
2746 } \
2747 if (TARGET_SH2E && MODE == SFmode) \
2748 { \
2749 X = copy_rtx (X); \
2750 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2751 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2752 (TYPE)); \
2753 goto WIN; \
2754 } \
2755 /* Instead of offset_base 128..131 use 124..127, so that \
2756 simple add suffices. */ \
2757 if (offset > 127) \
2758 { \
2759 offset_base = ((offset + 4) & ~60) - 4; \
2760 } \
2761 else \
2762 offset_base = offset & ~60; \
2763 /* Sometimes the normal form does not suit DImode. We \
2764 could avoid that by using smaller ranges, but that \
2765 would give less optimized code when SImode is \
2766 prevalent. */ \
2767 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2768 { \
2769 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2770 GEN_INT (offset_base)); \
2771 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2772 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2773 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2774 (TYPE)); \
2775 goto WIN; \
2776 } \
2777 } \
2778 /* We must re-recognize what we created before. */ \
2779 else if (GET_CODE (X) == PLUS \
2780 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2781 && GET_CODE (XEXP (X, 0)) == PLUS \
2782 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2783 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2784 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2785 && ! TARGET_SHMEDIA \
2786 && ! (TARGET_SH2E && MODE == SFmode)) \
2787 { \
2788 /* Because this address is so complex, we know it must have \
2789 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2790 it is already unshared, and needs no further unsharing. */ \
2791 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2792 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2793 goto WIN; \
2794 } \
2795 }
2796
2797 /* Go to LABEL if ADDR (a legitimate address expression)
2798 has an effect that depends on the machine mode it is used for.
2799
2800 ??? Strictly speaking, we should also include all indexed addressing,
2801 because the index scale factor is the length of the operand.
2802 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2803 high if we did that. So we rely on reload to fix things up.
2804
2805 Auto-increment addressing is now treated in recog.c. */
2806
2807 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2808 \f
2809 /* Specify the machine mode that this machine uses
2810 for the index in the tablejump instruction. */
2811 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2812
2813 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2814 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2815 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2816 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2817 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2818 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2819 : SImode)
2820
2821 /* Define as C expression which evaluates to nonzero if the tablejump
2822 instruction expects the table to contain offsets from the address of the
2823 table.
2824 Do not define this if the table should contain absolute addresses. */
2825 #define CASE_VECTOR_PC_RELATIVE 1
2826
2827 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2828 #define FLOAT_TYPE_SIZE 32
2829
2830 /* Since the SH2e has only `float' support, it is desirable to make all
2831 floating point types equivalent to `float'. */
2832 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2833
2834 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH4_SINGLE_ONLY__)
2835 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2836 #else
2837 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2838 #endif
2839
2840 /* 'char' is signed by default. */
2841 #define DEFAULT_SIGNED_CHAR 1
2842
2843 /* The type of size_t unsigned int. */
2844 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2845
2846 #undef PTRDIFF_TYPE
2847 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2848
2849 #define WCHAR_TYPE "short unsigned int"
2850 #define WCHAR_TYPE_SIZE 16
2851
2852 #define SH_ELF_WCHAR_TYPE "long int"
2853
2854 /* Max number of bytes we can move from memory to memory
2855 in one reasonably fast instruction. */
2856 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2857
2858 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2859 MOVE_MAX is not a compile-time constant. */
2860 #define MAX_MOVE_MAX 8
2861
2862 /* Max number of bytes we want move_by_pieces to be able to copy
2863 efficiently. */
2864 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2865
2866 /* Define if operations between registers always perform the operation
2867 on the full register even if a narrower mode is specified. */
2868 #define WORD_REGISTER_OPERATIONS
2869
2870 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2871 will either zero-extend or sign-extend. The value of this macro should
2872 be the code that says which one of the two operations is implicitly
2873 done, UNKNOWN if none. */
2874 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2875 /* FP registers can load SImode values, but don't implicitly sign-extend
2876 them to DImode. */
2877 #define LOAD_EXTEND_OP(MODE) \
2878 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2879 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2880
2881 /* Define if loading short immediate values into registers sign extends. */
2882 #define SHORT_IMMEDIATES_SIGN_EXTEND
2883
2884 /* Nonzero if access to memory by bytes is no faster than for words. */
2885 #define SLOW_BYTE_ACCESS 1
2886
2887 /* Immediate shift counts are truncated by the output routines (or was it
2888 the assembler?). Shift counts in a register are truncated by SH. Note
2889 that the native compiler puts too large (> 32) immediate shift counts
2890 into a register and shifts by the register, letting the SH decide what
2891 to do instead of doing that itself. */
2892 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2893 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2894 expects - the sign bit is significant - so it appears that we need to
2895 leave this zero for correct SH3 code. */
2896 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2897
2898 /* All integers have the same format so truncation is easy. */
2899 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2900 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2901 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2902
2903 /* Define this if addresses of constant functions
2904 shouldn't be put through pseudo regs where they can be cse'd.
2905 Desirable on machines where ordinary constants are expensive
2906 but a CALL with constant address is cheap. */
2907 /*#define NO_FUNCTION_CSE 1*/
2908
2909 /* The machine modes of pointers and functions. */
2910 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2911 #define FUNCTION_MODE Pmode
2912
2913 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2914 are actually function calls with some special constraints on arguments
2915 and register usage.
2916
2917 These macros tell reorg that the references to arguments and
2918 register clobbers for insns of type sfunc do not appear to happen
2919 until after the millicode call. This allows reorg to put insns
2920 which set the argument registers into the delay slot of the millicode
2921 call -- thus they act more like traditional CALL_INSNs.
2922
2923 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2924 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2925 in particular. */
2926
2927 #define INSN_SETS_ARE_DELAYED(X) \
2928 ((GET_CODE (X) == INSN \
2929 && GET_CODE (PATTERN (X)) != SEQUENCE \
2930 && GET_CODE (PATTERN (X)) != USE \
2931 && GET_CODE (PATTERN (X)) != CLOBBER \
2932 && get_attr_is_sfunc (X)))
2933
2934 #define INSN_REFERENCES_ARE_DELAYED(X) \
2935 ((GET_CODE (X) == INSN \
2936 && GET_CODE (PATTERN (X)) != SEQUENCE \
2937 && GET_CODE (PATTERN (X)) != USE \
2938 && GET_CODE (PATTERN (X)) != CLOBBER \
2939 && get_attr_is_sfunc (X)))
2940
2941 \f
2942 /* Position Independent Code. */
2943
2944 /* We can't directly access anything that contains a symbol,
2945 nor can we indirect via the constant pool. */
2946 #define LEGITIMATE_PIC_OPERAND_P(X) \
2947 ((! nonpic_symbol_mentioned_p (X) \
2948 && (GET_CODE (X) != SYMBOL_REF \
2949 || ! CONSTANT_POOL_ADDRESS_P (X) \
2950 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2951 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2952
2953 #define SYMBOLIC_CONST_P(X) \
2954 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2955 && nonpic_symbol_mentioned_p (X))
2956 \f
2957 /* Compute extra cost of moving data between one register class
2958 and another. */
2959
2960 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2961 uses this information. Hence, the general register <-> floating point
2962 register information here is not used for SFmode. */
2963
2964 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2965 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2966 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2967
2968 #define REGCLASS_HAS_FP_REG(CLASS) \
2969 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2970 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2971
2972 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2973 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2974
2975 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2976 would be so that people with slow memory systems could generate
2977 different code that does fewer memory accesses. */
2978
2979 /* A C expression for the cost of a branch instruction. A value of 1
2980 is the default; other values are interpreted relative to that.
2981 The SH1 does not have delay slots, hence we get a pipeline stall
2982 at every branch. The SH4 is superscalar, so the single delay slot
2983 is not sufficient to keep both pipelines filled. */
2984 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2985 \f
2986 /* Assembler output control. */
2987
2988 /* A C string constant describing how to begin a comment in the target
2989 assembler language. The compiler assumes that the comment will end at
2990 the end of the line. */
2991 #define ASM_COMMENT_START "!"
2992
2993 #define ASM_APP_ON ""
2994 #define ASM_APP_OFF ""
2995 #define FILE_ASM_OP "\t.file\n"
2996 #define SET_ASM_OP "\t.set\t"
2997
2998 /* How to change between sections. */
2999
3000 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
3001 #define DATA_SECTION_ASM_OP "\t.data"
3002
3003 #if defined CRT_BEGIN || defined CRT_END
3004 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
3005 # undef TEXT_SECTION_ASM_OP
3006 # if __SHMEDIA__ == 1 && __SH5__ == 32
3007 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
3008 # else
3009 # define TEXT_SECTION_ASM_OP "\t.text"
3010 # endif
3011 #endif
3012
3013
3014 /* If defined, a C expression whose value is a string containing the
3015 assembler operation to identify the following data as
3016 uninitialized global data. If not defined, and neither
3017 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
3018 uninitialized global data will be output in the data section if
3019 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
3020 used. */
3021 #ifndef BSS_SECTION_ASM_OP
3022 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
3023 #endif
3024
3025 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
3026 separate, explicit argument. If you define this macro, it is used
3027 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
3028 handling the required alignment of the variable. The alignment is
3029 specified as the number of bits.
3030
3031 Try to use function `asm_output_aligned_bss' defined in file
3032 `varasm.c' when defining this macro. */
3033 #ifndef ASM_OUTPUT_ALIGNED_BSS
3034 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3035 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
3036 #endif
3037
3038 /* Define this so that jump tables go in same section as the current function,
3039 which could be text or it could be a user defined section. */
3040 #define JUMP_TABLES_IN_TEXT_SECTION 1
3041
3042 #undef DO_GLOBAL_CTORS_BODY
3043 #define DO_GLOBAL_CTORS_BODY \
3044 { \
3045 typedef (*pfunc)(); \
3046 extern pfunc __ctors[]; \
3047 extern pfunc __ctors_end[]; \
3048 pfunc *p; \
3049 for (p = __ctors_end; p > __ctors; ) \
3050 { \
3051 (*--p)(); \
3052 } \
3053 }
3054
3055 #undef DO_GLOBAL_DTORS_BODY
3056 #define DO_GLOBAL_DTORS_BODY \
3057 { \
3058 typedef (*pfunc)(); \
3059 extern pfunc __dtors[]; \
3060 extern pfunc __dtors_end[]; \
3061 pfunc *p; \
3062 for (p = __dtors; p < __dtors_end; p++) \
3063 { \
3064 (*p)(); \
3065 } \
3066 }
3067
3068 #define ASM_OUTPUT_REG_PUSH(file, v) \
3069 { \
3070 if (TARGET_SHMEDIA) \
3071 { \
3072 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
3073 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
3074 } \
3075 else \
3076 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
3077 }
3078
3079 #define ASM_OUTPUT_REG_POP(file, v) \
3080 { \
3081 if (TARGET_SHMEDIA) \
3082 { \
3083 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
3084 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
3085 } \
3086 else \
3087 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
3088 }
3089
3090 /* DBX register number for a given compiler register number. */
3091 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3092 to match gdb. */
3093 /* svr4.h undefines this macro, yet we really want to use the same numbers
3094 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3095 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3096 register exists, so we should return -1 for invalid register numbers. */
3097 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3098
3099 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3100 used to use the encodings 245..260, but that doesn't make sense:
3101 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3102 the FP registers stay the same when switching between compact and media
3103 mode. Hence, we also need to use the same dwarf frame columns.
3104 Likewise, we need to support unwind information for SHmedia registers
3105 even in compact code. */
3106 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3107 (IN_RANGE ((REGNO), \
3108 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3109 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3110 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3111 : ((int) (REGNO) >= FIRST_FP_REG \
3112 && ((int) (REGNO) \
3113 <= (FIRST_FP_REG + \
3114 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3115 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3116 + (TARGET_SH5 ? 77 : 25)) \
3117 : XD_REGISTER_P (REGNO) \
3118 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3119 : TARGET_REGISTER_P (REGNO) \
3120 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3121 : (REGNO) == PR_REG \
3122 ? (TARGET_SH5 ? 18 : 17) \
3123 : (REGNO) == PR_MEDIA_REG \
3124 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3125 : (REGNO) == T_REG \
3126 ? (TARGET_SH5 ? 242 : 18) \
3127 : (REGNO) == GBR_REG \
3128 ? (TARGET_SH5 ? 238 : 19) \
3129 : (REGNO) == MACH_REG \
3130 ? (TARGET_SH5 ? 239 : 20) \
3131 : (REGNO) == MACL_REG \
3132 ? (TARGET_SH5 ? 240 : 21) \
3133 : (REGNO) == FPUL_REG \
3134 ? (TARGET_SH5 ? 244 : 23) \
3135 : (unsigned) -1)
3136
3137 /* This is how to output a reference to a symbol_ref. On SH5,
3138 references to non-code symbols must be preceded by `datalabel'. */
3139 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3140 do \
3141 { \
3142 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3143 fputs ("datalabel ", (FILE)); \
3144 assemble_name ((FILE), XSTR ((SYM), 0)); \
3145 } \
3146 while (0)
3147
3148 /* This is how to output an assembler line
3149 that says to advance the location counter
3150 to a multiple of 2**LOG bytes. */
3151
3152 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3153 if ((LOG) != 0) \
3154 fprintf ((FILE), "\t.align %d\n", (LOG))
3155
3156 /* Globalizing directive for a label. */
3157 #define GLOBAL_ASM_OP "\t.global\t"
3158
3159 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3160
3161 /* Output a relative address table. */
3162
3163 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3164 switch (GET_MODE (BODY)) \
3165 { \
3166 case SImode: \
3167 if (TARGET_SH5) \
3168 { \
3169 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3170 (VALUE), (REL)); \
3171 break; \
3172 } \
3173 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3174 break; \
3175 case HImode: \
3176 if (TARGET_SH5) \
3177 { \
3178 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3179 (VALUE), (REL)); \
3180 break; \
3181 } \
3182 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3183 break; \
3184 case QImode: \
3185 if (TARGET_SH5) \
3186 { \
3187 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3188 (VALUE), (REL)); \
3189 break; \
3190 } \
3191 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3192 break; \
3193 default: \
3194 break; \
3195 }
3196
3197 /* Output an absolute table element. */
3198
3199 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3200 if (! optimize || TARGET_BIGTABLE) \
3201 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3202 else \
3203 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3204
3205 \f
3206 /* A C statement to be executed just prior to the output of
3207 assembler code for INSN, to modify the extracted operands so
3208 they will be output differently.
3209
3210 Here the argument OPVEC is the vector containing the operands
3211 extracted from INSN, and NOPERANDS is the number of elements of
3212 the vector which contain meaningful data for this insn.
3213 The contents of this vector are what will be used to convert the insn
3214 template into assembler code, so you can change the assembler output
3215 by changing the contents of the vector. */
3216
3217 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3218 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3219
3220 /* Print operand X (an rtx) in assembler syntax to file FILE.
3221 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3222 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3223
3224 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3225
3226 /* Print a memory address as an operand to reference that memory location. */
3227
3228 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3229
3230 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3231 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3232 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3233
3234 /* Recognize machine-specific patterns that may appear within
3235 constants. Used for PIC-specific UNSPECs. */
3236 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3237 do \
3238 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3239 { \
3240 switch (XINT ((X), 1)) \
3241 { \
3242 case UNSPEC_DATALABEL: \
3243 fputs ("datalabel ", (STREAM)); \
3244 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3245 break; \
3246 case UNSPEC_PIC: \
3247 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3248 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3249 break; \
3250 case UNSPEC_GOT: \
3251 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3252 fputs ("@GOT", (STREAM)); \
3253 break; \
3254 case UNSPEC_GOTOFF: \
3255 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3256 fputs ("@GOTOFF", (STREAM)); \
3257 break; \
3258 case UNSPEC_PLT: \
3259 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3260 fputs ("@PLT", (STREAM)); \
3261 break; \
3262 case UNSPEC_GOTPLT: \
3263 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3264 fputs ("@GOTPLT", (STREAM)); \
3265 break; \
3266 case UNSPEC_DTPOFF: \
3267 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3268 fputs ("@DTPOFF", (STREAM)); \
3269 break; \
3270 case UNSPEC_GOTTPOFF: \
3271 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3272 fputs ("@GOTTPOFF", (STREAM)); \
3273 break; \
3274 case UNSPEC_TPOFF: \
3275 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3276 fputs ("@TPOFF", (STREAM)); \
3277 break; \
3278 case UNSPEC_CALLER: \
3279 { \
3280 char name[32]; \
3281 /* LPCS stands for Label for PIC Call Site. */ \
3282 ASM_GENERATE_INTERNAL_LABEL \
3283 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3284 assemble_name ((STREAM), name); \
3285 } \
3286 break; \
3287 default: \
3288 goto FAIL; \
3289 } \
3290 break; \
3291 } \
3292 else \
3293 goto FAIL; \
3294 while (0)
3295
3296 \f
3297 extern struct rtx_def *sh_compare_op0;
3298 extern struct rtx_def *sh_compare_op1;
3299
3300 /* Which processor to schedule for. The elements of the enumeration must
3301 match exactly the cpu attribute in the sh.md file. */
3302
3303 enum processor_type {
3304 PROCESSOR_SH1,
3305 PROCESSOR_SH2,
3306 PROCESSOR_SH2E,
3307 PROCESSOR_SH2A,
3308 PROCESSOR_SH3,
3309 PROCESSOR_SH3E,
3310 PROCESSOR_SH4,
3311 PROCESSOR_SH4A,
3312 PROCESSOR_SH5
3313 };
3314
3315 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3316 extern enum processor_type sh_cpu;
3317
3318 extern int optimize; /* needed for gen_casesi. */
3319
3320 enum mdep_reorg_phase_e
3321 {
3322 SH_BEFORE_MDEP_REORG,
3323 SH_INSERT_USES_LABELS,
3324 SH_SHORTEN_BRANCHES0,
3325 SH_FIXUP_PCLOAD,
3326 SH_SHORTEN_BRANCHES1,
3327 SH_AFTER_MDEP_REORG
3328 };
3329
3330 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3331
3332 /* Handle Renesas compiler's pragmas. */
3333 #define REGISTER_TARGET_PRAGMAS() do { \
3334 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3335 c_register_pragma (0, "trapa", sh_pr_trapa); \
3336 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3337 } while (0)
3338
3339 extern tree sh_deferred_function_attributes;
3340 extern tree *sh_deferred_function_attributes_tail;
3341
3342 /* Set when processing a function with interrupt attribute. */
3343
3344 extern int current_function_interrupt;
3345
3346 \f
3347 /* Instructions with unfilled delay slots take up an
3348 extra two bytes for the nop in the delay slot.
3349 sh-dsp parallel processing insns are four bytes long. */
3350
3351 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3352 (LENGTH) += sh_insn_length_adjustment (X);
3353 \f
3354 /* Define this macro if it is advisable to hold scalars in registers
3355 in a wider mode than that declared by the program. In such cases,
3356 the value is constrained to be within the bounds of the declared
3357 type, but kept valid in the wider mode. The signedness of the
3358 extension may differ from that of the type.
3359
3360 Leaving the unsignedp unchanged gives better code than always setting it
3361 to 0. This is despite the fact that we have only signed char and short
3362 load instructions. */
3363 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3364 if (GET_MODE_CLASS (MODE) == MODE_INT \
3365 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3366 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3367 (MODE) = (TARGET_SH1 ? SImode \
3368 : TARGET_SHMEDIA32 ? SImode : DImode);
3369
3370 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3371
3372 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3373
3374 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3375 and popping arguments. However, we do have push/pop instructions, and
3376 rather limited offsets (4 bits) in load/store instructions, so it isn't
3377 clear if this would give better code. If implemented, should check for
3378 compatibility problems. */
3379
3380 #define SH_DYNAMIC_SHIFT_COST \
3381 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3382
3383
3384 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3385
3386 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3387
3388 #define ACTUAL_NORMAL_MODE(ENTITY) \
3389 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3390
3391 #define NORMAL_MODE(ENTITY) \
3392 (sh_cfun_interrupt_handler_p () \
3393 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3394 : ACTUAL_NORMAL_MODE (ENTITY))
3395
3396 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3397
3398 #define MODE_EXIT(ENTITY) \
3399 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3400
3401 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3402 && (REGNO) == FPSCR_REG)
3403
3404 #define MODE_NEEDED(ENTITY, INSN) \
3405 (recog_memoized (INSN) >= 0 \
3406 ? get_attr_fp_mode (INSN) \
3407 : FP_MODE_NONE)
3408
3409 #define MODE_AFTER(MODE, INSN) \
3410 (TARGET_HITACHI \
3411 && recog_memoized (INSN) >= 0 \
3412 && get_attr_fp_set (INSN) != FP_SET_NONE \
3413 ? (int) get_attr_fp_set (INSN) \
3414 : (MODE))
3415
3416 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3417 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3418
3419 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3420 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3421
3422 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3423 sh_can_redirect_branch ((INSN), (SEQ))
3424
3425 #define DWARF_FRAME_RETURN_COLUMN \
3426 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3427
3428 #define EH_RETURN_DATA_REGNO(N) \
3429 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3430
3431 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3432 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3433
3434 /* We have to distinguish between code and data, so that we apply
3435 datalabel where and only where appropriate. Use sdataN for data. */
3436 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3437 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3438 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3439 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3440
3441 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3442 indirect are handled automatically. */
3443 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3444 do { \
3445 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3446 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3447 { \
3448 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3449 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3450 if (0) goto DONE; \
3451 } \
3452 } while (0)
3453
3454 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3455 /* SH constant pool breaks the devices in crtstuff.c to control section
3456 in where code resides. We have to write it as asm code. */
3457 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3458 asm (SECTION_OP "\n\
3459 mov.l 1f,r1\n\
3460 mova 2f,r0\n\
3461 braf r1\n\
3462 lds r0,pr\n\
3463 0: .p2align 2\n\
3464 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3465 2:\n" TEXT_SECTION_ASM_OP);
3466 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3467
3468 /* FIXME: middle-end support for highpart optimizations is missing. */
3469 #define high_life_started reload_in_progress
3470
3471 #endif /* ! GCC_SH_H */
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