libjava/sysdep/sparc/locks.h

   1 // locks.h - Thread synchronization primitives. Sparc implementation.
   2
   3 /* Copyright (C) 2002  Free Software Foundation
   4
   5    This file is part of libgcj.
   6
   7 This software is copyrighted work licensed under the terms of the
   8 Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
   9 details.  */
  10
  11 #ifndef __SYSDEP_LOCKS_H__
  12 #define __SYSDEP_LOCKS_H__
  13
  14 typedef size_t obj_addr_t;      /* Integer type big enough for object   */
  15                                 /* address.                             */
  16
  17 #ifdef __arch64__
  18 /* Sparc64 implementation, use cas instruction.  */
  19 inline static bool
  20 compare_and_swap(volatile obj_addr_t *addr,
  21                  obj_addr_t old,
  22                  obj_addr_t new_val)
  23 {
  24   __asm__ __volatile__("casx [%2], %3, %0\n\t"
  25                        "membar #StoreLoad | #StoreStore"
  26                        : "=&r" (new_val)
  27                        : "0" (new_val), "r" (addr), "r" (old)
  28                        : "memory");
  29
  30   return (new_val == old) ? true : false;
  31 }
  32
  33 inline static void
  34 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
  35 {
  36   __asm__ __volatile__("membar #StoreStore | #LoadStore" : : : "memory");
  37   *(addr) = new_val;
  38 }
  39
  40 inline static bool
  41 compare_and_swap_release(volatile obj_addr_t *addr,
  42                                                      obj_addr_t old,
  43                                                      obj_addr_t new_val)
  44 {
  45   return compare_and_swap(addr, old, new_val);
  46 }
  47 #else
  48 /* Sparc32 implementation, use a spinlock.  */
  49 static unsigned char __cas_lock = 0;
  50
  51 inline static void
  52 __cas_start_atomic(void)
  53 {
  54   unsigned int tmp;
  55   __asm__ __volatile__(
  56 "1:     ldstub  [%1], %0\n"
  57 "       orcc    %0, 0x0, %%g0\n"
  58 "       be      3f\n"
  59 "        nop\n"
  60 "2:     ldub    [%1], %0\n"
  61 "       orcc    %0, 0x0, %%g0\n"
  62 "       bne     2b\n"
  63 "        nop\n"
  64 "3:"    : "=&r" (tmp)
  65         : "r" (&__cas_lock)
  66         : "memory", "cc");
  67 }
  68
  69 inline static void
  70 __cas_end_atomic(void)
  71 {
  72   __asm__ __volatile__(
  73   "stb %%g0, [%0]"
  74   : /* no outputs */
  75   : "r" (&__cas_lock)
  76   : "memory");
  77 }
  78
  79 inline static bool
  80 compare_and_swap(volatile obj_addr_t *addr,
  81                  obj_addr_t old,
  82                  obj_addr_t new_val)
  83 {
  84   bool ret;
  85
  86   __cas_start_atomic ();
  87   if (*addr != old)
  88     {
  89       ret = false;
  90     }
  91   else
  92     {
  93       *addr = new_val;
  94       ret = true;
  95     }
  96   __cas_end_atomic ();
  97
  98   return ret;
  99 }
 100
 101 inline static void
 102 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
 103 {
 104   /* Technically stbar would be needed here but no sparc32
 105      system actually requires it.  Also the stbar would mean
 106      this code would not work on sparcv7 chips.  */
 107   __asm__ __volatile__("" : : : "memory");
 108   *(addr) = new_val;
 109 }
 110
 111 inline static bool
 112 compare_and_swap_release(volatile obj_addr_t *addr,
 113                                                      obj_addr_t old,
 114                                                      obj_addr_t new_val)
 115 {
 116   return compare_and_swap(addr, old, new_val);
 117 }
 118 #endif /* __arch64__ */
 119
 120 #endif /* ! __SYSDEP_LOCKS_H__ */