2003-12-26 Guilhem Lavaux <guilhem@kaffe.org>
[official-gcc.git] / libjava / sysdep / mips / locks.h
blob80509cadbbd5b859ec1c27926bdfce726f3b9202
1 // locks.h - Thread synchronization primitives. MIPS implementation.
3 /* Copyright (C) 2003 Free Software Foundation
5 This file is part of libgcj.
7 This software is copyrighted work licensed under the terms of the
8 Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
9 details. */
11 #ifndef __SYSDEP_LOCKS_H__
12 #define __SYSDEP_LOCKS_H__
14 /* Integer type big enough for object address. */
15 typedef unsigned obj_addr_t __attribute__((__mode__(__pointer__)));
18 // Atomically replace *addr by new_val if it was initially equal to old.
19 // Return true if the comparison succeeded.
20 // Assumed to have acquire semantics, i.e. later memory operations
21 // cannot execute before the compare_and_swap finishes.
22 inline static bool
23 compare_and_swap(volatile obj_addr_t *addr,
24 obj_addr_t old,
25 obj_addr_t new_val)
27 long result;
28 __asm__ __volatile__(".set\tpush\n\t"
29 ".set\tnoreorder\n\t"
30 ".set\tnomacro\n\t"
31 "1:\n\t"
32 #if _MIPS_SIM == _ABIO32
33 ".set\tmips2\n\t"
34 #endif
35 "ll\t%[result],0(%[addr])\n\t"
36 "bne\t%[result],%[old],2f\n\t"
37 "move\t%[result],$0\n\t" // delay slot
38 "move\t%[result],%[new_val]\n\t"
39 "sc\t%[result],0(%[addr])\n\t"
40 "beq\t%[result],$0,1b\n\t"
41 "nop\n\t" // delay slot
42 "2:\n\t"
43 ".set\tpop"
44 : [result] "=&r" (result)
45 : [addr] "r" (addr), [new_val] "r" (new_val), [old] "r"(old)
46 : "memory");
47 return (bool) result;
50 // Set *addr to new_val with release semantics, i.e. making sure
51 // that prior loads and stores complete before this
52 // assignment.
53 inline static void
54 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
56 __asm__ __volatile__(".set\tpush\n\t"
57 #if _MIPS_SIM == _ABIO32
58 ".set\tmips2\n\t"
59 #endif
60 "sync\n\t"
61 ".set\tpop" : : : "memory");
62 *(addr) = new_val;
65 // Compare_and_swap with release semantics instead of acquire semantics.
66 // On many architecture, the operation makes both guarantees, so the
67 // implementation can be the same.
68 inline static bool
69 compare_and_swap_release(volatile obj_addr_t *addr,
70 obj_addr_t old,
71 obj_addr_t new_val)
73 __asm__ __volatile__(".set\tpush\n\t"
74 #if _MIPS_SIM == _ABIO32
75 ".set\tmips2\n\t"
76 #endif
77 "sync\n\t"
78 ".set\tpop" : : : "memory");
79 return compare_and_swap(addr, old, new_val);
82 // Ensure that subsequent instructions do not execute on stale
83 // data that was loaded from memory before the barrier.
84 // On X86, the hardware ensures that reads are properly ordered.
85 inline static void
86 read_barrier()
88 __asm__ __volatile__(".set\tpush\n\t"
89 #if _MIPS_SIM == _ABIO32
90 ".set\tmips2\n\t"
91 #endif
92 "sync\n\t"
93 ".set\tpop" : : : "memory");
96 // Ensure that prior stores to memory are completed with respect to other
97 // processors.
98 inline static void
99 write_barrier()
101 __asm__ __volatile__(".set\tpush\n\t"
102 #if _MIPS_SIM == _ABIO32
103 ".set\tmips2\n\t"
104 #endif
105 "sync\n\t"
106 ".set\tpop" : : : "memory");
109 #endif // __SYSDEP_LOCKS_H__