gcc/config/rs6000/altivec.md

   1 ;; AltiVec patterns.
   2 ;; Copyright (C) 2002, 2003 Free Software Foundation, Inc.
   3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 2, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to the
  19 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  20 ;; MA 02111-1307, USA.
  21
  22 (define_constants
  23   [(UNSPEC_VSPLTISW     141)
  24    (UNSPEC_VSPLTISH     140)
  25    (UNSPEC_VSPLTISB     139)
  26    ])
  27
  28 ;; Generic LVX load instruction.
  29 (define_insn "altivec_lvx_4si"
  30   [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
  31         (match_operand:V4SI 1 "memory_operand" "m"))]
  32   "TARGET_ALTIVEC"
  33   "lvx %0,%y1"
  34   [(set_attr "type" "vecload")])
  35
  36 (define_insn "altivec_lvx_8hi"
  37   [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
  38         (match_operand:V8HI 1 "memory_operand" "m"))]
  39   "TARGET_ALTIVEC"
  40   "lvx %0,%y1"
  41   [(set_attr "type" "vecload")])
  42
  43 (define_insn "altivec_lvx_16qi"
  44   [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
  45         (match_operand:V16QI 1 "memory_operand" "m"))]
  46   "TARGET_ALTIVEC"
  47   "lvx %0,%y1"
  48   [(set_attr "type" "vecload")])
  49
  50 (define_insn "altivec_lvx_4sf"
  51   [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
  52         (match_operand:V4SF 1 "memory_operand" "m"))]
  53   "TARGET_ALTIVEC"
  54   "lvx %0,%y1"
  55   [(set_attr "type" "vecload")])
  56
  57 ;; Generic STVX store instruction.
  58 (define_insn "altivec_stvx_4si"
  59   [(set (match_operand:V4SI 0 "memory_operand" "=m")
  60         (match_operand:V4SI 1 "altivec_register_operand" "v"))]
  61   "TARGET_ALTIVEC"
  62   "stvx %1,%y0"
  63   [(set_attr "type" "vecstore")])
  64
  65 (define_insn "altivec_stvx_8hi"
  66   [(set (match_operand:V8HI 0 "memory_operand" "=m")
  67         (match_operand:V8HI 1 "altivec_register_operand" "v"))]
  68   "TARGET_ALTIVEC"
  69   "stvx %1,%y0"
  70   [(set_attr "type" "vecstore")])
  71
  72 (define_insn "altivec_stvx_16qi"
  73   [(set (match_operand:V16QI 0 "memory_operand" "=m")
  74         (match_operand:V16QI 1 "altivec_register_operand" "v"))]
  75   "TARGET_ALTIVEC"
  76   "stvx %1,%y0"
  77   [(set_attr "type" "vecstore")])
  78
  79 (define_insn "altivec_stvx_4sf"
  80   [(set (match_operand:V4SF 0 "memory_operand" "=m")
  81         (match_operand:V4SF 1 "altivec_register_operand" "v"))]
  82   "TARGET_ALTIVEC"
  83   "stvx %1,%y0"
  84   [(set_attr "type" "vecstore")])
  85
  86 ;; Vector move instructions.
  87 (define_expand "movv4si"
  88   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
  89         (match_operand:V4SI 1 "any_operand" ""))]
  90   "TARGET_ALTIVEC"
  91   "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
  92
  93 (define_insn "*movv4si_internal"
  94   [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
  95         (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r,W"))]
  96   "TARGET_ALTIVEC"
  97   "*
  98 {
  99   switch (which_alternative)
 100     {
 101     case 0: return \"stvx %1,%y0\";
 102     case 1: return \"lvx %0,%y1\";
 103     case 2: return \"vor %0,%1,%1\";
 104     case 3: return \"#\";
 105     case 4: return \"#\";
 106     case 5: return \"#\";
 107     case 6: return output_vec_const_move (operands);
 108     default: abort();
 109     }
 110 }"
 111   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 112
 113 (define_split
 114   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
 115         (match_operand:V4SI 1 "input_operand" ""))]
 116   "TARGET_ALTIVEC && reload_completed
 117    && gpr_or_gpr_p (operands[0], operands[1])"
 118   [(pc)]
 119 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 120
 121 (define_split
 122   [(set (match_operand:V4SI 0 "altivec_register_operand" "")
 123         (match_operand:V4SI 1 "easy_vector_constant_add_self" ""))]
 124   "TARGET_ALTIVEC && reload_completed"
 125   [(set (match_dup 0)
 126         (unspec:V4SI [(match_dup 3)] UNSPEC_VSPLTISW))
 127    (set (match_dup 0)
 128         (plus:V4SI (match_dup 0)
 129                    (match_dup 0)))]
 130   "
 131 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 132
 133 (define_expand "movv8hi"
 134   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 135         (match_operand:V8HI 1 "any_operand" ""))]
 136   "TARGET_ALTIVEC"
 137   "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
 138
 139 (define_insn "*movv8hi_internal1"
 140   [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 141         (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r,W"))]
 142   "TARGET_ALTIVEC"
 143   "*
 144 {
 145    switch (which_alternative)
 146      {
 147      case 0: return \"stvx %1,%y0\";
 148      case 1: return \"lvx %0,%y1\";
 149      case 2: return \"vor %0,%1,%1\";
 150      case 3: return \"#\";
 151      case 4: return \"#\";
 152      case 5: return \"#\";
 153      case 6: return output_vec_const_move (operands);
 154      default: abort ();
 155      }
 156 }"
 157   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 158
 159 (define_split
 160   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 161         (match_operand:V8HI 1 "input_operand" ""))]
 162   "TARGET_ALTIVEC && reload_completed
 163    && gpr_or_gpr_p (operands[0], operands[1])"
 164   [(pc)]
 165 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 166
 167 (define_split
 168   [(set (match_operand:V8HI 0 "altivec_register_operand" "")
 169         (match_operand:V8HI 1 "easy_vector_constant_add_self" ""))]
 170   "TARGET_ALTIVEC && reload_completed"
 171   [(set (match_dup 0)
 172         (unspec:V8HI [(match_dup 3)] UNSPEC_VSPLTISH))
 173    (set (match_dup 0)
 174         (plus:V8HI (match_dup 0)
 175                    (match_dup 0)))]
 176   "
 177 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 178
 179 (define_expand "movv16qi"
 180   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 181         (match_operand:V16QI 1 "any_operand" ""))]
 182   "TARGET_ALTIVEC"
 183   "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
 184
 185 (define_insn "*movv16qi_internal1"
 186   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 187         (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r,W"))]
 188   "TARGET_ALTIVEC"
 189   "*
 190 {
 191   switch (which_alternative)
 192     {
 193     case 0: return \"stvx %1,%y0\";
 194     case 1: return \"lvx %0,%y1\";
 195     case 2: return \"vor %0,%1,%1\";
 196     case 3: return \"#\";
 197     case 4: return \"#\";
 198     case 5: return \"#\";
 199     case 6: return output_vec_const_move (operands);
 200     default: abort ();
 201     }
 202 }"
 203   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 204
 205 (define_split
 206   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 207         (match_operand:V16QI 1 "input_operand" ""))]
 208   "TARGET_ALTIVEC && reload_completed
 209    && gpr_or_gpr_p (operands[0], operands[1])"
 210   [(pc)]
 211 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 212
 213 (define_split
 214   [(set (match_operand:V16QI 0 "altivec_register_operand" "")
 215         (match_operand:V16QI 1 "easy_vector_constant_add_self" ""))]
 216   "TARGET_ALTIVEC && reload_completed"
 217   [(set (match_dup 0)
 218         (unspec:V16QI [(match_dup 3)] UNSPEC_VSPLTISB))
 219    (set (match_dup 0)
 220         (plus:V16QI (match_dup 0)
 221                    (match_dup 0)))]
 222   "
 223 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 224
 225 (define_expand "movv4sf"
 226   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 227         (match_operand:V4SF 1 "any_operand" ""))]
 228   "TARGET_ALTIVEC"
 229   "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
 230
 231 (define_insn "*movv4sf_internal1"
 232   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 233         (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r,W"))]
 234   "TARGET_ALTIVEC"
 235   "*
 236 {
 237   switch (which_alternative)
 238     {
 239     case 0: return \"stvx %1,%y0\";
 240     case 1: return \"lvx %0,%y1\";
 241     case 2: return \"vor %0,%1,%1\";
 242     case 3: return \"#\";
 243     case 4: return \"#\";
 244     case 5: return \"#\";
 245     case 6: return output_vec_const_move (operands);
 246     default: abort ();
 247     }
 248 }"
 249   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 250
 251 (define_split
 252   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 253         (match_operand:V4SF 1 "input_operand" ""))]
 254   "TARGET_ALTIVEC && reload_completed
 255    && gpr_or_gpr_p (operands[0], operands[1])"
 256   [(pc)]
 257 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 258
 259 (define_insn "get_vrsave_internal"
 260   [(set (match_operand:SI 0 "register_operand" "=r")
 261         (unspec:SI [(reg:SI 109)] 214))]
 262   "TARGET_ALTIVEC"
 263   "*
 264 {
 265   if (TARGET_MACHO)
 266      return \"mfspr %0,256\";
 267   else
 268      return \"mfvrsave %0\";
 269 }"
 270   [(set_attr "type" "*")])
 271
 272 (define_insn "*set_vrsave_internal"
 273   [(match_parallel 0 "vrsave_operation"
 274      [(set (reg:SI 109)
 275            (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
 276                                 (reg:SI 109)] 30))])]
 277   "TARGET_ALTIVEC"
 278   "*
 279 {
 280   if (TARGET_MACHO)
 281     return \"mtspr 256,%1\";
 282   else
 283     return \"mtvrsave %1\";
 284 }"
 285   [(set_attr "type" "*")])
 286
 287 ;; Simple binary operations.
 288
 289 (define_insn "addv16qi3"
 290   [(set (match_operand:V16QI 0 "register_operand" "=v")
 291         (plus:V16QI (match_operand:V16QI 1 "register_operand" "v")
 292                     (match_operand:V16QI 2 "register_operand" "v")))]
 293   "TARGET_ALTIVEC"
 294   "vaddubm %0,%1,%2"
 295   [(set_attr "type" "vecsimple")])
 296
 297 (define_insn "addv8hi3"
 298   [(set (match_operand:V8HI 0 "register_operand" "=v")
 299         (plus:V8HI (match_operand:V8HI 1 "register_operand" "v")
 300                    (match_operand:V8HI 2 "register_operand" "v")))]
 301   "TARGET_ALTIVEC"
 302   "vadduhm %0,%1,%2"
 303   [(set_attr "type" "vecsimple")])
 304
 305 (define_insn "addv4si3"
 306   [(set (match_operand:V4SI 0 "register_operand" "=v")
 307         (plus:V4SI (match_operand:V4SI 1 "register_operand" "v")
 308                    (match_operand:V4SI 2 "register_operand" "v")))]
 309   "TARGET_ALTIVEC"
 310   "vadduwm %0,%1,%2"
 311   [(set_attr "type" "vecsimple")])
 312
 313 (define_insn "addv4sf3"
 314   [(set (match_operand:V4SF 0 "register_operand" "=v")
 315         (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 316                    (match_operand:V4SF 2 "register_operand" "v")))]
 317   "TARGET_ALTIVEC"
 318   "vaddfp %0,%1,%2"
 319   [(set_attr "type" "vecfloat")])
 320
 321 (define_insn "altivec_vaddcuw"
 322   [(set (match_operand:V4SI 0 "register_operand" "=v")
 323         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 324                       (match_operand:V4SI 2 "register_operand" "v")] 35))]
 325   "TARGET_ALTIVEC"
 326   "vaddcuw %0,%1,%2"
 327   [(set_attr "type" "vecsimple")])
 328
 329 (define_insn "altivec_vaddubs"
 330   [(set (match_operand:V16QI 0 "register_operand" "=v")
 331         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 332                        (match_operand:V16QI 2 "register_operand" "v")] 36))
 333    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 334   "TARGET_ALTIVEC"
 335   "vaddubs %0,%1,%2"
 336   [(set_attr "type" "vecsimple")])
 337
 338 (define_insn "altivec_vaddsbs"
 339   [(set (match_operand:V16QI 0 "register_operand" "=v")
 340         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 341                        (match_operand:V16QI 2 "register_operand" "v")] 37))
 342    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 343   "TARGET_ALTIVEC"
 344   "vaddsbs %0,%1,%2"
 345   [(set_attr "type" "vecsimple")])
 346
 347 (define_insn "altivec_vadduhs"
 348   [(set (match_operand:V8HI 0 "register_operand" "=v")
 349         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 350                       (match_operand:V8HI 2 "register_operand" "v")] 38))
 351    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 352   "TARGET_ALTIVEC"
 353   "vadduhs %0,%1,%2"
 354   [(set_attr "type" "vecsimple")])
 355
 356 (define_insn "altivec_vaddshs"
 357   [(set (match_operand:V8HI 0 "register_operand" "=v")
 358         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 359                       (match_operand:V8HI 2 "register_operand" "v")] 39))
 360    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 361   "TARGET_ALTIVEC"
 362   "vaddshs %0,%1,%2"
 363   [(set_attr "type" "vecsimple")])
 364
 365 (define_insn "altivec_vadduws"
 366   [(set (match_operand:V4SI 0 "register_operand" "=v")
 367         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 368                       (match_operand:V4SI 2 "register_operand" "v")] 40))
 369    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 370   "TARGET_ALTIVEC"
 371   "vadduws %0,%1,%2"
 372   [(set_attr "type" "vecsimple")])
 373
 374 (define_insn "altivec_vaddsws"
 375   [(set (match_operand:V4SI 0 "register_operand" "=v")
 376         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 377                       (match_operand:V4SI 2 "register_operand" "v")] 41))
 378    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 379   "TARGET_ALTIVEC"
 380   "vaddsws %0,%1,%2"
 381   [(set_attr "type" "vecsimple")])
 382
 383 (define_insn "andv4si3"
 384   [(set (match_operand:V4SI 0 "register_operand" "=v")
 385         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 386                   (match_operand:V4SI 2 "register_operand" "v")))]
 387   "TARGET_ALTIVEC"
 388   "vand %0,%1,%2"
 389   [(set_attr "type" "vecsimple")])
 390
 391 (define_insn "altivec_vandc"
 392   [(set (match_operand:V4SI 0 "register_operand" "=v")
 393         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 394                   (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))]
 395   "TARGET_ALTIVEC"
 396   "vandc %0,%1,%2"
 397   [(set_attr "type" "vecsimple")])
 398
 399 (define_insn "altivec_vavgub"
 400   [(set (match_operand:V16QI 0 "register_operand" "=v")
 401         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 402                        (match_operand:V16QI 2 "register_operand" "v")] 44))]
 403   "TARGET_ALTIVEC"
 404   "vavgub %0,%1,%2"
 405   [(set_attr "type" "vecsimple")])
 406
 407 (define_insn "altivec_vavgsb"
 408   [(set (match_operand:V16QI 0 "register_operand" "=v")
 409         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 410                        (match_operand:V16QI 2 "register_operand" "v")] 45))]
 411   "TARGET_ALTIVEC"
 412   "vavgsb %0,%1,%2"
 413   [(set_attr "type" "vecsimple")])
 414
 415 (define_insn "altivec_vavguh"
 416   [(set (match_operand:V8HI 0 "register_operand" "=v")
 417         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 418                       (match_operand:V8HI 2 "register_operand" "v")] 46))]
 419   "TARGET_ALTIVEC"
 420   "vavguh %0,%1,%2"
 421   [(set_attr "type" "vecsimple")])
 422
 423 (define_insn "altivec_vavgsh"
 424   [(set (match_operand:V8HI 0 "register_operand" "=v")
 425         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 426                       (match_operand:V8HI 2 "register_operand" "v")] 47))]
 427   "TARGET_ALTIVEC"
 428   "vavgsh %0,%1,%2"
 429   [(set_attr "type" "vecsimple")])
 430
 431 (define_insn "altivec_vavguw"
 432   [(set (match_operand:V4SI 0 "register_operand" "=v")
 433         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 434                       (match_operand:V4SI 2 "register_operand" "v")] 48))]
 435   "TARGET_ALTIVEC"
 436   "vavguw %0,%1,%2"
 437   [(set_attr "type" "vecsimple")])
 438
 439 (define_insn "altivec_vavgsw"
 440   [(set (match_operand:V4SI 0 "register_operand" "=v")
 441         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 442                       (match_operand:V4SI 2 "register_operand" "v")] 49))]
 443   "TARGET_ALTIVEC"
 444   "vavgsw %0,%1,%2"
 445   [(set_attr "type" "vecsimple")])
 446
 447 (define_insn "altivec_vcmpbfp"
 448   [(set (match_operand:V4SI 0 "register_operand" "=v")
 449         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 450                       (match_operand:V4SF 2 "register_operand" "v")] 50))]
 451   "TARGET_ALTIVEC"
 452   "vcmpbfp %0,%1,%2"
 453   [(set_attr "type" "veccmp")])
 454
 455 (define_insn "altivec_vcmpequb"
 456   [(set (match_operand:V16QI 0 "register_operand" "=v")
 457         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 458                        (match_operand:V16QI 2 "register_operand" "v")] 51))]
 459   "TARGET_ALTIVEC"
 460   "vcmpequb %0,%1,%2"
 461   [(set_attr "type" "vecsimple")])
 462
 463 (define_insn "altivec_vcmpequh"
 464   [(set (match_operand:V8HI 0 "register_operand" "=v")
 465         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 466                       (match_operand:V8HI 2 "register_operand" "v")] 52))]
 467   "TARGET_ALTIVEC"
 468   "vcmpequh %0,%1,%2"
 469   [(set_attr "type" "vecsimple")])
 470
 471 (define_insn "altivec_vcmpequw"
 472   [(set (match_operand:V4SI 0 "register_operand" "=v")
 473         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 474                       (match_operand:V4SI 2 "register_operand" "v")] 53))]
 475   "TARGET_ALTIVEC"
 476   "vcmpequw %0,%1,%2"
 477   [(set_attr "type" "vecsimple")])
 478
 479 (define_insn "altivec_vcmpeqfp"
 480   [(set (match_operand:V4SI 0 "register_operand" "=v")
 481         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 482                       (match_operand:V4SF 2 "register_operand" "v")] 54))]
 483   "TARGET_ALTIVEC"
 484   "vcmpeqfp %0,%1,%2"
 485   [(set_attr "type" "veccmp")])
 486
 487 (define_insn "altivec_vcmpgefp"
 488   [(set (match_operand:V4SI 0 "register_operand" "=v")
 489         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 490                       (match_operand:V4SF 2 "register_operand" "v")] 55))]
 491   "TARGET_ALTIVEC"
 492   "vcmpgefp %0,%1,%2"
 493   [(set_attr "type" "veccmp")])
 494
 495 (define_insn "altivec_vcmpgtub"
 496   [(set (match_operand:V16QI 0 "register_operand" "=v")
 497         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 498                        (match_operand:V16QI 2 "register_operand" "v")] 56))]
 499   "TARGET_ALTIVEC"
 500   "vcmpgtub %0,%1,%2"
 501   [(set_attr "type" "vecsimple")])
 502
 503 (define_insn "altivec_vcmpgtsb"
 504   [(set (match_operand:V16QI 0 "register_operand" "=v")
 505         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 506                        (match_operand:V16QI 2 "register_operand" "v")] 57))]
 507   "TARGET_ALTIVEC"
 508   "vcmpgtsb %0,%1,%2"
 509   [(set_attr "type" "vecsimple")])
 510
 511 (define_insn "altivec_vcmpgtuh"
 512   [(set (match_operand:V8HI 0 "register_operand" "=v")
 513         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 514                       (match_operand:V8HI 2 "register_operand" "v")] 58))]
 515   "TARGET_ALTIVEC"
 516   "vcmpgtuh %0,%1,%2"
 517   [(set_attr "type" "vecsimple")])
 518
 519 (define_insn "altivec_vcmpgtsh"
 520   [(set (match_operand:V8HI 0 "register_operand" "=v")
 521         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 522                       (match_operand:V8HI 2 "register_operand" "v")] 59))]
 523   "TARGET_ALTIVEC"
 524   "vcmpgtsh %0,%1,%2"
 525   [(set_attr "type" "vecsimple")])
 526
 527 (define_insn "altivec_vcmpgtuw"
 528   [(set (match_operand:V4SI 0 "register_operand" "=v")
 529         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 530                       (match_operand:V4SI 2 "register_operand" "v")] 60))]
 531   "TARGET_ALTIVEC"
 532   "vcmpgtuw %0,%1,%2"
 533   [(set_attr "type" "vecsimple")])
 534
 535 (define_insn "altivec_vcmpgtsw"
 536   [(set (match_operand:V4SI 0 "register_operand" "=v")
 537         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 538                       (match_operand:V4SI 2 "register_operand" "v")] 61))]
 539   "TARGET_ALTIVEC"
 540   "vcmpgtsw %0,%1,%2"
 541   [(set_attr "type" "vecsimple")])
 542
 543 (define_insn "altivec_vcmpgtfp"
 544   [(set (match_operand:V4SI 0 "register_operand" "=v")
 545         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 546                       (match_operand:V4SF 2 "register_operand" "v")] 62))]
 547   "TARGET_ALTIVEC"
 548   "vcmpgtfp %0,%1,%2"
 549   [(set_attr "type" "veccmp")])
 550
 551 ;; Fused multiply add
 552 (define_insn "altivec_vmaddfp"
 553   [(set (match_operand:V4SF 0 "register_operand" "=v")
 554         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 555                               (match_operand:V4SF 2 "register_operand" "v"))
 556                    (match_operand:V4SF 3 "register_operand" "v")))]
 557   "TARGET_ALTIVEC"
 558   "vmaddfp %0,%1,%2,%3"
 559   [(set_attr "type" "vecfloat")])
 560
 561 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
 562
 563 (define_expand "mulv4sf3"
 564   [(use (match_operand:V4SF 0 "register_operand" ""))
 565    (use (match_operand:V4SF 1 "register_operand" ""))
 566    (use (match_operand:V4SF 2 "register_operand" ""))]
 567   "TARGET_ALTIVEC && TARGET_FUSED_MADD"
 568   "
 569 {
 570   rtx neg0;
 571
 572   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
 573   neg0 = gen_reg_rtx (V4SFmode);
 574   emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1)));
 575   emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
 576
 577   /* Use the multiply-add.  */
 578   emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
 579                                   neg0));
 580   DONE;
 581 }")
 582
 583 ;; Fused multiply subtract
 584 (define_insn "altivec_vnmsubfp"
 585   [(set (match_operand:V4SF 0 "register_operand" "=v")
 586         (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 587                                (match_operand:V4SF 2 "register_operand" "v"))
 588                     (match_operand:V4SF 3 "register_operand" "v")))]
 589   "TARGET_ALTIVEC"
 590   "vnmsubfp %0,%1,%2,%3"
 591   [(set_attr "type" "vecfloat")])
 592
 593
 594 (define_insn "altivec_vmsumubm"
 595   [(set (match_operand:V4SI 0 "register_operand" "=v")
 596         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 597                       (match_operand:V16QI 2 "register_operand" "v")
 598                       (match_operand:V4SI 3 "register_operand" "v")] 65))]
 599   "TARGET_ALTIVEC"
 600   "vmsumubm %0,%1,%2,%3"
 601   [(set_attr "type" "veccomplex")])
 602
 603 (define_insn "altivec_vmsummbm"
 604   [(set (match_operand:V4SI 0 "register_operand" "=v")
 605         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 606                       (match_operand:V16QI 2 "register_operand" "v")
 607                       (match_operand:V4SI 3 "register_operand" "v")] 66))]
 608   "TARGET_ALTIVEC"
 609   "vmsummbm %0,%1,%2,%3"
 610   [(set_attr "type" "veccomplex")])
 611
 612 (define_insn "altivec_vmsumuhm"
 613   [(set (match_operand:V4SI 0 "register_operand" "=v")
 614         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 615                       (match_operand:V8HI 2 "register_operand" "v")
 616                       (match_operand:V4SI 3 "register_operand" "v")] 67))]
 617   "TARGET_ALTIVEC"
 618   "vmsumuhm %0,%1,%2,%3"
 619   [(set_attr "type" "veccomplex")])
 620
 621 (define_insn "altivec_vmsumshm"
 622   [(set (match_operand:V4SI 0 "register_operand" "=v")
 623         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 624                       (match_operand:V8HI 2 "register_operand" "v")
 625                       (match_operand:V4SI 3 "register_operand" "v")] 68))]
 626   "TARGET_ALTIVEC"
 627   "vmsumshm %0,%1,%2,%3"
 628   [(set_attr "type" "veccomplex")])
 629
 630 (define_insn "altivec_vmsumuhs"
 631   [(set (match_operand:V4SI 0 "register_operand" "=v")
 632         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 633                       (match_operand:V8HI 2 "register_operand" "v")
 634                       (match_operand:V4SI 3 "register_operand" "v")] 69))
 635    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 636   "TARGET_ALTIVEC"
 637   "vmsumuhs %0,%1,%2,%3"
 638   [(set_attr "type" "veccomplex")])
 639
 640 (define_insn "altivec_vmsumshs"
 641   [(set (match_operand:V4SI 0 "register_operand" "=v")
 642         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 643                       (match_operand:V8HI 2 "register_operand" "v")
 644                       (match_operand:V4SI 3 "register_operand" "v")] 70))
 645    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 646   "TARGET_ALTIVEC"
 647   "vmsumshs %0,%1,%2,%3"
 648   [(set_attr "type" "veccomplex")])
 649
 650 (define_insn "umaxv16qi3"
 651   [(set (match_operand:V16QI 0 "register_operand" "=v")
 652         (umax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 653                     (match_operand:V16QI 2 "register_operand" "v")))]
 654   "TARGET_ALTIVEC"
 655   "vmaxub %0,%1,%2"
 656   [(set_attr "type" "vecsimple")])
 657
 658 (define_insn "smaxv16qi3"
 659   [(set (match_operand:V16QI 0 "register_operand" "=v")
 660         (smax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 661                     (match_operand:V16QI 2 "register_operand" "v")))]
 662   "TARGET_ALTIVEC"
 663   "vmaxsb %0,%1,%2"
 664   [(set_attr "type" "vecsimple")])
 665
 666 (define_insn "umaxv8hi3"
 667   [(set (match_operand:V8HI 0 "register_operand" "=v")
 668         (umax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 669                    (match_operand:V8HI 2 "register_operand" "v")))]
 670   "TARGET_ALTIVEC"
 671   "vmaxuh %0,%1,%2"
 672   [(set_attr "type" "vecsimple")])
 673
 674 (define_insn "smaxv8hi3"
 675   [(set (match_operand:V8HI 0 "register_operand" "=v")
 676         (smax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 677                    (match_operand:V8HI 2 "register_operand" "v")))]
 678   "TARGET_ALTIVEC"
 679   "vmaxsh %0,%1,%2"
 680   [(set_attr "type" "vecsimple")])
 681
 682 (define_insn "umaxv4si3"
 683   [(set (match_operand:V4SI 0 "register_operand" "=v")
 684         (umax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 685                    (match_operand:V4SI 2 "register_operand" "v")))]
 686   "TARGET_ALTIVEC"
 687   "vmaxuw %0,%1,%2"
 688   [(set_attr "type" "vecsimple")])
 689
 690 (define_insn "smaxv4si3"
 691   [(set (match_operand:V4SI 0 "register_operand" "=v")
 692         (smax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 693                    (match_operand:V4SI 2 "register_operand" "v")))]
 694   "TARGET_ALTIVEC"
 695   "vmaxsw %0,%1,%2"
 696   [(set_attr "type" "vecsimple")])
 697
 698 (define_insn "smaxv4sf3"
 699   [(set (match_operand:V4SF 0 "register_operand" "=v")
 700         (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
 701                    (match_operand:V4SF 2 "register_operand" "v")))]
 702   "TARGET_ALTIVEC"
 703   "vmaxfp %0,%1,%2"
 704   [(set_attr "type" "veccmp")])
 705
 706 (define_insn "altivec_vmhaddshs"
 707   [(set (match_operand:V8HI 0 "register_operand" "=v")
 708         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 709                       (match_operand:V8HI 2 "register_operand" "v")
 710                       (match_operand:V8HI 3 "register_operand" "v")] 71))
 711    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 712   "TARGET_ALTIVEC"
 713   "vmhaddshs %0,%1,%2,%3"
 714   [(set_attr "type" "veccomplex")])
 715 (define_insn "altivec_vmhraddshs"
 716   [(set (match_operand:V8HI 0 "register_operand" "=v")
 717         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 718                       (match_operand:V8HI 2 "register_operand" "v")
 719                       (match_operand:V8HI 3 "register_operand" "v")] 72))
 720    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 721   "TARGET_ALTIVEC"
 722   "vmhraddshs %0,%1,%2,%3"
 723   [(set_attr "type" "veccomplex")])
 724 (define_insn "altivec_vmladduhm"
 725   [(set (match_operand:V8HI 0 "register_operand" "=v")
 726         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 727                       (match_operand:V8HI 2 "register_operand" "v")
 728                       (match_operand:V8HI 3 "register_operand" "v")] 73))]
 729   "TARGET_ALTIVEC"
 730   "vmladduhm %0,%1,%2,%3"
 731   [(set_attr "type" "veccomplex")])
 732
 733 (define_insn "altivec_vmrghb"
 734   [(set (match_operand:V16QI 0 "register_operand" "=v")
 735         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 736                                            (parallel [(const_int 8)
 737                                                       (const_int 9)
 738                                                       (const_int 10)
 739                                                       (const_int 11)
 740                                                       (const_int 12)
 741                                                       (const_int 13)
 742                                                       (const_int 14)
 743                                                       (const_int 15)
 744                                                       (const_int 0)
 745                                                       (const_int 1)
 746                                                       (const_int 2)
 747                                                       (const_int 3)
 748                                                       (const_int 4)
 749                                                       (const_int 5)
 750                                                       (const_int 6)
 751                                                       (const_int 7)]))
 752                       (match_operand:V16QI 2 "register_operand" "v")
 753                       (const_int 255)))]
 754   "TARGET_ALTIVEC"
 755   "vmrghb %0,%1,%2"
 756   [(set_attr "type" "vecperm")])
 757
 758 (define_insn "altivec_vmrghh"
 759   [(set (match_operand:V8HI 0 "register_operand" "=v")
 760         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 761                                            (parallel [(const_int 4)
 762                                                       (const_int 5)
 763                                                       (const_int 6)
 764                                                       (const_int 7)
 765                                                       (const_int 0)
 766                                                       (const_int 1)
 767                                                       (const_int 2)
 768                                                       (const_int 3)]))
 769                       (match_operand:V8HI 2 "register_operand" "v")
 770                       (const_int 15)))]
 771   "TARGET_ALTIVEC"
 772   "vmrghh %0,%1,%2"
 773   [(set_attr "type" "vecperm")])
 774
 775 (define_insn "altivec_vmrghw"
 776   [(set (match_operand:V4SI 0 "register_operand" "=v")
 777         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 778                                          (parallel [(const_int 2)
 779                                                     (const_int 3)
 780                                                     (const_int 0)
 781                                                     (const_int 1)]))
 782                       (match_operand:V4SI 2 "register_operand" "v")
 783                       (const_int 12)))]
 784   "TARGET_ALTIVEC"
 785   "vmrghw %0,%1,%2"
 786   [(set_attr "type" "vecperm")])
 787
 788 (define_insn "altivec_vmrglb"
 789   [(set (match_operand:V16QI 0 "register_operand" "=v")
 790         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 791                                            (parallel [(const_int 0)
 792                                                       (const_int 1)
 793                                                       (const_int 2)
 794                                                       (const_int 3)
 795                                                       (const_int 4)
 796                                                       (const_int 5)
 797                                                       (const_int 6)
 798                                                       (const_int 7)
 799                                                       (const_int 8)
 800                                                       (const_int 9)
 801                                                       (const_int 10)
 802                                                       (const_int 11)
 803                                                       (const_int 12)
 804                                                       (const_int 13)
 805                                                       (const_int 14)
 806                                                       (const_int 15)]))
 807                       (match_operand:V16QI 1 "register_operand" "v")
 808                       (const_int 255)))]
 809   "TARGET_ALTIVEC"
 810   "vmrglb %0,%1,%2"
 811   [(set_attr "type" "vecperm")])
 812
 813 (define_insn "altivec_vmrglh"
 814   [(set (match_operand:V8HI 0 "register_operand" "=v")
 815         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 816                                            (parallel [(const_int 0)
 817                                                       (const_int 1)
 818                                                       (const_int 2)
 819                                                       (const_int 3)
 820                                                       (const_int 4)
 821                                                       (const_int 5)
 822                                                       (const_int 6)
 823                                                       (const_int 7)]))
 824                       (match_operand:V8HI 1 "register_operand" "v")
 825                       (const_int 15)))]
 826   "TARGET_ALTIVEC"
 827   "vmrglh %0,%1,%2"
 828   [(set_attr "type" "vecperm")])
 829
 830 (define_insn "altivec_vmrglw"
 831   [(set (match_operand:V4SI 0 "register_operand" "=v")
 832         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 833                                          (parallel [(const_int 0)
 834                                                     (const_int 1)
 835                                                     (const_int 2)
 836                                                     (const_int 3)]))
 837                       (match_operand:V4SI 1 "register_operand" "v")
 838                       (const_int 12)))]
 839   "TARGET_ALTIVEC"
 840   "vmrglw %0,%1,%2"
 841   [(set_attr "type" "vecperm")])
 842
 843 (define_insn "uminv16qi3"
 844   [(set (match_operand:V16QI 0 "register_operand" "=v")
 845         (umin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 846                     (match_operand:V16QI 2 "register_operand" "v")))]
 847   "TARGET_ALTIVEC"
 848   "vminub %0,%1,%2"
 849   [(set_attr "type" "vecsimple")])
 850
 851 (define_insn "sminv16qi3"
 852   [(set (match_operand:V16QI 0 "register_operand" "=v")
 853         (smin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 854                     (match_operand:V16QI 2 "register_operand" "v")))]
 855   "TARGET_ALTIVEC"
 856   "vminsb %0,%1,%2"
 857   [(set_attr "type" "vecsimple")])
 858
 859 (define_insn "uminv8hi3"
 860   [(set (match_operand:V8HI 0 "register_operand" "=v")
 861         (umin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 862                    (match_operand:V8HI 2 "register_operand" "v")))]
 863   "TARGET_ALTIVEC"
 864   "vminuh %0,%1,%2"
 865   [(set_attr "type" "vecsimple")])
 866
 867 (define_insn "sminv8hi3"
 868   [(set (match_operand:V8HI 0 "register_operand" "=v")
 869         (smin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 870                    (match_operand:V8HI 2 "register_operand" "v")))]
 871   "TARGET_ALTIVEC"
 872   "vminsh %0,%1,%2"
 873   [(set_attr "type" "vecsimple")])
 874
 875 (define_insn "uminv4si3"
 876   [(set (match_operand:V4SI 0 "register_operand" "=v")
 877         (umin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 878                    (match_operand:V4SI 2 "register_operand" "v")))]
 879   "TARGET_ALTIVEC"
 880   "vminuw %0,%1,%2"
 881   [(set_attr "type" "vecsimple")])
 882
 883 (define_insn "sminv4si3"
 884   [(set (match_operand:V4SI 0 "register_operand" "=v")
 885         (smin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 886                    (match_operand:V4SI 2 "register_operand" "v")))]
 887   "TARGET_ALTIVEC"
 888   "vminsw %0,%1,%2"
 889   [(set_attr "type" "vecsimple")])
 890
 891 (define_insn "sminv4sf3"
 892   [(set (match_operand:V4SF 0 "register_operand" "=v")
 893         (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
 894                    (match_operand:V4SF 2 "register_operand" "v")))]
 895   "TARGET_ALTIVEC"
 896   "vminfp %0,%1,%2"
 897   [(set_attr "type" "veccmp")])
 898
 899 (define_insn "altivec_vmuleub"
 900   [(set (match_operand:V8HI 0 "register_operand" "=v")
 901         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 902                       (match_operand:V16QI 2 "register_operand" "v")] 83))]
 903   "TARGET_ALTIVEC"
 904   "vmuleub %0,%1,%2"
 905   [(set_attr "type" "veccomplex")])
 906
 907 (define_insn "altivec_vmulesb"
 908   [(set (match_operand:V8HI 0 "register_operand" "=v")
 909         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 910                       (match_operand:V16QI 2 "register_operand" "v")] 84))]
 911   "TARGET_ALTIVEC"
 912   "vmulesb %0,%1,%2"
 913   [(set_attr "type" "veccomplex")])
 914
 915 (define_insn "altivec_vmuleuh"
 916   [(set (match_operand:V4SI 0 "register_operand" "=v")
 917         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 918                       (match_operand:V8HI 2 "register_operand" "v")] 85))]
 919   "TARGET_ALTIVEC"
 920   "vmuleuh %0,%1,%2"
 921   [(set_attr "type" "veccomplex")])
 922
 923 (define_insn "altivec_vmulesh"
 924   [(set (match_operand:V4SI 0 "register_operand" "=v")
 925         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 926                       (match_operand:V8HI 2 "register_operand" "v")] 86))]
 927   "TARGET_ALTIVEC"
 928   "vmulesh %0,%1,%2"
 929   [(set_attr "type" "veccomplex")])
 930
 931 (define_insn "altivec_vmuloub"
 932   [(set (match_operand:V8HI 0 "register_operand" "=v")
 933         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 934                       (match_operand:V16QI 2 "register_operand" "v")] 87))]
 935   "TARGET_ALTIVEC"
 936   "vmuloub %0,%1,%2"
 937   [(set_attr "type" "veccomplex")])
 938
 939 (define_insn "altivec_vmulosb"
 940   [(set (match_operand:V8HI 0 "register_operand" "=v")
 941         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 942                       (match_operand:V16QI 2 "register_operand" "v")] 88))]
 943   "TARGET_ALTIVEC"
 944   "vmulosb %0,%1,%2"
 945   [(set_attr "type" "veccomplex")])
 946
 947 (define_insn "altivec_vmulouh"
 948   [(set (match_operand:V4SI 0 "register_operand" "=v")
 949         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 950                       (match_operand:V8HI 2 "register_operand" "v")] 89))]
 951   "TARGET_ALTIVEC"
 952   "vmulouh %0,%1,%2"
 953   [(set_attr "type" "veccomplex")])
 954
 955 (define_insn "altivec_vmulosh"
 956   [(set (match_operand:V4SI 0 "register_operand" "=v")
 957         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 958                       (match_operand:V8HI 2 "register_operand" "v")] 90))]
 959   "TARGET_ALTIVEC"
 960   "vmulosh %0,%1,%2"
 961   [(set_attr "type" "veccomplex")])
 962
 963 (define_insn "altivec_vnor"
 964   [(set (match_operand:V4SI 0 "register_operand" "=v")
 965         (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
 966                             (match_operand:V4SI 2 "register_operand" "v"))))]
 967   "TARGET_ALTIVEC"
 968   "vnor %0,%1,%2"
 969   [(set_attr "type" "vecsimple")])
 970
 971 (define_insn "iorv4si3"
 972   [(set (match_operand:V4SI 0 "register_operand" "=v")
 973         (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
 974                   (match_operand:V4SI 2 "register_operand" "v")))]
 975   "TARGET_ALTIVEC"
 976   "vor %0,%1,%2"
 977   [(set_attr "type" "vecsimple")])
 978
 979 (define_insn "altivec_vpkuhum"
 980   [(set (match_operand:V16QI 0 "register_operand" "=v")
 981         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 982                        (match_operand:V8HI 2 "register_operand" "v")] 93))]
 983   "TARGET_ALTIVEC"
 984   "vpkuhum %0,%1,%2"
 985   [(set_attr "type" "vecperm")])
 986
 987 (define_insn "altivec_vpkuwum"
 988   [(set (match_operand:V8HI 0 "register_operand" "=v")
 989         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 990                       (match_operand:V4SI 2 "register_operand" "v")] 94))]
 991   "TARGET_ALTIVEC"
 992   "vpkuwum %0,%1,%2"
 993   [(set_attr "type" "vecperm")])
 994
 995 (define_insn "altivec_vpkpx"
 996   [(set (match_operand:V8HI 0 "register_operand" "=v")
 997         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 998                       (match_operand:V4SI 2 "register_operand" "v")] 95))]
 999   "TARGET_ALTIVEC"
1000   "vpkpx %0,%1,%2"
1001   [(set_attr "type" "vecperm")])
1002
1003 (define_insn "altivec_vpkuhss"
1004   [(set (match_operand:V16QI 0 "register_operand" "=v")
1005         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1006                        (match_operand:V8HI 2 "register_operand" "v")] 96))
1007    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1008   "TARGET_ALTIVEC"
1009   "vpkuhss %0,%1,%2"
1010   [(set_attr "type" "vecperm")])
1011
1012 (define_insn "altivec_vpkshss"
1013   [(set (match_operand:V16QI 0 "register_operand" "=v")
1014         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1015                        (match_operand:V8HI 2 "register_operand" "v")] 97))
1016    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1017   "TARGET_ALTIVEC"
1018   "vpkshss %0,%1,%2"
1019   [(set_attr "type" "vecperm")])
1020
1021 (define_insn "altivec_vpkuwss"
1022   [(set (match_operand:V8HI 0 "register_operand" "=v")
1023         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1024                       (match_operand:V4SI 2 "register_operand" "v")] 98))
1025    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1026   "TARGET_ALTIVEC"
1027   "vpkuwss %0,%1,%2"
1028   [(set_attr "type" "vecperm")])
1029
1030 (define_insn "altivec_vpkswss"
1031   [(set (match_operand:V8HI 0 "register_operand" "=v")
1032         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1033                       (match_operand:V4SI 2 "register_operand" "v")] 99))
1034    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1035   "TARGET_ALTIVEC"
1036   "vpkswss %0,%1,%2"
1037   [(set_attr "type" "vecperm")])
1038
1039 (define_insn "altivec_vpkuhus"
1040   [(set (match_operand:V16QI 0 "register_operand" "=v")
1041         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1042                        (match_operand:V8HI 2 "register_operand" "v")] 100))
1043    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1044   "TARGET_ALTIVEC"
1045   "vpkuhus %0,%1,%2"
1046   [(set_attr "type" "vecperm")])
1047
1048 (define_insn "altivec_vpkshus"
1049   [(set (match_operand:V16QI 0 "register_operand" "=v")
1050         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1051                        (match_operand:V8HI 2 "register_operand" "v")] 101))
1052    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1053   "TARGET_ALTIVEC"
1054   "vpkshus %0,%1,%2"
1055   [(set_attr "type" "vecperm")])
1056
1057 (define_insn "altivec_vpkuwus"
1058   [(set (match_operand:V8HI 0 "register_operand" "=v")
1059         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1060                       (match_operand:V4SI 2 "register_operand" "v")] 102))
1061    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1062   "TARGET_ALTIVEC"
1063   "vpkuwus %0,%1,%2"
1064   [(set_attr "type" "vecperm")])
1065
1066 (define_insn "altivec_vpkswus"
1067   [(set (match_operand:V8HI 0 "register_operand" "=v")
1068         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1069                       (match_operand:V4SI 2 "register_operand" "v")] 103))
1070    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1071   "TARGET_ALTIVEC"
1072   "vpkswus %0,%1,%2"
1073   [(set_attr "type" "vecperm")])
1074
1075 (define_insn "altivec_vrlb"
1076   [(set (match_operand:V16QI 0 "register_operand" "=v")
1077         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1078                        (match_operand:V16QI 2 "register_operand" "v")] 104))]
1079   "TARGET_ALTIVEC"
1080   "vrlb %0,%1,%2"
1081   [(set_attr "type" "vecsimple")])
1082
1083 (define_insn "altivec_vrlh"
1084   [(set (match_operand:V8HI 0 "register_operand" "=v")
1085         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1086                       (match_operand:V8HI 2 "register_operand" "v")] 105))]
1087   "TARGET_ALTIVEC"
1088   "vrlh %0,%1,%2"
1089   [(set_attr "type" "vecsimple")])
1090
1091 (define_insn "altivec_vrlw"
1092   [(set (match_operand:V4SI 0 "register_operand" "=v")
1093         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1094                       (match_operand:V4SI 2 "register_operand" "v")] 106))]
1095   "TARGET_ALTIVEC"
1096   "vrlw %0,%1,%2"
1097   [(set_attr "type" "vecsimple")])
1098
1099 (define_insn "altivec_vslb"
1100   [(set (match_operand:V16QI 0 "register_operand" "=v")
1101         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1102                        (match_operand:V16QI 2 "register_operand" "v")] 107))]
1103   "TARGET_ALTIVEC"
1104   "vslb %0,%1,%2"
1105   [(set_attr "type" "vecsimple")])
1106
1107 (define_insn "altivec_vslh"
1108   [(set (match_operand:V8HI 0 "register_operand" "=v")
1109         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1110                       (match_operand:V8HI 2 "register_operand" "v")] 108))]
1111   "TARGET_ALTIVEC"
1112   "vslh %0,%1,%2"
1113   [(set_attr "type" "vecsimple")])
1114
1115 (define_insn "altivec_vslw"
1116   [(set (match_operand:V4SI 0 "register_operand" "=v")
1117         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1118                       (match_operand:V4SI 2 "register_operand" "v")] 109))]
1119   "TARGET_ALTIVEC"
1120   "vslw %0,%1,%2"
1121   [(set_attr "type" "vecsimple")])
1122
1123 (define_insn "altivec_vslw_v4sf"
1124   [(set (match_operand:V4SF 0 "register_operand" "=v")
1125         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1126                       (match_operand:V4SF 2 "register_operand" "v")] 109))]
1127   "TARGET_ALTIVEC"
1128   "vslw %0,%1,%2"
1129   [(set_attr "type" "vecsimple")])
1130
1131 (define_insn "altivec_vsl"
1132   [(set (match_operand:V4SI 0 "register_operand" "=v")
1133         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1134                       (match_operand:V4SI 2 "register_operand" "v")] 110))]
1135   "TARGET_ALTIVEC"
1136   "vsl %0,%1,%2"
1137   [(set_attr "type" "vecperm")])
1138
1139 (define_insn "altivec_vslo"
1140   [(set (match_operand:V4SI 0 "register_operand" "=v")
1141         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1142                       (match_operand:V4SI 2 "register_operand" "v")] 111))]
1143   "TARGET_ALTIVEC"
1144   "vslo %0,%1,%2"
1145   [(set_attr "type" "vecperm")])
1146
1147 (define_insn "altivec_vsrb"
1148   [(set (match_operand:V16QI 0 "register_operand" "=v")
1149         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1150                        (match_operand:V16QI 2 "register_operand" "v")] 112))]
1151   "TARGET_ALTIVEC"
1152   "vsrb %0,%1,%2"
1153   [(set_attr "type" "vecsimple")])
1154
1155 (define_insn "altivec_vsrh"
1156   [(set (match_operand:V8HI 0 "register_operand" "=v")
1157         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1158                       (match_operand:V8HI 2 "register_operand" "v")] 113))]
1159   "TARGET_ALTIVEC"
1160   "vsrh %0,%1,%2"
1161   [(set_attr "type" "vecsimple")])
1162
1163 (define_insn "altivec_vsrw"
1164   [(set (match_operand:V4SI 0 "register_operand" "=v")
1165         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1166                       (match_operand:V4SI 2 "register_operand" "v")] 114))]
1167   "TARGET_ALTIVEC"
1168   "vsrw %0,%1,%2"
1169   [(set_attr "type" "vecsimple")])
1170
1171 (define_insn "altivec_vsrab"
1172   [(set (match_operand:V16QI 0 "register_operand" "=v")
1173         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1174                        (match_operand:V16QI 2 "register_operand" "v")] 115))]
1175   "TARGET_ALTIVEC"
1176   "vsrab %0,%1,%2"
1177   [(set_attr "type" "vecsimple")])
1178
1179 (define_insn "altivec_vsrah"
1180   [(set (match_operand:V8HI 0 "register_operand" "=v")
1181         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1182                       (match_operand:V8HI 2 "register_operand" "v")] 116))]
1183   "TARGET_ALTIVEC"
1184   "vsrah %0,%1,%2"
1185   [(set_attr "type" "vecsimple")])
1186
1187 (define_insn "altivec_vsraw"
1188   [(set (match_operand:V4SI 0 "register_operand" "=v")
1189         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1190                       (match_operand:V4SI 2 "register_operand" "v")] 117))]
1191   "TARGET_ALTIVEC"
1192   "vsraw %0,%1,%2"
1193   [(set_attr "type" "vecsimple")])
1194
1195 (define_insn "altivec_vsr"
1196   [(set (match_operand:V4SI 0 "register_operand" "=v")
1197         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1198                       (match_operand:V4SI 2 "register_operand" "v")] 118))]
1199   "TARGET_ALTIVEC"
1200   "vsr %0,%1,%2"
1201   [(set_attr "type" "vecperm")])
1202
1203 (define_insn "altivec_vsro"
1204   [(set (match_operand:V4SI 0 "register_operand" "=v")
1205         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1206                       (match_operand:V4SI 2 "register_operand" "v")] 119))]
1207   "TARGET_ALTIVEC"
1208   "vsro %0,%1,%2"
1209   [(set_attr "type" "vecperm")])
1210
1211 (define_insn "subv16qi3"
1212   [(set (match_operand:V16QI 0 "register_operand" "=v")
1213         (minus:V16QI (match_operand:V16QI 1 "register_operand" "v")
1214                      (match_operand:V16QI 2 "register_operand" "v")))]
1215   "TARGET_ALTIVEC"
1216   "vsububm %0,%1,%2"
1217   [(set_attr "type" "vecsimple")])
1218
1219 (define_insn "subv8hi3"
1220   [(set (match_operand:V8HI 0 "register_operand" "=v")
1221         (minus:V8HI (match_operand:V8HI 1 "register_operand" "v")
1222                     (match_operand:V8HI 2 "register_operand" "v")))]
1223   "TARGET_ALTIVEC"
1224   "vsubuhm %0,%1,%2"
1225   [(set_attr "type" "vecsimple")])
1226
1227 (define_insn "subv4si3"
1228   [(set (match_operand:V4SI 0 "register_operand" "=v")
1229         (minus:V4SI (match_operand:V4SI 1 "register_operand" "v")
1230                     (match_operand:V4SI 2 "register_operand" "v")))]
1231   "TARGET_ALTIVEC"
1232   "vsubuwm %0,%1,%2"
1233   [(set_attr "type" "vecsimple")])
1234
1235 (define_insn "subv4sf3"
1236   [(set (match_operand:V4SF 0 "register_operand" "=v")
1237         (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
1238                     (match_operand:V4SF 2 "register_operand" "v")))]
1239   "TARGET_ALTIVEC"
1240   "vsubfp %0,%1,%2"
1241   [(set_attr "type" "vecfloat")])
1242
1243 (define_insn "altivec_vsubcuw"
1244   [(set (match_operand:V4SI 0 "register_operand" "=v")
1245         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1246                       (match_operand:V4SI 2 "register_operand" "v")] 124))]
1247   "TARGET_ALTIVEC"
1248   "vsubcuw %0,%1,%2"
1249   [(set_attr "type" "vecsimple")])
1250
1251 (define_insn "altivec_vsububs"
1252   [(set (match_operand:V16QI 0 "register_operand" "=v")
1253         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1254                        (match_operand:V16QI 2 "register_operand" "v")] 125))
1255    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1256   "TARGET_ALTIVEC"
1257   "vsububs %0,%1,%2"
1258   [(set_attr "type" "vecsimple")])
1259
1260 (define_insn "altivec_vsubsbs"
1261   [(set (match_operand:V16QI 0 "register_operand" "=v")
1262         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1263                        (match_operand:V16QI 2 "register_operand" "v")] 126))
1264    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1265   "TARGET_ALTIVEC"
1266   "vsubsbs %0,%1,%2"
1267   [(set_attr "type" "vecsimple")])
1268
1269 (define_insn "altivec_vsubuhs"
1270   [(set (match_operand:V8HI 0 "register_operand" "=v")
1271         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1272                       (match_operand:V8HI 2 "register_operand" "v")] 127))
1273    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1274   "TARGET_ALTIVEC"
1275   "vsubuhs %0,%1,%2"
1276   [(set_attr "type" "vecsimple")])
1277
1278 (define_insn "altivec_vsubshs"
1279   [(set (match_operand:V8HI 0 "register_operand" "=v")
1280         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1281                       (match_operand:V8HI 2 "register_operand" "v")] 128))
1282    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1283   "TARGET_ALTIVEC"
1284   "vsubshs %0,%1,%2"
1285   [(set_attr "type" "vecsimple")])
1286
1287 (define_insn "altivec_vsubuws"
1288   [(set (match_operand:V4SI 0 "register_operand" "=v")
1289         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1290                       (match_operand:V4SI 2 "register_operand" "v")] 129))
1291    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1292   "TARGET_ALTIVEC"
1293   "vsubuws %0,%1,%2"
1294   [(set_attr "type" "vecsimple")])
1295
1296 (define_insn "altivec_vsubsws"
1297   [(set (match_operand:V4SI 0 "register_operand" "=v")
1298         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1299                       (match_operand:V4SI 2 "register_operand" "v")] 130))
1300    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1301   "TARGET_ALTIVEC"
1302   "vsubsws %0,%1,%2"
1303   [(set_attr "type" "vecsimple")])
1304
1305 (define_insn "altivec_vsum4ubs"
1306   [(set (match_operand:V4SI 0 "register_operand" "=v")
1307         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1308                       (match_operand:V4SI 2 "register_operand" "v")] 131))
1309    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1310   "TARGET_ALTIVEC"
1311   "vsum4ubs %0,%1,%2"
1312   [(set_attr "type" "veccomplex")])
1313
1314 (define_insn "altivec_vsum4sbs"
1315   [(set (match_operand:V4SI 0 "register_operand" "=v")
1316         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1317                       (match_operand:V4SI 2 "register_operand" "v")] 132))
1318    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1319   "TARGET_ALTIVEC"
1320   "vsum4sbs %0,%1,%2"
1321   [(set_attr "type" "veccomplex")])
1322
1323 (define_insn "altivec_vsum4shs"
1324   [(set (match_operand:V4SI 0 "register_operand" "=v")
1325         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1326                       (match_operand:V4SI 2 "register_operand" "v")] 133))
1327    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1328   "TARGET_ALTIVEC"
1329   "vsum4shs %0,%1,%2"
1330   [(set_attr "type" "veccomplex")])
1331
1332 (define_insn "altivec_vsum2sws"
1333   [(set (match_operand:V4SI 0 "register_operand" "=v")
1334         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1335                       (match_operand:V4SI 2 "register_operand" "v")] 134))
1336    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1337   "TARGET_ALTIVEC"
1338   "vsum2sws %0,%1,%2"
1339   [(set_attr "type" "veccomplex")])
1340
1341 (define_insn "altivec_vsumsws"
1342   [(set (match_operand:V4SI 0 "register_operand" "=v")
1343         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1344                       (match_operand:V4SI 2 "register_operand" "v")] 135))
1345    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1346   "TARGET_ALTIVEC"
1347   "vsumsws %0,%1,%2"
1348   [(set_attr "type" "veccomplex")])
1349
1350 ;; Vector xor's
1351 (define_insn "xorv4si3"
1352   [(set (match_operand:V4SI 0 "register_operand" "=v")
1353         (xor:V4SI (match_operand:V4SI 1 "register_operand" "v")
1354                   (match_operand:V4SI 2 "register_operand" "v")))]
1355   "TARGET_ALTIVEC"
1356   "vxor %0,%1,%2"
1357   [(set_attr "type" "vecsimple")])
1358
1359 (define_insn "xorv8hi3"
1360   [(set (match_operand:V8HI 0 "register_operand" "=v")
1361         (xor:V8HI (match_operand:V8HI 1 "register_operand" "v")
1362                   (match_operand:V8HI 2 "register_operand" "v")))]
1363   "TARGET_ALTIVEC"
1364   "vxor %0,%1,%2"
1365   [(set_attr "type" "vecsimple")])
1366
1367 (define_insn "xorv16qi3"
1368   [(set (match_operand:V16QI 0 "register_operand" "=v")
1369         (xor:V16QI (match_operand:V16QI 1 "register_operand" "v")
1370                    (match_operand:V16QI 2 "register_operand" "v")))]
1371   "TARGET_ALTIVEC"
1372   "vxor %0,%1,%2"
1373   [(set_attr "type" "vecsimple")])
1374
1375 (define_insn "altivec_vspltb"
1376   [(set (match_operand:V16QI 0 "register_operand" "=v")
1377         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1378                        (match_operand:QI 2 "immediate_operand" "i")] 136))]
1379   "TARGET_ALTIVEC"
1380   "vspltb %0,%1,%2"
1381   [(set_attr "type" "vecperm")])
1382 ;; End of vector xor's
1383
1384 (define_insn "altivec_vsplth"
1385   [(set (match_operand:V8HI 0 "register_operand" "=v")
1386         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1387                       (match_operand:QI 2 "immediate_operand" "i")] 137))]
1388   "TARGET_ALTIVEC"
1389   "vsplth %0,%1,%2"
1390   [(set_attr "type" "vecperm")])
1391
1392 (define_insn "altivec_vspltw"
1393   [(set (match_operand:V4SI 0 "register_operand" "=v")
1394         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1395                       (match_operand:QI 2 "immediate_operand" "i")] 138))]
1396   "TARGET_ALTIVEC"
1397   "vspltw %0,%1,%2"
1398   [(set_attr "type" "vecperm")])
1399
1400 (define_insn "altivec_vspltisb"
1401   [(set (match_operand:V16QI 0 "register_operand" "=v")
1402         (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")]
1403                       UNSPEC_VSPLTISB))]
1404   "TARGET_ALTIVEC"
1405   "vspltisb %0,%1"
1406   [(set_attr "type" "vecperm")])
1407
1408 (define_insn "altivec_vspltish"
1409   [(set (match_operand:V8HI 0 "register_operand" "=v")
1410         (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")]
1411                      UNSPEC_VSPLTISH))]
1412   "TARGET_ALTIVEC"
1413   "vspltish %0,%1"
1414   [(set_attr "type" "vecperm")])
1415
1416 (define_insn "altivec_vspltisw"
1417   [(set (match_operand:V4SI 0 "register_operand" "=v")
1418         (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")]
1419                      UNSPEC_VSPLTISW))]
1420   "TARGET_ALTIVEC"
1421   "vspltisw %0,%1"
1422   [(set_attr "type" "vecperm")])
1423
1424 (define_insn "altivec_vspltisw_v4sf"
1425   [(set (match_operand:V4SF 0 "register_operand" "=v")
1426         (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
1427   "TARGET_ALTIVEC"
1428   "vspltisw %0,%1"
1429   [(set_attr "type" "vecperm")])
1430
1431 (define_insn "ftruncv4sf2"
1432   [(set (match_operand:V4SF 0 "register_operand" "=v")
1433         (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1434   "TARGET_ALTIVEC"
1435   "vrfiz %0,%1"
1436   [(set_attr "type" "vecfloat")])
1437
1438 (define_insn "altivec_vperm_4si"
1439   [(set (match_operand:V4SI 0 "register_operand" "=v")
1440         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1441                       (match_operand:V4SI 2 "register_operand" "v")
1442                       (match_operand:V16QI 3 "register_operand" "v")] 144))]
1443   "TARGET_ALTIVEC"
1444   "vperm %0,%1,%2,%3"
1445   [(set_attr "type" "vecperm")])
1446
1447 (define_insn "altivec_vperm_4sf"
1448   [(set (match_operand:V4SF 0 "register_operand" "=v")
1449         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1450                       (match_operand:V4SF 2 "register_operand" "v")
1451                       (match_operand:V16QI 3 "register_operand" "v")] 145))]
1452   "TARGET_ALTIVEC"
1453   "vperm %0,%1,%2,%3"
1454   [(set_attr "type" "vecperm")])
1455
1456 (define_insn "altivec_vperm_8hi"
1457   [(set (match_operand:V8HI 0 "register_operand" "=v")
1458         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1459                       (match_operand:V8HI 2 "register_operand" "v")
1460                       (match_operand:V16QI 3 "register_operand" "v")] 146))]
1461   "TARGET_ALTIVEC"
1462   "vperm %0,%1,%2,%3"
1463   [(set_attr "type" "vecperm")])
1464
1465 (define_insn "altivec_vperm_16qi"
1466   [(set (match_operand:V16QI 0 "register_operand" "=v")
1467         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1468                        (match_operand:V16QI 2 "register_operand" "v")
1469                        (match_operand:V16QI 3 "register_operand" "v")] 147))]
1470   "TARGET_ALTIVEC"
1471   "vperm %0,%1,%2,%3"
1472   [(set_attr "type" "vecperm")])
1473
1474 (define_insn "altivec_vrfip"
1475   [(set (match_operand:V4SF 0 "register_operand" "=v")
1476         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
1477   "TARGET_ALTIVEC"
1478   "vrfip %0,%1"
1479   [(set_attr "type" "vecfloat")])
1480
1481 (define_insn "altivec_vrfin"
1482   [(set (match_operand:V4SF 0 "register_operand" "=v")
1483         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
1484   "TARGET_ALTIVEC"
1485   "vrfin %0,%1"
1486   [(set_attr "type" "vecfloat")])
1487
1488 (define_insn "altivec_vrfim"
1489   [(set (match_operand:V4SF 0 "register_operand" "=v")
1490         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
1491   "TARGET_ALTIVEC"
1492   "vrfim %0,%1"
1493   [(set_attr "type" "vecfloat")])
1494
1495 (define_insn "altivec_vcfux"
1496   [(set (match_operand:V4SF 0 "register_operand" "=v")
1497         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1498                       (match_operand:QI 2 "immediate_operand" "i")] 151))]
1499   "TARGET_ALTIVEC"
1500   "vcfux %0,%1,%2"
1501   [(set_attr "type" "vecfloat")])
1502
1503 (define_insn "altivec_vcfsx"
1504   [(set (match_operand:V4SF 0 "register_operand" "=v")
1505         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1506                       (match_operand:QI 2 "immediate_operand" "i")] 152))]
1507   "TARGET_ALTIVEC"
1508   "vcfsx %0,%1,%2"
1509   [(set_attr "type" "vecfloat")])
1510
1511 (define_insn "altivec_vctuxs"
1512   [(set (match_operand:V4SI 0 "register_operand" "=v")
1513         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1514                       (match_operand:QI 2 "immediate_operand" "i")] 153))
1515    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1516   "TARGET_ALTIVEC"
1517   "vctuxs %0,%1,%2"
1518   [(set_attr "type" "vecfloat")])
1519
1520 (define_insn "altivec_vctsxs"
1521   [(set (match_operand:V4SI 0 "register_operand" "=v")
1522         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1523                       (match_operand:QI 2 "immediate_operand" "i")] 154))
1524    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1525   "TARGET_ALTIVEC"
1526   "vctsxs %0,%1,%2"
1527   [(set_attr "type" "vecfloat")])
1528
1529 (define_insn "altivec_vlogefp"
1530   [(set (match_operand:V4SF 0 "register_operand" "=v")
1531         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
1532   "TARGET_ALTIVEC"
1533   "vlogefp %0,%1"
1534   [(set_attr "type" "vecfloat")])
1535
1536 (define_insn "altivec_vexptefp"
1537   [(set (match_operand:V4SF 0 "register_operand" "=v")
1538         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
1539   "TARGET_ALTIVEC"
1540   "vexptefp %0,%1"
1541   [(set_attr "type" "vecfloat")])
1542
1543 (define_insn "altivec_vrsqrtefp"
1544   [(set (match_operand:V4SF 0 "register_operand" "=v")
1545         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
1546   "TARGET_ALTIVEC"
1547   "vrsqrtefp %0,%1"
1548   [(set_attr "type" "vecfloat")])
1549
1550 (define_insn "altivec_vrefp"
1551   [(set (match_operand:V4SF 0 "register_operand" "=v")
1552         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
1553   "TARGET_ALTIVEC"
1554   "vrefp %0,%1"
1555   [(set_attr "type" "vecfloat")])
1556
1557 (define_insn "altivec_vsel_4si"
1558   [(set (match_operand:V4SI 0 "register_operand" "=v")
1559         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1560                       (match_operand:V4SI 2 "register_operand" "v")
1561                       (match_operand:V4SI 3 "register_operand" "v")] 159))]
1562   "TARGET_ALTIVEC"
1563   "vsel %0,%1,%2,%3"
1564   [(set_attr "type" "vecperm")])
1565
1566 (define_insn "altivec_vsel_4sf"
1567   [(set (match_operand:V4SF 0 "register_operand" "=v")
1568         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1569                       (match_operand:V4SF 2 "register_operand" "v")
1570                       (match_operand:V4SI 3 "register_operand" "v")] 160))]
1571   "TARGET_ALTIVEC"
1572   "vsel %0,%1,%2,%3"
1573   [(set_attr "type" "vecperm")])
1574
1575 (define_insn "altivec_vsel_8hi"
1576   [(set (match_operand:V8HI 0 "register_operand" "=v")
1577         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1578                       (match_operand:V8HI 2 "register_operand" "v")
1579                       (match_operand:V8HI 3 "register_operand" "v")] 161))]
1580   "TARGET_ALTIVEC"
1581   "vsel %0,%1,%2,%3"
1582   [(set_attr "type" "vecperm")])
1583
1584 (define_insn "altivec_vsel_16qi"
1585   [(set (match_operand:V16QI 0 "register_operand" "=v")
1586         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1587                        (match_operand:V16QI 2 "register_operand" "v")
1588                        (match_operand:V16QI 3 "register_operand" "v")] 162))]
1589   "TARGET_ALTIVEC"
1590   "vsel %0,%1,%2,%3"
1591   [(set_attr "type" "vecperm")])
1592
1593 (define_insn "altivec_vsldoi_4si"
1594   [(set (match_operand:V4SI 0 "register_operand" "=v")
1595         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1596                       (match_operand:V4SI 2 "register_operand" "v")
1597                       (match_operand:QI 3 "immediate_operand" "i")] 163))]
1598   "TARGET_ALTIVEC"
1599   "vsldoi %0,%1,%2,%3"
1600   [(set_attr "type" "vecperm")])
1601
1602 (define_insn "altivec_vsldoi_4sf"
1603   [(set (match_operand:V4SF 0 "register_operand" "=v")
1604         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1605                       (match_operand:V4SF 2 "register_operand" "v")
1606                       (match_operand:QI 3 "immediate_operand" "i")] 164))]
1607   "TARGET_ALTIVEC"
1608   "vsldoi %0,%1,%2,%3"
1609   [(set_attr "type" "vecperm")])
1610
1611 (define_insn "altivec_vsldoi_8hi"
1612   [(set (match_operand:V8HI 0 "register_operand" "=v")
1613         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1614                       (match_operand:V8HI 2 "register_operand" "v")
1615                       (match_operand:QI 3 "immediate_operand" "i")] 165))]
1616   "TARGET_ALTIVEC"
1617   "vsldoi %0,%1,%2,%3"
1618   [(set_attr "type" "vecperm")])
1619
1620 (define_insn "altivec_vsldoi_16qi"
1621   [(set (match_operand:V16QI 0 "register_operand" "=v")
1622         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1623                        (match_operand:V16QI 2 "register_operand" "v")
1624                        (match_operand:QI 3 "immediate_operand" "i")] 166))]
1625   "TARGET_ALTIVEC"
1626   "vsldoi %0,%1,%2,%3"
1627   [(set_attr "type" "vecperm")])
1628
1629 (define_insn "altivec_vupkhsb"
1630   [(set (match_operand:V8HI 0 "register_operand" "=v")
1631         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
1632   "TARGET_ALTIVEC"
1633   "vupkhsb %0,%1"
1634   [(set_attr "type" "vecperm")])
1635
1636 (define_insn "altivec_vupkhpx"
1637   [(set (match_operand:V4SI 0 "register_operand" "=v")
1638         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
1639   "TARGET_ALTIVEC"
1640   "vupkhpx %0,%1"
1641   [(set_attr "type" "vecperm")])
1642
1643 (define_insn "altivec_vupkhsh"
1644   [(set (match_operand:V4SI 0 "register_operand" "=v")
1645         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
1646   "TARGET_ALTIVEC"
1647   "vupkhsh %0,%1"
1648   [(set_attr "type" "vecperm")])
1649
1650 (define_insn "altivec_vupklsb"
1651   [(set (match_operand:V8HI 0 "register_operand" "=v")
1652         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
1653   "TARGET_ALTIVEC"
1654   "vupklsb %0,%1"
1655   [(set_attr "type" "vecperm")])
1656
1657 (define_insn "altivec_vupklpx"
1658   [(set (match_operand:V4SI 0 "register_operand" "=v")
1659         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
1660   "TARGET_ALTIVEC"
1661   "vupklpx %0,%1"
1662   [(set_attr "type" "vecperm")])
1663
1664 (define_insn "altivec_vupklsh"
1665   [(set (match_operand:V4SI 0 "register_operand" "=v")
1666         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
1667   "TARGET_ALTIVEC"
1668   "vupklsh %0,%1"
1669   [(set_attr "type" "vecperm")])
1670
1671 ;; AltiVec predicates.
1672
1673 (define_expand "cr6_test_for_zero"
1674   [(set (match_operand:SI 0 "register_operand" "=r")
1675         (eq:SI (reg:CC 74)
1676                (const_int 0)))]
1677   "TARGET_ALTIVEC"
1678   "")
1679
1680 (define_expand "cr6_test_for_zero_reverse"
1681   [(set (match_operand:SI 0 "register_operand" "=r")
1682         (eq:SI (reg:CC 74)
1683                (const_int 0)))
1684    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1685   "TARGET_ALTIVEC"
1686   "")
1687
1688 (define_expand "cr6_test_for_lt"
1689   [(set (match_operand:SI 0 "register_operand" "=r")
1690         (lt:SI (reg:CC 74)
1691                (const_int 0)))]
1692   "TARGET_ALTIVEC"
1693   "")
1694
1695 (define_expand "cr6_test_for_lt_reverse"
1696   [(set (match_operand:SI 0 "register_operand" "=r")
1697         (lt:SI (reg:CC 74)
1698                (const_int 0)))
1699    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1700   "TARGET_ALTIVEC"
1701   "")
1702
1703 ;; We can get away with generating the opcode on the fly (%3 below)
1704 ;; because all the predicates have the same scheduling parameters.
1705
1706 (define_insn "altivec_predicate_v4si"
1707   [(set (reg:CC 74)
1708         (unspec:CC [(match_operand:V4SI 1 "register_operand" "v")
1709                     (match_operand:V4SI 2 "register_operand" "v")
1710                     (match_operand 3 "any_operand" "")] 173))
1711    (clobber (match_scratch:V4SI 0 "=v"))]
1712   "TARGET_ALTIVEC"
1713   "%3 %0,%1,%2"
1714 [(set_attr "type" "veccmp")])
1715
1716 (define_insn "altivec_predicate_v4sf"
1717   [(set (reg:CC 74)
1718         (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1719                     (match_operand:V4SF 2 "register_operand" "v")
1720                     (match_operand 3 "any_operand" "")] 174))
1721    (clobber (match_scratch:V4SF 0 "=v"))]
1722   "TARGET_ALTIVEC"
1723   "%3 %0,%1,%2"
1724 [(set_attr "type" "veccmp")])
1725
1726 (define_insn "altivec_predicate_v8hi"
1727   [(set (reg:CC 74)
1728         (unspec:CC [(match_operand:V8HI 1 "register_operand" "v")
1729                     (match_operand:V8HI 2 "register_operand" "v")
1730                     (match_operand 3 "any_operand" "")] 175))
1731    (clobber (match_scratch:V8HI 0 "=v"))]
1732   "TARGET_ALTIVEC"
1733   "%3 %0,%1,%2"
1734 [(set_attr "type" "veccmp")])
1735
1736 (define_insn "altivec_predicate_v16qi"
1737   [(set (reg:CC 74)
1738         (unspec:CC [(match_operand:V16QI 1 "register_operand" "v")
1739                     (match_operand:V16QI 2 "register_operand" "v")
1740                     (match_operand 3 "any_operand" "")] 175))
1741    (clobber (match_scratch:V16QI 0 "=v"))]
1742   "TARGET_ALTIVEC"
1743   "%3 %0,%1,%2"
1744 [(set_attr "type" "veccmp")])
1745
1746 (define_insn "altivec_mtvscr"
1747   [(set (reg:SI 110)
1748         (unspec_volatile:SI
1749          [(match_operand:V4SI 0 "register_operand" "v")] 186))]
1750   "TARGET_ALTIVEC"
1751   "mtvscr %0"
1752   [(set_attr "type" "vecsimple")])
1753
1754 (define_insn "altivec_mfvscr"
1755   [(set (match_operand:V8HI 0 "register_operand" "=v")
1756         (unspec_volatile:V8HI [(reg:SI 110)] 187))]
1757   "TARGET_ALTIVEC"
1758   "mfvscr %0"
1759   [(set_attr "type" "vecsimple")])
1760
1761 (define_insn "altivec_dssall"
1762   [(unspec [(const_int 0)] 188)]
1763   "TARGET_ALTIVEC"
1764   "dssall"
1765   [(set_attr "type" "vecsimple")])
1766
1767 (define_insn "altivec_dss"
1768   [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)]
1769   "TARGET_ALTIVEC"
1770   "dss %0"
1771   [(set_attr "type" "vecsimple")])
1772
1773 (define_insn "altivec_dst"
1774   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1775             (match_operand:SI 1 "register_operand" "r")
1776             (match_operand:QI 2 "immediate_operand" "i")] 190)]
1777   "TARGET_ALTIVEC"
1778   "dst %P0,%1,%2"
1779   [(set_attr "type" "vecsimple")])
1780
1781 (define_insn "altivec_dstt"
1782   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1783             (match_operand:SI 1 "register_operand" "r")
1784             (match_operand:QI 2 "immediate_operand" "i")] 191)]
1785   "TARGET_ALTIVEC"
1786   "dstt %P0,%1,%2"
1787   [(set_attr "type" "vecsimple")])
1788
1789 (define_insn "altivec_dstst"
1790   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1791             (match_operand:SI 1 "register_operand" "r")
1792             (match_operand:QI 2 "immediate_operand" "i")] 192)]
1793   "TARGET_ALTIVEC"
1794   "dstst %P0,%1,%2"
1795   [(set_attr "type" "vecsimple")])
1796
1797 (define_insn "altivec_dststt"
1798   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1799             (match_operand:SI 1 "register_operand" "r")
1800             (match_operand:QI 2 "immediate_operand" "i")] 193)]
1801   "TARGET_ALTIVEC"
1802   "dststt %P0,%1,%2"
1803   [(set_attr "type" "vecsimple")])
1804
1805 (define_insn "altivec_lvsl"
1806   [(set (match_operand:V16QI 0 "register_operand" "=v")
1807         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 194))]
1808   "TARGET_ALTIVEC"
1809   "lvsl %0,%y1"
1810   [(set_attr "type" "vecload")])
1811
1812 (define_insn "altivec_lvsr"
1813   [(set (match_operand:V16QI 0 "register_operand" "=v")
1814         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
1815   "TARGET_ALTIVEC"
1816   "lvsr %0,%y1"
1817   [(set_attr "type" "vecload")])
1818
1819 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1820 ;; identical rtl but different instructions-- and gcc gets confused.
1821
1822 (define_insn "altivec_lvebx"
1823   [(parallel
1824     [(set (match_operand:V16QI 0 "register_operand" "=v")
1825           (match_operand:V16QI 1 "memory_operand" "m"))
1826      (unspec [(const_int 0)] 196)])]
1827   "TARGET_ALTIVEC"
1828   "lvebx %0,%y1"
1829   [(set_attr "type" "vecload")])
1830
1831 (define_insn "altivec_lvehx"
1832   [(parallel
1833     [(set (match_operand:V8HI 0 "register_operand" "=v")
1834           (match_operand:V8HI 1 "memory_operand" "m"))
1835      (unspec [(const_int 0)] 197)])]
1836   "TARGET_ALTIVEC"
1837   "lvehx %0,%y1"
1838   [(set_attr "type" "vecload")])
1839
1840 (define_insn "altivec_lvewx"
1841   [(parallel
1842     [(set (match_operand:V4SI 0 "register_operand" "=v")
1843           (match_operand:V4SI 1 "memory_operand" "m"))
1844      (unspec [(const_int 0)] 198)])]
1845   "TARGET_ALTIVEC"
1846   "lvewx %0,%y1"
1847   [(set_attr "type" "vecload")])
1848
1849 (define_insn "altivec_lvxl"
1850   [(parallel
1851     [(set (match_operand:V4SI 0 "register_operand" "=v")
1852           (match_operand:V4SI 1 "memory_operand" "m"))
1853      (unspec [(const_int 0)] 213)])]
1854   "TARGET_ALTIVEC"
1855   "lvxl %0,%y1"
1856   [(set_attr "type" "vecload")])
1857
1858 (define_insn "altivec_lvx"
1859   [(set (match_operand:V4SI 0 "register_operand" "=v")
1860         (match_operand:V4SI 1 "memory_operand" "m"))]
1861   "TARGET_ALTIVEC"
1862   "lvx %0,%y1"
1863   [(set_attr "type" "vecload")])
1864
1865 (define_insn "altivec_stvx"
1866   [(parallel
1867     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1868           (match_operand:V4SI 1 "register_operand" "v"))
1869      (unspec [(const_int 0)] 201)])]
1870   "TARGET_ALTIVEC"
1871   "stvx %1,%y0"
1872   [(set_attr "type" "vecstore")])
1873
1874 (define_insn "altivec_stvxl"
1875   [(parallel
1876     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1877           (match_operand:V4SI 1 "register_operand" "v"))
1878      (unspec [(const_int 0)] 202)])]
1879   "TARGET_ALTIVEC"
1880   "stvxl %1,%y0"
1881   [(set_attr "type" "vecstore")])
1882
1883 (define_insn "altivec_stvebx"
1884   [(parallel
1885     [(set (match_operand:V16QI 0 "memory_operand" "=m")
1886           (match_operand:V16QI 1 "register_operand" "v"))
1887      (unspec [(const_int 0)] 203)])]
1888   "TARGET_ALTIVEC"
1889   "stvebx %1,%y0"
1890   [(set_attr "type" "vecstore")])
1891
1892 (define_insn "altivec_stvehx"
1893   [(parallel
1894     [(set (match_operand:V8HI 0 "memory_operand" "=m")
1895           (match_operand:V8HI 1 "register_operand" "v"))
1896      (unspec [(const_int 0)] 204)])]
1897   "TARGET_ALTIVEC"
1898   "stvehx %1,%y0"
1899   [(set_attr "type" "vecstore")])
1900
1901 (define_insn "altivec_stvewx"
1902   [(parallel
1903     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1904           (match_operand:V4SI 1 "register_operand" "v"))
1905      (unspec [(const_int 0)] 205)])]
1906   "TARGET_ALTIVEC"
1907   "stvewx %1,%y0"
1908   [(set_attr "type" "vecstore")])
1909
1910 (define_insn "absv16qi2"
1911   [(set (match_operand:V16QI 0 "register_operand" "=v")
1912         (abs:V16QI (match_operand:V16QI 1 "register_operand" "v")))
1913    (clobber (match_scratch:V16QI 2 "=&v"))
1914    (clobber (match_scratch:V16QI 3 "=&v"))]
1915   "TARGET_ALTIVEC"
1916   "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3"
1917   [(set_attr "type" "vecsimple")
1918    (set_attr "length" "12")])
1919
1920 (define_insn "absv8hi2"
1921   [(set (match_operand:V8HI 0 "register_operand" "=v")
1922         (abs:V8HI (match_operand:V8HI 1 "register_operand" "v")))
1923    (clobber (match_scratch:V8HI 2 "=&v"))
1924    (clobber (match_scratch:V8HI 3 "=&v"))]
1925   "TARGET_ALTIVEC"
1926   "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3"
1927   [(set_attr "type" "vecsimple")
1928    (set_attr "length" "12")])
1929
1930 (define_insn "absv4si2"
1931   [(set (match_operand:V4SI 0 "register_operand" "=v")
1932         (abs:V4SI (match_operand:V4SI 1 "register_operand" "v")))
1933    (clobber (match_scratch:V4SI 2 "=&v"))
1934    (clobber (match_scratch:V4SI 3 "=&v"))]
1935   "TARGET_ALTIVEC"
1936   "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3"
1937   [(set_attr "type" "vecsimple")
1938    (set_attr "length" "12")])
1939
1940 (define_insn "absv4sf2"
1941   [(set (match_operand:V4SF 0 "register_operand" "=v")
1942         (abs:V4SF (match_operand:V4SF 1 "register_operand" "v")))
1943    (clobber (match_scratch:V4SF 2 "=&v"))
1944    (clobber (match_scratch:V4SF 3 "=&v"))]
1945   "TARGET_ALTIVEC"
1946   "vspltisw %2,-1\;vslw %3,%2,%2\;vandc %0,%1,%3"
1947   [(set_attr "type" "vecsimple")
1948    (set_attr "length" "12")])
1949
1950 (define_insn "altivec_abss_v16qi"
1951   [(set (match_operand:V16QI 0 "register_operand" "=v")
1952         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210))
1953    (clobber (match_scratch:V16QI 2 "=&v"))
1954    (clobber (match_scratch:V16QI 3 "=&v"))]
1955   "TARGET_ALTIVEC"
1956   "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3"
1957   [(set_attr "type" "vecsimple")
1958    (set_attr "length" "12")])
1959
1960 (define_insn "altivec_abss_v8hi"
1961   [(set (match_operand:V8HI 0 "register_operand" "=v")
1962         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211))
1963    (clobber (match_scratch:V8HI 2 "=&v"))
1964    (clobber (match_scratch:V8HI 3 "=&v"))]
1965   "TARGET_ALTIVEC"
1966   "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3"
1967   [(set_attr "type" "vecsimple")
1968    (set_attr "length" "12")])
1969
1970 (define_insn "altivec_abss_v4si"
1971   [(set (match_operand:V4SI 0 "register_operand" "=v")
1972         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212))
1973    (clobber (match_scratch:V4SI 2 "=&v"))
1974    (clobber (match_scratch:V4SI 3 "=&v"))]
1975   "TARGET_ALTIVEC"
1976   "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3"
1977   [(set_attr "type" "vecsimple")
1978    (set_attr "length" "12")])