1 ;; Scheduling description for Motorola PowerPC 7450 processor.
2 ;; Copyright (C) 2003 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 2, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to the
18 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 ;; MA 02111-1307, USA.
21 (define_automaton "ppc7450,ppc7450fp,ppc7450vec")
22 (define_cpu_unit "iu1_7450,iu2_7450,iu3_7450,mciu_7450" "ppc7450")
23 (define_cpu_unit "fpu_7450" "ppc7450fp")
24 (define_cpu_unit "lsu_7450,bpu_7450" "ppc7450")
25 (define_cpu_unit "du1_7450,du2_7450,du3_7450" "ppc7450")
26 (define_cpu_unit "vecsmpl_7450,veccmplx_7450,vecflt_7450,vecperm_7450" "ppc7450vec")
27 (define_cpu_unit "vdu1_7450,vdu2_7450" "ppc7450vec")
30 ;; PPC7450 32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC
31 ;; IU1,IU2,IU3 can perform all integer operations
32 ;; MCIU performs imul and idiv, cr logical, SPR moves
33 ;; LSU 2 stage pipelined
34 ;; FPU 3 stage pipelined
35 ;; It also has 4 vector units, one for each type of vector instruction.
36 ;; However, we can only dispatch 2 instructions per cycle.
37 ;; Max issue 3 insns/clock cycle (includes 1 branch)
40 ;; Branches go straight to the BPU. All other insns are handled
41 ;; by a dispatch unit which can issue a max of 3 insns per cycle.
42 (define_reservation "ppc7450_du" "du1_7450|du2_7450|du3_7450")
43 (define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
45 (define_insn_reservation "ppc7450-load" 3
46 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\
47 load_ux,load_u,vecload")
48 (eq_attr "cpu" "ppc7450"))
49 "ppc7450_du,lsu_7450")
51 (define_insn_reservation "ppc7450-store" 3
52 (and (eq_attr "type" "store,store_ux,store_u,vecstore")
53 (eq_attr "cpu" "ppc7450"))
54 "ppc7450_du,lsu_7450")
56 (define_insn_reservation "ppc7450-fpload" 4
57 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
58 (eq_attr "cpu" "ppc7450"))
59 "ppc7450_du,lsu_7450")
61 (define_insn_reservation "ppc7450-fpstore" 3
62 (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
63 (eq_attr "cpu" "ppc7450"))
64 "ppc7450_du,lsu_7450*3")
66 (define_insn_reservation "ppc7450-integer" 1
67 (and (eq_attr "type" "integer,insert_word")
68 (eq_attr "cpu" "ppc7450"))
69 "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
71 (define_insn_reservation "ppc7450-imul" 4
72 (and (eq_attr "type" "imul,imul_compare")
73 (eq_attr "cpu" "ppc7450"))
74 "ppc7450_du,mciu_7450*2")
76 (define_insn_reservation "ppc7450-imul2" 3
77 (and (eq_attr "type" "imul2,imul3")
78 (eq_attr "cpu" "ppc7450"))
79 "ppc7450_du,mciu_7450")
81 (define_insn_reservation "ppc7450-idiv" 23
82 (and (eq_attr "type" "idiv")
83 (eq_attr "cpu" "ppc7450"))
84 "ppc7450_du,mciu_7450*23")
86 (define_insn_reservation "ppc7450-compare" 2
87 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
88 (eq_attr "cpu" "ppc7450"))
89 "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
91 (define_insn_reservation "ppc7450-fpcompare" 5
92 (and (eq_attr "type" "fpcompare")
93 (eq_attr "cpu" "ppc7450"))
94 "ppc7450_du,fpu_7450")
96 (define_insn_reservation "ppc7450-fp" 5
97 (and (eq_attr "type" "fp,dmul")
98 (eq_attr "cpu" "ppc7450"))
99 "ppc7450_du,fpu_7450")
101 ; Divides are not pipelined
102 (define_insn_reservation "ppc7450-sdiv" 21
103 (and (eq_attr "type" "sdiv")
104 (eq_attr "cpu" "ppc7450"))
105 "ppc7450_du,fpu_7450*21")
107 (define_insn_reservation "ppc7450-ddiv" 35
108 (and (eq_attr "type" "ddiv")
109 (eq_attr "cpu" "ppc7450"))
110 "ppc7450_du,fpu_7450*35")
112 (define_insn_reservation "ppc7450-mfcr" 2
113 (and (eq_attr "type" "mfcr,mtcr")
114 (eq_attr "cpu" "ppc7450"))
115 "ppc7450_du,mciu_7450")
117 (define_insn_reservation "ppc7450-crlogical" 1
118 (and (eq_attr "type" "cr_logical,delayed_cr")
119 (eq_attr "cpu" "ppc7450"))
120 "ppc7450_du,mciu_7450")
122 (define_insn_reservation "ppc7450-mtjmpr" 2
123 (and (eq_attr "type" "mtjmpr")
124 (eq_attr "cpu" "ppc7450"))
125 "nothing,mciu_7450*2")
127 (define_insn_reservation "ppc7450-mfjmpr" 3
128 (and (eq_attr "type" "mfjmpr")
129 (eq_attr "cpu" "ppc7450"))
130 "nothing,mciu_7450*2")
132 (define_insn_reservation "ppc7450-jmpreg" 1
133 (and (eq_attr "type" "jmpreg,branch")
134 (eq_attr "cpu" "ppc7450"))
138 (define_insn_reservation "ppc7450-vecsimple" 1
139 (and (eq_attr "type" "vecsimple")
140 (eq_attr "cpu" "ppc7450"))
141 "ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
143 (define_insn_reservation "ppc7450-veccomplex" 4
144 (and (eq_attr "type" "veccomplex")
145 (eq_attr "cpu" "ppc7450"))
146 "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
148 (define_insn_reservation "ppc7450-veccmp" 2
149 (and (eq_attr "type" "veccmp")
150 (eq_attr "cpu" "ppc7450"))
151 "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
153 (define_insn_reservation "ppc7450-vecfloat" 4
154 (and (eq_attr "type" "vecfloat")
155 (eq_attr "cpu" "ppc7450"))
156 "ppc7450_du,ppc7450_vec_du,vecflt_7450")
158 (define_insn_reservation "ppc7450-vecperm" 2
159 (and (eq_attr "type" "vecperm")
160 (eq_attr "cpu" "ppc7450"))
161 "ppc7450_du,ppc7450_vec_du,vecperm_7450")