1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
45 #include "target-def.h"
47 /* This is used by GOTaddr2picreg to uniquely identify
49 int mn10300_unspec_int_label_counter
;
51 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
52 names are not prefixed by underscores, to tell whether to prefix a
53 label with a plus sign or not, so that the assembler can tell
54 symbol names from register names. */
55 int mn10300_protect_label
;
57 /* The size of the callee register save area. Right now we save everything
58 on entry since it costs us nothing in code size. It does cost us from a
59 speed standpoint, so we want to optimize this sooner or later. */
60 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
61 + 4 * regs_ever_live[3] \
62 + 4 * regs_ever_live[6] \
63 + 4 * regs_ever_live[7] \
64 + 16 * (regs_ever_live[14] || regs_ever_live[15] \
65 || regs_ever_live[16] || regs_ever_live[17]))
68 static int mn10300_address_cost_1 (rtx
, int *);
69 static int mn10300_address_cost (rtx
);
70 static bool mn10300_rtx_costs (rtx
, int, int, int *);
71 static void mn10300_file_start (void);
74 /* Initialize the GCC target structure. */
75 #undef TARGET_ASM_ALIGNED_HI_OP
76 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
78 #undef TARGET_RTX_COSTS
79 #define TARGET_RTX_COSTS mn10300_rtx_costs
80 #undef TARGET_ADDRESS_COST
81 #define TARGET_ADDRESS_COST mn10300_address_cost
83 #undef TARGET_ASM_FILE_START
84 #define TARGET_ASM_FILE_START mn10300_file_start
85 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
86 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
88 #undef TARGET_ENCODE_SECTION_INFO
89 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
91 static void mn10300_encode_section_info (tree
, rtx
, int);
92 struct gcc_target targetm
= TARGET_INITIALIZER
;
95 mn10300_file_start (void)
97 default_file_start ();
100 fprintf (asm_out_file
, "\t.am33_2\n");
101 else if (TARGET_AM33
)
102 fprintf (asm_out_file
, "\t.am33\n");
106 /* Print operand X using operand code CODE to assembly language output file
110 print_operand (FILE *file
, rtx x
, int code
)
116 if (cc_status
.mdep
.fpCC
)
118 switch (code
== 'b' ? GET_CODE (x
)
119 : reverse_condition_maybe_unordered (GET_CODE (x
)))
122 fprintf (file
, "ne");
125 fprintf (file
, "eq");
128 fprintf (file
, "ge");
131 fprintf (file
, "gt");
134 fprintf (file
, "le");
137 fprintf (file
, "lt");
140 fprintf (file
, "lge");
143 fprintf (file
, "uo");
146 fprintf (file
, "lg");
149 fprintf (file
, "ue");
152 fprintf (file
, "uge");
155 fprintf (file
, "ug");
158 fprintf (file
, "ule");
161 fprintf (file
, "ul");
168 /* These are normal and reversed branches. */
169 switch (code
== 'b' ? GET_CODE (x
) : reverse_condition (GET_CODE (x
)))
172 fprintf (file
, "ne");
175 fprintf (file
, "eq");
178 fprintf (file
, "ge");
181 fprintf (file
, "gt");
184 fprintf (file
, "le");
187 fprintf (file
, "lt");
190 fprintf (file
, "cc");
193 fprintf (file
, "hi");
196 fprintf (file
, "ls");
199 fprintf (file
, "cs");
206 /* This is used for the operand to a call instruction;
207 if it's a REG, enclose it in parens, else output
208 the operand normally. */
209 if (GET_CODE (x
) == REG
)
212 print_operand (file
, x
, 0);
216 print_operand (file
, x
, 0);
220 switch (GET_CODE (x
))
224 output_address (XEXP (x
, 0));
229 fprintf (file
, "fd%d", REGNO (x
) - 18);
237 /* These are the least significant word in a 64bit value. */
239 switch (GET_CODE (x
))
243 output_address (XEXP (x
, 0));
248 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
252 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
260 switch (GET_MODE (x
))
263 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
264 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
265 fprintf (file
, "0x%lx", val
[0]);
268 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
269 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
[0]);
270 fprintf (file
, "0x%lx", val
[0]);
274 print_operand_address (file
,
275 GEN_INT (CONST_DOUBLE_LOW (x
)));
286 split_double (x
, &low
, &high
);
287 fprintf (file
, "%ld", (long)INTVAL (low
));
296 /* Similarly, but for the most significant word. */
298 switch (GET_CODE (x
))
302 x
= adjust_address (x
, SImode
, 4);
303 output_address (XEXP (x
, 0));
308 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
312 fprintf (file
, "%s", reg_names
[subreg_regno (x
) + 1]);
320 switch (GET_MODE (x
))
323 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
324 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
325 fprintf (file
, "0x%lx", val
[1]);
331 print_operand_address (file
,
332 GEN_INT (CONST_DOUBLE_HIGH (x
)));
343 split_double (x
, &low
, &high
);
344 fprintf (file
, "%ld", (long)INTVAL (high
));
355 if (GET_CODE (XEXP (x
, 0)) == REG
)
356 output_address (gen_rtx_PLUS (SImode
, XEXP (x
, 0), GEN_INT (0)));
358 output_address (XEXP (x
, 0));
363 if (INTVAL (x
) < -128 || INTVAL (x
) > 255)
365 fprintf (file
, "%d", (int)((~INTVAL (x
)) & 0xff));
369 if (INTVAL (x
) < -128 || INTVAL (x
) > 255)
371 fprintf (file
, "%d", (int)(INTVAL (x
) & 0xff));
374 /* For shift counts. The hardware ignores the upper bits of
375 any immediate, but the assembler will flag an out of range
376 shift count as an error. So we mask off the high bits
377 of the immediate here. */
379 if (GET_CODE (x
) == CONST_INT
)
381 fprintf (file
, "%d", (int)(INTVAL (x
) & 0x1f));
387 switch (GET_CODE (x
))
391 output_address (XEXP (x
, 0));
400 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
404 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
407 /* This will only be single precision.... */
413 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
414 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
415 fprintf (file
, "0x%lx", val
);
425 print_operand_address (file
, x
);
434 /* Output assembly language output for the address ADDR to FILE. */
437 print_operand_address (FILE *file
, rtx addr
)
439 switch (GET_CODE (addr
))
442 print_operand_address (file
, XEXP (addr
, 0));
446 print_operand (file
, addr
, 0);
451 if (REG_P (XEXP (addr
, 0))
452 && REG_OK_FOR_BASE_P (XEXP (addr
, 0)))
453 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
454 else if (REG_P (XEXP (addr
, 1))
455 && REG_OK_FOR_BASE_P (XEXP (addr
, 1)))
456 base
= XEXP (addr
, 1), index
= XEXP (addr
, 0);
459 print_operand (file
, index
, 0);
461 print_operand (file
, base
, 0);;
465 output_addr_const (file
, addr
);
468 output_addr_const (file
, addr
);
473 /* Count the number of FP registers that have to be saved. */
475 fp_regs_to_save (void)
482 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
483 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
489 /* Print a set of registers in the format required by "movm" and "ret".
490 Register K is saved if bit K of MASK is set. The data and address
491 registers can be stored individually, but the extended registers cannot.
492 We assume that the mask alread takes that into account. For instance,
493 bits 14 to 17 must have the same value. */
496 mn10300_print_reg_list (FILE *file
, int mask
)
504 for (i
= 0; i
< FIRST_EXTENDED_REGNUM
; i
++)
505 if ((mask
& (1 << i
)) != 0)
509 fputs (reg_names
[i
], file
);
513 if ((mask
& 0x3c000) != 0)
515 if ((mask
& 0x3c000) != 0x3c000)
519 fputs ("exreg1", file
);
527 can_use_return_insn (void)
529 /* size includes the fixed stack space needed for function calls. */
530 int size
= get_frame_size () + current_function_outgoing_args_size
;
532 /* And space for the return pointer. */
533 size
+= current_function_outgoing_args_size
? 4 : 0;
535 return (reload_completed
537 && !regs_ever_live
[2]
538 && !regs_ever_live
[3]
539 && !regs_ever_live
[6]
540 && !regs_ever_live
[7]
541 && !regs_ever_live
[14]
542 && !regs_ever_live
[15]
543 && !regs_ever_live
[16]
544 && !regs_ever_live
[17]
545 && fp_regs_to_save () == 0
546 && !frame_pointer_needed
);
549 /* Returns the set of live, callee-saved registers as a bitmask. The
550 callee-saved extended registers cannot be stored individually, so
551 all of them will be included in the mask if any one of them is used. */
554 mn10300_get_live_callee_saved_regs (void)
560 for (i
= 0; i
<= LAST_EXTENDED_REGNUM
; i
++)
561 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
563 if ((mask
& 0x3c000) != 0)
569 /* Generate an instruction that pushes several registers onto the stack.
570 Register K will be saved if bit K in MASK is set. The function does
571 nothing if MASK is zero.
573 To be compatible with the "movm" instruction, the lowest-numbered
574 register must be stored in the lowest slot. If MASK is the set
575 { R1,...,RN }, where R1...RN are ordered least first, the generated
576 instruction will have the form:
579 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
580 (set (mem:SI (plus:SI (reg:SI 9)
584 (set (mem:SI (plus:SI (reg:SI 9)
589 mn10300_gen_multiple_store (int mask
)
598 /* Count how many registers need to be saved. */
600 for (i
= 0; i
<= LAST_EXTENDED_REGNUM
; i
++)
601 if ((mask
& (1 << i
)) != 0)
604 /* We need one PARALLEL element to update the stack pointer and
605 an additional element for each register that is stored. */
606 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
+ 1));
608 /* Create the instruction that updates the stack pointer. */
610 = gen_rtx_SET (SImode
,
612 gen_rtx_PLUS (SImode
,
614 GEN_INT (-count
* 4)));
616 /* Create each store. */
618 for (i
= LAST_EXTENDED_REGNUM
; i
>= 0; i
--)
619 if ((mask
& (1 << i
)) != 0)
621 rtx address
= gen_rtx_PLUS (SImode
,
623 GEN_INT (-pari
* 4));
624 XVECEXP(par
, 0, pari
)
625 = gen_rtx_SET (VOIDmode
,
626 gen_rtx_MEM (SImode
, address
),
627 gen_rtx_REG (SImode
, i
));
631 par
= emit_insn (par
);
632 RTX_FRAME_RELATED_P (par
) = 1;
637 expand_prologue (void)
641 /* SIZE includes the fixed stack space needed for function calls. */
642 size
= get_frame_size () + current_function_outgoing_args_size
;
643 size
+= (current_function_outgoing_args_size
? 4 : 0);
645 /* If we use any of the callee-saved registers, save them now. */
646 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
648 if (TARGET_AM33_2
&& fp_regs_to_save ())
650 int num_regs_to_save
= fp_regs_to_save (), i
;
652 enum { save_sp_merge
,
654 save_sp_partial_merge
,
656 save_a0_no_merge
} strategy
;
657 unsigned int strategy_size
= (unsigned)-1, this_strategy_size
;
661 /* We have several different strategies to save FP registers.
662 We can store them using SP offsets, which is beneficial if
663 there are just a few registers to save, or we can use `a0' in
664 post-increment mode (`a0' is the only call-clobbered address
665 register that is never used to pass information to a
666 function). Furthermore, if we don't need a frame pointer, we
667 can merge the two SP adds into a single one, but this isn't
668 always beneficial; sometimes we can just split the two adds
669 so that we don't exceed a 16-bit constant size. The code
670 below will select which strategy to use, so as to generate
671 smallest code. Ties are broken in favor or shorter sequences
672 (in terms of number of instructions). */
674 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
675 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
676 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
677 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
678 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
679 (((S) >= (L)) ? (SIZE1) * (N) \
680 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
681 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
683 #define SIZE_FMOV_SP_(S,N) \
684 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
685 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
686 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
687 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
689 /* Consider alternative save_sp_merge only if we don't need the
690 frame pointer and size is nonzero. */
691 if (! frame_pointer_needed
&& size
)
693 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
694 this_strategy_size
= SIZE_ADD_SP (-(size
+ 4 * num_regs_to_save
));
695 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
696 this_strategy_size
+= SIZE_FMOV_SP (size
, num_regs_to_save
);
698 if (this_strategy_size
< strategy_size
)
700 strategy
= save_sp_merge
;
701 strategy_size
= this_strategy_size
;
705 /* Consider alternative save_sp_no_merge unconditionally. */
706 /* Insn: add -4 * num_regs_to_save, sp. */
707 this_strategy_size
= SIZE_ADD_SP (-4 * num_regs_to_save
);
708 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
709 this_strategy_size
+= SIZE_FMOV_SP (0, num_regs_to_save
);
712 /* Insn: add -size, sp. */
713 this_strategy_size
+= SIZE_ADD_SP (-size
);
716 if (this_strategy_size
< strategy_size
)
718 strategy
= save_sp_no_merge
;
719 strategy_size
= this_strategy_size
;
722 /* Consider alternative save_sp_partial_merge only if we don't
723 need a frame pointer and size is reasonably large. */
724 if (! frame_pointer_needed
&& size
+ 4 * num_regs_to_save
> 128)
726 /* Insn: add -128, sp. */
727 this_strategy_size
= SIZE_ADD_SP (-128);
728 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
729 this_strategy_size
+= SIZE_FMOV_SP (128 - 4 * num_regs_to_save
,
733 /* Insn: add 128-size, sp. */
734 this_strategy_size
+= SIZE_ADD_SP (128 - size
);
737 if (this_strategy_size
< strategy_size
)
739 strategy
= save_sp_partial_merge
;
740 strategy_size
= this_strategy_size
;
744 /* Consider alternative save_a0_merge only if we don't need a
745 frame pointer, size is nonzero and the user hasn't
746 changed the calling conventions of a0. */
747 if (! frame_pointer_needed
&& size
748 && call_used_regs
[FIRST_ADDRESS_REGNUM
]
749 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
])
751 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
752 this_strategy_size
= SIZE_ADD_SP (-(size
+ 4 * num_regs_to_save
));
753 /* Insn: mov sp, a0. */
754 this_strategy_size
++;
757 /* Insn: add size, a0. */
758 this_strategy_size
+= SIZE_ADD_AX (size
);
760 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
761 this_strategy_size
+= 3 * num_regs_to_save
;
763 if (this_strategy_size
< strategy_size
)
765 strategy
= save_a0_merge
;
766 strategy_size
= this_strategy_size
;
770 /* Consider alternative save_a0_no_merge if the user hasn't
771 changed the calling conventions of a0. */
772 if (call_used_regs
[FIRST_ADDRESS_REGNUM
]
773 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
])
775 /* Insn: add -4 * num_regs_to_save, sp. */
776 this_strategy_size
= SIZE_ADD_SP (-4 * num_regs_to_save
);
777 /* Insn: mov sp, a0. */
778 this_strategy_size
++;
779 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
780 this_strategy_size
+= 3 * num_regs_to_save
;
783 /* Insn: add -size, sp. */
784 this_strategy_size
+= SIZE_ADD_SP (-size
);
787 if (this_strategy_size
< strategy_size
)
789 strategy
= save_a0_no_merge
;
790 strategy_size
= this_strategy_size
;
794 /* Emit the initial SP add, common to all strategies. */
797 case save_sp_no_merge
:
798 case save_a0_no_merge
:
799 emit_insn (gen_addsi3 (stack_pointer_rtx
,
801 GEN_INT (-4 * num_regs_to_save
)));
805 case save_sp_partial_merge
:
806 emit_insn (gen_addsi3 (stack_pointer_rtx
,
809 xsize
= 128 - 4 * num_regs_to_save
;
815 emit_insn (gen_addsi3 (stack_pointer_rtx
,
817 GEN_INT (-(size
+ 4 * num_regs_to_save
))));
818 /* We'll have to adjust FP register saves according to the
821 /* Since we've already created the stack frame, don't do it
822 again at the end of the function. */
830 /* Now prepare register a0, if we have decided to use it. */
834 case save_sp_no_merge
:
835 case save_sp_partial_merge
:
840 case save_a0_no_merge
:
841 reg
= gen_rtx_REG (SImode
, FIRST_ADDRESS_REGNUM
);
842 emit_insn (gen_movsi (reg
, stack_pointer_rtx
));
844 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (xsize
)));
845 reg
= gen_rtx_POST_INC (SImode
, reg
);
852 /* Now actually save the FP registers. */
853 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
854 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
862 /* If we aren't using `a0', use an SP offset. */
865 addr
= gen_rtx_PLUS (SImode
,
870 addr
= stack_pointer_rtx
;
875 insn
= emit_insn (gen_movsi (gen_rtx_MEM (SImode
, addr
),
876 gen_rtx_REG (SImode
, i
)));
878 RTX_FRAME_RELATED_P (insn
) = 1;
882 /* Now put the frame pointer into the frame pointer register. */
883 if (frame_pointer_needed
)
884 emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
886 /* Allocate stack for this frame. */
888 emit_insn (gen_addsi3 (stack_pointer_rtx
,
891 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
893 rtx insn
= get_last_insn ();
894 rtx last
= emit_insn (gen_GOTaddr2picreg ());
896 /* Mark these insns as possibly dead. Sometimes, flow2 may
897 delete all uses of the PIC register. In this case, let it
898 delete the initialization too. */
901 insn
= NEXT_INSN (insn
);
903 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
907 while (insn
!= last
);
912 expand_epilogue (void)
916 /* SIZE includes the fixed stack space needed for function calls. */
917 size
= get_frame_size () + current_function_outgoing_args_size
;
918 size
+= (current_function_outgoing_args_size
? 4 : 0);
920 if (TARGET_AM33_2
&& fp_regs_to_save ())
922 int num_regs_to_save
= fp_regs_to_save (), i
;
925 /* We have several options to restore FP registers. We could
926 load them from SP offsets, but, if there are enough FP
927 registers to restore, we win if we use a post-increment
930 /* If we have a frame pointer, it's the best option, because we
931 already know it has the value we want. */
932 if (frame_pointer_needed
)
933 reg
= gen_rtx_REG (SImode
, FRAME_POINTER_REGNUM
);
934 /* Otherwise, we may use `a1', since it's call-clobbered and
935 it's never used for return values. But only do so if it's
936 smaller than using SP offsets. */
939 enum { restore_sp_post_adjust
,
940 restore_sp_pre_adjust
,
941 restore_sp_partial_adjust
,
942 restore_a1
} strategy
;
943 unsigned int this_strategy_size
, strategy_size
= (unsigned)-1;
945 /* Consider using sp offsets before adjusting sp. */
946 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
947 this_strategy_size
= SIZE_FMOV_SP (size
, num_regs_to_save
);
948 /* If size is too large, we'll have to adjust SP with an
950 if (size
+ 4 * num_regs_to_save
+ REG_SAVE_BYTES
> 255)
952 /* Insn: add size + 4 * num_regs_to_save, sp. */
953 this_strategy_size
+= SIZE_ADD_SP (size
+ 4 * num_regs_to_save
);
955 /* If we don't have to restore any non-FP registers,
956 we'll be able to save one byte by using rets. */
957 if (! REG_SAVE_BYTES
)
958 this_strategy_size
--;
960 if (this_strategy_size
< strategy_size
)
962 strategy
= restore_sp_post_adjust
;
963 strategy_size
= this_strategy_size
;
966 /* Consider using sp offsets after adjusting sp. */
967 /* Insn: add size, sp. */
968 this_strategy_size
= SIZE_ADD_SP (size
);
969 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
970 this_strategy_size
+= SIZE_FMOV_SP (0, num_regs_to_save
);
971 /* We're going to use ret to release the FP registers
972 save area, so, no savings. */
974 if (this_strategy_size
< strategy_size
)
976 strategy
= restore_sp_pre_adjust
;
977 strategy_size
= this_strategy_size
;
980 /* Consider using sp offsets after partially adjusting sp.
981 When size is close to 32Kb, we may be able to adjust SP
982 with an imm16 add instruction while still using fmov
984 if (size
+ 4 * num_regs_to_save
+ REG_SAVE_BYTES
> 255)
986 /* Insn: add size + 4 * num_regs_to_save
987 + REG_SAVE_BYTES - 252,sp. */
988 this_strategy_size
= SIZE_ADD_SP (size
+ 4 * num_regs_to_save
989 + REG_SAVE_BYTES
- 252);
990 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
991 this_strategy_size
+= SIZE_FMOV_SP (252 - REG_SAVE_BYTES
992 - 4 * num_regs_to_save
,
994 /* We're going to use ret to release the FP registers
995 save area, so, no savings. */
997 if (this_strategy_size
< strategy_size
)
999 strategy
= restore_sp_partial_adjust
;
1000 strategy_size
= this_strategy_size
;
1004 /* Consider using a1 in post-increment mode, as long as the
1005 user hasn't changed the calling conventions of a1. */
1006 if (call_used_regs
[FIRST_ADDRESS_REGNUM
+1]
1007 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
+1])
1009 /* Insn: mov sp,a1. */
1010 this_strategy_size
= 1;
1013 /* Insn: add size,a1. */
1014 this_strategy_size
+= SIZE_ADD_AX (size
);
1016 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1017 this_strategy_size
+= 3 * num_regs_to_save
;
1018 /* If size is large enough, we may be able to save a
1020 if (size
+ 4 * num_regs_to_save
+ REG_SAVE_BYTES
> 255)
1022 /* Insn: mov a1,sp. */
1023 this_strategy_size
+= 2;
1025 /* If we don't have to restore any non-FP registers,
1026 we'll be able to save one byte by using rets. */
1027 if (! REG_SAVE_BYTES
)
1028 this_strategy_size
--;
1030 if (this_strategy_size
< strategy_size
)
1032 strategy
= restore_a1
;
1033 strategy_size
= this_strategy_size
;
1039 case restore_sp_post_adjust
:
1042 case restore_sp_pre_adjust
:
1043 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1049 case restore_sp_partial_adjust
:
1050 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1052 GEN_INT (size
+ 4 * num_regs_to_save
1053 + REG_SAVE_BYTES
- 252)));
1054 size
= 252 - REG_SAVE_BYTES
- 4 * num_regs_to_save
;
1058 reg
= gen_rtx_REG (SImode
, FIRST_ADDRESS_REGNUM
+ 1);
1059 emit_insn (gen_movsi (reg
, stack_pointer_rtx
));
1061 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
1069 /* Adjust the selected register, if any, for post-increment. */
1071 reg
= gen_rtx_POST_INC (SImode
, reg
);
1073 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
1074 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1082 /* If we aren't using a post-increment register, use an
1084 addr
= gen_rtx_PLUS (SImode
,
1089 addr
= stack_pointer_rtx
;
1093 emit_insn (gen_movsi (gen_rtx_REG (SImode
, i
),
1094 gen_rtx_MEM (SImode
, addr
)));
1097 /* If we were using the restore_a1 strategy and the number of
1098 bytes to be released won't fit in the `ret' byte, copy `a1'
1099 to `sp', to avoid having to use `add' to adjust it. */
1100 if (! frame_pointer_needed
&& reg
&& size
+ REG_SAVE_BYTES
> 255)
1102 emit_move_insn (stack_pointer_rtx
, XEXP (reg
, 0));
1107 /* Maybe cut back the stack, except for the register save area.
1109 If the frame pointer exists, then use the frame pointer to
1112 If the stack size + register save area is more than 255 bytes,
1113 then the stack must be cut back here since the size + register
1114 save size is too big for a ret/retf instruction.
1116 Else leave it alone, it will be cut back as part of the
1117 ret/retf instruction, or there wasn't any stack to begin with.
1119 Under no circumstances should the register save area be
1120 deallocated here, that would leave a window where an interrupt
1121 could occur and trash the register save area. */
1122 if (frame_pointer_needed
)
1124 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
1127 else if (size
+ REG_SAVE_BYTES
> 255)
1129 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1135 /* Adjust the stack and restore callee-saved registers, if any. */
1136 if (size
|| regs_ever_live
[2] || regs_ever_live
[3]
1137 || regs_ever_live
[6] || regs_ever_live
[7]
1138 || regs_ever_live
[14] || regs_ever_live
[15]
1139 || regs_ever_live
[16] || regs_ever_live
[17]
1140 || frame_pointer_needed
)
1141 emit_jump_insn (gen_return_internal_regs
1142 (GEN_INT (size
+ REG_SAVE_BYTES
)));
1144 emit_jump_insn (gen_return_internal ());
1147 /* Update the condition code from the insn. */
1150 notice_update_cc (rtx body
, rtx insn
)
1152 switch (get_attr_cc (insn
))
1155 /* Insn does not affect CC at all. */
1159 /* Insn does not change CC, but the 0'th operand has been changed. */
1160 if (cc_status
.value1
!= 0
1161 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
1162 cc_status
.value1
= 0;
1166 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1167 V,C are unusable. */
1169 cc_status
.flags
|= CC_NO_CARRY
| CC_OVERFLOW_UNUSABLE
;
1170 cc_status
.value1
= recog_data
.operand
[0];
1174 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1177 cc_status
.flags
|= CC_NO_CARRY
;
1178 cc_status
.value1
= recog_data
.operand
[0];
1182 /* The insn is a compare instruction. */
1184 cc_status
.value1
= SET_SRC (body
);
1185 if (GET_CODE (cc_status
.value1
) == COMPARE
1186 && GET_MODE (XEXP (cc_status
.value1
, 0)) == SFmode
)
1187 cc_status
.mdep
.fpCC
= 1;
1191 /* The insn is a compare instruction. */
1193 cc_status
.value1
= SET_SRC (body
);
1194 cc_status
.flags
|= CC_INVERTED
;
1198 /* Insn doesn't leave CC in a usable state. */
1207 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1208 This function is for MATCH_PARALLEL and so assumes OP is known to be
1209 parallel. If OP is a multiple store, return a mask indicating which
1210 registers it saves. Return 0 otherwise. */
1213 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1221 count
= XVECLEN (op
, 0);
1225 /* Check that first instruction has the form (set (sp) (plus A B)) */
1226 elt
= XVECEXP (op
, 0, 0);
1227 if (GET_CODE (elt
) != SET
1228 || GET_CODE (SET_DEST (elt
)) != REG
1229 || REGNO (SET_DEST (elt
)) != STACK_POINTER_REGNUM
1230 || GET_CODE (SET_SRC (elt
)) != PLUS
)
1233 /* Check that A is the stack pointer and B is the expected stack size.
1234 For OP to match, each subsequent instruction should push a word onto
1235 the stack. We therefore expect the first instruction to create
1236 COUNT-1 stack slots. */
1237 elt
= SET_SRC (elt
);
1238 if (GET_CODE (XEXP (elt
, 0)) != REG
1239 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
1240 || GET_CODE (XEXP (elt
, 1)) != CONST_INT
1241 || INTVAL (XEXP (elt
, 1)) != -(count
- 1) * 4)
1244 /* Now go through the rest of the vector elements. They must be
1245 ordered so that the first instruction stores the highest-numbered
1246 register to the highest stack slot and that subsequent instructions
1247 store a lower-numbered register to the slot below.
1249 LAST keeps track of the smallest-numbered register stored so far.
1250 MASK is the set of stored registers. */
1251 last
= LAST_EXTENDED_REGNUM
+ 1;
1253 for (i
= 1; i
< count
; i
++)
1255 /* Check that element i is a (set (mem M) R) and that R is valid. */
1256 elt
= XVECEXP (op
, 0, i
);
1257 if (GET_CODE (elt
) != SET
1258 || GET_CODE (SET_DEST (elt
)) != MEM
1259 || GET_CODE (SET_SRC (elt
)) != REG
1260 || REGNO (SET_SRC (elt
)) >= last
)
1263 /* R was OK, so provisionally add it to MASK. We return 0 in any
1264 case if the rest of the instruction has a flaw. */
1265 last
= REGNO (SET_SRC (elt
));
1266 mask
|= (1 << last
);
1268 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1269 elt
= XEXP (SET_DEST (elt
), 0);
1270 if (GET_CODE (elt
) != PLUS
1271 || GET_CODE (XEXP (elt
, 0)) != REG
1272 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
1273 || GET_CODE (XEXP (elt
, 1)) != CONST_INT
1274 || INTVAL (XEXP (elt
, 1)) != -i
* 4)
1278 /* All or none of the callee-saved extended registers must be in the set. */
1279 if ((mask
& 0x3c000) != 0
1280 && (mask
& 0x3c000) != 0x3c000)
1286 /* Return true if OP is a valid call operand. */
1289 call_address_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1292 return (EXTRA_CONSTRAINT (op
, 'S') || GET_CODE (op
) == REG
);
1294 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == REG
);
1297 /* What (if any) secondary registers are needed to move IN with mode
1298 MODE into a register in register class CLASS.
1300 We might be able to simplify this. */
1302 secondary_reload_class (enum reg_class
class, enum machine_mode mode
, rtx in
)
1304 /* Memory loads less than a full word wide can't have an
1305 address or stack pointer destination. They must use
1306 a data register as an intermediate register. */
1307 if ((GET_CODE (in
) == MEM
1308 || (GET_CODE (in
) == REG
1309 && REGNO (in
) >= FIRST_PSEUDO_REGISTER
)
1310 || (GET_CODE (in
) == SUBREG
1311 && GET_CODE (SUBREG_REG (in
)) == REG
1312 && REGNO (SUBREG_REG (in
)) >= FIRST_PSEUDO_REGISTER
))
1313 && (mode
== QImode
|| mode
== HImode
)
1314 && (class == ADDRESS_REGS
|| class == SP_REGS
1315 || class == SP_OR_ADDRESS_REGS
))
1318 return DATA_OR_EXTENDED_REGS
;
1322 /* We can't directly load sp + const_int into a data register;
1323 we must use an address register as an intermediate. */
1324 if (class != SP_REGS
1325 && class != ADDRESS_REGS
1326 && class != SP_OR_ADDRESS_REGS
1327 && class != SP_OR_EXTENDED_REGS
1328 && class != ADDRESS_OR_EXTENDED_REGS
1329 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
1330 && (in
== stack_pointer_rtx
1331 || (GET_CODE (in
) == PLUS
1332 && (XEXP (in
, 0) == stack_pointer_rtx
1333 || XEXP (in
, 1) == stack_pointer_rtx
))))
1334 return ADDRESS_REGS
;
1336 if (GET_CODE (in
) == PLUS
1337 && (XEXP (in
, 0) == stack_pointer_rtx
1338 || XEXP (in
, 1) == stack_pointer_rtx
))
1341 return DATA_OR_EXTENDED_REGS
;
1345 if (TARGET_AM33_2
&& class == FP_REGS
1346 && GET_CODE (in
) == MEM
&& ! OK_FOR_Q (in
))
1349 return DATA_OR_EXTENDED_REGS
;
1353 /* Otherwise assume no secondary reloads are needed. */
1358 initial_offset (int from
, int to
)
1360 /* The difference between the argument pointer and the frame pointer
1361 is the size of the callee register save area. */
1362 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1364 if (regs_ever_live
[2] || regs_ever_live
[3]
1365 || regs_ever_live
[6] || regs_ever_live
[7]
1366 || regs_ever_live
[14] || regs_ever_live
[15]
1367 || regs_ever_live
[16] || regs_ever_live
[17]
1368 || fp_regs_to_save ()
1369 || frame_pointer_needed
)
1370 return REG_SAVE_BYTES
1371 + 4 * fp_regs_to_save ();
1376 /* The difference between the argument pointer and the stack pointer is
1377 the sum of the size of this function's frame, the callee register save
1378 area, and the fixed stack space needed for function calls (if any). */
1379 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1381 if (regs_ever_live
[2] || regs_ever_live
[3]
1382 || regs_ever_live
[6] || regs_ever_live
[7]
1383 || regs_ever_live
[14] || regs_ever_live
[15]
1384 || regs_ever_live
[16] || regs_ever_live
[17]
1385 || fp_regs_to_save ()
1386 || frame_pointer_needed
)
1387 return (get_frame_size () + REG_SAVE_BYTES
1388 + 4 * fp_regs_to_save ()
1389 + (current_function_outgoing_args_size
1390 ? current_function_outgoing_args_size
+ 4 : 0));
1392 return (get_frame_size ()
1393 + (current_function_outgoing_args_size
1394 ? current_function_outgoing_args_size
+ 4 : 0));
1397 /* The difference between the frame pointer and stack pointer is the sum
1398 of the size of this function's frame and the fixed stack space needed
1399 for function calls (if any). */
1400 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1401 return (get_frame_size ()
1402 + (current_function_outgoing_args_size
1403 ? current_function_outgoing_args_size
+ 4 : 0));
1408 /* Flush the argument registers to the stack for a stdarg function;
1409 return the new argument pointer. */
1411 mn10300_builtin_saveregs (void)
1414 tree fntype
= TREE_TYPE (current_function_decl
);
1415 int argadj
= ((!(TYPE_ARG_TYPES (fntype
) != 0
1416 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
1417 != void_type_node
)))
1418 ? UNITS_PER_WORD
: 0);
1419 int set
= get_varargs_alias_set ();
1422 offset
= plus_constant (current_function_arg_offset_rtx
, argadj
);
1424 offset
= current_function_arg_offset_rtx
;
1426 mem
= gen_rtx_MEM (SImode
, current_function_internal_arg_pointer
);
1427 set_mem_alias_set (mem
, set
);
1428 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
1430 mem
= gen_rtx_MEM (SImode
,
1431 plus_constant (current_function_internal_arg_pointer
, 4));
1432 set_mem_alias_set (mem
, set
);
1433 emit_move_insn (mem
, gen_rtx_REG (SImode
, 1));
1435 return copy_to_reg (expand_binop (Pmode
, add_optab
,
1436 current_function_internal_arg_pointer
,
1437 offset
, 0, 0, OPTAB_LIB_WIDEN
));
1441 mn10300_va_start (tree valist
, rtx nextarg
)
1443 nextarg
= expand_builtin_saveregs ();
1444 std_expand_builtin_va_start (valist
, nextarg
);
1448 mn10300_va_arg (tree valist
, tree type
)
1450 HOST_WIDE_INT align
, rsize
;
1453 /* Compute the rounded size of the type. */
1454 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
1455 rsize
= (((int_size_in_bytes (type
) + align
- 1) / align
) * align
);
1457 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (valist
), valist
,
1458 build_int_2 ((rsize
> 8 ? 4 : rsize
), 0));
1459 TREE_SIDE_EFFECTS (t
) = 1;
1461 ptr
= build_pointer_type (type
);
1463 /* "Large" types are passed by reference. */
1466 pptr
= build_pointer_type (ptr
);
1467 t
= build1 (NOP_EXPR
, pptr
, t
);
1468 TREE_SIDE_EFFECTS (t
) = 1;
1470 t
= build1 (INDIRECT_REF
, ptr
, t
);
1471 TREE_SIDE_EFFECTS (t
) = 1;
1475 t
= build1 (NOP_EXPR
, ptr
, t
);
1476 TREE_SIDE_EFFECTS (t
) = 1;
1480 return expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1483 /* Return an RTX to represent where a value with mode MODE will be returned
1484 from a function. If the result is 0, the argument is pushed. */
1487 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1488 tree type
, int named ATTRIBUTE_UNUSED
)
1493 /* We only support using 2 data registers as argument registers. */
1496 /* Figure out the size of the object to be passed. */
1497 if (mode
== BLKmode
)
1498 size
= int_size_in_bytes (type
);
1500 size
= GET_MODE_SIZE (mode
);
1502 /* Figure out the alignment of the object to be passed. */
1505 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1507 /* Don't pass this arg via a register if all the argument registers
1509 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1512 /* Don't pass this arg via a register if it would be split between
1513 registers and memory. */
1514 if (type
== NULL_TREE
1515 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1518 switch (cum
->nbytes
/ UNITS_PER_WORD
)
1521 result
= gen_rtx_REG (mode
, 0);
1524 result
= gen_rtx_REG (mode
, 1);
1533 /* Return the number of registers to use for an argument passed partially
1534 in registers and partially in memory. */
1537 function_arg_partial_nregs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1538 tree type
, int named ATTRIBUTE_UNUSED
)
1542 /* We only support using 2 data registers as argument registers. */
1545 /* Figure out the size of the object to be passed. */
1546 if (mode
== BLKmode
)
1547 size
= int_size_in_bytes (type
);
1549 size
= GET_MODE_SIZE (mode
);
1551 /* Figure out the alignment of the object to be passed. */
1554 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1556 /* Don't pass this arg via a register if all the argument registers
1558 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1561 if (cum
->nbytes
+ size
<= nregs
* UNITS_PER_WORD
)
1564 /* Don't pass this arg via a register if it would be split between
1565 registers and memory. */
1566 if (type
== NULL_TREE
1567 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1570 return (nregs
* UNITS_PER_WORD
- cum
->nbytes
) / UNITS_PER_WORD
;
1573 /* Output a tst insn. */
1575 output_tst (rtx operand
, rtx insn
)
1580 /* We can save a byte if we can find a register which has the value
1582 temp
= PREV_INSN (insn
);
1583 while (optimize
&& temp
)
1587 /* We allow the search to go through call insns. We record
1588 the fact that we've past a CALL_INSN and reject matches which
1589 use call clobbered registers. */
1590 if (GET_CODE (temp
) == CODE_LABEL
1591 || GET_CODE (temp
) == JUMP_INSN
1592 || GET_CODE (temp
) == BARRIER
)
1595 if (GET_CODE (temp
) == CALL_INSN
)
1598 if (GET_CODE (temp
) == NOTE
)
1600 temp
= PREV_INSN (temp
);
1604 /* It must be an insn, see if it is a simple set. */
1605 set
= single_set (temp
);
1608 temp
= PREV_INSN (temp
);
1612 /* Are we setting a data register to zero (this does not win for
1615 If it's a call clobbered register, have we past a call?
1617 Make sure the register we find isn't the same as ourself;
1618 the mn10300 can't encode that.
1620 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1621 so the code to detect calls here isn't doing anything useful. */
1622 if (REG_P (SET_DEST (set
))
1623 && SET_SRC (set
) == CONST0_RTX (GET_MODE (SET_DEST (set
)))
1624 && !reg_set_between_p (SET_DEST (set
), temp
, insn
)
1625 && (REGNO_REG_CLASS (REGNO (SET_DEST (set
)))
1626 == REGNO_REG_CLASS (REGNO (operand
)))
1627 && REGNO_REG_CLASS (REGNO (SET_DEST (set
))) != EXTENDED_REGS
1628 && REGNO (SET_DEST (set
)) != REGNO (operand
)
1630 || !call_used_regs
[REGNO (SET_DEST (set
))]))
1633 xoperands
[0] = operand
;
1634 xoperands
[1] = SET_DEST (set
);
1636 output_asm_insn ("cmp %1,%0", xoperands
);
1640 if (REGNO_REG_CLASS (REGNO (operand
)) == EXTENDED_REGS
1641 && REG_P (SET_DEST (set
))
1642 && SET_SRC (set
) == CONST0_RTX (GET_MODE (SET_DEST (set
)))
1643 && !reg_set_between_p (SET_DEST (set
), temp
, insn
)
1644 && (REGNO_REG_CLASS (REGNO (SET_DEST (set
)))
1645 != REGNO_REG_CLASS (REGNO (operand
)))
1646 && REGNO_REG_CLASS (REGNO (SET_DEST (set
))) == EXTENDED_REGS
1647 && REGNO (SET_DEST (set
)) != REGNO (operand
)
1649 || !call_used_regs
[REGNO (SET_DEST (set
))]))
1652 xoperands
[0] = operand
;
1653 xoperands
[1] = SET_DEST (set
);
1655 output_asm_insn ("cmp %1,%0", xoperands
);
1658 temp
= PREV_INSN (temp
);
1664 impossible_plus_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1666 if (GET_CODE (op
) != PLUS
)
1669 if (XEXP (op
, 0) == stack_pointer_rtx
1670 || XEXP (op
, 1) == stack_pointer_rtx
)
1676 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1677 for the btst insn which may examine memory or a register (the memory
1678 variant only allows an unsigned 8 bit integer). */
1680 const_8bit_operand (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1682 return (GET_CODE (op
) == CONST_INT
1684 && INTVAL (op
) < 256);
1687 /* Return true if the operand is the 1.0f constant. */
1689 const_1f_operand (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1691 return (op
== CONST1_RTX (SFmode
));
1694 /* Similarly, but when using a zero_extract pattern for a btst where
1695 the source operand might end up in memory. */
1697 mask_ok_for_mem_btst (int len
, int bit
)
1699 unsigned int mask
= 0;
1708 /* MASK must bit into an 8bit value. */
1709 return (((mask
& 0xff) == mask
)
1710 || ((mask
& 0xff00) == mask
)
1711 || ((mask
& 0xff0000) == mask
)
1712 || ((mask
& 0xff000000) == mask
));
1715 /* Return 1 if X contains a symbolic expression. We know these
1716 expressions will have one of a few well defined forms, so
1717 we need only check those forms. */
1719 symbolic_operand (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1721 switch (GET_CODE (op
))
1728 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1729 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1730 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1736 /* Try machine dependent ways of modifying an illegitimate address
1737 to be legitimate. If we find one, return the new valid address.
1738 This macro is used in only one place: `memory_address' in explow.c.
1740 OLDX is the address as it was before break_out_memory_refs was called.
1741 In some cases it is useful to look at this to decide what needs to be done.
1743 MODE and WIN are passed so that this macro can use
1744 GO_IF_LEGITIMATE_ADDRESS.
1746 Normally it is always safe for this macro to do nothing. It exists to
1747 recognize opportunities to optimize the output.
1749 But on a few ports with segmented architectures and indexed addressing
1750 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1752 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1753 enum machine_mode mode ATTRIBUTE_UNUSED
)
1755 if (flag_pic
&& ! legitimate_pic_operand_p (x
))
1756 x
= legitimize_pic_address (oldx
, NULL_RTX
);
1758 /* Uh-oh. We might have an address for x[n-100000]. This needs
1759 special handling to avoid creating an indexed memory address
1760 with x-100000 as the base. */
1761 if (GET_CODE (x
) == PLUS
1762 && symbolic_operand (XEXP (x
, 1), VOIDmode
))
1764 /* Ugly. We modify things here so that the address offset specified
1765 by the index expression is computed first, then added to x to form
1766 the entire address. */
1768 rtx regx1
, regy1
, regy2
, y
;
1770 /* Strip off any CONST. */
1772 if (GET_CODE (y
) == CONST
)
1775 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
1777 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1778 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1779 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1780 regx1
= force_reg (Pmode
,
1781 gen_rtx (GET_CODE (y
), Pmode
, regx1
, regy2
));
1782 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, regx1
, regy1
));
1788 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1789 @GOTOFF in `reg'. */
1791 legitimize_pic_address (rtx orig
, rtx reg
)
1793 if (GET_CODE (orig
) == LABEL_REF
1794 || (GET_CODE (orig
) == SYMBOL_REF
1795 && (CONSTANT_POOL_ADDRESS_P (orig
)
1796 || ! MN10300_GLOBAL_P (orig
))))
1799 reg
= gen_reg_rtx (Pmode
);
1801 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
1804 else if (GET_CODE (orig
) == SYMBOL_REF
)
1807 reg
= gen_reg_rtx (Pmode
);
1809 emit_insn (gen_symGOT2reg (reg
, orig
));
1815 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1816 isn't protected by a PIC unspec; nonzero otherwise. */
1818 legitimate_pic_operand_p (rtx x
)
1820 register const char *fmt
;
1823 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1826 if (GET_CODE (x
) == UNSPEC
1827 && (XINT (x
, 1) == UNSPEC_PIC
1828 || XINT (x
, 1) == UNSPEC_GOT
1829 || XINT (x
, 1) == UNSPEC_GOTOFF
1830 || XINT (x
, 1) == UNSPEC_PLT
))
1833 if (GET_CODE (x
) == QUEUED
)
1834 return legitimate_pic_operand_p (QUEUED_VAR (x
));
1836 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
1837 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
1843 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1844 if (! legitimate_pic_operand_p (XVECEXP (x
, i
, j
)))
1847 else if (fmt
[i
] == 'e' && ! legitimate_pic_operand_p (XEXP (x
, i
)))
1855 mn10300_address_cost_1 (rtx x
, int *unsig
)
1857 switch (GET_CODE (x
))
1860 switch (REGNO_REG_CLASS (REGNO (x
)))
1886 return (mn10300_address_cost_1 (XEXP (x
, 0), unsig
)
1887 + mn10300_address_cost_1 (XEXP (x
, 1), unsig
));
1892 return mn10300_address_cost (XEXP (x
, 0));
1896 return mn10300_address_cost_1 (XEXP (x
, 0), unsig
);
1899 if (INTVAL (x
) == 0)
1901 if (INTVAL (x
) + (*unsig
? 0 : 0x80) < 0x100)
1903 if (INTVAL (x
) + (*unsig
? 0 : 0x8000) < 0x10000)
1905 if (INTVAL (x
) + (*unsig
? 0 : 0x800000) < 0x1000000)
1915 switch (GET_CODE (XEXP (x
, 0)))
1918 return mn10300_address_cost (XEXP (x
, 0));
1934 mn10300_address_cost (rtx x
)
1937 return mn10300_address_cost_1 (x
, &s
);
1941 mn10300_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1946 /* Zeros are extremely cheap. */
1947 if (INTVAL (x
) == 0 && outer_code
== SET
)
1949 /* If it fits in 8 bits, then it's still relatively cheap. */
1950 else if (INT_8_BITS (INTVAL (x
)))
1952 /* This is the "base" cost, includes constants where either the
1953 upper or lower 16bits are all zeros. */
1954 else if (INT_16_BITS (INTVAL (x
))
1955 || (INTVAL (x
) & 0xffff) == 0
1956 || (INTVAL (x
) & 0xffff0000) == 0)
1965 /* These are more costly than a CONST_INT, but we can relax them,
1966 so they're less costly than a CONST_DOUBLE. */
1971 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
1972 so their cost is very high. */
1976 /* ??? This probably needs more work. */
1988 /* Check whether a constant used to initialize a DImode or DFmode can
1989 use a clr instruction. The code here must be kept in sync with
1993 mn10300_wide_const_load_uses_clr (rtx operands
[2])
1997 if (GET_CODE (operands
[0]) != REG
1998 || REGNO_REG_CLASS (REGNO (operands
[0])) != DATA_REGS
)
2001 switch (GET_CODE (operands
[1]))
2006 split_double (operands
[1], &low
, &high
);
2007 val
[0] = INTVAL (low
);
2008 val
[1] = INTVAL (high
);
2013 if (GET_MODE (operands
[1]) == DFmode
)
2017 REAL_VALUE_FROM_CONST_DOUBLE (rv
, operands
[1]);
2018 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
2020 else if (GET_MODE (operands
[1]) == VOIDmode
2021 || GET_MODE (operands
[1]) == DImode
)
2023 val
[0] = CONST_DOUBLE_LOW (operands
[1]);
2024 val
[1] = CONST_DOUBLE_HIGH (operands
[1]);
2032 return val
[0] == 0 || val
[1] == 0;
2034 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2035 may access it using GOTOFF instead of GOT. */
2038 mn10300_encode_section_info (tree decl
, rtx rtl
, int first ATTRIBUTE_UNUSED
)
2042 if (GET_CODE (rtl
) != MEM
)
2044 symbol
= XEXP (rtl
, 0);
2045 if (GET_CODE (symbol
) != SYMBOL_REF
)
2049 SYMBOL_REF_FLAG (symbol
) = (*targetm
.binds_local_p
) (decl
);