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2003-12-26 Guilhem Lavaux <guilhem@kaffe.org>
[official-gcc.git] / gcc / config / mips / mips.h
blobe144d64bc413bcf5b72048c6953164cbe6346072
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* comparison type */
34 enum cmp_type {
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
40 };
41
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
46
47 enum processor_type {
48 PROCESSOR_DEFAULT,
49 PROCESSOR_4KC,
50 PROCESSOR_5KC,
51 PROCESSOR_20KC,
52 PROCESSOR_M4K,
53 PROCESSOR_R3000,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4300,
61 PROCESSOR_R4600,
62 PROCESSOR_R4650,
63 PROCESSOR_R5000,
64 PROCESSOR_R5400,
65 PROCESSOR_R5500,
66 PROCESSOR_R7000,
67 PROCESSOR_R8000,
68 PROCESSOR_R9000,
69 PROCESSOR_SB1,
70 PROCESSOR_SR71000
71 };
72
73 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
74 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
75 to work on a 64 bit machine. */
76
77 #define ABI_32 0
78 #define ABI_N32 1
79 #define ABI_64 2
80 #define ABI_EABI 3
81 #define ABI_O64 4
82
83 /* Information about one recognized processor. Defined here for the
84 benefit of TARGET_CPU_CPP_BUILTINS. */
85 struct mips_cpu_info {
86 /* The 'canonical' name of the processor as far as GCC is concerned.
87 It's typically a manufacturer's prefix followed by a numerical
88 designation. It should be lower case. */
89 const char *name;
90
91 /* The internal processor number that most closely matches this
92 entry. Several processors can have the same value, if there's no
93 difference between them from GCC's point of view. */
94 enum processor_type cpu;
95
96 /* The ISA level that the processor implements. */
97 int isa;
98 };
99
100 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
101 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
102 extern const char *current_function_file; /* filename current function is in */
103 extern int num_source_filenames; /* current .file # */
104 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
105 extern int sym_lineno; /* sgi next label # for each stmt */
106 extern int set_noreorder; /* # of nested .set noreorder's */
107 extern int set_nomacro; /* # of nested .set nomacro's */
108 extern int set_noat; /* # of nested .set noat's */
109 extern int set_volatile; /* # of nested .set volatile's */
110 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
111 extern int mips_dbx_regno[]; /* Map register # to debug register # */
112 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
113 extern enum cmp_type branch_type; /* what type of branch to use */
114 extern enum processor_type mips_arch; /* which cpu to codegen for */
115 extern enum processor_type mips_tune; /* which cpu to schedule for */
116 extern int mips_isa; /* architectural level */
117 extern int mips_abi; /* which ABI to use */
118 extern int mips16_hard_float; /* mips16 without -msoft-float */
119 extern int mips_entry; /* generate entry/exit for mips16 */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
125 extern int mips_string_length; /* length of strings for mips16 */
126 extern const struct mips_cpu_info mips_cpu_info_table[];
127 extern const struct mips_cpu_info *mips_arch_info;
128 extern const struct mips_cpu_info *mips_tune_info;
129
130 /* Macros to silence warnings about numbers being signed in traditional
131 C and unsigned in ISO C when compiled on 32-bit hosts. */
132
133 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
134 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
135 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
136
137 \f
138 /* Run-time compilation parameters selecting different hardware subsets. */
139
140 /* Macros used in the machine description to test the flags. */
141
142 /* Bits for real switches */
143 #define MASK_INT64 0x00000001 /* ints are 64 bits */
144 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
145 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
146 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
147 multiply-add operations. */
148 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
149 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
150 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
151 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
152 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
153 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
154 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
155 #define MASK_XGOT 0x00000800 /* emit big-got PIC */
156 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
157 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
158 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
159 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
160 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
161 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
162 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
163 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
164 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
165 #define MASK_NO_CHECK_ZERO_DIV \
166 0x00200000 /* divide by zero checking */
167 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
168 instructions. */
169 #define MASK_UNINIT_CONST_IN_RODATA \
170 0x00800000 /* Store uninitialized
171 consts in rodata */
172 #define MASK_FIX_SB1 0x01000000 /* Work around SB-1 errata. */
173
174 /* Debug switches, not documented */
175 #define MASK_DEBUG 0 /* unused */
176 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
177 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
178 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
179 #define MASK_DEBUG_D 0 /* don't do define_split's */
180 #define MASK_DEBUG_E 0 /* function_arg debug */
181 #define MASK_DEBUG_F 0 /* ??? */
182 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
183 #define MASK_DEBUG_I 0 /* unused */
184
185 /* Dummy switches used only in specs */
186 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
187
188 /* r4000 64 bit sizes */
189 #define TARGET_INT64 (target_flags & MASK_INT64)
190 #define TARGET_LONG64 (target_flags & MASK_LONG64)
191 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
192 #define TARGET_64BIT (target_flags & MASK_64BIT)
193
194 /* Mips vs. GNU linker */
195 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
196
197 /* Mips vs. GNU assembler */
198 #define TARGET_GAS (target_flags & MASK_GAS)
199 #define TARGET_MIPS_AS (!TARGET_GAS)
200
201 /* Debug Modes */
202 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
203 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
204 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
205 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
206 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
207 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
208 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
209 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
210 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
211
212 /* Reg. Naming in .s ($21 vs. $a0) */
213 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
214
215 /* call memcpy instead of inline code */
216 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
217
218 /* .abicalls, etc from Pyramid V.4 */
219 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
220 #define TARGET_XGOT (target_flags & MASK_XGOT)
221
222 /* software floating point */
223 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
224 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
225
226 /* always call through a register */
227 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
228
229 /* generate embedded PIC code;
230 requires gas. */
231 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
232
233 /* for embedded systems, optimize for
234 reduced RAM space instead of for
235 fastest code. */
236 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
237
238 /* always store uninitialized const
239 variables in rodata, requires
240 TARGET_EMBEDDED_DATA. */
241 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
242
243 /* generate big endian code. */
244 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
245
246 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
247 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
248
249 #define TARGET_MAD (target_flags & MASK_MAD)
250
251 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
252
253 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
254
255 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
256
257 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
258
259 #define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
260
261 /* True if we should use NewABI-style relocation operators for
262 symbolic addresses. This is never true for mips16 code,
263 which has its own conventions. */
264
265 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
266
267
268 /* True if the call patterns should be split into a jalr followed by
269 an instruction to restore $gp. This is only ever true for SVR4 PIC,
270 in which $gp is call-clobbered. It is only safe to split the load
271 from the call when every use of $gp is explicit. */
272
273 #define TARGET_SPLIT_CALLS \
274 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
275
276 /* True if we can optimize sibling calls. For simplicity, we only
277 handle cases in which call_insn_operand will reject invalid
278 sibcall addresses. There are two cases in which this isn't true:
279
280 - TARGET_MIPS16. call_insn_operand accepts constant addresses
281 but there is no direct jump instruction. It isn't worth
282 using sibling calls in this case anyway; they would usually
283 be longer than normal calls.
284
285 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
286 accepts global constants, but "jr $25" is the only allowed
287 sibcall. */
288
289 #define TARGET_SIBCALLS \
290 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
291
292 /* True if .gpword or .gpdword should be used for switch tables.
293 Not all SGI assemblers support this. */
294
295 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
296
297 /* Generate mips16 code */
298 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
299
300 /* Generic ISA defines. */
301 #define ISA_MIPS1 (mips_isa == 1)
302 #define ISA_MIPS2 (mips_isa == 2)
303 #define ISA_MIPS3 (mips_isa == 3)
304 #define ISA_MIPS4 (mips_isa == 4)
305 #define ISA_MIPS32 (mips_isa == 32)
306 #define ISA_MIPS32R2 (mips_isa == 33)
307 #define ISA_MIPS64 (mips_isa == 64)
308
309 /* Architecture target defines. */
310 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
311 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
312 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
313 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
314 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
315 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
316 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
317 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
318 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
319 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
320 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
321 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
322 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
323
324 /* Scheduling target defines. */
325 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
326 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
327 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
328 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
329 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
330 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
331 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
332 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
333 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
334 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
335 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
336
337 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
338
339 /* IRIX specific stuff. */
340 #define TARGET_IRIX 0
341 #define TARGET_IRIX5 0
342 #define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
343
344 /* Define preprocessor macros for the -march and -mtune options.
345 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
346 processor. If INFO's canonical name is "foo", define PREFIX to
347 be "foo", and define an additional macro PREFIX_FOO. */
348 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
349 do \
350 { \
351 char *macro, *p; \
352 \
353 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
354 for (p = macro; *p != 0; p++) \
355 *p = TOUPPER (*p); \
356 \
357 builtin_define (macro); \
358 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
359 free (macro); \
360 } \
361 while (0)
362
363 /* Target CPU builtins. */
364 #define TARGET_CPU_CPP_BUILTINS() \
365 do \
366 { \
367 builtin_assert ("cpu=mips"); \
368 builtin_define ("__mips__"); \
369 builtin_define ("_mips"); \
370 \
371 /* We do this here because __mips is defined below \
372 and so we can't use builtin_define_std. */ \
373 if (!flag_iso) \
374 builtin_define ("mips"); \
375 \
376 /* Treat _R3000 and _R4000 like register-size defines, \
377 which is how they've historically been used. */ \
378 if (TARGET_64BIT) \
379 { \
380 builtin_define ("__mips64"); \
381 builtin_define_std ("R4000"); \
382 builtin_define ("_R4000"); \
383 } \
384 else \
385 { \
386 builtin_define_std ("R3000"); \
387 builtin_define ("_R3000"); \
388 } \
389 if (TARGET_FLOAT64) \
390 builtin_define ("__mips_fpr=64"); \
391 else \
392 builtin_define ("__mips_fpr=32"); \
393 \
394 if (TARGET_MIPS16) \
395 builtin_define ("__mips16"); \
396 \
397 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
398 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
399 \
400 if (ISA_MIPS1) \
401 { \
402 builtin_define ("__mips=1"); \
403 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
404 } \
405 else if (ISA_MIPS2) \
406 { \
407 builtin_define ("__mips=2"); \
408 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
409 } \
410 else if (ISA_MIPS3) \
411 { \
412 builtin_define ("__mips=3"); \
413 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
414 } \
415 else if (ISA_MIPS4) \
416 { \
417 builtin_define ("__mips=4"); \
418 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
419 } \
420 else if (ISA_MIPS32) \
421 { \
422 builtin_define ("__mips=32"); \
423 builtin_define ("__mips_isa_rev=1"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
425 } \
426 else if (ISA_MIPS32R2) \
427 { \
428 builtin_define ("__mips=32"); \
429 builtin_define ("__mips_isa_rev=2"); \
430 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
431 } \
432 else if (ISA_MIPS64) \
433 { \
434 builtin_define ("__mips=64"); \
435 builtin_define ("__mips_isa_rev=1"); \
436 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
437 } \
438 \
439 if (TARGET_HARD_FLOAT) \
440 builtin_define ("__mips_hard_float"); \
441 else if (TARGET_SOFT_FLOAT) \
442 builtin_define ("__mips_soft_float"); \
443 \
444 if (TARGET_SINGLE_FLOAT) \
445 builtin_define ("__mips_single_float"); \
446 \
447 if (TARGET_BIG_ENDIAN) \
448 { \
449 builtin_define_std ("MIPSEB"); \
450 builtin_define ("_MIPSEB"); \
451 } \
452 else \
453 { \
454 builtin_define_std ("MIPSEL"); \
455 builtin_define ("_MIPSEL"); \
456 } \
457 \
458 /* Macros dependent on the C dialect. */ \
459 if (preprocessing_asm_p ()) \
460 { \
461 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
462 builtin_define ("_LANGUAGE_ASSEMBLY"); \
463 } \
464 else if (c_dialect_cxx ()) \
465 { \
466 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
467 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
468 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
469 } \
470 else \
471 { \
472 builtin_define_std ("LANGUAGE_C"); \
473 builtin_define ("_LANGUAGE_C"); \
474 } \
475 if (c_dialect_objc ()) \
476 { \
477 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
478 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
479 /* Bizarre, but needed at least for Irix. */ \
480 builtin_define_std ("LANGUAGE_C"); \
481 builtin_define ("_LANGUAGE_C"); \
482 } \
483 \
484 if (mips_abi == ABI_EABI) \
485 builtin_define ("__mips_eabi"); \
486 \
487 } while (0)
488
489
490
491 /* Macro to define tables used to set the flags.
492 This is a list in braces of pairs in braces,
493 each pair being { "NAME", VALUE }
494 where VALUE is the bits to set or minus the bits to clear.
495 An empty string NAME is used to identify the default VALUE. */
496
497 #define TARGET_SWITCHES \
498 { \
499 SUBTARGET_TARGET_SWITCHES \
500 {"int64", MASK_INT64 | MASK_LONG64, \
501 N_("Use 64-bit int type")}, \
502 {"long64", MASK_LONG64, \
503 N_("Use 64-bit long type")}, \
504 {"long32", -(MASK_LONG64 | MASK_INT64), \
505 N_("Use 32-bit long type")}, \
506 {"split-addresses", MASK_SPLIT_ADDR, \
507 N_("Optimize lui/addiu address loads")}, \
508 {"no-split-addresses", -MASK_SPLIT_ADDR, \
509 N_("Don't optimize lui/addiu address loads")}, \
510 {"mips-as", -MASK_GAS, \
511 N_("Use MIPS as")}, \
512 {"gas", MASK_GAS, \
513 N_("Use GNU as")}, \
514 {"rnames", MASK_NAME_REGS, \
515 N_("Use symbolic register names")}, \
516 {"no-rnames", -MASK_NAME_REGS, \
517 N_("Don't use symbolic register names")}, \
518 {"gpOPT", 0, \
519 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
520 {"gpopt", 0, \
521 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
522 {"no-gpOPT", 0, \
523 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
524 {"no-gpopt", 0, \
525 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
526 {"stats", 0, \
527 N_("Output compiler statistics (now ignored)")}, \
528 {"no-stats", 0, \
529 N_("Don't output compiler statistics")}, \
530 {"memcpy", MASK_MEMCPY, \
531 N_("Don't optimize block moves")}, \
532 {"no-memcpy", -MASK_MEMCPY, \
533 N_("Optimize block moves")}, \
534 {"mips-tfile", MASK_MIPS_TFILE, \
535 N_("Use mips-tfile asm postpass")}, \
536 {"no-mips-tfile", -MASK_MIPS_TFILE, \
537 N_("Don't use mips-tfile asm postpass")}, \
538 {"soft-float", MASK_SOFT_FLOAT, \
539 N_("Use software floating point")}, \
540 {"hard-float", -MASK_SOFT_FLOAT, \
541 N_("Use hardware floating point")}, \
542 {"fp64", MASK_FLOAT64, \
543 N_("Use 64-bit FP registers")}, \
544 {"fp32", -MASK_FLOAT64, \
545 N_("Use 32-bit FP registers")}, \
546 {"gp64", MASK_64BIT, \
547 N_("Use 64-bit general registers")}, \
548 {"gp32", -MASK_64BIT, \
549 N_("Use 32-bit general registers")}, \
550 {"abicalls", MASK_ABICALLS, \
551 N_("Use Irix PIC")}, \
552 {"no-abicalls", -MASK_ABICALLS, \
553 N_("Don't use Irix PIC")}, \
554 {"long-calls", MASK_LONG_CALLS, \
555 N_("Use indirect calls")}, \
556 {"no-long-calls", -MASK_LONG_CALLS, \
557 N_("Don't use indirect calls")}, \
558 {"embedded-pic", MASK_EMBEDDED_PIC, \
559 N_("Use embedded PIC")}, \
560 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
561 N_("Don't use embedded PIC")}, \
562 {"embedded-data", MASK_EMBEDDED_DATA, \
563 N_("Use ROM instead of RAM")}, \
564 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
565 N_("Don't use ROM instead of RAM")}, \
566 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
567 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
568 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
569 N_("Don't put uninitialized constants in ROM")}, \
570 {"eb", MASK_BIG_ENDIAN, \
571 N_("Use big-endian byte order")}, \
572 {"el", -MASK_BIG_ENDIAN, \
573 N_("Use little-endian byte order")}, \
574 {"single-float", MASK_SINGLE_FLOAT, \
575 N_("Use single (32-bit) FP only")}, \
576 {"double-float", -MASK_SINGLE_FLOAT, \
577 N_("Don't use single (32-bit) FP only")}, \
578 {"mad", MASK_MAD, \
579 N_("Use multiply accumulate")}, \
580 {"no-mad", -MASK_MAD, \
581 N_("Don't use multiply accumulate")}, \
582 {"no-fused-madd", MASK_NO_FUSED_MADD, \
583 N_("Don't generate fused multiply/add instructions")}, \
584 {"fused-madd", -MASK_NO_FUSED_MADD, \
585 N_("Generate fused multiply/add instructions")}, \
586 {"fix4300", MASK_4300_MUL_FIX, \
587 N_("Work around early 4300 hardware bug")}, \
588 {"no-fix4300", -MASK_4300_MUL_FIX, \
589 N_("Don't work around early 4300 hardware bug")}, \
590 {"fix-sb1", MASK_FIX_SB1, \
591 N_("Work around errata for early SB-1 revision 2 cores")}, \
592 {"no-fix-sb1", -MASK_FIX_SB1, \
593 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
594 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
595 N_("Trap on integer divide by zero")}, \
596 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
597 N_("Don't trap on integer divide by zero")}, \
598 { "branch-likely", MASK_BRANCHLIKELY, \
599 N_("Use Branch Likely instructions, overriding default for arch")}, \
600 { "no-branch-likely", -MASK_BRANCHLIKELY, \
601 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
602 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
603 N_("Use NewABI-style %reloc() assembly operators")}, \
604 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
605 N_("Use assembler macros instead of relocation operators")}, \
606 {"ips16", MASK_MIPS16, \
607 N_("Generate mips16 code") }, \
608 {"no-mips16", -MASK_MIPS16, \
609 N_("Generate normal-mode code") }, \
610 {"xgot", MASK_XGOT, \
611 N_("Lift restrictions on GOT size") }, \
612 {"no-xgot", -MASK_XGOT, \
613 N_("Do not lift restrictions on GOT size") }, \
614 {"debug", MASK_DEBUG, \
615 NULL}, \
616 {"debuga", MASK_DEBUG_A, \
617 NULL}, \
618 {"debugb", MASK_DEBUG_B, \
619 NULL}, \
620 {"debugc", MASK_DEBUG_C, \
621 NULL}, \
622 {"debugd", MASK_DEBUG_D, \
623 NULL}, \
624 {"debuge", MASK_DEBUG_E, \
625 NULL}, \
626 {"debugf", MASK_DEBUG_F, \
627 NULL}, \
628 {"debugg", MASK_DEBUG_G, \
629 NULL}, \
630 {"debugi", MASK_DEBUG_I, \
631 NULL}, \
632 {"", (TARGET_DEFAULT \
633 | TARGET_CPU_DEFAULT \
634 | TARGET_ENDIAN_DEFAULT), \
635 NULL}, \
636 }
637
638 /* Default target_flags if no switches are specified */
639
640 #ifndef TARGET_DEFAULT
641 #define TARGET_DEFAULT 0
642 #endif
643
644 #ifndef TARGET_CPU_DEFAULT
645 #define TARGET_CPU_DEFAULT 0
646 #endif
647
648 #ifndef TARGET_ENDIAN_DEFAULT
649 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
650 #endif
651
652 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
653 #ifndef MIPS_ISA_DEFAULT
654 #ifndef MIPS_CPU_STRING_DEFAULT
655 #define MIPS_CPU_STRING_DEFAULT "from-abi"
656 #endif
657 #endif
658
659 #ifdef IN_LIBGCC2
660 #undef TARGET_64BIT
661 /* Make this compile time constant for libgcc2 */
662 #ifdef __mips64
663 #define TARGET_64BIT 1
664 #else
665 #define TARGET_64BIT 0
666 #endif
667 #endif /* IN_LIBGCC2 */
668
669 #ifndef MULTILIB_ENDIAN_DEFAULT
670 #if TARGET_ENDIAN_DEFAULT == 0
671 #define MULTILIB_ENDIAN_DEFAULT "EL"
672 #else
673 #define MULTILIB_ENDIAN_DEFAULT "EB"
674 #endif
675 #endif
676
677 #ifndef MULTILIB_ISA_DEFAULT
678 # if MIPS_ISA_DEFAULT == 1
679 # define MULTILIB_ISA_DEFAULT "mips1"
680 # else
681 # if MIPS_ISA_DEFAULT == 2
682 # define MULTILIB_ISA_DEFAULT "mips2"
683 # else
684 # if MIPS_ISA_DEFAULT == 3
685 # define MULTILIB_ISA_DEFAULT "mips3"
686 # else
687 # if MIPS_ISA_DEFAULT == 4
688 # define MULTILIB_ISA_DEFAULT "mips4"
689 # else
690 # if MIPS_ISA_DEFAULT == 32
691 # define MULTILIB_ISA_DEFAULT "mips32"
692 # else
693 # if MIPS_ISA_DEFAULT == 33
694 # define MULTILIB_ISA_DEFAULT "mips32r2"
695 # else
696 # if MIPS_ISA_DEFAULT == 64
697 # define MULTILIB_ISA_DEFAULT "mips64"
698 # else
699 # define MULTILIB_ISA_DEFAULT "mips1"
700 # endif
701 # endif
702 # endif
703 # endif
704 # endif
705 # endif
706 # endif
707 #endif
708
709 #ifndef MULTILIB_DEFAULTS
710 #define MULTILIB_DEFAULTS \
711 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
712 #endif
713
714 /* We must pass -EL to the linker by default for little endian embedded
715 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
716 linker will default to using big-endian output files. The OUTPUT_FORMAT
717 line must be in the linker script, otherwise -EB/-EL will not work. */
718
719 #ifndef ENDIAN_SPEC
720 #if TARGET_ENDIAN_DEFAULT == 0
721 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
722 #else
723 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
724 #endif
725 #endif
726
727 #define TARGET_OPTIONS \
728 { \
729 SUBTARGET_TARGET_OPTIONS \
730 { "tune=", &mips_tune_string, \
731 N_("Specify CPU for scheduling purposes"), 0}, \
732 { "arch=", &mips_arch_string, \
733 N_("Specify CPU for code generation purposes"), 0}, \
734 { "abi=", &mips_abi_string, \
735 N_("Specify an ABI"), 0}, \
736 { "ips", &mips_isa_string, \
737 N_("Specify a Standard MIPS ISA"), 0}, \
738 { "no-flush-func", &mips_cache_flush_func, \
739 N_("Don't call any cache flush functions"), 0}, \
740 { "flush-func=", &mips_cache_flush_func, \
741 N_("Specify cache flush function"), 0}, \
742 }
743
744 /* This is meant to be redefined in the host dependent files. */
745 #define SUBTARGET_TARGET_OPTIONS
746
747 /* Support for a compile-time default CPU, et cetera. The rules are:
748 --with-arch is ignored if -march is specified or a -mips is specified
749 (other than -mips16).
750 --with-tune is ignored if -mtune is specified.
751 --with-abi is ignored if -mabi is specified.
752 --with-float is ignored if -mhard-float or -msoft-float are
753 specified. */
754 #define OPTION_DEFAULT_SPECS \
755 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
756 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
757 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
758 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
759
760
761 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
762 && !TARGET_SR71K \
763 && !TARGET_MIPS16)
764
765 /* Generate three-operand multiply instructions for SImode. */
766 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
767 || TARGET_MIPS5400 \
768 || TARGET_MIPS5500 \
769 || TARGET_MIPS7000 \
770 || TARGET_MIPS9000 \
771 || ISA_MIPS32 \
772 || ISA_MIPS32R2 \
773 || ISA_MIPS64) \
774 && !TARGET_MIPS16)
775
776 /* Generate three-operand multiply instructions for DImode. */
777 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
778 && !TARGET_MIPS16)
779
780 /* Macros to decide whether certain features are available or not,
781 depending on the instruction set architecture level. */
782
783 #define HAVE_SQRT_P() (!ISA_MIPS1)
784
785 /* True if the ABI can only work with 64-bit integer registers. We
786 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
787 otherwise floating-point registers must also be 64-bit. */
788 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
789 || mips_abi == ABI_O64 \
790 || mips_abi == ABI_N32)
791
792 /* Likewise for 32-bit regs. */
793 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
794
795 /* True if symbols are 64 bits wide. At present, n64 is the only
796 ABI for which this is true. */
797 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
798
799 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
800 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
801 || ISA_MIPS4 \
802 || ISA_MIPS64)
803
804 /* ISA has branch likely instructions (eg. mips2). */
805 /* Disable branchlikely for tx39 until compare rewrite. They haven't
806 been generated up to this point. */
807 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
808 && !TARGET_MIPS5500)
809
810 /* ISA has the conditional move instructions introduced in mips4. */
811 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
812 || ISA_MIPS32 \
813 || ISA_MIPS32R2 \
814 || ISA_MIPS64) \
815 && !TARGET_MIPS5500 \
816 && !TARGET_MIPS16)
817
818 /* ISA has just the integer condition move instructions (movn,movz) */
819 #define ISA_HAS_INT_CONDMOVE 0
820
821 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
822 branch on CC, and move (both FP and non-FP) on CC. */
823 #define ISA_HAS_8CC (ISA_MIPS4 \
824 || ISA_MIPS32 \
825 || ISA_MIPS32R2 \
826 || ISA_MIPS64)
827
828 /* This is a catch all for other mips4 instructions: indexed load, the
829 FP madd and msub instructions, and the FP recip and recip sqrt
830 instructions. */
831 #define ISA_HAS_FP4 ((ISA_MIPS4 \
832 || ISA_MIPS64) \
833 && !TARGET_MIPS16)
834
835 /* ISA has conditional trap instructions. */
836 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
837 && !TARGET_MIPS16)
838
839 /* ISA has integer multiply-accumulate instructions, madd and msub. */
840 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
841 || ISA_MIPS32R2 \
842 || ISA_MIPS64 \
843 ) && !TARGET_MIPS16)
844
845 /* ISA has floating-point nmadd and nmsub instructions. */
846 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
847 || ISA_MIPS64) \
848 && (!TARGET_MIPS5400 || TARGET_MAD) \
849 && ! TARGET_MIPS16)
850
851 /* ISA has count leading zeroes/ones instruction (not implemented). */
852 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
853 || ISA_MIPS32R2 \
854 || ISA_MIPS64 \
855 ) && !TARGET_MIPS16)
856
857 /* ISA has double-word count leading zeroes/ones instruction (not
858 implemented). */
859 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
860 && !TARGET_MIPS16)
861
862 /* ISA has three operand multiply instructions that put
863 the high part in an accumulator: mulhi or mulhiu. */
864 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
865 || TARGET_MIPS5500 \
866 || TARGET_SR71K \
867 )
868
869 /* ISA has three operand multiply instructions that
870 negates the result and puts the result in an accumulator. */
871 #define ISA_HAS_MULS (TARGET_MIPS5400 \
872 || TARGET_MIPS5500 \
873 || TARGET_SR71K \
874 )
875
876 /* ISA has three operand multiply instructions that subtracts the
877 result from a 4th operand and puts the result in an accumulator. */
878 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
879 || TARGET_MIPS5500 \
880 || TARGET_SR71K \
881 )
882 /* ISA has three operand multiply instructions that the result
883 from a 4th operand and puts the result in an accumulator. */
884 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
885 || TARGET_MIPS5400 \
886 || TARGET_MIPS5500 \
887 || TARGET_SR71K \
888 )
889
890 /* ISA has 32-bit rotate right instruction. */
891 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
892 && (ISA_MIPS32R2 \
893 || TARGET_MIPS5400 \
894 || TARGET_MIPS5500 \
895 || TARGET_SR71K \
896 ))
897
898 /* ISA has 64-bit rotate right instruction. */
899 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
900 && !TARGET_MIPS16 \
901 && (TARGET_MIPS5400 \
902 || TARGET_MIPS5500 \
903 || TARGET_SR71K \
904 ))
905
906 /* ISA has data prefetch instructions. This controls use of 'pref'. */
907 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
908 || ISA_MIPS32 \
909 || ISA_MIPS32R2 \
910 || ISA_MIPS64) \
911 && !TARGET_MIPS16)
912
913 /* ISA has data indexed prefetch instructions. This controls use of
914 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
915 (prefx is a cop1x instruction, so can only be used if FP is
916 enabled.) */
917 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
918 || ISA_MIPS64) \
919 && !TARGET_MIPS16)
920
921 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
922 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
923 also requires TARGET_DOUBLE_FLOAT. */
924 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
925
926 /* ISA includes the MIPS32r2 seb and seh instructions. */
927 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
928 && (ISA_MIPS32R2 \
929 ))
930
931 /* True if the result of a load is not available to the next instruction.
932 A nop will then be needed between instructions like "lw $4,..."
933 and "addiu $4,$4,1". */
934 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
935 && !TARGET_MIPS3900 \
936 && !TARGET_MIPS16)
937
938 /* Likewise mtc1 and mfc1. */
939 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
940
941 /* Likewise floating-point comparisons. */
942 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
943
944 /* True if mflo and mfhi can be immediately followed by instructions
945 which write to the HI and LO registers. Most targets require a
946 two-instruction gap. */
947 #define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
948 \f
949 /* Add -G xx support. */
950
951 #undef SWITCH_TAKES_ARG
952 #define SWITCH_TAKES_ARG(CHAR) \
953 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
954
955 #define OVERRIDE_OPTIONS override_options ()
956
957 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
958
959 /* Show we can debug even without a frame pointer. */
960 #define CAN_DEBUG_WITHOUT_FP
961 \f
962 /* Tell collect what flags to pass to nm. */
963 #ifndef NM_FLAGS
964 #define NM_FLAGS "-Bn"
965 #endif
966
967 \f
968 /* Assembler specs. */
969
970 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
971 than gas. */
972
973 #define MIPS_AS_ASM_SPEC "\
974 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
975 %{pipe: %e-pipe is not supported} \
976 %{K} %(subtarget_mips_as_asm_spec)"
977
978 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
979 rather than gas. It may be overridden by subtargets. */
980
981 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
982 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
983 #endif
984
985 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
986 assembler. */
987
988 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
989
990 #define SUBTARGET_TARGET_SWITCHES
991
992 #ifndef MIPS_ABI_DEFAULT
993 #define MIPS_ABI_DEFAULT ABI_32
994 #endif
995
996 /* Use the most portable ABI flag for the ASM specs. */
997
998 #if MIPS_ABI_DEFAULT == ABI_32
999 #define MULTILIB_ABI_DEFAULT "mabi=32"
1000 #define ASM_ABI_DEFAULT_SPEC "-32"
1001 #endif
1002
1003 #if MIPS_ABI_DEFAULT == ABI_O64
1004 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1005 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1006 #endif
1007
1008 #if MIPS_ABI_DEFAULT == ABI_N32
1009 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1010 #define ASM_ABI_DEFAULT_SPEC "-n32"
1011 #endif
1012
1013 #if MIPS_ABI_DEFAULT == ABI_64
1014 #define MULTILIB_ABI_DEFAULT "mabi=64"
1015 #define ASM_ABI_DEFAULT_SPEC "-64"
1016 #endif
1017
1018 #if MIPS_ABI_DEFAULT == ABI_EABI
1019 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1020 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1021 #endif
1022
1023 /* Only ELF targets can switch the ABI. */
1024 #ifndef OBJECT_FORMAT_ELF
1025 #undef ASM_ABI_DEFAULT_SPEC
1026 #define ASM_ABI_DEFAULT_SPEC ""
1027 #endif
1028
1029 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1030 GAS_ASM_SPEC as the default, depending upon the value of
1031 TARGET_DEFAULT. */
1032
1033 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1034 /* GAS */
1035
1036 #define TARGET_ASM_SPEC "\
1037 %{mmips-as: %(mips_as_asm_spec)} \
1038 %{!mmips-as: %(gas_asm_spec)}"
1039
1040 #else /* not GAS */
1041
1042 #define TARGET_ASM_SPEC "\
1043 %{!mgas: %(mips_as_asm_spec)} \
1044 %{mgas: %(gas_asm_spec)}"
1045
1046 #endif /* not GAS */
1047
1048 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1049 to the assembler. It may be overridden by subtargets. */
1050 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1051 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1052 %{noasmopt:-O0} \
1053 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1054 #endif
1055
1056 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1057 the assembler. It may be overridden by subtargets. */
1058 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1059 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1060 %{g} %{g0} %{g1} %{g2} %{g3} \
1061 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1062 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1063 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1064 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1065 %(mdebug_asm_spec)"
1066 #endif
1067
1068 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1069 and stabs debugging info. */
1070 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1071 /* GAS */
1072 #define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1073 #else /* not GAS */
1074 #define MDEBUG_ASM_SPEC ""
1075 #endif /* not GAS */
1076
1077 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1078 overridden by subtargets. */
1079
1080 #ifndef SUBTARGET_ASM_SPEC
1081 #define SUBTARGET_ASM_SPEC ""
1082 #endif
1083
1084 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1085 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1086 whether we're using GAS. These options can only be used properly
1087 with GAS, and it is better to get an error from a non-GAS assembler
1088 than to silently generate bad code. */
1089
1090 #undef ASM_SPEC
1091 #define ASM_SPEC "\
1092 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1093 %{mips32} %{mips32r2} %{mips64} \
1094 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1095 %(subtarget_asm_optimizing_spec) \
1096 %(subtarget_asm_debugging_spec) \
1097 %{membedded-pic} \
1098 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1099 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1100 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1101 %(target_asm_spec) \
1102 %(subtarget_asm_spec)"
1103
1104 /* Extra switches sometimes passed to the linker. */
1105 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1106 will interpret it as a -b option. */
1107
1108 #ifndef LINK_SPEC
1109 #define LINK_SPEC "\
1110 %(endian_spec) \
1111 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1112 %{bestGnum} %{shared} %{non_shared}"
1113 #endif /* LINK_SPEC defined */
1114
1115
1116 /* Specs for the compiler proper */
1117
1118 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1119 overridden by subtargets. */
1120 #ifndef SUBTARGET_CC1_SPEC
1121 #define SUBTARGET_CC1_SPEC ""
1122 #endif
1123
1124 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1125
1126 #ifndef CC1_SPEC
1127 #define CC1_SPEC "\
1128 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1129 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1130 %{save-temps: } \
1131 %(subtarget_cc1_spec)"
1132 #endif
1133
1134 /* Preprocessor specs. */
1135
1136 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1137 overridden by subtargets. */
1138 #ifndef SUBTARGET_CPP_SPEC
1139 #define SUBTARGET_CPP_SPEC ""
1140 #endif
1141
1142 #define CPP_SPEC "%(subtarget_cpp_spec)"
1143
1144 /* This macro defines names of additional specifications to put in the specs
1145 that can be used in various specifications like CC1_SPEC. Its definition
1146 is an initializer with a subgrouping for each command option.
1147
1148 Each subgrouping contains a string constant, that defines the
1149 specification name, and a string constant that used by the GCC driver
1150 program.
1151
1152 Do not define this macro if it does not need to do anything. */
1153
1154 #define EXTRA_SPECS \
1155 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1156 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1157 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1158 { "gas_asm_spec", GAS_ASM_SPEC }, \
1159 { "target_asm_spec", TARGET_ASM_SPEC }, \
1160 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1161 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1162 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1163 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1164 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1165 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1166 { "endian_spec", ENDIAN_SPEC }, \
1167 SUBTARGET_EXTRA_SPECS
1168
1169 #ifndef SUBTARGET_EXTRA_SPECS
1170 #define SUBTARGET_EXTRA_SPECS
1171 #endif
1172
1173 /* If defined, this macro is an additional prefix to try after
1174 `STANDARD_EXEC_PREFIX'. */
1175
1176 #ifndef MD_EXEC_PREFIX
1177 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1178 #endif
1179
1180 #ifndef MD_STARTFILE_PREFIX
1181 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1182 #endif
1183
1184 \f
1185 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1186 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1187
1188 /* By default, turn on GDB extensions. */
1189 #define DEFAULT_GDB_EXTENSIONS 1
1190
1191 /* If we are passing smuggling stabs through the MIPS ECOFF object
1192 format, put a comment in front of the .stab<x> operation so
1193 that the MIPS assembler does not choke. The mips-tfile program
1194 will correctly put the stab into the object file. */
1195
1196 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1197 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1198 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1199
1200 /* Local compiler-generated symbols must have a prefix that the assembler
1201 understands. By default, this is $, although some targets (e.g.,
1202 NetBSD-ELF) need to override this. */
1203
1204 #ifndef LOCAL_LABEL_PREFIX
1205 #define LOCAL_LABEL_PREFIX "$"
1206 #endif
1207
1208 /* By default on the mips, external symbols do not have an underscore
1209 prepended, but some targets (e.g., NetBSD) require this. */
1210
1211 #ifndef USER_LABEL_PREFIX
1212 #define USER_LABEL_PREFIX ""
1213 #endif
1214
1215 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1216 since the length can run past this up to a continuation point. */
1217 #undef DBX_CONTIN_LENGTH
1218 #define DBX_CONTIN_LENGTH 1500
1219
1220 /* How to renumber registers for dbx and gdb. */
1221 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1222
1223 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1224 #define DWARF_FRAME_REGNUM(REG) (REG)
1225
1226 /* The DWARF 2 CFA column which tracks the return address. */
1227 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1228
1229 /* The DWARF 2 CFA column which tracks the return address from a
1230 signal handler context. */
1231 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1232
1233 /* Before the prologue, RA lives in r31. */
1234 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1235
1236 /* Describe how we implement __builtin_eh_return. */
1237 #define EH_RETURN_DATA_REGNO(N) \
1238 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1239
1240 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1241
1242 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1243 The default for this in 64-bit mode is 8, which causes problems with
1244 SFmode register saves. */
1245 #define DWARF_CIE_DATA_ALIGNMENT 4
1246
1247 /* Correct the offset of automatic variables and arguments. Note that
1248 the MIPS debug format wants all automatic variables and arguments
1249 to be in terms of the virtual frame pointer (stack pointer before
1250 any adjustment in the function), while the MIPS 3.0 linker wants
1251 the frame pointer to be the stack pointer after the initial
1252 adjustment. */
1253
1254 #define DEBUGGER_AUTO_OFFSET(X) \
1255 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1256 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1257 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1258 \f
1259 /* Target machine storage layout */
1260
1261 #define BITS_BIG_ENDIAN 0
1262 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1263 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1264
1265 /* Define this to set the endianness to use in libgcc2.c, which can
1266 not depend on target_flags. */
1267 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1268 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1269 #else
1270 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1271 #endif
1272
1273 #define MAX_BITS_PER_WORD 64
1274
1275 /* Width of a word, in units (bytes). */
1276 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1277 #define MIN_UNITS_PER_WORD 4
1278
1279 /* For MIPS, width of a floating point register. */
1280 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1281
1282 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1283 the next available register. */
1284 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1285
1286 /* The largest size of value that can be held in floating-point
1287 registers and moved with a single instruction. */
1288 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1289
1290 /* The largest size of value that can be held in floating-point
1291 registers. */
1292 #define UNITS_PER_FPVALUE \
1293 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1294
1295 /* The number of bytes in a double. */
1296 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1297
1298 /* Tell the preprocessor the maximum size of wchar_t. */
1299 #ifndef MAX_WCHAR_TYPE_SIZE
1300 #ifndef WCHAR_TYPE_SIZE
1301 #define MAX_WCHAR_TYPE_SIZE 64
1302 #endif
1303 #endif
1304
1305 /* Set the sizes of the core types. */
1306 #define SHORT_TYPE_SIZE 16
1307 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1308 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1309 #define LONG_LONG_TYPE_SIZE 64
1310
1311 #define MAX_LONG_TYPE_SIZE 64
1312
1313 #define FLOAT_TYPE_SIZE 32
1314 #define DOUBLE_TYPE_SIZE 64
1315 #define LONG_DOUBLE_TYPE_SIZE \
1316 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1317
1318 /* long double is not a fixed mode, but the idea is that, if we
1319 support long double, we also want a 128-bit integer type. */
1320 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1321
1322 #ifdef IN_LIBGCC2
1323 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1324 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1325 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1326 # else
1327 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1328 # endif
1329 #endif
1330
1331 /* Width in bits of a pointer. */
1332 #ifndef POINTER_SIZE
1333 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1334 #endif
1335
1336 #define POINTERS_EXTEND_UNSIGNED 0
1337
1338 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1339 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1340 || mips_abi == ABI_64 \
1341 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1342
1343
1344 /* Allocation boundary (in *bits*) for the code of a function. */
1345 #define FUNCTION_BOUNDARY 32
1346
1347 /* Alignment of field after `int : 0' in a structure. */
1348 #define EMPTY_FIELD_BOUNDARY 32
1349
1350 /* Every structure's size must be a multiple of this. */
1351 /* 8 is observed right on a DECstation and on riscos 4.02. */
1352 #define STRUCTURE_SIZE_BOUNDARY 8
1353
1354 /* There is no point aligning anything to a rounder boundary than this. */
1355 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1356
1357 /* All accesses must be aligned. */
1358 #define STRICT_ALIGNMENT 1
1359
1360 /* Define this if you wish to imitate the way many other C compilers
1361 handle alignment of bitfields and the structures that contain
1362 them.
1363
1364 The behavior is that the type written for a bit-field (`int',
1365 `short', or other integer type) imposes an alignment for the
1366 entire structure, as if the structure really did contain an
1367 ordinary field of that type. In addition, the bit-field is placed
1368 within the structure so that it would fit within such a field,
1369 not crossing a boundary for it.
1370
1371 Thus, on most machines, a bit-field whose type is written as `int'
1372 would not cross a four-byte boundary, and would force four-byte
1373 alignment for the whole structure. (The alignment used may not
1374 be four bytes; it is controlled by the other alignment
1375 parameters.)
1376
1377 If the macro is defined, its definition should be a C expression;
1378 a nonzero value for the expression enables this behavior. */
1379
1380 #define PCC_BITFIELD_TYPE_MATTERS 1
1381
1382 /* If defined, a C expression to compute the alignment given to a
1383 constant that is being placed in memory. CONSTANT is the constant
1384 and ALIGN is the alignment that the object would ordinarily have.
1385 The value of this macro is used instead of that alignment to align
1386 the object.
1387
1388 If this macro is not defined, then ALIGN is used.
1389
1390 The typical use of this macro is to increase alignment for string
1391 constants to be word aligned so that `strcpy' calls that copy
1392 constants can be done inline. */
1393
1394 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1395 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1396 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1397
1398 /* If defined, a C expression to compute the alignment for a static
1399 variable. TYPE is the data type, and ALIGN is the alignment that
1400 the object would ordinarily have. The value of this macro is used
1401 instead of that alignment to align the object.
1402
1403 If this macro is not defined, then ALIGN is used.
1404
1405 One use of this macro is to increase alignment of medium-size
1406 data to make it all fit in fewer cache lines. Another is to
1407 cause character arrays to be word-aligned so that `strcpy' calls
1408 that copy constants to character arrays can be done inline. */
1409
1410 #undef DATA_ALIGNMENT
1411 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1412 ((((ALIGN) < BITS_PER_WORD) \
1413 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1414 || TREE_CODE (TYPE) == UNION_TYPE \
1415 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1416
1417
1418 #define PAD_VARARGS_DOWN \
1419 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1420
1421 /* Arguments declared as 'char' or 'short' in a prototype should be
1422 passed as 'int's. */
1423 #define PROMOTE_PROTOTYPES 1
1424
1425 /* Define if operations between registers always perform the operation
1426 on the full register even if a narrower mode is specified. */
1427 #define WORD_REGISTER_OPERATIONS
1428
1429 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1430 moves. All other references are zero extended. */
1431 #define LOAD_EXTEND_OP(MODE) \
1432 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1433 ? SIGN_EXTEND : ZERO_EXTEND)
1434
1435 /* Define this macro if it is advisable to hold scalars in registers
1436 in a wider mode than that declared by the program. In such cases,
1437 the value is constrained to be within the bounds of the declared
1438 type, but kept valid in the wider mode. The signedness of the
1439 extension may differ from that of the type. */
1440
1441 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1442 if (GET_MODE_CLASS (MODE) == MODE_INT \
1443 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1444 { \
1445 if ((MODE) == SImode) \
1446 (UNSIGNEDP) = 0; \
1447 (MODE) = Pmode; \
1448 }
1449
1450 /* Define if loading short immediate values into registers sign extends. */
1451 #define SHORT_IMMEDIATES_SIGN_EXTEND
1452
1453
1454 /* Define this if function arguments should also be promoted using the above
1455 procedure. */
1456 #define PROMOTE_FUNCTION_ARGS
1457
1458 /* Likewise, if the function return value is promoted. */
1459 #define PROMOTE_FUNCTION_RETURN
1460
1461 \f
1462 /* Standard register usage. */
1463
1464 /* Number of hardware registers. We have:
1465
1466 - 32 integer registers
1467 - 32 floating point registers
1468 - 8 condition code registers
1469 - 2 accumulator registers (hi and lo)
1470 - 32 registers each for coprocessors 0, 2 and 3
1471 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1472 - 5 dummy entries that were used at various times in the past. */
1473
1474 #define FIRST_PSEUDO_REGISTER 176
1475
1476 /* By default, fix the kernel registers ($26 and $27), the global
1477 pointer ($28) and the stack pointer ($29). This can change
1478 depending on the command-line options.
1479
1480 Regarding coprocessor registers: without evidence to the contrary,
1481 it's best to assume that each coprocessor register has a unique
1482 use. This can be overridden, in, e.g., override_options() or
1483 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1484 for a particular target. */
1485
1486 #define FIXED_REGISTERS \
1487 { \
1488 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1489 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1491 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1492 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1493 /* COP0 registers */ \
1494 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1495 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1496 /* COP2 registers */ \
1497 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1498 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1499 /* COP3 registers */ \
1500 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1501 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1502 }
1503
1504
1505 /* Set up this array for o32 by default.
1506
1507 Note that we don't mark $31 as a call-clobbered register. The idea is
1508 that it's really the call instructions themselves which clobber $31.
1509 We don't care what the called function does with it afterwards.
1510
1511 This approach makes it easier to implement sibcalls. Unlike normal
1512 calls, sibcalls don't clobber $31, so the register reaches the
1513 called function in tact. EPILOGUE_USES says that $31 is useful
1514 to the called function. */
1515
1516 #define CALL_USED_REGISTERS \
1517 { \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1520 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1521 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1522 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1523 /* COP0 registers */ \
1524 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1525 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1526 /* COP2 registers */ \
1527 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1528 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1529 /* COP3 registers */ \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1531 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1532 }
1533
1534
1535 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1536
1537 #define CALL_REALLY_USED_REGISTERS \
1538 { /* General registers. */ \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1540 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1541 /* Floating-point registers. */ \
1542 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1543 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1544 /* Others. */ \
1545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1546 /* COP0 registers */ \
1547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1549 /* COP2 registers */ \
1550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1551 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1552 /* COP3 registers */ \
1553 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1554 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1555 }
1556
1557 /* Internal macros to classify a register number as to whether it's a
1558 general purpose register, a floating point register, a
1559 multiply/divide register, or a status register. */
1560
1561 #define GP_REG_FIRST 0
1562 #define GP_REG_LAST 31
1563 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1564 #define GP_DBX_FIRST 0
1565
1566 #define FP_REG_FIRST 32
1567 #define FP_REG_LAST 63
1568 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1569 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1570
1571 #define MD_REG_FIRST 64
1572 #define MD_REG_LAST 65
1573 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1574 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1575
1576 #define ST_REG_FIRST 67
1577 #define ST_REG_LAST 74
1578 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1579
1580
1581 /* FIXME: renumber. */
1582 #define COP0_REG_FIRST 80
1583 #define COP0_REG_LAST 111
1584 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1585
1586 #define COP2_REG_FIRST 112
1587 #define COP2_REG_LAST 143
1588 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1589
1590 #define COP3_REG_FIRST 144
1591 #define COP3_REG_LAST 175
1592 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1593 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1594 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1595
1596 #define AT_REGNUM (GP_REG_FIRST + 1)
1597 #define HI_REGNUM (MD_REG_FIRST + 0)
1598 #define LO_REGNUM (MD_REG_FIRST + 1)
1599
1600 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1601 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1602 should be used instead. */
1603 #define FPSW_REGNUM ST_REG_FIRST
1604
1605 #define GP_REG_P(REGNO) \
1606 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1607 #define M16_REG_P(REGNO) \
1608 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1609 #define FP_REG_P(REGNO) \
1610 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1611 #define MD_REG_P(REGNO) \
1612 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1613 #define ST_REG_P(REGNO) \
1614 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1615 #define COP0_REG_P(REGNO) \
1616 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1617 #define COP2_REG_P(REGNO) \
1618 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1619 #define COP3_REG_P(REGNO) \
1620 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1621 #define ALL_COP_REG_P(REGNO) \
1622 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1623
1624 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1625
1626 /* Return coprocessor number from register number. */
1627
1628 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1629 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1630 : COP3_REG_P (REGNO) ? '3' : '?')
1631
1632
1633 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1634
1635 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1636 array built in override_options. Because machmodes.h is not yet
1637 included before this file is processed, the MODE bound can't be
1638 expressed here. */
1639
1640 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1641
1642 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1643 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1644
1645 /* Value is 1 if it is a good idea to tie two pseudo registers
1646 when one has mode MODE1 and one has mode MODE2.
1647 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1648 for any hard reg, then this must be 0 for correct output. */
1649 #define MODES_TIEABLE_P(MODE1, MODE2) \
1650 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1651 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1652 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1653 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1654
1655 /* Register to use for pushing function arguments. */
1656 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1657
1658 /* Base register for access to local variables of the function. We
1659 pretend that the frame pointer is $1, and then eliminate it to
1660 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1661 a fixed register, and will not be used for anything else. */
1662 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1663
1664 /* $30 is not available on the mips16, so we use $17 as the frame
1665 pointer. */
1666 #define HARD_FRAME_POINTER_REGNUM \
1667 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1668
1669 /* Value should be nonzero if functions must have frame pointers.
1670 Zero means the frame pointer need not be set up (and parms
1671 may be accessed via the stack pointer) in functions that seem suitable.
1672 This is computed in `reload', in reload1.c. */
1673 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1674
1675 /* Base register for access to arguments of the function. */
1676 #define ARG_POINTER_REGNUM GP_REG_FIRST
1677
1678 /* Register in which static-chain is passed to a function. */
1679 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1680
1681 /* Pass structure addresses as an "invisible" first argument. */
1682 #define STRUCT_VALUE 0
1683
1684 /* Registers used as temporaries in prologue/epilogue code. If we're
1685 generating mips16 code, these registers must come from the core set
1686 of 8. The prologue register mustn't conflict with any incoming
1687 arguments, the static chain pointer, or the frame pointer. The
1688 epilogue temporary mustn't conflict with the return registers, the
1689 frame pointer, the EH stack adjustment, or the EH data registers. */
1690
1691 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1692 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1693
1694 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1695 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1696
1697 /* Define this macro if it is as good or better to call a constant
1698 function address than to call an address kept in a register. */
1699 #define NO_FUNCTION_CSE 1
1700
1701 /* Define this macro if it is as good or better for a function to
1702 call itself with an explicit address than to call an address
1703 kept in a register. */
1704 #define NO_RECURSIVE_FUNCTION_CSE 1
1705
1706 /* The ABI-defined global pointer. Sometimes we use a different
1707 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1708 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1709
1710 /* We normally use $28 as the global pointer. However, when generating
1711 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1712 register instead. They can then avoid saving and restoring $28
1713 and perhaps avoid using a frame at all.
1714
1715 When a leaf function uses something other than $28, mips_expand_prologue
1716 will modify pic_offset_table_rtx in place. Take the register number
1717 from there after reload. */
1718 #define PIC_OFFSET_TABLE_REGNUM \
1719 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1720
1721 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1722 \f
1723 /* Define the classes of registers for register constraints in the
1724 machine description. Also define ranges of constants.
1725
1726 One of the classes must always be named ALL_REGS and include all hard regs.
1727 If there is more than one class, another class must be named NO_REGS
1728 and contain no registers.
1729
1730 The name GENERAL_REGS must be the name of a class (or an alias for
1731 another name such as ALL_REGS). This is the class of registers
1732 that is allowed by "g" or "r" in a register constraint.
1733 Also, registers outside this class are allocated only when
1734 instructions express preferences for them.
1735
1736 The classes must be numbered in nondecreasing order; that is,
1737 a larger-numbered class must never be contained completely
1738 in a smaller-numbered class.
1739
1740 For any two classes, it is very desirable that there be another
1741 class that represents their union. */
1742
1743 enum reg_class
1744 {
1745 NO_REGS, /* no registers in set */
1746 M16_NA_REGS, /* mips16 regs not used to pass args */
1747 M16_REGS, /* mips16 directly accessible registers */
1748 T_REG, /* mips16 T register ($24) */
1749 M16_T_REGS, /* mips16 registers plus T register */
1750 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1751 LEA_REGS, /* Every GPR except $25 */
1752 GR_REGS, /* integer registers */
1753 FP_REGS, /* floating point registers */
1754 HI_REG, /* hi register */
1755 LO_REG, /* lo register */
1756 MD_REGS, /* multiply/divide registers (hi/lo) */
1757 COP0_REGS, /* generic coprocessor classes */
1758 COP2_REGS,
1759 COP3_REGS,
1760 HI_AND_GR_REGS, /* union classes */
1761 LO_AND_GR_REGS,
1762 HI_AND_FP_REGS,
1763 COP0_AND_GR_REGS,
1764 COP2_AND_GR_REGS,
1765 COP3_AND_GR_REGS,
1766 ALL_COP_REGS,
1767 ALL_COP_AND_GR_REGS,
1768 ST_REGS, /* status registers (fp status) */
1769 ALL_REGS, /* all registers */
1770 LIM_REG_CLASSES /* max value + 1 */
1771 };
1772
1773 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1774
1775 #define GENERAL_REGS GR_REGS
1776
1777 /* An initializer containing the names of the register classes as C
1778 string constants. These names are used in writing some of the
1779 debugging dumps. */
1780
1781 #define REG_CLASS_NAMES \
1782 { \
1783 "NO_REGS", \
1784 "M16_NA_REGS", \
1785 "M16_REGS", \
1786 "T_REG", \
1787 "M16_T_REGS", \
1788 "PIC_FN_ADDR_REG", \
1789 "LEA_REGS", \
1790 "GR_REGS", \
1791 "FP_REGS", \
1792 "HI_REG", \
1793 "LO_REG", \
1794 "MD_REGS", \
1795 /* coprocessor registers */ \
1796 "COP0_REGS", \
1797 "COP2_REGS", \
1798 "COP3_REGS", \
1799 "HI_AND_GR_REGS", \
1800 "LO_AND_GR_REGS", \
1801 "HI_AND_FP_REGS", \
1802 "COP0_AND_GR_REGS", \
1803 "COP2_AND_GR_REGS", \
1804 "COP3_AND_GR_REGS", \
1805 "ALL_COP_REGS", \
1806 "ALL_COP_AND_GR_REGS", \
1807 "ST_REGS", \
1808 "ALL_REGS" \
1809 }
1810
1811 /* An initializer containing the contents of the register classes,
1812 as integers which are bit masks. The Nth integer specifies the
1813 contents of class N. The way the integer MASK is interpreted is
1814 that register R is in the class if `MASK & (1 << R)' is 1.
1815
1816 When the machine has more than 32 registers, an integer does not
1817 suffice. Then the integers are replaced by sub-initializers,
1818 braced groupings containing several integers. Each
1819 sub-initializer must be suitable as an initializer for the type
1820 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1821
1822 #define REG_CLASS_CONTENTS \
1823 { \
1824 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1825 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1826 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1827 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1828 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1829 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1830 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1831 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1832 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1833 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1834 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1835 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1836 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1837 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1838 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1839 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1840 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1841 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1842 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1843 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1844 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1845 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1846 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1847 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1848 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1849 }
1850
1851
1852 /* A C expression whose value is a register class containing hard
1853 register REGNO. In general there is more that one such class;
1854 choose a class which is "minimal", meaning that no smaller class
1855 also contains the register. */
1856
1857 extern const enum reg_class mips_regno_to_class[];
1858
1859 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1860
1861 /* A macro whose definition is the name of the class to which a
1862 valid base register must belong. A base register is one used in
1863 an address which is the register value plus a displacement. */
1864
1865 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1866
1867 /* A macro whose definition is the name of the class to which a
1868 valid index register must belong. An index register is one used
1869 in an address where its value is either multiplied by a scale
1870 factor or added to another register (as well as added to a
1871 displacement). */
1872
1873 #define INDEX_REG_CLASS NO_REGS
1874
1875 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1876 registers explicitly used in the rtl to be used as spill registers
1877 but prevents the compiler from extending the lifetime of these
1878 registers. */
1879
1880 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1881
1882 /* This macro is used later on in the file. */
1883 #define GR_REG_CLASS_P(CLASS) \
1884 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1885 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1886 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1887
1888 /* This macro is also used later on in the file. */
1889 #define COP_REG_CLASS_P(CLASS) \
1890 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1891
1892 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1893 is the default value (allocate the registers in numeric order). We
1894 define it just so that we can override it for the mips16 target in
1895 ORDER_REGS_FOR_LOCAL_ALLOC. */
1896
1897 #define REG_ALLOC_ORDER \
1898 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1899 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1900 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1901 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1902 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1903 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1904 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1905 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1906 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1907 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1908 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1909 }
1910
1911 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1912 to be rearranged based on a particular function. On the mips16, we
1913 want to allocate $24 (T_REG) before other registers for
1914 instructions for which it is possible. */
1915
1916 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1917
1918 /* REGISTER AND CONSTANT CLASSES */
1919
1920 /* Get reg_class from a letter such as appears in the machine
1921 description.
1922
1923 DEFINED REGISTER CLASSES:
1924
1925 'd' General (aka integer) registers
1926 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1927 'y' General registers (in both mips16 and non mips16 mode)
1928 'e' mips16 non argument registers (M16_NA_REGS)
1929 't' mips16 temporary register ($24)
1930 'f' Floating point registers
1931 'h' Hi register
1932 'l' Lo register
1933 'x' Multiply/divide registers
1934 'z' FP Status register
1935 'B' Cop0 register
1936 'C' Cop2 register
1937 'D' Cop3 register
1938 'b' All registers */
1939
1940 extern enum reg_class mips_char_to_class[256];
1941
1942 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1943
1944 /* True if VALUE is a signed 16-bit number. */
1945
1946 #define SMALL_OPERAND(VALUE) \
1947 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1948
1949 /* True if VALUE is an unsigned 16-bit number. */
1950
1951 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1952 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1953
1954 /* True if VALUE can be loaded into a register using LUI. */
1955
1956 #define LUI_OPERAND(VALUE) \
1957 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1958 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1959
1960 /* Return a value X with the low 16 bits clear, and such that
1961 VALUE - X is a signed 16-bit value. */
1962
1963 #define CONST_HIGH_PART(VALUE) \
1964 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1965
1966 #define CONST_LOW_PART(VALUE) \
1967 ((VALUE) - CONST_HIGH_PART (VALUE))
1968
1969 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1970 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1971 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1972
1973 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1974 string can be used to stand for particular ranges of immediate
1975 operands. This macro defines what the ranges are. C is the
1976 letter, and VALUE is a constant value. Return 1 if VALUE is
1977 in the range specified by C. */
1978
1979 /* For MIPS:
1980
1981 `I' is used for the range of constants an arithmetic insn can
1982 actually contain (16 bits signed integers).
1983
1984 `J' is used for the range which is just zero (ie, $r0).
1985
1986 `K' is used for the range of constants a logical insn can actually
1987 contain (16 bit zero-extended integers).
1988
1989 `L' is used for the range of constants that be loaded with lui
1990 (ie, the bottom 16 bits are zero).
1991
1992 `M' is used for the range of constants that take two words to load
1993 (ie, not matched by `I', `K', and `L').
1994
1995 `N' is used for negative 16 bit constants other than -65536.
1996
1997 `O' is a 15 bit signed integer.
1998
1999 `P' is used for positive 16 bit constants. */
2000
2001 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2002 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2003 : (C) == 'J' ? ((VALUE) == 0) \
2004 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2005 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2006 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2007 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2008 && !LUI_OPERAND (VALUE)) \
2009 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2010 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2011 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2012 : 0)
2013
2014 /* Similar, but for floating constants, and defining letters G and H.
2015 Here VALUE is the CONST_DOUBLE rtx itself. */
2016
2017 /* For Mips
2018
2019 'G' : Floating point 0 */
2020
2021 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2022 ((C) == 'G' \
2023 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2024
2025 /* True if OP is a constant that should not be moved into $25.
2026 We need this because many versions of gas treat 'la $25,foo' as
2027 part of a call sequence and allow a global 'foo' to be lazily bound. */
2028
2029 #define DANGEROUS_FOR_LA25_P(OP) \
2030 (!TARGET_EXPLICIT_RELOCS && global_got_operand (OP, VOIDmode))
2031
2032 /* Letters in the range `Q' through `U' may be defined in a
2033 machine-dependent fashion to stand for arbitrary operand types.
2034 The machine description macro `EXTRA_CONSTRAINT' is passed the
2035 operand as its first argument and the constraint letter as its
2036 second operand.
2037
2038 `Q' is for signed 16-bit constants.
2039 `R' is for single-instruction memory references. Note that this
2040 constraint has often been used in linux and glibc code.
2041 `S' is for legitimate constant call addresses.
2042 `T' is for constant move_operands that cannot be safely loaded into $25.
2043 `U' is for constant move_operands that can be safely loaded into $25.
2044 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2045 This is true for all non-mips16 references (although it can somtimes
2046 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2047 stack and constant-pool references. */
2048
2049 #define EXTRA_CONSTRAINT(OP,CODE) \
2050 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2051 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2052 && mips_fetch_insns (OP) == 1) \
2053 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2054 && call_insn_operand (OP, VOIDmode)) \
2055 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2056 && move_operand (OP, VOIDmode) \
2057 && DANGEROUS_FOR_LA25_P (OP)) \
2058 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2059 && move_operand (OP, VOIDmode) \
2060 && !DANGEROUS_FOR_LA25_P (OP)) \
2061 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2062 && memory_operand (OP, VOIDmode) \
2063 && (!TARGET_MIPS16 \
2064 || (!stack_operand (OP, VOIDmode) \
2065 && !CONSTANT_P (XEXP (OP, 0))))) \
2066 : FALSE)
2067
2068 /* Say which of the above are memory constraints. */
2069 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2070
2071 /* Given an rtx X being reloaded into a reg required to be
2072 in class CLASS, return the class of reg to actually use.
2073 In general this is just CLASS; but on some machines
2074 in some cases it is preferable to use a more restrictive class. */
2075
2076 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2077 ((CLASS) != ALL_REGS \
2078 ? (! TARGET_MIPS16 \
2079 ? (CLASS) \
2080 : ((CLASS) != GR_REGS \
2081 ? (CLASS) \
2082 : M16_REGS)) \
2083 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2084 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2085 ? (TARGET_SOFT_FLOAT \
2086 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2087 : FP_REGS) \
2088 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2089 || GET_MODE (X) == VOIDmode) \
2090 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2091 : (CLASS))))
2092
2093 /* Certain machines have the property that some registers cannot be
2094 copied to some other registers without using memory. Define this
2095 macro on those machines to be a C expression that is nonzero if
2096 objects of mode MODE in registers of CLASS1 can only be copied to
2097 registers of class CLASS2 by storing a register of CLASS1 into
2098 memory and loading that memory location into a register of CLASS2.
2099
2100 Do not define this macro if its value would always be zero. */
2101 #if 0
2102 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2103 ((!TARGET_DEBUG_H_MODE \
2104 && GET_MODE_CLASS (MODE) == MODE_INT \
2105 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2106 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2107 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2108 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2109 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2110 #endif
2111 /* The HI and LO registers can only be reloaded via the general
2112 registers. Condition code registers can only be loaded to the
2113 general registers, and from the floating point registers. */
2114
2115 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2116 mips_secondary_reload_class (CLASS, MODE, X, 1)
2117 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2118 mips_secondary_reload_class (CLASS, MODE, X, 0)
2119
2120 /* Return the maximum number of consecutive registers
2121 needed to represent mode MODE in a register of class CLASS. */
2122
2123 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2124
2125 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2126 mips_cannot_change_mode_class (FROM, TO, CLASS)
2127 \f
2128 /* Stack layout; function entry, exit and calling. */
2129
2130 #define STACK_GROWS_DOWNWARD
2131
2132 /* The offset of the first local variable from the beginning of the frame.
2133 See compute_frame_size for details about the frame layout. */
2134 #define STARTING_FRAME_OFFSET \
2135 (current_function_outgoing_args_size \
2136 + (TARGET_ABICALLS && !TARGET_NEWABI \
2137 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2138
2139 #define RETURN_ADDR_RTX mips_return_addr
2140
2141 /* Since the mips16 ISA mode is encoded in the least-significant bit
2142 of the address, mask it off return addresses for purposes of
2143 finding exception handling regions. */
2144
2145 #define MASK_RETURN_ADDR GEN_INT (-2)
2146
2147
2148 /* Similarly, don't use the least-significant bit to tell pointers to
2149 code from vtable index. */
2150
2151 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2152
2153 /* The eliminations to $17 are only used for mips16 code. See the
2154 definition of HARD_FRAME_POINTER_REGNUM. */
2155
2156 #define ELIMINABLE_REGS \
2157 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2158 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2159 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2160 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2161 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2162 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2163
2164 /* We can always eliminate to the hard frame pointer. We can eliminate
2165 to the stack pointer unless a frame pointer is needed.
2166
2167 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2168 reload may be unable to compute the address of a local variable,
2169 since there is no way to add a large constant to the stack pointer
2170 without using a temporary register. */
2171 #define CAN_ELIMINATE(FROM, TO) \
2172 ((TO) == HARD_FRAME_POINTER_REGNUM \
2173 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2174 && (!TARGET_MIPS16 \
2175 || compute_frame_size (get_frame_size ()) < 32768)))
2176
2177 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2178 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2179
2180 /* Allocate stack space for arguments at the beginning of each function. */
2181 #define ACCUMULATE_OUTGOING_ARGS 1
2182
2183 /* The argument pointer always points to the first argument. */
2184 #define FIRST_PARM_OFFSET(FNDECL) 0
2185
2186 /* o32 and o64 reserve stack space for all argument registers. */
2187 #define REG_PARM_STACK_SPACE(FNDECL) \
2188 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2189 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2190 : 0)
2191
2192 /* Define this if it is the responsibility of the caller to
2193 allocate the area reserved for arguments passed in registers.
2194 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2195 of this macro is to determine whether the space is included in
2196 `current_function_outgoing_args_size'. */
2197 #define OUTGOING_REG_PARM_STACK_SPACE
2198
2199 #define STACK_BOUNDARY \
2200 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2201 ? 64 : 128)
2202
2203 \f
2204 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2205
2206 /* Symbolic macros for the registers used to return integer and floating
2207 point values. */
2208
2209 #define GP_RETURN (GP_REG_FIRST + 2)
2210 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2211
2212 #define MAX_ARGS_IN_REGISTERS \
2213 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2214
2215 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2216
2217 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2218
2219 /* Symbolic macros for the first/last argument registers. */
2220
2221 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2222 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2223 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2224 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2225
2226 #define LIBCALL_VALUE(MODE) \
2227 mips_function_value (NULL_TREE, NULL, (MODE))
2228
2229 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2230 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2231
2232 /* 1 if N is a possible register number for a function value.
2233 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2234 Currently, R2 and F0 are only implemented here (C has no complex type) */
2235
2236 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2237 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2238 && (N) == FP_RETURN + 2))
2239
2240 /* 1 if N is a possible register number for function argument passing.
2241 We have no FP argument registers when soft-float. When FP registers
2242 are 32 bits, we can't directly reference the odd numbered ones. */
2243
2244 #define FUNCTION_ARG_REGNO_P(N) \
2245 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2246 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2247 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2248 && !fixed_regs[N])
2249
2250 #define RETURN_IN_MEMORY(TYPE) mips_return_in_memory (TYPE)
2251
2252 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2253 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2254 (TYPE), (NO_RTL))
2255 \f
2256 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2257
2258 /* This structure has to cope with two different argument allocation
2259 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2260 first N words go in registers and the rest go on the stack. If I < N,
2261 the Ith word might go in Ith integer argument register or the
2262 Ith floating-point one. For these ABIs, we only need to remember
2263 the number of words passed so far.
2264
2265 The EABI instead allocates the integer and floating-point arguments
2266 separately. The first N words of FP arguments go in FP registers,
2267 the rest go on the stack. Likewise, the first N words of the other
2268 arguments go in integer registers, and the rest go on the stack. We
2269 need to maintain three counts: the number of integer registers used,
2270 the number of floating-point registers used, and the number of words
2271 passed on the stack.
2272
2273 We could keep separate information for the two ABIs (a word count for
2274 the standard ABIs, and three separate counts for the EABI). But it
2275 seems simpler to view the standard ABIs as forms of EABI that do not
2276 allocate floating-point registers.
2277
2278 So for the standard ABIs, the first N words are allocated to integer
2279 registers, and function_arg decides on an argument-by-argument basis
2280 whether that argument should really go in an integer register, or in
2281 a floating-point one. */
2282
2283 typedef struct mips_args {
2284 /* Always true for varargs functions. Otherwise true if at least
2285 one argument has been passed in an integer register. */
2286 int gp_reg_found;
2287
2288 /* The number of arguments seen so far. */
2289 unsigned int arg_number;
2290
2291 /* For EABI, the number of integer registers used so far. For other
2292 ABIs, the number of words passed in registers (whether integer
2293 or floating-point). */
2294 unsigned int num_gprs;
2295
2296 /* For EABI, the number of floating-point registers used so far. */
2297 unsigned int num_fprs;
2298
2299 /* The number of words passed on the stack. */
2300 unsigned int stack_words;
2301
2302 /* On the mips16, we need to keep track of which floating point
2303 arguments were passed in general registers, but would have been
2304 passed in the FP regs if this were a 32 bit function, so that we
2305 can move them to the FP regs if we wind up calling a 32 bit
2306 function. We record this information in fp_code, encoded in base
2307 four. A zero digit means no floating point argument, a one digit
2308 means an SFmode argument, and a two digit means a DFmode argument,
2309 and a three digit is not used. The low order digit is the first
2310 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2311 an SFmode argument. ??? A more sophisticated approach will be
2312 needed if MIPS_ABI != ABI_32. */
2313 int fp_code;
2314
2315 /* True if the function has a prototype. */
2316 int prototype;
2317 } CUMULATIVE_ARGS;
2318
2319 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2320 for a call to a function whose data type is FNTYPE.
2321 For a library call, FNTYPE is 0. */
2322
2323 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2324 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2325
2326 /* Update the data in CUM to advance over an argument
2327 of mode MODE and data type TYPE.
2328 (TYPE is null for libcalls where that information may not be available.) */
2329
2330 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2331 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2332
2333 /* Determine where to put an argument to a function.
2334 Value is zero to push the argument on the stack,
2335 or a hard register in which to store the argument.
2336
2337 MODE is the argument's machine mode.
2338 TYPE is the data type of the argument (as a tree).
2339 This is null for libcalls where that information may
2340 not be available.
2341 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2342 the preceding args and about the function being called.
2343 NAMED is nonzero if this argument is a named parameter
2344 (otherwise it is an extra parameter matching an ellipsis). */
2345
2346 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2347 function_arg( &CUM, MODE, TYPE, NAMED)
2348
2349 /* For an arg passed partly in registers and partly in memory,
2350 this is the number of registers used.
2351 For args passed entirely in registers or entirely in memory, zero. */
2352
2353 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2354 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2355
2356 /* If defined, a C expression that gives the alignment boundary, in
2357 bits, of an argument with the specified mode and type. If it is
2358 not defined, `PARM_BOUNDARY' is used for all arguments. */
2359
2360 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2361 (((TYPE) != 0) \
2362 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2363 ? PARM_BOUNDARY \
2364 : TYPE_ALIGN(TYPE)) \
2365 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2366 ? PARM_BOUNDARY \
2367 : GET_MODE_ALIGNMENT(MODE)))
2368
2369 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2370 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2371
2372 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2373 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2374
2375 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2376 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2377
2378 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2379 (mips_abi == ABI_EABI && (NAMED) \
2380 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2381
2382 /* Modified version of the macro in expr.h. Only return true if
2383 the type has a variable size or if the front end requires it
2384 to be passed by reference. */
2385 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2386 ((TYPE) != 0 \
2387 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2388 || TREE_ADDRESSABLE (TYPE)))
2389
2390 /* True if using EABI and varargs can be passed in floating-point
2391 registers. Under these conditions, we need a more complex form
2392 of va_list, which tracks GPR, FPR and stack arguments separately. */
2393 #define EABI_FLOAT_VARARGS_P \
2394 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2395
2396 \f
2397 /* Say that the epilogue uses the return address register. Note that
2398 in the case of sibcalls, the values "used by the epilogue" are
2399 considered live at the start of the called function. */
2400 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2401
2402 /* Treat LOC as a byte offset from the stack pointer and round it up
2403 to the next fully-aligned offset. */
2404 #define MIPS_STACK_ALIGN(LOC) \
2405 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2406 ? ((LOC) + 7) & ~7 \
2407 : ((LOC) + 15) & ~15)
2408
2409 \f
2410 /* Implement `va_start' for varargs and stdarg. */
2411 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2412 mips_va_start (valist, nextarg)
2413
2414 /* Implement `va_arg'. */
2415 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2416 mips_va_arg (valist, type)
2417 \f
2418 /* Output assembler code to FILE to increment profiler label # LABELNO
2419 for profiling a function entry. */
2420
2421 #define FUNCTION_PROFILER(FILE, LABELNO) \
2422 { \
2423 if (TARGET_MIPS16) \
2424 sorry ("mips16 function profiling"); \
2425 fprintf (FILE, "\t.set\tnoat\n"); \
2426 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2427 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2428 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2429 { \
2430 fprintf (FILE, \
2431 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2432 TARGET_64BIT ? "dsubu" : "subu", \
2433 reg_names[STACK_POINTER_REGNUM], \
2434 reg_names[STACK_POINTER_REGNUM], \
2435 Pmode == DImode ? 16 : 8); \
2436 } \
2437 fprintf (FILE, "\tjal\t_mcount\n"); \
2438 fprintf (FILE, "\t.set\tat\n"); \
2439 }
2440
2441 /* Define this macro if the code for function profiling should come
2442 before the function prologue. Normally, the profiling code comes
2443 after. */
2444
2445 /* #define PROFILE_BEFORE_PROLOGUE */
2446
2447 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2448 the stack pointer does not matter. The value is tested only in
2449 functions that have frame pointers.
2450 No definition is equivalent to always zero. */
2451
2452 #define EXIT_IGNORE_STACK 1
2453
2454 \f
2455 /* A C statement to output, on the stream FILE, assembler code for a
2456 block of data that contains the constant parts of a trampoline.
2457 This code should not include a label--the label is taken care of
2458 automatically. */
2459
2460 #define TRAMPOLINE_TEMPLATE(STREAM) \
2461 { \
2462 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2463 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2464 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2465 if (ptr_mode == DImode) \
2466 { \
2467 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2468 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2469 } \
2470 else \
2471 { \
2472 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2473 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2474 } \
2475 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2476 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2477 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2478 if (ptr_mode == DImode) \
2479 { \
2480 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2481 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2482 } \
2483 else \
2484 { \
2485 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2486 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2487 } \
2488 }
2489
2490 /* A C expression for the size in bytes of the trampoline, as an
2491 integer. */
2492
2493 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2494
2495 /* Alignment required for trampolines, in bits. */
2496
2497 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2498
2499 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2500 program and data caches. */
2501
2502 #ifndef CACHE_FLUSH_FUNC
2503 #define CACHE_FLUSH_FUNC "_flush_cache"
2504 #endif
2505
2506 /* A C statement to initialize the variable parts of a trampoline.
2507 ADDR is an RTX for the address of the trampoline; FNADDR is an
2508 RTX for the address of the nested function; STATIC_CHAIN is an
2509 RTX for the static chain value that should be passed to the
2510 function when it is called. */
2511
2512 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2513 { \
2514 rtx func_addr, chain_addr; \
2515 \
2516 func_addr = plus_constant (ADDR, 32); \
2517 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2518 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2519 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2520 \
2521 /* Flush both caches. We need to flush the data cache in case \
2522 the system has a write-back cache. */ \
2523 /* ??? Should check the return value for errors. */ \
2524 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2525 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2526 0, VOIDmode, 3, ADDR, Pmode, \
2527 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2528 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2529 }
2530 \f
2531 /* Addressing modes, and classification of registers for them. */
2532
2533 /* These assume that REGNO is a hard or pseudo reg number.
2534 They give nonzero only if REGNO is a hard reg of the suitable class
2535 or a pseudo reg currently allocated to a suitable hard reg.
2536 These definitions are NOT overridden anywhere. */
2537
2538 #define BASE_REG_P(regno, mode) \
2539 (TARGET_MIPS16 \
2540 ? (M16_REG_P (regno) \
2541 || (regno) == FRAME_POINTER_REGNUM \
2542 || (regno) == ARG_POINTER_REGNUM \
2543 || ((regno) == STACK_POINTER_REGNUM \
2544 && (GET_MODE_SIZE (mode) == 4 \
2545 || GET_MODE_SIZE (mode) == 8))) \
2546 : GP_REG_P (regno))
2547
2548 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2549 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2550 (mode))
2551
2552 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2553 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2554
2555 #define REGNO_OK_FOR_INDEX_P(regno) 0
2556 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2557 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2558
2559 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2560 and check its validity for a certain class.
2561 We have two alternate definitions for each of them.
2562 The usual definition accepts all pseudo regs; the other rejects them all.
2563 The symbol REG_OK_STRICT causes the latter definition to be used.
2564
2565 Most source files want to accept pseudo regs in the hope that
2566 they will get allocated to the class that the insn wants them to be in.
2567 Some source files that are used after register allocation
2568 need to be strict. */
2569
2570 #ifndef REG_OK_STRICT
2571 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2572 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2573 #else
2574 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2575 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2576 #endif
2577
2578 #define REG_OK_FOR_INDEX_P(X) 0
2579
2580 \f
2581 /* Maximum number of registers that can appear in a valid memory address. */
2582
2583 #define MAX_REGS_PER_ADDRESS 1
2584
2585 /* A C compound statement with a conditional `goto LABEL;' executed
2586 if X (an RTX) is a legitimate memory address on the target
2587 machine for a memory operand of mode MODE. */
2588
2589 #if 1
2590 #define GO_PRINTF(x) fprintf(stderr, (x))
2591 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2592 #define GO_DEBUG_RTX(x) debug_rtx(x)
2593
2594 #else
2595 #define GO_PRINTF(x)
2596 #define GO_PRINTF2(x,y)
2597 #define GO_DEBUG_RTX(x)
2598 #endif
2599
2600 #ifdef REG_OK_STRICT
2601 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2602 { \
2603 if (mips_legitimate_address_p (MODE, X, 1)) \
2604 goto ADDR; \
2605 }
2606 #else
2607 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2608 { \
2609 if (mips_legitimate_address_p (MODE, X, 0)) \
2610 goto ADDR; \
2611 }
2612 #endif
2613
2614 /* Check for constness inline but use mips_legitimate_address_p
2615 to check whether a constant really is an address. */
2616
2617 #define CONSTANT_ADDRESS_P(X) \
2618 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2619
2620 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2621
2622 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2623 do { \
2624 if (mips_legitimize_address (&(X), MODE)) \
2625 goto WIN; \
2626 } while (0)
2627
2628
2629 /* A C statement or compound statement with a conditional `goto
2630 LABEL;' executed if memory address X (an RTX) can have different
2631 meanings depending on the machine mode of the memory reference it
2632 is used for.
2633
2634 Autoincrement and autodecrement addresses typically have
2635 mode-dependent effects because the amount of the increment or
2636 decrement is the size of the operand being addressed. Some
2637 machines have other mode-dependent addresses. Many RISC machines
2638 have no mode-dependent addresses.
2639
2640 You may assume that ADDR is a valid address for the machine. */
2641
2642 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2643
2644 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2645 'the start of the function that this code is output in'. */
2646
2647 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2648 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2649 asm_fprintf ((FILE), "%U%s", \
2650 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2651 else \
2652 asm_fprintf ((FILE), "%U%s", (NAME))
2653
2654 /* The mips16 wants the constant pool to be after the function,
2655 because the PC relative load instructions use unsigned offsets. */
2656
2657 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
2658
2659 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
2660 mips_string_length = 0;
2661 \f
2662 /* Specify the machine mode that this machine uses
2663 for the index in the tablejump instruction.
2664 ??? Using HImode in mips16 mode can cause overflow. */
2665 #define CASE_VECTOR_MODE \
2666 (TARGET_MIPS16 ? HImode : ptr_mode)
2667
2668 /* Define as C expression which evaluates to nonzero if the tablejump
2669 instruction expects the table to contain offsets from the address of the
2670 table.
2671 Do not define this if the table should contain absolute addresses. */
2672 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2673
2674 /* Define this as 1 if `char' should by default be signed; else as 0. */
2675 #ifndef DEFAULT_SIGNED_CHAR
2676 #define DEFAULT_SIGNED_CHAR 1
2677 #endif
2678
2679 /* Max number of bytes we can move from memory to memory
2680 in one reasonably fast instruction. */
2681 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2682 #define MAX_MOVE_MAX 8
2683
2684 /* Define this macro as a C expression which is nonzero if
2685 accessing less than a word of memory (i.e. a `char' or a
2686 `short') is no faster than accessing a word of memory, i.e., if
2687 such access require more than one instruction or if there is no
2688 difference in cost between byte and (aligned) word loads.
2689
2690 On RISC machines, it tends to generate better code to define
2691 this as 1, since it avoids making a QI or HI mode register. */
2692 #define SLOW_BYTE_ACCESS 1
2693
2694 /* Define this to be nonzero if shift instructions ignore all but the low-order
2695 few bits. */
2696 #define SHIFT_COUNT_TRUNCATED 1
2697
2698 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2699 is done just by pretending it is already truncated. */
2700 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2701 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2702
2703
2704 /* Specify the machine mode that pointers have.
2705 After generation of rtl, the compiler makes no further distinction
2706 between pointers and any other objects of this machine mode. */
2707
2708 #ifndef Pmode
2709 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2710 #endif
2711
2712 /* Give call MEMs SImode since it is the "most permissive" mode
2713 for both 32-bit and 64-bit targets. */
2714
2715 #define FUNCTION_MODE SImode
2716
2717 \f
2718 /* The cost of loading values from the constant pool. It should be
2719 larger than the cost of any constant we want to synthesize in-line. */
2720
2721 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2722
2723 /* A C expression for the cost of moving data from a register in
2724 class FROM to one in class TO. The classes are expressed using
2725 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2726 the default; other values are interpreted relative to that.
2727
2728 It is not required that the cost always equal 2 when FROM is the
2729 same as TO; on some machines it is expensive to move between
2730 registers if they are not general registers.
2731
2732 If reload sees an insn consisting of a single `set' between two
2733 hard registers, and if `REGISTER_MOVE_COST' applied to their
2734 classes returns a value of 2, reload does not check to ensure
2735 that the constraints of the insn are met. Setting a cost of
2736 other than 2 will allow reload to verify that the constraints are
2737 met. You should do this if the `movM' pattern's constraints do
2738 not allow such copying. */
2739
2740 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2741 mips_register_move_cost (MODE, FROM, TO)
2742
2743 /* ??? Fix this to be right for the R8000. */
2744 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2745 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2746 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2747
2748 /* Define if copies to/from condition code registers should be avoided.
2749
2750 This is needed for the MIPS because reload_outcc is not complete;
2751 it needs to handle cases where the source is a general or another
2752 condition code register. */
2753 #define AVOID_CCMODE_COPIES
2754
2755 /* A C expression for the cost of a branch instruction. A value of
2756 1 is the default; other values are interpreted relative to that. */
2757
2758 /* ??? Fix this to be right for the R8000. */
2759 #define BRANCH_COST \
2760 ((! TARGET_MIPS16 \
2761 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2762 ? 2 : 1)
2763
2764 /* If defined, modifies the length assigned to instruction INSN as a
2765 function of the context in which it is used. LENGTH is an lvalue
2766 that contains the initially computed length of the insn and should
2767 be updated with the correct length of the insn. */
2768 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2769 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2770
2771 \f
2772 /* Optionally define this if you have added predicates to
2773 `MACHINE.c'. This macro is called within an initializer of an
2774 array of structures. The first field in the structure is the
2775 name of a predicate and the second field is an array of rtl
2776 codes. For each predicate, list all rtl codes that can be in
2777 expressions matched by the predicate. The list should have a
2778 trailing comma. Here is an example of two entries in the list
2779 for a typical RISC machine:
2780
2781 #define PREDICATE_CODES \
2782 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2783 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2784
2785 Defining this macro does not affect the generated code (however,
2786 incorrect definitions that omit an rtl code that may be matched
2787 by the predicate can cause the compiler to malfunction).
2788 Instead, it allows the table built by `genrecog' to be more
2789 compact and efficient, thus speeding up the compiler. The most
2790 important predicates to include in the list specified by this
2791 macro are thoses used in the most insn patterns. */
2792
2793 #define PREDICATE_CODES \
2794 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
2795 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2796 {"global_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2797 {"local_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2798 {"const_arith_operand", { CONST_INT }}, \
2799 {"small_data_pattern", { SET, PARALLEL, UNSPEC, \
2800 UNSPEC_VOLATILE }}, \
2801 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
2802 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
2803 {"small_int", { CONST_INT }}, \
2804 {"mips_const_double_ok", { CONST_DOUBLE }}, \
2805 {"const_float_1_operand", { CONST_DOUBLE }}, \
2806 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2807 {"simple_memory_operand", { MEM, SUBREG }}, \
2808 {"equality_op", { EQ, NE }}, \
2809 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2810 LTU, LEU }}, \
2811 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2812 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2813 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2814 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2815 SYMBOL_REF, LABEL_REF, SUBREG, \
2816 REG, MEM}}, \
2817 {"stack_operand", { MEM }}, \
2818 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2819 CONST_DOUBLE, CONST }}, \
2820 {"fcc_register_operand", { REG, SUBREG }}, \
2821 {"hilo_operand", { REG }}, \
2822 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2823
2824 /* A list of predicates that do special things with modes, and so
2825 should not elicit warnings for VOIDmode match_operand. */
2826
2827 #define SPECIAL_MODE_PREDICATES \
2828 "pc_or_label_operand",
2829 \f
2830 /* Control the assembler format that we output. */
2831
2832 /* Output to assembler file text saying following lines
2833 may contain character constants, extra white space, comments, etc. */
2834
2835 #ifndef ASM_APP_ON
2836 #define ASM_APP_ON " #APP\n"
2837 #endif
2838
2839 /* Output to assembler file text saying following lines
2840 no longer contain unusual constructs. */
2841
2842 #ifndef ASM_APP_OFF
2843 #define ASM_APP_OFF " #NO_APP\n"
2844 #endif
2845
2846 /* How to refer to registers in assembler output.
2847 This sequence is indexed by compiler's hard-register-number (see above).
2848
2849 In order to support the two different conventions for register names,
2850 we use the name of a table set up in mips.c, which is overwritten
2851 if -mrnames is used. */
2852
2853 #define REGISTER_NAMES \
2854 { \
2855 &mips_reg_names[ 0][0], \
2856 &mips_reg_names[ 1][0], \
2857 &mips_reg_names[ 2][0], \
2858 &mips_reg_names[ 3][0], \
2859 &mips_reg_names[ 4][0], \
2860 &mips_reg_names[ 5][0], \
2861 &mips_reg_names[ 6][0], \
2862 &mips_reg_names[ 7][0], \
2863 &mips_reg_names[ 8][0], \
2864 &mips_reg_names[ 9][0], \
2865 &mips_reg_names[10][0], \
2866 &mips_reg_names[11][0], \
2867 &mips_reg_names[12][0], \
2868 &mips_reg_names[13][0], \
2869 &mips_reg_names[14][0], \
2870 &mips_reg_names[15][0], \
2871 &mips_reg_names[16][0], \
2872 &mips_reg_names[17][0], \
2873 &mips_reg_names[18][0], \
2874 &mips_reg_names[19][0], \
2875 &mips_reg_names[20][0], \
2876 &mips_reg_names[21][0], \
2877 &mips_reg_names[22][0], \
2878 &mips_reg_names[23][0], \
2879 &mips_reg_names[24][0], \
2880 &mips_reg_names[25][0], \
2881 &mips_reg_names[26][0], \
2882 &mips_reg_names[27][0], \
2883 &mips_reg_names[28][0], \
2884 &mips_reg_names[29][0], \
2885 &mips_reg_names[30][0], \
2886 &mips_reg_names[31][0], \
2887 &mips_reg_names[32][0], \
2888 &mips_reg_names[33][0], \
2889 &mips_reg_names[34][0], \
2890 &mips_reg_names[35][0], \
2891 &mips_reg_names[36][0], \
2892 &mips_reg_names[37][0], \
2893 &mips_reg_names[38][0], \
2894 &mips_reg_names[39][0], \
2895 &mips_reg_names[40][0], \
2896 &mips_reg_names[41][0], \
2897 &mips_reg_names[42][0], \
2898 &mips_reg_names[43][0], \
2899 &mips_reg_names[44][0], \
2900 &mips_reg_names[45][0], \
2901 &mips_reg_names[46][0], \
2902 &mips_reg_names[47][0], \
2903 &mips_reg_names[48][0], \
2904 &mips_reg_names[49][0], \
2905 &mips_reg_names[50][0], \
2906 &mips_reg_names[51][0], \
2907 &mips_reg_names[52][0], \
2908 &mips_reg_names[53][0], \
2909 &mips_reg_names[54][0], \
2910 &mips_reg_names[55][0], \
2911 &mips_reg_names[56][0], \
2912 &mips_reg_names[57][0], \
2913 &mips_reg_names[58][0], \
2914 &mips_reg_names[59][0], \
2915 &mips_reg_names[60][0], \
2916 &mips_reg_names[61][0], \
2917 &mips_reg_names[62][0], \
2918 &mips_reg_names[63][0], \
2919 &mips_reg_names[64][0], \
2920 &mips_reg_names[65][0], \
2921 &mips_reg_names[66][0], \
2922 &mips_reg_names[67][0], \
2923 &mips_reg_names[68][0], \
2924 &mips_reg_names[69][0], \
2925 &mips_reg_names[70][0], \
2926 &mips_reg_names[71][0], \
2927 &mips_reg_names[72][0], \
2928 &mips_reg_names[73][0], \
2929 &mips_reg_names[74][0], \
2930 &mips_reg_names[75][0], \
2931 &mips_reg_names[76][0], \
2932 &mips_reg_names[77][0], \
2933 &mips_reg_names[78][0], \
2934 &mips_reg_names[79][0], \
2935 &mips_reg_names[80][0], \
2936 &mips_reg_names[81][0], \
2937 &mips_reg_names[82][0], \
2938 &mips_reg_names[83][0], \
2939 &mips_reg_names[84][0], \
2940 &mips_reg_names[85][0], \
2941 &mips_reg_names[86][0], \
2942 &mips_reg_names[87][0], \
2943 &mips_reg_names[88][0], \
2944 &mips_reg_names[89][0], \
2945 &mips_reg_names[90][0], \
2946 &mips_reg_names[91][0], \
2947 &mips_reg_names[92][0], \
2948 &mips_reg_names[93][0], \
2949 &mips_reg_names[94][0], \
2950 &mips_reg_names[95][0], \
2951 &mips_reg_names[96][0], \
2952 &mips_reg_names[97][0], \
2953 &mips_reg_names[98][0], \
2954 &mips_reg_names[99][0], \
2955 &mips_reg_names[100][0], \
2956 &mips_reg_names[101][0], \
2957 &mips_reg_names[102][0], \
2958 &mips_reg_names[103][0], \
2959 &mips_reg_names[104][0], \
2960 &mips_reg_names[105][0], \
2961 &mips_reg_names[106][0], \
2962 &mips_reg_names[107][0], \
2963 &mips_reg_names[108][0], \
2964 &mips_reg_names[109][0], \
2965 &mips_reg_names[110][0], \
2966 &mips_reg_names[111][0], \
2967 &mips_reg_names[112][0], \
2968 &mips_reg_names[113][0], \
2969 &mips_reg_names[114][0], \
2970 &mips_reg_names[115][0], \
2971 &mips_reg_names[116][0], \
2972 &mips_reg_names[117][0], \
2973 &mips_reg_names[118][0], \
2974 &mips_reg_names[119][0], \
2975 &mips_reg_names[120][0], \
2976 &mips_reg_names[121][0], \
2977 &mips_reg_names[122][0], \
2978 &mips_reg_names[123][0], \
2979 &mips_reg_names[124][0], \
2980 &mips_reg_names[125][0], \
2981 &mips_reg_names[126][0], \
2982 &mips_reg_names[127][0], \
2983 &mips_reg_names[128][0], \
2984 &mips_reg_names[129][0], \
2985 &mips_reg_names[130][0], \
2986 &mips_reg_names[131][0], \
2987 &mips_reg_names[132][0], \
2988 &mips_reg_names[133][0], \
2989 &mips_reg_names[134][0], \
2990 &mips_reg_names[135][0], \
2991 &mips_reg_names[136][0], \
2992 &mips_reg_names[137][0], \
2993 &mips_reg_names[138][0], \
2994 &mips_reg_names[139][0], \
2995 &mips_reg_names[140][0], \
2996 &mips_reg_names[141][0], \
2997 &mips_reg_names[142][0], \
2998 &mips_reg_names[143][0], \
2999 &mips_reg_names[144][0], \
3000 &mips_reg_names[145][0], \
3001 &mips_reg_names[146][0], \
3002 &mips_reg_names[147][0], \
3003 &mips_reg_names[148][0], \
3004 &mips_reg_names[149][0], \
3005 &mips_reg_names[150][0], \
3006 &mips_reg_names[151][0], \
3007 &mips_reg_names[152][0], \
3008 &mips_reg_names[153][0], \
3009 &mips_reg_names[154][0], \
3010 &mips_reg_names[155][0], \
3011 &mips_reg_names[156][0], \
3012 &mips_reg_names[157][0], \
3013 &mips_reg_names[158][0], \
3014 &mips_reg_names[159][0], \
3015 &mips_reg_names[160][0], \
3016 &mips_reg_names[161][0], \
3017 &mips_reg_names[162][0], \
3018 &mips_reg_names[163][0], \
3019 &mips_reg_names[164][0], \
3020 &mips_reg_names[165][0], \
3021 &mips_reg_names[166][0], \
3022 &mips_reg_names[167][0], \
3023 &mips_reg_names[168][0], \
3024 &mips_reg_names[169][0], \
3025 &mips_reg_names[170][0], \
3026 &mips_reg_names[171][0], \
3027 &mips_reg_names[172][0], \
3028 &mips_reg_names[173][0], \
3029 &mips_reg_names[174][0], \
3030 &mips_reg_names[175][0] \
3031 }
3032
3033 /* If defined, a C initializer for an array of structures
3034 containing a name and a register number. This macro defines
3035 additional names for hard registers, thus allowing the `asm'
3036 option in declarations to refer to registers using alternate
3037 names.
3038
3039 We define both names for the integer registers here. */
3040
3041 #define ADDITIONAL_REGISTER_NAMES \
3042 { \
3043 { "$0", 0 + GP_REG_FIRST }, \
3044 { "$1", 1 + GP_REG_FIRST }, \
3045 { "$2", 2 + GP_REG_FIRST }, \
3046 { "$3", 3 + GP_REG_FIRST }, \
3047 { "$4", 4 + GP_REG_FIRST }, \
3048 { "$5", 5 + GP_REG_FIRST }, \
3049 { "$6", 6 + GP_REG_FIRST }, \
3050 { "$7", 7 + GP_REG_FIRST }, \
3051 { "$8", 8 + GP_REG_FIRST }, \
3052 { "$9", 9 + GP_REG_FIRST }, \
3053 { "$10", 10 + GP_REG_FIRST }, \
3054 { "$11", 11 + GP_REG_FIRST }, \
3055 { "$12", 12 + GP_REG_FIRST }, \
3056 { "$13", 13 + GP_REG_FIRST }, \
3057 { "$14", 14 + GP_REG_FIRST }, \
3058 { "$15", 15 + GP_REG_FIRST }, \
3059 { "$16", 16 + GP_REG_FIRST }, \
3060 { "$17", 17 + GP_REG_FIRST }, \
3061 { "$18", 18 + GP_REG_FIRST }, \
3062 { "$19", 19 + GP_REG_FIRST }, \
3063 { "$20", 20 + GP_REG_FIRST }, \
3064 { "$21", 21 + GP_REG_FIRST }, \
3065 { "$22", 22 + GP_REG_FIRST }, \
3066 { "$23", 23 + GP_REG_FIRST }, \
3067 { "$24", 24 + GP_REG_FIRST }, \
3068 { "$25", 25 + GP_REG_FIRST }, \
3069 { "$26", 26 + GP_REG_FIRST }, \
3070 { "$27", 27 + GP_REG_FIRST }, \
3071 { "$28", 28 + GP_REG_FIRST }, \
3072 { "$29", 29 + GP_REG_FIRST }, \
3073 { "$30", 30 + GP_REG_FIRST }, \
3074 { "$31", 31 + GP_REG_FIRST }, \
3075 { "$sp", 29 + GP_REG_FIRST }, \
3076 { "$fp", 30 + GP_REG_FIRST }, \
3077 { "at", 1 + GP_REG_FIRST }, \
3078 { "v0", 2 + GP_REG_FIRST }, \
3079 { "v1", 3 + GP_REG_FIRST }, \
3080 { "a0", 4 + GP_REG_FIRST }, \
3081 { "a1", 5 + GP_REG_FIRST }, \
3082 { "a2", 6 + GP_REG_FIRST }, \
3083 { "a3", 7 + GP_REG_FIRST }, \
3084 { "t0", 8 + GP_REG_FIRST }, \
3085 { "t1", 9 + GP_REG_FIRST }, \
3086 { "t2", 10 + GP_REG_FIRST }, \
3087 { "t3", 11 + GP_REG_FIRST }, \
3088 { "t4", 12 + GP_REG_FIRST }, \
3089 { "t5", 13 + GP_REG_FIRST }, \
3090 { "t6", 14 + GP_REG_FIRST }, \
3091 { "t7", 15 + GP_REG_FIRST }, \
3092 { "s0", 16 + GP_REG_FIRST }, \
3093 { "s1", 17 + GP_REG_FIRST }, \
3094 { "s2", 18 + GP_REG_FIRST }, \
3095 { "s3", 19 + GP_REG_FIRST }, \
3096 { "s4", 20 + GP_REG_FIRST }, \
3097 { "s5", 21 + GP_REG_FIRST }, \
3098 { "s6", 22 + GP_REG_FIRST }, \
3099 { "s7", 23 + GP_REG_FIRST }, \
3100 { "t8", 24 + GP_REG_FIRST }, \
3101 { "t9", 25 + GP_REG_FIRST }, \
3102 { "k0", 26 + GP_REG_FIRST }, \
3103 { "k1", 27 + GP_REG_FIRST }, \
3104 { "gp", 28 + GP_REG_FIRST }, \
3105 { "sp", 29 + GP_REG_FIRST }, \
3106 { "fp", 30 + GP_REG_FIRST }, \
3107 { "ra", 31 + GP_REG_FIRST }, \
3108 { "$sp", 29 + GP_REG_FIRST }, \
3109 { "$fp", 30 + GP_REG_FIRST } \
3110 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3111 }
3112
3113 /* This is meant to be redefined in the host dependent files. It is a
3114 set of alternative names and regnums for mips coprocessors. */
3115
3116 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3117
3118 /* A C compound statement to output to stdio stream STREAM the
3119 assembler syntax for an instruction operand X. X is an RTL
3120 expression.
3121
3122 CODE is a value that can be used to specify one of several ways
3123 of printing the operand. It is used when identical operands
3124 must be printed differently depending on the context. CODE
3125 comes from the `%' specification that was used to request
3126 printing of the operand. If the specification was just `%DIGIT'
3127 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3128 is the ASCII code for LTR.
3129
3130 If X is a register, this macro should print the register's name.
3131 The names can be found in an array `reg_names' whose type is
3132 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3133
3134 When the machine description has a specification `%PUNCT' (a `%'
3135 followed by a punctuation character), this macro is called with
3136 a null pointer for X and the punctuation character for CODE.
3137
3138 See mips.c for the MIPS specific codes. */
3139
3140 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3141
3142 /* A C expression which evaluates to true if CODE is a valid
3143 punctuation character for use in the `PRINT_OPERAND' macro. If
3144 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3145 punctuation characters (except for the standard one, `%') are
3146 used in this way. */
3147
3148 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3149
3150 /* A C compound statement to output to stdio stream STREAM the
3151 assembler syntax for an instruction operand that is a memory
3152 reference whose address is ADDR. ADDR is an RTL expression. */
3153
3154 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3155
3156
3157 /* A C statement, to be executed after all slot-filler instructions
3158 have been output. If necessary, call `dbr_sequence_length' to
3159 determine the number of slots filled in a sequence (zero if not
3160 currently outputting a sequence), to decide how many no-ops to
3161 output, or whatever.
3162
3163 Don't define this macro if it has nothing to do, but it is
3164 helpful in reading assembly output if the extent of the delay
3165 sequence is made explicit (e.g. with white space).
3166
3167 Note that output routines for instructions with delay slots must
3168 be prepared to deal with not being output as part of a sequence
3169 (i.e. when the scheduling pass is not run, or when no slot
3170 fillers could be found.) The variable `final_sequence' is null
3171 when not processing a sequence, otherwise it contains the
3172 `sequence' rtx being output. */
3173
3174 #define DBR_OUTPUT_SEQEND(STREAM) \
3175 do \
3176 { \
3177 if (set_nomacro > 0 && --set_nomacro == 0) \
3178 fputs ("\t.set\tmacro\n", STREAM); \
3179 \
3180 if (set_noreorder > 0 && --set_noreorder == 0) \
3181 fputs ("\t.set\treorder\n", STREAM); \
3182 \
3183 fputs ("\n", STREAM); \
3184 } \
3185 while (0)
3186
3187
3188 /* How to tell the debugger about changes of source files. */
3189
3190 #ifndef SET_FILE_NUMBER
3191 #define SET_FILE_NUMBER() ++num_source_filenames
3192 #endif
3193
3194 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3195 mips_output_filename (STREAM, NAME)
3196
3197 /* This is defined so that it can be overridden in iris6.h. */
3198 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3199 do \
3200 { \
3201 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3202 output_quoted_string (STREAM, NAME); \
3203 fputs ("\n", STREAM); \
3204 } \
3205 while (0)
3206
3207 /* This is how to output a note the debugger telling it the line number
3208 to which the following sequence of instructions corresponds.
3209 Silicon graphics puts a label after each .loc. */
3210
3211 #ifndef LABEL_AFTER_LOC
3212 #define LABEL_AFTER_LOC(STREAM)
3213 #endif
3214
3215 #ifndef ASM_OUTPUT_SOURCE_LINE
3216 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3217 mips_output_lineno (STREAM, LINE)
3218 #endif
3219
3220 /* The MIPS implementation uses some labels for its own purpose. The
3221 following lists what labels are created, and are all formed by the
3222 pattern $L[a-z].*. The machine independent portion of GCC creates
3223 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3224
3225 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3226 $Lb[0-9]+ Begin blocks for MIPS debug support
3227 $Lc[0-9]+ Label for use in s<xx> operation.
3228 $Le[0-9]+ End blocks for MIPS debug support */
3229
3230 #undef ASM_DECLARE_OBJECT_NAME
3231 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3232 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3233
3234 /* Globalizing directive for a label. */
3235 #define GLOBAL_ASM_OP "\t.globl\t"
3236
3237 /* This says how to define a global common symbol. */
3238
3239 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3240 do { \
3241 /* If the target wants uninitialized const declarations in \
3242 .rdata then don't put them in .comm */ \
3243 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3244 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3245 && (DECL_INITIAL (DECL) == 0 \
3246 || DECL_INITIAL (DECL) == error_mark_node)) \
3247 { \
3248 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3249 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3250 \
3251 readonly_data_section (); \
3252 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3253 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3254 (SIZE)); \
3255 } \
3256 else \
3257 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3258 (SIZE)); \
3259 } while (0)
3260
3261
3262 /* This says how to define a local common symbol (ie, not visible to
3263 linker). */
3264
3265 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3266 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3267
3268
3269 /* This says how to output an external. It would be possible not to
3270 output anything and let undefined symbol become external. However
3271 the assembler uses length information on externals to allocate in
3272 data/sdata bss/sbss, thereby saving exec time. */
3273
3274 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3275 mips_output_external(STREAM,DECL,NAME)
3276
3277 /* This is how to declare a function name. The actual work of
3278 emitting the label is moved to function_prologue, so that we can
3279 get the line number correctly emitted before the .ent directive,
3280 and after any .file directives. Define as empty so that the function
3281 is not declared before the .ent directive elsewhere. */
3282
3283 #undef ASM_DECLARE_FUNCTION_NAME
3284 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3285
3286 #ifndef FUNCTION_NAME_ALREADY_DECLARED
3287 #define FUNCTION_NAME_ALREADY_DECLARED 0
3288 #endif
3289
3290 /* This is how to store into the string LABEL
3291 the symbol_ref name of an internal numbered label where
3292 PREFIX is the class of label and NUM is the number within the class.
3293 This is suitable for output with `assemble_name'. */
3294
3295 #undef ASM_GENERATE_INTERNAL_LABEL
3296 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3297 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3298
3299 /* This is how to output an element of a case-vector that is absolute. */
3300
3301 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3302 fprintf (STREAM, "\t%s\t%sL%d\n", \
3303 ptr_mode == DImode ? ".dword" : ".word", \
3304 LOCAL_LABEL_PREFIX, \
3305 VALUE)
3306
3307 /* This is how to output an element of a case-vector that is relative.
3308 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3309 TARGET_EMBEDDED_PIC). */
3310
3311 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3312 do { \
3313 if (TARGET_MIPS16) \
3314 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3315 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3316 else if (TARGET_EMBEDDED_PIC) \
3317 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3318 ptr_mode == DImode ? ".dword" : ".word", \
3319 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3320 else if (TARGET_GPWORD) \
3321 fprintf (STREAM, "\t%s\t%sL%d\n", \
3322 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3323 LOCAL_LABEL_PREFIX, VALUE); \
3324 else \
3325 fprintf (STREAM, "\t%s\t%sL%d\n", \
3326 ptr_mode == DImode ? ".dword" : ".word", \
3327 LOCAL_LABEL_PREFIX, VALUE); \
3328 } while (0)
3329
3330 /* When generating embedded PIC or mips16 code we want to put the jump
3331 table in the .text section. In all other cases, we want to put the
3332 jump table in the .rdata section. Unfortunately, we can't use
3333 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3334 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3335 section if appropriate. */
3336 #undef ASM_OUTPUT_CASE_LABEL
3337 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3338 do { \
3339 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3340 function_section (current_function_decl); \
3341 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3342 } while (0)
3343
3344 /* This is how to output an assembler line
3345 that says to advance the location counter
3346 to a multiple of 2**LOG bytes. */
3347
3348 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3349 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3350
3351 /* This is how to output an assembler line to advance the location
3352 counter by SIZE bytes. */
3353
3354 #undef ASM_OUTPUT_SKIP
3355 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3356 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3357
3358 /* This is how to output a string. */
3359 #undef ASM_OUTPUT_ASCII
3360 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3361 mips_output_ascii (STREAM, STRING, LEN)
3362
3363 /* Output #ident as a in the read-only data section. */
3364 #undef ASM_OUTPUT_IDENT
3365 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3366 { \
3367 const char *p = STRING; \
3368 int size = strlen (p) + 1; \
3369 readonly_data_section (); \
3370 assemble_string (p, size); \
3371 }
3372 \f
3373 /* Default to -G 8 */
3374 #ifndef MIPS_DEFAULT_GVALUE
3375 #define MIPS_DEFAULT_GVALUE 8
3376 #endif
3377
3378 /* Define the strings to put out for each section in the object file. */
3379 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3380 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3381 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3382
3383 #undef READONLY_DATA_SECTION_ASM_OP
3384 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3385
3386 /* Given a decl node or constant node, choose the section to output it in
3387 and select that section. */
3388
3389 #undef TARGET_ASM_SELECT_SECTION
3390 #define TARGET_ASM_SELECT_SECTION mips_select_section
3391 \f
3392 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3393 do \
3394 { \
3395 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3396 TARGET_64BIT ? "dsubu" : "subu", \
3397 reg_names[STACK_POINTER_REGNUM], \
3398 reg_names[STACK_POINTER_REGNUM], \
3399 TARGET_64BIT ? "sd" : "sw", \
3400 reg_names[REGNO], \
3401 reg_names[STACK_POINTER_REGNUM]); \
3402 } \
3403 while (0)
3404
3405 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3406 do \
3407 { \
3408 if (! set_noreorder) \
3409 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3410 \
3411 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3412 TARGET_64BIT ? "ld" : "lw", \
3413 reg_names[REGNO], \
3414 reg_names[STACK_POINTER_REGNUM], \
3415 TARGET_64BIT ? "daddu" : "addu", \
3416 reg_names[STACK_POINTER_REGNUM], \
3417 reg_names[STACK_POINTER_REGNUM]); \
3418 \
3419 if (! set_noreorder) \
3420 fprintf (STREAM, "\t.set\treorder\n"); \
3421 } \
3422 while (0)
3423
3424 /* How to start an assembler comment.
3425 The leading space is important (the mips native assembler requires it). */
3426 #ifndef ASM_COMMENT_START
3427 #define ASM_COMMENT_START " #"
3428 #endif
3429 \f
3430 /* Default definitions for size_t and ptrdiff_t. We must override the
3431 definitions from ../svr4.h on mips-*-linux-gnu. */
3432
3433 #undef SIZE_TYPE
3434 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3435
3436 #undef PTRDIFF_TYPE
3437 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3438
3439 /* See mips_expand_prologue's use of loadgp for when this should be
3440 true. */
3441
3442 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
3443 && mips_abi != ABI_32 \
3444 && mips_abi != ABI_O64)
3445 \f
3446
3447 #define DFMODE_NAN \
3448 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
3449 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
3450 #define SFMODE_NAN \
3451 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
3452 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
3453
3454 /* Generate calls to memcpy, etc., not bcopy, etc. */
3455 #define TARGET_MEM_FUNCTIONS
3456
3457 #ifndef __mips16
3458 /* Since the bits of the _init and _fini function is spread across
3459 many object files, each potentially with its own GP, we must assume
3460 we need to load our GP. We don't preserve $gp or $ra, since each
3461 init/fini chunk is supposed to initialize $gp, and crti/crtn
3462 already take care of preserving $ra and, when appropriate, $gp. */
3463 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3464 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3465 asm (SECTION_OP "\n\
3466 .set noreorder\n\
3467 bal 1f\n\
3468 nop\n\
3469 1: .cpload $31\n\
3470 .set reorder\n\
3471 jal " USER_LABEL_PREFIX #FUNC "\n\
3472 " TEXT_SECTION_ASM_OP);
3473 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3474 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3475 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3476 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3477 asm (SECTION_OP "\n\
3478 .set noreorder\n\
3479 bal 1f\n\
3480 nop\n\
3481 1: .set reorder\n\
3482 .cpsetup $31, $2, 1b\n\
3483 jal " USER_LABEL_PREFIX #FUNC "\n\
3484 " TEXT_SECTION_ASM_OP);
3485 #endif
3486 #endif
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