| blob | f53ee8d9817bc080d99bcfd242208a276f31bae4 |
1 /* Definitions of target machine for GNU compiler,
2 for Motorola M*CORE Processor.
3 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 #ifndef GCC_MCORE_H
24 #define GCC_MCORE_H
26 /* RBE: need to move these elsewhere. */
27 #undef LIKE_PPC_ABI
28 #define MCORE_STRUCT_ARGS
29 /* RBE: end of "move elsewhere". */
31 /* Run-time Target Specification. */
32 #define TARGET_MCORE
34 /* Get tree.c to declare a target-specific specialization of
35 merge_decl_attributes. */
36 #define TARGET_DLLIMPORT_DECL_ATTRIBUTES
38 /* Support the __declspec keyword by turning them into attributes.
39 We currently only support: dllexport and dllimport.
40 Note that the current way we do this may result in a collision with
41 predefined attributes later on. This can be solved by using one attribute,
42 say __declspec__, and passing args to it. The problem with that approach
43 is that args are not accumulated: each new appearance would clobber any
44 existing args. */
45 #define TARGET_CPU_CPP_BUILTINS() \
46 do \
47 { \
51 if (TARGET_LITTLE_END) \
53 else \
55 if (TARGET_M340) \
57 else \
59 } \
60 while (0)
62 /* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC
63 %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}. */
64 #undef CPP_SPEC
67 /* We don't have a -lg library, so don't put it in the list. */
68 #undef LIB_SPEC
71 #undef ASM_SPEC
74 #undef LINK_SPEC
77 /* Can only count on 16 bits of availability; change to long would affect
78 many architecture specific files (other architectures...). */
92 #define TARGET_DEFAULT \
93 (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT)
95 #ifndef MULTILIB_DEFAULTS
97 #endif
99 #define TARGET_HARDLIT (target_flags & HARDLIT_BIT)
100 /* The ability to have 4 byte alignment is being suppressed for now.
101 If this ability is reenabled, you must enable the definition below
102 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */
103 #if 0
104 #define TARGET_8ALIGN (target_flags & ALIGN8_BIT)
105 #else
106 #define TARGET_8ALIGN 1
107 #endif
108 #define TARGET_DIV (target_flags & DIV_BIT)
109 #define TARGET_RELAX_IMM (target_flags & RELAX_IMM_BIT)
110 #define TARGET_W_FIELD (target_flags & W_FIELD_BIT)
111 #define TARGET_OVERALIGN_FUNC (target_flags & OVERALIGN_FUNC_BIT)
112 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
113 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
114 #define TARGET_SLOW_BYTES (target_flags & SLOW_BYTES_BIT)
115 #define TARGET_LITTLE_END (target_flags & LITTLE_END_BIT)
116 #define TARGET_M340 (target_flags & M340_BIT)
119 #define TARGET_SWITCHES \
163 }
167 /* Target specific options (as opposed to the switches above). */
170 #define TARGET_OPTIONS \
171 { \
174 }
176 /* The MCore ABI says that bitfields are unsigned by default. */
179 /* What options are we going to default to specific settings when
180 -O* happens; the user can subsequently override these settings.
182 Omitting the frame pointer is a very good idea on the MCore.
183 Scheduling isn't worth anything on the current MCore implementation. */
184 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
185 { \
186 if (LEVEL) \
187 { \
188 flag_no_function_cse = 1; \
189 flag_omit_frame_pointer = 1; \
190 \
191 if (LEVEL >= 2) \
192 { \
193 flag_caller_saves = 0; \
194 flag_schedule_insns = 0; \
195 flag_schedule_insns_after_reload = 0; \
196 } \
197 } \
198 if (SIZE) \
199 { \
200 target_flags &= ~ HARDLIT_BIT; \
201 } \
202 }
204 /* What options are we going to force to specific settings,
205 regardless of what the user thought he wanted.
206 We also use this for some post-processing of options. */
207 #define OVERRIDE_OPTIONS mcore_override_options ()
209 /* Target machine storage Layout. */
211 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
212 if (GET_MODE_CLASS (MODE) == MODE_INT \
213 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
214 { \
215 (MODE) = SImode; \
216 (UNSIGNEDP) = 1; \
217 }
219 #define PROMOTE_FUNCTION_ARGS
221 #define PROMOTE_FUNCTION_RETURN
223 /* Define this if most significant bit is lowest numbered
224 in instructions that operate on numbered bit-fields. */
225 #define BITS_BIG_ENDIAN 0
227 /* Define this if most significant byte of a word is the lowest numbered. */
228 #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END)
230 /* Define this if most significant word of a multiword number is the lowest
231 numbered. */
232 #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END)
234 #define LIBGCC2_WORDS_BIG_ENDIAN 1
235 #ifdef __MCORELE__
236 #undef LIBGCC2_WORDS_BIG_ENDIAN
237 #define LIBGCC2_WORDS_BIG_ENDIAN 0
238 #endif
240 #define MAX_BITS_PER_WORD 32
242 /* Width of a word, in units (bytes). */
243 #define UNITS_PER_WORD 4
245 /* A C expression for the size in bits of the type `long long' on the
246 target machine. If you don't define this, the default is two
247 words. */
248 #define LONG_LONG_TYPE_SIZE 64
250 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
251 #define PARM_BOUNDARY 32
253 /* Doubles must be aligned to an 8 byte boundary. */
254 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
255 ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \
256 ? BIGGEST_ALIGNMENT : PARM_BOUNDARY)
258 /* Boundary (in *bits*) on which stack pointer should be aligned. */
259 #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32)
261 /* Largest increment in UNITS we allow the stack to grow in a single operation. */
263 #define STACK_UNITS_MAXSTEP 4096
265 /* Allocation boundary (in *bits*) for the code of a function. */
266 #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16)
268 /* Alignment of field after `int : 0' in a structure. */
269 #define EMPTY_FIELD_BOUNDARY 32
271 /* No data type wants to be aligned rounder than this. */
272 #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32)
274 /* The best alignment to use in cases where we have a choice. */
275 #define FASTEST_ALIGNMENT 32
277 /* Every structures size must be a multiple of 8 bits. */
278 #define STRUCTURE_SIZE_BOUNDARY 8
280 /* Look at the fundamental type that is used for a bit-field and use
281 that to impose alignment on the enclosing structure.
282 struct s {int a:8}; should have same alignment as "int", not "char". */
283 #define PCC_BITFIELD_TYPE_MATTERS 1
285 /* Largest integer machine mode for structures. If undefined, the default
286 is GET_MODE_SIZE(DImode). */
287 #define MAX_FIXED_MODE_SIZE 32
289 /* Make strings word-aligned so strcpy from constants will be faster. */
290 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
291 ((TREE_CODE (EXP) == STRING_CST \
292 && (ALIGN) < FASTEST_ALIGNMENT) \
293 ? FASTEST_ALIGNMENT : (ALIGN))
295 /* Make arrays of chars word-aligned for the same reasons. */
296 #define DATA_ALIGNMENT(TYPE, ALIGN) \
297 (TREE_CODE (TYPE) == ARRAY_TYPE \
298 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
299 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
301 /* Set this nonzero if move instructions will actually fail to work
302 when given unaligned data. */
303 #define STRICT_ALIGNMENT 1
305 /* Standard register usage. */
307 /* Register allocation for our first guess
309 r0 stack pointer
310 r1 scratch, target reg for xtrb?
311 r2-r7 arguments.
312 r8-r14 call saved
313 r15 link register
314 ap arg pointer (doesn't really exist, always eliminated)
315 c c bit
316 fp frame pointer (doesn't really exist, always eliminated)
317 x19 two control registers. */
319 /* Number of actual hardware registers.
320 The hardware registers are assigned numbers for the compiler
321 from 0 to just below FIRST_PSEUDO_REGISTER.
322 All registers that the compiler knows about must be given numbers,
323 even those that are not normally considered general registers.
325 MCore has 16 integer registers and 2 control registers + the arg
326 pointer. */
328 #define FIRST_PSEUDO_REGISTER 20
333 /* RBE: mcore.md depends on CC_REG being set to 17. */
337 /* Specify the registers used for certain standard purposes.
338 The values of these macros are register numbers. */
345 /* The assembler's names for the registers. RFP need not always be used as
346 the Real framepointer; it can also be used as a normal general register.
347 Note that the name `fp' is horribly misleading since `fp' is in fact only
348 the argument-and-return-context pointer. */
349 #define REGISTER_NAMES \
350 { \
354 }
356 /* 1 for registers that have pervasive standard uses
357 and are not available for the register allocator. */
358 #define FIXED_REGISTERS \
360 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
362 /* 1 for registers not available across function calls.
363 These must include the FIXED_REGISTERS and also any
364 registers that can be used without being saved.
365 The latter must include the registers where values are returned
366 and the register where structure-value addresses are passed.
367 Aside from that, you can include as many other registers as you like. */
369 /* RBE: r15 {link register} not available across calls,
370 But we don't mark it that way here... */
371 #define CALL_USED_REGISTERS \
373 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
375 /* The order in which register should be allocated. */
376 #define REG_ALLOC_ORDER \
378 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19}
380 /* Return number of consecutive hard regs needed starting at reg REGNO
381 to hold something of mode MODE.
382 This is ordinarily the length in words of a value of mode MODE
383 but can be less for certain modes in special long registers.
385 On the MCore regs are UNITS_PER_WORD bits wide; */
386 #define HARD_REGNO_NREGS(REGNO, MODE) \
387 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
389 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
390 We may keep double values in even registers. */
391 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
392 ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))
394 /* Value is 1 if it is a good idea to tie two pseudo registers
395 when one has mode MODE1 and one has mode MODE2.
396 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
397 for any hard reg, then this must be 0 for correct output. */
398 #define MODES_TIEABLE_P(MODE1, MODE2) \
399 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
401 /* Value should be nonzero if functions must have frame pointers.
402 Zero means the frame pointer need not be set up (and parms may be accessed
403 via the stack pointer) in functions that seem suitable. */
404 #define FRAME_POINTER_REQUIRED 0
406 /* Definitions for register eliminations.
408 We have two registers that can be eliminated on the MCore. First, the
409 frame pointer register can often be eliminated in favor of the stack
410 pointer register. Secondly, the argument pointer register can always be
411 eliminated; it is replaced with either the stack or frame pointer. */
413 /* Base register for access to arguments of the function. */
414 #define ARG_POINTER_REGNUM 16
416 /* Register in which the static-chain is passed to a function. */
417 #define STATIC_CHAIN_REGNUM 1
419 /* This is an array of structures. Each structure initializes one pair
420 of eliminable registers. The "from" register number is given first,
421 followed by "to". Eliminations of the same "from" register are listed
422 in order of preference. */
423 #define ELIMINABLE_REGS \
424 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
425 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
426 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
428 /* Given FROM and TO register numbers, say whether this elimination
429 is allowed. */
430 #define CAN_ELIMINATE(FROM, TO) \
431 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
433 /* Define the offset between two registers, one to be eliminated, and the other
434 its replacement, at the start of a routine. */
435 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
436 OFFSET = mcore_initial_elimination_offset (FROM, TO)
438 /* Place that structure value return address is placed. */
439 #define STRUCT_VALUE 0
441 /* Define the classes of registers for register constraints in the
442 machine description. Also define ranges of constants.
444 One of the classes must always be named ALL_REGS and include all hard regs.
445 If there is more than one class, another class must be named NO_REGS
446 and contain no registers.
448 The name GENERAL_REGS must be the name of a class (or an alias for
449 another name such as ALL_REGS). This is the class of registers
450 that is allowed by "g" or "r" in a register constraint.
451 Also, registers outside this class are allocated only when
452 instructions express preferences for them.
454 The classes must be numbered in nondecreasing order; that is,
455 a larger-numbered class must never be contained completely
456 in a smaller-numbered class.
458 For any two classes, it is very desirable that there be another
459 class that represents their union. */
461 /* The MCore has only general registers. There are
462 also some special purpose registers: the T bit register, the
463 procedure Link and the Count Registers. */
464 enum reg_class
465 {
466 NO_REGS,
467 ONLYR1_REGS,
468 LRW_REGS,
469 GENERAL_REGS,
470 C_REGS,
471 ALL_REGS,
472 LIM_REG_CLASSES
473 };
475 #define N_REG_CLASSES (int) LIM_REG_CLASSES
477 /* Give names of register classes as strings for dump file. */
478 #define REG_CLASS_NAMES \
479 { \
486 }
488 /* Define which registers fit in which classes.
489 This is an initializer for a vector of HARD_REG_SET
490 of length N_REG_CLASSES. */
492 /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */
493 #define REG_CLASS_CONTENTS \
494 { \
501 }
503 /* The same information, inverted:
504 Return the class number of the smallest class containing
505 reg number REGNO. This could be a conditional expression
506 or could index an array. */
509 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
511 /* When defined, the compiler allows registers explicitly used in the
512 rtl to be used as spill registers but prevents the compiler from
513 extending the lifetime of these registers. */
514 #define SMALL_REGISTER_CLASSES 1
516 /* The class value for index registers, and the one for base regs. */
517 #define INDEX_REG_CLASS NO_REGS
518 #define BASE_REG_CLASS GENERAL_REGS
520 /* Get reg_class from a letter such as appears in the machine
521 description. */
524 #define REG_CLASS_FROM_LETTER(C) \
527 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
528 can be used to stand for particular ranges of immediate operands.
529 This macro defines what the ranges are.
530 C is the letter, and VALUE is a constant value.
531 Return 1 if VALUE is in the range specified by C.
532 I: loadable by movi (0..127)
533 J: arithmetic operand 1..32
534 K: shift operand 0..31
535 L: negative arithmetic operand -1..-32
536 M: powers of two, constants loadable by bgeni
537 N: powers of two minus 1, constants loadable by bmaski, including -1
538 O: allowed by cmov with two constants +/- 1 of each other
539 P: values we will generate 'inline' -- without an 'lrw'
541 Others defined for use after reload
542 Q: constant 1
543 R: a label
544 S: 0/1/2 cleared bits out of 32 [for bclri's]
545 T: 2 set bits out of 32 [for bseti's]
546 U: constant 0
547 xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri
548 xxxT: 2 cleared bits out of 32. for pairs of bclris. */
549 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f)
550 #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32)
551 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32)
552 #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31)
553 #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0)
554 #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0)
555 #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \
556 CONST_OK_FOR_M(VALUE) || \
557 CONST_OK_FOR_N(VALUE) || \
558 CONST_OK_FOR_M((int)(VALUE) - 1) || \
559 CONST_OK_FOR_N((int)(VALUE) + 1))
561 #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE))
563 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
572 : 0)
574 /* Similar, but for floating constants, and defining letters G and H.
575 Here VALUE is the CONST_DOUBLE rtx itself. */
576 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
578 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
579 : 0)
581 /* Letters in the range `Q' through `U' in a register constraint string
582 may be defined in a machine-dependent fashion to stand for arbitrary
583 operand types. */
584 #define EXTRA_CONSTRAINT(OP, C) \
586 && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
588 && mcore_num_zeros (INTVAL (OP)) <= 2) \
590 && mcore_num_ones (INTVAL (OP)) == 2) \
592 && INTVAL(OP) == 1) \
594 && INTVAL(OP) == 0) \
595 : 0)
597 /* Given an rtx X being reloaded into a reg required to be
598 in class CLASS, return the class of reg to actually use.
599 In general this is just CLASS; but on some machines
600 in some cases it is preferable to use a more restrictive class. */
601 #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS)
603 /* Return the register class of a scratch register needed to copy IN into
604 or out of a register in CLASS in MODE. If it can be done directly,
605 NO_REGS is returned. */
606 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
607 mcore_secondary_reload_class (CLASS, MODE, X)
609 /* Return the maximum number of consecutive registers
610 needed to represent mode MODE in a register of class CLASS.
612 On MCore this is the size of MODE in words. */
613 #define CLASS_MAX_NREGS(CLASS, MODE) \
614 (ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
616 /* Stack layout; function entry, exit and calling. */
618 /* Define the number of register that can hold parameters.
619 These two macros are used only in other macro definitions below. */
620 #define NPARM_REGS 6
621 #define FIRST_PARM_REG 2
622 #define FIRST_RET_REG 2
624 /* Define this if pushing a word on the stack
625 makes the stack pointer a smaller address. */
626 #define STACK_GROWS_DOWNWARD
628 /* Offset within stack frame to start allocating local variables at.
629 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
630 first local allocated. Otherwise, it is the offset to the BEGINNING
631 of the first local allocated. */
632 #define STARTING_FRAME_OFFSET 0
634 /* If defined, the maximum amount of space required for outgoing arguments
635 will be computed and placed into the variable
636 `current_function_outgoing_args_size'. No space will be pushed
637 onto the stack for each call; instead, the function prologue should
638 increase the stack frame size by this amount. */
639 #define ACCUMULATE_OUTGOING_ARGS 1
641 /* Offset of first parameter from the argument pointer register value. */
642 #define FIRST_PARM_OFFSET(FNDECL) 0
644 /* Value is the number of byte of arguments automatically
645 popped when returning from a subroutine call.
646 FUNTYPE is the data type of the function (as a tree),
647 or for a library call it is an identifier node for the subroutine name.
648 SIZE is the number of bytes of arguments passed on the stack.
650 On the MCore, the callee does not pop any of its arguments that were passed
651 on the stack. */
652 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
654 /* Define how to find the value returned by a function.
655 VALTYPE is the data type of the value (as a tree).
656 If the precise function being called is known, FUNC is its FUNCTION_DECL;
657 otherwise, FUNC is 0. */
658 #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC)
660 /* Don't default to pcc-struct-return, because gcc is the only compiler, and
661 we want to retain compatibility with older gcc versions. */
662 #define DEFAULT_PCC_STRUCT_RETURN 0
664 /* How many registers to use for struct return. */
665 #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 2 * UNITS_PER_WORD)
667 /* Define how to find the value returned by a library function
668 assuming the value has mode MODE. */
669 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG)
671 /* 1 if N is a possible register number for a function value.
672 On the MCore, only r4 can return results. */
673 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
675 #define MUST_PASS_IN_STACK(MODE,TYPE) \
676 mcore_must_pass_on_stack (MODE, TYPE)
678 /* 1 if N is a possible register number for function argument passing. */
679 #define FUNCTION_ARG_REGNO_P(REGNO) \
680 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
682 /* Define a data type for recording info about an argument list
683 during the scan of that argument list. This data type should
684 hold all necessary information about the function itself
685 and about the args processed so far, enough to enable macros
686 such as FUNCTION_ARG to determine where the next arg should go.
688 On MCore, this is a single integer, which is a number of words
689 of arguments scanned so far (including the invisible argument,
690 if any, which holds the structure-value-address).
691 Thus NARGREGS or more means all following args should go on the stack. */
692 #define CUMULATIVE_ARGS int
694 #define ROUND_ADVANCE(SIZE) \
695 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
697 /* Round a register number up to a proper boundary for an arg of mode
698 MODE.
700 We round to an even reg for things larger than a word. */
701 #define ROUND_REG(X, MODE) \
702 ((TARGET_8ALIGN \
703 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
704 ? ((X) + ((X) & 1)) : (X))
707 /* Initialize a variable CUM of type CUMULATIVE_ARGS
708 for a call to a function whose data type is FNTYPE.
709 For a library call, FNTYPE is 0.
711 On MCore, the offset always starts at 0: the first parm reg is always
712 the same reg. */
713 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
714 ((CUM) = 0)
716 /* Update the data in CUM to advance over an argument
717 of mode MODE and data type TYPE.
718 (TYPE is null for libcalls where that information may not be
719 available.) */
720 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
721 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
722 + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \
724 /* Define where to put the arguments to a function. */
725 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
726 mcore_function_arg (CUM, MODE, TYPE, NAMED)
728 /* A C expression that indicates when an argument must be passed by
729 reference. If nonzero for an argument, a copy of that argument is
730 made in memory and a pointer to the argument is passed instead of
731 the argument itself. The pointer is passed in whatever way is
732 appropriate for passing a pointer to that type. */
733 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
734 MUST_PASS_IN_STACK (MODE, TYPE)
736 /* For an arg passed partly in registers and partly in memory,
737 this is the number of registers used.
738 For args passed entirely in registers or entirely in memory, zero.
739 Any arg that starts in the first NPARM_REGS regs but won't entirely
740 fit in them needs partial registers on the MCore. */
741 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
742 mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
744 /* Perform any needed actions needed for a function that is receiving a
745 variable number of arguments. */
746 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
747 mcore_setup_incoming_varargs (ASF, MODE, TYPE, & PAS)
749 /* Call the function profiler with a given profile label. */
750 #define FUNCTION_PROFILER(STREAM,LABELNO) \
751 { \
755 }
757 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
758 the stack pointer does not matter. The value is tested only in
759 functions that have frame pointers.
760 No definition is equivalent to always zero. */
761 #define EXIT_IGNORE_STACK 0
763 /* Output assembler code for a block containing the constant parts
764 of a trampoline, leaving space for the variable parts.
766 On the MCore, the trampoline looks like:
767 lrw r1, function
768 lrw r13, area
769 jmp r13
770 or r0, r0
771 .literals */
772 #define TRAMPOLINE_TEMPLATE(FILE) \
773 { \
780 }
782 /* Length in units of the trampoline for entering a nested function. */
783 #define TRAMPOLINE_SIZE 12
785 /* Alignment required for a trampoline in bits. */
786 #define TRAMPOLINE_ALIGNMENT 32
788 /* Emit RTL insns to initialize the variable parts of a trampoline.
789 FNADDR is an RTX for the address of the function's pure code.
790 CXT is an RTX for the static chain value for the function. */
791 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
792 { \
793 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
794 (CXT)); \
795 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
796 (FNADDR)); \
797 }
799 /* Macros to check register numbers against specific register classes. */
801 /* These assume that REGNO is a hard or pseudo reg number.
802 They give nonzero only if REGNO is a hard reg of the suitable class
803 or a pseudo reg currently allocated to a suitable hard reg.
804 Since they use reg_renumber, they are safe only once reg_renumber
805 has been allocated, which happens in local-alloc.c. */
806 #define REGNO_OK_FOR_BASE_P(REGNO) \
807 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG)
809 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
811 /* Maximum number of registers that can appear in a valid memory
812 address. */
813 #define MAX_REGS_PER_ADDRESS 1
815 /* Recognize any constant value that is a valid address. */
816 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
818 /* Nonzero if the constant value X is a legitimate general operand.
819 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
821 On the MCore, allow anything but a double. */
822 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
824 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
825 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
826 and check its validity for a certain class.
827 We have two alternate definitions for each of them.
828 The usual definition accepts all pseudo regs; the other rejects
829 them unless they have been allocated suitable hard regs.
830 The symbol REG_OK_STRICT causes the latter definition to be used. */
831 #ifndef REG_OK_STRICT
833 /* Nonzero if X is a hard reg that can be used as a base reg
834 or if it is a pseudo reg. */
835 #define REG_OK_FOR_BASE_P(X) \
836 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
838 /* Nonzero if X is a hard reg that can be used as an index
839 or if it is a pseudo reg. */
840 #define REG_OK_FOR_INDEX_P(X) 0
842 #else
844 /* Nonzero if X is a hard reg that can be used as a base reg. */
845 #define REG_OK_FOR_BASE_P(X) \
846 REGNO_OK_FOR_BASE_P (REGNO (X))
848 /* Nonzero if X is a hard reg that can be used as an index. */
849 #define REG_OK_FOR_INDEX_P(X) 0
851 #endif
852 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
853 that is a valid memory address for an instruction.
854 The MODE argument is the machine mode for the MEM expression
855 that wants to use this address.
857 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
858 #define BASE_REGISTER_RTX_P(X) \
859 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
861 #define INDEX_REGISTER_RTX_P(X) \
862 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
865 /* Jump to LABEL if X is a valid address RTX. This must also take
866 REG_OK_STRICT into account when deciding about valid registers, but it uses
867 the above macros so we are in luck.
869 Allow REG
870 REG+disp
872 A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
873 and for DI is 0..56 because we use two SI loads, etc. */
874 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
875 do \
876 { \
877 if (GET_CODE (OP) == CONST_INT) \
878 { \
879 if (GET_MODE_SIZE (MODE) >= 4 \
880 && (((unsigned)INTVAL (OP)) % 4) == 0 \
881 && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \
882 goto LABEL; \
883 if (GET_MODE_SIZE (MODE) == 2 \
884 && (((unsigned)INTVAL (OP)) % 2) == 0 \
885 && ((unsigned)INTVAL (OP)) <= 30) \
886 goto LABEL; \
887 if (GET_MODE_SIZE (MODE) == 1 \
888 && ((unsigned)INTVAL (OP)) <= 15) \
889 goto LABEL; \
890 } \
891 } \
892 while (0)
894 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
895 { \
896 if (BASE_REGISTER_RTX_P (X)) \
897 goto LABEL; \
898 else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \
899 { \
900 rtx xop0 = XEXP (X,0); \
901 rtx xop1 = XEXP (X,1); \
902 if (BASE_REGISTER_RTX_P (xop0)) \
903 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
904 if (BASE_REGISTER_RTX_P (xop1)) \
905 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
906 } \
907 }
909 /* Go to LABEL if ADDR (a legitimate address expression)
910 has an effect that depends on the machine mode it is used for. */
911 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
912 { \
913 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
914 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
915 goto LABEL; \
916 }
918 /* Specify the machine mode that this machine uses
919 for the index in the tablejump instruction. */
920 #define CASE_VECTOR_MODE SImode
922 /* 'char' is signed by default. */
923 #define DEFAULT_SIGNED_CHAR 0
925 /* The type of size_t unsigned int. */
928 /* Don't cse the address of the function being compiled. */
929 #define NO_RECURSIVE_FUNCTION_CSE 1
931 /* Max number of bytes we can move from memory to memory
932 in one reasonably fast instruction. */
933 #define MOVE_MAX 4
935 /* Define if operations between registers always perform the operation
936 on the full register even if a narrower mode is specified. */
937 #define WORD_REGISTER_OPERATIONS
939 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
940 will either zero-extend or sign-extend. The value of this macro should
941 be the code that says which one of the two operations is implicitly
942 done, NIL if none. */
943 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
945 /* Nonzero if access to memory by bytes is slow and undesirable. */
946 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
948 /* Immediate shift counts are truncated by the output routines (or was it
949 the assembler?). Shift counts in a register are truncated by ARM. Note
950 that the native compiler puts too large (> 32) immediate shift counts
951 into a register and shifts by the register, letting the ARM decide what
952 to do instead of doing that itself. */
953 #define SHIFT_COUNT_TRUNCATED 1
955 /* All integers have the same format so truncation is easy. */
956 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
958 /* Define this if addresses of constant functions
959 shouldn't be put through pseudo regs where they can be cse'd.
960 Desirable on machines where ordinary constants are expensive
961 but a CALL with constant address is cheap. */
962 /* why is this defined??? -- dac */
963 #define NO_FUNCTION_CSE 1
965 /* Chars and shorts should be passed as ints. */
966 #define PROMOTE_PROTOTYPES 1
968 /* The machine modes of pointers and functions. */
969 #define Pmode SImode
970 #define FUNCTION_MODE Pmode
972 /* Compute extra cost of moving data between one register class
973 and another. All register moves are cheap. */
974 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
976 #define WORD_REGISTER_OPERATIONS
978 /* Implicit library calls should use memcpy, not bcopy, etc. */
979 #define TARGET_MEM_FUNCTIONS
981 /* Assembler output control. */
989 /* Switch to the text or data segment. */
993 #undef EXTRA_SECTIONS
994 #define EXTRA_SECTIONS SUBTARGET_EXTRA_SECTIONS
996 #undef EXTRA_SECTION_FUNCTIONS
997 #define EXTRA_SECTION_FUNCTIONS \
998 SUBTARGET_EXTRA_SECTION_FUNCTIONS \
999 SWITCH_SECTION_FUNCTION
1001 /* Switch to SECTION (an `enum in_section').
1003 ??? This facility should be provided by GCC proper.
1004 The problem is that we want to temporarily switch sections in
1005 ASM_DECLARE_OBJECT_NAME and then switch back to the original section
1006 afterwards. */
1007 #define SWITCH_SECTION_FUNCTION \
1008 static void switch_to_section (enum in_section, tree); \
1009 static void \
1010 switch_to_section (enum in_section section, tree decl) \
1011 { \
1012 switch (section) \
1013 { \
1014 case in_text: text_section (); break; \
1015 case in_data: data_section (); break; \
1016 case in_named: named_section (decl, NULL, 0); break; \
1017 SUBTARGET_SWITCH_SECTIONS \
1018 default: abort (); break; \
1019 } \
1020 }
1022 /* Switch into a generic section. */
1023 #undef TARGET_ASM_NAMED_SECTION
1024 #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section
1026 /* This is how to output an insn to push a register on the stack.
1027 It need not be very fast code. */
1028 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1030 reg_names[STACK_POINTER_REGNUM], \
1031 (STACK_BOUNDARY / BITS_PER_UNIT), \
1032 reg_names[REGNO], \
1033 reg_names[STACK_POINTER_REGNUM])
1035 /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */
1036 #define REG_PUSH_LENGTH 2
1038 /* This is how to output an insn to pop a register from the stack. */
1039 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1041 reg_names[REGNO], \
1042 reg_names[STACK_POINTER_REGNUM], \
1043 reg_names[STACK_POINTER_REGNUM], \
1044 (STACK_BOUNDARY / BITS_PER_UNIT))
1047 /* Output a reference to a label. */
1048 #undef ASM_OUTPUT_LABELREF
1049 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1051 (* targetm.strip_name_encoding) (NAME))
1053 /* This is how to output an assembler line
1054 that says to advance the location counter
1055 to a multiple of 2**LOG bytes. */
1056 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1057 if ((LOG) != 0) \
1060 #ifndef ASM_DECLARE_RESULT
1061 #define ASM_DECLARE_RESULT(FILE, RESULT)
1062 #endif
1064 #define MULTIPLE_SYMBOL_SPACES 1
1066 #define SUPPORTS_ONE_ONLY 1
1068 /* A pair of macros to output things for the callgraph data.
1069 VALUE means (to the tools that reads this info later):
1070 0 a call from src to dst
1071 1 the call is special (e.g. dst is "unknown" or "alloca")
1072 2 the call is special (e.g., the src is a table instead of routine)
1074 Frame sizes are augmented with timestamps to help later tools
1075 differentiate between static entities with same names in different
1076 files. */
1078 #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \
1079 do \
1080 { \
1081 if (mcore_current_compilation_timestamp == 0) \
1082 mcore_current_compilation_timestamp = time (0); \
1084 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \
1085 } \
1086 while (0)
1088 #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \
1089 do \
1090 { \
1092 (SRCNAME), (DSTNAME), (VALUE)); \
1093 } \
1094 while (0)
1096 /* Globalizing directive for a label. */
1099 /* The prefix to add to user-visible assembler symbols. */
1100 #undef USER_LABEL_PREFIX
1103 /* Make an internal label into a string. */
1104 #undef ASM_GENERATE_INTERNAL_LABEL
1105 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1108 /* Jump tables must be 32 bit aligned. */
1109 #undef ASM_OUTPUT_CASE_LABEL
1110 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1113 /* Output a relative address. Not needed since jump tables are absolute
1114 but we must define it anyway. */
1115 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1118 /* Output an element of a dispatch table. */
1119 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1122 /* Output various types of constants. */
1124 /* This is how to output an assembler line
1125 that says to advance the location counter by SIZE bytes. */
1126 #undef ASM_OUTPUT_SKIP
1127 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1130 /* This says how to output an assembler line
1131 to define a global common symbol, with alignment information. */
1132 /* XXX - for now we ignore the alignment. */
1133 #undef ASM_OUTPUT_ALIGNED_COMMON
1134 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1135 do \
1136 { \
1137 if (mcore_dllexport_name_p (NAME)) \
1138 MCORE_EXPORT_NAME (FILE, NAME) \
1139 if (! mcore_dllimport_name_p (NAME)) \
1140 { \
1142 assemble_name (FILE, NAME); \
1144 } \
1145 } \
1146 while (0)
1148 /* This says how to output an assembler line
1149 to define an external symbol. */
1150 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1151 do \
1152 { \
1154 assemble_name ((FILE), (NAME)); \
1156 } \
1157 while (0)
1159 #undef ASM_OUTPUT_EXTERNAL
1160 /* RBE: we undefined this and let gas do it's "undefined is imported"
1161 games. This is because when we use this, we get a marked
1162 reference through the call to assemble_name and this forces C++
1163 inlined member functions (or any inlined function) to be instantiated
1164 regardless of whether any call sites remain.
1165 This makes this aspect of the compiler non-ABI compliant. */
1167 /* Similar, but for libcall. FUN is an rtx. */
1168 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
1169 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
1170 do \
1171 { \
1173 assemble_name (FILE, XSTR (FUN, 0)); \
1175 } \
1176 while (0)
1179 /* This says how to output an assembler line
1180 to define a local common symbol... */
1181 #undef ASM_OUTPUT_LOCAL
1182 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1184 assemble_name (FILE, NAME), \
1187 /* ... and how to define a local common symbol whose alignment
1188 we wish to specify. ALIGN comes in as bits, we have to turn
1189 it into bytes. */
1190 #undef ASM_OUTPUT_ALIGNED_LOCAL
1191 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1192 do \
1193 { \
1195 assemble_name ((FILE), (NAME)); \
1197 } \
1198 while (0)
1200 /* Print operand X (an rtx) in assembler syntax to file FILE.
1201 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1202 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1203 #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE)
1205 /* Print a memory address as an operand to reference that memory location. */
1206 #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X)
1208 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1211 #define PREDICATE_CODES \