| blob | 11f219c82661924fefb15bffa4a2d6abc0562267 |
1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
29 ;;-
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881 registers can be used
49 ;;- 'r' either a data or an address register can be used.
51 ;;- Immediate Floating point operator constraints
52 ;;- 'G' a floating point constant that is *NOT* one of the standard
53 ;; 68881 constant values (to force calling output_move_const_double
54 ;; to get it from rom if it is a 68881 constant).
55 ;;
56 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
57 ;; info.
59 ;;- Immediate integer operand constraints:
60 ;;- 'I' 1 .. 8
61 ;;- 'J' -32768 .. 32767
62 ;;- 'K' all integers EXCEPT -128 .. 127
63 ;;- 'L' -8 .. -1
64 ;;- 'M' all integers EXCEPT -256 .. 255
65 ;;- 'N' 24 .. 31
66 ;;- 'O' 16
67 ;;- 'P' 8 .. 15
69 ;;- Assembler specs:
70 ;;- "%." size separator ("." or "") move%.l d0,d1
71 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
72 ;;- "%-" push operand "sp@-" move%.l d0,%-
73 ;;- "%+" pop operand "sp@+" move%.l d0,%+
74 ;;- "%@" top of stack "sp@" move%.l d0,%@
75 ;;- "%!" fpcr register
76 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
77 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
79 ;;- Information about 68040 port.
81 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
82 ;;- be emulated in software by the OS. It is faster to avoid these
83 ;;- instructions and issue a library call rather than trapping into
84 ;;- the kernel. The affected instructions are fintrz and fscale. The
85 ;;- TARGET_68040 flag turns the use of the opcodes off.
87 ;;- The '040 also implements a set of new floating-point instructions
88 ;;- which specify the rounding precision in the opcode. This finally
89 ;;- permit the 68k series to be truly IEEE compliant, and solves all
90 ;;- issues of excess precision accumulating in the extended registers.
91 ;;- By default, GCC does not use these instructions, since such code will
92 ;;- not run on an '030. To use these instructions, use the -m68040-only
93 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
94 ;;- you can make these instructions the default.
96 ;;- These new instructions aren't directly in the md. They are brought
97 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
98 ;;- than "".
100 ;;- Information about 68060 port.
102 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
103 ;;- be emulated in software by the OS. It is faster to avoid these
104 ;;- instructions and issue a library call rather than trapping into
105 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
106 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
107 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
109 ;;- Some of these insn's are composites of several m68000 op codes.
110 ;;- The assembler (or final @@??) insures that the appropriate one is
111 ;;- selected.
113 ;; UNSPEC usage:
115 (define_constants
116 [(UNSPEC_SIN 1)
117 (UNSPEC_COS 2)
118 ])
120 ;; UNSPEC_VOLATILE usage:
122 (define_constants
123 [(UNSPECV_BLOCKAGE 0)
124 ])
125 \f
126 (define_insn ""
127 [(set (match_operand:DF 0 "push_operand" "=m")
128 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
129 ""
130 "*
131 {
132 if (FP_REG_P (operands[1]))
133 return \"fmove%.d %f1,%0\";
134 return output_move_double (operands);
135 }")
137 (define_insn "pushdi"
138 [(set (match_operand:DI 0 "push_operand" "=m")
139 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
140 ""
141 "*
142 {
143 return output_move_double (operands);
144 }")
145 \f
146 ;; We don't want to allow a constant operand for test insns because
147 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
148 ;; be folded while optimizing anyway.
150 (define_expand "tstdi"
151 [(parallel [(set (cc0)
152 (match_operand:DI 0 "nonimmediate_operand" ""))
153 (clobber (match_scratch:SI 1 ""))
154 (clobber (match_scratch:DI 2 ""))])]
155 ""
156 "m68k_last_compare_had_fp_operands = 0;")
158 (define_insn ""
159 [(set (cc0)
160 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
161 (clobber (match_scratch:SI 1 "=X,d"))
162 (clobber (match_scratch:DI 2 "=d,X"))]
163 ""
164 "*
165 {
166 if (which_alternative == 0)
167 {
168 rtx xoperands[2];
170 xoperands[0] = operands[2];
171 xoperands[1] = operands[0];
172 output_move_double (xoperands);
173 cc_status.flags |= CC_REVERSED;
174 return \"neg%.l %R2\;negx%.l %2\";
175 }
176 if (find_reg_note (insn, REG_DEAD, operands[0]))
177 {
178 cc_status.flags |= CC_REVERSED;
179 return \"neg%.l %R0\;negx%.l %0\";
180 }
181 else
182 /*
183 ** 'sub' clears %1, and also clears the X cc bit
184 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
185 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
186 */
187 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
188 }")
190 (define_expand "tstsi"
191 [(set (cc0)
192 (match_operand:SI 0 "nonimmediate_operand" ""))]
193 ""
194 "m68k_last_compare_had_fp_operands = 0;")
196 (define_insn ""
197 [(set (cc0)
198 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
199 ""
200 "*
201 {
202 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
203 return \"tst%.l %0\";
204 /* If you think that the 68020 does not support tstl a0,
205 reread page B-167 of the 68020 manual more carefully. */
206 /* On an address reg, cmpw may replace cmpl. */
207 #ifdef SGS_CMP_ORDER
208 return \"cmp%.w %0,%#0\";
209 #else
210 return \"cmp%.w %#0,%0\";
211 #endif
212 }")
214 ;; This can't use an address register, because comparisons
215 ;; with address registers as second operand always test the whole word.
216 (define_expand "tsthi"
217 [(set (cc0)
218 (match_operand:HI 0 "nonimmediate_operand" ""))]
219 ""
220 "m68k_last_compare_had_fp_operands = 0;")
222 (define_insn ""
223 [(set (cc0)
224 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
225 ""
226 "tst%.w %0")
228 (define_expand "tstqi"
229 [(set (cc0)
230 (match_operand:QI 0 "nonimmediate_operand" ""))]
231 ""
232 "m68k_last_compare_had_fp_operands = 0;")
234 (define_insn ""
235 [(set (cc0)
236 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
237 ""
238 "tst%.b %0")
240 (define_expand "tstsf"
241 [(set (cc0)
242 (match_operand:SF 0 "general_operand" ""))]
243 "TARGET_68881"
244 "
245 {
246 m68k_last_compare_had_fp_operands = 1;
247 }")
249 (define_insn ""
250 [(set (cc0)
251 (match_operand:SF 0 "general_operand" "fdm"))]
252 "TARGET_68881"
253 "*
254 {
255 cc_status.flags = CC_IN_68881;
256 if (FP_REG_P (operands[0]))
257 return \"ftst%.x %0\";
258 return \"ftst%.s %0\";
259 }")
261 (define_expand "tstdf"
262 [(set (cc0)
263 (match_operand:DF 0 "general_operand" ""))]
264 "TARGET_68881"
265 "
266 {
267 m68k_last_compare_had_fp_operands = 1;
268 }")
270 (define_insn ""
271 [(set (cc0)
272 (match_operand:DF 0 "general_operand" "fm"))]
273 "TARGET_68881"
274 "*
275 {
276 cc_status.flags = CC_IN_68881;
277 if (FP_REG_P (operands[0]))
278 return \"ftst%.x %0\";
279 return \"ftst%.d %0\";
280 }")
281 \f
282 ;; compare instructions.
284 (define_expand "cmpdi"
285 [(parallel
286 [(set (cc0)
287 (compare (match_operand:DI 0 "nonimmediate_operand" "")
288 (match_operand:DI 1 "general_operand" "")))
289 (clobber (match_dup 2))])]
290 ""
291 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
293 (define_insn ""
294 [(set (cc0)
295 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
296 (match_operand:DI 2 "general_operand" "d,0")))
297 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
298 ""
299 "*
300 {
301 if (rtx_equal_p (operands[0], operands[1]))
302 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
303 else
304 {
305 cc_status.flags |= CC_REVERSED;
306 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
307 }
308 }")
310 ;; This is the second "hook" for PIC code (in addition to movsi). See
311 ;; comment of movsi for a description of PIC handling.
312 (define_expand "cmpsi"
313 [(set (cc0)
314 (compare (match_operand:SI 0 "nonimmediate_operand" "")
315 (match_operand:SI 1 "general_operand" "")))]
316 ""
317 "
318 {
319 m68k_last_compare_had_fp_operands = 0;
320 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
321 {
322 /* The source is an address which requires PIC relocation.
323 Call legitimize_pic_address with the source, mode, and a relocation
324 register (a new pseudo, or the final destination if reload_in_progress
325 is set). Then fall through normally */
326 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
327 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
328 }
329 }")
331 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
332 (define_insn ""
333 [(set (cc0)
334 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
335 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
336 "!TARGET_COLDFIRE"
337 "*
338 {
339 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
340 #ifdef SGS_CMP_ORDER
341 return \"cmpm%.l %0,%1\";
342 #else
343 return \"cmpm%.l %1,%0\";
344 #endif
345 if (REG_P (operands[1])
346 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
347 { cc_status.flags |= CC_REVERSED;
348 #ifdef SGS_CMP_ORDER
349 return \"cmp%.l %d1,%d0\";
350 #else
351 return \"cmp%.l %d0,%d1\";
352 #endif
353 }
354 if (ADDRESS_REG_P (operands[0])
355 && GET_CODE (operands[1]) == CONST_INT
356 && INTVAL (operands[1]) < 0x8000
357 && INTVAL (operands[1]) >= -0x8000)
358 {
359 #ifdef SGS_CMP_ORDER
360 return \"cmp%.w %0,%1\";
361 #else
362 return \"cmp%.w %1,%0\";
363 #endif
364 }
365 #ifdef SGS_CMP_ORDER
366 return \"cmp%.l %d0,%d1\";
367 #else
368 return \"cmp%.l %d1,%d0\";
369 #endif
370 }")
372 (define_insn ""
373 [(set (cc0)
374 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
375 (match_operand:SI 1 "general_operand" "r,mrKs")))]
376 "TARGET_COLDFIRE"
377 "*
378 {
379 if (REG_P (operands[1])
380 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
381 { cc_status.flags |= CC_REVERSED;
382 #ifdef SGS_CMP_ORDER
383 return \"cmp%.l %d1,%d0\";
384 #else
385 return \"cmp%.l %d0,%d1\";
386 #endif
387 }
388 #ifdef SGS_CMP_ORDER
389 return \"cmp%.l %d0,%d1\";
390 #else
391 return \"cmp%.l %d1,%d0\";
392 #endif
393 }")
395 (define_expand "cmphi"
396 [(set (cc0)
397 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
398 (match_operand:HI 1 "general_src_operand" "")))]
399 "!TARGET_COLDFIRE"
400 "m68k_last_compare_had_fp_operands = 0;")
402 (define_insn ""
403 [(set (cc0)
404 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
405 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
406 "!TARGET_COLDFIRE"
407 "*
408 {
409 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
410 #ifdef SGS_CMP_ORDER
411 return \"cmpm%.w %0,%1\";
412 #else
413 return \"cmpm%.w %1,%0\";
414 #endif
415 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
416 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
417 { cc_status.flags |= CC_REVERSED;
418 #ifdef SGS_CMP_ORDER
419 return \"cmp%.w %d1,%d0\";
420 #else
421 return \"cmp%.w %d0,%d1\";
422 #endif
423 }
424 #ifdef SGS_CMP_ORDER
425 return \"cmp%.w %d0,%d1\";
426 #else
427 return \"cmp%.w %d1,%d0\";
428 #endif
429 }")
431 (define_expand "cmpqi"
432 [(set (cc0)
433 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
434 (match_operand:QI 1 "general_src_operand" "")))]
435 "!TARGET_COLDFIRE"
436 "m68k_last_compare_had_fp_operands = 0;")
438 (define_insn ""
439 [(set (cc0)
440 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
441 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
442 "!TARGET_COLDFIRE"
443 "*
444 {
445 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
446 #ifdef SGS_CMP_ORDER
447 return \"cmpm%.b %0,%1\";
448 #else
449 return \"cmpm%.b %1,%0\";
450 #endif
451 if (REG_P (operands[1])
452 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
453 { cc_status.flags |= CC_REVERSED;
454 #ifdef SGS_CMP_ORDER
455 return \"cmp%.b %d1,%d0\";
456 #else
457 return \"cmp%.b %d0,%d1\";
458 #endif
459 }
460 #ifdef SGS_CMP_ORDER
461 return \"cmp%.b %d0,%d1\";
462 #else
463 return \"cmp%.b %d1,%d0\";
464 #endif
465 }")
467 (define_expand "cmpdf"
468 [(set (cc0)
469 (compare (match_operand:DF 0 "general_operand" "")
470 (match_operand:DF 1 "general_operand" "")))]
471 "TARGET_68881"
472 "
473 {
474 m68k_last_compare_had_fp_operands = 1;
475 }")
477 (define_insn ""
478 [(set (cc0)
479 (compare (match_operand:DF 0 "general_operand" "f,mG")
480 (match_operand:DF 1 "general_operand" "fmG,f")))]
481 "TARGET_68881"
482 "*
483 {
484 cc_status.flags = CC_IN_68881;
485 #ifdef SGS_CMP_ORDER
486 if (REG_P (operands[0]))
487 {
488 if (REG_P (operands[1]))
489 return \"fcmp%.x %0,%1\";
490 else
491 return \"fcmp%.d %0,%f1\";
492 }
493 cc_status.flags |= CC_REVERSED;
494 return \"fcmp%.d %1,%f0\";
495 #else
496 if (REG_P (operands[0]))
497 {
498 if (REG_P (operands[1]))
499 return \"fcmp%.x %1,%0\";
500 else
501 return \"fcmp%.d %f1,%0\";
502 }
503 cc_status.flags |= CC_REVERSED;
504 return \"fcmp%.d %f0,%1\";
505 #endif
506 }")
508 (define_expand "cmpsf"
509 [(set (cc0)
510 (compare (match_operand:SF 0 "general_operand" "")
511 (match_operand:SF 1 "general_operand" "")))]
512 "TARGET_68881"
513 "
514 {
515 m68k_last_compare_had_fp_operands = 1;
516 }")
518 (define_insn ""
519 [(set (cc0)
520 (compare (match_operand:SF 0 "general_operand" "f,mdG")
521 (match_operand:SF 1 "general_operand" "fmdG,f")))]
522 "TARGET_68881"
523 "*
524 {
525 cc_status.flags = CC_IN_68881;
526 #ifdef SGS_CMP_ORDER
527 if (FP_REG_P (operands[0]))
528 {
529 if (FP_REG_P (operands[1]))
530 return \"fcmp%.x %0,%1\";
531 else
532 return \"fcmp%.s %0,%f1\";
533 }
534 cc_status.flags |= CC_REVERSED;
535 return \"fcmp%.s %1,%f0\";
536 #else
537 if (FP_REG_P (operands[0]))
538 {
539 if (FP_REG_P (operands[1]))
540 return \"fcmp%.x %1,%0\";
541 else
542 return \"fcmp%.s %f1,%0\";
543 }
544 cc_status.flags |= CC_REVERSED;
545 return \"fcmp%.s %f0,%1\";
546 #endif
547 }")
548 \f
549 ;; Recognizers for btst instructions.
551 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
552 ;; specified as a constant, so we must disable all patterns that may extract
553 ;; from a MEM at a constant bit position if we can't use this as a constraint.
555 (define_insn ""
556 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
557 (const_int 1)
558 (minus:SI (const_int 7)
559 (match_operand:SI 1 "general_operand" "di"))))]
560 "!TARGET_COLDFIRE"
561 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
563 ;; This is the same as the above pattern except for the constraints. The 'i'
564 ;; has been deleted.
566 (define_insn ""
567 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
568 (const_int 1)
569 (minus:SI (const_int 7)
570 (match_operand:SI 1 "general_operand" "d"))))]
571 "TARGET_COLDFIRE"
572 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
574 (define_insn ""
575 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
576 (const_int 1)
577 (minus:SI (const_int 31)
578 (match_operand:SI 1 "general_operand" "di"))))]
579 ""
580 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
582 ;; The following two patterns are like the previous two
583 ;; except that they use the fact that bit-number operands
584 ;; are automatically masked to 3 or 5 bits.
586 (define_insn ""
587 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
588 (const_int 1)
589 (minus:SI (const_int 7)
590 (and:SI
591 (match_operand:SI 1 "register_operand" "d")
592 (const_int 7)))))]
593 ""
594 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
596 (define_insn ""
597 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
598 (const_int 1)
599 (minus:SI (const_int 31)
600 (and:SI
601 (match_operand:SI 1 "register_operand" "d")
602 (const_int 31)))))]
603 ""
604 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
606 ;; Nonoffsettable mem refs are ok in this one pattern
607 ;; since we don't try to adjust them.
608 (define_insn ""
609 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
610 (const_int 1)
611 (match_operand:SI 1 "const_int_operand" "n")))]
612 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
613 "*
614 {
615 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
616 return output_btst (operands, operands[1], operands[0], insn, 7);
617 }")
619 (define_insn ""
620 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
621 (const_int 1)
622 (match_operand:SI 1 "const_int_operand" "n")))]
623 "!TARGET_COLDFIRE"
624 "*
625 {
626 if (GET_CODE (operands[0]) == MEM)
627 {
628 operands[0] = adjust_address (operands[0], QImode,
629 INTVAL (operands[1]) / 8);
630 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
631 return output_btst (operands, operands[1], operands[0], insn, 7);
632 }
633 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
634 return output_btst (operands, operands[1], operands[0], insn, 31);
635 }")
637 ;; This is the same as the above pattern except for the constraints.
638 ;; The 'o' has been replaced with 'Q'.
640 (define_insn ""
641 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
642 (const_int 1)
643 (match_operand:SI 1 "const_int_operand" "n")))]
644 "TARGET_COLDFIRE"
645 "*
646 {
647 if (GET_CODE (operands[0]) == MEM)
648 {
649 operands[0] = adjust_address (operands[0], QImode,
650 INTVAL (operands[1]) / 8);
651 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
652 return output_btst (operands, operands[1], operands[0], insn, 7);
653 }
654 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
655 return output_btst (operands, operands[1], operands[0], insn, 31);
656 }")
658 \f
659 ;; move instructions
661 ;; A special case in which it is not desirable
662 ;; to reload the constant into a data register.
663 (define_insn "pushexthisi_const"
664 [(set (match_operand:SI 0 "push_operand" "=m")
665 (match_operand:SI 1 "const_int_operand" "J"))]
666 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
667 "*
668 {
669 if (operands[1] == const0_rtx)
670 return \"clr%.l %0\";
671 return \"pea %a1\";
672 }")
674 ;This is never used.
675 ;(define_insn "swapsi"
676 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
677 ; (match_operand:SI 1 "general_operand" "+r"))
678 ; (set (match_dup 1) (match_dup 0))]
679 ; ""
680 ; "exg %1,%0")
682 ;; Special case of fullword move when source is zero.
683 ;; The reason this is special is to avoid loading a zero
684 ;; into a data reg with moveq in order to store it elsewhere.
686 (define_insn "movsi_const0"
687 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
688 (const_int 0))]
689 ;; clr insns on 68000 read before writing.
690 ;; This isn't so on the 68010, but we have no TARGET_68010.
691 "((TARGET_68020 || TARGET_COLDFIRE)
692 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
693 "*
694 {
695 if (ADDRESS_REG_P (operands[0]))
696 {
697 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
698 if (!TARGET_68040 && !TARGET_68060)
699 return \"sub%.l %0,%0\";
700 else
701 return MOTOROLA ?
702 #ifdef SGS
703 /* Many SGS assemblers croak on size specifiers for constants. */
704 \"lea 0,%0\" :
705 #else
706 \"lea 0.w,%0\" :
707 #endif
708 \"lea 0:w,%0\";
709 }
710 /* moveq is faster on the 68000. */
711 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE))
712 return \"moveq %#0,%0\";
713 return \"clr%.l %0\";
714 }")
716 ;; General case of fullword move.
717 ;;
718 ;; This is the main "hook" for PIC code. When generating
719 ;; PIC, movsi is responsible for determining when the source address
720 ;; needs PIC relocation and appropriately calling legitimize_pic_address
721 ;; to perform the actual relocation.
722 ;;
723 ;; In both the PIC and non-PIC cases the patterns generated will
724 ;; matched by the next define_insn.
725 (define_expand "movsi"
726 [(set (match_operand:SI 0 "nonimmediate_operand" "")
727 (match_operand:SI 1 "general_operand" ""))]
728 ""
729 "
730 {
731 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
732 {
733 /* The source is an address which requires PIC relocation.
734 Call legitimize_pic_address with the source, mode, and a relocation
735 register (a new pseudo, or the final destination if reload_in_progress
736 is set). Then fall through normally */
737 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
738 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
739 }
740 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
741 {
742 /* Don't allow writes to memory except via a register;
743 the m68k doesn't consider PC-relative addresses to be writable. */
744 if (symbolic_operand (operands[0], SImode))
745 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
746 else if (GET_CODE (operands[0]) == MEM
747 && symbolic_operand (XEXP (operands[0], 0), SImode))
748 operands[0] = gen_rtx (MEM, SImode,
749 force_reg (SImode, XEXP (operands[0], 0)));
750 }
751 }")
753 ;; General case of fullword move. The register constraints
754 ;; force integer constants in range for a moveq to be reloaded
755 ;; if they are headed for memory.
756 (define_insn ""
757 ;; Notes: make sure no alternative allows g vs g.
758 ;; We don't allow f-regs since fixed point cannot go in them.
759 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
760 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
762 "!TARGET_COLDFIRE"
763 "*
764 {
765 return output_move_simode (operands);
766 }")
768 (define_insn ""
769 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
770 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
771 "TARGET_COLDFIRE"
772 "* return output_move_simode (operands);")
774 ;; Special case of fullword move, where we need to get a non-GOT PIC
775 ;; reference into an address register.
776 (define_insn ""
777 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
778 (match_operand:SI 1 "pcrel_address" ""))]
779 "TARGET_PCREL"
780 "*
781 {
782 if (push_operand (operands[0], SImode))
783 return \"pea %a1\";
784 return \"lea %a1,%0\";
785 }")
787 (define_expand "movhi"
788 [(set (match_operand:HI 0 "nonimmediate_operand" "")
789 (match_operand:HI 1 "general_operand" ""))]
790 ""
791 "")
793 (define_insn ""
794 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
795 (match_operand:HI 1 "general_src_operand" "gS"))]
796 "!TARGET_COLDFIRE"
797 "* return output_move_himode (operands);")
799 (define_insn ""
800 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
801 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
802 "TARGET_COLDFIRE"
803 "* return output_move_himode (operands);")
805 (define_expand "movstricthi"
806 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
807 (match_operand:HI 1 "general_src_operand" ""))]
808 ""
809 "")
811 (define_insn ""
812 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
813 (match_operand:HI 1 "general_src_operand" "rmSn"))]
814 "!TARGET_COLDFIRE"
815 "* return output_move_stricthi (operands);")
817 (define_insn ""
818 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
819 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
820 "TARGET_COLDFIRE"
821 "* return output_move_stricthi (operands);")
823 (define_expand "movqi"
824 [(set (match_operand:QI 0 "nonimmediate_operand" "")
825 (match_operand:QI 1 "general_src_operand" ""))]
826 ""
827 "")
829 (define_insn ""
830 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
831 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
832 "!TARGET_COLDFIRE"
833 "* return output_move_qimode (operands);")
835 (define_insn ""
836 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
837 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
838 "TARGET_COLDFIRE"
839 "* return output_move_qimode (operands);")
841 (define_expand "movstrictqi"
842 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
843 (match_operand:QI 1 "general_src_operand" ""))]
844 ""
845 "")
847 (define_insn ""
848 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
849 (match_operand:QI 1 "general_src_operand" "dmSn"))]
850 "!TARGET_COLDFIRE"
851 "* return output_move_strictqi (operands);")
853 (define_insn ""
854 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
855 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
856 "TARGET_COLDFIRE"
857 "* return output_move_strictqi (operands);")
859 (define_expand "pushqi1"
860 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
861 (set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
862 (match_operand:QI 0 "general_operand" ""))]
863 "!TARGET_COLDFIRE"
864 "")
866 (define_expand "movsf"
867 [(set (match_operand:SF 0 "nonimmediate_operand" "")
868 (match_operand:SF 1 "general_operand" ""))]
869 ""
870 "")
872 (define_insn ""
873 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
874 (match_operand:SF 1 "general_operand" "rmfF"))]
875 "!TARGET_COLDFIRE"
876 "*
877 {
878 if (FP_REG_P (operands[0]))
879 {
880 if (FP_REG_P (operands[1]))
881 return \"f%$move%.x %1,%0\";
882 else if (ADDRESS_REG_P (operands[1]))
883 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
884 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
885 return output_move_const_single (operands);
886 return \"f%$move%.s %f1,%0\";
887 }
888 if (FP_REG_P (operands[1]))
889 {
890 if (ADDRESS_REG_P (operands[0]))
891 return \"fmove%.s %1,%-\;move%.l %+,%0\";
892 return \"fmove%.s %f1,%0\";
893 }
894 if (operands[1] == CONST0_RTX (SFmode)
895 /* clr insns on 68000 read before writing.
896 This isn't so on the 68010, but we have no TARGET_68010. */
897 && ((TARGET_68020 || TARGET_COLDFIRE)
898 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
899 {
900 if (ADDRESS_REG_P (operands[0]))
901 {
902 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
903 if (!TARGET_68040 && !TARGET_68060)
904 return \"sub%.l %0,%0\";
905 else
906 return MOTOROLA ?
907 #ifdef SGS
908 /* Many SGS assemblers croak on size specifiers for constants. */
909 \"lea 0,%0\" :
910 #else
911 \"lea 0.w,%0\" :
912 #endif
913 \"lea 0:w,%0\";
914 }
915 /* moveq is faster on the 68000. */
916 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE))
917 {
918 return \"moveq %#0,%0\";
919 }
920 return \"clr%.l %0\";
921 }
922 return \"move%.l %1,%0\";
923 }")
925 (define_insn ""
926 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
927 (match_operand:SF 1 "general_operand" "g,r"))]
928 "TARGET_COLDFIRE"
929 "* return \"move%.l %1,%0\";")
931 (define_expand "movdf"
932 [(set (match_operand:DF 0 "nonimmediate_operand" "")
933 (match_operand:DF 1 "general_operand" ""))]
934 ""
935 "")
937 (define_insn ""
938 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
939 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
940 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
941 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
942 "!TARGET_COLDFIRE"
943 "*
944 {
945 if (FP_REG_P (operands[0]))
946 {
947 if (FP_REG_P (operands[1]))
948 return \"f%&move%.x %1,%0\";
949 if (REG_P (operands[1]))
950 {
951 rtx xoperands[2];
952 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
953 output_asm_insn (\"move%.l %1,%-\", xoperands);
954 output_asm_insn (\"move%.l %1,%-\", operands);
955 return \"f%&move%.d %+,%0\";
956 }
957 if (GET_CODE (operands[1]) == CONST_DOUBLE)
958 return output_move_const_double (operands);
959 return \"f%&move%.d %f1,%0\";
960 }
961 else if (FP_REG_P (operands[1]))
962 {
963 if (REG_P (operands[0]))
964 {
965 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
966 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
967 return \"move%.l %+,%0\";
968 }
969 else
970 return \"fmove%.d %f1,%0\";
971 }
972 return output_move_double (operands);
973 }")
975 (define_insn ""
976 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
977 (match_operand:DF 1 "general_operand" "g,r"))]
978 "TARGET_COLDFIRE"
979 "* return output_move_double (operands);")
981 ;; ??? The XFmode patterns are schizophrenic about whether constants are
982 ;; allowed. Most but not all have predicates and constraint that disallow
983 ;; constants. Most but not all have output templates that handle constants.
984 ;; See also LEGITIMATE_CONSTANT_P.
986 (define_expand "movxf"
987 [(set (match_operand:XF 0 "nonimmediate_operand" "")
988 (match_operand:XF 1 "general_operand" ""))]
989 ""
990 "
991 {
992 /* We can't rewrite operands during reload. */
993 if (! reload_in_progress)
994 {
995 if (CONSTANT_P (operands[1]))
996 {
997 operands[1] = force_const_mem (XFmode, operands[1]);
998 if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
999 operands[1] = adjust_address (operands[1], XFmode, 0);
1000 }
1001 if (flag_pic && TARGET_PCREL)
1002 {
1003 /* Don't allow writes to memory except via a register; the
1004 m68k doesn't consider PC-relative addresses to be writable. */
1005 if (GET_CODE (operands[0]) == MEM
1006 && symbolic_operand (XEXP (operands[0], 0), SImode))
1007 operands[0] = gen_rtx (MEM, XFmode,
1008 force_reg (SImode, XEXP (operands[0], 0)));
1009 }
1010 }
1011 }")
1013 (define_insn ""
1014 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1015 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1016 "TARGET_68881"
1017 "*
1018 {
1019 if (FP_REG_P (operands[0]))
1020 {
1021 if (FP_REG_P (operands[1]))
1022 return \"fmove%.x %1,%0\";
1023 if (REG_P (operands[1]))
1024 {
1025 rtx xoperands[2];
1026 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1027 output_asm_insn (\"move%.l %1,%-\", xoperands);
1028 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1029 output_asm_insn (\"move%.l %1,%-\", xoperands);
1030 output_asm_insn (\"move%.l %1,%-\", operands);
1031 return \"fmove%.x %+,%0\";
1032 }
1033 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1034 return \"fmove%.x %1,%0\";
1035 return \"fmove%.x %f1,%0\";
1036 }
1037 if (FP_REG_P (operands[1]))
1038 {
1039 if (REG_P (operands[0]))
1040 {
1041 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1042 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1043 output_asm_insn (\"move%.l %+,%0\", operands);
1044 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1045 return \"move%.l %+,%0\";
1046 }
1047 /* Must be memory destination. */
1048 return \"fmove%.x %f1,%0\";
1049 }
1050 return output_move_double (operands);
1051 }
1052 ")
1054 (define_insn ""
1055 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1056 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1057 "! TARGET_68881 && ! TARGET_COLDFIRE"
1058 "*
1059 {
1060 if (FP_REG_P (operands[0]))
1061 {
1062 if (FP_REG_P (operands[1]))
1063 return \"fmove%.x %1,%0\";
1064 if (REG_P (operands[1]))
1065 {
1066 rtx xoperands[2];
1067 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1068 output_asm_insn (\"move%.l %1,%-\", xoperands);
1069 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1070 output_asm_insn (\"move%.l %1,%-\", xoperands);
1071 output_asm_insn (\"move%.l %1,%-\", operands);
1072 return \"fmove%.x %+,%0\";
1073 }
1074 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1075 return \"fmove%.x %1,%0\";
1076 return \"fmove%.x %f1,%0\";
1077 }
1078 if (FP_REG_P (operands[1]))
1079 {
1080 if (REG_P (operands[0]))
1081 {
1082 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1083 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1084 output_asm_insn (\"move%.l %+,%0\", operands);
1085 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1086 return \"move%.l %+,%0\";
1087 }
1088 else
1089 return \"fmove%.x %f1,%0\";
1090 }
1091 return output_move_double (operands);
1092 }
1093 ")
1095 (define_insn ""
1096 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1097 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1098 "! TARGET_68881 && TARGET_COLDFIRE"
1099 "* return output_move_double (operands);")
1101 (define_expand "movdi"
1102 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1103 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1104 (match_operand:DI 1 "general_operand" ""))]
1105 ""
1106 "")
1108 ;; movdi can apply to fp regs in some cases
1109 (define_insn ""
1110 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1111 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
1112 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
1113 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
1114 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
1115 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1116 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1117 "!TARGET_COLDFIRE"
1118 "*
1119 {
1120 if (FP_REG_P (operands[0]))
1121 {
1122 if (FP_REG_P (operands[1]))
1123 return \"fmove%.x %1,%0\";
1124 if (REG_P (operands[1]))
1125 {
1126 rtx xoperands[2];
1127 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1128 output_asm_insn (\"move%.l %1,%-\", xoperands);
1129 output_asm_insn (\"move%.l %1,%-\", operands);
1130 return \"fmove%.d %+,%0\";
1131 }
1132 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1133 return output_move_const_double (operands);
1134 return \"fmove%.d %f1,%0\";
1135 }
1136 else if (FP_REG_P (operands[1]))
1137 {
1138 if (REG_P (operands[0]))
1139 {
1140 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1141 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1142 return \"move%.l %+,%0\";
1143 }
1144 else
1145 return \"fmove%.d %f1,%0\";
1146 }
1147 return output_move_double (operands);
1148 }")
1150 (define_insn ""
1151 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1152 (match_operand:DI 1 "general_operand" "g,r"))]
1153 "TARGET_COLDFIRE"
1154 "* return output_move_double (operands);")
1156 ;; Thus goes after the move instructions
1157 ;; because the move instructions are better (require no spilling)
1158 ;; when they can apply. It goes before the add/sub insns
1159 ;; so we will prefer it to them.
1161 (define_insn "pushasi"
1162 [(set (match_operand:SI 0 "push_operand" "=m")
1163 (match_operand:SI 1 "address_operand" "p"))]
1164 ""
1165 "pea %a1")
1166 \f
1167 ;; truncation instructions
1168 (define_insn "truncsiqi2"
1169 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1170 (truncate:QI
1171 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1172 ""
1173 "*
1174 {
1175 if (GET_CODE (operands[0]) == REG)
1176 {
1177 /* Must clear condition codes, since the move.l bases them on
1178 the entire 32 bits, not just the desired 8 bits. */
1179 CC_STATUS_INIT;
1180 return \"move%.l %1,%0\";
1181 }
1182 if (GET_CODE (operands[1]) == MEM)
1183 operands[1] = adjust_address (operands[1], QImode, 3);
1184 return \"move%.b %1,%0\";
1185 }")
1187 (define_insn "trunchiqi2"
1188 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1189 (truncate:QI
1190 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1191 ""
1192 "*
1193 {
1194 if (GET_CODE (operands[0]) == REG
1195 && (GET_CODE (operands[1]) == MEM
1196 || GET_CODE (operands[1]) == CONST_INT))
1197 {
1198 /* Must clear condition codes, since the move.w bases them on
1199 the entire 16 bits, not just the desired 8 bits. */
1200 CC_STATUS_INIT;
1201 return \"move%.w %1,%0\";
1202 }
1203 if (GET_CODE (operands[0]) == REG)
1204 {
1205 /* Must clear condition codes, since the move.l bases them on
1206 the entire 32 bits, not just the desired 8 bits. */
1207 CC_STATUS_INIT;
1208 return \"move%.l %1,%0\";
1209 }
1210 if (GET_CODE (operands[1]) == MEM)
1211 operands[1] = adjust_address (operands[1], QImode, 1);
1212 return \"move%.b %1,%0\";
1213 }")
1215 (define_insn "truncsihi2"
1216 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1217 (truncate:HI
1218 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1219 ""
1220 "*
1221 {
1222 if (GET_CODE (operands[0]) == REG)
1223 {
1224 /* Must clear condition codes, since the move.l bases them on
1225 the entire 32 bits, not just the desired 8 bits. */
1226 CC_STATUS_INIT;
1227 return \"move%.l %1,%0\";
1228 }
1229 if (GET_CODE (operands[1]) == MEM)
1230 operands[1] = adjust_address (operands[1], QImode, 2);
1231 return \"move%.w %1,%0\";
1232 }")
1233 \f
1234 ;; zero extension instructions
1236 (define_insn "zero_extendqidi2"
1237 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1238 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1239 ""
1240 "*
1241 {
1242 CC_STATUS_INIT;
1243 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1244 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1245 }")
1247 (define_insn "zero_extendhidi2"
1248 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1249 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1250 ""
1251 "*
1252 {
1253 CC_STATUS_INIT;
1254 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1255 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1256 }")
1258 ;; this is the canonical form for (lshiftrt:DI x 32)
1259 (define_expand "zero_extendsidi2"
1260 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1261 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
1262 ""
1263 "")
1265 (define_insn "*zero_extendsidi2_cf"
1266 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
1267 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
1268 "TARGET_COLDFIRE"
1269 "*
1270 {
1271 CC_STATUS_INIT;
1272 if (GET_CODE (operands[0]) == REG)
1273 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1274 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1275 return \"move%.l %1,%0\;clr%.l %0\";
1276 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1277 return \"clr%.l %0\;move%.l %1,%0\";
1278 else
1279 operands[2] = adjust_address (operands[0], SImode, 4);
1280 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1281 || REGNO (operands[1]) != REGNO (operands[2]))
1282 output_asm_insn (\"move%.l %1,%2\", operands);
1283 if (ADDRESS_REG_P (operands[0]))
1284 return \"sub%.l %0,%0\";
1285 else
1286 return \"clr%.l %0\";
1287 }")
1289 (define_insn "*zero_extendsidi2"
1290 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
1291 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1292 "!TARGET_COLDFIRE"
1293 "*
1294 {
1295 CC_STATUS_INIT;
1296 if (GET_CODE (operands[0]) == REG)
1297 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1298 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1299 return \"move%.l %1,%0\;clr%.l %0\";
1300 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1301 return \"clr%.l %0\;move%.l %1,%0\";
1302 else
1303 operands[2] = adjust_address (operands[0], SImode, 4);
1304 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1305 || REGNO (operands[1]) != REGNO (operands[2]))
1306 output_asm_insn (\"move%.l %1,%2\", operands);
1307 if (ADDRESS_REG_P (operands[0]))
1308 return \"sub%.l %0,%0\";
1309 else
1310 return \"clr%.l %0\";
1311 }")
1313 (define_expand "zero_extendhisi2"
1314 [(set (match_operand:SI 0 "register_operand" "")
1315 (const_int 0))
1316 (set (strict_low_part (match_dup 2))
1317 (match_operand:HI 1 "general_operand" ""))]
1318 ""
1319 "
1320 {
1321 operands[1] = make_safe_from (operands[1], operands[0]);
1322 operands[2] = gen_lowpart_SUBREG (HImode, operands[0]);
1323 }")
1325 (define_expand "zero_extendqihi2"
1326 [(set (match_operand:HI 0 "register_operand" "")
1327 (const_int 0))
1328 (set (strict_low_part (match_dup 2))
1329 (match_operand:QI 1 "general_operand" ""))]
1330 ""
1331 "
1332 {
1333 operands[1] = make_safe_from (operands[1], operands[0]);
1334 operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
1335 }")
1337 (define_expand "zero_extendqisi2"
1338 [(set (match_operand:SI 0 "register_operand" "")
1339 (const_int 0))
1340 (set (strict_low_part (match_dup 2))
1341 (match_operand:QI 1 "general_operand" ""))]
1342 ""
1343 "
1344 {
1345 operands[1] = make_safe_from (operands[1], operands[0]);
1346 operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
1347 }")
1348 \f
1349 ;; Patterns to recognize zero-extend insns produced by the combiner.
1350 ;; We don't allow both operands in memory, because of aliasing problems.
1351 ;; Explicitly disallow two memory operands via the condition since reloading
1352 ;; of this case will result in worse code than the uncombined patterns.
1354 (define_insn ""
1355 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d<")
1356 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1357 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1358 "*
1359 {
1360 if (DATA_REG_P (operands[0]))
1361 {
1362 if (GET_CODE (operands[1]) == REG
1363 && REGNO (operands[0]) == REGNO (operands[1]))
1364 return \"and%.l %#0xFFFF,%0\";
1365 if (reg_mentioned_p (operands[0], operands[1]))
1366 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1367 return \"clr%.l %0\;move%.w %1,%0\";
1368 }
1369 else if (GET_CODE (operands[0]) == MEM
1370 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1371 return \"move%.w %1,%0\;clr%.w %0\";
1372 else if (GET_CODE (operands[0]) == MEM
1373 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1374 return \"clr%.w %0\;move%.w %1,%0\";
1375 else
1376 {
1377 output_asm_insn (\"clr%.w %0\", operands);
1378 operands[0] = adjust_address (operands[0], HImode, 2);
1379 return \"move%.w %1,%0\";
1380 }
1381 }")
1383 (define_insn ""
1384 [(set (match_operand:HI 0 "nonimmediate_operand" "=do<>,d")
1385 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1386 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1387 "*
1388 {
1389 if (DATA_REG_P (operands[0]))
1390 {
1391 if (GET_CODE (operands[1]) == REG
1392 && REGNO (operands[0]) == REGNO (operands[1]))
1393 return (!TARGET_COLDFIRE ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1394 if (reg_mentioned_p (operands[0], operands[1]))
1395 return (!TARGET_COLDFIRE ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1396 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1397 return \"clr%.w %0\;move%.b %1,%0\";
1398 }
1399 else if (GET_CODE (operands[0]) == MEM
1400 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1401 {
1402 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1403 == STACK_POINTER_REGNUM)
1404 {
1405 output_asm_insn (\"clr%.w %-\", operands);
1406 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1407 plus_constant (stack_pointer_rtx, 1));
1408 return \"move%.b %1,%0\";
1409 }
1410 else
1411 return \"move%.b %1,%0\;clr%.b %0\";
1412 }
1413 else if (GET_CODE (operands[0]) == MEM
1414 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1415 return \"clr%.b %0\;move%.b %1,%0\";
1416 else
1417 {
1418 output_asm_insn (\"clr%.b %0\", operands);
1419 operands[0] = adjust_address (operands[0], QImode, 1);
1420 return \"move%.b %1,%0\";
1421 }
1422 }")
1424 (define_insn ""
1425 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d")
1426 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1427 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1428 "*
1429 {
1430 if (DATA_REG_P (operands[0]))
1431 {
1432 if (GET_CODE (operands[1]) == REG
1433 && REGNO (operands[0]) == REGNO (operands[1]))
1434 return \"and%.l %#0xFF,%0\";
1435 if (reg_mentioned_p (operands[0], operands[1]))
1436 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1437 return \"clr%.l %0\;move%.b %1,%0\";
1438 }
1439 else if (GET_CODE (operands[0]) == MEM
1440 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1441 {
1442 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1443 return MOTOROLA ?
1444 #ifdef SGS
1445 \"clr%.l -(%0)\;move%.b %1,3(%0)\" :
1446 #else
1447 \"clr%.l -(%0)\;move%.b %1,(3,%0)\" :
1448 #endif
1449 \"clrl %0@-\;moveb %1,%0@(3)\";
1451 }
1452 else if (GET_CODE (operands[0]) == MEM
1453 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1454 {
1455 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1456 return MOTOROLA ?
1457 #ifdef SGS
1458 \"clr%.l (%0)+\;move%.b %1,-1(%0)\" :
1459 #else
1460 \"clr%.l (%0)+\;move%.b %1,(-1,%0)\" :
1461 #endif
1462 \"clrl %0@+\;moveb %1,%0@(-1)\";
1463 }
1464 else
1465 {
1466 output_asm_insn (\"clr%.l %0\", operands);
1467 operands[0] = adjust_address (operands[0], QImode, 3);
1468 return \"move%.b %1,%0\";
1469 }
1470 }")
1471 \f
1472 ;; sign extension instructions
1474 (define_insn "extendqidi2"
1475 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1476 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1477 ""
1478 "*
1479 {
1480 CC_STATUS_INIT;
1481 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1482 if (TARGET_68020 || TARGET_COLDFIRE)
1483 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1484 else
1485 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1486 }")
1488 (define_insn "extendhidi2"
1489 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1490 (sign_extend:DI
1491 (match_operand:HI 1 "general_src_operand" "rmS")))]
1492 ""
1493 "*
1494 {
1495 CC_STATUS_INIT;
1496 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1497 if (TARGET_68020 || TARGET_COLDFIRE)
1498 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1499 else
1500 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1501 }")
1503 (define_insn "extendsidi2"
1504 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1505 (sign_extend:DI
1506 (match_operand:SI 1 "general_operand" "rm")))]
1507 ""
1508 "*
1509 {
1510 CC_STATUS_INIT;
1511 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1512 if (TARGET_68020 || TARGET_COLDFIRE)
1513 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1514 else
1515 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1516 }")
1518 ;; Special case when one can avoid register clobbering, copy and test
1519 ;; Maybe there is a way to make that the general case, by forcing the
1520 ;; result of the SI tree to be in the lower register of the DI target
1522 (define_insn "extendplussidi"
1523 [(set (match_operand:DI 0 "register_operand" "=d")
1524 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1525 (match_operand:SI 2 "general_operand" "rmn"))))]
1526 ""
1527 "*
1528 {
1529 CC_STATUS_INIT;
1530 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1531 if (GET_CODE (operands[1]) == CONST_INT
1532 && (unsigned) INTVAL (operands[1]) > 8)
1533 {
1534 rtx tmp = operands[1];
1536 operands[1] = operands[2];
1537 operands[2] = tmp;
1538 }
1539 if (GET_CODE (operands[1]) == REG
1540 && REGNO (operands[1]) == REGNO (operands[3]))
1541 output_asm_insn (\"add%.l %2,%3\", operands);
1542 else
1543 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1544 if (TARGET_68020 || TARGET_COLDFIRE)
1545 return \"smi %0\;extb%.l %0\";
1546 else
1547 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1548 }")
1550 (define_insn "extendhisi2"
1551 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1552 (sign_extend:SI
1553 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1554 ""
1555 "*
1556 {
1557 if (ADDRESS_REG_P (operands[0]))
1558 return \"move%.w %1,%0\";
1559 return \"ext%.l %0\";
1560 }")
1562 (define_insn "extendqihi2"
1563 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1564 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1565 ""
1566 "ext%.w %0")
1568 (define_insn "extendqisi2"
1569 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1570 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1571 "TARGET_68020 || TARGET_COLDFIRE"
1572 "extb%.l %0")
1573 \f
1574 ;; Conversions between float and double.
1576 (define_expand "extendsfdf2"
1577 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1578 (float_extend:DF
1579 (match_operand:SF 1 "general_operand" "")))]
1580 "TARGET_68881"
1581 "")
1583 (define_insn ""
1584 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1585 (float_extend:DF
1586 (match_operand:SF 1 "general_operand" "f,dmF")))]
1587 "TARGET_68881"
1588 "*
1589 {
1590 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1591 {
1592 if (REGNO (operands[0]) == REGNO (operands[1]))
1593 {
1594 /* Extending float to double in an fp-reg is a no-op.
1595 NOTICE_UPDATE_CC has already assumed that the
1596 cc will be set. So cancel what it did. */
1597 cc_status = cc_prev_status;
1598 return \"\";
1599 }
1600 return \"f%&move%.x %1,%0\";
1601 }
1602 if (FP_REG_P (operands[0]))
1603 return \"f%&move%.s %f1,%0\";
1604 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1605 {
1606 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1607 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1608 return \"move%.l %+,%0\";
1609 }
1610 return \"fmove%.d %f1,%0\";
1611 }")
1613 ;; This cannot output into an f-reg because there is no way to be
1614 ;; sure of truncating in that case.
1615 (define_expand "truncdfsf2"
1616 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1617 (float_truncate:SF
1618 (match_operand:DF 1 "general_operand" "")))]
1619 "TARGET_68881"
1620 "")
1622 ;; On the '040 we can truncate in a register accurately and easily.
1623 (define_insn ""
1624 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1625 (float_truncate:SF
1626 (match_operand:DF 1 "general_operand" "fmG")))]
1627 "TARGET_68040_ONLY"
1628 "*
1629 {
1630 if (FP_REG_P (operands[1]))
1631 return \"f%$move%.x %1,%0\";
1632 return \"f%$move%.d %f1,%0\";
1633 }")
1635 (define_insn ""
1636 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
1637 (float_truncate:SF
1638 (match_operand:DF 1 "general_operand" "f")))]
1639 "TARGET_68881"
1640 "fmove%.s %f1,%0")
1641 \f
1642 ;; Conversion between fixed point and floating point.
1643 ;; Note that among the fix-to-float insns
1644 ;; the ones that start with SImode come first.
1645 ;; That is so that an operand that is a CONST_INT
1646 ;; (and therefore lacks a specific machine mode).
1647 ;; will be recognized as SImode (which is always valid)
1648 ;; rather than as QImode or HImode.
1650 (define_expand "floatsisf2"
1651 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1652 (float:SF (match_operand:SI 1 "general_operand" "")))]
1653 "TARGET_68881"
1654 "")
1656 (define_insn ""
1657 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1658 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1659 "TARGET_68881"
1660 "f%$move%.l %1,%0")
1662 (define_expand "floatsidf2"
1663 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1664 (float:DF (match_operand:SI 1 "general_operand" "")))]
1665 "TARGET_68881"
1666 "")
1668 (define_insn ""
1669 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1670 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1671 "TARGET_68881"
1672 "f%&move%.l %1,%0")
1674 (define_insn "floathisf2"
1675 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1676 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1677 "TARGET_68881"
1678 "f%$move%.w %1,%0")
1680 (define_insn "floathidf2"
1681 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1682 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1683 "TARGET_68881"
1684 "fmove%.w %1,%0")
1686 (define_insn "floatqisf2"
1687 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1688 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1689 "TARGET_68881"
1690 "fmove%.b %1,%0")
1692 (define_insn "floatqidf2"
1693 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1694 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1695 "TARGET_68881"
1696 "f%&move%.b %1,%0")
1698 ;; New routines to convert floating-point values to integers
1699 ;; to be used on the '040. These should be faster than trapping
1700 ;; into the kernel to emulate fintrz. They should also be faster
1701 ;; than calling the subroutines fixsfsi or fixdfsi.
1703 (define_insn "fix_truncdfsi2"
1704 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1705 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1706 (clobber (match_scratch:SI 2 "=d"))
1707 (clobber (match_scratch:SI 3 "=d"))]
1708 "TARGET_68881 && TARGET_68040"
1709 "*
1710 {
1711 CC_STATUS_INIT;
1712 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1713 }")
1715 (define_insn "fix_truncdfhi2"
1716 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1717 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1718 (clobber (match_scratch:SI 2 "=d"))
1719 (clobber (match_scratch:SI 3 "=d"))]
1720 "TARGET_68881 && TARGET_68040"
1721 "*
1722 {
1723 CC_STATUS_INIT;
1724 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1725 }")
1727 (define_insn "fix_truncdfqi2"
1728 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1729 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1730 (clobber (match_scratch:SI 2 "=d"))
1731 (clobber (match_scratch:SI 3 "=d"))]
1732 "TARGET_68881 && TARGET_68040"
1733 "*
1734 {
1735 CC_STATUS_INIT;
1736 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1737 }")
1739 ;; Convert a float to a float whose value is an integer.
1740 ;; This is the first stage of converting it to an integer type.
1742 (define_insn "ftruncdf2"
1743 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1744 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1745 "TARGET_68881 && !TARGET_68040"
1746 "*
1747 {
1748 if (FP_REG_P (operands[1]))
1749 return \"fintrz%.x %f1,%0\";
1750 return \"fintrz%.d %f1,%0\";
1751 }")
1753 (define_insn "ftruncsf2"
1754 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1755 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1756 "TARGET_68881 && !TARGET_68040"
1757 "*
1758 {
1759 if (FP_REG_P (operands[1]))
1760 return \"fintrz%.x %f1,%0\";
1761 return \"fintrz%.s %f1,%0\";
1762 }")
1764 ;; Convert a float whose value is an integer
1765 ;; to an actual integer. Second stage of converting float to integer type.
1766 (define_insn "fixsfqi2"
1767 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1768 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1769 "TARGET_68881"
1770 "fmove%.b %1,%0")
1772 (define_insn "fixsfhi2"
1773 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1774 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1775 "TARGET_68881"
1776 "fmove%.w %1,%0")
1778 (define_insn "fixsfsi2"
1779 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1780 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1781 "TARGET_68881"
1782 "fmove%.l %1,%0")
1784 (define_insn "fixdfqi2"
1785 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1786 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1787 "TARGET_68881"
1788 "fmove%.b %1,%0")
1790 (define_insn "fixdfhi2"
1791 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1792 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1793 "TARGET_68881"
1794 "fmove%.w %1,%0")
1796 (define_insn "fixdfsi2"
1797 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1798 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1799 "TARGET_68881"
1800 "fmove%.l %1,%0")
1801 \f
1802 ;; add instructions
1804 (define_insn "adddi_lshrdi_63"
1805 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1806 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1807 (const_int 63))
1808 (match_dup 1)))
1809 (clobber (match_scratch:SI 2 "=d"))]
1810 ""
1811 "*
1812 {
1813 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1814 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1815 return
1816 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1817 if (GET_CODE (operands[1]) == REG)
1818 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1819 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1820 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1821 operands[4] = operands[1];
1822 else
1823 operands[4] = adjust_address (operands[1], SImode, 4);
1824 if (GET_CODE (operands[1]) == MEM
1825 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1826 output_asm_insn (\"move%.l %4,%3\", operands);
1827 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1828 if (TARGET_68020 || TARGET_COLDFIRE)
1829 output_asm_insn (\"extb%.l %2\", operands);
1830 else
1831 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1832 if (GET_CODE (operands[1]) != MEM
1833 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1834 output_asm_insn (\"move%.l %4,%3\", operands);
1835 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1836 }")
1838 (define_insn "adddi_sexthishl32"
1839 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
1840 (plus:DI (ashift:DI (sign_extend:DI
1841 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1842 (const_int 32))
1843 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1844 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1845 "!TARGET_COLDFIRE"
1846 "*
1847 {
1848 CC_STATUS_INIT;
1849 if (ADDRESS_REG_P (operands[0]))
1850 return \"add%.w %1,%0\";
1851 else if (ADDRESS_REG_P (operands[3]))
1852 return \"move%.w %1,%3\;add%.l %3,%0\";
1853 else
1854 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
1855 } ")
1857 (define_insn "adddi_dilshr32"
1858 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
1859 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1860 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1861 ;; (const_int 32))))]
1862 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
1863 (const_int 32))
1864 (match_operand:DI 2 "general_operand" "0,0")))]
1865 ""
1866 "*
1867 {
1868 CC_STATUS_INIT;
1869 if (GET_CODE (operands[0]) == REG)
1870 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1871 else
1872 operands[2] = adjust_address (operands[0], SImode, 4);
1873 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
1874 } ")
1876 (define_insn "adddi_dishl32"
1877 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
1878 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1879 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
1880 ;; (const_int 32))))]
1881 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
1882 (const_int 32))
1883 (match_operand:DI 2 "general_operand" "0,0")))]
1884 ""
1885 "*
1886 {
1887 CC_STATUS_INIT;
1888 if (GET_CODE (operands[1]) == REG)
1889 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1890 else
1891 operands[1] = adjust_address (operands[1], SImode, 4);
1892 return \"add%.l %1,%0\";
1893 } ")
1895 (define_insn "adddi3"
1896 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
1897 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
1898 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
1899 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
1900 ""
1901 "*
1902 {
1903 if (DATA_REG_P (operands[0]))
1904 {
1905 if (DATA_REG_P (operands[2]))
1906 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
1907 else if (GET_CODE (operands[2]) == MEM
1908 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
1909 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
1910 else
1911 {
1912 rtx high, low;
1913 rtx xoperands[2];
1915 if (GET_CODE (operands[2]) == REG)
1916 {
1917 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
1918 high = operands[2];
1919 }
1920 else if (CONSTANT_P (operands[2]))
1921 split_double (operands[2], &high, &low);
1922 else
1923 {
1924 low = adjust_address (operands[2], SImode, 4);
1925 high = operands[2];
1926 }
1928 operands[1] = low, operands[2] = high;
1929 xoperands[0] = operands[3];
1930 if (GET_CODE (operands[1]) == CONST_INT
1931 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1932 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
1933 else
1934 xoperands[1] = operands[2];
1936 output_asm_insn (output_move_simode (xoperands), xoperands);
1937 if (GET_CODE (operands[1]) == CONST_INT)
1938 {
1939 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
1940 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
1941 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1942 {
1943 operands[1] = GEN_INT (-INTVAL (operands[1]));
1944 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
1945 }
1946 }
1947 return \"add%.l %1,%R0\;addx%.l %3,%0\";
1948 }
1949 }
1950 else if (GET_CODE (operands[0]) == MEM)
1951 {
1952 if (GET_CODE (operands[2]) == MEM
1953 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
1954 return \"add%.l %2,%0\;addx%.l %2,%0\";
1955 CC_STATUS_INIT;
1956 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1957 {
1958 operands[1] = gen_rtx_MEM (SImode,
1959 plus_constant (XEXP(operands[0], 0), -8));
1960 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
1961 }
1962 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1963 {
1964 operands[1] = XEXP(operands[0], 0);
1965 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
1966 }
1967 else
1968 {
1969 operands[1] = adjust_address (operands[0], SImode, 4);
1970 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
1971 }
1972 }
1973 else
1974 abort ();
1975 } ")
1977 (define_insn "addsi_lshrsi_31"
1978 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1979 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
1980 (const_int 31))
1981 (match_dup 1)))]
1982 ""
1983 "*
1984 {
1985 operands[2] = operands[0];
1986 operands[3] = gen_label_rtx();
1987 if (GET_CODE (operands[0]) == MEM)
1988 {
1989 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1990 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
1991 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1992 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
1993 }
1994 output_asm_insn (\"move%.l %1,%0\", operands);
1995 output_asm_insn (MOTOROLA ? \"jbpl %l3\" : \"jpl %l3\", operands);
1996 output_asm_insn (\"addq%.l %#1,%2\", operands);
1997 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
1998 CODE_LABEL_NUMBER (operands[3]));
1999 return \"\";
2000 }")
2002 (define_expand "addsi3"
2003 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2004 (plus:SI (match_operand:SI 1 "general_operand" "")
2005 (match_operand:SI 2 "general_src_operand" "")))]
2006 ""
2007 "")
2009 ;; Note that the middle two alternatives are near-duplicates
2010 ;; in order to handle insns generated by reload.
2011 ;; This is needed since they are not themselves reloaded,
2012 ;; so commutativity won't apply to them.
2013 (define_insn "*addsi3_internal"
2014 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
2015 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2016 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2019 "! TARGET_COLDFIRE"
2020 "* return output_addsi3 (operands);")
2022 (define_insn "*addsi3_5200"
2023 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
2024 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2025 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2026 "TARGET_COLDFIRE"
2027 "* return output_addsi3 (operands);")
2029 (define_insn ""
2030 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2031 (plus:SI (match_operand:SI 1 "general_operand" "0")
2032 (sign_extend:SI
2033 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2034 "!TARGET_COLDFIRE"
2035 "add%.w %2,%0")
2037 (define_insn "addhi3"
2038 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2039 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2040 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2041 "!TARGET_COLDFIRE"
2042 "*
2043 {
2044 if (GET_CODE (operands[2]) == CONST_INT)
2045 {
2046 /* If the constant would be a negative number when interpreted as
2047 HImode, make it negative. This is usually, but not always, done
2048 elsewhere in the compiler. First check for constants out of range,
2049 which could confuse us. */
2051 if (INTVAL (operands[2]) >= 32768)
2052 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2054 if (INTVAL (operands[2]) > 0
2055 && INTVAL (operands[2]) <= 8)
2056 return \"addq%.w %2,%0\";
2057 if (INTVAL (operands[2]) < 0
2058 && INTVAL (operands[2]) >= -8)
2059 {
2060 operands[2] = GEN_INT (- INTVAL (operands[2]));
2061 return \"subq%.w %2,%0\";
2062 }
2063 /* On the CPU32 it is faster to use two addqw instructions to
2064 add a small integer (8 < N <= 16) to a register.
2065 Likewise for subqw. */
2066 if (TARGET_CPU32 && REG_P (operands[0]))
2067 {
2068 if (INTVAL (operands[2]) > 8
2069 && INTVAL (operands[2]) <= 16)
2070 {
2071 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2072 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2073 }
2074 if (INTVAL (operands[2]) < -8
2075 && INTVAL (operands[2]) >= -16)
2076 {
2077 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2078 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2079 }
2080 }
2081 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2082 return MOTOROLA ? \"lea (%c2,%0),%0\" : \"lea %0@(%c2),%0\";
2083 }
2084 return \"add%.w %2,%0\";
2085 }")
2087 ;; These insns must use MATCH_DUP instead of the more expected
2088 ;; use of a matching constraint because the "output" here is also
2089 ;; an input, so you can't use the matching constraint. That also means
2090 ;; that you can't use the "%", so you need patterns with the matched
2091 ;; operand in both positions.
2093 (define_insn ""
2094 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2095 (plus:HI (match_dup 0)
2096 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2097 "!TARGET_COLDFIRE"
2098 "*
2099 {
2100 if (GET_CODE (operands[1]) == CONST_INT)
2101 {
2102 /* If the constant would be a negative number when interpreted as
2103 HImode, make it negative. This is usually, but not always, done
2104 elsewhere in the compiler. First check for constants out of range,
2105 which could confuse us. */
2107 if (INTVAL (operands[1]) >= 32768)
2108 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2110 if (INTVAL (operands[1]) > 0
2111 && INTVAL (operands[1]) <= 8)
2112 return \"addq%.w %1,%0\";
2113 if (INTVAL (operands[1]) < 0
2114 && INTVAL (operands[1]) >= -8)
2115 {
2116 operands[1] = GEN_INT (- INTVAL (operands[1]));
2117 return \"subq%.w %1,%0\";
2118 }
2119 /* On the CPU32 it is faster to use two addqw instructions to
2120 add a small integer (8 < N <= 16) to a register.
2121 Likewise for subqw. */
2122 if (TARGET_CPU32 && REG_P (operands[0]))
2123 {
2124 if (INTVAL (operands[1]) > 8
2125 && INTVAL (operands[1]) <= 16)
2126 {
2127 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2128 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2129 }
2130 if (INTVAL (operands[1]) < -8
2131 && INTVAL (operands[1]) >= -16)
2132 {
2133 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2134 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2135 }
2136 }
2137 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2138 return MOTOROLA ? \"lea (%c1,%0),%0\" : \"lea %0@(%c1),%0\";
2139 }
2140 return \"add%.w %1,%0\";
2141 }")
2143 (define_insn ""
2144 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2145 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2146 (match_dup 0)))]
2147 "!TARGET_COLDFIRE"
2148 "*
2149 {
2150 if (GET_CODE (operands[1]) == CONST_INT)
2151 {
2152 /* If the constant would be a negative number when interpreted as
2153 HImode, make it negative. This is usually, but not always, done
2154 elsewhere in the compiler. First check for constants out of range,
2155 which could confuse us. */
2157 if (INTVAL (operands[1]) >= 32768)
2158 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2160 if (INTVAL (operands[1]) > 0
2161 && INTVAL (operands[1]) <= 8)
2162 return \"addq%.w %1,%0\";
2163 if (INTVAL (operands[1]) < 0
2164 && INTVAL (operands[1]) >= -8)
2165 {
2166 operands[1] = GEN_INT (- INTVAL (operands[1]));
2167 return \"subq%.w %1,%0\";
2168 }
2169 /* On the CPU32 it is faster to use two addqw instructions to
2170 add a small integer (8 < N <= 16) to a register.
2171 Likewise for subqw. */
2172 if (TARGET_CPU32 && REG_P (operands[0]))
2173 {
2174 if (INTVAL (operands[1]) > 8
2175 && INTVAL (operands[1]) <= 16)
2176 {
2177 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2178 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2179 }
2180 if (INTVAL (operands[1]) < -8
2181 && INTVAL (operands[1]) >= -16)
2182 {
2183 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2184 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2185 }
2186 }
2187 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2188 return MOTOROLA ? \"lea (%c1,%0),%0\" : \"lea %0@(%c1),%0\";
2189 }
2190 return \"add%.w %1,%0\";
2191 }")
2193 (define_insn "addqi3"
2194 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2195 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2196 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2197 "!TARGET_COLDFIRE"
2198 "*
2199 {
2200 if (GET_CODE (operands[2]) == CONST_INT)
2201 {
2202 if (INTVAL (operands[2]) >= 128)
2203 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2205 if (INTVAL (operands[2]) > 0
2206 && INTVAL (operands[2]) <= 8)
2207 return \"addq%.b %2,%0\";
2208 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2209 {
2210 operands[2] = GEN_INT (- INTVAL (operands[2]));
2211 return \"subq%.b %2,%0\";
2212 }
2213 }
2214 return \"add%.b %2,%0\";
2215 }")
2217 (define_insn ""
2218 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2219 (plus:QI (match_dup 0)
2220 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2221 "!TARGET_COLDFIRE"
2222 "*
2223 {
2224 if (GET_CODE (operands[1]) == CONST_INT)
2225 {
2226 if (INTVAL (operands[1]) >= 128)
2227 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2229 if (INTVAL (operands[1]) > 0
2230 && INTVAL (operands[1]) <= 8)
2231 return \"addq%.b %1,%0\";
2232 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2233 {
2234 operands[1] = GEN_INT (- INTVAL (operands[1]));
2235 return \"subq%.b %1,%0\";
2236 }
2237 }
2238 return \"add%.b %1,%0\";
2239 }")
2241 (define_insn ""
2242 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2243 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2244 (match_dup 0)))]
2245 "!TARGET_COLDFIRE"
2246 "*
2247 {
2248 if (GET_CODE (operands[1]) == CONST_INT)
2249 {
2250 if (INTVAL (operands[1]) >= 128)
2251 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2253 if (INTVAL (operands[1]) > 0
2254 && INTVAL (operands[1]) <= 8)
2255 return \"addq%.b %1,%0\";
2256 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2257 {
2258 operands[1] = GEN_INT (- INTVAL (operands[1]));
2259 return \"subq%.b %1,%0\";
2260 }
2261 }
2262 return \"add%.b %1,%0\";
2263 }")
2265 (define_expand "adddf3"
2266 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2267 (plus:DF (match_operand:DF 1 "general_operand" "")
2268 (match_operand:DF 2 "general_operand" "")))]
2269 "TARGET_68881"
2270 "")
2272 (define_insn ""
2273 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2274 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2275 (match_operand:DF 1 "general_operand" "0")))]
2276 "TARGET_68881"
2277 "f%&add%.l %2,%0")
2279 (define_insn ""
2280 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2281 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2282 (match_operand:DF 1 "general_operand" "0")))]
2283 "TARGET_68881"
2284 "f%&add%.w %2,%0")
2286 (define_insn ""
2287 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2288 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2289 (match_operand:DF 1 "general_operand" "0")))]
2290 "TARGET_68881"
2291 "f%&add%.b %2,%0")
2293 (define_insn ""
2294 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2295 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2296 (match_operand:DF 2 "general_operand" "fmG")))]
2297 "TARGET_68881"
2298 "*
2299 {
2300 if (REG_P (operands[2]))
2301 return \"f%&add%.x %2,%0\";
2302 return \"f%&add%.d %f2,%0\";
2303 }")
2305 (define_expand "addsf3"
2306 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2307 (plus:SF (match_operand:SF 1 "general_operand" "")
2308 (match_operand:SF 2 "general_operand" "")))]
2309 "TARGET_68881"
2310 "")
2312 (define_insn ""
2313 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2314 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2315 (match_operand:SF 1 "general_operand" "0")))]
2316 "TARGET_68881"
2317 "f%$add%.l %2,%0")
2319 (define_insn ""
2320 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2321 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2322 (match_operand:SF 1 "general_operand" "0")))]
2323 "TARGET_68881"
2324 "f%$add%.w %2,%0")
2326 (define_insn ""
2327 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2328 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2329 (match_operand:SF 1 "general_operand" "0")))]
2330 "TARGET_68881"
2331 "f%$add%.b %2,%0")
2333 (define_insn ""
2334 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2335 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2336 (match_operand:SF 2 "general_operand" "fdmF")))]
2337 "TARGET_68881"
2338 "*
2339 {
2340 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2341 return \"f%$add%.x %2,%0\";
2342 return \"f%$add%.s %f2,%0\";
2343 }")
2344 \f
2345 ;; subtract instructions
2347 (define_insn "subdi_sexthishl32"
2348 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2349 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2350 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2351 (const_int 32))))
2352 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2353 "!TARGET_COLDFIRE"
2354 "*
2355 {
2356 CC_STATUS_INIT;
2357 if (ADDRESS_REG_P (operands[0]))
2358 return \"sub%.w %2,%0\";
2359 else if (ADDRESS_REG_P (operands[3]))
2360 return \"move%.w %2,%3\;sub%.l %3,%0\";
2361 else
2362 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2363 } ")
2365 (define_insn "subdi_dishl32"
2366 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2367 (minus:DI (match_dup 0)
2368 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2369 (const_int 32))))]
2370 ""
2371 "*
2372 {
2373 CC_STATUS_INIT;
2374 if (GET_CODE (operands[1]) == REG)
2375 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2376 else
2377 operands[1] = adjust_address (operands[1], SImode, 4);
2378 return \"sub%.l %1,%0\";
2379 } ")
2381 (define_insn "subdi3"
2382 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
2383 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2384 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2385 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2386 ""
2387 "*
2388 {
2389 if (DATA_REG_P (operands[0]))
2390 {
2391 if (DATA_REG_P (operands[2]))
2392 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2393 else if (GET_CODE (operands[2]) == MEM
2394 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2395 {
2396 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2397 }
2398 else
2399 {
2400 rtx high, low;
2401 rtx xoperands[2];
2403 if (GET_CODE (operands[2]) == REG)
2404 {
2405 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2406 high = operands[2];
2407 }
2408 else if (CONSTANT_P (operands[2]))
2409 split_double (operands[2], &high, &low);
2410 else
2411 {
2412 low = adjust_address (operands[2], SImode, 4);
2413 high = operands[2];
2414 }
2416 operands[1] = low, operands[2] = high;
2417 xoperands[0] = operands[3];
2418 if (GET_CODE (operands[1]) == CONST_INT
2419 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2420 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2421 else
2422 xoperands[1] = operands[2];
2424 output_asm_insn (output_move_simode (xoperands), xoperands);
2425 if (GET_CODE (operands[1]) == CONST_INT)
2426 {
2427 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2428 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2429 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2430 {
2431 operands[1] = GEN_INT (-INTVAL (operands[1]));
2432 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2433 }
2434 }
2435 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2436 }
2437 }
2438 else if (GET_CODE (operands[0]) == MEM)
2439 {
2440 if (GET_CODE (operands[2]) == MEM
2441 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2442 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2443 CC_STATUS_INIT;
2444 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2445 {
2446 operands[1]
2447 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2448 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2449 }
2450 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2451 {
2452 operands[1] = XEXP(operands[0], 0);
2453 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2454 }
2455 else
2456 {
2457 operands[1] = adjust_address (operands[0], SImode, 4);
2458 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2459 }
2460 }
2461 else
2462 abort ();
2463 } ")
2465 (define_insn "subsi3"
2466 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d,a")
2467 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2468 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2469 ""
2470 "sub%.l %2,%0")
2472 (define_insn ""
2473 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2474 (minus:SI (match_operand:SI 1 "general_operand" "0")
2475 (sign_extend:SI
2476 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2477 "!TARGET_COLDFIRE"
2478 "sub%.w %2,%0")
2480 (define_insn "subhi3"
2481 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2482 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2483 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2484 "!TARGET_COLDFIRE"
2485 "sub%.w %2,%0")
2487 (define_insn ""
2488 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2489 (minus:HI (match_dup 0)
2490 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2491 "!TARGET_COLDFIRE"
2492 "sub%.w %1,%0")
2494 (define_insn "subqi3"
2495 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2496 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2497 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2498 "!TARGET_COLDFIRE"
2499 "sub%.b %2,%0")
2501 (define_insn ""
2502 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2503 (minus:QI (match_dup 0)
2504 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2505 "!TARGET_COLDFIRE"
2506 "sub%.b %1,%0")
2508 (define_expand "subdf3"
2509 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2510 (minus:DF (match_operand:DF 1 "general_operand" "")
2511 (match_operand:DF 2 "general_operand" "")))]
2512 "TARGET_68881"
2513 "")
2515 (define_insn ""
2516 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2517 (minus:DF (match_operand:DF 1 "general_operand" "0")
2518 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2519 "TARGET_68881"
2520 "f%&sub%.l %2,%0")
2522 (define_insn ""
2523 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2524 (minus:DF (match_operand:DF 1 "general_operand" "0")
2525 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2526 "TARGET_68881"
2527 "f%&sub%.w %2,%0")
2529 (define_insn ""
2530 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2531 (minus:DF (match_operand:DF 1 "general_operand" "0")
2532 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2533 "TARGET_68881"
2534 "f%&sub%.b %2,%0")
2536 (define_insn ""
2537 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2538 (minus:DF (match_operand:DF 1 "general_operand" "0")
2539 (match_operand:DF 2 "general_operand" "fmG")))]
2540 "TARGET_68881"
2541 "*
2542 {
2543 if (REG_P (operands[2]))
2544 return \"f%&sub%.x %2,%0\";
2545 return \"f%&sub%.d %f2,%0\";
2546 }")
2548 (define_expand "subsf3"
2549 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2550 (minus:SF (match_operand:SF 1 "general_operand" "")
2551 (match_operand:SF 2 "general_operand" "")))]
2552 "TARGET_68881"
2553 "")
2555 (define_insn ""
2556 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2557 (minus:SF (match_operand:SF 1 "general_operand" "0")
2558 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2559 "TARGET_68881"
2560 "f%$sub%.l %2,%0")
2562 (define_insn ""
2563 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2564 (minus:SF (match_operand:SF 1 "general_operand" "0")
2565 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2566 "TARGET_68881"
2567 "f%$sub%.w %2,%0")
2569 (define_insn ""
2570 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2571 (minus:SF (match_operand:SF 1 "general_operand" "0")
2572 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2573 "TARGET_68881"
2574 "f%$sub%.b %2,%0")
2576 (define_insn ""
2577 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2578 (minus:SF (match_operand:SF 1 "general_operand" "0")
2579 (match_operand:SF 2 "general_operand" "fdmF")))]
2580 "TARGET_68881"
2581 "*
2582 {
2583 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2584 return \"f%$sub%.x %2,%0\";
2585 return \"f%$sub%.s %f2,%0\";
2586 }")
2587 \f
2588 ;; multiply instructions
2590 (define_insn "mulhi3"
2591 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
2592 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2593 (match_operand:HI 2 "general_src_operand" "dmSn")))]
2594 ""
2595 "*
2596 {
2597 return MOTOROLA ? \"muls%.w %2,%0\" : \"muls %2,%0\";
2598 }")
2600 (define_insn "mulhisi3"
2601 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2602 (mult:SI (sign_extend:SI
2603 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2604 (sign_extend:SI
2605 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2606 ""
2607 "*
2608 {
2609 return MOTOROLA ? \"muls%.w %2,%0\" : \"muls %2,%0\";
2610 }")
2612 (define_insn ""
2613 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2614 (mult:SI (sign_extend:SI
2615 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2616 (match_operand:SI 2 "const_int_operand" "n")))]
2617 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2618 "*
2619 {
2620 return MOTOROLA ? \"muls%.w %2,%0\" : \"muls %2,%0\";
2621 }")
2623 (define_expand "mulsi3"
2624 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2625 (mult:SI (match_operand:SI 1 "general_operand" "")
2626 (match_operand:SI 2 "general_operand" "")))]
2627 "TARGET_68020 || TARGET_COLDFIRE"
2628 "")
2630 (define_insn ""
2631 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2632 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2633 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
2635 "TARGET_68020"
2636 "muls%.l %2,%0")
2638 (define_insn ""
2639 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2640 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2641 (match_operand:SI 2 "general_operand" "d<Q>")))]
2642 "TARGET_COLDFIRE"
2643 "muls%.l %2,%0")
2645 (define_insn "umulhisi3"
2646 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2647 (mult:SI (zero_extend:SI
2648 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2649 (zero_extend:SI
2650 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2651 ""
2652 "*
2653 {
2654 return MOTOROLA ? \"mulu%.w %2,%0\" : \"mulu %2,%0\";
2655 }")
2657 (define_insn ""
2658 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2659 (mult:SI (zero_extend:SI
2660 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2661 (match_operand:SI 2 "const_int_operand" "n")))]
2662 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2663 "*
2664 {
2665 return MOTOROLA ? \"mulu%.w %2,%0\" : \"mulu %2,%0\";
2666 }")
2668 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2669 ;; proper matching constraint. This is because the matching is between
2670 ;; the high-numbered word of the DImode operand[0] and operand[1].
2671 (define_expand "umulsidi3"
2672 [(parallel
2673 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2674 (mult:SI (match_operand:SI 1 "register_operand" "")
2675 (match_operand:SI 2 "register_operand" "")))
2676 (set (subreg:SI (match_dup 0) 0)
2677 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2678 (zero_extend:DI (match_dup 2)))
2679 (const_int 32))))])]
2680 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2681 "")
2683 (define_insn ""
2684 [(set (match_operand:SI 0 "register_operand" "=d")
2685 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2686 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2687 (set (match_operand:SI 3 "register_operand" "=d")
2688 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2689 (zero_extend:DI (match_dup 2)))
2690 (const_int 32))))]
2691 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2692 "mulu%.l %2,%3:%0")
2694 ; Match immediate case. For 2.4 only match things < 2^31.
2695 ; It's tricky with larger values in these patterns since we need to match
2696 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2697 ; a CONST_INT.
2698 (define_insn ""
2699 [(set (match_operand:SI 0 "register_operand" "=d")
2700 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2701 (match_operand:SI 2 "const_int_operand" "n")))
2702 (set (match_operand:SI 3 "register_operand" "=d")
2703 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2704 (match_dup 2))
2705 (const_int 32))))]
2706 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE
2707 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2708 "mulu%.l %2,%3:%0")
2710 (define_expand "mulsidi3"
2711 [(parallel
2712 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2713 (mult:SI (match_operand:SI 1 "register_operand" "")
2714 (match_operand:SI 2 "register_operand" "")))
2715 (set (subreg:SI (match_dup 0) 0)
2716 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2717 (sign_extend:DI (match_dup 2)))
2718 (const_int 32))))])]
2719 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2720 "")
2722 (define_insn ""
2723 [(set (match_operand:SI 0 "register_operand" "=d")
2724 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2725 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2726 (set (match_operand:SI 3 "register_operand" "=d")
2727 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2728 (sign_extend:DI (match_dup 2)))
2729 (const_int 32))))]
2730 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2731 "muls%.l %2,%3:%0")
2733 (define_insn ""
2734 [(set (match_operand:SI 0 "register_operand" "=d")
2735 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2736 (match_operand:SI 2 "const_int_operand" "n")))
2737 (set (match_operand:SI 3 "register_operand" "=d")
2738 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2739 (match_dup 2))
2740 (const_int 32))))]
2741 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2742 "muls%.l %2,%3:%0")
2744 (define_expand "umulsi3_highpart"
2745 [(parallel
2746 [(set (match_operand:SI 0 "register_operand" "")
2747 (truncate:SI
2748 (lshiftrt:DI
2749 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2750 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2751 (const_int 32))))
2752 (clobber (match_dup 3))])]
2753 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2754 "
2755 {
2756 operands[3] = gen_reg_rtx (SImode);
2758 if (GET_CODE (operands[2]) == CONST_INT)
2759 {
2760 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
2761 0, DImode);
2763 /* We have to adjust the operand order for the matching constraints. */
2764 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2765 operands[1], operands[2]));
2766 DONE;
2767 }
2768 }")
2770 (define_insn ""
2771 [(set (match_operand:SI 0 "register_operand" "=d")
2772 (truncate:SI
2773 (lshiftrt:DI
2774 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2775 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2776 (const_int 32))))
2777 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2778 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2779 "mulu%.l %3,%0:%1")
2781 (define_insn "const_umulsi3_highpart"
2782 [(set (match_operand:SI 0 "register_operand" "=d")
2783 (truncate:SI
2784 (lshiftrt:DI
2785 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
2786 (match_operand:DI 3 "const_uint32_operand" "n"))
2787 (const_int 32))))
2788 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2789 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2790 "mulu%.l %3,%0:%1")
2792 (define_expand "smulsi3_highpart"
2793 [(parallel
2794 [(set (match_operand:SI 0 "register_operand" "")
2795 (truncate:SI
2796 (lshiftrt:DI
2797 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
2798 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
2799 (const_int 32))))
2800 (clobber (match_dup 3))])]
2801 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2802 "
2803 {
2804 operands[3] = gen_reg_rtx (SImode);
2805 if (GET_CODE (operands[2]) == CONST_INT)
2806 {
2807 /* We have to adjust the operand order for the matching constraints. */
2808 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
2809 operands[1], operands[2]));
2810 DONE;
2811 }
2812 }")
2814 (define_insn ""
2815 [(set (match_operand:SI 0 "register_operand" "=d")
2816 (truncate:SI
2817 (lshiftrt:DI
2818 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2819 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2820 (const_int 32))))
2821 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2822 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2823 "muls%.l %3,%0:%1")
2825 (define_insn "const_smulsi3_highpart"
2826 [(set (match_operand:SI 0 "register_operand" "=d")
2827 (truncate:SI
2828 (lshiftrt:DI
2829 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
2830 (match_operand:DI 3 "const_sint32_operand" "n"))
2831 (const_int 32))))
2832 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2833 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2834 "muls%.l %3,%0:%1")
2836 (define_expand "muldf3"
2837 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2838 (mult:DF (match_operand:DF 1 "general_operand" "")
2839 (match_operand:DF 2 "general_operand" "")))]
2840 "TARGET_68881"
2841 "")
2843 (define_insn ""
2844 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2845 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2846 (match_operand:DF 1 "general_operand" "0")))]
2847 "TARGET_68881"
2848 "f%&mul%.l %2,%0")
2850 (define_insn ""
2851 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2852 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2853 (match_operand:DF 1 "general_operand" "0")))]
2854 "TARGET_68881"
2855 "f%&mul%.w %2,%0")
2857 (define_insn ""
2858 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2859 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2860 (match_operand:DF 1 "general_operand" "0")))]
2861 "TARGET_68881"
2862 "f%&mul%.b %2,%0")
2864 (define_insn ""
2865 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2866 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2867 (match_operand:DF 2 "general_operand" "fmG")))]
2868 "TARGET_68881"
2869 "*
2870 {
2871 if (GET_CODE (operands[2]) == CONST_DOUBLE
2872 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
2873 {
2874 int i = floating_exact_log2 (operands[2]);
2875 operands[2] = GEN_INT (i);
2876 return \"fscale%.l %2,%0\";
2877 }
2878 if (REG_P (operands[2]))
2879 return \"f%&mul%.x %2,%0\";
2880 return \"f%&mul%.d %f2,%0\";
2881 }")
2883 (define_expand "mulsf3"
2884 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2885 (mult:SF (match_operand:SF 1 "general_operand" "")
2886 (match_operand:SF 2 "general_operand" "")))]
2887 "TARGET_68881"
2888 "")
2890 (define_insn ""
2891 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2892 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2893 (match_operand:SF 1 "general_operand" "0")))]
2894 "TARGET_68881"
2895 "*
2896 {
2897 return (TARGET_68040_ONLY
2898 ? \"fsmul%.l %2,%0\"
2899 : \"fsglmul%.l %2,%0\");
2900 }")
2902 (define_insn ""
2903 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2904 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2905 (match_operand:SF 1 "general_operand" "0")))]
2906 "TARGET_68881"
2907 "*
2908 {
2909 return (TARGET_68040_ONLY
2910 ? \"fsmul%.w %2,%0\"
2911 : \"fsglmul%.w %2,%0\");
2912 }")
2914 (define_insn ""
2915 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2916 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2917 (match_operand:SF 1 "general_operand" "0")))]
2918 "TARGET_68881"
2919 "*
2920 {
2921 return (TARGET_68040_ONLY
2922 ? \"fsmul%.b %2,%0\"
2923 : \"fsglmul%.b %2,%0\");
2924 }")
2926 (define_insn ""
2927 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2928 (mult:SF (match_operand:SF 1 "general_operand" "%0")
2929 (match_operand:SF 2 "general_operand" "fdmF")))]
2930 "TARGET_68881"
2931 "*
2932 {
2933 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2934 return (TARGET_68040_ONLY
2935 ? \"fsmul%.x %2,%0\"
2936 : \"fsglmul%.x %2,%0\");
2937 return (TARGET_68040_ONLY
2938 ? \"fsmul%.s %f2,%0\"
2939 : \"fsglmul%.s %f2,%0\");
2940 }")
2941 \f
2942 ;; divide instructions
2944 (define_expand "divdf3"
2945 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2946 (div:DF (match_operand:DF 1 "general_operand" "")
2947 (match_operand:DF 2 "general_operand" "")))]
2948 "TARGET_68881"
2949 "")
2951 (define_insn ""
2952 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2953 (div:DF (match_operand:DF 1 "general_operand" "0")
2954 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2955 "TARGET_68881"
2956 "f%&div%.l %2,%0")
2958 (define_insn ""
2959 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2960 (div:DF (match_operand:DF 1 "general_operand" "0")
2961 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2962 "TARGET_68881"
2963 "f%&div%.w %2,%0")
2965 (define_insn ""
2966 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2967 (div:DF (match_operand:DF 1 "general_operand" "0")
2968 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2969 "TARGET_68881"
2970 "f%&div%.b %2,%0")
2972 (define_insn ""
2973 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2974 (div:DF (match_operand:DF 1 "general_operand" "0")
2975 (match_operand:DF 2 "general_operand" "fmG")))]
2976 "TARGET_68881"
2977 "*
2978 {
2979 if (REG_P (operands[2]))
2980 return \"f%&div%.x %2,%0\";
2981 return \"f%&div%.d %f2,%0\";
2982 }")
2984 (define_expand "divsf3"
2985 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2986 (div:SF (match_operand:SF 1 "general_operand" "")
2987 (match_operand:SF 2 "general_operand" "")))]
2988 "TARGET_68881"
2989 "")
2991 (define_insn ""
2992 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2993 (div:SF (match_operand:SF 1 "general_operand" "0")
2994 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2995 "TARGET_68881"
2996 "*
2997 {
2998 return (TARGET_68040_ONLY
2999 ? \"fsdiv%.l %2,%0\"
3000 : \"fsgldiv%.l %2,%0\");
3001 }")
3003 (define_insn ""
3004 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3005 (div:SF (match_operand:SF 1 "general_operand" "0")
3006 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3007 "TARGET_68881"
3008 "*
3009 {
3010 return (TARGET_68040_ONLY
3011 ? \"fsdiv%.w %2,%0\"
3012 : \"fsgldiv%.w %2,%0\");
3013 }")
3015 (define_insn ""
3016 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3017 (div:SF (match_operand:SF 1 "general_operand" "0")
3018 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3019 "TARGET_68881"
3020 "*
3021 {
3022 return (TARGET_68040_ONLY
3023 ? \"fsdiv%.b %2,%0\"
3024 : \"fsgldiv%.b %2,%0\");
3025 }")
3027 (define_insn ""
3028 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3029 (div:SF (match_operand:SF 1 "general_operand" "0")
3030 (match_operand:SF 2 "general_operand" "fdmF")))]
3031 "TARGET_68881"
3032 "*
3033 {
3034 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3035 return (TARGET_68040_ONLY
3036 ? \"fsdiv%.x %2,%0\"
3037 : \"fsgldiv%.x %2,%0\");
3038 return (TARGET_68040_ONLY
3039 ? \"fsdiv%.s %f2,%0\"
3040 : \"fsgldiv%.s %f2,%0\");
3041 }")
3042 \f
3043 ;; Remainder instructions.
3045 (define_expand "divmodsi4"
3046 [(parallel
3047 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3048 (div:SI (match_operand:SI 1 "general_operand" "")
3049 (match_operand:SI 2 "general_src_operand" "")))
3050 (set (match_operand:SI 3 "nonimmediate_operand" "")
3051 (mod:SI (match_dup 1) (match_dup 2)))])]
3052 "TARGET_68020 || TARGET_CF_HWDIV"
3053 "")
3055 (define_insn ""
3056 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3057 (div:SI (match_operand:SI 1 "general_operand" "0")
3058 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3059 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3060 (mod:SI (match_dup 1) (match_dup 2)))]
3061 "TARGET_CF_HWDIV"
3062 "*
3063 {
3064 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3065 return \"divs%.l %2,%0\";
3066 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3067 return \"rems%.l %2,%3:%0\";
3068 else
3069 return \"rems%.l %2,%3:%0\;divs%.l %2,%0\";
3070 }")
3072 (define_insn ""
3073 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3074 (div:SI (match_operand:SI 1 "general_operand" "0")
3075 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3076 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3077 (mod:SI (match_dup 1) (match_dup 2)))]
3078 "TARGET_68020"
3079 "*
3080 {
3081 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3082 return \"divs%.l %2,%0\";
3083 else
3084 return \"divsl%.l %2,%3:%0\";
3085 }")
3087 (define_expand "udivmodsi4"
3088 [(parallel
3089 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3090 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3091 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3092 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3093 (umod:SI (match_dup 1) (match_dup 2)))])]
3094 "TARGET_68020 || TARGET_CF_HWDIV"
3095 "")
3097 (define_insn ""
3098 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3099 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3100 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3101 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3102 (umod:SI (match_dup 1) (match_dup 2)))]
3103 "TARGET_CF_HWDIV"
3104 "*
3105 {
3106 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3107 return \"divu%.l %2,%0\";
3108 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3109 return \"remu%.l %2,%3:%0\";
3110 else
3111 return \"remu%.l %2,%3:%0\;divu%.l %2,%0\";
3112 }")
3114 (define_insn ""
3115 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3116 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3117 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3118 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3119 (umod:SI (match_dup 1) (match_dup 2)))]
3120 "TARGET_68020 && !TARGET_COLDFIRE"
3121 "*
3122 {
3123 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3124 return \"divu%.l %2,%0\";
3125 else
3126 return \"divul%.l %2,%3:%0\";
3127 }")
3129 (define_insn "divmodhi4"
3130 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3131 (div:HI (match_operand:HI 1 "general_operand" "0")
3132 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3133 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3134 (mod:HI (match_dup 1) (match_dup 2)))]
3135 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3136 "*
3137 {
3138 output_asm_insn (MOTOROLA ?
3139 \"ext%.l %0\;divs%.w %2,%0\" :
3140 \"extl %0\;divs %2,%0\",
3141 operands);
3142 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3143 {
3144 CC_STATUS_INIT;
3145 return \"move%.l %0,%3\;swap %3\";
3146 }
3147 else
3148 return \"\";
3149 }")
3151 (define_insn "udivmodhi4"
3152 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3153 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3154 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3155 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3156 (umod:HI (match_dup 1) (match_dup 2)))]
3157 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3158 "*
3159 {
3160 output_asm_insn (MOTOROLA ?
3161 \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\" :
3162 \"and%.l %#0xFFFF,%0\;divu %2,%0\",
3163 operands);
3164 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3165 {
3166 CC_STATUS_INIT;
3167 return \"move%.l %0,%3\;swap %3\";
3168 }
3169 else
3170 return \"\";
3171 }")
3172 \f
3173 ;; logical-and instructions
3175 ;; "anddi3" is mainly here to help combine().
3176 (define_insn "anddi3"
3177 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3178 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3179 (match_operand:DI 2 "general_operand" "dn,don")))]
3180 "!TARGET_COLDFIRE"
3181 "*
3182 {
3183 CC_STATUS_INIT;
3184 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3185 if (CONSTANT_P (operands[2]))
3186 {
3187 rtx hi, lo;
3189 split_double (operands[2], &hi, &lo);
3191 switch (INTVAL (hi))
3192 {
3193 case 0 :
3194 output_asm_insn (\"clr%.l %0\", operands);
3195 break;
3196 case -1 :
3197 break;
3198 default :
3199 {
3200 rtx xoperands[3];
3202 xoperands[0] = operands[0];
3203 xoperands[2] = hi;
3204 output_asm_insn (output_andsi3 (xoperands), xoperands);
3205 }
3206 }
3207 if (GET_CODE (operands[0]) == REG)
3208 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3209 else
3210 operands[0] = adjust_address (operands[0], SImode, 4);
3211 switch (INTVAL (lo))
3212 {
3213 case 0 :
3214 output_asm_insn (\"clr%.l %0\", operands);
3215 break;
3216 case -1 :
3217 break;
3218 default :
3219 {
3220 rtx xoperands[3];
3222 xoperands[0] = operands[0];
3223 xoperands[2] = lo;
3224 output_asm_insn (output_andsi3 (xoperands), xoperands);
3225 }
3226 }
3227 return \"\";
3228 }
3229 if (GET_CODE (operands[0]) != REG)
3230 {
3231 operands[1] = adjust_address (operands[0], SImode, 4);
3232 return \"and%.l %2,%0\;and%.l %R2,%1\";
3233 }
3234 if (GET_CODE (operands[2]) != REG)
3235 {
3236 operands[1] = adjust_address (operands[2], SImode, 4);
3237 return \"and%.l %2,%0\;and%.l %1,%R0\";
3238 }
3239 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3240 }")
3242 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3243 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3244 ;; can't allocate pseudos into it.
3246 (define_expand "andsi3"
3247 [(set (match_operand:SI 0 "not_sp_operand" "")
3248 (and:SI (match_operand:SI 1 "general_operand" "")
3249 (match_operand:SI 2 "general_src_operand" "")))]
3250 ""
3251 "")
3253 (define_insn "andsi3_internal"
3254 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3255 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3256 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3257 "!TARGET_COLDFIRE"
3258 "*
3259 {
3260 return output_andsi3 (operands);
3261 }")
3263 (define_insn "andsi3_5200"
3264 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3265 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3266 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3267 "TARGET_COLDFIRE"
3268 "and%.l %2,%0")
3270 (define_insn "andhi3"
3271 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3272 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3273 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3274 "!TARGET_COLDFIRE"
3275 "and%.w %2,%0")
3277 (define_insn ""
3278 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3279 (and:HI (match_dup 0)
3280 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3281 "!TARGET_COLDFIRE"
3282 "and%.w %1,%0")
3284 (define_insn ""
3285 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3286 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3287 (match_dup 0)))]
3288 "!TARGET_COLDFIRE"
3289 "and%.w %1,%0")
3291 (define_insn "andqi3"
3292 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3293 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3294 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3295 "!TARGET_COLDFIRE"
3296 "and%.b %2,%0")
3298 (define_insn ""
3299 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3300 (and:QI (match_dup 0)
3301 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3302 "!TARGET_COLDFIRE"
3303 "and%.b %1,%0")
3305 (define_insn ""
3306 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3307 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3308 (match_dup 0)))]
3309 "!TARGET_COLDFIRE"
3310 "and%.b %1,%0")
3311 \f
3312 ;; inclusive-or instructions
3314 (define_insn "iordi_zext"
3315 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3316 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3317 (match_operand:DI 2 "general_operand" "0,0")))]
3318 "!TARGET_COLDFIRE"
3319 "*
3320 {
3321 int byte_mode;
3323 CC_STATUS_INIT;
3324 if (GET_CODE (operands[0]) == REG)
3325 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3326 else
3327 operands[0] = adjust_address (operands[0], SImode, 4);
3328 if (GET_MODE (operands[1]) == SImode)
3329 return \"or%.l %1,%0\";
3330 byte_mode = (GET_MODE (operands[1]) == QImode);
3331 if (GET_CODE (operands[0]) == MEM)
3332 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3333 byte_mode ? 3 : 2);
3334 if (byte_mode)
3335 return \"or%.b %1,%0\";
3336 else
3337 return \"or%.w %1,%0\";
3338 }")
3340 ;; "iordi3" is mainly here to help combine().
3341 (define_insn "iordi3"
3342 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3343 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3344 (match_operand:DI 2 "general_operand" "dn,don")))]
3345 "!TARGET_COLDFIRE"
3346 "*
3347 {
3348 CC_STATUS_INIT;
3349 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3350 if (CONSTANT_P (operands[2]))
3351 {
3352 rtx hi, lo;
3354 split_double (operands[2], &hi, &lo);
3356 switch (INTVAL (hi))
3357 {
3358 case 0 :
3359 break;
3360 case -1 :
3361 /* FIXME : a scratch register would be welcome here if operand[0]
3362 is not a register */
3363 output_asm_insn (\"move%.l %#-1,%0\", operands);
3364 break;
3365 default :
3366 {
3367 rtx xoperands[3];
3369 xoperands[0] = operands[0];
3370 xoperands[2] = hi;
3371 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3372 }
3373 }
3374 if (GET_CODE (operands[0]) == REG)
3375 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3376 else
3377 operands[0] = adjust_address (operands[0], SImode, 4);
3378 switch (INTVAL (lo))
3379 {
3380 case 0 :
3381 break;
3382 case -1 :
3383 /* FIXME : a scratch register would be welcome here if operand[0]
3384 is not a register */
3385 output_asm_insn (\"move%.l %#-1,%0\", operands);
3386 break;
3387 default :
3388 {
3389 rtx xoperands[3];
3391 xoperands[0] = operands[0];
3392 xoperands[2] = lo;
3393 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3394 }
3395 }
3396 return \"\";
3397 }
3398 if (GET_CODE (operands[0]) != REG)
3399 {
3400 operands[1] = adjust_address (operands[0], SImode, 4);
3401 return \"or%.l %2,%0\;or%.l %R2,%1\";
3402 }
3403 if (GET_CODE (operands[2]) != REG)
3404 {
3405 operands[1] = adjust_address (operands[2], SImode, 4);
3406 return \"or%.l %2,%0\;or%.l %1,%R0\";
3407 }
3408 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3409 }")
3411 (define_expand "iorsi3"
3412 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3413 (ior:SI (match_operand:SI 1 "general_operand" "")
3414 (match_operand:SI 2 "general_src_operand" "")))]
3415 ""
3416 "")
3418 (define_insn "iorsi3_internal"
3419 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3420 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3421 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3422 "! TARGET_COLDFIRE"
3423 "*
3424 {
3425 return output_iorsi3 (operands);
3426 }")
3428 (define_insn "iorsi3_5200"
3429 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3430 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3431 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3432 "TARGET_COLDFIRE"
3433 "or%.l %2,%0")
3435 (define_insn "iorhi3"
3436 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3437 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3438 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3439 "!TARGET_COLDFIRE"
3440 "or%.w %2,%0")
3442 (define_insn ""
3443 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3444 (ior:HI (match_dup 0)
3445 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3446 "!TARGET_COLDFIRE"
3447 "or%.w %1,%0")
3449 (define_insn ""
3450 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3451 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3452 (match_dup 0)))]
3453 "!TARGET_COLDFIRE"
3454 "or%.w %1,%0")
3456 (define_insn "iorqi3"
3457 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3458 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3459 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3460 "!TARGET_COLDFIRE"
3461 "or%.b %2,%0")
3463 (define_insn ""
3464 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3465 (ior:QI (match_dup 0)
3466 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3467 "!TARGET_COLDFIRE"
3468 "or%.b %1,%0")
3470 (define_insn ""
3471 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3472 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3473 (match_dup 0)))]
3474 "!TARGET_COLDFIRE"
3475 "or%.b %1,%0")
3477 ;; On all 68k models, this makes faster code in a special case.
3478 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3480 (define_insn "iorsi_zexthi_ashl16"
3481 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3482 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3483 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3484 (const_int 16))))]
3485 ""
3486 "*
3487 {
3488 CC_STATUS_INIT;
3489 if (GET_CODE (operands[2]) != REG)
3490 operands[2] = adjust_address (operands[2], HImode, 2);
3491 if (GET_CODE (operands[2]) != REG
3492 || REGNO (operands[2]) != REGNO (operands[0]))
3493 output_asm_insn (\"move%.w %2,%0\", operands);
3494 return \"swap %0\;mov%.w %1,%0\";
3495 }")
3497 (define_insn "iorsi_zext"
3498 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3499 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3500 (match_operand:SI 2 "general_operand" "0,0")))]
3501 "!TARGET_COLDFIRE"
3502 "*
3503 {
3504 int byte_mode;
3506 CC_STATUS_INIT;
3507 byte_mode = (GET_MODE (operands[1]) == QImode);
3508 if (GET_CODE (operands[0]) == MEM)
3509 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3510 byte_mode ? 3 : 2);
3511 if (byte_mode)
3512 return \"or%.b %1,%0\";
3513 else
3514 return \"or%.w %1,%0\";
3515 }")
3516 \f
3517 ;; xor instructions
3519 ;; "xordi3" is mainly here to help combine().
3520 (define_insn "xordi3"
3521 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3522 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3523 (match_operand:DI 2 "general_operand" "dn")))]
3524 "!TARGET_COLDFIRE"
3525 "*
3526 {
3527 CC_STATUS_INIT;
3528 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3530 if (CONSTANT_P (operands[2]))
3531 {
3532 rtx hi, lo;
3534 split_double (operands[2], &hi, &lo);
3536 switch (INTVAL (hi))
3537 {
3538 case 0 :
3539 break;
3540 case -1 :
3541 output_asm_insn (\"not%.l %0\", operands);
3542 break;
3543 default :
3544 /* FIXME : a scratch register would be welcome here if
3545 -128 <= INTVAL (hi) < -1 */
3546 {
3547 rtx xoperands[3];
3549 xoperands[0] = operands[0];
3550 xoperands[2] = hi;
3551 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3552 }
3553 }
3554 if (GET_CODE (operands[0]) == REG)
3555 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3556 else
3557 operands[0] = adjust_address (operands[0], SImode, 4);
3558 switch (INTVAL (lo))
3559 {
3560 case 0 :
3561 break;
3562 case -1 :
3563 output_asm_insn (\"not%.l %0\", operands);
3564 break;
3565 default :
3566 /* FIXME : a scratch register would be welcome here if
3567 -128 <= INTVAL (lo) < -1 */
3568 operands[2] = lo;
3569 /* FIXME : this should be merged with xorsi3 */
3570 {
3571 rtx xoperands[3];
3573 xoperands[0] = operands[0];
3574 xoperands[2] = lo;
3575 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3576 }
3577 }
3578 return \"\";
3579 }
3580 if (GET_CODE (operands[0]) != REG)
3581 {
3582 operands[1] = adjust_address (operands[0], SImode, 4);
3583 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
3584 }
3585 if (GET_CODE (operands[2]) != REG)
3586 {
3587 operands[1] = adjust_address (operands[2], SImode, 4);
3588 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
3589 }
3590 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
3591 }")
3593 (define_expand "xorsi3"
3594 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3595 (xor:SI (match_operand:SI 1 "general_operand" "")
3596 (match_operand:SI 2 "general_operand" "")))]
3597 ""
3598 "")
3600 (define_insn "xorsi3_internal"
3601 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
3602 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3603 (match_operand:SI 2 "general_operand" "di,dKT")))]
3605 "!TARGET_COLDFIRE"
3606 "*
3607 {
3608 return output_xorsi3 (operands);
3609 }")
3611 (define_insn "xorsi3_5200"
3612 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
3613 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3614 (match_operand:SI 2 "general_operand" "d,Ks")))]
3615 "TARGET_COLDFIRE"
3616 "eor%.l %2,%0")
3618 (define_insn "xorhi3"
3619 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3620 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3621 (match_operand:HI 2 "general_operand" "dn")))]
3622 "!TARGET_COLDFIRE"
3623 "eor%.w %2,%0")
3625 (define_insn ""
3626 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3627 (xor:HI (match_dup 0)
3628 (match_operand:HI 1 "general_operand" "dn")))]
3629 "!TARGET_COLDFIRE"
3630 "eor%.w %1,%0")
3632 (define_insn ""
3633 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3634 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3635 (match_dup 0)))]
3636 "!TARGET_COLDFIRE"
3637 "eor%.w %1,%0")
3639 (define_insn "xorqi3"
3640 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3641 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3642 (match_operand:QI 2 "general_operand" "dn")))]
3643 "!TARGET_COLDFIRE"
3644 "eor%.b %2,%0")
3646 (define_insn ""
3647 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3648 (xor:QI (match_dup 0)
3649 (match_operand:QI 1 "general_operand" "dn")))]
3650 "!TARGET_COLDFIRE"
3651 "eor%.b %1,%0")
3653 (define_insn ""
3654 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3655 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3656 (match_dup 0)))]
3657 "!TARGET_COLDFIRE"
3658 "eor%.b %1,%0")
3659 \f
3660 ;; negation instructions
3662 (define_expand "negdi2"
3663 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3664 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3665 ""
3666 "
3667 {
3668 if (TARGET_COLDFIRE)
3669 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3670 else
3671 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3672 DONE;
3673 }")
3675 (define_insn "negdi2_internal"
3676 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
3677 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3678 "!TARGET_COLDFIRE"
3679 "*
3680 {
3681 if (which_alternative == 0)
3682 return \"neg%.l %0\;negx%.l %0\";
3683 if (GET_CODE (operands[0]) == REG)
3684 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3685 else
3686 operands[1] = adjust_address (operands[0], SImode, 4);
3687 if (ADDRESS_REG_P (operands[0]))
3688 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3689 else
3690 return \"neg%.l %1\;negx%.l %0\";
3691 } ")
3693 (define_insn "negdi2_5200"
3694 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3695 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3696 "TARGET_COLDFIRE"
3697 "*
3698 {
3699 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3700 return \"neg%.l %1\;negx%.l %0\";
3701 } ")
3703 (define_expand "negsi2"
3704 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3705 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3706 ""
3707 "
3708 {
3709 if (TARGET_COLDFIRE)
3710 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3711 else
3712 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3713 DONE;
3714 }")
3716 (define_insn "negsi2_internal"
3717 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3718 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3719 "!TARGET_COLDFIRE"
3720 "neg%.l %0")
3722 (define_insn "negsi2_5200"
3723 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3724 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3725 "TARGET_COLDFIRE"
3726 "neg%.l %0")
3728 (define_insn "neghi2"
3729 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3730 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3731 "!TARGET_COLDFIRE"
3732 "neg%.w %0")
3734 (define_insn ""
3735 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3736 (neg:HI (match_dup 0)))]
3737 "!TARGET_COLDFIRE"
3738 "neg%.w %0")
3740 (define_insn "negqi2"
3741 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3742 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3743 "!TARGET_COLDFIRE"
3744 "neg%.b %0")
3746 (define_insn ""
3747 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3748 (neg:QI (match_dup 0)))]
3749 "!TARGET_COLDFIRE"
3750 "neg%.b %0")
3752 ;; If using software floating point, just flip the sign bit.
3754 (define_expand "negsf2"
3755 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3756 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3757 ""
3758 "
3759 {
3760 if (!TARGET_68881)
3761 {
3762 rtx result;
3763 rtx target;
3765 target = operand_subword_force (operands[0], 0, SFmode);
3766 result = expand_binop (SImode, xor_optab,
3767 operand_subword_force (operands[1], 0, SFmode),
3768 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
3769 if (result == 0)
3770 abort ();
3772 if (result != target)
3773 emit_move_insn (result, target);
3775 /* Make a place for REG_EQUAL. */
3776 emit_move_insn (operands[0], operands[0]);
3777 DONE;
3778 }
3779 }")
3781 (define_insn ""
3782 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
3783 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3784 "TARGET_68881"
3785 "*
3786 {
3787 if (DATA_REG_P (operands[0]))
3788 {
3789 operands[1] = GEN_INT (31);
3790 return \"bchg %1,%0\";
3791 }
3792 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3793 return \"f%$neg%.x %1,%0\";
3794 return \"f%$neg%.s %f1,%0\";
3795 }")
3797 (define_expand "negdf2"
3798 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3799 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3800 ""
3801 "
3802 {
3803 if (!TARGET_68881)
3804 {
3805 rtx result;
3806 rtx target;
3807 rtx insns;
3809 start_sequence ();
3810 target = operand_subword (operands[0], 0, 1, DFmode);
3811 result = expand_binop (SImode, xor_optab,
3812 operand_subword_force (operands[1], 0, DFmode),
3813 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
3814 if (result == 0)
3815 abort ();
3817 if (result != target)
3818 emit_move_insn (result, target);
3820 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3821 operand_subword_force (operands[1], 1, DFmode));
3823 insns = get_insns ();
3824 end_sequence ();
3826 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3827 DONE;
3828 }
3829 }")
3831 (define_insn ""
3832 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
3833 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3834 "TARGET_68881"
3835 "*
3836 {
3837 if (DATA_REG_P (operands[0]))
3838 {
3839 operands[1] = GEN_INT (31);
3840 return \"bchg %1,%0\";
3841 }
3842 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3843 return \"f%&neg%.x %1,%0\";
3844 return \"f%&neg%.d %f1,%0\";
3845 }")
3846 \f
3847 ;; Sqrt instruction for the 68881
3849 (define_insn "sqrtsf2"
3850 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3851 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3852 "TARGET_68881"
3853 "*
3854 {
3855 if (FP_REG_P (operands[1]))
3856 return \"f%$sqrt%.x %1,%0\";
3857 else
3858 return \"f%$sqrt%.s %1,%0\";
3859 }")
3861 (define_insn "sqrtdf2"
3862 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3863 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3864 "TARGET_68881"
3865 "*
3866 {
3867 if (FP_REG_P (operands[1]))
3868 return \"f%&sqrt%.x %1,%0\";
3869 else
3870 return \"f%&sqrt%.d %1,%0\";
3871 }")
3873 ;; Absolute value instructions
3874 ;; If using software floating point, just zero the sign bit.
3876 (define_expand "abssf2"
3877 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3878 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3879 ""
3880 "
3881 {
3882 if (!TARGET_68881)
3883 {
3884 rtx result;
3885 rtx target;
3887 target = operand_subword_force (operands[0], 0, SFmode);
3888 result = expand_binop (SImode, and_optab,
3889 operand_subword_force (operands[1], 0, SFmode),
3890 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3891 if (result == 0)
3892 abort ();
3894 if (result != target)
3895 emit_move_insn (result, target);
3897 /* Make a place for REG_EQUAL. */
3898 emit_move_insn (operands[0], operands[0]);
3899 DONE;
3900 }
3901 }")
3903 (define_insn ""
3904 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3905 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
3906 "TARGET_68881"
3907 "*
3908 {
3909 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3910 return \"f%$abs%.x %1,%0\";
3911 return \"f%$abs%.s %f1,%0\";
3912 }")
3914 (define_expand "absdf2"
3915 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3916 (abs:DF (match_operand:DF 1 "general_operand" "")))]
3917 ""
3918 "
3919 {
3920 if (!TARGET_68881)
3921 {
3922 rtx result;
3923 rtx target;
3924 rtx insns;
3926 start_sequence ();
3927 target = operand_subword (operands[0], 0, 1, DFmode);
3928 result = expand_binop (SImode, and_optab,
3929 operand_subword_force (operands[1], 0, DFmode),
3930 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3931 if (result == 0)
3932 abort ();
3934 if (result != target)
3935 emit_move_insn (result, target);
3937 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3938 operand_subword_force (operands[1], 1, DFmode));
3940 insns = get_insns ();
3941 end_sequence ();
3943 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3944 DONE;
3945 }
3946 }")
3948 (define_insn ""
3949 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3950 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
3951 "TARGET_68881"
3952 "*
3953 {
3954 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3955 return \"f%&abs%.x %1,%0\";
3956 return \"f%&abs%.d %f1,%0\";
3957 }")
3958 \f
3959 ;; one complement instructions
3961 ;; "one_cmpldi2" is mainly here to help combine().
3962 (define_insn "one_cmpldi2"
3963 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
3964 (not:DI (match_operand:DI 1 "general_operand" "0")))]
3965 "!TARGET_COLDFIRE"
3966 "*
3967 {
3968 CC_STATUS_INIT;
3969 if (GET_CODE (operands[0]) == REG)
3970 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3971 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
3972 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3973 operands[1] = operands[0];
3974 else
3975 operands[1] = adjust_address (operands[0], SImode, 4);
3976 return \"not%.l %1\;not%.l %0\";
3977 }")
3979 (define_expand "one_cmplsi2"
3980 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3981 (not:SI (match_operand:SI 1 "general_operand" "")))]
3982 ""
3983 "
3984 {
3985 if (TARGET_COLDFIRE)
3986 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
3987 else
3988 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
3989 DONE;
3990 }")
3992 (define_insn "one_cmplsi2_internal"
3993 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3994 (not:SI (match_operand:SI 1 "general_operand" "0")))]
3995 "!TARGET_COLDFIRE"
3996 "not%.l %0")
3998 (define_insn "one_cmplsi2_5200"
3999 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4000 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4001 "TARGET_COLDFIRE"
4002 "not%.l %0")
4004 (define_insn "one_cmplhi2"
4005 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4006 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4007 "!TARGET_COLDFIRE"
4008 "not%.w %0")
4010 (define_insn ""
4011 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4012 (not:HI (match_dup 0)))]
4013 "!TARGET_COLDFIRE"
4014 "not%.w %0")
4016 (define_insn "one_cmplqi2"
4017 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4018 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4019 "!TARGET_COLDFIRE"
4020 "not%.b %0")
4022 (define_insn ""
4023 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4024 (not:QI (match_dup 0)))]
4025 "!TARGET_COLDFIRE"
4026 "not%.b %0")
4027 \f
4028 ;; arithmetic shift instructions
4029 ;; We don't need the shift memory by 1 bit instruction
4031 (define_insn "ashldi_extsi"
4032 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4033 (ashift:DI
4034 (match_operator:DI 2 "extend_operator"
4035 [(match_operand:SI 1 "general_operand" "rm")])
4036 (const_int 32)))]
4037 ""
4038 "*
4039 {
4040 CC_STATUS_INIT;
4041 if (GET_CODE (operands[0]) == REG)
4042 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4043 else
4044 operands[2] = adjust_address (operands[0], SImode, 4);
4045 if (ADDRESS_REG_P (operands[0]))
4046 return \"move%.l %1,%0\;sub%.l %2,%2\";
4047 else
4048 return \"move%.l %1,%0\;clr%.l %2\";
4049 } ")
4051 (define_insn "ashldi_sexthi"
4052 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4053 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4054 (const_int 32)))
4055 (clobber (match_scratch:SI 2 "=a,X"))]
4056 ""
4057 "*
4058 {
4059 CC_STATUS_INIT;
4060 if (GET_CODE (operands[0]) == MEM)
4061 {
4062 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4063 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4064 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4065 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4066 else
4067 {
4068 operands[3] = adjust_address (operands[0], SImode, 4);
4069 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4070 }
4071 }
4072 else if (DATA_REG_P (operands[0]))
4073 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4074 else
4075 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4076 } ")
4078 (define_insn "ashldi_const32"
4079 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
4080 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4081 (const_int 32)))]
4082 ""
4083 "*
4084 {
4085 CC_STATUS_INIT;
4086 if (GET_CODE (operands[1]) == REG)
4087 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4088 else
4089 operands[3] = adjust_address (operands[1], SImode, 4);
4090 if (GET_CODE (operands[0]) == REG)
4091 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4092 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4093 return \"clr%.l %0\;move%.l %3,%0\";
4094 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4095 return \"move%.l %3,%0\;clr%.l %0\";
4096 else
4097 operands[2] = adjust_address (operands[0], SImode, 4);
4098 if (ADDRESS_REG_P (operands[2]))
4099 return \"move%.l %3,%0\;sub%.l %2,%2\";
4100 else
4101 return \"move%.l %3,%0\;clr%.l %2\";
4102 } ")
4104 ;; The predicate below must be general_operand, because ashldi3 allows that
4105 (define_insn "ashldi_const"
4106 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4107 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4108 (match_operand 2 "const_int_operand" "n")))]
4109 "(!TARGET_COLDFIRE
4110 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4111 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4112 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4113 "*
4114 {
4115 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4116 if (INTVAL (operands[2]) == 1)
4117 return \"add%.l %1,%1\;addx%.l %0,%0\";
4118 else if (INTVAL (operands[2]) == 8)
4119 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4120 else if (INTVAL (operands[2]) == 16)
4121 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4122 else if (INTVAL (operands[2]) == 48)
4123 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4124 else if (INTVAL (operands[2]) == 2)
4125 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4126 else if (INTVAL (operands[2]) == 3)
4127 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4128 else /* 32 < INTVAL (operands[2]) <= 63 */
4129 {
4130 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4131 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4132 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4133 return \"mov%.l %1,%0\;moveq %#0,%1\";
4134 }
4135 } ")
4137 (define_expand "ashldi3"
4138 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4139 (ashift:DI (match_operand:DI 1 "general_operand" "")
4140 (match_operand 2 "const_int_operand" "")))]
4141 "!TARGET_COLDFIRE"
4142 "
4143 {
4144 /* ??? This is a named pattern like this is not allowed to FAIL based
4145 on its operands. */
4146 if (GET_CODE (operands[2]) != CONST_INT
4147 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4148 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4149 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4150 FAIL;
4151 } ")
4153 ;; On most 68k models, this makes faster code in a special case.
4155 (define_insn "ashlsi_16"
4156 [(set (match_operand:SI 0 "register_operand" "=d")
4157 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4158 (const_int 16)))]
4159 "!TARGET_68060"
4160 "*
4161 {
4162 CC_STATUS_INIT;
4163 return \"swap %0\;clr%.w %0\";
4164 }")
4166 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4167 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4169 ;; On the 68000, this makes faster code in a special case.
4171 (define_insn "ashlsi_17_24"
4172 [(set (match_operand:SI 0 "register_operand" "=d")
4173 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4174 (match_operand:SI 2 "const_int_operand" "n")))]
4175 "(! TARGET_68020 && !TARGET_COLDFIRE
4176 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4177 "*
4178 {
4179 CC_STATUS_INIT;
4181 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4182 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4183 }")
4185 (define_insn "ashlsi3"
4186 [(set (match_operand:SI 0 "register_operand" "=d")
4187 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4188 (match_operand:SI 2 "general_operand" "dI")))]
4189 ""
4190 "*
4191 {
4192 if (operands[2] == const1_rtx)
4193 {
4194 cc_status.flags = CC_NO_OVERFLOW;
4195 return \"add%.l %0,%0\";
4196 }
4197 return \"lsl%.l %2,%0\";
4198 }")
4200 (define_insn "ashlhi3"
4201 [(set (match_operand:HI 0 "register_operand" "=d")
4202 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4203 (match_operand:HI 2 "general_operand" "dI")))]
4204 "!TARGET_COLDFIRE"
4205 "lsl%.w %2,%0")
4207 (define_insn ""
4208 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4209 (ashift:HI (match_dup 0)
4210 (match_operand:HI 1 "general_operand" "dI")))]
4211 "!TARGET_COLDFIRE"
4212 "lsl%.w %1,%0")
4214 (define_insn "ashlqi3"
4215 [(set (match_operand:QI 0 "register_operand" "=d")
4216 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4217 (match_operand:QI 2 "general_operand" "dI")))]
4218 "!TARGET_COLDFIRE"
4219 "lsl%.b %2,%0")
4221 (define_insn ""
4222 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4223 (ashift:QI (match_dup 0)
4224 (match_operand:QI 1 "general_operand" "dI")))]
4225 "!TARGET_COLDFIRE"
4226 "lsl%.b %1,%0")
4228 ;; On most 68k models, this makes faster code in a special case.
4230 (define_insn "ashrsi_16"
4231 [(set (match_operand:SI 0 "register_operand" "=d")
4232 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4233 (const_int 16)))]
4234 "!TARGET_68060"
4235 "swap %0\;ext%.l %0")
4237 ;; On the 68000, this makes faster code in a special case.
4239 (define_insn ""
4240 [(set (match_operand:SI 0 "register_operand" "=d")
4241 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4242 (match_operand:SI 2 "const_int_operand" "n")))]
4243 "(! TARGET_68020 && !TARGET_COLDFIRE
4244 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4245 "*
4246 {
4247 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4248 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4249 }")
4251 (define_insn "subreghi1ashrdi_const32"
4252 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4253 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4254 (const_int 32)) 6))]
4255 ""
4256 "*
4257 {
4258 if (GET_CODE (operands[1]) != REG)
4259 operands[1] = adjust_address (operands[1], HImode, 2);
4260 return \"move%.w %1,%0\";
4261 } ")
4263 (define_insn "subregsi1ashrdi_const32"
4264 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4265 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4266 (const_int 32)) 4))]
4267 ""
4268 "*
4269 {
4270 return \"move%.l %1,%0\";
4271 } ")
4273 (define_insn "ashrdi_const32"
4274 [(set (match_operand:DI 0 "register_operand" "=d")
4275 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4276 (const_int 32)))]
4277 ""
4278 "*
4279 {
4280 CC_STATUS_INIT;
4281 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4282 if (TARGET_68020)
4283 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4284 else
4285 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4286 } ")
4288 (define_insn "ashrdi_const32_mem"
4289 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,<")
4290 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4291 (const_int 32)))
4292 (clobber (match_scratch:SI 2 "=d,d"))]
4293 ""
4294 "*
4295 {
4296 CC_STATUS_INIT;
4297 if (which_alternative == 1)
4298 operands[3] = operands[0];
4299 else
4300 operands[3] = adjust_address (operands[0], SImode, 4);
4301 if (TARGET_68020)
4302 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4303 else
4304 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4305 } ")
4307 ;; The predicate below must be general_operand, because ashrdi3 allows that
4308 (define_insn "ashrdi_const"
4309 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4310 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4311 (match_operand 2 "const_int_operand" "n")))]
4312 "(!TARGET_COLDFIRE
4313 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4314 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4315 || INTVAL (operands[2]) == 31
4316 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4317 "*
4318 {
4319 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4320 if (INTVAL (operands[2]) == 63)
4321 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4322 CC_STATUS_INIT;
4323 if (INTVAL (operands[2]) == 1)
4324 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4325 else if (INTVAL (operands[2]) == 8)
4326 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4327 else if (INTVAL (operands[2]) == 16)
4328 return \"move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1\";
4329 else if (INTVAL (operands[2]) == 48)
4330 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4331 else if (INTVAL (operands[2]) == 31)
4332 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4333 else if (INTVAL (operands[2]) == 2)
4334 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4335 else if (INTVAL (operands[2]) == 3)
4336 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4337 else /* 32 < INTVAL (operands[2]) <= 63 */
4338 {
4339 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4340 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4341 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4342 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4343 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4344 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4345 }
4346 } ")
4348 (define_expand "ashrdi3"
4349 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4350 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4351 (match_operand 2 "const_int_operand" "")))]
4352 "!TARGET_COLDFIRE"
4353 "
4354 {
4355 /* ??? This is a named pattern like this is not allowed to FAIL based
4356 on its operands. */
4357 if (GET_CODE (operands[2]) != CONST_INT
4358 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4359 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4360 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4361 FAIL;
4362 } ")
4364 ;; On all 68k models, this makes faster code in a special case.
4366 (define_insn "ashrsi_31"
4367 [(set (match_operand:SI 0 "register_operand" "=d")
4368 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4369 (const_int 31)))]
4370 ""
4371 "*
4372 {
4373 return \"add%.l %0,%0\;subx%.l %0,%0\";
4374 }")
4376 (define_insn "ashrsi3"
4377 [(set (match_operand:SI 0 "register_operand" "=d")
4378 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4379 (match_operand:SI 2 "general_operand" "dI")))]
4380 ""
4381 "asr%.l %2,%0")
4383 (define_insn "ashrhi3"
4384 [(set (match_operand:HI 0 "register_operand" "=d")
4385 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4386 (match_operand:HI 2 "general_operand" "dI")))]
4387 "!TARGET_COLDFIRE"
4388 "asr%.w %2,%0")
4390 (define_insn ""
4391 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4392 (ashiftrt:HI (match_dup 0)
4393 (match_operand:HI 1 "general_operand" "dI")))]
4394 "!TARGET_COLDFIRE"
4395 "asr%.w %1,%0")
4397 (define_insn "ashrqi3"
4398 [(set (match_operand:QI 0 "register_operand" "=d")
4399 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4400 (match_operand:QI 2 "general_operand" "dI")))]
4401 "!TARGET_COLDFIRE"
4402 "asr%.b %2,%0")
4404 (define_insn ""
4405 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4406 (ashiftrt:QI (match_dup 0)
4407 (match_operand:QI 1 "general_operand" "dI")))]
4408 "!TARGET_COLDFIRE"
4409 "asr%.b %1,%0")
4410 \f
4411 ;; logical shift instructions
4413 ;; commented out because of reload problems in 950612-1.c
4414 ;;(define_insn ""
4415 ;; [(set (cc0)
4416 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4417 ;; (const_int 32)) 4))
4418 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
4419 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4420 ;; (const_int 32)) 4))]
4421 ;; ""
4422 ;; "*
4423 ;;{
4424 ;; return \"move%.l %0,%1\";
4425 ;;} ")
4426 ;;
4427 ;;(define_insn ""
4428 ;; [(set (cc0)
4429 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4430 ;; (const_int 32)) 0))
4431 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
4432 ;; (lshiftrt:DI (match_dup 0)
4433 ;; (const_int 32)))]
4434 ;; ""
4435 ;; "*
4436 ;;{
4437 ;; if (GET_CODE (operands[1]) == REG)
4438 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4439 ;; else
4440 ;; operands[2] = adjust_address (operands[1], SImode, 4);
4441 ;; return \"move%.l %0,%2\;clr%.l %1\";
4442 ;;} ")
4444 (define_insn "subreg1lshrdi_const32"
4445 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4446 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4447 (const_int 32)) 4))]
4448 ""
4449 "*
4450 {
4451 return \"move%.l %1,%0\";
4452 } ")
4454 (define_insn "lshrdi_const32"
4455 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,<,>")
4456 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4457 (const_int 32)))]
4458 ""
4459 "*
4460 {
4461 CC_STATUS_INIT;
4462 if (which_alternative == 1)
4463 return \"move%.l %1,%0\;clr%.l %0\";
4464 if (which_alternative == 2)
4465 return \"clr%.l %0\;move%.l %1,%0\";
4466 if (GET_CODE (operands[0]) == REG)
4467 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4468 else
4469 operands[2] = adjust_address (operands[0], SImode, 4);
4470 if (GET_CODE (operands[1]) == REG)
4471 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4472 else
4473 operands[3] = adjust_address (operands[1], SImode, 4);
4474 if (ADDRESS_REG_P (operands[0]))
4475 return \"move%.l %1,%2\;sub%.l %0,%0\";
4476 else
4477 return \"move%.l %1,%2\;clr%.l %0\";
4478 } ")
4480 ;; The predicate below must be general_operand, because lshrdi3 allows that
4481 (define_insn "lshrdi_const"
4482 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4483 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4484 (match_operand 2 "const_int_operand" "n")))]
4485 "(!TARGET_COLDFIRE
4486 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4487 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4488 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4489 "*
4490 {
4491 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4492 if (INTVAL (operands[2]) == 63)
4493 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4494 CC_STATUS_INIT;
4495 if (INTVAL (operands[2]) == 1)
4496 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4497 else if (INTVAL (operands[2]) == 8)
4498 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4499 else if (INTVAL (operands[2]) == 16)
4500 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4501 else if (INTVAL (operands[2]) == 48)
4502 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4503 else if (INTVAL (operands[2]) == 2)
4504 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4505 else if (INTVAL (operands[2]) == 3)
4506 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4507 else /* 32 < INTVAL (operands[2]) <= 63 */
4508 {
4509 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4510 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4511 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4512 return \"mov%.l %0,%1\;moveq %#0,%0\";
4513 }
4514 } ")
4516 (define_expand "lshrdi3"
4517 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4518 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4519 (match_operand 2 "const_int_operand" "")))]
4520 "!TARGET_COLDFIRE"
4521 "
4522 {
4523 /* ??? This is a named pattern like this is not allowed to FAIL based
4524 on its operands. */
4525 if (GET_CODE (operands[2]) != CONST_INT
4526 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4527 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4528 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4529 FAIL;
4530 } ")
4532 ;; On all 68k models, this makes faster code in a special case.
4534 (define_insn "lshrsi_31"
4535 [(set (match_operand:SI 0 "register_operand" "=d")
4536 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4537 (const_int 31)))]
4538 ""
4539 "*
4540 {
4541 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4542 }")
4544 ;; On most 68k models, this makes faster code in a special case.
4546 (define_insn "lshrsi_16"
4547 [(set (match_operand:SI 0 "register_operand" "=d")
4548 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4549 (const_int 16)))]
4550 "!TARGET_68060"
4551 "*
4552 {
4553 CC_STATUS_INIT;
4554 return \"clr%.w %0\;swap %0\";
4555 }")
4557 ;; On the 68000, this makes faster code in a special case.
4559 (define_insn "lshrsi_17_24"
4560 [(set (match_operand:SI 0 "register_operand" "=d")
4561 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4562 (match_operand:SI 2 "const_int_operand" "n")))]
4563 "(! TARGET_68020 && !TARGET_COLDFIRE
4564 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4565 "*
4566 {
4567 /* I think lsr%.w sets the CC properly. */
4568 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4569 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4570 }")
4572 (define_insn "lshrsi3"
4573 [(set (match_operand:SI 0 "register_operand" "=d")
4574 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4575 (match_operand:SI 2 "general_operand" "dI")))]
4576 ""
4577 "lsr%.l %2,%0")
4579 (define_insn "lshrhi3"
4580 [(set (match_operand:HI 0 "register_operand" "=d")
4581 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4582 (match_operand:HI 2 "general_operand" "dI")))]
4583 "!TARGET_COLDFIRE"
4584 "lsr%.w %2,%0")
4586 (define_insn ""
4587 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4588 (lshiftrt:HI (match_dup 0)
4589 (match_operand:HI 1 "general_operand" "dI")))]
4590 "!TARGET_COLDFIRE"
4591 "lsr%.w %1,%0")
4593 (define_insn "lshrqi3"
4594 [(set (match_operand:QI 0 "register_operand" "=d")
4595 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4596 (match_operand:QI 2 "general_operand" "dI")))]
4597 "!TARGET_COLDFIRE"
4598 "lsr%.b %2,%0")
4600 (define_insn ""
4601 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4602 (lshiftrt:QI (match_dup 0)
4603 (match_operand:QI 1 "general_operand" "dI")))]
4604 "!TARGET_COLDFIRE"
4605 "lsr%.b %1,%0")
4606 \f
4607 ;; rotate instructions
4609 (define_insn "rotlsi3"
4610 [(set (match_operand:SI 0 "register_operand" "=d")
4611 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4612 (match_operand:SI 2 "general_operand" "dINO")))]
4613 "!TARGET_COLDFIRE"
4614 "*
4615 {
4616 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4617 return \"swap %0\";
4618 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4619 {
4620 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
4621 return \"ror%.l %2,%0\";
4622 }
4623 else
4624 return \"rol%.l %2,%0\";
4625 }")
4627 (define_insn "rotlhi3"
4628 [(set (match_operand:HI 0 "register_operand" "=d")
4629 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4630 (match_operand:HI 2 "general_operand" "dIP")))]
4631 "!TARGET_COLDFIRE"
4632 "*
4633 {
4634 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4635 {
4636 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4637 return \"ror%.w %2,%0\";
4638 }
4639 else
4640 return \"rol%.w %2,%0\";
4641 }")
4643 (define_insn ""
4644 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4645 (rotate:HI (match_dup 0)
4646 (match_operand:HI 1 "general_operand" "dIP")))]
4647 "!TARGET_COLDFIRE"
4648 "*
4649 {
4650 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4651 {
4652 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4653 return \"ror%.w %2,%0\";
4654 }
4655 else
4656 return \"rol%.w %2,%0\";
4657 }")
4659 (define_insn "rotlqi3"
4660 [(set (match_operand:QI 0 "register_operand" "=d")
4661 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4662 (match_operand:QI 2 "general_operand" "dI")))]
4663 "!TARGET_COLDFIRE"
4664 "*
4665 {
4666 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4667 {
4668 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4669 return \"ror%.b %2,%0\";
4670 }
4671 else
4672 return \"rol%.b %2,%0\";
4673 }")
4675 (define_insn ""
4676 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4677 (rotate:QI (match_dup 0)
4678 (match_operand:QI 1 "general_operand" "dI")))]
4679 "!TARGET_COLDFIRE"
4680 "*
4681 {
4682 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4683 {
4684 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4685 return \"ror%.b %2,%0\";
4686 }
4687 else
4688 return \"rol%.b %2,%0\";
4689 }")
4691 (define_insn "rotrsi3"
4692 [(set (match_operand:SI 0 "register_operand" "=d")
4693 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4694 (match_operand:SI 2 "general_operand" "dI")))]
4695 "!TARGET_COLDFIRE"
4696 "ror%.l %2,%0")
4698 (define_insn "rotrhi3"
4699 [(set (match_operand:HI 0 "register_operand" "=d")
4700 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4701 (match_operand:HI 2 "general_operand" "dI")))]
4702 "!TARGET_COLDFIRE"
4703 "ror%.w %2,%0")
4705 (define_insn ""
4706 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4707 (rotatert:HI (match_dup 0)
4708 (match_operand:HI 1 "general_operand" "dI")))]
4709 "!TARGET_COLDFIRE"
4710 "ror%.w %1,%0")
4712 (define_insn "rotrqi3"
4713 [(set (match_operand:QI 0 "register_operand" "=d")
4714 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4715 (match_operand:QI 2 "general_operand" "dI")))]
4716 "!TARGET_COLDFIRE"
4717 "ror%.b %2,%0")
4719 (define_insn ""
4720 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4721 (rotatert:QI (match_dup 0)
4722 (match_operand:QI 1 "general_operand" "dI")))]
4723 "!TARGET_COLDFIRE"
4724 "ror%.b %1,%0")
4725 \f
4727 ;; Bit set/clear in memory byte.
4729 ;; set bit, bit number is int
4730 (define_insn "bsetmemqi"
4731 [(set (match_operand:QI 0 "memory_operand" "+m")
4732 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4733 (match_operand:SI 1 "general_operand" "d")) 3)
4734 (match_dup 0)))]
4735 ""
4736 "*
4737 {
4738 CC_STATUS_INIT;
4739 return \"bset %1,%0\";
4740 }")
4742 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4743 (define_insn ""
4744 [(set (match_operand:QI 0 "memory_operand" "+m")
4745 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4746 (match_operator:SI 2 "extend_operator"
4747 [(match_operand 1 "general_operand" "d")])) 3)
4748 (match_dup 0)))]
4749 ""
4750 "*
4751 {
4752 CC_STATUS_INIT;
4753 return \"bset %1,%0\";
4754 }")
4756 ;; clear bit, bit number is int
4757 (define_insn "bclrmemqi"
4758 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4759 (const_int 1)
4760 (minus:SI (const_int 7)
4761 (match_operand:SI 1 "general_operand" "d")))
4762 (const_int 0))]
4763 ""
4764 "*
4765 {
4766 CC_STATUS_INIT;
4767 return \"bclr %1,%0\";
4768 }")
4770 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4771 (define_insn ""
4772 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4773 (const_int 1)
4774 (minus:SI (const_int 7)
4775 (match_operator:SI 2 "extend_operator"
4776 [(match_operand 1 "general_operand" "d")])))
4777 (const_int 0))]
4778 ""
4779 "*
4780 {
4781 CC_STATUS_INIT;
4782 return \"bclr %1,%0\";
4783 }")
4785 ;; Special cases of bit-field insns which we should
4786 ;; recognize in preference to the general case.
4787 ;; These handle aligned 8-bit and 16-bit fields,
4788 ;; which can usually be done with move instructions.
4790 ;
4791 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4792 ; alignment of structure members is specified.
4793 ;
4794 ; The move is allowed to be odd byte aligned, because that's still faster
4795 ; than an odd byte aligned bit-field instruction.
4796 ;
4797 (define_insn ""
4798 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4799 (const_int 32)
4800 (match_operand:SI 1 "const_int_operand" "n"))
4801 (match_operand:SI 2 "general_src_operand" "rmSi"))]
4802 "TARGET_68020 && TARGET_BITFIELD
4803 && (INTVAL (operands[1]) % 8) == 0
4804 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4805 "*
4806 {
4807 operands[0]
4808 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
4810 return \"move%.l %2,%0\";
4811 }")
4813 (define_insn ""
4814 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4815 (match_operand:SI 1 "const_int_operand" "n")
4816 (match_operand:SI 2 "const_int_operand" "n"))
4817 (match_operand:SI 3 "register_operand" "d"))]
4818 "TARGET_68020 && TARGET_BITFIELD
4819 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4820 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4821 && (GET_CODE (operands[0]) == REG
4822 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4823 "*
4824 {
4825 if (REG_P (operands[0]))
4826 {
4827 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4828 return \"bfins %3,%0{%b2:%b1}\";
4829 }
4830 else
4831 operands[0] = adjust_address (operands[0],
4832 INTVAL (operands[1]) == 8 ? QImode : HImode,
4833 INTVAL (operands[2]) / 8);
4835 if (GET_CODE (operands[3]) == MEM)
4836 operands[3] = adjust_address (operands[3],
4837 INTVAL (operands[1]) == 8 ? QImode : HImode,
4838 (32 - INTVAL (operands[1])) / 8);
4840 if (INTVAL (operands[1]) == 8)
4841 return \"move%.b %3,%0\";
4842 return \"move%.w %3,%0\";
4843 }")
4846 ;
4847 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4848 ; alignment of structure members is specified.
4849 ;
4850 ; The move is allowed to be odd byte aligned, because that's still faster
4851 ; than an odd byte aligned bit-field instruction.
4852 ;
4853 (define_insn ""
4854 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4855 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4856 (const_int 32)
4857 (match_operand:SI 2 "const_int_operand" "n")))]
4858 "TARGET_68020 && TARGET_BITFIELD
4859 && (INTVAL (operands[2]) % 8) == 0
4860 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4861 "*
4862 {
4863 operands[1]
4864 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4866 return \"move%.l %1,%0\";
4867 }")
4869 (define_insn ""
4870 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
4871 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4872 (match_operand:SI 2 "const_int_operand" "n")
4873 (match_operand:SI 3 "const_int_operand" "n")))]
4874 "TARGET_68020 && TARGET_BITFIELD
4875 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4876 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4877 && (GET_CODE (operands[1]) == REG
4878 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4879 "*
4880 {
4881 cc_status.flags |= CC_NOT_NEGATIVE;
4882 if (REG_P (operands[1]))
4883 {
4884 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4885 return \"bfextu %1{%b3:%b2},%0\";
4886 }
4887 else
4888 operands[1]
4889 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
4891 output_asm_insn (\"clr%.l %0\", operands);
4892 if (GET_CODE (operands[0]) == MEM)
4893 operands[0] = adjust_address (operands[0],
4894 INTVAL (operands[2]) == 8 ? QImode : HImode,
4895 (32 - INTVAL (operands[1])) / 8);
4897 if (INTVAL (operands[2]) == 8)
4898 return \"move%.b %1,%0\";
4899 return \"move%.w %1,%0\";
4900 }")
4902 ;
4903 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4904 ; alignment of structure members is specified.
4905 ;
4906 ; The move is allowed to be odd byte aligned, because that's still faster
4907 ; than an odd byte aligned bit-field instruction.
4908 ;
4909 (define_insn ""
4910 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4911 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4912 (const_int 32)
4913 (match_operand:SI 2 "const_int_operand" "n")))]
4914 "TARGET_68020 && TARGET_BITFIELD
4915 && (INTVAL (operands[2]) % 8) == 0
4916 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4917 "*
4918 {
4919 operands[1]
4920 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4922 return \"move%.l %1,%0\";
4923 }")
4925 (define_insn ""
4926 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4927 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
4928 (match_operand:SI 2 "const_int_operand" "n")
4929 (match_operand:SI 3 "const_int_operand" "n")))]
4930 "TARGET_68020 && TARGET_BITFIELD
4931 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4932 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4933 && (GET_CODE (operands[1]) == REG
4934 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4935 "*
4936 {
4937 if (REG_P (operands[1]))
4938 {
4939 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4940 return \"bfexts %1{%b3:%b2},%0\";
4941 }
4942 else
4943 operands[1]
4944 = adjust_address (operands[1],
4945 INTVAL (operands[2]) == 8 ? QImode : HImode,
4946 INTVAL (operands[3]) / 8);
4948 if (INTVAL (operands[2]) == 8)
4949 return \"move%.b %1,%0\;extb%.l %0\";
4950 return \"move%.w %1,%0\;ext%.l %0\";
4951 }")
4952 \f
4953 ;; Bit-field instructions, general cases.
4954 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
4955 ;; so that its address is reloaded.
4957 (define_expand "extv"
4958 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4959 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
4960 (match_operand:SI 2 "general_operand" "")
4961 (match_operand:SI 3 "general_operand" "")))]
4962 "TARGET_68020 && TARGET_BITFIELD"
4963 "")
4965 (define_insn ""
4966 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4967 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
4968 (match_operand:SI 2 "general_operand" "di")
4969 (match_operand:SI 3 "general_operand" "di")))]
4970 "TARGET_68020 && TARGET_BITFIELD"
4971 "bfexts %1{%b3:%b2},%0")
4973 (define_expand "extzv"
4974 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4975 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
4976 (match_operand:SI 2 "general_operand" "")
4977 (match_operand:SI 3 "general_operand" "")))]
4978 "TARGET_68020 && TARGET_BITFIELD"
4979 "")
4981 (define_insn ""
4982 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d")
4983 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
4984 (match_operand:SI 2 "general_operand" "di,di")
4985 (match_operand:SI 3 "general_operand" "di,di")))]
4986 "TARGET_68020 && TARGET_BITFIELD"
4987 "*
4988 {
4989 if (GET_CODE (operands[2]) == CONST_INT)
4990 {
4991 if (INTVAL (operands[2]) != 32)
4992 cc_status.flags |= CC_NOT_NEGATIVE;
4993 }
4994 else
4995 {
4996 CC_STATUS_INIT;
4997 }
4998 return \"bfextu %1{%b3:%b2},%0\";
4999 }")
5001 (define_insn ""
5002 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5003 (match_operand:SI 1 "general_operand" "di")
5004 (match_operand:SI 2 "general_operand" "di"))
5005 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5006 (match_operand 3 "const_int_operand" "n")))]
5007 "TARGET_68020 && TARGET_BITFIELD
5008 && (INTVAL (operands[3]) == -1
5009 || (GET_CODE (operands[1]) == CONST_INT
5010 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5011 "*
5012 {
5013 CC_STATUS_INIT;
5014 return \"bfchg %0{%b2:%b1}\";
5015 }")
5017 (define_insn ""
5018 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5019 (match_operand:SI 1 "general_operand" "di")
5020 (match_operand:SI 2 "general_operand" "di"))
5021 (const_int 0))]
5022 "TARGET_68020 && TARGET_BITFIELD"
5023 "*
5024 {
5025 CC_STATUS_INIT;
5026 return \"bfclr %0{%b2:%b1}\";
5027 }")
5029 (define_insn ""
5030 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5031 (match_operand:SI 1 "general_operand" "di")
5032 (match_operand:SI 2 "general_operand" "di"))
5033 (const_int -1))]
5034 "TARGET_68020 && TARGET_BITFIELD"
5035 "*
5036 {
5037 CC_STATUS_INIT;
5038 return \"bfset %0{%b2:%b1}\";
5039 }")
5041 (define_expand "insv"
5042 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5043 (match_operand:SI 1 "general_operand" "")
5044 (match_operand:SI 2 "general_operand" ""))
5045 (match_operand:SI 3 "register_operand" ""))]
5046 "TARGET_68020 && TARGET_BITFIELD"
5047 "")
5049 (define_insn ""
5050 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5051 (match_operand:SI 1 "general_operand" "di")
5052 (match_operand:SI 2 "general_operand" "di"))
5053 (match_operand:SI 3 "register_operand" "d"))]
5054 "TARGET_68020 && TARGET_BITFIELD"
5055 "bfins %3,%0{%b2:%b1}")
5057 ;; Now recognize bit-field insns that operate on registers
5058 ;; (or at least were intended to do so).
5060 (define_insn ""
5061 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5062 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5063 (match_operand:SI 2 "general_operand" "di")
5064 (match_operand:SI 3 "general_operand" "di")))]
5065 "TARGET_68020 && TARGET_BITFIELD"
5066 "bfexts %1{%b3:%b2},%0")
5068 (define_insn ""
5069 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5070 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5071 (match_operand:SI 2 "general_operand" "di")
5072 (match_operand:SI 3 "general_operand" "di")))]
5073 "TARGET_68020 && TARGET_BITFIELD"
5074 "*
5075 {
5076 if (GET_CODE (operands[2]) == CONST_INT)
5077 {
5078 if (INTVAL (operands[2]) != 32)
5079 cc_status.flags |= CC_NOT_NEGATIVE;
5080 }
5081 else
5082 {
5083 CC_STATUS_INIT;
5084 }
5085 return \"bfextu %1{%b3:%b2},%0\";
5086 }")
5088 (define_insn ""
5089 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5090 (match_operand:SI 1 "general_operand" "di")
5091 (match_operand:SI 2 "general_operand" "di"))
5092 (const_int 0))]
5093 "TARGET_68020 && TARGET_BITFIELD"
5094 "*
5095 {
5096 CC_STATUS_INIT;
5097 return \"bfclr %0{%b2:%b1}\";
5098 }")
5100 (define_insn ""
5101 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5102 (match_operand:SI 1 "general_operand" "di")
5103 (match_operand:SI 2 "general_operand" "di"))
5104 (const_int -1))]
5105 "TARGET_68020 && TARGET_BITFIELD"
5106 "*
5107 {
5108 CC_STATUS_INIT;
5109 return \"bfset %0{%b2:%b1}\";
5110 }")
5112 (define_insn ""
5113 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5114 (match_operand:SI 1 "general_operand" "di")
5115 (match_operand:SI 2 "general_operand" "di"))
5116 (match_operand:SI 3 "register_operand" "d"))]
5117 "TARGET_68020 && TARGET_BITFIELD"
5118 "*
5119 {
5120 #if 0
5121 /* These special cases are now recognized by a specific pattern. */
5122 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5123 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5124 return \"move%.w %3,%0\";
5125 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5126 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5127 return \"move%.b %3,%0\";
5128 #endif
5129 return \"bfins %3,%0{%b2:%b1}\";
5130 }")
5131 \f
5132 ;; Special patterns for optimizing bit-field instructions.
5134 (define_insn ""
5135 [(set (cc0)
5136 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5137 (match_operand:SI 1 "const_int_operand" "n")
5138 (match_operand:SI 2 "general_operand" "di")))]
5139 "TARGET_68020 && TARGET_BITFIELD"
5140 "*
5141 {
5142 if (operands[1] == const1_rtx
5143 && GET_CODE (operands[2]) == CONST_INT)
5144 {
5145 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5146 return output_btst (operands,
5147 GEN_INT (width - INTVAL (operands[2])),
5148 operands[0], insn, 1000);
5149 /* Pass 1000 as SIGNPOS argument so that btst will
5150 not think we are testing the sign bit for an `and'
5151 and assume that nonzero implies a negative result. */
5152 }
5153 if (INTVAL (operands[1]) != 32)
5154 cc_status.flags = CC_NOT_NEGATIVE;
5155 return \"bftst %0{%b2:%b1}\";
5156 }")
5159 ;;; now handle the register cases
5160 (define_insn ""
5161 [(set (cc0)
5162 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5163 (match_operand:SI 1 "const_int_operand" "n")
5164 (match_operand:SI 2 "general_operand" "di")))]
5165 "TARGET_68020 && TARGET_BITFIELD"
5166 "*
5167 {
5168 if (operands[1] == const1_rtx
5169 && GET_CODE (operands[2]) == CONST_INT)
5170 {
5171 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5172 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5173 operands[0], insn, 1000);
5174 /* Pass 1000 as SIGNPOS argument so that btst will
5175 not think we are testing the sign bit for an `and'
5176 and assume that nonzero implies a negative result. */
5177 }
5178 if (INTVAL (operands[1]) != 32)
5179 cc_status.flags = CC_NOT_NEGATIVE;
5180 return \"bftst %0{%b2:%b1}\";
5181 }")
5182 \f
5183 (define_insn "scc0_di"
5184 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5185 (match_operator 1 "valid_dbcc_comparison_p"
5186 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5187 "! TARGET_COLDFIRE"
5188 "*
5189 {
5190 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5191 } ")
5193 (define_insn "scc0_di_5200"
5194 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5195 (match_operator 1 "valid_dbcc_comparison_p"
5196 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5197 "TARGET_COLDFIRE"
5198 "*
5199 {
5200 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5201 } ")
5203 (define_insn "scc_di"
5204 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5205 (match_operator 1 "valid_dbcc_comparison_p"
5206 [(match_operand:DI 2 "general_operand" "ro,r")
5207 (match_operand:DI 3 "general_operand" "r,ro")]))]
5208 "! TARGET_COLDFIRE"
5209 "*
5210 {
5211 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5212 } ")
5214 (define_insn "scc_di_5200"
5215 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5216 (match_operator 1 "valid_dbcc_comparison_p"
5217 [(match_operand:DI 2 "general_operand" "ro,r")
5218 (match_operand:DI 3 "general_operand" "r,ro")]))]
5219 "TARGET_COLDFIRE"
5220 "*
5221 {
5222 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5223 } ")
5225 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5226 ;; memory, but we cannot allow it to be in memory in case the address
5227 ;; needs to be reloaded.
5229 (define_expand "seq"
5230 [(set (match_operand:QI 0 "register_operand" "")
5231 (eq:QI (cc0) (const_int 0)))]
5232 ""
5233 "
5234 {
5235 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5236 {
5237 m68k_last_compare_had_fp_operands = 0;
5238 FAIL;
5239 }
5240 }")
5242 (define_insn ""
5243 [(set (match_operand:QI 0 "register_operand" "=d")
5244 (eq:QI (cc0) (const_int 0)))]
5245 ""
5246 "*
5247 cc_status = cc_prev_status;
5248 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5249 ")
5251 (define_expand "sne"
5252 [(set (match_operand:QI 0 "register_operand" "")
5253 (ne:QI (cc0) (const_int 0)))]
5254 ""
5255 "
5256 {
5257 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5258 {
5259 m68k_last_compare_had_fp_operands = 0;
5260 FAIL;
5261 }
5262 }")
5264 (define_insn ""
5265 [(set (match_operand:QI 0 "register_operand" "=d")
5266 (ne:QI (cc0) (const_int 0)))]
5267 ""
5268 "*
5269 cc_status = cc_prev_status;
5270 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5271 ")
5273 (define_expand "sgt"
5274 [(set (match_operand:QI 0 "register_operand" "")
5275 (gt:QI (cc0) (const_int 0)))]
5276 ""
5277 "
5278 {
5279 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5280 {
5281 m68k_last_compare_had_fp_operands = 0;
5282 FAIL;
5283 }
5284 }")
5286 (define_insn ""
5287 [(set (match_operand:QI 0 "register_operand" "=d")
5288 (gt:QI (cc0) (const_int 0)))]
5289 ""
5290 "*
5291 cc_status = cc_prev_status;
5292 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5293 ")
5295 (define_expand "sgtu"
5296 [(set (match_operand:QI 0 "register_operand" "")
5297 (gtu:QI (cc0) (const_int 0)))]
5298 ""
5299 "")
5301 (define_insn ""
5302 [(set (match_operand:QI 0 "register_operand" "=d")
5303 (gtu:QI (cc0) (const_int 0)))]
5304 ""
5305 "*
5306 cc_status = cc_prev_status;
5307 return \"shi %0\"; ")
5309 (define_expand "slt"
5310 [(set (match_operand:QI 0 "register_operand" "")
5311 (lt:QI (cc0) (const_int 0)))]
5312 ""
5313 "
5314 {
5315 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5316 {
5317 m68k_last_compare_had_fp_operands = 0;
5318 FAIL;
5319 }
5320 }")
5322 (define_insn ""
5323 [(set (match_operand:QI 0 "register_operand" "=d")
5324 (lt:QI (cc0) (const_int 0)))]
5325 ""
5326 "*
5327 cc_status = cc_prev_status;
5328 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5330 (define_expand "sltu"
5331 [(set (match_operand:QI 0 "register_operand" "")
5332 (ltu:QI (cc0) (const_int 0)))]
5333 ""
5334 "")
5336 (define_insn ""
5337 [(set (match_operand:QI 0 "register_operand" "=d")
5338 (ltu:QI (cc0) (const_int 0)))]
5339 ""
5340 "*
5341 cc_status = cc_prev_status;
5342 return \"scs %0\"; ")
5344 (define_expand "sge"
5345 [(set (match_operand:QI 0 "register_operand" "")
5346 (ge:QI (cc0) (const_int 0)))]
5347 ""
5348 "
5349 {
5350 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5351 {
5352 m68k_last_compare_had_fp_operands = 0;
5353 FAIL;
5354 }
5355 }")
5357 (define_insn ""
5358 [(set (match_operand:QI 0 "register_operand" "=d")
5359 (ge:QI (cc0) (const_int 0)))]
5360 ""
5361 "*
5362 cc_status = cc_prev_status;
5363 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5365 (define_expand "sgeu"
5366 [(set (match_operand:QI 0 "register_operand" "")
5367 (geu:QI (cc0) (const_int 0)))]
5368 ""
5369 "")
5371 (define_insn ""
5372 [(set (match_operand:QI 0 "register_operand" "=d")
5373 (geu:QI (cc0) (const_int 0)))]
5374 ""
5375 "*
5376 cc_status = cc_prev_status;
5377 return \"scc %0\"; ")
5379 (define_expand "sle"
5380 [(set (match_operand:QI 0 "register_operand" "")
5381 (le:QI (cc0) (const_int 0)))]
5382 ""
5383 "
5384 {
5385 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5386 {
5387 m68k_last_compare_had_fp_operands = 0;
5388 FAIL;
5389 }
5390 }")
5392 (define_insn ""
5393 [(set (match_operand:QI 0 "register_operand" "=d")
5394 (le:QI (cc0) (const_int 0)))]
5395 ""
5396 "*
5397 cc_status = cc_prev_status;
5398 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5399 ")
5401 (define_expand "sleu"
5402 [(set (match_operand:QI 0 "register_operand" "")
5403 (leu:QI (cc0) (const_int 0)))]
5404 ""
5405 "")
5407 (define_insn ""
5408 [(set (match_operand:QI 0 "register_operand" "=d")
5409 (leu:QI (cc0) (const_int 0)))]
5410 ""
5411 "*
5412 cc_status = cc_prev_status;
5413 return \"sls %0\"; ")
5415 (define_expand "sordered"
5416 [(set (match_operand:QI 0 "register_operand" "")
5417 (ordered:QI (cc0) (const_int 0)))]
5418 "TARGET_68881 && !TARGET_68060"
5419 {
5420 if (! m68k_last_compare_had_fp_operands)
5421 abort ();
5422 m68k_last_compare_had_fp_operands = 0;
5423 })
5425 (define_insn "*sordered_1"
5426 [(set (match_operand:QI 0 "register_operand" "=d")
5427 (ordered:QI (cc0) (const_int 0)))]
5428 "TARGET_68881 && !TARGET_68060"
5429 {
5430 cc_status = cc_prev_status;
5431 return "fsor %0";
5432 })
5434 (define_expand "sunordered"
5435 [(set (match_operand:QI 0 "register_operand" "")
5436 (unordered:QI (cc0) (const_int 0)))]
5437 "TARGET_68881 && !TARGET_68060"
5438 {
5439 if (! m68k_last_compare_had_fp_operands)
5440 abort ();
5441 m68k_last_compare_had_fp_operands = 0;
5442 })
5444 (define_insn "*sunordered_1"
5445 [(set (match_operand:QI 0 "register_operand" "=d")
5446 (unordered:QI (cc0) (const_int 0)))]
5447 "TARGET_68881 && !TARGET_68060"
5448 {
5449 cc_status = cc_prev_status;
5450 return "fsun %0";
5451 })
5453 (define_expand "suneq"
5454 [(set (match_operand:QI 0 "register_operand" "")
5455 (uneq:QI (cc0) (const_int 0)))]
5456 "TARGET_68881 && !TARGET_68060"
5457 {
5458 if (! m68k_last_compare_had_fp_operands)
5459 abort ();
5460 m68k_last_compare_had_fp_operands = 0;
5461 })
5463 (define_insn "*suneq_1"
5464 [(set (match_operand:QI 0 "register_operand" "=d")
5465 (uneq:QI (cc0) (const_int 0)))]
5466 "TARGET_68881 && !TARGET_68060"
5467 {
5468 cc_status = cc_prev_status;
5469 return "fsueq %0";
5470 })
5472 (define_expand "sunge"
5473 [(set (match_operand:QI 0 "register_operand" "")
5474 (unge:QI (cc0) (const_int 0)))]
5475 "TARGET_68881 && !TARGET_68060"
5476 {
5477 if (! m68k_last_compare_had_fp_operands)
5478 abort ();
5479 m68k_last_compare_had_fp_operands = 0;
5480 })
5482 (define_insn "*sunge_1"
5483 [(set (match_operand:QI 0 "register_operand" "=d")
5484 (unge:QI (cc0) (const_int 0)))]
5485 "TARGET_68881 && !TARGET_68060"
5486 {
5487 cc_status = cc_prev_status;
5488 return "fsuge %0";
5489 })
5491 (define_expand "sungt"
5492 [(set (match_operand:QI 0 "register_operand" "")
5493 (ungt:QI (cc0) (const_int 0)))]
5494 "TARGET_68881 && !TARGET_68060"
5495 {
5496 if (! m68k_last_compare_had_fp_operands)
5497 abort ();
5498 m68k_last_compare_had_fp_operands = 0;
5499 })
5501 (define_insn "*sungt_1"
5502 [(set (match_operand:QI 0 "register_operand" "=d")
5503 (ungt:QI (cc0) (const_int 0)))]
5504 "TARGET_68881 && !TARGET_68060"
5505 {
5506 cc_status = cc_prev_status;
5507 return "fsugt %0";
5508 })
5510 (define_expand "sunle"
5511 [(set (match_operand:QI 0 "register_operand" "")
5512 (unle:QI (cc0) (const_int 0)))]
5513 "TARGET_68881 && !TARGET_68060"
5514 {
5515 if (! m68k_last_compare_had_fp_operands)
5516 abort ();
5517 m68k_last_compare_had_fp_operands = 0;
5518 })
5520 (define_insn "*sunle_1"
5521 [(set (match_operand:QI 0 "register_operand" "=d")
5522 (unle:QI (cc0) (const_int 0)))]
5523 "TARGET_68881 && !TARGET_68060"
5524 {
5525 cc_status = cc_prev_status;
5526 return "fsule %0";
5527 })
5529 (define_expand "sunlt"
5530 [(set (match_operand:QI 0 "register_operand" "")
5531 (unlt:QI (cc0) (const_int 0)))]
5532 "TARGET_68881 && !TARGET_68060"
5533 {
5534 if (! m68k_last_compare_had_fp_operands)
5535 abort ();
5536 m68k_last_compare_had_fp_operands = 0;
5537 })
5539 (define_insn "*sunlt_1"
5540 [(set (match_operand:QI 0 "register_operand" "=d")
5541 (unlt:QI (cc0) (const_int 0)))]
5542 "TARGET_68881 && !TARGET_68060"
5543 {
5544 cc_status = cc_prev_status;
5545 return "fsult %0";
5546 })
5548 (define_expand "sltgt"
5549 [(set (match_operand:QI 0 "register_operand" "")
5550 (ltgt:QI (cc0) (const_int 0)))]
5551 "TARGET_68881 && !TARGET_68060"
5552 {
5553 if (! m68k_last_compare_had_fp_operands)
5554 abort ();
5555 m68k_last_compare_had_fp_operands = 0;
5556 })
5558 (define_insn "*sltgt_1"
5559 [(set (match_operand:QI 0 "register_operand" "=d")
5560 (ltgt:QI (cc0) (const_int 0)))]
5561 "TARGET_68881 && !TARGET_68060"
5562 {
5563 cc_status = cc_prev_status;
5564 return "fsogl %0";
5565 })
5567 (define_insn "*fsogt_1"
5568 [(set (match_operand:QI 0 "register_operand" "=d")
5569 (not:QI (unle:QI (cc0) (const_int 0))))]
5570 "TARGET_68881 && !TARGET_68060"
5571 {
5572 cc_status = cc_prev_status;
5573 return "fsogt %0";
5574 })
5576 (define_insn "*fsoge_1"
5577 [(set (match_operand:QI 0 "register_operand" "=d")
5578 (not:QI (unlt:QI (cc0) (const_int 0))))]
5579 "TARGET_68881 && !TARGET_68060"
5580 {
5581 cc_status = cc_prev_status;
5582 return "fsoge %0";
5583 })
5585 (define_insn "*fsolt_1"
5586 [(set (match_operand:QI 0 "register_operand" "=d")
5587 (not:QI (unge:QI (cc0) (const_int 0))))]
5588 "TARGET_68881 && !TARGET_68060"
5589 {
5590 cc_status = cc_prev_status;
5591 return "fsolt %0";
5592 })
5594 (define_insn "*fsole_1"
5595 [(set (match_operand:QI 0 "register_operand" "=d")
5596 (not:QI (ungt:QI (cc0) (const_int 0))))]
5597 "TARGET_68881 && !TARGET_68060"
5598 {
5599 cc_status = cc_prev_status;
5600 return "fsole %0";
5601 })
5602 \f
5603 ;; Basic conditional jump instructions.
5605 (define_insn "beq0_di"
5606 [(set (pc)
5607 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5608 (const_int 0))
5609 (label_ref (match_operand 1 "" ","))
5610 (pc)))
5611 (clobber (match_scratch:SI 2 "=d,d"))]
5612 ""
5613 "*
5614 {
5615 CC_STATUS_INIT;
5616 if (which_alternative == 1)
5617 {
5618 if (MOTOROLA)
5619 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5620 else
5621 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5622 }
5623 if ((cc_prev_status.value1
5624 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5625 || (cc_prev_status.value2
5626 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5627 {
5628 cc_status = cc_prev_status;
5629 return MOTOROLA ? \"jbeq %l1\" : \"jeq %l1\";
5630 }
5631 if (GET_CODE (operands[0]) == REG)
5632 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5633 else
5634 operands[3] = adjust_address (operands[0], SImode, 4);
5635 if (! ADDRESS_REG_P (operands[0]))
5636 {
5637 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5638 {
5639 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5640 {
5641 if (MOTOROLA)
5642 return \"or%.l %0,%2\;jbeq %l1\";
5643 else
5644 return \"or%.l %0,%2\;jeq %l1\";
5645 }
5646 else
5647 {
5648 if (MOTOROLA)
5649 return \"or%.l %3,%2\;jbeq %l1\";
5650 else
5651 return \"or%.l %3,%2\;jeq %l1\";
5652 }
5653 }
5654 if (MOTOROLA)
5655 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5656 else
5657 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5658 }
5659 operands[4] = gen_label_rtx();
5660 if (TARGET_68020 || TARGET_COLDFIRE)
5661 {
5662 if (MOTOROLA)
5663 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5664 else
5665 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5666 }
5667 else
5668 {
5669 if (MOTOROLA)
5670 #ifdef SGS_CMP_ORDER
5671 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5672 #else
5673 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5674 #endif
5675 else
5676 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5677 }
5678 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5679 CODE_LABEL_NUMBER (operands[4]));
5680 return \"\";
5681 } ")
5683 (define_insn "bne0_di"
5684 [(set (pc)
5685 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5686 (const_int 0))
5687 (label_ref (match_operand 1 "" ","))
5688 (pc)))
5689 (clobber (match_scratch:SI 2 "=d,X"))]
5690 ""
5691 "*
5692 {
5693 if ((cc_prev_status.value1
5694 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5695 || (cc_prev_status.value2
5696 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5697 {
5698 cc_status = cc_prev_status;
5699 return MOTOROLA ? \"jbne %l1\" : \"jne %l1\";
5700 }
5701 CC_STATUS_INIT;
5702 if (GET_CODE (operands[0]) == REG)
5703 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5704 else
5705 operands[3] = adjust_address (operands[0], SImode, 4);
5706 if (!ADDRESS_REG_P (operands[0]))
5707 {
5708 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5709 {
5710 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5711 {
5712 if (MOTOROLA)
5713 return \"or%.l %0,%2\;jbne %l1\";
5714 else
5715 return \"or%.l %0,%2\;jne %l1\";
5716 }
5717 else
5718 {
5719 if (MOTOROLA)
5720 return \"or%.l %3,%2\;jbne %l1\";
5721 else
5722 return \"or%.l %3,%2\;jne %l1\";
5723 }
5724 }
5725 if (MOTOROLA)
5726 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5727 else
5728 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5729 }
5730 if (TARGET_68020 || TARGET_COLDFIRE)
5731 {
5732 if (MOTOROLA)
5733 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5734 else
5735 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5736 }
5737 else
5738 {
5739 if (MOTOROLA)
5740 #ifdef SGS_CMP_ORDER
5741 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5742 #else
5743 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5744 #endif
5745 else
5746 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5747 }
5748 } ")
5750 (define_insn "bge0_di"
5751 [(set (pc)
5752 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5753 (const_int 0))
5754 (label_ref (match_operand 1 "" ""))
5755 (pc)))]
5756 ""
5757 "*
5758 {
5759 if ((cc_prev_status.value1
5760 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5761 || (cc_prev_status.value2
5762 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5763 {
5764 cc_status = cc_prev_status;
5765 if (cc_status.flags & CC_REVERSED)
5766 {
5767 return MOTOROLA ? \"jble %l1\" : \"jle %l1\";
5768 }
5769 else
5770 {
5771 return MOTOROLA ? \"jbpl %l1\" : \"jpl %l1\";
5772 }
5773 }
5774 CC_STATUS_INIT;
5775 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
5776 output_asm_insn(\"tst%.l %0\", operands);
5777 else
5778 {
5779 /* On an address reg, cmpw may replace cmpl. */
5780 #ifdef SGS_CMP_ORDER
5781 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5782 #else
5783 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5784 #endif
5785 }
5787 return MOTOROLA ? \"jbpl %l1\" : \"jpl %l1\";
5788 } ")
5790 (define_insn "blt0_di"
5791 [(set (pc)
5792 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5793 (const_int 0))
5794 (label_ref (match_operand 1 "" ""))
5795 (pc)))]
5796 ""
5797 "*
5798 {
5799 if ((cc_prev_status.value1
5800 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5801 || (cc_prev_status.value2
5802 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5803 {
5804 cc_status = cc_prev_status;
5805 if (cc_status.flags & CC_REVERSED)
5806 {
5807 return MOTOROLA ? \"jbgt %l1\" : \"jgt %l1\";
5808 }
5809 else
5810 {
5811 return MOTOROLA ? \"jbmi %l1\" : \"jmi %l1\";
5812 }
5813 }
5814 CC_STATUS_INIT;
5815 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
5816 output_asm_insn(\"tst%.l %0\", operands);
5817 else
5818 {
5819 /* On an address reg, cmpw may replace cmpl. */
5820 #ifdef SGS_CMP_ORDER
5821 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5822 #else
5823 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5824 #endif
5825 }
5827 return MOTOROLA ? \"jbmi %l1\" : \"jmi %l1\";
5828 } ")
5830 (define_insn "beq"
5831 [(set (pc)
5832 (if_then_else (eq (cc0)
5833 (const_int 0))
5834 (label_ref (match_operand 0 "" ""))
5835 (pc)))]
5836 ""
5837 "*
5838 {
5839 if (MOTOROLA)
5840 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5841 else
5842 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5843 }")
5845 (define_insn "bne"
5846 [(set (pc)
5847 (if_then_else (ne (cc0)
5848 (const_int 0))
5849 (label_ref (match_operand 0 "" ""))
5850 (pc)))]
5851 ""
5852 "*
5853 {
5854 if (MOTOROLA)
5855 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5856 else
5857 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5858 }")
5860 (define_insn "bgt"
5861 [(set (pc)
5862 (if_then_else (gt (cc0)
5863 (const_int 0))
5864 (label_ref (match_operand 0 "" ""))
5865 (pc)))]
5866 ""
5867 "*
5868 if (MOTOROLA)
5869 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5870 else
5871 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5872 ")
5874 (define_insn "bgtu"
5875 [(set (pc)
5876 (if_then_else (gtu (cc0)
5877 (const_int 0))
5878 (label_ref (match_operand 0 "" ""))
5879 (pc)))]
5880 ""
5881 "*
5882 return MOTOROLA ? \"jbhi %l0\" : \"jhi %l0\";
5883 ")
5885 (define_insn "blt"
5886 [(set (pc)
5887 (if_then_else (lt (cc0)
5888 (const_int 0))
5889 (label_ref (match_operand 0 "" ""))
5890 (pc)))]
5891 ""
5892 "*
5893 if (MOTOROLA)
5894 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
5895 else
5896 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
5897 ")
5899 (define_insn "bltu"
5900 [(set (pc)
5901 (if_then_else (ltu (cc0)
5902 (const_int 0))
5903 (label_ref (match_operand 0 "" ""))
5904 (pc)))]
5905 ""
5906 "*
5907 return MOTOROLA ? \"jbcs %l0\" : \"jcs %l0\";
5908 ")
5910 (define_insn "bge"
5911 [(set (pc)
5912 (if_then_else (ge (cc0)
5913 (const_int 0))
5914 (label_ref (match_operand 0 "" ""))
5915 (pc)))]
5916 ""
5917 "*
5918 if (MOTOROLA)
5919 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
5920 else
5921 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
5922 ")
5924 (define_insn "bgeu"
5925 [(set (pc)
5926 (if_then_else (geu (cc0)
5927 (const_int 0))
5928 (label_ref (match_operand 0 "" ""))
5929 (pc)))]
5930 ""
5931 "*
5932 return MOTOROLA ? \"jbcc %l0\" : \"jcc %l0\";
5933 ")
5935 (define_insn "ble"
5936 [(set (pc)
5937 (if_then_else (le (cc0)
5938 (const_int 0))
5939 (label_ref (match_operand 0 "" ""))
5940 (pc)))]
5941 ""
5942 "*
5943 if (MOTOROLA)
5944 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
5945 else
5946 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
5947 ")
5949 (define_insn "bleu"
5950 [(set (pc)
5951 (if_then_else (leu (cc0)
5952 (const_int 0))
5953 (label_ref (match_operand 0 "" ""))
5954 (pc)))]
5955 ""
5956 "*
5957 return MOTOROLA ? \"jbls %l0\" : \"jls %l0\";
5958 ")
5960 (define_insn "bordered"
5961 [(set (pc)
5962 (if_then_else (ordered (cc0) (const_int 0))
5963 (label_ref (match_operand 0 "" ""))
5964 (pc)))]
5965 "TARGET_68881"
5966 {
5967 if (!(cc_prev_status.flags & CC_IN_68881))
5968 abort ();
5969 return MOTOROLA ? "fbor %l0" : "fjor %l0";
5970 })
5972 (define_insn "bunordered"
5973 [(set (pc)
5974 (if_then_else (unordered (cc0) (const_int 0))
5975 (label_ref (match_operand 0 "" ""))
5976 (pc)))]
5977 "TARGET_68881"
5978 {
5979 if (!(cc_prev_status.flags & CC_IN_68881))
5980 abort ();
5981 return MOTOROLA ? "fbun %l0" : "fjun %l0";
5982 })
5984 (define_insn "buneq"
5985 [(set (pc)
5986 (if_then_else (uneq (cc0) (const_int 0))
5987 (label_ref (match_operand 0 "" ""))
5988 (pc)))]
5989 "TARGET_68881"
5990 {
5991 if (!(cc_prev_status.flags & CC_IN_68881))
5992 abort ();
5993 return MOTOROLA ? "fbueq %l0" : "fjueq %l0";
5994 })
5996 (define_insn "bunge"
5997 [(set (pc)
5998 (if_then_else (unge (cc0) (const_int 0))
5999 (label_ref (match_operand 0 "" ""))
6000 (pc)))]
6001 "TARGET_68881"
6002 {
6003 if (!(cc_prev_status.flags & CC_IN_68881))
6004 abort ();
6005 return MOTOROLA ? "fbuge %l0" : "fjuge %l0";
6006 })
6008 (define_insn "bungt"
6009 [(set (pc)
6010 (if_then_else (ungt (cc0) (const_int 0))
6011 (label_ref (match_operand 0 "" ""))
6012 (pc)))]
6013 "TARGET_68881"
6014 {
6015 if (!(cc_prev_status.flags & CC_IN_68881))
6016 abort ();
6017 return MOTOROLA ? "fbugt %l0" : "fjugt %l0";
6018 })
6020 (define_insn "bunle"
6021 [(set (pc)
6022 (if_then_else (unle (cc0) (const_int 0))
6023 (label_ref (match_operand 0 "" ""))
6024 (pc)))]
6025 "TARGET_68881"
6026 {
6027 if (!(cc_prev_status.flags & CC_IN_68881))
6028 abort ();
6029 return MOTOROLA ? "fbule %l0" : "fjule %l0";
6030 })
6032 (define_insn "bunlt"
6033 [(set (pc)
6034 (if_then_else (unlt (cc0) (const_int 0))
6035 (label_ref (match_operand 0 "" ""))
6036 (pc)))]
6037 "TARGET_68881"
6038 {
6039 if (!(cc_prev_status.flags & CC_IN_68881))
6040 abort ();
6041 return MOTOROLA ? "fbult %l0" : "fjult %l0";
6042 })
6044 (define_insn "bltgt"
6045 [(set (pc)
6046 (if_then_else (ltgt (cc0) (const_int 0))
6047 (label_ref (match_operand 0 "" ""))
6048 (pc)))]
6049 "TARGET_68881"
6050 {
6051 if (!(cc_prev_status.flags & CC_IN_68881))
6052 abort ();
6053 return MOTOROLA ? "fbogl %l0" : "fjogl %l0";
6054 })
6055 \f
6056 ;; Negated conditional jump instructions.
6058 (define_insn ""
6059 [(set (pc)
6060 (if_then_else (eq (cc0)
6061 (const_int 0))
6062 (pc)
6063 (label_ref (match_operand 0 "" ""))))]
6064 ""
6065 "*
6066 {
6067 if (MOTOROLA)
6068 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6069 else
6070 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6071 }")
6073 (define_insn ""
6074 [(set (pc)
6075 (if_then_else (ne (cc0)
6076 (const_int 0))
6077 (pc)
6078 (label_ref (match_operand 0 "" ""))))]
6079 ""
6080 "*
6081 {
6082 if (MOTOROLA)
6083 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6084 else
6085 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6086 }")
6088 (define_insn ""
6089 [(set (pc)
6090 (if_then_else (gt (cc0)
6091 (const_int 0))
6092 (pc)
6093 (label_ref (match_operand 0 "" ""))))]
6094 ""
6095 "*
6096 if (MOTOROLA)
6097 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6098 else
6099 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6100 ")
6102 (define_insn ""
6103 [(set (pc)
6104 (if_then_else (gtu (cc0)
6105 (const_int 0))
6106 (pc)
6107 (label_ref (match_operand 0 "" ""))))]
6108 ""
6109 "*
6110 return MOTOROLA ? \"jbls %l0\" : \"jls %l0\";
6111 ")
6113 (define_insn ""
6114 [(set (pc)
6115 (if_then_else (lt (cc0)
6116 (const_int 0))
6117 (pc)
6118 (label_ref (match_operand 0 "" ""))))]
6119 ""
6120 "*
6121 if (MOTOROLA)
6122 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6123 else
6124 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6125 ")
6127 (define_insn ""
6128 [(set (pc)
6129 (if_then_else (ltu (cc0)
6130 (const_int 0))
6131 (pc)
6132 (label_ref (match_operand 0 "" ""))))]
6133 ""
6134 "*
6135 return MOTOROLA ? \"jbcc %l0\" : \"jcc %l0\";
6136 ")
6138 (define_insn ""
6139 [(set (pc)
6140 (if_then_else (ge (cc0)
6141 (const_int 0))
6142 (pc)
6143 (label_ref (match_operand 0 "" ""))))]
6144 ""
6145 "*
6146 if (MOTOROLA)
6147 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6148 else
6149 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6150 ")
6152 (define_insn ""
6153 [(set (pc)
6154 (if_then_else (geu (cc0)
6155 (const_int 0))
6156 (pc)
6157 (label_ref (match_operand 0 "" ""))))]
6158 ""
6159 "*
6160 return MOTOROLA ? \"jbcs %l0\" : \"jcs %l0\";
6161 ")
6163 (define_insn ""
6164 [(set (pc)
6165 (if_then_else (le (cc0)
6166 (const_int 0))
6167 (pc)
6168 (label_ref (match_operand 0 "" ""))))]
6169 ""
6170 "*
6171 if (MOTOROLA)
6172 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6173 else
6174 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6175 ")
6177 (define_insn ""
6178 [(set (pc)
6179 (if_then_else (leu (cc0)
6180 (const_int 0))
6181 (pc)
6182 (label_ref (match_operand 0 "" ""))))]
6183 ""
6184 "*
6185 return MOTOROLA ? \"jbhi %l0\" : \"jhi %l0\";
6186 ")
6188 (define_insn "*bordered_rev"
6189 [(set (pc)
6190 (if_then_else (ordered (cc0) (const_int 0))
6191 (pc)
6192 (label_ref (match_operand 0 "" ""))))]
6193 "TARGET_68881"
6194 {
6195 if (!(cc_prev_status.flags & CC_IN_68881))
6196 abort ();
6197 return MOTOROLA ? "fbun %l0" : "fjun %l0";
6198 })
6200 (define_insn "*bunordered_rev"
6201 [(set (pc)
6202 (if_then_else (unordered (cc0) (const_int 0))
6203 (pc)
6204 (label_ref (match_operand 0 "" ""))))]
6205 "TARGET_68881"
6206 {
6207 if (!(cc_prev_status.flags & CC_IN_68881))
6208 abort ();
6209 return MOTOROLA ? "fbor %l0" : "fjor %l0";
6210 })
6212 (define_insn "*buneq_rev"
6213 [(set (pc)
6214 (if_then_else (uneq (cc0) (const_int 0))
6215 (pc)
6216 (label_ref (match_operand 0 "" ""))))]
6217 "TARGET_68881"
6218 {
6219 if (!(cc_prev_status.flags & CC_IN_68881))
6220 abort ();
6221 return MOTOROLA ? "fbogl %l0" : "fjogl %l0";
6222 })
6224 (define_insn "*bunge_rev"
6225 [(set (pc)
6226 (if_then_else (unge (cc0) (const_int 0))
6227 (pc)
6228 (label_ref (match_operand 0 "" ""))))]
6229 "TARGET_68881"
6230 {
6231 if (!(cc_prev_status.flags & CC_IN_68881))
6232 abort ();
6233 return MOTOROLA ? "fbolt %l0" : "fjolt %l0";
6234 })
6236 (define_insn "*bunle_rev"
6237 [(set (pc)
6238 (if_then_else (unle (cc0) (const_int 0))
6239 (pc)
6240 (label_ref (match_operand 0 "" ""))))]
6241 "TARGET_68881"
6242 {
6243 if (!(cc_prev_status.flags & CC_IN_68881))
6244 abort ();
6245 return MOTOROLA ? "fbogt %l0" : "fjogt %l0";
6246 })
6248 (define_insn "*bunlt_rev"
6249 [(set (pc)
6250 (if_then_else (unlt (cc0) (const_int 0))
6251 (pc)
6252 (label_ref (match_operand 0 "" ""))))]
6253 "TARGET_68881"
6254 {
6255 if (!(cc_prev_status.flags & CC_IN_68881))
6256 abort ();
6257 return MOTOROLA ? "fboge %l0" : "fjoge %l0";
6258 })
6260 (define_insn "*bltgt_rev"
6261 [(set (pc)
6262 (if_then_else (ltgt (cc0) (const_int 0))
6263 (pc)
6264 (label_ref (match_operand 0 "" ""))))]
6265 "TARGET_68881"
6266 {
6267 if (!(cc_prev_status.flags & CC_IN_68881))
6268 abort ();
6269 return MOTOROLA ? "fbueq %l0" : "fjueq %l0";
6270 })
6271 \f
6272 ;; Unconditional and other jump instructions
6273 (define_insn "jump"
6274 [(set (pc)
6275 (label_ref (match_operand 0 "" "")))]
6276 ""
6277 "*
6278 return MOTOROLA ? \"jbra %l0\" : \"jra %l0\";
6279 ")
6281 ;; We support two different ways of handling dispatch tables.
6282 ;; The NeXT uses absolute tables, and other machines use relative.
6283 ;; This define_expand can generate either kind.
6284 (define_expand "tablejump"
6285 [(parallel [(set (pc) (match_operand 0 "" ""))
6286 (use (label_ref (match_operand 1 "" "")))])]
6287 ""
6288 "
6289 {
6290 #ifdef CASE_VECTOR_PC_RELATIVE
6291 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6292 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6293 #endif
6294 }")
6296 ;; Jump to variable address from dispatch table of absolute addresses.
6297 (define_insn ""
6298 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6299 (use (label_ref (match_operand 1 "" "")))]
6300 ""
6301 "*
6302 return MOTOROLA ? \"jmp (%0)\" : \"jmp %0@\";
6303 ")
6305 ;; Jump to variable address from dispatch table of relative addresses.
6306 (define_insn ""
6307 [(set (pc)
6308 (plus:SI (pc)
6309 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6310 (use (label_ref (match_operand 1 "" "")))]
6311 ""
6312 "*
6313 #ifdef ASM_RETURN_CASE_JUMP
6314 ASM_RETURN_CASE_JUMP;
6315 #else
6316 #ifdef SGS
6317 #ifdef ASM_OUTPUT_CASE_LABEL
6318 if (TARGET_COLDFIRE)
6319 {
6320 if (ADDRESS_REG_P (operands[0]))
6321 return \"jmp 6(%%pc,%0.l)\";
6322 else
6323 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6324 }
6325 else
6326 return \"jmp 6(%%pc,%0.w)\";
6327 #else
6328 if (TARGET_COLDFIRE)
6329 {
6330 if (ADDRESS_REG_P (operands[0]))
6331 return \"jmp 2(%%pc,%0.l)\";
6332 else
6333 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6334 }
6335 else
6336 return \"jmp 2(%%pc,%0.w)\";
6337 #endif
6338 #else /* not SGS */
6339 if (TARGET_COLDFIRE)
6340 {
6341 if (ADDRESS_REG_P (operands[0]))
6342 {
6343 return MOTOROLA ? \"jmp (2,pc,%0.l)\" : \"jmp pc@(2,%0:l)\";
6344 }
6345 else if (MOTOROLA)
6346 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6347 else
6348 return \"extl %0\;jmp pc@(2,%0:l)\";
6349 }
6350 else
6351 {
6352 return MOTOROLA ? \"jmp (2,pc,%0.w)\" : \"jmp pc@(2,%0:w)\";
6353 }
6354 #endif
6355 #endif
6356 ")
6358 ;; Decrement-and-branch insns.
6359 (define_insn ""
6360 [(set (pc)
6361 (if_then_else
6362 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
6363 (const_int 0))
6364 (label_ref (match_operand 1 "" ""))
6365 (pc)))
6366 (set (match_dup 0)
6367 (plus:HI (match_dup 0)
6368 (const_int -1)))]
6369 "!TARGET_COLDFIRE"
6370 "*
6371 {
6372 CC_STATUS_INIT;
6373 if (DATA_REG_P (operands[0]))
6374 return \"dbra %0,%l1\";
6375 if (GET_CODE (operands[0]) == MEM)
6376 {
6377 if (MOTOROLA)
6378 return \"subq%.w %#1,%0\;jbcc %l1\";
6379 else
6380 return \"subqw %#1,%0\;jcc %l1\";
6381 }
6382 if (MOTOROLA)
6383 #ifdef SGS_CMP_ORDER
6384 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6385 #else /* not SGS_CMP_ORDER */
6386 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6387 #endif
6388 else
6389 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6390 }")
6392 (define_insn ""
6393 [(set (pc)
6394 (if_then_else
6395 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
6396 (const_int 0))
6397 (label_ref (match_operand 1 "" ""))
6398 (pc)))
6399 (set (match_dup 0)
6400 (plus:SI (match_dup 0)
6401 (const_int -1)))]
6402 "!TARGET_COLDFIRE"
6403 "*
6404 {
6405 CC_STATUS_INIT;
6406 if (MOTOROLA)
6407 {
6408 if (DATA_REG_P (operands[0]))
6409 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6410 if (GET_CODE (operands[0]) == MEM)
6411 return \"subq%.l %#1,%0\;jbcc %l1\";
6412 #ifdef SGS_CMP_ORDER
6413 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6414 #else /* not SGS_CMP_ORDER */
6415 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6416 #endif /* not SGS_CMP_ORDER */
6417 }
6418 else
6419 {
6420 if (DATA_REG_P (operands[0]))
6421 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6422 if (GET_CODE (operands[0]) == MEM)
6423 return \"subql %#1,%0\;jcc %l1\";
6424 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6425 }
6426 }")
6428 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6430 (define_insn ""
6431 [(set (pc)
6432 (if_then_else
6433 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
6434 (const_int -1))
6435 (const_int 0))
6436 (label_ref (match_operand 1 "" ""))
6437 (pc)))
6438 (set (match_dup 0)
6439 (plus:HI (match_dup 0)
6440 (const_int -1)))]
6441 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6442 "*
6443 {
6444 CC_STATUS_INIT;
6445 if (MOTOROLA)
6446 {
6447 if (DATA_REG_P (operands[0]))
6448 return \"dbra %0,%l1\";
6449 if (GET_CODE (operands[0]) == MEM)
6450 return \"subq%.w %#1,%0\;jbcc %l1\";
6451 #ifdef SGS_CMP_ORDER
6452 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6453 #else /* not SGS_CMP_ORDER */
6454 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6455 #endif /* not SGS_CMP_ORDER */
6456 }
6457 else
6458 {
6459 if (DATA_REG_P (operands[0]))
6460 return \"dbra %0,%l1\";
6461 if (GET_CODE (operands[0]) == MEM)
6462 return \"subqw %#1,%0\;jcc %l1\";
6463 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6464 }
6465 }")
6467 (define_expand "decrement_and_branch_until_zero"
6468 [(parallel [(set (pc)
6469 (if_then_else
6470 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
6471 (const_int -1))
6472 (const_int 0))
6473 (label_ref (match_operand 1 "" ""))
6474 (pc)))
6475 (set (match_dup 0)
6476 (plus:SI (match_dup 0)
6477 (const_int -1)))])]
6478 ""
6479 "")
6481 (define_insn ""
6482 [(set (pc)
6483 (if_then_else
6484 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
6485 (const_int -1))
6486 (const_int 0))
6487 (label_ref (match_operand 1 "" ""))
6488 (pc)))
6489 (set (match_dup 0)
6490 (plus:SI (match_dup 0)
6491 (const_int -1)))]
6492 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6493 "*
6494 {
6495 CC_STATUS_INIT;
6496 if (MOTOROLA)
6497 {
6498 if (DATA_REG_P (operands[0]))
6499 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6500 if (GET_CODE (operands[0]) == MEM)
6501 return \"subq%.l %#1,%0\;jbcc %l1\";
6502 #ifdef SGS_CMP_ORDER
6503 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6504 #else /* not SGS_CMP_ORDER */
6505 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6506 #endif /* not SGS_CMP_ORDER */
6507 }
6508 else
6509 {
6510 if (DATA_REG_P (operands[0]))
6511 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6512 if (GET_CODE (operands[0]) == MEM)
6513 return \"subql %#1,%0\;jcc %l1\";
6514 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6515 }
6516 }")
6519 ;; For PIC calls, in order to be able to support
6520 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6521 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6522 ;;
6523 ;; PIC calls are handled by loading the address of the function into a
6524 ;; register (via movsi), then emitting a register indirect call using
6525 ;; the "jsr" function call syntax.
6526 ;;
6527 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6528 ;; operand to the jbsr statement to indicate that this call should
6529 ;; go through the PLT (why? because this is the way that Sun does it).
6530 ;;
6531 ;; We have different patterns for PIC calls and non-PIC calls. The
6532 ;; different patterns are only used to choose the right syntax.
6533 ;;
6534 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6535 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6536 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6537 ;; section at link time. However, all global objects reference are still
6538 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6539 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6540 ;; We need to have a way to differentiate these two different operands.
6541 ;;
6542 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6543 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6544 ;; to be changed to recognize function calls symbol_ref operand as a valid
6545 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6546 ;; avoid the compiler to load this symbol_ref operand into a register.
6547 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6548 ;; since the value is a PC relative offset, not a real address.
6549 ;;
6550 ;; All global objects are treated in the similar way as in SUN3. The only
6551 ;; difference is: on m68k svr4, the reference of such global object needs
6552 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6553 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6554 ;; m68k.c.
6556 ;; Call subroutine with no return value.
6557 (define_expand "call"
6558 [(call (match_operand:QI 0 "memory_operand" "")
6559 (match_operand:SI 1 "general_operand" ""))]
6560 ;; Operand 1 not really used on the m68000.
6562 ""
6563 "
6564 {
6565 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6566 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6567 }")
6569 ;; This is a normal call sequence.
6570 (define_insn ""
6571 [(call (match_operand:QI 0 "memory_operand" "o")
6572 (match_operand:SI 1 "general_operand" "g"))]
6573 ;; Operand 1 not really used on the m68000.
6575 "! flag_pic"
6576 "*
6577 #if MOTOROLA && !defined (USE_GAS)
6578 return \"jsr %0\";
6579 #else
6580 return \"jbsr %0\";
6581 #endif
6582 ")
6584 ;; This is a PIC call sequence.
6585 (define_insn ""
6586 [(call (match_operand:QI 0 "memory_operand" "o")
6587 (match_operand:SI 1 "general_operand" "g"))]
6588 ;; Operand 1 not really used on the m68000.
6590 "flag_pic"
6591 "*
6592 m68k_output_pic_call(operands[0]);
6593 return \"\";
6594 ")
6596 ;; Call subroutine, returning value in operand 0
6597 ;; (which must be a hard register).
6598 ;; See comments before "call" regarding PIC calls.
6599 (define_expand "call_value"
6600 [(set (match_operand 0 "" "")
6601 (call (match_operand:QI 1 "memory_operand" "")
6602 (match_operand:SI 2 "general_operand" "")))]
6603 ;; Operand 2 not really used on the m68000.
6604 ""
6605 "
6606 {
6607 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6608 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6609 }")
6611 ;; This is a normal call_value
6612 (define_insn ""
6613 [(set (match_operand 0 "" "=rf")
6614 (call (match_operand:QI 1 "memory_operand" "o")
6615 (match_operand:SI 2 "general_operand" "g")))]
6616 ;; Operand 2 not really used on the m68000.
6617 "! flag_pic"
6618 "*
6619 #if MOTOROLA && !defined (USE_GAS)
6620 return \"jsr %1\";
6621 #else
6622 return \"jbsr %1\";
6623 #endif
6624 ")
6626 ;; This is a PIC call_value
6627 (define_insn ""
6628 [(set (match_operand 0 "" "=rf")
6629 (call (match_operand:QI 1 "memory_operand" "o")
6630 (match_operand:SI 2 "general_operand" "g")))]
6631 ;; Operand 2 not really used on the m68000.
6632 "flag_pic"
6633 "*
6634 m68k_output_pic_call(operands[1]);
6635 return \"\";
6636 ")
6638 ;; Call subroutine returning any type.
6640 (define_expand "untyped_call"
6641 [(parallel [(call (match_operand 0 "" "")
6642 (const_int 0))
6643 (match_operand 1 "" "")
6644 (match_operand 2 "" "")])]
6645 "NEEDS_UNTYPED_CALL"
6646 "
6647 {
6648 int i;
6650 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6652 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6653 {
6654 rtx set = XVECEXP (operands[2], 0, i);
6655 emit_move_insn (SET_DEST (set), SET_SRC (set));
6656 }
6658 /* The optimizer does not know that the call sets the function value
6659 registers we stored in the result block. We avoid problems by
6660 claiming that all hard registers are used and clobbered at this
6661 point. */
6662 emit_insn (gen_blockage ());
6664 DONE;
6665 }")
6667 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6668 ;; all of memory. This blocks insns from being moved across this point.
6670 (define_insn "blockage"
6671 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6672 ""
6673 "")
6675 (define_insn "nop"
6676 [(const_int 0)]
6677 ""
6678 "nop")
6680 ;; Used for frameless functions which save no regs and allocate no locals.
6681 (define_insn "return"
6682 [(return)]
6683 "USE_RETURN_INSN"
6684 "*
6685 {
6686 if (current_function_pops_args == 0)
6687 return \"rts\";
6688 operands[0] = GEN_INT (current_function_pops_args);
6689 return \"rtd %0\";
6690 }")
6692 (define_insn "indirect_jump"
6693 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6694 ""
6695 "jmp %a0")
6696 \f
6697 ;; This should not be used unless the add/sub insns can't be.
6699 (define_insn ""
6700 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
6701 (match_operand:QI 1 "address_operand" "p"))]
6702 ""
6703 "*
6704 {
6705 /* Recognize an insn that refers to a table of offsets. Such an insn will
6706 need to refer to a label on the insn. So output one. Use the
6707 label-number of the table of offsets to generate this label. This code,
6708 and similar code above, assumes that there will be at most one reference
6709 to each table. */
6710 if (GET_CODE (operands[1]) == PLUS
6711 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6712 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6713 {
6714 rtx labelref = XEXP (operands[1], 1);
6715 #if MOTOROLA && !defined (SGS_SWITCH_TABLES)
6716 #ifdef SGS
6717 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6718 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6719 #else /* not SGS */
6720 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6721 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6722 #endif /* not SGS */
6723 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6724 (*targetm.asm_out.internal_label) (asm_out_file, \"LI\",
6725 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6726 #ifdef SGS_SWITCH_TABLES
6727 /* Set flag saying we need to define the symbol
6728 LD%n (with value L%n-LI%n) at the end of the switch table. */
6729 switch_table_difference_label_flag = 1;
6730 #endif /* SGS_SWITCH_TABLES */
6731 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6732 }
6734 return \"lea %a1,%0\";
6735 }")
6736 \f
6737 ;; This is the first machine-dependent peephole optimization.
6738 ;; It is useful when a floating value is returned from a function call
6739 ;; and then is moved into an FP register.
6740 ;; But it is mainly intended to test the support for these optimizations.
6742 (define_peephole
6743 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6744 (set (match_operand:DF 0 "register_operand" "=f")
6745 (match_operand:DF 1 "register_operand" "ad"))]
6746 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6747 "*
6748 {
6749 rtx xoperands[2];
6750 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6751 output_asm_insn (\"move%.l %1,%@\", xoperands);
6752 output_asm_insn (\"move%.l %1,%-\", operands);
6753 return \"fmove%.d %+,%0\";
6754 }
6755 ")
6757 ;; Optimize a stack-adjust followed by a push of an argument.
6758 ;; This is said to happen frequently with -msoft-float
6759 ;; when there are consecutive library calls.
6761 (define_peephole
6762 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6763 (match_operand:SI 0 "const_int_operand" "n")))
6764 (set (match_operand:SF 1 "push_operand" "=m")
6765 (match_operand:SF 2 "general_operand" "rmfF"))]
6766 "INTVAL (operands[0]) >= 4
6767 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6768 "*
6769 {
6770 if (INTVAL (operands[0]) > 4)
6771 {
6772 rtx xoperands[2];
6773 xoperands[0] = stack_pointer_rtx;
6774 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
6775 if (INTVAL (xoperands[1]) <= 8)
6776 {
6777 if (!TARGET_COLDFIRE)
6778 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6779 else
6780 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6781 }
6782 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6783 {
6784 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
6785 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6786 }
6787 else if (INTVAL (xoperands[1]) <= 0x7FFF)
6788 {
6789 if (TARGET_68040)
6790 output_asm_insn (\"add%.w %1,%0\", xoperands);
6791 else if (MOTOROLA)
6792 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6793 else
6794 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6795 }
6796 else
6797 output_asm_insn (\"add%.l %1,%0\", xoperands);
6798 }
6799 if (FP_REG_P (operands[2]))
6800 return \"fmove%.s %2,%@\";
6801 return \"move%.l %2,%@\";
6802 }")
6804 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6806 (define_peephole
6807 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6808 (match_operand:SI 0 "const_int_operand" "n")))
6809 (set (match_operand:SI 1 "push_operand" "=m")
6810 (match_operand:SI 2 "general_operand" "g"))]
6811 "INTVAL (operands[0]) >= 4
6812 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6813 "*
6814 {
6815 if (INTVAL (operands[0]) > 4)
6816 {
6817 rtx xoperands[2];
6818 xoperands[0] = stack_pointer_rtx;
6819 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
6820 if (INTVAL (xoperands[1]) <= 8)
6821 {
6822 if (!TARGET_COLDFIRE)
6823 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6824 else
6825 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6826 }
6827 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6828 {
6829 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
6830 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6831 }
6832 else if (INTVAL (xoperands[1]) <= 0x7FFF)
6833 {
6834 if (TARGET_68040)
6835 output_asm_insn (\"add%.w %1,%0\", xoperands);
6836 else if (MOTOROLA)
6837 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6838 else
6839 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6840 }
6841 else
6842 output_asm_insn (\"add%.l %1,%0\", xoperands);
6843 }
6844 if (operands[2] == const0_rtx)
6845 return \"clr%.l %@\";
6846 return \"move%.l %2,%@\";
6847 }")
6849 ;; Speed up pushing a single byte but leaving four bytes of space.
6851 (define_peephole
6852 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
6853 (match_operand:QI 1 "general_operand" "dami"))
6854 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
6855 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6856 "*
6857 {
6858 rtx xoperands[4];
6860 if (GET_CODE (operands[1]) == REG)
6861 return \"move%.l %1,%-\";
6863 xoperands[1] = operands[1];
6864 xoperands[2]
6865 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
6866 xoperands[3] = stack_pointer_rtx;
6867 if (!TARGET_COLDFIRE)
6868 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
6869 else
6870 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
6871 return \"\";
6872 }")
6874 (define_peephole
6875 [(set (match_operand:SI 0 "register_operand" "=d")
6876 (const_int 0))
6877 (set (strict_low_part (subreg:HI (match_dup 0) 2))
6878 (match_operand:HI 1 "general_operand" "rmn"))]
6879 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6880 "*
6881 {
6882 if (GET_CODE (operands[1]) == CONST_INT)
6883 {
6884 if (operands[1] == const0_rtx
6885 && (DATA_REG_P (operands[0])
6886 || GET_CODE (operands[0]) == MEM)
6887 /* clr insns on 68000 read before writing.
6888 This isn't so on the 68010, but we have no TARGET_68010. */
6889 && ((TARGET_68020 || TARGET_COLDFIRE)
6890 || !(GET_CODE (operands[0]) == MEM
6891 && MEM_VOLATILE_P (operands[0]))))
6892 return \"clr%.w %0\";
6893 }
6894 return \"move%.w %1,%0\";
6895 }")
6897 ;; dbCC peepholes
6898 ;;
6899 ;; Turns
6900 ;; loop:
6901 ;; [ ... ]
6902 ;; jCC label ; abnormal loop termination
6903 ;; dbra dN, loop ; normal loop termination
6904 ;;
6905 ;; Into
6906 ;; loop:
6907 ;; [ ... ]
6908 ;; dbCC dN, loop
6909 ;; jCC label
6910 ;;
6911 ;; Which moves the jCC condition outside the inner loop for free.
6912 ;;
6914 (define_peephole
6915 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6916 [(cc0) (const_int 0)])
6917 (label_ref (match_operand 2 "" ""))
6918 (pc)))
6919 (parallel
6920 [(set (pc)
6921 (if_then_else
6922 (ne (match_operand:HI 0 "register_operand" "")
6923 (const_int 0))
6924 (label_ref (match_operand 1 "" ""))
6925 (pc)))
6926 (set (match_dup 0)
6927 (plus:HI (match_dup 0)
6928 (const_int -1)))])]
6929 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6930 "*
6931 {
6932 CC_STATUS_INIT;
6933 output_dbcc_and_branch (operands);
6934 return \"\";
6935 }")
6937 (define_peephole
6938 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6939 [(cc0) (const_int 0)])
6940 (label_ref (match_operand 2 "" ""))
6941 (pc)))
6942 (parallel
6943 [(set (pc)
6944 (if_then_else
6945 (ne (match_operand:SI 0 "register_operand" "")
6946 (const_int 0))
6947 (label_ref (match_operand 1 "" ""))
6948 (pc)))
6949 (set (match_dup 0)
6950 (plus:SI (match_dup 0)
6951 (const_int -1)))])]
6952 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6953 "*
6954 {
6955 CC_STATUS_INIT;
6956 output_dbcc_and_branch (operands);
6957 return \"\";
6958 }")
6960 (define_peephole
6961 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6962 [(cc0) (const_int 0)])
6963 (label_ref (match_operand 2 "" ""))
6964 (pc)))
6965 (parallel
6966 [(set (pc)
6967 (if_then_else
6968 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
6969 (const_int -1))
6970 (const_int 0))
6971 (label_ref (match_operand 1 "" ""))
6972 (pc)))
6973 (set (match_dup 0)
6974 (plus:HI (match_dup 0)
6975 (const_int -1)))])]
6976 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6977 "*
6978 {
6979 CC_STATUS_INIT;
6980 output_dbcc_and_branch (operands);
6981 return \"\";
6982 }")
6984 (define_peephole
6985 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6986 [(cc0) (const_int 0)])
6987 (label_ref (match_operand 2 "" ""))
6988 (pc)))
6989 (parallel
6990 [(set (pc)
6991 (if_then_else
6992 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
6993 (const_int -1))
6994 (const_int 0))
6995 (label_ref (match_operand 1 "" ""))
6996 (pc)))
6997 (set (match_dup 0)
6998 (plus:SI (match_dup 0)
6999 (const_int -1)))])]
7000 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7001 "*
7002 {
7003 CC_STATUS_INIT;
7004 output_dbcc_and_branch (operands);
7005 return \"\";
7006 }")
7008 \f
7009 (define_expand "tstxf"
7010 [(set (cc0)
7011 (match_operand:XF 0 "nonimmediate_operand" ""))]
7012 "TARGET_68881"
7013 "m68k_last_compare_had_fp_operands = 1;")
7015 (define_insn ""
7016 [(set (cc0)
7017 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7018 "TARGET_68881"
7019 "*
7020 {
7021 cc_status.flags = CC_IN_68881;
7022 return \"ftst%.x %0\";
7023 }")
7025 (define_expand "cmpxf"
7026 [(set (cc0)
7027 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7028 (match_operand:XF 1 "nonimmediate_operand" "")))]
7029 "TARGET_68881"
7030 "m68k_last_compare_had_fp_operands = 1;")
7032 (define_insn ""
7033 [(set (cc0)
7034 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7035 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7036 "TARGET_68881"
7037 "*
7038 {
7039 cc_status.flags = CC_IN_68881;
7040 #ifdef SGS_CMP_ORDER
7041 if (REG_P (operands[0]))
7042 {
7043 if (REG_P (operands[1]))
7044 return \"fcmp%.x %0,%1\";
7045 else
7046 return \"fcmp%.x %0,%f1\";
7047 }
7048 cc_status.flags |= CC_REVERSED;
7049 return \"fcmp%.x %1,%f0\";
7050 #else
7051 if (REG_P (operands[0]))
7052 {
7053 if (REG_P (operands[1]))
7054 return \"fcmp%.x %1,%0\";
7055 else
7056 return \"fcmp%.x %f1,%0\";
7057 }
7058 cc_status.flags |= CC_REVERSED;
7059 return \"fcmp%.x %f0,%1\";
7060 #endif
7061 }")
7063 (define_insn "extendsfxf2"
7064 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7065 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7066 "TARGET_68881"
7067 "*
7068 {
7069 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7070 {
7071 if (REGNO (operands[0]) == REGNO (operands[1]))
7072 {
7073 /* Extending float to double in an fp-reg is a no-op.
7074 NOTICE_UPDATE_CC has already assumed that the
7075 cc will be set. So cancel what it did. */
7076 cc_status = cc_prev_status;
7077 return \"\";
7078 }
7079 return \"f%$move%.x %1,%0\";
7080 }
7081 if (FP_REG_P (operands[0]))
7082 {
7083 if (FP_REG_P (operands[1]))
7084 return \"f%$move%.x %1,%0\";
7085 else if (ADDRESS_REG_P (operands[1]))
7086 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7087 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7088 return output_move_const_single (operands);
7089 return \"f%$move%.s %f1,%0\";
7090 }
7091 return \"fmove%.x %f1,%0\";
7092 }")
7095 (define_insn "extenddfxf2"
7096 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7097 (float_extend:XF
7098 (match_operand:DF 1 "general_operand" "f,rmE")))]
7099 "TARGET_68881"
7100 "*
7101 {
7102 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7103 {
7104 if (REGNO (operands[0]) == REGNO (operands[1]))
7105 {
7106 /* Extending float to double in an fp-reg is a no-op.
7107 NOTICE_UPDATE_CC has already assumed that the
7108 cc will be set. So cancel what it did. */
7109 cc_status = cc_prev_status;
7110 return \"\";
7111 }
7112 return \"fmove%.x %1,%0\";
7113 }
7114 if (FP_REG_P (operands[0]))
7115 {
7116 if (REG_P (operands[1]))
7117 {
7118 rtx xoperands[2];
7119 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7120 output_asm_insn (\"move%.l %1,%-\", xoperands);
7121 output_asm_insn (\"move%.l %1,%-\", operands);
7122 return \"f%&move%.d %+,%0\";
7123 }
7124 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7125 return output_move_const_double (operands);
7126 return \"f%&move%.d %f1,%0\";
7127 }
7128 return \"fmove%.x %f1,%0\";
7129 }")
7131 (define_insn "truncxfdf2"
7132 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
7133 (float_truncate:DF
7134 (match_operand:XF 1 "general_operand" "f,f")))]
7135 "TARGET_68881"
7136 "*
7137 {
7138 if (REG_P (operands[0]))
7139 {
7140 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7141 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7142 return \"move%.l %+,%0\";
7143 }
7144 return \"fmove%.d %f1,%0\";
7145 }")
7147 (define_insn "truncxfsf2"
7148 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
7149 (float_truncate:SF
7150 (match_operand:XF 1 "general_operand" "f")))]
7151 "TARGET_68881"
7152 "fmove%.s %f1,%0")
7154 (define_insn "floatsixf2"
7155 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7156 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7157 "TARGET_68881"
7158 "fmove%.l %1,%0")
7160 (define_insn "floathixf2"
7161 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7162 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7163 "TARGET_68881"
7164 "fmove%.w %1,%0")
7166 (define_insn "floatqixf2"
7167 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7168 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7169 "TARGET_68881"
7170 "fmove%.b %1,%0")
7172 (define_insn "ftruncxf2"
7173 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7174 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7175 "TARGET_68881"
7176 "*
7177 {
7178 if (FP_REG_P (operands[1]))
7179 return \"fintrz%.x %f1,%0\";
7180 return \"fintrz%.x %f1,%0\";
7181 }")
7183 (define_insn "fixxfqi2"
7184 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
7185 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7186 "TARGET_68881"
7187 "fmove%.b %1,%0")
7189 (define_insn "fixxfhi2"
7190 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
7191 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7192 "TARGET_68881"
7193 "fmove%.w %1,%0")
7195 (define_insn "fixxfsi2"
7196 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
7197 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7198 "TARGET_68881"
7199 "fmove%.l %1,%0")
7201 (define_insn ""
7202 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7203 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7204 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7205 "TARGET_68881"
7206 "fadd%.l %2,%0")
7208 (define_insn ""
7209 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7210 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7211 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7212 "TARGET_68881"
7213 "fadd%.w %2,%0")
7215 (define_insn ""
7216 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7217 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7218 (match_operand:XF 1 "general_operand" "0")))]
7219 "TARGET_68881"
7220 "fadd%.b %2,%0")
7222 (define_insn "addxf3"
7223 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7224 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7225 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7226 "TARGET_68881"
7227 "*
7228 {
7229 if (REG_P (operands[2]))
7230 return \"fadd%.x %2,%0\";
7231 return \"fadd%.x %f2,%0\";
7232 }")
7234 (define_insn ""
7235 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7236 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7237 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7238 "TARGET_68881"
7239 "fsub%.l %2,%0")
7241 (define_insn ""
7242 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7243 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7244 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7245 "TARGET_68881"
7246 "fsub%.w %2,%0")
7248 (define_insn ""
7249 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7250 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7251 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7252 "TARGET_68881"
7253 "fsub%.b %2,%0")
7255 (define_insn "subxf3"
7256 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7257 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7258 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7259 "TARGET_68881"
7260 "*
7261 {
7262 if (REG_P (operands[2]))
7263 return \"fsub%.x %2,%0\";
7264 return \"fsub%.x %f2,%0\";
7265 }")
7267 (define_insn ""
7268 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7269 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7270 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7271 "TARGET_68881"
7272 "fmul%.l %2,%0")
7274 (define_insn ""
7275 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7276 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7277 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7278 "TARGET_68881"
7279 "fmul%.w %2,%0")
7281 (define_insn ""
7282 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7283 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7284 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7285 "TARGET_68881"
7286 "fmul%.b %2,%0")
7288 (define_insn "mulxf3"
7289 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7290 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7291 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7292 "TARGET_68881"
7293 "*
7294 {
7295 if (REG_P (operands[2]))
7296 return \"fmul%.x %2,%0\";
7297 return \"fmul%.x %f2,%0\";
7298 }")
7300 (define_insn ""
7301 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7302 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7303 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7304 "TARGET_68881"
7305 "fdiv%.l %2,%0")
7307 (define_insn ""
7308 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7309 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7310 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7311 "TARGET_68881"
7312 "fdiv%.w %2,%0")
7314 (define_insn ""
7315 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7316 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7317 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7318 "TARGET_68881"
7319 "fdiv%.b %2,%0")
7321 (define_insn "divxf3"
7322 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7323 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7324 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7325 "TARGET_68881"
7326 "*
7327 {
7328 if (REG_P (operands[2]))
7329 return \"fdiv%.x %2,%0\";
7330 return \"fdiv%.x %f2,%0\";
7331 }")
7333 (define_expand "negxf2"
7334 [(set (match_operand:XF 0 "nonimmediate_operand" "")
7335 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7336 ""
7337 "
7338 {
7339 if (!TARGET_68881)
7340 {
7341 rtx result;
7342 rtx target;
7343 rtx insns;
7345 start_sequence ();
7346 target = operand_subword (operands[0], 0, 1, XFmode);
7347 result = expand_binop (SImode, xor_optab,
7348 operand_subword_force (operands[1], 0, XFmode),
7349 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
7350 if (result == 0)
7351 abort ();
7353 if (result != target)
7354 emit_move_insn (result, target);
7356 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7357 operand_subword_force (operands[1], 1, XFmode));
7358 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7359 operand_subword_force (operands[1], 2, XFmode));
7361 insns = get_insns ();
7362 end_sequence ();
7364 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7365 DONE;
7366 }
7367 }")
7369 (define_insn "negxf2_68881"
7370 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7371 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7372 "TARGET_68881"
7373 "*
7374 {
7375 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7376 return \"fneg%.x %1,%0\";
7377 return \"fneg%.x %f1,%0\";
7378 }")
7380 (define_expand "absxf2"
7381 [(set (match_operand:XF 0 "nonimmediate_operand" "")
7382 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7383 ""
7384 "
7385 {
7386 if (!TARGET_68881)
7387 {
7388 rtx result;
7389 rtx target;
7390 rtx insns;
7392 start_sequence ();
7393 target = operand_subword (operands[0], 0, 1, XFmode);
7394 result = expand_binop (SImode, and_optab,
7395 operand_subword_force (operands[1], 0, XFmode),
7396 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
7397 if (result == 0)
7398 abort ();
7400 if (result != target)
7401 emit_move_insn (result, target);
7403 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7404 operand_subword_force (operands[1], 1, XFmode));
7405 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7406 operand_subword_force (operands[1], 2, XFmode));
7408 insns = get_insns ();
7409 end_sequence ();
7411 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7412 DONE;
7413 }
7414 }")
7416 (define_insn "absxf2_68881"
7417 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7418 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7419 "TARGET_68881"
7420 "*
7421 {
7422 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7423 return \"fabs%.x %1,%0\";
7424 return \"fabs%.x %f1,%0\";
7425 }")
7427 (define_insn "sqrtxf2"
7428 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7429 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7430 "TARGET_68881"
7431 "fsqrt%.x %1,%0")
7433 (define_insn "sinsf2"
7434 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
7435 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_SIN))]
7436 "TARGET_68881 && flag_unsafe_math_optimizations"
7437 "*
7438 {
7439 if (FP_REG_P (operands[1]))
7440 return \"fsin%.x %1,%0\";
7441 else
7442 return \"fsin%.s %1,%0\";
7443 }")
7445 (define_insn "sindf2"
7446 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
7447 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_SIN))]
7448 "TARGET_68881 && flag_unsafe_math_optimizations"
7449 "*
7450 {
7451 if (FP_REG_P (operands[1]))
7452 return \"fsin%.x %1,%0\";
7453 else
7454 return \"fsin%.d %1,%0\";
7455 }")
7457 (define_insn "sinxf2"
7458 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7459 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_SIN))]
7460 "TARGET_68881 && flag_unsafe_math_optimizations"
7461 "fsin%.x %1,%0")
7463 (define_insn "cossf2"
7464 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
7465 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_COS))]
7466 "TARGET_68881 && flag_unsafe_math_optimizations"
7467 "*
7468 {
7469 if (FP_REG_P (operands[1]))
7470 return \"fcos%.x %1,%0\";
7471 else
7472 return \"fcos%.s %1,%0\";
7473 }")
7475 (define_insn "cosdf2"
7476 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
7477 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_COS))]
7478 "TARGET_68881 && flag_unsafe_math_optimizations"
7479 "*
7480 {
7481 if (FP_REG_P (operands[1]))
7482 return \"fcos%.x %1,%0\";
7483 else
7484 return \"fcos%.d %1,%0\";
7485 }")
7487 (define_insn "cosxf2"
7488 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7489 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_COS))]
7490 "TARGET_68881 && flag_unsafe_math_optimizations"
7491 "fcos%.x %1,%0")
7493 (define_insn "trap"
7494 [(trap_if (const_int -1) (const_int 7))]
7495 ""
7496 "trap %#7")
7498 (define_insn "conditional_trap"
7499 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7500 [(cc0) (const_int 0)])
7501 (match_operand:SI 1 "const_int_operand" "I"))]
7502 "TARGET_68020 && ! flags_in_68881 ()"
7503 "*
7504 {
7505 switch (GET_CODE (operands[0]))
7506 {
7507 case EQ: return \"trapeq\";
7508 case NE: return \"trapne\";
7509 case GT: return \"trapgt\";
7510 case GTU: return \"traphi\";
7511 case LT: return \"traplt\";
7512 case LTU: return \"trapcs\";
7513 case GE: return \"trapge\";
7514 case GEU: return \"trapcc\";
7515 case LE: return \"traple\";
7516 case LEU: return \"trapls\";
7517 default: abort();
7518 }
7519 }")