1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Steven McGeady, Intel Corp.
5 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
6 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
47 #include "target-def.h"
49 static void i960_output_function_prologue (FILE *, HOST_WIDE_INT
);
50 static void i960_output_function_epilogue (FILE *, HOST_WIDE_INT
);
51 static void i960_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
53 static bool i960_rtx_costs (rtx
, int, int, int *);
54 static int i960_address_cost (rtx
);
55 static tree
i960_build_builtin_va_list (void);
57 /* Save the operands last given to a compare for use when we
58 generate a scc or bcc insn. */
60 rtx i960_compare_op0
, i960_compare_op1
;
62 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
65 int i960_maxbitalignment
;
66 int i960_last_maxbitalignment
;
68 /* Used to implement switching between MEM and ALU insn types, for better
69 C series performance. */
71 enum insn_types i960_last_insn_type
;
73 /* The leaf-procedure return register. Set only if this is a leaf routine. */
75 static int i960_leaf_ret_reg
;
77 /* True if replacing tail calls with jumps is OK. */
79 static int tail_call_ok
;
81 /* A string containing a list of insns to emit in the epilogue so as to
82 restore all registers saved by the prologue. Created by the prologue
83 code as it saves registers away. */
85 char epilogue_string
[1000];
87 /* A unique number (per function) for return labels. */
89 static int ret_label
= 0;
91 /* This is true if FNDECL is either a varargs or a stdarg function.
92 This is used to help identify functions that use an argument block. */
94 #define VARARGS_STDARG_FUNCTION(FNDECL) \
95 (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
96 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL))))) \
99 /* Initialize the GCC target structure. */
100 #undef TARGET_ASM_ALIGNED_SI_OP
101 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
103 #undef TARGET_ASM_FUNCTION_PROLOGUE
104 #define TARGET_ASM_FUNCTION_PROLOGUE i960_output_function_prologue
105 #undef TARGET_ASM_FUNCTION_EPILOGUE
106 #define TARGET_ASM_FUNCTION_EPILOGUE i960_output_function_epilogue
108 #undef TARGET_ASM_OUTPUT_MI_THUNK
109 #define TARGET_ASM_OUTPUT_MI_THUNK i960_output_mi_thunk
110 #undef TARGET_CAN_ASM_OUTPUT_MI_THUNK
111 #define TARGET_CAN_ASM_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
113 #undef TARGET_RTX_COSTS
114 #define TARGET_RTX_COSTS i960_rtx_costs
115 #undef TARGET_ADDRESS_COST
116 #define TARGET_ADDRESS_COST i960_address_cost
118 #undef TARGET_BUILD_BUILTIN_VA_LIST
119 #define TARGET_BUILD_BUILTIN_VA_LIST i960_build_builtin_va_list
121 struct gcc_target targetm
= TARGET_INITIALIZER
;
123 /* Override conflicting target switch options.
124 Doesn't actually detect if more than one -mARCH option is given, but
125 does handle the case of two blatantly conflicting -mARCH options.
127 Also initialize variables before compiling any files. */
132 if (TARGET_K_SERIES
&& TARGET_C_SERIES
)
134 warning ("conflicting architectures defined - using C series");
135 target_flags
&= ~TARGET_FLAG_K_SERIES
;
137 if (TARGET_K_SERIES
&& TARGET_MC
)
139 warning ("conflicting architectures defined - using K series");
140 target_flags
&= ~TARGET_FLAG_MC
;
142 if (TARGET_C_SERIES
&& TARGET_MC
)
144 warning ("conflicting architectures defined - using C series");
145 target_flags
&= ~TARGET_FLAG_MC
;
147 if (TARGET_IC_COMPAT3_0
)
149 flag_short_enums
= 1;
150 flag_signed_char
= 1;
151 target_flags
|= TARGET_FLAG_CLEAN_LINKAGE
;
152 if (TARGET_IC_COMPAT2_0
)
154 warning ("iC2.0 and iC3.0 are incompatible - using iC3.0");
155 target_flags
&= ~TARGET_FLAG_IC_COMPAT2_0
;
158 if (TARGET_IC_COMPAT2_0
)
160 flag_signed_char
= 1;
161 target_flags
|= TARGET_FLAG_CLEAN_LINKAGE
;
164 if (TARGET_IC_COMPAT2_0
)
166 i960_maxbitalignment
= 8;
167 i960_last_maxbitalignment
= 128;
171 i960_maxbitalignment
= 128;
172 i960_last_maxbitalignment
= 8;
176 /* Return true if OP can be used as the source of an fp move insn. */
179 fpmove_src_operand (op
, mode
)
181 enum machine_mode mode
;
183 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
187 /* Return true if OP is a register or zero. */
190 reg_or_zero_operand (op
, mode
)
192 enum machine_mode mode
;
194 return register_operand (op
, mode
) || op
== const0_rtx
;
198 /* Return truth value of whether OP can be used as an operands in a three
199 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
202 arith_operand (op
, mode
)
204 enum machine_mode mode
;
206 return (register_operand (op
, mode
) || literal (op
, mode
));
209 /* Return truth value of whether OP can be used as an operands in a three
210 address logic insn, possibly complementing OP, of mode MODE. */
213 logic_operand (op
, mode
)
215 enum machine_mode mode
;
217 return (register_operand (op
, mode
)
218 || (GET_CODE (op
) == CONST_INT
219 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
222 /* Return true if OP is a register or a valid floating point literal. */
225 fp_arith_operand (op
, mode
)
227 enum machine_mode mode
;
229 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
232 /* Return true if OP is a register or a valid signed integer literal. */
235 signed_arith_operand (op
, mode
)
237 enum machine_mode mode
;
239 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
242 /* Return truth value of whether OP is an integer which fits the
243 range constraining immediate operands in three-address insns. */
248 enum machine_mode mode ATTRIBUTE_UNUSED
;
250 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
253 /* Return true if OP is a float constant of 1. */
256 fp_literal_one (op
, mode
)
258 enum machine_mode mode
;
260 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
263 /* Return true if OP is a float constant of 0. */
266 fp_literal_zero (op
, mode
)
268 enum machine_mode mode
;
270 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
273 /* Return true if OP is a valid floating point literal. */
278 enum machine_mode mode
;
280 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
283 /* Return true if OP is a valid signed immediate constant. */
286 signed_literal(op
, mode
)
288 enum machine_mode mode ATTRIBUTE_UNUSED
;
290 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
293 /* Return truth value of statement that OP is a symbolic memory
294 operand of mode MODE. */
297 symbolic_memory_operand (op
, mode
)
299 enum machine_mode mode ATTRIBUTE_UNUSED
;
301 if (GET_CODE (op
) == SUBREG
)
302 op
= SUBREG_REG (op
);
303 if (GET_CODE (op
) != MEM
)
306 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
307 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
310 /* Return truth value of whether OP is EQ or NE. */
315 enum machine_mode mode ATTRIBUTE_UNUSED
;
317 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
320 /* OP is an integer register or a constant. */
323 arith32_operand (op
, mode
)
325 enum machine_mode mode
;
327 if (register_operand (op
, mode
))
329 return (CONSTANT_P (op
));
332 /* Return true if OP is an integer constant which is a power of 2. */
335 power2_operand (op
,mode
)
337 enum machine_mode mode ATTRIBUTE_UNUSED
;
339 if (GET_CODE (op
) != CONST_INT
)
342 return exact_log2 (INTVAL (op
)) >= 0;
345 /* Return true if OP is an integer constant which is the complement of a
349 cmplpower2_operand (op
, mode
)
351 enum machine_mode mode ATTRIBUTE_UNUSED
;
353 if (GET_CODE (op
) != CONST_INT
)
356 return exact_log2 (~ INTVAL (op
)) >= 0;
359 /* If VAL has only one bit set, return the index of that bit. Otherwise
368 for (i
= 0; val
!= 0; i
++, val
>>= 1)
380 /* Return nonzero if OP is a mask, i.e. all one bits are consecutive.
381 The return value indicates how many consecutive nonzero bits exist
382 if this is a mask. This is the same as the next function, except that
383 it does not indicate what the start and stop bit positions are. */
389 register int start
, end
= 0, i
;
392 for (i
= 0; val
!= 0; val
>>= 1, i
++)
402 /* Still looking for the first bit. */
406 /* We've seen the start of a bit sequence, and now a zero. There
407 must be more one bits, otherwise we would have exited the loop.
408 Therefore, it is not a mask. */
413 /* The bit string has ones from START to END bit positions only. */
414 return end
- start
+ 1;
417 /* If VAL is a mask, then return nonzero, with S set to the starting bit
418 position and E set to the ending bit position of the mask. The return
419 value indicates how many consecutive bits exist in the mask. This is
420 the same as the previous function, except that it also indicates the
421 start and end bit positions of the mask. */
428 register int start
, end
, i
;
432 for (i
= 0; val
!= 0; val
>>= 1, i
++)
443 /* Still looking for the first bit. */
447 /* We've seen the start of a bit sequence, and now a zero. There
448 must be more one bits, otherwise we would have exited the loop.
449 Therefor, it is not a mask. */
458 /* The bit string has ones from START to END bit positions only. */
461 return ((start
< 0) ? 0 : end
- start
+ 1);
464 /* Return the machine mode to use for a comparison. */
467 select_cc_mode (op
, x
)
469 rtx x ATTRIBUTE_UNUSED
;
471 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
476 /* X and Y are two things to compare using CODE. Emit the compare insn and
477 return the rtx for register 36 in the proper mode. */
480 gen_compare_reg (code
, x
, y
)
485 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
486 enum machine_mode mode
487 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
491 if (! arith_operand (x
, mode
))
492 x
= force_reg (SImode
, x
);
493 if (! arith_operand (y
, mode
))
494 y
= force_reg (SImode
, y
);
497 cc_reg
= gen_rtx_REG (ccmode
, 36);
498 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
499 gen_rtx_COMPARE (ccmode
, x
, y
)));
504 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
505 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
506 are 4. Indexed addresses are cost 6. */
508 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
511 i960_address_cost (x
)
514 if (GET_CODE (x
) == REG
)
517 /* This is a MEMA operand -- it's free. */
518 if (GET_CODE (x
) == CONST_INT
520 && INTVAL (x
) < 4096)
523 if (GET_CODE (x
) == PLUS
)
525 rtx base
= XEXP (x
, 0);
526 rtx offset
= XEXP (x
, 1);
528 if (GET_CODE (base
) == SUBREG
)
529 base
= SUBREG_REG (base
);
530 if (GET_CODE (offset
) == SUBREG
)
531 offset
= SUBREG_REG (offset
);
533 if (GET_CODE (base
) == REG
)
535 if (GET_CODE (offset
) == REG
)
537 if (GET_CODE (offset
) == CONST_INT
)
539 if ((unsigned)INTVAL (offset
) < 2047)
543 if (CONSTANT_P (offset
))
546 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
549 /* This is an invalid address. The return value doesn't matter, but
550 for convenience we make this more expensive than anything else. */
553 if (GET_CODE (x
) == MULT
)
556 /* Symbol_refs and other unrecognized addresses are cost 4. */
560 /* Emit insns to move operands[1] into operands[0].
562 Return 1 if we have written out everything that needs to be done to
563 do the move. Otherwise, return 0 and the caller will emit the move
567 emit_move_sequence (operands
, mode
)
569 enum machine_mode mode
;
571 /* We can only store registers to memory. */
573 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
574 && (operands
[1] != const0_rtx
|| current_function_args_size
575 || current_function_stdarg
576 || rtx_equal_function_value_matters
))
577 /* Here we use the same test as movsi+1 pattern -- see i960.md. */
578 operands
[1] = force_reg (mode
, operands
[1]);
580 /* Storing multi-word values in unaligned hard registers to memory may
581 require a scratch since we have to store them a register at a time and
582 adding 4 to the memory address may not yield a valid insn. */
583 /* ??? We don't always need the scratch, but that would complicate things.
585 /* ??? We must also handle stores to pseudos here, because the pseudo may be
586 replaced with a MEM later. This would be cleaner if we didn't have
587 a separate pattern for unaligned DImode/TImode stores. */
588 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
589 && (GET_CODE (operands
[0]) == MEM
590 || (GET_CODE (operands
[0]) == REG
591 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
592 && GET_CODE (operands
[1]) == REG
593 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
594 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
596 emit_insn (gen_rtx_PARALLEL
599 gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]),
600 gen_rtx_CLOBBER (VOIDmode
,
601 gen_rtx_SCRATCH (Pmode
)))));
608 /* Output assembler to move a double word value. */
611 i960_output_move_double (dst
, src
)
616 if (GET_CODE (dst
) == REG
617 && GET_CODE (src
) == REG
)
619 if ((REGNO (src
) & 1)
620 || (REGNO (dst
) & 1))
622 /* We normally copy the low-numbered register first. However, if
623 the second source register is the same as the first destination
624 register, we must copy in the opposite order. */
625 if (REGNO (src
) + 1 == REGNO (dst
))
626 return "mov %D1,%D0\n\tmov %1,%0";
628 return "mov %1,%0\n\tmov %D1,%D0";
633 else if (GET_CODE (dst
) == REG
634 && GET_CODE (src
) == CONST_INT
635 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
638 return "mov %1,%0\n\tmov 0,%D0";
642 else if (GET_CODE (dst
) == REG
643 && GET_CODE (src
) == MEM
)
647 /* One can optimize a few cases here, but you have to be
648 careful of clobbering registers used in the address and
652 operands
[2] = gen_rtx_REG (Pmode
, REGNO (dst
) + 1);
653 operands
[3] = gen_rtx_MEM (word_mode
, operands
[2]);
654 operands
[4] = adjust_address (operands
[3], word_mode
,
657 ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
663 else if (GET_CODE (dst
) == MEM
664 && GET_CODE (src
) == REG
)
669 operands
[1] = adjust_address (dst
, word_mode
, UNITS_PER_WORD
);
670 if (! memory_address_p (word_mode
, XEXP (operands
[1], 0)))
673 output_asm_insn ("st %2,%0\n\tst %D2,%1", operands
);
682 /* Output assembler to move a double word zero. */
685 i960_output_move_double_zero (dst
)
692 operands
[1] = adjust_address (dst
, word_mode
, 4);
693 output_asm_insn ("st g14,%0\n\tst g14,%1", operands
);
698 /* Output assembler to move a quad word value. */
701 i960_output_move_quad (dst
, src
)
706 if (GET_CODE (dst
) == REG
707 && GET_CODE (src
) == REG
)
709 if ((REGNO (src
) & 3)
710 || (REGNO (dst
) & 3))
712 /* We normally copy starting with the low numbered register.
713 However, if there is an overlap such that the first dest reg
714 is <= the last source reg but not < the first source reg, we
715 must copy in the opposite order. */
716 if (REGNO (dst
) <= REGNO (src
) + 3
717 && REGNO (dst
) >= REGNO (src
))
718 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
720 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
725 else if (GET_CODE (dst
) == REG
726 && GET_CODE (src
) == CONST_INT
727 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
730 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
734 else if (GET_CODE (dst
) == REG
735 && GET_CODE (src
) == MEM
)
739 /* One can optimize a few cases here, but you have to be
740 careful of clobbering registers used in the address and
744 operands
[2] = gen_rtx_REG (Pmode
, REGNO (dst
) + 3);
745 operands
[3] = gen_rtx_MEM (word_mode
, operands
[2]);
747 = adjust_address (operands
[3], word_mode
, UNITS_PER_WORD
);
749 = adjust_address (operands
[4], word_mode
, UNITS_PER_WORD
);
751 = adjust_address (operands
[5], word_mode
, UNITS_PER_WORD
);
752 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
758 else if (GET_CODE (dst
) == MEM
759 && GET_CODE (src
) == REG
)
764 operands
[1] = adjust_address (dst
, word_mode
, UNITS_PER_WORD
);
765 operands
[2] = adjust_address (dst
, word_mode
, 2 * UNITS_PER_WORD
);
766 operands
[3] = adjust_address (dst
, word_mode
, 3 * UNITS_PER_WORD
);
767 if (! memory_address_p (word_mode
, XEXP (operands
[3], 0)))
770 output_asm_insn ("st %4,%0\n\tst %D4,%1\n\tst %E4,%2\n\tst %F4,%3", operands
);
779 /* Output assembler to move a quad word zero. */
782 i960_output_move_quad_zero (dst
)
789 operands
[1] = adjust_address (dst
, word_mode
, 4);
790 operands
[2] = adjust_address (dst
, word_mode
, 8);
791 operands
[3] = adjust_address (dst
, word_mode
, 12);
792 output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands
);
798 /* Emit insns to load a constant to non-floating point registers.
799 Uses several strategies to try to use as few insns as possible. */
802 i960_output_ldconst (dst
, src
)
803 register rtx dst
, src
;
806 register unsigned rsrc2
;
807 enum machine_mode mode
= GET_MODE (dst
);
810 operands
[0] = operands
[2] = dst
;
811 operands
[1] = operands
[3] = src
;
813 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
814 must be a ldconst insn. */
816 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
818 output_asm_insn ("ldconst %1,%0", operands
);
821 else if (mode
== TFmode
)
827 if (fp_literal_zero (src
, TFmode
))
830 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
831 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
833 output_asm_insn ("# ldconst %1,%0",operands
);
835 for (i
= 0; i
< 3; i
++)
837 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + i
);
838 operands
[1] = GEN_INT (value_long
[i
]);
839 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
845 else if (mode
== DFmode
)
849 if (fp_literal_zero (src
, DFmode
))
852 split_double (src
, &first
, &second
);
854 output_asm_insn ("# ldconst %1,%0",operands
);
856 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
));
858 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
860 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + 1);
861 operands
[1] = second
;
862 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
866 else if (mode
== SFmode
)
871 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
872 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
874 output_asm_insn ("# ldconst %1,%0",operands
);
875 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
));
876 operands
[1] = GEN_INT (value
);
877 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
881 else if (mode
== TImode
)
883 /* ??? This is currently not handled at all. */
886 /* Note: lowest order word goes in lowest numbered reg. */
887 rsrc1
= INTVAL (src
);
888 if (rsrc1
>= 0 && rsrc1
< 32)
891 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
892 /* Go pick up the low-order word. */
894 else if (mode
== DImode
)
896 rtx upperhalf
, lowerhalf
, xoperands
[2];
898 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
899 split_double (src
, &lowerhalf
, &upperhalf
);
904 /* Note: lowest order word goes in lowest numbered reg. */
905 /* Numbers from 0 to 31 can be handled with a single insn. */
906 rsrc1
= INTVAL (lowerhalf
);
907 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
910 /* Output the upper half with a recursive call. */
911 xoperands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + 1);
912 xoperands
[1] = upperhalf
;
913 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
915 /* The lower word is emitted as normally. */
919 rsrc1
= INTVAL (src
);
925 else if (mode
== HImode
)
934 /* ldconst 0..31,X -> mov 0..31,X */
937 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
942 /* ldconst 32..63,X -> add 31,nn,X */
945 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
947 operands
[1] = GEN_INT (rsrc1
- 31);
948 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
954 /* ldconst -1..-31 -> sub 0,0..31,X */
957 /* return 'sub -(%1),0,%0' */
958 operands
[1] = GEN_INT (- rsrc1
);
959 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
963 /* ldconst -32 -> not 31,X */
966 operands
[1] = GEN_INT (~rsrc1
);
967 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
972 /* If const is a single bit. */
973 if (bitpos (rsrc1
) >= 0)
975 operands
[1] = GEN_INT (bitpos (rsrc1
));
976 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
980 /* If const is a bit string of less than 6 bits (1..31 shifted). */
985 if (bitstr (rsrc1
, &s
, &e
) < 6)
987 rsrc2
= ((unsigned int) rsrc1
) >> s
;
988 operands
[1] = GEN_INT (rsrc2
);
989 operands
[2] = GEN_INT (s
);
990 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
995 /* Unimplemented cases:
996 const is in range 0..31 but rotated around end of word:
997 ror 31,3,g0 -> ldconst 0xe0000003,g0
999 and any 2 instruction cases that might be worthwhile */
1001 output_asm_insn ("ldconst %1,%0", operands
);
1005 /* Determine if there is an opportunity for a bypass optimization.
1006 Bypass succeeds on the 960K* if the destination of the previous
1007 instruction is the second operand of the current instruction.
1008 Bypass always succeeds on the C*.
1010 Return 1 if the pattern should interchange the operands.
1012 CMPBR_FLAG is true if this is for a compare-and-branch insn.
1013 OP1 and OP2 are the two source operands of a 3 operand insn. */
1016 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
1017 register rtx insn
, op1
, op2
;
1020 register rtx prev_insn
, prev_dest
;
1022 if (TARGET_C_SERIES
)
1025 /* Can't do this if op1 isn't a register. */
1029 /* Can't do this for a compare-and-branch if both ops aren't regs. */
1030 if (cmpbr_flag
&& ! REG_P (op2
))
1033 prev_insn
= prev_real_insn (insn
);
1035 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
1036 && GET_CODE (PATTERN (prev_insn
)) == SET
)
1038 prev_dest
= SET_DEST (PATTERN (prev_insn
));
1039 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
1040 || (GET_CODE (prev_dest
) == SUBREG
1041 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
1042 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
1048 /* Output the code which declares the function name. This also handles
1049 leaf routines, which have special requirements, and initializes some
1050 global variables. */
1053 i960_function_name_declare (file
, name
, fndecl
)
1062 /* Increment global return label. */
1066 /* Compute whether tail calls and leaf routine optimizations can be performed
1067 for this function. */
1069 if (TARGET_TAILCALL
)
1074 if (TARGET_LEAFPROC
)
1079 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1080 argblock, because argblock uses g14 implicitly. */
1082 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1088 /* See if caller passes in an address to return value. */
1090 if (aggregate_value_p (DECL_RESULT (fndecl
), fndecl
))
1096 /* Can not use tail calls or make this a leaf routine if there is a non
1099 if (get_frame_size () != 0)
1102 /* I don't understand this condition, and do not think that it is correct.
1103 Apparently this is just checking whether the frame pointer is used, and
1104 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1107 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1108 if (GET_CODE (insn
) == INSN
1109 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1115 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1118 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1119 if (GET_CODE (insn
) == CALL_INSN
)
1125 /* Can not be a leaf routine if any non-call clobbered registers are
1126 used in this function. */
1129 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1130 if (regs_ever_live
[i
]
1131 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1133 /* Global registers. */
1134 if (i
< 16 && i
> 7 && i
!= 13)
1136 /* Local registers. */
1141 /* Now choose a leaf return register, if we can find one, and if it is
1142 OK for this to be a leaf routine. */
1144 i960_leaf_ret_reg
= -1;
1146 if (optimize
&& leaf_proc_ok
)
1148 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1149 if (regs_ever_live
[i
] == 0)
1151 i960_leaf_ret_reg
= i
;
1152 regs_ever_live
[i
] = 1;
1157 /* Do this after choosing the leaf return register, so it will be listed
1158 if one was chosen. */
1160 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1161 fprintf (file
, "\t# Registers used: ");
1163 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1165 if (regs_ever_live
[i
])
1167 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1169 if (i
> 15 && j
== 0)
1171 fprintf (file
,"\n\t#\t\t ");
1177 fprintf (file
, "\n");
1179 if (i960_leaf_ret_reg
>= 0)
1181 /* Make it a leaf procedure. */
1183 if (TREE_PUBLIC (fndecl
))
1184 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1186 fprintf (file
, "\t.leafproc\t");
1187 assemble_name (file
, name
);
1188 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1189 ASM_OUTPUT_LABEL (file
, name
);
1190 fprintf (file
, "\tlda Li960R%d,g14\n", ret_label
);
1191 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1192 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1194 if (TARGET_C_SERIES
)
1196 fprintf (file
, "\tlda 0,g14\n");
1197 i960_last_insn_type
= I_TYPE_MEM
;
1201 fprintf (file
, "\tmov 0,g14\n");
1202 i960_last_insn_type
= I_TYPE_REG
;
1207 ASM_OUTPUT_LABEL (file
, name
);
1208 i960_last_insn_type
= I_TYPE_CTRL
;
1212 /* Compute and return the frame size. */
1215 compute_frame_size (size
)
1219 int outgoing_args_size
= current_function_outgoing_args_size
;
1221 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1222 as size is concerned. */
1223 actual_fsize
= (size
+ 15) & -16;
1224 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1226 return actual_fsize
;
1229 /* Here register group is range of registers which can be moved by
1230 one i960 instruction. */
1238 static int i960_form_reg_groups (int, int, int *, int, struct reg_group
*);
1239 static int i960_reg_group_compare (const void *, const void *);
1240 static int i960_split_reg_group (struct reg_group
*, int, int);
1241 static void i960_arg_size_and_align (enum machine_mode
, tree
, int *, int *);
1243 /* The following functions forms the biggest as possible register
1244 groups with registers in STATE. REGS contain states of the
1245 registers in range [start, finish_reg). The function returns the
1246 number of groups formed. */
1248 i960_form_reg_groups (start_reg
, finish_reg
, regs
, state
, reg_groups
)
1253 struct reg_group
*reg_groups
;
1258 for (i
= start_reg
; i
< finish_reg
; )
1260 if (regs
[i
] != state
)
1265 else if (i
% 2 != 0 || regs
[i
+ 1] != state
)
1266 reg_groups
[nw
].length
= 1;
1267 else if (i
% 4 != 0 || regs
[i
+ 2] != state
)
1268 reg_groups
[nw
].length
= 2;
1269 else if (regs
[i
+ 3] != state
)
1270 reg_groups
[nw
].length
= 3;
1272 reg_groups
[nw
].length
= 4;
1273 reg_groups
[nw
].start_reg
= i
;
1274 i
+= reg_groups
[nw
].length
;
1280 /* We sort register winodws in descending order by length. */
1282 i960_reg_group_compare (group1
, group2
)
1286 const struct reg_group
*w1
= group1
;
1287 const struct reg_group
*w2
= group2
;
1289 if (w1
->length
> w2
->length
)
1291 else if (w1
->length
< w2
->length
)
1297 /* Split the first register group in REG_GROUPS on subgroups one of
1298 which will contain SUBGROUP_LENGTH registers. The function
1299 returns new number of winodws. */
1301 i960_split_reg_group (reg_groups
, nw
, subgroup_length
)
1302 struct reg_group
*reg_groups
;
1304 int subgroup_length
;
1306 if (subgroup_length
< reg_groups
->length
- subgroup_length
)
1307 /* This guarantees correct alignments of the two subgroups for
1308 i960 (see spliting for the group length 2, 3, 4). More
1309 generalized algorithm would require splitting the group more
1311 subgroup_length
= reg_groups
->length
- subgroup_length
;
1312 /* More generalized algorithm would require to try merging
1313 subgroups here. But in case i960 it always results in failure
1314 because of register group alignment. */
1315 reg_groups
[nw
].length
= reg_groups
->length
- subgroup_length
;
1316 reg_groups
[nw
].start_reg
= reg_groups
->start_reg
+ subgroup_length
;
1318 reg_groups
->length
= subgroup_length
;
1319 qsort (reg_groups
, nw
, sizeof (struct reg_group
), i960_reg_group_compare
);
1323 /* Output code for the function prologue. */
1326 i960_output_function_prologue (file
, size
)
1330 register int i
, j
, nr
;
1331 int n_saved_regs
= 0;
1332 int n_remaining_saved_regs
;
1333 HOST_WIDE_INT lvar_size
;
1334 HOST_WIDE_INT actual_fsize
, offset
;
1336 struct reg_group
*g
, *l
;
1338 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1340 int regs
[FIRST_PSEUDO_REGISTER
];
1341 /* All global registers (which must be saved) divided by groups. */
1342 struct reg_group global_reg_groups
[16];
1343 /* All local registers (which are available) divided by groups. */
1344 struct reg_group local_reg_groups
[16];
1347 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1348 if (regs_ever_live
[i
]
1349 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12))
1350 /* No need to save the static chain pointer. */
1351 && ! (i
== STATIC_CHAIN_REGNUM
&& current_function_needs_context
))
1354 /* Count global registers that need saving. */
1361 n_remaining_saved_regs
= n_saved_regs
;
1363 epilogue_string
[0] = '\0';
1365 if (current_function_profile
)
1367 /* When profiling, we may use registers 20 to 27 to save arguments, so
1368 they can't be used here for saving globals. J is the number of
1369 argument registers the mcount call will save. */
1370 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1373 for (i
= 20; i
<= j
+ 20; i
++)
1377 gnw
= i960_form_reg_groups (0, 16, regs
, -1, global_reg_groups
);
1378 lnw
= i960_form_reg_groups (19, 32, regs
, 0, local_reg_groups
);
1379 qsort (global_reg_groups
, gnw
, sizeof (struct reg_group
),
1380 i960_reg_group_compare
);
1381 qsort (local_reg_groups
, lnw
, sizeof (struct reg_group
),
1382 i960_reg_group_compare
);
1383 for (g
= global_reg_groups
, l
= local_reg_groups
; lnw
!= 0 && gnw
!= 0;)
1385 if (g
->length
== l
->length
)
1387 fprintf (file
, "\tmov%s %s,%s\n",
1388 ((g
->length
== 4) ? "q" :
1389 (g
->length
== 3) ? "t" :
1390 (g
->length
== 2) ? "l" : ""),
1391 reg_names
[(unsigned char) g
->start_reg
],
1392 reg_names
[(unsigned char) l
->start_reg
]);
1393 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1394 ((g
->length
== 4) ? "q" :
1395 (g
->length
== 3) ? "t" :
1396 (g
->length
== 2) ? "l" : ""),
1397 reg_names
[(unsigned char) l
->start_reg
],
1398 reg_names
[(unsigned char) g
->start_reg
]);
1399 strcat (epilogue_string
, tmpstr
);
1400 n_remaining_saved_regs
-= g
->length
;
1401 for (i
= 0; i
< g
->length
; i
++)
1403 regs
[i
+ g
->start_reg
] = 1;
1404 regs
[i
+ l
->start_reg
] = -1;
1405 regs_ever_live
[i
+ l
->start_reg
] = 1;
1412 else if (g
->length
> l
->length
)
1413 gnw
= i960_split_reg_group (g
, gnw
, l
->length
);
1415 lnw
= i960_split_reg_group (l
, lnw
, g
->length
);
1418 actual_fsize
= compute_frame_size (size
) + 4 * n_remaining_saved_regs
;
1420 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1421 size up to the nearest multiple of 16. I don't know whether this is
1422 necessary, or even desirable.
1424 The frame pointer must be aligned, but the call instruction takes care of
1425 that. If we leave the stack pointer unaligned, we may save a little on
1426 dynamic stack allocation. And we don't lose, at least according to the
1428 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1431 /* Check stack limit if necessary. */
1432 if (current_function_limit_stack
)
1434 rtx min_stack
= stack_limit_rtx
;
1435 if (actual_fsize
!= 0)
1436 min_stack
= plus_constant (stack_limit_rtx
, -actual_fsize
);
1438 /* Now, emulate a little bit of reload. We want to turn 'min_stack'
1439 into an arith_operand. Use register 20 as the temporary. */
1440 if (legitimate_address_p (Pmode
, min_stack
, 1)
1441 && !arith_operand (min_stack
, Pmode
))
1443 rtx tmp
= gen_rtx_MEM (Pmode
, min_stack
);
1444 fputs ("\tlda\t", file
);
1445 i960_print_operand (file
, tmp
, 0);
1446 fputs (",r4\n", file
);
1447 min_stack
= gen_rtx_REG (Pmode
, 20);
1449 if (arith_operand (min_stack
, Pmode
))
1451 fputs ("\tcmpo\tsp,", file
);
1452 i960_print_operand (file
, min_stack
, 0);
1453 fputs ("\n\tfaultge.f\n", file
);
1456 warning ("stack limit expression is not supported");
1459 /* Allocate space for register save and locals. */
1460 if (actual_fsize
> 0)
1462 if (actual_fsize
< 32)
1463 fprintf (file
, "\taddo " HOST_WIDE_INT_PRINT_DEC
",sp,sp\n",
1466 fprintf (file
, "\tlda\t" HOST_WIDE_INT_PRINT_DEC
"(sp),sp\n",
1470 /* Take hardware register save area created by the call instruction
1471 into account, but store them before the argument block area. */
1472 lvar_size
= actual_fsize
- compute_frame_size (0) - n_remaining_saved_regs
* 4;
1473 offset
= STARTING_FRAME_OFFSET
+ lvar_size
;
1474 /* Save registers on stack if needed. */
1475 /* ??? Is it worth to use the same algorithm as one for saving
1476 global registers in local registers? */
1477 for (i
= 0, j
= n_remaining_saved_regs
; j
> 0 && i
< 16; i
++)
1484 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1487 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1491 if (nr
== 3 && regs
[i
+3] == -1)
1494 fprintf (file
,"\tst%s %s," HOST_WIDE_INT_PRINT_DEC
"(fp)\n",
1497 (nr
== 2) ? "l" : ""),
1498 reg_names
[i
], offset
);
1499 sprintf (tmpstr
,"\tld%s " HOST_WIDE_INT_PRINT_DEC
"(fp),%s\n",
1502 (nr
== 2) ? "l" : ""),
1503 offset
, reg_names
[i
]);
1504 strcat (epilogue_string
, tmpstr
);
1510 if (actual_fsize
== 0)
1513 fprintf (file
, "\t#Prologue stats:\n");
1514 fprintf (file
, "\t# Total Frame Size: " HOST_WIDE_INT_PRINT_DEC
" bytes\n",
1518 fprintf (file
, "\t# Local Variable Size: " HOST_WIDE_INT_PRINT_DEC
1519 " bytes\n", lvar_size
);
1521 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1522 n_saved_regs
, n_saved_regs
* 4);
1523 fprintf (file
, "\t#End Prologue#\n");
1526 /* Output code for the function profiler. */
1529 output_function_profiler (file
, labelno
)
1533 /* The last used parameter register. */
1535 int i
, j
, increment
;
1536 int varargs_stdarg_function
1537 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1539 /* Figure out the last used parameter register. The proper thing to do
1540 is to walk incoming args of the function. A function might have live
1541 parameter registers even if it has no incoming args. Note that we
1542 don't have to save parameter registers g8 to g11 because they are
1545 /* See also output_function_prologue, which tries to use local registers
1546 for preserved call-saved global registers. */
1548 for (last_parm_reg
= 7;
1549 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1553 /* Save parameter registers in regs r4 (20) to r11 (27). */
1555 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1557 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1559 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1561 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1566 fprintf (file
, "\tmov%s g%d,r%d\n",
1567 (increment
== 4 ? "q" : increment
== 3 ? "t"
1568 : increment
== 2 ? "l": ""), i
, j
);
1571 /* If this function uses the arg pointer, then save it in r3 and then
1574 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1575 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1577 /* Load location address into g0 and call mcount. */
1579 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1581 /* If this function uses the arg pointer, restore it. */
1583 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1584 fprintf (file
, "\tmov r3,g14\n");
1586 /* Restore parameter registers. */
1588 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1590 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1592 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1594 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1599 fprintf (file
, "\tmov%s r%d,g%d\n",
1600 (increment
== 4 ? "q" : increment
== 3 ? "t"
1601 : increment
== 2 ? "l": ""), j
, i
);
1605 /* Output code for the function epilogue. */
1608 i960_output_function_epilogue (file
, size
)
1610 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
1612 if (i960_leaf_ret_reg
>= 0)
1614 fprintf (file
, "Li960R%d: ret\n", ret_label
);
1618 if (*epilogue_string
== 0)
1622 /* Emit a return insn, but only if control can fall through to here. */
1624 tmp
= get_last_insn ();
1627 if (GET_CODE (tmp
) == BARRIER
)
1629 if (GET_CODE (tmp
) == CODE_LABEL
)
1631 if (GET_CODE (tmp
) == JUMP_INSN
)
1633 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1637 if (GET_CODE (tmp
) == NOTE
)
1639 tmp
= PREV_INSN (tmp
);
1644 fprintf (file
, "Li960R%d: ret\n", ret_label
);
1648 fprintf (file
, "Li960R%d:\n", ret_label
);
1650 fprintf (file
, "\t#EPILOGUE#\n");
1652 /* Output the string created by the prologue which will restore all
1653 registers saved by the prologue. */
1655 if (epilogue_string
[0] != '\0')
1656 fprintf (file
, "%s", epilogue_string
);
1658 /* Must clear g14 on return if this function set it.
1659 Only varargs/stdarg functions modify g14. */
1661 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1662 fprintf (file
, "\tmov 0,g14\n");
1664 fprintf (file
, "\tret\n");
1665 fprintf (file
, "\t#End Epilogue#\n");
1668 /* Output code for a call insn. */
1671 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1672 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1674 int argsize
= INTVAL (argsize_rtx
);
1675 rtx nexti
= next_real_insn (insn
);
1677 int varargs_stdarg_function
1678 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1680 operands
[0] = target
;
1681 operands
[1] = arg_pointer
;
1683 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1684 output_asm_insn ("mov g14,r3", operands
);
1687 output_asm_insn ("lda %a1,g14", operands
);
1688 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1689 output_asm_insn ("mov 0,g14", operands
);
1691 /* The code used to assume that calls to SYMBOL_REFs could not be more
1692 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1693 feature is now implemented by relaxing in the GNU linker. It can convert
1694 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1696 /* Nexti could be zero if the called routine is volatile. */
1697 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1698 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1700 /* Delete following return insn. */
1701 if (nexti
&& no_labels_between_p (insn
, nexti
))
1702 delete_insn (nexti
);
1703 output_asm_insn ("bx %0", operands
);
1704 return "# notreached";
1707 output_asm_insn ("callx %0", operands
);
1709 /* If the caller sets g14 to the address of the argblock, then the caller
1710 must clear it after the return. */
1712 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1713 output_asm_insn ("mov r3,g14", operands
);
1714 else if (argsize
> 48)
1715 output_asm_insn ("mov 0,g14", operands
);
1720 /* Output code for a return insn. */
1723 i960_output_ret_insn (insn
)
1726 static char lbuf
[20];
1728 if (*epilogue_string
!= 0)
1730 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1733 sprintf (lbuf
, "b Li960R%d", ret_label
);
1737 /* Must clear g14 on return if this function set it.
1738 Only varargs/stdarg functions modify g14. */
1740 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1741 output_asm_insn ("mov 0,g14", 0);
1743 if (i960_leaf_ret_reg
>= 0)
1745 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1751 /* Print the operand represented by rtx X formatted by code CODE. */
1754 i960_print_operand (file
, x
, code
)
1759 enum rtx_code rtxcode
= x
? GET_CODE (x
) : NIL
;
1766 /* Second reg of a double or quad. */
1767 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1771 /* Third reg of a quad. */
1772 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1776 /* Fourth reg of a quad. */
1777 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1781 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1789 else if (rtxcode
== MEM
)
1791 output_address (XEXP (x
, 0));
1794 else if (rtxcode
== CONST_INT
)
1796 HOST_WIDE_INT val
= INTVAL (x
);
1799 if (val
> 9999 || val
< -999)
1800 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, val
);
1802 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, val
);
1805 else if (rtxcode
== CONST_DOUBLE
)
1809 if (x
== CONST0_RTX (GET_MODE (x
)))
1811 fprintf (file
, "0f0.0");
1814 else if (x
== CONST1_RTX (GET_MODE (x
)))
1816 fprintf (file
, "0f1.0");
1820 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (dstr
), 0, 1);
1821 fprintf (file
, "0f%s", dstr
);
1828 /* Branch or jump, depending on assembler. */
1829 if (TARGET_ASM_COMPAT
)
1836 /* Sign of condition. */
1837 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1838 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1840 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1841 || (rtxcode
== GE
) || (rtxcode
== LE
))
1848 /* Inverted condition. */
1849 rtxcode
= reverse_condition (rtxcode
);
1853 /* Inverted condition w/ reversed operands. */
1854 rtxcode
= reverse_condition (rtxcode
);
1858 /* Reversed operand condition. */
1859 rtxcode
= swap_condition (rtxcode
);
1863 /* Normal condition. */
1865 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1866 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1867 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1868 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1869 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1870 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1871 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1872 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1873 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1874 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1879 /* For conditional branches, substitute ".t" or ".f". */
1880 if (TARGET_BRANCH_PREDICT
)
1882 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
1885 int pred_val
= INTVAL (XEXP (x
, 0));
1886 fputs ((pred_val
< REG_BR_PROB_BASE
/ 2 ? ".f" : ".t"), file
);
1892 output_addr_const (file
, x
);
1902 /* Print a memory address as an operand to reference that memory location.
1904 This is exactly the same as legitimate_address_p, except that it the prints
1905 addresses instead of recognizing them. */
1908 i960_print_operand_addr (file
, addr
)
1920 if (GET_CODE (addr
) == REG
)
1922 else if (CONSTANT_P (addr
))
1924 else if (GET_CODE (addr
) == PLUS
)
1928 op0
= XEXP (addr
, 0);
1929 op1
= XEXP (addr
, 1);
1931 if (GET_CODE (op0
) == REG
)
1934 if (GET_CODE (op1
) == REG
)
1936 else if (CONSTANT_P (op1
))
1941 else if (GET_CODE (op0
) == PLUS
)
1943 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1945 ireg
= XEXP (XEXP (op0
, 0), 0);
1946 scale
= XEXP (XEXP (op0
, 0), 1);
1947 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1949 breg
= XEXP (op0
, 1);
1955 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1957 breg
= XEXP (op0
, 0);
1958 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1960 ireg
= XEXP (op0
, 1);
1969 else if (GET_CODE (op0
) == MULT
)
1971 ireg
= XEXP (op0
, 0);
1972 scale
= XEXP (op0
, 1);
1973 if (GET_CODE (op1
) == REG
)
1975 else if (CONSTANT_P (op1
))
1983 else if (GET_CODE (addr
) == MULT
)
1985 ireg
= XEXP (addr
, 0);
1986 scale
= XEXP (addr
, 1);
1992 output_addr_const (file
, offset
);
1994 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1996 fprintf (file
, "[%s*" HOST_WIDE_INT_PRINT_DEC
"]",
1997 reg_names
[REGNO (ireg
)], INTVAL (scale
));
2000 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2001 that is a valid memory address for an instruction.
2002 The MODE argument is the machine mode for the MEM expression
2003 that wants to use this address.
2005 On 80960, legitimate addresses are:
2007 disp (12 or 32 bit) ld foo,r0
2008 base + index ld (g0)[g1*1],r0
2009 base + displ ld 0xf00(g0),r0
2010 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
2011 index*scale + base ld (g0)[g1*4],r0
2012 index*scale + displ ld 0xf00[g1*4],r0
2013 index*scale ld [g1*4],r0
2014 index + base + displ ld 0xf00(g0)[g1*1],r0
2016 In each case, scale can be 1, 2, 4, 8, or 16. */
2018 /* This is exactly the same as i960_print_operand_addr, except that
2019 it recognizes addresses instead of printing them.
2021 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2022 convert common non-canonical forms to canonical form so that they will
2025 /* These two macros allow us to accept either a REG or a SUBREG anyplace
2026 where a register is valid. */
2028 #define RTX_OK_FOR_BASE_P(X, STRICT) \
2029 ((GET_CODE (X) == REG \
2030 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
2031 || (GET_CODE (X) == SUBREG \
2032 && GET_CODE (SUBREG_REG (X)) == REG \
2033 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
2034 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
2036 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
2037 ((GET_CODE (X) == REG \
2038 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
2039 || (GET_CODE (X) == SUBREG \
2040 && GET_CODE (SUBREG_REG (X)) == REG \
2041 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
2042 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
2045 legitimate_address_p (mode
, addr
, strict
)
2046 enum machine_mode mode ATTRIBUTE_UNUSED
;
2050 if (RTX_OK_FOR_BASE_P (addr
, strict
))
2052 else if (CONSTANT_P (addr
))
2054 else if (GET_CODE (addr
) == PLUS
)
2058 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2061 op0
= XEXP (addr
, 0);
2062 op1
= XEXP (addr
, 1);
2064 if (RTX_OK_FOR_BASE_P (op0
, strict
))
2066 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
2068 else if (CONSTANT_P (op1
))
2073 else if (GET_CODE (op0
) == PLUS
)
2075 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
2077 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
2078 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
2081 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
2082 && CONSTANT_P (op1
))
2087 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
2089 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
2090 && CONSTANT_P (op1
))
2098 else if (GET_CODE (op0
) == MULT
)
2100 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
2101 && SCALE_TERM_P (XEXP (op0
, 1))))
2104 if (RTX_OK_FOR_BASE_P (op1
, strict
))
2106 else if (CONSTANT_P (op1
))
2114 else if (GET_CODE (addr
) == MULT
)
2116 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2119 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
2120 && SCALE_TERM_P (XEXP (addr
, 1)));
2126 /* Try machine-dependent ways of modifying an illegitimate address
2127 to be legitimate. If we find one, return the new, valid address.
2128 This macro is used in only one place: `memory_address' in explow.c.
2130 This converts some non-canonical addresses to canonical form so they
2131 can be recognized. */
2134 legitimize_address (x
, oldx
, mode
)
2136 register rtx oldx ATTRIBUTE_UNUSED
;
2137 enum machine_mode mode ATTRIBUTE_UNUSED
;
2139 if (GET_CODE (x
) == SYMBOL_REF
)
2142 x
= copy_to_reg (x
);
2145 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2148 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2149 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2150 created by virtual register instantiation, register elimination, and
2151 similar optimizations. */
2152 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2153 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2154 x
= gen_rtx_PLUS (Pmode
,
2155 gen_rtx_PLUS (Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2156 XEXP (XEXP (x
, 1), 1));
2158 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2159 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2160 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2161 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2162 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2163 && CONSTANT_P (XEXP (x
, 1)))
2165 rtx constant
, other
;
2167 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2169 constant
= XEXP (x
, 1);
2170 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2172 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2174 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2175 other
= XEXP (x
, 1);
2178 constant
= 0, other
= 0;
2181 x
= gen_rtx_PLUS (Pmode
,
2182 gen_rtx_PLUS (Pmode
, XEXP (XEXP (x
, 0), 0),
2183 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2184 plus_constant (other
, INTVAL (constant
)));
2191 /* Return the most stringent alignment that we are willing to consider
2192 objects of size SIZE and known alignment ALIGN as having. */
2195 i960_alignment (size
, align
)
2201 if (! TARGET_STRICT_ALIGN
)
2202 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2204 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2215 hard_regno_mode_ok (regno
, mode
)
2217 enum machine_mode mode
;
2223 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2226 case DImode
: case DFmode
:
2227 return (regno
& 1) == 0;
2229 case TImode
: case TFmode
:
2230 return (regno
& 3) == 0;
2236 else if (regno
>= 32 && regno
< 36)
2240 case SFmode
: case DFmode
: case TFmode
:
2241 case SCmode
: case DCmode
:
2248 else if (regno
== 36)
2252 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2259 else if (regno
== 37)
2266 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2267 advantage of machine specific facts, such as knowing that the frame pointer
2268 is always 16 byte aligned. */
2271 i960_expr_alignment (x
, size
)
2280 switch (GET_CODE(x
))
2285 if ((align
& 0xf) == 0)
2287 else if ((align
& 0x7) == 0)
2289 else if ((align
& 0x3) == 0)
2291 else if ((align
& 0x1) == 0)
2298 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2299 i960_expr_alignment (XEXP (x
, 1), size
));
2303 /* If this is a valid program, objects are guaranteed to be
2304 correctly aligned for whatever size the reference actually is. */
2305 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2309 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2314 align
= i960_expr_alignment (XEXP (x
, 0), size
);
2316 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2318 align
= align
<< INTVAL (XEXP (x
, 1));
2319 align
= MIN (align
, 16);
2324 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2325 i960_expr_alignment (XEXP (x
, 1), size
));
2327 align
= MIN (align
, 16);
2336 /* Return true if it is possible to reference both BASE and OFFSET, which
2337 have alignment at least as great as 4 byte, as if they had alignment valid
2338 for an object of size SIZE. */
2341 i960_improve_align (base
, offset
, size
)
2348 /* We have at least a word reference to the object, so we know it has to
2349 be aligned at least to 4 bytes. */
2351 i
= MIN (i960_expr_alignment (base
, 4),
2352 i960_expr_alignment (offset
, 4));
2356 /* We know the size of the request. If strict align is not enabled, we
2357 can guess that the alignment is OK for the requested size. */
2359 if (! TARGET_STRICT_ALIGN
)
2360 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2366 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2367 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2370 i960_si_ti (base
, offset
)
2374 return i960_improve_align (base
, offset
, 16);
2377 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2378 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2381 i960_si_di (base
, offset
)
2385 return i960_improve_align (base
, offset
, 8);
2388 /* Return raw values of size and alignment (in words) for the data
2389 type being accessed. These values will be rounded by the caller. */
2392 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2393 enum machine_mode mode
;
2400 /* Use formal alignment requirements of type being passed, except make
2401 it at least a word. If we don't have a type, this is a library call,
2402 and the parm has to be of scalar type. In this case, consider its
2403 formal alignment requirement to be its size in words. */
2405 if (mode
== BLKmode
)
2406 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2407 else if (mode
== VOIDmode
)
2409 /* End of parm list. */
2410 if (type
== 0 || TYPE_MODE (type
) != VOIDmode
)
2415 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2419 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2420 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2428 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2429 Any arg that is bigger than 4 words is placed on the stack and all
2430 subsequent arguments are placed on the stack.
2432 Additionally, parameters with an alignment requirement stronger than
2433 a word must be aligned appropriately. Note that this means that a
2434 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2435 passed in an odd/even register pair. */
2437 /* Update CUM to advance past an argument described by MODE and TYPE. */
2440 i960_function_arg_advance (cum
, mode
, type
, named
)
2441 CUMULATIVE_ARGS
*cum
;
2442 enum machine_mode mode
;
2444 int named ATTRIBUTE_UNUSED
;
2448 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2450 if (size
> 4 || cum
->ca_nstackparms
!= 0
2451 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2452 || MUST_PASS_IN_STACK (mode
, type
))
2454 /* Indicate that all the registers are in use, even if all are not,
2455 so va_start will compute the right value. */
2456 cum
->ca_nregparms
= NPARM_REGS
;
2457 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2460 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2463 /* Return the register that the argument described by MODE and TYPE is
2464 passed in, or else return 0 if it is passed on the stack. */
2467 i960_function_arg (cum
, mode
, type
, named
)
2468 CUMULATIVE_ARGS
*cum
;
2469 enum machine_mode mode
;
2471 int named ATTRIBUTE_UNUSED
;
2476 if (mode
== VOIDmode
)
2479 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2481 if (size
> 4 || cum
->ca_nstackparms
!= 0
2482 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2483 || MUST_PASS_IN_STACK (mode
, type
))
2485 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2490 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2491 ret
= gen_rtx_REG (mode
, cum
->ca_nregparms
);
2497 /* Return the number of bits that an object of size N bytes is aligned to. */
2500 i960_object_bytes_bitalign (n
)
2504 else if (n
> 4) n
= 64;
2505 else if (n
> 2) n
= 32;
2506 else if (n
> 1) n
= 16;
2512 /* Compute the alignment for an aggregate type TSIZE.
2513 Alignment is MAX (greatest member alignment,
2514 MIN (pragma align, structure size alignment)). */
2517 i960_round_align (align
, type
)
2524 if (TARGET_OLD_ALIGN
|| TYPE_PACKED (type
))
2526 if (TREE_CODE (type
) != RECORD_TYPE
)
2528 tsize
= TYPE_SIZE (type
);
2530 if (! tsize
|| TREE_CODE (tsize
) != INTEGER_CST
)
2533 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2535 /* Handle #pragma align. */
2536 if (new_align
> i960_maxbitalignment
)
2537 new_align
= i960_maxbitalignment
;
2539 if (align
< new_align
)
2545 /* Do any needed setup for a varargs function. For the i960, we must
2546 create a register parameter block if one doesn't exist, and then copy
2547 all register parameters to memory. */
2550 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2551 CUMULATIVE_ARGS
*cum
;
2552 enum machine_mode mode ATTRIBUTE_UNUSED
;
2553 tree type ATTRIBUTE_UNUSED
;
2554 int *pretend_size ATTRIBUTE_UNUSED
;
2557 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2558 int first_reg
= cum
->ca_nregparms
;
2560 /* Copy only unnamed register arguments to memory. If there are
2561 any stack parms, there are no unnamed arguments in registers, and
2562 an argument block was already allocated by the caller.
2563 Remember that any arg bigger than 4 words is passed on the stack as
2564 are all subsequent args.
2566 If there are no stack arguments but there are exactly NPARM_REGS
2567 registers, either there were no extra arguments or the caller
2568 allocated an argument block. */
2570 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2572 rtx label
= gen_label_rtx ();
2573 rtx regblock
, fake_arg_pointer_rtx
;
2575 /* Use a different rtx than arg_pointer_rtx so that cse and friends
2576 can go on believing that the argument pointer can never be zero. */
2577 fake_arg_pointer_rtx
= gen_raw_REG (Pmode
, ARG_POINTER_REGNUM
);
2579 /* If the argument pointer is 0, no arguments were passed on the stack
2580 and we need to allocate a chunk to save the registers (if any
2581 arguments were passed on the stack the caller would allocate the
2582 48 bytes as well). We must allocate all 48 bytes (12*4) because
2583 va_start assumes it. */
2584 emit_insn (gen_cmpsi (fake_arg_pointer_rtx
, const0_rtx
));
2585 emit_jump_insn (gen_bne (label
));
2586 emit_insn (gen_rtx_SET (VOIDmode
, fake_arg_pointer_rtx
,
2587 stack_pointer_rtx
));
2588 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
2589 memory_address (SImode
,
2590 plus_constant (stack_pointer_rtx
,
2594 /* ??? Note that we unnecessarily store one extra register for stdarg
2595 fns. We could optimize this, but it's kept as for now. */
2596 regblock
= gen_rtx_MEM (BLKmode
,
2597 plus_constant (arg_pointer_rtx
, first_reg
* 4));
2598 set_mem_alias_set (regblock
, get_varargs_alias_set ());
2599 set_mem_align (regblock
, BITS_PER_WORD
);
2600 move_block_from_reg (first_reg
, regblock
,
2601 NPARM_REGS
- first_reg
);
2605 /* Define the `__builtin_va_list' type for the ABI. */
2608 i960_build_builtin_va_list ()
2610 return build_array_type (unsigned_type_node
,
2611 build_index_type (size_one_node
));
2614 /* Implement `va_start' for varargs and stdarg. */
2617 i960_va_start (valist
, nextarg
)
2619 rtx nextarg ATTRIBUTE_UNUSED
;
2621 tree s
, t
, base
, num
;
2622 rtx fake_arg_pointer_rtx
;
2624 /* The array type always decays to a pointer before we get here, so we
2625 can't use ARRAY_REF. */
2626 base
= build1 (INDIRECT_REF
, unsigned_type_node
, valist
);
2627 num
= build1 (INDIRECT_REF
, unsigned_type_node
,
2628 build (PLUS_EXPR
, unsigned_type_node
, valist
,
2629 TYPE_SIZE_UNIT (TREE_TYPE (valist
))));
2631 /* Use a different rtx than arg_pointer_rtx so that cse and friends
2632 can go on believing that the argument pointer can never be zero. */
2633 fake_arg_pointer_rtx
= gen_raw_REG (Pmode
, ARG_POINTER_REGNUM
);
2634 s
= make_tree (unsigned_type_node
, fake_arg_pointer_rtx
);
2635 t
= build (MODIFY_EXPR
, unsigned_type_node
, base
, s
);
2636 TREE_SIDE_EFFECTS (t
) = 1;
2637 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2639 s
= build_int_2 ((current_function_args_info
.ca_nregparms
2640 + current_function_args_info
.ca_nstackparms
) * 4, 0);
2641 t
= build (MODIFY_EXPR
, unsigned_type_node
, num
, s
);
2642 TREE_SIDE_EFFECTS (t
) = 1;
2643 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2646 /* Implement `va_arg'. */
2649 i960_va_arg (valist
, type
)
2652 HOST_WIDE_INT siz
, ali
;
2653 tree base
, num
, pad
, next
, this, t1
, t2
, int48
;
2656 /* The array type always decays to a pointer before we get here, so we
2657 can't use ARRAY_REF. */
2658 base
= build1 (INDIRECT_REF
, unsigned_type_node
, valist
);
2659 num
= build1 (INDIRECT_REF
, unsigned_type_node
,
2660 build (PLUS_EXPR
, unsigned_type_node
, valist
,
2661 TYPE_SIZE_UNIT (TREE_TYPE (valist
))));
2663 /* Round up sizeof(type) to a word. */
2664 siz
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
2666 /* Round up alignment to a word. */
2667 ali
= TYPE_ALIGN (type
);
2668 if (ali
< BITS_PER_WORD
)
2669 ali
= BITS_PER_WORD
;
2670 ali
/= BITS_PER_UNIT
;
2672 /* Align NUM appropriate for the argument. */
2673 pad
= fold (build (PLUS_EXPR
, unsigned_type_node
, num
,
2674 build_int_2 (ali
- 1, 0)));
2675 pad
= fold (build (BIT_AND_EXPR
, unsigned_type_node
, pad
,
2676 build_int_2 (-ali
, -1)));
2677 pad
= save_expr (pad
);
2679 /* Increment VPAD past this argument. */
2680 next
= fold (build (PLUS_EXPR
, unsigned_type_node
, pad
,
2681 build_int_2 (siz
, 0)));
2682 next
= save_expr (next
);
2684 /* Find the offset for the current argument. Mind peculiar overflow
2685 from registers to stack. */
2686 int48
= build_int_2 (48, 0);
2688 t2
= integer_one_node
;
2690 t2
= fold (build (GT_EXPR
, integer_type_node
, next
, int48
));
2691 t1
= fold (build (LE_EXPR
, integer_type_node
, num
, int48
));
2692 t1
= fold (build (TRUTH_AND_EXPR
, integer_type_node
, t1
, t2
));
2693 this = fold (build (COND_EXPR
, unsigned_type_node
, t1
, int48
, pad
));
2695 /* Find the address for the current argument. */
2696 t1
= fold (build (PLUS_EXPR
, unsigned_type_node
, base
, this));
2697 t1
= build1 (NOP_EXPR
, ptr_type_node
, t1
);
2698 addr_rtx
= expand_expr (t1
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
2700 /* Increment NUM. */
2701 t1
= build (MODIFY_EXPR
, unsigned_type_node
, num
, next
);
2702 TREE_SIDE_EFFECTS (t1
) = 1;
2703 expand_expr (t1
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2708 /* Calculate the final size of the reg parm stack space for the current
2709 function, based on how many bytes would be allocated on the stack. */
2712 i960_final_reg_parm_stack_space (const_size
, var_size
)
2716 if (var_size
|| const_size
> 48)
2722 /* Calculate the size of the reg parm stack space. This is a bit complicated
2726 i960_reg_parm_stack_space (fndecl
)
2729 /* In this case, we are called from emit_library_call, and we don't need
2730 to pretend we have more space for parameters than what's apparent. */
2734 /* In this case, we are called from locate_and_pad_parms when we're
2735 not IN_REGS, so we have an arg block. */
2736 if (fndecl
!= current_function_decl
)
2739 /* Otherwise, we have an arg block if the current function has more than
2740 48 bytes of parameters. */
2741 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2747 /* Return the register class of a scratch register needed to copy IN into
2748 or out of a register in CLASS in MODE. If it can be done directly,
2749 NO_REGS is returned. */
2752 secondary_reload_class (class, mode
, in
)
2753 enum reg_class
class;
2754 enum machine_mode mode
;
2759 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2760 regno
= true_regnum (in
);
2762 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2763 LOCAL_OR_GLOBAL_REGS into anything. */
2764 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2765 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2768 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2769 if (class == FP_REGS
2770 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2771 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2774 return LOCAL_OR_GLOBAL_REGS
;
2777 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2778 function unit it executed on. */
2780 /* ??? This would make more sense as an attribute. */
2783 i960_scan_opcode (p
)
2795 /* Ret is not actually of type REG, but it won't matter, because no
2796 insn will ever follow it. */
2799 i960_last_insn_type
= I_TYPE_REG
;
2803 if (p
[1] == 'x' || p
[3] == 'x')
2804 i960_last_insn_type
= I_TYPE_MEM
;
2805 i960_last_insn_type
= I_TYPE_CTRL
;
2810 i960_last_insn_type
= I_TYPE_CTRL
;
2817 i960_last_insn_type
= I_TYPE_MEM
;
2819 i960_last_insn_type
= I_TYPE_CTRL
;
2821 else if (p
[1] == 'm')
2824 i960_last_insn_type
= I_TYPE_REG
;
2825 else if (p
[4] == 'b' || p
[4] == 'j')
2826 i960_last_insn_type
= I_TYPE_CTRL
;
2828 i960_last_insn_type
= I_TYPE_REG
;
2831 i960_last_insn_type
= I_TYPE_REG
;
2835 i960_last_insn_type
= I_TYPE_MEM
;
2840 i960_last_insn_type
= I_TYPE_MEM
;
2842 i960_last_insn_type
= I_TYPE_REG
;
2848 i960_output_mi_thunk (file
, thunk
, delta
, vcall_offset
, function
)
2850 tree thunk ATTRIBUTE_UNUSED
;
2851 HOST_WIDE_INT delta
;
2852 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
;
2856 if (d
< 0 && d
> -32)
2857 fprintf (file
, "\tsubo %d,g0,g0\n", -d
);
2858 else if (d
> 0 && d
< 32)
2859 fprintf (file
, "\taddo %d,g0,g0\n", d
);
2862 fprintf (file
, "\tldconst %d,r5\n", d
);
2863 fprintf (file
, "\taddo r5,g0,g0\n");
2865 fprintf (file
, "\tbx ");
2866 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
2867 fprintf (file
, "\n");
2871 i960_rtx_costs (x
, code
, outer_code
, total
)
2873 int code
, outer_code
;
2878 /* Constants that can be (non-ldconst) insn operands are cost 0.
2879 Constants that can be non-ldconst operands in rare cases are cost 1.
2880 Other constants have higher costs.
2882 Must check for OUTER_CODE of SET for power2_operand, because
2883 reload_cse_move2add calls us with OUTER_CODE of PLUS to decide
2884 when to replace set with add. */
2887 if ((INTVAL (x
) >= 0 && INTVAL (x
) < 32)
2888 || (outer_code
== SET
&& power2_operand (x
, VOIDmode
)))
2893 else if (INTVAL (x
) >= -31 && INTVAL (x
) < 0)
2903 *total
= (TARGET_C_SERIES
? 6 : 8);
2907 if (x
== CONST0_RTX (DFmode
) || x
== CONST0_RTX (SFmode
)
2908 || x
== CONST1_RTX (DFmode
) || x
== CONST1_RTX (SFmode
))