1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 ;; Contributed by Axis Communications.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
28 ;; The function cris_notice_update_cc in cris.c handles condition code
29 ;; updates for most instructions, helped by the "cc" attribute.
31 ;; There are several instructions that are orthogonal in size, and seems
32 ;; they could be matched by a single pattern without a specified size
33 ;; for the operand that is orthogonal. However, this did not work on
34 ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
35 ;; constant is substituted into an operand, the actual mode must be
36 ;; deduced from the pattern. There is reasonable hope that that has been
37 ;; fixed, so FIXME: try again.
39 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
40 ;; are marked with a "!" constraint modifier to avoid being reloaded
41 ;; into. This is because gcc would otherwise prefer to use the constant
42 ;; pool and its offsettable address instead of reloading to an
43 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
44 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
46 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
47 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
48 ;; pointer). Thus the instructions that get into trouble have specific
49 ;; checks against matching frame_pointer_rtx.
50 ;; ??? But it should be re-checked for gcc > 2.7.2
51 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
53 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
54 ;; [rX=gotless_symbol].
55 ;; The movsi for a gotless symbol could be split (post reload).
58 ;; 0 PLT reference from call expansion: operand 0 is the address,
59 ;; the mode is VOIDmode. Always wrapped in CONST.
61 ;; We need an attribute to define whether an instruction can be put in
62 ;; a branch-delay slot or not, and whether it has a delay slot.
64 ;; Branches and return instructions have a delay slot, and cannot
65 ;; themselves be put in a delay slot. This has changed *for short
66 ;; branches only* between architecture variants, but the possible win
67 ;; is presumed negligible compared to the added complexity of the machine
68 ;; description: one would have to add always-correct infrastructure to
69 ;; distinguish short branches.
71 ;; Whether an instruction can be put in a delay slot depends on the
72 ;; instruction (all short instructions except jumps and branches)
73 ;; and the addressing mode (must not be prefixed or referring to pc).
74 ;; In short, any "slottable" instruction must be 16 bit and not refer
75 ;; to pc, or alter it.
77 ;; The possible values are "yes", "no" and "has_slot". Yes/no means if
78 ;; the insn is slottable or not. Has_slot means that the insn is a
79 ;; return insn or branch insn (which are not considered slottable since
80 ;; that is generally true). Having the seemingly illogical value
81 ;; "has_slot" means we do not have to add another attribute just to say
82 ;; that an insn has a delay-slot, since it also infers that it is not
83 ;; slottable. Better names for the attribute were found to be longer and
84 ;; not add readability to the machine description.
86 ;; The default that is defined here for this attribute is "no", not
87 ;; slottable, not having a delay-slot, so there's no need to worry about
88 ;; it being wrong for non-branch and return instructions.
89 ;; The default could depend on the kind of insn and the addressing
90 ;; mode, but that would need more attributes and hairier, more error
93 ;; There is an extra constraint, 'Q', which recognizes indirect reg,
94 ;; except when the reg is pc. The constraints 'Q' and '>' together match
95 ;; all possible memory operands that are slottable.
96 ;; For other operands, you need to check if it has a valid "slottable"
97 ;; quick-immediate operand, where the particular signedness-variation
98 ;; may match the constraints 'I' or 'J'.), and include it in the
99 ;; constraint pattern for the slottable pattern. An alternative using
100 ;; only "r" constraints is most often slottable.
102 (define_attr "slottable" "no,yes,has_slot" (const_string "no"))
104 ;; We also need attributes to sanely determine the condition code
105 ;; state. See cris_notice_update_cc for how this is used.
107 (define_attr "cc" "none,clobber,normal" (const_string "normal"))
109 ;; A branch or return has one delay-slot. The instruction in the
110 ;; delay-slot is always executed, independent of whether the branch is
111 ;; taken or not. Note that besides setting "slottable" to "has_slot",
112 ;; there also has to be a "%#" at the end of a "delayed" instruction
113 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
114 ;; catch it and print a "nop" if necessary. This method was stolen from
117 (define_delay (eq_attr "slottable" "has_slot")
118 [(eq_attr "slottable" "yes") (nil) (nil)])
124 ;; Allow register and offsettable mem operands only; post-increment is
125 ;; not worth the trouble.
129 (match_operand:DI 0 "nonimmediate_operand" "r,o"))]
131 "test.d %M0\;ax\;test.d %H0")
133 ;; No test insns with side-effect on the mem addressing.
135 ;; See note on cmp-insns with side-effects (or lack of them)
137 ;; Normal named test patterns from SI on.
138 ;; FIXME: Seems they should change to be in order smallest..largest.
142 (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m"))]
145 [(set_attr "slottable" "yes,yes,no")])
149 (match_operand:HI 0 "nonimmediate_operand" "r,Q>,m"))]
152 [(set_attr "slottable" "yes,yes,no")])
156 (match_operand:QI 0 "nonimmediate_operand" "r,Q>,m"))]
159 [(set_attr "slottable" "yes,yes,no")])
161 ;; It seems that the position of the sign-bit and the fact that 0.0 is
162 ;; all 0-bits would make "tstsf" a straight-forward implementation;
163 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
166 ;; FIXME: Do that some time; check next_cc0_user to determine if
167 ;; zero or negative is tested for.
171 ;; We could optimize the sizes of the immediate operands for various
172 ;; cases, but that is not worth it because of the very little usage of
173 ;; DImode for anything else but a structure/block-mode. Just do the
174 ;; obvious stuff for the straight-forward constraint letters.
178 (compare (match_operand:DI 0 "nonimmediate_operand" "r,r,r,r,r,r,o")
179 (match_operand:DI 1 "general_operand" "K,I,P,n,r,o,r")))]
182 cmpq %1,%M0\;ax\;cmpq 0,%H0
183 cmpq %1,%M0\;ax\;cmpq -1,%H0
184 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
185 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
186 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
187 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
188 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
190 ;; Note that compare insns with side effect addressing mode (e.g.):
192 ;; cmp.S [rx=ry+i],rz;
193 ;; cmp.S [%3=%1+%2],%0
195 ;; are *not* usable for gcc since the reloader *does not accept*
196 ;; cc0-changing insns with side-effects other than setting the condition
197 ;; codes. The reason is that the reload stage *may* cause another insn to
198 ;; be output after the main instruction, in turn invalidating cc0 for the
199 ;; insn using the test. (This does not apply to the CRIS case, since a
200 ;; reload for output -- move to memory -- does not change the condition
201 ;; code. Unfortunately we have no way to describe that at the moment. I
202 ;; think code would improve being in the order of one percent faster.
204 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
205 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
206 ;; constants, but sometimes gcc will find its way to use it for other
207 ;; (memory) operands. Avoid side-effect patterns, though (see above).
209 ;; FIXME: These could have an anonymous mode for operand 1.
213 (define_insn "*cmp_extsi"
216 (match_operand:SI 0 "register_operand" "r,r")
217 (match_operator:SI 2 "cris_extend_operator"
218 [(match_operand:QI 1 "memory_operand" "Q>,m")])))]
221 [(set_attr "slottable" "yes,no")])
224 (define_insn "*cmp_exthi"
227 (match_operand:SI 0 "register_operand" "r,r")
228 (match_operator:SI 2 "cris_extend_operator"
229 [(match_operand:HI 1 "memory_operand" "Q>,m")])))]
232 [(set_attr "slottable" "yes,no")])
234 ;; Swap operands; it seems the canonical look (if any) is not enforced.
236 ;; FIXME: Investigate that.
237 ;; FIXME: These could have an anonymous mode for operand 1.
241 (define_insn "*cmp_swapextqi"
244 (match_operator:SI 2 "cris_extend_operator"
245 [(match_operand:QI 0 "memory_operand" "Q>,m")])
246 (match_operand:SI 1 "register_operand" "r,r")))]
248 "cmp%e2.%s0 %0,%1" ; The function cris_notice_update_cc knows about
249 ; swapped operands to compares.
250 [(set_attr "slottable" "yes,no")])
254 (define_insn "*cmp_swapexthi"
257 (match_operator:SI 2 "cris_extend_operator"
258 [(match_operand:HI 0 "memory_operand" "Q>,m")])
259 (match_operand:SI 1 "register_operand" "r,r")))]
261 "cmp%e2.%s0 %0,%1" ; The function cris_notice_update_cc knows about
262 ; swapped operands to compares.
263 [(set_attr "slottable" "yes,no")])
265 ;; The "normal" compare patterns, from SI on.
270 (match_operand:SI 0 "nonimmediate_operand" "r,r,r,r,Q>,Q>,r,r,m,m")
271 (match_operand:SI 1 "general_operand" "I,r,Q>,M,M,r,P,g,M,r")))]
284 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no")])
288 (compare (match_operand:HI 0 "nonimmediate_operand" "r,r,Q>,Q>,r,m,m")
289 (match_operand:HI 1 "general_operand" "r,Q>,M,r,g,M,r")))]
299 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")])
304 (match_operand:QI 0 "nonimmediate_operand" "r,r,r,Q>,Q>,r,m,m")
305 (match_operand:QI 1 "general_operand" "r,Q>,M,M,r,g,M,r")))]
316 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
318 ;; Pattern matching the BTST insn.
319 ;; It is useful for "if (i & val)" constructs, where val is an exact
320 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
321 ;; of zeros starting at bit 0).
323 ;; SImode. This mode is the only one needed, since gcc automatically
324 ;; extends subregs for lower-size modes. FIXME: Add testcase.
328 (match_operand:SI 0 "nonmemory_operand" "r,r,r,r,r,r,n")
329 (match_operand:SI 1 "const_int_operand" "K,n,K,n,K,n,n")
330 (match_operand:SI 2 "nonmemory_operand" "M,M,K,n,r,r,r")))]
331 ;; Either it is a single bit, or consecutive ones starting at 0.
332 "GET_CODE (operands[1]) == CONST_INT
333 && (operands[1] == const1_rtx || operands[2] == const0_rtx)
334 && (REG_S_P (operands[0])
335 || (operands[1] == const1_rtx
336 && REG_S_P (operands[2])
337 && GET_CODE (operands[0]) == CONST_INT
338 && exact_log2 (INTVAL (operands[0])) >= 0))"
340 ;; The last "&&" condition above should be caught by some kind of
341 ;; canonicalization in gcc, but we can easily help with it here.
342 ;; It results from expressions of the type
343 ;; "power_of_2_value & (1 << y)".
345 ;; Since there may be codes with tests in on bits (in constant position)
346 ;; beyond the size of a word, handle that by assuming those bits are 0.
347 ;; GCC should handle that, but it's a matter of easily-added belts while
348 ;; having suspenders.
358 [(set_attr "slottable" "yes")])
362 ;; The whole mandatory movdi family is here; expander, "anonymous"
363 ;; recognizer and splitter. We're forced to have a movdi pattern,
364 ;; although GCC should be able to split it up itself. Normally it can,
365 ;; but if other insns have DI operands (as is the case here), reload
366 ;; must be able to generate or match a movdi. many testcases fail at
367 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
368 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
369 ;; However, a patch from Richard Kenner (similar to the cause of
370 ;; discussion at the URL above), indicates otherwise. See
371 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
372 ;; The truth has IMO is not been decided yet, so check from time to
373 ;; time by disabling the movdi patterns.
375 (define_expand "movdi"
376 [(set (match_operand:DI 0 "nonimmediate_operand" "")
377 (match_operand:DI 1 "general_operand" ""))]
381 if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
382 operands[1] = copy_to_mode_reg (DImode, operands[1]);
384 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
385 prefer to split up constants early, like this. The testcase in
386 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
387 resulting subreg sets when using the construct from mcore (as of FSF
388 CVS, version -r 1.5), and it believes that the high part (the last one
389 emitted) is the final value. This construct from romp seems more
390 robust, especially considering the head comments from
391 emit_no_conflict_block. */
392 if ((GET_CODE (operands[1]) == CONST_INT
393 || GET_CODE (operands[1]) == CONST_DOUBLE)
394 && ! reload_completed
395 && ! reload_in_progress)
398 rtx op0 = operands[0];
399 rtx op1 = operands[1];
402 emit_move_insn (operand_subword (op0, 0, 1, DImode),
403 operand_subword (op1, 0, 1, DImode));
404 emit_move_insn (operand_subword (op0, 1, 1, DImode),
405 operand_subword (op1, 1, 1, DImode));
406 insns = get_insns ();
409 emit_no_conflict_block (insns, op0, op1, 0, op1);
414 (define_insn "*movdi_insn"
415 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
416 (match_operand:DI 1 "general_operand" "r,g,rM"))]
417 "register_operand (operands[0], DImode)
418 || register_operand (operands[1], DImode)
419 || operands[1] == const0_rtx"
423 [(set (match_operand:DI 0 "nonimmediate_operand" "")
424 (match_operand:DI 1 "general_operand" ""))]
427 "operands[2] = cris_split_movdx (operands);")
429 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
430 ;; and move.S1 [rx=ry+i],rz
431 ;; Then movs.S1 and movu.S1 for both modes.
433 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
434 ;; FIXME: These could have anonymous mode for operand 0.
438 (define_insn "*mov_sideqi_biap"
439 [(set (match_operand:QI 0 "register_operand" "=r,r")
441 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
442 (match_operand:SI 2 "const_int_operand" "n,n"))
443 (match_operand:SI 3 "register_operand" "r,r"))))
444 (set (match_operand:SI 4 "register_operand" "=*3,r")
445 (plus:SI (mult:SI (match_dup 1)
448 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
451 move.%s0 [%4=%3+%1%T2],%0")
455 (define_insn "*mov_sidehi_biap"
456 [(set (match_operand:HI 0 "register_operand" "=r,r")
458 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
459 (match_operand:SI 2 "const_int_operand" "n,n"))
460 (match_operand:SI 3 "register_operand" "r,r"))))
461 (set (match_operand:SI 4 "register_operand" "=*3,r")
462 (plus:SI (mult:SI (match_dup 1)
465 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
468 move.%s0 [%4=%3+%1%T2],%0")
472 (define_insn "*mov_sidesi_biap"
473 [(set (match_operand:SI 0 "register_operand" "=r,r")
475 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
476 (match_operand:SI 2 "const_int_operand" "n,n"))
477 (match_operand:SI 3 "register_operand" "r,r"))))
478 (set (match_operand:SI 4 "register_operand" "=*3,r")
479 (plus:SI (mult:SI (match_dup 1)
482 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
485 move.%s0 [%4=%3+%1%T2],%0")
487 ;; move.S1 [rx=ry+i],rz
488 ;; avoiding move.S1 [ry=ry+i],rz
489 ;; and move.S1 [rz=ry+i],rz
490 ;; Note that "i" is allowed to be a register.
491 ;; FIXME: These could have anonymous mode for operand 0.
495 (define_insn "*mov_sideqi"
496 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
498 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
499 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
500 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
501 (plus:SI (match_dup 1)
503 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
506 if (which_alternative == 0
507 && (GET_CODE (operands[2]) != CONST_INT
508 || INTVAL (operands[2]) > 127
509 || INTVAL (operands[2]) < -128
510 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
511 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
513 return \"move.%s0 [%3=%1%S2],%0\";
518 (define_insn "*mov_sidehi"
519 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
521 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
522 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
523 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
524 (plus:SI (match_dup 1)
526 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
529 if (which_alternative == 0
530 && (GET_CODE (operands[2]) != CONST_INT
531 || INTVAL (operands[2]) > 127
532 || INTVAL (operands[2]) < -128
533 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
534 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
536 return \"move.%s0 [%3=%1%S2],%0\";
541 (define_insn "*mov_sidesi"
542 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
544 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
545 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
546 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
547 (plus:SI (match_dup 1)
549 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
552 if (which_alternative == 0
553 && (GET_CODE (operands[2]) != CONST_INT
554 || INTVAL (operands[2]) > 127
555 || INTVAL (operands[2]) < -128
556 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
557 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
559 return \"move.%s0 [%3=%1%S2],%0\";
562 ;; Other way around; move to memory.
564 ;; Note that the condition (which for side-effect patterns is usually a
565 ;; call to cris_side_effect_mode_ok), isn't consulted for register
566 ;; allocation preferences -- constraints is the method for that. The
567 ;; drawback is that we can't exclude register allocation to cause
568 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
569 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
570 ;; Instead of that, we recognize and split the cases where dangerous
571 ;; register combinations are spotted: where a register is set in the
572 ;; side-effect, and used in the main insn. We don't handle the case where
573 ;; the set in the main insn overlaps the set in the side-effect; that case
574 ;; must be handled in gcc. We handle just the case where the set in the
575 ;; side-effect overlaps the input operand of the main insn (i.e. just
579 ;; move.s rz,[ry=rx+rw.S]
580 ;; FIXME: These could have anonymous mode for operand 3.
584 (define_insn "*mov_sideqi_biap_mem"
585 [(set (mem:QI (plus:SI
586 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
587 (match_operand:SI 1 "const_int_operand" "n,n,n"))
588 (match_operand:SI 2 "register_operand" "r,r,r")))
589 (match_operand:QI 3 "register_operand" "r,r,r"))
590 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
591 (plus:SI (mult:SI (match_dup 0)
594 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
598 move.%s3 %3,[%4=%2+%0%T1]")
602 (define_insn "*mov_sidehi_biap_mem"
603 [(set (mem:HI (plus:SI
604 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
605 (match_operand:SI 1 "const_int_operand" "n,n,n"))
606 (match_operand:SI 2 "register_operand" "r,r,r")))
607 (match_operand:HI 3 "register_operand" "r,r,r"))
608 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
609 (plus:SI (mult:SI (match_dup 0)
612 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
616 move.%s3 %3,[%4=%2+%0%T1]")
620 (define_insn "*mov_sidesi_biap_mem"
621 [(set (mem:SI (plus:SI
622 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
623 (match_operand:SI 1 "const_int_operand" "n,n,n"))
624 (match_operand:SI 2 "register_operand" "r,r,r")))
625 (match_operand:SI 3 "register_operand" "r,r,r"))
626 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
627 (plus:SI (mult:SI (match_dup 0)
630 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
634 move.%s3 %3,[%4=%2+%0%T1]")
636 ;; Split for the case above where we're out of luck with register
637 ;; allocation (again, the condition isn't checked for that), and we end up
638 ;; with the set in the side-effect getting the same register as the input
643 [(set (match_operator
646 (mult:SI (match_operand:SI 0 "register_operand" "")
647 (match_operand:SI 1 "const_int_operand" ""))
648 (match_operand:SI 2 "register_operand" ""))])
649 (match_operand 3 "register_operand" ""))
650 (set (match_operand:SI 4 "register_operand" "")
651 (plus:SI (mult:SI (match_dup 0)
654 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"
655 [(set (match_dup 5) (match_dup 3))
656 (set (match_dup 4) (match_dup 2))
658 (plus:SI (mult:SI (match_dup 0)
662 = replace_equiv_address (operands[6],
663 gen_rtx_PLUS (SImode,
664 gen_rtx_MULT (SImode,
669 ;; move.s rx,[ry=rz+i]
670 ;; FIXME: These could have anonymous mode for operand 2.
674 (define_insn "*mov_sideqi_mem"
676 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r")
677 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn")))
678 (match_operand:QI 2 "register_operand" "r,r,r,r"))
679 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r")
680 (plus:SI (match_dup 0)
682 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
685 if (which_alternative == 0
686 && (GET_CODE (operands[1]) != CONST_INT
687 || INTVAL (operands[1]) > 127
688 || INTVAL (operands[1]) < -128
689 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
690 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
692 if (which_alternative == 1)
694 return \"move.%s2 %2,[%3=%0%S1]\";
699 (define_insn "*mov_sidehi_mem"
701 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r")
702 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn")))
703 (match_operand:HI 2 "register_operand" "r,r,r,r"))
704 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r")
705 (plus:SI (match_dup 0)
707 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
710 if (which_alternative == 0
711 && (GET_CODE (operands[1]) != CONST_INT
712 || INTVAL (operands[1]) > 127
713 || INTVAL (operands[1]) < -128
714 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
715 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
717 if (which_alternative == 1)
719 return \"move.%s2 %2,[%3=%0%S1]\";
724 (define_insn "*mov_sidesi_mem"
726 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r")
727 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn")))
728 (match_operand:SI 2 "register_operand" "r,r,r,r"))
729 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r")
730 (plus:SI (match_dup 0)
732 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
735 if (which_alternative == 0
736 && (GET_CODE (operands[1]) != CONST_INT
737 || INTVAL (operands[1]) > 127
738 || INTVAL (operands[1]) < -128
739 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
740 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
742 if (which_alternative == 1)
744 return \"move.%s2 %2,[%3=%0%S1]\";
747 ;; Like the biap case, a split where the set in the side-effect gets the
748 ;; same register as the input register to the main insn, since the
749 ;; condition isn't checked at register allocation.
753 [(set (match_operator
756 (match_operand:SI 0 "cris_bdap_operand" "")
757 (match_operand:SI 1 "cris_bdap_operand" ""))])
758 (match_operand 2 "register_operand" ""))
759 (set (match_operand:SI 3 "register_operand" "")
760 (plus:SI (match_dup 0) (match_dup 1)))])]
761 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
762 [(set (match_dup 4) (match_dup 2))
763 (set (match_dup 3) (match_dup 0))
764 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]
767 ;; Clear memory side-effect patterns. It is hard to get to the mode if
768 ;; the MEM was anonymous, so there will be one for each mode.
770 ;; clear.d [ry=rx+rw.s2]
772 (define_insn "*clear_sidesi_biap"
773 [(set (mem:SI (plus:SI
774 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
775 (match_operand:SI 1 "const_int_operand" "n,n"))
776 (match_operand:SI 2 "register_operand" "r,r")))
778 (set (match_operand:SI 3 "register_operand" "=*2,r")
779 (plus:SI (mult:SI (match_dup 0)
782 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
785 clear.d [%3=%2+%0%T1]")
789 (define_insn "*clear_sidesi"
791 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r")
792 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn")))
794 (set (match_operand:SI 2 "register_operand" "=*0,r,r")
795 (plus:SI (match_dup 0)
797 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
800 if (which_alternative == 0
801 && (GET_CODE (operands[1]) != CONST_INT
802 || INTVAL (operands[1]) > 127
803 || INTVAL (operands[1]) < -128
804 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
805 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
807 return \"clear.d [%2=%0%S1]\";
810 ;; clear.w [ry=rx+rw.s2]
812 (define_insn "*clear_sidehi_biap"
813 [(set (mem:HI (plus:SI
814 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
815 (match_operand:SI 1 "const_int_operand" "n,n"))
816 (match_operand:SI 2 "register_operand" "r,r")))
818 (set (match_operand:SI 3 "register_operand" "=*2,r")
819 (plus:SI (mult:SI (match_dup 0)
822 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
825 clear.w [%3=%2+%0%T1]")
829 (define_insn "*clear_sidehi"
831 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r")
832 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn")))
834 (set (match_operand:SI 2 "register_operand" "=*0,r,r")
835 (plus:SI (match_dup 0)
837 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
840 if (which_alternative == 0
841 && (GET_CODE (operands[1]) != CONST_INT
842 || INTVAL (operands[1]) > 127
843 || INTVAL (operands[1]) < -128
844 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
845 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
847 return \"clear.w [%2=%0%S1]\";
850 ;; clear.b [ry=rx+rw.s2]
852 (define_insn "*clear_sideqi_biap"
853 [(set (mem:QI (plus:SI
854 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
855 (match_operand:SI 1 "const_int_operand" "n,n"))
856 (match_operand:SI 2 "register_operand" "r,r")))
858 (set (match_operand:SI 3 "register_operand" "=*2,r")
859 (plus:SI (mult:SI (match_dup 0)
862 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
865 clear.b [%3=%2+%0%T1]")
869 (define_insn "*clear_sideqi"
871 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r")
872 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn")))
874 (set (match_operand:SI 2 "register_operand" "=*0,r,r")
875 (plus:SI (match_dup 0)
877 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
880 if (which_alternative == 0
881 && (GET_CODE (operands[1]) != CONST_INT
882 || INTVAL (operands[1]) > 127
883 || INTVAL (operands[1]) < -128
884 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
885 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
887 return \"clear.b [%2=%0%S1]\";
890 ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at
891 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
892 ;; A cmpdi RTX needs reloading (global):
893 ;; (insn 185 326 186 (set (cc0)
894 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
895 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
897 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
898 ;; out of the instruction (into a register), since one of the operands
899 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
900 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
901 ;; wrt. overlap). The bad things happen with the synthesis in
902 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
903 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
904 ;; 22 is recognized to have an equivalent in memory which is substituted
905 ;; straight in, and we end up with an unrecognizable insn:
906 ;; (insn 325 324 326 (set (reg:SI 9 r9)
907 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
908 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
910 ;; which is the first part of the reloaded synthesized "movdi".
911 ;; The right thing would be to add equivalent replacement locations for
912 ;; insn with pseudos that need more reloading. The question is where.
914 ;; Normal move patterns from SI on.
916 (define_expand "movsi"
918 (match_operand:SI 0 "nonimmediate_operand" "")
919 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]
923 /* If the output goes to a MEM, make sure we have zero or a register as
925 if (GET_CODE (operands[0]) == MEM
926 && ! REG_S_P (operands[1])
927 && operands[1] != const0_rtx
929 operands[1] = force_reg (SImode, operands[1]);
931 /* If we're generating PIC and have an incoming symbol, validize it to a
932 general operand or something that will match a special pattern.
934 FIXME: Do we *have* to recognize anything that would normally be a
935 valid symbol? Can we exclude global PIC addresses with an added
938 && CONSTANT_ADDRESS_P (operands[1])
939 && cris_symbol (operands[1]))
941 /* We must have a register as destination for what we're about to
942 do, and for the patterns we generate. */
943 if (! REG_S_P (operands[0]))
947 operands[1] = force_reg (SImode, operands[1]);
951 /* Mark a needed PIC setup for a LABEL_REF:s coming in here:
952 they are so rare not-being-branch-targets that we don't mark
953 a function as needing PIC setup just because we have
954 inspected LABEL_REF:s as operands. It is only in
955 __builtin_setjmp and such that we can get a LABEL_REF
956 assigned to a register. */
957 if (GET_CODE (operands[1]) == LABEL_REF)
958 current_function_uses_pic_offset_table = 1;
960 /* We don't have to do anything for global PIC operands; they
961 look just like ``[rPIC+sym]''. */
962 if (! cris_got_symbol (operands[1])
963 /* We don't do anything for local PIC operands; we match
964 that with a special alternative. */
965 && ! cris_gotless_symbol (operands[1]))
967 /* We get here when we have to change something that would
968 be recognizable if it wasn't PIC. A ``sym'' is ok for
969 PIC symbols both with and without a GOT entry. And ``sym
970 + offset'' is ok for local symbols, so the only thing it
971 could be, is a global symbol with an offset. Check and
973 rtx sym = get_related_value (operands[1]);
974 HOST_WIDE_INT offs = get_integer_term (operands[1]);
976 if (sym == NULL_RTX || offs == 0)
978 emit_move_insn (operands[0], sym);
979 if (expand_binop (SImode, add_optab, operands[0],
980 GEN_INT (offs), operands[0], 0,
981 OPTAB_LIB_WIDEN) != operands[0])
989 (define_insn "*movsi_internal"
991 (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Q>,r,Q>,g,r,r,r,g")
993 ;; FIXME: We want to put S last, but apparently g matches S.
994 ;; It's a bug: an S is not a general_operand and shouldn't match g.
995 "cris_general_operand_or_gotless_symbol" "r,Q>,M,M,I,r,M,n,!S,g,r"))]
999 /* Better to have c-switch here; it is worth it to optimize the size of
1000 move insns. The alternative would be to try to find more constraint
1001 letters. FIXME: Check again. It seems this could shrink a bit. */
1002 switch (which_alternative)
1009 return \"move.d %1,%0\";
1014 return \"clear.d %0\";
1016 /* Constants -32..31 except 0. */
1018 return \"moveq %1,%0\";
1020 /* We can win a little on constants -32768..-33, 32..65535. */
1022 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
1024 if (INTVAL (operands[1]) < 256)
1025 return \"movu.b %1,%0\";
1026 return \"movu.w %1,%0\";
1028 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
1030 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
1031 return \"movs.b %1,%0\";
1032 return \"movs.w %1,%0\";
1034 return \"move.d %1,%0\";
1037 /* FIXME: Try and split this into pieces GCC makes better code of,
1038 than this multi-insn pattern. Synopsis: wrap the GOT-relative
1039 symbol into an unspec, and when PIC, recognize the unspec
1040 everywhere a symbol is normally recognized. (The PIC register
1041 should be recognized by GCC as pic_offset_table_rtx when needed
1042 and similar for PC.) Each component can then be optimized with
1043 the rest of the code; it should be possible to have a constant
1044 term added on an unspec. Don't forget to add a REG_EQUAL (or
1045 is it REG_EQUIV) note to the destination. It might not be
1048 Note that the 'v' modifier makes PLT references be output as
1049 sym:PLT rather than [rPIC+sym:GOTPLT]. */
1050 return \"move.d %v1,%0\;add.d %P1,%0\";
1053 return \"BOGUS: %1 to %0\";
1056 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no")])
1058 ;; Extend operations with side-effect from mem to register, using
1059 ;; MOVS/MOVU. These are from mem to register only.
1065 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
1066 ;; HImode by itself? Perhaps use only anonymous modes?
1068 (define_insn "*ext_sideqihi_biap"
1069 [(set (match_operand:HI 0 "register_operand" "=r,r")
1071 5 "cris_extend_operator"
1073 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1074 (match_operand:SI 2 "const_int_operand" "n,n"))
1075 (match_operand:SI 3 "register_operand" "r,r")))]))
1076 (set (match_operand:SI 4 "register_operand" "=*3,r")
1077 (plus:SI (mult:SI (match_dup 1)
1080 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1083 mov%e5.%m5 [%4=%3+%1%T2],%0")
1087 (define_insn "*ext_sideqisi_biap"
1088 [(set (match_operand:SI 0 "register_operand" "=r,r")
1090 5 "cris_extend_operator"
1092 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1093 (match_operand:SI 2 "const_int_operand" "n,n"))
1094 (match_operand:SI 3 "register_operand" "r,r")))]))
1095 (set (match_operand:SI 4 "register_operand" "=*3,r")
1096 (plus:SI (mult:SI (match_dup 1)
1099 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1102 mov%e5.%m5 [%4=%3+%1%T2],%0")
1106 (define_insn "*ext_sidehisi_biap"
1107 [(set (match_operand:SI 0 "register_operand" "=r,r")
1109 5 "cris_extend_operator"
1111 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1112 (match_operand:SI 2 "const_int_operand" "n,n"))
1113 (match_operand:SI 3 "register_operand" "r,r")))]))
1114 (set (match_operand:SI 4 "register_operand" "=*3,r")
1115 (plus:SI (mult:SI (match_dup 1)
1118 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1121 mov%e5.%m5 [%4=%3+%1%T2],%0")
1123 ;; Same but [rx=ry+i]
1127 (define_insn "*ext_sideqihi"
1128 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1130 4 "cris_extend_operator"
1132 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
1133 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1134 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
1135 (plus:SI (match_dup 1)
1137 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1140 if (which_alternative == 0
1141 && (GET_CODE (operands[2]) != CONST_INT
1142 || INTVAL (operands[2]) > 127
1143 || INTVAL (operands[2]) < -128
1144 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1145 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1147 return \"mov%e4.%m4 [%3=%1%S2],%0\";
1152 (define_insn "*ext_sideqisi"
1153 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1155 4 "cris_extend_operator"
1157 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
1158 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1159 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
1160 (plus:SI (match_dup 1)
1162 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1165 if (which_alternative == 0
1166 && (GET_CODE (operands[2]) != CONST_INT
1167 || INTVAL (operands[2]) > 127
1168 || INTVAL (operands[2]) < -128
1169 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1170 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1172 return \"mov%e4.%m4 [%3=%1%S2],%0\";
1177 (define_insn "*ext_sidehisi"
1178 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1180 4 "cris_extend_operator"
1182 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
1183 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1184 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
1185 (plus:SI (match_dup 1)
1187 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1190 if (which_alternative == 0
1191 && (GET_CODE (operands[2]) != CONST_INT
1192 || INTVAL (operands[2]) > 127
1193 || INTVAL (operands[2]) < -128
1194 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1195 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1197 return \"mov%e4.%m4 [%3=%1%S2],%0\";
1200 ;; FIXME: See movsi.
1202 (define_insn "movhi"
1204 (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,Q>,r,Q>,r,r,r,g,g,r")
1205 (match_operand:HI 1 "general_operand" "r,Q>,M,M,I,r,L,O,n,M,r,g"))]
1209 switch (which_alternative)
1216 return \"move.w %1,%0\";
1220 return \"clear.w %0\";
1222 return \"moveq %1,%0\";
1225 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
1227 if (INTVAL (operands[1]) > 0)
1228 return \"movu.b %1,%0\";
1229 return \"movs.b %1,%0\";
1231 return \"move.w %1,%0\";
1233 return \"movEq %b1,%0\";
1235 return \"BOGUS: %1 to %0\";
1238 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no")
1240 (if_then_else (eq_attr "alternative" "7")
1241 (const_string "clobber")
1242 (const_string "normal")))])
1244 (define_insn "movstricthi"
1247 (match_operand:HI 0 "nonimmediate_operand" "+r,r,r,Q>,Q>,g,r,g"))
1248 (match_operand:HI 1 "general_operand" "r,Q>,M,M,r,M,g,r"))]
1259 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1261 (define_insn "movqi"
1262 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,r,g,g,r,r")
1263 (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,I,M,r,O,g"))]
1276 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no")
1278 (if_then_else (eq_attr "alternative" "8")
1279 (const_string "clobber")
1280 (const_string "normal")))])
1282 (define_insn "movstrictqi"
1283 [(set (strict_low_part
1284 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r,r,Q>,g,g,r"))
1285 (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,M,r,g"))]
1296 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1298 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
1299 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
1300 ;; all ones); the worthwhile one is "0.0".
1301 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
1303 (define_insn "movsf"
1304 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,g,g,r")
1305 (match_operand:SF 1 "general_operand" "r,r,Q>,G,G,G,r,g"))]
1316 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1319 ;; Sign- and zero-extend insns with standard names.
1320 ;; Those for integer source operand are ordered with the widest source
1325 (define_insn "extendsidi2"
1326 [(set (match_operand:DI 0 "register_operand" "=r")
1327 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
1329 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
1331 (define_insn "extendhidi2"
1332 [(set (match_operand:DI 0 "register_operand" "=r")
1333 (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))]
1335 "movs.w %1,%M0\;smi %H0\;neg.d %H0,%H0")
1337 (define_insn "extendhisi2"
1338 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1339 (sign_extend:SI (match_operand:HI 1 "general_operand" "r,Q>,g")))]
1342 [(set_attr "slottable" "yes,yes,no")])
1344 (define_insn "extendqidi2"
1345 [(set (match_operand:DI 0 "register_operand" "=r")
1346 (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))]
1348 "movs.b %1,%M0\;smi %H0\;neg.d %H0,%H0")
1350 (define_insn "extendqisi2"
1351 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1352 (sign_extend:SI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1355 [(set_attr "slottable" "yes,yes,no")])
1357 ;; To do a byte->word extension, extend to dword, exept that the top half
1358 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1360 (define_insn "extendqihi2"
1361 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1362 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1365 [(set_attr "slottable" "yes,yes,no")])
1368 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1369 ;; specify them here.
1371 (define_insn "zero_extendhisi2"
1372 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1374 (match_operand:HI 1 "nonimmediate_operand" "r,Q>,m")))]
1377 [(set_attr "slottable" "yes,yes,no")])
1379 (define_insn "zero_extendqisi2"
1380 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1382 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1385 [(set_attr "slottable" "yes,yes,no")])
1387 ;; Same comment as sign-extend QImode to HImode above applies.
1389 (define_insn "zero_extendqihi2"
1390 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1392 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1395 [(set_attr "slottable" "yes,yes,no")])
1397 ;; All kinds of arithmetic and logical instructions.
1399 ;; First, anonymous patterns to match addressing modes with
1402 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1405 ;; FIXME: These could have anonymous mode for operand 0.
1409 (define_insn "*op_sideqi_biap"
1410 [(set (match_operand:QI 0 "register_operand" "=r,r")
1412 6 "cris_orthogonal_operator"
1413 [(match_operand:QI 1 "register_operand" "0,0")
1415 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1416 (match_operand:SI 3 "const_int_operand" "n,n"))
1417 (match_operand:SI 4 "register_operand" "r,r")))]))
1418 (set (match_operand:SI 5 "register_operand" "=*4,r")
1419 (plus:SI (mult:SI (match_dup 2)
1422 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1425 %x6.%s0 [%5=%4+%2%T3],%0")
1429 (define_insn "*op_sidehi_biap"
1430 [(set (match_operand:HI 0 "register_operand" "=r,r")
1432 6 "cris_orthogonal_operator"
1433 [(match_operand:HI 1 "register_operand" "0,0")
1435 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1436 (match_operand:SI 3 "const_int_operand" "n,n"))
1437 (match_operand:SI 4 "register_operand" "r,r")))]))
1438 (set (match_operand:SI 5 "register_operand" "=*4,r")
1439 (plus:SI (mult:SI (match_dup 2)
1442 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1445 %x6.%s0 [%5=%4+%2%T3],%0")
1449 (define_insn "*op_sidesi_biap"
1450 [(set (match_operand:SI 0 "register_operand" "=r,r")
1452 6 "cris_orthogonal_operator"
1453 [(match_operand:SI 1 "register_operand" "0,0")
1455 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1456 (match_operand:SI 3 "const_int_operand" "n,n"))
1457 (match_operand:SI 4 "register_operand" "r,r")))]))
1458 (set (match_operand:SI 5 "register_operand" "=*4,r")
1459 (plus:SI (mult:SI (match_dup 2)
1462 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1465 %x6.%s0 [%5=%4+%2%T3],%0")
1467 ;; [rx=ry+i] ([%4=%2+%3])
1468 ;; FIXME: These could have anonymous mode for operand 0.
1472 (define_insn "*op_sideqi"
1473 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
1475 5 "cris_orthogonal_operator"
1476 [(match_operand:QI 1 "register_operand" "0,0,0")
1478 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1479 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1480 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1481 (plus:SI (match_dup 2)
1483 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1486 if (which_alternative == 0
1487 && (GET_CODE (operands[3]) != CONST_INT
1488 || INTVAL (operands[3]) > 127
1489 || INTVAL (operands[3]) < -128
1490 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1491 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1493 return \"%x5.%s0 [%4=%2%S3],%0\";
1498 (define_insn "*op_sidehi"
1499 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1501 5 "cris_orthogonal_operator"
1502 [(match_operand:HI 1 "register_operand" "0,0,0")
1504 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1505 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1506 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1507 (plus:SI (match_dup 2)
1509 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1512 if (which_alternative == 0
1513 && (GET_CODE (operands[3]) != CONST_INT
1514 || INTVAL (operands[3]) > 127
1515 || INTVAL (operands[3]) < -128
1516 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1517 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1519 return \"%x5.%s0 [%4=%2%S3],%0\";
1524 (define_insn "*op_sidesi"
1525 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1527 5 "cris_orthogonal_operator"
1528 [(match_operand:SI 1 "register_operand" "0,0,0")
1530 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1531 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1532 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1533 (plus:SI (match_dup 2)
1535 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1538 if (which_alternative == 0
1539 && (GET_CODE (operands[3]) != CONST_INT
1540 || INTVAL (operands[3]) > 127
1541 || INTVAL (operands[3]) < -128
1542 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1543 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1545 return \"%x5.%s0 [%4=%2%S3],%0\";
1548 ;; To match all cases for commutative operations we may have to have the
1549 ;; following pattern for add, or & and. I do not know really, but it does
1550 ;; not break anything.
1552 ;; FIXME: This really ought to be checked.
1554 ;; op.S [rx=ry+I],rz;
1557 ;; FIXME: These could have anonymous mode for operand 0.
1561 (define_insn "*op_swap_sideqi_biap"
1562 [(set (match_operand:QI 0 "register_operand" "=r,r")
1564 6 "cris_commutative_orth_op"
1566 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1567 (match_operand:SI 3 "const_int_operand" "n,n"))
1568 (match_operand:SI 4 "register_operand" "r,r")))
1569 (match_operand:QI 1 "register_operand" "0,0")]))
1570 (set (match_operand:SI 5 "register_operand" "=*4,r")
1571 (plus:SI (mult:SI (match_dup 2)
1574 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1577 %x6.%s0 [%5=%4+%2%T3],%0")
1581 (define_insn "*op_swap_sidehi_biap"
1582 [(set (match_operand:HI 0 "register_operand" "=r,r")
1584 6 "cris_commutative_orth_op"
1586 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1587 (match_operand:SI 3 "const_int_operand" "n,n"))
1588 (match_operand:SI 4 "register_operand" "r,r")))
1589 (match_operand:HI 1 "register_operand" "0,0")]))
1590 (set (match_operand:SI 5 "register_operand" "=*4,r")
1591 (plus:SI (mult:SI (match_dup 2)
1594 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1597 %x6.%s0 [%5=%4+%2%T3],%0")
1601 (define_insn "*op_swap_sidesi_biap"
1602 [(set (match_operand:SI 0 "register_operand" "=r,r")
1604 6 "cris_commutative_orth_op"
1606 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1607 (match_operand:SI 3 "const_int_operand" "n,n"))
1608 (match_operand:SI 4 "register_operand" "r,r")))
1609 (match_operand:SI 1 "register_operand" "0,0")]))
1610 (set (match_operand:SI 5 "register_operand" "=*4,r")
1611 (plus:SI (mult:SI (match_dup 2)
1614 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1617 %x6.%s0 [%5=%4+%2%T3],%0")
1619 ;; [rx=ry+i] ([%4=%2+%3])
1620 ;; FIXME: These could have anonymous mode for operand 0.
1624 (define_insn "*op_swap_sideqi"
1625 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
1627 5 "cris_commutative_orth_op"
1629 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1630 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))
1631 (match_operand:QI 1 "register_operand" "0,0,0")]))
1632 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1633 (plus:SI (match_dup 2)
1635 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1638 if (which_alternative == 0
1639 && (GET_CODE (operands[3]) != CONST_INT
1640 || INTVAL (operands[3]) > 127
1641 || INTVAL (operands[3]) < -128
1642 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1643 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1645 return \"%x5.%s0 [%4=%2%S3],%0\";
1650 (define_insn "*op_swap_sidehi"
1651 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1653 5 "cris_commutative_orth_op"
1655 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1656 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))
1657 (match_operand:HI 1 "register_operand" "0,0,0")]))
1658 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1659 (plus:SI (match_dup 2)
1661 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1664 if (which_alternative == 0
1665 && (GET_CODE (operands[3]) != CONST_INT
1666 || INTVAL (operands[3]) > 127
1667 || INTVAL (operands[3]) < -128
1668 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1669 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1671 return \"%x5.%s0 [%4=%2%S3],%0\";
1676 (define_insn "*op_swap_sidesi"
1677 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1679 5 "cris_commutative_orth_op"
1681 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1682 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))
1683 (match_operand:SI 1 "register_operand" "0,0,0")]))
1684 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1685 (plus:SI (match_dup 2)
1687 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1690 if (which_alternative == 0
1691 && (GET_CODE (operands[3]) != CONST_INT
1692 || INTVAL (operands[3]) > 127
1693 || INTVAL (operands[3]) < -128
1694 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1695 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1697 return \"%x5.%s0 [%4=%2%S3],%0\";
1700 ;; Add operations, standard names.
1702 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1703 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1705 (define_insn "adddi3"
1706 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1707 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
1708 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1711 addq %2,%M0\;ax\;addq 0,%H0
1712 subq %n2,%M0\;ax\;subq 0,%H0
1713 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
1714 add.d %M2,%M0\;ax\;add.d %H2,%H0
1715 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1717 (define_insn "addsi3"
1718 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1720 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r")
1721 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))]
1723 ;; The last constraint is due to that after reload, the '%' is not
1724 ;; honored, and canonicalization doesn't care about keeping the same
1725 ;; register as in destination. This will happen after insn splitting.
1726 ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x
1731 switch (which_alternative)
1735 return \"add.d %2,%0\";
1737 return \"addq %2,%0\";
1739 return \"subq %n2,%0\";
1741 /* 'Known value', but not in -63..63.
1742 Check if addu/subu may be used. */
1743 if (INTVAL (operands[2]) > 0)
1745 if (INTVAL (operands[2]) < 256)
1746 return \"addu.b %2,%0\";
1747 if (INTVAL (operands[2]) < 65536)
1748 return \"addu.w %2,%0\";
1752 if (INTVAL (operands[2]) >= -255)
1753 return \"subu.b %n2,%0\";
1754 if (INTVAL (operands[2]) >= -65535)
1755 return \"subu.w %n2,%0\";
1757 return \"add.d %2,%0\";
1759 return \"add.d %2,%1,%0\";
1761 return \"add.d %2,%0\";
1763 return \"add.d %1,%0\";
1765 return \"BOGUS addsi %2+%1 to %0\";
1768 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")])
1770 (define_insn "addhi3"
1771 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
1772 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r")
1773 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1782 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1783 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1785 (define_insn "addqi3"
1786 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r,r")
1787 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,r")
1788 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1798 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1799 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1803 ;; Note that because of insn canonicalization these will *seldom* but
1804 ;; rarely be used with a known constant as an operand.
1806 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1807 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1809 (define_insn "subdi3"
1810 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1811 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1812 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1815 subq %2,%M0\;ax\;subq 0,%H0
1816 addq %n2,%M0\;ax\;addq 0,%H0
1817 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1818 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1819 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1821 (define_insn "subsi3"
1822 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1824 (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0,r")
1825 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
1828 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
1829 ;; But then again, %2 should not be negative.
1840 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
1842 (define_insn "subhi3"
1843 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
1844 (minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,r")
1845 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1854 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1855 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1857 (define_insn "subqi3"
1858 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
1859 (minus:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,r")
1860 (match_operand:QI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1869 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1870 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1872 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
1873 ;; Although these perform sign/zero-extension to SImode, they are
1874 ;; equally applicable for the HImode case.
1875 ;; FIXME: Check; GCC should handle the widening.
1876 ;; Note that these must be located after the normal add/sub patterns,
1877 ;; so not to get constants into any less specific operands.
1879 ;; Extend with add/sub and side-effect.
1881 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
1883 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
1884 ;; FIXME: These could have anonymous mode for operand 0.
1887 ;; FIXME: GCC should widen.
1889 (define_insn "*extopqihi_side_biap"
1890 [(set (match_operand:HI 0 "register_operand" "=r,r")
1892 6 "cris_additive_operand_extend_operator"
1893 [(match_operand:HI 1 "register_operand" "0,0")
1895 7 "cris_extend_operator"
1897 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1898 (match_operand:SI 3 "const_int_operand" "n,n"))
1899 (match_operand:SI 4 "register_operand" "r,r")))])]))
1900 (set (match_operand:SI 5 "register_operand" "=*4,r")
1901 (plus:SI (mult:SI (match_dup 2)
1904 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1907 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1911 (define_insn "*extopqisi_side_biap"
1912 [(set (match_operand:SI 0 "register_operand" "=r,r")
1914 6 "cris_operand_extend_operator"
1915 [(match_operand:SI 1 "register_operand" "0,0")
1917 7 "cris_extend_operator"
1919 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1920 (match_operand:SI 3 "const_int_operand" "n,n"))
1921 (match_operand:SI 4 "register_operand" "r,r")))])]))
1922 (set (match_operand:SI 5 "register_operand" "=*4,r")
1923 (plus:SI (mult:SI (match_dup 2)
1926 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
1927 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1930 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1934 (define_insn "*extophisi_side_biap"
1935 [(set (match_operand:SI 0 "register_operand" "=r,r")
1937 6 "cris_operand_extend_operator"
1938 [(match_operand:SI 1 "register_operand" "0,0")
1940 7 "cris_extend_operator"
1942 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1943 (match_operand:SI 3 "const_int_operand" "n,n"))
1944 (match_operand:SI 4 "register_operand" "r,r")))])]))
1945 (set (match_operand:SI 5 "register_operand" "=*4,r")
1946 (plus:SI (mult:SI (match_dup 2)
1949 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
1950 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1953 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1957 ;; FIXME: These could have anonymous mode for operand 0.
1961 (define_insn "*extopqihi_side"
1962 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1964 5 "cris_additive_operand_extend_operator"
1965 [(match_operand:HI 1 "register_operand" "0,0,0")
1967 6 "cris_extend_operator"
1969 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1970 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")
1972 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1973 (plus:SI (match_dup 2)
1975 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1978 if (which_alternative == 0
1979 && (GET_CODE (operands[3]) != CONST_INT
1980 || INTVAL (operands[3]) > 127
1981 || INTVAL (operands[3]) < -128
1982 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1983 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1985 return \"%x5%e6.%m6 [%4=%2%S3],%0\";
1990 (define_insn "*extopqisi_side"
1991 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1993 5 "cris_operand_extend_operator"
1994 [(match_operand:SI 1 "register_operand" "0,0,0")
1996 6 "cris_extend_operator"
1998 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1999 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")
2001 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2002 (plus:SI (match_dup 2)
2005 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2006 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2009 if (which_alternative == 0
2010 && (GET_CODE (operands[3]) != CONST_INT
2011 || INTVAL (operands[3]) > 127
2012 || INTVAL (operands[3]) < -128
2013 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2014 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2016 return \"%x5%e6.%m6 [%4=%2%S3],%0\";
2021 (define_insn "*extophisi_side"
2022 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2024 5 "cris_operand_extend_operator"
2025 [(match_operand:SI 1 "register_operand" "0,0,0")
2027 6 "cris_extend_operator"
2029 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2030 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")
2032 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2033 (plus:SI (match_dup 2)
2035 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2036 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2039 if (which_alternative == 0
2040 && (GET_CODE (operands[3]) != CONST_INT
2041 || INTVAL (operands[3]) > 127
2042 || INTVAL (operands[3]) < -128
2043 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2044 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2046 return \"%x5%e6.%m6 [%4=%2%S3],%0\";
2050 ;; As with op.S we may have to add special pattern to match commuted
2051 ;; operands to adds/addu and bound
2053 ;; adds/addu/bound [rx=ry+rz.S]
2056 ;; FIXME: GCC should widen.
2058 (define_insn "*extopqihi_swap_side_biap"
2059 [(set (match_operand:HI 0 "register_operand" "=r,r")
2062 6 "cris_extend_operator"
2064 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2065 (match_operand:SI 3 "const_int_operand" "n,n"))
2066 (match_operand:SI 4 "register_operand" "r,r")))])
2067 (match_operand:HI 1 "register_operand" "0,0")))
2068 (set (match_operand:SI 5 "register_operand" "=*4,r")
2069 (plus:SI (mult:SI (match_dup 2)
2072 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2075 add%e6.b [%5=%4+%2%T3],%0")
2079 (define_insn "*extopqisi_swap_side_biap"
2080 [(set (match_operand:SI 0 "register_operand" "=r,r")
2082 7 "cris_plus_or_bound_operator"
2084 6 "cris_extend_operator"
2086 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2087 (match_operand:SI 3 "const_int_operand" "n,n"))
2088 (match_operand:SI 4 "register_operand" "r,r")))])
2089 (match_operand:SI 1 "register_operand" "0,0")]))
2090 (set (match_operand:SI 5 "register_operand" "=*4,r")
2091 (plus:SI (mult:SI (match_dup 2)
2094 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2095 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2098 %x7%e6.%m6 [%5=%4+%2%T3],%0")
2101 (define_insn "*extophisi_swap_side_biap"
2102 [(set (match_operand:SI 0 "register_operand" "=r,r")
2104 7 "cris_plus_or_bound_operator"
2106 6 "cris_extend_operator"
2108 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2109 (match_operand:SI 3 "const_int_operand" "n,n"))
2110 (match_operand:SI 4 "register_operand" "r,r")))])
2111 (match_operand:SI 1 "register_operand" "0,0")]))
2112 (set (match_operand:SI 5 "register_operand" "=*4,r")
2113 (plus:SI (mult:SI (match_dup 2)
2116 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2117 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2120 %x7%e6.%m6 [%5=%4+%2%T3],%0")
2123 ;; FIXME: These could have anonymous mode for operand 0.
2124 ;; FIXME: GCC should widen.
2128 (define_insn "*extopqihi_swap_side"
2129 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2132 5 "cris_extend_operator"
2134 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2135 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])
2136 (match_operand:HI 1 "register_operand" "0,0,0")))
2137 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2138 (plus:SI (match_dup 2)
2140 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2143 if (which_alternative == 0
2144 && (GET_CODE (operands[3]) != CONST_INT
2145 || INTVAL (operands[3]) > 127
2146 || INTVAL (operands[3]) < -128
2147 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2148 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2150 return \"add%e5.b [%4=%2%S3],%0\";
2155 (define_insn "*extopqisi_swap_side"
2156 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2158 6 "cris_plus_or_bound_operator"
2160 5 "cris_extend_operator"
2162 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2163 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])
2164 (match_operand:SI 1 "register_operand" "0,0,0")]))
2165 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2166 (plus:SI (match_dup 2)
2168 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2169 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2172 if (which_alternative == 0
2173 && (GET_CODE (operands[3]) != CONST_INT
2174 || INTVAL (operands[3]) > 127
2175 || INTVAL (operands[3]) < -128
2176 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2177 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2179 return \"%x6%e5.%m5 [%4=%2%S3],%0\";
2184 (define_insn "*extophisi_swap_side"
2185 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2187 6 "cris_plus_or_bound_operator"
2189 5 "cris_extend_operator"
2191 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2192 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])
2193 (match_operand:SI 1 "register_operand" "0,0,0")]))
2194 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2195 (plus:SI (match_dup 2)
2197 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2198 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2201 if (which_alternative == 0
2202 && (GET_CODE (operands[3]) != CONST_INT
2203 || INTVAL (operands[3]) > 127
2204 || INTVAL (operands[3]) < -128
2205 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2206 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2208 return \"%x6%e5.%m5 [%4=%2%S3],%0\";
2211 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
2212 ;; FIXME: These could have anonymous mode for operand 0.
2215 ;; FIXME: GCC should widen.
2217 (define_insn "*extopqihi"
2218 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2220 3 "cris_additive_operand_extend_operator"
2221 [(match_operand:HI 1 "register_operand" "0,0,0,r")
2223 4 "cris_extend_operator"
2224 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2225 "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2226 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2231 %x3%e4.%m4 %2,%1,%0"
2232 [(set_attr "slottable" "yes,yes,no,no")
2233 (set_attr "cc" "clobber")])
2237 (define_insn "*extopqisi"
2238 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2240 3 "cris_operand_extend_operator"
2241 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2243 4 "cris_extend_operator"
2244 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2245 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2246 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2247 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2252 %x3%e4.%m4 %2,%1,%0"
2253 [(set_attr "slottable" "yes,yes,no,no")])
2257 (define_insn "*extophisi"
2258 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2260 3 "cris_operand_extend_operator"
2261 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2263 4 "cris_extend_operator"
2264 [(match_operand:HI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2265 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2266 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2267 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2272 %x3%e4.%m4 %2,%1,%0"
2273 [(set_attr "slottable" "yes,yes,no,no")])
2276 ;; As with the side-effect patterns, may have to have swapped operands for add.
2277 ;; FIXME: *should* be redundant to gcc.
2281 (define_insn "*extopqihi_swap"
2282 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2285 3 "cris_extend_operator"
2286 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2287 (match_operand:HI 1 "register_operand" "0,0,0,r")))]
2288 "operands[1] != frame_pointer_rtx"
2294 [(set_attr "slottable" "yes,yes,no,no")
2295 (set_attr "cc" "clobber")])
2299 (define_insn "*extopqisi_swap"
2300 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2302 4 "cris_plus_or_bound_operator"
2304 3 "cris_extend_operator"
2305 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2306 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2307 "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
2308 && operands[1] != frame_pointer_rtx"
2313 %x4%e3.%m3 %2,%1,%0"
2314 [(set_attr "slottable" "yes,yes,no,no")])
2318 (define_insn "*extophisi_swap"
2319 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2321 4 "cris_plus_or_bound_operator"
2323 3 "cris_extend_operator"
2324 [(match_operand:HI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2325 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2326 "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
2327 && operands[1] != frame_pointer_rtx"
2332 %x4%e3.%m3 %2,%1,%0"
2333 [(set_attr "slottable" "yes,yes,no,no")])
2335 ;; This is the special case when we use what corresponds to the
2336 ;; instruction above in "casesi". Do *not* change it to use the generic
2337 ;; pattern and "REG 15" as pc; I did that and it led to madness and
2338 ;; maintenance problems: Instead of (as imagined) recognizing and removing
2339 ;; or replacing this pattern with something simpler, other variant
2340 ;; patterns were recognized or combined, including some prefix variants
2341 ;; where the value in pc is not that of the next instruction (which means
2342 ;; this instruction actually *is* special and *should* be marked as such).
2343 ;; When switching from the "generic pattern match" approach to this simpler
2344 ;; approach, there were insignificant differences in gcc, ipps and
2345 ;; product code, somehow due to scratching reload behind the ear or
2346 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
2347 ;; product code became .001% smaller but "looked better". The testcase
2348 ;; "ipps" was just different at register allocation).
2350 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
2351 ;; pattern with the default-label as the else, with the "if" being
2352 ;; index-is-less-than the max number of cases plus one. The default-label
2353 ;; is attached to the end of the case-table at time of output.
2355 (define_insn "*casesi_adds_w"
2358 (ltu (match_operand:SI 0 "register_operand" "r")
2359 (match_operand:SI 1 "const_int_operand" "n"))
2360 (plus:SI (sign_extend:SI
2362 (plus:SI (mult:SI (match_dup 0) (const_int 2))
2365 (label_ref (match_operand 2 "" ""))))
2366 (use (label_ref (match_operand 3 "" "")))]
2368 "operands[0] != frame_pointer_rtx"
2370 "adds.w [$pc+%0.w],$pc"
2371 [(set_attr "cc" "clobber")])
2373 ;; Multiply instructions.
2375 ;; Sometimes powers of 2 (which are normally canonicalized to a
2376 ;; left-shift) appear here, as a result of address reloading.
2377 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
2379 ;; FIXME: This may be unnecessary now.
2380 ;; Explicitly named for convenience of having a gen_... function.
2382 (define_insn "addi_mul"
2383 [(set (match_operand:SI 0 "register_operand" "=r")
2385 (match_operand:SI 1 "register_operand" "%0")
2386 (match_operand:SI 2 "const_int_operand" "n")))]
2387 "operands[0] != frame_pointer_rtx
2388 && operands[1] != frame_pointer_rtx
2389 && GET_CODE (operands[2]) == CONST_INT
2390 && (INTVAL (operands[2]) == 2
2391 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
2392 || INTVAL (operands[2]) == 5)"
2395 if (INTVAL (operands[2]) == 2)
2396 return \"lslq 1,%0\";
2397 else if (INTVAL (operands[2]) == 4)
2398 return \"lslq 2,%0\";
2399 else if (INTVAL (operands[2]) == 3)
2400 return \"addi %0.w,%0\";
2401 else if (INTVAL (operands[2]) == 5)
2402 return \"addi %0.d,%0\";
2403 return \"BAD: adr_mulsi: %0=%1*%2\";
2405 [(set_attr "slottable" "yes")
2406 ;; No flags are changed if this insn is "addi", but it does not seem
2407 ;; worth the trouble to distinguish that to the lslq cases.
2408 (set_attr "cc" "clobber")])
2410 ;; The addi insn as it is normally used.
2412 (define_insn "*addi"
2413 [(set (match_operand:SI 0 "register_operand" "=r")
2415 (mult:SI (match_operand:SI 2 "register_operand" "r")
2416 (match_operand:SI 3 "const_int_operand" "n"))
2417 (match_operand:SI 1 "register_operand" "0")))]
2418 "operands[0] != frame_pointer_rtx
2419 && operands[1] != frame_pointer_rtx
2420 && GET_CODE (operands[3]) == CONST_INT
2421 && (INTVAL (operands[3]) == 1
2422 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)"
2424 [(set_attr "slottable" "yes")
2425 (set_attr "cc" "none")])
2427 ;; The mstep instruction. Probably not useful by itself; it's to
2428 ;; non-linear wrt. the other insns. We used to expand to it, so at least
2431 (define_insn "mstep_shift"
2432 [(set (match_operand:SI 0 "register_operand" "=r")
2434 (lt:SI (cc0) (const_int 0))
2435 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2437 (match_operand:SI 2 "register_operand" "r"))
2438 (ashift:SI (match_operand:SI 3 "register_operand" "0")
2442 [(set_attr "slottable" "yes")])
2444 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
2445 ;; to canonicalize the multiplications.
2447 ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc.
2449 (define_insn "mstep_mul"
2450 [(set (match_operand:SI 0 "register_operand" "=r")
2452 (lt:SI (cc0) (const_int 0))
2453 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2455 (match_operand:SI 2 "register_operand" "r"))
2456 (mult:SI (match_operand:SI 3 "register_operand" "0")
2458 "operands[0] != frame_pointer_rtx
2459 && operands[1] != frame_pointer_rtx
2460 && operands[2] != frame_pointer_rtx
2461 && operands[3] != frame_pointer_rtx"
2463 [(set_attr "slottable" "yes")])
2465 (define_insn "umulhisi3"
2466 [(set (match_operand:SI 0 "register_operand" "=r")
2468 (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2469 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
2470 "TARGET_HAS_MUL_INSNS"
2472 [(set_attr "slottable" "yes")
2473 ;; Just N unusable here, but let's be safe.
2474 (set_attr "cc" "clobber")])
2476 (define_insn "umulqihi3"
2477 [(set (match_operand:HI 0 "register_operand" "=r")
2479 (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2480 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
2481 "TARGET_HAS_MUL_INSNS"
2483 [(set_attr "slottable" "yes")
2484 ;; Not exactly sure, but let's be safe.
2485 (set_attr "cc" "clobber")])
2487 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
2488 ;; confused and will erroneously use it instead of umulhisi3, failing (at
2489 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
2490 ;; Inspection of optab code shows that there must be only one widening
2491 ;; multiplication per mode widened to.
2493 (define_insn "mulsi3"
2494 [(set (match_operand:SI 0 "register_operand" "=r")
2495 (mult:SI (match_operand:SI 1 "register_operand" "0")
2496 (match_operand:SI 2 "register_operand" "r")))]
2497 "TARGET_HAS_MUL_INSNS"
2499 [(set_attr "slottable" "yes")
2500 ;; Just N unusable here, but let's be safe.
2501 (set_attr "cc" "clobber")])
2503 ;; A few multiply variations.
2505 ;; This really extends to SImode, so cc should be considered clobbered.
2507 (define_insn "mulqihi3"
2508 [(set (match_operand:HI 0 "register_operand" "=r")
2510 (sign_extend:HI (match_operand:QI 1 "register_operand" "0"))
2511 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
2512 "TARGET_HAS_MUL_INSNS"
2514 [(set_attr "slottable" "yes")
2515 (set_attr "cc" "clobber")])
2517 (define_insn "mulhisi3"
2518 [(set (match_operand:SI 0 "register_operand" "=r")
2520 (sign_extend:SI (match_operand:HI 1 "register_operand" "0"))
2521 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
2522 "TARGET_HAS_MUL_INSNS"
2524 [(set_attr "slottable" "yes")
2525 ;; Just N unusable here, but let's be safe.
2526 (set_attr "cc" "clobber")])
2528 ;; When needed, we can get the high 32 bits from the overflow
2529 ;; register. We don't care to split and optimize these.
2531 ;; Note that cc0 is still valid after the move-from-overflow-register
2532 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
2534 (define_insn "mulsidi3"
2535 [(set (match_operand:DI 0 "register_operand" "=r")
2537 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
2538 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
2539 "TARGET_HAS_MUL_INSNS"
2540 "muls.d %2,%M0\;move $mof,%H0")
2542 (define_insn "umulsidi3"
2543 [(set (match_operand:DI 0 "register_operand" "=r")
2545 (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
2546 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
2547 "TARGET_HAS_MUL_INSNS"
2548 "mulu.d %2,%M0\;move $mof,%H0")
2550 ;; This pattern would probably not be needed if we add "mof" in its own
2551 ;; register class (and open a can of worms about /not/ pairing it with a
2552 ;; "normal" register). Having multiple register classes here, and
2553 ;; applicable to the v10 variant only, seems worse than having these two
2554 ;; patterns with multi-insn contents for now (may change; having a free
2555 ;; call-clobbered register is worth some trouble).
2557 (define_insn "smulsi3_highpart"
2558 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m")
2562 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
2563 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r,r")))
2565 (clobber (match_scratch:SI 3 "=X,1,1"))]
2566 "TARGET_HAS_MUL_INSNS"
2567 "muls.d %2,%1\;move $mof,%0"
2568 [(set_attr "cc" "clobber")])
2570 (define_insn "umulsi3_highpart"
2571 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m")
2575 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
2576 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r,r")))
2578 (clobber (match_scratch:SI 3 "=X,1,1"))]
2579 "TARGET_HAS_MUL_INSNS"
2580 "mulu.d %2,%1\;move $mof,%0"
2581 [(set_attr "cc" "clobber")])
2583 ;; Divide and modulus instructions. CRIS only has a step instruction.
2585 (define_insn "dstep_shift"
2586 [(set (match_operand:SI 0 "register_operand" "=r")
2588 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2590 (match_operand:SI 2 "register_operand" "r"))
2591 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
2593 (match_operand:SI 4 "register_operand" "2"))
2594 (ashift:SI (match_operand:SI 5 "register_operand" "0")
2598 [(set_attr "slottable" "yes")])
2600 ;; Here's a variant with mult instead of ashift.
2602 ;; FIXME: This should be investigated. Which one matches through combination?
2604 (define_insn "dstep_mul"
2605 [(set (match_operand:SI 0 "register_operand" "=r")
2607 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2609 (match_operand:SI 2 "register_operand" "r"))
2610 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
2612 (match_operand:SI 4 "register_operand" "2"))
2613 (mult:SI (match_operand:SI 5 "register_operand" "0")
2615 "operands[0] != frame_pointer_rtx
2616 && operands[1] != frame_pointer_rtx
2617 && operands[2] != frame_pointer_rtx
2618 && operands[3] != frame_pointer_rtx"
2620 [(set_attr "slottable" "yes")])
2622 ;; Logical operators.
2626 ;; There is no use in defining "anddi3", because gcc can expand this by
2627 ;; itself, and make reasonable code without interference.
2629 ;; If the first operand is memory or a register and is the same as the
2630 ;; second operand, and the third operand is -256 or -65536, we can use
2631 ;; CLEAR instead. Or, if the first operand is a register, and the third
2632 ;; operand is 255 or 65535, we can zero_extend.
2633 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2634 ;; to be common enough to be worthwhile.
2635 ;; FIXME: This should be made obsolete.
2637 (define_expand "andsi3"
2638 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2639 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2640 (match_operand:SI 2 "general_operand" "")))]
2644 if (! (GET_CODE (operands[2]) == CONST_INT
2645 && (((INTVAL (operands[2]) == -256
2646 || INTVAL (operands[2]) == -65536)
2647 && rtx_equal_p (operands[1], operands[0]))
2648 || ((INTVAL (operands[2]) == 255
2649 || INTVAL (operands[2]) == 65535)
2650 && REG_P (operands[0])))))
2652 /* Make intermediate steps if operand0 is not a register or
2653 operand1 is not a register, and hope that the reload pass will
2654 make something useful out of it. Note that the operands are
2655 *not* canonicalized. For the moment, I chicken out on this,
2656 because all or most ports do not describe 'and' with
2657 canonicalized operands, and I seem to remember magic in reload,
2658 checking that operand1 has constraint '%0', in which case
2659 operand0 and operand1 must have similar predicates.
2660 FIXME: Investigate. */
2661 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
2662 rtx reg1 = operands[1];
2666 emit_move_insn (reg0, reg1);
2670 emit_insn (gen_rtx_SET (SImode, reg0,
2671 gen_rtx_AND (SImode, reg1, operands[2])));
2673 /* Make sure we get the right *final* destination. */
2674 if (! REG_P (operands[0]))
2675 emit_move_insn (operands[0], reg0);
2681 ;; Some special cases of andsi3.
2683 (define_insn "*andsi_movu"
2684 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2685 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q>,m")
2686 (match_operand:SI 2 "const_int_operand" "n,n,n")))]
2687 "INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535"
2689 [(set_attr "slottable" "yes,yes,no")])
2691 (define_insn "*andsi_clear"
2692 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q>,Q>,m,m")
2693 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
2694 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
2695 "INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256"
2703 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2704 (set_attr "cc" "none")])
2706 ;; This is a catch-all pattern, taking care of everything that was not
2707 ;; matched in the insns above.
2709 ;; Sidenote: the tightening from "nonimmediate_operand" to
2710 ;; "register_operand" for operand 1 actually increased the register
2711 ;; pressure (worse code). That will hopefully change with an
2712 ;; improved reload pass.
2714 (define_insn "*expanded_andsi"
2715 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2716 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,r")
2717 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
2725 [(set_attr "slottable" "yes,yes,yes,no,no")])
2727 ;; For both QI and HI we may use the quick patterns. This results in
2728 ;; useless condition codes, but that is used rarely enough for it to
2729 ;; normally be a win (could check ahead for use of cc0, but seems to be
2730 ;; more pain than win).
2732 ;; FIXME: See note for andsi3
2734 (define_expand "andhi3"
2735 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2736 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
2737 (match_operand:HI 2 "general_operand" "")))]
2741 if (! (GET_CODE (operands[2]) == CONST_INT
2742 && (((INTVAL (operands[2]) == -256
2743 || INTVAL (operands[2]) == 65280)
2744 && rtx_equal_p (operands[1], operands[0]))
2745 || (INTVAL (operands[2]) == 255
2746 && REG_P (operands[0])))))
2748 /* See comment for andsi3. */
2749 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
2750 rtx reg1 = operands[1];
2754 emit_move_insn (reg0, reg1);
2758 emit_insn (gen_rtx_SET (HImode, reg0,
2759 gen_rtx_AND (HImode, reg1, operands[2])));
2761 /* Make sure we get the right destination. */
2762 if (! REG_P (operands[0]))
2763 emit_move_insn (operands[0], reg0);
2769 ;; Some fast andhi3 special cases.
2771 (define_insn "*andhi_movu"
2772 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2773 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q>,m")
2777 [(set_attr "slottable" "yes,yes,no")])
2779 (define_insn "*andhi_clear_signed"
2780 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q>,m")
2781 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2785 [(set_attr "slottable" "yes,yes,no")
2786 (set_attr "cc" "none")])
2788 ;; FIXME: Either this or the pattern above should be redundant.
2789 (define_insn "*andhi_clear_unsigned"
2790 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q>,m")
2791 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2792 (const_int 65280)))]
2795 [(set_attr "slottable" "yes,yes,no")
2796 (set_attr "cc" "none")])
2798 ;; Catch-all andhi3 pattern.
2800 (define_insn "*expanded_andhi"
2801 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
2802 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,r")
2803 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2805 ;; Sidenote: the tightening from "general_operand" to
2806 ;; "register_operand" for operand 1 actually increased the register
2807 ;; pressure (worse code). That will hopefully change with an
2808 ;; improved reload pass.
2819 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2820 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2822 ;; A strict_low_part pattern.
2824 (define_insn "*andhi_lowpart"
2825 [(set (strict_low_part
2826 (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r"))
2827 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r")
2828 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
2837 [(set_attr "slottable" "yes,yes,no,yes,no,no")
2838 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2840 (define_insn "andqi3"
2841 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
2842 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,r")
2843 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2852 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2853 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2855 (define_insn "*andqi_lowpart"
2856 [(set (strict_low_part
2857 (match_operand:QI 0 "register_operand" "=r,r,r,r,r"))
2858 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,r")
2859 (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
2867 [(set_attr "slottable" "yes,yes,yes,no,no")
2868 (set_attr "cc" "normal,normal,clobber,normal,normal")])
2872 ;; Same comment as anddi3 applies here - no need for such a pattern.
2874 ;; It seems there's no need to jump through hoops to get good code such as
2877 (define_insn "iorsi3"
2878 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
2879 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,r")
2880 (match_operand:SI 2 "general_operand" "I,r,Q>,n,g,!To")))]
2889 [(set_attr "slottable" "yes,yes,yes,no,no,no")
2890 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2892 (define_insn "iorhi3"
2893 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
2894 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,r")
2895 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2905 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2906 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2908 (define_insn "iorqi3"
2909 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
2910 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,r")
2911 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2920 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2921 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2925 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
2927 (define_insn "xorsi3"
2928 [(set (match_operand:SI 0 "register_operand" "=r")
2929 (xor:SI (match_operand:SI 1 "register_operand" "%0")
2930 (match_operand:SI 2 "register_operand" "r")))]
2933 [(set_attr "slottable" "yes")])
2935 (define_insn "xorhi3"
2936 [(set (match_operand:HI 0 "register_operand" "=r")
2937 (xor:HI (match_operand:HI 1 "register_operand" "%0")
2938 (match_operand:HI 2 "register_operand" "r")))]
2941 [(set_attr "slottable" "yes")
2942 (set_attr "cc" "clobber")])
2944 (define_insn "xorqi3"
2945 [(set (match_operand:QI 0 "register_operand" "=r")
2946 (xor:QI (match_operand:QI 1 "register_operand" "%0")
2947 (match_operand:QI 2 "register_operand" "r")))]
2950 [(set_attr "slottable" "yes")
2951 (set_attr "cc" "clobber")])
2955 ;; Questionable use, here mostly as a (slightly usable) define_expand
2958 (define_expand "negsf2"
2961 (parallel [(set (match_operand:SF 0 "register_operand" "=r")
2962 (neg:SF (match_operand:SF 1
2963 "register_operand" "0")))
2964 (use (match_dup 2))])]
2968 operands[2] = gen_reg_rtx (SImode);
2969 operands[3] = GEN_INT (1 << 31);
2972 (define_insn "*expanded_negsf2"
2973 [(set (match_operand:SF 0 "register_operand" "=r")
2974 (neg:SF (match_operand:SF 1 "register_operand" "0")))
2975 (use (match_operand:SI 2 "register_operand" "r"))]
2978 [(set_attr "slottable" "yes")])
2980 ;; No "negdi2" although we could make one up that may be faster than
2981 ;; the one in libgcc.
2983 (define_insn "negsi2"
2984 [(set (match_operand:SI 0 "register_operand" "=r")
2985 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
2988 [(set_attr "slottable" "yes")])
2990 (define_insn "neghi2"
2991 [(set (match_operand:HI 0 "register_operand" "=r")
2992 (neg:HI (match_operand:HI 1 "register_operand" "r")))]
2995 [(set_attr "slottable" "yes")])
2997 (define_insn "negqi2"
2998 [(set (match_operand:QI 0 "register_operand" "=r")
2999 (neg:QI (match_operand:QI 1 "register_operand" "r")))]
3002 [(set_attr "slottable" "yes")])
3006 ;; See comment on anddi3 - no need for a DImode pattern.
3008 (define_insn "one_cmplsi2"
3009 [(set (match_operand:SI 0 "register_operand" "=r")
3010 (not:SI (match_operand:SI 1 "register_operand" "0")))]
3013 [(set_attr "slottable" "yes")])
3015 (define_insn "one_cmplhi2"
3016 [(set (match_operand:HI 0 "register_operand" "=r")
3017 (not:HI (match_operand:HI 1 "register_operand" "0")))]
3020 [(set_attr "slottable" "yes")
3021 (set_attr "cc" "clobber")])
3023 (define_insn "one_cmplqi2"
3024 [(set (match_operand:QI 0 "register_operand" "=r")
3025 (not:QI (match_operand:QI 1 "register_operand" "0")))]
3028 [(set_attr "slottable" "yes")
3029 (set_attr "cc" "clobber")])
3031 ;; Arithmetic shift right.
3033 (define_insn "ashrsi3"
3034 [(set (match_operand:SI 0 "register_operand" "=r")
3035 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
3036 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3040 if (REG_S_P (operands[2]))
3041 return \"asr.d %2,%0\";
3043 return \"asrq %2,%0\";
3045 [(set_attr "slottable" "yes")])
3047 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
3048 ;; the destination) when it changes shifts of lower modes into SImode,
3049 ;; it is better to make these expands an anonymous patterns instead of
3050 ;; the more correct define_insns. This occurs when gcc thinks that is
3051 ;; is better to widen to SImode and use immediate shift count.
3053 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
3055 (define_expand "ashrhi3"
3057 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))
3059 (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm")))
3060 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3061 (set (match_operand:HI 0 "general_operand" "=g")
3062 (subreg:HI (match_dup 5) 0))]
3068 for (i = 3; i < 6; i++)
3069 operands[i] = gen_reg_rtx (SImode);
3072 (define_insn "*expanded_ashrhi"
3073 [(set (match_operand:HI 0 "register_operand" "=r")
3074 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
3075 (match_operand:HI 2 "register_operand" "r")))]
3078 [(set_attr "slottable" "yes")])
3080 (define_insn "*ashrhi_lowpart"
3081 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
3082 (ashiftrt:HI (match_dup 0)
3083 (match_operand:HI 1 "register_operand" "r")))]
3086 [(set_attr "slottable" "yes")])
3088 ;; Same comment goes as for "ashrhi3".
3090 (define_expand "ashrqi3"
3092 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
3094 (zero_extend:SI (match_operand:QI 2 "nonimmediate_operand" "g")))
3095 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3096 (set (match_operand:QI 0 "general_operand" "=g")
3097 (subreg:QI (match_dup 5) 0))]
3103 for (i = 3; i < 6; i++)
3104 operands[i] = gen_reg_rtx (SImode);
3107 (define_insn "*expanded_ashrqi"
3108 [(set (match_operand:QI 0 "register_operand" "=r")
3109 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
3110 (match_operand:QI 2 "register_operand" "r")))]
3113 [(set_attr "slottable" "yes")])
3115 ;; A strict_low_part matcher.
3117 (define_insn "*ashrqi_lowpart"
3118 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
3119 (ashiftrt:QI (match_dup 0)
3120 (match_operand:QI 1 "register_operand" "r")))]
3123 [(set_attr "slottable" "yes")])
3125 ;; Logical shift right.
3127 (define_insn "lshrsi3"
3128 [(set (match_operand:SI 0 "register_operand" "=r")
3129 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3130 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3134 if (REG_S_P (operands[2]))
3135 return \"lsr.d %2,%0\";
3137 return \"lsrq %2,%0\";
3139 [(set_attr "slottable" "yes")])
3141 ;; Same comments as for ashrhi3.
3143 (define_expand "lshrhi3"
3145 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))
3147 (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "g")))
3148 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3149 (set (match_operand:HI 0 "general_operand" "=g")
3150 (subreg:HI (match_dup 5) 0))]
3156 for (i = 3; i < 6; i++)
3157 operands[i] = gen_reg_rtx (SImode);
3160 (define_insn "*expanded_lshrhi"
3161 [(set (match_operand:HI 0 "register_operand" "=r")
3162 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
3163 (match_operand:HI 2 "register_operand" "r")))]
3166 [(set_attr "slottable" "yes")])
3168 ;; A strict_low_part matcher.
3170 (define_insn "*lshrhi_lowpart"
3171 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
3172 (lshiftrt:HI (match_dup 0)
3173 (match_operand:HI 1 "register_operand" "r")))]
3176 [(set_attr "slottable" "yes")])
3178 ;; Same comments as for ashrhi3.
3180 (define_expand "lshrqi3"
3182 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
3184 (zero_extend:SI (match_operand:QI 2 "nonimmediate_operand" "g")))
3185 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3186 (set (match_operand:QI 0 "general_operand" "=g")
3187 (subreg:QI (match_dup 5) 0))]
3193 for (i = 3; i < 6; i++)
3194 operands[i] = gen_reg_rtx (SImode);
3197 (define_insn "*expanded_lshrqi"
3198 [(set (match_operand:QI 0 "register_operand" "=r")
3199 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
3200 (match_operand:QI 2 "register_operand" "r")))]
3203 [(set_attr "slottable" "yes")])
3205 ;; A strict_low_part matcher.
3207 (define_insn "*lshrqi_lowpart"
3208 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
3209 (lshiftrt:QI (match_dup 0)
3210 (match_operand:QI 1 "register_operand" "r")))]
3213 [(set_attr "slottable" "yes")])
3215 ;; Arithmetic/logical shift left.
3217 (define_insn "ashlsi3"
3218 [(set (match_operand:SI 0 "register_operand" "=r")
3219 (ashift:SI (match_operand:SI 1 "register_operand" "0")
3220 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3224 if (REG_S_P (operands[2]))
3225 return \"lsl.d %2,%0\";
3227 return \"lslq %2,%0\";
3229 [(set_attr "slottable" "yes")])
3231 ;; For narrower modes than SI, we can use lslq although it makes cc
3232 ;; unusable. The win is that we do not have to reload the shift-count
3235 (define_insn "ashlhi3"
3236 [(set (match_operand:HI 0 "register_operand" "=r,r")
3237 (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
3238 (match_operand:HI 2 "nonmemory_operand" "r,K")))]
3243 (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 15)
3245 : (CONSTANT_P (operands[2])
3246 ? \"lslq %2,%0\" : \"lsl.w %2,%0\");
3248 [(set_attr "slottable" "yes")
3249 (set_attr "cc" "normal,clobber")])
3251 ;; A strict_low_part matcher.
3253 (define_insn "*ashlhi_lowpart"
3254 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
3255 (ashift:HI (match_dup 0)
3256 (match_operand:HI 1 "register_operand" "r")))]
3259 [(set_attr "slottable" "yes")])
3261 (define_insn "ashlqi3"
3262 [(set (match_operand:QI 0 "register_operand" "=r,r")
3263 (ashift:QI (match_operand:QI 1 "register_operand" "0,0")
3264 (match_operand:QI 2 "nonmemory_operand" "r,K")))]
3269 (GET_CODE (operands[2]) == CONST_INT
3270 && INTVAL (operands[2]) > 7)
3272 : (CONSTANT_P (operands[2])
3273 ? \"lslq %2,%0\" : \"lsl.b %2,%0\");
3275 [(set_attr "slottable" "yes")
3276 (set_attr "cc" "normal,clobber")])
3278 ;; A strict_low_part matcher.
3280 (define_insn "*ashlqi_lowpart"
3281 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
3282 (ashift:QI (match_dup 0)
3283 (match_operand:QI 1 "register_operand" "r")))]
3286 [(set_attr "slottable" "yes")])
3288 ;; Various strange insns that gcc likes.
3290 ;; Fortunately, it is simple to construct an abssf (although it may not
3291 ;; be very much used in practice).
3293 (define_insn "abssf2"
3294 [(set (match_operand:SF 0 "register_operand" "=r")
3295 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
3297 "lslq 1,%0\;lsrq 1,%0")
3299 (define_insn "abssi2"
3300 [(set (match_operand:SI 0 "register_operand" "=r")
3301 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
3304 [(set_attr "slottable" "yes")])
3306 ;; FIXME: GCC should be able to do these expansions itself.
3308 (define_expand "abshi2"
3310 (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))
3311 (set (match_dup 3) (abs:SI (match_dup 2)))
3312 (set (match_operand:HI 0 "register_operand" "=r")
3313 (subreg:HI (match_dup 3) 0))]
3315 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3317 (define_expand "absqi2"
3319 (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))
3320 (set (match_dup 3) (abs:SI (match_dup 2)))
3321 (set (match_operand:QI 0 "register_operand" "=r")
3322 (subreg:QI (match_dup 3) 0))]
3324 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3326 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
3327 ;; operation supported by gcc. Used in casesi, but used now and then in
3330 (define_insn "uminsi3"
3331 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3332 (umin:SI (match_operand:SI 1 "register_operand" "%0,0,0,r")
3333 (match_operand:SI 2 "general_operand" "r,Q>,g,!STo")))]
3337 if (GET_CODE (operands[2]) == CONST_INT)
3339 if (INTVAL (operands[2]) < 256)
3340 return \"bound.b %2,%0\";
3342 if (INTVAL (operands[2]) < 65536)
3343 return \"bound.w %2,%0\";
3345 else if (which_alternative == 3)
3346 return \"bound.d %2,%1,%0\";
3348 return \"bound.d %2,%0\";
3350 [(set_attr "slottable" "yes,yes,no,no")])
3352 ;; Jump and branch insns.
3356 (label_ref (match_operand 0 "" "")))]
3359 [(set_attr "slottable" "has_slot")])
3361 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
3362 ;; here, since the insn is not recognized as an indirect jump by
3363 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
3364 ;; change from general_operand to nonimmediate_operand (at least the docs
3365 ;; should be changed), but then again the pattern is called indirect_jump.
3366 (define_insn "indirect_jump"
3367 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
3371 ;; Return insn. Used whenever the epilogue is very simple; if it is only
3372 ;; a single ret or jump [sp+] or a contiguous sequence of movem:able saved
3373 ;; registers. No allocated stack space is allowed.
3374 ;; Note that for this pattern, although named, it is ok to check the
3375 ;; context of the insn in the test, not only compiler switches.
3377 (define_insn "return"
3379 "cris_simple_epilogue ()"
3384 /* Just needs to hold a 'movem [sp+],rN'. */
3385 char rd[sizeof (\"movem [$sp+],$r99\")];
3387 /* Try to avoid reorg.c surprises; avoid emitting invalid code, prefer
3388 crashing. This test would have avoided invalid code for target/7042. */
3389 if (current_function_epilogue_delay_list != NULL)
3394 /* Start from the last call-saved register. We know that we have a
3395 simple epilogue, so we just have to find the last register in the
3397 for (i = 8; i >= 0; i--)
3398 if (regs_ever_live[i]
3399 || (i == PIC_OFFSET_TABLE_REGNUM
3400 && current_function_uses_pic_offset_table))
3404 sprintf (rd, \"movem [$sp+],$%s\", reg_names [i]);
3406 if (regs_ever_live[CRIS_SRP_REGNUM])
3409 output_asm_insn (rd, operands);
3410 return \"jump [$sp+]\";
3415 output_asm_insn (\"reT\", operands);
3416 output_asm_insn (rd, operands);
3422 [(set (attr "slottable")
3424 (ne (symbol_ref "regs_ever_live[CRIS_SRP_REGNUM]") (const_int 0))
3425 (const_string "no") ; If jump then not slottable.
3429 || (flag_pic != 0 && regs_ever_live[1])
3430 || (PIC_OFFSET_TABLE_REGNUM == 0
3431 && cris_cfun_uses_pic_table ()))")
3433 (const_string "no") ; ret+movem [sp+],rx: slot already filled.
3434 (const_string "has_slot")))) ; If ret then need to fill a slot.
3435 (set_attr "cc" "none")])
3437 ;; Conditional branches.
3439 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
3440 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
3445 (if_then_else (eq (cc0)
3447 (label_ref (match_operand 0 "" ""))
3451 [(set_attr "slottable" "has_slot")])
3455 (if_then_else (ne (cc0)
3457 (label_ref (match_operand 0 "" ""))
3461 [(set_attr "slottable" "has_slot")])
3465 (if_then_else (gt (cc0)
3467 (label_ref (match_operand 0 "" ""))
3473 (cc_prev_status.flags & CC_NO_OVERFLOW)
3474 ? 0 : \"bgt %l0%#\";
3476 [(set_attr "slottable" "has_slot")])
3480 (if_then_else (gtu (cc0)
3482 (label_ref (match_operand 0 "" ""))
3486 [(set_attr "slottable" "has_slot")])
3490 (if_then_else (lt (cc0)
3492 (label_ref (match_operand 0 "" ""))
3498 (cc_prev_status.flags & CC_NO_OVERFLOW)
3499 ? \"bmi %l0%#\" : \"blt %l0%#\";
3501 [(set_attr "slottable" "has_slot")])
3505 (if_then_else (ltu (cc0)
3507 (label_ref (match_operand 0 "" ""))
3511 [(set_attr "slottable" "has_slot")])
3515 (if_then_else (ge (cc0)
3517 (label_ref (match_operand 0 "" ""))
3523 (cc_prev_status.flags & CC_NO_OVERFLOW)
3524 ? \"bpl %l0%#\" : \"bge %l0%#\";
3526 [(set_attr "slottable" "has_slot")])
3530 (if_then_else (geu (cc0)
3532 (label_ref (match_operand 0 "" ""))
3536 [(set_attr "slottable" "has_slot")])
3540 (if_then_else (le (cc0)
3542 (label_ref (match_operand 0 "" ""))
3548 (cc_prev_status.flags & CC_NO_OVERFLOW)
3549 ? 0 : \"ble %l0%#\";
3551 [(set_attr "slottable" "has_slot")])
3555 (if_then_else (leu (cc0)
3557 (label_ref (match_operand 0 "" ""))
3561 [(set_attr "slottable" "has_slot")])
3563 ;; Reversed anonymous patterns to the ones above, as mandated.
3565 (define_insn "*beq_reversed"
3567 (if_then_else (eq (cc0)
3570 (label_ref (match_operand 0 "" ""))))]
3573 [(set_attr "slottable" "has_slot")])
3575 (define_insn "*bne_reversed"
3577 (if_then_else (ne (cc0)
3580 (label_ref (match_operand 0 "" ""))))]
3583 [(set_attr "slottable" "has_slot")])
3585 (define_insn "*bgt_reversed"
3587 (if_then_else (gt (cc0)
3590 (label_ref (match_operand 0 "" ""))))]
3595 (cc_prev_status.flags & CC_NO_OVERFLOW)
3596 ? 0 : \"ble %l0%#\";
3598 [(set_attr "slottable" "has_slot")])
3600 (define_insn "*bgtu_reversed"
3602 (if_then_else (gtu (cc0)
3605 (label_ref (match_operand 0 "" ""))))]
3608 [(set_attr "slottable" "has_slot")])
3610 (define_insn "*blt_reversed"
3612 (if_then_else (lt (cc0)
3615 (label_ref (match_operand 0 "" ""))))]
3620 (cc_prev_status.flags & CC_NO_OVERFLOW)
3621 ? \"bpl %l0%#\" : \"bge %l0%#\";
3623 [(set_attr "slottable" "has_slot")])
3625 (define_insn "*bltu_reversed"
3627 (if_then_else (ltu (cc0)
3630 (label_ref (match_operand 0 "" ""))))]
3633 [(set_attr "slottable" "has_slot")])
3635 (define_insn "*bge_reversed"
3637 (if_then_else (ge (cc0)
3640 (label_ref (match_operand 0 "" ""))))]
3645 (cc_prev_status.flags & CC_NO_OVERFLOW)
3646 ? \"bmi %l0%#\" : \"blt %l0%#\";
3648 [(set_attr "slottable" "has_slot")])
3650 (define_insn "*bgeu_reversed"
3652 (if_then_else (geu (cc0)
3655 (label_ref (match_operand 0 "" ""))))]
3658 [(set_attr "slottable" "has_slot")])
3660 (define_insn "*ble_reversed"
3662 (if_then_else (le (cc0)
3665 (label_ref (match_operand 0 "" ""))))]
3670 (cc_prev_status.flags & CC_NO_OVERFLOW)
3671 ? 0 : \"bgt %l0%#\";
3673 [(set_attr "slottable" "has_slot")])
3675 (define_insn "*bleu_reversed"
3677 (if_then_else (leu (cc0)
3680 (label_ref (match_operand 0 "" ""))))]
3683 [(set_attr "slottable" "has_slot")])
3685 ;; Set on condition: sCC.
3687 ;; Like bCC, we have to check the overflow bit for
3688 ;; signed conditions.
3691 [(set (match_operand:SI 0 "register_operand" "=r")
3692 (geu:SI (cc0) (const_int 0)))]
3695 [(set_attr "slottable" "yes")
3696 (set_attr "cc" "none")])
3699 [(set (match_operand:SI 0 "register_operand" "=r")
3700 (ltu:SI (cc0) (const_int 0)))]
3703 [(set_attr "slottable" "yes")
3704 (set_attr "cc" "none")])
3707 [(set (match_operand:SI 0 "register_operand" "=r")
3708 (eq:SI (cc0) (const_int 0)))]
3711 [(set_attr "slottable" "yes")
3712 (set_attr "cc" "none")])
3715 [(set (match_operand:SI 0 "register_operand" "=r")
3716 (ge:SI (cc0) (const_int 0)))]
3721 (cc_prev_status.flags & CC_NO_OVERFLOW)
3722 ? \"spl %0\" : \"sge %0\";
3724 [(set_attr "slottable" "yes")
3725 (set_attr "cc" "none")])
3728 [(set (match_operand:SI 0 "register_operand" "=r")
3729 (gt:SI (cc0) (const_int 0)))]
3734 (cc_prev_status.flags & CC_NO_OVERFLOW)
3737 [(set_attr "slottable" "yes")
3738 (set_attr "cc" "none")])
3741 [(set (match_operand:SI 0 "register_operand" "=r")
3742 (gtu:SI (cc0) (const_int 0)))]
3745 [(set_attr "slottable" "yes")
3746 (set_attr "cc" "none")])
3749 [(set (match_operand:SI 0 "register_operand" "=r")
3750 (le:SI (cc0) (const_int 0)))]
3755 (cc_prev_status.flags & CC_NO_OVERFLOW)
3758 [(set_attr "slottable" "yes")
3759 (set_attr "cc" "none")])
3762 [(set (match_operand:SI 0 "register_operand" "=r")
3763 (leu:SI (cc0) (const_int 0)))]
3766 [(set_attr "slottable" "yes")
3767 (set_attr "cc" "none")])
3770 [(set (match_operand:SI 0 "register_operand" "=r")
3771 (lt:SI (cc0) (const_int 0)))]
3776 (cc_prev_status.flags & CC_NO_OVERFLOW)
3777 ? \"smi %0\" : \"slt %0\";
3779 [(set_attr "slottable" "yes")
3780 (set_attr "cc" "none")])
3783 [(set (match_operand:SI 0 "register_operand" "=r")
3784 (ne:SI (cc0) (const_int 0)))]
3787 [(set_attr "slottable" "yes")
3788 (set_attr "cc" "none")])
3792 ;; We need to make these patterns "expand", since the real operand is
3793 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
3794 ;; and cannot be checked if it were a "normal" pattern.
3795 ;; Note that "call" and "call_value" are *always* called with a
3796 ;; mem-operand for operand 0 and 1 respective. What happens for combined
3797 ;; instructions is a different issue.
3799 (define_expand "call"
3800 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "")
3801 (match_operand 1 "general_operand" ""))
3802 ;; 16 is the srp (can't use the symbolic name here)
3803 (clobber (reg:SI 16))])]
3809 if (GET_CODE (operands[0]) != MEM)
3814 op0 = XEXP (operands[0], 0);
3816 /* It might be that code can be generated that jumps to 0 (or to a
3817 specific address). Don't abort on that. At least there's a
3819 if (CONSTANT_ADDRESS_P (op0) && GET_CODE (op0) != CONST_INT)
3824 /* For local symbols (non-PLT), get the plain symbol reference
3825 into a register. For symbols that can be PLT, make them PLT. */
3826 if (cris_gotless_symbol (op0) || GET_CODE (op0) != SYMBOL_REF)
3827 op0 = force_reg (Pmode, op0);
3828 else if (cris_symbol (op0))
3829 /* FIXME: Would hanging a REG_EQUIV/EQUAL on that register
3830 for the symbol cause bad recombinatorial effects? */
3831 op0 = force_reg (Pmode,
3834 gen_rtx_UNSPEC (VOIDmode,
3835 gen_rtvec (1, op0), 0)));
3839 operands[0] = replace_equiv_address (operands[0], op0);
3844 ;; Accept *anything* as operand 1. Accept operands for operand 0 in
3845 ;; order of preference (Q includes r, but r is shorter, faster)
3847 (define_insn "*expanded_call"
3848 [(call (mem:QI (match_operand:SI
3849 0 "cris_general_operand_or_plt_symbol" "r,Q>,g,S"))
3850 (match_operand 1 "" ""))
3851 (clobber (reg:SI 16))] ;; 16 is the srp (can't use symbolic name)
3852 "! TARGET_AVOID_GOTPLT"
3855 ;; Same as above, since can't afford wasting a constraint letter to mean
3856 ;; "S unless TARGET_AVOID_GOTPLT".
3857 (define_insn "*expanded_call_no_gotplt"
3858 [(call (mem:QI (match_operand:SI
3859 0 "cris_general_operand_or_plt_symbol" "r,Q>,g"))
3860 (match_operand 1 "" ""))
3861 (clobber (reg:SI 16))] ;; 16 is the srp (can't use symbolic name)
3862 "TARGET_AVOID_GOTPLT"
3865 (define_expand "call_value"
3866 [(parallel [(set (match_operand 0 "" "")
3867 (call (match_operand:QI 1 "cris_mem_call_operand" "")
3868 (match_operand 2 "" "")))
3869 ;; 16 is the srp (can't use symbolic name)
3870 (clobber (reg:SI 16))])]
3876 if (GET_CODE (operands[1]) != MEM)
3881 op1 = XEXP (operands[1], 0);
3883 /* It might be that code can be generated that jumps to 0 (or to a
3884 specific address). Don't abort on that. At least there's a
3886 if (CONSTANT_ADDRESS_P (op1) && GET_CODE (op1) != CONST_INT)
3891 if (cris_gotless_symbol (op1))
3892 op1 = force_reg (Pmode, op1);
3893 else if (cris_symbol (op1))
3894 /* FIXME: Would hanging a REG_EQUIV/EQUAL on that register
3895 for the symbol cause bad recombinatorial effects? */
3896 op1 = force_reg (Pmode,
3899 gen_rtx_UNSPEC (VOIDmode,
3900 gen_rtvec (1, op1), 0)));
3904 operands[1] = replace_equiv_address (operands[1], op1);
3909 ;; Accept *anything* as operand 2. The validity other than "general" of
3910 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
3911 ;; order of preference (Q includes r, but r is shorter, faster).
3912 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
3913 ;; than requiring getting rPIC + sym:PLT into a register.
3915 (define_insn "*expanded_call_value"
3916 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g,g")
3917 (call (mem:QI (match_operand:SI
3918 1 "cris_general_operand_or_plt_symbol" "r,Q>,g,S"))
3919 (match_operand 2 "" "")))
3920 (clobber (reg:SI 16))]
3921 "! TARGET_AVOID_GOTPLT"
3923 [(set_attr "cc" "clobber")])
3925 ;; Same as above, since can't afford wasting a constraint letter to mean
3926 ;; "S unless TARGET_AVOID_GOTPLT".
3927 (define_insn "*expanded_call_value_no_gotplt"
3928 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3929 (call (mem:QI (match_operand:SI
3930 1 "cris_general_operand_or_plt_symbol" "r,Q>,g"))
3931 (match_operand 2 "" "")))
3932 (clobber (reg:SI 16))]
3933 "TARGET_AVOID_GOTPLT"
3935 [(set_attr "cc" "clobber")])
3937 ;; Used in debugging. No use for the direct pattern; unfilled
3938 ;; delayed-branches are taken care of by other means.
3944 [(set_attr "cc" "none")])
3946 ;; We expand on casesi so we can use "bound" and "add offset fetched from
3947 ;; a table to pc" (adds.w [pc+%0.w],pc).
3949 ;; Note: if you change the "parallel" (or add anything after it) in
3950 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
3951 ;; accordingly, to add the default case at the end of the jump-table.
3953 (define_expand "casesi"
3954 [(set (match_dup 5) (match_operand:SI 0 "general_operand" ""))
3956 (minus:SI (match_dup 5)
3957 (match_operand:SI 1 "const_int_operand" "n")))
3959 (umin:SI (match_dup 6)
3960 (match_operand:SI 2 "const_int_operand" "n")))
3964 (ltu (match_dup 7) (match_dup 2))
3965 (plus:SI (sign_extend:SI
3967 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3970 (label_ref (match_operand 4 "" ""))))
3971 (use (label_ref (match_operand 3 "" "")))])]
3975 operands[2] = plus_constant (operands[2], 1);
3976 operands[5] = gen_reg_rtx (SImode);
3977 operands[6] = gen_reg_rtx (SImode);
3978 operands[7] = gen_reg_rtx (SImode);
3981 ;; Split-patterns. Some of them have modes unspecified. This
3982 ;; should always be ok; if for no other reason sparc.md has it as
3985 ;; When register_operand is specified for an operand, we can get a
3986 ;; subreg as well (Axis-990331), so don't just assume that REG_P is true
3987 ;; for a register_operand and that REGNO can be used as is. It is best to
3988 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
3990 ;; op [rx + 0],ry,rz
3991 ;; The index to rx is optimized into zero, and gone.
3993 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
3994 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
3998 ;; Lose if rz=ry or rx=rz.
3999 ;; Call this op-extend-split
4002 [(set (match_operand 0 "register_operand" "")
4004 4 "cris_operand_extend_operator"
4005 [(match_operand 1 "register_operand" "")
4007 3 "cris_extend_operator"
4008 [(match_operand 2 "memory_operand" "")])]))]
4009 "REG_P (operands[0])
4010 && REG_P (operands[1])
4011 && REGNO (operands[1]) != REGNO (operands[0])
4012 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4013 && REG_P (XEXP (operands[2], 0))
4014 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4020 (match_op_dup 3 [(match_dup 2)])]))]
4023 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
4026 ;; Do this for plus or bound only, being commutative operations, since we
4027 ;; have swapped the operands.
4028 ;; Call this op-extend-split-rx=rz
4031 [(set (match_operand 0 "register_operand" "")
4033 4 "cris_plus_or_bound_operator"
4034 [(match_operand 1 "register_operand" "")
4036 3 "cris_extend_operator"
4037 [(match_operand 2 "memory_operand" "")])]))]
4038 "REG_P (operands[0])
4039 && REG_P (operands[1])
4040 && REGNO (operands[1]) != REGNO (operands[0])
4041 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4042 && REG_P (XEXP (operands[2], 0))
4043 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4045 (match_op_dup 3 [(match_dup 2)]))
4052 ;; As the op-extend-split, but swapped operands, and only for
4053 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
4054 ;; this needed? Is it?
4055 ;; Call this op-extend-split-swapped
4058 [(set (match_operand 0 "register_operand" "")
4060 4 "cris_plus_or_bound_operator"
4062 3 "cris_extend_operator"
4063 [(match_operand 2 "memory_operand" "")])
4064 (match_operand 1 "register_operand" "")]))]
4065 "REG_P (operands[0])
4066 && REG_P (operands[1])
4067 && REGNO (operands[1]) != REGNO (operands[0])
4068 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4069 && REG_P (XEXP (operands[2], 0))
4070 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4076 (match_op_dup 3 [(match_dup 2)])]))]
4079 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
4080 ;; bound. Call this op-extend-split-swapped-rx=rz.
4083 [(set (match_operand 0 "register_operand" "")
4085 4 "cris_plus_or_bound_operator"
4087 3 "cris_extend_operator"
4088 [(match_operand 2 "memory_operand" "")])
4089 (match_operand 1 "register_operand" "")]))]
4090 "REG_P (operands[0])
4091 && REG_P (operands[1])
4092 && REGNO (operands[1]) != REGNO (operands[0])
4093 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4094 && REG_P (XEXP (operands[2], 0))
4095 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4097 (match_op_dup 3 [(match_dup 2)]))
4104 ;; As op-extend-split, but the mem operand is not extended.
4106 ;; op [rx],ry,rz changed into
4109 ;; lose if ry=rz or rx=rz
4110 ;; Call this op-extend.
4113 [(set (match_operand 0 "register_operand" "")
4115 3 "cris_orthogonal_operator"
4116 [(match_operand 1 "register_operand" "")
4117 (match_operand 2 "memory_operand" "")]))]
4118 "REG_P (operands[0])
4119 && REG_P (operands[1])
4120 && REGNO (operands[1]) != REGNO (operands[0])
4121 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4122 && REG_P (XEXP (operands[2], 0))
4123 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4132 ;; As op-extend-split-rx=rz, non-extended.
4133 ;; Call this op-split-rx=rz
4136 [(set (match_operand 0 "register_operand" "")
4138 3 "cris_commutative_orth_op"
4139 [(match_operand 2 "memory_operand" "")
4140 (match_operand 1 "register_operand" "")]))]
4141 "REG_P (operands[0])
4142 && REG_P (operands[1])
4143 && REGNO (operands[1]) != REGNO (operands[0])
4144 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4145 && REG_P (XEXP (operands[2], 0))
4146 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4155 ;; As op-extend-split-swapped, nonextended.
4156 ;; Call this op-split-swapped.
4159 [(set (match_operand 0 "register_operand" "")
4161 3 "cris_commutative_orth_op"
4162 [(match_operand 1 "register_operand" "")
4163 (match_operand 2 "memory_operand" "")]))]
4164 "REG_P (operands[0]) && REG_P (operands[1])
4165 && REGNO (operands[1]) != REGNO (operands[0])
4166 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4167 && REG_P (XEXP (operands[2], 0))
4168 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4177 ;; As op-extend-split-swapped-rx=rz, non-extended.
4178 ;; Call this op-split-swapped-rx=rz.
4181 [(set (match_operand 0 "register_operand" "")
4183 3 "cris_orthogonal_operator"
4184 [(match_operand 2 "memory_operand" "")
4185 (match_operand 1 "register_operand" "")]))]
4186 "REG_P (operands[0]) && REG_P (operands[1])
4187 && REGNO (operands[1]) != REGNO (operands[0])
4188 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4189 && REG_P (XEXP (operands[2], 0))
4190 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4199 ;; Splits for all cases in side-effect insns where (possibly after reload
4200 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
4202 ;; move.S1 [rx=rx+rz.S2],ry
4206 [(set (match_operand 0 "register_operand" "")
4210 (mult:SI (match_operand:SI 1 "register_operand" "")
4211 (match_operand:SI 2 "const_int_operand" ""))
4212 (match_operand:SI 3 "register_operand" ""))]))
4213 (set (match_operand:SI 4 "register_operand" "")
4214 (plus:SI (mult:SI (match_dup 1)
4217 "REG_P (operands[3]) && REG_P (operands[4])
4218 && REGNO (operands[3]) == REGNO (operands[4])"
4219 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4221 (set (match_dup 0) (match_dup 5))]
4222 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
4224 ;; move.S1 [rx=rx+i],ry
4228 [(set (match_operand 0 "register_operand" "")
4231 [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "")
4232 (match_operand:SI 2 "cris_bdap_operand" ""))]))
4233 (set (match_operand:SI 3 "register_operand" "")
4234 (plus:SI (match_dup 1)
4236 "(rtx_equal_p (operands[3], operands[1])
4237 || rtx_equal_p (operands[3], operands[2]))"
4238 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4239 (set (match_dup 0) (match_dup 4))]
4240 "operands[4] = replace_equiv_address (operands[5], operands[3]);")
4242 ;; move.S1 ry,[rx=rx+rz.S2]
4246 [(set (match_operator
4249 (mult:SI (match_operand:SI 0 "register_operand" "")
4250 (match_operand:SI 1 "const_int_operand" ""))
4251 (match_operand:SI 2 "register_operand" ""))])
4252 (match_operand 3 "register_operand" ""))
4253 (set (match_operand:SI 4 "register_operand" "")
4254 (plus:SI (mult:SI (match_dup 0)
4257 "REG_P (operands[2]) && REG_P (operands[4])
4258 && REGNO (operands[4]) == REGNO (operands[2])"
4259 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4261 (set (match_dup 5) (match_dup 3))]
4262 "operands[5] = replace_equiv_address (operands[6], operands[4]);")
4264 ;; move.S1 ry,[rx=rx+i]
4268 [(set (match_operator
4270 [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4271 (match_operand:SI 1 "cris_bdap_operand" ""))])
4272 (match_operand 2 "register_operand" ""))
4273 (set (match_operand:SI 3 "register_operand" "")
4274 (plus:SI (match_dup 0)
4276 "(rtx_equal_p (operands[3], operands[0])
4277 || rtx_equal_p (operands[3], operands[1]))"
4278 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
4279 (set (match_dup 5) (match_dup 2))]
4280 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
4282 ;; clear.d [rx=rx+rz.S2]
4286 [(set (mem:SI (plus:SI
4287 (mult:SI (match_operand:SI 0 "register_operand" "")
4288 (match_operand:SI 1 "const_int_operand" ""))
4289 (match_operand:SI 2 "register_operand" "")))
4291 (set (match_operand:SI 3 "register_operand" "")
4292 (plus:SI (mult:SI (match_dup 0)
4295 "REG_P (operands[2]) && REG_P (operands[3])
4296 && REGNO (operands[3]) == REGNO (operands[2])"
4297 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4299 (set (mem:SI (match_dup 3)) (const_int 0))]
4302 ;; clear.w [rx=rx+rz.S2]
4306 [(set (mem:HI (plus:SI
4307 (mult:SI (match_operand:SI 0 "register_operand" "")
4308 (match_operand:SI 1 "const_int_operand" ""))
4309 (match_operand:SI 2 "register_operand" "")))
4311 (set (match_operand:SI 3 "register_operand" "")
4312 (plus:SI (mult:SI (match_dup 0)
4315 "REG_P (operands[2]) && REG_P (operands[3])
4316 && REGNO (operands[3]) == REGNO (operands[2])"
4317 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4319 (set (mem:HI (match_dup 3)) (const_int 0))]
4322 ;; clear.b [rx=rx+rz.S2]
4326 [(set (mem:QI (plus:SI
4327 (mult:SI (match_operand:SI 0 "register_operand" "")
4328 (match_operand:SI 1 "const_int_operand" ""))
4329 (match_operand:SI 2 "register_operand" "")))
4331 (set (match_operand:SI 3 "register_operand" "")
4332 (plus:SI (mult:SI (match_dup 0)
4335 "REG_P (operands[2]) && REG_P (operands[3])
4336 && REGNO (operands[3]) == REGNO (operands[2])"
4337 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4339 (set (mem:QI (match_dup 3)) (const_int 0))]
4342 ;; clear.d [rx=rx+i]
4347 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4348 (match_operand:SI 1 "cris_bdap_operand" "")))
4350 (set (match_operand:SI 2 "register_operand" "")
4351 (plus:SI (match_dup 0)
4353 "(rtx_equal_p (operands[0], operands[2])
4354 || rtx_equal_p (operands[2], operands[1]))"
4355 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4356 (set (mem:SI (match_dup 2)) (const_int 0))]
4359 ;; clear.w [rx=rx+i]
4364 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4365 (match_operand:SI 1 "cris_bdap_operand" "")))
4367 (set (match_operand:SI 2 "register_operand" "")
4368 (plus:SI (match_dup 0)
4370 "(rtx_equal_p (operands[0], operands[2])
4371 || rtx_equal_p (operands[2], operands[1]))"
4372 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4373 (set (mem:HI (match_dup 2)) (const_int 0))]
4376 ;; clear.b [rx=rx+i]
4381 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4382 (match_operand:SI 1 "cris_bdap_operand" "")))
4384 (set (match_operand:SI 2 "register_operand" "")
4385 (plus:SI (match_dup 0)
4387 "(rtx_equal_p (operands[0], operands[2])
4388 || rtx_equal_p (operands[2], operands[1]))"
4389 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4390 (set (mem:QI (match_dup 2)) (const_int 0))]
4393 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
4397 [(set (match_operand 0 "register_operand" "")
4399 5 "cris_extend_operator"
4401 (mult:SI (match_operand:SI 1 "register_operand" "")
4402 (match_operand:SI 2 "const_int_operand" ""))
4403 (match_operand:SI 3 "register_operand" "")))]))
4404 (set (match_operand:SI 4 "register_operand" "")
4405 (plus:SI (mult:SI (match_dup 1)
4408 "REG_P (operands[3])
4409 && REG_P (operands[4])
4410 && REGNO (operands[3]) == REGNO (operands[4])"
4411 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4413 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))]
4414 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
4416 ;; mov(s|u).S1 [rx=rx+i],ry
4420 [(set (match_operand 0 "register_operand" "")
4422 4 "cris_extend_operator"
4424 (match_operand:SI 1 "cris_bdap_operand" "")
4425 (match_operand:SI 2 "cris_bdap_operand" "")))]))
4426 (set (match_operand:SI 3 "register_operand" "")
4427 (plus:SI (match_dup 1)
4429 "(rtx_equal_p (operands[1], operands[3])
4430 || rtx_equal_p (operands[2], operands[3]))"
4431 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4432 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
4433 "operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);")
4435 ;; op.S1 [rx=rx+i],ry
4439 [(set (match_operand 0 "register_operand" "")
4441 5 "cris_orthogonal_operator"
4442 [(match_operand 1 "register_operand" "")
4444 (match_operand:SI 2 "cris_bdap_operand" "")
4445 (match_operand:SI 3 "cris_bdap_operand" "")))]))
4446 (set (match_operand:SI 4 "register_operand" "")
4447 (plus:SI (match_dup 2)
4449 "(rtx_equal_p (operands[4], operands[2])
4450 || rtx_equal_p (operands[4], operands[3]))"
4451 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4452 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
4453 "operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);")
4455 ;; op.S1 [rx=rx+rz.S2],ry
4459 [(set (match_operand 0 "register_operand" "")
4461 6 "cris_orthogonal_operator"
4462 [(match_operand 1 "register_operand" "")
4464 (mult:SI (match_operand:SI 2 "register_operand" "")
4465 (match_operand:SI 3 "const_int_operand" ""))
4466 (match_operand:SI 4 "register_operand" "")))]))
4467 (set (match_operand:SI 5 "register_operand" "")
4468 (plus:SI (mult:SI (match_dup 2)
4471 "REG_P (operands[4])
4472 && REG_P (operands[5])
4473 && REGNO (operands[5]) == REGNO (operands[4])"
4474 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4476 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))]
4477 "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);")
4479 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
4483 [(set (match_operand 0 "register_operand" "")
4485 6 "cris_commutative_orth_op"
4487 (mult:SI (match_operand:SI 2 "register_operand" "")
4488 (match_operand:SI 3 "const_int_operand" ""))
4489 (match_operand:SI 4 "register_operand" "")))
4490 (match_operand 1 "register_operand" "")]))
4491 (set (match_operand:SI 5 "register_operand" "")
4492 (plus:SI (mult:SI (match_dup 2)
4495 "REG_P (operands[4])
4496 && REG_P (operands[5])
4497 && REGNO (operands[5]) == REGNO (operands[4])"
4498 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4500 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4501 "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);")
4503 ;; op.S1 [rx=rx+i],ry (swapped)
4507 [(set (match_operand 0 "register_operand" "")
4509 5 "cris_commutative_orth_op"
4511 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4512 (match_operand:SI 3 "cris_bdap_operand" "")))
4513 (match_operand 1 "register_operand" "")]))
4514 (set (match_operand:SI 4 "register_operand" "")
4515 (plus:SI (match_dup 2)
4517 "(rtx_equal_p (operands[4], operands[2])
4518 || rtx_equal_p (operands[4], operands[3]))"
4519 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4520 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
4521 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
4523 ;; op(s|u).S1 [rx=rx+rz.S2],ry
4527 [(set (match_operand 0 "register_operand" "")
4529 6 "cris_operand_extend_operator"
4530 [(match_operand 1 "register_operand" "")
4532 7 "cris_extend_operator"
4534 (mult:SI (match_operand:SI 2 "register_operand" "")
4535 (match_operand:SI 3 "const_int_operand" ""))
4536 (match_operand:SI 4 "register_operand" "")))])]))
4537 (set (match_operand:SI 5 "register_operand" "")
4538 (plus:SI (mult:SI (match_dup 2)
4541 "REG_P (operands[4])
4542 && REG_P (operands[5])
4543 && REGNO (operands[5]) == REGNO (operands[4])"
4544 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4546 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))]
4547 "operands[8] = gen_rtx (GET_CODE (operands[7]), GET_MODE (operands[7]),
4548 replace_equiv_address (XEXP (operands[7], 0),
4551 ;; op(s|u).S1 [rx=rx+i],ry
4555 [(set (match_operand 0 "register_operand" "")
4557 5 "cris_operand_extend_operator"
4558 [(match_operand 1 "register_operand" "")
4560 6 "cris_extend_operator"
4562 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4563 (match_operand:SI 3 "cris_bdap_operand" "")
4565 (set (match_operand:SI 4 "register_operand" "")
4566 (plus:SI (match_dup 2)
4568 "(rtx_equal_p (operands[4], operands[2])
4569 || rtx_equal_p (operands[4], operands[3]))"
4570 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4571 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
4572 "operands[7] = gen_rtx (GET_CODE (operands[6]), GET_MODE (operands[6]),
4573 replace_equiv_address (XEXP (operands[6], 0),
4576 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
4580 [(set (match_operand 0 "register_operand" "")
4582 7 "cris_plus_or_bound_operator"
4584 6 "cris_extend_operator"
4586 (mult:SI (match_operand:SI 2 "register_operand" "")
4587 (match_operand:SI 3 "const_int_operand" ""))
4588 (match_operand:SI 4 "register_operand" "")))])
4589 (match_operand 1 "register_operand" "")]))
4590 (set (match_operand:SI 5 "register_operand" "")
4591 (plus:SI (mult:SI (match_dup 2)
4594 "REG_P (operands[4]) && REG_P (operands[5])
4595 && REGNO (operands[5]) == REGNO (operands[4])"
4596 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4598 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))]
4599 "operands[8] = gen_rtx (GET_CODE (operands[6]), GET_MODE (operands[6]),
4600 replace_equiv_address (XEXP (operands[6], 0),
4603 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
4607 [(set (match_operand 0 "register_operand" "")
4609 6 "cris_plus_or_bound_operator"
4611 5 "cris_extend_operator"
4613 (match_operand:SI 2 "cris_bdap_operand" "")
4614 (match_operand:SI 3 "cris_bdap_operand" "")))])
4615 (match_operand 1 "register_operand" "")]))
4616 (set (match_operand:SI 4 "register_operand" "")
4617 (plus:SI (match_dup 2)
4619 "(rtx_equal_p (operands[4], operands[2])
4620 || rtx_equal_p (operands[4], operands[3]))"
4621 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4622 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4623 "operands[7] = gen_rtx (GET_CODE (operands[5]), GET_MODE (operands[5]),
4624 replace_equiv_address (XEXP (operands[5], 0),
4627 ;; Splits for addressing prefixes that have no side-effects, so we can
4628 ;; fill a delay slot. Never split if we lose something, though.
4631 ;; move [indirect_ref],rx
4632 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
4633 ;; move indirect_ref,rx
4635 ;; Take care not to allow indirect_ref = register.
4637 ;; We're not allowed to generate copies of registers with different mode
4638 ;; until after reload; copying pseudos upsets reload. CVS as of
4639 ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
4640 ;; cselib_invalidate_regno.
4643 [(set (match_operand 0 "register_operand" "")
4644 (match_operand 1 "indirect_operand" ""))]
4646 && REG_P (operands[0])
4647 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4648 && (GET_CODE (XEXP (operands[1], 0)) == MEM
4649 || CONSTANT_P (XEXP (operands[1], 0)))"
4650 [(set (match_dup 2) (match_dup 4))
4651 (set (match_dup 0) (match_dup 3))]
4652 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4653 operands[3] = replace_equiv_address (operands[1], operands[2]);
4654 operands[4] = XEXP (operands[1], 0);")
4656 ;; As the above, but MOVS and MOVU.
4659 [(set (match_operand 0 "register_operand" "")
4661 4 "cris_extend_operator"
4662 [(match_operand 1 "indirect_operand" "")]))]
4664 && REG_P (operands[0])
4665 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4666 && (GET_CODE (XEXP (operands[1], 0)) == MEM
4667 || CONSTANT_P (XEXP (operands[1], 0)))"
4668 [(set (match_dup 2) (match_dup 5))
4669 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))]
4670 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4671 operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]);
4672 operands[5] = XEXP (operands[1], 0);")
4674 ;; Various peephole optimizations.
4676 ;; Watch out: when you exchange one set of instructions for another, the
4677 ;; condition codes setting must be the same, or you have to CC_INIT or
4678 ;; whatever is appropriate, in the pattern before you emit the
4679 ;; assembly text. This is best done here, not in cris_notice_update_cc,
4680 ;; to keep changes local to their cause.
4682 ;; Do not add patterns that you do not know will be matched.
4683 ;; Please also add a self-contained testcase.
4685 ;; We have trouble with and:s and shifts. Maybe something is broken in
4686 ;; gcc? Or it could just be that bit-field insn expansion is a bit
4687 ;; suboptimal when not having extzv insns.
4690 [(set (match_operand 0 "register_operand" "=r")
4691 (ashiftrt:SI (match_dup 0)
4692 (match_operand:SI 1 "const_int_operand" "n")))
4694 (and:SI (match_dup 0)
4695 (match_operand 2 "const_int_operand" "n")))]
4696 "INTVAL (operands[2]) > 31
4697 && INTVAL (operands[2]) < 255
4698 && INTVAL (operands[1]) > 23"
4700 ;; The m flag should be ignored, because this will be a *byte* "and"
4705 cc_status.flags |= CC_NOT_NEGATIVE;
4707 return \"lsrq %1,%0\;and.b %2,%0\";
4711 [(set (match_operand 0 "register_operand" "=r")
4712 (ashiftrt:SI (match_dup 0)
4713 (match_operand:SI 1 "const_int_operand" "n")))
4715 (and:SI (match_dup 0)
4716 (match_operand 2 "const_int_operand" "n")))]
4717 "INTVAL (operands[2]) > 31
4718 && INTVAL (operands[2]) < 65535
4719 && INTVAL (operands[2]) != 255
4720 && INTVAL (operands[1]) > 15"
4722 ;; The m flag should be ignored, because this will be a *word* "and"
4727 cc_status.flags |= CC_NOT_NEGATIVE;
4729 return \"lsrq %1,%0\;and.w %2,%0\";
4733 [(set (match_operand 0 "register_operand" "=r")
4734 (lshiftrt:SI (match_dup 0)
4735 (match_operand:SI 1 "const_int_operand" "n")))
4737 (and:SI (match_dup 0)
4738 (match_operand 2 "const_int_operand" "n")))]
4739 "INTVAL (operands[2]) > 31
4740 && INTVAL (operands[2]) < 255
4741 && INTVAL (operands[1]) > 23"
4743 ;; The m flag should be ignored, because this will be a *byte* "and"
4748 cc_status.flags |= CC_NOT_NEGATIVE;
4750 return \"lsrq %1,%0\;and.b %2,%0\";
4754 [(set (match_operand 0 "register_operand" "=r")
4755 (lshiftrt:SI (match_dup 0)
4756 (match_operand:SI 1 "const_int_operand" "n")))
4758 (and:SI (match_dup 0)
4759 (match_operand 2 "const_int_operand" "n")))]
4760 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
4761 && INTVAL (operands[2]) != 255
4762 && INTVAL (operands[1]) > 15"
4764 ;; The m flag should be ignored, because this will be a *word* "and"
4769 cc_status.flags |= CC_NOT_NEGATIVE;
4771 return \"lsrq %1,%0\;and.w %2,%0\";
4779 ;; move [rx=rx+n],ry
4780 ;; when -128 <= n <= 127.
4781 ;; This will reduce the size of the assembler code for n = [-128..127],
4782 ;; and speed up accordingly.
4785 [(set (match_operand:SI 0 "register_operand" "=r")
4786 (plus:SI (match_operand:SI 1 "register_operand" "0")
4787 (match_operand:SI 2 "const_int_operand" "n")))
4788 (set (match_operand 3 "register_operand" "=r")
4789 (mem (match_dup 0)))]
4790 "GET_MODE (operands[3]) != DImode
4791 && REGNO (operands[3]) != REGNO (operands[0])
4792 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4793 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4794 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4795 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)"
4796 "move.%s3 [%0=%1%S2],%3")
4798 ;; Vice versa: move ry,[rx=rx+n]
4801 [(set (match_operand:SI 0 "register_operand" "=r")
4802 (plus:SI (match_operand:SI 1 "register_operand" "0")
4803 (match_operand:SI 2 "const_int_operand" "n")))
4804 (set (mem (match_dup 0))
4805 (match_operand 3 "register_operand" "=r"))]
4806 "GET_MODE (operands[3]) != DImode
4807 && REGNO (operands[3]) != REGNO (operands[0])
4808 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4809 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4810 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4811 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)"
4812 "move.%s3 %3,[%0=%1%S2]"
4813 [(set_attr "cc" "none")])
4815 ;; As above, change:
4819 ;; op.d [rx=rx+n],ry
4820 ;; Saves when n = [-128..127].
4822 ;; Splitting and joining combinations for side-effect modes are slightly
4823 ;; out of hand. They probably will not save the time they take typing in,
4824 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
4825 ;; the splits and peepholes as possible.
4828 [(set (match_operand:SI 0 "register_operand" "=r")
4829 (plus:SI (match_operand:SI 1 "register_operand" "0")
4830 (match_operand:SI 2 "const_int_operand" "n")))
4831 (set (match_operand 3 "register_operand" "=r")
4832 (match_operator 4 "cris_orthogonal_operator"
4834 (mem (match_dup 0))]))]
4835 "GET_MODE (operands[3]) != DImode
4836 && REGNO (operands[0]) != REGNO (operands[3])
4837 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4838 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4839 && INTVAL (operands[2]) >= -128
4840 && INTVAL (operands[2]) <= 127"
4841 "%x4.%s3 [%0=%1%S2],%3")
4843 ;; Sometimes, for some reason the pattern
4847 ;; will occur. Solve this, and likewise for to-memory.
4850 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
4851 (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Rn,r,>Rn"))
4853 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Rn,r")
4854 (match_operand:SI 3 "cris_bdap_biap_operand" "r>Rn,r,0,0")))
4855 (set (match_operand 4 "register_operand" "=r,r,r,r")
4856 (mem (match_dup 0)))]
4857 "(rtx_equal_p (operands[2], operands[0])
4858 || rtx_equal_p (operands[3], operands[0]))
4859 && cris_side_effect_mode_ok (PLUS, operands, 0,
4860 (REG_S_P (operands[1])
4862 : (rtx_equal_p (operands[2], operands[0])
4864 (! REG_S_P (operands[1])
4866 : (rtx_equal_p (operands[2], operands[0])
4870 move.%s4 [%0=%1%S3],%4
4871 move.%s4 [%0=%3%S1],%4
4872 move.%s4 [%0=%1%S2],%4
4873 move.%s4 [%0=%2%S1],%4")
4875 ;; As above but to memory.
4878 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
4879 (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Rn,r,>Rn"))
4881 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Rn,r")
4882 (match_operand:SI 3 "cris_bdap_biap_operand" "r>Rn,r,0,0")))
4883 (set (mem (match_dup 0))
4884 (match_operand 4 "register_operand" "=r,r,r,r"))]
4885 "(rtx_equal_p (operands[2], operands[0])
4886 || rtx_equal_p (operands[3], operands[0]))
4887 && cris_side_effect_mode_ok (PLUS, operands, 0,
4888 (REG_S_P (operands[1])
4890 : (rtx_equal_p (operands[2], operands[0])
4892 (! REG_S_P (operands[1])
4894 : (rtx_equal_p (operands[2], operands[0])
4898 move.%s4 %4,[%0=%1%S3]
4899 move.%s4 %4,[%0=%3%S1]
4900 move.%s4 %4,[%0=%1%S2]
4901 move.%s4 %4,[%0=%2%S1]"
4902 [(set_attr "cc" "none")])
4905 ;; As the move from-memory above, but with an operation.
4908 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
4909 (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Rn,r,>Rn"))
4911 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Rn,r")
4912 (match_operand:SI 3 "cris_bdap_biap_operand" "r>Rn,r,0,0")))
4913 (set (match_operand 4 "register_operand" "=r,r,r,r")
4914 (match_operator 5 "cris_orthogonal_operator"
4916 (mem (match_dup 0))]))]
4917 "(rtx_equal_p (operands[2], operands[0])
4918 || rtx_equal_p (operands[3], operands[0]))
4919 && cris_side_effect_mode_ok (PLUS, operands, 0,
4920 (REG_S_P (operands[1])
4922 : (rtx_equal_p (operands[2], operands[0])
4924 (! REG_S_P (operands[1])
4926 : (rtx_equal_p (operands[2], operands[0])
4930 %x5.%s4 [%0=%1%S3],%4
4931 %x5.%s4 [%0=%3%S1],%4
4932 %x5.%s4 [%0=%1%S2],%4
4933 %x5.%s4 [%0=%2%S1],%4")
4935 ;; Same, but with swapped operands (and commutative operation).
4938 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
4939 (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Rn,r,>Rn"))
4941 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Rn,r")
4942 (match_operand:SI 3 "cris_bdap_biap_operand" "r>Rn,r,0,0")))
4943 (set (match_operand 4 "register_operand" "=r,r,r,r")
4944 (match_operator 5 "cris_commutative_orth_op"
4945 [(mem (match_dup 0))
4947 "(rtx_equal_p (operands[2], operands[0])
4948 || rtx_equal_p (operands[3], operands[0]))
4949 && cris_side_effect_mode_ok (PLUS, operands, 0,
4950 (REG_S_P (operands[1])
4952 : (rtx_equal_p (operands[2], operands[0])
4954 (! REG_S_P (operands[1])
4956 : (rtx_equal_p (operands[2], operands[0])
4960 %x5.%s4 [%0=%1%S3],%4
4961 %x5.%s4 [%0=%3%S1],%4
4962 %x5.%s4 [%0=%1%S2],%4
4963 %x5.%s4 [%0=%2%S1],%4")
4965 ;; Another spotted bad code:
4970 [(set (match_operand:SI 0 "register_operand" "=r")
4971 (match_operand:SI 1 "register_operand" "r"))
4972 (set (match_operand 2 "register_operand" "=r")
4973 (mem (match_dup 0)))]
4974 "REGNO (operands[0]) == REGNO (operands[2])
4975 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
4977 [(set_attr "slottable" "yes")])
4979 ;; And a simple variant with extended operand.
4982 [(set (match_operand:SI 0 "register_operand" "=r")
4983 (match_operand:SI 1 "register_operand" "r"))
4984 (set (match_operand 2 "register_operand" "=r")
4985 (match_operator 3 "cris_extend_operator" [(mem (match_dup 0))]))]
4986 "REGNO (operands[0]) == REGNO (operands[2])
4987 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
4988 "mov%e3.%m3 [%1],%0"
4989 [(set_attr "slottable" "yes")])
4991 ;; Here are all peepholes that have a saved testcase.
4992 ;; Do not add new peepholes without testcases.
4995 ;; move.d [r10+16],r9
4998 ;; and.d [r10+16],r12,r9
4999 ;; With generalization of the operation, the size and the addressing mode.
5000 ;; This seems to be the result of a quirk in register allocation
5001 ;; missing the three-operand cases when having different predicates.
5002 ;; Maybe that it matters that it is a commutative operation.
5003 ;; This pattern helps that situation, but there's still the increased
5004 ;; register pressure.
5005 ;; Note that adding the noncommutative variant did not show any matches
5006 ;; in ipps and cc1, so it's not here.
5009 [(set (match_operand 0 "register_operand" "=r,r,r,r")
5011 (match_operand:SI 1 "cris_bdap_biap_operand" "r,r>Rn,r,r>Rn")
5012 (match_operand:SI 2 "cris_bdap_biap_operand" "r>Rn,r,r>Rn,r"))))
5014 (match_operator 5 "cris_commutative_orth_op"
5015 [(match_operand 3 "register_operand" "0,0,r,r")
5016 (match_operand 4 "register_operand" "r,r,0,0")]))]
5017 "(rtx_equal_p (operands[3], operands[0])
5018 || rtx_equal_p (operands[4], operands[0]))
5019 && ! rtx_equal_p (operands[3], operands[4])
5020 && (REG_S_P (operands[1]) || REG_S_P (operands[2]))
5021 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD"
5023 %x5.%s0 [%1%S2],%4,%0
5024 %x5.%s0 [%2%S1],%4,%0
5025 %x5.%s0 [%1%S2],%3,%0
5026 %x5.%s0 [%2%S1],%3,%0")
5029 ;; I cannot tell GCC (2.1, 2.7.2) how to correctly reload an instruction
5031 ;; and.b some_byte,const,reg_32
5032 ;; where reg_32 is the destination of the "three-address" code optimally.
5034 ;; movu.b some_byte,reg_32
5035 ;; and.b const,reg_32
5036 ;; but is turns into:
5037 ;; move.b some_byte,reg_32
5038 ;; and.d const,reg_32
5042 [(set (match_operand:SI 0 "register_operand" "=r")
5043 (match_operand:SI 1 "nonimmediate_operand" "rm"))
5044 (set (match_operand:SI 2 "register_operand" "=0")
5045 (and:SI (match_dup 0)
5046 (match_operand:SI 3 "const_int_operand" "n")))]
5048 ;; Since the size of the memory access could be made different here,
5049 ;; don't do this for a mem-volatile access.
5051 "REGNO (operands[2]) == REGNO (operands[0])
5052 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
5053 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I')
5054 && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))"
5057 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O'))
5058 return \"movu.%z3 %1,%0\;andq %b3,%0\";
5060 cc_status.flags |= CC_NOT_NEGATIVE;
5062 return \"movu.%z3 %1,%0\;and.%z3 %3,%0\";
5068 [(set (match_operand 0 "register_operand" "=r")
5069 (match_operand 1 "nonimmediate_operand" "rm"))
5070 (set (match_operand:SI 2 "register_operand" "=r")
5071 (and:SI (subreg:SI (match_dup 0) 0)
5072 (match_operand 3 "const_int_operand" "n")))]
5074 ;; Since the size of the memory access could be made different here,
5075 ;; don't do this for a mem-volatile access.
5077 "REGNO (operands[0]) == REGNO (operands[2])
5078 && INTVAL (operands[3]) > 0
5079 && INTVAL (operands[3]) <= 65535
5080 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I')
5081 && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))"
5084 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O'))
5085 return \"movu.%z3 %1,%0\;andq %b3,%0\";
5087 cc_status.flags |= CC_NOT_NEGATIVE;
5089 return \"movu.%z3 %1,%0\;and.%z3 %3,%0\";
5094 ;; comment-start: ";; "
5095 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
5096 ;; eval: (modify-syntax-entry ?[ "(]")
5097 ;; eval: (modify-syntax-entry ?] ")[")
5098 ;; eval: (modify-syntax-entry ?{ "(}")
5099 ;; eval: (modify-syntax-entry ?} "){")
5100 ;; eval: (setq indent-tabs-mode t)