1 /* Subroutines for assembler code output on the TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
3 Free Software Foundation, Inc.
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Some output-actions in c4x.md need these. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "basic-block.h"
36 #include "insn-config.h"
37 #include "insn-attr.h"
38 #include "conditions.h"
52 #include "target-def.h"
56 rtx fix_truncqfhi2_libfunc
;
57 rtx fixuns_truncqfhi2_libfunc
;
58 rtx fix_trunchfhi2_libfunc
;
59 rtx fixuns_trunchfhi2_libfunc
;
60 rtx floathiqf2_libfunc
;
61 rtx floatunshiqf2_libfunc
;
62 rtx floathihf2_libfunc
;
63 rtx floatunshihf2_libfunc
;
65 static int c4x_leaf_function
;
67 static const char *const float_reg_names
[] = FLOAT_REGISTER_NAMES
;
69 /* Array of the smallest class containing reg number REGNO, indexed by
70 REGNO. Used by REGNO_REG_CLASS in c4x.h. We assume that all these
71 registers are available and set the class to NO_REGS for registers
72 that the target switches say are unavailable. */
74 enum reg_class c4x_regclass_map
[FIRST_PSEUDO_REGISTER
] =
76 /* Reg Modes Saved. */
77 R0R1_REGS
, /* R0 QI, QF, HF No. */
78 R0R1_REGS
, /* R1 QI, QF, HF No. */
79 R2R3_REGS
, /* R2 QI, QF, HF No. */
80 R2R3_REGS
, /* R3 QI, QF, HF No. */
81 EXT_LOW_REGS
, /* R4 QI, QF, HF QI. */
82 EXT_LOW_REGS
, /* R5 QI, QF, HF QI. */
83 EXT_LOW_REGS
, /* R6 QI, QF, HF QF. */
84 EXT_LOW_REGS
, /* R7 QI, QF, HF QF. */
85 ADDR_REGS
, /* AR0 QI No. */
86 ADDR_REGS
, /* AR1 QI No. */
87 ADDR_REGS
, /* AR2 QI No. */
88 ADDR_REGS
, /* AR3 QI QI. */
89 ADDR_REGS
, /* AR4 QI QI. */
90 ADDR_REGS
, /* AR5 QI QI. */
91 ADDR_REGS
, /* AR6 QI QI. */
92 ADDR_REGS
, /* AR7 QI QI. */
93 DP_REG
, /* DP QI No. */
94 INDEX_REGS
, /* IR0 QI No. */
95 INDEX_REGS
, /* IR1 QI No. */
96 BK_REG
, /* BK QI QI. */
97 SP_REG
, /* SP QI No. */
98 ST_REG
, /* ST CC No. */
99 NO_REGS
, /* DIE/IE No. */
100 NO_REGS
, /* IIE/IF No. */
101 NO_REGS
, /* IIF/IOF No. */
102 INT_REGS
, /* RS QI No. */
103 INT_REGS
, /* RE QI No. */
104 RC_REG
, /* RC QI No. */
105 EXT_REGS
, /* R8 QI, QF, HF QI. */
106 EXT_REGS
, /* R9 QI, QF, HF No. */
107 EXT_REGS
, /* R10 QI, QF, HF No. */
108 EXT_REGS
, /* R11 QI, QF, HF No. */
111 enum machine_mode c4x_caller_save_map
[FIRST_PSEUDO_REGISTER
] =
113 /* Reg Modes Saved. */
114 HFmode
, /* R0 QI, QF, HF No. */
115 HFmode
, /* R1 QI, QF, HF No. */
116 HFmode
, /* R2 QI, QF, HF No. */
117 HFmode
, /* R3 QI, QF, HF No. */
118 QFmode
, /* R4 QI, QF, HF QI. */
119 QFmode
, /* R5 QI, QF, HF QI. */
120 QImode
, /* R6 QI, QF, HF QF. */
121 QImode
, /* R7 QI, QF, HF QF. */
122 QImode
, /* AR0 QI No. */
123 QImode
, /* AR1 QI No. */
124 QImode
, /* AR2 QI No. */
125 QImode
, /* AR3 QI QI. */
126 QImode
, /* AR4 QI QI. */
127 QImode
, /* AR5 QI QI. */
128 QImode
, /* AR6 QI QI. */
129 QImode
, /* AR7 QI QI. */
130 VOIDmode
, /* DP QI No. */
131 QImode
, /* IR0 QI No. */
132 QImode
, /* IR1 QI No. */
133 QImode
, /* BK QI QI. */
134 VOIDmode
, /* SP QI No. */
135 VOIDmode
, /* ST CC No. */
136 VOIDmode
, /* DIE/IE No. */
137 VOIDmode
, /* IIE/IF No. */
138 VOIDmode
, /* IIF/IOF No. */
139 QImode
, /* RS QI No. */
140 QImode
, /* RE QI No. */
141 VOIDmode
, /* RC QI No. */
142 QFmode
, /* R8 QI, QF, HF QI. */
143 HFmode
, /* R9 QI, QF, HF No. */
144 HFmode
, /* R10 QI, QF, HF No. */
145 HFmode
, /* R11 QI, QF, HF No. */
149 /* Test and compare insns in c4x.md store the information needed to
150 generate branch and scc insns here. */
155 const char *c4x_rpts_cycles_string
;
156 int c4x_rpts_cycles
= 0; /* Max. cycles for RPTS. */
157 const char *c4x_cpu_version_string
;
158 int c4x_cpu_version
= 40; /* CPU version C30/31/32/33/40/44. */
160 /* Pragma definitions. */
162 tree code_tree
= NULL_TREE
;
163 tree data_tree
= NULL_TREE
;
164 tree pure_tree
= NULL_TREE
;
165 tree noreturn_tree
= NULL_TREE
;
166 tree interrupt_tree
= NULL_TREE
;
167 tree naked_tree
= NULL_TREE
;
169 /* Forward declarations */
170 static int c4x_isr_reg_used_p (unsigned int);
171 static int c4x_leaf_function_p (void);
172 static int c4x_naked_function_p (void);
173 static int c4x_immed_float_p (rtx
);
174 static int c4x_a_register (rtx
);
175 static int c4x_x_register (rtx
);
176 static int c4x_immed_int_constant (rtx
);
177 static int c4x_immed_float_constant (rtx
);
178 static int c4x_K_constant (rtx
);
179 static int c4x_N_constant (rtx
);
180 static int c4x_O_constant (rtx
);
181 static int c4x_R_indirect (rtx
);
182 static int c4x_S_indirect (rtx
);
183 static void c4x_S_address_parse (rtx
, int *, int *, int *, int *);
184 static int c4x_valid_operands (enum rtx_code
, rtx
*, enum machine_mode
, int);
185 static int c4x_arn_reg_operand (rtx
, enum machine_mode
, unsigned int);
186 static int c4x_arn_mem_operand (rtx
, enum machine_mode
, unsigned int);
187 static void c4x_file_start (void);
188 static void c4x_file_end (void);
189 static void c4x_check_attribute (const char *, tree
, tree
, tree
*);
190 static int c4x_r11_set_p (rtx
);
191 static int c4x_rptb_valid_p (rtx
, rtx
);
192 static void c4x_reorg (void);
193 static int c4x_label_ref_used_p (rtx
, rtx
);
194 static tree
c4x_handle_fntype_attribute (tree
*, tree
, tree
, int, bool *);
195 const struct attribute_spec c4x_attribute_table
[];
196 static void c4x_insert_attributes (tree
, tree
*);
197 static void c4x_asm_named_section (const char *, unsigned int);
198 static int c4x_adjust_cost (rtx
, rtx
, rtx
, int);
199 static void c4x_globalize_label (FILE *, const char *);
200 static bool c4x_rtx_costs (rtx
, int, int, int *);
201 static int c4x_address_cost (rtx
);
202 static void c4x_init_libfuncs (void);
204 /* Initialize the GCC target structure. */
205 #undef TARGET_ASM_BYTE_OP
206 #define TARGET_ASM_BYTE_OP "\t.word\t"
207 #undef TARGET_ASM_ALIGNED_HI_OP
208 #define TARGET_ASM_ALIGNED_HI_OP NULL
209 #undef TARGET_ASM_ALIGNED_SI_OP
210 #define TARGET_ASM_ALIGNED_SI_OP NULL
211 #undef TARGET_ASM_FILE_START
212 #define TARGET_ASM_FILE_START c4x_file_start
213 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
214 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
215 #undef TARGET_ASM_FILE_END
216 #define TARGET_ASM_FILE_END c4x_file_end
218 #undef TARGET_ATTRIBUTE_TABLE
219 #define TARGET_ATTRIBUTE_TABLE c4x_attribute_table
221 #undef TARGET_INSERT_ATTRIBUTES
222 #define TARGET_INSERT_ATTRIBUTES c4x_insert_attributes
224 #undef TARGET_INIT_BUILTINS
225 #define TARGET_INIT_BUILTINS c4x_init_builtins
227 #undef TARGET_EXPAND_BUILTIN
228 #define TARGET_EXPAND_BUILTIN c4x_expand_builtin
230 #undef TARGET_SCHED_ADJUST_COST
231 #define TARGET_SCHED_ADJUST_COST c4x_adjust_cost
233 #undef TARGET_ASM_GLOBALIZE_LABEL
234 #define TARGET_ASM_GLOBALIZE_LABEL c4x_globalize_label
236 #undef TARGET_RTX_COSTS
237 #define TARGET_RTX_COSTS c4x_rtx_costs
238 #undef TARGET_ADDRESS_COST
239 #define TARGET_ADDRESS_COST c4x_address_cost
241 #undef TARGET_MACHINE_DEPENDENT_REORG
242 #define TARGET_MACHINE_DEPENDENT_REORG c4x_reorg
244 #undef TARGET_INIT_LIBFUNCS
245 #define TARGET_INIT_LIBFUNCS c4x_init_libfuncs
247 struct gcc_target targetm
= TARGET_INITIALIZER
;
249 /* Override command line options.
250 Called once after all options have been parsed.
251 Mostly we process the processor
252 type and sometimes adjust other TARGET_ options. */
255 c4x_override_options (void)
257 if (c4x_rpts_cycles_string
)
258 c4x_rpts_cycles
= atoi (c4x_rpts_cycles_string
);
263 c4x_cpu_version
= 30;
265 c4x_cpu_version
= 31;
267 c4x_cpu_version
= 32;
269 c4x_cpu_version
= 33;
271 c4x_cpu_version
= 40;
273 c4x_cpu_version
= 44;
275 c4x_cpu_version
= 40;
277 /* -mcpu=xx overrides -m40 etc. */
278 if (c4x_cpu_version_string
)
280 const char *p
= c4x_cpu_version_string
;
282 /* Also allow -mcpu=c30 etc. */
283 if (*p
== 'c' || *p
== 'C')
285 c4x_cpu_version
= atoi (p
);
288 target_flags
&= ~(C30_FLAG
| C31_FLAG
| C32_FLAG
| C33_FLAG
|
289 C40_FLAG
| C44_FLAG
);
291 switch (c4x_cpu_version
)
293 case 30: target_flags
|= C30_FLAG
; break;
294 case 31: target_flags
|= C31_FLAG
; break;
295 case 32: target_flags
|= C32_FLAG
; break;
296 case 33: target_flags
|= C33_FLAG
; break;
297 case 40: target_flags
|= C40_FLAG
; break;
298 case 44: target_flags
|= C44_FLAG
; break;
300 warning ("unknown CPU version %d, using 40.\n", c4x_cpu_version
);
301 c4x_cpu_version
= 40;
302 target_flags
|= C40_FLAG
;
305 if (TARGET_C30
|| TARGET_C31
|| TARGET_C32
|| TARGET_C33
)
306 target_flags
|= C3X_FLAG
;
308 target_flags
&= ~C3X_FLAG
;
310 /* Convert foo / 8.0 into foo * 0.125, etc. */
311 set_fast_math_flags (1);
313 /* We should phase out the following at some stage.
314 This provides compatibility with the old -mno-aliases option. */
315 if (! TARGET_ALIASES
&& ! flag_argument_noalias
)
316 flag_argument_noalias
= 1;
320 /* This is called before c4x_override_options. */
323 c4x_optimization_options (int level ATTRIBUTE_UNUSED
,
324 int size ATTRIBUTE_UNUSED
)
326 /* Scheduling before register allocation can screw up global
327 register allocation, especially for functions that use MPY||ADD
328 instructions. The benefit we gain we get by scheduling before
329 register allocation is probably marginal anyhow. */
330 flag_schedule_insns
= 0;
334 /* Write an ASCII string. */
336 #define C4X_ASCII_LIMIT 40
339 c4x_output_ascii (FILE *stream
, const char *ptr
, int len
)
341 char sbuf
[C4X_ASCII_LIMIT
+ 1];
342 int s
, l
, special
, first
= 1, onlys
;
345 fprintf (stream
, "\t.byte\t");
347 for (s
= l
= 0; len
> 0; --len
, ++ptr
)
351 /* Escape " and \ with a \". */
352 special
= *ptr
== '\"' || *ptr
== '\\';
354 /* If printable - add to buff. */
355 if ((! TARGET_TI
|| ! special
) && *ptr
>= 0x20 && *ptr
< 0x7f)
360 if (s
< C4X_ASCII_LIMIT
- 1)
375 fprintf (stream
, "\"%s\"", sbuf
);
377 if (TARGET_TI
&& l
>= 80 && len
> 1)
379 fprintf (stream
, "\n\t.byte\t");
397 fprintf (stream
, "%d", *ptr
);
399 if (TARGET_TI
&& l
>= 80 && len
> 1)
401 fprintf (stream
, "\n\t.byte\t");
412 fprintf (stream
, "\"%s\"", sbuf
);
415 fputc ('\n', stream
);
420 c4x_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
425 case Pmode
: /* Pointer (24/32 bits). */
427 case QImode
: /* Integer (32 bits). */
428 return IS_INT_REGNO (regno
);
430 case QFmode
: /* Float, Double (32 bits). */
431 case HFmode
: /* Long Double (40 bits). */
432 return IS_EXT_REGNO (regno
);
434 case CCmode
: /* Condition Codes. */
435 case CC_NOOVmode
: /* Condition Codes. */
436 return IS_ST_REGNO (regno
);
438 case HImode
: /* Long Long (64 bits). */
439 /* We need two registers to store long longs. Note that
440 it is much easier to constrain the first register
441 to start on an even boundary. */
442 return IS_INT_REGNO (regno
)
443 && IS_INT_REGNO (regno
+ 1)
447 return 0; /* We don't support these modes. */
453 /* Return nonzero if REGNO1 can be renamed to REGNO2. */
455 c4x_hard_regno_rename_ok (unsigned int regno1
, unsigned int regno2
)
457 /* We can not copy call saved registers from mode QI into QF or from
459 if (IS_FLOAT_CALL_SAVED_REGNO (regno1
) && IS_INT_CALL_SAVED_REGNO (regno2
))
461 if (IS_INT_CALL_SAVED_REGNO (regno1
) && IS_FLOAT_CALL_SAVED_REGNO (regno2
))
463 /* We cannot copy from an extended (40 bit) register to a standard
464 (32 bit) register because we only set the condition codes for
465 extended registers. */
466 if (IS_EXT_REGNO (regno1
) && ! IS_EXT_REGNO (regno2
))
468 if (IS_EXT_REGNO (regno2
) && ! IS_EXT_REGNO (regno1
))
473 /* The TI C3x C compiler register argument runtime model uses 6 registers,
474 AR2, R2, R3, RC, RS, RE.
476 The first two floating point arguments (float, double, long double)
477 that are found scanning from left to right are assigned to R2 and R3.
479 The remaining integer (char, short, int, long) or pointer arguments
480 are assigned to the remaining registers in the order AR2, R2, R3,
481 RC, RS, RE when scanning left to right, except for the last named
482 argument prior to an ellipsis denoting variable number of
483 arguments. We don't have to worry about the latter condition since
484 function.c treats the last named argument as anonymous (unnamed).
486 All arguments that cannot be passed in registers are pushed onto
487 the stack in reverse order (right to left). GCC handles that for us.
489 c4x_init_cumulative_args() is called at the start, so we can parse
490 the args to see how many floating point arguments and how many
491 integer (or pointer) arguments there are. c4x_function_arg() is
492 then called (sometimes repeatedly) for each argument (parsed left
493 to right) to obtain the register to pass the argument in, or zero
494 if the argument is to be passed on the stack. Once the compiler is
495 happy, c4x_function_arg_advance() is called.
497 Don't use R0 to pass arguments in, we use 0 to indicate a stack
500 static const int c4x_int_reglist
[3][6] =
502 {AR2_REGNO
, R2_REGNO
, R3_REGNO
, RC_REGNO
, RS_REGNO
, RE_REGNO
},
503 {AR2_REGNO
, R3_REGNO
, RC_REGNO
, RS_REGNO
, RE_REGNO
, 0},
504 {AR2_REGNO
, RC_REGNO
, RS_REGNO
, RE_REGNO
, 0, 0}
507 static const int c4x_fp_reglist
[2] = {R2_REGNO
, R3_REGNO
};
510 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
511 function whose data type is FNTYPE.
512 For a library call, FNTYPE is 0. */
515 c4x_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
, rtx libname
)
517 tree param
, next_param
;
519 cum
->floats
= cum
->ints
= 0;
526 fprintf (stderr
, "\nc4x_init_cumulative_args (");
529 tree ret_type
= TREE_TYPE (fntype
);
531 fprintf (stderr
, "fntype code = %s, ret code = %s",
532 tree_code_name
[(int) TREE_CODE (fntype
)],
533 tree_code_name
[(int) TREE_CODE (ret_type
)]);
536 fprintf (stderr
, "no fntype");
539 fprintf (stderr
, ", libname = %s", XSTR (libname
, 0));
542 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
544 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
545 param
; param
= next_param
)
549 next_param
= TREE_CHAIN (param
);
551 type
= TREE_VALUE (param
);
552 if (type
&& type
!= void_type_node
)
554 enum machine_mode mode
;
556 /* If the last arg doesn't have void type then we have
557 variable arguments. */
561 if ((mode
= TYPE_MODE (type
)))
563 if (! MUST_PASS_IN_STACK (mode
, type
))
565 /* Look for float, double, or long double argument. */
566 if (mode
== QFmode
|| mode
== HFmode
)
568 /* Look for integer, enumeral, boolean, char, or pointer
570 else if (mode
== QImode
|| mode
== Pmode
)
579 fprintf (stderr
, "%s%s, args = %d)\n",
580 cum
->prototype
? ", prototype" : "",
581 cum
->var
? ", variable args" : "",
586 /* Update the data in CUM to advance over an argument
587 of mode MODE and data type TYPE.
588 (TYPE is null for libcalls where that information may not be available.) */
591 c4x_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
592 tree type
, int named
)
595 fprintf (stderr
, "c4x_function_adv(mode=%s, named=%d)\n\n",
596 GET_MODE_NAME (mode
), named
);
600 && ! MUST_PASS_IN_STACK (mode
, type
))
602 /* Look for float, double, or long double argument. */
603 if (mode
== QFmode
|| mode
== HFmode
)
605 /* Look for integer, enumeral, boolean, char, or pointer argument. */
606 else if (mode
== QImode
|| mode
== Pmode
)
609 else if (! TARGET_MEMPARM
&& ! type
)
611 /* Handle libcall arguments. */
612 if (mode
== QFmode
|| mode
== HFmode
)
614 else if (mode
== QImode
|| mode
== Pmode
)
621 /* Define where to put the arguments to a function. Value is zero to
622 push the argument on the stack, or a hard register in which to
625 MODE is the argument's machine mode.
626 TYPE is the data type of the argument (as a tree).
627 This is null for libcalls where that information may
629 CUM is a variable of type CUMULATIVE_ARGS which gives info about
630 the preceding args and about the function being called.
631 NAMED is nonzero if this argument is a named parameter
632 (otherwise it is an extra parameter matching an ellipsis). */
635 c4x_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
636 tree type
, int named
)
638 int reg
= 0; /* Default to passing argument on stack. */
642 /* We can handle at most 2 floats in R2, R3. */
643 cum
->maxfloats
= (cum
->floats
> 2) ? 2 : cum
->floats
;
645 /* We can handle at most 6 integers minus number of floats passed
647 cum
->maxints
= (cum
->ints
> 6 - cum
->maxfloats
) ?
648 6 - cum
->maxfloats
: cum
->ints
;
650 /* If there is no prototype, assume all the arguments are integers. */
651 if (! cum
->prototype
)
654 cum
->ints
= cum
->floats
= 0;
658 /* This marks the last argument. We don't need to pass this through
660 if (type
== void_type_node
)
666 && ! MUST_PASS_IN_STACK (mode
, type
))
668 /* Look for float, double, or long double argument. */
669 if (mode
== QFmode
|| mode
== HFmode
)
671 if (cum
->floats
< cum
->maxfloats
)
672 reg
= c4x_fp_reglist
[cum
->floats
];
674 /* Look for integer, enumeral, boolean, char, or pointer argument. */
675 else if (mode
== QImode
|| mode
== Pmode
)
677 if (cum
->ints
< cum
->maxints
)
678 reg
= c4x_int_reglist
[cum
->maxfloats
][cum
->ints
];
681 else if (! TARGET_MEMPARM
&& ! type
)
683 /* We could use a different argument calling model for libcalls,
684 since we're only calling functions in libgcc. Thus we could
685 pass arguments for long longs in registers rather than on the
686 stack. In the meantime, use the odd TI format. We make the
687 assumption that we won't have more than two floating point
688 args, six integer args, and that all the arguments are of the
690 if (mode
== QFmode
|| mode
== HFmode
)
691 reg
= c4x_fp_reglist
[cum
->floats
];
692 else if (mode
== QImode
|| mode
== Pmode
)
693 reg
= c4x_int_reglist
[0][cum
->ints
];
698 fprintf (stderr
, "c4x_function_arg(mode=%s, named=%d",
699 GET_MODE_NAME (mode
), named
);
701 fprintf (stderr
, ", reg=%s", reg_names
[reg
]);
703 fprintf (stderr
, ", stack");
704 fprintf (stderr
, ")\n");
707 return gen_rtx_REG (mode
, reg
);
712 /* C[34]x arguments grow in weird ways (downwards) that the standard
713 varargs stuff can't handle.. */
715 c4x_va_arg (tree valist
, tree type
)
719 t
= build (PREDECREMENT_EXPR
, TREE_TYPE (valist
), valist
,
720 build_int_2 (int_size_in_bytes (type
), 0));
721 TREE_SIDE_EFFECTS (t
) = 1;
723 return expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
728 c4x_isr_reg_used_p (unsigned int regno
)
730 /* Don't save/restore FP or ST, we handle them separately. */
731 if (regno
== FRAME_POINTER_REGNUM
732 || IS_ST_REGNO (regno
))
735 /* We could be a little smarter abut saving/restoring DP.
736 We'll only save if for the big memory model or if
737 we're paranoid. ;-) */
738 if (IS_DP_REGNO (regno
))
739 return ! TARGET_SMALL
|| TARGET_PARANOID
;
741 /* Only save/restore regs in leaf function that are used. */
742 if (c4x_leaf_function
)
743 return regs_ever_live
[regno
] && fixed_regs
[regno
] == 0;
745 /* Only save/restore regs that are used by the ISR and regs
746 that are likely to be used by functions the ISR calls
747 if they are not fixed. */
748 return IS_EXT_REGNO (regno
)
749 || ((regs_ever_live
[regno
] || call_used_regs
[regno
])
750 && fixed_regs
[regno
] == 0);
755 c4x_leaf_function_p (void)
757 /* A leaf function makes no calls, so we only need
758 to save/restore the registers we actually use.
759 For the global variable leaf_function to be set, we need
760 to define LEAF_REGISTERS and all that it entails.
761 Let's check ourselves... */
763 if (lookup_attribute ("leaf_pretend",
764 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
767 /* Use the leaf_pretend attribute at your own risk. This is a hack
768 to speed up ISRs that call a function infrequently where the
769 overhead of saving and restoring the additional registers is not
770 warranted. You must save and restore the additional registers
771 required by the called function. Caveat emptor. Here's enough
774 if (leaf_function_p ())
782 c4x_naked_function_p (void)
786 type
= TREE_TYPE (current_function_decl
);
787 return lookup_attribute ("naked", TYPE_ATTRIBUTES (type
)) != NULL
;
792 c4x_interrupt_function_p (void)
794 if (lookup_attribute ("interrupt",
795 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
798 /* Look for TI style c_intnn. */
799 return current_function_name
[0] == 'c'
800 && current_function_name
[1] == '_'
801 && current_function_name
[2] == 'i'
802 && current_function_name
[3] == 'n'
803 && current_function_name
[4] == 't'
804 && ISDIGIT (current_function_name
[5])
805 && ISDIGIT (current_function_name
[6]);
809 c4x_expand_prologue (void)
812 int size
= get_frame_size ();
815 /* In functions where ar3 is not used but frame pointers are still
816 specified, frame pointers are not adjusted (if >= -O2) and this
817 is used so it won't needlessly push the frame pointer. */
820 /* For __naked__ function don't build a prologue. */
821 if (c4x_naked_function_p ())
826 /* For __interrupt__ function build specific prologue. */
827 if (c4x_interrupt_function_p ())
829 c4x_leaf_function
= c4x_leaf_function_p ();
831 insn
= emit_insn (gen_push_st ());
832 RTX_FRAME_RELATED_P (insn
) = 1;
835 insn
= emit_insn (gen_pushqi ( gen_rtx_REG (QImode
, AR3_REGNO
)));
836 RTX_FRAME_RELATED_P (insn
) = 1;
837 insn
= emit_insn (gen_movqi (gen_rtx_REG (QImode
, AR3_REGNO
),
838 gen_rtx_REG (QImode
, SP_REGNO
)));
839 RTX_FRAME_RELATED_P (insn
) = 1;
840 /* We require that an ISR uses fewer than 32768 words of
841 local variables, otherwise we have to go to lots of
842 effort to save a register, load it with the desired size,
843 adjust the stack pointer, and then restore the modified
844 register. Frankly, I think it is a poor ISR that
845 requires more than 32767 words of local temporary
848 error ("ISR %s requires %d words of local vars, max is 32767",
849 current_function_name
, size
);
851 insn
= emit_insn (gen_addqi3 (gen_rtx_REG (QImode
, SP_REGNO
),
852 gen_rtx_REG (QImode
, SP_REGNO
),
854 RTX_FRAME_RELATED_P (insn
) = 1;
856 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
858 if (c4x_isr_reg_used_p (regno
))
860 if (regno
== DP_REGNO
)
862 insn
= emit_insn (gen_push_dp ());
863 RTX_FRAME_RELATED_P (insn
) = 1;
867 insn
= emit_insn (gen_pushqi (gen_rtx_REG (QImode
, regno
)));
868 RTX_FRAME_RELATED_P (insn
) = 1;
869 if (IS_EXT_REGNO (regno
))
871 insn
= emit_insn (gen_pushqf
872 (gen_rtx_REG (QFmode
, regno
)));
873 RTX_FRAME_RELATED_P (insn
) = 1;
878 /* We need to clear the repeat mode flag if the ISR is
879 going to use a RPTB instruction or uses the RC, RS, or RE
881 if (regs_ever_live
[RC_REGNO
]
882 || regs_ever_live
[RS_REGNO
]
883 || regs_ever_live
[RE_REGNO
])
885 insn
= emit_insn (gen_andn_st (GEN_INT(~0x100)));
886 RTX_FRAME_RELATED_P (insn
) = 1;
889 /* Reload DP reg if we are paranoid about some turkey
890 violating small memory model rules. */
891 if (TARGET_SMALL
&& TARGET_PARANOID
)
893 insn
= emit_insn (gen_set_ldp_prologue
894 (gen_rtx_REG (QImode
, DP_REGNO
),
895 gen_rtx_SYMBOL_REF (QImode
, "data_sec")));
896 RTX_FRAME_RELATED_P (insn
) = 1;
901 if (frame_pointer_needed
)
904 || (current_function_args_size
!= 0)
907 insn
= emit_insn (gen_pushqi ( gen_rtx_REG (QImode
, AR3_REGNO
)));
908 RTX_FRAME_RELATED_P (insn
) = 1;
909 insn
= emit_insn (gen_movqi (gen_rtx_REG (QImode
, AR3_REGNO
),
910 gen_rtx_REG (QImode
, SP_REGNO
)));
911 RTX_FRAME_RELATED_P (insn
) = 1;
916 /* Since ar3 is not used, we don't need to push it. */
922 /* If we use ar3, we need to push it. */
924 if ((size
!= 0) || (current_function_args_size
!= 0))
926 /* If we are omitting the frame pointer, we still have
927 to make space for it so the offsets are correct
928 unless we don't use anything on the stack at all. */
935 /* Local vars are too big, it will take multiple operations
939 insn
= emit_insn (gen_movqi (gen_rtx_REG (QImode
, R1_REGNO
),
940 GEN_INT(size
>> 16)));
941 RTX_FRAME_RELATED_P (insn
) = 1;
942 insn
= emit_insn (gen_lshrqi3 (gen_rtx_REG (QImode
, R1_REGNO
),
943 gen_rtx_REG (QImode
, R1_REGNO
),
945 RTX_FRAME_RELATED_P (insn
) = 1;
949 insn
= emit_insn (gen_movqi (gen_rtx_REG (QImode
, R1_REGNO
),
950 GEN_INT(size
& ~0xffff)));
951 RTX_FRAME_RELATED_P (insn
) = 1;
953 insn
= emit_insn (gen_iorqi3 (gen_rtx_REG (QImode
, R1_REGNO
),
954 gen_rtx_REG (QImode
, R1_REGNO
),
955 GEN_INT(size
& 0xffff)));
956 RTX_FRAME_RELATED_P (insn
) = 1;
957 insn
= emit_insn (gen_addqi3 (gen_rtx_REG (QImode
, SP_REGNO
),
958 gen_rtx_REG (QImode
, SP_REGNO
),
959 gen_rtx_REG (QImode
, R1_REGNO
)));
960 RTX_FRAME_RELATED_P (insn
) = 1;
964 /* Local vars take up less than 32767 words, so we can directly
966 insn
= emit_insn (gen_addqi3 (gen_rtx_REG (QImode
, SP_REGNO
),
967 gen_rtx_REG (QImode
, SP_REGNO
),
969 RTX_FRAME_RELATED_P (insn
) = 1;
972 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
974 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
976 if (IS_FLOAT_CALL_SAVED_REGNO (regno
))
978 if (TARGET_PRESERVE_FLOAT
)
980 insn
= emit_insn (gen_pushqi
981 (gen_rtx_REG (QImode
, regno
)));
982 RTX_FRAME_RELATED_P (insn
) = 1;
984 insn
= emit_insn (gen_pushqf (gen_rtx_REG (QFmode
, regno
)));
985 RTX_FRAME_RELATED_P (insn
) = 1;
987 else if ((! dont_push_ar3
) || (regno
!= AR3_REGNO
))
989 insn
= emit_insn (gen_pushqi ( gen_rtx_REG (QImode
, regno
)));
990 RTX_FRAME_RELATED_P (insn
) = 1;
999 c4x_expand_epilogue(void)
1005 int size
= get_frame_size ();
1007 /* For __naked__ function build no epilogue. */
1008 if (c4x_naked_function_p ())
1010 insn
= emit_jump_insn (gen_return_from_epilogue ());
1011 RTX_FRAME_RELATED_P (insn
) = 1;
1015 /* For __interrupt__ function build specific epilogue. */
1016 if (c4x_interrupt_function_p ())
1018 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; --regno
)
1020 if (! c4x_isr_reg_used_p (regno
))
1022 if (regno
== DP_REGNO
)
1024 insn
= emit_insn (gen_pop_dp ());
1025 RTX_FRAME_RELATED_P (insn
) = 1;
1029 /* We have to use unspec because the compiler will delete insns
1030 that are not call-saved. */
1031 if (IS_EXT_REGNO (regno
))
1033 insn
= emit_insn (gen_popqf_unspec
1034 (gen_rtx_REG (QFmode
, regno
)));
1035 RTX_FRAME_RELATED_P (insn
) = 1;
1037 insn
= emit_insn (gen_popqi_unspec (gen_rtx_REG (QImode
, regno
)));
1038 RTX_FRAME_RELATED_P (insn
) = 1;
1043 insn
= emit_insn (gen_subqi3 (gen_rtx_REG (QImode
, SP_REGNO
),
1044 gen_rtx_REG (QImode
, SP_REGNO
),
1046 RTX_FRAME_RELATED_P (insn
) = 1;
1047 insn
= emit_insn (gen_popqi
1048 (gen_rtx_REG (QImode
, AR3_REGNO
)));
1049 RTX_FRAME_RELATED_P (insn
) = 1;
1051 insn
= emit_insn (gen_pop_st ());
1052 RTX_FRAME_RELATED_P (insn
) = 1;
1053 insn
= emit_jump_insn (gen_return_from_interrupt_epilogue ());
1054 RTX_FRAME_RELATED_P (insn
) = 1;
1058 if (frame_pointer_needed
)
1061 || (current_function_args_size
!= 0)
1065 (gen_movqi (gen_rtx_REG (QImode
, R2_REGNO
),
1066 gen_rtx_MEM (QImode
,
1068 (QImode
, gen_rtx_REG (QImode
,
1071 RTX_FRAME_RELATED_P (insn
) = 1;
1073 /* We already have the return value and the fp,
1074 so we need to add those to the stack. */
1081 /* Since ar3 is not used for anything, we don't need to
1088 dont_pop_ar3
= 0; /* If we use ar3, we need to pop it. */
1089 if (size
|| current_function_args_size
)
1091 /* If we are omitting the frame pointer, we still have
1092 to make space for it so the offsets are correct
1093 unless we don't use anything on the stack at all. */
1098 /* Now restore the saved registers, putting in the delayed branch
1100 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
--)
1102 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1104 if (regno
== AR3_REGNO
&& dont_pop_ar3
)
1107 if (IS_FLOAT_CALL_SAVED_REGNO (regno
))
1109 insn
= emit_insn (gen_popqf_unspec
1110 (gen_rtx_REG (QFmode
, regno
)));
1111 RTX_FRAME_RELATED_P (insn
) = 1;
1112 if (TARGET_PRESERVE_FLOAT
)
1114 insn
= emit_insn (gen_popqi_unspec
1115 (gen_rtx_REG (QImode
, regno
)));
1116 RTX_FRAME_RELATED_P (insn
) = 1;
1121 insn
= emit_insn (gen_popqi (gen_rtx_REG (QImode
, regno
)));
1122 RTX_FRAME_RELATED_P (insn
) = 1;
1127 if (frame_pointer_needed
)
1130 || (current_function_args_size
!= 0)
1133 /* Restore the old FP. */
1136 (gen_rtx_REG (QImode
, AR3_REGNO
),
1137 gen_rtx_MEM (QImode
, gen_rtx_REG (QImode
, AR3_REGNO
))));
1139 RTX_FRAME_RELATED_P (insn
) = 1;
1145 /* Local vars are too big, it will take multiple operations
1149 insn
= emit_insn (gen_movqi (gen_rtx_REG (QImode
, R3_REGNO
),
1150 GEN_INT(size
>> 16)));
1151 RTX_FRAME_RELATED_P (insn
) = 1;
1152 insn
= emit_insn (gen_lshrqi3 (gen_rtx_REG (QImode
, R3_REGNO
),
1153 gen_rtx_REG (QImode
, R3_REGNO
),
1155 RTX_FRAME_RELATED_P (insn
) = 1;
1159 insn
= emit_insn (gen_movqi (gen_rtx_REG (QImode
, R3_REGNO
),
1160 GEN_INT(size
& ~0xffff)));
1161 RTX_FRAME_RELATED_P (insn
) = 1;
1163 insn
= emit_insn (gen_iorqi3 (gen_rtx_REG (QImode
, R3_REGNO
),
1164 gen_rtx_REG (QImode
, R3_REGNO
),
1165 GEN_INT(size
& 0xffff)));
1166 RTX_FRAME_RELATED_P (insn
) = 1;
1167 insn
= emit_insn (gen_subqi3 (gen_rtx_REG (QImode
, SP_REGNO
),
1168 gen_rtx_REG (QImode
, SP_REGNO
),
1169 gen_rtx_REG (QImode
, R3_REGNO
)));
1170 RTX_FRAME_RELATED_P (insn
) = 1;
1174 /* Local vars take up less than 32768 words, so we can directly
1175 subtract the number. */
1176 insn
= emit_insn (gen_subqi3 (gen_rtx_REG (QImode
, SP_REGNO
),
1177 gen_rtx_REG (QImode
, SP_REGNO
),
1179 RTX_FRAME_RELATED_P (insn
) = 1;
1184 insn
= emit_jump_insn (gen_return_indirect_internal
1185 (gen_rtx_REG (QImode
, R2_REGNO
)));
1186 RTX_FRAME_RELATED_P (insn
) = 1;
1190 insn
= emit_jump_insn (gen_return_from_epilogue ());
1191 RTX_FRAME_RELATED_P (insn
) = 1;
1198 c4x_null_epilogue_p (void)
1202 if (reload_completed
1203 && ! c4x_naked_function_p ()
1204 && ! c4x_interrupt_function_p ()
1205 && ! current_function_calls_alloca
1206 && ! current_function_args_size
1208 && ! get_frame_size ())
1210 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
--)
1211 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
]
1212 && (regno
!= AR3_REGNO
))
1221 c4x_emit_move_sequence (rtx
*operands
, enum machine_mode mode
)
1223 rtx op0
= operands
[0];
1224 rtx op1
= operands
[1];
1226 if (! reload_in_progress
1229 && ! (stik_const_operand (op1
, mode
) && ! push_operand (op0
, mode
)))
1230 op1
= force_reg (mode
, op1
);
1232 if (GET_CODE (op1
) == LO_SUM
1233 && GET_MODE (op1
) == Pmode
1234 && dp_reg_operand (XEXP (op1
, 0), mode
))
1236 /* expand_increment will sometimes create a LO_SUM immediate
1238 op1
= XEXP (op1
, 1);
1240 else if (symbolic_address_operand (op1
, mode
))
1242 if (TARGET_LOAD_ADDRESS
)
1244 /* Alias analysis seems to do a better job if we force
1245 constant addresses to memory after reload. */
1246 emit_insn (gen_load_immed_address (op0
, op1
));
1251 /* Stick symbol or label address into the constant pool. */
1252 op1
= force_const_mem (Pmode
, op1
);
1255 else if (mode
== HFmode
&& CONSTANT_P (op1
) && ! LEGITIMATE_CONSTANT_P (op1
))
1257 /* We could be a lot smarter about loading some of these
1259 op1
= force_const_mem (mode
, op1
);
1262 /* Convert (MEM (SYMREF)) to a (MEM (LO_SUM (REG) (SYMREF)))
1263 and emit associated (HIGH (SYMREF)) if large memory model.
1264 c4x_legitimize_address could be used to do this,
1265 perhaps by calling validize_address. */
1266 if (TARGET_EXPOSE_LDP
1267 && ! (reload_in_progress
|| reload_completed
)
1268 && GET_CODE (op1
) == MEM
1269 && symbolic_address_operand (XEXP (op1
, 0), Pmode
))
1271 rtx dp_reg
= gen_rtx_REG (Pmode
, DP_REGNO
);
1273 emit_insn (gen_set_ldp (dp_reg
, XEXP (op1
, 0)));
1274 op1
= change_address (op1
, mode
,
1275 gen_rtx_LO_SUM (Pmode
, dp_reg
, XEXP (op1
, 0)));
1278 if (TARGET_EXPOSE_LDP
1279 && ! (reload_in_progress
|| reload_completed
)
1280 && GET_CODE (op0
) == MEM
1281 && symbolic_address_operand (XEXP (op0
, 0), Pmode
))
1283 rtx dp_reg
= gen_rtx_REG (Pmode
, DP_REGNO
);
1285 emit_insn (gen_set_ldp (dp_reg
, XEXP (op0
, 0)));
1286 op0
= change_address (op0
, mode
,
1287 gen_rtx_LO_SUM (Pmode
, dp_reg
, XEXP (op0
, 0)));
1290 if (GET_CODE (op0
) == SUBREG
1291 && mixed_subreg_operand (op0
, mode
))
1293 /* We should only generate these mixed mode patterns
1294 during RTL generation. If we need do it later on
1295 then we'll have to emit patterns that won't clobber CC. */
1296 if (reload_in_progress
|| reload_completed
)
1298 if (GET_MODE (SUBREG_REG (op0
)) == QImode
)
1299 op0
= SUBREG_REG (op0
);
1300 else if (GET_MODE (SUBREG_REG (op0
)) == HImode
)
1302 op0
= copy_rtx (op0
);
1303 PUT_MODE (op0
, QImode
);
1309 emit_insn (gen_storeqf_int_clobber (op0
, op1
));
1315 if (GET_CODE (op1
) == SUBREG
1316 && mixed_subreg_operand (op1
, mode
))
1318 /* We should only generate these mixed mode patterns
1319 during RTL generation. If we need do it later on
1320 then we'll have to emit patterns that won't clobber CC. */
1321 if (reload_in_progress
|| reload_completed
)
1323 if (GET_MODE (SUBREG_REG (op1
)) == QImode
)
1324 op1
= SUBREG_REG (op1
);
1325 else if (GET_MODE (SUBREG_REG (op1
)) == HImode
)
1327 op1
= copy_rtx (op1
);
1328 PUT_MODE (op1
, QImode
);
1334 emit_insn (gen_loadqf_int_clobber (op0
, op1
));
1341 && reg_operand (op0
, mode
)
1342 && const_int_operand (op1
, mode
)
1343 && ! IS_INT16_CONST (INTVAL (op1
))
1344 && ! IS_HIGH_CONST (INTVAL (op1
)))
1346 emit_insn (gen_loadqi_big_constant (op0
, op1
));
1351 && reg_operand (op0
, mode
)
1352 && const_int_operand (op1
, mode
))
1354 emit_insn (gen_loadhi_big_constant (op0
, op1
));
1358 /* Adjust operands in case we have modified them. */
1362 /* Emit normal pattern. */
1368 c4x_emit_libcall (rtx libcall
, enum rtx_code code
,
1369 enum machine_mode dmode
, enum machine_mode smode
,
1370 int noperands
, rtx
*operands
)
1380 ret
= emit_library_call_value (libcall
, NULL_RTX
, 1, dmode
, 1,
1381 operands
[1], smode
);
1382 equiv
= gen_rtx (code
, dmode
, operands
[1]);
1386 ret
= emit_library_call_value (libcall
, NULL_RTX
, 1, dmode
, 2,
1387 operands
[1], smode
, operands
[2], smode
);
1388 equiv
= gen_rtx (code
, dmode
, operands
[1], operands
[2]);
1395 insns
= get_insns ();
1397 emit_libcall_block (insns
, operands
[0], ret
, equiv
);
1402 c4x_emit_libcall3 (rtx libcall
, enum rtx_code code
,
1403 enum machine_mode mode
, rtx
*operands
)
1405 c4x_emit_libcall (libcall
, code
, mode
, mode
, 3, operands
);
1410 c4x_emit_libcall_mulhi (rtx libcall
, enum rtx_code code
,
1411 enum machine_mode mode
, rtx
*operands
)
1418 ret
= emit_library_call_value (libcall
, NULL_RTX
, 1, mode
, 2,
1419 operands
[1], mode
, operands
[2], mode
);
1420 equiv
= gen_rtx_TRUNCATE (mode
,
1421 gen_rtx_LSHIFTRT (HImode
,
1422 gen_rtx_MULT (HImode
,
1423 gen_rtx (code
, HImode
, operands
[1]),
1424 gen_rtx (code
, HImode
, operands
[2])),
1426 insns
= get_insns ();
1428 emit_libcall_block (insns
, operands
[0], ret
, equiv
);
1433 c4x_check_legit_addr (enum machine_mode mode
, rtx addr
, int strict
)
1435 rtx base
= NULL_RTX
; /* Base register (AR0-AR7). */
1436 rtx indx
= NULL_RTX
; /* Index register (IR0,IR1). */
1437 rtx disp
= NULL_RTX
; /* Displacement. */
1440 code
= GET_CODE (addr
);
1443 /* Register indirect with auto increment/decrement. We don't
1444 allow SP here---push_operand should recognize an operand
1445 being pushed on the stack. */
1450 if (mode
!= QImode
&& mode
!= QFmode
)
1454 base
= XEXP (addr
, 0);
1462 rtx op0
= XEXP (addr
, 0);
1463 rtx op1
= XEXP (addr
, 1);
1465 if (mode
!= QImode
&& mode
!= QFmode
)
1469 || (GET_CODE (op1
) != PLUS
&& GET_CODE (op1
) != MINUS
))
1471 base
= XEXP (op1
, 0);
1474 if (REG_P (XEXP (op1
, 1)))
1475 indx
= XEXP (op1
, 1);
1477 disp
= XEXP (op1
, 1);
1481 /* Register indirect. */
1486 /* Register indirect with displacement or index. */
1489 rtx op0
= XEXP (addr
, 0);
1490 rtx op1
= XEXP (addr
, 1);
1491 enum rtx_code code0
= GET_CODE (op0
);
1498 base
= op0
; /* Base + index. */
1500 if (IS_INDEX_REG (base
) || IS_ADDR_REG (indx
))
1508 base
= op0
; /* Base + displacement. */
1519 /* Direct addressing with DP register. */
1522 rtx op0
= XEXP (addr
, 0);
1523 rtx op1
= XEXP (addr
, 1);
1525 /* HImode and HFmode direct memory references aren't truly
1526 offsettable (consider case at end of data page). We
1527 probably get better code by loading a pointer and using an
1528 indirect memory reference. */
1529 if (mode
== HImode
|| mode
== HFmode
)
1532 if (!REG_P (op0
) || REGNO (op0
) != DP_REGNO
)
1535 if ((GET_CODE (op1
) == SYMBOL_REF
|| GET_CODE (op1
) == LABEL_REF
))
1538 if (GET_CODE (op1
) == CONST
)
1544 /* Direct addressing with some work for the assembler... */
1546 /* Direct addressing. */
1549 if (! TARGET_EXPOSE_LDP
&& ! strict
&& mode
!= HFmode
&& mode
!= HImode
)
1551 /* These need to be converted to a LO_SUM (...).
1552 LEGITIMIZE_RELOAD_ADDRESS will do this during reload. */
1555 /* Do not allow direct memory access to absolute addresses.
1556 This is more pain than it's worth, especially for the
1557 small memory model where we can't guarantee that
1558 this address is within the data page---we don't want
1559 to modify the DP register in the small memory model,
1560 even temporarily, since an interrupt can sneak in.... */
1564 /* Indirect indirect addressing. */
1569 fatal_insn ("using CONST_DOUBLE for address", addr
);
1575 /* Validate the base register. */
1578 /* Check that the address is offsettable for HImode and HFmode. */
1579 if (indx
&& (mode
== HImode
|| mode
== HFmode
))
1582 /* Handle DP based stuff. */
1583 if (REGNO (base
) == DP_REGNO
)
1585 if (strict
&& ! REGNO_OK_FOR_BASE_P (REGNO (base
)))
1587 else if (! strict
&& ! IS_ADDR_OR_PSEUDO_REG (base
))
1591 /* Now validate the index register. */
1594 if (GET_CODE (indx
) != REG
)
1596 if (strict
&& ! REGNO_OK_FOR_INDEX_P (REGNO (indx
)))
1598 else if (! strict
&& ! IS_INDEX_OR_PSEUDO_REG (indx
))
1602 /* Validate displacement. */
1605 if (GET_CODE (disp
) != CONST_INT
)
1607 if (mode
== HImode
|| mode
== HFmode
)
1609 /* The offset displacement must be legitimate. */
1610 if (! IS_DISP8_OFF_CONST (INTVAL (disp
)))
1615 if (! IS_DISP8_CONST (INTVAL (disp
)))
1618 /* Can't add an index with a disp. */
1627 c4x_legitimize_address (rtx orig ATTRIBUTE_UNUSED
,
1628 enum machine_mode mode ATTRIBUTE_UNUSED
)
1630 if (GET_CODE (orig
) == SYMBOL_REF
1631 || GET_CODE (orig
) == LABEL_REF
)
1633 if (mode
== HImode
|| mode
== HFmode
)
1635 /* We need to force the address into
1636 a register so that it is offsettable. */
1637 rtx addr_reg
= gen_reg_rtx (Pmode
);
1638 emit_move_insn (addr_reg
, orig
);
1643 rtx dp_reg
= gen_rtx_REG (Pmode
, DP_REGNO
);
1646 emit_insn (gen_set_ldp (dp_reg
, orig
));
1648 return gen_rtx_LO_SUM (Pmode
, dp_reg
, orig
);
1656 /* Provide the costs of an addressing mode that contains ADDR.
1657 If ADDR is not a valid address, its cost is irrelevant.
1658 This is used in cse and loop optimization to determine
1659 if it is worthwhile storing a common address into a register.
1660 Unfortunately, the C4x address cost depends on other operands. */
1663 c4x_address_cost (rtx addr
)
1665 switch (GET_CODE (addr
))
1676 /* These shouldn't be directly generated. */
1684 rtx op1
= XEXP (addr
, 1);
1686 if (GET_CODE (op1
) == LABEL_REF
|| GET_CODE (op1
) == SYMBOL_REF
)
1687 return TARGET_SMALL
? 3 : 4;
1689 if (GET_CODE (op1
) == CONST
)
1691 rtx offset
= const0_rtx
;
1693 op1
= eliminate_constant_term (op1
, &offset
);
1695 /* ??? These costs need rethinking... */
1696 if (GET_CODE (op1
) == LABEL_REF
)
1699 if (GET_CODE (op1
) != SYMBOL_REF
)
1702 if (INTVAL (offset
) == 0)
1707 fatal_insn ("c4x_address_cost: Invalid addressing mode", addr
);
1713 register rtx op0
= XEXP (addr
, 0);
1714 register rtx op1
= XEXP (addr
, 1);
1716 if (GET_CODE (op0
) != REG
)
1719 switch (GET_CODE (op1
))
1725 /* This cost for REG+REG must be greater than the cost
1726 for REG if we want autoincrement addressing modes. */
1730 /* The following tries to improve GIV combination
1731 in strength reduce but appears not to help. */
1732 if (TARGET_DEVEL
&& IS_UINT5_CONST (INTVAL (op1
)))
1735 if (IS_DISP1_CONST (INTVAL (op1
)))
1738 if (! TARGET_C3X
&& IS_UINT5_CONST (INTVAL (op1
)))
1753 c4x_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
1755 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
1758 if (mode
== CC_NOOVmode
1759 && (code
== LE
|| code
== GE
|| code
== LT
|| code
== GT
))
1762 cc_reg
= gen_rtx_REG (mode
, ST_REGNO
);
1763 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
1764 gen_rtx_COMPARE (mode
, x
, y
)));
1769 c4x_output_cbranch (const char *form
, rtx seq
)
1776 static char str
[100];
1780 delay
= XVECEXP (final_sequence
, 0, 1);
1781 delayed
= ! INSN_ANNULLED_BRANCH_P (seq
);
1782 annultrue
= INSN_ANNULLED_BRANCH_P (seq
) && ! INSN_FROM_TARGET_P (delay
);
1783 annulfalse
= INSN_ANNULLED_BRANCH_P (seq
) && INSN_FROM_TARGET_P (delay
);
1786 cp
= &str
[strlen (str
)];
1811 c4x_print_operand (FILE *file
, rtx op
, int letter
)
1818 case '#': /* Delayed. */
1820 fprintf (file
, "d");
1824 code
= GET_CODE (op
);
1827 case 'A': /* Direct address. */
1828 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== CONST
)
1829 fprintf (file
, "@");
1832 case 'H': /* Sethi. */
1833 output_addr_const (file
, op
);
1836 case 'I': /* Reversed condition. */
1837 code
= reverse_condition (code
);
1840 case 'L': /* Log 2 of constant. */
1841 if (code
!= CONST_INT
)
1842 fatal_insn ("c4x_print_operand: %%L inconsistency", op
);
1843 fprintf (file
, "%d", exact_log2 (INTVAL (op
)));
1846 case 'N': /* Ones complement of small constant. */
1847 if (code
!= CONST_INT
)
1848 fatal_insn ("c4x_print_operand: %%N inconsistency", op
);
1849 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~INTVAL (op
));
1852 case 'K': /* Generate ldp(k) if direct address. */
1855 && GET_CODE (XEXP (op
, 0)) == LO_SUM
1856 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == REG
1857 && REGNO (XEXP (XEXP (op
, 0), 0)) == DP_REGNO
)
1859 op1
= XEXP (XEXP (op
, 0), 1);
1860 if (GET_CODE(op1
) == CONST_INT
|| GET_CODE(op1
) == SYMBOL_REF
)
1862 fprintf (file
, "\t%s\t@", TARGET_C3X
? "ldp" : "ldpk");
1863 output_address (XEXP (adjust_address (op
, VOIDmode
, 1), 0));
1864 fprintf (file
, "\n");
1869 case 'M': /* Generate ldp(k) if direct address. */
1870 if (! TARGET_SMALL
/* Only used in asm statements. */
1872 && (GET_CODE (XEXP (op
, 0)) == CONST
1873 || GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
))
1875 fprintf (file
, "%s\t@", TARGET_C3X
? "ldp" : "ldpk");
1876 output_address (XEXP (op
, 0));
1877 fprintf (file
, "\n\t");
1881 case 'O': /* Offset address. */
1882 if (code
== MEM
&& c4x_autoinc_operand (op
, Pmode
))
1884 else if (code
== MEM
)
1885 output_address (XEXP (adjust_address (op
, VOIDmode
, 1), 0));
1886 else if (code
== REG
)
1887 fprintf (file
, "%s", reg_names
[REGNO (op
) + 1]);
1889 fatal_insn ("c4x_print_operand: %%O inconsistency", op
);
1892 case 'C': /* Call. */
1895 case 'U': /* Call/callu. */
1896 if (code
!= SYMBOL_REF
)
1897 fprintf (file
, "u");
1907 if (GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
1909 fprintf (file
, "%s", float_reg_names
[REGNO (op
)]);
1911 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
1915 output_address (XEXP (op
, 0));
1922 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (op
),
1923 sizeof (str
), 0, 1);
1924 fprintf (file
, "%s", str
);
1929 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
1933 fprintf (file
, "ne");
1937 fprintf (file
, "eq");
1941 fprintf (file
, "ge");
1945 fprintf (file
, "gt");
1949 fprintf (file
, "le");
1953 fprintf (file
, "lt");
1957 fprintf (file
, "hs");
1961 fprintf (file
, "hi");
1965 fprintf (file
, "ls");
1969 fprintf (file
, "lo");
1973 output_addr_const (file
, op
);
1977 output_addr_const (file
, XEXP (op
, 0));
1984 fatal_insn ("c4x_print_operand: Bad operand case", op
);
1991 c4x_print_operand_address (FILE *file
, rtx addr
)
1993 switch (GET_CODE (addr
))
1996 fprintf (file
, "*%s", reg_names
[REGNO (addr
)]);
2000 fprintf (file
, "*--%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2004 fprintf (file
, "*%s++", reg_names
[REGNO (XEXP (addr
, 0))]);
2009 rtx op0
= XEXP (XEXP (addr
, 1), 0);
2010 rtx op1
= XEXP (XEXP (addr
, 1), 1);
2012 if (GET_CODE (XEXP (addr
, 1)) == PLUS
&& REG_P (op1
))
2013 fprintf (file
, "*%s++(%s)", reg_names
[REGNO (op0
)],
2014 reg_names
[REGNO (op1
)]);
2015 else if (GET_CODE (XEXP (addr
, 1)) == PLUS
&& INTVAL (op1
) > 0)
2016 fprintf (file
, "*%s++(" HOST_WIDE_INT_PRINT_DEC
")",
2017 reg_names
[REGNO (op0
)], INTVAL (op1
));
2018 else if (GET_CODE (XEXP (addr
, 1)) == PLUS
&& INTVAL (op1
) < 0)
2019 fprintf (file
, "*%s--(" HOST_WIDE_INT_PRINT_DEC
")",
2020 reg_names
[REGNO (op0
)], -INTVAL (op1
));
2021 else if (GET_CODE (XEXP (addr
, 1)) == MINUS
&& REG_P (op1
))
2022 fprintf (file
, "*%s--(%s)", reg_names
[REGNO (op0
)],
2023 reg_names
[REGNO (op1
)]);
2025 fatal_insn ("c4x_print_operand_address: Bad post_modify", addr
);
2031 rtx op0
= XEXP (XEXP (addr
, 1), 0);
2032 rtx op1
= XEXP (XEXP (addr
, 1), 1);
2034 if (GET_CODE (XEXP (addr
, 1)) == PLUS
&& REG_P (op1
))
2035 fprintf (file
, "*++%s(%s)", reg_names
[REGNO (op0
)],
2036 reg_names
[REGNO (op1
)]);
2037 else if (GET_CODE (XEXP (addr
, 1)) == PLUS
&& INTVAL (op1
) > 0)
2038 fprintf (file
, "*++%s(" HOST_WIDE_INT_PRINT_DEC
")",
2039 reg_names
[REGNO (op0
)], INTVAL (op1
));
2040 else if (GET_CODE (XEXP (addr
, 1)) == PLUS
&& INTVAL (op1
) < 0)
2041 fprintf (file
, "*--%s(" HOST_WIDE_INT_PRINT_DEC
")",
2042 reg_names
[REGNO (op0
)], -INTVAL (op1
));
2043 else if (GET_CODE (XEXP (addr
, 1)) == MINUS
&& REG_P (op1
))
2044 fprintf (file
, "*--%s(%s)", reg_names
[REGNO (op0
)],
2045 reg_names
[REGNO (op1
)]);
2047 fatal_insn ("c4x_print_operand_address: Bad pre_modify", addr
);
2052 fprintf (file
, "*++%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2056 fprintf (file
, "*%s--", reg_names
[REGNO (XEXP (addr
, 0))]);
2059 case PLUS
: /* Indirect with displacement. */
2061 rtx op0
= XEXP (addr
, 0);
2062 rtx op1
= XEXP (addr
, 1);
2068 if (IS_INDEX_REG (op0
))
2070 fprintf (file
, "*+%s(%s)",
2071 reg_names
[REGNO (op1
)],
2072 reg_names
[REGNO (op0
)]); /* Index + base. */
2076 fprintf (file
, "*+%s(%s)",
2077 reg_names
[REGNO (op0
)],
2078 reg_names
[REGNO (op1
)]); /* Base + index. */
2081 else if (INTVAL (op1
) < 0)
2083 fprintf (file
, "*-%s(" HOST_WIDE_INT_PRINT_DEC
")",
2084 reg_names
[REGNO (op0
)],
2085 -INTVAL (op1
)); /* Base - displacement. */
2089 fprintf (file
, "*+%s(" HOST_WIDE_INT_PRINT_DEC
")",
2090 reg_names
[REGNO (op0
)],
2091 INTVAL (op1
)); /* Base + displacement. */
2095 fatal_insn ("c4x_print_operand_address: Bad operand case", addr
);
2101 rtx op0
= XEXP (addr
, 0);
2102 rtx op1
= XEXP (addr
, 1);
2104 if (REG_P (op0
) && REGNO (op0
) == DP_REGNO
)
2105 c4x_print_operand_address (file
, op1
);
2107 fatal_insn ("c4x_print_operand_address: Bad operand case", addr
);
2114 fprintf (file
, "@");
2115 output_addr_const (file
, addr
);
2118 /* We shouldn't access CONST_INT addresses. */
2122 fatal_insn ("c4x_print_operand_address: Bad operand case", addr
);
2128 /* Return nonzero if the floating point operand will fit
2129 in the immediate field. */
2132 c4x_immed_float_p (rtx op
)
2138 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2139 if (GET_MODE (op
) == HFmode
)
2140 REAL_VALUE_TO_TARGET_DOUBLE (r
, convval
);
2143 REAL_VALUE_TO_TARGET_SINGLE (r
, convval
[0]);
2147 /* Sign extend exponent. */
2148 exponent
= (((convval
[0] >> 24) & 0xff) ^ 0x80) - 0x80;
2149 if (exponent
== -128)
2151 if ((convval
[0] & 0x00000fff) != 0 || convval
[1] != 0)
2152 return 0; /* Precision doesn't fit. */
2153 return (exponent
<= 7) /* Positive exp. */
2154 && (exponent
>= -7); /* Negative exp. */
2158 /* The last instruction in a repeat block cannot be a Bcond, DBcound,
2159 CALL, CALLCond, TRAPcond, RETIcond, RETScond, IDLE, RPTB or RPTS.
2161 None of the last four instructions from the bottom of the block can
2162 be a BcondD, BRD, DBcondD, RPTBD, LAJ, LAJcond, LATcond, BcondAF,
2163 BcondAT or RETIcondD.
2165 This routine scans the four previous insns for a jump insn, and if
2166 one is found, returns 1 so that we bung in a nop instruction.
2167 This simple minded strategy will add a nop, when it may not
2168 be required. Say when there is a JUMP_INSN near the end of the
2169 block that doesn't get converted into a delayed branch.
2171 Note that we cannot have a call insn, since we don't generate
2172 repeat loops with calls in them (although I suppose we could, but
2173 there's no benefit.)
2175 !!! FIXME. The rptb_top insn may be sucked into a SEQUENCE. */
2178 c4x_rptb_nop_p (rtx insn
)
2183 /* Extract the start label from the jump pattern (rptb_end). */
2184 start_label
= XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn
), 0, 0)), 1), 0);
2186 /* If there is a label at the end of the loop we must insert
2189 insn
= previous_insn (insn
);
2190 } while (GET_CODE (insn
) == NOTE
2191 || GET_CODE (insn
) == USE
2192 || GET_CODE (insn
) == CLOBBER
);
2193 if (GET_CODE (insn
) == CODE_LABEL
)
2196 for (i
= 0; i
< 4; i
++)
2198 /* Search back for prev non-note and non-label insn. */
2199 while (GET_CODE (insn
) == NOTE
|| GET_CODE (insn
) == CODE_LABEL
2200 || GET_CODE (insn
) == USE
|| GET_CODE (insn
) == CLOBBER
)
2202 if (insn
== start_label
)
2205 insn
= previous_insn (insn
);
2208 /* If we have a jump instruction we should insert a NOP. If we
2209 hit repeat block top we should only insert a NOP if the loop
2211 if (GET_CODE (insn
) == JUMP_INSN
)
2213 insn
= previous_insn (insn
);
2219 /* The C4x looping instruction needs to be emitted at the top of the
2220 loop. Emitting the true RTL for a looping instruction at the top of
2221 the loop can cause problems with flow analysis. So instead, a dummy
2222 doloop insn is emitted at the end of the loop. This routine checks
2223 for the presence of this doloop insn and then searches back to the
2224 top of the loop, where it inserts the true looping insn (provided
2225 there are no instructions in the loop which would cause problems).
2226 Any additional labels can be emitted at this point. In addition, if
2227 the desired loop count register was not allocated, this routine does
2230 Before we can create a repeat block looping instruction we have to
2231 verify that there are no jumps outside the loop and no jumps outside
2232 the loop go into this loop. This can happen in the basic blocks reorder
2233 pass. The C4x cpu can not handle this. */
2236 c4x_label_ref_used_p (rtx x
, rtx code_label
)
2245 code
= GET_CODE (x
);
2246 if (code
== LABEL_REF
)
2247 return INSN_UID (XEXP (x
,0)) == INSN_UID (code_label
);
2249 fmt
= GET_RTX_FORMAT (code
);
2250 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2254 if (c4x_label_ref_used_p (XEXP (x
, i
), code_label
))
2257 else if (fmt
[i
] == 'E')
2258 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2259 if (c4x_label_ref_used_p (XVECEXP (x
, i
, j
), code_label
))
2267 c4x_rptb_valid_p (rtx insn
, rtx start_label
)
2273 /* Find the start label. */
2274 for (; insn
; insn
= PREV_INSN (insn
))
2275 if (insn
== start_label
)
2278 /* Note found then we can not use a rptb or rpts. The label was
2279 probably moved by the basic block reorder pass. */
2284 /* If any jump jumps inside this block then we must fail. */
2285 for (insn
= PREV_INSN (start
); insn
; insn
= PREV_INSN (insn
))
2287 if (GET_CODE (insn
) == CODE_LABEL
)
2289 for (tmp
= NEXT_INSN (start
); tmp
!= end
; tmp
= NEXT_INSN(tmp
))
2290 if (GET_CODE (tmp
) == JUMP_INSN
2291 && c4x_label_ref_used_p (tmp
, insn
))
2295 for (insn
= NEXT_INSN (end
); insn
; insn
= NEXT_INSN (insn
))
2297 if (GET_CODE (insn
) == CODE_LABEL
)
2299 for (tmp
= NEXT_INSN (start
); tmp
!= end
; tmp
= NEXT_INSN(tmp
))
2300 if (GET_CODE (tmp
) == JUMP_INSN
2301 && c4x_label_ref_used_p (tmp
, insn
))
2305 /* If any jump jumps outside this block then we must fail. */
2306 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
2308 if (GET_CODE (insn
) == CODE_LABEL
)
2310 for (tmp
= NEXT_INSN (end
); tmp
; tmp
= NEXT_INSN(tmp
))
2311 if (GET_CODE (tmp
) == JUMP_INSN
2312 && c4x_label_ref_used_p (tmp
, insn
))
2314 for (tmp
= PREV_INSN (start
); tmp
; tmp
= PREV_INSN(tmp
))
2315 if (GET_CODE (tmp
) == JUMP_INSN
2316 && c4x_label_ref_used_p (tmp
, insn
))
2321 /* All checks OK. */
2327 c4x_rptb_insert (rtx insn
)
2331 rtx new_start_label
;
2334 /* If the count register has not been allocated to RC, say if
2335 there is a movstr pattern in the loop, then do not insert a
2336 RPTB instruction. Instead we emit a decrement and branch
2337 at the end of the loop. */
2338 count_reg
= XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn
), 0, 0)), 0), 0);
2339 if (REGNO (count_reg
) != RC_REGNO
)
2342 /* Extract the start label from the jump pattern (rptb_end). */
2343 start_label
= XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn
), 0, 0)), 1), 0);
2345 if (! c4x_rptb_valid_p (insn
, start_label
))
2347 /* We can not use the rptb insn. Replace it so reorg can use
2348 the delay slots of the jump insn. */
2349 emit_insn_before (gen_addqi3 (count_reg
, count_reg
, GEN_INT (-1)), insn
);
2350 emit_insn_before (gen_cmpqi (count_reg
, GEN_INT (0)), insn
);
2351 emit_insn_before (gen_bge (start_label
), insn
);
2352 LABEL_NUSES (start_label
)++;
2357 end_label
= gen_label_rtx ();
2358 LABEL_NUSES (end_label
)++;
2359 emit_label_after (end_label
, insn
);
2361 new_start_label
= gen_label_rtx ();
2362 LABEL_NUSES (new_start_label
)++;
2364 for (; insn
; insn
= PREV_INSN (insn
))
2366 if (insn
== start_label
)
2368 if (GET_CODE (insn
) == JUMP_INSN
&&
2369 JUMP_LABEL (insn
) == start_label
)
2370 redirect_jump (insn
, new_start_label
, 0);
2373 fatal_insn ("c4x_rptb_insert: Cannot find start label", start_label
);
2375 emit_label_after (new_start_label
, insn
);
2377 if (TARGET_RPTS
&& c4x_rptb_rpts_p (PREV_INSN (insn
), 0))
2378 emit_insn_after (gen_rpts_top (new_start_label
, end_label
), insn
);
2380 emit_insn_after (gen_rptb_top (new_start_label
, end_label
), insn
);
2381 if (LABEL_NUSES (start_label
) == 0)
2382 delete_insn (start_label
);
2386 /* We need to use direct addressing for large constants and addresses
2387 that cannot fit within an instruction. We must check for these
2388 after after the final jump optimization pass, since this may
2389 introduce a local_move insn for a SYMBOL_REF. This pass
2390 must come before delayed branch slot filling since it can generate
2391 additional instructions.
2393 This function also fixes up RTPB style loops that didn't get RC
2394 allocated as the loop counter. */
2401 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
2403 /* Look for insn. */
2406 int insn_code_number
;
2409 insn_code_number
= recog_memoized (insn
);
2411 if (insn_code_number
< 0)
2414 /* Insert the RTX for RPTB at the top of the loop
2415 and a label at the end of the loop. */
2416 if (insn_code_number
== CODE_FOR_rptb_end
)
2417 c4x_rptb_insert(insn
);
2419 /* We need to split the insn here. Otherwise the calls to
2420 force_const_mem will not work for load_immed_address. */
2423 /* Don't split the insn if it has been deleted. */
2424 if (! INSN_DELETED_P (old
))
2425 insn
= try_split (PATTERN(old
), old
, 1);
2427 /* When not optimizing, the old insn will be still left around
2428 with only the 'deleted' bit set. Transform it into a note
2429 to avoid confusion of subsequent processing. */
2430 if (INSN_DELETED_P (old
))
2432 PUT_CODE (old
, NOTE
);
2433 NOTE_LINE_NUMBER (old
) = NOTE_INSN_DELETED
;
2434 NOTE_SOURCE_FILE (old
) = 0;
2442 c4x_a_register (rtx op
)
2444 return REG_P (op
) && IS_ADDR_OR_PSEUDO_REG (op
);
2449 c4x_x_register (rtx op
)
2451 return REG_P (op
) && IS_INDEX_OR_PSEUDO_REG (op
);
2456 c4x_immed_int_constant (rtx op
)
2458 if (GET_CODE (op
) != CONST_INT
)
2461 return GET_MODE (op
) == VOIDmode
2462 || GET_MODE_CLASS (GET_MODE (op
)) == MODE_INT
2463 || GET_MODE_CLASS (GET_MODE (op
)) == MODE_PARTIAL_INT
;
2468 c4x_immed_float_constant (rtx op
)
2470 if (GET_CODE (op
) != CONST_DOUBLE
)
2473 /* Do not check if the CONST_DOUBLE is in memory. If there is a MEM
2474 present this only means that a MEM rtx has been generated. It does
2475 not mean the rtx is really in memory. */
2477 return GET_MODE (op
) == QFmode
|| GET_MODE (op
) == HFmode
;
2482 c4x_shiftable_constant (rtx op
)
2486 int val
= INTVAL (op
);
2488 for (i
= 0; i
< 16; i
++)
2493 mask
= ((0xffff >> i
) << 16) | 0xffff;
2494 if (IS_INT16_CONST (val
& (1 << 31) ? (val
>> i
) | ~mask
2495 : (val
>> i
) & mask
))
2502 c4x_H_constant (rtx op
)
2504 return c4x_immed_float_constant (op
) && c4x_immed_float_p (op
);
2509 c4x_I_constant (rtx op
)
2511 return c4x_immed_int_constant (op
) && IS_INT16_CONST (INTVAL (op
));
2516 c4x_J_constant (rtx op
)
2520 return c4x_immed_int_constant (op
) && IS_INT8_CONST (INTVAL (op
));
2525 c4x_K_constant (rtx op
)
2527 if (TARGET_C3X
|| ! c4x_immed_int_constant (op
))
2529 return IS_INT5_CONST (INTVAL (op
));
2534 c4x_L_constant (rtx op
)
2536 return c4x_immed_int_constant (op
) && IS_UINT16_CONST (INTVAL (op
));
2541 c4x_N_constant (rtx op
)
2543 return c4x_immed_int_constant (op
) && IS_NOT_UINT16_CONST (INTVAL (op
));
2548 c4x_O_constant (rtx op
)
2550 return c4x_immed_int_constant (op
) && IS_HIGH_CONST (INTVAL (op
));
2554 /* The constraints do not have to check the register class,
2555 except when needed to discriminate between the constraints.
2556 The operand has been checked by the predicates to be valid. */
2558 /* ARx + 9-bit signed const or IRn
2559 *ARx, *+ARx(n), *-ARx(n), *+ARx(IRn), *-Arx(IRn) for -256 < n < 256
2560 We don't include the pre/post inc/dec forms here since
2561 they are handled by the <> constraints. */
2564 c4x_Q_constraint (rtx op
)
2566 enum machine_mode mode
= GET_MODE (op
);
2568 if (GET_CODE (op
) != MEM
)
2571 switch (GET_CODE (op
))
2578 rtx op0
= XEXP (op
, 0);
2579 rtx op1
= XEXP (op
, 1);
2587 if (GET_CODE (op1
) != CONST_INT
)
2590 /* HImode and HFmode must be offsettable. */
2591 if (mode
== HImode
|| mode
== HFmode
)
2592 return IS_DISP8_OFF_CONST (INTVAL (op1
));
2594 return IS_DISP8_CONST (INTVAL (op1
));
2605 /* ARx + 5-bit unsigned const
2606 *ARx, *+ARx(n) for n < 32. */
2609 c4x_R_constraint (rtx op
)
2611 enum machine_mode mode
= GET_MODE (op
);
2615 if (GET_CODE (op
) != MEM
)
2618 switch (GET_CODE (op
))
2625 rtx op0
= XEXP (op
, 0);
2626 rtx op1
= XEXP (op
, 1);
2631 if (GET_CODE (op1
) != CONST_INT
)
2634 /* HImode and HFmode must be offsettable. */
2635 if (mode
== HImode
|| mode
== HFmode
)
2636 return IS_UINT5_CONST (INTVAL (op1
) + 1);
2638 return IS_UINT5_CONST (INTVAL (op1
));
2650 c4x_R_indirect (rtx op
)
2652 enum machine_mode mode
= GET_MODE (op
);
2654 if (TARGET_C3X
|| GET_CODE (op
) != MEM
)
2658 switch (GET_CODE (op
))
2661 return IS_ADDR_OR_PSEUDO_REG (op
);
2665 rtx op0
= XEXP (op
, 0);
2666 rtx op1
= XEXP (op
, 1);
2668 /* HImode and HFmode must be offsettable. */
2669 if (mode
== HImode
|| mode
== HFmode
)
2670 return IS_ADDR_OR_PSEUDO_REG (op0
)
2671 && GET_CODE (op1
) == CONST_INT
2672 && IS_UINT5_CONST (INTVAL (op1
) + 1);
2675 && IS_ADDR_OR_PSEUDO_REG (op0
)
2676 && GET_CODE (op1
) == CONST_INT
2677 && IS_UINT5_CONST (INTVAL (op1
));
2688 /* ARx + 1-bit unsigned const or IRn
2689 *ARx, *+ARx(1), *-ARx(1), *+ARx(IRn), *-Arx(IRn)
2690 We don't include the pre/post inc/dec forms here since
2691 they are handled by the <> constraints. */
2694 c4x_S_constraint (rtx op
)
2696 enum machine_mode mode
= GET_MODE (op
);
2697 if (GET_CODE (op
) != MEM
)
2700 switch (GET_CODE (op
))
2708 rtx op0
= XEXP (op
, 0);
2709 rtx op1
= XEXP (op
, 1);
2711 if ((GET_CODE (op1
) != PLUS
&& GET_CODE (op1
) != MINUS
)
2712 || (op0
!= XEXP (op1
, 0)))
2715 op0
= XEXP (op1
, 0);
2716 op1
= XEXP (op1
, 1);
2717 return REG_P (op0
) && REG_P (op1
);
2718 /* Pre or post_modify with a displacement of 0 or 1
2719 should not be generated. */
2725 rtx op0
= XEXP (op
, 0);
2726 rtx op1
= XEXP (op
, 1);
2734 if (GET_CODE (op1
) != CONST_INT
)
2737 /* HImode and HFmode must be offsettable. */
2738 if (mode
== HImode
|| mode
== HFmode
)
2739 return IS_DISP1_OFF_CONST (INTVAL (op1
));
2741 return IS_DISP1_CONST (INTVAL (op1
));
2753 c4x_S_indirect (rtx op
)
2755 enum machine_mode mode
= GET_MODE (op
);
2756 if (GET_CODE (op
) != MEM
)
2760 switch (GET_CODE (op
))
2764 if (mode
!= QImode
&& mode
!= QFmode
)
2771 return IS_ADDR_OR_PSEUDO_REG (op
);
2776 rtx op0
= XEXP (op
, 0);
2777 rtx op1
= XEXP (op
, 1);
2779 if (mode
!= QImode
&& mode
!= QFmode
)
2782 if ((GET_CODE (op1
) != PLUS
&& GET_CODE (op1
) != MINUS
)
2783 || (op0
!= XEXP (op1
, 0)))
2786 op0
= XEXP (op1
, 0);
2787 op1
= XEXP (op1
, 1);
2788 return REG_P (op0
) && IS_ADDR_OR_PSEUDO_REG (op0
)
2789 && REG_P (op1
) && IS_INDEX_OR_PSEUDO_REG (op1
);
2790 /* Pre or post_modify with a displacement of 0 or 1
2791 should not be generated. */
2796 rtx op0
= XEXP (op
, 0);
2797 rtx op1
= XEXP (op
, 1);
2801 /* HImode and HFmode must be offsettable. */
2802 if (mode
== HImode
|| mode
== HFmode
)
2803 return IS_ADDR_OR_PSEUDO_REG (op0
)
2804 && GET_CODE (op1
) == CONST_INT
2805 && IS_DISP1_OFF_CONST (INTVAL (op1
));
2808 return (IS_INDEX_OR_PSEUDO_REG (op1
)
2809 && IS_ADDR_OR_PSEUDO_REG (op0
))
2810 || (IS_ADDR_OR_PSEUDO_REG (op1
)
2811 && IS_INDEX_OR_PSEUDO_REG (op0
));
2813 return IS_ADDR_OR_PSEUDO_REG (op0
)
2814 && GET_CODE (op1
) == CONST_INT
2815 && IS_DISP1_CONST (INTVAL (op1
));
2827 /* Direct memory operand. */
2830 c4x_T_constraint (rtx op
)
2832 if (GET_CODE (op
) != MEM
)
2836 if (GET_CODE (op
) != LO_SUM
)
2838 /* Allow call operands. */
2839 return GET_CODE (op
) == SYMBOL_REF
2840 && GET_MODE (op
) == Pmode
2841 && SYMBOL_REF_FUNCTION_P (op
);
2844 /* HImode and HFmode are not offsettable. */
2845 if (GET_MODE (op
) == HImode
|| GET_CODE (op
) == HFmode
)
2848 if ((GET_CODE (XEXP (op
, 0)) == REG
)
2849 && (REGNO (XEXP (op
, 0)) == DP_REGNO
))
2850 return c4x_U_constraint (XEXP (op
, 1));
2856 /* Symbolic operand. */
2859 c4x_U_constraint (rtx op
)
2861 /* Don't allow direct addressing to an arbitrary constant. */
2862 return GET_CODE (op
) == CONST
2863 || GET_CODE (op
) == SYMBOL_REF
2864 || GET_CODE (op
) == LABEL_REF
;
2869 c4x_autoinc_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2871 if (GET_CODE (op
) == MEM
)
2873 enum rtx_code code
= GET_CODE (XEXP (op
, 0));
2879 || code
== PRE_MODIFY
2880 || code
== POST_MODIFY
2888 /* Match any operand. */
2891 any_operand (register rtx op ATTRIBUTE_UNUSED
,
2892 enum machine_mode mode ATTRIBUTE_UNUSED
)
2898 /* Nonzero if OP is a floating point value with value 0.0. */
2901 fp_zero_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2905 if (GET_CODE (op
) != CONST_DOUBLE
)
2907 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2908 return REAL_VALUES_EQUAL (r
, dconst0
);
2913 const_operand (register rtx op
, register enum machine_mode mode
)
2919 if (GET_CODE (op
) != CONST_DOUBLE
2920 || GET_MODE (op
) != mode
2921 || GET_MODE_CLASS (mode
) != MODE_FLOAT
)
2924 return c4x_immed_float_p (op
);
2930 if (GET_CODE (op
) == CONSTANT_P_RTX
)
2933 if (GET_CODE (op
) != CONST_INT
2934 || (GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != mode
)
2935 || GET_MODE_CLASS (mode
) != MODE_INT
)
2938 return IS_HIGH_CONST (INTVAL (op
)) || IS_INT16_CONST (INTVAL (op
));
2950 stik_const_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2952 return c4x_K_constant (op
);
2957 not_const_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2959 return c4x_N_constant (op
);
2964 reg_operand (rtx op
, enum machine_mode mode
)
2966 if (GET_CODE (op
) == SUBREG
2967 && GET_MODE (op
) == QFmode
)
2969 return register_operand (op
, mode
);
2974 mixed_subreg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2976 /* Allow (subreg:HF (reg:HI)) that be generated for a union of an
2977 int and a long double. */
2978 if (GET_CODE (op
) == SUBREG
2979 && (GET_MODE (op
) == QFmode
)
2980 && (GET_MODE (SUBREG_REG (op
)) == QImode
2981 || GET_MODE (SUBREG_REG (op
)) == HImode
))
2988 reg_imm_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2990 if (REG_P (op
) || CONSTANT_P (op
))
2997 not_modify_reg (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2999 if (REG_P (op
) || CONSTANT_P (op
))
3001 if (GET_CODE (op
) != MEM
)
3004 switch (GET_CODE (op
))
3011 rtx op0
= XEXP (op
, 0);
3012 rtx op1
= XEXP (op
, 1);
3017 if (REG_P (op1
) || GET_CODE (op1
) == CONST_INT
)
3023 rtx op0
= XEXP (op
, 0);
3025 if (REG_P (op0
) && REGNO (op0
) == DP_REGNO
)
3043 not_rc_reg (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3045 if (REG_P (op
) && REGNO (op
) == RC_REGNO
)
3051 /* Extended precision register R0-R1. */
3054 r0r1_reg_operand (rtx op
, enum machine_mode mode
)
3056 if (! reg_operand (op
, mode
))
3058 if (GET_CODE (op
) == SUBREG
)
3059 op
= SUBREG_REG (op
);
3060 return REG_P (op
) && IS_R0R1_OR_PSEUDO_REG (op
);
3064 /* Extended precision register R2-R3. */
3067 r2r3_reg_operand (rtx op
, enum machine_mode mode
)
3069 if (! reg_operand (op
, mode
))
3071 if (GET_CODE (op
) == SUBREG
)
3072 op
= SUBREG_REG (op
);
3073 return REG_P (op
) && IS_R2R3_OR_PSEUDO_REG (op
);
3077 /* Low extended precision register R0-R7. */
3080 ext_low_reg_operand (rtx op
, enum machine_mode mode
)
3082 if (! reg_operand (op
, mode
))
3084 if (GET_CODE (op
) == SUBREG
)
3085 op
= SUBREG_REG (op
);
3086 return REG_P (op
) && IS_EXT_LOW_OR_PSEUDO_REG (op
);
3090 /* Extended precision register. */
3093 ext_reg_operand (rtx op
, enum machine_mode mode
)
3095 if (! reg_operand (op
, mode
))
3097 if (GET_CODE (op
) == SUBREG
)
3098 op
= SUBREG_REG (op
);
3101 return IS_EXT_OR_PSEUDO_REG (op
);
3105 /* Standard precision register. */
3108 std_reg_operand (rtx op
, enum machine_mode mode
)
3110 if (! reg_operand (op
, mode
))
3112 if (GET_CODE (op
) == SUBREG
)
3113 op
= SUBREG_REG (op
);
3114 return REG_P (op
) && IS_STD_OR_PSEUDO_REG (op
);
3117 /* Standard precision or normal register. */
3120 std_or_reg_operand (rtx op
, enum machine_mode mode
)
3122 if (reload_in_progress
)
3123 return std_reg_operand (op
, mode
);
3124 return reg_operand (op
, mode
);
3127 /* Address register. */
3130 addr_reg_operand (rtx op
, enum machine_mode mode
)
3132 if (! reg_operand (op
, mode
))
3134 return c4x_a_register (op
);
3138 /* Index register. */
3141 index_reg_operand (rtx op
, enum machine_mode mode
)
3143 if (! reg_operand (op
, mode
))
3145 if (GET_CODE (op
) == SUBREG
)
3146 op
= SUBREG_REG (op
);
3147 return c4x_x_register (op
);
3154 dp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3156 return REG_P (op
) && IS_DP_OR_PSEUDO_REG (op
);
3163 sp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3165 return REG_P (op
) && IS_SP_OR_PSEUDO_REG (op
);
3172 st_reg_operand (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3174 return REG_P (op
) && IS_ST_OR_PSEUDO_REG (op
);
3181 rc_reg_operand (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3183 return REG_P (op
) && IS_RC_OR_PSEUDO_REG (op
);
3188 call_address_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3190 return (REG_P (op
) || symbolic_address_operand (op
, mode
));
3194 /* Symbolic address operand. */
3197 symbolic_address_operand (register rtx op
,
3198 enum machine_mode mode ATTRIBUTE_UNUSED
)
3200 switch (GET_CODE (op
))
3212 /* Check dst operand of a move instruction. */
3215 dst_operand (rtx op
, enum machine_mode mode
)
3217 if (GET_CODE (op
) == SUBREG
3218 && mixed_subreg_operand (op
, mode
))
3222 return reg_operand (op
, mode
);
3224 return nonimmediate_operand (op
, mode
);
3228 /* Check src operand of two operand arithmetic instructions. */
3231 src_operand (rtx op
, enum machine_mode mode
)
3233 if (GET_CODE (op
) == SUBREG
3234 && mixed_subreg_operand (op
, mode
))
3238 return reg_operand (op
, mode
);
3240 if (mode
== VOIDmode
)
3241 mode
= GET_MODE (op
);
3243 if (GET_CODE (op
) == CONST_INT
)
3244 return (mode
== QImode
|| mode
== Pmode
|| mode
== HImode
)
3245 && c4x_I_constant (op
);
3247 /* We don't like CONST_DOUBLE integers. */
3248 if (GET_CODE (op
) == CONST_DOUBLE
)
3249 return c4x_H_constant (op
);
3251 /* Disallow symbolic addresses. Only the predicate
3252 symbolic_address_operand will match these. */
3253 if (GET_CODE (op
) == SYMBOL_REF
3254 || GET_CODE (op
) == LABEL_REF
3255 || GET_CODE (op
) == CONST
)
3258 /* If TARGET_LOAD_DIRECT_MEMS is nonzero, disallow direct memory
3259 access to symbolic addresses. These operands will get forced
3260 into a register and the movqi expander will generate a
3261 HIGH/LO_SUM pair if TARGET_EXPOSE_LDP is nonzero. */
3262 if (GET_CODE (op
) == MEM
3263 && ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3264 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3265 || GET_CODE (XEXP (op
, 0)) == CONST
)))
3266 return ! TARGET_LOAD_DIRECT_MEMS
&& GET_MODE (op
) == mode
;
3268 return general_operand (op
, mode
);
3273 src_hi_operand (rtx op
, enum machine_mode mode
)
3275 if (c4x_O_constant (op
))
3277 return src_operand (op
, mode
);
3281 /* Check src operand of two operand logical instructions. */
3284 lsrc_operand (rtx op
, enum machine_mode mode
)
3286 if (mode
== VOIDmode
)
3287 mode
= GET_MODE (op
);
3289 if (mode
!= QImode
&& mode
!= Pmode
)
3290 fatal_insn ("mode not QImode", op
);
3292 if (GET_CODE (op
) == CONST_INT
)
3293 return c4x_L_constant (op
) || c4x_J_constant (op
);
3295 return src_operand (op
, mode
);
3299 /* Check src operand of two operand tricky instructions. */
3302 tsrc_operand (rtx op
, enum machine_mode mode
)
3304 if (mode
== VOIDmode
)
3305 mode
= GET_MODE (op
);
3307 if (mode
!= QImode
&& mode
!= Pmode
)
3308 fatal_insn ("mode not QImode", op
);
3310 if (GET_CODE (op
) == CONST_INT
)
3311 return c4x_L_constant (op
) || c4x_N_constant (op
) || c4x_J_constant (op
);
3313 return src_operand (op
, mode
);
3317 /* Check src operand of two operand non immedidate instructions. */
3320 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3322 if (GET_CODE (op
) == CONST_INT
|| GET_CODE (op
) == CONST_DOUBLE
)
3325 return src_operand (op
, mode
);
3329 /* Check logical src operand of two operand non immedidate instructions. */
3332 nonimmediate_lsrc_operand (rtx op
, enum machine_mode mode
)
3334 if (GET_CODE (op
) == CONST_INT
|| GET_CODE (op
) == CONST_DOUBLE
)
3337 return lsrc_operand (op
, mode
);
3342 reg_or_const_operand (rtx op
, enum machine_mode mode
)
3344 return reg_operand (op
, mode
) || const_operand (op
, mode
);
3348 /* Check for indirect operands allowable in parallel instruction. */
3351 par_ind_operand (rtx op
, enum machine_mode mode
)
3353 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
3356 return c4x_S_indirect (op
);
3360 /* Check for operands allowable in parallel instruction. */
3363 parallel_operand (rtx op
, enum machine_mode mode
)
3365 return ext_low_reg_operand (op
, mode
) || par_ind_operand (op
, mode
);
3370 c4x_S_address_parse (rtx op
, int *base
, int *incdec
, int *index
, int *disp
)
3377 if (GET_CODE (op
) != MEM
)
3378 fatal_insn ("invalid indirect memory address", op
);
3381 switch (GET_CODE (op
))
3384 *base
= REGNO (XEXP (op
, 0));
3390 *base
= REGNO (XEXP (op
, 0));
3396 *base
= REGNO (XEXP (op
, 0));
3402 *base
= REGNO (XEXP (op
, 0));
3408 *base
= REGNO (XEXP (op
, 0));
3409 if (REG_P (XEXP (XEXP (op
, 1), 1)))
3411 *index
= REGNO (XEXP (XEXP (op
, 1), 1));
3412 *disp
= 0; /* ??? */
3415 *disp
= INTVAL (XEXP (XEXP (op
, 1), 1));
3420 *base
= REGNO (XEXP (op
, 0));
3421 if (REG_P (XEXP (XEXP (op
, 1), 1)))
3423 *index
= REGNO (XEXP (XEXP (op
, 1), 1));
3424 *disp
= 1; /* ??? */
3427 *disp
= INTVAL (XEXP (XEXP (op
, 1), 1));
3438 rtx op0
= XEXP (op
, 0);
3439 rtx op1
= XEXP (op
, 1);
3441 if (c4x_a_register (op0
))
3443 if (c4x_x_register (op1
))
3445 *base
= REGNO (op0
);
3446 *index
= REGNO (op1
);
3449 else if ((GET_CODE (op1
) == CONST_INT
3450 && IS_DISP1_CONST (INTVAL (op1
))))
3452 *base
= REGNO (op0
);
3453 *disp
= INTVAL (op1
);
3457 else if (c4x_x_register (op0
) && c4x_a_register (op1
))
3459 *base
= REGNO (op1
);
3460 *index
= REGNO (op0
);
3467 fatal_insn ("invalid indirect (S) memory address", op
);
3473 c4x_address_conflict (rtx op0
, rtx op1
, int store0
, int store1
)
3484 if (MEM_VOLATILE_P (op0
) && MEM_VOLATILE_P (op1
))
3487 c4x_S_address_parse (op0
, &base0
, &incdec0
, &index0
, &disp0
);
3488 c4x_S_address_parse (op1
, &base1
, &incdec1
, &index1
, &disp1
);
3490 if (store0
&& store1
)
3492 /* If we have two stores in parallel to the same address, then
3493 the C4x only executes one of the stores. This is unlikely to
3494 cause problems except when writing to a hardware device such
3495 as a FIFO since the second write will be lost. The user
3496 should flag the hardware location as being volatile so that
3497 we don't do this optimization. While it is unlikely that we
3498 have an aliased address if both locations are not marked
3499 volatile, it is probably safer to flag a potential conflict
3500 if either location is volatile. */
3501 if (! flag_argument_noalias
)
3503 if (MEM_VOLATILE_P (op0
) || MEM_VOLATILE_P (op1
))
3508 /* If have a parallel load and a store to the same address, the load
3509 is performed first, so there is no conflict. Similarly, there is
3510 no conflict if have parallel loads from the same address. */
3512 /* Cannot use auto increment or auto decrement twice for same
3514 if (base0
== base1
&& incdec0
&& incdec0
)
3517 /* It might be too confusing for GCC if we have use a base register
3518 with a side effect and a memory reference using the same register
3520 if (! TARGET_DEVEL
&& base0
== base1
&& (incdec0
|| incdec1
))
3523 /* We can not optimize the case where op1 and op2 refer to the same
3525 if (base0
== base1
&& disp0
== disp1
&& index0
== index1
)
3533 /* Check for while loop inside a decrement and branch loop. */
3536 c4x_label_conflict (rtx insn
, rtx jump
, rtx db
)
3540 if (GET_CODE (insn
) == CODE_LABEL
)
3542 if (CODE_LABEL_NUMBER (jump
) == CODE_LABEL_NUMBER (insn
))
3544 if (CODE_LABEL_NUMBER (db
) == CODE_LABEL_NUMBER (insn
))
3547 insn
= PREV_INSN (insn
);
3553 /* Validate combination of operands for parallel load/store instructions. */
3556 valid_parallel_load_store (rtx
*operands
,
3557 enum machine_mode mode ATTRIBUTE_UNUSED
)
3559 rtx op0
= operands
[0];
3560 rtx op1
= operands
[1];
3561 rtx op2
= operands
[2];
3562 rtx op3
= operands
[3];
3564 if (GET_CODE (op0
) == SUBREG
)
3565 op0
= SUBREG_REG (op0
);
3566 if (GET_CODE (op1
) == SUBREG
)
3567 op1
= SUBREG_REG (op1
);
3568 if (GET_CODE (op2
) == SUBREG
)
3569 op2
= SUBREG_REG (op2
);
3570 if (GET_CODE (op3
) == SUBREG
)
3571 op3
= SUBREG_REG (op3
);
3573 /* The patterns should only allow ext_low_reg_operand() or
3574 par_ind_operand() operands. Thus of the 4 operands, only 2
3575 should be REGs and the other 2 should be MEMs. */
3577 /* This test prevents the multipack pass from using this pattern if
3578 op0 is used as an index or base register in op2 or op3, since
3579 this combination will require reloading. */
3580 if (GET_CODE (op0
) == REG
3581 && ((GET_CODE (op2
) == MEM
&& reg_mentioned_p (op0
, XEXP (op2
, 0)))
3582 || (GET_CODE (op3
) == MEM
&& reg_mentioned_p (op0
, XEXP (op3
, 0)))))
3586 if (GET_CODE (op0
) == REG
&& GET_CODE (op2
) == REG
)
3587 return (REGNO (op0
) != REGNO (op2
))
3588 && GET_CODE (op1
) == MEM
&& GET_CODE (op3
) == MEM
3589 && ! c4x_address_conflict (op1
, op3
, 0, 0);
3592 if (GET_CODE (op1
) == REG
&& GET_CODE (op3
) == REG
)
3593 return GET_CODE (op0
) == MEM
&& GET_CODE (op2
) == MEM
3594 && ! c4x_address_conflict (op0
, op2
, 1, 1);
3597 if (GET_CODE (op0
) == REG
&& GET_CODE (op3
) == REG
)
3598 return GET_CODE (op1
) == MEM
&& GET_CODE (op2
) == MEM
3599 && ! c4x_address_conflict (op1
, op2
, 0, 1);
3602 if (GET_CODE (op1
) == REG
&& GET_CODE (op2
) == REG
)
3603 return GET_CODE (op0
) == MEM
&& GET_CODE (op3
) == MEM
3604 && ! c4x_address_conflict (op0
, op3
, 1, 0);
3611 valid_parallel_operands_4 (rtx
*operands
,
3612 enum machine_mode mode ATTRIBUTE_UNUSED
)
3614 rtx op0
= operands
[0];
3615 rtx op2
= operands
[2];
3617 if (GET_CODE (op0
) == SUBREG
)
3618 op0
= SUBREG_REG (op0
);
3619 if (GET_CODE (op2
) == SUBREG
)
3620 op2
= SUBREG_REG (op2
);
3622 /* This test prevents the multipack pass from using this pattern if
3623 op0 is used as an index or base register in op2, since this combination
3624 will require reloading. */
3625 if (GET_CODE (op0
) == REG
3626 && GET_CODE (op2
) == MEM
3627 && reg_mentioned_p (op0
, XEXP (op2
, 0)))
3635 valid_parallel_operands_5 (rtx
*operands
,
3636 enum machine_mode mode ATTRIBUTE_UNUSED
)
3639 rtx op0
= operands
[0];
3640 rtx op1
= operands
[1];
3641 rtx op2
= operands
[2];
3642 rtx op3
= operands
[3];
3644 if (GET_CODE (op0
) == SUBREG
)
3645 op0
= SUBREG_REG (op0
);
3646 if (GET_CODE (op1
) == SUBREG
)
3647 op1
= SUBREG_REG (op1
);
3648 if (GET_CODE (op2
) == SUBREG
)
3649 op2
= SUBREG_REG (op2
);
3651 /* The patterns should only allow ext_low_reg_operand() or
3652 par_ind_operand() operands. Operands 1 and 2 may be commutative
3653 but only one of them can be a register. */
3654 if (GET_CODE (op1
) == REG
)
3656 if (GET_CODE (op2
) == REG
)
3662 /* This test prevents the multipack pass from using this pattern if
3663 op0 is used as an index or base register in op3, since this combination
3664 will require reloading. */
3665 if (GET_CODE (op0
) == REG
3666 && GET_CODE (op3
) == MEM
3667 && reg_mentioned_p (op0
, XEXP (op3
, 0)))
3675 valid_parallel_operands_6 (rtx
*operands
,
3676 enum machine_mode mode ATTRIBUTE_UNUSED
)
3679 rtx op0
= operands
[0];
3680 rtx op1
= operands
[1];
3681 rtx op2
= operands
[2];
3682 rtx op4
= operands
[4];
3683 rtx op5
= operands
[5];
3685 if (GET_CODE (op1
) == SUBREG
)
3686 op1
= SUBREG_REG (op1
);
3687 if (GET_CODE (op2
) == SUBREG
)
3688 op2
= SUBREG_REG (op2
);
3689 if (GET_CODE (op4
) == SUBREG
)
3690 op4
= SUBREG_REG (op4
);
3691 if (GET_CODE (op5
) == SUBREG
)
3692 op5
= SUBREG_REG (op5
);
3694 /* The patterns should only allow ext_low_reg_operand() or
3695 par_ind_operand() operands. Thus of the 4 input operands, only 2
3696 should be REGs and the other 2 should be MEMs. */
3698 if (GET_CODE (op1
) == REG
)
3700 if (GET_CODE (op2
) == REG
)
3702 if (GET_CODE (op4
) == REG
)
3704 if (GET_CODE (op5
) == REG
)
3707 /* The new C30/C40 silicon dies allow 3 regs of the 4 input operands.
3708 Perhaps we should count the MEMs as well? */
3712 /* This test prevents the multipack pass from using this pattern if
3713 op0 is used as an index or base register in op4 or op5, since
3714 this combination will require reloading. */
3715 if (GET_CODE (op0
) == REG
3716 && ((GET_CODE (op4
) == MEM
&& reg_mentioned_p (op0
, XEXP (op4
, 0)))
3717 || (GET_CODE (op5
) == MEM
&& reg_mentioned_p (op0
, XEXP (op5
, 0)))))
3724 /* Validate combination of src operands. Note that the operands have
3725 been screened by the src_operand predicate. We just have to check
3726 that the combination of operands is valid. If FORCE is set, ensure
3727 that the destination regno is valid if we have a 2 operand insn. */
3730 c4x_valid_operands (enum rtx_code code
, rtx
*operands
,
3731 enum machine_mode mode ATTRIBUTE_UNUSED
,
3736 enum rtx_code code1
;
3737 enum rtx_code code2
;
3739 if (code
== COMPARE
)
3750 if (GET_CODE (op1
) == SUBREG
)
3751 op1
= SUBREG_REG (op1
);
3752 if (GET_CODE (op2
) == SUBREG
)
3753 op2
= SUBREG_REG (op2
);
3755 code1
= GET_CODE (op1
);
3756 code2
= GET_CODE (op2
);
3758 if (code1
== REG
&& code2
== REG
)
3761 if (code1
== MEM
&& code2
== MEM
)
3763 if (c4x_S_indirect (op1
) && c4x_S_indirect (op2
))
3765 return c4x_R_indirect (op1
) && c4x_R_indirect (op2
);
3776 if (c4x_J_constant (op2
) && c4x_R_indirect (op1
))
3781 if (! c4x_H_constant (op2
))
3785 /* Any valid memory operand screened by src_operand is OK. */
3788 /* After CSE, any remaining (ADDRESSOF:P reg) gets converted
3789 into a stack slot memory address comprising a PLUS and a
3795 fatal_insn ("c4x_valid_operands: Internal error", op2
);
3799 /* Check that we have a valid destination register for a two operand
3801 return ! force
|| code
== COMPARE
|| REGNO (op1
) == REGNO (operands
[0]);
3804 /* We assume MINUS is commutative since the subtract patterns
3805 also support the reverse subtract instructions. Since op1
3806 is not a register, and op2 is a register, op1 can only
3807 be a restricted memory operand for a shift instruction. */
3808 if (code
== ASHIFTRT
|| code
== LSHIFTRT
3809 || code
== ASHIFT
|| code
== COMPARE
)
3811 && (c4x_S_indirect (op1
) || c4x_R_indirect (op1
));
3816 if (c4x_J_constant (op1
) && c4x_R_indirect (op2
))
3821 if (! c4x_H_constant (op1
))
3825 /* Any valid memory operand screened by src_operand is OK. */
3833 /* After CSE, any remaining (ADDRESSOF:P reg) gets converted
3834 into a stack slot memory address comprising a PLUS and a
3844 /* Check that we have a valid destination register for a two operand
3846 return ! force
|| REGNO (op1
) == REGNO (operands
[0]);
3850 int valid_operands (enum rtx_code code
, rtx
*operands
, enum machine_mode mode
)
3853 /* If we are not optimizing then we have to let anything go and let
3854 reload fix things up. instantiate_decl in function.c can produce
3855 invalid insns by changing the offset of a memory operand from a
3856 valid one into an invalid one, when the second operand is also a
3857 memory operand. The alternative is not to allow two memory
3858 operands for an insn when not optimizing. The problem only rarely
3859 occurs, for example with the C-torture program DFcmp.c. */
3861 return ! optimize
|| c4x_valid_operands (code
, operands
, mode
, 0);
3866 legitimize_operands (enum rtx_code code
, rtx
*operands
, enum machine_mode mode
)
3868 /* Compare only has 2 operands. */
3869 if (code
== COMPARE
)
3871 /* During RTL generation, force constants into pseudos so that
3872 they can get hoisted out of loops. This will tie up an extra
3873 register but can save an extra cycle. Only do this if loop
3874 optimization enabled. (We cannot pull this trick for add and
3875 sub instructions since the flow pass won't find
3876 autoincrements etc.) This allows us to generate compare
3877 instructions like CMPI R0, *AR0++ where R0 = 42, say, instead
3878 of LDI *AR0++, R0; CMPI 42, R0.
3880 Note that expand_binops will try to load an expensive constant
3881 into a register if it is used within a loop. Unfortunately,
3882 the cost mechanism doesn't allow us to look at the other
3883 operand to decide whether the constant is expensive. */
3885 if (! reload_in_progress
3888 && GET_CODE (operands
[1]) == CONST_INT
3889 && preserve_subexpressions_p ()
3890 && rtx_cost (operands
[1], code
) > 1)
3891 operands
[1] = force_reg (mode
, operands
[1]);
3893 if (! reload_in_progress
3894 && ! c4x_valid_operands (code
, operands
, mode
, 0))
3895 operands
[0] = force_reg (mode
, operands
[0]);
3899 /* We cannot do this for ADDI/SUBI insns since we will
3900 defeat the flow pass from finding autoincrement addressing
3902 if (! reload_in_progress
3903 && ! ((code
== PLUS
|| code
== MINUS
) && mode
== Pmode
)
3906 && GET_CODE (operands
[2]) == CONST_INT
3907 && preserve_subexpressions_p ()
3908 && rtx_cost (operands
[2], code
) > 1)
3909 operands
[2] = force_reg (mode
, operands
[2]);
3911 /* We can get better code on a C30 if we force constant shift counts
3912 into a register. This way they can get hoisted out of loops,
3913 tying up a register, but saving an instruction. The downside is
3914 that they may get allocated to an address or index register, and
3915 thus we will get a pipeline conflict if there is a nearby
3916 indirect address using an address register.
3918 Note that expand_binops will not try to load an expensive constant
3919 into a register if it is used within a loop for a shift insn. */
3921 if (! reload_in_progress
3922 && ! c4x_valid_operands (code
, operands
, mode
, TARGET_FORCE
))
3924 /* If the operand combination is invalid, we force operand1 into a
3925 register, preventing reload from having doing to do this at a
3927 operands
[1] = force_reg (mode
, operands
[1]);
3930 emit_move_insn (operands
[0], operands
[1]);
3931 operands
[1] = copy_rtx (operands
[0]);
3935 /* Just in case... */
3936 if (! c4x_valid_operands (code
, operands
, mode
, 0))
3937 operands
[2] = force_reg (mode
, operands
[2]);
3941 /* Right shifts require a negative shift count, but GCC expects
3942 a positive count, so we emit a NEG. */
3943 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
3944 && (GET_CODE (operands
[2]) != CONST_INT
))
3945 operands
[2] = gen_rtx_NEG (mode
, negate_rtx (mode
, operands
[2]));
3951 /* The following predicates are used for instruction scheduling. */
3954 group1_reg_operand (rtx op
, enum machine_mode mode
)
3956 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
3958 if (GET_CODE (op
) == SUBREG
)
3959 op
= SUBREG_REG (op
);
3960 return REG_P (op
) && (! reload_completed
|| IS_GROUP1_REG (op
));
3965 group1_mem_operand (rtx op
, enum machine_mode mode
)
3967 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
3970 if (GET_CODE (op
) == MEM
)
3973 if (GET_CODE (op
) == PLUS
)
3975 rtx op0
= XEXP (op
, 0);
3976 rtx op1
= XEXP (op
, 1);
3978 if ((REG_P (op0
) && (! reload_completed
|| IS_GROUP1_REG (op0
)))
3979 || (REG_P (op1
) && (! reload_completed
|| IS_GROUP1_REG (op1
))))
3982 else if ((REG_P (op
)) && (! reload_completed
|| IS_GROUP1_REG (op
)))
3990 /* Return true if any one of the address registers. */
3993 arx_reg_operand (rtx op
, enum machine_mode mode
)
3995 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
3997 if (GET_CODE (op
) == SUBREG
)
3998 op
= SUBREG_REG (op
);
3999 return REG_P (op
) && (! reload_completed
|| IS_ADDR_REG (op
));
4004 c4x_arn_reg_operand (rtx op
, enum machine_mode mode
, unsigned int regno
)
4006 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4008 if (GET_CODE (op
) == SUBREG
)
4009 op
= SUBREG_REG (op
);
4010 return REG_P (op
) && (! reload_completed
|| (REGNO (op
) == regno
));
4015 c4x_arn_mem_operand (rtx op
, enum machine_mode mode
, unsigned int regno
)
4017 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4020 if (GET_CODE (op
) == MEM
)
4023 switch (GET_CODE (op
))
4032 return REG_P (op
) && (! reload_completed
|| (REGNO (op
) == regno
));
4036 if (REG_P (XEXP (op
, 0)) && (! reload_completed
4037 || (REGNO (XEXP (op
, 0)) == regno
)))
4039 if (REG_P (XEXP (XEXP (op
, 1), 1))
4040 && (! reload_completed
4041 || (REGNO (XEXP (XEXP (op
, 1), 1)) == regno
)))
4047 rtx op0
= XEXP (op
, 0);
4048 rtx op1
= XEXP (op
, 1);
4050 if ((REG_P (op0
) && (! reload_completed
4051 || (REGNO (op0
) == regno
)))
4052 || (REG_P (op1
) && (! reload_completed
4053 || (REGNO (op1
) == regno
))))
4067 ar0_reg_operand (rtx op
, enum machine_mode mode
)
4069 return c4x_arn_reg_operand (op
, mode
, AR0_REGNO
);
4074 ar0_mem_operand (rtx op
, enum machine_mode mode
)
4076 return c4x_arn_mem_operand (op
, mode
, AR0_REGNO
);
4081 ar1_reg_operand (rtx op
, enum machine_mode mode
)
4083 return c4x_arn_reg_operand (op
, mode
, AR1_REGNO
);
4088 ar1_mem_operand (rtx op
, enum machine_mode mode
)
4090 return c4x_arn_mem_operand (op
, mode
, AR1_REGNO
);
4095 ar2_reg_operand (rtx op
, enum machine_mode mode
)
4097 return c4x_arn_reg_operand (op
, mode
, AR2_REGNO
);
4102 ar2_mem_operand (rtx op
, enum machine_mode mode
)
4104 return c4x_arn_mem_operand (op
, mode
, AR2_REGNO
);
4109 ar3_reg_operand (rtx op
, enum machine_mode mode
)
4111 return c4x_arn_reg_operand (op
, mode
, AR3_REGNO
);
4116 ar3_mem_operand (rtx op
, enum machine_mode mode
)
4118 return c4x_arn_mem_operand (op
, mode
, AR3_REGNO
);
4123 ar4_reg_operand (rtx op
, enum machine_mode mode
)
4125 return c4x_arn_reg_operand (op
, mode
, AR4_REGNO
);
4130 ar4_mem_operand (rtx op
, enum machine_mode mode
)
4132 return c4x_arn_mem_operand (op
, mode
, AR4_REGNO
);
4137 ar5_reg_operand (rtx op
, enum machine_mode mode
)
4139 return c4x_arn_reg_operand (op
, mode
, AR5_REGNO
);
4144 ar5_mem_operand (rtx op
, enum machine_mode mode
)
4146 return c4x_arn_mem_operand (op
, mode
, AR5_REGNO
);
4151 ar6_reg_operand (rtx op
, enum machine_mode mode
)
4153 return c4x_arn_reg_operand (op
, mode
, AR6_REGNO
);
4158 ar6_mem_operand (rtx op
, enum machine_mode mode
)
4160 return c4x_arn_mem_operand (op
, mode
, AR6_REGNO
);
4165 ar7_reg_operand (rtx op
, enum machine_mode mode
)
4167 return c4x_arn_reg_operand (op
, mode
, AR7_REGNO
);
4172 ar7_mem_operand (rtx op
, enum machine_mode mode
)
4174 return c4x_arn_mem_operand (op
, mode
, AR7_REGNO
);
4179 ir0_reg_operand (rtx op
, enum machine_mode mode
)
4181 return c4x_arn_reg_operand (op
, mode
, IR0_REGNO
);
4186 ir0_mem_operand (rtx op
, enum machine_mode mode
)
4188 return c4x_arn_mem_operand (op
, mode
, IR0_REGNO
);
4193 ir1_reg_operand (rtx op
, enum machine_mode mode
)
4195 return c4x_arn_reg_operand (op
, mode
, IR1_REGNO
);
4200 ir1_mem_operand (rtx op
, enum machine_mode mode
)
4202 return c4x_arn_mem_operand (op
, mode
, IR1_REGNO
);
4206 /* This is similar to operand_subword but allows autoincrement
4210 c4x_operand_subword (rtx op
, int i
, int validate_address
,
4211 enum machine_mode mode
)
4213 if (mode
!= HImode
&& mode
!= HFmode
)
4214 fatal_insn ("c4x_operand_subword: invalid mode", op
);
4216 if (mode
== HFmode
&& REG_P (op
))
4217 fatal_insn ("c4x_operand_subword: invalid operand", op
);
4219 if (GET_CODE (op
) == MEM
)
4221 enum rtx_code code
= GET_CODE (XEXP (op
, 0));
4222 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
4223 enum machine_mode submode
;
4228 else if (mode
== HFmode
)
4235 return gen_rtx_MEM (submode
, XEXP (op
, 0));
4241 /* We could handle these with some difficulty.
4242 e.g., *p-- => *(p-=2); *(p+1). */
4243 fatal_insn ("c4x_operand_subword: invalid autoincrement", op
);
4249 fatal_insn ("c4x_operand_subword: invalid address", op
);
4251 /* Even though offsettable_address_p considers (MEM
4252 (LO_SUM)) to be offsettable, it is not safe if the
4253 address is at the end of the data page since we also have
4254 to fix up the associated high PART. In this case where
4255 we are trying to split a HImode or HFmode memory
4256 reference, we would have to emit another insn to reload a
4257 new HIGH value. It's easier to disable LO_SUM memory references
4258 in HImode or HFmode and we probably get better code. */
4260 fatal_insn ("c4x_operand_subword: address not offsettable", op
);
4267 return operand_subword (op
, i
, validate_address
, mode
);
4272 struct name_list
*next
;
4276 static struct name_list
*global_head
;
4277 static struct name_list
*extern_head
;
4280 /* Add NAME to list of global symbols and remove from external list if
4281 present on external list. */
4284 c4x_global_label (const char *name
)
4286 struct name_list
*p
, *last
;
4288 /* Do not insert duplicate names, so linearly search through list of
4293 if (strcmp (p
->name
, name
) == 0)
4297 p
= (struct name_list
*) xmalloc (sizeof *p
);
4298 p
->next
= global_head
;
4302 /* Remove this name from ref list if present. */
4307 if (strcmp (p
->name
, name
) == 0)
4310 last
->next
= p
->next
;
4312 extern_head
= p
->next
;
4321 /* Add NAME to list of external symbols. */
4324 c4x_external_ref (const char *name
)
4326 struct name_list
*p
;
4328 /* Do not insert duplicate names. */
4332 if (strcmp (p
->name
, name
) == 0)
4337 /* Do not insert ref if global found. */
4341 if (strcmp (p
->name
, name
) == 0)
4345 p
= (struct name_list
*) xmalloc (sizeof *p
);
4346 p
->next
= extern_head
;
4351 /* We need to have a data section we can identify so that we can set
4352 the DP register back to a data pointer in the small memory model.
4353 This is only required for ISRs if we are paranoid that someone
4354 may have quietly changed this register on the sly. */
4356 c4x_file_start (void)
4359 if (TARGET_C30
) dspversion
= 30;
4360 if (TARGET_C31
) dspversion
= 31;
4361 if (TARGET_C32
) dspversion
= 32;
4362 if (TARGET_C33
) dspversion
= 33;
4363 if (TARGET_C40
) dspversion
= 40;
4364 if (TARGET_C44
) dspversion
= 44;
4366 default_file_start ();
4367 fprintf (asm_out_file
, "\t.version\t%d\n", dspversion
);
4368 fputs ("\n\t.data\ndata_sec:\n", asm_out_file
);
4375 struct name_list
*p
;
4377 /* Output all external names that are not global. */
4381 fprintf (asm_out_file
, "\t.ref\t");
4382 assemble_name (asm_out_file
, p
->name
);
4383 fprintf (asm_out_file
, "\n");
4386 fprintf (asm_out_file
, "\t.end\n");
4391 c4x_check_attribute (const char *attrib
, tree list
, tree decl
, tree
*attributes
)
4393 while (list
!= NULL_TREE
4394 && IDENTIFIER_POINTER (TREE_PURPOSE (list
))
4395 != IDENTIFIER_POINTER (DECL_NAME (decl
)))
4396 list
= TREE_CHAIN (list
);
4398 *attributes
= tree_cons (get_identifier (attrib
), TREE_VALUE (list
),
4404 c4x_insert_attributes (tree decl
, tree
*attributes
)
4406 switch (TREE_CODE (decl
))
4409 c4x_check_attribute ("section", code_tree
, decl
, attributes
);
4410 c4x_check_attribute ("const", pure_tree
, decl
, attributes
);
4411 c4x_check_attribute ("noreturn", noreturn_tree
, decl
, attributes
);
4412 c4x_check_attribute ("interrupt", interrupt_tree
, decl
, attributes
);
4413 c4x_check_attribute ("naked", naked_tree
, decl
, attributes
);
4417 c4x_check_attribute ("section", data_tree
, decl
, attributes
);
4425 /* Table of valid machine attributes. */
4426 const struct attribute_spec c4x_attribute_table
[] =
4428 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4429 { "interrupt", 0, 0, false, true, true, c4x_handle_fntype_attribute
},
4430 { "naked", 0, 0, false, true, true, c4x_handle_fntype_attribute
},
4431 { "leaf_pretend", 0, 0, false, true, true, c4x_handle_fntype_attribute
},
4432 { NULL
, 0, 0, false, false, false, NULL
}
4435 /* Handle an attribute requiring a FUNCTION_TYPE;
4436 arguments as in struct attribute_spec.handler. */
4438 c4x_handle_fntype_attribute (tree
*node
, tree name
,
4439 tree args ATTRIBUTE_UNUSED
,
4440 int flags ATTRIBUTE_UNUSED
,
4443 if (TREE_CODE (*node
) != FUNCTION_TYPE
)
4445 warning ("`%s' attribute only applies to functions",
4446 IDENTIFIER_POINTER (name
));
4447 *no_add_attrs
= true;
4454 /* !!! FIXME to emit RPTS correctly. */
4457 c4x_rptb_rpts_p (rtx insn
, rtx op
)
4459 /* The next insn should be our label marking where the
4460 repeat block starts. */
4461 insn
= NEXT_INSN (insn
);
4462 if (GET_CODE (insn
) != CODE_LABEL
)
4464 /* Some insns may have been shifted between the RPTB insn
4465 and the top label... They were probably destined to
4466 be moved out of the loop. For now, let's leave them
4467 where they are and print a warning. We should
4468 probably move these insns before the repeat block insn. */
4470 fatal_insn("c4x_rptb_rpts_p: Repeat block top label moved\n",
4475 /* Skip any notes. */
4476 insn
= next_nonnote_insn (insn
);
4478 /* This should be our first insn in the loop. */
4479 if (! INSN_P (insn
))
4482 /* Skip any notes. */
4483 insn
= next_nonnote_insn (insn
);
4485 if (! INSN_P (insn
))
4488 if (recog_memoized (insn
) != CODE_FOR_rptb_end
)
4494 return (GET_CODE (op
) == CONST_INT
) && TARGET_RPTS_CYCLES (INTVAL (op
));
4498 /* Check if register r11 is used as the destination of an insn. */
4501 c4x_r11_set_p(rtx x
)
4510 if (INSN_P (x
) && GET_CODE (PATTERN (x
)) == SEQUENCE
)
4511 x
= XVECEXP (PATTERN (x
), 0, XVECLEN (PATTERN (x
), 0) - 1);
4513 if (INSN_P (x
) && (set
= single_set (x
)))
4516 if (GET_CODE (x
) == REG
&& REGNO (x
) == R11_REGNO
)
4519 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
4520 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
4524 if (c4x_r11_set_p (XEXP (x
, i
)))
4527 else if (fmt
[i
] == 'E')
4528 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4529 if (c4x_r11_set_p (XVECEXP (x
, i
, j
)))
4536 /* The c4x sometimes has a problem when the insn before the laj insn
4537 sets the r11 register. Check for this situation. */
4540 c4x_check_laj_p (rtx insn
)
4542 insn
= prev_nonnote_insn (insn
);
4544 /* If this is the start of the function no nop is needed. */
4548 /* If the previous insn is a code label we have to insert a nop. This
4549 could be a jump or table jump. We can find the normal jumps by
4550 scanning the function but this will not find table jumps. */
4551 if (GET_CODE (insn
) == CODE_LABEL
)
4554 /* If the previous insn sets register r11 we have to insert a nop. */
4555 if (c4x_r11_set_p (insn
))
4558 /* No nop needed. */
4563 /* Adjust the cost of a scheduling dependency. Return the new cost of
4564 a dependency LINK or INSN on DEP_INSN. COST is the current cost.
4565 A set of an address register followed by a use occurs a 2 cycle
4566 stall (reduced to a single cycle on the c40 using LDA), while
4567 a read of an address register followed by a use occurs a single cycle. */
4569 #define SET_USE_COST 3
4570 #define SETLDA_USE_COST 2
4571 #define READ_USE_COST 2
4574 c4x_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
4576 /* Don't worry about this until we know what registers have been
4578 if (flag_schedule_insns
== 0 && ! reload_completed
)
4581 /* How do we handle dependencies where a read followed by another
4582 read causes a pipeline stall? For example, a read of ar0 followed
4583 by the use of ar0 for a memory reference. It looks like we
4584 need to extend the scheduler to handle this case. */
4586 /* Reload sometimes generates a CLOBBER of a stack slot, e.g.,
4587 (clobber (mem:QI (plus:QI (reg:QI 11 ar3) (const_int 261)))),
4588 so only deal with insns we know about. */
4589 if (recog_memoized (dep_insn
) < 0)
4592 if (REG_NOTE_KIND (link
) == 0)
4596 /* Data dependency; DEP_INSN writes a register that INSN reads some
4600 if (get_attr_setgroup1 (dep_insn
) && get_attr_usegroup1 (insn
))
4601 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4602 if (get_attr_readarx (dep_insn
) && get_attr_usegroup1 (insn
))
4603 max
= READ_USE_COST
> max
? READ_USE_COST
: max
;
4607 /* This could be significantly optimized. We should look
4608 to see if dep_insn sets ar0-ar7 or ir0-ir1 and if
4609 insn uses ar0-ar7. We then test if the same register
4610 is used. The tricky bit is that some operands will
4611 use several registers... */
4612 if (get_attr_setar0 (dep_insn
) && get_attr_usear0 (insn
))
4613 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4614 if (get_attr_setlda_ar0 (dep_insn
) && get_attr_usear0 (insn
))
4615 max
= SETLDA_USE_COST
> max
? SETLDA_USE_COST
: max
;
4616 if (get_attr_readar0 (dep_insn
) && get_attr_usear0 (insn
))
4617 max
= READ_USE_COST
> max
? READ_USE_COST
: max
;
4619 if (get_attr_setar1 (dep_insn
) && get_attr_usear1 (insn
))
4620 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4621 if (get_attr_setlda_ar1 (dep_insn
) && get_attr_usear1 (insn
))
4622 max
= SETLDA_USE_COST
> max
? SETLDA_USE_COST
: max
;
4623 if (get_attr_readar1 (dep_insn
) && get_attr_usear1 (insn
))
4624 max
= READ_USE_COST
> max
? READ_USE_COST
: max
;
4626 if (get_attr_setar2 (dep_insn
) && get_attr_usear2 (insn
))
4627 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4628 if (get_attr_setlda_ar2 (dep_insn
) && get_attr_usear2 (insn
))
4629 max
= SETLDA_USE_COST
> max
? SETLDA_USE_COST
: max
;
4630 if (get_attr_readar2 (dep_insn
) && get_attr_usear2 (insn
))
4631 max
= READ_USE_COST
> max
? READ_USE_COST
: max
;
4633 if (get_attr_setar3 (dep_insn
) && get_attr_usear3 (insn
))
4634 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4635 if (get_attr_setlda_ar3 (dep_insn
) && get_attr_usear3 (insn
))
4636 max
= SETLDA_USE_COST
> max
? SETLDA_USE_COST
: max
;
4637 if (get_attr_readar3 (dep_insn
) && get_attr_usear3 (insn
))
4638 max
= READ_USE_COST
> max
? READ_USE_COST
: max
;
4640 if (get_attr_setar4 (dep_insn
) && get_attr_usear4 (insn
))
4641 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4642 if (get_attr_setlda_ar4 (dep_insn
) && get_attr_usear4 (insn
))
4643 max
= SETLDA_USE_COST
> max
? SETLDA_USE_COST
: max
;
4644 if (get_attr_readar4 (dep_insn
) && get_attr_usear4 (insn
))
4645 max
= READ_USE_COST
> max
? READ_USE_COST
: max
;
4647 if (get_attr_setar5 (dep_insn
) && get_attr_usear5 (insn
))
4648 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4649 if (get_attr_setlda_ar5 (dep_insn
) && get_attr_usear5 (insn
))
4650 max
= SETLDA_USE_COST
> max
? SETLDA_USE_COST
: max
;
4651 if (get_attr_readar5 (dep_insn
) && get_attr_usear5 (insn
))
4652 max
= READ_USE_COST
> max
? READ_USE_COST
: max
;
4654 if (get_attr_setar6 (dep_insn
) && get_attr_usear6 (insn
))
4655 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4656 if (get_attr_setlda_ar6 (dep_insn
) && get_attr_usear6 (insn
))
4657 max
= SETLDA_USE_COST
> max
? SETLDA_USE_COST
: max
;
4658 if (get_attr_readar6 (dep_insn
) && get_attr_usear6 (insn
))
4659 max
= READ_USE_COST
> max
? READ_USE_COST
: max
;
4661 if (get_attr_setar7 (dep_insn
) && get_attr_usear7 (insn
))
4662 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4663 if (get_attr_setlda_ar7 (dep_insn
) && get_attr_usear7 (insn
))
4664 max
= SETLDA_USE_COST
> max
? SETLDA_USE_COST
: max
;
4665 if (get_attr_readar7 (dep_insn
) && get_attr_usear7 (insn
))
4666 max
= READ_USE_COST
> max
? READ_USE_COST
: max
;
4668 if (get_attr_setir0 (dep_insn
) && get_attr_useir0 (insn
))
4669 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4670 if (get_attr_setlda_ir0 (dep_insn
) && get_attr_useir0 (insn
))
4671 max
= SETLDA_USE_COST
> max
? SETLDA_USE_COST
: max
;
4673 if (get_attr_setir1 (dep_insn
) && get_attr_useir1 (insn
))
4674 max
= SET_USE_COST
> max
? SET_USE_COST
: max
;
4675 if (get_attr_setlda_ir1 (dep_insn
) && get_attr_useir1 (insn
))
4676 max
= SETLDA_USE_COST
> max
? SETLDA_USE_COST
: max
;
4682 /* For other data dependencies, the default cost specified in the
4686 else if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
4688 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4691 /* For c4x anti dependencies, the cost is 0. */
4694 else if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
4696 /* Output dependency; DEP_INSN writes a register that INSN writes some
4699 /* For c4x output dependencies, the cost is 0. */
4707 c4x_init_builtins (void)
4709 tree endlink
= void_list_node
;
4711 builtin_function ("fast_ftoi",
4714 tree_cons (NULL_TREE
, double_type_node
, endlink
)),
4715 C4X_BUILTIN_FIX
, BUILT_IN_MD
, NULL
, NULL_TREE
);
4716 builtin_function ("ansi_ftoi",
4719 tree_cons (NULL_TREE
, double_type_node
, endlink
)),
4720 C4X_BUILTIN_FIX_ANSI
, BUILT_IN_MD
, NULL
, NULL_TREE
);
4722 builtin_function ("fast_imult",
4725 tree_cons (NULL_TREE
, integer_type_node
,
4726 tree_cons (NULL_TREE
,
4727 integer_type_node
, endlink
))),
4728 C4X_BUILTIN_MPYI
, BUILT_IN_MD
, NULL
, NULL_TREE
);
4731 builtin_function ("toieee",
4734 tree_cons (NULL_TREE
, double_type_node
, endlink
)),
4735 C4X_BUILTIN_TOIEEE
, BUILT_IN_MD
, NULL
, NULL_TREE
);
4736 builtin_function ("frieee",
4739 tree_cons (NULL_TREE
, double_type_node
, endlink
)),
4740 C4X_BUILTIN_FRIEEE
, BUILT_IN_MD
, NULL
, NULL_TREE
);
4741 builtin_function ("fast_invf",
4744 tree_cons (NULL_TREE
, double_type_node
, endlink
)),
4745 C4X_BUILTIN_RCPF
, BUILT_IN_MD
, NULL
, NULL_TREE
);
4751 c4x_expand_builtin (tree exp
, rtx target
,
4752 rtx subtarget ATTRIBUTE_UNUSED
,
4753 enum machine_mode mode ATTRIBUTE_UNUSED
,
4754 int ignore ATTRIBUTE_UNUSED
)
4756 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
4757 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
4758 tree arglist
= TREE_OPERAND (exp
, 1);
4764 case C4X_BUILTIN_FIX
:
4765 arg0
= TREE_VALUE (arglist
);
4766 r0
= expand_expr (arg0
, NULL_RTX
, QFmode
, 0);
4767 r0
= protect_from_queue (r0
, 0);
4768 if (! target
|| ! register_operand (target
, QImode
))
4769 target
= gen_reg_rtx (QImode
);
4770 emit_insn (gen_fixqfqi_clobber (target
, r0
));
4773 case C4X_BUILTIN_FIX_ANSI
:
4774 arg0
= TREE_VALUE (arglist
);
4775 r0
= expand_expr (arg0
, NULL_RTX
, QFmode
, 0);
4776 r0
= protect_from_queue (r0
, 0);
4777 if (! target
|| ! register_operand (target
, QImode
))
4778 target
= gen_reg_rtx (QImode
);
4779 emit_insn (gen_fix_truncqfqi2 (target
, r0
));
4782 case C4X_BUILTIN_MPYI
:
4785 arg0
= TREE_VALUE (arglist
);
4786 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
4787 r0
= expand_expr (arg0
, NULL_RTX
, QImode
, 0);
4788 r1
= expand_expr (arg1
, NULL_RTX
, QImode
, 0);
4789 r0
= protect_from_queue (r0
, 0);
4790 r1
= protect_from_queue (r1
, 0);
4791 if (! target
|| ! register_operand (target
, QImode
))
4792 target
= gen_reg_rtx (QImode
);
4793 emit_insn (gen_mulqi3_24_clobber (target
, r0
, r1
));
4796 case C4X_BUILTIN_TOIEEE
:
4799 arg0
= TREE_VALUE (arglist
);
4800 r0
= expand_expr (arg0
, NULL_RTX
, QFmode
, 0);
4801 r0
= protect_from_queue (r0
, 0);
4802 if (! target
|| ! register_operand (target
, QFmode
))
4803 target
= gen_reg_rtx (QFmode
);
4804 emit_insn (gen_toieee (target
, r0
));
4807 case C4X_BUILTIN_FRIEEE
:
4810 arg0
= TREE_VALUE (arglist
);
4811 if (TREE_CODE (arg0
) == VAR_DECL
|| TREE_CODE (arg0
) == PARM_DECL
)
4812 put_var_into_stack (arg0
, /*rescan=*/true);
4813 r0
= expand_expr (arg0
, NULL_RTX
, QFmode
, 0);
4814 r0
= protect_from_queue (r0
, 0);
4815 if (register_operand (r0
, QFmode
))
4817 r1
= assign_stack_local (QFmode
, GET_MODE_SIZE (QFmode
), 0);
4818 emit_move_insn (r1
, r0
);
4821 if (! target
|| ! register_operand (target
, QFmode
))
4822 target
= gen_reg_rtx (QFmode
);
4823 emit_insn (gen_frieee (target
, r0
));
4826 case C4X_BUILTIN_RCPF
:
4829 arg0
= TREE_VALUE (arglist
);
4830 r0
= expand_expr (arg0
, NULL_RTX
, QFmode
, 0);
4831 r0
= protect_from_queue (r0
, 0);
4832 if (! target
|| ! register_operand (target
, QFmode
))
4833 target
= gen_reg_rtx (QFmode
);
4834 emit_insn (gen_rcpfqf_clobber (target
, r0
));
4841 c4x_init_libfuncs (void)
4843 set_optab_libfunc (smul_optab
, QImode
, "__mulqi3");
4844 set_optab_libfunc (sdiv_optab
, QImode
, "__divqi3");
4845 set_optab_libfunc (udiv_optab
, QImode
, "__udivqi3");
4846 set_optab_libfunc (smod_optab
, QImode
, "__modqi3");
4847 set_optab_libfunc (umod_optab
, QImode
, "__umodqi3");
4848 set_optab_libfunc (sdiv_optab
, QFmode
, "__divqf3");
4849 set_optab_libfunc (smul_optab
, HFmode
, "__mulhf3");
4850 set_optab_libfunc (sdiv_optab
, HFmode
, "__divhf3");
4851 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
4852 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
4853 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
4854 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
4855 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
4856 set_optab_libfunc (ffs_optab
, QImode
, "__ffs");
4857 smulhi3_libfunc
= init_one_libfunc ("__smulhi3_high");
4858 umulhi3_libfunc
= init_one_libfunc ("__umulhi3_high");
4859 fix_truncqfhi2_libfunc
= init_one_libfunc ("__fix_truncqfhi2");
4860 fixuns_truncqfhi2_libfunc
= init_one_libfunc ("__ufix_truncqfhi2");
4861 fix_trunchfhi2_libfunc
= init_one_libfunc ("__fix_trunchfhi2");
4862 fixuns_trunchfhi2_libfunc
= init_one_libfunc ("__ufix_trunchfhi2");
4863 floathiqf2_libfunc
= init_one_libfunc ("__floathiqf2");
4864 floatunshiqf2_libfunc
= init_one_libfunc ("__ufloathiqf2");
4865 floathihf2_libfunc
= init_one_libfunc ("__floathihf2");
4866 floatunshihf2_libfunc
= init_one_libfunc ("__ufloathihf2");
4870 c4x_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
)
4872 fprintf (asm_out_file
, "\t.sect\t\"%s\"\n", name
);
4876 c4x_globalize_label (FILE *stream
, const char *name
)
4878 default_globalize_label (stream
, name
);
4879 c4x_global_label (name
);
4882 #define SHIFT_CODE_P(C) \
4883 ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
4884 #define LOGICAL_CODE_P(C) \
4885 ((C) == NOT || (C) == AND || (C) == IOR || (C) == XOR)
4887 /* Compute a (partial) cost for rtx X. Return true if the complete
4888 cost has been computed, and false if subexpressions should be
4889 scanned. In either case, *TOTAL contains the cost result. */
4892 c4x_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4898 /* Some small integers are effectively free for the C40. We should
4899 also consider if we are using the small memory model. With
4900 the big memory model we require an extra insn for a constant
4901 loaded from memory. */
4905 if (c4x_J_constant (x
))
4907 else if (! TARGET_C3X
4908 && outer_code
== AND
4909 && (val
== 255 || val
== 65535))
4911 else if (! TARGET_C3X
4912 && (outer_code
== ASHIFTRT
|| outer_code
== LSHIFTRT
)
4913 && (val
== 16 || val
== 24))
4915 else if (TARGET_C3X
&& SHIFT_CODE_P (outer_code
))
4917 else if (LOGICAL_CODE_P (outer_code
)
4918 ? c4x_L_constant (x
) : c4x_I_constant (x
))
4931 if (c4x_H_constant (x
))
4933 else if (GET_MODE (x
) == QFmode
)
4939 /* ??? Note that we return true, rather than false so that rtx_cost
4940 doesn't include the constant costs. Otherwise expand_mult will
4941 think that it is cheaper to synthesize a multiply rather than to
4942 use a multiply instruction. I think this is because the algorithm
4943 synth_mult doesn't take into account the loading of the operands,
4944 whereas the calculation of mult_cost does. */
4953 *total
= COSTS_N_INSNS (1);
4957 *total
= COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
4958 || TARGET_MPYI
? 1 : 14);
4965 *total
= COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT