| blob | 87408d6f5f7b348e5c69f2356b32c4f6d61193da |
1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
53 #include <splay-tree.h>
56 /* Specify which cpu to schedule for. */
60 {
62 };
64 /* Specify how accurate floating-point traps need to be. */
68 /* Specify the floating-point rounding mode. */
72 /* Specify which things cause traps. */
76 /* Specify bit size of immediate TLS offsets. */
80 /* Strings decoded into the above options. */
90 /* Save information from a "cmpxx" operation until the branch or scc is
91 emitted. */
95 /* Nonzero if inside of a function, because the Alpha asm can't
96 handle .files inside of functions. */
100 /* The number of cycles of latency we should assume on memory reads. */
104 /* Whether the function needs the GP. */
108 /* The alias set for prologue/epilogue register save/restore. */
112 /* The assembler name of the current function. */
116 /* The next explicit relocation sequence number. */
120 /* The literal and gpdisp sequence numbers for this insn, as printed
121 by %# and %* respectively. */
127 /* Costs of various operations on the different architectures. */
129 struct alpha_rtx_cost_data
130 {
139 };
142 {
152 },
162 },
172 },
173 };
175 /* Get the number of args of a function in one of two ways. */
176 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
177 #define NUM_ARGS current_function_args_info.num_args
178 #else
179 #define NUM_ARGS current_function_args_info
180 #endif
182 #define REG_PV 27
183 #define REG_RA 26
185 /* Declarations of static functions. */
189 #if TARGET_ABI_OPEN_VMS
191 #endif
197 \f
198 /* Parse target option strings. */
200 void
202 {
209 #define EV5_MASK (MASK_CPU_EV5)
210 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
226 };
228 /* Unicos/Mk doesn't have shared libraries. */
230 {
234 }
236 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
237 floating-point instructions. Make that the default for this target. */
240 else
246 /* We cannot use su and sui qualifiers for conversion instructions on
247 Unicos/Mk. I'm not sure if this is due to assembler or hardware
248 limitations. Right now, we issue a warning if -mieee is specified
249 and then ignore it; eventually, we should either get it right or
250 disable the option altogether. */
253 {
256 else
257 {
260 }
261 }
264 {
267 else
268 {
271 }
272 }
275 {
282 else
284 }
287 {
296 else
298 alpha_fprm_string);
299 }
302 {
311 else
313 }
316 {
323 else
325 }
327 alpha_cpu
332 {
335 {
341 }
344 }
347 {
350 {
353 }
356 }
358 /* Do some sanity checks on the above options. */
361 {
364 }
368 {
371 }
374 {
375 /* Except for EV6 pass 1 (not released), we always have precise
376 arithmetic traps. Which means we can do software completion
377 without minding trap shadows. */
379 }
382 {
384 {
387 }
389 {
392 }
393 }
395 {
404 ;
408 {
410 {
414 };
418 {
422 }
423 else
425 }
427 {
428 /* Most current memories have about 370ns latency. This is
429 a reasonable guess for a fast cpu. */
431 }
432 else
433 {
436 }
439 }
441 /* Default the definition of "small data" to 8 bytes. */
445 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
451 /* Align labels and loops for optimal branching. */
452 /* ??? Kludge these by not doing anything if we don't optimize and also if
453 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
455 {
460 }
464 /* Acquire a unique set number for our register saves and restores. */
467 /* Register variables and functions with the garbage collector. */
469 /* Set up function hooks. */
472 /* Tell the compiler when we're using VAX floating point. */
474 {
478 }
479 }
480 \f
481 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
483 int
485 {
494 }
496 /* Returns 1 if OP is either the constant zero or a register. If a
497 register, it must be in the proper mode unless MODE is VOIDmode. */
499 int
501 {
503 }
505 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
506 any register. */
508 int
510 {
514 }
517 /* Return 1 if OP is an 8-bit constant or any register. */
519 int
521 {
525 }
527 /* Return 1 if OP is a constant or any register. */
529 int
531 {
533 }
535 /* Return 1 if OP is an 8-bit constant. */
537 int
539 {
542 }
544 /* Return 1 if the operand is a valid second operand to an add insn. */
546 int
548 {
550 /* Constraints I, J, O and P are covered by K. */
555 }
557 /* Return 1 if the operand is a valid second operand to a sign-extending
558 add insn. */
560 int
562 {
568 }
570 /* Return 1 if OP is the constant 4 or 8. */
572 int
574 {
577 }
579 /* Return 1 if OP is a valid first operand to an AND insn. */
581 int
583 {
594 }
596 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
598 int
600 {
606 }
608 /* Return 1 if OP is a constant that is the width, in bits, of an integral
609 mode smaller than DImode. */
611 int
613 {
617 }
619 /* Return 1 if OP is a constant that is the width of an integral machine mode
620 smaller than an integer. */
622 int
624 {
626 {
637 }
639 {
642 }
645 }
647 /* Return 1 if OP is a multiple of 8 less than 64. */
649 int
651 {
655 }
657 /* Return 1 if OP is the zero constant for MODE. */
659 int
661 {
663 }
665 /* Return 1 if OP is a hard floating-point register. */
667 int
669 {
676 }
678 /* Return 1 if OP is a hard general register. */
680 int
682 {
689 }
691 /* Return 1 if OP is a register or a constant integer. */
694 int
696 {
699 }
701 /* Return 1 if OP is something that can be reloaded into a register;
702 if it is a MEM, it need not be valid. */
704 int
706 {
711 {
728 }
731 }
733 /* Likewise, but don't accept constants. */
735 int
737 {
745 }
747 /* Return 1 if OP is a valid operand for the source of a move insn. */
749 int
751 {
759 {
764 {
765 /* We don't split symbolic operands into something unintelligable
766 until after reload, but we do not wish non-small, non-global
767 symbolic operands to be reconstructed from their high/lo_sum
768 form. */
773 }
775 /* This handles both the Windows/NT and OSF cases. */
789 /* ... fall through ... */
806 }
809 }
811 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
812 file, and in the same section as the current function. */
814 int
816 {
820 /* Easy test for recursion. */
824 /* Functions that are not local can be overridden, and thus may
825 not share the same gp. */
829 /* If -msmall-data is in effect, assume that there is only one GP
830 for the module, and so any local symbol has this property. We
831 need explicit relocations to be able to enforce this for symbols
832 not defined in this unit of translation, however. */
836 /* Functions that are not external are defined in this UoT,
837 and thus must share the same gp. */
839 }
841 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
843 int
845 {
848 /* Must share the same GP. */
852 /* If profiling is implemented via linker tricks, we can't jump
853 to the nogp alternate entry point. Note that current_function_profile
854 would not be correct, since that doesn't indicate if the target
855 function uses profiling. */
856 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
857 but is approximately correct for the OSF ABIs. Don't know
858 what to do for VMS, NT, or UMK. */
862 /* Must be a function. In some cases folks create thunks in static
863 data structures and then make calls to them. If we allow the
864 direct call, we'll get an error from the linker about !samegp reloc
865 against a symbol without a .prologue directive. */
869 /* Must be "near" so that the branch is assumed to reach. With
870 -msmall-text, this is assumed true of all local symbols. Since
871 we've already checked samegp, locality is already assured. */
875 /* Otherwise, a decl is "near" if it is defined in the same section. */
890 }
892 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
893 a (non-tls) variable known to be defined in this file. */
895 int
897 {
913 }
915 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
916 known to be defined in this file in the small data area. */
918 int
920 {
935 /* ??? There's no encode_section_info equivalent for the rtl
936 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
943 }
945 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
946 not known (or known not) to be defined in this file. */
948 int
950 {
963 }
965 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
967 int
969 {
974 {
976 {
977 /* Disallow virtual registers to cope with pathological test cases
978 such as compile/930117-1.c in which the virtual reg decomposes
979 to the frame pointer. Which is a hard reg that is not $27. */
981 }
982 else
984 }
991 }
993 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
994 possibly with an offset. */
996 int
998 {
1009 }
1011 /* Return true if OP is valid for a particular TLS relocation. */
1013 static int
1015 {
1031 {
1034 }
1035 else
1036 {
1039 }
1042 {
1051 }
1052 }
1054 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1056 int
1058 {
1060 }
1062 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1064 int
1066 {
1068 }
1070 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1072 int
1074 {
1076 }
1078 /* Return true if OP is valid for 16-bit TP relative relocations. */
1080 int
1082 {
1084 }
1086 /* Return true if OP is valid for 32-bit TP relative relocations. */
1088 int
1090 {
1092 }
1094 /* Return true if OP is valid for 64-bit TP relative relocations. */
1096 int
1098 {
1100 }
1102 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1103 comparisons are valid in which insn. */
1105 int
1107 {
1115 }
1117 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1118 Here we know which comparisons are valid in which insn. */
1120 int
1122 {
1130 }
1132 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1134 int
1136 {
1146 }
1148 /* Return 1 if OP is a signed comparison operation. */
1150 int
1152 {
1161 }
1163 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1164 Here we know which comparisons are valid in which insn. */
1166 int
1168 {
1175 }
1177 /* Return 1 if this is a divide or modulus operator. */
1179 int
1181 {
1185 }
1187 /* Return 1 if this is a float->int conversion operator. */
1189 int
1191 {
1195 }
1197 /* Return 1 if this memory address is a known aligned register plus
1198 a constant. It must be a valid address. This means that we can do
1199 this as an aligned reference plus some offset.
1201 Take into account what reload will do. */
1203 int
1205 {
1206 rtx base;
1209 {
1215 {
1219 }
1220 }
1227 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1228 sorts of constructs. Dig for the real base register. */
1233 else
1234 {
1238 }
1241 }
1243 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1245 int
1247 {
1248 rtx base;
1251 {
1257 {
1261 }
1262 }
1269 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1270 sorts of constructs. Dig for the real base register. */
1275 else
1276 {
1280 }
1283 }
1285 /* Return 1 if OP is either a register or an unaligned memory location. */
1287 int
1289 {
1291 }
1293 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1295 int
1297 {
1305 }
1307 /* Returns 1 if OP is not an eliminable register.
1309 This exists to cure a pathological abort in the s8addq (et al) patterns,
1311 long foo () { long t; bar(); return (long) &t * 26107; }
1313 which run afoul of a hack in reload to cure a (presumably) similar
1314 problem with lea-type instructions on other targets. But there is
1315 one of us and many of them, so work around the problem by selectively
1316 preventing combine from making the optimization. */
1318 int
1320 {
1328 }
1330 /* Return 1 is OP is a memory location that is not a reference (using
1331 an AND) to an unaligned location. Take into account what reload
1332 will do. */
1334 int
1336 {
1338 {
1344 {
1347 /* This may not have been assigned an equivalent address if it will
1348 be eliminated. In that case, it doesn't matter what we do. */
1351 }
1352 }
1355 }
1357 /* Accept a register, but not a subreg of any kind. This allows us to
1358 avoid pathological cases in reload wrt data movement common in
1359 int->fp conversion. */
1361 int
1363 {
1367 }
1369 /* Recognize an addition operation that includes a constant. Used to
1370 convince reload to canonize (plus (plus reg c1) c2) during register
1371 elimination. */
1373 int
1375 {
1384 }
1386 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1387 the range defined for C in [I-P]. */
1389 bool
1391 {
1393 {
1395 /* An unsigned 8 bit constant. */
1398 /* The constant zero. */
1401 /* A signed 16 bit constant. */
1404 /* A shifted signed 16 bit constant appropriate for LDAH. */
1408 /* A constant that can be AND'ed with using a ZAP insn. */
1411 /* A complemented unsigned 8 bit constant. */
1414 /* A negated unsigned 8 bit constant. */
1417 /* The constant 1, 2 or 3. */
1422 }
1423 }
1425 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1426 matches for C in [GH]. */
1428 bool
1430 {
1432 {
1434 /* The floating point zero constant. */
1439 /* A valid operand of a ZAP insn. */
1446 }
1447 }
1449 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1450 matches for C. */
1452 bool
1454 {
1456 {
1473 }
1474 }
1476 /* Return 1 if this function can directly return via $26. */
1478 int
1480 {
1482 && reload_completed
1487 }
1489 /* Return the ADDR_VEC associated with a tablejump insn. */
1491 rtx
1493 {
1494 rtx tmp;
1506 }
1508 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1510 rtx
1512 {
1516 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1517 there for edge frequency counts from profile data. */
1520 {
1526 {
1532 count++;
1536 }
1537 }
1540 }
1542 /* Return the TLS model to use for SYMBOL. */
1544 static enum tls_model
1546 {
1553 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1558 }
1559 \f
1560 /* Return true if the function DECL will share the same GP as any
1561 function in the current unit of translation. */
1563 static bool
1565 {
1566 /* Functions that are not local can be overridden, and thus may
1567 not share the same gp. */
1571 /* If -msmall-data is in effect, assume that there is only one GP
1572 for the module, and so any local symbol has this property. We
1573 need explicit relocations to be able to enforce this for symbols
1574 not defined in this unit of translation, however. */
1578 /* Functions that are not external are defined in this UoT. */
1579 /* ??? Irritatingly, static functions not yet emitted are still
1580 marked "external". Apply this to non-static functions only. */
1582 }
1584 /* Return true if EXP should be placed in the small data section. */
1586 static bool
1588 {
1589 /* We want to merge strings, so we never consider them small data. */
1594 {
1599 }
1600 else
1601 {
1604 /* If this is an incomplete type with size 0, then we can't put it
1605 in sdata because it might be too big when completed. */
1608 }
1611 }
1613 #if TARGET_ABI_OPEN_VMS
1614 static bool
1616 {
1623 }
1625 #define LINKAGE_SYMBOL_REF_P(X) \
1626 ((GET_CODE (X) == SYMBOL_REF \
1627 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1628 || (GET_CODE (X) == CONST \
1629 && GET_CODE (XEXP (X, 0)) == PLUS \
1630 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1631 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1632 #endif
1634 /* legitimate_address_p recognizes an RTL expression that is a valid
1635 memory address for an instruction. The MODE argument is the
1636 machine mode for the MEM expression that wants to use this address.
1638 For Alpha, we have either a constant address or the sum of a
1639 register and a constant address, or just a register. For DImode,
1640 any of those forms can be surrounded with an AND that clear the
1641 low-order three bits; this is an "unaligned" access. */
1643 bool
1645 {
1646 /* If this is an ldq_u type address, discard the outer AND. */
1653 /* Discard non-paradoxical subregs. */
1659 /* Unadorned general registers are valid. */
1661 && (strict
1666 /* Constant addresses (i.e. +/- 32k) are valid. */
1670 #if TARGET_ABI_OPEN_VMS
1673 #endif
1675 /* Register plus a small constant offset is valid. */
1677 {
1681 /* Discard non-paradoxical subregs. */
1688 {
1698 }
1702 }
1704 /* If we're managing explicit relocations, LO_SUM is valid, as
1705 are small data symbols. */
1707 {
1712 {
1716 /* Discard non-paradoxical subregs. */
1722 /* Must have a valid base register. */
1724 && (strict
1729 /* The symbol must be local. */
1734 }
1735 }
1738 }
1740 /* Build the SYMBOL_REF for __tls_get_addr. */
1744 static rtx
1746 {
1750 }
1752 /* Try machine-dependent ways of modifying an illegitimate address
1753 to be legitimate. If we find one, return the new, valid address. */
1755 rtx
1758 {
1759 HOST_WIDE_INT addend;
1761 /* If the address is (plus reg const_int) and the CONST_INT is not a
1762 valid offset, compute the high part of the constant and add it to
1763 the register. Then our address is (plus temp low-part-const). */
1768 {
1772 }
1774 /* If the address is (const (plus FOO const_int)), find the low-order
1775 part of the CONST_INT. Then load FOO plus any high-order part of the
1776 CONST_INT into a register. Our address is (plus reg low-part-const).
1777 This is done to reduce the number of GOT entries. */
1782 {
1786 }
1788 /* If we have a (plus reg const), emit the load as in (2), then add
1789 the two registers, and finally generate (plus reg low-part-const) as
1790 our address. */
1797 {
1803 }
1805 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1807 {
1811 {
1852 UNSPEC_TLSLDM_CALL);
1859 {
1864 }
1866 {
1871 }
1893 {
1898 }
1900 }
1903 {
1906 else
1907 {
1913 }
1914 }
1915 }
1919 split_addend:
1920 {
1938 }
1939 }
1941 /* We do not allow indirect calls to be optimized into sibling calls, nor
1942 can we allow a call to a function with a different GP to be optimized
1943 into a sibcall. */
1945 static bool
1947 {
1948 /* Can't do indirect tail calls, since we don't know if the target
1949 uses the same GP. */
1953 /* Otherwise, we can make a tail call if the target function shares
1954 the same GP. */
1956 }
1958 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1959 small symbolic operand until after reload. At which point we need
1960 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1961 so that sched2 has the proper dependency information. */
1963 static int
1965 {
1968 /* Don't re-split. */
1973 }
1975 int
1977 {
1979 }
1981 static int
1983 {
1986 /* Don't re-split. */
1991 {
1995 }
1998 }
2000 rtx
2002 {
2006 }
2008 /* Indicate that INSN cannot be duplicated. This is true for any insn
2009 that we've marked with gpdisp relocs, since those have to stay in
2010 1-1 correspondence with one another.
2012 Technically we could copy them if we could set up a mapping from one
2013 sequence number to another, across the set of insns to be duplicated.
2014 This seems overly complicated and error-prone since interblock motion
2015 from sched-ebb could move one of the pair of insns to a different block.
2017 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2018 then they'll be in a different block from their ldgp. Which could lead
2019 the bb reorder code to think that it would be ok to copy just the block
2020 containing the call and branch to the block containing the ldgp. */
2022 static bool
2024 {
2029 else
2031 }
2034 /* Try a machine-dependent way of reloading an illegitimate address
2035 operand. If we find one, push the reload and return the new rtx. */
2037 rtx
2042 {
2043 /* We must recognize output that we have already generated ourselves. */
2049 {
2054 }
2056 /* We wish to handle large displacements off a base register by
2057 splitting the addend across an ldah and the mem insn. This
2058 cuts number of extra insns needed from 3 to 1. */
2064 {
2067 HOST_WIDE_INT high
2070 /* Check for 32-bit overflow. */
2074 /* Reload the high part into a base reg; leave the low part
2075 in the mem directly. */
2085 }
2088 }
2089 \f
2090 /* Compute a (partial) cost for rtx X. Return true if the complete
2091 cost has been computed, and false if subexpressions should be
2092 scanned. In either case, *TOTAL contains the cost result. */
2094 static bool
2096 {
2101 {
2102 /* If this is an 8-bit constant, return zero since it can be used
2103 nearly anywhere with no cost. If it is a valid operand for an
2104 ADD or AND, likewise return 0 if we know it will be used in that
2105 context. Otherwise, return 2 since it might be used there later.
2106 All other constants take at least two insns. */
2109 {
2112 }
2113 /* FALLTHRU */
2123 else
2135 /* Estimate of cost for call_pal rduniq. */
2137 else
2138 /* Otherwise we do a load from the GOT. */
2148 {
2152 }
2160 else
2167 {
2170 }
2171 /* FALLTHRU */
2181 else
2193 else
2203 {
2206 }
2207 /* FALLTHRU */
2211 {
2214 }
2215 /* FALLTHRU */
2228 }
2229 }
2230 \f
2231 /* REF is an alignable memory location. Place an aligned SImode
2232 reference into *PALIGNED_MEM and the number of bits to shift into
2233 *PBITNUM. SCRATCH is a free register for use in reloading out
2234 of range stack slots. */
2236 void
2238 {
2239 rtx base;
2247 {
2252 }
2253 else
2254 {
2256 }
2261 *paligned_mem
2267 else
2269 }
2271 /* Similar, but just get the address. Handle the two reload cases.
2272 Add EXTRA_OFFSET to the address we return. */
2274 rtx
2276 {
2277 rtx base;
2285 {
2290 }
2291 else
2292 {
2294 }
2300 }
2302 /* On the Alpha, all (non-symbolic) constants except zero go into
2303 a floating-point register via memory. Note that we cannot
2304 return anything that is not a subset of CLASS, and that some
2305 symbolic constants cannot be dropped to memory. */
2307 enum reg_class
2309 {
2310 /* Zero is present in any register class. */
2314 /* These sorts of constants we can easily drop to memory. */
2316 {
2322 }
2324 /* All other kinds of constants should not (and in the case of HIGH
2325 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2326 secondary reload. */
2331 }
2333 /* Loading and storing HImode or QImode values to and from memory
2334 usually requires a scratch register. The exceptions are loading
2335 QImode and HImode from an aligned address to a general register
2336 unless byte instructions are permitted.
2338 We also cannot load an unaligned address or a paradoxical SUBREG
2339 into an FP register.
2341 We also cannot do integral arithmetic into FP regs, as might result
2342 from register elimination into a DImode fp register. */
2344 enum reg_class
2347 {
2349 {
2356 {
2359 }
2360 }
2363 {
2375 }
2378 }
2379 \f
2380 /* Subfunction of the following function. Update the flags of any MEM
2381 found in part of X. */
2383 static void
2385 {
2389 {
2396 unchanging_p);
2401 unchanging_p);
2406 unchanging_p);
2408 unchanging_p);
2415 /* Sadly, we cannot use alias sets because the extra aliasing
2416 produced by the AND interferes. Given that two-byte quantities
2417 are the only thing we would be able to differentiate anyway,
2418 there does not seem to be any point in convoluting the early
2419 out of the alias check. */
2424 }
2425 }
2427 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2428 generated to perform a memory operation, look for any MEMs in either
2429 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2430 volatile flags from REF into each of the MEMs found. If REF is not
2431 a MEM, don't do anything. */
2433 void
2435 {
2445 /* This is only called from alpha.md, after having had something
2446 generated from one of the insn patterns. So if everything is
2447 zero, the pattern is already up-to-date. */
2452 }
2453 \f
2454 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2456 static rtx
2459 {
2462 /* Use a pseudo if highly optimizing and still generating RTL. */
2463 rtx subtarget
2467 /* If this is a sign-extended 32-bit constant, we can do this in at most
2468 three insns, so do it if we have enough insns left. We always have
2469 a sign-extended 32-bit constant when compiling on a narrow machine. */
2473 {
2479 /* If HIGH will be interpreted as negative but the constant is
2480 positive, we must adjust it to do two ldha insns. */
2483 {
2487 }
2490 {
2491 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2492 but that meant that we can't handle INT_MIN on 32-bit machines
2493 (like NT/Alpha), because we recurse indefinitely through
2494 emit_move_insn to gen_movdi. So instead, since we know exactly
2495 what we want, create it explicitly. */
2501 }
2503 {
2506 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2507 This means that if we go through expand_binop, we'll try to
2508 generate extensions, etc, which will require new pseudos, which
2509 will fail during some split phases. The SImode add patterns
2510 still exist, but are not named. So build the insns by hand. */
2513 {
2520 }
2528 }
2529 }
2531 /* If we couldn't do it that way, try some other methods. But if we have
2532 no instructions left, don't bother. Likewise, if this is SImode and
2533 we can't make pseudos, we can't do anything since the expand_binop
2534 and expand_unop calls will widen and try to make pseudos. */
2539 /* Next, see if we can load a related constant and then shift and possibly
2540 negate it to get the constant we want. Try this once each increasing
2541 numbers of insns. */
2544 {
2545 /* First, see if minus some low bits, we've an easy load of
2546 high bits. */
2554 /* Next try complementing. */
2558 /* Next try to form a constant and do a left shift. We can do this
2559 if some low-order bits are zero; the exact_log2 call below tells
2560 us that information. The bits we are shifting out could be any
2561 value, but here we'll just try the 0- and sign-extended forms of
2562 the constant. To try to increase the chance of having the same
2563 constant in more than one insn, start at the highest number of
2564 bits to shift, but try all possibilities in case a ZAPNOT will
2565 be useful. */
2578 /* Now try high-order zero bits. Here we try the shifted-in bits as
2579 all zero and all ones. Be careful to avoid shifting outside the
2580 mode and to avoid shifting outside the host wide int size. */
2581 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2582 confuse the recursive call and set all of the high 32 bits. */
2592 i)))
2597 /* Now try high-order 1 bits. We get that with a sign-extension.
2598 But one bit isn't enough here. Be careful to avoid shifting outside
2599 the mode and to avoid shifting outside the host wide int size. */
2609 i)))
2613 }
2615 #if HOST_BITS_PER_WIDE_INT == 64
2616 /* Finally, see if can load a value into the target that is the same as the
2617 constant except that all bytes that are 0 are changed to be 0xff. If we
2618 can, then we can do a ZAPNOT to obtain the desired constant. */
2625 /* We are only called for SImode and DImode. If this is SImode, ensure that
2626 we are sign extended to a full word. */
2635 #endif
2638 }
2640 /* Try to output insns to set TARGET equal to the constant C if it can be
2641 done in less than N insns. Do all computations in MODE. Returns the place
2642 where the output has been placed if it can be done and the insns have been
2643 emitted. If it would take more than N insns, zero is returned and no
2644 insns and emitted. */
2646 rtx
2649 {
2654 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2655 can't load this constant in one insn, do this in DImode. */
2659 {
2662 }
2664 /* Try 1 insn, then 2, then up to N. */
2666 {
2669 {
2675 }
2676 }
2678 /* Allow for the case where we changed the mode of TARGET. */
2683 }
2685 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2686 fall back to a straight forward decomposition. We do this to avoid
2687 exponential run times encountered when looking for longer sequences
2688 with alpha_emit_set_const. */
2690 rtx
2692 {
2695 /* Decompose the entire word */
2696 #if HOST_BITS_PER_WIDE_INT >= 64
2708 #else
2720 #endif
2722 /* Construct the high word */
2724 {
2728 }
2729 else
2732 /* Shift it into place */
2735 /* Add in the low bits. */
2742 }
2744 /* Expand a move instruction; return true if all work is done.
2745 We don't handle non-bwx subword loads here. */
2747 bool
2749 {
2750 /* If the output is not a register, the input must be. */
2755 /* Allow legitimize_address to perform some simplifications. */
2757 {
2758 rtx tmp;
2760 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2761 compiled at the end of compilation. In the meantime, someone can
2762 re-encode-section-info on some symbol changing it e.g. from global
2763 to local-not-small. If this happens, we'd have emitted a plain
2764 load rather than a high+losum load and not recognize the insn.
2766 So if rtl inlining is in effect, we delay the global/not-global
2767 decision until rest_of_compilation by wrapping it in an
2768 UNSPEC_SYMBOL. */
2770 && rtx_equal_function_value_matters
2772 {
2775 }
2779 {
2784 }
2785 }
2787 /* Early out for non-constants and valid constants. */
2791 /* Split large integers. */
2794 {
2799 {
2802 }
2804 {
2807 }
2808 else
2809 {
2812 }
2821 {
2826 }
2827 }
2829 /* Otherwise we've nothing left but to drop the thing to memory. */
2832 {
2836 }
2837 else
2840 }
2842 /* Expand a non-bwx QImode or HImode move instruction;
2843 return true if all work is done. */
2845 bool
2847 {
2848 /* If the output is not a register, the input must be. */
2852 /* Handle four memory cases, unaligned and aligned for either the input
2853 or the output. The only case where we can be called during reload is
2854 for aligned loads; all other cases require temporaries. */
2864 {
2866 {
2868 {
2870 ? gen_reload_inqi_help
2874 }
2875 else
2876 {
2883 ? gen_aligned_loadqi
2886 }
2887 }
2888 else
2889 {
2890 /* Don't pass these as parameters since that makes the generated
2891 code depend on parameter evaluation order which will cause
2892 bootstrap failures. */
2897 ? gen_unaligned_loadqi
2904 }
2906 }
2916 {
2918 {
2927 }
2928 else
2929 {
2934 ? gen_unaligned_storeqi
2941 }
2943 }
2946 }
2948 /* Generate an unsigned DImode to FP conversion. This is the same code
2949 optabs would emit if we didn't have TFmode patterns.
2951 For SFmode, this is the only construction I've found that can pass
2952 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2953 intermediates will work, because you'll get intermediate rounding
2954 that ruins the end result. Some of this could be fixed by turning
2955 on round-to-positive-infinity, but that requires diddling the fpsr,
2956 which kills performance. I tried turning this around and converting
2957 to a negative number, so that I could turn on /m, but either I did
2958 it wrong or there's something else cause I wound up with the exact
2959 same single-bit error. There is a branch-less form of this same code:
2961 srl $16,1,$1
2962 and $16,1,$2
2963 cmplt $16,0,$3
2964 or $1,$2,$2
2965 cmovge $16,$16,$2
2966 itoft $3,$f10
2967 itoft $2,$f11
2968 cvtqs $f11,$f11
2969 adds $f11,$f11,$f0
2970 fcmoveq $f10,$f11,$f0
2972 I'm not using it because it's the same number of instructions as
2973 this branch-full form, and it has more serialized long latency
2974 instructions on the critical path.
2976 For DFmode, we can avoid rounding errors by breaking up the word
2977 into two pieces, converting them separately, and adding them back:
2979 LC0: .long 0,0x5f800000
2981 itoft $16,$f11
2982 lda $2,LC0
2983 cmplt $16,0,$1
2984 cpyse $f11,$f31,$f10
2985 cpyse $f31,$f11,$f11
2986 s4addq $1,$2,$1
2987 lds $f12,0($1)
2988 cvtqt $f10,$f10
2989 cvtqt $f11,$f11
2990 addt $f12,$f10,$f0
2991 addt $f0,$f11,$f0
2993 This doesn't seem to be a clear-cut win over the optabs form.
2994 It probably all depends on the distribution of numbers being
2995 converted -- in the optabs form, all but high-bit-set has a
2996 much lower minimum execution time. */
2998 void
3000 {
3028 }
3030 /* Generate the comparison for a conditional branch. */
3032 rtx
3034 {
3038 rtx tem;
3041 {
3045 /* X_floating library comparison functions return
3046 -1 unordered
3047 0 false
3048 1 true
3049 Convert the compare against the raw return value. */
3052 {
3069 }
3074 }
3076 /* The general case: fold the comparison code to the types of compares
3077 that we have, choosing the branch as necessary. */
3079 {
3082 /* We have these compares: */
3088 /* These must be reversed. */
3093 /* For FP, we swap them, for INT, we reverse them. */
3095 {
3099 }
3100 else
3101 {
3104 }
3109 }
3112 {
3115 {
3116 /* When we are not as concerned about non-finite values, and we
3117 are comparing against zero, we can branch directly. */
3121 {
3122 /* Undo the swap we probably did just above. */
3126 }
3127 }
3128 else
3129 {
3130 /* ??? We mark the branch mode to be CCmode to prevent the
3131 compare and branch from being combined, since the compare
3132 insn follows IEEE rules that the branch does not. */
3134 }
3135 }
3136 else
3137 {
3140 /* The following optimizations are only for signed compares. */
3142 {
3143 /* Whee. Compare and branch against 0 directly. */
3147 /* If the constants doesn't fit into an immediate, but can
3148 be generated by lda/ldah, we adjust the argument and
3149 compare against zero, so we can use beq/bne directly. */
3151 {
3157 {
3160 }
3161 }
3162 }
3168 }
3170 /* Emit an initial compare instruction, if necessary. */
3173 {
3176 }
3178 /* Zero the operands. */
3181 /* Return the branch comparison. */
3183 }
3185 /* Certain simplifications can be done to make invalid setcc operations
3186 valid. Return the final comparison, or NULL if we can't work. */
3188 rtx
3190 {
3194 rtx tmp;
3196 /* Zero the operands. */
3200 {
3204 /* X_floating library comparison functions return
3205 -1 unordered
3206 0 false
3207 1 true
3208 Convert the compare against the raw return value. */
3212 else
3223 else
3225 }
3230 /* The general case: fold the comparison code to the types of compares
3231 that we have, choosing the branch as necessary. */
3235 {
3238 /* We have these compares. */
3246 /* FALLTHRU */
3254 /* These normally need swapping, but for integer zero we have
3255 special patterns that recognize swapped operands. */
3266 }
3269 {
3274 }
3276 /* Emit an initial compare instruction, if necessary. */
3278 {
3287 }
3289 /* Return the setcc comparison. */
3291 }
3294 /* Rewrite a comparison against zero CMP of the form
3295 (CODE (cc0) (const_int 0)) so it can be written validly in
3296 a conditional move (if_then_else CMP ...).
3297 If both of the operands that set cc0 are nonzero we must emit
3298 an insn to perform the compare (it can't be done within
3299 the conditional move). */
3301 rtx
3303 {
3309 enum machine_mode cmp_mode
3314 rtx tem;
3316 /* Zero the operands. */
3320 {
3326 /* If we have fp<->int register move instructions, do a cmov by
3327 performing the comparison in fp registers, and move the
3328 zero/nonzero value to integer registers, where we can then
3329 use a normal cmov, or vice-versa. */
3332 {
3334 /* We have these compares. */
3339 /* This must be reversed. */
3344 /* These normally need swapping, but for integer zero we have
3345 special patterns that recognize swapped operands. */
3348 else
3349 {
3353 }
3358 }
3370 }
3372 /* We may be able to use a conditional move directly.
3373 This avoids emitting spurious compares. */
3379 /* We can't put the comparison inside the conditional move;
3380 emit a compare instruction and put that inside the
3381 conditional move. Make sure we emit only comparisons we have;
3382 swap or reverse as necessary. */
3388 {
3390 /* We have these compares: */
3394 /* This must be reversed. */
3400 /* These must be swapped. */
3402 {
3405 }
3410 }
3413 {
3418 }
3420 /* ??? We mark the branch mode to be CCmode to prevent the compare
3421 and cmov from being combined, since the compare insn follows IEEE
3422 rules that the cmov does not. */
3429 }
3431 /* Simplify a conditional move of two constants into a setcc with
3432 arithmetic. This is done with a splitter since combine would
3433 just undo the work if done during code generation. It also catches
3434 cases we wouldn't have before cse. */
3436 int
3439 {
3451 {
3455 }
3459 {
3463 else
3465 }
3466 /* Below, we must be careful to use copy_rtx on target and subtarget
3467 in intermediate insns, as they may be a subreg rtx, which may not
3468 be shared. */
3471 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3472 viable over a longer latency cmove. On EV5, the E0 slot is a
3473 scarce resource, and on EV4 shift has the same latency as a cmove. */
3475 {
3482 }
3484 {
3489 }
3491 {
3492 rtx add_op;
3499 else
3500 {
3503 {
3508 }
3509 else
3511 }
3512 }
3513 else
3517 }
3518 \f
3519 /* Look up the function X_floating library function name for the
3520 given operation. */
3524 {
3525 struct xfloating_op
3526 {
3529 };
3532 {
3548 };
3551 {
3567 };
3573 /* How irritating. Nothing to key off for the table. Hardcode
3574 knowledge of the G_floating routines. */
3576 {
3578 {
3583 }
3584 else
3585 {
3590 }
3591 }
3595 else
3603 }
3605 /* Most X_floating operations take the rounding mode as an argument.
3606 Compute that here. */
3608 static int
3611 {
3615 {
3631 /* XXX For reference, round to +inf is mode = 3. */
3632 }
3638 }
3640 /* Emit an X_floating library function call.
3642 Note that these functions do not follow normal calling conventions:
3643 TFmode arguments are passed in two integer registers (as opposed to
3644 indirect); TFmode return values appear in R16+R17.
3646 FUNC is the function name to call.
3647 TARGET is where the output belongs.
3648 OPERANDS are the inputs.
3649 NOPERANDS is the count of inputs.
3650 EQUIV is the expression equivalent for the function.
3651 */
3653 static void
3656 {
3663 {
3665 {
3679 /* FALLTHRU */
3687 }
3691 }
3694 {
3706 }
3717 }
3719 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3721 void
3723 {
3737 }
3739 /* Emit an X_floating library function call for a comparison. */
3741 static rtx
3743 {
3753 /* ??? Strange mode for equiv because what's actually returned
3754 is -1,0,1, not a proper boolean value. */
3759 }
3761 /* Emit an X_floating library function call for a conversion. */
3763 void
3765 {
3779 {
3792 }
3798 }
3800 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3801 OP[0] into OP[0,1]. Naturally, output operand ordering is
3802 little-endian. */
3804 void
3806 {
3808 {
3811 }
3813 {
3816 }
3819 else
3823 {
3826 }
3828 {
3831 }
3832 else
3834 }
3836 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3837 op2 is a register containing the sign bit, operation is the
3838 logical operation to be performed. */
3840 void
3842 {
3844 rtx scratch;
3849 /* Detect three flavors of operand overlap. */
3854 {
3857 else
3859 }
3864 /* ??? If the destination overlaps both source tf and high_bit, then
3865 assume source tf is dead in its entirety and use the other half
3866 for a scratch register. Otherwise "scratch" is just the proper
3867 destination register. */
3873 {
3877 }
3878 }
3879 \f
3880 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3881 unaligned data:
3883 unsigned: signed:
3884 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3885 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3886 lda r3,X(r11) lda r3,X+2(r11)
3887 extwl r1,r3,r1 extql r1,r3,r1
3888 extwh r2,r3,r2 extqh r2,r3,r2
3889 or r1.r2.r1 or r1,r2,r1
3890 sra r1,48,r1
3892 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3893 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3894 lda r3,X(r11) lda r3,X(r11)
3895 extll r1,r3,r1 extll r1,r3,r1
3896 extlh r2,r3,r2 extlh r2,r3,r2
3897 or r1.r2.r1 addl r1,r2,r1
3899 quad: ldq_u r1,X(r11)
3900 ldq_u r2,X+7(r11)
3901 lda r3,X(r11)
3902 extql r1,r3,r1
3903 extqh r2,r3,r2
3904 or r1.r2.r1
3905 */
3907 void
3910 {
3924 /* AND addresses cannot be in any alias set, since they may implicitly
3925 alias surrounding code. Ideally we'd have some alias set that
3926 covered all types except those with alignment 8 or higher. */
3943 {
3952 }
3954 {
3960 /* We must use tgt here for the target. Alpha-vms port fails if we use
3961 addr for the target, because addr is marked as a pointer and combine
3962 knows that pointers are always sign-extended 32 bit values. */
3966 }
3967 else
3968 {
3970 {
3973 {
3991 }
3993 }
3994 else
3995 {
3999 {
4017 }
4018 }
4023 }
4027 }
4029 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4031 void
4034 {
4046 /* AND addresses cannot be in any alias set, since they may implicitly
4047 alias surrounding code. Ideally we'd have some alias set that
4048 covered all types except those with alignment 8 or higher. */
4065 {
4069 {
4071 {
4081 }
4084 }
4087 {
4092 {
4096 }
4100 }
4103 }
4104 else
4105 {
4109 {
4114 {
4124 }
4125 }
4130 {
4135 {
4139 }
4143 }
4144 }
4147 {
4150 }
4153 {
4156 }
4157 else
4158 {
4159 /* Must store high before low for degenerate case of aligned. */
4162 }
4163 }
4165 /* The block move code tries to maximize speed by separating loads and
4166 stores at the expense of register pressure: we load all of the data
4167 before we store it back out. There are two secondary effects worth
4168 mentioning, that this speeds copying to/from aligned and unaligned
4169 buffers, and that it makes the code significantly easier to write. */
4171 #define MAX_MOVE_WORDS 8
4173 /* Load an integral number of consecutive unaligned quadwords. */
4175 static void
4178 {
4183 HOST_WIDE_INT i;
4189 /* Generate all the tmp registers we need. */
4191 {
4194 }
4200 /* Load up all of the source data. */
4202 {
4206 im8));
4209 }
4214 im8));
4218 /* Extract the half-word fragments. Unfortunately DEC decided to make
4219 extxh with offset zero a noop instead of zeroing the register, so
4220 we must take care of that edge condition ourselves with cmov. */
4228 {
4230 {
4233 }
4234 else
4235 {
4238 }
4242 const0_rtx),
4244 }
4246 /* Merge the half-words into whole words. */
4248 {
4251 }
4252 }
4254 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4255 may be NULL to store zeros. */
4257 static void
4260 {
4266 HOST_WIDE_INT i;
4272 /* Generate all the tmp registers we need. */
4285 im8));
4292 /* Load up the destination end bits. */
4296 /* Shift the input data into place. */
4301 {
4303 {
4305 {
4308 }
4309 else
4310 {
4313 }
4314 }
4316 {
4319 OPTAB_WIDEN);
4320 }
4321 }
4323 /* Split and merge the ends with the destination data. */
4325 {
4328 }
4329 else
4330 {
4333 }
4336 {
4341 }
4343 /* Store it all. */
4346 else
4349 {
4354 im8));
4357 }
4360 else
4362 }
4365 /* Expand string/block move operations.
4367 operands[0] is the pointer to the destination.
4368 operands[1] is the pointer to the source.
4369 operands[2] is the number of bytes to move.
4370 operands[3] is the alignment. */
4372 int
4374 {
4384 rtx tmp;
4392 /* Look for additional alignment information from recorded register info. */
4400 {
4405 {
4412 }
4413 }
4421 {
4426 {
4433 }
4434 }
4436 /* Load the entire block into registers. */
4438 {
4443 /* Don't use the existing register if we're reading more than
4444 is held in the register. Nor if there is not a mode that
4445 handles the exact size. */
4450 {
4452 {
4456 }
4457 else
4461 }
4463 /* No appropriate mode; fall back on memory. */
4467 }
4471 {
4484 }
4487 {
4500 }
4503 {
4515 }
4518 {
4523 }
4526 {
4528 {
4535 }
4537 {
4542 }
4543 }
4546 {
4551 }
4553 src_done:
4558 /* Now save it back out again. */
4563 {
4569 {
4571 {
4575 }
4578 {
4579 /* Undo the subregging done above when copying between
4580 two TImode registers. */
4584 else
4585 {
4586 rtx seq;
4596 }
4600 }
4601 }
4603 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4604 /* ??? Optimize mode < dst_mode with strict_low_part. */
4606 /* No appropriate mode; fall back on memory. We can speed things
4607 up by recognizing extra alignment information. */
4611 }
4613 /* Write out the data in whatever chunks reading the source allowed. */
4615 {
4617 {
4621 i++;
4622 }
4623 }
4626 {
4627 /* If the source has remaining DImode regs, write them out in
4628 two pieces. */
4630 {
4639 i++;
4640 }
4643 {
4647 i++;
4648 }
4649 }
4652 {
4653 /* Write out a remaining block of words using unaligned methods. */
4661 else
4667 }
4669 /* Due to the above, this won't be aligned. */
4670 /* ??? If we have more than one of these, consider constructing full
4671 words in registers and using alpha_expand_unaligned_store_words. */
4673 {
4676 i++;
4677 }
4681 {
4683 i++;
4685 }
4686 else
4688 {
4690 i++;
4692 }
4695 {
4697 i++;
4699 }
4701 dst_done:
4707 }
4709 int
4711 {
4719 rtx tmp;
4727 /* Look for stricter alignment. */
4734 {
4739 {
4746 }
4747 }
4749 {
4754 {
4757 }
4759 /* No appropriate mode; fall back on memory. */
4762 }
4764 /* Handle an unaligned prefix first. */
4767 {
4768 #if HOST_BITS_PER_WIDE_INT >= 64
4769 /* Given that alignofs is bounded by align, the only time BWX could
4770 generate three stores is for a 7 byte fill. Prefer two individual
4771 stores over a load/mask/store sequence. */
4775 {
4779 HOST_WIDE_INT mask;
4786 {
4790 }
4791 else
4792 {
4795 }
4802 }
4803 #endif
4806 {
4811 }
4813 {
4818 }
4820 {
4825 }
4827 /* If we've not used the extra lead alignment information by now,
4828 we won't be able to. Downgrade align to match what's left over. */
4830 {
4833 }
4834 }
4836 /* Handle a block of contiguous long-words. */
4839 {
4844 const0_rtx);
4848 }
4850 /* If the block is large and appropriately aligned, emit a single
4851 store followed by a sequence of stq_u insns. */
4854 {
4855 rtx orig_dsta;
4867 {
4868 rtx mem
4875 }
4877 /* Depending on the alignment, the first stq_u may have overlapped
4878 with the initial stl, which means that the last stq_u didn't
4879 write as much as it would appear. Leave those questionable bytes
4880 unaccounted for. */
4883 }
4885 /* Handle a smaller block of aligned words. */
4889 {
4894 const0_rtx);
4898 }
4900 /* An unaligned block uses stq_u stores for as many as possible. */
4903 {
4910 }
4912 /* Next clean up any trailing pieces. */
4914 #if HOST_BITS_PER_WIDE_INT >= 64
4915 /* Count the number of bits in BYTES for which aligned stores could
4916 be emitted. */
4922 /* If we have appropriate alignment (and it wouldn't take too many
4923 instructions otherwise), mask out the bytes we need. */
4925 {
4927 {
4929 HOST_WIDE_INT mask;
4941 }
4943 {
4945 HOST_WIDE_INT mask;
4957 }
4958 }
4959 #endif
4962 {
4966 }
4969 {
4971 {
4974 const0_rtx);
4978 }
4980 {
4984 }
4985 }
4988 {
4992 }
4995 }
4997 /* Returns a mask so that zap(x, value) == x & mask. */
4999 rtx
5001 {
5002 rtx result;
5006 {
5010 {
5014 }
5017 }
5019 {
5023 {
5027 }
5030 {
5034 }
5037 }
5038 else
5042 }
5044 void
5048 {
5053 else
5058 else
5062 }
5063 \f
5064 /* Adjust the cost of a scheduling dependency. Return the new cost of
5065 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5067 static int
5069 {
5072 /* If the dependence is an anti-dependence, there is no cost. For an
5073 output dependence, there is sometimes a cost, but it doesn't seem
5074 worth handling those few cases. */
5078 /* If we can't recognize the insns, we can't really do anything. */
5085 /* Bring in the user-defined memory latency. */
5091 /* Everything else handled in DFA bypasses now. */
5094 }
5096 /* The number of instructions that can be issued per cycle. */
5098 static int
5100 {
5102 }
5104 static int
5106 {
5108 }
5110 /* How many alternative schedules to try. This should be as wide as the
5111 scheduling freedom in the DFA, but no wider. Making this value too
5112 large results extra work for the scheduler.
5114 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5115 alternative schedules. For EV5, we can choose between E0/E1 and
5116 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5118 static int
5120 {
5122 }
5123 \f
5124 /* Machine-specific function data. */
5127 {
5128 /* For unicosmk. */
5129 /* List of call information words for calls from this function. */
5134 /* List of deferred case vectors. */
5137 /* For OSF. */
5139 };
5141 /* How to allocate a 'struct machine_function'. */
5145 {
5148 }
5150 /* Functions to save and restore alpha_return_addr_rtx. */
5152 /* Start the ball rolling with RETURN_ADDR_RTX. */
5154 rtx
5156 {
5161 }
5163 /* Return or create a pseudo containing the gp value for the current
5164 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5166 rtx
5168 {
5173 }
5175 static int
5177 {
5178 rtx top;
5188 }
5190 \f
5191 /* Return the trap mode suffix applicable to the current
5192 instruction, or NULL. */
5196 {
5200 {
5216 {
5224 }
5229 {
5238 }
5243 {
5252 }
5254 }
5256 }
5258 /* Return the rounding mode suffix applicable to the current
5259 instruction, or NULL. */
5263 {
5267 {
5272 {
5281 }
5286 }
5288 }
5290 /* Locate some local-dynamic symbol still in use by this function
5291 so that we can print its name in some movdi_er_tlsldm pattern. */
5293 static int
5295 {
5300 {
5303 }
5306 }
5310 {
5311 rtx insn;
5322 }
5324 /* Print an operand. Recognize special options, documented below. */
5326 void
5328 {
5332 {
5334 /* Print the assembler name of the current function. */
5343 {
5351 }
5354 /* Generates single precision instruction suffix. */
5359 /* Generates double precision instruction suffix. */
5364 /* Generates a nop after a noreturn call at the very end of the
5365 function. */
5385 else
5390 {
5394 {
5397 }
5399 {
5402 }
5405 else
5406 {
5409 }
5413 }
5417 /* If this operand is the constant zero, write it as "$31". */
5422 else
5427 /* Similar, but for floating-point. */
5432 else
5437 /* Write the 1's complement of a constant. */
5445 /* Write 1 << C, for a constant C. */
5453 /* Write the high-order 16 bits of a constant, sign-extended. */
5461 /* Write the low-order 16 bits of a constant, sign-extended. */
5470 /* Write mask for ZAP insn. */
5472 {
5474 HOST_WIDE_INT value;
5489 }
5492 {
5500 }
5501 else
5506 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5520 /* Similar, except do it from the mask. */
5522 {
5526 {
5529 }
5531 {
5534 }
5536 {
5539 }
5541 {
5544 }
5545 }
5550 {
5553 }
5558 /* Write the constant value divided by 8 for little-endian mode or
5559 (56 - value) / 8 for big-endian mode. */
5569 WORDS_BIG_ENDIAN
5575 /* Same, except compute (64 - c) / 8 */
5586 {
5587 /* On Unicos/Mk systems: use a DEX expression if the symbol
5588 clashes with a register name. */
5592 else
5594 }
5598 /* Write out comparison name. */
5599 {
5618 else
5620 }
5624 /* Write the divide or modulus operator. */
5626 {
5642 }
5646 /* Write "_u" for unaligned access. */
5657 {
5659 {
5667 }
5668 }
5669 else
5675 }
5676 }
5678 void
5680 {
5689 {
5692 }
5695 {
5700 {
5703 {
5715 }
5718 }
5719 else
5720 {
5724 }
5735 else
5741 }
5751 #if TARGET_ABI_OPEN_VMS
5753 {
5756 }
5760 {
5765 }
5766 #endif
5768 else
5772 }
5773 \f
5774 /* Emit RTL insns to initialize the variable parts of a trampoline at
5775 TRAMP. FNADDR is an RTX for the address of the function's pure
5776 code. CXT is an RTX for the static chain value for the function.
5778 The three offset parameters are for the individual template's
5779 layout. A JMPOFS < 0 indicates that the trampoline does not
5780 contain instructions at all.
5782 We assume here that a function will be called many more times than
5783 its address is taken (e.g., it might be passed to qsort), so we
5784 take the trouble to initialize the "hint" field in the JMP insn.
5785 Note that the hint field is PC (new) + 4 * bits 13:0. */
5787 void
5790 {
5792 /* VMS really uses DImode pointers in memory at this point. */
5795 #ifdef POINTERS_EXTEND_UNSIGNED
5798 #endif
5800 /* Store function address and CXT. */
5806 /* This has been disabled since the hint only has a 32k range, and in
5807 no existing OS is the stack within 32k of the text segment. */
5809 {
5810 /* Compute hint value. */
5813 OPTAB_WIDEN);
5819 /* Merge in the hint. */
5824 OPTAB_WIDEN);
5826 }
5828 #ifdef TRANSFER_FROM_TRAMPOLINE
5831 #endif
5835 }
5836 \f
5837 /* Determine where to put an argument to a function.
5838 Value is zero to push the argument on the stack,
5839 or a hard register in which to store the argument.
5841 MODE is the argument's machine mode.
5842 TYPE is the data type of the argument (as a tree).
5843 This is null for libcalls where that information may
5844 not be available.
5845 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5846 the preceding args and about the function being called.
5847 NAMED is nonzero if this argument is a named parameter
5848 (otherwise it is an extra parameter matching an ellipsis).
5850 On Alpha the first 6 words of args are normally in registers
5851 and the rest are pushed. */
5853 rtx
5856 {
5860 /* Don't get confused and pass small structures in FP registers. */
5863 else
5864 {
5865 #ifdef ENABLE_CHECKING
5866 /* With SPLIT_COMPLEX_ARGS, we shouldn't see any raw complex
5867 values here. */
5870 #endif
5872 /* Set up defaults for FP operands passed in FP registers, and
5873 integral operands passed in integer registers. */
5876 else
5878 }
5880 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5881 the three platforms, so we can't avoid conditional compilation. */
5882 #if TARGET_ABI_OPEN_VMS
5883 {
5890 }
5891 #elif TARGET_ABI_UNICOSMK
5892 {
5895 /* If this is the last argument, generate the call info word (CIW). */
5896 /* ??? We don't include the caller's line number in the CIW because
5897 I don't know how to determine it if debug infos are turned off. */
5899 {
5901 HOST_WIDE_INT lo;
5902 HOST_WIDE_INT hi;
5903 rtx ciw;
5913 else
5916 #if HOST_BITS_PER_WIDE_INT == 32
5918 #else
5922 #endif
5926 UNSPEC_UMK_LOAD_CIW);
5927 }
5935 {
5941 /* The argument fits in two registers. Note that we still need to
5942 reserve a register for empty structures. */
5947 else
5948 {
5952 }
5953 }
5954 }
5955 #elif TARGET_ABI_OSF
5956 {
5961 /* VOID is passed as a special flag for "last argument". */
5968 }
5969 #else
5970 #error Unhandled ABI
5971 #endif
5974 }
5976 /* Return true if TYPE must be returned in memory, instead of in registers. */
5978 static bool
5980 {
5985 {
5988 /* All aggregates are returned in memory. */
5991 }
5995 {
5997 /* Pass all float vectors in memory, like an aggregate. */
6001 /* We judge complex floats on the size of their element,
6002 not the size of the whole type. */
6013 /* ??? We get called on all sorts of random stuff from
6014 aggregate_value_p. We can't abort, but it's not clear
6015 what's safe to return. Pretend it's a struct I guess. */
6017 }
6019 /* Otherwise types must fit in one register. */
6021 }
6023 /* Define how to find the value returned by a function. VALTYPE is the
6024 data type of the value (as a tree). If the precise function being
6025 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6026 MODE is set instead of VALTYPE for libcalls.
6028 On Alpha the value is found in $0 for integer functions and
6029 $f0 for floating-point functions. */
6031 rtx
6034 {
6038 #ifdef ENABLE_CHECKING
6041 #endif
6048 {
6050 /* Do the same thing as PROMOTE_MODE. */
6052 /* FALLTHRU */
6064 {
6067 return gen_rtx_PARALLEL
6074 }
6078 }
6081 }
6083 static tree
6085 {
6096 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6098 /* Dummy field to prevent alignment warnings. */
6105 integer_type_node);
6110 ptr_type_node);
6118 }
6120 /* Perform any needed actions needed for a function that is receiving a
6121 variable number of arguments. */
6123 static void
6126 tree type ATTRIBUTE_UNUSED,
6128 {
6129 #if TARGET_ABI_UNICOSMK
6130 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6131 arguments on the stack. Unfortunately, it doesn't always store the first
6132 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6133 with stdargs as we always have at least one named argument there. */
6136 {
6138 {
6141 }
6143 }
6144 #elif TARGET_ABI_OPEN_VMS
6145 /* For VMS, we allocate space for all 6 arg registers plus a count.
6147 However, if NO registers need to be saved, don't allocate any space.
6148 This is not only because we won't need the space, but because AP
6149 includes the current_pretend_args_size and we don't want to mess up
6150 any ap-relative addresses already made. */
6152 {
6154 {
6157 }
6159 }
6160 #else
6161 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6162 only push those that are remaining. However, if NO registers need to
6163 be saved, don't allocate any space. This is not only because we won't
6164 need the space, but because AP includes the current_pretend_args_size
6165 and we don't want to mess up any ap-relative addresses already made.
6167 If we are not to use the floating-point registers, save the integer
6168 registers where we would put the floating-point registers. This is
6169 not the most efficient way to implement varargs with just one register
6170 class, but it isn't worth doing anything more efficient in this rare
6171 case. */
6178 {
6180 rtx tmp;
6194 }
6196 #endif
6197 }
6199 void
6201 {
6202 HOST_WIDE_INT offset;
6211 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6212 up by 48, storing fp arg registers in the first 48 bytes, and the
6213 integer arg registers in the next 48 bytes. This is only done,
6214 however, if any integer registers need to be stored.
6216 If no integer registers need be stored, then we must subtract 48
6217 in order to account for the integer arg registers which are counted
6218 in argsize above, but which are not actually stored on the stack.
6219 Must further be careful here about structures straddling the last
6220 integer argument register; that futzes with pretend_args_size,
6221 which changes the meaning of AP. */
6225 else
6229 {
6237 }
6238 else
6239 {
6258 }
6259 }
6261 rtx
6263 {
6264 rtx addr;
6277 else
6281 type_size,
6294 /* If the type could not be passed in registers, skip the block
6295 reserved for the registers. */
6297 {
6303 }
6311 {
6314 }
6316 {
6322 /* ??? Most irritatingly, we're not returning the value here,
6323 but the address. Since real_part and imag_part are not
6324 necessarily contiguous, we must copy to local storage. */
6334 }
6336 {
6347 }
6362 {
6365 }
6368 }
6369 \f
6370 /* Builtins. */
6372 enum alpha_builtin
6373 {
6374 ALPHA_BUILTIN_CMPBGE,
6375 ALPHA_BUILTIN_EXTBL,
6376 ALPHA_BUILTIN_EXTWL,
6377 ALPHA_BUILTIN_EXTLL,
6378 ALPHA_BUILTIN_EXTQL,
6379 ALPHA_BUILTIN_EXTWH,
6380 ALPHA_BUILTIN_EXTLH,
6381 ALPHA_BUILTIN_EXTQH,
6382 ALPHA_BUILTIN_INSBL,
6383 ALPHA_BUILTIN_INSWL,
6384 ALPHA_BUILTIN_INSLL,
6385 ALPHA_BUILTIN_INSQL,
6386 ALPHA_BUILTIN_INSWH,
6387 ALPHA_BUILTIN_INSLH,
6388 ALPHA_BUILTIN_INSQH,
6389 ALPHA_BUILTIN_MSKBL,
6390 ALPHA_BUILTIN_MSKWL,
6391 ALPHA_BUILTIN_MSKLL,
6392 ALPHA_BUILTIN_MSKQL,
6393 ALPHA_BUILTIN_MSKWH,
6394 ALPHA_BUILTIN_MSKLH,
6395 ALPHA_BUILTIN_MSKQH,
6396 ALPHA_BUILTIN_UMULH,
6397 ALPHA_BUILTIN_ZAP,
6398 ALPHA_BUILTIN_ZAPNOT,
6399 ALPHA_BUILTIN_AMASK,
6400 ALPHA_BUILTIN_IMPLVER,
6401 ALPHA_BUILTIN_RPCC,
6402 ALPHA_BUILTIN_THREAD_POINTER,
6403 ALPHA_BUILTIN_SET_THREAD_POINTER,
6405 /* TARGET_MAX */
6406 ALPHA_BUILTIN_MINUB8,
6407 ALPHA_BUILTIN_MINSB8,
6408 ALPHA_BUILTIN_MINUW4,
6409 ALPHA_BUILTIN_MINSW4,
6410 ALPHA_BUILTIN_MAXUB8,
6411 ALPHA_BUILTIN_MAXSB8,
6412 ALPHA_BUILTIN_MAXUW4,
6413 ALPHA_BUILTIN_MAXSW4,
6414 ALPHA_BUILTIN_PERR,
6415 ALPHA_BUILTIN_PKLB,
6416 ALPHA_BUILTIN_PKWB,
6417 ALPHA_BUILTIN_UNPKBL,
6418 ALPHA_BUILTIN_UNPKBW,
6420 /* TARGET_CIX */
6421 ALPHA_BUILTIN_CTTZ,
6422 ALPHA_BUILTIN_CTLZ,
6423 ALPHA_BUILTIN_CTPOP,
6425 ALPHA_BUILTIN_max
6426 };
6429 CODE_FOR_builtin_cmpbge,
6430 CODE_FOR_builtin_extbl,
6431 CODE_FOR_builtin_extwl,
6432 CODE_FOR_builtin_extll,
6433 CODE_FOR_builtin_extql,
6434 CODE_FOR_builtin_extwh,
6435 CODE_FOR_builtin_extlh,
6436 CODE_FOR_builtin_extqh,
6437 CODE_FOR_builtin_insbl,
6438 CODE_FOR_builtin_inswl,
6439 CODE_FOR_builtin_insll,
6440 CODE_FOR_builtin_insql,
6441 CODE_FOR_builtin_inswh,
6442 CODE_FOR_builtin_inslh,
6443 CODE_FOR_builtin_insqh,
6444 CODE_FOR_builtin_mskbl,
6445 CODE_FOR_builtin_mskwl,
6446 CODE_FOR_builtin_mskll,
6447 CODE_FOR_builtin_mskql,
6448 CODE_FOR_builtin_mskwh,
6449 CODE_FOR_builtin_msklh,
6450 CODE_FOR_builtin_mskqh,
6451 CODE_FOR_umuldi3_highpart,
6452 CODE_FOR_builtin_zap,
6453 CODE_FOR_builtin_zapnot,
6454 CODE_FOR_builtin_amask,
6455 CODE_FOR_builtin_implver,
6456 CODE_FOR_builtin_rpcc,
6457 CODE_FOR_load_tp,
6458 CODE_FOR_set_tp,
6460 /* TARGET_MAX */
6461 CODE_FOR_builtin_minub8,
6462 CODE_FOR_builtin_minsb8,
6463 CODE_FOR_builtin_minuw4,
6464 CODE_FOR_builtin_minsw4,
6465 CODE_FOR_builtin_maxub8,
6466 CODE_FOR_builtin_maxsb8,
6467 CODE_FOR_builtin_maxuw4,
6468 CODE_FOR_builtin_maxsw4,
6469 CODE_FOR_builtin_perr,
6470 CODE_FOR_builtin_pklb,
6471 CODE_FOR_builtin_pkwb,
6472 CODE_FOR_builtin_unpkbl,
6473 CODE_FOR_builtin_unpkbw,
6475 /* TARGET_CIX */
6476 CODE_FOR_builtin_cttz,
6477 CODE_FOR_builtin_ctlz,
6478 CODE_FOR_builtin_ctpop
6479 };
6481 struct alpha_builtin_def
6482 {
6486 };
6491 };
6502 };
6539 };
6541 static void
6543 {
6545 tree ftype;
6566 long_integer_type_node,
6584 }
6586 /* Expand an expression EXP that calls a built-in function,
6587 with result going to TARGET if that's convenient
6588 (and in mode MODE if that's convenient).
6589 SUBTARGET may be used as the target for computing one of EXP's operands.
6590 IGNORE is nonzero if the value is to be ignored. */
6592 static rtx
6594 rtx subtarget ATTRIBUTE_UNUSED,
6597 {
6598 #define MAX_ARGS 2
6617 arglist;
6619 {
6634 }
6637 {
6643 }
6646 {
6653 else
6661 }
6668 else
6670 }
6671 \f
6672 /* This page contains routines that are used to determine what the function
6673 prologue and epilogue code will do and write them out. */
6675 /* Compute the size of the save area in the stack. */
6677 /* These variables are used for communication between the following functions.
6678 They indicate various things about the current function being compiled
6679 that are used to tell what kind of prologue, epilogue and procedure
6680 descriptor to generate. */
6682 /* Nonzero if we need a stack procedure. */
6686 /* Register number (either FP or SP) that is used to unwind the frame. */
6689 /* Register number used to save FP. We need not have one for RA since
6690 we don't modify it for register procedures. This is only defined
6691 for register frame procedures. */
6694 /* Register number used to reference objects off our PV. */
6697 /* Compute register masks for saved registers. */
6699 static void
6701 {
6706 /* Irritatingly, there are two kinds of thunks -- those created with
6707 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
6708 through the regular part of the compiler. In the
6709 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
6710 info, but assemble_start_function wants to output .frame and
6711 .mask directives. */
6713 {
6717 }
6722 /* One for every register we have to save. */
6727 {
6730 else
6732 }
6734 /* We need to restore these for the handler. */
6736 {
6738 {
6743 }
6745 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6746 avoid hackery in unwind-dw2.c, we need to actively store a
6747 zero in the prologue of _Unwind_RaiseException et al. */
6749 }
6751 /* If any register spilled, then spill the return address also. */
6752 /* ??? This is required by the Digital stack unwind specification
6753 and isn't needed if we're doing Dwarf2 unwinding. */
6759 }
6761 int
6763 {
6771 {
6774 }
6775 else
6776 {
6780 sa_size++;
6781 }
6784 {
6785 /* We might not need to generate a frame if we don't make any calls
6786 (including calls to __T3E_MISMATCH if this is a vararg function),
6787 don't have any local variables which require stack slots, don't
6788 use alloca and have not determined that we need a frame for other
6789 reasons. */
6791 alpha_procedure_type
6793 || current_function_outgoing_args_size
6798 /* Always reserve space for saving callee-saved registers if we
6799 need a frame as required by the calling convention. */
6802 }
6804 {
6805 /* Start by assuming we can use a register procedure if we don't
6806 make any calls (REG_RA not used) or need to save any
6807 registers and a stack procedure if we do. */
6812 else
6815 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6816 made the final decision on stack procedure vs register procedure. */
6820 /* Decide whether to refer to objects off our PV via FP or PV.
6821 If we need FP for something else or if we receive a nonlocal
6822 goto (which expects PV to contain the value), we must use PV.
6823 Otherwise, start by assuming we can use FP. */
6825 vms_base_regno
6826 = (frame_pointer_needed
6827 || current_function_has_nonlocal_label
6832 /* If we want to copy PV into FP, we need to find some register
6833 in which to save FP. */
6846 /* Stack unwinding should be done via FP unless we use it for PV. */
6850 /* If this is a stack procedure, allow space for saving FP and RA. */
6853 }
6854 else
6855 {
6856 /* Our size must be even (multiple of 16 bytes). */
6858 sa_size++;
6859 }
6862 }
6864 /* Define the offset between two registers, one to be eliminated,
6865 and the other its replacement, at the start of a routine. */
6867 HOST_WIDE_INT
6870 {
6871 HOST_WIDE_INT ret;
6877 ;
6882 else
6886 }
6888 int
6890 {
6893 }
6895 int
6897 {
6900 }
6902 #if TARGET_ABI_OPEN_VMS
6905 {
6906 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6911 };
6913 #endif
6915 static int
6917 {
6919 }
6921 int
6923 {
6925 }
6927 static int
6929 {
6930 rtx insn;
6932 /* The GP being variable is an OSF abi thing. */
6936 /* We need the gp to load the address of __mcount. */
6940 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6944 /* The nonlocal receiver pattern assumes that the gp is valid for
6945 the nested function. Reasonable because it's almost always set
6946 correctly already. For the cases where that's wrong, make sure
6947 the nested function loads its gp on entry. */
6951 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6952 Even if we are a static function, we still need to do this in case
6953 our address is taken and passed to something like qsort. */
6967 }
6969 \f
6970 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6971 sequences. */
6973 static rtx
6975 {
6977 rtx insn;
6985 {
6988 {
6991 }
6993 }
6994 else
6995 {
6998 }
7000 }
7002 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7004 /* Write function prologue. */
7006 /* On vms we have two kinds of functions:
7008 - stack frame (PROC_STACK)
7009 these are 'normal' functions with local vars and which are
7010 calling other functions
7011 - register frame (PROC_REGISTER)
7012 keeps all data in registers, needs no stack
7014 We must pass this to the assembler so it can generate the
7015 proper pdsc (procedure descriptor)
7016 This is done with the '.pdesc' command.
7018 On not-vms, we don't really differentiate between the two, as we can
7019 simply allocate stack without saving registers. */
7021 void
7023 {
7024 /* Registers to save. */
7027 /* Stack space needed for pushing registers clobbered by us. */
7028 HOST_WIDE_INT sa_size;
7029 /* Complete stack size needed. */
7030 HOST_WIDE_INT frame_size;
7031 /* Offset from base reg to register save area. */
7032 HOST_WIDE_INT reg_offset;
7042 + frame_size
7045 /* We have to allocate space for the DSIB if we generate a frame. */
7050 else
7052 + sa_size
7058 else
7063 /* Emit an insn to reload GP, if needed. */
7065 {
7069 }
7071 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7072 the call to mcount ourselves, rather than having the linker do it
7073 magically in response to -pg. Since _mcount has special linkage,
7074 don't represent the call as a call. */
7081 /* Adjust the stack by the frame size. If the frame size is > 4096
7082 bytes, we need to be sure we probe somewhere in the first and last
7083 4096 bytes (we can probably get away without the latter test) and
7084 every 8192 bytes in between. If the frame size is > 32768, we
7085 do this in a loop. Otherwise, we generate the explicit probe
7086 instructions.
7088 Note that we are only allowed to adjust sp once in the prologue. */
7091 {
7093 {
7096 do
7102 /* We only have to do this probe if we aren't saving registers. */
7105 }
7112 }
7113 else
7114 {
7115 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7116 number of 8192 byte blocks to probe. We then probe each block
7117 in the loop and then set SP to the proper location. If the
7118 amount remaining is > 4096, we have to do one more probe if we
7119 are not saving any registers. */
7125 rtx seq;
7131 /* Because of the difficulty in emitting a new basic block this
7132 late in the compilation, generate the loop as a single insn. */
7136 {
7140 }
7143 {
7144 /* For NT stack unwind (done by 'reverse execution'), it's
7145 not OK to take the result of a loop, even though the value
7146 is already in ptr, so we reload it via a single operation
7147 and subtract it to sp.
7149 Yes, that's correct -- we have to reload the whole constant
7150 into a temporary via ldah+lda then subtract from sp. To
7151 ensure we get ldah+lda, we use a special pattern. */
7160 ptr));
7161 }
7162 else
7163 {
7166 }
7168 /* This alternative is special, because the DWARF code cannot
7169 possibly intuit through the loop above. So we invent this
7170 note it looks at instead. */
7180 }
7183 {
7184 /* Cope with very large offsets to the register save area. */
7187 {
7189 HOST_WIDE_INT bias;
7193 else
7199 }
7201 /* Save regs in stack order. Beginning with VMS PV. */
7203 {
7207 }
7209 /* Save register RA next. */
7211 {
7217 }
7219 /* Now save any other registers required to be saved. */
7222 {
7227 }
7229 /* Store a zero if requested for unwinding. */
7231 {
7245 }
7249 {
7254 }
7255 }
7257 {
7258 /* The standard frame on the T3E includes space for saving registers.
7259 We just have to use it. We don't have to save the return address and
7260 the old frame pointer here - they are saved in the DSIB. */
7265 {
7267 reg_offset));
7271 }
7274 {
7276 reg_offset));
7280 }
7281 }
7284 {
7286 /* Register frame procedures save the fp.
7287 ?? Ought to have a dwarf2 save for this. */
7289 hard_frame_pointer_rtx);
7299 /* If we have to allocate space for outgoing args, do it now. */
7301 {
7302 rtx seq
7304 plus_constant
7306 - (ALPHA_ROUND
7309 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7310 if ! frame_pointer_needed. Setting the bit will change the CFA
7311 computation rule to use sp again, which would be wrong if we had
7312 frame_pointer_needed, as this means sp might move unpredictably
7313 later on.
7315 Also, note that
7316 frame_pointer_needed
7317 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7318 and
7319 current_function_outgoing_args_size != 0
7320 => alpha_procedure_type != PT_NULL,
7322 so when we are not setting the bit here, we are guaranteed to
7323 have emitted an FRP frame pointer update just before. */
7325 }
7326 }
7328 {
7329 /* If we need a frame pointer, set it from the stack pointer. */
7331 {
7334 else
7335 /* This must always be the last instruction in the
7336 prologue, thus we emit a special move + clobber. */
7339 }
7340 }
7342 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7343 the prologue, for exception handling reasons, we cannot do this for
7344 any insn that might fault. We could prevent this for mems with a
7345 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7346 have to prevent all such scheduling with a blockage.
7348 Linux, on the other hand, never bothered to implement OSF/1's
7349 exception handling, and so doesn't care about such things. Anyone
7350 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7354 }
7356 /* Output the textual info surrounding the prologue. */
7358 void
7360 tree decl ATTRIBUTE_UNUSED)
7361 {
7364 /* Stack space needed for pushing registers clobbered by us. */
7365 HOST_WIDE_INT sa_size;
7366 /* Complete stack size needed. */
7368 /* Offset from base reg to register save area. */
7369 HOST_WIDE_INT reg_offset;
7373 /* Don't emit an extern directive for functions defined in the same file. */
7375 {
7376 tree name_tree;
7379 }
7388 + frame_size
7395 else
7397 + sa_size
7403 else
7408 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7409 We have to do that before the .ent directive as we cannot switch
7410 files within procedures with native ecoff because line numbers are
7411 linked to procedure descriptors.
7412 Outputting the lineno helps debugging of one line functions as they
7413 would otherwise get no line number at all. Please note that we would
7414 like to put out last_linenum from final.c, but it is not accessible. */
7417 {
7418 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7421 #endif
7422 #ifdef ASM_OUTPUT_SOURCE_LINE
7426 #endif
7427 }
7429 /* Issue function start and label. */
7432 {
7437 /* If the function needs GP, we'll write the "..ng" label there.
7438 Otherwise, do it here. */
7440 && ! alpha_function_needs_gp
7442 {
7446 }
7447 }
7453 /* For public functions, the label must be globalized by appending an
7454 additional colon. */
7466 {
7467 /* Set flags in procedure descriptor to request IEEE-conformant
7468 math-library routines. The value we set it to is PDSC_EXC_IEEE
7469 (/usr/include/pdsc.h). */
7471 }
7473 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7477 /* Describe our frame. If the frame size is larger than an integer,
7478 print it as zero to avoid an assembler error. We won't be
7479 properly describing such a frame, but that's the best we can do. */
7481 ;
7485 vms_unwind_regno,
7487 reg_offset);
7490 (frame_pointer_needed
7493 current_function_pretend_args_size);
7495 /* Describe which registers were spilled. */
7497 ;
7499 {
7501 /* ??? Does VMS care if mask contains ra? The old code didn't
7502 set it, so I don't here. */
7508 }
7510 {
7512 {
7519 }
7524 }
7526 #if TARGET_ABI_OPEN_VMS
7527 /* Ifdef'ed cause link_section are only available then. */
7536 #endif
7537 }
7539 /* Emit the .prologue note at the scheduled end of the prologue. */
7541 static void
7543 {
7545 ;
7553 }
7555 /* Write function epilogue. */
7557 /* ??? At some point we will want to support full unwind, and so will
7558 need to mark the epilogue as well. At the moment, we just confuse
7559 dwarf2out. */
7560 #undef FRP
7561 #define FRP(exp) exp
7563 void
7565 {
7566 /* Registers to save. */
7569 /* Stack space needed for pushing registers clobbered by us. */
7570 HOST_WIDE_INT sa_size;
7571 /* Complete stack size needed. */
7572 HOST_WIDE_INT frame_size;
7573 /* Offset from base reg to register save area. */
7574 HOST_WIDE_INT reg_offset;
7578 rtx eh_ofs;
7587 + frame_size
7594 else
7596 + sa_size
7601 {
7604 else
7606 }
7607 else
7612 fp_is_frame_pointer
7620 else
7624 {
7625 /* If we have a frame pointer, restore SP from it. */
7631 /* Cope with very large offsets to the register save area. */
7633 {
7635 HOST_WIDE_INT bias;
7639 else
7646 }
7648 /* Restore registers in order, excepting a true frame pointer. */
7660 {
7663 else
7664 {
7668 }
7670 }
7677 {
7682 }
7683 }
7685 {
7686 /* Restore callee-saved general-purpose registers. */
7692 {
7694 reg_offset));
7698 }
7702 {
7704 reg_offset));
7708 }
7710 /* Restore the return address from the DSIB. */
7715 }
7718 {
7722 {
7726 }
7728 /* If the stack size is large, begin computation into a temporary
7729 register so as not to interfere with a potential fp restore,
7730 which must be consecutive with an SP restore. */
7735 {
7739 }
7741 {
7747 else
7748 {
7751 }
7753 }
7754 else
7755 {
7759 {
7760 /* We can't drop new things to memory this late, afaik,
7761 so build it up by pieces. */
7766 }
7767 }
7769 /* From now on, things must be in order. So emit blockages. */
7771 /* Restore the frame pointer. */
7773 {
7779 }
7781 {
7786 }
7788 {
7792 }
7794 /* Restore the stack pointer. */
7798 else
7801 }
7802 else
7803 {
7805 {
7809 }
7811 {
7812 /* Decrement the frame pointer if the function does not have a
7813 frame. */
7818 }
7819 }
7820 }
7821 \f
7822 /* Output the rest of the textual info surrounding the epilogue. */
7824 void
7826 {
7827 /* End the function. */
7829 {
7833 }
7836 #if TARGET_ABI_OPEN_VMS
7838 #endif
7840 /* Output jump tables and the static subroutine information block. */
7842 {
7845 }
7846 }
7848 #if TARGET_ABI_OSF
7849 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7851 In order to avoid the hordes of differences between generated code
7852 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7853 lots of code loading up large constants, generate rtl and emit it
7854 instead of going straight to text.
7856 Not sure why this idea hasn't been explored before... */
7858 static void
7861 tree function)
7862 {
7866 /* We always require a valid GP. */
7870 /* Find the "this" pointer. If the function returns a structure,
7871 the structure return pointer is in $16. */
7874 else
7877 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7878 entire constant for the add. */
7882 {
7887 }
7888 else
7889 {
7893 }
7895 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7897 {
7906 {
7909 }
7910 else
7911 {
7916 }
7919 else
7924 }
7926 /* Generate a tail call to the target function. */
7928 {
7931 }
7937 /* Run just enough of rest_of_compilation to get the insns emitted.
7938 There's not really enough bulk here to make other passes such as
7939 instruction scheduling worth while. Note that use_thunk calls
7940 assemble_start_function and assemble_end_function. */
7947 }
7949 \f
7950 /* Debugging support. */
7954 /* Count the number of sdb related labels are generated (to find block
7955 start and end boundaries). */
7959 /* Next label # for each statement. */
7963 /* Count the number of .file directives, so that .loc is up to date. */
7967 /* Name of the file containing the current function. */
7971 /* Offsets to alpha virtual arg/local debugging pointers. */
7975 \f
7976 /* Emit a new filename to a stream. */
7978 void
7980 {
7985 {
7994 }
7997 {
8002 }
8006 {
8009 else
8010 {
8014 }
8018 }
8019 }
8021 /* Emit a linenumber to a stream. */
8023 void
8025 {
8027 {
8028 /* mips-tfile doesn't understand .stabd directives. */
8032 }
8033 else
8035 }
8036 \f
8037 /* Structure to show the current status of registers and memory. */
8039 struct shadow_summary
8040 {
8046 };
8048 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8049 to the summary structure. SET is nonzero if the insn is setting the
8050 object, otherwise zero. */
8052 static void
8054 {
8062 {
8063 /* ??? Note that this case would be incorrect if the Alpha had a
8064 ZERO_EXTRACT in SET_DEST. */
8093 {
8101 {
8104 else
8106 }
8107 else
8108 {
8111 else
8113 }
8114 }
8120 else
8123 /* Find the regs used in memory address computation: */
8132 /* Handle common unary and binary ops for efficiency. */
8154 {
8169 }
8170 }
8171 }
8173 /* Ensure a sufficient number of `trapb' insns are in the code when
8174 the user requests code with a trap precision of functions or
8175 instructions.
8177 In naive mode, when the user requests a trap-precision of
8178 "instruction", a trapb is needed after every instruction that may
8179 generate a trap. This ensures that the code is resumption safe but
8180 it is also slow.
8182 When optimizations are turned on, we delay issuing a trapb as long
8183 as possible. In this context, a trap shadow is the sequence of
8184 instructions that starts with a (potentially) trap generating
8185 instruction and extends to the next trapb or call_pal instruction
8186 (but GCC never generates call_pal by itself). We can delay (and
8187 therefore sometimes omit) a trapb subject to the following
8188 conditions:
8190 (a) On entry to the trap shadow, if any Alpha register or memory
8191 location contains a value that is used as an operand value by some
8192 instruction in the trap shadow (live on entry), then no instruction
8193 in the trap shadow may modify the register or memory location.
8195 (b) Within the trap shadow, the computation of the base register
8196 for a memory load or store instruction may not involve using the
8197 result of an instruction that might generate an UNPREDICTABLE
8198 result.
8200 (c) Within the trap shadow, no register may be used more than once
8201 as a destination register. (This is to make life easier for the
8202 trap-handler.)
8204 (d) The trap shadow may not include any branch instructions. */
8206 static void
8208 {
8221 {
8223 {
8225 {
8227 exception_nesting++;
8233 exception_nesting--;
8242 }
8243 }
8245 {
8247 {
8251 }
8253 {
8255 {
8264 {
8266 /* Annoyingly, get_attr_trap will abort on these. */
8275 {
8276 /* (c) would be violated */
8278 }
8280 /* Combine shadow with summary of current insn: */
8291 {
8292 /* (a) would be violated (also takes care of (b)) */
8299 }
8309 }
8310 }
8311 else
8312 {
8313 close_shadow:
8322 }
8323 }
8324 }
8331 {
8335 }
8336 }
8337 }
8338 \f
8339 /* Alpha can only issue instruction groups simultaneously if they are
8340 suitably aligned. This is very processor-specific. */
8347 };
8358 };
8360 static enum alphaev4_pipe
8362 {
8369 {
8399 }
8400 }
8402 static enum alphaev5_pipe
8404 {
8411 {
8448 }
8449 }
8451 /* IN_USE is a mask of the slots currently filled within the insn group.
8452 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8453 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8455 LEN is, of course, the length of the group in bytes. */
8457 static rtx
8459 {
8470 {
8475 {
8477 /* Force complex instructions to start new groups. */
8481 /* If this is a completely unrecognized insn, its an asm.
8482 We don't know how long it is, so record length as -1 to
8483 signal a needed realignment. */
8486 else
8492 {
8496 }
8497 else
8503 {
8507 }
8519 }
8522 /* Haifa doesn't do well scheduling branches. */
8526 next:
8532 /* Let Haifa tell us where it thinks insn group boundaries are. */
8538 }
8540 next_and_done:
8543 done:
8547 }
8549 /* IN_USE is a mask of the slots currently filled within the insn group.
8550 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8551 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8553 LEN is, of course, the length of the group in bytes. */
8555 static rtx
8557 {
8568 {
8573 {
8575 /* Force complex instructions to start new groups. */
8579 /* If this is a completely unrecognized insn, its an asm.
8580 We don't know how long it is, so record length as -1 to
8581 signal a needed realignment. */
8584 else
8588 /* ??? Most of the places below, we would like to abort, as
8589 it would indicate an error either in Haifa, or in the
8590 scheduling description. Unfortunately, Haifa never
8591 schedules the last instruction of the BB, so we don't
8592 have an accurate TI bit to go off. */
8595 {
8599 }
8600 else
8606 {
8610 }
8622 {
8626 }
8627 else
8648 }
8651 /* Haifa doesn't do well scheduling branches. */
8652 /* ??? If this is predicted not-taken, slotting continues, except
8653 that no more IBR, FBR, or JSR insns may be slotted. */
8657 next:
8663 /* Let Haifa tell us where it thinks insn group boundaries are. */
8669 }
8671 next_and_done:
8674 done:
8678 }
8680 static rtx
8682 {
8684 rtx nop;
8687 {
8690 }
8692 {
8695 }
8697 {
8700 }
8701 else
8706 }
8708 static rtx
8710 {
8712 rtx nop;
8715 {
8718 }
8720 {
8723 }
8725 {
8728 }
8729 else
8734 }
8736 /* The instruction group alignment main loop. */
8738 static void
8742 {
8743 /* ALIGN is the known alignment for the insn group. */
8745 /* OFS is the offset of the current insn in the insn group. */
8750 /* Let shorten branches care for assigning alignments to code labels. */
8757 else
8766 {
8769 /* When we see a label, resync alignment etc. */
8771 {
8775 {
8778 }
8784 }
8786 /* Handle complex instructions special. */
8788 {
8789 /* Asms will have length < 0. This is a signal that we have
8790 lost alignment knowledge. Assume, however, that the asm
8791 will not mis-align instructions. */
8793 {
8797 }
8798 }
8800 /* If the known alignment is smaller than the recognized insn group,
8801 realign the output. */
8803 {
8811 /* Can't realign between a call and its gp reload. */
8814 {
8818 }
8819 }
8821 /* If the group won't fit in the same INT16 as the previous,
8822 we need to add padding to keep the group together. Rather
8823 than simply leaving the insn filling to the assembler, we
8824 can make use of the knowledge of what sorts of instructions
8825 were issued in the previous group to make sure that all of
8826 the added nops are really free. */
8828 {
8830 rtx where;
8832 /* Insert nops before labels, branches, and calls to truly merge
8833 the execution of the nops with the previous instruction group. */
8836 {
8838 {
8842 }
8845 }
8846 else
8849 do
8853 }
8858 }
8859 }
8860 \f
8861 /* Machine dependent reorg pass. */
8863 static void
8865 {
8869 /* Due to the number of extra trapb insns, don't bother fixing up
8870 alignment when trap precision is instruction. Moreover, we can
8871 only do our job when sched2 is run. */
8875 {
8880 }
8881 }
8882 \f
8883 #if !TARGET_ABI_UNICOSMK
8885 #ifdef HAVE_STAMP_H
8886 #include <stamp.h>
8887 #endif
8889 static void
8891 {
8892 #ifdef OBJECT_FORMAT_ELF
8893 /* If emitting dwarf2 debug information, we cannot generate a .file
8894 directive to start the file, as it will conflict with dwarf2out
8895 file numbers. So it's only useful when emitting mdebug output. */
8897 #endif
8900 #ifdef MS_STAMP
8902 #endif
8914 : (TARGET_CPU_EV5
8917 }
8918 #endif
8920 #ifdef OBJECT_FORMAT_ELF
8922 /* Switch to the section to which we should output X. The only thing
8923 special we do here is to honor small data. */
8925 static void
8928 {
8930 /* ??? Consider using mergeable sdata sections. */
8932 else
8934 }
8937 \f
8938 /* Structure to collect function names for final output in link section. */
8939 /* Note that items marked with GTY can't be ifdef'ed out. */
8945 {
8947 rtx linkage;
8950 };
8953 {
8956 links;
8957 };
8960 splay_tree alpha_links_tree;
8962 splay_tree alpha_funcs_tree;
8966 #if TARGET_ABI_OPEN_VMS
8968 /* Return the VMS argument type corresponding to MODE. */
8970 enum avms_arg_type
8972 {
8974 {
8981 }
8982 }
8984 /* Return an rtx for an integer representing the VMS Argument Information
8985 register value. */
8987 rtx
8989 {
8997 }
8998 \f
8999 /* Make (or fake) .linkage entry for function call.
9001 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9003 Return an SYMBOL_REF rtx for the linkage. */
9005 rtx
9007 {
9008 splay_tree_node node;
9012 name++;
9015 {
9020 splay_tree_compare_pointers);
9030 }
9033 {
9034 /* Is this name already defined? */
9038 {
9041 {
9042 /* Defined here but external assumed. */
9045 }
9046 else
9047 {
9048 /* Used here but unused assumed. */
9051 }
9053 }
9054 }
9055 else
9061 /* Assume external if no definition. */
9064 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9067 /* Construct a SYMBOL_REF for us to call. */
9068 {
9076 }
9082 }
9084 rtx
9086 {
9087 splay_tree_node cfunnode;
9099 {
9100 splay_tree_node lnode;
9102 /* Is this name already defined? */
9107 }
9108 else
9112 {
9121 name++;
9130 {
9133 }
9145 }
9149 else
9154 else
9156 }
9158 static int
9160 {
9167 {
9169 {
9170 /* Local and used */
9172 }
9173 else
9174 {
9175 /* External and used, request code address. */
9177 }
9178 }
9179 else
9180 {
9182 {
9183 /* Local and used, build linkage pair. */
9186 }
9187 else
9188 {
9189 /* External and used, request linkage pair. */
9191 }
9192 }
9195 }
9197 static void
9199 {
9200 splay_tree_node node;
9219 {
9221 /* splay_tree_delete (func->links); */
9222 }
9223 }
9225 /* Given a decl, a section name, and whether the decl initializer
9226 has relocs, choose attributes for the section. */
9228 #define SECTION_VMS_OVERLAY SECTION_FORGET
9229 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9230 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9232 static unsigned int
9234 {
9248 }
9250 /* Switch to an arbitrary section NAME with attributes as specified
9251 by FLAGS. ALIGN specifies any known alignment requirements for
9252 the section; 0 if the default should be used. */
9254 static void
9256 {
9270 }
9272 /* Record an element in the table of global constructors. SYMBOL is
9273 a SYMBOL_REF of the function to be called; PRIORITY is a number
9274 between 0 and MAX_INIT_PRIORITY.
9276 Differs from default_ctors_section_asm_out_constructor in that the
9277 width of the .ctors entry is always 64 bits, rather than the 32 bits
9278 used by a normal pointer. */
9280 static void
9282 {
9286 }
9288 static void
9290 {
9294 }
9295 #else
9297 rtx
9300 {
9302 }
9304 rtx
9306 tree cfundecl ATTRIBUTE_UNUSED,
9309 {
9311 }
9314 \f
9315 #if TARGET_ABI_UNICOSMK
9317 /* Define the offset between two registers, one to be eliminated, and the
9318 other its replacement, at the start of a routine. */
9320 int
9322 {
9340 else
9342 }
9344 /* Output the module name for .ident and .end directives. We have to strip
9345 directories and add make sure that the module name starts with a letter
9346 or '$'. */
9348 static void
9350 {
9356 /* CAM only accepts module names that start with a letter or '$'. We
9357 prefix the module name with a '$' if necessary. */
9364 }
9366 /* Output the definition of a common variable. */
9368 void
9370 {
9371 tree name_tree;
9380 /* Mark the symbol as defined in this module. */
9383 }
9385 #define SECTION_PUBLIC SECTION_MACH_DEP
9386 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9389 static unsigned int
9392 {
9399 {
9406 }
9407 else
9414 }
9416 /* Generate a section name for decl and associate it with the
9417 declaration. */
9419 static void
9421 {
9433 {
9436 /* It is essential that we prefix the section name here because
9437 otherwise the section names generated for constructors and
9438 destructors confuse collect2. */
9443 }
9446 else
9447 {
9453 }
9454 }
9456 /* Switch to an arbitrary section NAME with attributes as specified
9457 by FLAGS. ALIGN specifies any known alignment requirements for
9458 the section; 0 if the default should be used. */
9460 static void
9462 {
9465 /* Close the previous section. */
9469 /* Find out what kind of section we are opening. */
9478 else
9484 else
9486 }
9488 static void
9490 {
9494 }
9496 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9497 in code sections because .align fill unused space with zeroes. */
9499 void
9501 {
9504 else
9506 }
9508 /* Add a case vector to the current function's list of deferred case
9509 vectors. Case vectors have to be put into a separate section because CAM
9510 does not allow data definitions in code sections. */
9512 void
9514 {
9520 }
9522 /* Output a case vector. */
9524 static void
9526 {
9535 {
9536 ASM_OUTPUT_ADDR_VEC_ELT
9538 }
9539 }
9541 /* Output current function's deferred case vectors. */
9543 static void
9545 {
9547 rtx t;
9555 }
9557 /* Generate the name of the SSIB section for the current function. */
9560 #define SSIB_PREFIX_LEN 7
9564 {
9565 /* This is ok since CAM won't be able to deal with names longer than that
9566 anyway. */
9570 rtx x;
9591 }
9593 /* Set up the dynamic subprogram information block (DSIB) and update the
9594 frame pointer register ($15) for subroutines which have a frame. If the
9595 subroutine doesn't have a frame, simply increment $15. */
9597 static void
9599 {
9601 {
9603 rtx mem;
9605 /* Allocate 64 bytes for the DSIB. */
9611 /* Save the return address. */
9618 /* Save the old frame pointer. */
9627 /* Store the SSIB pointer. */
9637 /* Save the CIW index. */
9645 /* Set the new frame pointer. */
9650 }
9651 else
9652 {
9653 /* Increment the frame pointer register to indicate that we do not
9654 have a frame. */
9658 }
9659 }
9661 /* Output the static subroutine information block for the current
9662 function. */
9664 static void
9666 {
9669 rtx x;
9670 rtx ciw;
9677 /* Some required stuff and the function name length. */
9682 /* Saved registers
9683 ??? We don't do that yet. */
9687 /* Function address. */
9696 /* Function name.
9697 ??? We do it the same way Cray CC does it but this could be
9698 simplified. */
9704 else
9707 /* All call information words used in the function. */
9710 {
9712 #if HOST_BITS_PER_WIDE_INT == 32
9715 #else
9717 #endif
9718 }
9719 }
9721 /* Add a call information word (CIW) to the list of the current function's
9722 CIWs and return its index.
9724 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9726 rtx
9728 {
9729 rtx node;
9735 else
9743 }
9749 {
9752 count++);
9754 }
9758 {
9761 count++);
9763 }
9765 /* The Cray assembler doesn't accept extern declarations for symbols which
9766 are defined in the same file. We have to keep track of all global
9767 symbols which are referenced and/or defined in a source file and output
9768 extern declarations for those which are referenced but not defined at
9769 the end of file. */
9771 /* List of identifiers for which an extern declaration might have to be
9772 emitted. */
9773 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9775 struct unicosmk_extern_list
9776 {
9779 };
9783 /* Output extern declarations which are required for every asm file. */
9785 static void
9787 {
9798 }
9800 /* Output extern declarations for global symbols which are have been
9801 referenced but not defined. */
9803 static void
9805 {
9809 tree name_tree;
9813 {
9814 /* We have to strip the encoding and possibly remove user_label_prefix
9815 from the identifier in order to handle -fleading-underscore and
9816 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9824 {
9829 }
9830 }
9831 }
9833 /* Record an extern. */
9835 void
9837 {
9845 }
9847 /* The Cray assembler generates incorrect code if identifiers which
9848 conflict with register names are used as instruction operands. We have
9849 to replace such identifiers with DEX expressions. */
9851 /* Structure to collect identifiers which have been replaced by DEX
9852 expressions. */
9853 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9858 };
9860 /* List of identifiers which have been replaced by DEX expressions. The DEX
9861 number is determined by the position in the list. */
9865 /* The number of elements in the DEX list. */
9869 /* Check if NAME must be replaced by a DEX expression. */
9871 static int
9873 {
9884 {
9894 }
9895 }
9897 /* Return the DEX number if X must be replaced by a DEX expression and 0
9898 otherwise. */
9900 static int
9902 {
9916 {
9920 }
9929 }
9931 /* Output the DEX definitions for this file. */
9933 static void
9935 {
9946 {
9951 }
9954 }
9956 /* Output text that to appear at the beginning of an assembler file. */
9958 static void
9960 {
9967 /* The Unicos/Mk assembler uses different register names. Instead of trying
9968 to support them, we simply use micro definitions. */
9970 /* CAM has different register names: rN for the integer register N and fN
9971 for the floating-point register N. Instead of trying to use these in
9972 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9973 register. */
9983 /* The .align directive fill unused space with zeroes which does not work
9984 in code sections. We define the macro 'gcc@code@align' which uses nops
9985 instead. Note that it assumes that code sections always have the
9986 biggest possible alignment since . refers to the current offset from
9987 the beginning of the section. */
9999 /* Output extern declarations which should always be visible. */
10002 /* Open a dummy section. We always need to be inside a section for the
10003 section-switching code to work correctly.
10004 ??? This should be a module id or something like that. I still have to
10005 figure out what the rules for those are. */
10007 }
10009 /* Output text to appear at the end of an assembler file. This includes all
10010 pending extern declarations and DEX expressions. */
10012 static void
10014 {
10017 /* Output all pending externs. */
10021 /* Output dex definitions used for functions whose names conflict with
10022 register names. */
10029 }
10031 #else
10033 static void
10035 {}
10037 static void
10039 {}
10041 static void
10044 {}
10046 rtx
10048 {
10050 }
10052 static int
10054 {
10056 }
10060 static void
10062 {
10064 {
10065 /* Prevent gcc from generating calls to __divsi3. */
10069 /* Use the functions provided by the system library
10070 for DImode integer division. */
10073 }
10075 {
10076 /* Use the VMS runtime library functions for division and
10077 remainder. */
10086 }
10087 }
10089 \f
10090 /* Initialize the GCC target structure. */
10091 #if TARGET_ABI_OPEN_VMS
10092 # undef TARGET_ATTRIBUTE_TABLE
10093 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10094 # undef TARGET_SECTION_TYPE_FLAGS
10095 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10096 #endif
10098 #undef TARGET_IN_SMALL_DATA_P
10099 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10101 #if TARGET_ABI_UNICOSMK
10102 # undef TARGET_INSERT_ATTRIBUTES
10103 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10104 # undef TARGET_SECTION_TYPE_FLAGS
10105 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10106 # undef TARGET_ASM_UNIQUE_SECTION
10107 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10108 # undef TARGET_ASM_GLOBALIZE_LABEL
10109 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10110 #endif
10112 #undef TARGET_ASM_ALIGNED_HI_OP
10114 #undef TARGET_ASM_ALIGNED_DI_OP
10117 /* Default unaligned ops are provided for ELF systems. To get unaligned
10118 data for non-ELF systems, we have to turn off auto alignment. */
10119 #ifndef OBJECT_FORMAT_ELF
10120 #undef TARGET_ASM_UNALIGNED_HI_OP
10122 #undef TARGET_ASM_UNALIGNED_SI_OP
10124 #undef TARGET_ASM_UNALIGNED_DI_OP
10126 #endif
10128 #ifdef OBJECT_FORMAT_ELF
10129 #undef TARGET_ASM_SELECT_RTX_SECTION
10130 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10131 #endif
10133 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10134 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10136 #undef TARGET_INIT_LIBFUNCS
10137 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10139 #if TARGET_ABI_UNICOSMK
10140 #undef TARGET_ASM_FILE_START
10141 #define TARGET_ASM_FILE_START unicosmk_file_start
10142 #undef TARGET_ASM_FILE_END
10143 #define TARGET_ASM_FILE_END unicosmk_file_end
10144 #else
10145 #undef TARGET_ASM_FILE_START
10146 #define TARGET_ASM_FILE_START alpha_file_start
10147 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10148 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10149 #endif
10151 #undef TARGET_SCHED_ADJUST_COST
10152 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10153 #undef TARGET_SCHED_ISSUE_RATE
10154 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10155 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10156 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10157 alpha_use_dfa_pipeline_interface
10158 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10159 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10160 alpha_multipass_dfa_lookahead
10162 #undef TARGET_HAVE_TLS
10163 #define TARGET_HAVE_TLS HAVE_AS_TLS
10165 #undef TARGET_INIT_BUILTINS
10166 #define TARGET_INIT_BUILTINS alpha_init_builtins
10167 #undef TARGET_EXPAND_BUILTIN
10168 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10170 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10171 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10172 #undef TARGET_CANNOT_COPY_INSN_P
10173 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10175 #if TARGET_ABI_OSF
10176 #undef TARGET_ASM_OUTPUT_MI_THUNK
10177 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10178 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10179 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10180 #endif
10182 #undef TARGET_RTX_COSTS
10183 #define TARGET_RTX_COSTS alpha_rtx_costs
10184 #undef TARGET_ADDRESS_COST
10185 #define TARGET_ADDRESS_COST hook_int_rtx_0
10187 #undef TARGET_MACHINE_DEPENDENT_REORG
10188 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10190 #undef TARGET_PROMOTE_FUNCTION_ARGS
10191 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10192 #undef TARGET_PROMOTE_FUNCTION_RETURN
10193 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10194 #undef TARGET_PROMOTE_PROTOTYPES
10195 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10196 #undef TARGET_STRUCT_VALUE_RTX
10197 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
10198 #undef TARGET_RETURN_IN_MEMORY
10199 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10200 #undef TARGET_SETUP_INCOMING_VARARGS
10201 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10202 #undef TARGET_STRICT_ARGUMENT_NAMING
10203 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10204 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10205 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10207 #undef TARGET_BUILD_BUILTIN_VA_LIST
10208 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10212 \f