1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93-99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
43 #include "arm-protos.h"
45 /* The maximum number of insns skipped which will be conditionalised if
47 static int max_insns_skipped
= 5;
49 extern FILE * asm_out_file
;
50 /* Some function declarations. */
53 #define Mmode enum machine_mode
56 static HOST_WIDE_INT int_log2
PARAMS ((HOST_WIDE_INT
));
57 static char * output_multi_immediate
PARAMS ((rtx
*, char *, char *, int, HOST_WIDE_INT
));
58 static int arm_gen_constant
PARAMS ((enum rtx_code
, Mmode
, HOST_WIDE_INT
, rtx
, rtx
, int, int));
59 static int arm_naked_function_p
PARAMS ((tree
));
60 static void init_fpa_table
PARAMS ((void));
61 static enum machine_mode select_dominance_cc_mode
PARAMS ((rtx
, rtx
, HOST_WIDE_INT
));
62 static HOST_WIDE_INT add_minipool_constant
PARAMS ((rtx
, Mmode
));
63 static void dump_minipool
PARAMS ((rtx
));
64 static rtx find_barrier
PARAMS ((rtx
, int));
65 static void push_minipool_fix
PARAMS ((rtx
, int, rtx
*, Mmode
, rtx
));
66 static void push_minipool_barrier
PARAMS ((rtx
, int));
67 static void note_invalid_constants
PARAMS ((rtx
, int));
68 static char * fp_const_from_val
PARAMS ((REAL_VALUE_TYPE
*));
69 static int eliminate_lr2ip
PARAMS ((rtx
*));
70 static char * shift_op
PARAMS ((rtx
, HOST_WIDE_INT
*));
71 static int pattern_really_clobbers_lr
PARAMS ((rtx
));
72 static int function_really_clobbers_lr
PARAMS ((rtx
));
73 static void emit_multi_reg_push
PARAMS ((int));
74 static void emit_sfm
PARAMS ((int, int));
75 static enum arm_cond_code get_arm_condition_code
PARAMS ((rtx
));
76 static int const_ok_for_op
PARAMS ((HOST_WIDE_INT
, enum rtx_code
));
77 static void arm_add_gc_roots
PARAMS ((void));
79 /* True if we are currently building a constant table. */
80 int making_const_table
;
82 /* Define the information needed to generate branch insns. This is
83 stored from the compare operation. */
84 rtx arm_compare_op0
, arm_compare_op1
;
86 /* What type of floating point are we tuning for? */
87 enum floating_point_type arm_fpu
;
89 /* What type of floating point instructions are available? */
90 enum floating_point_type arm_fpu_arch
;
92 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
93 enum prog_mode_type arm_prgmode
;
95 /* Set by the -mfp=... option */
96 const char * target_fp_name
= NULL
;
98 /* Used to parse -mstructure_size_boundary command line option. */
99 const char * structure_size_string
= NULL
;
100 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
102 /* Bit values used to identify processor capabilities. */
103 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
104 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
105 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
106 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
107 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
108 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
109 #define FL_THUMB (1 << 6) /* Thumb aware */
110 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
111 #define FL_STRONG (1 << 8) /* StrongARM */
113 /* The bits in this mask specify which instructions we are allowed to
115 static int insn_flags
= 0;
116 /* The bits in this mask specify which instruction scheduling options should
117 be used. Note - there is an overlap with the FL_FAST_MULT. For some
118 hardware we want to be able to generate the multiply instructions, but to
119 tune as if they were not present in the architecture. */
120 static int tune_flags
= 0;
122 /* The following are used in the arm.md file as equivalents to bits
123 in the above two flag variables. */
125 /* Nonzero if this is an "M" variant of the processor. */
126 int arm_fast_multiply
= 0;
128 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
131 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
134 /* Nonzero if this chip can benefit from load scheduling. */
135 int arm_ld_sched
= 0;
137 /* Nonzero if this chip is a StrongARM. */
138 int arm_is_strong
= 0;
140 /* Nonzero if this chip is a an ARM6 or an ARM7. */
141 int arm_is_6_or_7
= 0;
143 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
144 must report the mode of the memory reference from PRINT_OPERAND to
145 PRINT_OPERAND_ADDRESS. */
146 enum machine_mode output_memory_reference_mode
;
148 /* Nonzero if the prologue must setup `fp'. */
149 int current_function_anonymous_args
;
151 /* The register number to be used for the PIC offset register. */
152 const char * arm_pic_register_string
= NULL
;
153 int arm_pic_register
= 9;
155 /* Set to one if we think that lr is only saved because of subroutine calls,
156 but all of these can be `put after' return insns */
157 int lr_save_eliminated
;
159 /* Set to 1 when a return insn is output, this means that the epilogue
161 static int return_used_this_function
;
163 /* Set to 1 after arm_reorg has started. Reset to start at the start of
164 the next function. */
165 static int after_arm_reorg
= 0;
167 /* The maximum number of insns to be used when loading a constant. */
168 static int arm_constant_limit
= 3;
170 /* For an explanation of these variables, see final_prescan_insn below. */
172 enum arm_cond_code arm_current_cc
;
174 int arm_target_label
;
176 /* The condition codes of the ARM, and the inverse function. */
177 char * arm_condition_codes
[] =
179 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
180 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
183 static enum arm_cond_code
get_arm_condition_code ();
185 #define streq(string1, string2) (strcmp (string1, string2) == 0)
187 /* Initialization code */
195 /* Not all of these give usefully different compilation alternatives,
196 but there is no simple way of generalizing them. */
197 static struct processors all_cores
[] =
201 {"arm2", FL_CO_PROC
| FL_MODE26
},
202 {"arm250", FL_CO_PROC
| FL_MODE26
},
203 {"arm3", FL_CO_PROC
| FL_MODE26
},
204 {"arm6", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
205 {"arm60", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
206 {"arm600", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
207 {"arm610", FL_MODE26
| FL_MODE32
},
208 {"arm620", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
209 {"arm7", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
210 /* arm7m doesn't exist on its own, but only with D, (and I), but
211 those don't alter the code, so arm7m is sometimes used. */
212 {"arm7m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
213 {"arm7d", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
214 {"arm7dm", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
215 {"arm7di", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
216 {"arm7dmi", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
217 {"arm70", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
218 {"arm700", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
219 {"arm700i", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
220 {"arm710", FL_MODE26
| FL_MODE32
},
221 {"arm720", FL_MODE26
| FL_MODE32
},
222 {"arm710c", FL_MODE26
| FL_MODE32
},
223 {"arm7100", FL_MODE26
| FL_MODE32
},
224 {"arm7500", FL_MODE26
| FL_MODE32
},
225 /* Doesn't have an external co-proc, but does have embedded fpu. */
226 {"arm7500fe", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
227 {"arm7tdmi", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
228 {"arm8", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
229 {"arm810", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
230 {"arm9", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
231 {"arm920", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
232 {"arm920t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
233 {"arm9tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
234 {"strongarm", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
235 {"strongarm110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
236 {"strongarm1100", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
241 static struct processors all_architectures
[] =
243 /* ARM Architectures */
245 { "armv2", FL_CO_PROC
| FL_MODE26
},
246 { "armv2a", FL_CO_PROC
| FL_MODE26
},
247 { "armv3", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
248 { "armv3m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
249 { "armv4", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
},
250 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
251 implementations that support it, so we will leave it out for now. */
252 { "armv4t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
253 { "armv5", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
257 /* This is a magic stucture. The 'string' field is magically filled in
258 with a pointer to the value specified by the user on the command line
259 assuming that the user has specified such a value. */
261 struct arm_cpu_select arm_select
[] =
263 /* string name processors */
264 { NULL
, "-mcpu=", all_cores
},
265 { NULL
, "-march=", all_architectures
},
266 { NULL
, "-mtune=", all_cores
}
269 /* Return the number of bits set in value' */
274 unsigned int count
= 0;
278 value
&= ~(value
& - value
);
285 /* Fix up any incompatible options that the user has specified.
286 This has now turned into a maze. */
288 arm_override_options ()
292 /* Set up the flags based on the cpu/architecture selected by the user. */
293 for (i
= sizeof (arm_select
) / sizeof (arm_select
[0]); i
--;)
295 struct arm_cpu_select
* ptr
= arm_select
+ i
;
297 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
299 const struct processors
* sel
;
301 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
302 if (streq (ptr
->string
, sel
->name
))
305 tune_flags
= sel
->flags
;
308 /* If we have been given an architecture and a processor
309 make sure that they are compatible. We only generate
310 a warning though, and we prefer the CPU over the
312 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
313 warning ("switch -mcpu=%s conflicts with -march= switch",
316 insn_flags
= sel
->flags
;
322 if (sel
->name
== NULL
)
323 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
327 /* If the user did not specify a processor, choose one for them. */
330 struct processors
* sel
;
332 static struct cpu_default
339 { TARGET_CPU_arm2
, "arm2" },
340 { TARGET_CPU_arm6
, "arm6" },
341 { TARGET_CPU_arm610
, "arm610" },
342 { TARGET_CPU_arm710
, "arm710" },
343 { TARGET_CPU_arm7m
, "arm7m" },
344 { TARGET_CPU_arm7500fe
, "arm7500fe" },
345 { TARGET_CPU_arm7tdmi
, "arm7tdmi" },
346 { TARGET_CPU_arm8
, "arm8" },
347 { TARGET_CPU_arm810
, "arm810" },
348 { TARGET_CPU_arm9
, "arm9" },
349 { TARGET_CPU_strongarm
, "strongarm" },
350 { TARGET_CPU_generic
, "arm" },
353 struct cpu_default
* def
;
355 /* Find the default. */
356 for (def
= cpu_defaults
; def
->name
; def
++)
357 if (def
->cpu
== TARGET_CPU_DEFAULT
)
360 /* Make sure we found the default CPU. */
361 if (def
->name
== NULL
)
364 /* Find the default CPU's flags. */
365 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
366 if (streq (def
->name
, sel
->name
))
369 if (sel
->name
== NULL
)
372 insn_flags
= sel
->flags
;
374 /* Now check to see if the user has specified some command line
375 switch that require certain abilities from the cpu. */
378 if (TARGET_INTERWORK
)
380 sought
|= (FL_THUMB
| FL_MODE32
);
382 /* Force apcs-32 to be used for interworking. */
383 target_flags
|= ARM_FLAG_APCS_32
;
385 /* There are no ARM processor that supports both APCS-26 and
386 interworking. Therefore we force FL_MODE26 to be removed
387 from insn_flags here (if it was set), so that the search
388 below will always be able to find a compatible processor. */
389 insn_flags
&= ~ FL_MODE26
;
392 if (! TARGET_APCS_32
)
395 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
397 /* Try to locate a CPU type that supports all of the abilities
398 of the default CPU, plus the extra abilities requested by
400 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
401 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
404 if (sel
->name
== NULL
)
406 unsigned int current_bit_count
= 0;
407 struct processors
* best_fit
= NULL
;
409 /* Ideally we would like to issue an error message here
410 saying that it was not possible to find a CPU compatible
411 with the default CPU, but which also supports the command
412 line options specified by the programmer, and so they
413 ought to use the -mcpu=<name> command line option to
414 override the default CPU type.
416 Unfortunately this does not work with multilibing. We
417 need to be able to support multilibs for -mapcs-26 and for
418 -mthumb-interwork and there is no CPU that can support both
419 options. Instead if we cannot find a cpu that has both the
420 characteristics of the default cpu and the given command line
421 options we scan the array again looking for a best match. */
422 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
423 if ((sel
->flags
& sought
) == sought
)
427 count
= bit_count (sel
->flags
& insn_flags
);
429 if (count
>= current_bit_count
)
432 current_bit_count
= count
;
436 if (best_fit
== NULL
)
442 insn_flags
= sel
->flags
;
446 /* If tuning has not been specified, tune for whichever processor or
447 architecture has been selected. */
449 tune_flags
= insn_flags
;
451 /* Make sure that the processor choice does not conflict with any of the
452 other command line choices. */
453 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
455 /* If APCS-32 was not the default then it must have been set by the
456 user, so issue a warning message. If the user has specified
457 "-mapcs-32 -mcpu=arm2" then we loose here. */
458 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
459 warning ("target CPU does not support APCS-32" );
460 target_flags
&= ~ ARM_FLAG_APCS_32
;
462 else if (! TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
464 warning ("target CPU does not support APCS-26" );
465 target_flags
|= ARM_FLAG_APCS_32
;
468 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
470 warning ("target CPU does not support interworking" );
471 target_flags
&= ~ARM_FLAG_INTERWORK
;
474 /* If interworking is enabled then APCS-32 must be selected as well. */
475 if (TARGET_INTERWORK
)
477 if (! TARGET_APCS_32
)
478 warning ("interworking forces APCS-32 to be used" );
479 target_flags
|= ARM_FLAG_APCS_32
;
482 if (TARGET_APCS_STACK
&& ! TARGET_APCS
)
484 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
485 target_flags
|= ARM_FLAG_APCS_FRAME
;
488 if (TARGET_POKE_FUNCTION_NAME
)
489 target_flags
|= ARM_FLAG_APCS_FRAME
;
491 if (TARGET_APCS_REENT
&& flag_pic
)
492 fatal ("-fpic and -mapcs-reent are incompatible");
494 if (TARGET_APCS_REENT
)
495 warning ("APCS reentrant code not supported. Ignored");
497 if (write_symbols
!= NO_DEBUG
&& flag_omit_frame_pointer
)
498 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
500 /* If stack checking is disabled, we can use r10 as the PIC register,
501 which keeps r9 available. */
502 if (flag_pic
&& ! TARGET_APCS_STACK
)
503 arm_pic_register
= 10;
505 if (TARGET_APCS_FLOAT
)
506 warning ("Passing floating point arguments in fp regs not yet supported");
508 /* Initialise boolean versions of the flags, for use in the arm.md file. */
509 arm_fast_multiply
= (insn_flags
& FL_FAST_MULT
) != 0;
510 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
511 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
513 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
514 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
515 arm_is_6_or_7
= ((tune_flags
& (FL_MODE26
| FL_MODE32
))
516 && !(tune_flags
& FL_ARCH4
)) != 0;
518 /* Default value for floating point code... if no co-processor
519 bus, then schedule for emulated floating point. Otherwise,
520 assume the user has an FPA.
521 Note: this does not prevent use of floating point instructions,
522 -msoft-float does that. */
523 arm_fpu
= (tune_flags
& FL_CO_PROC
) ? FP_HARD
: FP_SOFT3
;
527 if (streq (target_fp_name
, "2"))
528 arm_fpu_arch
= FP_SOFT2
;
529 else if (streq (target_fp_name
, "3"))
530 arm_fpu_arch
= FP_SOFT3
;
532 fatal ("Invalid floating point emulation option: -mfpe-%s",
536 arm_fpu_arch
= FP_DEFAULT
;
538 if (TARGET_FPE
&& arm_fpu
!= FP_HARD
)
541 /* For arm2/3 there is no need to do any scheduling if there is only
542 a floating point emulator, or we are doing software floating-point. */
543 if ((TARGET_SOFT_FLOAT
|| arm_fpu
!= FP_HARD
)
544 && (tune_flags
& FL_MODE32
) == 0)
545 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
547 arm_prog_mode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
549 if (structure_size_string
!= NULL
)
551 int size
= strtol (structure_size_string
, NULL
, 0);
553 if (size
== 8 || size
== 32)
554 arm_structure_size_boundary
= size
;
556 warning ("Structure size boundary can only be set to 8 or 32");
559 if (arm_pic_register_string
!= NULL
)
564 warning ("-mpic-register= is useless without -fpic");
566 pic_register
= decode_reg_name (arm_pic_register_string
);
568 /* Prevent the user from choosing an obviously stupid PIC register. */
569 if (pic_register
< 0 || call_used_regs
[pic_register
]
570 || pic_register
== HARD_FRAME_POINTER_REGNUM
571 || pic_register
== STACK_POINTER_REGNUM
572 || pic_register
>= PC_REGNUM
)
573 error ("Unable to use '%s' for PIC register", arm_pic_register_string
);
575 arm_pic_register
= pic_register
;
578 /* If optimizing for space, don't synthesize constants.
579 For processors with load scheduling, it never costs more than 2 cycles
580 to load a constant, and the load scheduler may well reduce that to 1. */
581 if (optimize_size
|| (tune_flags
& FL_LDSCHED
))
582 arm_constant_limit
= 1;
584 /* If optimizing for size, bump the number of instructions that we
585 are prepared to conditionally execute (even on a StrongARM).
586 Otherwise for the StrongARM, which has early execution of branches,
587 a sequence that is worth skipping is shorter. */
589 max_insns_skipped
= 6;
590 else if (arm_is_strong
)
591 max_insns_skipped
= 3;
593 /* Register global variables with the garbage collector. */
600 ggc_add_rtx_root (&arm_compare_op0
, 1);
601 ggc_add_rtx_root (&arm_compare_op1
, 1);
602 ggc_add_rtx_root (&arm_target_insn
, 1); /* Not sure this is really a root */
603 /* XXX: What about the minipool tables? */
607 /* Return 1 if it is possible to return using a single instruction */
610 use_return_insn (iscond
)
615 if (!reload_completed
616 || current_function_pretend_args_size
617 || current_function_anonymous_args
618 || ((get_frame_size () + current_function_outgoing_args_size
!= 0)
619 && !(TARGET_APCS
&& frame_pointer_needed
)))
622 /* Can't be done if interworking with Thumb, and any registers have been
623 stacked. Similarly, on StrongARM, conditional returns are expensive
624 if they aren't taken and registers have been stacked. */
625 if (iscond
&& arm_is_strong
&& frame_pointer_needed
)
627 if ((iscond
&& arm_is_strong
)
630 for (regno
= 0; regno
< 16; regno
++)
631 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
634 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
638 /* Can't be done if any of the FPU regs are pushed, since this also
640 for (regno
= 16; regno
< 24; regno
++)
641 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
644 /* If a function is naked, don't use the "return" insn. */
645 if (arm_naked_function_p (current_function_decl
))
651 /* Return TRUE if int I is a valid immediate ARM constant. */
657 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
659 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
660 be all zero, or all one. */
661 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffffUL
) != 0
662 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffffUL
)
663 != ((~(unsigned HOST_WIDE_INT
) 0)
664 & ~(unsigned HOST_WIDE_INT
) 0xffffffffUL
)))
667 /* Fast return for 0 and powers of 2 */
668 if ((i
& (i
- 1)) == 0)
673 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffffUL
) == 0)
676 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffffUL
)
677 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT
) 0xffffffffUL
);
678 } while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
683 /* Return true if I is a valid constant for the operation CODE. */
685 const_ok_for_op (i
, code
)
689 if (const_ok_for_arm (i
))
695 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
697 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
703 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
710 /* Emit a sequence of insns to handle a large constant.
711 CODE is the code of the operation required, it can be any of SET, PLUS,
712 IOR, AND, XOR, MINUS;
713 MODE is the mode in which the operation is being performed;
714 VAL is the integer to operate on;
715 SOURCE is the other operand (a register, or a null-pointer for SET);
716 SUBTARGETS means it is safe to create scratch registers if that will
717 either produce a simpler sequence, or we will want to cse the values.
718 Return value is the number of insns emitted. */
721 arm_split_constant (code
, mode
, val
, target
, source
, subtargets
)
723 enum machine_mode mode
;
729 if (subtargets
|| code
== SET
730 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
731 && REGNO (target
) != REGNO (source
)))
733 /* After arm_reorg has been called, we can't fix up expensive
734 constants by pushing them into memory so we must synthesise
735 them in-line, regardless of the cost. This is only likely to
736 be more costly on chips that have load delay slots and we are
737 compiling without running the scheduler (so no splitting
738 occurred before the final instruction emission).
740 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
742 if (! after_arm_reorg
743 && (arm_gen_constant (code
, mode
, val
, target
, source
, 1, 0)
744 > arm_constant_limit
+ (code
!= SET
)))
748 /* Currently SET is the only monadic value for CODE, all
749 the rest are diadic. */
750 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
755 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
757 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
758 /* For MINUS, the value is subtracted from, since we never
759 have subtraction of a constant. */
761 emit_insn (gen_rtx_SET (VOIDmode
, target
,
762 gen_rtx (code
, mode
, temp
, source
)));
764 emit_insn (gen_rtx_SET (VOIDmode
, target
,
765 gen_rtx (code
, mode
, source
, temp
)));
771 return arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, 1);
774 /* As above, but extra parameter GENERATE which, if clear, suppresses
777 arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, generate
)
779 enum machine_mode mode
;
788 int can_negate_initial
= 0;
791 int num_bits_set
= 0;
792 int set_sign_bit_copies
= 0;
793 int clear_sign_bit_copies
= 0;
794 int clear_zero_bit_copies
= 0;
795 int set_zero_bit_copies
= 0;
797 unsigned HOST_WIDE_INT temp1
, temp2
;
798 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffffUL
;
800 /* find out which operations are safe for a given CODE. Also do a quick
801 check for degenerate cases; these can occur when DImode operations
813 can_negate_initial
= 1;
817 if (remainder
== 0xffffffffUL
)
820 emit_insn (gen_rtx_SET (VOIDmode
, target
,
821 GEN_INT (ARM_SIGN_EXTEND (val
))));
826 if (reload_completed
&& rtx_equal_p (target
, source
))
829 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
838 emit_insn (gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
841 if (remainder
== 0xffffffffUL
)
843 if (reload_completed
&& rtx_equal_p (target
, source
))
846 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
855 if (reload_completed
&& rtx_equal_p (target
, source
))
858 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
861 if (remainder
== 0xffffffffUL
)
864 emit_insn (gen_rtx_SET (VOIDmode
, target
,
865 gen_rtx_NOT (mode
, source
)));
869 /* We don't know how to handle this yet below. */
873 /* We treat MINUS as (val - source), since (source - val) is always
874 passed as (source + (-val)). */
878 emit_insn (gen_rtx_SET (VOIDmode
, target
,
879 gen_rtx_NEG (mode
, source
)));
882 if (const_ok_for_arm (val
))
885 emit_insn (gen_rtx_SET (VOIDmode
, target
,
886 gen_rtx_MINUS (mode
, GEN_INT (val
),
898 /* If we can do it in one insn get out quickly */
899 if (const_ok_for_arm (val
)
900 || (can_negate_initial
&& const_ok_for_arm (-val
))
901 || (can_invert
&& const_ok_for_arm (~val
)))
904 emit_insn (gen_rtx_SET (VOIDmode
, target
,
905 (source
? gen_rtx (code
, mode
, source
,
912 /* Calculate a few attributes that may be useful for specific
915 for (i
= 31; i
>= 0; i
--)
917 if ((remainder
& (1 << i
)) == 0)
918 clear_sign_bit_copies
++;
923 for (i
= 31; i
>= 0; i
--)
925 if ((remainder
& (1 << i
)) != 0)
926 set_sign_bit_copies
++;
931 for (i
= 0; i
<= 31; i
++)
933 if ((remainder
& (1 << i
)) == 0)
934 clear_zero_bit_copies
++;
939 for (i
= 0; i
<= 31; i
++)
941 if ((remainder
& (1 << i
)) != 0)
942 set_zero_bit_copies
++;
950 /* See if we can do this by sign_extending a constant that is known
951 to be negative. This is a good, way of doing it, since the shift
952 may well merge into a subsequent insn. */
953 if (set_sign_bit_copies
> 1)
956 (temp1
= ARM_SIGN_EXTEND (remainder
957 << (set_sign_bit_copies
- 1))))
961 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
962 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
964 emit_insn (gen_ashrsi3 (target
, new_src
,
965 GEN_INT (set_sign_bit_copies
- 1)));
969 /* For an inverted constant, we will need to set the low bits,
970 these will be shifted out of harm's way. */
971 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
972 if (const_ok_for_arm (~temp1
))
976 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
977 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
979 emit_insn (gen_ashrsi3 (target
, new_src
,
980 GEN_INT (set_sign_bit_copies
- 1)));
986 /* See if we can generate this by setting the bottom (or the top)
987 16 bits, and then shifting these into the other half of the
988 word. We only look for the simplest cases, to do more would cost
989 too much. Be careful, however, not to generate this when the
990 alternative would take fewer insns. */
991 if (val
& 0xffff0000UL
)
993 temp1
= remainder
& 0xffff0000UL
;
994 temp2
= remainder
& 0x0000ffff;
996 /* Overlaps outside this range are best done using other methods. */
997 for (i
= 9; i
< 24; i
++)
999 if ((((temp2
| (temp2
<< i
)) & 0xffffffffUL
) == remainder
)
1000 && ! const_ok_for_arm (temp2
))
1002 rtx new_src
= (subtargets
1003 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1005 insns
= arm_gen_constant (code
, mode
, temp2
, new_src
,
1006 source
, subtargets
, generate
);
1009 emit_insn (gen_rtx_SET
1012 gen_rtx_ASHIFT (mode
, source
,
1019 /* Don't duplicate cases already considered. */
1020 for (i
= 17; i
< 24; i
++)
1022 if (((temp1
| (temp1
>> i
)) == remainder
)
1023 && ! const_ok_for_arm (temp1
))
1025 rtx new_src
= (subtargets
1026 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1028 insns
= arm_gen_constant (code
, mode
, temp1
, new_src
,
1029 source
, subtargets
, generate
);
1033 (gen_rtx_SET (VOIDmode
, target
,
1036 gen_rtx_LSHIFTRT (mode
, source
,
1047 /* If we have IOR or XOR, and the constant can be loaded in a
1048 single instruction, and we can find a temporary to put it in,
1049 then this can be done in two instructions instead of 3-4. */
1051 /* TARGET can't be NULL if SUBTARGETS is 0 */
1052 || (reload_completed
&& ! reg_mentioned_p (target
, source
)))
1054 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val
)))
1058 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1060 emit_insn (gen_rtx_SET (VOIDmode
, sub
, GEN_INT (val
)));
1061 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1062 gen_rtx (code
, mode
, source
, sub
)));
1071 if (set_sign_bit_copies
> 8
1072 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1076 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1077 rtx shift
= GEN_INT (set_sign_bit_copies
);
1079 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1081 gen_rtx_ASHIFT (mode
,
1084 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1086 gen_rtx_LSHIFTRT (mode
, sub
,
1092 if (set_zero_bit_copies
> 8
1093 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1097 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1098 rtx shift
= GEN_INT (set_zero_bit_copies
);
1100 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1102 gen_rtx_LSHIFTRT (mode
,
1105 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1107 gen_rtx_ASHIFT (mode
, sub
,
1113 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~ val
)))
1117 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1118 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1119 gen_rtx_NOT (mode
, source
)));
1122 sub
= gen_reg_rtx (mode
);
1123 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1124 gen_rtx_AND (mode
, source
,
1126 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1127 gen_rtx_NOT (mode
, sub
)));
1134 /* See if two shifts will do 2 or more insn's worth of work. */
1135 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1137 HOST_WIDE_INT shift_mask
= ((0xffffffffUL
1138 << (32 - clear_sign_bit_copies
))
1141 if ((remainder
| shift_mask
) != 0xffffffffUL
)
1145 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1146 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1147 new_src
, source
, subtargets
, 1);
1152 rtx targ
= subtargets
? NULL_RTX
: target
;
1153 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1154 targ
, source
, subtargets
, 0);
1160 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1161 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1163 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1164 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1170 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1172 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1174 if ((remainder
| shift_mask
) != 0xffffffffUL
)
1178 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1180 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1181 new_src
, source
, subtargets
, 1);
1186 rtx targ
= subtargets
? NULL_RTX
: target
;
1188 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1189 targ
, source
, subtargets
, 0);
1195 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1196 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1198 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1199 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1211 for (i
= 0; i
< 32; i
++)
1212 if (remainder
& (1 << i
))
1215 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1216 remainder
= (~remainder
) & 0xffffffffUL
;
1217 else if (code
== PLUS
&& num_bits_set
> 16)
1218 remainder
= (-remainder
) & 0xffffffffUL
;
1225 /* Now try and find a way of doing the job in either two or three
1227 We start by looking for the largest block of zeros that are aligned on
1228 a 2-bit boundary, we then fill up the temps, wrapping around to the
1229 top of the word when we drop off the bottom.
1230 In the worst case this code should produce no more than four insns. */
1233 int best_consecutive_zeros
= 0;
1235 for (i
= 0; i
< 32; i
+= 2)
1237 int consecutive_zeros
= 0;
1239 if (! (remainder
& (3 << i
)))
1241 while ((i
< 32) && ! (remainder
& (3 << i
)))
1243 consecutive_zeros
+= 2;
1246 if (consecutive_zeros
> best_consecutive_zeros
)
1248 best_consecutive_zeros
= consecutive_zeros
;
1249 best_start
= i
- consecutive_zeros
;
1255 /* Now start emitting the insns, starting with the one with the highest
1256 bit set: we do this so that the smallest number will be emitted last;
1257 this is more likely to be combinable with addressing insns. */
1265 if (remainder
& (3 << (i
- 2)))
1270 temp1
= remainder
& ((0x0ff << end
)
1271 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1272 remainder
&= ~temp1
;
1279 emit_insn (gen_rtx_SET (VOIDmode
,
1280 new_src
= (subtargets
1281 ? gen_reg_rtx (mode
)
1284 ? ~temp1
: temp1
)));
1285 else if (code
== MINUS
)
1286 emit_insn (gen_rtx_SET (VOIDmode
,
1287 new_src
= (subtargets
1288 ? gen_reg_rtx (mode
)
1290 gen_rtx (code
, mode
, GEN_INT (temp1
),
1293 emit_insn (gen_rtx_SET (VOIDmode
,
1294 new_src
= (remainder
1296 ? gen_reg_rtx (mode
)
1299 gen_rtx (code
, mode
, source
,
1300 GEN_INT (can_invert
? ~temp1
1312 else if (code
== MINUS
)
1319 } while (remainder
);
1324 /* Canonicalize a comparison so that we are more likely to recognize it.
1325 This can be done for a few constant compares, where we can make the
1326 immediate value easier to load. */
1328 arm_canonicalize_comparison (code
, op1
)
1332 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
1342 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1344 && (const_ok_for_arm (i
+1) || const_ok_for_arm (- (i
+1))))
1346 *op1
= GEN_INT (i
+1);
1347 return code
== GT
? GE
: LT
;
1353 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1354 && (const_ok_for_arm (i
-1) || const_ok_for_arm (- (i
-1))))
1356 *op1
= GEN_INT (i
-1);
1357 return code
== GE
? GT
: LE
;
1363 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
1364 && (const_ok_for_arm (i
+1) || const_ok_for_arm (- (i
+1))))
1366 *op1
= GEN_INT (i
+ 1);
1367 return code
== GTU
? GEU
: LTU
;
1374 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (- (i
- 1))))
1376 *op1
= GEN_INT (i
- 1);
1377 return code
== GEU
? GTU
: LEU
;
1388 /* Decide whether a type should be returned in memory (true)
1389 or in a register (false). This is called by the macro
1390 RETURN_IN_MEMORY. */
1392 arm_return_in_memory (type
)
1395 if (! AGGREGATE_TYPE_P (type
))
1397 /* All simple types are returned in registers. */
1400 else if (int_size_in_bytes (type
) > 4)
1402 /* All structures/unions bigger than one word are returned in memory. */
1405 else if (TREE_CODE (type
) == RECORD_TYPE
)
1409 /* For a struct the APCS says that we only return in a register
1410 if the type is 'integer like' and every addressable element
1411 has an offset of zero. For practical purposes this means
1412 that the structure can have at most one non bit-field element
1413 and that this element must be the first one in the structure. */
1415 /* Find the first field, ignoring non FIELD_DECL things which will
1416 have been created by C++. */
1417 for (field
= TYPE_FIELDS (type
);
1418 field
&& TREE_CODE (field
) != FIELD_DECL
;
1419 field
= TREE_CHAIN (field
))
1423 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1425 /* Check that the first field is valid for returning in a register... */
1427 /* ... Floats are not allowed */
1428 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1431 /* ... Aggregates that are not themselves valid for returning in
1432 a register are not allowed. */
1433 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1436 /* Now check the remaining fields, if any. Only bitfields are allowed,
1437 since they are not addressable. */
1438 for (field
= TREE_CHAIN (field
);
1440 field
= TREE_CHAIN (field
))
1442 if (TREE_CODE (field
) != FIELD_DECL
)
1445 if (! DECL_BIT_FIELD_TYPE (field
))
1451 else if (TREE_CODE (type
) == UNION_TYPE
)
1455 /* Unions can be returned in registers if every element is
1456 integral, or can be returned in an integer register. */
1457 for (field
= TYPE_FIELDS (type
);
1459 field
= TREE_CHAIN (field
))
1461 if (TREE_CODE (field
) != FIELD_DECL
)
1464 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1467 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1474 /* XXX Not sure what should be done for other aggregates, so put them in
1479 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1480 for a call to a function whose data type is FNTYPE.
1481 For a library call, FNTYPE is NULL. */
1483 arm_init_cumulative_args (pcum
, fntype
, libname
, indirect
)
1484 CUMULATIVE_ARGS
* pcum
;
1486 rtx libname ATTRIBUTE_UNUSED
;
1487 int indirect ATTRIBUTE_UNUSED
;
1489 /* On the ARM, the offset starts at 0. */
1490 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
)))
1493 pcum
->call_cookie
= CALL_NORMAL
;
1495 if (TARGET_LONG_CALLS
)
1496 pcum
->call_cookie
= CALL_LONG
;
1498 /* Check for long call/short call attributes. The attributes
1499 override any command line option. */
1502 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
1503 pcum
->call_cookie
= CALL_SHORT
;
1504 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
1505 pcum
->call_cookie
= CALL_LONG
;
1509 /* Determine where to put an argument to a function.
1510 Value is zero to push the argument on the stack,
1511 or a hard register in which to store the argument.
1513 MODE is the argument's machine mode.
1514 TYPE is the data type of the argument (as a tree).
1515 This is null for libcalls where that information may
1517 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1518 the preceding args and about the function being called.
1519 NAMED is nonzero if this argument is a named parameter
1520 (otherwise it is an extra parameter matching an ellipsis). */
1522 arm_function_arg (pcum
, mode
, type
, named
)
1523 CUMULATIVE_ARGS
* pcum
;
1524 enum machine_mode mode
;
1525 tree type ATTRIBUTE_UNUSED
;
1528 if (mode
== VOIDmode
)
1529 /* Compute operand 2 of the call insn. */
1530 return GEN_INT (pcum
->call_cookie
);
1532 if (! named
|| pcum
->nregs
>= NUM_ARG_REGS
)
1535 return gen_rtx_REG (mode
, pcum
->nregs
);
1539 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
1542 current_file_function_operand (sym_ref
)
1545 return (SYMBOL_REF_FLAG (sym_ref
)
1546 || sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0));
1549 /* Return non-zero if a 32 bit "long call" should be generated for this
1552 We generate a long call if the function is not declared
1553 __attribute__ ((short_call),
1557 (1) the function is declared __attribute__ ((long_call))
1561 (2) -mlong-calls is enabled and we don't know whether the target
1562 function is declared in this file.
1564 This function will typically be called by C fragments in the machine
1565 description file. CALL_REF is the matched rtl operand. CALL_COOKIE
1566 describes the value of the long_call and short_call attributes for
1567 the called functiion. CALL_SYMBOL is used to distinguish between
1568 two different callers of the function. It is set to 1 in the "call_symbol"
1569 and "call_symbol_value" patterns in arm.md and to 0 in the "call" and
1570 "call_value" patterns. This is because of the difference of SYM_REFs passed
1571 from "call_symbol" and "call" patterns. */
1573 arm_is_longcall_p (sym_ref
, call_cookie
, call_symbol
)
1580 if (GET_CODE (sym_ref
) != MEM
)
1583 sym_ref
= XEXP (sym_ref
, 0);
1586 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
1589 if (call_cookie
& CALL_SHORT
)
1592 if (TARGET_LONG_CALLS
&& flag_function_sections
)
1595 if (current_file_function_operand (sym_ref
, VOIDmode
))
1598 return (call_cookie
& CALL_LONG
) || TARGET_LONG_CALLS
;
1601 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
1602 attribute for TYPE. The attributes in ATTRIBUTES have previously been
1603 assigned to TYPE. */
1605 arm_valid_type_attribute_p (type
, attributes
, identifier
, args
)
1607 tree attributes ATTRIBUTE_UNUSED
;
1611 if ( TREE_CODE (type
) != FUNCTION_TYPE
1612 && TREE_CODE (type
) != METHOD_TYPE
1613 && TREE_CODE (type
) != FIELD_DECL
1614 && TREE_CODE (type
) != TYPE_DECL
)
1617 /* Function calls made to this symbol must be done indirectly, because
1618 it may lie outside of the 26 bit addressing range of a normal function
1620 if (is_attribute_p ("long_call", identifier
))
1621 return (args
== NULL_TREE
);
1623 /* Whereas these functions are always known to reside within the 26 bit
1624 addressing range. */
1625 if (is_attribute_p ("short_call", identifier
))
1626 return (args
== NULL_TREE
);
1631 /* Return 0 if the attributes for two types are incompatible, 1 if they
1632 are compatible, and 2 if they are nearly compatible (which causes a
1633 warning to be generated). */
1635 arm_comp_type_attributes (type1
, type2
)
1640 /* Check for mismatch of non-default calling convention. */
1641 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
1644 /* Check for mismatched call attributes. */
1645 l1
= ! lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
));
1646 l2
= ! lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
));
1647 s1
= ! lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
));
1648 s2
= ! lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
));
1650 return ! ((l1
^ l2
) || (s1
^s2
) || (l1
| s2
) || (s1
| l2
));
1655 legitimate_pic_operand_p (x
)
1658 if (CONSTANT_P (x
) && flag_pic
1659 && (GET_CODE (x
) == SYMBOL_REF
1660 || (GET_CODE (x
) == CONST
1661 && GET_CODE (XEXP (x
, 0)) == PLUS
1662 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
1669 legitimize_pic_address (orig
, mode
, reg
)
1671 enum machine_mode mode
;
1674 if (GET_CODE (orig
) == SYMBOL_REF
)
1676 rtx pic_ref
, address
;
1682 if (reload_in_progress
|| reload_completed
)
1685 reg
= gen_reg_rtx (Pmode
);
1690 #ifdef AOF_ASSEMBLER
1691 /* The AOF assembler can generate relocations for these directly, and
1692 understands that the PIC register has to be added into the offset.
1694 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
1697 address
= gen_reg_rtx (Pmode
);
1701 emit_insn (gen_pic_load_addr (address
, orig
));
1703 pic_ref
= gen_rtx_MEM (Pmode
,
1704 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
1706 RTX_UNCHANGING_P (pic_ref
) = 1;
1707 insn
= emit_move_insn (reg
, pic_ref
);
1709 current_function_uses_pic_offset_table
= 1;
1710 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1712 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
1716 else if (GET_CODE (orig
) == CONST
)
1720 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1721 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1726 if (reload_in_progress
|| reload_completed
)
1729 reg
= gen_reg_rtx (Pmode
);
1732 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1734 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1735 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1736 base
== reg
? 0 : reg
);
1741 if (GET_CODE (offset
) == CONST_INT
)
1743 /* The base register doesn't really matter, we only want to
1744 test the index for the appropriate mode. */
1745 GO_IF_LEGITIMATE_INDEX (mode
, 0, offset
, win
);
1747 if (! reload_in_progress
&& ! reload_completed
)
1748 offset
= force_reg (Pmode
, offset
);
1753 if (GET_CODE (offset
) == CONST_INT
)
1754 return plus_constant_for_output (base
, INTVAL (offset
));
1757 if (GET_MODE_SIZE (mode
) > 4
1758 && (GET_MODE_CLASS (mode
) == MODE_INT
1759 || TARGET_SOFT_FLOAT
))
1761 emit_insn (gen_addsi3 (reg
, base
, offset
));
1765 return gen_rtx_PLUS (Pmode
, base
, offset
);
1767 else if (GET_CODE (orig
) == LABEL_REF
)
1769 current_function_uses_pic_offset_table
= 1;
1773 rtx pic_ref
, address
= gen_reg_rtx (Pmode
);
1775 emit_insn (gen_pic_load_addr (address
, orig
));
1776 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
1778 emit_move_insn (address
, pic_ref
);
1800 #ifndef AOF_ASSEMBLER
1801 rtx l1
, pic_tmp
, pic_tmp2
, seq
;
1802 rtx global_offset_table
;
1804 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
1811 l1
= gen_label_rtx ();
1813 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1814 /* On the ARM the PC register contains 'dot + 8' at the time of the
1816 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), 8);
1818 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
1819 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
1821 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
1823 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
1825 emit_insn (gen_pic_load_addr (pic_offset_table_rtx
, pic_rtx
));
1826 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
1828 seq
= gen_sequence ();
1830 emit_insn_after (seq
, get_insns ());
1832 /* Need to emit this whether or not we obey regdecls,
1833 since setjmp/longjmp can cause life info to screw up. */
1834 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
1835 #endif /* AOF_ASSEMBLER */
1838 #define REG_OR_SUBREG_REG(X) \
1839 (GET_CODE (X) == REG \
1840 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1842 #define REG_OR_SUBREG_RTX(X) \
1843 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1845 #define ARM_FRAME_RTX(X) \
1846 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1847 || (X) == arg_pointer_rtx)
1850 arm_rtx_costs (x
, code
)
1854 enum machine_mode mode
= GET_MODE (x
);
1855 enum rtx_code subcode
;
1861 /* Memory costs quite a lot for the first word, but subsequent words
1862 load at the equivalent of a single insn each. */
1863 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
1864 + (CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
1871 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
1878 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
1880 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
1881 + ((GET_CODE (XEXP (x
, 0)) == REG
1882 || (GET_CODE (XEXP (x
, 0)) == SUBREG
1883 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
1885 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
1886 || (GET_CODE (XEXP (x
, 0)) == SUBREG
1887 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
1889 + ((GET_CODE (XEXP (x
, 1)) == REG
1890 || (GET_CODE (XEXP (x
, 1)) == SUBREG
1891 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
1892 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
1897 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
1898 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
1899 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
1900 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
1903 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1904 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
1905 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
1906 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
1908 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
1909 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
1910 && const_double_rtx_ok_for_fpu (XEXP (x
, 0))))
1913 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
1914 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
1915 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
1916 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
1917 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
1918 || subcode
== ROTATE
|| subcode
== ROTATERT
1920 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
1921 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
1922 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
1923 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
1924 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
1925 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
1926 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
1931 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1932 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
1933 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
1934 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
1935 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
1939 case AND
: case XOR
: case IOR
:
1942 /* Normally the frame registers will be spilt into reg+const during
1943 reload, so it is a bad idea to combine them with other instructions,
1944 since then they might not be moved outside of loops. As a compromise
1945 we allow integration with ops that have a constant as their second
1947 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
1948 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
1949 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1950 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
1951 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
1955 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
1956 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
1957 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
1958 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
1961 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
1962 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
1963 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
1964 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
1965 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
1968 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
1969 return (1 + extra_cost
1970 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
1971 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
1972 || subcode
== ROTATE
|| subcode
== ROTATERT
1974 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1975 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
1976 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
1977 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
1978 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
1979 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
1985 /* There is no point basing this on the tuning, since it is always the
1986 fast variant if it exists at all */
1987 if (arm_fast_multiply
&& mode
== DImode
1988 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
1989 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1990 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
1993 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1997 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1999 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
2000 & (unsigned HOST_WIDE_INT
) 0xffffffffUL
);
2001 int add_cost
= const_ok_for_arm (i
) ? 4 : 8;
2003 /* Tune as appropriate */
2004 int booth_unit_size
= ((tune_flags
& FL_FAST_MULT
) ? 8 : 2);
2006 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
2008 i
>>= booth_unit_size
;
2015 return (((tune_flags
& FL_FAST_MULT
) ? 8 : 30)
2016 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
2017 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4));
2020 if (arm_fast_multiply
&& mode
== SImode
2021 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
2022 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2023 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
2024 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
2025 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
2026 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
2031 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2032 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
2036 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
2038 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
2041 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
2049 return 4 + (mode
== DImode
? 4 : 0);
2052 if (GET_MODE (XEXP (x
, 0)) == QImode
)
2053 return (4 + (mode
== DImode
? 4 : 0)
2054 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2057 switch (GET_MODE (XEXP (x
, 0)))
2060 return (1 + (mode
== DImode
? 4 : 0)
2061 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2064 return (4 + (mode
== DImode
? 4 : 0)
2065 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2068 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2081 arm_adjust_cost (insn
, link
, dep
, cost
)
2089 /* XXX This is not strictly true for the FPA. */
2090 if (REG_NOTE_KIND(link
) == REG_DEP_ANTI
2091 || REG_NOTE_KIND(link
) == REG_DEP_OUTPUT
)
2094 if ((i_pat
= single_set (insn
)) != NULL
2095 && GET_CODE (SET_SRC (i_pat
)) == MEM
2096 && (d_pat
= single_set (dep
)) != NULL
2097 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
2099 /* This is a load after a store, there is no conflict if the load reads
2100 from a cached area. Assume that loads from the stack, and from the
2101 constant pool are cached, and that others will miss. This is a
2104 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat
), 0))
2105 || reg_mentioned_p (stack_pointer_rtx
, XEXP (SET_SRC (i_pat
), 0))
2106 || reg_mentioned_p (frame_pointer_rtx
, XEXP (SET_SRC (i_pat
), 0))
2107 || reg_mentioned_p (hard_frame_pointer_rtx
,
2108 XEXP (SET_SRC (i_pat
), 0)))
2115 /* This code has been fixed for cross compilation. */
2117 static int fpa_consts_inited
= 0;
2119 char * strings_fpa
[8] =
2122 "4", "5", "0.5", "10"
2125 static REAL_VALUE_TYPE values_fpa
[8];
2133 for (i
= 0; i
< 8; i
++)
2135 r
= REAL_VALUE_ATOF (strings_fpa
[i
], DFmode
);
2139 fpa_consts_inited
= 1;
2142 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2145 const_double_rtx_ok_for_fpu (x
)
2151 if (!fpa_consts_inited
)
2154 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2155 if (REAL_VALUE_MINUS_ZERO (r
))
2158 for (i
= 0; i
< 8; i
++)
2159 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
2165 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2168 neg_const_double_rtx_ok_for_fpu (x
)
2174 if (!fpa_consts_inited
)
2177 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2178 r
= REAL_VALUE_NEGATE (r
);
2179 if (REAL_VALUE_MINUS_ZERO (r
))
2182 for (i
= 0; i
< 8; i
++)
2183 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
2189 /* Predicates for `match_operand' and `match_operator'. */
2191 /* s_register_operand is the same as register_operand, but it doesn't accept
2194 This function exists because at the time it was put in it led to better
2195 code. SUBREG(MEM) always needs a reload in the places where
2196 s_register_operand is used, and this seemed to lead to excessive
2200 s_register_operand (op
, mode
)
2202 enum machine_mode mode
;
2204 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
2207 if (GET_CODE (op
) == SUBREG
)
2208 op
= SUBREG_REG (op
);
2210 /* We don't consider registers whose class is NO_REGS
2211 to be a register operand. */
2212 return (GET_CODE (op
) == REG
2213 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
2214 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
2217 /* Only accept reg, subreg(reg), const_int. */
2220 reg_or_int_operand (op
, mode
)
2222 enum machine_mode mode
;
2224 if (GET_CODE (op
) == CONST_INT
)
2227 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
2230 if (GET_CODE (op
) == SUBREG
)
2231 op
= SUBREG_REG (op
);
2233 /* We don't consider registers whose class is NO_REGS
2234 to be a register operand. */
2235 return (GET_CODE (op
) == REG
2236 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
2237 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
2240 /* Return 1 if OP is an item in memory, given that we are in reload. */
2243 reload_memory_operand (op
, mode
)
2245 enum machine_mode mode ATTRIBUTE_UNUSED
;
2247 int regno
= true_regnum (op
);
2249 return (! CONSTANT_P (op
)
2251 || (GET_CODE (op
) == REG
2252 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
2255 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2256 memory access (architecture V4) */
2258 bad_signed_byte_operand (op
, mode
)
2260 enum machine_mode mode
;
2262 if (! memory_operand (op
, mode
) || GET_CODE (op
) != MEM
)
2267 /* A sum of anything more complex than reg + reg or reg + const is bad */
2268 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
2269 && (! s_register_operand (XEXP (op
, 0), VOIDmode
)
2270 || (! s_register_operand (XEXP (op
, 1), VOIDmode
)
2271 && GET_CODE (XEXP (op
, 1)) != CONST_INT
)))
2274 /* Big constants are also bad */
2275 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
2276 && (INTVAL (XEXP (op
, 1)) > 0xff
2277 || -INTVAL (XEXP (op
, 1)) > 0xff))
2280 /* Everything else is good, or can will automatically be made so. */
2284 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2287 arm_rhs_operand (op
, mode
)
2289 enum machine_mode mode
;
2291 return (s_register_operand (op
, mode
)
2292 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
2295 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2299 arm_rhsm_operand (op
, mode
)
2301 enum machine_mode mode
;
2303 return (s_register_operand (op
, mode
)
2304 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
2305 || memory_operand (op
, mode
));
2308 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2309 constant that is valid when negated. */
2312 arm_add_operand (op
, mode
)
2314 enum machine_mode mode
;
2316 return (s_register_operand (op
, mode
)
2317 || (GET_CODE (op
) == CONST_INT
2318 && (const_ok_for_arm (INTVAL (op
))
2319 || const_ok_for_arm (-INTVAL (op
)))));
2323 arm_not_operand (op
, mode
)
2325 enum machine_mode mode
;
2327 return (s_register_operand (op
, mode
)
2328 || (GET_CODE (op
) == CONST_INT
2329 && (const_ok_for_arm (INTVAL (op
))
2330 || const_ok_for_arm (~INTVAL (op
)))));
2333 /* Return TRUE if the operand is a memory reference which contains an
2334 offsettable address. */
2336 offsettable_memory_operand (op
, mode
)
2338 enum machine_mode mode
;
2340 if (mode
== VOIDmode
)
2341 mode
= GET_MODE (op
);
2343 return (mode
== GET_MODE (op
)
2344 && GET_CODE (op
) == MEM
2345 && offsettable_address_p (reload_completed
| reload_in_progress
,
2346 mode
, XEXP (op
, 0)));
2349 /* Return TRUE if the operand is a memory reference which is, or can be
2350 made word aligned by adjusting the offset. */
2352 alignable_memory_operand (op
, mode
)
2354 enum machine_mode mode
;
2358 if (mode
== VOIDmode
)
2359 mode
= GET_MODE (op
);
2361 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
2366 return ((GET_CODE (reg
= op
) == REG
2367 || (GET_CODE (op
) == SUBREG
2368 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
2369 || (GET_CODE (op
) == PLUS
2370 && GET_CODE (XEXP (op
, 1)) == CONST_INT
2371 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
2372 || (GET_CODE (XEXP (op
, 0)) == SUBREG
2373 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
2374 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 4);
2377 /* Similar to s_register_operand, but does not allow hard integer
2380 f_register_operand (op
, mode
)
2382 enum machine_mode mode
;
2384 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
2387 if (GET_CODE (op
) == SUBREG
)
2388 op
= SUBREG_REG (op
);
2390 /* We don't consider registers whose class is NO_REGS
2391 to be a register operand. */
2392 return (GET_CODE (op
) == REG
2393 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
2394 || REGNO_REG_CLASS (REGNO (op
)) == FPU_REGS
));
2397 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2400 fpu_rhs_operand (op
, mode
)
2402 enum machine_mode mode
;
2404 if (s_register_operand (op
, mode
))
2407 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
2410 if (GET_CODE (op
) == CONST_DOUBLE
)
2411 return const_double_rtx_ok_for_fpu (op
);
2417 fpu_add_operand (op
, mode
)
2419 enum machine_mode mode
;
2421 if (s_register_operand (op
, mode
))
2424 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
2427 if (GET_CODE (op
) == CONST_DOUBLE
)
2428 return (const_double_rtx_ok_for_fpu (op
)
2429 || neg_const_double_rtx_ok_for_fpu (op
));
2434 /* Return nonzero if OP is a constant power of two. */
2437 power_of_two_operand (op
, mode
)
2439 enum machine_mode mode ATTRIBUTE_UNUSED
;
2441 if (GET_CODE (op
) == CONST_INT
)
2443 HOST_WIDE_INT value
= INTVAL(op
);
2444 return value
!= 0 && (value
& (value
- 1)) == 0;
2449 /* Return TRUE for a valid operand of a DImode operation.
2450 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2451 Note that this disallows MEM(REG+REG), but allows
2452 MEM(PRE/POST_INC/DEC(REG)). */
2455 di_operand (op
, mode
)
2457 enum machine_mode mode
;
2459 if (s_register_operand (op
, mode
))
2462 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
2465 if (GET_CODE (op
) == SUBREG
)
2466 op
= SUBREG_REG (op
);
2468 switch (GET_CODE (op
))
2475 return memory_address_p (DImode
, XEXP (op
, 0));
2482 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2483 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2484 Note that this disallows MEM(REG+REG), but allows
2485 MEM(PRE/POST_INC/DEC(REG)). */
2488 soft_df_operand (op
, mode
)
2490 enum machine_mode mode
;
2492 if (s_register_operand (op
, mode
))
2495 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
2498 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
2501 if (GET_CODE (op
) == SUBREG
)
2502 op
= SUBREG_REG (op
);
2504 switch (GET_CODE (op
))
2510 return memory_address_p (DFmode
, XEXP (op
, 0));
2517 /* Return TRUE for valid index operands. */
2520 index_operand (op
, mode
)
2522 enum machine_mode mode
;
2524 return (s_register_operand(op
, mode
)
2525 || (immediate_operand (op
, mode
)
2526 && INTVAL (op
) < 4096 && INTVAL (op
) > -4096));
2529 /* Return TRUE for valid shifts by a constant. This also accepts any
2530 power of two on the (somewhat overly relaxed) assumption that the
2531 shift operator in this case was a mult. */
2534 const_shift_operand (op
, mode
)
2536 enum machine_mode mode
;
2538 return (power_of_two_operand (op
, mode
)
2539 || (immediate_operand (op
, mode
)
2540 && (INTVAL (op
) < 32 && INTVAL (op
) > 0)));
2543 /* Return TRUE for arithmetic operators which can be combined with a multiply
2547 shiftable_operator (x
, mode
)
2549 enum machine_mode mode
;
2551 if (GET_MODE (x
) != mode
)
2555 enum rtx_code code
= GET_CODE (x
);
2557 return (code
== PLUS
|| code
== MINUS
2558 || code
== IOR
|| code
== XOR
|| code
== AND
);
2562 /* Return TRUE for binary logical operators. */
2565 logical_binary_operator (x
, mode
)
2567 enum machine_mode mode
;
2569 if (GET_MODE (x
) != mode
)
2573 enum rtx_code code
= GET_CODE (x
);
2575 return (code
== IOR
|| code
== XOR
|| code
== AND
);
2579 /* Return TRUE for shift operators. */
2582 shift_operator (x
, mode
)
2584 enum machine_mode mode
;
2586 if (GET_MODE (x
) != mode
)
2590 enum rtx_code code
= GET_CODE (x
);
2593 return power_of_two_operand (XEXP (x
, 1), mode
);
2595 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
2596 || code
== ROTATERT
);
2600 int equality_operator (x
, mode
)
2602 enum machine_mode mode ATTRIBUTE_UNUSED
;
2604 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
2607 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2610 minmax_operator (x
, mode
)
2612 enum machine_mode mode
;
2614 enum rtx_code code
= GET_CODE (x
);
2616 if (GET_MODE (x
) != mode
)
2619 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
2622 /* return TRUE if x is EQ or NE */
2624 /* Return TRUE if this is the condition code register, if we aren't given
2625 a mode, accept any class CCmode register */
2628 cc_register (x
, mode
)
2630 enum machine_mode mode
;
2632 if (mode
== VOIDmode
)
2634 mode
= GET_MODE (x
);
2635 if (GET_MODE_CLASS (mode
) != MODE_CC
)
2639 if (mode
== GET_MODE (x
) && GET_CODE (x
) == REG
&& REGNO (x
) == 24)
2645 /* Return TRUE if this is the condition code register, if we aren't given
2646 a mode, accept any class CCmode register which indicates a dominance
2650 dominant_cc_register (x
, mode
)
2652 enum machine_mode mode
;
2654 if (mode
== VOIDmode
)
2656 mode
= GET_MODE (x
);
2657 if (GET_MODE_CLASS (mode
) != MODE_CC
)
2661 if (mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
2662 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
2663 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
2664 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
2665 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
2668 if (mode
== GET_MODE (x
) && GET_CODE (x
) == REG
&& REGNO (x
) == 24)
2674 /* Return TRUE if X references a SYMBOL_REF. */
2676 symbol_mentioned_p (x
)
2679 register const char * fmt
;
2682 if (GET_CODE (x
) == SYMBOL_REF
)
2685 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
2686 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
2692 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2693 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
2696 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
2703 /* Return TRUE if X references a LABEL_REF. */
2705 label_mentioned_p (x
)
2708 register const char * fmt
;
2711 if (GET_CODE (x
) == LABEL_REF
)
2714 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
2715 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
2721 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2722 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
2725 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
2736 enum rtx_code code
= GET_CODE (x
);
2740 else if (code
== SMIN
)
2742 else if (code
== UMIN
)
2744 else if (code
== UMAX
)
2750 /* Return 1 if memory locations are adjacent */
2753 adjacent_mem_locations (a
, b
)
2756 int val0
= 0, val1
= 0;
2759 if ((GET_CODE (XEXP (a
, 0)) == REG
2760 || (GET_CODE (XEXP (a
, 0)) == PLUS
2761 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
2762 && (GET_CODE (XEXP (b
, 0)) == REG
2763 || (GET_CODE (XEXP (b
, 0)) == PLUS
2764 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
2766 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
2768 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
2769 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
2772 reg0
= REGNO (XEXP (a
, 0));
2773 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
2775 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
2776 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
2779 reg1
= REGNO (XEXP (b
, 0));
2780 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
2785 /* Return 1 if OP is a load multiple operation. It is known to be
2786 parallel and the first section will be tested. */
2789 load_multiple_operation (op
, mode
)
2791 enum machine_mode mode ATTRIBUTE_UNUSED
;
2793 HOST_WIDE_INT count
= XVECLEN (op
, 0);
2796 HOST_WIDE_INT i
= 1, base
= 0;
2800 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
2803 /* Check to see if this might be a write-back */
2804 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
2809 /* Now check it more carefully */
2810 if (GET_CODE (SET_DEST (elt
)) != REG
2811 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
2812 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
2813 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
2814 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 2) * 4
2815 || GET_CODE (XVECEXP (op
, 0, count
- 1)) != CLOBBER
2816 || GET_CODE (XEXP (XVECEXP (op
, 0, count
- 1), 0)) != REG
2817 || REGNO (XEXP (XVECEXP (op
, 0, count
- 1), 0))
2818 != REGNO (SET_DEST (elt
)))
2824 /* Perform a quick check so we don't blow up below. */
2826 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
2827 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
2828 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
2831 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
2832 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
2834 for (; i
< count
; i
++)
2836 elt
= XVECEXP (op
, 0, i
);
2838 if (GET_CODE (elt
) != SET
2839 || GET_CODE (SET_DEST (elt
)) != REG
2840 || GET_MODE (SET_DEST (elt
)) != SImode
2841 || REGNO (SET_DEST (elt
)) != dest_regno
+ i
- base
2842 || GET_CODE (SET_SRC (elt
)) != MEM
2843 || GET_MODE (SET_SRC (elt
)) != SImode
2844 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
2845 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
2846 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
2847 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
2854 /* Return 1 if OP is a store multiple operation. It is known to be
2855 parallel and the first section will be tested. */
2858 store_multiple_operation (op
, mode
)
2860 enum machine_mode mode ATTRIBUTE_UNUSED
;
2862 HOST_WIDE_INT count
= XVECLEN (op
, 0);
2865 HOST_WIDE_INT i
= 1, base
= 0;
2869 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
2872 /* Check to see if this might be a write-back */
2873 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
2878 /* Now check it more carefully */
2879 if (GET_CODE (SET_DEST (elt
)) != REG
2880 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
2881 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
2882 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
2883 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 2) * 4
2884 || GET_CODE (XVECEXP (op
, 0, count
- 1)) != CLOBBER
2885 || GET_CODE (XEXP (XVECEXP (op
, 0, count
- 1), 0)) != REG
2886 || REGNO (XEXP (XVECEXP (op
, 0, count
- 1), 0))
2887 != REGNO (SET_DEST (elt
)))
2893 /* Perform a quick check so we don't blow up below. */
2895 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
2896 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
2897 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
2900 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
2901 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
2903 for (; i
< count
; i
++)
2905 elt
= XVECEXP (op
, 0, i
);
2907 if (GET_CODE (elt
) != SET
2908 || GET_CODE (SET_SRC (elt
)) != REG
2909 || GET_MODE (SET_SRC (elt
)) != SImode
2910 || REGNO (SET_SRC (elt
)) != src_regno
+ i
- base
2911 || GET_CODE (SET_DEST (elt
)) != MEM
2912 || GET_MODE (SET_DEST (elt
)) != SImode
2913 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
2914 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
2915 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
2916 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
2924 load_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
2929 HOST_WIDE_INT
* load_offset
;
2931 int unsorted_regs
[4];
2932 HOST_WIDE_INT unsorted_offsets
[4];
2937 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2938 extended if required. */
2939 if (nops
< 2 || nops
> 4)
2942 /* Loop over the operands and check that the memory references are
2943 suitable (ie immediate offsets from the same base register). At
2944 the same time, extract the target register, and the memory
2946 for (i
= 0; i
< nops
; i
++)
2951 /* Convert a subreg of a mem into the mem itself. */
2952 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
2953 operands
[nops
+ i
] = alter_subreg(operands
[nops
+ i
]);
2955 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
2958 /* Don't reorder volatile memory references; it doesn't seem worth
2959 looking for the case where the order is ok anyway. */
2960 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
2963 offset
= const0_rtx
;
2965 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
2966 || (GET_CODE (reg
) == SUBREG
2967 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
2968 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
2969 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
2971 || (GET_CODE (reg
) == SUBREG
2972 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
2973 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
2978 base_reg
= REGNO(reg
);
2979 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
2980 ? REGNO (operands
[i
])
2981 : REGNO (SUBREG_REG (operands
[i
])));
2986 if (base_reg
!= REGNO (reg
))
2987 /* Not addressed from the same base register. */
2990 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
2991 ? REGNO (operands
[i
])
2992 : REGNO (SUBREG_REG (operands
[i
])));
2993 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
2997 /* If it isn't an integer register, or if it overwrites the
2998 base register but isn't the last insn in the list, then
2999 we can't do this. */
3000 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
3001 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
3004 unsorted_offsets
[i
] = INTVAL (offset
);
3007 /* Not a suitable memory address. */
3011 /* All the useful information has now been extracted from the
3012 operands into unsorted_regs and unsorted_offsets; additionally,
3013 order[0] has been set to the lowest numbered register in the
3014 list. Sort the registers into order, and check that the memory
3015 offsets are ascending and adjacent. */
3017 for (i
= 1; i
< nops
; i
++)
3021 order
[i
] = order
[i
- 1];
3022 for (j
= 0; j
< nops
; j
++)
3023 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
3024 && (order
[i
] == order
[i
- 1]
3025 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
3028 /* Have we found a suitable register? if not, one must be used more
3030 if (order
[i
] == order
[i
- 1])
3033 /* Is the memory address adjacent and ascending? */
3034 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
3042 for (i
= 0; i
< nops
; i
++)
3043 regs
[i
] = unsorted_regs
[order
[i
]];
3045 *load_offset
= unsorted_offsets
[order
[0]];
3048 if (unsorted_offsets
[order
[0]] == 0)
3049 return 1; /* ldmia */
3051 if (unsorted_offsets
[order
[0]] == 4)
3052 return 2; /* ldmib */
3054 if (unsorted_offsets
[order
[nops
- 1]] == 0)
3055 return 3; /* ldmda */
3057 if (unsorted_offsets
[order
[nops
- 1]] == -4)
3058 return 4; /* ldmdb */
3060 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3061 if the offset isn't small enough. The reason 2 ldrs are faster
3062 is because these ARMs are able to do more than one cache access
3063 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3064 whilst the ARM8 has a double bandwidth cache. This means that
3065 these cores can do both an instruction fetch and a data fetch in
3066 a single cycle, so the trick of calculating the address into a
3067 scratch register (one of the result regs) and then doing a load
3068 multiple actually becomes slower (and no smaller in code size).
3069 That is the transformation
3071 ldr rd1, [rbase + offset]
3072 ldr rd2, [rbase + offset + 4]
3076 add rd1, rbase, offset
3077 ldmia rd1, {rd1, rd2}
3079 produces worse code -- '3 cycles + any stalls on rd2' instead of
3080 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3081 access per cycle, the first sequence could never complete in less
3082 than 6 cycles, whereas the ldm sequence would only take 5 and
3083 would make better use of sequential accesses if not hitting the
3086 We cheat here and test 'arm_ld_sched' which we currently know to
3087 only be true for the ARM8, ARM9 and StrongARM. If this ever
3088 changes, then the test below needs to be reworked. */
3089 if (nops
== 2 && arm_ld_sched
)
3092 /* Can't do it without setting up the offset, only do this if it takes
3093 no more than one insn. */
3094 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
3095 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
3099 emit_ldm_seq (operands
, nops
)
3105 HOST_WIDE_INT offset
;
3109 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
3112 strcpy (buf
, "ldm%?ia\t");
3116 strcpy (buf
, "ldm%?ib\t");
3120 strcpy (buf
, "ldm%?da\t");
3124 strcpy (buf
, "ldm%?db\t");
3129 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
3130 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
3133 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
3134 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
3136 output_asm_insn (buf
, operands
);
3138 strcpy (buf
, "ldm%?ia\t");
3145 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
3146 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
3148 for (i
= 1; i
< nops
; i
++)
3149 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
3150 reg_names
[regs
[i
]]);
3152 strcat (buf
, "}\t%@ phole ldm");
3154 output_asm_insn (buf
, operands
);
3159 store_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
3164 HOST_WIDE_INT
* load_offset
;
3166 int unsorted_regs
[4];
3167 HOST_WIDE_INT unsorted_offsets
[4];
3172 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3173 extended if required. */
3174 if (nops
< 2 || nops
> 4)
3177 /* Loop over the operands and check that the memory references are
3178 suitable (ie immediate offsets from the same base register). At
3179 the same time, extract the target register, and the memory
3181 for (i
= 0; i
< nops
; i
++)
3186 /* Convert a subreg of a mem into the mem itself. */
3187 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
3188 operands
[nops
+ i
] = alter_subreg(operands
[nops
+ i
]);
3190 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
3193 /* Don't reorder volatile memory references; it doesn't seem worth
3194 looking for the case where the order is ok anyway. */
3195 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
3198 offset
= const0_rtx
;
3200 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
3201 || (GET_CODE (reg
) == SUBREG
3202 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
3203 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
3204 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
3206 || (GET_CODE (reg
) == SUBREG
3207 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
3208 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
3213 base_reg
= REGNO (reg
);
3214 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
3215 ? REGNO (operands
[i
])
3216 : REGNO (SUBREG_REG (operands
[i
])));
3221 if (base_reg
!= REGNO (reg
))
3222 /* Not addressed from the same base register. */
3225 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
3226 ? REGNO (operands
[i
])
3227 : REGNO (SUBREG_REG (operands
[i
])));
3228 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
3232 /* If it isn't an integer register, then we can't do this. */
3233 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
3236 unsorted_offsets
[i
] = INTVAL (offset
);
3239 /* Not a suitable memory address. */
3243 /* All the useful information has now been extracted from the
3244 operands into unsorted_regs and unsorted_offsets; additionally,
3245 order[0] has been set to the lowest numbered register in the
3246 list. Sort the registers into order, and check that the memory
3247 offsets are ascending and adjacent. */
3249 for (i
= 1; i
< nops
; i
++)
3253 order
[i
] = order
[i
- 1];
3254 for (j
= 0; j
< nops
; j
++)
3255 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
3256 && (order
[i
] == order
[i
- 1]
3257 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
3260 /* Have we found a suitable register? if not, one must be used more
3262 if (order
[i
] == order
[i
- 1])
3265 /* Is the memory address adjacent and ascending? */
3266 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
3274 for (i
= 0; i
< nops
; i
++)
3275 regs
[i
] = unsorted_regs
[order
[i
]];
3277 *load_offset
= unsorted_offsets
[order
[0]];
3280 if (unsorted_offsets
[order
[0]] == 0)
3281 return 1; /* stmia */
3283 if (unsorted_offsets
[order
[0]] == 4)
3284 return 2; /* stmib */
3286 if (unsorted_offsets
[order
[nops
- 1]] == 0)
3287 return 3; /* stmda */
3289 if (unsorted_offsets
[order
[nops
- 1]] == -4)
3290 return 4; /* stmdb */
3296 emit_stm_seq (operands
, nops
)
3302 HOST_WIDE_INT offset
;
3306 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
3309 strcpy (buf
, "stm%?ia\t");
3313 strcpy (buf
, "stm%?ib\t");
3317 strcpy (buf
, "stm%?da\t");
3321 strcpy (buf
, "stm%?db\t");
3328 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
3329 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
3331 for (i
= 1; i
< nops
; i
++)
3332 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
3333 reg_names
[regs
[i
]]);
3335 strcat (buf
, "}\t%@ phole stm");
3337 output_asm_insn (buf
, operands
);
3342 multi_register_push (op
, mode
)
3344 enum machine_mode mode ATTRIBUTE_UNUSED
;
3346 if (GET_CODE (op
) != PARALLEL
3347 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
3348 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
3349 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != 2))
3356 /* Routines for use with attributes */
3358 /* Return nonzero if ATTR is a valid attribute for DECL.
3359 ATTRIBUTES are any existing attributes and ARGS are the arguments
3362 Supported attributes:
3364 naked: don't output any prologue or epilogue code, the user is assumed
3365 to do the right thing. */
3368 arm_valid_machine_decl_attribute (decl
, attr
, args
)
3373 if (args
!= NULL_TREE
)
3376 if (is_attribute_p ("naked", attr
))
3377 return TREE_CODE (decl
) == FUNCTION_DECL
;
3381 /* Return non-zero if FUNC is a naked function. */
3384 arm_naked_function_p (func
)
3389 if (TREE_CODE (func
) != FUNCTION_DECL
)
3392 a
= lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func
));
3393 return a
!= NULL_TREE
;
3396 /* Routines for use in generating RTL */
3399 arm_gen_load_multiple (base_regno
, count
, from
, up
, write_back
, unchanging_p
,
3400 in_struct_p
, scalar_p
)
3412 int sign
= up
? 1 : -1;
3415 result
= gen_rtx_PARALLEL (VOIDmode
,
3416 rtvec_alloc (count
+ (write_back
? 2 : 0)));
3419 XVECEXP (result
, 0, 0)
3420 = gen_rtx_SET (GET_MODE (from
), from
,
3421 plus_constant (from
, count
* 4 * sign
));
3426 for (j
= 0; i
< count
; i
++, j
++)
3428 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
3429 RTX_UNCHANGING_P (mem
) = unchanging_p
;
3430 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
3431 MEM_SCALAR_P (mem
) = scalar_p
;
3432 XVECEXP (result
, 0, i
)
3433 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
3437 XVECEXP (result
, 0, i
) = gen_rtx_CLOBBER (SImode
, from
);
3443 arm_gen_store_multiple (base_regno
, count
, to
, up
, write_back
, unchanging_p
,
3444 in_struct_p
, scalar_p
)
3456 int sign
= up
? 1 : -1;
3459 result
= gen_rtx_PARALLEL (VOIDmode
,
3460 rtvec_alloc (count
+ (write_back
? 2 : 0)));
3463 XVECEXP (result
, 0, 0)
3464 = gen_rtx_SET (GET_MODE (to
), to
,
3465 plus_constant (to
, count
* 4 * sign
));
3470 for (j
= 0; i
< count
; i
++, j
++)
3472 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
3473 RTX_UNCHANGING_P (mem
) = unchanging_p
;
3474 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
3475 MEM_SCALAR_P (mem
) = scalar_p
;
3477 XVECEXP (result
, 0, i
)
3478 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
3482 XVECEXP (result
, 0, i
) = gen_rtx_CLOBBER (SImode
, to
);
3488 arm_gen_movstrqi (operands
)
3491 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
3494 rtx st_src
, st_dst
, fin_src
, fin_dst
;
3495 rtx part_bytes_reg
= NULL
;
3497 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
3498 int dst_scalar_p
, src_scalar_p
;
3500 if (GET_CODE (operands
[2]) != CONST_INT
3501 || GET_CODE (operands
[3]) != CONST_INT
3502 || INTVAL (operands
[2]) > 64
3503 || INTVAL (operands
[3]) & 3)
3506 st_dst
= XEXP (operands
[0], 0);
3507 st_src
= XEXP (operands
[1], 0);
3509 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
3510 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
3511 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
3512 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
3513 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
3514 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
3516 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
3517 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
3519 in_words_to_go
= (INTVAL (operands
[2]) + 3) / 4;
3520 out_words_to_go
= INTVAL (operands
[2]) / 4;
3521 last_bytes
= INTVAL (operands
[2]) & 3;
3523 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
3524 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
3526 for (i
= 0; in_words_to_go
>= 2; i
+=4)
3528 if (in_words_to_go
> 4)
3529 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
3534 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
3535 FALSE
, src_unchanging_p
,
3536 src_in_struct_p
, src_scalar_p
));
3538 if (out_words_to_go
)
3540 if (out_words_to_go
> 4)
3541 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
3545 else if (out_words_to_go
!= 1)
3546 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
3555 mem
= gen_rtx_MEM (SImode
, dst
);
3556 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
3557 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
3558 MEM_SCALAR_P (mem
) = dst_scalar_p
;
3559 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
3560 if (last_bytes
!= 0)
3561 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
3565 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
3566 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
3569 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3570 if (out_words_to_go
)
3574 mem
= gen_rtx_MEM (SImode
, src
);
3575 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
3576 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
3577 MEM_SCALAR_P (mem
) = src_scalar_p
;
3578 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
3579 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
3581 mem
= gen_rtx_MEM (SImode
, dst
);
3582 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
3583 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
3584 MEM_SCALAR_P (mem
) = dst_scalar_p
;
3585 emit_move_insn (mem
, sreg
);
3586 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
3589 if (in_words_to_go
) /* Sanity check */
3595 if (in_words_to_go
< 0)
3598 mem
= gen_rtx_MEM (SImode
, src
);
3599 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
3600 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
3601 MEM_SCALAR_P (mem
) = src_scalar_p
;
3602 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
3605 if (BYTES_BIG_ENDIAN
&& last_bytes
)
3607 rtx tmp
= gen_reg_rtx (SImode
);
3609 if (part_bytes_reg
== NULL
)
3612 /* The bytes we want are in the top end of the word */
3613 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
3614 GEN_INT (8 * (4 - last_bytes
))));
3615 part_bytes_reg
= tmp
;
3619 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
3620 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
3621 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
3622 MEM_SCALAR_P (mem
) = dst_scalar_p
;
3623 emit_move_insn (mem
, gen_rtx_SUBREG (QImode
, part_bytes_reg
, 0));
3627 tmp
= gen_reg_rtx (SImode
);
3628 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
3629 part_bytes_reg
= tmp
;
3638 if (part_bytes_reg
== NULL
)
3641 mem
= gen_rtx_MEM (QImode
, dst
);
3642 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
3643 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
3644 MEM_SCALAR_P (mem
) = dst_scalar_p
;
3645 emit_move_insn (mem
, gen_rtx_SUBREG (QImode
, part_bytes_reg
, 0));
3649 rtx tmp
= gen_reg_rtx (SImode
);
3651 emit_insn (gen_addsi3 (dst
, dst
, const1_rtx
));
3652 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
3653 part_bytes_reg
= tmp
;
3661 /* Generate a memory reference for a half word, such that it will be loaded
3662 into the top 16 bits of the word. We can assume that the address is
3663 known to be alignable and of the form reg, or plus (reg, const). */
3665 gen_rotated_half_load (memref
)
3668 HOST_WIDE_INT offset
= 0;
3669 rtx base
= XEXP (memref
, 0);
3671 if (GET_CODE (base
) == PLUS
)
3673 offset
= INTVAL (XEXP (base
, 1));
3674 base
= XEXP (base
, 0);
3677 /* If we aren't allowed to generate unaligned addresses, then fail. */
3678 if (TARGET_MMU_TRAPS
3679 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
3682 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
3684 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
3687 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
3690 static enum machine_mode
3691 select_dominance_cc_mode (x
, y
, cond_or
)
3694 HOST_WIDE_INT cond_or
;
3696 enum rtx_code cond1
, cond2
;
3699 /* Currently we will probably get the wrong result if the individual
3700 comparisons are not simple. This also ensures that it is safe to
3701 reverse a comparison if necessary. */
3702 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
3704 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
3709 cond1
= reverse_condition (cond1
);
3711 /* If the comparisons are not equal, and one doesn't dominate the other,
3712 then we can't do this. */
3714 && ! comparison_dominates_p (cond1
, cond2
)
3715 && (swapped
= 1, ! comparison_dominates_p (cond2
, cond1
)))
3720 enum rtx_code temp
= cond1
;
3728 if (cond2
== EQ
|| ! cond_or
)
3733 case LE
: return CC_DLEmode
;
3734 case LEU
: return CC_DLEUmode
;
3735 case GE
: return CC_DGEmode
;
3736 case GEU
: return CC_DGEUmode
;
3743 if (cond2
== LT
|| ! cond_or
)
3752 if (cond2
== GT
|| ! cond_or
)
3761 if (cond2
== LTU
|| ! cond_or
)
3770 if (cond2
== GTU
|| ! cond_or
)
3778 /* The remaining cases only occur when both comparisons are the
3803 arm_select_cc_mode (op
, x
, y
)
3808 /* All floating point compares return CCFP if it is an equality
3809 comparison, and CCFPE otherwise. */
3810 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3811 return (op
== EQ
|| op
== NE
) ? CCFPmode
: CCFPEmode
;
3813 /* A compare with a shifted operand. Because of canonicalization, the
3814 comparison will have to be swapped when we emit the assembler. */
3815 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
3816 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
3817 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
3818 || GET_CODE (x
) == ROTATERT
))
3821 /* This is a special case that is used by combine to allow a
3822 comparison of a shifted byte load to be split into a zero-extend
3823 followed by a comparison of the shifted integer (only valid for
3824 equalities and unsigned inequalities). */
3825 if (GET_MODE (x
) == SImode
3826 && GET_CODE (x
) == ASHIFT
3827 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
3828 && GET_CODE (XEXP (x
, 0)) == SUBREG
3829 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
3830 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
3831 && (op
== EQ
|| op
== NE
3832 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
3833 && GET_CODE (y
) == CONST_INT
)
3836 /* An operation that sets the condition codes as a side-effect, the
3837 V flag is not set correctly, so we can only use comparisons where
3838 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3840 if (GET_MODE (x
) == SImode
3842 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
3843 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
3844 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
3845 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
3846 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
3847 || GET_CODE (x
) == LSHIFTRT
3848 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
3849 || GET_CODE (x
) == ROTATERT
|| GET_CODE (x
) == ZERO_EXTRACT
))
3852 /* A construct for a conditional compare, if the false arm contains
3853 0, then both conditions must be true, otherwise either condition
3854 must be true. Not all conditions are possible, so CCmode is
3855 returned if it can't be done. */
3856 if (GET_CODE (x
) == IF_THEN_ELSE
3857 && (XEXP (x
, 2) == const0_rtx
3858 || XEXP (x
, 2) == const1_rtx
)
3859 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3860 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
3861 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
3862 INTVAL (XEXP (x
, 2)));
3864 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
3867 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
3868 && GET_CODE (x
) == PLUS
3869 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
3875 /* X and Y are two things to compare using CODE. Emit the compare insn and
3876 return the rtx for register 0 in the proper mode. FP means this is a
3877 floating point compare: I don't think that it is needed on the arm. */
3880 gen_compare_reg (code
, x
, y
)
3884 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
3885 rtx cc_reg
= gen_rtx_REG (mode
, 24);
3887 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
3888 gen_rtx_COMPARE (mode
, x
, y
)));
3894 arm_reload_in_hi (operands
)
3897 rtx ref
= operands
[1];
3899 HOST_WIDE_INT offset
= 0;
3901 if (GET_CODE (ref
) == SUBREG
)
3903 offset
= SUBREG_WORD (ref
) * UNITS_PER_WORD
;
3904 if (BYTES_BIG_ENDIAN
)
3905 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (ref
)))
3906 - MIN (UNITS_PER_WORD
,
3907 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref
)))));
3908 ref
= SUBREG_REG (ref
);
3911 if (GET_CODE (ref
) == REG
)
3913 /* We have a pseudo which has been spilt onto the stack; there
3914 are two cases here: the first where there is a simple
3915 stack-slot replacement and a second where the stack-slot is
3916 out of range, or is used as a subreg. */
3917 if (reg_equiv_mem
[REGNO (ref
)])
3919 ref
= reg_equiv_mem
[REGNO (ref
)];
3920 base
= find_replacement (&XEXP (ref
, 0));
3923 /* The slot is out of range, or was dressed up in a SUBREG */
3924 base
= reg_equiv_address
[REGNO (ref
)];
3927 base
= find_replacement (&XEXP (ref
, 0));
3929 /* Handle the case where the address is too complex to be offset by 1. */
3930 if (GET_CODE (base
) == MINUS
3931 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
3933 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
3935 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
3938 else if (GET_CODE (base
) == PLUS
)
3940 /* The addend must be CONST_INT, or we would have dealt with it above */
3941 HOST_WIDE_INT hi
, lo
;
3943 offset
+= INTVAL (XEXP (base
, 1));
3944 base
= XEXP (base
, 0);
3946 /* Rework the address into a legal sequence of insns */
3947 /* Valid range for lo is -4095 -> 4095 */
3950 : -((-offset
) & 0xfff));
3952 /* Corner case, if lo is the max offset then we would be out of range
3953 once we have added the additional 1 below, so bump the msb into the
3954 pre-loading insn(s). */
3958 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xFFFFFFFFUL
)
3959 ^ (HOST_WIDE_INT
) 0x80000000UL
)
3960 - (HOST_WIDE_INT
) 0x80000000UL
);
3962 if (hi
+ lo
!= offset
)
3967 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
3969 /* Get the base address; addsi3 knows how to handle constants
3970 that require more than one insn */
3971 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
3977 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
3978 emit_insn (gen_zero_extendqisi2 (scratch
,
3979 gen_rtx_MEM (QImode
,
3980 plus_constant (base
,
3982 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
3983 gen_rtx_MEM (QImode
,
3984 plus_constant (base
,
3986 if (! BYTES_BIG_ENDIAN
)
3987 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
3988 gen_rtx_IOR (SImode
,
3991 gen_rtx_SUBREG (SImode
, operands
[0], 0),
3995 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
3996 gen_rtx_IOR (SImode
,
3997 gen_rtx_ASHIFT (SImode
, scratch
,
3999 gen_rtx_SUBREG (SImode
, operands
[0],
4003 /* Handle storing a half-word to memory during reload by synthesising as two
4004 byte stores. Take care not to clobber the input values until after we
4005 have moved them somewhere safe. This code assumes that if the DImode
4006 scratch in operands[2] overlaps either the input value or output address
4007 in some way, then that value must die in this insn (we absolutely need
4008 two scratch registers for some corner cases). */
4010 arm_reload_out_hi (operands
)
4013 rtx ref
= operands
[0];
4014 rtx outval
= operands
[1];
4016 HOST_WIDE_INT offset
= 0;
4018 if (GET_CODE (ref
) == SUBREG
)
4020 offset
= SUBREG_WORD (ref
) * UNITS_PER_WORD
;
4021 if (BYTES_BIG_ENDIAN
)
4022 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (ref
)))
4023 - MIN (UNITS_PER_WORD
,
4024 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref
)))));
4025 ref
= SUBREG_REG (ref
);
4029 if (GET_CODE (ref
) == REG
)
4031 /* We have a pseudo which has been spilt onto the stack; there
4032 are two cases here: the first where there is a simple
4033 stack-slot replacement and a second where the stack-slot is
4034 out of range, or is used as a subreg. */
4035 if (reg_equiv_mem
[REGNO (ref
)])
4037 ref
= reg_equiv_mem
[REGNO (ref
)];
4038 base
= find_replacement (&XEXP (ref
, 0));
4041 /* The slot is out of range, or was dressed up in a SUBREG */
4042 base
= reg_equiv_address
[REGNO (ref
)];
4045 base
= find_replacement (&XEXP (ref
, 0));
4047 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
4049 /* Handle the case where the address is too complex to be offset by 1. */
4050 if (GET_CODE (base
) == MINUS
4051 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
4053 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
4055 /* Be careful not to destroy OUTVAL. */
4056 if (reg_overlap_mentioned_p (base_plus
, outval
))
4058 /* Updating base_plus might destroy outval, see if we can
4059 swap the scratch and base_plus. */
4060 if (! reg_overlap_mentioned_p (scratch
, outval
))
4063 scratch
= base_plus
;
4068 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
4070 /* Be conservative and copy OUTVAL into the scratch now,
4071 this should only be necessary if outval is a subreg
4072 of something larger than a word. */
4073 /* XXX Might this clobber base? I can't see how it can,
4074 since scratch is known to overlap with OUTVAL, and
4075 must be wider than a word. */
4076 emit_insn (gen_movhi (scratch_hi
, outval
));
4077 outval
= scratch_hi
;
4081 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
4084 else if (GET_CODE (base
) == PLUS
)
4086 /* The addend must be CONST_INT, or we would have dealt with it above */
4087 HOST_WIDE_INT hi
, lo
;
4089 offset
+= INTVAL (XEXP (base
, 1));
4090 base
= XEXP (base
, 0);
4092 /* Rework the address into a legal sequence of insns */
4093 /* Valid range for lo is -4095 -> 4095 */
4096 : -((-offset
) & 0xfff));
4098 /* Corner case, if lo is the max offset then we would be out of range
4099 once we have added the additional 1 below, so bump the msb into the
4100 pre-loading insn(s). */
4104 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xFFFFFFFFUL
)
4105 ^ (HOST_WIDE_INT
) 0x80000000UL
)
4106 - (HOST_WIDE_INT
) 0x80000000UL
);
4108 if (hi
+ lo
!= offset
)
4113 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
4115 /* Be careful not to destroy OUTVAL. */
4116 if (reg_overlap_mentioned_p (base_plus
, outval
))
4118 /* Updating base_plus might destroy outval, see if we
4119 can swap the scratch and base_plus. */
4120 if (! reg_overlap_mentioned_p (scratch
, outval
))
4123 scratch
= base_plus
;
4128 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
4130 /* Be conservative and copy outval into scratch now,
4131 this should only be necessary if outval is a
4132 subreg of something larger than a word. */
4133 /* XXX Might this clobber base? I can't see how it
4134 can, since scratch is known to overlap with
4136 emit_insn (gen_movhi (scratch_hi
, outval
));
4137 outval
= scratch_hi
;
4141 /* Get the base address; addsi3 knows how to handle constants
4142 that require more than one insn */
4143 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
4149 if (BYTES_BIG_ENDIAN
)
4151 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
4152 plus_constant (base
, offset
+ 1)),
4153 gen_rtx_SUBREG (QImode
, outval
, 0)));
4154 emit_insn (gen_lshrsi3 (scratch
,
4155 gen_rtx_SUBREG (SImode
, outval
, 0),
4157 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
4158 gen_rtx_SUBREG (QImode
, scratch
, 0)));
4162 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
4163 gen_rtx_SUBREG (QImode
, outval
, 0)));
4164 emit_insn (gen_lshrsi3 (scratch
,
4165 gen_rtx_SUBREG (SImode
, outval
, 0),
4167 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
4168 plus_constant (base
, offset
+ 1)),
4169 gen_rtx_SUBREG (QImode
, scratch
, 0)));
4173 /* Routines for manipulation of the constant pool. */
4175 /* Arm instructions cannot load a large constant directly into a
4176 register; they have to come from a pc relative load. The constant
4177 must therefore be placed in the addressable range of the pc
4178 relative load. Depending on the precise pc relative load
4179 instruction the range is somewhere between 256 bytes and 4k. This
4180 means that we often have to dump a constant inside a function, and
4181 generate code to branch around it.
4183 It is important to minimize this, since the branches will slow
4184 things down and make the code larger.
4186 Normally we can hide the table after an existing unconditional
4187 branch so that there is no interruption of the flow, but in the
4188 worst case the code looks like this:
4206 We fix this by performing a scan after scheduling, which notices
4207 which instructions need to have their operands fetched from the
4208 constant table and builds the table.
4210 The algorithm starts by building a table of all the constants that
4211 need fixing up and all the natural barriers in the function (places
4212 where a constant table can be dropped without breaking the flow).
4213 For each fixup we note how far the pc-relative replacement will be
4214 able to reach and the offset of the instruction into the function.
4216 Having built the table we then group the fixes together to form
4217 tables that are as large as possible (subject to addressing
4218 constraints) and emit each table of constants after the last
4219 barrier that is within range of all the instructions in the group.
4220 If a group does not contain a barrier, then we forcibly create one
4221 by inserting a jump instruction into the flow. Once the table has
4222 been inserted, the insns are then modified to reference the
4223 relevant entry in the pool.
4225 Possible enhancements to the alogorithm (not implemented) are:
4227 1) ARM instructions (but not thumb) can use negative offsets, so we
4228 could reference back to a previous pool rather than forwards to a
4229 new one. For large functions this may reduce the number of pools
4232 2) For some processors and object formats, there may be benefit in
4233 aligning the pools to the start of cache lines; this alignment
4234 would need to be taken into account when calculating addressability
4241 rtx value
; /* Value in table */
4242 HOST_WIDE_INT next_offset
;
4243 enum machine_mode mode
; /* Mode of value */
4246 /* The maximum number of constants that can fit into one pool, since
4247 the pc relative range is 0...4092 bytes and constants are at least 4
4250 #define MAX_MINIPOOL_SIZE (4092/4)
4251 static minipool_node minipool_vector
[MAX_MINIPOOL_SIZE
];
4252 static int minipool_size
;
4253 static rtx minipool_vector_label
;
4255 /* Add a constant to the pool and return its offset within the current
4258 X is the rtx we want to replace. MODE is its mode. On return,
4259 ADDRESS_ONLY will be non-zero if we really want the address of such
4260 a constant, not the constant itself. */
4261 static HOST_WIDE_INT
4262 add_minipool_constant (x
, mode
)
4264 enum machine_mode mode
;
4267 HOST_WIDE_INT offset
;
4269 /* First, see if we've already got it. */
4270 for (i
= 0; i
< minipool_size
; i
++)
4272 if (GET_CODE (x
) == minipool_vector
[i
].value
->code
4273 && mode
== minipool_vector
[i
].mode
)
4275 if (GET_CODE (x
) == CODE_LABEL
)
4277 if (XINT (x
, 3) != XINT (minipool_vector
[i
].value
, 3))
4280 if (rtx_equal_p (x
, minipool_vector
[i
].value
))
4281 return minipool_vector
[i
].next_offset
- GET_MODE_SIZE (mode
);
4285 /* Need a new one */
4286 minipool_vector
[minipool_size
].next_offset
= GET_MODE_SIZE (mode
);
4288 if (minipool_size
== 0)
4289 minipool_vector_label
= gen_label_rtx ();
4291 minipool_vector
[minipool_size
].next_offset
4292 += (offset
= minipool_vector
[minipool_size
- 1].next_offset
);
4294 minipool_vector
[minipool_size
].value
= x
;
4295 minipool_vector
[minipool_size
].mode
= mode
;
4300 /* Output the literal table */
4302 dump_minipool (scan
)
4307 scan
= emit_label_after (gen_label_rtx (), scan
);
4308 scan
= emit_insn_after (gen_align_4 (), scan
);
4309 scan
= emit_label_after (minipool_vector_label
, scan
);
4311 for (i
= 0; i
< minipool_size
; i
++)
4313 minipool_node
*p
= minipool_vector
+ i
;
4315 switch (GET_MODE_SIZE (p
->mode
))
4318 scan
= emit_insn_after (gen_consttable_4 (p
->value
), scan
);
4322 scan
= emit_insn_after (gen_consttable_8 (p
->value
), scan
);
4331 scan
= emit_insn_after (gen_consttable_end (), scan
);
4332 scan
= emit_barrier_after (scan
);
4336 /* Find the last barrier less than MAX_COUNT bytes from FROM, or
4339 find_barrier (from
, max_count
)
4344 rtx found_barrier
= 0;
4347 while (from
&& count
< max_count
)
4351 if (GET_CODE (from
) == BARRIER
)
4352 found_barrier
= from
;
4354 /* Count the length of this insn */
4355 if (GET_CODE (from
) == JUMP_INSN
4356 && JUMP_LABEL (from
) != 0
4357 && ((tmp
= next_real_insn (JUMP_LABEL (from
)))
4358 == next_real_insn (from
))
4360 && GET_CODE (tmp
) == JUMP_INSN
4361 && (GET_CODE (PATTERN (tmp
)) == ADDR_VEC
4362 || GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
))
4364 int elt
= GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
? 1 : 0;
4365 count
+= (get_attr_length (from
)
4366 + GET_MODE_SIZE (SImode
) * XVECLEN (PATTERN (tmp
), elt
));
4367 /* Continue after the dispatch table. */
4369 from
= NEXT_INSN (tmp
);
4373 count
+= get_attr_length (from
);
4376 from
= NEXT_INSN (from
);
4379 if (! found_barrier
)
4381 /* We didn't find a barrier in time to
4382 dump our stuff, so we'll make one. */
4383 rtx label
= gen_label_rtx ();
4386 from
= PREV_INSN (last
);
4388 from
= get_last_insn ();
4390 /* Walk back to be just before any jump. */
4391 while (GET_CODE (from
) == JUMP_INSN
4392 || GET_CODE (from
) == NOTE
4393 || GET_CODE (from
) == CODE_LABEL
)
4394 from
= PREV_INSN (from
);
4396 from
= emit_jump_insn_after (gen_jump (label
), from
);
4397 JUMP_LABEL (from
) = label
;
4398 found_barrier
= emit_barrier_after (from
);
4399 emit_label_after (label
, found_barrier
);
4402 return found_barrier
;
4405 struct minipool_fixup
4407 struct minipool_fixup
*next
;
4411 enum machine_mode mode
;
4416 struct minipool_fixup
*minipool_fix_head
;
4417 struct minipool_fixup
*minipool_fix_tail
;
4420 push_minipool_barrier (insn
, address
)
4424 struct minipool_fixup
*fix
4425 = (struct minipool_fixup
*) oballoc (sizeof (struct minipool_fixup
));
4428 fix
->address
= address
;
4431 if (minipool_fix_head
!= NULL
)
4432 minipool_fix_tail
->next
= fix
;
4434 minipool_fix_head
= fix
;
4436 minipool_fix_tail
= fix
;
4440 push_minipool_fix (insn
, address
, loc
, mode
, value
)
4444 enum machine_mode mode
;
4447 struct minipool_fixup
*fix
4448 = (struct minipool_fixup
*) oballoc (sizeof (struct minipool_fixup
));
4450 #ifdef AOF_ASSEMBLER
4451 /* PIC symbol refereneces need to be converted into offsets into the
4453 if (flag_pic
&& GET_MODE
== SYMBOL_REF
)
4454 value
= aof_pic_entry (value
);
4455 #endif /* AOF_ASSEMBLER */
4458 fix
->address
= address
;
4462 fix
->range
= get_attr_pool_range (insn
);
4464 /* If an insn doesn't have a range defined for it, then it isn't
4465 expecting to be reworked by this code. Better to abort now than
4466 to generate duff assembly code. */
4467 if (fix
->range
== 0)
4470 /* Add it to the chain of fixes */
4472 if (minipool_fix_head
!= NULL
)
4473 minipool_fix_tail
->next
= fix
;
4475 minipool_fix_head
= fix
;
4477 minipool_fix_tail
= fix
;
4481 note_invalid_constants (insn
, address
)
4487 /* Extract the operands of the insn */
4490 /* Find the alternative selected */
4491 if (! constrain_operands (1))
4492 fatal_insn_not_found (insn
);
4494 /* Preprocess the constraints, to extract some useful information. */
4495 preprocess_constraints ();
4497 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
4499 /* Things we need to fix can only occur in inputs */
4500 if (recog_data
.operand_type
[opno
] != OP_IN
)
4503 /* If this alternative is a memory reference, then any mention
4504 of constants in this alternative is really to fool reload
4505 into allowing us to accept one there. We need to fix them up
4506 now so that we output the right code. */
4507 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
4509 rtx op
= recog_data
.operand
[opno
];
4511 if (CONSTANT_P (op
))
4512 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
4513 recog_data
.operand_mode
[opno
], op
);
4514 #ifndef AOF_ASSEMBLER
4515 else if (GET_CODE (op
) == UNSPEC
&& XINT (op
, 1) == 3)
4516 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
4517 recog_data
.operand_mode
[opno
],
4518 XVECEXP (op
, 0, 0));
4520 else if (recog_data
.operand_mode
[opno
] == SImode
4521 && GET_CODE (op
) == MEM
4522 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
4523 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
4524 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
4525 recog_data
.operand_mode
[opno
],
4526 get_pool_constant (XEXP (op
, 0)));
4537 struct minipool_fixup
*fix
;
4539 minipool_fix_head
= minipool_fix_tail
= NULL
;
4541 /* The first insn must always be a note, or the code below won't
4542 scan it properly. */
4543 if (GET_CODE (first
) != NOTE
)
4546 /* Scan all the insns and record the operands that will need fixing. */
4547 for (insn
= next_nonnote_insn (first
); insn
; insn
= next_nonnote_insn (insn
))
4550 if (GET_CODE (insn
) == BARRIER
)
4551 push_minipool_barrier(insn
, address
);
4552 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
4553 || GET_CODE (insn
) == JUMP_INSN
)
4557 note_invalid_constants (insn
, address
);
4558 address
+= get_attr_length (insn
);
4559 /* If the insn is a vector jump, add the size of the table
4560 and skip the table. */
4561 if (GET_CODE (insn
) == JUMP_INSN
4562 && JUMP_LABEL (insn
) != NULL
4563 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
4564 == next_real_insn (insn
))
4566 && GET_CODE (table
) == JUMP_INSN
4567 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
4568 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
4570 int elt
= GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
? 1 : 0;
4572 address
+= GET_MODE_SIZE (SImode
) * XVECLEN (PATTERN (table
),
4579 /* Now scan the fixups and perform the required changes. */
4580 for (fix
= minipool_fix_head
; fix
; fix
= fix
->next
)
4582 struct minipool_fixup
*ftmp
;
4583 struct minipool_fixup
*last_barrier
= NULL
;
4586 struct minipool_fixup
*this_fix
;
4587 int new_minipool_size
= 0;
4589 /* Skip any further barriers before the next fix. */
4590 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
4597 max_range
= fix
->address
+ fix
->range
;
4599 /* Find all the other fixes that can live in the same pool. */
4600 while (ftmp
->next
&& ftmp
->next
->address
< max_range
4601 && (GET_CODE (ftmp
->next
->insn
) == BARRIER
4602 /* Ensure we can reach the constant inside the pool. */
4603 || ftmp
->next
->range
> new_minipool_size
))
4606 if (GET_CODE (ftmp
->insn
) == BARRIER
)
4607 last_barrier
= ftmp
;
4610 /* Does this fix constrain the range we can search? */
4611 if (ftmp
->address
+ ftmp
->range
- new_minipool_size
< max_range
)
4612 max_range
= ftmp
->address
+ ftmp
->range
- new_minipool_size
;
4614 new_minipool_size
+= GET_MODE_SIZE (ftmp
->mode
);
4618 /* If we found a barrier, drop back to that; any fixes that we could
4619 have reached but come after the barrier will now go in the next
4621 if (last_barrier
!= NULL
)
4623 barrier
= last_barrier
->insn
;
4624 ftmp
= last_barrier
;
4626 /* ftmp is last fix that we can fit into this pool and we
4627 failed to find a barrier that we could use. Insert a new
4628 barrier in the code and arrange to jump around it. */
4631 /* Check that there isn't another fix that is in range that
4632 we couldn't fit into this pool because the pool was
4633 already too large: we need to put the pool before such an
4635 if (ftmp
->next
&& ftmp
->next
->address
< max_range
)
4636 max_range
= ftmp
->address
;
4638 barrier
= find_barrier (ftmp
->insn
, max_range
- ftmp
->address
);
4641 /* Scan over the fixes we have identified for this pool, fixing them
4642 up and adding the constants to the pool itself. */
4643 for (this_fix
= fix
; this_fix
&& ftmp
->next
!= this_fix
;
4644 this_fix
= this_fix
->next
)
4645 if (GET_CODE (this_fix
->insn
) != BARRIER
)
4647 int offset
= add_minipool_constant (this_fix
->value
,
4650 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
4651 minipool_vector_label
),
4653 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
4656 dump_minipool (barrier
);
4660 /* From now on we must synthesize any constants that we can't handle
4661 directly. This can happen if the RTL gets split during final
4662 instruction generation. */
4663 after_arm_reorg
= 1;
4667 /* Routines to output assembly language. */
4669 /* If the rtx is the correct value then return the string of the number.
4670 In this way we can ensure that valid double constants are generated even
4671 when cross compiling. */
4673 fp_immediate_constant (x
)
4679 if (!fpa_consts_inited
)
4682 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4683 for (i
= 0; i
< 8; i
++)
4684 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
4685 return strings_fpa
[i
];
4690 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
4692 fp_const_from_val (r
)
4693 REAL_VALUE_TYPE
* r
;
4697 if (! fpa_consts_inited
)
4700 for (i
= 0; i
< 8; i
++)
4701 if (REAL_VALUES_EQUAL (*r
, values_fpa
[i
]))
4702 return strings_fpa
[i
];
4707 /* Output the operands of a LDM/STM instruction to STREAM.
4708 MASK is the ARM register set mask of which only bits 0-15 are important.
4709 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
4710 must follow the register list. */
4713 print_multi_reg (stream
, instr
, reg
, mask
, hat
)
4721 int not_first
= FALSE
;
4723 fputc ('\t', stream
);
4724 asm_fprintf (stream
, instr
, reg
);
4725 fputs (", {", stream
);
4727 for (i
= 0; i
< 16; i
++)
4728 if (mask
& (1 << i
))
4731 fprintf (stream
, ", ");
4733 asm_fprintf (stream
, "%r", i
);
4737 fprintf (stream
, "}%s\n", hat
? "^" : "");
4740 /* Output a 'call' insn. */
4743 output_call (operands
)
4746 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
4748 if (REGNO (operands
[0]) == LR_REGNUM
)
4750 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
4751 output_asm_insn ("mov%?\t%0, %|lr", operands
);
4754 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
4756 if (TARGET_INTERWORK
)
4757 output_asm_insn ("bx%?\t%0", operands
);
4759 output_asm_insn ("mov%?\t%|pc, %0", operands
);
4768 int something_changed
= 0;
4770 int code
= GET_CODE (x0
);
4772 register const char * fmt
;
4777 if (REGNO (x0
) == LR_REGNUM
)
4779 *x
= gen_rtx_REG (SImode
, IP_REGNUM
);
4784 /* Scan through the sub-elements and change any references there */
4785 fmt
= GET_RTX_FORMAT (code
);
4787 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4789 something_changed
|= eliminate_lr2ip (&XEXP (x0
, i
));
4790 else if (fmt
[i
] == 'E')
4791 for (j
= 0; j
< XVECLEN (x0
, i
); j
++)
4792 something_changed
|= eliminate_lr2ip (&XVECEXP (x0
, i
, j
));
4794 return something_changed
;
4798 /* Output a 'call' insn that is a reference in memory. */
4801 output_call_mem (operands
)
4804 operands
[0] = copy_rtx (operands
[0]); /* Be ultra careful */
4805 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
4807 if (eliminate_lr2ip (&operands
[0]))
4808 output_asm_insn ("mov%?\t%|ip, %|lr", operands
);
4810 if (TARGET_INTERWORK
)
4812 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
4813 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
4814 output_asm_insn ("bx%?\t%|ip", operands
);
4818 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
4819 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
4826 /* Output a move from arm registers to an fpu registers.
4827 OPERANDS[0] is an fpu register.
4828 OPERANDS[1] is the first registers of an arm register pair. */
4831 output_mov_long_double_fpu_from_arm (operands
)
4834 int arm_reg0
= REGNO (operands
[1]);
4837 if (arm_reg0
== IP_REGNUM
)
4840 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
4841 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
4842 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
4844 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
4845 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
4850 /* Output a move from an fpu register to arm registers.
4851 OPERANDS[0] is the first registers of an arm register pair.
4852 OPERANDS[1] is an fpu register. */
4855 output_mov_long_double_arm_from_fpu (operands
)
4858 int arm_reg0
= REGNO (operands
[0]);
4861 if (arm_reg0
== IP_REGNUM
)
4864 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
4865 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
4866 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
4868 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
4869 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
4873 /* Output a move from arm registers to arm registers of a long double
4874 OPERANDS[0] is the destination.
4875 OPERANDS[1] is the source. */
4877 output_mov_long_double_arm_from_arm (operands
)
4880 /* We have to be careful here because the two might overlap */
4881 int dest_start
= REGNO (operands
[0]);
4882 int src_start
= REGNO (operands
[1]);
4886 if (dest_start
< src_start
)
4888 for (i
= 0; i
< 3; i
++)
4890 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
4891 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
4892 output_asm_insn ("mov%?\t%0, %1", ops
);
4897 for (i
= 2; i
>= 0; i
--)
4899 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
4900 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
4901 output_asm_insn ("mov%?\t%0, %1", ops
);
4909 /* Output a move from arm registers to an fpu registers.
4910 OPERANDS[0] is an fpu register.
4911 OPERANDS[1] is the first registers of an arm register pair. */
4914 output_mov_double_fpu_from_arm (operands
)
4917 int arm_reg0
= REGNO (operands
[1]);
4920 if (arm_reg0
== IP_REGNUM
)
4923 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
4924 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
4925 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
4926 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
4930 /* Output a move from an fpu register to arm registers.
4931 OPERANDS[0] is the first registers of an arm register pair.
4932 OPERANDS[1] is an fpu register. */
4935 output_mov_double_arm_from_fpu (operands
)
4938 int arm_reg0
= REGNO (operands
[0]);
4941 if (arm_reg0
== IP_REGNUM
)
4944 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
4945 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
4946 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
4947 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
4951 /* Output a move between double words.
4952 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4953 or MEM<-REG and all MEMs must be offsettable addresses. */
4956 output_move_double (operands
)
4959 enum rtx_code code0
= GET_CODE (operands
[0]);
4960 enum rtx_code code1
= GET_CODE (operands
[1]);
4965 int reg0
= REGNO (operands
[0]);
4967 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
4971 int reg1
= REGNO (operands
[1]);
4972 if (reg1
== IP_REGNUM
)
4975 /* Ensure the second source is not overwritten */
4976 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
4977 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
4979 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
4981 else if (code1
== CONST_DOUBLE
)
4983 if (GET_MODE (operands
[1]) == DFmode
)
4986 union real_extract u
;
4988 bcopy ((char *) &CONST_DOUBLE_LOW (operands
[1]), (char *) &u
,
4990 REAL_VALUE_TO_TARGET_DOUBLE (u
.d
, l
);
4991 otherops
[1] = GEN_INT(l
[1]);
4992 operands
[1] = GEN_INT(l
[0]);
4994 else if (GET_MODE (operands
[1]) != VOIDmode
)
4996 else if (WORDS_BIG_ENDIAN
)
4999 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
5000 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
5005 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
5006 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
5009 output_mov_immediate (operands
);
5010 output_mov_immediate (otherops
);
5012 else if (code1
== CONST_INT
)
5014 #if HOST_BITS_PER_WIDE_INT > 32
5015 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
5016 what the upper word is. */
5017 if (WORDS_BIG_ENDIAN
)
5019 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
5020 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
5024 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
5025 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
5028 /* Sign extend the intval into the high-order word */
5029 if (WORDS_BIG_ENDIAN
)
5031 otherops
[1] = operands
[1];
5032 operands
[1] = (INTVAL (operands
[1]) < 0
5033 ? constm1_rtx
: const0_rtx
);
5036 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
5038 output_mov_immediate (otherops
);
5039 output_mov_immediate (operands
);
5041 else if (code1
== MEM
)
5043 switch (GET_CODE (XEXP (operands
[1], 0)))
5046 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
5050 abort (); /* Should never happen now */
5054 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
5058 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
5062 abort (); /* Should never happen now */
5067 output_asm_insn ("adr%?\t%0, %1", operands
);
5068 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
5072 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
5073 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
5075 otherops
[0] = operands
[0];
5076 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
5077 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
5078 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
5080 if (GET_CODE (otherops
[2]) == CONST_INT
)
5082 switch (INTVAL (otherops
[2]))
5085 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
5088 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
5091 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
5094 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
5095 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
5097 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
5100 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
5103 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
5105 return "ldm%?ia\t%0, %M0";
5109 otherops
[1] = adj_offsettable_operand (operands
[1], 4);
5110 /* Take care of overlapping base/data reg. */
5111 if (reg_mentioned_p (operands
[0], operands
[1]))
5113 output_asm_insn ("ldr%?\t%0, %1", otherops
);
5114 output_asm_insn ("ldr%?\t%0, %1", operands
);
5118 output_asm_insn ("ldr%?\t%0, %1", operands
);
5119 output_asm_insn ("ldr%?\t%0, %1", otherops
);
5125 abort (); /* Constraints should prevent this */
5127 else if (code0
== MEM
&& code1
== REG
)
5129 if (REGNO (operands
[1]) == IP_REGNUM
)
5132 switch (GET_CODE (XEXP (operands
[0], 0)))
5135 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
5139 abort (); /* Should never happen now */
5143 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
5147 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
5151 abort (); /* Should never happen now */
5155 if (GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
)
5157 switch (INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
5160 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
5164 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
5168 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
5175 otherops
[0] = adj_offsettable_operand (operands
[0], 4);
5176 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
5177 output_asm_insn ("str%?\t%1, %0", operands
);
5178 output_asm_insn ("str%?\t%1, %0", otherops
);
5182 abort (); /* Constraints should prevent this */
5188 /* Output an arbitrary MOV reg, #n.
5189 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
5192 output_mov_immediate (operands
)
5195 HOST_WIDE_INT n
= INTVAL (operands
[1]);
5199 /* Try to use one MOV */
5200 if (const_ok_for_arm (n
))
5202 output_asm_insn ("mov%?\t%0, %1", operands
);
5206 /* Try to use one MVN */
5207 if (const_ok_for_arm (~n
))
5209 operands
[1] = GEN_INT (~n
);
5210 output_asm_insn ("mvn%?\t%0, %1", operands
);
5214 /* If all else fails, make it out of ORRs or BICs as appropriate. */
5216 for (i
=0; i
< 32; i
++)
5220 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
5221 output_multi_immediate(operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
5224 output_multi_immediate(operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
5231 /* Output an ADD r, s, #n where n may be too big for one instruction. If
5232 adding zero to one register, output nothing. */
5235 output_add_immediate (operands
)
5238 HOST_WIDE_INT n
= INTVAL (operands
[2]);
5240 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
5243 output_multi_immediate (operands
,
5244 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
5247 output_multi_immediate (operands
,
5248 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
5255 /* Output a multiple immediate operation.
5256 OPERANDS is the vector of operands referred to in the output patterns.
5257 INSTR1 is the output pattern to use for the first constant.
5258 INSTR2 is the output pattern to use for subsequent constants.
5259 IMMED_OP is the index of the constant slot in OPERANDS.
5260 N is the constant value. */
5263 output_multi_immediate (operands
, instr1
, instr2
, immed_op
, n
)
5265 char * instr1
, * instr2
;
5269 #if HOST_BITS_PER_WIDE_INT > 32
5275 operands
[immed_op
] = const0_rtx
;
5276 output_asm_insn (instr1
, operands
); /* Quick and easy output */
5281 char *instr
= instr1
;
5283 /* Note that n is never zero here (which would give no output) */
5284 for (i
= 0; i
< 32; i
+= 2)
5288 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
5289 output_asm_insn (instr
, operands
);
5299 /* Return the appropriate ARM instruction for the operation code.
5300 The returned result should not be overwritten. OP is the rtx of the
5301 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
5305 arithmetic_instr (op
, shift_first_arg
)
5307 int shift_first_arg
;
5309 switch (GET_CODE (op
))
5315 return shift_first_arg
? "rsb" : "sub";
5332 /* Ensure valid constant shifts and return the appropriate shift mnemonic
5333 for the operation code. The returned result should not be overwritten.
5334 OP is the rtx code of the shift.
5335 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
5339 shift_op (op
, amountp
)
5341 HOST_WIDE_INT
*amountp
;
5344 enum rtx_code code
= GET_CODE (op
);
5346 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
5348 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
5349 *amountp
= INTVAL (XEXP (op
, 1));
5372 /* We never have to worry about the amount being other than a
5373 power of 2, since this case can never be reloaded from a reg. */
5375 *amountp
= int_log2 (*amountp
);
5386 /* This is not 100% correct, but follows from the desire to merge
5387 multiplication by a power of 2 with the recognizer for a
5388 shift. >=32 is not a valid shift for "asl", so we must try and
5389 output a shift that produces the correct arithmetical result.
5390 Using lsr #32 is identical except for the fact that the carry bit
5391 is not set correctly if we set the flags; but we never use the
5392 carry bit from such an operation, so we can ignore that. */
5393 if (code
== ROTATERT
)
5394 *amountp
&= 31; /* Rotate is just modulo 32 */
5395 else if (*amountp
!= (*amountp
& 31))
5402 /* Shifts of 0 are no-ops. */
5411 /* Obtain the shift from the POWER of two. */
5413 static HOST_WIDE_INT
5415 HOST_WIDE_INT power
;
5417 HOST_WIDE_INT shift
= 0;
5419 while (((((HOST_WIDE_INT
) 1) << shift
) & power
) == 0)
5429 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
5430 /bin/as is horribly restrictive. */
5431 #define MAX_ASCII_LEN 51
5434 output_ascii_pseudo_op (stream
, p
, len
)
5442 fputs ("\t.ascii\t\"", stream
);
5444 for (i
= 0; i
< len
; i
++)
5446 register int c
= p
[i
];
5448 if (len_so_far
>= MAX_ASCII_LEN
)
5450 fputs ("\"\n\t.ascii\t\"", stream
);
5457 fputs ("\\t", stream
);
5462 fputs ("\\f", stream
);
5467 fputs ("\\b", stream
);
5472 fputs ("\\r", stream
);
5476 case TARGET_NEWLINE
:
5477 fputs ("\\n", stream
);
5479 if ((c
>= ' ' && c
<= '~')
5481 /* This is a good place for a line break. */
5482 len_so_far
= MAX_ASCII_LEN
;
5489 putc ('\\', stream
);
5494 if (c
>= ' ' && c
<= '~')
5501 fprintf (stream
, "\\%03o", c
);
5508 fputs ("\"\n", stream
);
5512 /* Try to determine whether a pattern really clobbers the link register.
5513 This information is useful when peepholing, so that lr need not be pushed
5514 if we combine a call followed by a return.
5515 NOTE: This code does not check for side-effect expressions in a SET_SRC:
5516 such a check should not be needed because these only update an existing
5517 value within a register; the register must still be set elsewhere within
5521 pattern_really_clobbers_lr (x
)
5526 switch (GET_CODE (x
))
5529 switch (GET_CODE (SET_DEST (x
)))
5532 return REGNO (SET_DEST (x
)) == LR_REGNUM
;
5535 if (GET_CODE (XEXP (SET_DEST (x
), 0)) == REG
)
5536 return REGNO (XEXP (SET_DEST (x
), 0)) == LR_REGNUM
;
5538 if (GET_CODE (XEXP (SET_DEST (x
), 0)) == MEM
)
5547 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
5548 if (pattern_really_clobbers_lr (XVECEXP (x
, 0, i
)))
5553 switch (GET_CODE (XEXP (x
, 0)))
5556 return REGNO (XEXP (x
, 0)) == LR_REGNUM
;
5559 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
)
5560 return REGNO (XEXP (XEXP (x
, 0), 0)) == LR_REGNUM
;
5576 function_really_clobbers_lr (first
)
5581 for (insn
= first
; insn
; insn
= next_nonnote_insn (insn
))
5583 switch (GET_CODE (insn
))
5588 case JUMP_INSN
: /* Jump insns only change the PC (and conds) */
5592 if (pattern_really_clobbers_lr (PATTERN (insn
)))
5597 /* Don't yet know how to handle those calls that are not to a
5599 if (GET_CODE (PATTERN (insn
)) != PARALLEL
)
5602 switch (GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)))
5605 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn
), 0, 0), 0), 0))
5611 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn
),
5617 default: /* Don't recognize it, be safe */
5621 /* A call can be made (by peepholing) not to clobber lr iff it is
5622 followed by a return. There may, however, be a use insn iff
5623 we are returning the result of the call.
5624 If we run off the end of the insn chain, then that means the
5625 call was at the end of the function. Unfortunately we don't
5626 have a return insn for the peephole to recognize, so we
5627 must reject this. (Can this be fixed by adding our own insn?) */
5628 if ((next
= next_nonnote_insn (insn
)) == NULL
)
5631 /* No need to worry about lr if the call never returns */
5632 if (GET_CODE (next
) == BARRIER
)
5635 if (GET_CODE (next
) == INSN
&& GET_CODE (PATTERN (next
)) == USE
5636 && (GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
5637 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn
), 0, 0)))
5638 == REGNO (XEXP (PATTERN (next
), 0))))
5639 if ((next
= next_nonnote_insn (next
)) == NULL
)
5642 if (GET_CODE (next
) == JUMP_INSN
5643 && GET_CODE (PATTERN (next
)) == RETURN
)
5652 /* We have reached the end of the chain so lr was _not_ clobbered */
5657 output_return_instruction (operand
, really_return
, reverse
)
5663 int reg
, live_regs
= 0;
5664 int volatile_func
= (optimize
> 0
5665 && TREE_THIS_VOLATILE (current_function_decl
));
5667 return_used_this_function
= 1;
5669 if (TARGET_ABORT_NORETURN
&& volatile_func
)
5671 /* If this function was declared non-returning, and we have found a tail
5672 call, then we have to trust that the called function won't return. */
5677 /* Otherwise, trap an attempted return by aborting. */
5679 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
5681 assemble_external_libcall (ops
[1]);
5682 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
5688 if (current_function_calls_alloca
&& ! really_return
)
5691 for (reg
= 0; reg
<= 10; reg
++)
5692 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5695 if (flag_pic
&& ! TARGET_SINGLE_PIC_BASE
5696 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
5699 if (live_regs
|| (regs_ever_live
[LR_REGNUM
] && ! lr_save_eliminated
))
5702 if (frame_pointer_needed
)
5705 /* On some ARM architectures it is faster to use LDR rather than LDM to
5706 load a single register. On other architectures, the cost is the same. */
5708 && regs_ever_live
[LR_REGNUM
]
5709 && ! lr_save_eliminated
5710 /* FIXME: We ought to handle the case TARGET_APCS_32 is true,
5711 really_return is true, and only the PC needs restoring. */
5714 output_asm_insn (reverse
? "ldr%?%D0\t%|lr, [%|sp], #4"
5715 : "ldr%?%d0\t%|lr, [%|sp], #4", &operand
);
5719 if (lr_save_eliminated
|| ! regs_ever_live
[LR_REGNUM
])
5722 if (frame_pointer_needed
)
5724 reverse
? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
5727 reverse
? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
5729 for (reg
= 0; reg
<= 10; reg
++)
5730 if (regs_ever_live
[reg
]
5731 && (! call_used_regs
[reg
]
5732 || (flag_pic
&& ! TARGET_SINGLE_PIC_BASE
5733 && reg
== PIC_OFFSET_TABLE_REGNUM
)))
5735 strcat (instr
, "%|");
5736 strcat (instr
, reg_names
[reg
]);
5738 strcat (instr
, ", ");
5741 if (frame_pointer_needed
)
5743 strcat (instr
, "%|");
5744 strcat (instr
, reg_names
[11]);
5745 strcat (instr
, ", ");
5746 strcat (instr
, "%|");
5747 strcat (instr
, reg_names
[13]);
5748 strcat (instr
, ", ");
5749 strcat (instr
, "%|");
5750 strcat (instr
, TARGET_INTERWORK
|| (! really_return
)
5751 ? reg_names
[LR_REGNUM
] : reg_names
[PC_REGNUM
] );
5755 strcat (instr
, "%|");
5756 if (TARGET_INTERWORK
&& really_return
)
5757 strcat (instr
, reg_names
[IP_REGNUM
]);
5759 strcat (instr
, really_return
? reg_names
[PC_REGNUM
] : reg_names
[LR_REGNUM
]);
5761 strcat (instr
, (TARGET_APCS_32
|| !really_return
) ? "}" : "}^");
5762 output_asm_insn (instr
, &operand
);
5764 if (TARGET_INTERWORK
&& really_return
)
5766 strcpy (instr
, "bx%?");
5767 strcat (instr
, reverse
? "%D0" : "%d0");
5768 strcat (instr
, "\t%|");
5769 strcat (instr
, frame_pointer_needed
? "lr" : "ip");
5771 output_asm_insn (instr
, & operand
);
5774 else if (really_return
)
5776 if (TARGET_INTERWORK
)
5777 sprintf (instr
, "bx%%?%%%s0\t%%|lr", reverse
? "D" : "d");
5779 sprintf (instr
, "mov%%?%%%s0%s\t%%|pc, %%|lr",
5780 reverse
? "D" : "d", TARGET_APCS_32
? "" : "s");
5782 output_asm_insn (instr
, & operand
);
5788 /* Return nonzero if optimizing and the current function is volatile.
5789 Such functions never return, and many memory cycles can be saved
5790 by not storing register values that will never be needed again.
5791 This optimization was added to speed up context switching in a
5792 kernel application. */
5795 arm_volatile_func ()
5797 return (optimize
> 0 && TREE_THIS_VOLATILE (current_function_decl
));
5800 /* Write the function name into the code section, directly preceding
5801 the function prologue.
5803 Code will be output similar to this:
5805 .ascii "arm_poke_function_name", 0
5808 .word 0xff000000 + (t1 - t0)
5809 arm_poke_function_name
5811 stmfd sp!, {fp, ip, lr, pc}
5814 When performing a stack backtrace, code can inspect the value
5815 of 'pc' stored at 'fp' + 0. If the trace function then looks
5816 at location pc - 12 and the top 8 bits are set, then we know
5817 that there is a function name embedded immediately preceding this
5818 location and has length ((pc[-3]) & 0xff000000).
5820 We assume that pc is declared as a pointer to an unsigned long.
5822 It is of no benefit to output the function name if we are assembling
5823 a leaf function. These function types will not contain a stack
5824 backtrace structure, therefore it is not possible to determine the
5828 arm_poke_function_name (stream
, name
)
5832 unsigned long alignlength
;
5833 unsigned long length
;
5836 length
= strlen (name
) + 1;
5837 alignlength
= (length
+ 3) & ~3;
5839 ASM_OUTPUT_ASCII (stream
, name
, length
);
5840 ASM_OUTPUT_ALIGN (stream
, 2);
5841 x
= GEN_INT (0xff000000UL
+ alignlength
);
5842 ASM_OUTPUT_INT (stream
, x
);
5845 /* The amount of stack adjustment that happens here, in output_return and in
5846 output_epilogue must be exactly the same as was calculated during reload,
5847 or things will point to the wrong place. The only time we can safely
5848 ignore this constraint is when a function has no arguments on the stack,
5849 no stack frame requirement and no live registers execpt for `lr'. If we
5850 can guarantee that by making all function calls into tail calls and that
5851 lr is not clobbered in any other way, then there is no need to push lr
5855 output_func_prologue (f
, frame_size
)
5859 int reg
, live_regs_mask
= 0;
5860 int volatile_func
= (optimize
> 0
5861 && TREE_THIS_VOLATILE (current_function_decl
));
5863 /* Nonzero if we must stuff some register arguments onto the stack as if
5864 they were passed there. */
5865 int store_arg_regs
= 0;
5867 if (arm_ccfsm_state
|| arm_target_insn
)
5868 abort (); /* Sanity check */
5870 if (arm_naked_function_p (current_function_decl
))
5873 return_used_this_function
= 0;
5874 lr_save_eliminated
= 0;
5876 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %d\n",
5877 current_function_args_size
,
5878 current_function_pretend_args_size
, frame_size
);
5879 asm_fprintf (f
, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
5880 frame_pointer_needed
,
5881 current_function_anonymous_args
);
5884 asm_fprintf (f
, "\t%@ Volatile function.\n");
5886 if (current_function_anonymous_args
&& current_function_pretend_args_size
)
5889 for (reg
= 0; reg
<= 10; reg
++)
5890 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5891 live_regs_mask
|= (1 << reg
);
5893 if (flag_pic
&& ! TARGET_SINGLE_PIC_BASE
5894 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
5895 live_regs_mask
|= (1 << PIC_OFFSET_TABLE_REGNUM
);
5897 if (frame_pointer_needed
)
5898 live_regs_mask
|= 0xD800;
5899 else if (regs_ever_live
[LR_REGNUM
])
5901 if (! current_function_args_size
5902 && ! function_really_clobbers_lr (get_insns ()))
5903 lr_save_eliminated
= 1;
5905 live_regs_mask
|= 1 << LR_REGNUM
;
5910 /* if a di mode load/store multiple is used, and the base register
5911 is r3, then r4 can become an ever live register without lr
5912 doing so, in this case we need to push lr as well, or we
5913 will fail to get a proper return. */
5915 live_regs_mask
|= 1 << LR_REGNUM
;
5916 lr_save_eliminated
= 0;
5920 if (lr_save_eliminated
)
5921 asm_fprintf (f
,"\t%@ I don't think this function clobbers lr\n");
5923 #ifdef AOF_ASSEMBLER
5925 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
5930 arm_output_epilogue ()
5933 int live_regs_mask
= 0;
5934 /* If we need this, then it will always be at least this much */
5935 int floats_offset
= 12;
5937 int frame_size
= get_frame_size ();
5938 FILE *f
= asm_out_file
;
5939 int volatile_func
= (optimize
> 0
5940 && TREE_THIS_VOLATILE (current_function_decl
));
5942 if (use_return_insn (FALSE
) && return_used_this_function
)
5945 /* Naked functions don't have epilogues. */
5946 if (arm_naked_function_p (current_function_decl
))
5949 /* A volatile function should never return. Call abort. */
5950 if (TARGET_ABORT_NORETURN
&& volatile_func
)
5953 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
5954 assemble_external_libcall (op
);
5955 output_asm_insn ("bl\t%a0", &op
);
5959 for (reg
= 0; reg
<= 10; reg
++)
5960 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5962 live_regs_mask
|= (1 << reg
);
5966 /* If we aren't loading the PIC register, don't stack it even though it may
5968 if (flag_pic
&& ! TARGET_SINGLE_PIC_BASE
5969 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
5971 live_regs_mask
|= (1 << PIC_OFFSET_TABLE_REGNUM
);
5975 if (frame_pointer_needed
)
5977 if (arm_fpu_arch
== FP_SOFT2
)
5979 for (reg
= 23; reg
> 15; reg
--)
5980 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5982 floats_offset
+= 12;
5983 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
5984 reg
, FP_REGNUM
, floats_offset
);
5991 for (reg
= 23; reg
> 15; reg
--)
5993 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
5995 floats_offset
+= 12;
5997 /* We can't unstack more than four registers at once */
5998 if (start_reg
- reg
== 3)
6000 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
6001 reg
, FP_REGNUM
, floats_offset
);
6002 start_reg
= reg
- 1;
6007 if (reg
!= start_reg
)
6008 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
6009 reg
+ 1, start_reg
- reg
,
6010 FP_REGNUM
, floats_offset
);
6011 start_reg
= reg
- 1;
6015 /* Just in case the last register checked also needs unstacking. */
6016 if (reg
!= start_reg
)
6017 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
6018 reg
+ 1, start_reg
- reg
,
6019 FP_REGNUM
, floats_offset
);
6022 if (TARGET_INTERWORK
)
6024 live_regs_mask
|= 0x6800;
6025 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, live_regs_mask
, FALSE
);
6026 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
6030 live_regs_mask
|= 0xA800;
6031 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, live_regs_mask
,
6032 TARGET_APCS_32
? FALSE
: TRUE
);
6037 /* Restore stack pointer if necessary. */
6038 if (frame_size
+ current_function_outgoing_args_size
!= 0)
6040 operands
[0] = operands
[1] = stack_pointer_rtx
;
6041 operands
[2] = GEN_INT (frame_size
6042 + current_function_outgoing_args_size
);
6043 output_add_immediate (operands
);
6046 if (arm_fpu_arch
== FP_SOFT2
)
6048 for (reg
= 16; reg
< 24; reg
++)
6049 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
6050 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
6057 for (reg
= 16; reg
< 24; reg
++)
6059 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
6061 if (reg
- start_reg
== 3)
6063 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
6064 start_reg
, SP_REGNUM
);
6065 start_reg
= reg
+ 1;
6070 if (reg
!= start_reg
)
6071 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
6072 start_reg
, reg
- start_reg
,
6075 start_reg
= reg
+ 1;
6079 /* Just in case the last register checked also needs unstacking. */
6080 if (reg
!= start_reg
)
6081 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
6082 start_reg
, reg
- start_reg
, SP_REGNUM
);
6085 if (current_function_pretend_args_size
== 0 && regs_ever_live
[LR_REGNUM
])
6087 if (TARGET_INTERWORK
)
6089 if (! lr_save_eliminated
)
6090 live_regs_mask
|= 1 << LR_REGNUM
;
6092 if (live_regs_mask
!= 0)
6093 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, live_regs_mask
, FALSE
);
6095 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
6097 else if (lr_save_eliminated
)
6098 asm_fprintf (f
, "\tmov%c\t%r, %r\n",
6099 TARGET_APCS_32
? ' ' : 's',
6100 PC_REGNUM
, LR_REGNUM
);
6102 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, live_regs_mask
| 0x8000,
6103 TARGET_APCS_32
? FALSE
: TRUE
);
6107 if (live_regs_mask
|| regs_ever_live
[LR_REGNUM
])
6109 /* Restore the integer regs, and the return address into lr */
6110 if (! lr_save_eliminated
)
6111 live_regs_mask
|= 1 << LR_REGNUM
;
6113 if (live_regs_mask
!= 0)
6114 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, live_regs_mask
, FALSE
);
6117 if (current_function_pretend_args_size
)
6119 /* Unwind the pre-pushed regs */
6120 operands
[0] = operands
[1] = stack_pointer_rtx
;
6121 operands
[2] = GEN_INT (current_function_pretend_args_size
);
6122 output_add_immediate (operands
);
6124 /* And finally, go home */
6125 if (TARGET_INTERWORK
)
6126 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
6127 else if (TARGET_APCS_32
)
6128 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
6130 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
6138 output_func_epilogue (frame_size
)
6141 if (use_return_insn (FALSE
) && return_used_this_function
6142 && (frame_size
+ current_function_outgoing_args_size
) != 0
6143 && ! (frame_pointer_needed
&& TARGET_APCS
))
6146 /* Reset the ARM-specific per-function variables. */
6147 current_function_anonymous_args
= 0;
6148 after_arm_reorg
= 0;
6152 emit_multi_reg_push (mask
)
6159 for (i
= 0; i
< 16; i
++)
6160 if (mask
& (1 << i
))
6163 if (num_regs
== 0 || num_regs
> 16)
6166 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
6168 for (i
= 0; i
< 16; i
++)
6170 if (mask
& (1 << i
))
6173 = gen_rtx_SET (VOIDmode
,
6174 gen_rtx_MEM (BLKmode
,
6175 gen_rtx_PRE_DEC (BLKmode
,
6176 stack_pointer_rtx
)),
6177 gen_rtx_UNSPEC (BLKmode
,
6179 gen_rtx_REG (SImode
, i
)),
6185 for (j
= 1, i
++; j
< num_regs
; i
++)
6187 if (mask
& (1 << i
))
6190 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, i
));
6199 emit_sfm (base_reg
, count
)
6206 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
6209 = gen_rtx_SET (VOIDmode
,
6210 gen_rtx_MEM (BLKmode
,
6211 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
6212 gen_rtx_UNSPEC (BLKmode
,
6213 gen_rtvec (1, gen_rtx_REG (XFmode
,
6216 for (i
= 1; i
< count
; i
++)
6217 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
,
6218 gen_rtx_REG (XFmode
, base_reg
++));
6224 arm_expand_prologue ()
6227 rtx amount
= GEN_INT (-(get_frame_size ()
6228 + current_function_outgoing_args_size
));
6229 int live_regs_mask
= 0;
6230 int store_arg_regs
= 0;
6231 /* If this function doesn't return, then there is no need to push
6232 the call-saved regs. */
6233 int volatile_func
= (optimize
> 0
6234 && TREE_THIS_VOLATILE (current_function_decl
));
6236 /* Naked functions don't have prologues. */
6237 if (arm_naked_function_p (current_function_decl
))
6240 if (current_function_anonymous_args
&& current_function_pretend_args_size
)
6243 if (! volatile_func
)
6245 for (reg
= 0; reg
<= 10; reg
++)
6246 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
6247 live_regs_mask
|= 1 << reg
;
6249 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
6250 live_regs_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
6252 if (regs_ever_live
[LR_REGNUM
])
6253 live_regs_mask
|= 1 << LR_REGNUM
;
6256 if (frame_pointer_needed
)
6258 live_regs_mask
|= 0xD800;
6259 emit_insn (gen_movsi (gen_rtx_REG (SImode
, IP_REGNUM
),
6260 stack_pointer_rtx
));
6263 if (current_function_pretend_args_size
)
6266 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size
/ 4))
6269 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6270 GEN_INT (-current_function_pretend_args_size
)));
6275 /* If we have to push any regs, then we must push lr as well, or
6276 we won't get a proper return. */
6277 live_regs_mask
|= 1 << LR_REGNUM
;
6278 emit_multi_reg_push (live_regs_mask
);
6281 /* For now the integer regs are still pushed in output_func_epilogue (). */
6283 if (! volatile_func
)
6285 if (arm_fpu_arch
== FP_SOFT2
)
6287 for (reg
= 23; reg
> 15; reg
--)
6288 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
6289 emit_insn (gen_rtx_SET
6291 gen_rtx_MEM (XFmode
,
6292 gen_rtx_PRE_DEC (XFmode
,
6293 stack_pointer_rtx
)),
6294 gen_rtx_REG (XFmode
, reg
)));
6300 for (reg
= 23; reg
> 15; reg
--)
6302 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
6304 if (start_reg
- reg
== 3)
6307 start_reg
= reg
- 1;
6312 if (start_reg
!= reg
)
6313 emit_sfm (reg
+ 1, start_reg
- reg
);
6314 start_reg
= reg
- 1;
6318 if (start_reg
!= reg
)
6319 emit_sfm (reg
+ 1, start_reg
- reg
);
6323 if (frame_pointer_needed
)
6324 emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, gen_rtx_REG (SImode
, IP_REGNUM
),
6326 (-(4 + current_function_pretend_args_size
)))));
6328 if (amount
!= const0_rtx
)
6330 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, amount
));
6331 emit_insn (gen_rtx_CLOBBER (VOIDmode
,
6332 gen_rtx_MEM (BLKmode
, stack_pointer_rtx
)));
6335 /* If we are profiling, make sure no instructions are scheduled before
6336 the call to mcount. Similarly if the user has requested no
6337 scheduling in the prolog. */
6338 if (profile_flag
|| profile_block_flag
|| TARGET_NO_SCHED_PRO
)
6339 emit_insn (gen_blockage ());
6343 /* If CODE is 'd', then the X is a condition operand and the instruction
6344 should only be executed if the condition is true.
6345 if CODE is 'D', then the X is a condition operand and the instruction
6346 should only be executed if the condition is false: however, if the mode
6347 of the comparison is CCFPEmode, then always execute the instruction -- we
6348 do this because in these circumstances !GE does not necessarily imply LT;
6349 in these cases the instruction pattern will take care to make sure that
6350 an instruction containing %d will follow, thereby undoing the effects of
6351 doing this instruction unconditionally.
6352 If CODE is 'N' then X is a floating point operand that must be negated
6354 If CODE is 'B' then output a bitwise inverted value of X (a const int).
6355 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
6358 arm_print_operand (stream
, x
, code
)
6366 fputs (ASM_COMMENT_START
, stream
);
6370 fputs (REGISTER_PREFIX
, stream
);
6374 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
6375 fputs (arm_condition_codes
[arm_current_cc
], stream
);
6381 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6382 r
= REAL_VALUE_NEGATE (r
);
6383 fprintf (stream
, "%s", fp_const_from_val (&r
));
6388 if (GET_CODE (x
) == CONST_INT
)
6391 val
= ARM_SIGN_EXTEND (~ INTVAL (x
));
6392 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
6397 output_addr_const (stream
, x
);
6402 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
6406 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
6412 char * shift
= shift_op (x
, & val
);
6416 fprintf (stream
, ", %s ", shift_op (x
, & val
));
6418 arm_print_operand (stream
, XEXP (x
, 1), 0);
6421 fputc ('#', stream
);
6422 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
6431 fputs (REGISTER_PREFIX
, stream
);
6432 fputs (reg_names
[REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0)], stream
);
6438 fputs (REGISTER_PREFIX
, stream
);
6439 fputs (reg_names
[REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1)], stream
);
6443 fputs (REGISTER_PREFIX
, stream
);
6444 if (GET_CODE (XEXP (x
, 0)) == REG
)
6445 fputs (reg_names
[REGNO (XEXP (x
, 0))], stream
);
6447 fputs (reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))], stream
);
6451 asm_fprintf (stream
, "{%r-%r}",
6452 REGNO (x
), REGNO (x
) + NUM_REGS (GET_MODE (x
)) - 1);
6457 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
6463 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
6464 (get_arm_condition_code (x
))],
6472 if (GET_CODE (x
) == REG
)
6474 fputs (REGISTER_PREFIX
, stream
);
6475 fputs (reg_names
[REGNO (x
)], stream
);
6477 else if (GET_CODE (x
) == MEM
)
6479 output_memory_reference_mode
= GET_MODE (x
);
6480 output_address (XEXP (x
, 0));
6482 else if (GET_CODE (x
) == CONST_DOUBLE
)
6483 fprintf (stream
, "#%s", fp_immediate_constant (x
));
6484 else if (GET_CODE (x
) == NEG
)
6485 abort (); /* This should never happen now. */
6488 fputc ('#', stream
);
6489 output_addr_const (stream
, x
);
6494 /* A finite state machine takes care of noticing whether or not instructions
6495 can be conditionally executed, and thus decrease execution time and code
6496 size by deleting branch instructions. The fsm is controlled by
6497 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
6499 /* The state of the fsm controlling condition codes are:
6500 0: normal, do nothing special
6501 1: make ASM_OUTPUT_OPCODE not output this instruction
6502 2: make ASM_OUTPUT_OPCODE not output this instruction
6503 3: make instructions conditional
6504 4: make instructions conditional
6506 State transitions (state->state by whom under condition):
6507 0 -> 1 final_prescan_insn if the `target' is a label
6508 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
6509 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
6510 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
6511 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
6512 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
6513 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
6514 (the target insn is arm_target_insn).
6516 If the jump clobbers the conditions then we use states 2 and 4.
6518 A similar thing can be done with conditional return insns.
6520 XXX In case the `target' is an unconditional branch, this conditionalising
6521 of the instructions always reduces code size, but not always execution
6522 time. But then, I want to reduce the code size to somewhere near what
6523 /bin/cc produces. */
6525 /* Returns the index of the ARM condition code string in
6526 `arm_condition_codes'. COMPARISON should be an rtx like
6527 `(eq (...) (...))'. */
6529 static enum arm_cond_code
6530 get_arm_condition_code (comparison
)
6533 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
6535 register enum rtx_code comp_code
= GET_CODE (comparison
);
6537 if (GET_MODE_CLASS (mode
) != MODE_CC
)
6538 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
6539 XEXP (comparison
, 1));
6543 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
6544 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
6545 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
6546 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
6547 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
6548 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
6549 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
6550 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
6551 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
6552 case CC_DLTUmode
: code
= ARM_CC
;
6555 if (comp_code
!= EQ
&& comp_code
!= NE
)
6558 if (comp_code
== EQ
)
6559 return ARM_INVERSE_CONDITION_CODE (code
);
6565 case NE
: return ARM_NE
;
6566 case EQ
: return ARM_EQ
;
6567 case GE
: return ARM_PL
;
6568 case LT
: return ARM_MI
;
6576 case NE
: return ARM_NE
;
6577 case EQ
: return ARM_EQ
;
6584 case GE
: return ARM_GE
;
6585 case GT
: return ARM_GT
;
6586 case LE
: return ARM_LS
;
6587 case LT
: return ARM_MI
;
6594 case NE
: return ARM_NE
;
6595 case EQ
: return ARM_EQ
;
6596 case GE
: return ARM_LE
;
6597 case GT
: return ARM_LT
;
6598 case LE
: return ARM_GE
;
6599 case LT
: return ARM_GT
;
6600 case GEU
: return ARM_LS
;
6601 case GTU
: return ARM_CC
;
6602 case LEU
: return ARM_CS
;
6603 case LTU
: return ARM_HI
;
6610 case LTU
: return ARM_CS
;
6611 case GEU
: return ARM_CC
;
6618 case NE
: return ARM_NE
;
6619 case EQ
: return ARM_EQ
;
6620 case GE
: return ARM_GE
;
6621 case GT
: return ARM_GT
;
6622 case LE
: return ARM_LE
;
6623 case LT
: return ARM_LT
;
6624 case GEU
: return ARM_CS
;
6625 case GTU
: return ARM_HI
;
6626 case LEU
: return ARM_LS
;
6627 case LTU
: return ARM_CC
;
6639 arm_final_prescan_insn (insn
)
6642 /* BODY will hold the body of INSN. */
6643 register rtx body
= PATTERN (insn
);
6645 /* This will be 1 if trying to repeat the trick, and things need to be
6646 reversed if it appears to fail. */
6649 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
6650 taken are clobbered, even if the rtl suggests otherwise. It also
6651 means that we have to grub around within the jump expression to find
6652 out what the conditions are when the jump isn't taken. */
6653 int jump_clobbers
= 0;
6655 /* If we start with a return insn, we only succeed if we find another one. */
6656 int seeking_return
= 0;
6658 /* START_INSN will hold the insn from where we start looking. This is the
6659 first insn after the following code_label if REVERSE is true. */
6660 rtx start_insn
= insn
;
6662 /* If in state 4, check if the target branch is reached, in order to
6663 change back to state 0. */
6664 if (arm_ccfsm_state
== 4)
6666 if (insn
== arm_target_insn
)
6668 arm_target_insn
= NULL
;
6669 arm_ccfsm_state
= 0;
6674 /* If in state 3, it is possible to repeat the trick, if this insn is an
6675 unconditional branch to a label, and immediately following this branch
6676 is the previous target label which is only used once, and the label this
6677 branch jumps to is not too far off. */
6678 if (arm_ccfsm_state
== 3)
6680 if (simplejump_p (insn
))
6682 start_insn
= next_nonnote_insn (start_insn
);
6683 if (GET_CODE (start_insn
) == BARRIER
)
6685 /* XXX Isn't this always a barrier? */
6686 start_insn
= next_nonnote_insn (start_insn
);
6688 if (GET_CODE (start_insn
) == CODE_LABEL
6689 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
6690 && LABEL_NUSES (start_insn
) == 1)
6695 else if (GET_CODE (body
) == RETURN
)
6697 start_insn
= next_nonnote_insn (start_insn
);
6698 if (GET_CODE (start_insn
) == BARRIER
)
6699 start_insn
= next_nonnote_insn (start_insn
);
6700 if (GET_CODE (start_insn
) == CODE_LABEL
6701 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
6702 && LABEL_NUSES (start_insn
) == 1)
6714 if (arm_ccfsm_state
!= 0 && !reverse
)
6716 if (GET_CODE (insn
) != JUMP_INSN
)
6719 /* This jump might be paralleled with a clobber of the condition codes
6720 the jump should always come first */
6721 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
6722 body
= XVECEXP (body
, 0, 0);
6725 /* If this is a conditional return then we don't want to know */
6726 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
6727 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
6728 && (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
6729 || GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
))
6734 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
6735 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
6738 int fail
= FALSE
, succeed
= FALSE
;
6739 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
6740 int then_not_else
= TRUE
;
6741 rtx this_insn
= start_insn
, label
= 0;
6743 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
6745 /* The code below is wrong for these, and I haven't time to
6746 fix it now. So we just do the safe thing and return. This
6747 whole function needs re-writing anyway. */
6752 /* Register the insn jumped to. */
6755 if (!seeking_return
)
6756 label
= XEXP (SET_SRC (body
), 0);
6758 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
6759 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
6760 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
6762 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
6763 then_not_else
= FALSE
;
6765 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
6767 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
6770 then_not_else
= FALSE
;
6775 /* See how many insns this branch skips, and what kind of insns. If all
6776 insns are okay, and the label or unconditional branch to the same
6777 label is not too far away, succeed. */
6778 for (insns_skipped
= 0;
6779 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
6783 this_insn
= next_nonnote_insn (this_insn
);
6787 switch (GET_CODE (this_insn
))
6790 /* Succeed if it is the target label, otherwise fail since
6791 control falls in from somewhere else. */
6792 if (this_insn
== label
)
6796 arm_ccfsm_state
= 2;
6797 this_insn
= next_nonnote_insn (this_insn
);
6800 arm_ccfsm_state
= 1;
6808 /* Succeed if the following insn is the target label.
6810 If return insns are used then the last insn in a function
6811 will be a barrier. */
6812 this_insn
= next_nonnote_insn (this_insn
);
6813 if (this_insn
&& this_insn
== label
)
6817 arm_ccfsm_state
= 2;
6818 this_insn
= next_nonnote_insn (this_insn
);
6821 arm_ccfsm_state
= 1;
6829 /* If using 32-bit addresses the cc is not preserved over
6833 /* Succeed if the following insn is the target label,
6834 or if the following two insns are a barrier and
6835 the target label. */
6836 this_insn
= next_nonnote_insn (this_insn
);
6837 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
6838 this_insn
= next_nonnote_insn (this_insn
);
6840 if (this_insn
&& this_insn
== label
6841 && insns_skipped
< max_insns_skipped
)
6845 arm_ccfsm_state
= 2;
6846 this_insn
= next_nonnote_insn (this_insn
);
6849 arm_ccfsm_state
= 1;
6858 /* If this is an unconditional branch to the same label, succeed.
6859 If it is to another label, do nothing. If it is conditional,
6861 /* XXX Probably, the tests for SET and the PC are unnecessary. */
6863 scanbody
= PATTERN (this_insn
);
6864 if (GET_CODE (scanbody
) == SET
6865 && GET_CODE (SET_DEST (scanbody
)) == PC
)
6867 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
6868 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
6870 arm_ccfsm_state
= 2;
6873 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
6876 /* Fail if a conditional return is undesirable (eg on a
6877 StrongARM), but still allow this if optimizing for size. */
6878 else if (GET_CODE (scanbody
) == RETURN
6879 && ! use_return_insn (TRUE
)
6882 else if (GET_CODE (scanbody
) == RETURN
6885 arm_ccfsm_state
= 2;
6888 else if (GET_CODE (scanbody
) == PARALLEL
)
6890 switch (get_attr_conds (this_insn
))
6902 /* Instructions using or affecting the condition codes make it
6904 scanbody
= PATTERN (this_insn
);
6905 if (! (GET_CODE (scanbody
) == SET
6906 || GET_CODE (scanbody
) == PARALLEL
)
6907 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
6917 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
6918 arm_target_label
= CODE_LABEL_NUMBER (label
);
6919 else if (seeking_return
|| arm_ccfsm_state
== 2)
6921 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
6923 this_insn
= next_nonnote_insn (this_insn
);
6924 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
6925 || GET_CODE (this_insn
) == CODE_LABEL
))
6930 /* Oh, dear! we ran off the end.. give up */
6931 recog (PATTERN (insn
), insn
, NULL_PTR
);
6932 arm_ccfsm_state
= 0;
6933 arm_target_insn
= NULL
;
6936 arm_target_insn
= this_insn
;
6945 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
6947 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
6948 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
6949 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
6950 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
6954 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
6957 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
6961 if (reverse
|| then_not_else
)
6962 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
6965 /* Restore recog_data (getting the attributes of other insns can
6966 destroy this array, but final.c assumes that it remains intact
6967 across this call; since the insn has been recognized already we
6968 call recog direct). */
6969 recog (PATTERN (insn
), insn
, NULL_PTR
);
6973 #ifdef AOF_ASSEMBLER
6974 /* Special functions only needed when producing AOF syntax assembler. */
6976 rtx aof_pic_label
= NULL_RTX
;
6979 struct pic_chain
* next
;
6983 static struct pic_chain
* aof_pic_chain
= NULL
;
6989 struct pic_chain
** chainp
;
6992 if (aof_pic_label
== NULL_RTX
)
6994 /* We mark this here and not in arm_add_gc_roots() to avoid
6995 polluting even more code with ifdefs, and because it never
6996 contains anything useful until we assign to it here. */
6997 ggc_add_rtx_root (&aof_pic_label
, 1);
6998 /* This needs to persist throughout the compilation. */
6999 end_temporary_allocation ();
7000 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
7001 resume_temporary_allocation ();
7004 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
7005 offset
+= 4, chainp
= &(*chainp
)->next
)
7006 if ((*chainp
)->symname
== XSTR (x
, 0))
7007 return plus_constant (aof_pic_label
, offset
);
7009 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
7010 (*chainp
)->next
= NULL
;
7011 (*chainp
)->symname
= XSTR (x
, 0);
7012 return plus_constant (aof_pic_label
, offset
);
7016 aof_dump_pic_table (f
)
7019 struct pic_chain
* chain
;
7021 if (aof_pic_chain
== NULL
)
7024 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
7025 PIC_OFFSET_TABLE_REGNUM
,
7026 PIC_OFFSET_TABLE_REGNUM
);
7027 fputs ("|x$adcons|\n", f
);
7029 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
7031 fputs ("\tDCD\t", f
);
7032 assemble_name (f
, chain
->symname
);
7037 int arm_text_section_count
= 1;
7042 static char buf
[100];
7043 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
7044 arm_text_section_count
++);
7046 strcat (buf
, ", PIC, REENTRANT");
7050 static int arm_data_section_count
= 1;
7055 static char buf
[100];
7056 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
7060 /* The AOF assembler is religiously strict about declarations of
7061 imported and exported symbols, so that it is impossible to declare
7062 a function as imported near the beginning of the file, and then to
7063 export it later on. It is, however, possible to delay the decision
7064 until all the functions in the file have been compiled. To get
7065 around this, we maintain a list of the imports and exports, and
7066 delete from it any that are subsequently defined. At the end of
7067 compilation we spit the remainder of the list out before the END
7072 struct import
* next
;
7076 static struct import
* imports_list
= NULL
;
7079 aof_add_import (name
)
7082 struct import
* new;
7084 for (new = imports_list
; new; new = new->next
)
7085 if (new->name
== name
)
7088 new = (struct import
*) xmalloc (sizeof (struct import
));
7089 new->next
= imports_list
;
7095 aof_delete_import (name
)
7098 struct import
** old
;
7100 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
7102 if ((*old
)->name
== name
)
7104 *old
= (*old
)->next
;
7110 int arm_main_function
= 0;
7113 aof_dump_imports (f
)
7116 /* The AOF assembler needs this to cause the startup code to be extracted
7117 from the library. Brining in __main causes the whole thing to work
7119 if (arm_main_function
)
7122 fputs ("\tIMPORT __main\n", f
);
7123 fputs ("\tDCD __main\n", f
);
7126 /* Now dump the remaining imports. */
7127 while (imports_list
)
7129 fprintf (f
, "\tIMPORT\t");
7130 assemble_name (f
, imports_list
->name
);
7132 imports_list
= imports_list
->next
;
7135 #endif /* AOF_ASSEMBLER */