1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
60 #ifndef TARGET_NO_PROTOTYPE
61 #define TARGET_NO_PROTOTYPE 0
64 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
65 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e \
68 #define min(A,B) ((A) < (B) ? (A) : (B))
69 #define max(A,B) ((A) > (B) ? (A) : (B))
71 /* Structure used to define the rs6000 stack */
72 typedef struct rs6000_stack
{
73 int first_gp_reg_save
; /* first callee saved GP register used */
74 int first_fp_reg_save
; /* first callee saved FP register used */
75 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
76 int lr_save_p
; /* true if the link reg needs to be saved */
77 int cr_save_p
; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask
; /* mask of vec registers to save */
79 int toc_save_p
; /* true if the TOC needs to be saved */
80 int push_p
; /* true if we need to allocate stack space */
81 int calls_p
; /* true if the function makes any calls */
82 int world_save_p
; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi
; /* which ABI to use */
85 int gp_save_offset
; /* offset to save GP regs from initial SP */
86 int fp_save_offset
; /* offset to save FP regs from initial SP */
87 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset
; /* offset to save LR from initial SP */
89 int cr_save_offset
; /* offset to save CR from initial SP */
90 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
92 int toc_save_offset
; /* offset to save the TOC pointer */
93 int varargs_save_offset
; /* offset to save the varargs registers */
94 int ehrd_offset
; /* offset to EH return data */
95 int reg_size
; /* register size (4 or 8) */
96 int varargs_size
; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size
; /* variable save area size */
98 int parm_size
; /* outgoing parameter size */
99 int save_size
; /* save area size */
100 int fixed_size
; /* fixed size of stack frame */
101 int gp_size
; /* size of saved GP registers */
102 int fp_size
; /* size of saved FP registers */
103 int altivec_size
; /* size of saved AltiVec registers */
104 int cr_size
; /* size to hold CR if not in save_size */
105 int lr_size
; /* size to hold LR if not in save_size */
106 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size
; /* size of altivec alignment padding if
109 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size
;
111 int toc_size
; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
113 int spe_64bit_regs_used
;
116 /* Target cpu type */
118 enum processor_type rs6000_cpu
;
119 struct rs6000_cpu_select rs6000_select
[3] =
121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
127 /* Always emit branch hint bits. */
128 static GTY(()) bool rs6000_always_hint
;
130 /* Schedule instructions for group formation. */
131 static GTY(()) bool rs6000_sched_groups
;
133 /* Support adjust_priority scheduler hook
134 and -mprioritize-restricted-insns= option. */
135 const char *rs6000_sched_restricted_insns_priority_str
;
136 int rs6000_sched_restricted_insns_priority
;
138 /* Support for -msched-costly-dep option. */
139 const char *rs6000_sched_costly_dep_str
;
140 enum rs6000_dependence_cost rs6000_sched_costly_dep
;
142 /* Support for -minsert-sched-nops option. */
143 const char *rs6000_sched_insert_nops_str
;
144 enum rs6000_nop_insertion rs6000_sched_insert_nops
;
146 /* Size of long double */
147 const char *rs6000_long_double_size_string
;
148 int rs6000_long_double_type_size
;
150 /* Whether -mabi=altivec has appeared */
151 int rs6000_altivec_abi
;
153 /* Whether VRSAVE instructions should be generated. */
154 int rs6000_altivec_vrsave
;
156 /* String from -mvrsave= option. */
157 const char *rs6000_altivec_vrsave_string
;
159 /* Nonzero if we want SPE ABI extensions. */
162 /* Whether isel instructions should be generated. */
165 /* Whether SPE simd instructions should be generated. */
168 /* Nonzero if floating point operations are done in the GPRs. */
169 int rs6000_float_gprs
= 0;
171 /* String from -mfloat-gprs=. */
172 const char *rs6000_float_gprs_string
;
174 /* String from -misel=. */
175 const char *rs6000_isel_string
;
177 /* String from -mspe=. */
178 const char *rs6000_spe_string
;
180 /* Set to nonzero once AIX common-mode calls have been defined. */
181 static GTY(()) int common_mode_defined
;
183 /* Save information from a "cmpxx" operation until the branch or scc is
185 rtx rs6000_compare_op0
, rs6000_compare_op1
;
186 int rs6000_compare_fp_p
;
188 /* Label number of label created for -mrelocatable, to call to so we can
189 get the address of the GOT section */
190 int rs6000_pic_labelno
;
193 /* Which abi to adhere to */
194 const char *rs6000_abi_name
;
196 /* Semantics of the small data area */
197 enum rs6000_sdata_type rs6000_sdata
= SDATA_DATA
;
199 /* Which small data model to use */
200 const char *rs6000_sdata_name
= (char *)0;
202 /* Counter for labels which are to be placed in .fixup. */
203 int fixuplabelno
= 0;
206 /* Bit size of immediate TLS offsets and string from which it is decoded. */
207 int rs6000_tls_size
= 32;
208 const char *rs6000_tls_size_string
;
210 /* ABI enumeration available for subtarget to use. */
211 enum rs6000_abi rs6000_current_abi
;
213 /* ABI string from -mabi= option. */
214 const char *rs6000_abi_string
;
216 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
220 const char *rs6000_debug_name
;
221 int rs6000_debug_stack
; /* debug stack applications */
222 int rs6000_debug_arg
; /* debug argument handling */
224 /* Value is TRUE if register/mode pair is accepatable. */
225 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
228 static GTY(()) tree opaque_V2SI_type_node
;
229 static GTY(()) tree opaque_V2SF_type_node
;
230 static GTY(()) tree opaque_p_V2SI_type_node
;
231 static GTY(()) tree V16QI_type_node
;
232 static GTY(()) tree V2SI_type_node
;
233 static GTY(()) tree V2SF_type_node
;
234 static GTY(()) tree V4HI_type_node
;
235 static GTY(()) tree V4SI_type_node
;
236 static GTY(()) tree V4SF_type_node
;
237 static GTY(()) tree V8HI_type_node
;
238 static GTY(()) tree unsigned_V16QI_type_node
;
239 static GTY(()) tree unsigned_V8HI_type_node
;
240 static GTY(()) tree unsigned_V4SI_type_node
;
241 static GTY(()) tree bool_char_type_node
; /* __bool char */
242 static GTY(()) tree bool_short_type_node
; /* __bool short */
243 static GTY(()) tree bool_int_type_node
; /* __bool int */
244 static GTY(()) tree pixel_type_node
; /* __pixel */
245 static GTY(()) tree bool_V16QI_type_node
; /* __vector __bool char */
246 static GTY(()) tree bool_V8HI_type_node
; /* __vector __bool short */
247 static GTY(()) tree bool_V4SI_type_node
; /* __vector __bool int */
248 static GTY(()) tree pixel_V8HI_type_node
; /* __vector __pixel */
250 int rs6000_warn_altivec_long
= 1; /* On by default. */
251 const char *rs6000_warn_altivec_long_switch
;
253 const char *rs6000_traceback_name
;
255 traceback_default
= 0,
261 /* Flag to say the TOC is initialized */
263 char toc_label_name
[10];
265 /* Alias set for saves and restores from the rs6000 stack. */
266 static GTY(()) int rs6000_sr_alias_set
;
268 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
269 The only place that looks at this is rs6000_set_default_type_attributes;
270 everywhere else should rely on the presence or absence of a longcall
271 attribute on the function declaration. */
272 int rs6000_default_long_calls
;
273 const char *rs6000_longcall_switch
;
275 /* Control alignment for fields within structures. */
276 /* String from -malign-XXXXX. */
277 const char *rs6000_alignment_string
;
278 int rs6000_alignment_flags
;
280 struct builtin_description
282 /* mask is not const because we're going to alter it below. This
283 nonsense will go away when we rewrite the -march infrastructure
284 to give us more target flag bits. */
286 const enum insn_code icode
;
287 const char *const name
;
288 const enum rs6000_builtins code
;
291 /* Target cpu costs. */
293 struct processor_costs
{
294 const int mulsi
; /* cost of SImode multiplication. */
295 const int mulsi_const
; /* cost of SImode multiplication by constant. */
296 const int mulsi_const9
; /* cost of SImode mult by short constant. */
297 const int muldi
; /* cost of DImode multiplication. */
298 const int divsi
; /* cost of SImode division. */
299 const int divdi
; /* cost of DImode division. */
300 const int fp
; /* cost of simple SFmode and DFmode insns. */
301 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
302 const int sdiv
; /* cost of SFmode division (fdivs). */
303 const int ddiv
; /* cost of DFmode division (fdiv). */
306 const struct processor_costs
*rs6000_cost
;
308 /* Processor costs (relative to an add) */
310 /* Instruction size costs on 32bit processors. */
312 struct processor_costs size32_cost
= {
313 COSTS_N_INSNS (1), /* mulsi */
314 COSTS_N_INSNS (1), /* mulsi_const */
315 COSTS_N_INSNS (1), /* mulsi_const9 */
316 COSTS_N_INSNS (1), /* muldi */
317 COSTS_N_INSNS (1), /* divsi */
318 COSTS_N_INSNS (1), /* divdi */
319 COSTS_N_INSNS (1), /* fp */
320 COSTS_N_INSNS (1), /* dmul */
321 COSTS_N_INSNS (1), /* sdiv */
322 COSTS_N_INSNS (1), /* ddiv */
325 /* Instruction size costs on 64bit processors. */
327 struct processor_costs size64_cost
= {
328 COSTS_N_INSNS (1), /* mulsi */
329 COSTS_N_INSNS (1), /* mulsi_const */
330 COSTS_N_INSNS (1), /* mulsi_const9 */
331 COSTS_N_INSNS (1), /* muldi */
332 COSTS_N_INSNS (1), /* divsi */
333 COSTS_N_INSNS (1), /* divdi */
334 COSTS_N_INSNS (1), /* fp */
335 COSTS_N_INSNS (1), /* dmul */
336 COSTS_N_INSNS (1), /* sdiv */
337 COSTS_N_INSNS (1), /* ddiv */
340 /* Instruction costs on RIOS1 processors. */
342 struct processor_costs rios1_cost
= {
343 COSTS_N_INSNS (5), /* mulsi */
344 COSTS_N_INSNS (4), /* mulsi_const */
345 COSTS_N_INSNS (3), /* mulsi_const9 */
346 COSTS_N_INSNS (5), /* muldi */
347 COSTS_N_INSNS (19), /* divsi */
348 COSTS_N_INSNS (19), /* divdi */
349 COSTS_N_INSNS (2), /* fp */
350 COSTS_N_INSNS (2), /* dmul */
351 COSTS_N_INSNS (19), /* sdiv */
352 COSTS_N_INSNS (19), /* ddiv */
355 /* Instruction costs on RIOS2 processors. */
357 struct processor_costs rios2_cost
= {
358 COSTS_N_INSNS (2), /* mulsi */
359 COSTS_N_INSNS (2), /* mulsi_const */
360 COSTS_N_INSNS (2), /* mulsi_const9 */
361 COSTS_N_INSNS (2), /* muldi */
362 COSTS_N_INSNS (13), /* divsi */
363 COSTS_N_INSNS (13), /* divdi */
364 COSTS_N_INSNS (2), /* fp */
365 COSTS_N_INSNS (2), /* dmul */
366 COSTS_N_INSNS (17), /* sdiv */
367 COSTS_N_INSNS (17), /* ddiv */
370 /* Instruction costs on RS64A processors. */
372 struct processor_costs rs64a_cost
= {
373 COSTS_N_INSNS (20), /* mulsi */
374 COSTS_N_INSNS (12), /* mulsi_const */
375 COSTS_N_INSNS (8), /* mulsi_const9 */
376 COSTS_N_INSNS (34), /* muldi */
377 COSTS_N_INSNS (65), /* divsi */
378 COSTS_N_INSNS (67), /* divdi */
379 COSTS_N_INSNS (4), /* fp */
380 COSTS_N_INSNS (4), /* dmul */
381 COSTS_N_INSNS (31), /* sdiv */
382 COSTS_N_INSNS (31), /* ddiv */
385 /* Instruction costs on MPCCORE processors. */
387 struct processor_costs mpccore_cost
= {
388 COSTS_N_INSNS (2), /* mulsi */
389 COSTS_N_INSNS (2), /* mulsi_const */
390 COSTS_N_INSNS (2), /* mulsi_const9 */
391 COSTS_N_INSNS (2), /* muldi */
392 COSTS_N_INSNS (6), /* divsi */
393 COSTS_N_INSNS (6), /* divdi */
394 COSTS_N_INSNS (4), /* fp */
395 COSTS_N_INSNS (5), /* dmul */
396 COSTS_N_INSNS (10), /* sdiv */
397 COSTS_N_INSNS (17), /* ddiv */
400 /* Instruction costs on PPC403 processors. */
402 struct processor_costs ppc403_cost
= {
403 COSTS_N_INSNS (4), /* mulsi */
404 COSTS_N_INSNS (4), /* mulsi_const */
405 COSTS_N_INSNS (4), /* mulsi_const9 */
406 COSTS_N_INSNS (4), /* muldi */
407 COSTS_N_INSNS (33), /* divsi */
408 COSTS_N_INSNS (33), /* divdi */
409 COSTS_N_INSNS (11), /* fp */
410 COSTS_N_INSNS (11), /* dmul */
411 COSTS_N_INSNS (11), /* sdiv */
412 COSTS_N_INSNS (11), /* ddiv */
415 /* Instruction costs on PPC405 processors. */
417 struct processor_costs ppc405_cost
= {
418 COSTS_N_INSNS (5), /* mulsi */
419 COSTS_N_INSNS (4), /* mulsi_const */
420 COSTS_N_INSNS (3), /* mulsi_const9 */
421 COSTS_N_INSNS (5), /* muldi */
422 COSTS_N_INSNS (35), /* divsi */
423 COSTS_N_INSNS (35), /* divdi */
424 COSTS_N_INSNS (11), /* fp */
425 COSTS_N_INSNS (11), /* dmul */
426 COSTS_N_INSNS (11), /* sdiv */
427 COSTS_N_INSNS (11), /* ddiv */
430 /* Instruction costs on PPC440 processors. */
432 struct processor_costs ppc440_cost
= {
433 COSTS_N_INSNS (3), /* mulsi */
434 COSTS_N_INSNS (2), /* mulsi_const */
435 COSTS_N_INSNS (2), /* mulsi_const9 */
436 COSTS_N_INSNS (3), /* muldi */
437 COSTS_N_INSNS (34), /* divsi */
438 COSTS_N_INSNS (34), /* divdi */
439 COSTS_N_INSNS (5), /* fp */
440 COSTS_N_INSNS (5), /* dmul */
441 COSTS_N_INSNS (19), /* sdiv */
442 COSTS_N_INSNS (33), /* ddiv */
445 /* Instruction costs on PPC601 processors. */
447 struct processor_costs ppc601_cost
= {
448 COSTS_N_INSNS (5), /* mulsi */
449 COSTS_N_INSNS (5), /* mulsi_const */
450 COSTS_N_INSNS (5), /* mulsi_const9 */
451 COSTS_N_INSNS (5), /* muldi */
452 COSTS_N_INSNS (36), /* divsi */
453 COSTS_N_INSNS (36), /* divdi */
454 COSTS_N_INSNS (4), /* fp */
455 COSTS_N_INSNS (5), /* dmul */
456 COSTS_N_INSNS (17), /* sdiv */
457 COSTS_N_INSNS (31), /* ddiv */
460 /* Instruction costs on PPC603 processors. */
462 struct processor_costs ppc603_cost
= {
463 COSTS_N_INSNS (5), /* mulsi */
464 COSTS_N_INSNS (3), /* mulsi_const */
465 COSTS_N_INSNS (2), /* mulsi_const9 */
466 COSTS_N_INSNS (5), /* muldi */
467 COSTS_N_INSNS (37), /* divsi */
468 COSTS_N_INSNS (37), /* divdi */
469 COSTS_N_INSNS (3), /* fp */
470 COSTS_N_INSNS (4), /* dmul */
471 COSTS_N_INSNS (18), /* sdiv */
472 COSTS_N_INSNS (33), /* ddiv */
475 /* Instruction costs on PPC604 processors. */
477 struct processor_costs ppc604_cost
= {
478 COSTS_N_INSNS (4), /* mulsi */
479 COSTS_N_INSNS (4), /* mulsi_const */
480 COSTS_N_INSNS (4), /* mulsi_const9 */
481 COSTS_N_INSNS (4), /* muldi */
482 COSTS_N_INSNS (20), /* divsi */
483 COSTS_N_INSNS (20), /* divdi */
484 COSTS_N_INSNS (3), /* fp */
485 COSTS_N_INSNS (3), /* dmul */
486 COSTS_N_INSNS (18), /* sdiv */
487 COSTS_N_INSNS (32), /* ddiv */
490 /* Instruction costs on PPC604e processors. */
492 struct processor_costs ppc604e_cost
= {
493 COSTS_N_INSNS (2), /* mulsi */
494 COSTS_N_INSNS (2), /* mulsi_const */
495 COSTS_N_INSNS (2), /* mulsi_const9 */
496 COSTS_N_INSNS (2), /* muldi */
497 COSTS_N_INSNS (20), /* divsi */
498 COSTS_N_INSNS (20), /* divdi */
499 COSTS_N_INSNS (3), /* fp */
500 COSTS_N_INSNS (3), /* dmul */
501 COSTS_N_INSNS (18), /* sdiv */
502 COSTS_N_INSNS (32), /* ddiv */
505 /* Instruction costs on PPC620 processors. */
507 struct processor_costs ppc620_cost
= {
508 COSTS_N_INSNS (5), /* mulsi */
509 COSTS_N_INSNS (4), /* mulsi_const */
510 COSTS_N_INSNS (3), /* mulsi_const9 */
511 COSTS_N_INSNS (7), /* muldi */
512 COSTS_N_INSNS (21), /* divsi */
513 COSTS_N_INSNS (37), /* divdi */
514 COSTS_N_INSNS (3), /* fp */
515 COSTS_N_INSNS (3), /* dmul */
516 COSTS_N_INSNS (18), /* sdiv */
517 COSTS_N_INSNS (32), /* ddiv */
520 /* Instruction costs on PPC630 processors. */
522 struct processor_costs ppc630_cost
= {
523 COSTS_N_INSNS (5), /* mulsi */
524 COSTS_N_INSNS (4), /* mulsi_const */
525 COSTS_N_INSNS (3), /* mulsi_const9 */
526 COSTS_N_INSNS (7), /* muldi */
527 COSTS_N_INSNS (21), /* divsi */
528 COSTS_N_INSNS (37), /* divdi */
529 COSTS_N_INSNS (3), /* fp */
530 COSTS_N_INSNS (3), /* dmul */
531 COSTS_N_INSNS (17), /* sdiv */
532 COSTS_N_INSNS (21), /* ddiv */
535 /* Instruction costs on PPC750 and PPC7400 processors. */
537 struct processor_costs ppc750_cost
= {
538 COSTS_N_INSNS (5), /* mulsi */
539 COSTS_N_INSNS (3), /* mulsi_const */
540 COSTS_N_INSNS (2), /* mulsi_const9 */
541 COSTS_N_INSNS (5), /* muldi */
542 COSTS_N_INSNS (17), /* divsi */
543 COSTS_N_INSNS (17), /* divdi */
544 COSTS_N_INSNS (3), /* fp */
545 COSTS_N_INSNS (3), /* dmul */
546 COSTS_N_INSNS (17), /* sdiv */
547 COSTS_N_INSNS (31), /* ddiv */
550 /* Instruction costs on PPC7450 processors. */
552 struct processor_costs ppc7450_cost
= {
553 COSTS_N_INSNS (4), /* mulsi */
554 COSTS_N_INSNS (3), /* mulsi_const */
555 COSTS_N_INSNS (3), /* mulsi_const9 */
556 COSTS_N_INSNS (4), /* muldi */
557 COSTS_N_INSNS (23), /* divsi */
558 COSTS_N_INSNS (23), /* divdi */
559 COSTS_N_INSNS (5), /* fp */
560 COSTS_N_INSNS (5), /* dmul */
561 COSTS_N_INSNS (21), /* sdiv */
562 COSTS_N_INSNS (35), /* ddiv */
565 /* Instruction costs on PPC8540 processors. */
567 struct processor_costs ppc8540_cost
= {
568 COSTS_N_INSNS (4), /* mulsi */
569 COSTS_N_INSNS (4), /* mulsi_const */
570 COSTS_N_INSNS (4), /* mulsi_const9 */
571 COSTS_N_INSNS (4), /* muldi */
572 COSTS_N_INSNS (19), /* divsi */
573 COSTS_N_INSNS (19), /* divdi */
574 COSTS_N_INSNS (4), /* fp */
575 COSTS_N_INSNS (4), /* dmul */
576 COSTS_N_INSNS (29), /* sdiv */
577 COSTS_N_INSNS (29), /* ddiv */
580 /* Instruction costs on POWER4 and POWER5 processors. */
582 struct processor_costs power4_cost
= {
583 COSTS_N_INSNS (3), /* mulsi */
584 COSTS_N_INSNS (2), /* mulsi_const */
585 COSTS_N_INSNS (2), /* mulsi_const9 */
586 COSTS_N_INSNS (4), /* muldi */
587 COSTS_N_INSNS (18), /* divsi */
588 COSTS_N_INSNS (34), /* divdi */
589 COSTS_N_INSNS (3), /* fp */
590 COSTS_N_INSNS (3), /* dmul */
591 COSTS_N_INSNS (17), /* sdiv */
592 COSTS_N_INSNS (17), /* ddiv */
596 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
597 static int num_insns_constant_wide (HOST_WIDE_INT
);
598 static void validate_condition_mode (enum rtx_code
, enum machine_mode
);
599 static rtx
rs6000_generate_compare (enum rtx_code
);
600 static void rs6000_maybe_dead (rtx
);
601 static void rs6000_emit_stack_tie (void);
602 static void rs6000_frame_related (rtx
, rtx
, HOST_WIDE_INT
, rtx
, rtx
);
603 static rtx
spe_synthesize_frame_save (rtx
);
604 static bool spe_func_has_64bit_regs_p (void);
605 static void emit_frame_save (rtx
, rtx
, enum machine_mode
, unsigned int,
607 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
608 static void rs6000_emit_allocate_stack (HOST_WIDE_INT
, int);
609 static unsigned rs6000_hash_constant (rtx
);
610 static unsigned toc_hash_function (const void *);
611 static int toc_hash_eq (const void *, const void *);
612 static int constant_pool_expr_1 (rtx
, int *, int *);
613 static bool constant_pool_expr_p (rtx
);
614 static bool toc_relative_expr_p (rtx
);
615 static bool legitimate_small_data_p (enum machine_mode
, rtx
);
616 static bool legitimate_indexed_address_p (rtx
, int);
617 static bool legitimate_indirect_address_p (rtx
, int);
618 static bool macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
);
619 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
620 static struct machine_function
* rs6000_init_machine_status (void);
621 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
622 #ifdef HAVE_GAS_HIDDEN
623 static void rs6000_assemble_visibility (tree
, int);
625 static int rs6000_ra_ever_killed (void);
626 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
627 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
628 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
629 static const char *rs6000_mangle_fundamental_type (tree
);
630 extern const struct attribute_spec rs6000_attribute_table
[];
631 static void rs6000_set_default_type_attributes (tree
);
632 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
633 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
634 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
636 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
637 static bool rs6000_return_in_memory (tree
, tree
);
638 static void rs6000_file_start (void);
640 static unsigned int rs6000_elf_section_type_flags (tree
, const char *, int);
641 static void rs6000_elf_asm_out_constructor (rtx
, int);
642 static void rs6000_elf_asm_out_destructor (rtx
, int);
643 static void rs6000_elf_select_section (tree
, int, unsigned HOST_WIDE_INT
);
644 static void rs6000_elf_unique_section (tree
, int);
645 static void rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
646 unsigned HOST_WIDE_INT
);
647 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
649 static bool rs6000_elf_in_small_data_p (tree
);
652 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
653 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
654 static void rs6000_xcoff_select_section (tree
, int, unsigned HOST_WIDE_INT
);
655 static void rs6000_xcoff_unique_section (tree
, int);
656 static void rs6000_xcoff_select_rtx_section (enum machine_mode
, rtx
,
657 unsigned HOST_WIDE_INT
);
658 static const char * rs6000_xcoff_strip_name_encoding (const char *);
659 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
660 static void rs6000_xcoff_file_start (void);
661 static void rs6000_xcoff_file_end (void);
664 static bool rs6000_binds_local_p (tree
);
666 static int rs6000_variable_issue (FILE *, int, rtx
, int);
667 static bool rs6000_rtx_costs (rtx
, int, int, int *);
668 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
669 static bool is_microcoded_insn (rtx
);
670 static int is_dispatch_slot_restricted (rtx
);
671 static bool is_cracked_insn (rtx
);
672 static bool is_branch_slot_insn (rtx
);
673 static int rs6000_adjust_priority (rtx
, int);
674 static int rs6000_issue_rate (void);
675 static bool rs6000_is_costly_dependence (rtx
, rtx
, rtx
, int, int);
676 static rtx
get_next_active_insn (rtx
, rtx
);
677 static bool insn_terminates_group_p (rtx
, enum group_termination
);
678 static bool is_costly_group (rtx
*, rtx
);
679 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
680 static int redefine_groups (FILE *, int, rtx
, rtx
);
681 static int pad_groups (FILE *, int, rtx
, rtx
);
682 static void rs6000_sched_finish (FILE *, int);
683 static int rs6000_use_sched_lookahead (void);
685 static void rs6000_init_builtins (void);
686 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
687 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
688 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
689 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
690 static void altivec_init_builtins (void);
691 static void rs6000_common_init_builtins (void);
692 static void rs6000_init_libfuncs (void);
694 static void enable_mask_for_builtins (struct builtin_description
*, int,
695 enum rs6000_builtins
,
696 enum rs6000_builtins
);
697 static tree
build_opaque_vector_type (tree
, int);
698 static void spe_init_builtins (void);
699 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
700 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
701 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
702 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
703 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
704 static rs6000_stack_t
*rs6000_stack_info (void);
705 static void debug_stack_info (rs6000_stack_t
*);
707 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
708 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
709 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
710 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
711 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
712 static rtx
altivec_expand_predicate_builtin (enum insn_code
,
713 const char *, tree
, rtx
);
714 static rtx
altivec_expand_lv_builtin (enum insn_code
, tree
, rtx
);
715 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
716 static void rs6000_parse_abi_options (void);
717 static void rs6000_parse_alignment_option (void);
718 static void rs6000_parse_tls_size_option (void);
719 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
720 static int first_altivec_reg_to_save (void);
721 static unsigned int compute_vrsave_mask (void);
722 static void compute_save_world_info(rs6000_stack_t
*info_ptr
);
723 static void is_altivec_return_reg (rtx
, void *);
724 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
725 int easy_vector_constant (rtx
, enum machine_mode
);
726 static int easy_vector_same (rtx
, enum machine_mode
);
727 static int easy_vector_splat_const (int, enum machine_mode
);
728 static bool is_ev64_opaque_type (tree
);
729 static rtx
rs6000_dwarf_register_span (rtx
);
730 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
731 static rtx
rs6000_tls_get_addr (void);
732 static rtx
rs6000_got_sym (void);
733 static inline int rs6000_tls_symbol_ref_1 (rtx
*, void *);
734 static const char *rs6000_get_some_local_dynamic_name (void);
735 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
736 static rtx
rs6000_complex_function_value (enum machine_mode
);
737 static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS
*,
738 enum machine_mode
, tree
);
739 static rtx
rs6000_mixed_function_arg (enum machine_mode
, tree
, int);
740 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
741 static void setup_incoming_varargs (CUMULATIVE_ARGS
*,
742 enum machine_mode
, tree
,
744 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
747 static void macho_branch_islands (void);
748 static void add_compiler_branch_island (tree
, tree
, int);
749 static int no_previous_def (tree function_name
);
750 static tree
get_prev_label (tree function_name
);
753 static tree
rs6000_build_builtin_va_list (void);
754 static tree
rs6000_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
755 static bool rs6000_must_pass_in_stack (enum machine_mode
, tree
);
756 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
758 static enum machine_mode
rs6000_eh_return_filter_mode (void);
760 /* Hash table stuff for keeping track of TOC entries. */
762 struct toc_hash_struct
GTY(())
764 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
765 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
767 enum machine_mode key_mode
;
771 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
773 /* Default register names. */
774 char rs6000_reg_names
[][8] =
776 "0", "1", "2", "3", "4", "5", "6", "7",
777 "8", "9", "10", "11", "12", "13", "14", "15",
778 "16", "17", "18", "19", "20", "21", "22", "23",
779 "24", "25", "26", "27", "28", "29", "30", "31",
780 "0", "1", "2", "3", "4", "5", "6", "7",
781 "8", "9", "10", "11", "12", "13", "14", "15",
782 "16", "17", "18", "19", "20", "21", "22", "23",
783 "24", "25", "26", "27", "28", "29", "30", "31",
784 "mq", "lr", "ctr","ap",
785 "0", "1", "2", "3", "4", "5", "6", "7",
787 /* AltiVec registers. */
788 "0", "1", "2", "3", "4", "5", "6", "7",
789 "8", "9", "10", "11", "12", "13", "14", "15",
790 "16", "17", "18", "19", "20", "21", "22", "23",
791 "24", "25", "26", "27", "28", "29", "30", "31",
797 #ifdef TARGET_REGNAMES
798 static const char alt_reg_names
[][8] =
800 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
801 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
802 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
803 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
804 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
805 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
806 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
807 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
808 "mq", "lr", "ctr", "ap",
809 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
811 /* AltiVec registers. */
812 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
813 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
814 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
815 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
822 #ifndef MASK_STRICT_ALIGN
823 #define MASK_STRICT_ALIGN 0
825 #ifndef TARGET_PROFILE_KERNEL
826 #define TARGET_PROFILE_KERNEL 0
829 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
830 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
832 /* Return 1 for a symbol ref for a thread-local storage symbol. */
833 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
834 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
836 /* Initialize the GCC target structure. */
837 #undef TARGET_ATTRIBUTE_TABLE
838 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
839 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
840 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
842 #undef TARGET_ASM_ALIGNED_DI_OP
843 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
845 /* Default unaligned ops are only provided for ELF. Find the ops needed
846 for non-ELF systems. */
847 #ifndef OBJECT_FORMAT_ELF
849 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
851 #undef TARGET_ASM_UNALIGNED_HI_OP
852 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
853 #undef TARGET_ASM_UNALIGNED_SI_OP
854 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
855 #undef TARGET_ASM_UNALIGNED_DI_OP
856 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
859 #undef TARGET_ASM_UNALIGNED_HI_OP
860 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
861 #undef TARGET_ASM_UNALIGNED_SI_OP
862 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
863 #undef TARGET_ASM_UNALIGNED_DI_OP
864 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
865 #undef TARGET_ASM_ALIGNED_DI_OP
866 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
870 /* This hook deals with fixups for relocatable code and DI-mode objects
872 #undef TARGET_ASM_INTEGER
873 #define TARGET_ASM_INTEGER rs6000_assemble_integer
875 #ifdef HAVE_GAS_HIDDEN
876 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
877 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
880 #undef TARGET_HAVE_TLS
881 #define TARGET_HAVE_TLS HAVE_AS_TLS
883 #undef TARGET_CANNOT_FORCE_CONST_MEM
884 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
886 #undef TARGET_ASM_FUNCTION_PROLOGUE
887 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
888 #undef TARGET_ASM_FUNCTION_EPILOGUE
889 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
891 #undef TARGET_SCHED_VARIABLE_ISSUE
892 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
894 #undef TARGET_SCHED_ISSUE_RATE
895 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
896 #undef TARGET_SCHED_ADJUST_COST
897 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
898 #undef TARGET_SCHED_ADJUST_PRIORITY
899 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
900 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
901 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
902 #undef TARGET_SCHED_FINISH
903 #define TARGET_SCHED_FINISH rs6000_sched_finish
905 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
906 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
908 #undef TARGET_INIT_BUILTINS
909 #define TARGET_INIT_BUILTINS rs6000_init_builtins
911 #undef TARGET_EXPAND_BUILTIN
912 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
914 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
915 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
917 #undef TARGET_INIT_LIBFUNCS
918 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
921 #undef TARGET_BINDS_LOCAL_P
922 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
925 #undef TARGET_ASM_OUTPUT_MI_THUNK
926 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
928 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
929 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
931 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
932 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
934 #undef TARGET_RTX_COSTS
935 #define TARGET_RTX_COSTS rs6000_rtx_costs
936 #undef TARGET_ADDRESS_COST
937 #define TARGET_ADDRESS_COST hook_int_rtx_0
939 #undef TARGET_VECTOR_OPAQUE_P
940 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
942 #undef TARGET_DWARF_REGISTER_SPAN
943 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
945 /* On rs6000, function arguments are promoted, as are function return
947 #undef TARGET_PROMOTE_FUNCTION_ARGS
948 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
949 #undef TARGET_PROMOTE_FUNCTION_RETURN
950 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
952 #undef TARGET_RETURN_IN_MEMORY
953 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
955 #undef TARGET_SETUP_INCOMING_VARARGS
956 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
958 /* Always strict argument naming on rs6000. */
959 #undef TARGET_STRICT_ARGUMENT_NAMING
960 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
961 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
962 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
963 #undef TARGET_SPLIT_COMPLEX_ARG
964 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
965 #undef TARGET_MUST_PASS_IN_STACK
966 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
967 #undef TARGET_PASS_BY_REFERENCE
968 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
970 #undef TARGET_BUILD_BUILTIN_VA_LIST
971 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
973 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
974 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
976 #undef TARGET_EH_RETURN_FILTER_MODE
977 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
979 #undef TARGET_VECTOR_MODE_SUPPORTED_P
980 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
982 struct gcc_target targetm
= TARGET_INITIALIZER
;
985 /* Value is 1 if hard register REGNO can hold a value of machine-mode
988 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
990 /* The GPRs can hold any mode, but values bigger than one register
991 cannot go past R31. */
992 if (INT_REGNO_P (regno
))
993 return INT_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1);
995 /* The float registers can only hold floating modes and DImode. */
996 if (FP_REGNO_P (regno
))
998 (GET_MODE_CLASS (mode
) == MODE_FLOAT
999 && FP_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1))
1000 || (GET_MODE_CLASS (mode
) == MODE_INT
1001 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
);
1003 /* The CR register can only hold CC modes. */
1004 if (CR_REGNO_P (regno
))
1005 return GET_MODE_CLASS (mode
) == MODE_CC
;
1007 if (XER_REGNO_P (regno
))
1008 return mode
== PSImode
;
1010 /* AltiVec only in AldyVec registers. */
1011 if (ALTIVEC_REGNO_P (regno
))
1012 return ALTIVEC_VECTOR_MODE (mode
);
1014 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1015 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1018 /* We cannot put TImode anywhere except general register and it must be
1019 able to fit within the register set. */
1021 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1024 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1026 rs6000_init_hard_regno_mode_ok (void)
1030 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1031 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1032 if (rs6000_hard_regno_mode_ok (r
, m
))
1033 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
1036 /* If not otherwise specified by a target, make 'long double' equivalent to
1039 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1040 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1043 /* Override command line options. Mostly we process the processor
1044 type and sometimes adjust other TARGET_ options. */
1047 rs6000_override_options (const char *default_cpu
)
1050 struct rs6000_cpu_select
*ptr
;
1053 /* Simplifications for entries below. */
1056 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1057 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1060 /* This table occasionally claims that a processor does not support
1061 a particular feature even though it does, but the feature is slower
1062 than the alternative. Thus, it shouldn't be relied on as a
1063 complete description of the processor's support.
1065 Please keep this list in order, and don't forget to update the
1066 documentation in invoke.texi when adding a new processor or
1070 const char *const name
; /* Canonical processor name. */
1071 const enum processor_type processor
; /* Processor type enum value. */
1072 const int target_enable
; /* Target flags to enable. */
1073 } const processor_target_table
[]
1074 = {{"401", PROCESSOR_PPC403
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1075 {"403", PROCESSOR_PPC403
,
1076 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_STRICT_ALIGN
},
1077 {"405", PROCESSOR_PPC405
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1078 {"405fp", PROCESSOR_PPC405
, POWERPC_BASE_MASK
},
1079 {"440", PROCESSOR_PPC440
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1080 {"440fp", PROCESSOR_PPC440
, POWERPC_BASE_MASK
},
1081 {"505", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
},
1082 {"601", PROCESSOR_PPC601
,
1083 MASK_POWER
| POWERPC_BASE_MASK
| MASK_MULTIPLE
| MASK_STRING
},
1084 {"602", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1085 {"603", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1086 {"603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1087 {"604", PROCESSOR_PPC604
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1088 {"604e", PROCESSOR_PPC604e
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1089 {"620", PROCESSOR_PPC620
,
1090 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1091 {"630", PROCESSOR_PPC630
,
1092 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1093 {"740", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1094 {"7400", PROCESSOR_PPC7400
, POWERPC_7400_MASK
},
1095 {"7450", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1096 {"750", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1097 {"801", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1098 {"821", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1099 {"823", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1100 {"8540", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1101 {"860", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1102 {"970", PROCESSOR_POWER4
,
1103 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1104 {"common", PROCESSOR_COMMON
, MASK_NEW_MNEMONICS
},
1105 {"ec603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1106 {"G3", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1107 {"G4", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1108 {"G5", PROCESSOR_POWER4
,
1109 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1110 {"power", PROCESSOR_POWER
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1111 {"power2", PROCESSOR_POWER
,
1112 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1113 {"power3", PROCESSOR_PPC630
,
1114 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1115 {"power4", PROCESSOR_POWER4
,
1116 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1117 {"power5", PROCESSOR_POWER5
,
1118 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1119 {"powerpc", PROCESSOR_POWERPC
, POWERPC_BASE_MASK
},
1120 {"powerpc64", PROCESSOR_POWERPC64
,
1121 POWERPC_BASE_MASK
| MASK_POWERPC64
},
1122 {"rios", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1123 {"rios1", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1124 {"rios2", PROCESSOR_RIOS2
,
1125 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1126 {"rsc", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1127 {"rsc1", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1128 {"rs64a", PROCESSOR_RS64A
, POWERPC_BASE_MASK
| MASK_POWERPC64
},
1131 const size_t ptt_size
= ARRAY_SIZE (processor_target_table
);
1133 /* Some OSs don't support saving the high part of 64-bit registers on
1134 context switch. Other OSs don't support saving Altivec registers.
1135 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1136 settings; if the user wants either, the user must explicitly specify
1137 them and we won't interfere with the user's specification. */
1140 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1141 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
1142 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1146 rs6000_init_hard_regno_mode_ok ();
1148 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
1149 #ifdef OS_MISSING_POWERPC64
1150 if (OS_MISSING_POWERPC64
)
1151 set_masks
&= ~MASK_POWERPC64
;
1153 #ifdef OS_MISSING_ALTIVEC
1154 if (OS_MISSING_ALTIVEC
)
1155 set_masks
&= ~MASK_ALTIVEC
;
1158 /* Don't override these by the processor default if given explicitly. */
1159 set_masks
&= ~(target_flags_explicit
1160 & (MASK_MULTIPLE
| MASK_STRING
| MASK_SOFT_FLOAT
));
1162 /* Identify the processor type. */
1163 rs6000_select
[0].string
= default_cpu
;
1164 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
1166 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1168 ptr
= &rs6000_select
[i
];
1169 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1171 for (j
= 0; j
< ptt_size
; j
++)
1172 if (! strcmp (ptr
->string
, processor_target_table
[j
].name
))
1174 if (ptr
->set_tune_p
)
1175 rs6000_cpu
= processor_target_table
[j
].processor
;
1177 if (ptr
->set_arch_p
)
1179 target_flags
&= ~set_masks
;
1180 target_flags
|= (processor_target_table
[j
].target_enable
1187 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1194 /* If we are optimizing big endian systems for space, use the load/store
1195 multiple and string instructions. */
1196 if (BYTES_BIG_ENDIAN
&& optimize_size
)
1197 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
1199 /* Don't allow -mmultiple or -mstring on little endian systems
1200 unless the cpu is a 750, because the hardware doesn't support the
1201 instructions used in little endian mode, and causes an alignment
1202 trap. The 750 does not cause an alignment trap (except when the
1203 target is unaligned). */
1205 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
1207 if (TARGET_MULTIPLE
)
1209 target_flags
&= ~MASK_MULTIPLE
;
1210 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
1211 warning ("-mmultiple is not supported on little endian systems");
1216 target_flags
&= ~MASK_STRING
;
1217 if ((target_flags_explicit
& MASK_STRING
) != 0)
1218 warning ("-mstring is not supported on little endian systems");
1222 /* Set debug flags */
1223 if (rs6000_debug_name
)
1225 if (! strcmp (rs6000_debug_name
, "all"))
1226 rs6000_debug_stack
= rs6000_debug_arg
= 1;
1227 else if (! strcmp (rs6000_debug_name
, "stack"))
1228 rs6000_debug_stack
= 1;
1229 else if (! strcmp (rs6000_debug_name
, "arg"))
1230 rs6000_debug_arg
= 1;
1232 error ("unknown -mdebug-%s switch", rs6000_debug_name
);
1235 if (rs6000_traceback_name
)
1237 if (! strncmp (rs6000_traceback_name
, "full", 4))
1238 rs6000_traceback
= traceback_full
;
1239 else if (! strncmp (rs6000_traceback_name
, "part", 4))
1240 rs6000_traceback
= traceback_part
;
1241 else if (! strncmp (rs6000_traceback_name
, "no", 2))
1242 rs6000_traceback
= traceback_none
;
1244 error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
1245 rs6000_traceback_name
);
1248 /* Set size of long double */
1249 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1250 if (rs6000_long_double_size_string
)
1253 int size
= strtol (rs6000_long_double_size_string
, &tail
, 10);
1254 if (*tail
!= '\0' || (size
!= 64 && size
!= 128))
1255 error ("Unknown switch -mlong-double-%s",
1256 rs6000_long_double_size_string
);
1258 rs6000_long_double_type_size
= size
;
1261 /* Set Altivec ABI as default for powerpc64 linux. */
1262 if (TARGET_ELF
&& TARGET_64BIT
)
1264 rs6000_altivec_abi
= 1;
1265 rs6000_altivec_vrsave
= 1;
1268 /* Handle -mabi= options. */
1269 rs6000_parse_abi_options ();
1271 /* Handle -malign-XXXXX option. */
1272 rs6000_parse_alignment_option ();
1274 /* Handle generic -mFOO=YES/NO options. */
1275 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string
,
1276 &rs6000_altivec_vrsave
);
1277 rs6000_parse_yes_no_option ("isel", rs6000_isel_string
,
1279 rs6000_parse_yes_no_option ("spe", rs6000_spe_string
, &rs6000_spe
);
1280 rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string
,
1281 &rs6000_float_gprs
);
1283 /* Handle -mtls-size option. */
1284 rs6000_parse_tls_size_option ();
1286 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1287 SUBTARGET_OVERRIDE_OPTIONS
;
1289 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1290 SUBSUBTARGET_OVERRIDE_OPTIONS
;
1296 error ("AltiVec and E500 instructions cannot coexist");
1298 /* The e500 does not have string instructions, and we set
1299 MASK_STRING above when optimizing for size. */
1300 if ((target_flags
& MASK_STRING
) != 0)
1301 target_flags
= target_flags
& ~MASK_STRING
;
1303 /* No SPE means 64-bit long doubles, even if an E500. */
1304 if (rs6000_spe_string
!= 0
1305 && !strcmp (rs6000_spe_string
, "no"))
1306 rs6000_long_double_type_size
= 64;
1308 else if (rs6000_select
[1].string
!= NULL
)
1310 /* For the powerpc-eabispe configuration, we set all these by
1311 default, so let's unset them if we manually set another
1312 CPU that is not the E500. */
1313 if (rs6000_abi_string
== 0)
1315 if (rs6000_spe_string
== 0)
1317 if (rs6000_float_gprs_string
== 0)
1318 rs6000_float_gprs
= 0;
1319 if (rs6000_isel_string
== 0)
1321 if (rs6000_long_double_size_string
== 0)
1322 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1325 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
1326 && rs6000_cpu
!= PROCESSOR_POWER5
);
1327 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
1328 || rs6000_cpu
== PROCESSOR_POWER5
);
1330 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1331 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1332 bits in target_flags so TARGET_SWITCHES cannot be used.
1333 Assumption here is that rs6000_longcall_switch points into the
1334 text of the complete option, rather than being a copy, so we can
1335 scan back for the presence or absence of the no- modifier. */
1336 if (rs6000_longcall_switch
)
1338 const char *base
= rs6000_longcall_switch
;
1339 while (base
[-1] != 'm') base
--;
1341 if (*rs6000_longcall_switch
!= '\0')
1342 error ("invalid option `%s'", base
);
1343 rs6000_default_long_calls
= (base
[0] != 'n');
1346 /* Handle -m(no-)warn-altivec-long similarly. */
1347 if (rs6000_warn_altivec_long_switch
)
1349 const char *base
= rs6000_warn_altivec_long_switch
;
1350 while (base
[-1] != 'm') base
--;
1352 if (*rs6000_warn_altivec_long_switch
!= '\0')
1353 error ("invalid option `%s'", base
);
1354 rs6000_warn_altivec_long
= (base
[0] != 'n');
1357 /* Handle -mprioritize-restricted-insns option. */
1358 rs6000_sched_restricted_insns_priority
1359 = (rs6000_sched_groups
? 1 : 0);
1360 if (rs6000_sched_restricted_insns_priority_str
)
1361 rs6000_sched_restricted_insns_priority
=
1362 atoi (rs6000_sched_restricted_insns_priority_str
);
1364 /* Handle -msched-costly-dep option. */
1365 rs6000_sched_costly_dep
1366 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
1367 if (rs6000_sched_costly_dep_str
)
1369 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
1370 rs6000_sched_costly_dep
= no_dep_costly
;
1371 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
1372 rs6000_sched_costly_dep
= all_deps_costly
;
1373 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
1374 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
1375 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
1376 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
1378 rs6000_sched_costly_dep
= atoi (rs6000_sched_costly_dep_str
);
1381 /* Handle -minsert-sched-nops option. */
1382 rs6000_sched_insert_nops
1383 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
1384 if (rs6000_sched_insert_nops_str
)
1386 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
1387 rs6000_sched_insert_nops
= sched_finish_none
;
1388 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
1389 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
1390 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
1391 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
1393 rs6000_sched_insert_nops
= atoi (rs6000_sched_insert_nops_str
);
1396 #ifdef TARGET_REGNAMES
1397 /* If the user desires alternate register names, copy in the
1398 alternate names now. */
1399 if (TARGET_REGNAMES
)
1400 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
1403 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1404 If -maix-struct-return or -msvr4-struct-return was explicitly
1405 used, don't override with the ABI default. */
1406 if ((target_flags_explicit
& MASK_AIX_STRUCT_RET
) == 0)
1408 if (DEFAULT_ABI
== ABI_V4
&& !DRAFT_V4_STRUCT_RET
)
1409 target_flags
= (target_flags
& ~MASK_AIX_STRUCT_RET
);
1411 target_flags
|= MASK_AIX_STRUCT_RET
;
1414 if (TARGET_LONG_DOUBLE_128
1415 && (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
))
1416 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
1418 /* Allocate an alias set for register saves & restores from stack. */
1419 rs6000_sr_alias_set
= new_alias_set ();
1422 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
1424 /* We can only guarantee the availability of DI pseudo-ops when
1425 assembling for 64-bit targets. */
1428 targetm
.asm_out
.aligned_op
.di
= NULL
;
1429 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1432 /* Set branch target alignment, if not optimizing for size. */
1435 if (rs6000_sched_groups
)
1437 if (align_functions
<= 0)
1438 align_functions
= 16;
1439 if (align_jumps
<= 0)
1441 if (align_loops
<= 0)
1444 if (align_jumps_max_skip
<= 0)
1445 align_jumps_max_skip
= 15;
1446 if (align_loops_max_skip
<= 0)
1447 align_loops_max_skip
= 15;
1450 /* Arrange to save and restore machine status around nested functions. */
1451 init_machine_status
= rs6000_init_machine_status
;
1453 /* We should always be splitting complex arguments, but we can't break
1454 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1455 if (DEFAULT_ABI
!= ABI_AIX
)
1456 targetm
.calls
.split_complex_arg
= NULL
;
1458 /* Initialize rs6000_cost with the appropriate target costs. */
1460 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
1464 case PROCESSOR_RIOS1
:
1465 rs6000_cost
= &rios1_cost
;
1468 case PROCESSOR_RIOS2
:
1469 rs6000_cost
= &rios2_cost
;
1472 case PROCESSOR_RS64A
:
1473 rs6000_cost
= &rs64a_cost
;
1476 case PROCESSOR_MPCCORE
:
1477 rs6000_cost
= &mpccore_cost
;
1480 case PROCESSOR_PPC403
:
1481 rs6000_cost
= &ppc403_cost
;
1484 case PROCESSOR_PPC405
:
1485 rs6000_cost
= &ppc405_cost
;
1488 case PROCESSOR_PPC440
:
1489 rs6000_cost
= &ppc440_cost
;
1492 case PROCESSOR_PPC601
:
1493 rs6000_cost
= &ppc601_cost
;
1496 case PROCESSOR_PPC603
:
1497 rs6000_cost
= &ppc603_cost
;
1500 case PROCESSOR_PPC604
:
1501 rs6000_cost
= &ppc604_cost
;
1504 case PROCESSOR_PPC604e
:
1505 rs6000_cost
= &ppc604e_cost
;
1508 case PROCESSOR_PPC620
:
1509 rs6000_cost
= &ppc620_cost
;
1512 case PROCESSOR_PPC630
:
1513 rs6000_cost
= &ppc630_cost
;
1516 case PROCESSOR_PPC750
:
1517 case PROCESSOR_PPC7400
:
1518 rs6000_cost
= &ppc750_cost
;
1521 case PROCESSOR_PPC7450
:
1522 rs6000_cost
= &ppc7450_cost
;
1525 case PROCESSOR_PPC8540
:
1526 rs6000_cost
= &ppc8540_cost
;
1529 case PROCESSOR_POWER4
:
1530 case PROCESSOR_POWER5
:
1531 rs6000_cost
= &power4_cost
;
1539 /* Handle generic options of the form -mfoo=yes/no.
1540 NAME is the option name.
1541 VALUE is the option value.
1542 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1543 whether the option value is 'yes' or 'no' respectively. */
1545 rs6000_parse_yes_no_option (const char *name
, const char *value
, int *flag
)
1549 else if (!strcmp (value
, "yes"))
1551 else if (!strcmp (value
, "no"))
1554 error ("unknown -m%s= option specified: '%s'", name
, value
);
1557 /* Handle -mabi= options. */
1559 rs6000_parse_abi_options (void)
1561 if (rs6000_abi_string
== 0)
1563 else if (! strcmp (rs6000_abi_string
, "altivec"))
1565 rs6000_altivec_abi
= 1;
1568 else if (! strcmp (rs6000_abi_string
, "no-altivec"))
1569 rs6000_altivec_abi
= 0;
1570 else if (! strcmp (rs6000_abi_string
, "spe"))
1573 rs6000_altivec_abi
= 0;
1574 if (!TARGET_SPE_ABI
)
1575 error ("not configured for ABI: '%s'", rs6000_abi_string
);
1578 else if (! strcmp (rs6000_abi_string
, "no-spe"))
1581 error ("unknown ABI specified: '%s'", rs6000_abi_string
);
1584 /* Handle -malign-XXXXXX options. */
1586 rs6000_parse_alignment_option (void)
1588 if (rs6000_alignment_string
== 0)
1590 else if (! strcmp (rs6000_alignment_string
, "power"))
1591 rs6000_alignment_flags
= MASK_ALIGN_POWER
;
1592 else if (! strcmp (rs6000_alignment_string
, "natural"))
1593 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1595 error ("unknown -malign-XXXXX option specified: '%s'",
1596 rs6000_alignment_string
);
1599 /* Validate and record the size specified with the -mtls-size option. */
1602 rs6000_parse_tls_size_option (void)
1604 if (rs6000_tls_size_string
== 0)
1606 else if (strcmp (rs6000_tls_size_string
, "16") == 0)
1607 rs6000_tls_size
= 16;
1608 else if (strcmp (rs6000_tls_size_string
, "32") == 0)
1609 rs6000_tls_size
= 32;
1610 else if (strcmp (rs6000_tls_size_string
, "64") == 0)
1611 rs6000_tls_size
= 64;
1613 error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string
);
1617 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
1621 /* Do anything needed at the start of the asm file. */
1624 rs6000_file_start (void)
1628 const char *start
= buffer
;
1629 struct rs6000_cpu_select
*ptr
;
1630 const char *default_cpu
= TARGET_CPU_DEFAULT
;
1631 FILE *file
= asm_out_file
;
1633 default_file_start ();
1635 #ifdef TARGET_BI_ARCH
1636 if ((TARGET_DEFAULT
^ target_flags
) & MASK_64BIT
)
1640 if (flag_verbose_asm
)
1642 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
1643 rs6000_select
[0].string
= default_cpu
;
1645 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1647 ptr
= &rs6000_select
[i
];
1648 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1650 fprintf (file
, "%s %s%s", start
, ptr
->name
, ptr
->string
);
1655 #ifdef USING_ELFOS_H
1656 switch (rs6000_sdata
)
1658 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
1659 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
1660 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
1661 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
1664 if (rs6000_sdata
&& g_switch_value
)
1666 fprintf (file
, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED
, start
,
1677 /* Return nonzero if this function is known to have a null epilogue. */
1680 direct_return (void)
1682 if (reload_completed
)
1684 rs6000_stack_t
*info
= rs6000_stack_info ();
1686 if (info
->first_gp_reg_save
== 32
1687 && info
->first_fp_reg_save
== 64
1688 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
1689 && ! info
->lr_save_p
1690 && ! info
->cr_save_p
1691 && info
->vrsave_mask
== 0
1699 /* Returns 1 always. */
1702 any_operand (rtx op ATTRIBUTE_UNUSED
,
1703 enum machine_mode mode ATTRIBUTE_UNUSED
)
1708 /* Returns 1 always. */
1711 any_parallel_operand (rtx op ATTRIBUTE_UNUSED
,
1712 enum machine_mode mode ATTRIBUTE_UNUSED
)
1717 /* Returns 1 if op is the count register. */
1720 count_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1722 if (GET_CODE (op
) != REG
)
1725 if (REGNO (op
) == COUNT_REGISTER_REGNUM
)
1728 if (REGNO (op
) > FIRST_PSEUDO_REGISTER
)
1734 /* Returns 1 if op is an altivec register. */
1737 altivec_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1740 return (register_operand (op
, mode
)
1741 && (GET_CODE (op
) != REG
1742 || REGNO (op
) > FIRST_PSEUDO_REGISTER
1743 || ALTIVEC_REGNO_P (REGNO (op
))));
1747 xer_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1749 if (GET_CODE (op
) != REG
)
1752 if (XER_REGNO_P (REGNO (op
)))
1758 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1759 by such constants completes more quickly. */
1762 s8bit_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1764 return ( GET_CODE (op
) == CONST_INT
1765 && (INTVAL (op
) >= -128 && INTVAL (op
) <= 127));
1768 /* Return 1 if OP is a constant that can fit in a D field. */
1771 short_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1773 return (GET_CODE (op
) == CONST_INT
1774 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I'));
1777 /* Similar for an unsigned D field. */
1780 u_short_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1782 return (GET_CODE (op
) == CONST_INT
1783 && CONST_OK_FOR_LETTER_P (INTVAL (op
) & GET_MODE_MASK (mode
), 'K'));
1786 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1789 non_short_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1791 return (GET_CODE (op
) == CONST_INT
1792 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x8000) >= 0x10000);
1795 /* Returns 1 if OP is a CONST_INT that is a positive value
1796 and an exact power of 2. */
1799 exact_log2_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1801 return (GET_CODE (op
) == CONST_INT
1803 && exact_log2 (INTVAL (op
)) >= 0);
1806 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1810 gpc_reg_operand (rtx op
, enum machine_mode mode
)
1812 return (register_operand (op
, mode
)
1813 && (GET_CODE (op
) != REG
1814 || (REGNO (op
) >= ARG_POINTER_REGNUM
1815 && !XER_REGNO_P (REGNO (op
)))
1816 || REGNO (op
) < MQ_REGNO
));
1819 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1823 cc_reg_operand (rtx op
, enum machine_mode mode
)
1825 return (register_operand (op
, mode
)
1826 && (GET_CODE (op
) != REG
1827 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
1828 || CR_REGNO_P (REGNO (op
))));
1831 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1832 CR field that isn't CR0. */
1835 cc_reg_not_cr0_operand (rtx op
, enum machine_mode mode
)
1837 return (register_operand (op
, mode
)
1838 && (GET_CODE (op
) != REG
1839 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
1840 || CR_REGNO_NOT_CR0_P (REGNO (op
))));
1843 /* Returns 1 if OP is either a constant integer valid for a D-field or
1844 a non-special register. If a register, it must be in the proper
1845 mode unless MODE is VOIDmode. */
1848 reg_or_short_operand (rtx op
, enum machine_mode mode
)
1850 return short_cint_operand (op
, mode
) || gpc_reg_operand (op
, mode
);
1853 /* Similar, except check if the negation of the constant would be
1854 valid for a D-field. Don't allow a constant zero, since all the
1855 patterns that call this predicate use "addic r1,r2,-constant" on
1856 a constant value to set a carry when r2 is greater or equal to
1857 "constant". That doesn't work for zero. */
1860 reg_or_neg_short_operand (rtx op
, enum machine_mode mode
)
1862 if (GET_CODE (op
) == CONST_INT
)
1863 return CONST_OK_FOR_LETTER_P (INTVAL (op
), 'P') && INTVAL (op
) != 0;
1865 return gpc_reg_operand (op
, mode
);
1868 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1869 a non-special register. If a register, it must be in the proper
1870 mode unless MODE is VOIDmode. */
1873 reg_or_aligned_short_operand (rtx op
, enum machine_mode mode
)
1875 if (gpc_reg_operand (op
, mode
))
1877 else if (short_cint_operand (op
, mode
) && !(INTVAL (op
) & 3))
1884 /* Return 1 if the operand is either a register or an integer whose
1885 high-order 16 bits are zero. */
1888 reg_or_u_short_operand (rtx op
, enum machine_mode mode
)
1890 return u_short_cint_operand (op
, mode
) || gpc_reg_operand (op
, mode
);
1893 /* Return 1 is the operand is either a non-special register or ANY
1894 constant integer. */
1897 reg_or_cint_operand (rtx op
, enum machine_mode mode
)
1899 return (GET_CODE (op
) == CONST_INT
|| gpc_reg_operand (op
, mode
));
1902 /* Return 1 is the operand is either a non-special register or ANY
1903 32-bit signed constant integer. */
1906 reg_or_arith_cint_operand (rtx op
, enum machine_mode mode
)
1908 return (gpc_reg_operand (op
, mode
)
1909 || (GET_CODE (op
) == CONST_INT
1910 #if HOST_BITS_PER_WIDE_INT != 32
1911 && ((unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x80000000)
1912 < (unsigned HOST_WIDE_INT
) 0x100000000ll
)
1917 /* Return 1 is the operand is either a non-special register or a 32-bit
1918 signed constant integer valid for 64-bit addition. */
1921 reg_or_add_cint64_operand (rtx op
, enum machine_mode mode
)
1923 return (gpc_reg_operand (op
, mode
)
1924 || (GET_CODE (op
) == CONST_INT
1925 #if HOST_BITS_PER_WIDE_INT == 32
1926 && INTVAL (op
) < 0x7fff8000
1928 && ((unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x80008000)
1934 /* Return 1 is the operand is either a non-special register or a 32-bit
1935 signed constant integer valid for 64-bit subtraction. */
1938 reg_or_sub_cint64_operand (rtx op
, enum machine_mode mode
)
1940 return (gpc_reg_operand (op
, mode
)
1941 || (GET_CODE (op
) == CONST_INT
1942 #if HOST_BITS_PER_WIDE_INT == 32
1943 && (- INTVAL (op
)) < 0x7fff8000
1945 && ((unsigned HOST_WIDE_INT
) ((- INTVAL (op
)) + 0x80008000)
1951 /* Return 1 is the operand is either a non-special register or ANY
1952 32-bit unsigned constant integer. */
1955 reg_or_logical_cint_operand (rtx op
, enum machine_mode mode
)
1957 if (GET_CODE (op
) == CONST_INT
)
1959 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
1961 if (GET_MODE_BITSIZE (mode
) <= 32)
1964 if (INTVAL (op
) < 0)
1968 return ((INTVAL (op
) & GET_MODE_MASK (mode
)
1969 & (~ (unsigned HOST_WIDE_INT
) 0xffffffff)) == 0);
1971 else if (GET_CODE (op
) == CONST_DOUBLE
)
1973 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
1977 return CONST_DOUBLE_HIGH (op
) == 0;
1980 return gpc_reg_operand (op
, mode
);
1983 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
1986 got_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1988 return (GET_CODE (op
) == SYMBOL_REF
1989 || GET_CODE (op
) == CONST
1990 || GET_CODE (op
) == LABEL_REF
);
1993 /* Return 1 if the operand is a simple references that can be loaded via
1994 the GOT (labels involving addition aren't allowed). */
1997 got_no_const_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1999 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
);
2002 /* Return the number of instructions it takes to form a constant in an
2003 integer register. */
2006 num_insns_constant_wide (HOST_WIDE_INT value
)
2008 /* signed constant loadable with {cal|addi} */
2009 if (CONST_OK_FOR_LETTER_P (value
, 'I'))
2012 /* constant loadable with {cau|addis} */
2013 else if (CONST_OK_FOR_LETTER_P (value
, 'L'))
2016 #if HOST_BITS_PER_WIDE_INT == 64
2017 else if (TARGET_POWERPC64
)
2019 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2020 HOST_WIDE_INT high
= value
>> 31;
2022 if (high
== 0 || high
== -1)
2028 return num_insns_constant_wide (high
) + 1;
2030 return (num_insns_constant_wide (high
)
2031 + num_insns_constant_wide (low
) + 1);
2040 num_insns_constant (rtx op
, enum machine_mode mode
)
2042 if (GET_CODE (op
) == CONST_INT
)
2044 #if HOST_BITS_PER_WIDE_INT == 64
2045 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
2046 && mask64_operand (op
, mode
))
2050 return num_insns_constant_wide (INTVAL (op
));
2053 else if (GET_CODE (op
) == CONST_DOUBLE
&& mode
== SFmode
)
2058 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2059 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2060 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
2063 else if (GET_CODE (op
) == CONST_DOUBLE
)
2069 int endian
= (WORDS_BIG_ENDIAN
== 0);
2071 if (mode
== VOIDmode
|| mode
== DImode
)
2073 high
= CONST_DOUBLE_HIGH (op
);
2074 low
= CONST_DOUBLE_LOW (op
);
2078 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2079 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
2081 low
= l
[1 - endian
];
2085 return (num_insns_constant_wide (low
)
2086 + num_insns_constant_wide (high
));
2090 if (high
== 0 && low
>= 0)
2091 return num_insns_constant_wide (low
);
2093 else if (high
== -1 && low
< 0)
2094 return num_insns_constant_wide (low
);
2096 else if (mask64_operand (op
, mode
))
2100 return num_insns_constant_wide (high
) + 1;
2103 return (num_insns_constant_wide (high
)
2104 + num_insns_constant_wide (low
) + 1);
2112 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
2113 register with one instruction per word. We only do this if we can
2114 safely read CONST_DOUBLE_{LOW,HIGH}. */
2117 easy_fp_constant (rtx op
, enum machine_mode mode
)
2119 if (GET_CODE (op
) != CONST_DOUBLE
2120 || GET_MODE (op
) != mode
2121 || (GET_MODE_CLASS (mode
) != MODE_FLOAT
&& mode
!= DImode
))
2124 /* Consider all constants with -msoft-float to be easy. */
2125 if ((TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
2129 /* If we are using V.4 style PIC, consider all constants to be hard. */
2130 if (flag_pic
&& DEFAULT_ABI
== ABI_V4
)
2133 #ifdef TARGET_RELOCATABLE
2134 /* Similarly if we are using -mrelocatable, consider all constants
2136 if (TARGET_RELOCATABLE
)
2145 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2146 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
2148 return (num_insns_constant_wide ((HOST_WIDE_INT
) k
[0]) == 1
2149 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[1]) == 1
2150 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[2]) == 1
2151 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[3]) == 1);
2154 else if (mode
== DFmode
)
2159 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2160 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
2162 return (num_insns_constant_wide ((HOST_WIDE_INT
) k
[0]) == 1
2163 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[1]) == 1);
2166 else if (mode
== SFmode
)
2171 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2172 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2174 return num_insns_constant_wide (l
) == 1;
2177 else if (mode
== DImode
)
2178 return ((TARGET_POWERPC64
2179 && GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_LOW (op
) == 0)
2180 || (num_insns_constant (op
, DImode
) <= 2));
2182 else if (mode
== SImode
)
2188 /* Returns the constant for the splat instruction, if exists. */
2191 easy_vector_splat_const (int cst
, enum machine_mode mode
)
2196 if (EASY_VECTOR_15 (cst
)
2197 || EASY_VECTOR_15_ADD_SELF (cst
))
2199 if ((cst
& 0xffff) != ((cst
>> 16) & 0xffff))
2203 if (EASY_VECTOR_15 (cst
)
2204 || EASY_VECTOR_15_ADD_SELF (cst
))
2206 if ((cst
& 0xff) != ((cst
>> 8) & 0xff))
2210 if (EASY_VECTOR_15 (cst
)
2211 || EASY_VECTOR_15_ADD_SELF (cst
))
2220 /* Return nonzero if all elements of a vector have the same value. */
2223 easy_vector_same (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2227 units
= CONST_VECTOR_NUNITS (op
);
2229 cst
= INTVAL (CONST_VECTOR_ELT (op
, 0));
2230 for (i
= 1; i
< units
; ++i
)
2231 if (INTVAL (CONST_VECTOR_ELT (op
, i
)) != cst
)
2233 if (i
== units
&& easy_vector_splat_const (cst
, mode
))
2238 /* Return 1 if the operand is a CONST_INT and can be put into a
2239 register without using memory. */
2242 easy_vector_constant (rtx op
, enum machine_mode mode
)
2246 if (GET_CODE (op
) != CONST_VECTOR
2251 if (zero_constant (op
, mode
)
2252 && ((TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
2253 || (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))))
2256 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
2259 if (TARGET_SPE
&& mode
== V1DImode
)
2262 cst
= INTVAL (CONST_VECTOR_ELT (op
, 0));
2263 cst2
= INTVAL (CONST_VECTOR_ELT (op
, 1));
2265 /* Limit SPE vectors to 15 bits signed. These we can generate with:
2267 evmergelo r0, r0, r0
2270 I don't know how efficient it would be to allow bigger constants,
2271 considering we'll have an extra 'ori' for every 'li'. I doubt 5
2272 instructions is better than a 64-bit memory load, but I don't
2273 have the e500 timing specs. */
2274 if (TARGET_SPE
&& mode
== V2SImode
2275 && cst
>= -0x7fff && cst
<= 0x7fff
2276 && cst2
>= -0x7fff && cst2
<= 0x7fff)
2280 && easy_vector_same (op
, mode
))
2282 cst
= easy_vector_splat_const (cst
, mode
);
2283 if (EASY_VECTOR_15_ADD_SELF (cst
)
2284 || EASY_VECTOR_15 (cst
))
2290 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
2293 easy_vector_constant_add_self (rtx op
, enum machine_mode mode
)
2297 && GET_CODE (op
) == CONST_VECTOR
2298 && easy_vector_same (op
, mode
))
2300 cst
= easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op
, 0)), mode
);
2301 if (EASY_VECTOR_15_ADD_SELF (cst
))
2307 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2310 gen_easy_vector_constant_add_self (rtx op
)
2314 units
= GET_MODE_NUNITS (GET_MODE (op
));
2315 v
= rtvec_alloc (units
);
2317 for (i
= 0; i
< units
; i
++)
2319 GEN_INT (INTVAL (CONST_VECTOR_ELT (op
, i
)) >> 1);
2320 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op
), v
);
2324 output_vec_const_move (rtx
*operands
)
2327 enum machine_mode mode
;
2333 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
2334 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
2335 mode
= GET_MODE (dest
);
2339 if (zero_constant (vec
, mode
))
2340 return "vxor %0,%0,%0";
2341 else if (easy_vector_constant (vec
, mode
))
2343 operands
[1] = GEN_INT (cst
);
2347 if (EASY_VECTOR_15 (cst
))
2349 operands
[1] = GEN_INT (cst
);
2350 return "vspltisw %0,%1";
2352 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2356 if (EASY_VECTOR_15 (cst
))
2358 operands
[1] = GEN_INT (cst
);
2359 return "vspltish %0,%1";
2361 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2365 if (EASY_VECTOR_15 (cst
))
2367 operands
[1] = GEN_INT (cst
);
2368 return "vspltisb %0,%1";
2370 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2382 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2383 pattern of V1DI, V4HI, and V2SF.
2385 FIXME: We should probably return # and add post reload
2386 splitters for these, but this way is so easy ;-).
2388 operands
[1] = GEN_INT (cst
);
2389 operands
[2] = GEN_INT (cst2
);
2391 return "li %0,%1\n\tevmergelo %0,%0,%0";
2393 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2399 /* Return 1 if the operand is the constant 0. This works for scalars
2400 as well as vectors. */
2402 zero_constant (rtx op
, enum machine_mode mode
)
2404 return op
== CONST0_RTX (mode
);
2407 /* Return 1 if the operand is 0.0. */
2409 zero_fp_constant (rtx op
, enum machine_mode mode
)
2411 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
);
2414 /* Return 1 if the operand is in volatile memory. Note that during
2415 the RTL generation phase, memory_operand does not return TRUE for
2416 volatile memory references. So this function allows us to
2417 recognize volatile references where its safe. */
2420 volatile_mem_operand (rtx op
, enum machine_mode mode
)
2422 if (GET_CODE (op
) != MEM
)
2425 if (!MEM_VOLATILE_P (op
))
2428 if (mode
!= GET_MODE (op
))
2431 if (reload_completed
)
2432 return memory_operand (op
, mode
);
2434 if (reload_in_progress
)
2435 return strict_memory_address_p (mode
, XEXP (op
, 0));
2437 return memory_address_p (mode
, XEXP (op
, 0));
2440 /* Return 1 if the operand is an offsettable memory operand. */
2443 offsettable_mem_operand (rtx op
, enum machine_mode mode
)
2445 return ((GET_CODE (op
) == MEM
)
2446 && offsettable_address_p (reload_completed
|| reload_in_progress
,
2447 mode
, XEXP (op
, 0)));
2450 /* Return 1 if the operand is either an easy FP constant (see above) or
2454 mem_or_easy_const_operand (rtx op
, enum machine_mode mode
)
2456 return memory_operand (op
, mode
) || easy_fp_constant (op
, mode
);
2459 /* Return 1 if the operand is either a non-special register or an item
2460 that can be used as the operand of a `mode' add insn. */
2463 add_operand (rtx op
, enum machine_mode mode
)
2465 if (GET_CODE (op
) == CONST_INT
)
2466 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
2467 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
2469 return gpc_reg_operand (op
, mode
);
2472 /* Return 1 if OP is a constant but not a valid add_operand. */
2475 non_add_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2477 return (GET_CODE (op
) == CONST_INT
2478 && !CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
2479 && !CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
2482 /* Return 1 if the operand is a non-special register or a constant that
2483 can be used as the operand of an OR or XOR insn on the RS/6000. */
2486 logical_operand (rtx op
, enum machine_mode mode
)
2488 HOST_WIDE_INT opl
, oph
;
2490 if (gpc_reg_operand (op
, mode
))
2493 if (GET_CODE (op
) == CONST_INT
)
2495 opl
= INTVAL (op
) & GET_MODE_MASK (mode
);
2497 #if HOST_BITS_PER_WIDE_INT <= 32
2498 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
&& opl
< 0)
2502 else if (GET_CODE (op
) == CONST_DOUBLE
)
2504 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
2507 opl
= CONST_DOUBLE_LOW (op
);
2508 oph
= CONST_DOUBLE_HIGH (op
);
2515 return ((opl
& ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0
2516 || (opl
& ~ (unsigned HOST_WIDE_INT
) 0xffff0000) == 0);
2519 /* Return 1 if C is a constant that is not a logical operand (as
2520 above), but could be split into one. */
2523 non_logical_cint_operand (rtx op
, enum machine_mode mode
)
2525 return ((GET_CODE (op
) == CONST_INT
|| GET_CODE (op
) == CONST_DOUBLE
)
2526 && ! logical_operand (op
, mode
)
2527 && reg_or_logical_cint_operand (op
, mode
));
2530 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2531 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2532 Reject all ones and all zeros, since these should have been optimized
2533 away and confuse the making of MB and ME. */
2536 mask_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2538 HOST_WIDE_INT c
, lsb
;
2540 if (GET_CODE (op
) != CONST_INT
)
2545 /* Fail in 64-bit mode if the mask wraps around because the upper
2546 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2547 if (TARGET_POWERPC64
&& (c
& 0x80000001) == 0x80000001)
2550 /* We don't change the number of transitions by inverting,
2551 so make sure we start with the LS bit zero. */
2555 /* Reject all zeros or all ones. */
2559 /* Find the first transition. */
2562 /* Invert to look for a second transition. */
2565 /* Erase first transition. */
2568 /* Find the second transition (if any). */
2571 /* Match if all the bits above are 1's (or c is zero). */
2575 /* Return 1 for the PowerPC64 rlwinm corner case. */
2578 mask_operand_wrap (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2580 HOST_WIDE_INT c
, lsb
;
2582 if (GET_CODE (op
) != CONST_INT
)
2587 if ((c
& 0x80000001) != 0x80000001)
2601 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2602 It is if there are no more than one 1->0 or 0->1 transitions.
2603 Reject all zeros, since zero should have been optimized away and
2604 confuses the making of MB and ME. */
2607 mask64_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2609 if (GET_CODE (op
) == CONST_INT
)
2611 HOST_WIDE_INT c
, lsb
;
2615 /* Reject all zeros. */
2619 /* We don't change the number of transitions by inverting,
2620 so make sure we start with the LS bit zero. */
2624 /* Find the transition, and check that all bits above are 1's. */
2627 /* Match if all the bits above are 1's (or c is zero). */
2633 /* Like mask64_operand, but allow up to three transitions. This
2634 predicate is used by insn patterns that generate two rldicl or
2635 rldicr machine insns. */
2638 mask64_2_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2640 if (GET_CODE (op
) == CONST_INT
)
2642 HOST_WIDE_INT c
, lsb
;
2646 /* Disallow all zeros. */
2650 /* We don't change the number of transitions by inverting,
2651 so make sure we start with the LS bit zero. */
2655 /* Find the first transition. */
2658 /* Invert to look for a second transition. */
2661 /* Erase first transition. */
2664 /* Find the second transition. */
2667 /* Invert to look for a third transition. */
2670 /* Erase second transition. */
2673 /* Find the third transition (if any). */
2676 /* Match if all the bits above are 1's (or c is zero). */
2682 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2683 implement ANDing by the mask IN. */
2685 build_mask64_2_operands (rtx in
, rtx
*out
)
2687 #if HOST_BITS_PER_WIDE_INT >= 64
2688 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
2691 if (GET_CODE (in
) != CONST_INT
)
2697 /* Assume c initially something like 0x00fff000000fffff. The idea
2698 is to rotate the word so that the middle ^^^^^^ group of zeros
2699 is at the MS end and can be cleared with an rldicl mask. We then
2700 rotate back and clear off the MS ^^ group of zeros with a
2702 c
= ~c
; /* c == 0xff000ffffff00000 */
2703 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
2704 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
2705 c
= ~c
; /* c == 0x00fff000000fffff */
2706 c
&= -lsb
; /* c == 0x00fff00000000000 */
2707 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2708 c
= ~c
; /* c == 0xff000fffffffffff */
2709 c
&= -lsb
; /* c == 0xff00000000000000 */
2711 while ((lsb
>>= 1) != 0)
2712 shift
++; /* shift == 44 on exit from loop */
2713 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
2714 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
2715 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
2719 /* Assume c initially something like 0xff000f0000000000. The idea
2720 is to rotate the word so that the ^^^ middle group of zeros
2721 is at the LS end and can be cleared with an rldicr mask. We then
2722 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2724 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
2725 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
2726 c
= ~c
; /* c == 0x00fff0ffffffffff */
2727 c
&= -lsb
; /* c == 0x00fff00000000000 */
2728 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2729 c
= ~c
; /* c == 0xff000fffffffffff */
2730 c
&= -lsb
; /* c == 0xff00000000000000 */
2732 while ((lsb
>>= 1) != 0)
2733 shift
++; /* shift == 44 on exit from loop */
2734 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
2735 m1
>>= shift
; /* m1 == 0x0000000000000fff */
2736 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
2739 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2740 masks will be all 1's. We are guaranteed more than one transition. */
2741 out
[0] = GEN_INT (64 - shift
);
2742 out
[1] = GEN_INT (m1
);
2743 out
[2] = GEN_INT (shift
);
2744 out
[3] = GEN_INT (m2
);
2752 /* Return 1 if the operand is either a non-special register or a constant
2753 that can be used as the operand of a PowerPC64 logical AND insn. */
2756 and64_operand (rtx op
, enum machine_mode mode
)
2758 if (fixed_regs
[CR0_REGNO
]) /* CR0 not available, don't do andi./andis. */
2759 return (gpc_reg_operand (op
, mode
) || mask64_operand (op
, mode
));
2761 return (logical_operand (op
, mode
) || mask64_operand (op
, mode
));
2764 /* Like the above, but also match constants that can be implemented
2765 with two rldicl or rldicr insns. */
2768 and64_2_operand (rtx op
, enum machine_mode mode
)
2770 if (fixed_regs
[CR0_REGNO
]) /* CR0 not available, don't do andi./andis. */
2771 return gpc_reg_operand (op
, mode
) || mask64_2_operand (op
, mode
);
2773 return logical_operand (op
, mode
) || mask64_2_operand (op
, mode
);
2776 /* Return 1 if the operand is either a non-special register or a
2777 constant that can be used as the operand of an RS/6000 logical AND insn. */
2780 and_operand (rtx op
, enum machine_mode mode
)
2782 if (fixed_regs
[CR0_REGNO
]) /* CR0 not available, don't do andi./andis. */
2783 return (gpc_reg_operand (op
, mode
) || mask_operand (op
, mode
));
2785 return (logical_operand (op
, mode
) || mask_operand (op
, mode
));
2788 /* Return 1 if the operand is a general register or memory operand. */
2791 reg_or_mem_operand (rtx op
, enum machine_mode mode
)
2793 return (gpc_reg_operand (op
, mode
)
2794 || memory_operand (op
, mode
)
2795 || macho_lo_sum_memory_operand (op
, mode
)
2796 || volatile_mem_operand (op
, mode
));
2799 /* Return 1 if the operand is a general register or memory operand without
2800 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2804 lwa_operand (rtx op
, enum machine_mode mode
)
2808 if (reload_completed
&& GET_CODE (inner
) == SUBREG
)
2809 inner
= SUBREG_REG (inner
);
2811 return gpc_reg_operand (inner
, mode
)
2812 || (memory_operand (inner
, mode
)
2813 && GET_CODE (XEXP (inner
, 0)) != PRE_INC
2814 && GET_CODE (XEXP (inner
, 0)) != PRE_DEC
2815 && (GET_CODE (XEXP (inner
, 0)) != PLUS
2816 || GET_CODE (XEXP (XEXP (inner
, 0), 1)) != CONST_INT
2817 || INTVAL (XEXP (XEXP (inner
, 0), 1)) % 4 == 0));
2820 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2823 symbol_ref_operand (rtx op
, enum machine_mode mode
)
2825 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
2828 return (GET_CODE (op
) == SYMBOL_REF
2829 && (DEFAULT_ABI
!= ABI_AIX
|| SYMBOL_REF_FUNCTION_P (op
)));
2832 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2833 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2836 call_operand (rtx op
, enum machine_mode mode
)
2838 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
2841 return (GET_CODE (op
) == SYMBOL_REF
2842 || (GET_CODE (op
) == REG
2843 && (REGNO (op
) == LINK_REGISTER_REGNUM
2844 || REGNO (op
) == COUNT_REGISTER_REGNUM
2845 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
2848 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2852 current_file_function_operand (rtx op
,
2853 enum machine_mode mode ATTRIBUTE_UNUSED
)
2855 return (GET_CODE (op
) == SYMBOL_REF
2856 && (DEFAULT_ABI
!= ABI_AIX
|| SYMBOL_REF_FUNCTION_P (op
))
2857 && (SYMBOL_REF_LOCAL_P (op
)
2858 || (op
== XEXP (DECL_RTL (current_function_decl
), 0))));
2861 /* Return 1 if this operand is a valid input for a move insn. */
2864 input_operand (rtx op
, enum machine_mode mode
)
2866 /* Memory is always valid. */
2867 if (memory_operand (op
, mode
))
2870 /* For floating-point, easy constants are valid. */
2871 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
2873 && easy_fp_constant (op
, mode
))
2876 /* Allow any integer constant. */
2877 if (GET_MODE_CLASS (mode
) == MODE_INT
2878 && (GET_CODE (op
) == CONST_INT
2879 || GET_CODE (op
) == CONST_DOUBLE
))
2882 /* Allow easy vector constants. */
2883 if (GET_CODE (op
) == CONST_VECTOR
2884 && easy_vector_constant (op
, mode
))
2887 /* For floating-point or multi-word mode, the only remaining valid type
2889 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
2890 || GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
2891 return register_operand (op
, mode
);
2893 /* The only cases left are integral modes one word or smaller (we
2894 do not get called for MODE_CC values). These can be in any
2896 if (register_operand (op
, mode
))
2899 /* A SYMBOL_REF referring to the TOC is valid. */
2900 if (legitimate_constant_pool_address_p (op
))
2903 /* A constant pool expression (relative to the TOC) is valid */
2904 if (toc_relative_expr_p (op
))
2907 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
2909 if (DEFAULT_ABI
== ABI_V4
2910 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
)
2911 && small_data_operand (op
, Pmode
))
2918 /* Darwin, AIX increases natural record alignment to doubleword if the first
2919 field is an FP double while the FP fields remain word aligned. */
2922 rs6000_special_round_type_align (tree type
, int computed
, int specified
)
2924 tree field
= TYPE_FIELDS (type
);
2926 /* Skip all the static variables only if ABI is greater than
2928 while (field
!= NULL
&& TREE_CODE (field
) == VAR_DECL
)
2929 field
= TREE_CHAIN (field
);
2931 if (field
== NULL
|| field
== type
|| DECL_MODE (field
) != DFmode
)
2932 return MAX (computed
, specified
);
2934 return MAX (MAX (computed
, specified
), 64);
2937 /* Return 1 for an operand in small memory on V.4/eabi. */
2940 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
2941 enum machine_mode mode ATTRIBUTE_UNUSED
)
2946 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
2949 if (DEFAULT_ABI
!= ABI_V4
)
2952 if (GET_CODE (op
) == SYMBOL_REF
)
2955 else if (GET_CODE (op
) != CONST
2956 || GET_CODE (XEXP (op
, 0)) != PLUS
2957 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
2958 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
2963 rtx sum
= XEXP (op
, 0);
2964 HOST_WIDE_INT summand
;
2966 /* We have to be careful here, because it is the referenced address
2967 that must be 32k from _SDA_BASE_, not just the symbol. */
2968 summand
= INTVAL (XEXP (sum
, 1));
2969 if (summand
< 0 || (unsigned HOST_WIDE_INT
) summand
> g_switch_value
)
2972 sym_ref
= XEXP (sum
, 0);
2975 return SYMBOL_REF_SMALL_P (sym_ref
);
2981 /* Return true, if operand is a memory operand and has a
2982 displacement divisible by 4. */
2985 word_offset_memref_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2990 if (!memory_operand (op
, mode
))
2993 addr
= XEXP (op
, 0);
2994 if (GET_CODE (addr
) == PLUS
2995 && GET_CODE (XEXP (addr
, 0)) == REG
2996 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
2997 off
= INTVAL (XEXP (addr
, 1));
2999 return (off
% 4) == 0;
3002 /* Return true if either operand is a general purpose register. */
3005 gpr_or_gpr_p (rtx op0
, rtx op1
)
3007 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
3008 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
3012 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3015 constant_pool_expr_1 (rtx op
, int *have_sym
, int *have_toc
)
3017 switch (GET_CODE(op
))
3020 if (RS6000_SYMBOL_REF_TLS_P (op
))
3022 else if (CONSTANT_POOL_ADDRESS_P (op
))
3024 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op
), Pmode
))
3032 else if (! strcmp (XSTR (op
, 0), toc_label_name
))
3041 return (constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
)
3042 && constant_pool_expr_1 (XEXP (op
, 1), have_sym
, have_toc
));
3044 return constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
);
3053 constant_pool_expr_p (rtx op
)
3057 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_sym
;
3061 toc_relative_expr_p (rtx op
)
3065 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_toc
;
3069 legitimate_constant_pool_address_p (rtx x
)
3072 && GET_CODE (x
) == PLUS
3073 && GET_CODE (XEXP (x
, 0)) == REG
3074 && (TARGET_MINIMAL_TOC
|| REGNO (XEXP (x
, 0)) == TOC_REGISTER
)
3075 && constant_pool_expr_p (XEXP (x
, 1)));
3079 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
3081 return (DEFAULT_ABI
== ABI_V4
3082 && !flag_pic
&& !TARGET_TOC
3083 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
3084 && small_data_operand (x
, mode
));
3087 /* SPE offset addressing is limited to 5-bits worth of double words. */
3088 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3091 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
3093 unsigned HOST_WIDE_INT offset
, extra
;
3095 if (GET_CODE (x
) != PLUS
)
3097 if (GET_CODE (XEXP (x
, 0)) != REG
)
3099 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3101 if (legitimate_constant_pool_address_p (x
))
3103 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3106 offset
= INTVAL (XEXP (x
, 1));
3114 /* AltiVec vector modes. Only reg+reg addressing is valid here,
3115 which leaves the only valid constant offset of zero, which by
3116 canonicalization rules is also invalid. */
3123 /* SPE vector modes. */
3124 return SPE_CONST_OFFSET_OK (offset
);
3128 if (mode
== DFmode
|| !TARGET_POWERPC64
)
3130 else if (offset
& 3)
3136 if (mode
== TFmode
|| !TARGET_POWERPC64
)
3138 else if (offset
& 3)
3149 return (offset
< 0x10000) && (offset
+ extra
< 0x10000);
3153 legitimate_indexed_address_p (rtx x
, int strict
)
3157 if (GET_CODE (x
) != PLUS
)
3162 if (!REG_P (op0
) || !REG_P (op1
))
3165 return ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
3166 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
3167 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
3168 && INT_REG_OK_FOR_INDEX_P (op0
, strict
)));
3172 legitimate_indirect_address_p (rtx x
, int strict
)
3174 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
3178 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
3180 if (!TARGET_MACHO
|| !flag_pic
3181 || mode
!= SImode
|| GET_CODE(x
) != MEM
)
3185 if (GET_CODE (x
) != LO_SUM
)
3187 if (GET_CODE (XEXP (x
, 0)) != REG
)
3189 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
3193 return CONSTANT_P (x
);
3197 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
3199 if (GET_CODE (x
) != LO_SUM
)
3201 if (GET_CODE (XEXP (x
, 0)) != REG
)
3203 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3207 if (TARGET_ELF
|| TARGET_MACHO
)
3209 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
3213 if (GET_MODE_NUNITS (mode
) != 1)
3215 if (GET_MODE_BITSIZE (mode
) > 64)
3218 return CONSTANT_P (x
);
3225 /* Try machine-dependent ways of modifying an illegitimate address
3226 to be legitimate. If we find one, return the new, valid address.
3227 This is used from only one place: `memory_address' in explow.c.
3229 OLDX is the address as it was before break_out_memory_refs was
3230 called. In some cases it is useful to look at this to decide what
3233 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3235 It is always safe for this function to do nothing. It exists to
3236 recognize opportunities to optimize the output.
3238 On RS/6000, first check for the sum of a register with a constant
3239 integer that is out of range. If so, generate code to add the
3240 constant with the low-order 16 bits masked to the register and force
3241 this result into another register (this can be done with `cau').
3242 Then generate an address of REG+(CONST&0xffff), allowing for the
3243 possibility of bit 16 being a one.
3245 Then check for the sum of a register and something not constant, try to
3246 load the other things into a register and return the sum. */
3249 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3250 enum machine_mode mode
)
3252 if (GET_CODE (x
) == SYMBOL_REF
)
3254 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3256 return rs6000_legitimize_tls_address (x
, model
);
3259 if (GET_CODE (x
) == PLUS
3260 && GET_CODE (XEXP (x
, 0)) == REG
3261 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3262 && (unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000) >= 0x10000)
3264 HOST_WIDE_INT high_int
, low_int
;
3266 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3267 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
3268 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3269 GEN_INT (high_int
)), 0);
3270 return gen_rtx_PLUS (Pmode
, sum
, GEN_INT (low_int
));
3272 else if (GET_CODE (x
) == PLUS
3273 && GET_CODE (XEXP (x
, 0)) == REG
3274 && GET_CODE (XEXP (x
, 1)) != CONST_INT
3275 && GET_MODE_NUNITS (mode
) == 1
3276 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3278 || (mode
!= DFmode
&& mode
!= TFmode
))
3279 && (TARGET_POWERPC64
|| mode
!= DImode
)
3282 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3283 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
3285 else if (ALTIVEC_VECTOR_MODE (mode
))
3289 /* Make sure both operands are registers. */
3290 if (GET_CODE (x
) == PLUS
)
3291 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
3292 force_reg (Pmode
, XEXP (x
, 1)));
3294 reg
= force_reg (Pmode
, x
);
3297 else if (SPE_VECTOR_MODE (mode
))
3299 /* We accept [reg + reg] and [reg + OFFSET]. */
3301 if (GET_CODE (x
) == PLUS
)
3303 rtx op1
= XEXP (x
, 0);
3304 rtx op2
= XEXP (x
, 1);
3306 op1
= force_reg (Pmode
, op1
);
3308 if (GET_CODE (op2
) != REG
3309 && (GET_CODE (op2
) != CONST_INT
3310 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))))
3311 op2
= force_reg (Pmode
, op2
);
3313 return gen_rtx_PLUS (Pmode
, op1
, op2
);
3316 return force_reg (Pmode
, x
);
3322 && GET_CODE (x
) != CONST_INT
3323 && GET_CODE (x
) != CONST_DOUBLE
3325 && GET_MODE_NUNITS (mode
) == 1
3326 && (GET_MODE_BITSIZE (mode
) <= 32
3327 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) && mode
== DFmode
)))
3329 rtx reg
= gen_reg_rtx (Pmode
);
3330 emit_insn (gen_elf_high (reg
, x
));
3331 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3333 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
3336 && ! MACHO_DYNAMIC_NO_PIC_P
3338 && GET_CODE (x
) != CONST_INT
3339 && GET_CODE (x
) != CONST_DOUBLE
3341 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) || mode
!= DFmode
)
3345 rtx reg
= gen_reg_rtx (Pmode
);
3346 emit_insn (gen_macho_high (reg
, x
));
3347 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3350 && constant_pool_expr_p (x
)
3351 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
3353 return create_TOC_reference (x
);
3359 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3360 We need to emit DTP-relative relocations. */
3363 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3368 fputs ("\t.long\t", file
);
3371 fputs (DOUBLE_INT_ASM_OP
, file
);
3376 output_addr_const (file
, x
);
3377 fputs ("@dtprel+0x8000", file
);
3380 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3382 static GTY(()) rtx rs6000_tls_symbol
;
3384 rs6000_tls_get_addr (void)
3386 if (!rs6000_tls_symbol
)
3387 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3389 return rs6000_tls_symbol
;
3392 /* Construct the SYMBOL_REF for TLS GOT references. */
3394 static GTY(()) rtx rs6000_got_symbol
;
3396 rs6000_got_sym (void)
3398 if (!rs6000_got_symbol
)
3400 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3401 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
3402 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
3405 return rs6000_got_symbol
;
3408 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3409 this (thread-local) address. */
3412 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
3416 dest
= gen_reg_rtx (Pmode
);
3417 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
3423 tlsreg
= gen_rtx_REG (Pmode
, 13);
3424 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
3428 tlsreg
= gen_rtx_REG (Pmode
, 2);
3429 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
3433 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
3437 tmp
= gen_reg_rtx (Pmode
);
3440 tlsreg
= gen_rtx_REG (Pmode
, 13);
3441 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
3445 tlsreg
= gen_rtx_REG (Pmode
, 2);
3446 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
3450 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
3452 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
3457 rtx r3
, got
, tga
, tmp1
, tmp2
, eqv
;
3460 got
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
3464 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
3467 rtx gsym
= rs6000_got_sym ();
3468 got
= gen_reg_rtx (Pmode
);
3470 rs6000_emit_move (got
, gsym
, Pmode
);
3474 static int tls_got_labelno
= 0;
3475 rtx tempLR
, lab
, tmp3
, mem
;
3478 ASM_GENERATE_INTERNAL_LABEL (buf
, "LTLS", tls_got_labelno
++);
3479 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
3480 tempLR
= gen_reg_rtx (Pmode
);
3481 tmp1
= gen_reg_rtx (Pmode
);
3482 tmp2
= gen_reg_rtx (Pmode
);
3483 tmp3
= gen_reg_rtx (Pmode
);
3484 mem
= gen_const_mem (Pmode
, tmp1
);
3486 first
= emit_insn (gen_load_toc_v4_PIC_1b (tempLR
, lab
,
3488 emit_move_insn (tmp1
, tempLR
);
3489 emit_move_insn (tmp2
, mem
);
3490 emit_insn (gen_addsi3 (tmp3
, tmp1
, tmp2
));
3491 last
= emit_move_insn (got
, tmp3
);
3492 REG_NOTES (last
) = gen_rtx_EXPR_LIST (REG_EQUAL
, gsym
,
3494 REG_NOTES (first
) = gen_rtx_INSN_LIST (REG_LIBCALL
, last
,
3496 REG_NOTES (last
) = gen_rtx_INSN_LIST (REG_RETVAL
, first
,
3502 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
3504 r3
= gen_rtx_REG (Pmode
, 3);
3506 insn
= gen_tls_gd_64 (r3
, got
, addr
);
3508 insn
= gen_tls_gd_32 (r3
, got
, addr
);
3511 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3512 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3513 insn
= emit_call_insn (insn
);
3514 CONST_OR_PURE_CALL_P (insn
) = 1;
3515 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3516 insn
= get_insns ();
3518 emit_libcall_block (insn
, dest
, r3
, addr
);
3520 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
3522 r3
= gen_rtx_REG (Pmode
, 3);
3524 insn
= gen_tls_ld_64 (r3
, got
);
3526 insn
= gen_tls_ld_32 (r3
, got
);
3529 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3530 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3531 insn
= emit_call_insn (insn
);
3532 CONST_OR_PURE_CALL_P (insn
) = 1;
3533 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3534 insn
= get_insns ();
3536 tmp1
= gen_reg_rtx (Pmode
);
3537 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3539 emit_libcall_block (insn
, tmp1
, r3
, eqv
);
3540 if (rs6000_tls_size
== 16)
3543 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
3545 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
3547 else if (rs6000_tls_size
== 32)
3549 tmp2
= gen_reg_rtx (Pmode
);
3551 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
3553 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
3556 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
3558 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
3562 tmp2
= gen_reg_rtx (Pmode
);
3564 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
3566 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
3568 insn
= gen_rtx_SET (Pmode
, dest
,
3569 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
3575 /* IE, or 64 bit offset LE. */
3576 tmp2
= gen_reg_rtx (Pmode
);
3578 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
3580 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
3583 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
3585 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
3593 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3594 instruction definitions. */
3597 rs6000_tls_symbol_ref (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3599 return RS6000_SYMBOL_REF_TLS_P (x
);
3602 /* Return 1 if X contains a thread-local symbol. */
3605 rs6000_tls_referenced_p (rtx x
)
3607 if (! TARGET_HAVE_TLS
)
3610 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
3613 /* Return 1 if *X is a thread-local symbol. This is the same as
3614 rs6000_tls_symbol_ref except for the type of the unused argument. */
3617 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
3619 return RS6000_SYMBOL_REF_TLS_P (*x
);
3622 /* The convention appears to be to define this wherever it is used.
3623 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3624 is now used here. */
3625 #ifndef REG_MODE_OK_FOR_BASE_P
3626 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3629 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3630 replace the input X, or the original X if no replacement is called for.
3631 The output parameter *WIN is 1 if the calling macro should goto WIN,
3634 For RS/6000, we wish to handle large displacements off a base
3635 register by splitting the addend across an addiu/addis and the mem insn.
3636 This cuts number of extra insns needed from 3 to 1.
3638 On Darwin, we use this to generate code for floating point constants.
3639 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3640 The Darwin code is inside #if TARGET_MACHO because only then is
3641 machopic_function_base_name() defined. */
3643 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3644 int opnum
, int type
, int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3646 /* We must recognize output that we have already generated ourselves. */
3647 if (GET_CODE (x
) == PLUS
3648 && GET_CODE (XEXP (x
, 0)) == PLUS
3649 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
3650 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3651 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3653 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3654 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3655 opnum
, (enum reload_type
)type
);
3661 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
3662 && GET_CODE (x
) == LO_SUM
3663 && GET_CODE (XEXP (x
, 0)) == PLUS
3664 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
3665 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
3666 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 0)) == CONST
3667 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
3668 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == MINUS
3669 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 0)) == SYMBOL_REF
3670 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == SYMBOL_REF
)
3672 /* Result of previous invocation of this function on Darwin
3673 floating point constant. */
3674 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3675 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3676 opnum
, (enum reload_type
)type
);
3681 if (GET_CODE (x
) == PLUS
3682 && GET_CODE (XEXP (x
, 0)) == REG
3683 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
3684 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
3685 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3686 && !SPE_VECTOR_MODE (mode
)
3687 && !ALTIVEC_VECTOR_MODE (mode
))
3689 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
3690 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
3692 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3694 /* Check for 32-bit overflow. */
3695 if (high
+ low
!= val
)
3701 /* Reload the high part into a base reg; leave the low part
3702 in the mem directly. */
3704 x
= gen_rtx_PLUS (GET_MODE (x
),
3705 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
3709 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3710 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3711 opnum
, (enum reload_type
)type
);
3716 if (GET_CODE (x
) == SYMBOL_REF
3717 && DEFAULT_ABI
== ABI_DARWIN
3718 && !ALTIVEC_VECTOR_MODE (mode
)
3719 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
3720 /* Don't do this for TFmode, since the result isn't offsettable. */
3725 rtx offset
= gen_rtx_CONST (Pmode
,
3726 gen_rtx_MINUS (Pmode
, x
,
3727 machopic_function_base_sym ()));
3728 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3729 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3730 gen_rtx_HIGH (Pmode
, offset
)), offset
);
3733 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3734 gen_rtx_HIGH (Pmode
, x
), x
);
3736 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3737 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3738 opnum
, (enum reload_type
)type
);
3744 && constant_pool_expr_p (x
)
3745 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
3747 (x
) = create_TOC_reference (x
);
3755 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3756 that is a valid memory address for an instruction.
3757 The MODE argument is the machine mode for the MEM expression
3758 that wants to use this address.
3760 On the RS/6000, there are four valid address: a SYMBOL_REF that
3761 refers to a constant pool entry of an address (or the sum of it
3762 plus a constant), a short (16-bit signed) constant plus a register,
3763 the sum of two registers, or a register indirect, possibly with an
3764 auto-increment. For DFmode and DImode with a constant plus register,
3765 we must ensure that both words are addressable or PowerPC64 with offset
3768 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3769 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3770 adjacent memory cells are accessed by adding word-sized offsets
3771 during assembly output. */
3773 rs6000_legitimate_address (enum machine_mode mode
, rtx x
, int reg_ok_strict
)
3775 if (RS6000_SYMBOL_REF_TLS_P (x
))
3777 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
3779 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
3780 && !ALTIVEC_VECTOR_MODE (mode
)
3781 && !SPE_VECTOR_MODE (mode
)
3783 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
3785 if (legitimate_small_data_p (mode
, x
))
3787 if (legitimate_constant_pool_address_p (x
))
3789 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3791 && GET_CODE (x
) == PLUS
3792 && GET_CODE (XEXP (x
, 0)) == REG
3793 && (XEXP (x
, 0) == virtual_stack_vars_rtx
3794 || XEXP (x
, 0) == arg_pointer_rtx
)
3795 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3797 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
3801 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3803 || (mode
!= DFmode
&& mode
!= TFmode
))
3804 && (TARGET_POWERPC64
|| mode
!= DImode
)
3805 && legitimate_indexed_address_p (x
, reg_ok_strict
))
3807 if (legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
3812 /* Go to LABEL if ADDR (a legitimate address expression)
3813 has an effect that depends on the machine mode it is used for.
3815 On the RS/6000 this is true of all integral offsets (since AltiVec
3816 modes don't allow them) or is a pre-increment or decrement.
3818 ??? Except that due to conceptual problems in offsettable_address_p
3819 we can't really report the problems of integral offsets. So leave
3820 this assuming that the adjustable offset must be valid for the
3821 sub-words of a TFmode operand, which is what we had before. */
3824 rs6000_mode_dependent_address (rtx addr
)
3826 switch (GET_CODE (addr
))
3829 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3831 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
3832 return val
+ 12 + 0x8000 >= 0x10000;
3841 return TARGET_UPDATE
;
3850 /* Return number of consecutive hard regs needed starting at reg REGNO
3851 to hold something of mode MODE.
3852 This is ordinarily the length in words of a value of mode MODE
3853 but can be less for certain modes in special long registers.
3855 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3856 scalar instructions. The upper 32 bits are only available to the
3859 POWER and PowerPC GPRs hold 32 bits worth;
3860 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3863 rs6000_hard_regno_nregs (int regno
, enum machine_mode mode
)
3865 if (FP_REGNO_P (regno
))
3866 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
3868 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
3869 return (GET_MODE_SIZE (mode
) + UNITS_PER_SPE_WORD
- 1) / UNITS_PER_SPE_WORD
;
3871 if (ALTIVEC_REGNO_P (regno
))
3873 (GET_MODE_SIZE (mode
) + UNITS_PER_ALTIVEC_WORD
- 1) / UNITS_PER_ALTIVEC_WORD
;
3875 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3878 /* Change register usage conditional on target flags. */
3880 rs6000_conditional_register_usage (void)
3884 /* Set MQ register fixed (already call_used) if not POWER
3885 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3890 /* 64-bit AIX reserves GPR13 for thread-private data. */
3892 fixed_regs
[13] = call_used_regs
[13]
3893 = call_really_used_regs
[13] = 1;
3895 /* Conditionally disable FPRs. */
3896 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
3897 for (i
= 32; i
< 64; i
++)
3898 fixed_regs
[i
] = call_used_regs
[i
]
3899 = call_really_used_regs
[i
] = 1;
3901 if (DEFAULT_ABI
== ABI_V4
3902 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
3904 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3906 if (DEFAULT_ABI
== ABI_V4
3907 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
3909 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3910 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3911 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3913 if (DEFAULT_ABI
== ABI_DARWIN
3914 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
3915 global_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3916 = fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3917 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3918 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3920 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
3921 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3922 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3925 global_regs
[VSCR_REGNO
] = 1;
3929 global_regs
[SPEFSCR_REGNO
] = 1;
3930 fixed_regs
[FIXED_SCRATCH
]
3931 = call_used_regs
[FIXED_SCRATCH
]
3932 = call_really_used_regs
[FIXED_SCRATCH
] = 1;
3935 if (! TARGET_ALTIVEC
)
3937 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
3938 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
3939 call_really_used_regs
[VRSAVE_REGNO
] = 1;
3942 if (TARGET_ALTIVEC_ABI
)
3943 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
3944 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
3947 /* Try to output insns to set TARGET equal to the constant C if it can
3948 be done in less than N insns. Do all computations in MODE.
3949 Returns the place where the output has been placed if it can be
3950 done and the insns have been emitted. If it would take more than N
3951 insns, zero is returned and no insns and emitted. */
3954 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
3955 rtx source
, int n ATTRIBUTE_UNUSED
)
3957 rtx result
, insn
, set
;
3958 HOST_WIDE_INT c0
, c1
;
3960 if (mode
== QImode
|| mode
== HImode
)
3963 dest
= gen_reg_rtx (mode
);
3964 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
3967 else if (mode
== SImode
)
3969 result
= no_new_pseudos
? dest
: gen_reg_rtx (SImode
);
3971 emit_insn (gen_rtx_SET (VOIDmode
, result
,
3972 GEN_INT (INTVAL (source
)
3973 & (~ (HOST_WIDE_INT
) 0xffff))));
3974 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
3975 gen_rtx_IOR (SImode
, result
,
3976 GEN_INT (INTVAL (source
) & 0xffff))));
3979 else if (mode
== DImode
)
3981 if (GET_CODE (source
) == CONST_INT
)
3983 c0
= INTVAL (source
);
3986 else if (GET_CODE (source
) == CONST_DOUBLE
)
3988 #if HOST_BITS_PER_WIDE_INT >= 64
3989 c0
= CONST_DOUBLE_LOW (source
);
3992 c0
= CONST_DOUBLE_LOW (source
);
3993 c1
= CONST_DOUBLE_HIGH (source
);
3999 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
4004 insn
= get_last_insn ();
4005 set
= single_set (insn
);
4006 if (! CONSTANT_P (SET_SRC (set
)))
4007 set_unique_reg_note (insn
, REG_EQUAL
, source
);
4012 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4013 fall back to a straight forward decomposition. We do this to avoid
4014 exponential run times encountered when looking for longer sequences
4015 with rs6000_emit_set_const. */
4017 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
4019 if (!TARGET_POWERPC64
)
4021 rtx operand1
, operand2
;
4023 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
4025 operand2
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
4027 emit_move_insn (operand1
, GEN_INT (c1
));
4028 emit_move_insn (operand2
, GEN_INT (c2
));
4032 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
4035 ud2
= (c1
& 0xffff0000) >> 16;
4036 #if HOST_BITS_PER_WIDE_INT >= 64
4040 ud4
= (c2
& 0xffff0000) >> 16;
4042 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
4043 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
4046 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
4048 emit_move_insn (dest
, GEN_INT (ud1
));
4051 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
4052 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
4055 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
4058 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
4060 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
4062 else if ((ud4
== 0xffff && (ud3
& 0x8000))
4063 || (ud4
== 0 && ! (ud3
& 0x8000)))
4066 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
4069 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
4072 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud2
)));
4073 emit_move_insn (dest
, gen_rtx_ASHIFT (DImode
, dest
, GEN_INT (16)));
4075 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
4080 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
4083 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
4086 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud3
)));
4088 emit_move_insn (dest
, gen_rtx_ASHIFT (DImode
, dest
, GEN_INT (32)));
4090 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
,
4091 GEN_INT (ud2
<< 16)));
4093 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
4099 /* Helper for the following. Get rid of [r+r] memory refs
4100 in cases where it won't work (TImode, TFmode). */
4103 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
4105 if (GET_CODE (operands
[0]) == MEM
4106 && GET_CODE (XEXP (operands
[0], 0)) != REG
4107 && ! reload_in_progress
)
4109 = replace_equiv_address (operands
[0],
4110 copy_addr_to_reg (XEXP (operands
[0], 0)));
4112 if (GET_CODE (operands
[1]) == MEM
4113 && GET_CODE (XEXP (operands
[1], 0)) != REG
4114 && ! reload_in_progress
)
4116 = replace_equiv_address (operands
[1],
4117 copy_addr_to_reg (XEXP (operands
[1], 0)));
4120 /* Emit a move from SOURCE to DEST in mode MODE. */
4122 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
4126 operands
[1] = source
;
4128 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4129 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4130 && ! FLOAT_MODE_P (mode
)
4131 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4133 /* FIXME. This should never happen. */
4134 /* Since it seems that it does, do the safe thing and convert
4136 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
4138 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4139 && ! FLOAT_MODE_P (mode
)
4140 && ((CONST_DOUBLE_HIGH (operands
[1]) == 0
4141 && CONST_DOUBLE_LOW (operands
[1]) >= 0)
4142 || (CONST_DOUBLE_HIGH (operands
[1]) == -1
4143 && CONST_DOUBLE_LOW (operands
[1]) < 0)))
4146 /* Check if GCC is setting up a block move that will end up using FP
4147 registers as temporaries. We must make sure this is acceptable. */
4148 if (GET_CODE (operands
[0]) == MEM
4149 && GET_CODE (operands
[1]) == MEM
4151 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
4152 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
4153 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
4154 ? 32 : MEM_ALIGN (operands
[0])))
4155 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
4157 : MEM_ALIGN (operands
[1]))))
4158 && ! MEM_VOLATILE_P (operands
[0])
4159 && ! MEM_VOLATILE_P (operands
[1]))
4161 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
4162 adjust_address (operands
[1], SImode
, 0));
4163 emit_move_insn (adjust_address (operands
[0], SImode
, 4),
4164 adjust_address (operands
[1], SImode
, 4));
4168 if (!no_new_pseudos
)
4170 if (GET_CODE (operands
[1]) == MEM
&& optimize
> 0
4171 && (mode
== QImode
|| mode
== HImode
|| mode
== SImode
)
4172 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (word_mode
))
4174 rtx reg
= gen_reg_rtx (word_mode
);
4176 emit_insn (gen_rtx_SET (word_mode
, reg
,
4177 gen_rtx_ZERO_EXTEND (word_mode
,
4179 operands
[1] = gen_lowpart (mode
, reg
);
4181 if (GET_CODE (operands
[0]) != REG
)
4182 operands
[1] = force_reg (mode
, operands
[1]);
4185 if (mode
== SFmode
&& ! TARGET_POWERPC
4186 && TARGET_HARD_FLOAT
&& TARGET_FPRS
4187 && GET_CODE (operands
[0]) == MEM
)
4191 if (reload_in_progress
|| reload_completed
)
4192 regnum
= true_regnum (operands
[1]);
4193 else if (GET_CODE (operands
[1]) == REG
)
4194 regnum
= REGNO (operands
[1]);
4198 /* If operands[1] is a register, on POWER it may have
4199 double-precision data in it, so truncate it to single
4201 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
4204 newreg
= (no_new_pseudos
? operands
[1] : gen_reg_rtx (mode
));
4205 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
4206 operands
[1] = newreg
;
4210 /* Recognize the case where operand[1] is a reference to thread-local
4211 data and load its address to a register. */
4212 if (GET_CODE (operands
[1]) == SYMBOL_REF
)
4214 enum tls_model model
= SYMBOL_REF_TLS_MODEL (operands
[1]);
4216 operands
[1] = rs6000_legitimize_tls_address (operands
[1], model
);
4219 /* Handle the case where reload calls us with an invalid address. */
4220 if (reload_in_progress
&& mode
== Pmode
4221 && (! general_operand (operands
[1], mode
)
4222 || ! nonimmediate_operand (operands
[0], mode
)))
4225 /* 128-bit constant floating-point values on Darwin should really be
4226 loaded as two parts. */
4227 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
)
4228 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
4229 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
4231 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4232 know how to get a DFmode SUBREG of a TFmode. */
4233 rs6000_emit_move (simplify_gen_subreg (DImode
, operands
[0], mode
, 0),
4234 simplify_gen_subreg (DImode
, operands
[1], mode
, 0),
4236 rs6000_emit_move (simplify_gen_subreg (DImode
, operands
[0], mode
,
4237 GET_MODE_SIZE (DImode
)),
4238 simplify_gen_subreg (DImode
, operands
[1], mode
,
4239 GET_MODE_SIZE (DImode
)),
4244 /* FIXME: In the long term, this switch statement should go away
4245 and be replaced by a sequence of tests based on things like
4251 if (CONSTANT_P (operands
[1])
4252 && GET_CODE (operands
[1]) != CONST_INT
)
4253 operands
[1] = force_const_mem (mode
, operands
[1]);
4257 rs6000_eliminate_indexed_memrefs (operands
);
4262 if (CONSTANT_P (operands
[1])
4263 && ! easy_fp_constant (operands
[1], mode
))
4264 operands
[1] = force_const_mem (mode
, operands
[1]);
4275 if (CONSTANT_P (operands
[1])
4276 && !easy_vector_constant (operands
[1], mode
))
4277 operands
[1] = force_const_mem (mode
, operands
[1]);
4282 /* Use default pattern for address of ELF small data */
4285 && DEFAULT_ABI
== ABI_V4
4286 && (GET_CODE (operands
[1]) == SYMBOL_REF
4287 || GET_CODE (operands
[1]) == CONST
)
4288 && small_data_operand (operands
[1], mode
))
4290 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4294 if (DEFAULT_ABI
== ABI_V4
4295 && mode
== Pmode
&& mode
== SImode
4296 && flag_pic
== 1 && got_operand (operands
[1], mode
))
4298 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
4302 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
4306 && CONSTANT_P (operands
[1])
4307 && GET_CODE (operands
[1]) != HIGH
4308 && GET_CODE (operands
[1]) != CONST_INT
)
4310 rtx target
= (no_new_pseudos
? operands
[0] : gen_reg_rtx (mode
));
4312 /* If this is a function address on -mcall-aixdesc,
4313 convert it to the address of the descriptor. */
4314 if (DEFAULT_ABI
== ABI_AIX
4315 && GET_CODE (operands
[1]) == SYMBOL_REF
4316 && XSTR (operands
[1], 0)[0] == '.')
4318 const char *name
= XSTR (operands
[1], 0);
4320 while (*name
== '.')
4322 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
4323 CONSTANT_POOL_ADDRESS_P (new_ref
)
4324 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
4325 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
4326 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
4327 SYMBOL_REF_DECL (new_ref
) = SYMBOL_REF_DECL (operands
[1]);
4328 operands
[1] = new_ref
;
4331 if (DEFAULT_ABI
== ABI_DARWIN
)
4334 if (MACHO_DYNAMIC_NO_PIC_P
)
4336 /* Take care of any required data indirection. */
4337 operands
[1] = rs6000_machopic_legitimize_pic_address (
4338 operands
[1], mode
, operands
[0]);
4339 if (operands
[0] != operands
[1])
4340 emit_insn (gen_rtx_SET (VOIDmode
,
4341 operands
[0], operands
[1]));
4347 emit_insn (gen_macho_high_di (target
, operands
[1]));
4348 emit_insn (gen_macho_low_di (operands
[0], target
, operands
[1]));
4352 emit_insn (gen_macho_high (target
, operands
[1]));
4353 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
4358 emit_insn (gen_elf_high (target
, operands
[1]));
4359 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
4363 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4364 and we have put it in the TOC, we just need to make a TOC-relative
4367 && GET_CODE (operands
[1]) == SYMBOL_REF
4368 && constant_pool_expr_p (operands
[1])
4369 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
4370 get_pool_mode (operands
[1])))
4372 operands
[1] = create_TOC_reference (operands
[1]);
4374 else if (mode
== Pmode
4375 && CONSTANT_P (operands
[1])
4376 && ((GET_CODE (operands
[1]) != CONST_INT
4377 && ! easy_fp_constant (operands
[1], mode
))
4378 || (GET_CODE (operands
[1]) == CONST_INT
4379 && num_insns_constant (operands
[1], mode
) > 2)
4380 || (GET_CODE (operands
[0]) == REG
4381 && FP_REGNO_P (REGNO (operands
[0]))))
4382 && GET_CODE (operands
[1]) != HIGH
4383 && ! legitimate_constant_pool_address_p (operands
[1])
4384 && ! toc_relative_expr_p (operands
[1]))
4386 /* Emit a USE operation so that the constant isn't deleted if
4387 expensive optimizations are turned on because nobody
4388 references it. This should only be done for operands that
4389 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4390 This should not be done for operands that contain LABEL_REFs.
4391 For now, we just handle the obvious case. */
4392 if (GET_CODE (operands
[1]) != LABEL_REF
)
4393 emit_insn (gen_rtx_USE (VOIDmode
, operands
[1]));
4396 /* Darwin uses a special PIC legitimizer. */
4397 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
4400 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
4402 if (operands
[0] != operands
[1])
4403 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4408 /* If we are to limit the number of things we put in the TOC and
4409 this is a symbol plus a constant we can add in one insn,
4410 just put the symbol in the TOC and add the constant. Don't do
4411 this if reload is in progress. */
4412 if (GET_CODE (operands
[1]) == CONST
4413 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
4414 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
4415 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
4416 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
4417 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
4418 && ! side_effects_p (operands
[0]))
4421 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
4422 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
4424 sym
= force_reg (mode
, sym
);
4426 emit_insn (gen_addsi3 (operands
[0], sym
, other
));
4428 emit_insn (gen_adddi3 (operands
[0], sym
, other
));
4432 operands
[1] = force_const_mem (mode
, operands
[1]);
4435 && constant_pool_expr_p (XEXP (operands
[1], 0))
4436 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4437 get_pool_constant (XEXP (operands
[1], 0)),
4438 get_pool_mode (XEXP (operands
[1], 0))))
4441 = gen_const_mem (mode
,
4442 create_TOC_reference (XEXP (operands
[1], 0)));
4443 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
4449 rs6000_eliminate_indexed_memrefs (operands
);
4453 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4455 gen_rtx_SET (VOIDmode
,
4456 operands
[0], operands
[1]),
4457 gen_rtx_CLOBBER (VOIDmode
,
4458 gen_rtx_SCRATCH (SImode
)))));
4467 /* Above, we may have called force_const_mem which may have returned
4468 an invalid address. If we can, fix this up; otherwise, reload will
4469 have to deal with it. */
4470 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
4471 operands
[1] = validize_mem (operands
[1]);
4474 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4477 /* Nonzero if we can use a floating-point register to pass this arg. */
4478 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4479 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4480 && (CUM)->fregno <= FP_ARG_MAX_REG \
4481 && TARGET_HARD_FLOAT && TARGET_FPRS)
4483 /* Nonzero if we can use an AltiVec register to pass this arg. */
4484 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4485 (ALTIVEC_VECTOR_MODE (MODE) \
4486 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4487 && TARGET_ALTIVEC_ABI \
4490 /* Return a nonzero value to say to return the function value in
4491 memory, just as large structures are always returned. TYPE will be
4492 the data type of the value, and FNTYPE will be the type of the
4493 function doing the returning, or @code{NULL} for libcalls.
4495 The AIX ABI for the RS/6000 specifies that all structures are
4496 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4497 specifies that structures <= 8 bytes are returned in r3/r4, but a
4498 draft put them in memory, and GCC used to implement the draft
4499 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
4500 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4501 compatibility can change DRAFT_V4_STRUCT_RET to override the
4502 default, and -m switches get the final word. See
4503 rs6000_override_options for more details.
4505 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4506 long double support is enabled. These values are returned in memory.
4508 int_size_in_bytes returns -1 for variable size objects, which go in
4509 memory always. The cast to unsigned makes -1 > 8. */
4512 rs6000_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
4514 if (AGGREGATE_TYPE_P (type
)
4515 && (TARGET_AIX_STRUCT_RET
4516 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
4518 if (DEFAULT_ABI
== ABI_V4
&& TYPE_MODE (type
) == TFmode
)
4523 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4524 for a call to a function whose data type is FNTYPE.
4525 For a library call, FNTYPE is 0.
4527 For incoming args we set the number of arguments in the prototype large
4528 so we never return a PARALLEL. */
4531 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
4532 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
4533 int libcall
, int n_named_args
)
4535 static CUMULATIVE_ARGS zero_cumulative
;
4537 *cum
= zero_cumulative
;
4539 cum
->fregno
= FP_ARG_MIN_REG
;
4540 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
4541 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
4542 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
4543 ? CALL_LIBCALL
: CALL_NORMAL
);
4544 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
4545 cum
->stdarg
= fntype
4546 && (TYPE_ARG_TYPES (fntype
) != 0
4547 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
4548 != void_type_node
));
4550 cum
->nargs_prototype
= 0;
4551 if (incoming
|| cum
->prototype
)
4552 cum
->nargs_prototype
= n_named_args
;
4554 /* Check for a longcall attribute. */
4556 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
4557 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
)))
4558 cum
->call_cookie
= CALL_LONG
;
4560 if (TARGET_DEBUG_ARG
)
4562 fprintf (stderr
, "\ninit_cumulative_args:");
4565 tree ret_type
= TREE_TYPE (fntype
);
4566 fprintf (stderr
, " ret code = %s,",
4567 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
4570 if (cum
->call_cookie
& CALL_LONG
)
4571 fprintf (stderr
, " longcall,");
4573 fprintf (stderr
, " proto = %d, nargs = %d\n",
4574 cum
->prototype
, cum
->nargs_prototype
);
4579 && TARGET_ALTIVEC_ABI
4580 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
4582 error ("Cannot return value in vector register because"
4583 " altivec instructions are disabled, use -maltivec"
4584 " to enable them.");
4588 /* Return true if TYPE must be passed on the stack and not in registers. */
4591 rs6000_must_pass_in_stack (enum machine_mode mode
, tree type
)
4593 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
4594 return must_pass_in_stack_var_size (mode
, type
);
4596 return must_pass_in_stack_var_size_or_pad (mode
, type
);
4599 /* If defined, a C expression which determines whether, and in which
4600 direction, to pad out an argument with extra space. The value
4601 should be of type `enum direction': either `upward' to pad above
4602 the argument, `downward' to pad below, or `none' to inhibit
4605 For the AIX ABI structs are always stored left shifted in their
4609 function_arg_padding (enum machine_mode mode
, tree type
)
4611 #ifndef AGGREGATE_PADDING_FIXED
4612 #define AGGREGATE_PADDING_FIXED 0
4614 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4615 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4618 if (!AGGREGATE_PADDING_FIXED
)
4620 /* GCC used to pass structures of the same size as integer types as
4621 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4622 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4623 passed padded downward, except that -mstrict-align further
4624 muddied the water in that multi-component structures of 2 and 4
4625 bytes in size were passed padded upward.
4627 The following arranges for best compatibility with previous
4628 versions of gcc, but removes the -mstrict-align dependency. */
4629 if (BYTES_BIG_ENDIAN
)
4631 HOST_WIDE_INT size
= 0;
4633 if (mode
== BLKmode
)
4635 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
4636 size
= int_size_in_bytes (type
);
4639 size
= GET_MODE_SIZE (mode
);
4641 if (size
== 1 || size
== 2 || size
== 4)
4647 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
4649 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
4653 /* Fall back to the default. */
4654 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
4657 /* If defined, a C expression that gives the alignment boundary, in bits,
4658 of an argument with the specified mode and type. If it is not defined,
4659 PARM_BOUNDARY is used for all arguments.
4661 V.4 wants long longs to be double word aligned. */
4664 function_arg_boundary (enum machine_mode mode
, tree type ATTRIBUTE_UNUSED
)
4666 if (DEFAULT_ABI
== ABI_V4
&& GET_MODE_SIZE (mode
) == 8)
4668 else if (SPE_VECTOR_MODE (mode
))
4670 else if (ALTIVEC_VECTOR_MODE (mode
))
4673 return PARM_BOUNDARY
;
4676 /* Compute the size (in words) of a function argument. */
4678 static unsigned long
4679 rs6000_arg_size (enum machine_mode mode
, tree type
)
4683 if (mode
!= BLKmode
)
4684 size
= GET_MODE_SIZE (mode
);
4686 size
= int_size_in_bytes (type
);
4689 return (size
+ 3) >> 2;
4691 return (size
+ 7) >> 3;
4694 /* Update the data in CUM to advance over an argument
4695 of mode MODE and data type TYPE.
4696 (TYPE is null for libcalls where that information may not be available.)
4698 Note that for args passed by reference, function_arg will be called
4699 with MODE and TYPE set to that of the pointer to the arg, not the arg
4703 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4704 tree type
, int named
)
4706 cum
->nargs_prototype
--;
4708 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
4712 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
4715 if (!TARGET_ALTIVEC
)
4716 error ("Cannot pass argument in vector register because"
4717 " altivec instructions are disabled, use -maltivec"
4718 " to enable them.");
4720 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4721 even if it is going to be passed in a vector register.
4722 Darwin does the same for variable-argument functions. */
4723 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
4724 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
4734 /* Vector parameters must be 16-byte aligned. This places
4735 them at 2 mod 4 in terms of words in 32-bit mode, since
4736 the parameter save area starts at offset 24 from the
4737 stack. In 64-bit mode, they just have to start on an
4738 even word, since the parameter save area is 16-byte
4739 aligned. Space for GPRs is reserved even if the argument
4740 will be passed in memory. */
4742 align
= (2 - cum
->words
) & 3;
4744 align
= cum
->words
& 1;
4745 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
4747 if (TARGET_DEBUG_ARG
)
4749 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
4751 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
4752 cum
->nargs_prototype
, cum
->prototype
,
4753 GET_MODE_NAME (mode
));
4757 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
4759 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
4761 else if (DEFAULT_ABI
== ABI_V4
)
4763 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
4764 && (mode
== SFmode
|| mode
== DFmode
))
4766 if (cum
->fregno
<= FP_ARG_V4_MAX_REG
)
4771 cum
->words
+= cum
->words
& 1;
4772 cum
->words
+= rs6000_arg_size (mode
, type
);
4777 int n_words
= rs6000_arg_size (mode
, type
);
4778 int gregno
= cum
->sysv_gregno
;
4780 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4781 (r7,r8) or (r9,r10). As does any other 2 word item such
4782 as complex int due to a historical mistake. */
4784 gregno
+= (1 - gregno
) & 1;
4786 /* Multi-reg args are not split between registers and stack. */
4787 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
4789 /* Long long and SPE vectors are aligned on the stack.
4790 So are other 2 word items such as complex int due to
4791 a historical mistake. */
4793 cum
->words
+= cum
->words
& 1;
4794 cum
->words
+= n_words
;
4797 /* Note: continuing to accumulate gregno past when we've started
4798 spilling to the stack indicates the fact that we've started
4799 spilling to the stack to expand_builtin_saveregs. */
4800 cum
->sysv_gregno
= gregno
+ n_words
;
4803 if (TARGET_DEBUG_ARG
)
4805 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
4806 cum
->words
, cum
->fregno
);
4807 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
4808 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
4809 fprintf (stderr
, "mode = %4s, named = %d\n",
4810 GET_MODE_NAME (mode
), named
);
4815 int n_words
= rs6000_arg_size (mode
, type
);
4816 int align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
4818 /* The simple alignment calculation here works because
4819 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
4820 If we ever want to handle alignments larger than 8 bytes for
4821 32-bit or 16 bytes for 64-bit, then we'll need to take into
4822 account the offset to the start of the parm save area. */
4823 align
&= cum
->words
;
4824 cum
->words
+= align
+ n_words
;
4826 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4827 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4828 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
4830 if (TARGET_DEBUG_ARG
)
4832 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
4833 cum
->words
, cum
->fregno
);
4834 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
4835 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
4836 fprintf (stderr
, "named = %d, align = %d\n", named
, align
);
4841 /* Determine where to put a SIMD argument on the SPE. */
4844 rs6000_spe_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4849 int gregno
= cum
->sysv_gregno
;
4850 int n_words
= rs6000_arg_size (mode
, type
);
4852 /* SPE vectors are put in odd registers. */
4853 if (n_words
== 2 && (gregno
& 1) == 0)
4856 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
4859 enum machine_mode m
= SImode
;
4861 r1
= gen_rtx_REG (m
, gregno
);
4862 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
4863 r2
= gen_rtx_REG (m
, gregno
+ 1);
4864 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
4865 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
4872 if (cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
4873 return gen_rtx_REG (mode
, cum
->sysv_gregno
);
4879 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4882 rs6000_mixed_function_arg (enum machine_mode mode
, tree type
, int align_words
)
4886 rtx rvec
[GP_ARG_NUM_REG
+ 1];
4888 if (align_words
>= GP_ARG_NUM_REG
)
4891 n_units
= rs6000_arg_size (mode
, type
);
4893 /* Optimize the simple case where the arg fits in one gpr, except in
4894 the case of BLKmode due to assign_parms assuming that registers are
4895 BITS_PER_WORD wide. */
4897 || (n_units
== 1 && mode
!= BLKmode
))
4898 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
4901 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
4902 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4903 using a magic NULL_RTX component.
4904 FIXME: This is not strictly correct. Only some of the arg
4905 belongs in memory, not all of it. However, there isn't any way
4906 to do this currently, apart from building rtx descriptions for
4907 the pieces of memory we want stored. Due to bugs in the generic
4908 code we can't use the normal function_arg_partial_nregs scheme
4909 with the PARALLEL arg description we emit here.
4910 In any case, the code to store the whole arg to memory is often
4911 more efficient than code to store pieces, and we know that space
4912 is available in the right place for the whole arg. */
4913 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4918 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
4919 rtx off
= GEN_INT (i
++ * 4);
4920 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
4922 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
4924 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
4927 /* Determine where to put an argument to a function.
4928 Value is zero to push the argument on the stack,
4929 or a hard register in which to store the argument.
4931 MODE is the argument's machine mode.
4932 TYPE is the data type of the argument (as a tree).
4933 This is null for libcalls where that information may
4935 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4936 the preceding args and about the function being called.
4937 NAMED is nonzero if this argument is a named parameter
4938 (otherwise it is an extra parameter matching an ellipsis).
4940 On RS/6000 the first eight words of non-FP are normally in registers
4941 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4942 Under V.4, the first 8 FP args are in registers.
4944 If this is floating-point and no prototype is specified, we use
4945 both an FP and integer register (or possibly FP reg and stack). Library
4946 functions (when CALL_LIBCALL is set) always have the proper types for args,
4947 so we can pass the FP value just in one register. emit_library_function
4948 doesn't support PARALLEL anyway.
4950 Note that for args passed by reference, function_arg will be called
4951 with MODE and TYPE set to that of the pointer to the arg, not the arg
4955 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4956 tree type
, int named
)
4958 enum rs6000_abi abi
= DEFAULT_ABI
;
4960 /* Return a marker to indicate whether CR1 needs to set or clear the
4961 bit that V.4 uses to say fp args were passed in registers.
4962 Assume that we don't need the marker for software floating point,
4963 or compiler generated library calls. */
4964 if (mode
== VOIDmode
)
4967 && cum
->nargs_prototype
< 0
4968 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
4969 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))
4971 /* For the SPE, we need to crxor CR6 always. */
4973 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
4974 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4975 return GEN_INT (cum
->call_cookie
4976 | ((cum
->fregno
== FP_ARG_MIN_REG
)
4977 ? CALL_V4_SET_FP_ARGS
4978 : CALL_V4_CLEAR_FP_ARGS
));
4981 return GEN_INT (cum
->call_cookie
);
4984 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
4985 if (TARGET_64BIT
&& ! cum
->prototype
)
4987 /* Vector parameters get passed in vector register
4988 and also in GPRs or memory, in absence of prototype. */
4991 align_words
= (cum
->words
+ 1) & ~1;
4993 if (align_words
>= GP_ARG_NUM_REG
)
4999 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5001 return gen_rtx_PARALLEL (mode
,
5003 gen_rtx_EXPR_LIST (VOIDmode
,
5005 gen_rtx_EXPR_LIST (VOIDmode
,
5006 gen_rtx_REG (mode
, cum
->vregno
),
5010 return gen_rtx_REG (mode
, cum
->vregno
);
5011 else if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
5013 if (named
|| abi
== ABI_V4
)
5017 /* Vector parameters to varargs functions under AIX or Darwin
5018 get passed in memory and possibly also in GPRs. */
5019 int align
, align_words
, n_words
;
5020 enum machine_mode part_mode
;
5022 /* Vector parameters must be 16-byte aligned. This places them at
5023 2 mod 4 in terms of words in 32-bit mode, since the parameter
5024 save area starts at offset 24 from the stack. In 64-bit mode,
5025 they just have to start on an even word, since the parameter
5026 save area is 16-byte aligned. */
5028 align
= (2 - cum
->words
) & 3;
5030 align
= cum
->words
& 1;
5031 align_words
= cum
->words
+ align
;
5033 /* Out of registers? Memory, then. */
5034 if (align_words
>= GP_ARG_NUM_REG
)
5037 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5038 return rs6000_mixed_function_arg (mode
, type
, align_words
);
5040 /* The vector value goes in GPRs. Only the part of the
5041 value in GPRs is reported here. */
5043 n_words
= rs6000_arg_size (mode
, type
);
5044 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
5045 /* Fortunately, there are only two possibilities, the value
5046 is either wholly in GPRs or half in GPRs and half not. */
5049 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
5052 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
5053 return rs6000_spe_function_arg (cum
, mode
, type
);
5054 else if (abi
== ABI_V4
)
5056 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5057 && (mode
== SFmode
|| mode
== DFmode
))
5059 if (cum
->fregno
<= FP_ARG_V4_MAX_REG
)
5060 return gen_rtx_REG (mode
, cum
->fregno
);
5066 int n_words
= rs6000_arg_size (mode
, type
);
5067 int gregno
= cum
->sysv_gregno
;
5069 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5070 (r7,r8) or (r9,r10). As does any other 2 word item such
5071 as complex int due to a historical mistake. */
5073 gregno
+= (1 - gregno
) & 1;
5075 /* Multi-reg args are not split between registers and stack. */
5076 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5079 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5080 return rs6000_mixed_function_arg (mode
, type
,
5081 gregno
- GP_ARG_MIN_REG
);
5082 return gen_rtx_REG (mode
, gregno
);
5087 int align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5088 int align_words
= cum
->words
+ (cum
->words
& align
);
5090 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
5092 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5096 enum machine_mode fmode
= mode
;
5097 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
5099 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
5101 /* Currently, we only ever need one reg here because complex
5102 doubles are split. */
5103 if (cum
->fregno
!= FP_ARG_MAX_REG
|| fmode
!= TFmode
)
5106 /* Long double split over regs and memory. */
5110 /* Do we also need to pass this arg in the parameter save
5113 && (cum
->nargs_prototype
<= 0
5114 || (DEFAULT_ABI
== ABI_AIX
5116 && align_words
>= GP_ARG_NUM_REG
)));
5118 if (!needs_psave
&& mode
== fmode
)
5119 return gen_rtx_REG (fmode
, cum
->fregno
);
5124 /* Describe the part that goes in gprs or the stack.
5125 This piece must come first, before the fprs. */
5126 if (align_words
< GP_ARG_NUM_REG
)
5128 unsigned long n_words
= rs6000_arg_size (mode
, type
);
5130 if (align_words
+ n_words
> GP_ARG_NUM_REG
5131 || (TARGET_32BIT
&& TARGET_POWERPC64
))
5133 /* If this is partially on the stack, then we only
5134 include the portion actually in registers here. */
5135 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
5138 if (align_words
+ n_words
> GP_ARG_NUM_REG
5139 && (TARGET_32BIT
&& TARGET_POWERPC64
))
5140 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5141 using a magic NULL_RTX component. Also see comment in
5142 rs6000_mixed_function_arg for why the normal
5143 function_arg_partial_nregs scheme doesn't work in this case. */
5144 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5147 r
= gen_rtx_REG (rmode
,
5148 GP_ARG_MIN_REG
+ align_words
);
5149 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
5150 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
5152 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
5156 /* The whole arg fits in gprs. */
5157 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5158 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
5162 /* It's entirely in memory. */
5163 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5166 /* Describe where this piece goes in the fprs. */
5167 r
= gen_rtx_REG (fmode
, cum
->fregno
);
5168 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
5170 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5172 else if (align_words
< GP_ARG_NUM_REG
)
5174 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5175 return rs6000_mixed_function_arg (mode
, type
, align_words
);
5177 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5184 /* For an arg passed partly in registers and partly in memory, this is
5185 the number of registers used. For args passed entirely in registers
5186 or entirely in memory, zero. When an arg is described by a PARALLEL,
5187 perhaps using more than one register type, this function returns the
5188 number of registers used by the first element of the PARALLEL. */
5191 function_arg_partial_nregs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5192 tree type
, int named
)
5199 if (DEFAULT_ABI
== ABI_V4
)
5202 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
5203 && cum
->nargs_prototype
>= 0)
5206 align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5207 parm_offset
= TARGET_32BIT
? 2 : 0;
5208 align_words
= cum
->words
+ ((parm_offset
- cum
->words
) & align
);
5210 if (USE_FP_FOR_ARG_P (cum
, mode
, type
)
5211 /* If we are passing this arg in gprs as well, then this function
5212 should return the number of gprs (or memory) partially passed,
5213 *not* the number of fprs. */
5215 && (cum
->nargs_prototype
<= 0
5216 || (DEFAULT_ABI
== ABI_AIX
5218 && align_words
>= GP_ARG_NUM_REG
))))
5220 if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3) > FP_ARG_MAX_REG
+ 1)
5221 ret
= FP_ARG_MAX_REG
+ 1 - cum
->fregno
;
5222 else if (cum
->nargs_prototype
>= 0)
5226 if (align_words
< GP_ARG_NUM_REG
5227 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
5228 ret
= GP_ARG_NUM_REG
- align_words
;
5230 if (ret
!= 0 && TARGET_DEBUG_ARG
)
5231 fprintf (stderr
, "function_arg_partial_nregs: %d\n", ret
);
5236 /* A C expression that indicates when an argument must be passed by
5237 reference. If nonzero for an argument, a copy of that argument is
5238 made in memory and a pointer to the argument is passed instead of
5239 the argument itself. The pointer is passed in whatever way is
5240 appropriate for passing a pointer to that type.
5242 Under V.4, aggregates and long double are passed by reference.
5244 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5245 reference unless the AltiVec vector extension ABI is in force.
5247 As an extension to all ABIs, variable sized types are passed by
5251 rs6000_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5252 enum machine_mode mode ATTRIBUTE_UNUSED
,
5253 tree type
, bool named ATTRIBUTE_UNUSED
)
5255 if ((DEFAULT_ABI
== ABI_V4
5256 && ((type
&& AGGREGATE_TYPE_P (type
))
5258 || (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
5259 || (type
&& int_size_in_bytes (type
) < 0))
5261 if (TARGET_DEBUG_ARG
)
5262 fprintf (stderr
, "function_arg_pass_by_reference\n");
5270 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
5273 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
5278 for (i
= 0; i
< nregs
; i
++)
5280 rtx tem
= adjust_address_nv (x
, reg_mode
, i
*GET_MODE_SIZE(reg_mode
));
5281 if (reload_completed
)
5283 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
5286 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
5287 i
* GET_MODE_SIZE(reg_mode
));
5290 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
5292 if (tem
== NULL_RTX
)
5295 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
5300 /* Perform any needed actions needed for a function that is receiving a
5301 variable number of arguments.
5305 MODE and TYPE are the mode and type of the current parameter.
5307 PRETEND_SIZE is a variable that should be set to the amount of stack
5308 that must be pushed by the prolog to pretend that our caller pushed
5311 Normally, this macro will push all remaining incoming registers on the
5312 stack and set PRETEND_SIZE to the length of the registers pushed. */
5315 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5316 tree type
, int *pretend_size ATTRIBUTE_UNUSED
, int no_rtl
)
5318 CUMULATIVE_ARGS next_cum
;
5319 int reg_size
= TARGET_32BIT
? 4 : 8;
5320 rtx save_area
= NULL_RTX
, mem
;
5321 int first_reg_offset
, set
;
5323 /* Skip the last named argument. */
5325 function_arg_advance (&next_cum
, mode
, type
, 1);
5327 if (DEFAULT_ABI
== ABI_V4
)
5330 save_area
= plus_constant (virtual_stack_vars_rtx
,
5331 - RS6000_VARARGS_SIZE
);
5333 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
5337 first_reg_offset
= next_cum
.words
;
5338 save_area
= virtual_incoming_args_rtx
;
5340 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5341 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
5344 set
= get_varargs_alias_set ();
5345 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
)
5347 mem
= gen_rtx_MEM (BLKmode
,
5348 plus_constant (save_area
,
5349 first_reg_offset
* reg_size
)),
5350 set_mem_alias_set (mem
, set
);
5351 set_mem_align (mem
, BITS_PER_WORD
);
5353 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
5354 GP_ARG_NUM_REG
- first_reg_offset
);
5357 /* Save FP registers if needed. */
5358 if (DEFAULT_ABI
== ABI_V4
5359 && TARGET_HARD_FLOAT
&& TARGET_FPRS
5361 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
)
5363 int fregno
= next_cum
.fregno
;
5364 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
5365 rtx lab
= gen_label_rtx ();
5366 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
) * 8);
5368 emit_jump_insn (gen_rtx_SET (VOIDmode
,
5370 gen_rtx_IF_THEN_ELSE (VOIDmode
,
5371 gen_rtx_NE (VOIDmode
, cr1
,
5373 gen_rtx_LABEL_REF (VOIDmode
, lab
),
5376 while (fregno
<= FP_ARG_V4_MAX_REG
)
5378 mem
= gen_rtx_MEM (DFmode
, plus_constant (save_area
, off
));
5379 set_mem_alias_set (mem
, set
);
5380 emit_move_insn (mem
, gen_rtx_REG (DFmode
, fregno
));
5389 /* Create the va_list data type. */
5392 rs6000_build_builtin_va_list (void)
5394 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
5396 /* For AIX, prefer 'char *' because that's what the system
5397 header files like. */
5398 if (DEFAULT_ABI
!= ABI_V4
)
5399 return build_pointer_type (char_type_node
);
5401 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5402 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5404 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gpr"),
5405 unsigned_char_type_node
);
5406 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fpr"),
5407 unsigned_char_type_node
);
5408 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5410 f_res
= build_decl (FIELD_DECL
, get_identifier ("reserved"),
5411 short_unsigned_type_node
);
5412 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
5414 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
5417 DECL_FIELD_CONTEXT (f_gpr
) = record
;
5418 DECL_FIELD_CONTEXT (f_fpr
) = record
;
5419 DECL_FIELD_CONTEXT (f_res
) = record
;
5420 DECL_FIELD_CONTEXT (f_ovf
) = record
;
5421 DECL_FIELD_CONTEXT (f_sav
) = record
;
5423 TREE_CHAIN (record
) = type_decl
;
5424 TYPE_NAME (record
) = type_decl
;
5425 TYPE_FIELDS (record
) = f_gpr
;
5426 TREE_CHAIN (f_gpr
) = f_fpr
;
5427 TREE_CHAIN (f_fpr
) = f_res
;
5428 TREE_CHAIN (f_res
) = f_ovf
;
5429 TREE_CHAIN (f_ovf
) = f_sav
;
5431 layout_type (record
);
5433 /* The correct type is an array type of one element. */
5434 return build_array_type (record
, build_index_type (size_zero_node
));
5437 /* Implement va_start. */
5440 rs6000_va_start (tree valist
, rtx nextarg
)
5442 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
5443 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
5444 tree gpr
, fpr
, ovf
, sav
, t
;
5446 /* Only SVR4 needs something special. */
5447 if (DEFAULT_ABI
!= ABI_V4
)
5449 std_expand_builtin_va_start (valist
, nextarg
);
5453 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
5454 f_fpr
= TREE_CHAIN (f_gpr
);
5455 f_res
= TREE_CHAIN (f_fpr
);
5456 f_ovf
= TREE_CHAIN (f_res
);
5457 f_sav
= TREE_CHAIN (f_ovf
);
5459 valist
= build1 (INDIRECT_REF
, TREE_TYPE (TREE_TYPE (valist
)), valist
);
5460 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
5461 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
5462 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
5463 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
5465 /* Count number of gp and fp argument registers used. */
5466 words
= current_function_args_info
.words
;
5467 n_gpr
= current_function_args_info
.sysv_gregno
- GP_ARG_MIN_REG
;
5468 n_fpr
= current_function_args_info
.fregno
- FP_ARG_MIN_REG
;
5470 if (TARGET_DEBUG_ARG
)
5471 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
5472 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
5473 words
, n_gpr
, n_fpr
);
5475 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
5476 build_int_cst (NULL_TREE
, n_gpr
));
5477 TREE_SIDE_EFFECTS (t
) = 1;
5478 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5480 t
= build (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
5481 build_int_cst (NULL_TREE
, n_fpr
));
5482 TREE_SIDE_EFFECTS (t
) = 1;
5483 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5485 /* Find the overflow area. */
5486 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
5488 t
= build (PLUS_EXPR
, TREE_TYPE (ovf
), t
,
5489 build_int_cst (NULL_TREE
, words
* UNITS_PER_WORD
));
5490 t
= build (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
5491 TREE_SIDE_EFFECTS (t
) = 1;
5492 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5494 /* Find the register save area. */
5495 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
5496 t
= build (PLUS_EXPR
, TREE_TYPE (sav
), t
,
5497 build_int_cst (NULL_TREE
, -RS6000_VARARGS_SIZE
));
5498 t
= build (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
5499 TREE_SIDE_EFFECTS (t
) = 1;
5500 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5503 /* Implement va_arg. */
5506 rs6000_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
5508 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
5509 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
5510 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
5511 tree lab_false
, lab_over
, addr
;
5513 tree ptrtype
= build_pointer_type (type
);
5515 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
5517 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
5518 return build_fold_indirect_ref (t
);
5521 if (DEFAULT_ABI
!= ABI_V4
)
5523 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
5525 tree elem_type
= TREE_TYPE (type
);
5526 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
5527 int elem_size
= GET_MODE_SIZE (elem_mode
);
5529 if (elem_size
< UNITS_PER_WORD
)
5531 tree real_part
, imag_part
;
5532 tree post
= NULL_TREE
;
5534 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
5536 /* Copy the value into a temporary, lest the formal temporary
5537 be reused out from under us. */
5538 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
5539 append_to_statement_list (post
, pre_p
);
5541 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
5544 return build (COMPLEX_EXPR
, type
, real_part
, imag_part
);
5548 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5551 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
5552 f_fpr
= TREE_CHAIN (f_gpr
);
5553 f_res
= TREE_CHAIN (f_fpr
);
5554 f_ovf
= TREE_CHAIN (f_res
);
5555 f_sav
= TREE_CHAIN (f_ovf
);
5557 valist
= build1 (INDIRECT_REF
, TREE_TYPE (TREE_TYPE (valist
)), valist
);
5558 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
5559 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
5560 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
5561 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
5563 size
= int_size_in_bytes (type
);
5564 rsize
= (size
+ 3) / 4;
5567 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5568 && (TYPE_MODE (type
) == SFmode
|| TYPE_MODE (type
) == DFmode
))
5570 /* FP args go in FP registers, if present. */
5575 if (TYPE_MODE (type
) == DFmode
)
5580 /* Otherwise into GP registers. */
5589 /* Pull the value out of the saved registers.... */
5592 addr
= create_tmp_var (ptr_type_node
, "addr");
5593 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
5595 /* AltiVec vectors never go in registers when -mabi=altivec. */
5596 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
5600 lab_false
= create_artificial_label ();
5601 lab_over
= create_artificial_label ();
5603 /* Long long and SPE vectors are aligned in the registers.
5604 As are any other 2 gpr item such as complex int due to a
5605 historical mistake. */
5609 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), reg
,
5610 size_int (n_reg
- 1));
5611 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, u
);
5614 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
5615 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
5616 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
5617 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
5618 gimplify_and_add (t
, pre_p
);
5622 t
= build2 (PLUS_EXPR
, ptr_type_node
, sav
, size_int (sav_ofs
));
5624 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, size_int (n_reg
));
5625 u
= build1 (CONVERT_EXPR
, integer_type_node
, u
);
5626 u
= build2 (MULT_EXPR
, integer_type_node
, u
, size_int (sav_scale
));
5627 t
= build2 (PLUS_EXPR
, ptr_type_node
, t
, u
);
5629 t
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
5630 gimplify_and_add (t
, pre_p
);
5632 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
5633 gimplify_and_add (t
, pre_p
);
5635 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
5636 append_to_statement_list (t
, pre_p
);
5640 /* Ensure that we don't find any more args in regs.
5641 Alignment has taken care of the n_reg == 2 case. */
5642 t
= build (MODIFY_EXPR
, TREE_TYPE (reg
), reg
, size_int (8));
5643 gimplify_and_add (t
, pre_p
);
5647 /* ... otherwise out of the overflow area. */
5649 /* Care for on-stack alignment if needed. */
5653 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (align
- 1));
5654 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
5655 build_int_cst (NULL_TREE
, -align
));
5657 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
5659 u
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
5660 gimplify_and_add (u
, pre_p
);
5662 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
5663 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
5664 gimplify_and_add (t
, pre_p
);
5668 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
5669 append_to_statement_list (t
, pre_p
);
5672 addr
= fold_convert (ptrtype
, addr
);
5673 return build_fold_indirect_ref (addr
);
5678 #define def_builtin(MASK, NAME, TYPE, CODE) \
5680 if ((MASK) & target_flags) \
5681 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5685 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5687 static const struct builtin_description bdesc_3arg
[] =
5689 { MASK_ALTIVEC
, CODE_FOR_altivec_vmaddfp
, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP
},
5690 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhaddshs
, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS
},
5691 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhraddshs
, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS
},
5692 { MASK_ALTIVEC
, CODE_FOR_altivec_vmladduhm
, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM
},
5693 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumubm
, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM
},
5694 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsummbm
, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM
},
5695 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhm
, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM
},
5696 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshm
, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM
},
5697 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhs
, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS
},
5698 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshs
, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS
},
5699 { MASK_ALTIVEC
, CODE_FOR_altivec_vnmsubfp
, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP
},
5700 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_4sf
, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF
},
5701 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_4si
, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI
},
5702 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_8hi
, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI
},
5703 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_16qi
, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI
},
5704 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_4sf
, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF
},
5705 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_4si
, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI
},
5706 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_8hi
, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI
},
5707 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_16qi
, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI
},
5708 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_16qi
, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI
},
5709 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_8hi
, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI
},
5710 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_4si
, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI
},
5711 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_4sf
, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF
},
5714 /* DST operations: void foo (void *, const int, const char). */
5716 static const struct builtin_description bdesc_dst
[] =
5718 { MASK_ALTIVEC
, CODE_FOR_altivec_dst
, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST
},
5719 { MASK_ALTIVEC
, CODE_FOR_altivec_dstt
, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT
},
5720 { MASK_ALTIVEC
, CODE_FOR_altivec_dstst
, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST
},
5721 { MASK_ALTIVEC
, CODE_FOR_altivec_dststt
, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT
}
5724 /* Simple binary operations: VECc = foo (VECa, VECb). */
5726 static struct builtin_description bdesc_2arg
[] =
5728 { MASK_ALTIVEC
, CODE_FOR_addv16qi3
, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM
},
5729 { MASK_ALTIVEC
, CODE_FOR_addv8hi3
, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM
},
5730 { MASK_ALTIVEC
, CODE_FOR_addv4si3
, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM
},
5731 { MASK_ALTIVEC
, CODE_FOR_addv4sf3
, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP
},
5732 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddcuw
, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW
},
5733 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddubs
, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS
},
5734 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsbs
, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS
},
5735 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduhs
, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS
},
5736 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddshs
, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS
},
5737 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduws
, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS
},
5738 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsws
, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS
},
5739 { MASK_ALTIVEC
, CODE_FOR_andv4si3
, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND
},
5740 { MASK_ALTIVEC
, CODE_FOR_altivec_vandc
, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC
},
5741 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgub
, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB
},
5742 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsb
, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB
},
5743 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguh
, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH
},
5744 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsh
, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH
},
5745 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguw
, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW
},
5746 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsw
, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW
},
5747 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfux
, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX
},
5748 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfsx
, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX
},
5749 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpbfp
, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP
},
5750 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequb
, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB
},
5751 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequh
, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH
},
5752 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequw
, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW
},
5753 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpeqfp
, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP
},
5754 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgefp
, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP
},
5755 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtub
, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB
},
5756 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsb
, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB
},
5757 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuh
, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH
},
5758 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsh
, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH
},
5759 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuw
, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW
},
5760 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsw
, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW
},
5761 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtfp
, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP
},
5762 { MASK_ALTIVEC
, CODE_FOR_altivec_vctsxs
, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS
},
5763 { MASK_ALTIVEC
, CODE_FOR_altivec_vctuxs
, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS
},
5764 { MASK_ALTIVEC
, CODE_FOR_umaxv16qi3
, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB
},
5765 { MASK_ALTIVEC
, CODE_FOR_smaxv16qi3
, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB
},
5766 { MASK_ALTIVEC
, CODE_FOR_umaxv8hi3
, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH
},
5767 { MASK_ALTIVEC
, CODE_FOR_smaxv8hi3
, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH
},
5768 { MASK_ALTIVEC
, CODE_FOR_umaxv4si3
, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW
},
5769 { MASK_ALTIVEC
, CODE_FOR_smaxv4si3
, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW
},
5770 { MASK_ALTIVEC
, CODE_FOR_smaxv4sf3
, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP
},
5771 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB
},
5772 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH
},
5773 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW
},
5774 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB
},
5775 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH
},
5776 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW
},
5777 { MASK_ALTIVEC
, CODE_FOR_uminv16qi3
, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB
},
5778 { MASK_ALTIVEC
, CODE_FOR_sminv16qi3
, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB
},
5779 { MASK_ALTIVEC
, CODE_FOR_uminv8hi3
, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH
},
5780 { MASK_ALTIVEC
, CODE_FOR_sminv8hi3
, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH
},
5781 { MASK_ALTIVEC
, CODE_FOR_uminv4si3
, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW
},
5782 { MASK_ALTIVEC
, CODE_FOR_sminv4si3
, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW
},
5783 { MASK_ALTIVEC
, CODE_FOR_sminv4sf3
, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP
},
5784 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleub
, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB
},
5785 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesb
, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB
},
5786 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleuh
, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH
},
5787 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesh
, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH
},
5788 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuloub
, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB
},
5789 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosb
, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB
},
5790 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulouh
, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH
},
5791 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosh
, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH
},
5792 { MASK_ALTIVEC
, CODE_FOR_altivec_vnor
, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR
},
5793 { MASK_ALTIVEC
, CODE_FOR_iorv4si3
, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR
},
5794 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM
},
5795 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM
},
5796 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkpx
, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX
},
5797 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhss
, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS
},
5798 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshss
, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS
},
5799 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwss
, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS
},
5800 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswss
, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS
},
5801 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhus
, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS
},
5802 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshus
, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS
},
5803 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwus
, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS
},
5804 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswus
, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS
},
5805 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlb
, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB
},
5806 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlh
, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH
},
5807 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlw
, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW
},
5808 { MASK_ALTIVEC
, CODE_FOR_altivec_vslb
, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB
},
5809 { MASK_ALTIVEC
, CODE_FOR_altivec_vslh
, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH
},
5810 { MASK_ALTIVEC
, CODE_FOR_altivec_vslw
, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW
},
5811 { MASK_ALTIVEC
, CODE_FOR_altivec_vsl
, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL
},
5812 { MASK_ALTIVEC
, CODE_FOR_altivec_vslo
, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO
},
5813 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltb
, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB
},
5814 { MASK_ALTIVEC
, CODE_FOR_altivec_vsplth
, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH
},
5815 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltw
, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW
},
5816 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrb
, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB
},
5817 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrh
, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH
},
5818 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrw
, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW
},
5819 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrab
, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB
},
5820 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrah
, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH
},
5821 { MASK_ALTIVEC
, CODE_FOR_altivec_vsraw
, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW
},
5822 { MASK_ALTIVEC
, CODE_FOR_altivec_vsr
, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR
},
5823 { MASK_ALTIVEC
, CODE_FOR_altivec_vsro
, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO
},
5824 { MASK_ALTIVEC
, CODE_FOR_subv16qi3
, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM
},
5825 { MASK_ALTIVEC
, CODE_FOR_subv8hi3
, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM
},
5826 { MASK_ALTIVEC
, CODE_FOR_subv4si3
, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM
},
5827 { MASK_ALTIVEC
, CODE_FOR_subv4sf3
, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP
},
5828 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubcuw
, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW
},
5829 { MASK_ALTIVEC
, CODE_FOR_altivec_vsububs
, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS
},
5830 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsbs
, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS
},
5831 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuhs
, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS
},
5832 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubshs
, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS
},
5833 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuws
, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS
},
5834 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsws
, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS
},
5835 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4ubs
, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS
},
5836 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4sbs
, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS
},
5837 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4shs
, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS
},
5838 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum2sws
, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS
},
5839 { MASK_ALTIVEC
, CODE_FOR_altivec_vsumsws
, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS
},
5840 { MASK_ALTIVEC
, CODE_FOR_xorv4si3
, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR
},
5842 /* Place holder, leave as first spe builtin. */
5843 { 0, CODE_FOR_spe_evaddw
, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW
},
5844 { 0, CODE_FOR_spe_evand
, "__builtin_spe_evand", SPE_BUILTIN_EVAND
},
5845 { 0, CODE_FOR_spe_evandc
, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC
},
5846 { 0, CODE_FOR_spe_evdivws
, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS
},
5847 { 0, CODE_FOR_spe_evdivwu
, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU
},
5848 { 0, CODE_FOR_spe_eveqv
, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV
},
5849 { 0, CODE_FOR_spe_evfsadd
, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD
},
5850 { 0, CODE_FOR_spe_evfsdiv
, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV
},
5851 { 0, CODE_FOR_spe_evfsmul
, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL
},
5852 { 0, CODE_FOR_spe_evfssub
, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB
},
5853 { 0, CODE_FOR_spe_evmergehi
, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI
},
5854 { 0, CODE_FOR_spe_evmergehilo
, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO
},
5855 { 0, CODE_FOR_spe_evmergelo
, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO
},
5856 { 0, CODE_FOR_spe_evmergelohi
, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI
},
5857 { 0, CODE_FOR_spe_evmhegsmfaa
, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA
},
5858 { 0, CODE_FOR_spe_evmhegsmfan
, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN
},
5859 { 0, CODE_FOR_spe_evmhegsmiaa
, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA
},
5860 { 0, CODE_FOR_spe_evmhegsmian
, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN
},
5861 { 0, CODE_FOR_spe_evmhegumiaa
, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA
},
5862 { 0, CODE_FOR_spe_evmhegumian
, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN
},
5863 { 0, CODE_FOR_spe_evmhesmf
, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF
},
5864 { 0, CODE_FOR_spe_evmhesmfa
, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA
},
5865 { 0, CODE_FOR_spe_evmhesmfaaw
, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW
},
5866 { 0, CODE_FOR_spe_evmhesmfanw
, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW
},
5867 { 0, CODE_FOR_spe_evmhesmi
, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI
},
5868 { 0, CODE_FOR_spe_evmhesmia
, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA
},
5869 { 0, CODE_FOR_spe_evmhesmiaaw
, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW
},
5870 { 0, CODE_FOR_spe_evmhesmianw
, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW
},
5871 { 0, CODE_FOR_spe_evmhessf
, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF
},
5872 { 0, CODE_FOR_spe_evmhessfa
, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA
},
5873 { 0, CODE_FOR_spe_evmhessfaaw
, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW
},
5874 { 0, CODE_FOR_spe_evmhessfanw
, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW
},
5875 { 0, CODE_FOR_spe_evmhessiaaw
, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW
},
5876 { 0, CODE_FOR_spe_evmhessianw
, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW
},
5877 { 0, CODE_FOR_spe_evmheumi
, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI
},
5878 { 0, CODE_FOR_spe_evmheumia
, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA
},
5879 { 0, CODE_FOR_spe_evmheumiaaw
, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW
},
5880 { 0, CODE_FOR_spe_evmheumianw
, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW
},
5881 { 0, CODE_FOR_spe_evmheusiaaw
, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW
},
5882 { 0, CODE_FOR_spe_evmheusianw
, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW
},
5883 { 0, CODE_FOR_spe_evmhogsmfaa
, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA
},
5884 { 0, CODE_FOR_spe_evmhogsmfan
, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN
},
5885 { 0, CODE_FOR_spe_evmhogsmiaa
, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA
},
5886 { 0, CODE_FOR_spe_evmhogsmian
, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN
},
5887 { 0, CODE_FOR_spe_evmhogumiaa
, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA
},
5888 { 0, CODE_FOR_spe_evmhogumian
, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN
},
5889 { 0, CODE_FOR_spe_evmhosmf
, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF
},
5890 { 0, CODE_FOR_spe_evmhosmfa
, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA
},
5891 { 0, CODE_FOR_spe_evmhosmfaaw
, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW
},
5892 { 0, CODE_FOR_spe_evmhosmfanw
, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW
},
5893 { 0, CODE_FOR_spe_evmhosmi
, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI
},
5894 { 0, CODE_FOR_spe_evmhosmia
, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA
},
5895 { 0, CODE_FOR_spe_evmhosmiaaw
, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW
},
5896 { 0, CODE_FOR_spe_evmhosmianw
, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW
},
5897 { 0, CODE_FOR_spe_evmhossf
, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF
},
5898 { 0, CODE_FOR_spe_evmhossfa
, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA
},
5899 { 0, CODE_FOR_spe_evmhossfaaw
, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW
},
5900 { 0, CODE_FOR_spe_evmhossfanw
, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW
},
5901 { 0, CODE_FOR_spe_evmhossiaaw
, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW
},
5902 { 0, CODE_FOR_spe_evmhossianw
, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW
},
5903 { 0, CODE_FOR_spe_evmhoumi
, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI
},
5904 { 0, CODE_FOR_spe_evmhoumia
, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA
},
5905 { 0, CODE_FOR_spe_evmhoumiaaw
, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW
},
5906 { 0, CODE_FOR_spe_evmhoumianw
, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW
},
5907 { 0, CODE_FOR_spe_evmhousiaaw
, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW
},
5908 { 0, CODE_FOR_spe_evmhousianw
, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW
},
5909 { 0, CODE_FOR_spe_evmwhsmf
, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF
},
5910 { 0, CODE_FOR_spe_evmwhsmfa
, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA
},
5911 { 0, CODE_FOR_spe_evmwhsmi
, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI
},
5912 { 0, CODE_FOR_spe_evmwhsmia
, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA
},
5913 { 0, CODE_FOR_spe_evmwhssf
, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF
},
5914 { 0, CODE_FOR_spe_evmwhssfa
, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA
},
5915 { 0, CODE_FOR_spe_evmwhumi
, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI
},
5916 { 0, CODE_FOR_spe_evmwhumia
, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA
},
5917 { 0, CODE_FOR_spe_evmwlsmiaaw
, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW
},
5918 { 0, CODE_FOR_spe_evmwlsmianw
, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW
},
5919 { 0, CODE_FOR_spe_evmwlssiaaw
, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW
},
5920 { 0, CODE_FOR_spe_evmwlssianw
, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW
},
5921 { 0, CODE_FOR_spe_evmwlumi
, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI
},
5922 { 0, CODE_FOR_spe_evmwlumia
, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA
},
5923 { 0, CODE_FOR_spe_evmwlumiaaw
, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW
},
5924 { 0, CODE_FOR_spe_evmwlumianw
, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW
},
5925 { 0, CODE_FOR_spe_evmwlusiaaw
, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW
},
5926 { 0, CODE_FOR_spe_evmwlusianw
, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW
},
5927 { 0, CODE_FOR_spe_evmwsmf
, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF
},
5928 { 0, CODE_FOR_spe_evmwsmfa
, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA
},
5929 { 0, CODE_FOR_spe_evmwsmfaa
, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA
},
5930 { 0, CODE_FOR_spe_evmwsmfan
, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN
},
5931 { 0, CODE_FOR_spe_evmwsmi
, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI
},
5932 { 0, CODE_FOR_spe_evmwsmia
, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA
},
5933 { 0, CODE_FOR_spe_evmwsmiaa
, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA
},
5934 { 0, CODE_FOR_spe_evmwsmian
, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN
},
5935 { 0, CODE_FOR_spe_evmwssf
, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF
},
5936 { 0, CODE_FOR_spe_evmwssfa
, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA
},
5937 { 0, CODE_FOR_spe_evmwssfaa
, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA
},
5938 { 0, CODE_FOR_spe_evmwssfan
, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN
},
5939 { 0, CODE_FOR_spe_evmwumi
, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI
},
5940 { 0, CODE_FOR_spe_evmwumia
, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA
},
5941 { 0, CODE_FOR_spe_evmwumiaa
, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA
},
5942 { 0, CODE_FOR_spe_evmwumian
, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN
},
5943 { 0, CODE_FOR_spe_evnand
, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND
},
5944 { 0, CODE_FOR_spe_evnor
, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR
},
5945 { 0, CODE_FOR_spe_evor
, "__builtin_spe_evor", SPE_BUILTIN_EVOR
},
5946 { 0, CODE_FOR_spe_evorc
, "__builtin_spe_evorc", SPE_BUILTIN_EVORC
},
5947 { 0, CODE_FOR_spe_evrlw
, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW
},
5948 { 0, CODE_FOR_spe_evslw
, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW
},
5949 { 0, CODE_FOR_spe_evsrws
, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS
},
5950 { 0, CODE_FOR_spe_evsrwu
, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU
},
5951 { 0, CODE_FOR_spe_evsubfw
, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW
},
5953 /* SPE binary operations expecting a 5-bit unsigned literal. */
5954 { 0, CODE_FOR_spe_evaddiw
, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW
},
5956 { 0, CODE_FOR_spe_evrlwi
, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI
},
5957 { 0, CODE_FOR_spe_evslwi
, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI
},
5958 { 0, CODE_FOR_spe_evsrwis
, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS
},
5959 { 0, CODE_FOR_spe_evsrwiu
, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU
},
5960 { 0, CODE_FOR_spe_evsubifw
, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW
},
5961 { 0, CODE_FOR_spe_evmwhssfaa
, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA
},
5962 { 0, CODE_FOR_spe_evmwhssmaa
, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA
},
5963 { 0, CODE_FOR_spe_evmwhsmfaa
, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA
},
5964 { 0, CODE_FOR_spe_evmwhsmiaa
, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA
},
5965 { 0, CODE_FOR_spe_evmwhusiaa
, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA
},
5966 { 0, CODE_FOR_spe_evmwhumiaa
, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA
},
5967 { 0, CODE_FOR_spe_evmwhssfan
, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN
},
5968 { 0, CODE_FOR_spe_evmwhssian
, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN
},
5969 { 0, CODE_FOR_spe_evmwhsmfan
, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN
},
5970 { 0, CODE_FOR_spe_evmwhsmian
, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN
},
5971 { 0, CODE_FOR_spe_evmwhusian
, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN
},
5972 { 0, CODE_FOR_spe_evmwhumian
, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN
},
5973 { 0, CODE_FOR_spe_evmwhgssfaa
, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA
},
5974 { 0, CODE_FOR_spe_evmwhgsmfaa
, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA
},
5975 { 0, CODE_FOR_spe_evmwhgsmiaa
, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA
},
5976 { 0, CODE_FOR_spe_evmwhgumiaa
, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA
},
5977 { 0, CODE_FOR_spe_evmwhgssfan
, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN
},
5978 { 0, CODE_FOR_spe_evmwhgsmfan
, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN
},
5979 { 0, CODE_FOR_spe_evmwhgsmian
, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN
},
5980 { 0, CODE_FOR_spe_evmwhgumian
, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN
},
5981 { 0, CODE_FOR_spe_brinc
, "__builtin_spe_brinc", SPE_BUILTIN_BRINC
},
5983 /* Place-holder. Leave as last binary SPE builtin. */
5984 { 0, CODE_FOR_xorv2si3
, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR
},
5987 /* AltiVec predicates. */
5989 struct builtin_description_predicates
5991 const unsigned int mask
;
5992 const enum insn_code icode
;
5994 const char *const name
;
5995 const enum rs6000_builtins code
;
5998 static const struct builtin_description_predicates bdesc_altivec_preds
[] =
6000 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P
},
6001 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P
},
6002 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P
},
6003 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P
},
6004 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P
},
6005 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P
},
6006 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P
},
6007 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P
},
6008 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P
},
6009 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P
},
6010 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P
},
6011 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P
},
6012 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P
}
6015 /* SPE predicates. */
6016 static struct builtin_description bdesc_spe_predicates
[] =
6018 /* Place-holder. Leave as first. */
6019 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ
},
6020 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS
},
6021 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU
},
6022 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS
},
6023 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU
},
6024 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ
},
6025 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT
},
6026 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT
},
6027 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ
},
6028 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT
},
6029 /* Place-holder. Leave as last. */
6030 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT
},
6033 /* SPE evsel predicates. */
6034 static struct builtin_description bdesc_spe_evsel
[] =
6036 /* Place-holder. Leave as first. */
6037 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS
},
6038 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU
},
6039 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS
},
6040 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU
},
6041 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ
},
6042 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT
},
6043 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT
},
6044 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ
},
6045 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT
},
6046 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT
},
6047 /* Place-holder. Leave as last. */
6048 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ
},
6051 /* ABS* operations. */
6053 static const struct builtin_description bdesc_abs
[] =
6055 { MASK_ALTIVEC
, CODE_FOR_absv4si2
, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI
},
6056 { MASK_ALTIVEC
, CODE_FOR_absv8hi2
, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI
},
6057 { MASK_ALTIVEC
, CODE_FOR_absv4sf2
, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF
},
6058 { MASK_ALTIVEC
, CODE_FOR_absv16qi2
, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI
},
6059 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v4si
, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI
},
6060 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v8hi
, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI
},
6061 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v16qi
, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI
}
6064 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6067 static struct builtin_description bdesc_1arg
[] =
6069 { MASK_ALTIVEC
, CODE_FOR_altivec_vexptefp
, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP
},
6070 { MASK_ALTIVEC
, CODE_FOR_altivec_vlogefp
, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP
},
6071 { MASK_ALTIVEC
, CODE_FOR_altivec_vrefp
, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP
},
6072 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfim
, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM
},
6073 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfin
, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN
},
6074 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfip
, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP
},
6075 { MASK_ALTIVEC
, CODE_FOR_ftruncv4sf2
, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ
},
6076 { MASK_ALTIVEC
, CODE_FOR_altivec_vrsqrtefp
, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP
},
6077 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisb
, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB
},
6078 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltish
, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH
},
6079 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisw
, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW
},
6080 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsb
, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB
},
6081 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhpx
, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX
},
6082 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsh
, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH
},
6083 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsb
, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB
},
6084 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklpx
, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX
},
6085 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsh
, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH
},
6087 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6088 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6089 { 0, CODE_FOR_spe_evabs
, "__builtin_spe_evabs", SPE_BUILTIN_EVABS
},
6090 { 0, CODE_FOR_spe_evaddsmiaaw
, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW
},
6091 { 0, CODE_FOR_spe_evaddssiaaw
, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW
},
6092 { 0, CODE_FOR_spe_evaddumiaaw
, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW
},
6093 { 0, CODE_FOR_spe_evaddusiaaw
, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW
},
6094 { 0, CODE_FOR_spe_evcntlsw
, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW
},
6095 { 0, CODE_FOR_spe_evcntlzw
, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW
},
6096 { 0, CODE_FOR_spe_evextsb
, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB
},
6097 { 0, CODE_FOR_spe_evextsh
, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH
},
6098 { 0, CODE_FOR_spe_evfsabs
, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS
},
6099 { 0, CODE_FOR_spe_evfscfsf
, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF
},
6100 { 0, CODE_FOR_spe_evfscfsi
, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI
},
6101 { 0, CODE_FOR_spe_evfscfuf
, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF
},
6102 { 0, CODE_FOR_spe_evfscfui
, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI
},
6103 { 0, CODE_FOR_spe_evfsctsf
, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF
},
6104 { 0, CODE_FOR_spe_evfsctsi
, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI
},
6105 { 0, CODE_FOR_spe_evfsctsiz
, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ
},
6106 { 0, CODE_FOR_spe_evfsctuf
, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF
},
6107 { 0, CODE_FOR_spe_evfsctui
, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI
},
6108 { 0, CODE_FOR_spe_evfsctuiz
, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ
},
6109 { 0, CODE_FOR_spe_evfsnabs
, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS
},
6110 { 0, CODE_FOR_spe_evfsneg
, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG
},
6111 { 0, CODE_FOR_spe_evmra
, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA
},
6112 { 0, CODE_FOR_negv2si2
, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG
},
6113 { 0, CODE_FOR_spe_evrndw
, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW
},
6114 { 0, CODE_FOR_spe_evsubfsmiaaw
, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW
},
6115 { 0, CODE_FOR_spe_evsubfssiaaw
, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW
},
6116 { 0, CODE_FOR_spe_evsubfumiaaw
, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW
},
6118 /* Place-holder. Leave as last unary SPE builtin. */
6119 { 0, CODE_FOR_spe_evsubfusiaaw
, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW
},
6123 rs6000_expand_unop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6126 tree arg0
= TREE_VALUE (arglist
);
6127 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6128 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6129 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6131 if (icode
== CODE_FOR_nothing
)
6132 /* Builtin not supported on this processor. */
6135 /* If we got invalid arguments bail out before generating bad rtl. */
6136 if (arg0
== error_mark_node
)
6139 if (icode
== CODE_FOR_altivec_vspltisb
6140 || icode
== CODE_FOR_altivec_vspltish
6141 || icode
== CODE_FOR_altivec_vspltisw
6142 || icode
== CODE_FOR_spe_evsplatfi
6143 || icode
== CODE_FOR_spe_evsplati
)
6145 /* Only allow 5-bit *signed* literals. */
6146 if (GET_CODE (op0
) != CONST_INT
6147 || INTVAL (op0
) > 0x1f
6148 || INTVAL (op0
) < -0x1f)
6150 error ("argument 1 must be a 5-bit signed literal");
6156 || GET_MODE (target
) != tmode
6157 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6158 target
= gen_reg_rtx (tmode
);
6160 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6161 op0
= copy_to_mode_reg (mode0
, op0
);
6163 pat
= GEN_FCN (icode
) (target
, op0
);
6172 altivec_expand_abs_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6174 rtx pat
, scratch1
, scratch2
;
6175 tree arg0
= TREE_VALUE (arglist
);
6176 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6177 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6178 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6180 /* If we have invalid arguments, bail out before generating bad rtl. */
6181 if (arg0
== error_mark_node
)
6185 || GET_MODE (target
) != tmode
6186 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6187 target
= gen_reg_rtx (tmode
);
6189 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6190 op0
= copy_to_mode_reg (mode0
, op0
);
6192 scratch1
= gen_reg_rtx (mode0
);
6193 scratch2
= gen_reg_rtx (mode0
);
6195 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
6204 rs6000_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6207 tree arg0
= TREE_VALUE (arglist
);
6208 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6209 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6210 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6211 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6212 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6213 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6215 if (icode
== CODE_FOR_nothing
)
6216 /* Builtin not supported on this processor. */
6219 /* If we got invalid arguments bail out before generating bad rtl. */
6220 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6223 if (icode
== CODE_FOR_altivec_vcfux
6224 || icode
== CODE_FOR_altivec_vcfsx
6225 || icode
== CODE_FOR_altivec_vctsxs
6226 || icode
== CODE_FOR_altivec_vctuxs
6227 || icode
== CODE_FOR_altivec_vspltb
6228 || icode
== CODE_FOR_altivec_vsplth
6229 || icode
== CODE_FOR_altivec_vspltw
6230 || icode
== CODE_FOR_spe_evaddiw
6231 || icode
== CODE_FOR_spe_evldd
6232 || icode
== CODE_FOR_spe_evldh
6233 || icode
== CODE_FOR_spe_evldw
6234 || icode
== CODE_FOR_spe_evlhhesplat
6235 || icode
== CODE_FOR_spe_evlhhossplat
6236 || icode
== CODE_FOR_spe_evlhhousplat
6237 || icode
== CODE_FOR_spe_evlwhe
6238 || icode
== CODE_FOR_spe_evlwhos
6239 || icode
== CODE_FOR_spe_evlwhou
6240 || icode
== CODE_FOR_spe_evlwhsplat
6241 || icode
== CODE_FOR_spe_evlwwsplat
6242 || icode
== CODE_FOR_spe_evrlwi
6243 || icode
== CODE_FOR_spe_evslwi
6244 || icode
== CODE_FOR_spe_evsrwis
6245 || icode
== CODE_FOR_spe_evsubifw
6246 || icode
== CODE_FOR_spe_evsrwiu
)
6248 /* Only allow 5-bit unsigned literals. */
6250 if (TREE_CODE (arg1
) != INTEGER_CST
6251 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
6253 error ("argument 2 must be a 5-bit unsigned literal");
6259 || GET_MODE (target
) != tmode
6260 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6261 target
= gen_reg_rtx (tmode
);
6263 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6264 op0
= copy_to_mode_reg (mode0
, op0
);
6265 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6266 op1
= copy_to_mode_reg (mode1
, op1
);
6268 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
6277 altivec_expand_predicate_builtin (enum insn_code icode
, const char *opcode
,
6278 tree arglist
, rtx target
)
6281 tree cr6_form
= TREE_VALUE (arglist
);
6282 tree arg0
= TREE_VALUE (TREE_CHAIN (arglist
));
6283 tree arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6284 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6285 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6286 enum machine_mode tmode
= SImode
;
6287 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6288 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6291 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
6293 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6297 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
6302 /* If we have invalid arguments, bail out before generating bad rtl. */
6303 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6307 || GET_MODE (target
) != tmode
6308 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6309 target
= gen_reg_rtx (tmode
);
6311 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6312 op0
= copy_to_mode_reg (mode0
, op0
);
6313 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6314 op1
= copy_to_mode_reg (mode1
, op1
);
6316 scratch
= gen_reg_rtx (mode0
);
6318 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
,
6319 gen_rtx_SYMBOL_REF (Pmode
, opcode
));
6324 /* The vec_any* and vec_all* predicates use the same opcodes for two
6325 different operations, but the bits in CR6 will be different
6326 depending on what information we want. So we have to play tricks
6327 with CR6 to get the right bits out.
6329 If you think this is disgusting, look at the specs for the
6330 AltiVec predicates. */
6332 switch (cr6_form_int
)
6335 emit_insn (gen_cr6_test_for_zero (target
));
6338 emit_insn (gen_cr6_test_for_zero_reverse (target
));
6341 emit_insn (gen_cr6_test_for_lt (target
));
6344 emit_insn (gen_cr6_test_for_lt_reverse (target
));
6347 error ("argument 1 of __builtin_altivec_predicate is out of range");
6355 altivec_expand_lv_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6358 tree arg0
= TREE_VALUE (arglist
);
6359 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6360 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6361 enum machine_mode mode0
= Pmode
;
6362 enum machine_mode mode1
= Pmode
;
6363 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6364 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6366 if (icode
== CODE_FOR_nothing
)
6367 /* Builtin not supported on this processor. */
6370 /* If we got invalid arguments bail out before generating bad rtl. */
6371 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6375 || GET_MODE (target
) != tmode
6376 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6377 target
= gen_reg_rtx (tmode
);
6379 op1
= copy_to_mode_reg (mode1
, op1
);
6381 if (op0
== const0_rtx
)
6383 addr
= gen_rtx_MEM (tmode
, op1
);
6387 op0
= copy_to_mode_reg (mode0
, op0
);
6388 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
6391 pat
= GEN_FCN (icode
) (target
, addr
);
6401 spe_expand_stv_builtin (enum insn_code icode
, tree arglist
)
6403 tree arg0
= TREE_VALUE (arglist
);
6404 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6405 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6406 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6407 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6408 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6410 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
6411 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
6412 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
6414 /* Invalid arguments. Bail before doing anything stoopid! */
6415 if (arg0
== error_mark_node
6416 || arg1
== error_mark_node
6417 || arg2
== error_mark_node
)
6420 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
6421 op0
= copy_to_mode_reg (mode2
, op0
);
6422 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
6423 op1
= copy_to_mode_reg (mode0
, op1
);
6424 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
6425 op2
= copy_to_mode_reg (mode1
, op2
);
6427 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
6434 altivec_expand_stv_builtin (enum insn_code icode
, tree arglist
)
6436 tree arg0
= TREE_VALUE (arglist
);
6437 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6438 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6439 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6440 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6441 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6443 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6444 enum machine_mode mode1
= Pmode
;
6445 enum machine_mode mode2
= Pmode
;
6447 /* Invalid arguments. Bail before doing anything stoopid! */
6448 if (arg0
== error_mark_node
6449 || arg1
== error_mark_node
6450 || arg2
== error_mark_node
)
6453 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
6454 op0
= copy_to_mode_reg (tmode
, op0
);
6456 op2
= copy_to_mode_reg (mode2
, op2
);
6458 if (op1
== const0_rtx
)
6460 addr
= gen_rtx_MEM (tmode
, op2
);
6464 op1
= copy_to_mode_reg (mode1
, op1
);
6465 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
6468 pat
= GEN_FCN (icode
) (addr
, op0
);
6475 rs6000_expand_ternop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6478 tree arg0
= TREE_VALUE (arglist
);
6479 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6480 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6481 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6482 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6483 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6484 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6485 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6486 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6487 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
6489 if (icode
== CODE_FOR_nothing
)
6490 /* Builtin not supported on this processor. */
6493 /* If we got invalid arguments bail out before generating bad rtl. */
6494 if (arg0
== error_mark_node
6495 || arg1
== error_mark_node
6496 || arg2
== error_mark_node
)
6499 if (icode
== CODE_FOR_altivec_vsldoi_4sf
6500 || icode
== CODE_FOR_altivec_vsldoi_4si
6501 || icode
== CODE_FOR_altivec_vsldoi_8hi
6502 || icode
== CODE_FOR_altivec_vsldoi_16qi
)
6504 /* Only allow 4-bit unsigned literals. */
6506 if (TREE_CODE (arg2
) != INTEGER_CST
6507 || TREE_INT_CST_LOW (arg2
) & ~0xf)
6509 error ("argument 3 must be a 4-bit unsigned literal");
6515 || GET_MODE (target
) != tmode
6516 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6517 target
= gen_reg_rtx (tmode
);
6519 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6520 op0
= copy_to_mode_reg (mode0
, op0
);
6521 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6522 op1
= copy_to_mode_reg (mode1
, op1
);
6523 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
6524 op2
= copy_to_mode_reg (mode2
, op2
);
6526 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
6534 /* Expand the lvx builtins. */
6536 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
6538 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6539 tree arglist
= TREE_OPERAND (exp
, 1);
6540 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6542 enum machine_mode tmode
, mode0
;
6544 enum insn_code icode
;
6548 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
6549 icode
= CODE_FOR_altivec_lvx_16qi
;
6551 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
6552 icode
= CODE_FOR_altivec_lvx_8hi
;
6554 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
6555 icode
= CODE_FOR_altivec_lvx_4si
;
6557 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
6558 icode
= CODE_FOR_altivec_lvx_4sf
;
6567 arg0
= TREE_VALUE (arglist
);
6568 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6569 tmode
= insn_data
[icode
].operand
[0].mode
;
6570 mode0
= insn_data
[icode
].operand
[1].mode
;
6573 || GET_MODE (target
) != tmode
6574 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6575 target
= gen_reg_rtx (tmode
);
6577 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6578 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
6580 pat
= GEN_FCN (icode
) (target
, op0
);
6587 /* Expand the stvx builtins. */
6589 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
6592 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6593 tree arglist
= TREE_OPERAND (exp
, 1);
6594 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6596 enum machine_mode mode0
, mode1
;
6598 enum insn_code icode
;
6602 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
6603 icode
= CODE_FOR_altivec_stvx_16qi
;
6605 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
6606 icode
= CODE_FOR_altivec_stvx_8hi
;
6608 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
6609 icode
= CODE_FOR_altivec_stvx_4si
;
6611 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
6612 icode
= CODE_FOR_altivec_stvx_4sf
;
6619 arg0
= TREE_VALUE (arglist
);
6620 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6621 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6622 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6623 mode0
= insn_data
[icode
].operand
[0].mode
;
6624 mode1
= insn_data
[icode
].operand
[1].mode
;
6626 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
6627 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
6628 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
6629 op1
= copy_to_mode_reg (mode1
, op1
);
6631 pat
= GEN_FCN (icode
) (op0
, op1
);
6639 /* Expand the dst builtins. */
6641 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
6644 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6645 tree arglist
= TREE_OPERAND (exp
, 1);
6646 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6647 tree arg0
, arg1
, arg2
;
6648 enum machine_mode mode0
, mode1
, mode2
;
6649 rtx pat
, op0
, op1
, op2
;
6650 struct builtin_description
*d
;
6655 /* Handle DST variants. */
6656 d
= (struct builtin_description
*) bdesc_dst
;
6657 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
6658 if (d
->code
== fcode
)
6660 arg0
= TREE_VALUE (arglist
);
6661 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6662 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6663 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6664 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6665 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6666 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
6667 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
6668 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
6670 /* Invalid arguments, bail out before generating bad rtl. */
6671 if (arg0
== error_mark_node
6672 || arg1
== error_mark_node
6673 || arg2
== error_mark_node
)
6678 if (TREE_CODE (arg2
) != INTEGER_CST
6679 || TREE_INT_CST_LOW (arg2
) & ~0x3)
6681 error ("argument to `%s' must be a 2-bit unsigned literal", d
->name
);
6685 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
6686 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
6687 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
6688 op1
= copy_to_mode_reg (mode1
, op1
);
6690 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
6700 /* Expand the builtin in EXP and store the result in TARGET. Store
6701 true in *EXPANDEDP if we found a builtin to expand. */
6703 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
6705 struct builtin_description
*d
;
6706 struct builtin_description_predicates
*dp
;
6708 enum insn_code icode
;
6709 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6710 tree arglist
= TREE_OPERAND (exp
, 1);
6713 enum machine_mode tmode
, mode0
;
6714 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6716 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
6720 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
6724 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
6732 case ALTIVEC_BUILTIN_STVX
:
6733 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx
, arglist
);
6734 case ALTIVEC_BUILTIN_STVEBX
:
6735 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, arglist
);
6736 case ALTIVEC_BUILTIN_STVEHX
:
6737 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, arglist
);
6738 case ALTIVEC_BUILTIN_STVEWX
:
6739 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, arglist
);
6740 case ALTIVEC_BUILTIN_STVXL
:
6741 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, arglist
);
6743 case ALTIVEC_BUILTIN_MFVSCR
:
6744 icode
= CODE_FOR_altivec_mfvscr
;
6745 tmode
= insn_data
[icode
].operand
[0].mode
;
6748 || GET_MODE (target
) != tmode
6749 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6750 target
= gen_reg_rtx (tmode
);
6752 pat
= GEN_FCN (icode
) (target
);
6758 case ALTIVEC_BUILTIN_MTVSCR
:
6759 icode
= CODE_FOR_altivec_mtvscr
;
6760 arg0
= TREE_VALUE (arglist
);
6761 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6762 mode0
= insn_data
[icode
].operand
[0].mode
;
6764 /* If we got invalid arguments bail out before generating bad rtl. */
6765 if (arg0
== error_mark_node
)
6768 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
6769 op0
= copy_to_mode_reg (mode0
, op0
);
6771 pat
= GEN_FCN (icode
) (op0
);
6776 case ALTIVEC_BUILTIN_DSSALL
:
6777 emit_insn (gen_altivec_dssall ());
6780 case ALTIVEC_BUILTIN_DSS
:
6781 icode
= CODE_FOR_altivec_dss
;
6782 arg0
= TREE_VALUE (arglist
);
6784 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6785 mode0
= insn_data
[icode
].operand
[0].mode
;
6787 /* If we got invalid arguments bail out before generating bad rtl. */
6788 if (arg0
== error_mark_node
)
6791 if (TREE_CODE (arg0
) != INTEGER_CST
6792 || TREE_INT_CST_LOW (arg0
) & ~0x3)
6794 error ("argument to dss must be a 2-bit unsigned literal");
6798 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
6799 op0
= copy_to_mode_reg (mode0
, op0
);
6801 emit_insn (gen_altivec_dss (op0
));
6804 case ALTIVEC_BUILTIN_COMPILETIME_ERROR
:
6805 arg0
= TREE_VALUE (arglist
);
6806 while (TREE_CODE (arg0
) == NOP_EXPR
|| TREE_CODE (arg0
) == ADDR_EXPR
6807 || TREE_CODE (arg0
) == ARRAY_REF
)
6808 arg0
= TREE_OPERAND (arg0
, 0);
6809 error ("invalid parameter combination for `%s' AltiVec intrinsic",
6810 TREE_STRING_POINTER (arg0
));
6815 /* Expand abs* operations. */
6816 d
= (struct builtin_description
*) bdesc_abs
;
6817 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
6818 if (d
->code
== fcode
)
6819 return altivec_expand_abs_builtin (d
->icode
, arglist
, target
);
6821 /* Expand the AltiVec predicates. */
6822 dp
= (struct builtin_description_predicates
*) bdesc_altivec_preds
;
6823 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
6824 if (dp
->code
== fcode
)
6825 return altivec_expand_predicate_builtin (dp
->icode
, dp
->opcode
, arglist
, target
);
6827 /* LV* are funky. We initialized them differently. */
6830 case ALTIVEC_BUILTIN_LVSL
:
6831 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
6833 case ALTIVEC_BUILTIN_LVSR
:
6834 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
6836 case ALTIVEC_BUILTIN_LVEBX
:
6837 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
6839 case ALTIVEC_BUILTIN_LVEHX
:
6840 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
6842 case ALTIVEC_BUILTIN_LVEWX
:
6843 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
6845 case ALTIVEC_BUILTIN_LVXL
:
6846 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
6848 case ALTIVEC_BUILTIN_LVX
:
6849 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx
,
6860 /* Binops that need to be initialized manually, but can be expanded
6861 automagically by rs6000_expand_binop_builtin. */
6862 static struct builtin_description bdesc_2arg_spe
[] =
6864 { 0, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
6865 { 0, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
6866 { 0, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
6867 { 0, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
6868 { 0, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
6869 { 0, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
6870 { 0, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
6871 { 0, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
6872 { 0, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
6873 { 0, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
6874 { 0, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
6875 { 0, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
6876 { 0, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
6877 { 0, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
6878 { 0, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
6879 { 0, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
6880 { 0, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
6881 { 0, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
6882 { 0, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
6883 { 0, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
6884 { 0, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
6885 { 0, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
6888 /* Expand the builtin in EXP and store the result in TARGET. Store
6889 true in *EXPANDEDP if we found a builtin to expand.
6891 This expands the SPE builtins that are not simple unary and binary
6894 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
6896 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6897 tree arglist
= TREE_OPERAND (exp
, 1);
6899 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6900 enum insn_code icode
;
6901 enum machine_mode tmode
, mode0
;
6903 struct builtin_description
*d
;
6908 /* Syntax check for a 5-bit unsigned immediate. */
6911 case SPE_BUILTIN_EVSTDD
:
6912 case SPE_BUILTIN_EVSTDH
:
6913 case SPE_BUILTIN_EVSTDW
:
6914 case SPE_BUILTIN_EVSTWHE
:
6915 case SPE_BUILTIN_EVSTWHO
:
6916 case SPE_BUILTIN_EVSTWWE
:
6917 case SPE_BUILTIN_EVSTWWO
:
6918 arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6919 if (TREE_CODE (arg1
) != INTEGER_CST
6920 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
6922 error ("argument 2 must be a 5-bit unsigned literal");
6930 /* The evsplat*i instructions are not quite generic. */
6933 case SPE_BUILTIN_EVSPLATFI
:
6934 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
6936 case SPE_BUILTIN_EVSPLATI
:
6937 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
6943 d
= (struct builtin_description
*) bdesc_2arg_spe
;
6944 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
6945 if (d
->code
== fcode
)
6946 return rs6000_expand_binop_builtin (d
->icode
, arglist
, target
);
6948 d
= (struct builtin_description
*) bdesc_spe_predicates
;
6949 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
6950 if (d
->code
== fcode
)
6951 return spe_expand_predicate_builtin (d
->icode
, arglist
, target
);
6953 d
= (struct builtin_description
*) bdesc_spe_evsel
;
6954 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
6955 if (d
->code
== fcode
)
6956 return spe_expand_evsel_builtin (d
->icode
, arglist
, target
);
6960 case SPE_BUILTIN_EVSTDDX
:
6961 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, arglist
);
6962 case SPE_BUILTIN_EVSTDHX
:
6963 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, arglist
);
6964 case SPE_BUILTIN_EVSTDWX
:
6965 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, arglist
);
6966 case SPE_BUILTIN_EVSTWHEX
:
6967 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, arglist
);
6968 case SPE_BUILTIN_EVSTWHOX
:
6969 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, arglist
);
6970 case SPE_BUILTIN_EVSTWWEX
:
6971 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, arglist
);
6972 case SPE_BUILTIN_EVSTWWOX
:
6973 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, arglist
);
6974 case SPE_BUILTIN_EVSTDD
:
6975 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, arglist
);
6976 case SPE_BUILTIN_EVSTDH
:
6977 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, arglist
);
6978 case SPE_BUILTIN_EVSTDW
:
6979 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, arglist
);
6980 case SPE_BUILTIN_EVSTWHE
:
6981 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, arglist
);
6982 case SPE_BUILTIN_EVSTWHO
:
6983 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, arglist
);
6984 case SPE_BUILTIN_EVSTWWE
:
6985 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, arglist
);
6986 case SPE_BUILTIN_EVSTWWO
:
6987 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, arglist
);
6988 case SPE_BUILTIN_MFSPEFSCR
:
6989 icode
= CODE_FOR_spe_mfspefscr
;
6990 tmode
= insn_data
[icode
].operand
[0].mode
;
6993 || GET_MODE (target
) != tmode
6994 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6995 target
= gen_reg_rtx (tmode
);
6997 pat
= GEN_FCN (icode
) (target
);
7002 case SPE_BUILTIN_MTSPEFSCR
:
7003 icode
= CODE_FOR_spe_mtspefscr
;
7004 arg0
= TREE_VALUE (arglist
);
7005 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7006 mode0
= insn_data
[icode
].operand
[0].mode
;
7008 if (arg0
== error_mark_node
)
7011 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7012 op0
= copy_to_mode_reg (mode0
, op0
);
7014 pat
= GEN_FCN (icode
) (op0
);
7027 spe_expand_predicate_builtin (enum insn_code icode
, tree arglist
, rtx target
)
7029 rtx pat
, scratch
, tmp
;
7030 tree form
= TREE_VALUE (arglist
);
7031 tree arg0
= TREE_VALUE (TREE_CHAIN (arglist
));
7032 tree arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7033 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7034 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7035 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7036 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7040 if (TREE_CODE (form
) != INTEGER_CST
)
7042 error ("argument 1 of __builtin_spe_predicate must be a constant");
7046 form_int
= TREE_INT_CST_LOW (form
);
7051 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7055 || GET_MODE (target
) != SImode
7056 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
7057 target
= gen_reg_rtx (SImode
);
7059 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7060 op0
= copy_to_mode_reg (mode0
, op0
);
7061 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7062 op1
= copy_to_mode_reg (mode1
, op1
);
7064 scratch
= gen_reg_rtx (CCmode
);
7066 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
7071 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7072 _lower_. We use one compare, but look in different bits of the
7073 CR for each variant.
7075 There are 2 elements in each SPE simd type (upper/lower). The CR
7076 bits are set as follows:
7078 BIT0 | BIT 1 | BIT 2 | BIT 3
7079 U | L | (U | L) | (U & L)
7081 So, for an "all" relationship, BIT 3 would be set.
7082 For an "any" relationship, BIT 2 would be set. Etc.
7084 Following traditional nomenclature, these bits map to:
7086 BIT0 | BIT 1 | BIT 2 | BIT 3
7089 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7094 /* All variant. OV bit. */
7096 /* We need to get to the OV bit, which is the ORDERED bit. We
7097 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7098 that's ugly and will trigger a validate_condition_mode abort.
7099 So let's just use another pattern. */
7100 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
7102 /* Any variant. EQ bit. */
7106 /* Upper variant. LT bit. */
7110 /* Lower variant. GT bit. */
7115 error ("argument 1 of __builtin_spe_predicate is out of range");
7119 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
7120 emit_move_insn (target
, tmp
);
7125 /* The evsel builtins look like this:
7127 e = __builtin_spe_evsel_OP (a, b, c, d);
7131 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7132 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7136 spe_expand_evsel_builtin (enum insn_code icode
, tree arglist
, rtx target
)
7139 tree arg0
= TREE_VALUE (arglist
);
7140 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7141 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7142 tree arg3
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist
))));
7143 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7144 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7145 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
7146 rtx op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, 0);
7147 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7148 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7153 if (arg0
== error_mark_node
|| arg1
== error_mark_node
7154 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
7158 || GET_MODE (target
) != mode0
7159 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
7160 target
= gen_reg_rtx (mode0
);
7162 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7163 op0
= copy_to_mode_reg (mode0
, op0
);
7164 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
7165 op1
= copy_to_mode_reg (mode0
, op1
);
7166 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
7167 op2
= copy_to_mode_reg (mode0
, op2
);
7168 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
7169 op3
= copy_to_mode_reg (mode0
, op3
);
7171 /* Generate the compare. */
7172 scratch
= gen_reg_rtx (CCmode
);
7173 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
7178 if (mode0
== V2SImode
)
7179 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
7181 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
7186 /* Expand an expression EXP that calls a built-in function,
7187 with result going to TARGET if that's convenient
7188 (and in mode MODE if that's convenient).
7189 SUBTARGET may be used as the target for computing one of EXP's operands.
7190 IGNORE is nonzero if the value is to be ignored. */
7193 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
7194 enum machine_mode mode ATTRIBUTE_UNUSED
,
7195 int ignore ATTRIBUTE_UNUSED
)
7197 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7198 tree arglist
= TREE_OPERAND (exp
, 1);
7199 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7200 struct builtin_description
*d
;
7207 ret
= altivec_expand_builtin (exp
, target
, &success
);
7214 ret
= spe_expand_builtin (exp
, target
, &success
);
7220 if (TARGET_ALTIVEC
|| TARGET_SPE
)
7222 /* Handle simple unary operations. */
7223 d
= (struct builtin_description
*) bdesc_1arg
;
7224 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
7225 if (d
->code
== fcode
)
7226 return rs6000_expand_unop_builtin (d
->icode
, arglist
, target
);
7228 /* Handle simple binary operations. */
7229 d
= (struct builtin_description
*) bdesc_2arg
;
7230 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
7231 if (d
->code
== fcode
)
7232 return rs6000_expand_binop_builtin (d
->icode
, arglist
, target
);
7234 /* Handle simple ternary operations. */
7235 d
= (struct builtin_description
*) bdesc_3arg
;
7236 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
7237 if (d
->code
== fcode
)
7238 return rs6000_expand_ternop_builtin (d
->icode
, arglist
, target
);
7246 build_opaque_vector_type (tree node
, int nunits
)
7248 node
= copy_node (node
);
7249 TYPE_MAIN_VARIANT (node
) = node
;
7250 return build_vector_type (node
, nunits
);
7254 rs6000_init_builtins (void)
7256 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
7257 V2SF_type_node
= build_vector_type (float_type_node
, 2);
7258 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
7259 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
7260 V4SF_type_node
= build_vector_type (float_type_node
, 4);
7261 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
7262 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
7264 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
7265 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
7266 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
7268 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
7269 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
7270 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
7272 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7273 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7274 'vector unsigned short'. */
7276 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
7277 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
7278 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
7279 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
7281 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7282 get_identifier ("__bool char"),
7283 bool_char_type_node
));
7284 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7285 get_identifier ("__bool short"),
7286 bool_short_type_node
));
7287 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7288 get_identifier ("__bool int"),
7289 bool_int_type_node
));
7290 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7291 get_identifier ("__pixel"),
7294 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
7295 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
7296 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
7297 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
7299 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7300 get_identifier ("__vector unsigned char"),
7301 unsigned_V16QI_type_node
));
7302 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7303 get_identifier ("__vector signed char"),
7305 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7306 get_identifier ("__vector __bool char"),
7307 bool_V16QI_type_node
));
7309 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7310 get_identifier ("__vector unsigned short"),
7311 unsigned_V8HI_type_node
));
7312 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7313 get_identifier ("__vector signed short"),
7315 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7316 get_identifier ("__vector __bool short"),
7317 bool_V8HI_type_node
));
7319 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7320 get_identifier ("__vector unsigned int"),
7321 unsigned_V4SI_type_node
));
7322 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7323 get_identifier ("__vector signed int"),
7325 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7326 get_identifier ("__vector __bool int"),
7327 bool_V4SI_type_node
));
7329 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7330 get_identifier ("__vector float"),
7332 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7333 get_identifier ("__vector __pixel"),
7334 pixel_V8HI_type_node
));
7337 spe_init_builtins ();
7339 altivec_init_builtins ();
7340 if (TARGET_ALTIVEC
|| TARGET_SPE
)
7341 rs6000_common_init_builtins ();
7344 /* Search through a set of builtins and enable the mask bits.
7345 DESC is an array of builtins.
7346 SIZE is the total number of builtins.
7347 START is the builtin enum at which to start.
7348 END is the builtin enum at which to end. */
7350 enable_mask_for_builtins (struct builtin_description
*desc
, int size
,
7351 enum rs6000_builtins start
,
7352 enum rs6000_builtins end
)
7356 for (i
= 0; i
< size
; ++i
)
7357 if (desc
[i
].code
== start
)
7363 for (; i
< size
; ++i
)
7365 /* Flip all the bits on. */
7366 desc
[i
].mask
= target_flags
;
7367 if (desc
[i
].code
== end
)
7373 spe_init_builtins (void)
7375 tree endlink
= void_list_node
;
7376 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
7377 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
7378 struct builtin_description
*d
;
7381 tree v2si_ftype_4_v2si
7382 = build_function_type
7383 (opaque_V2SI_type_node
,
7384 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7385 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7386 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7387 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7390 tree v2sf_ftype_4_v2sf
7391 = build_function_type
7392 (opaque_V2SF_type_node
,
7393 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7394 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7395 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7396 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7399 tree int_ftype_int_v2si_v2si
7400 = build_function_type
7402 tree_cons (NULL_TREE
, integer_type_node
,
7403 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7404 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7407 tree int_ftype_int_v2sf_v2sf
7408 = build_function_type
7410 tree_cons (NULL_TREE
, integer_type_node
,
7411 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7412 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7415 tree void_ftype_v2si_puint_int
7416 = build_function_type (void_type_node
,
7417 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7418 tree_cons (NULL_TREE
, puint_type_node
,
7419 tree_cons (NULL_TREE
,
7423 tree void_ftype_v2si_puint_char
7424 = build_function_type (void_type_node
,
7425 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7426 tree_cons (NULL_TREE
, puint_type_node
,
7427 tree_cons (NULL_TREE
,
7431 tree void_ftype_v2si_pv2si_int
7432 = build_function_type (void_type_node
,
7433 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7434 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
7435 tree_cons (NULL_TREE
,
7439 tree void_ftype_v2si_pv2si_char
7440 = build_function_type (void_type_node
,
7441 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7442 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
7443 tree_cons (NULL_TREE
,
7448 = build_function_type (void_type_node
,
7449 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
7452 = build_function_type (integer_type_node
, endlink
);
7454 tree v2si_ftype_pv2si_int
7455 = build_function_type (opaque_V2SI_type_node
,
7456 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
7457 tree_cons (NULL_TREE
, integer_type_node
,
7460 tree v2si_ftype_puint_int
7461 = build_function_type (opaque_V2SI_type_node
,
7462 tree_cons (NULL_TREE
, puint_type_node
,
7463 tree_cons (NULL_TREE
, integer_type_node
,
7466 tree v2si_ftype_pushort_int
7467 = build_function_type (opaque_V2SI_type_node
,
7468 tree_cons (NULL_TREE
, pushort_type_node
,
7469 tree_cons (NULL_TREE
, integer_type_node
,
7472 tree v2si_ftype_signed_char
7473 = build_function_type (opaque_V2SI_type_node
,
7474 tree_cons (NULL_TREE
, signed_char_type_node
,
7477 /* The initialization of the simple binary and unary builtins is
7478 done in rs6000_common_init_builtins, but we have to enable the
7479 mask bits here manually because we have run out of `target_flags'
7480 bits. We really need to redesign this mask business. */
7482 enable_mask_for_builtins ((struct builtin_description
*) bdesc_2arg
,
7483 ARRAY_SIZE (bdesc_2arg
),
7486 enable_mask_for_builtins ((struct builtin_description
*) bdesc_1arg
,
7487 ARRAY_SIZE (bdesc_1arg
),
7489 SPE_BUILTIN_EVSUBFUSIAAW
);
7490 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_predicates
,
7491 ARRAY_SIZE (bdesc_spe_predicates
),
7492 SPE_BUILTIN_EVCMPEQ
,
7493 SPE_BUILTIN_EVFSTSTLT
);
7494 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_evsel
,
7495 ARRAY_SIZE (bdesc_spe_evsel
),
7496 SPE_BUILTIN_EVSEL_CMPGTS
,
7497 SPE_BUILTIN_EVSEL_FSTSTEQ
);
7499 (*lang_hooks
.decls
.pushdecl
)
7500 (build_decl (TYPE_DECL
, get_identifier ("__ev64_opaque__"),
7501 opaque_V2SI_type_node
));
7503 /* Initialize irregular SPE builtins. */
7505 def_builtin (target_flags
, "__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
7506 def_builtin (target_flags
, "__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
7507 def_builtin (target_flags
, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
7508 def_builtin (target_flags
, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
7509 def_builtin (target_flags
, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
7510 def_builtin (target_flags
, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
7511 def_builtin (target_flags
, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
7512 def_builtin (target_flags
, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
7513 def_builtin (target_flags
, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
7514 def_builtin (target_flags
, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
7515 def_builtin (target_flags
, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
7516 def_builtin (target_flags
, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
7517 def_builtin (target_flags
, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
7518 def_builtin (target_flags
, "__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
7519 def_builtin (target_flags
, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
7520 def_builtin (target_flags
, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
7521 def_builtin (target_flags
, "__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
7522 def_builtin (target_flags
, "__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
7525 def_builtin (target_flags
, "__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
7526 def_builtin (target_flags
, "__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
7527 def_builtin (target_flags
, "__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
7528 def_builtin (target_flags
, "__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
7529 def_builtin (target_flags
, "__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
7530 def_builtin (target_flags
, "__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
7531 def_builtin (target_flags
, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
7532 def_builtin (target_flags
, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
7533 def_builtin (target_flags
, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
7534 def_builtin (target_flags
, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
7535 def_builtin (target_flags
, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
7536 def_builtin (target_flags
, "__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
7537 def_builtin (target_flags
, "__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
7538 def_builtin (target_flags
, "__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
7539 def_builtin (target_flags
, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
7540 def_builtin (target_flags
, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
7541 def_builtin (target_flags
, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
7542 def_builtin (target_flags
, "__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
7543 def_builtin (target_flags
, "__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
7544 def_builtin (target_flags
, "__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
7545 def_builtin (target_flags
, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
7546 def_builtin (target_flags
, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
7549 d
= (struct builtin_description
*) bdesc_spe_predicates
;
7550 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
7554 switch (insn_data
[d
->icode
].operand
[1].mode
)
7557 type
= int_ftype_int_v2si_v2si
;
7560 type
= int_ftype_int_v2sf_v2sf
;
7566 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
7569 /* Evsel predicates. */
7570 d
= (struct builtin_description
*) bdesc_spe_evsel
;
7571 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
7575 switch (insn_data
[d
->icode
].operand
[1].mode
)
7578 type
= v2si_ftype_4_v2si
;
7581 type
= v2sf_ftype_4_v2sf
;
7587 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
7592 altivec_init_builtins (void)
7594 struct builtin_description
*d
;
7595 struct builtin_description_predicates
*dp
;
7597 tree pfloat_type_node
= build_pointer_type (float_type_node
);
7598 tree pint_type_node
= build_pointer_type (integer_type_node
);
7599 tree pshort_type_node
= build_pointer_type (short_integer_type_node
);
7600 tree pchar_type_node
= build_pointer_type (char_type_node
);
7602 tree pvoid_type_node
= build_pointer_type (void_type_node
);
7604 tree pcfloat_type_node
= build_pointer_type (build_qualified_type (float_type_node
, TYPE_QUAL_CONST
));
7605 tree pcint_type_node
= build_pointer_type (build_qualified_type (integer_type_node
, TYPE_QUAL_CONST
));
7606 tree pcshort_type_node
= build_pointer_type (build_qualified_type (short_integer_type_node
, TYPE_QUAL_CONST
));
7607 tree pcchar_type_node
= build_pointer_type (build_qualified_type (char_type_node
, TYPE_QUAL_CONST
));
7609 tree pcvoid_type_node
= build_pointer_type (build_qualified_type (void_type_node
, TYPE_QUAL_CONST
));
7611 tree int_ftype_int_v4si_v4si
7612 = build_function_type_list (integer_type_node
,
7613 integer_type_node
, V4SI_type_node
,
7614 V4SI_type_node
, NULL_TREE
);
7615 tree v4sf_ftype_pcfloat
7616 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
7617 tree void_ftype_pfloat_v4sf
7618 = build_function_type_list (void_type_node
,
7619 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
7620 tree v4si_ftype_pcint
7621 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
7622 tree void_ftype_pint_v4si
7623 = build_function_type_list (void_type_node
,
7624 pint_type_node
, V4SI_type_node
, NULL_TREE
);
7625 tree v8hi_ftype_pcshort
7626 = build_function_type_list (V8HI_type_node
, pcshort_type_node
, NULL_TREE
);
7627 tree void_ftype_pshort_v8hi
7628 = build_function_type_list (void_type_node
,
7629 pshort_type_node
, V8HI_type_node
, NULL_TREE
);
7630 tree v16qi_ftype_pcchar
7631 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
7632 tree void_ftype_pchar_v16qi
7633 = build_function_type_list (void_type_node
,
7634 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
7635 tree void_ftype_v4si
7636 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
7637 tree v8hi_ftype_void
7638 = build_function_type (V8HI_type_node
, void_list_node
);
7639 tree void_ftype_void
7640 = build_function_type (void_type_node
, void_list_node
);
7642 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
7644 tree v16qi_ftype_long_pcvoid
7645 = build_function_type_list (V16QI_type_node
,
7646 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
7647 tree v8hi_ftype_long_pcvoid
7648 = build_function_type_list (V8HI_type_node
,
7649 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
7650 tree v4si_ftype_long_pcvoid
7651 = build_function_type_list (V4SI_type_node
,
7652 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
7654 tree void_ftype_v4si_long_pvoid
7655 = build_function_type_list (void_type_node
,
7656 V4SI_type_node
, long_integer_type_node
,
7657 pvoid_type_node
, NULL_TREE
);
7658 tree void_ftype_v16qi_long_pvoid
7659 = build_function_type_list (void_type_node
,
7660 V16QI_type_node
, long_integer_type_node
,
7661 pvoid_type_node
, NULL_TREE
);
7662 tree void_ftype_v8hi_long_pvoid
7663 = build_function_type_list (void_type_node
,
7664 V8HI_type_node
, long_integer_type_node
,
7665 pvoid_type_node
, NULL_TREE
);
7666 tree int_ftype_int_v8hi_v8hi
7667 = build_function_type_list (integer_type_node
,
7668 integer_type_node
, V8HI_type_node
,
7669 V8HI_type_node
, NULL_TREE
);
7670 tree int_ftype_int_v16qi_v16qi
7671 = build_function_type_list (integer_type_node
,
7672 integer_type_node
, V16QI_type_node
,
7673 V16QI_type_node
, NULL_TREE
);
7674 tree int_ftype_int_v4sf_v4sf
7675 = build_function_type_list (integer_type_node
,
7676 integer_type_node
, V4SF_type_node
,
7677 V4SF_type_node
, NULL_TREE
);
7678 tree v4si_ftype_v4si
7679 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
7680 tree v8hi_ftype_v8hi
7681 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
7682 tree v16qi_ftype_v16qi
7683 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
7684 tree v4sf_ftype_v4sf
7685 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
7686 tree void_ftype_pcvoid_int_int
7687 = build_function_type_list (void_type_node
,
7688 pcvoid_type_node
, integer_type_node
,
7689 integer_type_node
, NULL_TREE
);
7690 tree int_ftype_pcchar
7691 = build_function_type_list (integer_type_node
,
7692 pcchar_type_node
, NULL_TREE
);
7694 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat
,
7695 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
);
7696 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf
,
7697 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
);
7698 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint
,
7699 ALTIVEC_BUILTIN_LD_INTERNAL_4si
);
7700 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si
,
7701 ALTIVEC_BUILTIN_ST_INTERNAL_4si
);
7702 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort
,
7703 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
);
7704 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi
,
7705 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
);
7706 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar
,
7707 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
);
7708 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi
,
7709 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
);
7710 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
7711 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
7712 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
7713 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
7714 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
7715 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
7716 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
7717 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
7718 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
7719 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
7720 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
7721 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
7722 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
7723 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
7724 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
7725 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
7727 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7728 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_compiletime_error", int_ftype_pcchar
,
7729 ALTIVEC_BUILTIN_COMPILETIME_ERROR
);
7731 /* Add the DST variants. */
7732 d
= (struct builtin_description
*) bdesc_dst
;
7733 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
7734 def_builtin (d
->mask
, d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
7736 /* Initialize the predicates. */
7737 dp
= (struct builtin_description_predicates
*) bdesc_altivec_preds
;
7738 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
7740 enum machine_mode mode1
;
7743 mode1
= insn_data
[dp
->icode
].operand
[1].mode
;
7748 type
= int_ftype_int_v4si_v4si
;
7751 type
= int_ftype_int_v8hi_v8hi
;
7754 type
= int_ftype_int_v16qi_v16qi
;
7757 type
= int_ftype_int_v4sf_v4sf
;
7763 def_builtin (dp
->mask
, dp
->name
, type
, dp
->code
);
7766 /* Initialize the abs* operators. */
7767 d
= (struct builtin_description
*) bdesc_abs
;
7768 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
7770 enum machine_mode mode0
;
7773 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
7778 type
= v4si_ftype_v4si
;
7781 type
= v8hi_ftype_v8hi
;
7784 type
= v16qi_ftype_v16qi
;
7787 type
= v4sf_ftype_v4sf
;
7793 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
7798 rs6000_common_init_builtins (void)
7800 struct builtin_description
*d
;
7803 tree v4sf_ftype_v4sf_v4sf_v16qi
7804 = build_function_type_list (V4SF_type_node
,
7805 V4SF_type_node
, V4SF_type_node
,
7806 V16QI_type_node
, NULL_TREE
);
7807 tree v4si_ftype_v4si_v4si_v16qi
7808 = build_function_type_list (V4SI_type_node
,
7809 V4SI_type_node
, V4SI_type_node
,
7810 V16QI_type_node
, NULL_TREE
);
7811 tree v8hi_ftype_v8hi_v8hi_v16qi
7812 = build_function_type_list (V8HI_type_node
,
7813 V8HI_type_node
, V8HI_type_node
,
7814 V16QI_type_node
, NULL_TREE
);
7815 tree v16qi_ftype_v16qi_v16qi_v16qi
7816 = build_function_type_list (V16QI_type_node
,
7817 V16QI_type_node
, V16QI_type_node
,
7818 V16QI_type_node
, NULL_TREE
);
7820 = build_function_type_list (V4SI_type_node
, integer_type_node
, NULL_TREE
);
7822 = build_function_type_list (V8HI_type_node
, integer_type_node
, NULL_TREE
);
7823 tree v16qi_ftype_int
7824 = build_function_type_list (V16QI_type_node
, integer_type_node
, NULL_TREE
);
7825 tree v8hi_ftype_v16qi
7826 = build_function_type_list (V8HI_type_node
, V16QI_type_node
, NULL_TREE
);
7827 tree v4sf_ftype_v4sf
7828 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
7830 tree v2si_ftype_v2si_v2si
7831 = build_function_type_list (opaque_V2SI_type_node
,
7832 opaque_V2SI_type_node
,
7833 opaque_V2SI_type_node
, NULL_TREE
);
7835 tree v2sf_ftype_v2sf_v2sf
7836 = build_function_type_list (opaque_V2SF_type_node
,
7837 opaque_V2SF_type_node
,
7838 opaque_V2SF_type_node
, NULL_TREE
);
7840 tree v2si_ftype_int_int
7841 = build_function_type_list (opaque_V2SI_type_node
,
7842 integer_type_node
, integer_type_node
,
7845 tree v2si_ftype_v2si
7846 = build_function_type_list (opaque_V2SI_type_node
,
7847 opaque_V2SI_type_node
, NULL_TREE
);
7849 tree v2sf_ftype_v2sf
7850 = build_function_type_list (opaque_V2SF_type_node
,
7851 opaque_V2SF_type_node
, NULL_TREE
);
7853 tree v2sf_ftype_v2si
7854 = build_function_type_list (opaque_V2SF_type_node
,
7855 opaque_V2SI_type_node
, NULL_TREE
);
7857 tree v2si_ftype_v2sf
7858 = build_function_type_list (opaque_V2SI_type_node
,
7859 opaque_V2SF_type_node
, NULL_TREE
);
7861 tree v2si_ftype_v2si_char
7862 = build_function_type_list (opaque_V2SI_type_node
,
7863 opaque_V2SI_type_node
,
7864 char_type_node
, NULL_TREE
);
7866 tree v2si_ftype_int_char
7867 = build_function_type_list (opaque_V2SI_type_node
,
7868 integer_type_node
, char_type_node
, NULL_TREE
);
7870 tree v2si_ftype_char
7871 = build_function_type_list (opaque_V2SI_type_node
,
7872 char_type_node
, NULL_TREE
);
7874 tree int_ftype_int_int
7875 = build_function_type_list (integer_type_node
,
7876 integer_type_node
, integer_type_node
,
7879 tree v4si_ftype_v4si_v4si
7880 = build_function_type_list (V4SI_type_node
,
7881 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
7882 tree v4sf_ftype_v4si_int
7883 = build_function_type_list (V4SF_type_node
,
7884 V4SI_type_node
, integer_type_node
, NULL_TREE
);
7885 tree v4si_ftype_v4sf_int
7886 = build_function_type_list (V4SI_type_node
,
7887 V4SF_type_node
, integer_type_node
, NULL_TREE
);
7888 tree v4si_ftype_v4si_int
7889 = build_function_type_list (V4SI_type_node
,
7890 V4SI_type_node
, integer_type_node
, NULL_TREE
);
7891 tree v8hi_ftype_v8hi_int
7892 = build_function_type_list (V8HI_type_node
,
7893 V8HI_type_node
, integer_type_node
, NULL_TREE
);
7894 tree v16qi_ftype_v16qi_int
7895 = build_function_type_list (V16QI_type_node
,
7896 V16QI_type_node
, integer_type_node
, NULL_TREE
);
7897 tree v16qi_ftype_v16qi_v16qi_int
7898 = build_function_type_list (V16QI_type_node
,
7899 V16QI_type_node
, V16QI_type_node
,
7900 integer_type_node
, NULL_TREE
);
7901 tree v8hi_ftype_v8hi_v8hi_int
7902 = build_function_type_list (V8HI_type_node
,
7903 V8HI_type_node
, V8HI_type_node
,
7904 integer_type_node
, NULL_TREE
);
7905 tree v4si_ftype_v4si_v4si_int
7906 = build_function_type_list (V4SI_type_node
,
7907 V4SI_type_node
, V4SI_type_node
,
7908 integer_type_node
, NULL_TREE
);
7909 tree v4sf_ftype_v4sf_v4sf_int
7910 = build_function_type_list (V4SF_type_node
,
7911 V4SF_type_node
, V4SF_type_node
,
7912 integer_type_node
, NULL_TREE
);
7913 tree v4sf_ftype_v4sf_v4sf
7914 = build_function_type_list (V4SF_type_node
,
7915 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
7916 tree v4sf_ftype_v4sf_v4sf_v4si
7917 = build_function_type_list (V4SF_type_node
,
7918 V4SF_type_node
, V4SF_type_node
,
7919 V4SI_type_node
, NULL_TREE
);
7920 tree v4sf_ftype_v4sf_v4sf_v4sf
7921 = build_function_type_list (V4SF_type_node
,
7922 V4SF_type_node
, V4SF_type_node
,
7923 V4SF_type_node
, NULL_TREE
);
7924 tree v4si_ftype_v4si_v4si_v4si
7925 = build_function_type_list (V4SI_type_node
,
7926 V4SI_type_node
, V4SI_type_node
,
7927 V4SI_type_node
, NULL_TREE
);
7928 tree v8hi_ftype_v8hi_v8hi
7929 = build_function_type_list (V8HI_type_node
,
7930 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
7931 tree v8hi_ftype_v8hi_v8hi_v8hi
7932 = build_function_type_list (V8HI_type_node
,
7933 V8HI_type_node
, V8HI_type_node
,
7934 V8HI_type_node
, NULL_TREE
);
7935 tree v4si_ftype_v8hi_v8hi_v4si
7936 = build_function_type_list (V4SI_type_node
,
7937 V8HI_type_node
, V8HI_type_node
,
7938 V4SI_type_node
, NULL_TREE
);
7939 tree v4si_ftype_v16qi_v16qi_v4si
7940 = build_function_type_list (V4SI_type_node
,
7941 V16QI_type_node
, V16QI_type_node
,
7942 V4SI_type_node
, NULL_TREE
);
7943 tree v16qi_ftype_v16qi_v16qi
7944 = build_function_type_list (V16QI_type_node
,
7945 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
7946 tree v4si_ftype_v4sf_v4sf
7947 = build_function_type_list (V4SI_type_node
,
7948 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
7949 tree v8hi_ftype_v16qi_v16qi
7950 = build_function_type_list (V8HI_type_node
,
7951 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
7952 tree v4si_ftype_v8hi_v8hi
7953 = build_function_type_list (V4SI_type_node
,
7954 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
7955 tree v8hi_ftype_v4si_v4si
7956 = build_function_type_list (V8HI_type_node
,
7957 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
7958 tree v16qi_ftype_v8hi_v8hi
7959 = build_function_type_list (V16QI_type_node
,
7960 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
7961 tree v4si_ftype_v16qi_v4si
7962 = build_function_type_list (V4SI_type_node
,
7963 V16QI_type_node
, V4SI_type_node
, NULL_TREE
);
7964 tree v4si_ftype_v16qi_v16qi
7965 = build_function_type_list (V4SI_type_node
,
7966 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
7967 tree v4si_ftype_v8hi_v4si
7968 = build_function_type_list (V4SI_type_node
,
7969 V8HI_type_node
, V4SI_type_node
, NULL_TREE
);
7970 tree v4si_ftype_v8hi
7971 = build_function_type_list (V4SI_type_node
, V8HI_type_node
, NULL_TREE
);
7972 tree int_ftype_v4si_v4si
7973 = build_function_type_list (integer_type_node
,
7974 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
7975 tree int_ftype_v4sf_v4sf
7976 = build_function_type_list (integer_type_node
,
7977 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
7978 tree int_ftype_v16qi_v16qi
7979 = build_function_type_list (integer_type_node
,
7980 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
7981 tree int_ftype_v8hi_v8hi
7982 = build_function_type_list (integer_type_node
,
7983 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
7985 /* Add the simple ternary operators. */
7986 d
= (struct builtin_description
*) bdesc_3arg
;
7987 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
7990 enum machine_mode mode0
, mode1
, mode2
, mode3
;
7993 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
7996 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
7997 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
7998 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
7999 mode3
= insn_data
[d
->icode
].operand
[3].mode
;
8001 /* When all four are of the same mode. */
8002 if (mode0
== mode1
&& mode1
== mode2
&& mode2
== mode3
)
8007 type
= v4si_ftype_v4si_v4si_v4si
;
8010 type
= v4sf_ftype_v4sf_v4sf_v4sf
;
8013 type
= v8hi_ftype_v8hi_v8hi_v8hi
;
8016 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
8022 else if (mode0
== mode1
&& mode1
== mode2
&& mode3
== V16QImode
)
8027 type
= v4si_ftype_v4si_v4si_v16qi
;
8030 type
= v4sf_ftype_v4sf_v4sf_v16qi
;
8033 type
= v8hi_ftype_v8hi_v8hi_v16qi
;
8036 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
8042 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
8043 && mode3
== V4SImode
)
8044 type
= v4si_ftype_v16qi_v16qi_v4si
;
8045 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
8046 && mode3
== V4SImode
)
8047 type
= v4si_ftype_v8hi_v8hi_v4si
;
8048 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
8049 && mode3
== V4SImode
)
8050 type
= v4sf_ftype_v4sf_v4sf_v4si
;
8052 /* vchar, vchar, vchar, 4 bit literal. */
8053 else if (mode0
== V16QImode
&& mode1
== mode0
&& mode2
== mode0
8055 type
= v16qi_ftype_v16qi_v16qi_int
;
8057 /* vshort, vshort, vshort, 4 bit literal. */
8058 else if (mode0
== V8HImode
&& mode1
== mode0
&& mode2
== mode0
8060 type
= v8hi_ftype_v8hi_v8hi_int
;
8062 /* vint, vint, vint, 4 bit literal. */
8063 else if (mode0
== V4SImode
&& mode1
== mode0
&& mode2
== mode0
8065 type
= v4si_ftype_v4si_v4si_int
;
8067 /* vfloat, vfloat, vfloat, 4 bit literal. */
8068 else if (mode0
== V4SFmode
&& mode1
== mode0
&& mode2
== mode0
8070 type
= v4sf_ftype_v4sf_v4sf_int
;
8075 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8078 /* Add the simple binary operators. */
8079 d
= (struct builtin_description
*) bdesc_2arg
;
8080 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
8082 enum machine_mode mode0
, mode1
, mode2
;
8085 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8088 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8089 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8090 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8092 /* When all three operands are of the same mode. */
8093 if (mode0
== mode1
&& mode1
== mode2
)
8098 type
= v4sf_ftype_v4sf_v4sf
;
8101 type
= v4si_ftype_v4si_v4si
;
8104 type
= v16qi_ftype_v16qi_v16qi
;
8107 type
= v8hi_ftype_v8hi_v8hi
;
8110 type
= v2si_ftype_v2si_v2si
;
8113 type
= v2sf_ftype_v2sf_v2sf
;
8116 type
= int_ftype_int_int
;
8123 /* A few other combos we really don't want to do manually. */
8125 /* vint, vfloat, vfloat. */
8126 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
)
8127 type
= v4si_ftype_v4sf_v4sf
;
8129 /* vshort, vchar, vchar. */
8130 else if (mode0
== V8HImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
8131 type
= v8hi_ftype_v16qi_v16qi
;
8133 /* vint, vshort, vshort. */
8134 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
8135 type
= v4si_ftype_v8hi_v8hi
;
8137 /* vshort, vint, vint. */
8138 else if (mode0
== V8HImode
&& mode1
== V4SImode
&& mode2
== V4SImode
)
8139 type
= v8hi_ftype_v4si_v4si
;
8141 /* vchar, vshort, vshort. */
8142 else if (mode0
== V16QImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
8143 type
= v16qi_ftype_v8hi_v8hi
;
8145 /* vint, vchar, vint. */
8146 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V4SImode
)
8147 type
= v4si_ftype_v16qi_v4si
;
8149 /* vint, vchar, vchar. */
8150 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
8151 type
= v4si_ftype_v16qi_v16qi
;
8153 /* vint, vshort, vint. */
8154 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V4SImode
)
8155 type
= v4si_ftype_v8hi_v4si
;
8157 /* vint, vint, 5 bit literal. */
8158 else if (mode0
== V4SImode
&& mode1
== V4SImode
&& mode2
== QImode
)
8159 type
= v4si_ftype_v4si_int
;
8161 /* vshort, vshort, 5 bit literal. */
8162 else if (mode0
== V8HImode
&& mode1
== V8HImode
&& mode2
== QImode
)
8163 type
= v8hi_ftype_v8hi_int
;
8165 /* vchar, vchar, 5 bit literal. */
8166 else if (mode0
== V16QImode
&& mode1
== V16QImode
&& mode2
== QImode
)
8167 type
= v16qi_ftype_v16qi_int
;
8169 /* vfloat, vint, 5 bit literal. */
8170 else if (mode0
== V4SFmode
&& mode1
== V4SImode
&& mode2
== QImode
)
8171 type
= v4sf_ftype_v4si_int
;
8173 /* vint, vfloat, 5 bit literal. */
8174 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== QImode
)
8175 type
= v4si_ftype_v4sf_int
;
8177 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== SImode
)
8178 type
= v2si_ftype_int_int
;
8180 else if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
8181 type
= v2si_ftype_v2si_char
;
8183 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== QImode
)
8184 type
= v2si_ftype_int_char
;
8187 else if (mode0
== SImode
)
8192 type
= int_ftype_v4si_v4si
;
8195 type
= int_ftype_v4sf_v4sf
;
8198 type
= int_ftype_v16qi_v16qi
;
8201 type
= int_ftype_v8hi_v8hi
;
8211 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8214 /* Add the simple unary operators. */
8215 d
= (struct builtin_description
*) bdesc_1arg
;
8216 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
8218 enum machine_mode mode0
, mode1
;
8221 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8224 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8225 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8227 if (mode0
== V4SImode
&& mode1
== QImode
)
8228 type
= v4si_ftype_int
;
8229 else if (mode0
== V8HImode
&& mode1
== QImode
)
8230 type
= v8hi_ftype_int
;
8231 else if (mode0
== V16QImode
&& mode1
== QImode
)
8232 type
= v16qi_ftype_int
;
8233 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
)
8234 type
= v4sf_ftype_v4sf
;
8235 else if (mode0
== V8HImode
&& mode1
== V16QImode
)
8236 type
= v8hi_ftype_v16qi
;
8237 else if (mode0
== V4SImode
&& mode1
== V8HImode
)
8238 type
= v4si_ftype_v8hi
;
8239 else if (mode0
== V2SImode
&& mode1
== V2SImode
)
8240 type
= v2si_ftype_v2si
;
8241 else if (mode0
== V2SFmode
&& mode1
== V2SFmode
)
8242 type
= v2sf_ftype_v2sf
;
8243 else if (mode0
== V2SFmode
&& mode1
== V2SImode
)
8244 type
= v2sf_ftype_v2si
;
8245 else if (mode0
== V2SImode
&& mode1
== V2SFmode
)
8246 type
= v2si_ftype_v2sf
;
8247 else if (mode0
== V2SImode
&& mode1
== QImode
)
8248 type
= v2si_ftype_char
;
8252 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8257 rs6000_init_libfuncs (void)
8259 if (!TARGET_HARD_FLOAT
)
8262 if (DEFAULT_ABI
!= ABI_V4
)
8264 if (TARGET_XCOFF
&& ! TARGET_POWER2
&& ! TARGET_POWERPC
)
8266 /* AIX library routines for float->int conversion. */
8267 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
8268 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
8269 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
8270 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
8273 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8274 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
8275 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
8276 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
8277 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
8281 /* 32-bit SVR4 quad floating point routines. */
8283 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
8284 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
8285 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
8286 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
8287 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
8288 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
8289 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
8291 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
8292 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
8293 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
8294 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
8295 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
8296 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
8298 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
8299 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
8300 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
8301 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
8302 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
8303 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
8304 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
8309 /* Expand a block clear operation, and return 1 if successful. Return 0
8310 if we should let the compiler generate normal code.
8312 operands[0] is the destination
8313 operands[1] is the length
8314 operands[2] is the alignment */
8317 expand_block_clear (rtx operands
[])
8319 rtx orig_dest
= operands
[0];
8320 rtx bytes_rtx
= operands
[1];
8321 rtx align_rtx
= operands
[2];
8322 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
8323 HOST_WIDE_INT align
;
8324 HOST_WIDE_INT bytes
;
8329 /* If this is not a fixed size move, just call memcpy */
8333 /* If this is not a fixed size alignment, abort */
8334 if (GET_CODE (align_rtx
) != CONST_INT
)
8336 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
8338 /* Anything to clear? */
8339 bytes
= INTVAL (bytes_rtx
);
8343 /* Use the builtin memset after a point, to avoid huge code bloat.
8344 When optimize_size, avoid any significant code bloat; calling
8345 memset is about 4 instructions, so allow for one instruction to
8346 load zero and three to do clearing. */
8347 if (TARGET_ALTIVEC
&& align
>= 128)
8349 else if (TARGET_POWERPC64
&& align
>= 32)
8354 if (optimize_size
&& bytes
> 3 * clear_step
)
8356 if (! optimize_size
&& bytes
> 8 * clear_step
)
8359 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
8361 enum machine_mode mode
= BLKmode
;
8364 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
8369 else if (bytes
>= 8 && TARGET_POWERPC64
8370 /* 64-bit loads and stores require word-aligned
8372 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
8377 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
8378 { /* move 4 bytes */
8382 else if (bytes
== 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
8383 { /* move 2 bytes */
8387 else /* move 1 byte at a time */
8393 dest
= adjust_address (orig_dest
, mode
, offset
);
8395 emit_move_insn (dest
, CONST0_RTX (mode
));
8402 /* Expand a block move operation, and return 1 if successful. Return 0
8403 if we should let the compiler generate normal code.
8405 operands[0] is the destination
8406 operands[1] is the source
8407 operands[2] is the length
8408 operands[3] is the alignment */
8410 #define MAX_MOVE_REG 4
8413 expand_block_move (rtx operands
[])
8415 rtx orig_dest
= operands
[0];
8416 rtx orig_src
= operands
[1];
8417 rtx bytes_rtx
= operands
[2];
8418 rtx align_rtx
= operands
[3];
8419 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
8424 rtx stores
[MAX_MOVE_REG
];
8427 /* If this is not a fixed size move, just call memcpy */
8431 /* If this is not a fixed size alignment, abort */
8432 if (GET_CODE (align_rtx
) != CONST_INT
)
8434 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
8436 /* Anything to move? */
8437 bytes
= INTVAL (bytes_rtx
);
8441 /* store_one_arg depends on expand_block_move to handle at least the size of
8442 reg_parm_stack_space. */
8443 if (bytes
> (TARGET_POWERPC64
? 64 : 32))
8446 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
8449 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
8450 rtx (*mov
) (rtx
, rtx
);
8452 enum machine_mode mode
= BLKmode
;
8455 /* Altivec first, since it will be faster than a string move
8456 when it applies, and usually not significantly larger. */
8457 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
8461 gen_func
.mov
= gen_movv4si
;
8463 else if (TARGET_STRING
8464 && bytes
> 24 /* move up to 32 bytes at a time */
8472 && ! fixed_regs
[12])
8474 move_bytes
= (bytes
> 32) ? 32 : bytes
;
8475 gen_func
.movmemsi
= gen_movmemsi_8reg
;
8477 else if (TARGET_STRING
8478 && bytes
> 16 /* move up to 24 bytes at a time */
8484 && ! fixed_regs
[10])
8486 move_bytes
= (bytes
> 24) ? 24 : bytes
;
8487 gen_func
.movmemsi
= gen_movmemsi_6reg
;
8489 else if (TARGET_STRING
8490 && bytes
> 8 /* move up to 16 bytes at a time */
8496 move_bytes
= (bytes
> 16) ? 16 : bytes
;
8497 gen_func
.movmemsi
= gen_movmemsi_4reg
;
8499 else if (bytes
>= 8 && TARGET_POWERPC64
8500 /* 64-bit loads and stores require word-aligned
8502 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
8506 gen_func
.mov
= gen_movdi
;
8508 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
8509 { /* move up to 8 bytes at a time */
8510 move_bytes
= (bytes
> 8) ? 8 : bytes
;
8511 gen_func
.movmemsi
= gen_movmemsi_2reg
;
8513 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
8514 { /* move 4 bytes */
8517 gen_func
.mov
= gen_movsi
;
8519 else if (bytes
== 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
8520 { /* move 2 bytes */
8523 gen_func
.mov
= gen_movhi
;
8525 else if (TARGET_STRING
&& bytes
> 1)
8526 { /* move up to 4 bytes at a time */
8527 move_bytes
= (bytes
> 4) ? 4 : bytes
;
8528 gen_func
.movmemsi
= gen_movmemsi_1reg
;
8530 else /* move 1 byte at a time */
8534 gen_func
.mov
= gen_movqi
;
8537 src
= adjust_address (orig_src
, mode
, offset
);
8538 dest
= adjust_address (orig_dest
, mode
, offset
);
8540 if (mode
!= BLKmode
)
8542 rtx tmp_reg
= gen_reg_rtx (mode
);
8544 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
8545 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
8548 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
8551 for (i
= 0; i
< num_reg
; i
++)
8552 emit_insn (stores
[i
]);
8556 if (mode
== BLKmode
)
8558 /* Move the address into scratch registers. The movmemsi
8559 patterns require zero offset. */
8560 if (!REG_P (XEXP (src
, 0)))
8562 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
8563 src
= replace_equiv_address (src
, src_reg
);
8565 set_mem_size (src
, GEN_INT (move_bytes
));
8567 if (!REG_P (XEXP (dest
, 0)))
8569 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
8570 dest
= replace_equiv_address (dest
, dest_reg
);
8572 set_mem_size (dest
, GEN_INT (move_bytes
));
8574 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
8575 GEN_INT (move_bytes
& 31),
8584 /* Return 1 if OP is suitable for a save_world call in prologue. It is
8585 known to be a PARALLEL. */
8587 save_world_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
8592 int count
= XVECLEN (op
, 0);
8598 if (GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
8599 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
)
8602 for (i
=1; i
<= 18; i
++)
8604 elt
= XVECEXP (op
, 0, index
++);
8605 if (GET_CODE (elt
) != SET
8606 || GET_CODE (SET_DEST (elt
)) != MEM
8607 || ! memory_operand (SET_DEST (elt
), DFmode
)
8608 || GET_CODE (SET_SRC (elt
)) != REG
8609 || GET_MODE (SET_SRC (elt
)) != DFmode
)
8613 for (i
=1; i
<= 12; i
++)
8615 elt
= XVECEXP (op
, 0, index
++);
8616 if (GET_CODE (elt
) != SET
8617 || GET_CODE (SET_DEST (elt
)) != MEM
8618 || GET_CODE (SET_SRC (elt
)) != REG
8619 || GET_MODE (SET_SRC (elt
)) != V4SImode
)
8623 for (i
=1; i
<= 19; i
++)
8625 elt
= XVECEXP (op
, 0, index
++);
8626 if (GET_CODE (elt
) != SET
8627 || GET_CODE (SET_DEST (elt
)) != MEM
8628 || ! memory_operand (SET_DEST (elt
), Pmode
)
8629 || GET_CODE (SET_SRC (elt
)) != REG
8630 || GET_MODE (SET_SRC (elt
)) != Pmode
)
8634 elt
= XVECEXP (op
, 0, index
++);
8635 if (GET_CODE (elt
) != SET
8636 || GET_CODE (SET_DEST (elt
)) != MEM
8637 || ! memory_operand (SET_DEST (elt
), Pmode
)
8638 || GET_CODE (SET_SRC (elt
)) != REG
8639 || REGNO (SET_SRC (elt
)) != CR2_REGNO
8640 || GET_MODE (SET_SRC (elt
)) != Pmode
)
8643 if (GET_CODE (XVECEXP (op
, 0, index
++)) != USE
8644 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
8645 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
)
8650 /* Return 1 if OP is suitable for a save_world call in prologue. It is
8651 known to be a PARALLEL. */
8653 restore_world_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
8658 int count
= XVECLEN (op
, 0);
8664 if (GET_CODE (XVECEXP (op
, 0, index
++)) != RETURN
8665 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
8666 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
8667 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
)
8670 elt
= XVECEXP (op
, 0, index
++);
8671 if (GET_CODE (elt
) != SET
8672 || GET_CODE (SET_SRC (elt
)) != MEM
8673 || ! memory_operand (SET_SRC (elt
), Pmode
)
8674 || GET_CODE (SET_DEST (elt
)) != REG
8675 || REGNO (SET_DEST (elt
)) != CR2_REGNO
8676 || GET_MODE (SET_DEST (elt
)) != Pmode
)
8679 for (i
=1; i
<= 19; i
++)
8681 elt
= XVECEXP (op
, 0, index
++);
8682 if (GET_CODE (elt
) != SET
8683 || GET_CODE (SET_SRC (elt
)) != MEM
8684 || ! memory_operand (SET_SRC (elt
), Pmode
)
8685 || GET_CODE (SET_DEST (elt
)) != REG
8686 || GET_MODE (SET_DEST (elt
)) != Pmode
)
8690 for (i
=1; i
<= 12; i
++)
8692 elt
= XVECEXP (op
, 0, index
++);
8693 if (GET_CODE (elt
) != SET
8694 || GET_CODE (SET_SRC (elt
)) != MEM
8695 || GET_CODE (SET_DEST (elt
)) != REG
8696 || GET_MODE (SET_DEST (elt
)) != V4SImode
)
8700 for (i
=1; i
<= 18; i
++)
8702 elt
= XVECEXP (op
, 0, index
++);
8703 if (GET_CODE (elt
) != SET
8704 || GET_CODE (SET_SRC (elt
)) != MEM
8705 || ! memory_operand (SET_SRC (elt
), DFmode
)
8706 || GET_CODE (SET_DEST (elt
)) != REG
8707 || GET_MODE (SET_DEST (elt
)) != DFmode
)
8711 if (GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
8712 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
8713 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
8714 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
8715 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
)
8721 /* Return 1 if OP is a load multiple operation. It is known to be a
8722 PARALLEL and the first section will be tested. */
8725 load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
8727 int count
= XVECLEN (op
, 0);
8728 unsigned int dest_regno
;
8732 /* Perform a quick check so we don't blow up below. */
8734 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
8735 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
8736 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != MEM
)
8739 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
8740 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0);
8742 for (i
= 1; i
< count
; i
++)
8744 rtx elt
= XVECEXP (op
, 0, i
);
8746 if (GET_CODE (elt
) != SET
8747 || GET_CODE (SET_DEST (elt
)) != REG
8748 || GET_MODE (SET_DEST (elt
)) != SImode
8749 || REGNO (SET_DEST (elt
)) != dest_regno
+ i
8750 || GET_CODE (SET_SRC (elt
)) != MEM
8751 || GET_MODE (SET_SRC (elt
)) != SImode
8752 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
8753 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
8754 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
8755 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != i
* 4)
8762 /* Similar, but tests for store multiple. Here, the second vector element
8763 is a CLOBBER. It will be tested later. */
8766 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
8768 int count
= XVECLEN (op
, 0) - 1;
8769 unsigned int src_regno
;
8773 /* Perform a quick check so we don't blow up below. */
8775 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
8776 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != MEM
8777 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != REG
)
8780 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
8781 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, 0)), 0);
8783 for (i
= 1; i
< count
; i
++)
8785 rtx elt
= XVECEXP (op
, 0, i
+ 1);
8787 if (GET_CODE (elt
) != SET
8788 || GET_CODE (SET_SRC (elt
)) != REG
8789 || GET_MODE (SET_SRC (elt
)) != SImode
8790 || REGNO (SET_SRC (elt
)) != src_regno
+ i
8791 || GET_CODE (SET_DEST (elt
)) != MEM
8792 || GET_MODE (SET_DEST (elt
)) != SImode
8793 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
8794 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
8795 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
8796 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != i
* 4)
8803 /* Return a string to perform a load_multiple operation.
8804 operands[0] is the vector.
8805 operands[1] is the source address.
8806 operands[2] is the first destination register. */
8809 rs6000_output_load_multiple (rtx operands
[3])
8811 /* We have to handle the case where the pseudo used to contain the address
8812 is assigned to one of the output registers. */
8814 int words
= XVECLEN (operands
[0], 0);
8817 if (XVECLEN (operands
[0], 0) == 1)
8818 return "{l|lwz} %2,0(%1)";
8820 for (i
= 0; i
< words
; i
++)
8821 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
8822 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
8826 xop
[0] = GEN_INT (4 * (words
-1));
8827 xop
[1] = operands
[1];
8828 xop
[2] = operands
[2];
8829 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
8834 xop
[0] = GEN_INT (4 * (words
-1));
8835 xop
[1] = operands
[1];
8836 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
8837 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
8842 for (j
= 0; j
< words
; j
++)
8845 xop
[0] = GEN_INT (j
* 4);
8846 xop
[1] = operands
[1];
8847 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
8848 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
8850 xop
[0] = GEN_INT (i
* 4);
8851 xop
[1] = operands
[1];
8852 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
8857 return "{lsi|lswi} %2,%1,%N0";
8860 /* Return 1 for a parallel vrsave operation. */
8863 vrsave_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
8865 int count
= XVECLEN (op
, 0);
8866 unsigned int dest_regno
, src_regno
;
8870 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
8871 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
8872 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC_VOLATILE
)
8875 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
8876 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
8878 if (dest_regno
!= VRSAVE_REGNO
8879 && src_regno
!= VRSAVE_REGNO
)
8882 for (i
= 1; i
< count
; i
++)
8884 rtx elt
= XVECEXP (op
, 0, i
);
8886 if (GET_CODE (elt
) != CLOBBER
8887 && GET_CODE (elt
) != SET
)
8894 /* Return 1 for an PARALLEL suitable for mfcr. */
8897 mfcr_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
8899 int count
= XVECLEN (op
, 0);
8902 /* Perform a quick check so we don't blow up below. */
8904 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
8905 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
8906 || XVECLEN (SET_SRC (XVECEXP (op
, 0, 0)), 0) != 2)
8909 for (i
= 0; i
< count
; i
++)
8911 rtx exp
= XVECEXP (op
, 0, i
);
8916 src_reg
= XVECEXP (SET_SRC (exp
), 0, 0);
8918 if (GET_CODE (src_reg
) != REG
8919 || GET_MODE (src_reg
) != CCmode
8920 || ! CR_REGNO_P (REGNO (src_reg
)))
8923 if (GET_CODE (exp
) != SET
8924 || GET_CODE (SET_DEST (exp
)) != REG
8925 || GET_MODE (SET_DEST (exp
)) != SImode
8926 || ! INT_REGNO_P (REGNO (SET_DEST (exp
))))
8928 unspec
= SET_SRC (exp
);
8929 maskval
= 1 << (MAX_CR_REGNO
- REGNO (src_reg
));
8931 if (GET_CODE (unspec
) != UNSPEC
8932 || XINT (unspec
, 1) != UNSPEC_MOVESI_FROM_CR
8933 || XVECLEN (unspec
, 0) != 2
8934 || XVECEXP (unspec
, 0, 0) != src_reg
8935 || GET_CODE (XVECEXP (unspec
, 0, 1)) != CONST_INT
8936 || INTVAL (XVECEXP (unspec
, 0, 1)) != maskval
)
8942 /* Return 1 for an PARALLEL suitable for mtcrf. */
8945 mtcrf_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
8947 int count
= XVECLEN (op
, 0);
8951 /* Perform a quick check so we don't blow up below. */
8953 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
8954 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
8955 || XVECLEN (SET_SRC (XVECEXP (op
, 0, 0)), 0) != 2)
8957 src_reg
= XVECEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0, 0);
8959 if (GET_CODE (src_reg
) != REG
8960 || GET_MODE (src_reg
) != SImode
8961 || ! INT_REGNO_P (REGNO (src_reg
)))
8964 for (i
= 0; i
< count
; i
++)
8966 rtx exp
= XVECEXP (op
, 0, i
);
8970 if (GET_CODE (exp
) != SET
8971 || GET_CODE (SET_DEST (exp
)) != REG
8972 || GET_MODE (SET_DEST (exp
)) != CCmode
8973 || ! CR_REGNO_P (REGNO (SET_DEST (exp
))))
8975 unspec
= SET_SRC (exp
);
8976 maskval
= 1 << (MAX_CR_REGNO
- REGNO (SET_DEST (exp
)));
8978 if (GET_CODE (unspec
) != UNSPEC
8979 || XINT (unspec
, 1) != UNSPEC_MOVESI_TO_CR
8980 || XVECLEN (unspec
, 0) != 2
8981 || XVECEXP (unspec
, 0, 0) != src_reg
8982 || GET_CODE (XVECEXP (unspec
, 0, 1)) != CONST_INT
8983 || INTVAL (XVECEXP (unspec
, 0, 1)) != maskval
)
8989 /* Return 1 for an PARALLEL suitable for lmw. */
8992 lmw_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
8994 int count
= XVECLEN (op
, 0);
8995 unsigned int dest_regno
;
8997 unsigned int base_regno
;
8998 HOST_WIDE_INT offset
;
9001 /* Perform a quick check so we don't blow up below. */
9003 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9004 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
9005 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != MEM
)
9008 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
9009 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0);
9012 || count
!= 32 - (int) dest_regno
)
9015 if (legitimate_indirect_address_p (src_addr
, 0))
9018 base_regno
= REGNO (src_addr
);
9019 if (base_regno
== 0)
9022 else if (rs6000_legitimate_offset_address_p (SImode
, src_addr
, 0))
9024 offset
= INTVAL (XEXP (src_addr
, 1));
9025 base_regno
= REGNO (XEXP (src_addr
, 0));
9030 for (i
= 0; i
< count
; i
++)
9032 rtx elt
= XVECEXP (op
, 0, i
);
9035 HOST_WIDE_INT newoffset
;
9037 if (GET_CODE (elt
) != SET
9038 || GET_CODE (SET_DEST (elt
)) != REG
9039 || GET_MODE (SET_DEST (elt
)) != SImode
9040 || REGNO (SET_DEST (elt
)) != dest_regno
+ i
9041 || GET_CODE (SET_SRC (elt
)) != MEM
9042 || GET_MODE (SET_SRC (elt
)) != SImode
)
9044 newaddr
= XEXP (SET_SRC (elt
), 0);
9045 if (legitimate_indirect_address_p (newaddr
, 0))
9050 else if (rs6000_legitimate_offset_address_p (SImode
, newaddr
, 0))
9052 addr_reg
= XEXP (newaddr
, 0);
9053 newoffset
= INTVAL (XEXP (newaddr
, 1));
9057 if (REGNO (addr_reg
) != base_regno
9058 || newoffset
!= offset
+ 4 * i
)
9065 /* Return 1 for an PARALLEL suitable for stmw. */
9068 stmw_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9070 int count
= XVECLEN (op
, 0);
9071 unsigned int src_regno
;
9073 unsigned int base_regno
;
9074 HOST_WIDE_INT offset
;
9077 /* Perform a quick check so we don't blow up below. */
9079 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9080 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != MEM
9081 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != REG
)
9084 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
9085 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, 0)), 0);
9088 || count
!= 32 - (int) src_regno
)
9091 if (legitimate_indirect_address_p (dest_addr
, 0))
9094 base_regno
= REGNO (dest_addr
);
9095 if (base_regno
== 0)
9098 else if (rs6000_legitimate_offset_address_p (SImode
, dest_addr
, 0))
9100 offset
= INTVAL (XEXP (dest_addr
, 1));
9101 base_regno
= REGNO (XEXP (dest_addr
, 0));
9106 for (i
= 0; i
< count
; i
++)
9108 rtx elt
= XVECEXP (op
, 0, i
);
9111 HOST_WIDE_INT newoffset
;
9113 if (GET_CODE (elt
) != SET
9114 || GET_CODE (SET_SRC (elt
)) != REG
9115 || GET_MODE (SET_SRC (elt
)) != SImode
9116 || REGNO (SET_SRC (elt
)) != src_regno
+ i
9117 || GET_CODE (SET_DEST (elt
)) != MEM
9118 || GET_MODE (SET_DEST (elt
)) != SImode
)
9120 newaddr
= XEXP (SET_DEST (elt
), 0);
9121 if (legitimate_indirect_address_p (newaddr
, 0))
9126 else if (rs6000_legitimate_offset_address_p (SImode
, newaddr
, 0))
9128 addr_reg
= XEXP (newaddr
, 0);
9129 newoffset
= INTVAL (XEXP (newaddr
, 1));
9133 if (REGNO (addr_reg
) != base_regno
9134 || newoffset
!= offset
+ 4 * i
)
9141 /* A validation routine: say whether CODE, a condition code, and MODE
9142 match. The other alternatives either don't make sense or should
9143 never be generated. */
9146 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
9148 if ((GET_RTX_CLASS (code
) != RTX_COMPARE
9149 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
)
9150 || GET_MODE_CLASS (mode
) != MODE_CC
)
9153 /* These don't make sense. */
9154 if ((code
== GT
|| code
== LT
|| code
== GE
|| code
== LE
)
9155 && mode
== CCUNSmode
)
9158 if ((code
== GTU
|| code
== LTU
|| code
== GEU
|| code
== LEU
)
9159 && mode
!= CCUNSmode
)
9162 if (mode
!= CCFPmode
9163 && (code
== ORDERED
|| code
== UNORDERED
9164 || code
== UNEQ
|| code
== LTGT
9165 || code
== UNGT
|| code
== UNLT
9166 || code
== UNGE
|| code
== UNLE
))
9169 /* These should never be generated except for
9170 flag_finite_math_only. */
9171 if (mode
== CCFPmode
9172 && ! flag_finite_math_only
9173 && (code
== LE
|| code
== GE
9174 || code
== UNEQ
|| code
== LTGT
9175 || code
== UNGT
|| code
== UNLT
))
9178 /* These are invalid; the information is not there. */
9179 if (mode
== CCEQmode
9180 && code
!= EQ
&& code
!= NE
)
9184 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
9185 We only check the opcode against the mode of the CC value here. */
9188 branch_comparison_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9190 enum rtx_code code
= GET_CODE (op
);
9191 enum machine_mode cc_mode
;
9193 if (!COMPARISON_P (op
))
9196 cc_mode
= GET_MODE (XEXP (op
, 0));
9197 if (GET_MODE_CLASS (cc_mode
) != MODE_CC
)
9200 validate_condition_mode (code
, cc_mode
);
9205 /* Return 1 if OP is a comparison operation that is valid for a branch
9206 insn and which is true if the corresponding bit in the CC register
9210 branch_positive_comparison_operator (rtx op
, enum machine_mode mode
)
9214 if (! branch_comparison_operator (op
, mode
))
9217 code
= GET_CODE (op
);
9218 return (code
== EQ
|| code
== LT
|| code
== GT
9219 || code
== LTU
|| code
== GTU
9220 || code
== UNORDERED
);
9223 /* Return 1 if OP is a comparison operation that is valid for an scc
9224 insn: it must be a positive comparison. */
9227 scc_comparison_operator (rtx op
, enum machine_mode mode
)
9229 return branch_positive_comparison_operator (op
, mode
);
9233 trap_comparison_operator (rtx op
, enum machine_mode mode
)
9235 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
9237 return COMPARISON_P (op
);
9241 boolean_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9243 enum rtx_code code
= GET_CODE (op
);
9244 return (code
== AND
|| code
== IOR
|| code
== XOR
);
9248 boolean_or_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9250 enum rtx_code code
= GET_CODE (op
);
9251 return (code
== IOR
|| code
== XOR
);
9255 min_max_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9257 enum rtx_code code
= GET_CODE (op
);
9258 return (code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
);
9261 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9262 mask required to convert the result of a rotate insn into a shift
9263 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9266 includes_lshift_p (rtx shiftop
, rtx andop
)
9268 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
9270 shift_mask
<<= INTVAL (shiftop
);
9272 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
9275 /* Similar, but for right shift. */
9278 includes_rshift_p (rtx shiftop
, rtx andop
)
9280 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
9282 shift_mask
>>= INTVAL (shiftop
);
9284 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
9287 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9288 to perform a left shift. It must have exactly SHIFTOP least
9289 significant 0's, then one or more 1's, then zero or more 0's. */
9292 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
9294 if (GET_CODE (andop
) == CONST_INT
)
9296 HOST_WIDE_INT c
, lsb
, shift_mask
;
9299 if (c
== 0 || c
== ~0)
9303 shift_mask
<<= INTVAL (shiftop
);
9305 /* Find the least significant one bit. */
9308 /* It must coincide with the LSB of the shift mask. */
9309 if (-lsb
!= shift_mask
)
9312 /* Invert to look for the next transition (if any). */
9315 /* Remove the low group of ones (originally low group of zeros). */
9318 /* Again find the lsb, and check we have all 1's above. */
9322 else if (GET_CODE (andop
) == CONST_DOUBLE
9323 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
9325 HOST_WIDE_INT low
, high
, lsb
;
9326 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
9328 low
= CONST_DOUBLE_LOW (andop
);
9329 if (HOST_BITS_PER_WIDE_INT
< 64)
9330 high
= CONST_DOUBLE_HIGH (andop
);
9332 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
9333 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
9336 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
9338 shift_mask_high
= ~0;
9339 if (INTVAL (shiftop
) > 32)
9340 shift_mask_high
<<= INTVAL (shiftop
) - 32;
9344 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
9351 return high
== -lsb
;
9354 shift_mask_low
= ~0;
9355 shift_mask_low
<<= INTVAL (shiftop
);
9359 if (-lsb
!= shift_mask_low
)
9362 if (HOST_BITS_PER_WIDE_INT
< 64)
9367 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
9370 return high
== -lsb
;
9374 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
9380 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9381 to perform a left shift. It must have SHIFTOP or more least
9382 significant 0's, with the remainder of the word 1's. */
9385 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
9387 if (GET_CODE (andop
) == CONST_INT
)
9389 HOST_WIDE_INT c
, lsb
, shift_mask
;
9392 shift_mask
<<= INTVAL (shiftop
);
9395 /* Find the least significant one bit. */
9398 /* It must be covered by the shift mask.
9399 This test also rejects c == 0. */
9400 if ((lsb
& shift_mask
) == 0)
9403 /* Check we have all 1's above the transition, and reject all 1's. */
9404 return c
== -lsb
&& lsb
!= 1;
9406 else if (GET_CODE (andop
) == CONST_DOUBLE
9407 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
9409 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
9411 low
= CONST_DOUBLE_LOW (andop
);
9413 if (HOST_BITS_PER_WIDE_INT
< 64)
9415 HOST_WIDE_INT high
, shift_mask_high
;
9417 high
= CONST_DOUBLE_HIGH (andop
);
9421 shift_mask_high
= ~0;
9422 if (INTVAL (shiftop
) > 32)
9423 shift_mask_high
<<= INTVAL (shiftop
) - 32;
9427 if ((lsb
& shift_mask_high
) == 0)
9430 return high
== -lsb
;
9436 shift_mask_low
= ~0;
9437 shift_mask_low
<<= INTVAL (shiftop
);
9441 if ((lsb
& shift_mask_low
) == 0)
9444 return low
== -lsb
&& lsb
!= 1;
9450 /* Return 1 if operands will generate a valid arguments to rlwimi
9451 instruction for insert with right shift in 64-bit mode. The mask may
9452 not start on the first bit or stop on the last bit because wrap-around
9453 effects of instruction do not correspond to semantics of RTL insn. */
9456 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
9458 if (INTVAL (startop
) < 64
9459 && INTVAL (startop
) > 32
9460 && (INTVAL (sizeop
) + INTVAL (startop
) < 64)
9461 && (INTVAL (sizeop
) + INTVAL (startop
) > 33)
9462 && (INTVAL (sizeop
) + INTVAL (startop
) + INTVAL (shiftop
) < 96)
9463 && (INTVAL (sizeop
) + INTVAL (startop
) + INTVAL (shiftop
) >= 64)
9464 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
9470 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9471 for lfq and stfq insns iff the registers are hard registers. */
9474 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
9476 /* We might have been passed a SUBREG. */
9477 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
9480 /* We might have been passed non floating point registers. */
9481 if (!FP_REGNO_P (REGNO (reg1
))
9482 || !FP_REGNO_P (REGNO (reg2
)))
9485 return (REGNO (reg1
) == REGNO (reg2
) - 1);
9488 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9489 addr1 and addr2 must be in consecutive memory locations
9490 (addr2 == addr1 + 8). */
9493 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
9499 /* The mems cannot be volatile. */
9500 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
9503 addr1
= XEXP (mem1
, 0);
9504 addr2
= XEXP (mem2
, 0);
9506 /* Extract an offset (if used) from the first addr. */
9507 if (GET_CODE (addr1
) == PLUS
)
9509 /* If not a REG, return zero. */
9510 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
9514 reg1
= REGNO (XEXP (addr1
, 0));
9515 /* The offset must be constant! */
9516 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
9518 offset1
= INTVAL (XEXP (addr1
, 1));
9521 else if (GET_CODE (addr1
) != REG
)
9525 reg1
= REGNO (addr1
);
9526 /* This was a simple (mem (reg)) expression. Offset is 0. */
9530 /* Make sure the second address is a (mem (plus (reg) (const_int)))
9531 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
9532 register as addr1. */
9533 if (offset1
== -8 && GET_CODE (addr2
) == REG
&& reg1
== REGNO (addr2
))
9535 if (GET_CODE (addr2
) != PLUS
)
9538 if (GET_CODE (XEXP (addr2
, 0)) != REG
9539 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
9542 if (reg1
!= REGNO (XEXP (addr2
, 0)))
9545 /* The offset for the second addr must be 8 more than the first addr. */
9546 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 8)
9549 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9554 /* Return the register class of a scratch register needed to copy IN into
9555 or out of a register in CLASS in MODE. If it can be done directly,
9556 NO_REGS is returned. */
9559 secondary_reload_class (enum reg_class
class,
9560 enum machine_mode mode ATTRIBUTE_UNUSED
,
9565 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
9567 && MACHOPIC_INDIRECT
9571 /* We cannot copy a symbolic operand directly into anything
9572 other than BASE_REGS for TARGET_ELF. So indicate that a
9573 register from BASE_REGS is needed as an intermediate
9576 On Darwin, pic addresses require a load from memory, which
9577 needs a base register. */
9578 if (class != BASE_REGS
9579 && (GET_CODE (in
) == SYMBOL_REF
9580 || GET_CODE (in
) == HIGH
9581 || GET_CODE (in
) == LABEL_REF
9582 || GET_CODE (in
) == CONST
))
9586 if (GET_CODE (in
) == REG
)
9589 if (regno
>= FIRST_PSEUDO_REGISTER
)
9591 regno
= true_regnum (in
);
9592 if (regno
>= FIRST_PSEUDO_REGISTER
)
9596 else if (GET_CODE (in
) == SUBREG
)
9598 regno
= true_regnum (in
);
9599 if (regno
>= FIRST_PSEUDO_REGISTER
)
9605 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9607 if (class == GENERAL_REGS
|| class == BASE_REGS
9608 || (regno
>= 0 && INT_REGNO_P (regno
)))
9611 /* Constants, memory, and FP registers can go into FP registers. */
9612 if ((regno
== -1 || FP_REGNO_P (regno
))
9613 && (class == FLOAT_REGS
|| class == NON_SPECIAL_REGS
))
9616 /* Memory, and AltiVec registers can go into AltiVec registers. */
9617 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
9618 && class == ALTIVEC_REGS
)
9621 /* We can copy among the CR registers. */
9622 if ((class == CR_REGS
|| class == CR0_REGS
)
9623 && regno
>= 0 && CR_REGNO_P (regno
))
9626 /* Otherwise, we need GENERAL_REGS. */
9627 return GENERAL_REGS
;
9630 /* Given a comparison operation, return the bit number in CCR to test. We
9631 know this is a valid comparison.
9633 SCC_P is 1 if this is for an scc. That means that %D will have been
9634 used instead of %C, so the bits will be in different places.
9636 Return -1 if OP isn't a valid comparison for some reason. */
9639 ccr_bit (rtx op
, int scc_p
)
9641 enum rtx_code code
= GET_CODE (op
);
9642 enum machine_mode cc_mode
;
9647 if (!COMPARISON_P (op
))
9652 if (GET_CODE (reg
) != REG
9653 || ! CR_REGNO_P (REGNO (reg
)))
9656 cc_mode
= GET_MODE (reg
);
9657 cc_regnum
= REGNO (reg
);
9658 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
9660 validate_condition_mode (code
, cc_mode
);
9662 /* When generating a sCOND operation, only positive conditions are
9664 if (scc_p
&& code
!= EQ
&& code
!= GT
&& code
!= LT
&& code
!= UNORDERED
9665 && code
!= GTU
&& code
!= LTU
)
9671 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
9673 return base_bit
+ 2;
9674 case GT
: case GTU
: case UNLE
:
9675 return base_bit
+ 1;
9676 case LT
: case LTU
: case UNGE
:
9678 case ORDERED
: case UNORDERED
:
9679 return base_bit
+ 3;
9682 /* If scc, we will have done a cror to put the bit in the
9683 unordered position. So test that bit. For integer, this is ! LT
9684 unless this is an scc insn. */
9685 return scc_p
? base_bit
+ 3 : base_bit
;
9688 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
9695 /* Return the GOT register. */
9698 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
9700 /* The second flow pass currently (June 1999) can't update
9701 regs_ever_live without disturbing other parts of the compiler, so
9702 update it here to make the prolog/epilogue code happy. */
9703 if (no_new_pseudos
&& ! regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
])
9704 regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9706 current_function_uses_pic_offset_table
= 1;
9708 return pic_offset_table_rtx
;
9711 /* Function to init struct machine_function.
9712 This will be called, via a pointer variable,
9713 from push_function_context. */
9715 static struct machine_function
*
9716 rs6000_init_machine_status (void)
9718 return ggc_alloc_cleared (sizeof (machine_function
));
9721 /* These macros test for integers and extract the low-order bits. */
9723 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9724 && GET_MODE (X) == VOIDmode)
9726 #define INT_LOWPART(X) \
9727 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9733 unsigned long val
= INT_LOWPART (op
);
9735 /* If the high bit is zero, the value is the first 1 bit we find
9737 if ((val
& 0x80000000) == 0)
9739 if ((val
& 0xffffffff) == 0)
9743 while (((val
<<= 1) & 0x80000000) == 0)
9748 /* If the high bit is set and the low bit is not, or the mask is all
9749 1's, the value is zero. */
9750 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
9753 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9756 while (((val
>>= 1) & 1) != 0)
9766 unsigned long val
= INT_LOWPART (op
);
9768 /* If the low bit is zero, the value is the first 1 bit we find from
9772 if ((val
& 0xffffffff) == 0)
9776 while (((val
>>= 1) & 1) == 0)
9782 /* If the low bit is set and the high bit is not, or the mask is all
9783 1's, the value is 31. */
9784 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
9787 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9790 while (((val
<<= 1) & 0x80000000) != 0)
9796 /* Locate some local-dynamic symbol still in use by this function
9797 so that we can print its name in some tls_ld pattern. */
9800 rs6000_get_some_local_dynamic_name (void)
9804 if (cfun
->machine
->some_ld_name
)
9805 return cfun
->machine
->some_ld_name
;
9807 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9809 && for_each_rtx (&PATTERN (insn
),
9810 rs6000_get_some_local_dynamic_name_1
, 0))
9811 return cfun
->machine
->some_ld_name
;
9816 /* Helper function for rs6000_get_some_local_dynamic_name. */
9819 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
9823 if (GET_CODE (x
) == SYMBOL_REF
)
9825 const char *str
= XSTR (x
, 0);
9826 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
9828 cfun
->machine
->some_ld_name
= str
;
9836 /* Write out a function code label. */
9839 rs6000_output_function_entry (FILE *file
, const char *fname
)
9841 if (fname
[0] != '.')
9843 switch (DEFAULT_ABI
)
9852 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
9861 RS6000_OUTPUT_BASENAME (file
, fname
);
9863 assemble_name (file
, fname
);
9866 /* Print an operand. Recognize special options, documented below. */
9869 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
9870 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
9872 #define SMALL_DATA_RELOC "sda21"
9873 #define SMALL_DATA_REG 0
9877 print_operand (FILE *file
, rtx x
, int code
)
9881 unsigned HOST_WIDE_INT uval
;
9886 /* Write out an instruction after the call which may be replaced
9887 with glue code by the loader. This depends on the AIX version. */
9888 asm_fprintf (file
, RS6000_CALL_GLUE
);
9891 /* %a is output_address. */
9894 /* If X is a constant integer whose low-order 5 bits are zero,
9895 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
9896 in the AIX assembler where "sri" with a zero shift count
9897 writes a trash instruction. */
9898 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
9905 /* If constant, low-order 16 bits of constant, unsigned.
9906 Otherwise, write normally. */
9908 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
9910 print_operand (file
, x
, 0);
9914 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9915 for 64-bit mask direction. */
9916 putc (((INT_LOWPART(x
) & 1) == 0 ? 'r' : 'l'), file
);
9919 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9923 /* X is a CR register. Print the number of the GT bit of the CR. */
9924 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
9925 output_operand_lossage ("invalid %%E value");
9927 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
9931 /* Like 'J' but get to the EQ bit. */
9932 if (GET_CODE (x
) != REG
)
9935 /* Bit 1 is EQ bit. */
9936 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 2;
9938 /* If we want bit 31, write a shift count of zero, not 32. */
9939 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
9943 /* X is a CR register. Print the number of the EQ bit of the CR */
9944 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
9945 output_operand_lossage ("invalid %%E value");
9947 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
9951 /* X is a CR register. Print the shift count needed to move it
9952 to the high-order four bits. */
9953 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
9954 output_operand_lossage ("invalid %%f value");
9956 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
9960 /* Similar, but print the count for the rotate in the opposite
9962 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
9963 output_operand_lossage ("invalid %%F value");
9965 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
9969 /* X is a constant integer. If it is negative, print "m",
9970 otherwise print "z". This is to make an aze or ame insn. */
9971 if (GET_CODE (x
) != CONST_INT
)
9972 output_operand_lossage ("invalid %%G value");
9973 else if (INTVAL (x
) >= 0)
9980 /* If constant, output low-order five bits. Otherwise, write
9983 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
9985 print_operand (file
, x
, 0);
9989 /* If constant, output low-order six bits. Otherwise, write
9992 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
9994 print_operand (file
, x
, 0);
9998 /* Print `i' if this is a constant, else nothing. */
10004 /* Write the bit number in CCR for jump. */
10005 i
= ccr_bit (x
, 0);
10007 output_operand_lossage ("invalid %%j code");
10009 fprintf (file
, "%d", i
);
10013 /* Similar, but add one for shift count in rlinm for scc and pass
10014 scc flag to `ccr_bit'. */
10015 i
= ccr_bit (x
, 1);
10017 output_operand_lossage ("invalid %%J code");
10019 /* If we want bit 31, write a shift count of zero, not 32. */
10020 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
10024 /* X must be a constant. Write the 1's complement of the
10027 output_operand_lossage ("invalid %%k value");
10029 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
10033 /* X must be a symbolic constant on ELF. Write an
10034 expression suitable for an 'addi' that adds in the low 16
10035 bits of the MEM. */
10036 if (GET_CODE (x
) != CONST
)
10038 print_operand_address (file
, x
);
10039 fputs ("@l", file
);
10043 if (GET_CODE (XEXP (x
, 0)) != PLUS
10044 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
10045 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
10046 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
10047 output_operand_lossage ("invalid %%K value");
10048 print_operand_address (file
, XEXP (XEXP (x
, 0), 0));
10049 fputs ("@l", file
);
10050 /* For GNU as, there must be a non-alphanumeric character
10051 between 'l' and the number. The '-' is added by
10052 print_operand() already. */
10053 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
10055 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
10059 /* %l is output_asm_label. */
10062 /* Write second word of DImode or DFmode reference. Works on register
10063 or non-indexed memory only. */
10064 if (GET_CODE (x
) == REG
)
10065 fputs (reg_names
[REGNO (x
) + 1], file
);
10066 else if (GET_CODE (x
) == MEM
)
10068 /* Handle possible auto-increment. Since it is pre-increment and
10069 we have already done it, we can just use an offset of word. */
10070 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
10071 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10072 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
10075 output_address (XEXP (adjust_address_nv (x
, SImode
,
10079 if (small_data_operand (x
, GET_MODE (x
)))
10080 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10081 reg_names
[SMALL_DATA_REG
]);
10086 /* MB value for a mask operand. */
10087 if (! mask_operand (x
, SImode
))
10088 output_operand_lossage ("invalid %%m value");
10090 fprintf (file
, "%d", extract_MB (x
));
10094 /* ME value for a mask operand. */
10095 if (! mask_operand (x
, SImode
))
10096 output_operand_lossage ("invalid %%M value");
10098 fprintf (file
, "%d", extract_ME (x
));
10101 /* %n outputs the negative of its operand. */
10104 /* Write the number of elements in the vector times 4. */
10105 if (GET_CODE (x
) != PARALLEL
)
10106 output_operand_lossage ("invalid %%N value");
10108 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
10112 /* Similar, but subtract 1 first. */
10113 if (GET_CODE (x
) != PARALLEL
)
10114 output_operand_lossage ("invalid %%O value");
10116 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
10120 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10122 || INT_LOWPART (x
) < 0
10123 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
10124 output_operand_lossage ("invalid %%p value");
10126 fprintf (file
, "%d", i
);
10130 /* The operand must be an indirect memory reference. The result
10131 is the register name. */
10132 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
10133 || REGNO (XEXP (x
, 0)) >= 32)
10134 output_operand_lossage ("invalid %%P value");
10136 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
10140 /* This outputs the logical code corresponding to a boolean
10141 expression. The expression may have one or both operands
10142 negated (if one, only the first one). For condition register
10143 logical operations, it will also treat the negated
10144 CR codes as NOTs, but not handle NOTs of them. */
10146 const char *const *t
= 0;
10148 enum rtx_code code
= GET_CODE (x
);
10149 static const char * const tbl
[3][3] = {
10150 { "and", "andc", "nor" },
10151 { "or", "orc", "nand" },
10152 { "xor", "eqv", "xor" } };
10156 else if (code
== IOR
)
10158 else if (code
== XOR
)
10161 output_operand_lossage ("invalid %%q value");
10163 if (GET_CODE (XEXP (x
, 0)) != NOT
)
10167 if (GET_CODE (XEXP (x
, 1)) == NOT
)
10185 /* X is a CR register. Print the mask for `mtcrf'. */
10186 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10187 output_operand_lossage ("invalid %%R value");
10189 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
10193 /* Low 5 bits of 32 - value */
10195 output_operand_lossage ("invalid %%s value");
10197 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
10201 /* PowerPC64 mask position. All 0's is excluded.
10202 CONST_INT 32-bit mask is considered sign-extended so any
10203 transition must occur within the CONST_INT, not on the boundary. */
10204 if (! mask64_operand (x
, DImode
))
10205 output_operand_lossage ("invalid %%S value");
10207 uval
= INT_LOWPART (x
);
10209 if (uval
& 1) /* Clear Left */
10211 #if HOST_BITS_PER_WIDE_INT > 64
10212 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
10216 else /* Clear Right */
10219 #if HOST_BITS_PER_WIDE_INT > 64
10220 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
10228 fprintf (file
, "%d", i
);
10232 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10233 if (GET_CODE (x
) != REG
|| GET_MODE (x
) != CCmode
)
10236 /* Bit 3 is OV bit. */
10237 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
10239 /* If we want bit 31, write a shift count of zero, not 32. */
10240 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
10244 /* Print the symbolic name of a branch target register. */
10245 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LINK_REGISTER_REGNUM
10246 && REGNO (x
) != COUNT_REGISTER_REGNUM
))
10247 output_operand_lossage ("invalid %%T value");
10248 else if (REGNO (x
) == LINK_REGISTER_REGNUM
)
10249 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
10251 fputs ("ctr", file
);
10255 /* High-order 16 bits of constant for use in unsigned operand. */
10257 output_operand_lossage ("invalid %%u value");
10259 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
10260 (INT_LOWPART (x
) >> 16) & 0xffff);
10264 /* High-order 16 bits of constant for use in signed operand. */
10266 output_operand_lossage ("invalid %%v value");
10268 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
10269 (INT_LOWPART (x
) >> 16) & 0xffff);
10273 /* Print `u' if this has an auto-increment or auto-decrement. */
10274 if (GET_CODE (x
) == MEM
10275 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
10276 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
))
10281 /* Print the trap code for this operand. */
10282 switch (GET_CODE (x
))
10285 fputs ("eq", file
); /* 4 */
10288 fputs ("ne", file
); /* 24 */
10291 fputs ("lt", file
); /* 16 */
10294 fputs ("le", file
); /* 20 */
10297 fputs ("gt", file
); /* 8 */
10300 fputs ("ge", file
); /* 12 */
10303 fputs ("llt", file
); /* 2 */
10306 fputs ("lle", file
); /* 6 */
10309 fputs ("lgt", file
); /* 1 */
10312 fputs ("lge", file
); /* 5 */
10320 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10323 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
10324 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
10326 print_operand (file
, x
, 0);
10330 /* MB value for a PowerPC64 rldic operand. */
10331 val
= (GET_CODE (x
) == CONST_INT
10332 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
10337 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
10338 if ((val
<<= 1) < 0)
10341 #if HOST_BITS_PER_WIDE_INT == 32
10342 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
10343 i
+= 32; /* zero-extend high-part was all 0's */
10344 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
10346 val
= CONST_DOUBLE_LOW (x
);
10353 for ( ; i
< 64; i
++)
10354 if ((val
<<= 1) < 0)
10359 fprintf (file
, "%d", i
+ 1);
10363 if (GET_CODE (x
) == MEM
10364 && legitimate_indexed_address_p (XEXP (x
, 0), 0))
10369 /* Like 'L', for third word of TImode */
10370 if (GET_CODE (x
) == REG
)
10371 fputs (reg_names
[REGNO (x
) + 2], file
);
10372 else if (GET_CODE (x
) == MEM
)
10374 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
10375 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10376 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
10378 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
10379 if (small_data_operand (x
, GET_MODE (x
)))
10380 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10381 reg_names
[SMALL_DATA_REG
]);
10386 /* X is a SYMBOL_REF. Write out the name preceded by a
10387 period and without any trailing data in brackets. Used for function
10388 names. If we are configured for System V (or the embedded ABI) on
10389 the PowerPC, do not emit the period, since those systems do not use
10390 TOCs and the like. */
10391 if (GET_CODE (x
) != SYMBOL_REF
)
10394 /* Mark the decl as referenced so that cgraph will output the function. */
10395 if (SYMBOL_REF_DECL (x
))
10396 mark_decl_referenced (SYMBOL_REF_DECL (x
));
10398 /* For macho, check to see if we need a stub. */
10401 const char *name
= XSTR (x
, 0);
10403 if (MACHOPIC_INDIRECT
10404 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
10405 name
= machopic_indirection_name (x
, /*stub_p=*/true);
10407 assemble_name (file
, name
);
10409 else if (!DOT_SYMBOLS
)
10410 assemble_name (file
, XSTR (x
, 0));
10412 rs6000_output_function_entry (file
, XSTR (x
, 0));
10416 /* Like 'L', for last word of TImode. */
10417 if (GET_CODE (x
) == REG
)
10418 fputs (reg_names
[REGNO (x
) + 3], file
);
10419 else if (GET_CODE (x
) == MEM
)
10421 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
10422 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10423 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
10425 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
10426 if (small_data_operand (x
, GET_MODE (x
)))
10427 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10428 reg_names
[SMALL_DATA_REG
]);
10432 /* Print AltiVec or SPE memory operand. */
10437 if (GET_CODE (x
) != MEM
)
10444 /* Handle [reg]. */
10445 if (GET_CODE (tmp
) == REG
)
10447 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
10450 /* Handle [reg+UIMM]. */
10451 else if (GET_CODE (tmp
) == PLUS
&&
10452 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
10456 if (GET_CODE (XEXP (tmp
, 0)) != REG
)
10459 x
= INTVAL (XEXP (tmp
, 1));
10460 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
10464 /* Fall through. Must be [reg+reg]. */
10466 if (GET_CODE (tmp
) == REG
)
10467 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
10468 else if (GET_CODE (tmp
) == PLUS
&& GET_CODE (XEXP (tmp
, 1)) == REG
)
10470 if (REGNO (XEXP (tmp
, 0)) == 0)
10471 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
10472 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
10474 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
10475 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
10483 if (GET_CODE (x
) == REG
)
10484 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
10485 else if (GET_CODE (x
) == MEM
)
10487 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10488 know the width from the mode. */
10489 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
10490 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
10491 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
10492 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10493 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
10494 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
10496 output_address (XEXP (x
, 0));
10499 output_addr_const (file
, x
);
10503 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
10507 output_operand_lossage ("invalid %%xn code");
10511 /* Print the address of an operand. */
10514 print_operand_address (FILE *file
, rtx x
)
10516 if (GET_CODE (x
) == REG
)
10517 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
10518 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
10519 || GET_CODE (x
) == LABEL_REF
)
10521 output_addr_const (file
, x
);
10522 if (small_data_operand (x
, GET_MODE (x
)))
10523 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10524 reg_names
[SMALL_DATA_REG
]);
10525 else if (TARGET_TOC
)
10528 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
10530 if (REGNO (XEXP (x
, 0)) == 0)
10531 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
10532 reg_names
[ REGNO (XEXP (x
, 0)) ]);
10534 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
10535 reg_names
[ REGNO (XEXP (x
, 1)) ]);
10537 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
10538 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
10539 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
10541 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
10542 && CONSTANT_P (XEXP (x
, 1)))
10544 output_addr_const (file
, XEXP (x
, 1));
10545 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
10549 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
10550 && CONSTANT_P (XEXP (x
, 1)))
10552 fprintf (file
, "lo16(");
10553 output_addr_const (file
, XEXP (x
, 1));
10554 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
10557 else if (legitimate_constant_pool_address_p (x
))
10559 if (TARGET_AIX
&& (!TARGET_ELF
|| !TARGET_MINIMAL_TOC
))
10561 rtx contains_minus
= XEXP (x
, 1);
10565 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10566 turn it into (sym) for output_addr_const. */
10567 while (GET_CODE (XEXP (contains_minus
, 0)) != MINUS
)
10568 contains_minus
= XEXP (contains_minus
, 0);
10570 minus
= XEXP (contains_minus
, 0);
10571 symref
= XEXP (minus
, 0);
10572 XEXP (contains_minus
, 0) = symref
;
10577 name
= XSTR (symref
, 0);
10578 newname
= alloca (strlen (name
) + sizeof ("@toc"));
10579 strcpy (newname
, name
);
10580 strcat (newname
, "@toc");
10581 XSTR (symref
, 0) = newname
;
10583 output_addr_const (file
, XEXP (x
, 1));
10585 XSTR (symref
, 0) = name
;
10586 XEXP (contains_minus
, 0) = minus
;
10589 output_addr_const (file
, XEXP (x
, 1));
10591 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
10597 /* Target hook for assembling integer objects. The PowerPC version has
10598 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10599 is defined. It also needs to handle DI-mode objects on 64-bit
10603 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
10605 #ifdef RELOCATABLE_NEEDS_FIXUP
10606 /* Special handling for SI values. */
10607 if (size
== 4 && aligned_p
)
10609 extern int in_toc_section (void);
10610 static int recurse
= 0;
10612 /* For -mrelocatable, we mark all addresses that need to be fixed up
10613 in the .fixup section. */
10614 if (TARGET_RELOCATABLE
10615 && !in_toc_section ()
10616 && !in_text_section ()
10617 && !in_unlikely_text_section ()
10619 && GET_CODE (x
) != CONST_INT
10620 && GET_CODE (x
) != CONST_DOUBLE
10626 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
10628 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
10629 fprintf (asm_out_file
, "\t.long\t(");
10630 output_addr_const (asm_out_file
, x
);
10631 fprintf (asm_out_file
, ")@fixup\n");
10632 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
10633 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
10634 fprintf (asm_out_file
, "\t.long\t");
10635 assemble_name (asm_out_file
, buf
);
10636 fprintf (asm_out_file
, "\n\t.previous\n");
10640 /* Remove initial .'s to turn a -mcall-aixdesc function
10641 address into the address of the descriptor, not the function
10643 else if (GET_CODE (x
) == SYMBOL_REF
10644 && XSTR (x
, 0)[0] == '.'
10645 && DEFAULT_ABI
== ABI_AIX
)
10647 const char *name
= XSTR (x
, 0);
10648 while (*name
== '.')
10651 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
10655 #endif /* RELOCATABLE_NEEDS_FIXUP */
10656 return default_assemble_integer (x
, size
, aligned_p
);
10659 #ifdef HAVE_GAS_HIDDEN
10660 /* Emit an assembler directive to set symbol visibility for DECL to
10661 VISIBILITY_TYPE. */
10664 rs6000_assemble_visibility (tree decl
, int vis
)
10666 /* Functions need to have their entry point symbol visibility set as
10667 well as their descriptor symbol visibility. */
10668 if (DEFAULT_ABI
== ABI_AIX
10670 && TREE_CODE (decl
) == FUNCTION_DECL
)
10672 static const char * const visibility_types
[] = {
10673 NULL
, "internal", "hidden", "protected"
10676 const char *name
, *type
;
10678 name
= ((* targetm
.strip_name_encoding
)
10679 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
10680 type
= visibility_types
[vis
];
10682 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
10683 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
10686 default_assemble_visibility (decl
, vis
);
10691 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
10693 /* Reversal of FP compares takes care -- an ordered compare
10694 becomes an unordered compare and vice versa. */
10695 if (mode
== CCFPmode
10696 && (!flag_finite_math_only
10697 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
10698 || code
== UNEQ
|| code
== LTGT
))
10699 return reverse_condition_maybe_unordered (code
);
10701 return reverse_condition (code
);
10704 /* Generate a compare for CODE. Return a brand-new rtx that
10705 represents the result of the compare. */
10708 rs6000_generate_compare (enum rtx_code code
)
10710 enum machine_mode comp_mode
;
10711 rtx compare_result
;
10713 if (rs6000_compare_fp_p
)
10714 comp_mode
= CCFPmode
;
10715 else if (code
== GTU
|| code
== LTU
10716 || code
== GEU
|| code
== LEU
)
10717 comp_mode
= CCUNSmode
;
10719 comp_mode
= CCmode
;
10721 /* First, the compare. */
10722 compare_result
= gen_reg_rtx (comp_mode
);
10724 /* SPE FP compare instructions on the GPRs. Yuck! */
10725 if ((TARGET_E500
&& !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
10726 && rs6000_compare_fp_p
)
10728 rtx cmp
, or1
, or2
, or_result
, compare_result2
;
10730 /* Note: The E500 comparison instructions set the GT bit (x +
10731 1), on success. This explains the mess. */
10735 case EQ
: case UNEQ
: case NE
: case LTGT
:
10736 cmp
= flag_finite_math_only
10737 ? gen_tstsfeq_gpr (compare_result
, rs6000_compare_op0
,
10738 rs6000_compare_op1
)
10739 : gen_cmpsfeq_gpr (compare_result
, rs6000_compare_op0
,
10740 rs6000_compare_op1
);
10742 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
10743 cmp
= flag_finite_math_only
10744 ? gen_tstsfgt_gpr (compare_result
, rs6000_compare_op0
,
10745 rs6000_compare_op1
)
10746 : gen_cmpsfgt_gpr (compare_result
, rs6000_compare_op0
,
10747 rs6000_compare_op1
);
10749 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
10750 cmp
= flag_finite_math_only
10751 ? gen_tstsflt_gpr (compare_result
, rs6000_compare_op0
,
10752 rs6000_compare_op1
)
10753 : gen_cmpsflt_gpr (compare_result
, rs6000_compare_op0
,
10754 rs6000_compare_op1
);
10760 /* Synthesize LE and GE from LT/GT || EQ. */
10761 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
10767 case LE
: code
= LT
; break;
10768 case GE
: code
= GT
; break;
10769 case LEU
: code
= LT
; break;
10770 case GEU
: code
= GT
; break;
10774 or1
= gen_reg_rtx (SImode
);
10775 or2
= gen_reg_rtx (SImode
);
10776 or_result
= gen_reg_rtx (CCEQmode
);
10777 compare_result2
= gen_reg_rtx (CCFPmode
);
10780 cmp
= flag_finite_math_only
10781 ? gen_tstsfeq_gpr (compare_result2
, rs6000_compare_op0
,
10782 rs6000_compare_op1
)
10783 : gen_cmpsfeq_gpr (compare_result2
, rs6000_compare_op0
,
10784 rs6000_compare_op1
);
10787 or1
= gen_rtx_GT (SImode
, compare_result
, const0_rtx
);
10788 or2
= gen_rtx_GT (SImode
, compare_result2
, const0_rtx
);
10790 /* OR them together. */
10791 cmp
= gen_rtx_SET (VOIDmode
, or_result
,
10792 gen_rtx_COMPARE (CCEQmode
,
10793 gen_rtx_IOR (SImode
, or1
, or2
),
10795 compare_result
= or_result
;
10800 if (code
== NE
|| code
== LTGT
)
10809 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
10810 gen_rtx_COMPARE (comp_mode
,
10811 rs6000_compare_op0
,
10812 rs6000_compare_op1
)));
10814 /* Some kinds of FP comparisons need an OR operation;
10815 under flag_finite_math_only we don't bother. */
10816 if (rs6000_compare_fp_p
10817 && ! flag_finite_math_only
10818 && ! (TARGET_HARD_FLOAT
&& TARGET_E500
&& !TARGET_FPRS
)
10819 && (code
== LE
|| code
== GE
10820 || code
== UNEQ
|| code
== LTGT
10821 || code
== UNGT
|| code
== UNLT
))
10823 enum rtx_code or1
, or2
;
10824 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
10825 rtx or_result
= gen_reg_rtx (CCEQmode
);
10829 case LE
: or1
= LT
; or2
= EQ
; break;
10830 case GE
: or1
= GT
; or2
= EQ
; break;
10831 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
10832 case LTGT
: or1
= LT
; or2
= GT
; break;
10833 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
10834 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
10837 validate_condition_mode (or1
, comp_mode
);
10838 validate_condition_mode (or2
, comp_mode
);
10839 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
10840 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
10841 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
10842 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
10844 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
10846 compare_result
= or_result
;
10850 validate_condition_mode (code
, GET_MODE (compare_result
));
10852 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
10856 /* Emit the RTL for an sCOND pattern. */
10859 rs6000_emit_sCOND (enum rtx_code code
, rtx result
)
10862 enum machine_mode op_mode
;
10863 enum rtx_code cond_code
;
10865 condition_rtx
= rs6000_generate_compare (code
);
10866 cond_code
= GET_CODE (condition_rtx
);
10868 if (TARGET_E500
&& rs6000_compare_fp_p
10869 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
10873 PUT_MODE (condition_rtx
, SImode
);
10874 t
= XEXP (condition_rtx
, 0);
10876 if (cond_code
!= NE
&& cond_code
!= EQ
)
10879 if (cond_code
== NE
)
10880 emit_insn (gen_e500_flip_eq_bit (t
, t
));
10882 emit_insn (gen_move_from_CR_eq_bit (result
, t
));
10886 if (cond_code
== NE
10887 || cond_code
== GE
|| cond_code
== LE
10888 || cond_code
== GEU
|| cond_code
== LEU
10889 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
10891 rtx not_result
= gen_reg_rtx (CCEQmode
);
10892 rtx not_op
, rev_cond_rtx
;
10893 enum machine_mode cc_mode
;
10895 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
10897 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
10898 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
10899 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
10900 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
10901 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
10904 op_mode
= GET_MODE (rs6000_compare_op0
);
10905 if (op_mode
== VOIDmode
)
10906 op_mode
= GET_MODE (rs6000_compare_op1
);
10908 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| rs6000_compare_fp_p
))
10910 PUT_MODE (condition_rtx
, DImode
);
10911 convert_move (result
, condition_rtx
, 0);
10915 PUT_MODE (condition_rtx
, SImode
);
10916 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
10920 /* Emit a branch of kind CODE to location LOC. */
10923 rs6000_emit_cbranch (enum rtx_code code
, rtx loc
)
10925 rtx condition_rtx
, loc_ref
;
10927 condition_rtx
= rs6000_generate_compare (code
);
10928 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, loc
);
10929 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
10930 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
10931 loc_ref
, pc_rtx
)));
10934 /* Return the string to output a conditional branch to LABEL, which is
10935 the operand number of the label, or -1 if the branch is really a
10936 conditional return.
10938 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10939 condition code register and its mode specifies what kind of
10940 comparison we made.
10942 REVERSED is nonzero if we should reverse the sense of the comparison.
10944 INSN is the insn. */
10947 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
10949 static char string
[64];
10950 enum rtx_code code
= GET_CODE (op
);
10951 rtx cc_reg
= XEXP (op
, 0);
10952 enum machine_mode mode
= GET_MODE (cc_reg
);
10953 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
10954 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
10955 int really_reversed
= reversed
^ need_longbranch
;
10961 validate_condition_mode (code
, mode
);
10963 /* Work out which way this really branches. We could use
10964 reverse_condition_maybe_unordered here always but this
10965 makes the resulting assembler clearer. */
10966 if (really_reversed
)
10968 /* Reversal of FP compares takes care -- an ordered compare
10969 becomes an unordered compare and vice versa. */
10970 if (mode
== CCFPmode
)
10971 code
= reverse_condition_maybe_unordered (code
);
10973 code
= reverse_condition (code
);
10976 if ((TARGET_E500
&& !TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
10978 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10981 /* Opposite of GT. */
10983 else if (code
== NE
)
10991 /* Not all of these are actually distinct opcodes, but
10992 we distinguish them for clarity of the resulting assembler. */
10993 case NE
: case LTGT
:
10994 ccode
= "ne"; break;
10995 case EQ
: case UNEQ
:
10996 ccode
= "eq"; break;
10998 ccode
= "ge"; break;
10999 case GT
: case GTU
: case UNGT
:
11000 ccode
= "gt"; break;
11002 ccode
= "le"; break;
11003 case LT
: case LTU
: case UNLT
:
11004 ccode
= "lt"; break;
11005 case UNORDERED
: ccode
= "un"; break;
11006 case ORDERED
: ccode
= "nu"; break;
11007 case UNGE
: ccode
= "nl"; break;
11008 case UNLE
: ccode
= "ng"; break;
11013 /* Maybe we have a guess as to how likely the branch is.
11014 The old mnemonics don't have a way to specify this information. */
11016 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
11017 if (note
!= NULL_RTX
)
11019 /* PROB is the difference from 50%. */
11020 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
11022 /* Only hint for highly probable/improbable branches on newer
11023 cpus as static prediction overrides processor dynamic
11024 prediction. For older cpus we may as well always hint, but
11025 assume not taken for branches that are very close to 50% as a
11026 mispredicted taken branch is more expensive than a
11027 mispredicted not-taken branch. */
11028 if (rs6000_always_hint
11029 || abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48)
11031 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
11032 && ((prob
> 0) ^ need_longbranch
))
11040 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
11042 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
11044 /* We need to escape any '%' characters in the reg_names string.
11045 Assume they'd only be the first character.... */
11046 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
11048 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
11052 /* If the branch distance was too far, we may have to use an
11053 unconditional branch to go the distance. */
11054 if (need_longbranch
)
11055 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
11057 s
+= sprintf (s
, ",%s", label
);
11063 /* Return the string to flip the EQ bit on a CR. */
11065 output_e500_flip_eq_bit (rtx dst
, rtx src
)
11067 static char string
[64];
11070 if (GET_CODE (dst
) != REG
|| ! CR_REGNO_P (REGNO (dst
))
11071 || GET_CODE (src
) != REG
|| ! CR_REGNO_P (REGNO (src
)))
11075 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 2;
11076 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 2;
11078 sprintf (string
, "crnot %d,%d", a
, b
);
11082 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11083 operands of the last comparison is nonzero/true, FALSE_COND if it
11084 is zero/false. Return 0 if the hardware has no such operation. */
11087 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
11089 enum rtx_code code
= GET_CODE (op
);
11090 rtx op0
= rs6000_compare_op0
;
11091 rtx op1
= rs6000_compare_op1
;
11092 REAL_VALUE_TYPE c1
;
11093 enum machine_mode compare_mode
= GET_MODE (op0
);
11094 enum machine_mode result_mode
= GET_MODE (dest
);
11097 /* These modes should always match. */
11098 if (GET_MODE (op1
) != compare_mode
11099 /* In the isel case however, we can use a compare immediate, so
11100 op1 may be a small constant. */
11101 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
11103 if (GET_MODE (true_cond
) != result_mode
)
11105 if (GET_MODE (false_cond
) != result_mode
)
11108 /* First, work out if the hardware can do this at all, or
11109 if it's too slow.... */
11110 if (! rs6000_compare_fp_p
)
11113 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
11116 else if (TARGET_E500
&& TARGET_HARD_FLOAT
&& !TARGET_FPRS
11117 && GET_MODE_CLASS (compare_mode
) == MODE_FLOAT
)
11120 /* Eliminate half of the comparisons by switching operands, this
11121 makes the remaining code simpler. */
11122 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
11123 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
11125 code
= reverse_condition_maybe_unordered (code
);
11127 true_cond
= false_cond
;
11131 /* UNEQ and LTGT take four instructions for a comparison with zero,
11132 it'll probably be faster to use a branch here too. */
11133 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
11136 if (GET_CODE (op1
) == CONST_DOUBLE
)
11137 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
11139 /* We're going to try to implement comparisons by performing
11140 a subtract, then comparing against zero. Unfortunately,
11141 Inf - Inf is NaN which is not zero, and so if we don't
11142 know that the operand is finite and the comparison
11143 would treat EQ different to UNORDERED, we can't do it. */
11144 if (HONOR_INFINITIES (compare_mode
)
11145 && code
!= GT
&& code
!= UNGE
11146 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
11147 /* Constructs of the form (a OP b ? a : b) are safe. */
11148 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
11149 || (! rtx_equal_p (op0
, true_cond
)
11150 && ! rtx_equal_p (op1
, true_cond
))))
11152 /* At this point we know we can use fsel. */
11154 /* Reduce the comparison to a comparison against zero. */
11155 temp
= gen_reg_rtx (compare_mode
);
11156 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
11157 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
11159 op1
= CONST0_RTX (compare_mode
);
11161 /* If we don't care about NaNs we can reduce some of the comparisons
11162 down to faster ones. */
11163 if (! HONOR_NANS (compare_mode
))
11169 true_cond
= false_cond
;
11182 /* Now, reduce everything down to a GE. */
11189 temp
= gen_reg_rtx (compare_mode
);
11190 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
11195 temp
= gen_reg_rtx (compare_mode
);
11196 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
11201 temp
= gen_reg_rtx (compare_mode
);
11202 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
11203 gen_rtx_NEG (compare_mode
,
11204 gen_rtx_ABS (compare_mode
, op0
))));
11209 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11210 temp
= gen_reg_rtx (result_mode
);
11211 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
11212 gen_rtx_IF_THEN_ELSE (result_mode
,
11213 gen_rtx_GE (VOIDmode
,
11215 true_cond
, false_cond
)));
11216 false_cond
= true_cond
;
11219 temp
= gen_reg_rtx (compare_mode
);
11220 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
11225 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11226 temp
= gen_reg_rtx (result_mode
);
11227 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
11228 gen_rtx_IF_THEN_ELSE (result_mode
,
11229 gen_rtx_GE (VOIDmode
,
11231 true_cond
, false_cond
)));
11232 true_cond
= false_cond
;
11235 temp
= gen_reg_rtx (compare_mode
);
11236 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
11244 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
11245 gen_rtx_IF_THEN_ELSE (result_mode
,
11246 gen_rtx_GE (VOIDmode
,
11248 true_cond
, false_cond
)));
11252 /* Same as above, but for ints (isel). */
11255 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
11257 rtx condition_rtx
, cr
;
11259 /* All isel implementations thus far are 32-bits. */
11260 if (GET_MODE (rs6000_compare_op0
) != SImode
)
11263 /* We still have to do the compare, because isel doesn't do a
11264 compare, it just looks at the CRx bits set by a previous compare
11266 condition_rtx
= rs6000_generate_compare (GET_CODE (op
));
11267 cr
= XEXP (condition_rtx
, 0);
11269 if (GET_MODE (cr
) == CCmode
)
11270 emit_insn (gen_isel_signed (dest
, condition_rtx
,
11271 true_cond
, false_cond
, cr
));
11273 emit_insn (gen_isel_unsigned (dest
, condition_rtx
,
11274 true_cond
, false_cond
, cr
));
11280 output_isel (rtx
*operands
)
11282 enum rtx_code code
;
11284 code
= GET_CODE (operands
[1]);
11285 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
11287 PUT_CODE (operands
[1], reverse_condition (code
));
11288 return "isel %0,%3,%2,%j1";
11291 return "isel %0,%2,%3,%j1";
11295 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
11297 enum machine_mode mode
= GET_MODE (op0
);
11301 if (code
== SMAX
|| code
== SMIN
)
11306 if (code
== SMAX
|| code
== UMAX
)
11307 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
11308 op0
, op1
, mode
, 0);
11310 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
11311 op1
, op0
, mode
, 0);
11312 if (target
== NULL_RTX
)
11314 if (target
!= dest
)
11315 emit_move_insn (dest
, target
);
11318 /* Emit instructions to move SRC to DST. Called by splitters for
11319 multi-register moves. It will emit at most one instruction for
11320 each register that is accessed; that is, it won't emit li/lis pairs
11321 (or equivalent for 64-bit code). One of SRC or DST must be a hard
11325 rs6000_split_multireg_move (rtx dst
, rtx src
)
11327 /* The register number of the first register being moved. */
11329 /* The mode that is to be moved. */
11330 enum machine_mode mode
;
11331 /* The mode that the move is being done in, and its size. */
11332 enum machine_mode reg_mode
;
11334 /* The number of registers that will be moved. */
11337 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
11338 mode
= GET_MODE (dst
);
11339 nregs
= HARD_REGNO_NREGS (reg
, mode
);
11340 if (FP_REGNO_P (reg
))
11342 else if (ALTIVEC_REGNO_P (reg
))
11343 reg_mode
= V16QImode
;
11345 reg_mode
= word_mode
;
11346 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
11348 if (reg_mode_size
* nregs
!= GET_MODE_SIZE (mode
))
11351 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
11353 /* Move register range backwards, if we might have destructive
11356 for (i
= nregs
- 1; i
>= 0; i
--)
11357 emit_insn (gen_rtx_SET (VOIDmode
,
11358 simplify_gen_subreg (reg_mode
, dst
, mode
,
11359 i
* reg_mode_size
),
11360 simplify_gen_subreg (reg_mode
, src
, mode
,
11361 i
* reg_mode_size
)));
11367 bool used_update
= false;
11369 if (MEM_P (src
) && INT_REGNO_P (reg
))
11373 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
11374 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
11377 breg
= XEXP (XEXP (src
, 0), 0);
11378 delta_rtx
= GET_CODE (XEXP (src
, 0)) == PRE_INC
11379 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
11380 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
)));
11381 emit_insn (TARGET_32BIT
11382 ? gen_addsi3 (breg
, breg
, delta_rtx
)
11383 : gen_adddi3 (breg
, breg
, delta_rtx
));
11384 src
= gen_rtx_MEM (mode
, breg
);
11386 else if (! offsettable_memref_p (src
))
11388 rtx newsrc
, basereg
;
11389 basereg
= gen_rtx_REG (Pmode
, reg
);
11390 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
11391 newsrc
= gen_rtx_MEM (GET_MODE (src
), basereg
);
11392 MEM_COPY_ATTRIBUTES (newsrc
, src
);
11396 breg
= XEXP (src
, 0);
11397 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
11398 breg
= XEXP (breg
, 0);
11400 /* If the base register we are using to address memory is
11401 also a destination reg, then change that register last. */
11403 && REGNO (breg
) >= REGNO (dst
)
11404 && REGNO (breg
) < REGNO (dst
) + nregs
)
11405 j
= REGNO (breg
) - REGNO (dst
);
11408 if (GET_CODE (dst
) == MEM
&& INT_REGNO_P (reg
))
11412 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
11413 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
11416 breg
= XEXP (XEXP (dst
, 0), 0);
11417 delta_rtx
= GET_CODE (XEXP (dst
, 0)) == PRE_INC
11418 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
11419 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
)));
11421 /* We have to update the breg before doing the store.
11422 Use store with update, if available. */
11426 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
11427 emit_insn (TARGET_32BIT
11428 ? (TARGET_POWERPC64
11429 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
11430 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
11431 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
11432 used_update
= true;
11435 emit_insn (TARGET_32BIT
11436 ? gen_addsi3 (breg
, breg
, delta_rtx
)
11437 : gen_adddi3 (breg
, breg
, delta_rtx
));
11438 dst
= gen_rtx_MEM (mode
, breg
);
11440 else if (! offsettable_memref_p (dst
))
11444 for (i
= 0; i
< nregs
; i
++)
11446 /* Calculate index to next subword. */
11451 /* If compiler already emitted move of first word by
11452 store with update, no need to do anything. */
11453 if (j
== 0 && used_update
)
11456 emit_insn (gen_rtx_SET (VOIDmode
,
11457 simplify_gen_subreg (reg_mode
, dst
, mode
,
11458 j
* reg_mode_size
),
11459 simplify_gen_subreg (reg_mode
, src
, mode
,
11460 j
* reg_mode_size
)));
11466 /* This page contains routines that are used to determine what the
11467 function prologue and epilogue code will do and write them out. */
11469 /* Return the first fixed-point register that is required to be
11470 saved. 32 if none. */
11473 first_reg_to_save (void)
11477 /* Find lowest numbered live register. */
11478 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
11479 if (regs_ever_live
[first_reg
]
11480 && (! call_used_regs
[first_reg
]
11481 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
11482 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
11483 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
11484 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
11489 && current_function_uses_pic_offset_table
11490 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
11491 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
11497 /* Similar, for FP regs. */
11500 first_fp_reg_to_save (void)
11504 /* Find lowest numbered live register. */
11505 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
11506 if (regs_ever_live
[first_reg
])
11512 /* Similar, for AltiVec regs. */
11515 first_altivec_reg_to_save (void)
11519 /* Stack frame remains as is unless we are in AltiVec ABI. */
11520 if (! TARGET_ALTIVEC_ABI
)
11521 return LAST_ALTIVEC_REGNO
+ 1;
11523 /* Find lowest numbered live register. */
11524 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
11525 if (regs_ever_live
[i
])
11531 /* Return a 32-bit mask of the AltiVec registers we need to set in
11532 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11533 the 32-bit word is 0. */
11535 static unsigned int
11536 compute_vrsave_mask (void)
11538 unsigned int i
, mask
= 0;
11540 /* First, find out if we use _any_ altivec registers. */
11541 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
11542 if (regs_ever_live
[i
])
11543 mask
|= ALTIVEC_REG_BIT (i
);
11548 /* Next, remove the argument registers from the set. These must
11549 be in the VRSAVE mask set by the caller, so we don't need to add
11550 them in again. More importantly, the mask we compute here is
11551 used to generate CLOBBERs in the set_vrsave insn, and we do not
11552 wish the argument registers to die. */
11553 for (i
= cfun
->args_info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
11554 mask
&= ~ALTIVEC_REG_BIT (i
);
11556 /* Similarly, remove the return value from the set. */
11559 diddle_return_value (is_altivec_return_reg
, &yes
);
11561 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
11567 /* For a very restricted set of circumstances, we can cut down the
11568 size of prologs/epilogs by calling our own save/restore-the-world
11572 compute_save_world_info(rs6000_stack_t
*info_ptr
)
11574 info_ptr
->world_save_p
=
11575 (DEFAULT_ABI
== ABI_DARWIN
)
11576 && ! (current_function_calls_setjmp
&& flag_exceptions
)
11577 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
11578 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
11579 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
11580 && info_ptr
->cr_save_p
;
11582 /* This will not work in conjunction with sibcalls. Make sure there
11583 are none. (This check is expensive, but seldom executed.) */
11584 if ( info_ptr
->world_save_p
)
11587 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
11588 if ( GET_CODE (insn
) == CALL_INSN
11589 && SIBLING_CALL_P (insn
))
11591 info_ptr
->world_save_p
= 0;
11596 if (info_ptr
->world_save_p
)
11598 /* Even if we're not touching VRsave, make sure there's room on the
11599 stack for it, if it looks like we're calling SAVE_WORLD, which
11600 will attempt to save it. */
11601 info_ptr
->vrsave_size
= 4;
11603 /* "Save" the VRsave register too if we're saving the world. */
11604 if (info_ptr
->vrsave_mask
== 0)
11605 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
11607 /* Because the Darwin register save/restore routines only handle
11608 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
11609 check and abort if there's something worng. */
11610 if (info_ptr
->first_fp_reg_save
< FIRST_SAVED_FP_REGNO
11611 || info_ptr
->first_altivec_reg_save
< FIRST_SAVED_ALTIVEC_REGNO
)
11619 is_altivec_return_reg (rtx reg
, void *xyes
)
11621 bool *yes
= (bool *) xyes
;
11622 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
11627 /* Calculate the stack information for the current function. This is
11628 complicated by having two separate calling sequences, the AIX calling
11629 sequence and the V.4 calling sequence.
11631 AIX (and Darwin/Mac OS X) stack frames look like:
11633 SP----> +---------------------------------------+
11634 | back chain to caller | 0 0
11635 +---------------------------------------+
11636 | saved CR | 4 8 (8-11)
11637 +---------------------------------------+
11639 +---------------------------------------+
11640 | reserved for compilers | 12 24
11641 +---------------------------------------+
11642 | reserved for binders | 16 32
11643 +---------------------------------------+
11644 | saved TOC pointer | 20 40
11645 +---------------------------------------+
11646 | Parameter save area (P) | 24 48
11647 +---------------------------------------+
11648 | Alloca space (A) | 24+P etc.
11649 +---------------------------------------+
11650 | Local variable space (L) | 24+P+A
11651 +---------------------------------------+
11652 | Float/int conversion temporary (X) | 24+P+A+L
11653 +---------------------------------------+
11654 | Save area for AltiVec registers (W) | 24+P+A+L+X
11655 +---------------------------------------+
11656 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11657 +---------------------------------------+
11658 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
11659 +---------------------------------------+
11660 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11661 +---------------------------------------+
11662 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
11663 +---------------------------------------+
11664 old SP->| back chain to caller's caller |
11665 +---------------------------------------+
11667 The required alignment for AIX configurations is two words (i.e., 8
11671 V.4 stack frames look like:
11673 SP----> +---------------------------------------+
11674 | back chain to caller | 0
11675 +---------------------------------------+
11676 | caller's saved LR | 4
11677 +---------------------------------------+
11678 | Parameter save area (P) | 8
11679 +---------------------------------------+
11680 | Alloca space (A) | 8+P
11681 +---------------------------------------+
11682 | Varargs save area (V) | 8+P+A
11683 +---------------------------------------+
11684 | Local variable space (L) | 8+P+A+V
11685 +---------------------------------------+
11686 | Float/int conversion temporary (X) | 8+P+A+V+L
11687 +---------------------------------------+
11688 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11689 +---------------------------------------+
11690 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11691 +---------------------------------------+
11692 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11693 +---------------------------------------+
11694 | SPE: area for 64-bit GP registers |
11695 +---------------------------------------+
11696 | SPE alignment padding |
11697 +---------------------------------------+
11698 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
11699 +---------------------------------------+
11700 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
11701 +---------------------------------------+
11702 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
11703 +---------------------------------------+
11704 old SP->| back chain to caller's caller |
11705 +---------------------------------------+
11707 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11708 given. (But note below and in sysv4.h that we require only 8 and
11709 may round up the size of our stack frame anyways. The historical
11710 reason is early versions of powerpc-linux which didn't properly
11711 align the stack at program startup. A happy side-effect is that
11712 -mno-eabi libraries can be used with -meabi programs.)
11714 The EABI configuration defaults to the V.4 layout. However,
11715 the stack alignment requirements may differ. If -mno-eabi is not
11716 given, the required stack alignment is 8 bytes; if -mno-eabi is
11717 given, the required alignment is 16 bytes. (But see V.4 comment
11720 #ifndef ABI_STACK_BOUNDARY
11721 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
11724 static rs6000_stack_t
*
11725 rs6000_stack_info (void)
11727 static rs6000_stack_t info
, zero_info
;
11728 rs6000_stack_t
*info_ptr
= &info
;
11729 int reg_size
= TARGET_32BIT
? 4 : 8;
11732 HOST_WIDE_INT non_fixed_size
;
11734 /* Zero all fields portably. */
11739 /* Cache value so we don't rescan instruction chain over and over. */
11740 if (cfun
->machine
->insn_chain_scanned_p
== 0)
11742 cfun
->machine
->insn_chain_scanned_p
= 1;
11743 info_ptr
->spe_64bit_regs_used
= (int) spe_func_has_64bit_regs_p ();
11747 /* Select which calling sequence. */
11748 info_ptr
->abi
= DEFAULT_ABI
;
11750 /* Calculate which registers need to be saved & save area size. */
11751 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
11752 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
11753 even if it currently looks like we won't. */
11754 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
11755 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
11756 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
11757 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
11758 info_ptr
->gp_size
= reg_size
* (32 - RS6000_PIC_OFFSET_TABLE_REGNUM
);
11760 info_ptr
->gp_size
= reg_size
* (32 - info_ptr
->first_gp_reg_save
);
11762 /* For the SPE, we have an additional upper 32-bits on each GPR.
11763 Ideally we should save the entire 64-bits only when the upper
11764 half is used in SIMD instructions. Since we only record
11765 registers live (not the size they are used in), this proves
11766 difficult because we'd have to traverse the instruction chain at
11767 the right time, taking reload into account. This is a real pain,
11768 so we opt to save the GPRs in 64-bits always if but one register
11769 gets used in 64-bits. Otherwise, all the registers in the frame
11770 get saved in 32-bits.
11772 So... since when we save all GPRs (except the SP) in 64-bits, the
11773 traditional GP save area will be empty. */
11774 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
11775 info_ptr
->gp_size
= 0;
11777 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
11778 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
11780 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
11781 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
11782 - info_ptr
->first_altivec_reg_save
);
11784 /* Does this function call anything? */
11785 info_ptr
->calls_p
= (! current_function_is_leaf
11786 || cfun
->machine
->ra_needs_full_frame
);
11788 /* Determine if we need to save the link register. */
11789 if (rs6000_ra_ever_killed ()
11790 || (DEFAULT_ABI
== ABI_AIX
11791 && current_function_profile
11792 && !TARGET_PROFILE_KERNEL
)
11793 #ifdef TARGET_RELOCATABLE
11794 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
11796 || (info_ptr
->first_fp_reg_save
!= 64
11797 && !FP_SAVE_INLINE (info_ptr
->first_fp_reg_save
))
11798 || info_ptr
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
11799 || (DEFAULT_ABI
== ABI_V4
&& current_function_calls_alloca
)
11800 || (DEFAULT_ABI
== ABI_DARWIN
11802 && current_function_uses_pic_offset_table
)
11803 || info_ptr
->calls_p
)
11805 info_ptr
->lr_save_p
= 1;
11806 regs_ever_live
[LINK_REGISTER_REGNUM
] = 1;
11809 /* Determine if we need to save the condition code registers. */
11810 if (regs_ever_live
[CR2_REGNO
]
11811 || regs_ever_live
[CR3_REGNO
]
11812 || regs_ever_live
[CR4_REGNO
])
11814 info_ptr
->cr_save_p
= 1;
11815 if (DEFAULT_ABI
== ABI_V4
)
11816 info_ptr
->cr_size
= reg_size
;
11819 /* If the current function calls __builtin_eh_return, then we need
11820 to allocate stack space for registers that will hold data for
11821 the exception handler. */
11822 if (current_function_calls_eh_return
)
11825 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
11828 /* SPE saves EH registers in 64-bits. */
11829 ehrd_size
= i
* (TARGET_SPE_ABI
11830 && info_ptr
->spe_64bit_regs_used
!= 0
11831 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
11836 /* Determine various sizes. */
11837 info_ptr
->reg_size
= reg_size
;
11838 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
11839 info_ptr
->varargs_size
= RS6000_VARARGS_AREA
;
11840 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
11841 info_ptr
->parm_size
= RS6000_ALIGN (current_function_outgoing_args_size
,
11842 TARGET_ALTIVEC
? 16 : 8);
11844 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
11845 info_ptr
->spe_gp_size
= 8 * (32 - info_ptr
->first_gp_reg_save
);
11847 info_ptr
->spe_gp_size
= 0;
11849 if (TARGET_ALTIVEC_ABI
)
11850 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
11852 info_ptr
->vrsave_mask
= 0;
11854 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
11855 info_ptr
->vrsave_size
= 4;
11857 info_ptr
->vrsave_size
= 0;
11859 compute_save_world_info (info_ptr
);
11861 /* Calculate the offsets. */
11862 switch (DEFAULT_ABI
)
11870 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
11871 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
11873 if (TARGET_ALTIVEC_ABI
)
11875 info_ptr
->vrsave_save_offset
11876 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
11878 /* Align stack so vector save area is on a quadword boundary. */
11879 if (info_ptr
->altivec_size
!= 0)
11880 info_ptr
->altivec_padding_size
11881 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
11883 info_ptr
->altivec_padding_size
= 0;
11885 info_ptr
->altivec_save_offset
11886 = info_ptr
->vrsave_save_offset
11887 - info_ptr
->altivec_padding_size
11888 - info_ptr
->altivec_size
;
11890 /* Adjust for AltiVec case. */
11891 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
11894 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
11895 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
11896 info_ptr
->lr_save_offset
= 2*reg_size
;
11900 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
11901 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
11902 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
11904 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
11906 /* Align stack so SPE GPR save area is aligned on a
11907 double-word boundary. */
11908 if (info_ptr
->spe_gp_size
!= 0)
11909 info_ptr
->spe_padding_size
11910 = 8 - (-info_ptr
->cr_save_offset
% 8);
11912 info_ptr
->spe_padding_size
= 0;
11914 info_ptr
->spe_gp_save_offset
11915 = info_ptr
->cr_save_offset
11916 - info_ptr
->spe_padding_size
11917 - info_ptr
->spe_gp_size
;
11919 /* Adjust for SPE case. */
11920 info_ptr
->toc_save_offset
11921 = info_ptr
->spe_gp_save_offset
- info_ptr
->toc_size
;
11923 else if (TARGET_ALTIVEC_ABI
)
11925 info_ptr
->vrsave_save_offset
11926 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
11928 /* Align stack so vector save area is on a quadword boundary. */
11929 if (info_ptr
->altivec_size
!= 0)
11930 info_ptr
->altivec_padding_size
11931 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
11933 info_ptr
->altivec_padding_size
= 0;
11935 info_ptr
->altivec_save_offset
11936 = info_ptr
->vrsave_save_offset
11937 - info_ptr
->altivec_padding_size
11938 - info_ptr
->altivec_size
;
11940 /* Adjust for AltiVec case. */
11941 info_ptr
->toc_save_offset
11942 = info_ptr
->altivec_save_offset
- info_ptr
->toc_size
;
11945 info_ptr
->toc_save_offset
= info_ptr
->cr_save_offset
- info_ptr
->toc_size
;
11946 info_ptr
->ehrd_offset
= info_ptr
->toc_save_offset
- ehrd_size
;
11947 info_ptr
->lr_save_offset
= reg_size
;
11951 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
11952 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
11953 + info_ptr
->gp_size
11954 + info_ptr
->altivec_size
11955 + info_ptr
->altivec_padding_size
11956 + info_ptr
->spe_gp_size
11957 + info_ptr
->spe_padding_size
11959 + info_ptr
->cr_size
11960 + info_ptr
->lr_size
11961 + info_ptr
->vrsave_size
11962 + info_ptr
->toc_size
,
11965 non_fixed_size
= (info_ptr
->vars_size
11966 + info_ptr
->parm_size
11967 + info_ptr
->save_size
11968 + info_ptr
->varargs_size
);
11970 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
11971 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
11973 /* Determine if we need to allocate any stack frame:
11975 For AIX we need to push the stack if a frame pointer is needed
11976 (because the stack might be dynamically adjusted), if we are
11977 debugging, if we make calls, or if the sum of fp_save, gp_save,
11978 and local variables are more than the space needed to save all
11979 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
11980 + 18*8 = 288 (GPR13 reserved).
11982 For V.4 we don't have the stack cushion that AIX uses, but assume
11983 that the debugger can handle stackless frames. */
11985 if (info_ptr
->calls_p
)
11986 info_ptr
->push_p
= 1;
11988 else if (DEFAULT_ABI
== ABI_V4
)
11989 info_ptr
->push_p
= non_fixed_size
!= 0;
11991 else if (frame_pointer_needed
)
11992 info_ptr
->push_p
= 1;
11994 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
11995 info_ptr
->push_p
= 1;
11998 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
12000 /* Zero offsets if we're not saving those registers. */
12001 if (info_ptr
->fp_size
== 0)
12002 info_ptr
->fp_save_offset
= 0;
12004 if (info_ptr
->gp_size
== 0)
12005 info_ptr
->gp_save_offset
= 0;
12007 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
12008 info_ptr
->altivec_save_offset
= 0;
12010 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
12011 info_ptr
->vrsave_save_offset
= 0;
12013 if (! TARGET_SPE_ABI
12014 || info_ptr
->spe_64bit_regs_used
== 0
12015 || info_ptr
->spe_gp_size
== 0)
12016 info_ptr
->spe_gp_save_offset
= 0;
12018 if (! info_ptr
->lr_save_p
)
12019 info_ptr
->lr_save_offset
= 0;
12021 if (! info_ptr
->cr_save_p
)
12022 info_ptr
->cr_save_offset
= 0;
12024 if (! info_ptr
->toc_save_p
)
12025 info_ptr
->toc_save_offset
= 0;
12030 /* Return true if the current function uses any GPRs in 64-bit SIMD
12034 spe_func_has_64bit_regs_p (void)
12038 /* Functions that save and restore all the call-saved registers will
12039 need to save/restore the registers in 64-bits. */
12040 if (current_function_calls_eh_return
12041 || current_function_calls_setjmp
12042 || current_function_has_nonlocal_goto
)
12045 insns
= get_insns ();
12047 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
12053 i
= PATTERN (insn
);
12054 if (GET_CODE (i
) == SET
12055 && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i
))))
12064 debug_stack_info (rs6000_stack_t
*info
)
12066 const char *abi_string
;
12069 info
= rs6000_stack_info ();
12071 fprintf (stderr
, "\nStack information for function %s:\n",
12072 ((current_function_decl
&& DECL_NAME (current_function_decl
))
12073 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
12078 default: abi_string
= "Unknown"; break;
12079 case ABI_NONE
: abi_string
= "NONE"; break;
12080 case ABI_AIX
: abi_string
= "AIX"; break;
12081 case ABI_DARWIN
: abi_string
= "Darwin"; break;
12082 case ABI_V4
: abi_string
= "V.4"; break;
12085 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
12087 if (TARGET_ALTIVEC_ABI
)
12088 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
12090 if (TARGET_SPE_ABI
)
12091 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
12093 if (info
->first_gp_reg_save
!= 32)
12094 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
12096 if (info
->first_fp_reg_save
!= 64)
12097 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
12099 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
12100 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
12101 info
->first_altivec_reg_save
);
12103 if (info
->lr_save_p
)
12104 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
12106 if (info
->cr_save_p
)
12107 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
12109 if (info
->toc_save_p
)
12110 fprintf (stderr
, "\ttoc_save_p = %5d\n", info
->toc_save_p
);
12112 if (info
->vrsave_mask
)
12113 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
12116 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
12119 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
12121 if (info
->gp_save_offset
)
12122 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
12124 if (info
->fp_save_offset
)
12125 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
12127 if (info
->altivec_save_offset
)
12128 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
12129 info
->altivec_save_offset
);
12131 if (info
->spe_gp_save_offset
)
12132 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
12133 info
->spe_gp_save_offset
);
12135 if (info
->vrsave_save_offset
)
12136 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
12137 info
->vrsave_save_offset
);
12139 if (info
->lr_save_offset
)
12140 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
12142 if (info
->cr_save_offset
)
12143 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
12145 if (info
->toc_save_offset
)
12146 fprintf (stderr
, "\ttoc_save_offset = %5d\n", info
->toc_save_offset
);
12148 if (info
->varargs_save_offset
)
12149 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
12151 if (info
->total_size
)
12152 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
12155 if (info
->varargs_size
)
12156 fprintf (stderr
, "\tvarargs_size = %5d\n", info
->varargs_size
);
12158 if (info
->vars_size
)
12159 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
12162 if (info
->parm_size
)
12163 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
12165 if (info
->fixed_size
)
12166 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
12169 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
12171 if (info
->spe_gp_size
)
12172 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
12175 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
12177 if (info
->altivec_size
)
12178 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
12180 if (info
->vrsave_size
)
12181 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
12183 if (info
->altivec_padding_size
)
12184 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
12185 info
->altivec_padding_size
);
12187 if (info
->spe_padding_size
)
12188 fprintf (stderr
, "\tspe_padding_size = %5d\n",
12189 info
->spe_padding_size
);
12192 fprintf (stderr
, "\tlr_size = %5d\n", info
->lr_size
);
12195 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
12197 if (info
->toc_size
)
12198 fprintf (stderr
, "\ttoc_size = %5d\n", info
->toc_size
);
12200 if (info
->save_size
)
12201 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
12203 if (info
->reg_size
!= 4)
12204 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
12206 fprintf (stderr
, "\n");
12210 rs6000_return_addr (int count
, rtx frame
)
12212 /* Currently we don't optimize very well between prolog and body
12213 code and for PIC code the code can be actually quite bad, so
12214 don't try to be too clever here. */
12215 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
12217 cfun
->machine
->ra_needs_full_frame
= 1;
12224 plus_constant (copy_to_reg
12225 (gen_rtx_MEM (Pmode
,
12226 memory_address (Pmode
, frame
))),
12227 RETURN_ADDRESS_OFFSET
)));
12230 cfun
->machine
->ra_need_lr
= 1;
12231 return get_hard_reg_initial_val (Pmode
, LINK_REGISTER_REGNUM
);
12234 /* Say whether a function is a candidate for sibcall handling or not.
12235 We do not allow indirect calls to be optimized into sibling calls.
12236 Also, we can't do it if there are any vector parameters; there's
12237 nowhere to put the VRsave code so it works; note that functions with
12238 vector parameters are required to have a prototype, so the argument
12239 type info must be available here. (The tail recursion case can work
12240 with vector parameters, but there's no way to distinguish here.) */
12242 rs6000_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
12247 if (TARGET_ALTIVEC_VRSAVE
)
12249 for (type
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
12250 type
; type
= TREE_CHAIN (type
))
12252 if (TREE_CODE (TREE_VALUE (type
)) == VECTOR_TYPE
)
12256 if (DEFAULT_ABI
== ABI_DARWIN
12257 || (*targetm
.binds_local_p
) (decl
))
12259 tree attr_list
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
12261 if (!lookup_attribute ("longcall", attr_list
)
12262 || lookup_attribute ("shortcall", attr_list
))
12270 rs6000_ra_ever_killed (void)
12276 if (current_function_is_thunk
)
12279 /* regs_ever_live has LR marked as used if any sibcalls are present,
12280 but this should not force saving and restoring in the
12281 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
12282 clobbers LR, so that is inappropriate. */
12284 /* Also, the prologue can generate a store into LR that
12285 doesn't really count, like this:
12288 bcl to set PIC register
12292 When we're called from the epilogue, we need to avoid counting
12293 this as a store. */
12295 push_topmost_sequence ();
12296 top
= get_insns ();
12297 pop_topmost_sequence ();
12298 reg
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
12300 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
12304 if (FIND_REG_INC_NOTE (insn
, reg
))
12306 else if (GET_CODE (insn
) == CALL_INSN
12307 && !SIBLING_CALL_P (insn
))
12309 else if (set_of (reg
, insn
) != NULL_RTX
12310 && !prologue_epilogue_contains (insn
))
12317 /* Add a REG_MAYBE_DEAD note to the insn. */
12319 rs6000_maybe_dead (rtx insn
)
12321 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
12326 /* Emit instructions needed to load the TOC register.
12327 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
12328 a constant pool; or for SVR4 -fpic. */
12331 rs6000_emit_load_toc_table (int fromprolog
)
12334 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
12336 if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
12338 rtx temp
= (fromprolog
12339 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
12340 : gen_reg_rtx (Pmode
));
12341 insn
= emit_insn (gen_load_toc_v4_pic_si (temp
));
12343 rs6000_maybe_dead (insn
);
12344 insn
= emit_move_insn (dest
, temp
);
12346 rs6000_maybe_dead (insn
);
12348 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
12351 rtx tempLR
= (fromprolog
12352 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
12353 : gen_reg_rtx (Pmode
));
12354 rtx temp0
= (fromprolog
12355 ? gen_rtx_REG (Pmode
, 0)
12356 : gen_reg_rtx (Pmode
));
12359 /* possibly create the toc section */
12360 if (! toc_initialized
)
12363 function_section (current_function_decl
);
12370 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
12371 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
12373 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
12374 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
12376 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR
,
12378 rs6000_maybe_dead (emit_move_insn (dest
, tempLR
));
12379 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
,
12386 static int reload_toc_labelno
= 0;
12388 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
12390 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCG", reload_toc_labelno
++);
12391 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
12393 emit_insn (gen_load_toc_v4_PIC_1b (tempLR
, symF
, tocsym
));
12394 emit_move_insn (dest
, tempLR
);
12395 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
12397 insn
= emit_insn (gen_addsi3 (dest
, temp0
, dest
));
12399 rs6000_maybe_dead (insn
);
12401 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
12403 /* This is for AIX code running in non-PIC ELF32. */
12406 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
12407 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
12409 insn
= emit_insn (gen_elf_high (dest
, realsym
));
12411 rs6000_maybe_dead (insn
);
12412 insn
= emit_insn (gen_elf_low (dest
, dest
, realsym
));
12414 rs6000_maybe_dead (insn
);
12416 else if (DEFAULT_ABI
== ABI_AIX
)
12419 insn
= emit_insn (gen_load_toc_aix_si (dest
));
12421 insn
= emit_insn (gen_load_toc_aix_di (dest
));
12423 rs6000_maybe_dead (insn
);
12429 /* Emit instructions to restore the link register after determining where
12430 its value has been stored. */
12433 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
12435 rs6000_stack_t
*info
= rs6000_stack_info ();
12438 operands
[0] = source
;
12439 operands
[1] = scratch
;
12441 if (info
->lr_save_p
)
12443 rtx frame_rtx
= stack_pointer_rtx
;
12444 HOST_WIDE_INT sp_offset
= 0;
12447 if (frame_pointer_needed
12448 || current_function_calls_alloca
12449 || info
->total_size
> 32767)
12451 emit_move_insn (operands
[1], gen_rtx_MEM (Pmode
, frame_rtx
));
12452 frame_rtx
= operands
[1];
12454 else if (info
->push_p
)
12455 sp_offset
= info
->total_size
;
12457 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
12458 tmp
= gen_rtx_MEM (Pmode
, tmp
);
12459 emit_move_insn (tmp
, operands
[0]);
12462 emit_move_insn (gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
), operands
[0]);
12465 static GTY(()) int set
= -1;
12468 get_TOC_alias_set (void)
12471 set
= new_alias_set ();
12475 /* This returns nonzero if the current function uses the TOC. This is
12476 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12477 is generated by the ABI_V4 load_toc_* patterns. */
12484 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12487 rtx pat
= PATTERN (insn
);
12490 if (GET_CODE (pat
) == PARALLEL
)
12491 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
12493 rtx sub
= XVECEXP (pat
, 0, i
);
12494 if (GET_CODE (sub
) == USE
)
12496 sub
= XEXP (sub
, 0);
12497 if (GET_CODE (sub
) == UNSPEC
12498 && XINT (sub
, 1) == UNSPEC_TOC
)
12508 create_TOC_reference (rtx symbol
)
12510 return gen_rtx_PLUS (Pmode
,
12511 gen_rtx_REG (Pmode
, TOC_REGISTER
),
12512 gen_rtx_CONST (Pmode
,
12513 gen_rtx_MINUS (Pmode
, symbol
,
12514 gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
))));
12517 /* If _Unwind_* has been called from within the same module,
12518 toc register is not guaranteed to be saved to 40(1) on function
12519 entry. Save it there in that case. */
12522 rs6000_aix_emit_builtin_unwind_init (void)
12525 rtx stack_top
= gen_reg_rtx (Pmode
);
12526 rtx opcode_addr
= gen_reg_rtx (Pmode
);
12527 rtx opcode
= gen_reg_rtx (SImode
);
12528 rtx tocompare
= gen_reg_rtx (SImode
);
12529 rtx no_toc_save_needed
= gen_label_rtx ();
12531 mem
= gen_rtx_MEM (Pmode
, hard_frame_pointer_rtx
);
12532 emit_move_insn (stack_top
, mem
);
12534 mem
= gen_rtx_MEM (Pmode
,
12535 gen_rtx_PLUS (Pmode
, stack_top
,
12536 GEN_INT (2 * GET_MODE_SIZE (Pmode
))));
12537 emit_move_insn (opcode_addr
, mem
);
12538 emit_move_insn (opcode
, gen_rtx_MEM (SImode
, opcode_addr
));
12539 emit_move_insn (tocompare
, gen_int_mode (TARGET_32BIT
? 0x80410014
12540 : 0xE8410028, SImode
));
12542 do_compare_rtx_and_jump (opcode
, tocompare
, EQ
, 1,
12543 SImode
, NULL_RTX
, NULL_RTX
,
12544 no_toc_save_needed
);
12546 mem
= gen_rtx_MEM (Pmode
,
12547 gen_rtx_PLUS (Pmode
, stack_top
,
12548 GEN_INT (5 * GET_MODE_SIZE (Pmode
))));
12549 emit_move_insn (mem
, gen_rtx_REG (Pmode
, 2));
12550 emit_label (no_toc_save_needed
);
12553 /* This ties together stack memory (MEM with an alias set of
12554 rs6000_sr_alias_set) and the change to the stack pointer. */
12557 rs6000_emit_stack_tie (void)
12559 rtx mem
= gen_rtx_MEM (BLKmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
12561 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
12562 emit_insn (gen_stack_tie (mem
));
12565 /* Emit the correct code for allocating stack space, as insns.
12566 If COPY_R12, make sure a copy of the old frame is left in r12.
12567 The generated code may use hard register 0 as a temporary. */
12570 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, int copy_r12
)
12573 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
12574 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
12575 rtx todec
= GEN_INT (-size
);
12577 if (current_function_limit_stack
)
12579 if (REG_P (stack_limit_rtx
)
12580 && REGNO (stack_limit_rtx
) > 1
12581 && REGNO (stack_limit_rtx
) <= 31)
12583 emit_insn (TARGET_32BIT
12584 ? gen_addsi3 (tmp_reg
,
12587 : gen_adddi3 (tmp_reg
,
12591 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
12594 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
12596 && DEFAULT_ABI
== ABI_V4
)
12598 rtx toload
= gen_rtx_CONST (VOIDmode
,
12599 gen_rtx_PLUS (Pmode
,
12603 emit_insn (gen_elf_high (tmp_reg
, toload
));
12604 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
12605 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
12609 warning ("stack limit expression is not supported");
12612 if (copy_r12
|| ! TARGET_UPDATE
)
12613 emit_move_insn (gen_rtx_REG (Pmode
, 12), stack_reg
);
12619 /* Need a note here so that try_split doesn't get confused. */
12620 if (get_last_insn() == NULL_RTX
)
12621 emit_note (NOTE_INSN_DELETED
);
12622 insn
= emit_move_insn (tmp_reg
, todec
);
12623 try_split (PATTERN (insn
), insn
, 0);
12627 insn
= emit_insn (TARGET_32BIT
12628 ? gen_movsi_update (stack_reg
, stack_reg
,
12630 : gen_movdi_di_update (stack_reg
, stack_reg
,
12631 todec
, stack_reg
));
12635 insn
= emit_insn (TARGET_32BIT
12636 ? gen_addsi3 (stack_reg
, stack_reg
, todec
)
12637 : gen_adddi3 (stack_reg
, stack_reg
, todec
));
12638 emit_move_insn (gen_rtx_MEM (Pmode
, stack_reg
),
12639 gen_rtx_REG (Pmode
, 12));
12642 RTX_FRAME_RELATED_P (insn
) = 1;
12644 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
12645 gen_rtx_SET (VOIDmode
, stack_reg
,
12646 gen_rtx_PLUS (Pmode
, stack_reg
,
12651 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12652 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12653 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12654 deduce these equivalences by itself so it wasn't necessary to hold
12655 its hand so much. */
12658 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
12659 rtx reg2
, rtx rreg
)
12663 /* copy_rtx will not make unique copies of registers, so we need to
12664 ensure we don't have unwanted sharing here. */
12666 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
12669 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
12671 real
= copy_rtx (PATTERN (insn
));
12673 if (reg2
!= NULL_RTX
)
12674 real
= replace_rtx (real
, reg2
, rreg
);
12676 real
= replace_rtx (real
, reg
,
12677 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
12678 STACK_POINTER_REGNUM
),
12681 /* We expect that 'real' is either a SET or a PARALLEL containing
12682 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12683 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12685 if (GET_CODE (real
) == SET
)
12689 temp
= simplify_rtx (SET_SRC (set
));
12691 SET_SRC (set
) = temp
;
12692 temp
= simplify_rtx (SET_DEST (set
));
12694 SET_DEST (set
) = temp
;
12695 if (GET_CODE (SET_DEST (set
)) == MEM
)
12697 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
12699 XEXP (SET_DEST (set
), 0) = temp
;
12702 else if (GET_CODE (real
) == PARALLEL
)
12705 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
12706 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
12708 rtx set
= XVECEXP (real
, 0, i
);
12710 temp
= simplify_rtx (SET_SRC (set
));
12712 SET_SRC (set
) = temp
;
12713 temp
= simplify_rtx (SET_DEST (set
));
12715 SET_DEST (set
) = temp
;
12716 if (GET_CODE (SET_DEST (set
)) == MEM
)
12718 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
12720 XEXP (SET_DEST (set
), 0) = temp
;
12722 RTX_FRAME_RELATED_P (set
) = 1;
12729 real
= spe_synthesize_frame_save (real
);
12731 RTX_FRAME_RELATED_P (insn
) = 1;
12732 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
12737 /* Given an SPE frame note, return a PARALLEL of SETs with the
12738 original note, plus a synthetic register save. */
12741 spe_synthesize_frame_save (rtx real
)
12743 rtx synth
, offset
, reg
, real2
;
12745 if (GET_CODE (real
) != SET
12746 || GET_MODE (SET_SRC (real
)) != V2SImode
)
12749 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12750 frame related note. The parallel contains a set of the register
12751 being saved, and another set to a synthetic register (n+1200).
12752 This is so we can differentiate between 64-bit and 32-bit saves.
12753 Words cannot describe this nastiness. */
12755 if (GET_CODE (SET_DEST (real
)) != MEM
12756 || GET_CODE (XEXP (SET_DEST (real
), 0)) != PLUS
12757 || GET_CODE (SET_SRC (real
)) != REG
)
12761 (set (mem (plus (reg x) (const y)))
12764 (set (mem (plus (reg x) (const y+4)))
12768 real2
= copy_rtx (real
);
12769 PUT_MODE (SET_DEST (real2
), SImode
);
12770 reg
= SET_SRC (real2
);
12771 real2
= replace_rtx (real2
, reg
, gen_rtx_REG (SImode
, REGNO (reg
)));
12772 synth
= copy_rtx (real2
);
12774 if (BYTES_BIG_ENDIAN
)
12776 offset
= XEXP (XEXP (SET_DEST (real2
), 0), 1);
12777 real2
= replace_rtx (real2
, offset
, GEN_INT (INTVAL (offset
) + 4));
12780 reg
= SET_SRC (synth
);
12782 synth
= replace_rtx (synth
, reg
,
12783 gen_rtx_REG (SImode
, REGNO (reg
) + 1200));
12785 offset
= XEXP (XEXP (SET_DEST (synth
), 0), 1);
12786 synth
= replace_rtx (synth
, offset
,
12787 GEN_INT (INTVAL (offset
)
12788 + (BYTES_BIG_ENDIAN
? 0 : 4)));
12790 RTX_FRAME_RELATED_P (synth
) = 1;
12791 RTX_FRAME_RELATED_P (real2
) = 1;
12792 if (BYTES_BIG_ENDIAN
)
12793 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, synth
, real2
));
12795 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, real2
, synth
));
12800 /* Returns an insn that has a vrsave set operation with the
12801 appropriate CLOBBERs. */
12804 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
12807 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
12808 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
12811 = gen_rtx_SET (VOIDmode
,
12813 gen_rtx_UNSPEC_VOLATILE (SImode
,
12814 gen_rtvec (2, reg
, vrsave
),
12819 /* We need to clobber the registers in the mask so the scheduler
12820 does not move sets to VRSAVE before sets of AltiVec registers.
12822 However, if the function receives nonlocal gotos, reload will set
12823 all call saved registers live. We will end up with:
12825 (set (reg 999) (mem))
12826 (parallel [ (set (reg vrsave) (unspec blah))
12827 (clobber (reg 999))])
12829 The clobber will cause the store into reg 999 to be dead, and
12830 flow will attempt to delete an epilogue insn. In this case, we
12831 need an unspec use/set of the register. */
12833 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
12834 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
12836 if (!epiloguep
|| call_used_regs
[i
])
12837 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
12838 gen_rtx_REG (V4SImode
, i
));
12841 rtx reg
= gen_rtx_REG (V4SImode
, i
);
12844 = gen_rtx_SET (VOIDmode
,
12846 gen_rtx_UNSPEC (V4SImode
,
12847 gen_rtvec (1, reg
), 27));
12851 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
12853 for (i
= 0; i
< nclobs
; ++i
)
12854 XVECEXP (insn
, 0, i
) = clobs
[i
];
12859 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
12860 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
12863 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
12864 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
12866 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
12867 rtx replacea
, replaceb
;
12869 int_rtx
= GEN_INT (offset
);
12871 /* Some cases that need register indexed addressing. */
12872 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
12874 && SPE_VECTOR_MODE (mode
)
12875 && !SPE_CONST_OFFSET_OK (offset
)))
12877 /* Whomever calls us must make sure r11 is available in the
12878 flow path of instructions in the prologue. */
12879 offset_rtx
= gen_rtx_REG (Pmode
, 11);
12880 emit_move_insn (offset_rtx
, int_rtx
);
12882 replacea
= offset_rtx
;
12883 replaceb
= int_rtx
;
12887 offset_rtx
= int_rtx
;
12888 replacea
= NULL_RTX
;
12889 replaceb
= NULL_RTX
;
12892 reg
= gen_rtx_REG (mode
, regno
);
12893 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
12894 mem
= gen_rtx_MEM (mode
, addr
);
12895 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
12897 insn
= emit_move_insn (mem
, reg
);
12899 rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
12902 /* Emit an offset memory reference suitable for a frame store, while
12903 converting to a valid addressing mode. */
12906 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
12908 rtx int_rtx
, offset_rtx
;
12910 int_rtx
= GEN_INT (offset
);
12912 if (TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
12914 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
12915 emit_move_insn (offset_rtx
, int_rtx
);
12918 offset_rtx
= int_rtx
;
12920 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
12923 #ifndef TARGET_FIX_AND_CONTINUE
12924 #define TARGET_FIX_AND_CONTINUE 0
12927 /* Emit function prologue as insns. */
12930 rs6000_emit_prologue (void)
12932 rs6000_stack_t
*info
= rs6000_stack_info ();
12933 enum machine_mode reg_mode
= Pmode
;
12934 int reg_size
= TARGET_32BIT
? 4 : 8;
12935 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
12936 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
12937 rtx frame_reg_rtx
= sp_reg_rtx
;
12938 rtx cr_save_rtx
= NULL_RTX
;
12940 int saving_FPRs_inline
;
12941 int using_store_multiple
;
12942 HOST_WIDE_INT sp_offset
= 0;
12944 if (TARGET_FIX_AND_CONTINUE
)
12946 /* gdb on darwin arranges to forward a function from the old
12947 address by modifying the first 4 instructions of the function
12948 to branch to the overriding function. This is necessary to
12949 permit function pointers that point to the old function to
12950 actually forward to the new function. */
12951 emit_insn (gen_nop ());
12952 emit_insn (gen_nop ());
12953 emit_insn (gen_nop ());
12954 emit_insn (gen_nop ());
12957 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
12959 reg_mode
= V2SImode
;
12963 using_store_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
12964 && (!TARGET_SPE_ABI
12965 || info
->spe_64bit_regs_used
== 0)
12966 && info
->first_gp_reg_save
< 31);
12967 saving_FPRs_inline
= (info
->first_fp_reg_save
== 64
12968 || FP_SAVE_INLINE (info
->first_fp_reg_save
)
12969 || current_function_calls_eh_return
12970 || cfun
->machine
->ra_need_lr
);
12972 /* For V.4, update stack before we do any saving and set back pointer. */
12974 && (DEFAULT_ABI
== ABI_V4
12975 || current_function_calls_eh_return
))
12977 if (info
->total_size
< 32767)
12978 sp_offset
= info
->total_size
;
12980 frame_reg_rtx
= frame_ptr_rtx
;
12981 rs6000_emit_allocate_stack (info
->total_size
,
12982 (frame_reg_rtx
!= sp_reg_rtx
12983 && (info
->cr_save_p
12985 || info
->first_fp_reg_save
< 64
12986 || info
->first_gp_reg_save
< 32
12988 if (frame_reg_rtx
!= sp_reg_rtx
)
12989 rs6000_emit_stack_tie ();
12992 /* Handle world saves specially here. */
12993 if (info
->world_save_p
)
12999 /* save_world expects lr in r0. */
13000 if (info
->lr_save_p
)
13002 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
13003 gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
));
13004 RTX_FRAME_RELATED_P (insn
) = 1;
13007 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13008 assumptions about the offsets of various bits of the stack
13009 frame. Abort if things aren't what they should be. */
13010 if (info
->gp_save_offset
!= -220
13011 || info
->fp_save_offset
!= -144
13012 || info
->lr_save_offset
!= 8
13013 || info
->cr_save_offset
!= 4
13015 || !info
->lr_save_p
13016 || (current_function_calls_eh_return
&& info
->ehrd_offset
!= -432)
13017 || (info
->vrsave_save_offset
!= -224
13018 || info
->altivec_save_offset
!= (-224 -16 -192)))
13021 treg
= gen_rtx_REG (SImode
, 11);
13022 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
13024 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
13025 in R11. It also clobbers R12, so beware! */
13027 /* Preserve CR2 for save_world prologues */
13029 sz
+= 32 - info
->first_gp_reg_save
;
13030 sz
+= 64 - info
->first_fp_reg_save
;
13031 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
13032 p
= rtvec_alloc (sz
);
13034 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
13035 gen_rtx_REG (Pmode
,
13036 LINK_REGISTER_REGNUM
));
13037 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
13038 gen_rtx_SYMBOL_REF (Pmode
,
13040 /* We do floats first so that the instruction pattern matches
13042 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
13044 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
13045 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13046 GEN_INT (info
->fp_save_offset
13047 + sp_offset
+ 8 * i
));
13048 rtx mem
= gen_rtx_MEM (DFmode
, addr
);
13049 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13051 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
13053 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
13055 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
13056 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13057 GEN_INT (info
->altivec_save_offset
13058 + sp_offset
+ 16 * i
));
13059 rtx mem
= gen_rtx_MEM (V4SImode
, addr
);
13060 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13062 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
13064 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13066 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
13067 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13068 GEN_INT (info
->gp_save_offset
13069 + sp_offset
+ reg_size
* i
));
13070 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13071 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13073 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
13077 /* CR register traditionally saved as CR2. */
13078 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
13079 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13080 GEN_INT (info
->cr_save_offset
13082 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13083 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13085 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
13087 /* Prevent any attempt to delete the setting of r0 and treg! */
13088 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
13089 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
, treg
);
13090 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
, sp_reg_rtx
);
13092 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13093 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13094 NULL_RTX
, NULL_RTX
);
13096 if (current_function_calls_eh_return
)
13101 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
13102 if (regno
== INVALID_REGNUM
)
13104 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
13105 info
->ehrd_offset
+ sp_offset
13106 + reg_size
* (int) i
,
13112 /* Save AltiVec registers if needed. */
13113 if (! info
->world_save_p
&& TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
13117 /* There should be a non inline version of this, for when we
13118 are saving lots of vector registers. */
13119 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
13120 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
13122 rtx areg
, savereg
, mem
;
13125 offset
= info
->altivec_save_offset
+ sp_offset
13126 + 16 * (i
- info
->first_altivec_reg_save
);
13128 savereg
= gen_rtx_REG (V4SImode
, i
);
13130 areg
= gen_rtx_REG (Pmode
, 0);
13131 emit_move_insn (areg
, GEN_INT (offset
));
13133 /* AltiVec addressing mode is [reg+reg]. */
13134 mem
= gen_rtx_MEM (V4SImode
,
13135 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
13137 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13139 insn
= emit_move_insn (mem
, savereg
);
13141 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13142 areg
, GEN_INT (offset
));
13146 /* VRSAVE is a bit vector representing which AltiVec registers
13147 are used. The OS uses this to determine which vector
13148 registers to save on a context switch. We need to save
13149 VRSAVE on the stack frame, add whatever AltiVec registers we
13150 used in this function, and do the corresponding magic in the
13153 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
13154 && ! info
->world_save_p
&& info
->vrsave_mask
!= 0)
13156 rtx reg
, mem
, vrsave
;
13159 /* Get VRSAVE onto a GPR. */
13160 reg
= gen_rtx_REG (SImode
, 12);
13161 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
13163 emit_insn (gen_get_vrsave_internal (reg
));
13165 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
13168 offset
= info
->vrsave_save_offset
+ sp_offset
;
13170 = gen_rtx_MEM (SImode
,
13171 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, GEN_INT (offset
)));
13172 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13173 insn
= emit_move_insn (mem
, reg
);
13175 /* Include the registers in the mask. */
13176 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
13178 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
13181 /* If we use the link register, get it into r0. */
13182 if (! info
->world_save_p
&& info
->lr_save_p
)
13184 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
13185 gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
));
13186 RTX_FRAME_RELATED_P (insn
) = 1;
13189 /* If we need to save CR, put it into r12. */
13190 if (! info
->world_save_p
&& info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
13194 cr_save_rtx
= gen_rtx_REG (SImode
, 12);
13195 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
13196 RTX_FRAME_RELATED_P (insn
) = 1;
13197 /* Now, there's no way that dwarf2out_frame_debug_expr is going
13198 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
13199 But that's OK. All we have to do is specify that _one_ condition
13200 code register is saved in this stack slot. The thrower's epilogue
13201 will then restore all the call-saved registers.
13202 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
13203 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
13204 gen_rtx_REG (SImode
, CR2_REGNO
));
13205 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
13210 /* Do any required saving of fpr's. If only one or two to save, do
13211 it ourselves. Otherwise, call function. */
13212 if (! info
->world_save_p
&& saving_FPRs_inline
)
13215 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
13216 if ((regs_ever_live
[info
->first_fp_reg_save
+i
]
13217 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
13218 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, DFmode
,
13219 info
->first_fp_reg_save
+ i
,
13220 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
13223 else if (! info
->world_save_p
&& info
->first_fp_reg_save
!= 64)
13227 const char *alloc_rname
;
13229 p
= rtvec_alloc (2 + 64 - info
->first_fp_reg_save
);
13231 RTVEC_ELT (p
, 0) = gen_rtx_CLOBBER (VOIDmode
,
13232 gen_rtx_REG (Pmode
,
13233 LINK_REGISTER_REGNUM
));
13234 sprintf (rname
, "%s%d%s", SAVE_FP_PREFIX
,
13235 info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
);
13236 alloc_rname
= ggc_strdup (rname
);
13237 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
13238 gen_rtx_SYMBOL_REF (Pmode
,
13240 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
13242 rtx addr
, reg
, mem
;
13243 reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
13244 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13245 GEN_INT (info
->fp_save_offset
13246 + sp_offset
+ 8*i
));
13247 mem
= gen_rtx_MEM (DFmode
, addr
);
13248 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13250 RTVEC_ELT (p
, i
+ 2) = gen_rtx_SET (VOIDmode
, mem
, reg
);
13252 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13253 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13254 NULL_RTX
, NULL_RTX
);
13257 /* Save GPRs. This is done as a PARALLEL if we are using
13258 the store-multiple instructions. */
13259 if (! info
->world_save_p
&& using_store_multiple
)
13263 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
13264 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13266 rtx addr
, reg
, mem
;
13267 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
13268 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13269 GEN_INT (info
->gp_save_offset
13272 mem
= gen_rtx_MEM (reg_mode
, addr
);
13273 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13275 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
13277 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13278 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13279 NULL_RTX
, NULL_RTX
);
13281 else if (! info
->world_save_p
)
13284 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13285 if ((regs_ever_live
[info
->first_gp_reg_save
+i
]
13286 && (! call_used_regs
[info
->first_gp_reg_save
+i
]
13287 || (i
+info
->first_gp_reg_save
13288 == RS6000_PIC_OFFSET_TABLE_REGNUM
13289 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
13290 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
13291 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
13292 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))))
13294 rtx addr
, reg
, mem
;
13295 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
13297 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
13299 int offset
= info
->spe_gp_save_offset
+ sp_offset
+ 8 * i
;
13302 if (!SPE_CONST_OFFSET_OK (offset
))
13304 b
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
13305 emit_move_insn (b
, GEN_INT (offset
));
13308 b
= GEN_INT (offset
);
13310 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, b
);
13311 mem
= gen_rtx_MEM (V2SImode
, addr
);
13312 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13313 insn
= emit_move_insn (mem
, reg
);
13315 if (GET_CODE (b
) == CONST_INT
)
13316 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13317 NULL_RTX
, NULL_RTX
);
13319 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13320 b
, GEN_INT (offset
));
13324 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13325 GEN_INT (info
->gp_save_offset
13328 mem
= gen_rtx_MEM (reg_mode
, addr
);
13329 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13331 insn
= emit_move_insn (mem
, reg
);
13332 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13333 NULL_RTX
, NULL_RTX
);
13338 /* ??? There's no need to emit actual instructions here, but it's the
13339 easiest way to get the frame unwind information emitted. */
13340 if (! info
->world_save_p
&& current_function_calls_eh_return
)
13342 unsigned int i
, regno
;
13344 /* In AIX ABI we need to pretend we save r2 here. */
13347 rtx addr
, reg
, mem
;
13349 reg
= gen_rtx_REG (reg_mode
, 2);
13350 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13351 GEN_INT (sp_offset
+ 5 * reg_size
));
13352 mem
= gen_rtx_MEM (reg_mode
, addr
);
13353 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13355 insn
= emit_move_insn (mem
, reg
);
13356 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13357 NULL_RTX
, NULL_RTX
);
13358 PATTERN (insn
) = gen_blockage ();
13363 regno
= EH_RETURN_DATA_REGNO (i
);
13364 if (regno
== INVALID_REGNUM
)
13367 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
13368 info
->ehrd_offset
+ sp_offset
13369 + reg_size
* (int) i
,
13374 /* Save lr if we used it. */
13375 if (! info
->world_save_p
&& info
->lr_save_p
)
13377 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13378 GEN_INT (info
->lr_save_offset
+ sp_offset
));
13379 rtx reg
= gen_rtx_REG (Pmode
, 0);
13380 rtx mem
= gen_rtx_MEM (Pmode
, addr
);
13381 /* This should not be of rs6000_sr_alias_set, because of
13382 __builtin_return_address. */
13384 insn
= emit_move_insn (mem
, reg
);
13385 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13386 NULL_RTX
, NULL_RTX
);
13389 /* Save CR if we use any that must be preserved. */
13390 if (! info
->world_save_p
&& info
->cr_save_p
)
13392 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13393 GEN_INT (info
->cr_save_offset
+ sp_offset
));
13394 rtx mem
= gen_rtx_MEM (SImode
, addr
);
13395 /* See the large comment above about why CR2_REGNO is used. */
13396 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
13398 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13400 /* If r12 was used to hold the original sp, copy cr into r0 now
13402 if (REGNO (frame_reg_rtx
) == 12)
13406 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
13407 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
13408 RTX_FRAME_RELATED_P (insn
) = 1;
13409 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
13410 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
13415 insn
= emit_move_insn (mem
, cr_save_rtx
);
13417 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13418 NULL_RTX
, NULL_RTX
);
13421 /* Update stack and set back pointer unless this is V.4,
13422 for which it was done previously. */
13423 if (! info
->world_save_p
&& info
->push_p
13424 && !(DEFAULT_ABI
== ABI_V4
|| current_function_calls_eh_return
))
13425 rs6000_emit_allocate_stack (info
->total_size
, FALSE
);
13427 /* Set frame pointer, if needed. */
13428 if (frame_pointer_needed
)
13430 insn
= emit_move_insn (gen_rtx_REG (Pmode
, FRAME_POINTER_REGNUM
),
13432 RTX_FRAME_RELATED_P (insn
) = 1;
13435 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
13436 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
13437 || (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1
13438 && regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
]))
13440 /* If emit_load_toc_table will use the link register, we need to save
13441 it. We use R12 for this purpose because emit_load_toc_table
13442 can use register 0. This allows us to use a plain 'blr' to return
13443 from the procedure more often. */
13444 int save_LR_around_toc_setup
= (TARGET_ELF
13445 && DEFAULT_ABI
!= ABI_AIX
13447 && ! info
->lr_save_p
13448 && EXIT_BLOCK_PTR
->pred
!= NULL
);
13449 if (save_LR_around_toc_setup
)
13451 rtx lr
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
13453 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
13454 rs6000_maybe_dead (insn
);
13455 RTX_FRAME_RELATED_P (insn
) = 1;
13457 rs6000_emit_load_toc_table (TRUE
);
13459 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
13460 rs6000_maybe_dead (insn
);
13461 RTX_FRAME_RELATED_P (insn
) = 1;
13464 rs6000_emit_load_toc_table (TRUE
);
13468 if (DEFAULT_ABI
== ABI_DARWIN
13469 && flag_pic
&& current_function_uses_pic_offset_table
)
13471 rtx lr
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
13472 rtx src
= machopic_function_base_sym ();
13474 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr
, src
)));
13476 insn
= emit_move_insn (gen_rtx_REG (Pmode
,
13477 RS6000_PIC_OFFSET_TABLE_REGNUM
),
13479 rs6000_maybe_dead (insn
);
13484 /* Write function prologue. */
13487 rs6000_output_function_prologue (FILE *file
,
13488 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13490 rs6000_stack_t
*info
= rs6000_stack_info ();
13492 if (TARGET_DEBUG_STACK
)
13493 debug_stack_info (info
);
13495 /* Write .extern for any function we will call to save and restore
13497 if (info
->first_fp_reg_save
< 64
13498 && !FP_SAVE_INLINE (info
->first_fp_reg_save
))
13499 fprintf (file
, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
13500 SAVE_FP_PREFIX
, info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
,
13501 RESTORE_FP_PREFIX
, info
->first_fp_reg_save
- 32,
13502 RESTORE_FP_SUFFIX
);
13504 /* Write .extern for AIX common mode routines, if needed. */
13505 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
13507 fputs ("\t.extern __mulh\n", file
);
13508 fputs ("\t.extern __mull\n", file
);
13509 fputs ("\t.extern __divss\n", file
);
13510 fputs ("\t.extern __divus\n", file
);
13511 fputs ("\t.extern __quoss\n", file
);
13512 fputs ("\t.extern __quous\n", file
);
13513 common_mode_defined
= 1;
13516 if (! HAVE_prologue
)
13520 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13521 the "toplevel" insn chain. */
13522 emit_note (NOTE_INSN_DELETED
);
13523 rs6000_emit_prologue ();
13524 emit_note (NOTE_INSN_DELETED
);
13526 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13530 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
13532 INSN_ADDRESSES_NEW (insn
, addr
);
13537 if (TARGET_DEBUG_STACK
)
13538 debug_rtx_list (get_insns (), 100);
13539 final (get_insns (), file
, FALSE
, FALSE
);
13543 rs6000_pic_labelno
++;
13546 /* Emit function epilogue as insns.
13548 At present, dwarf2out_frame_debug_expr doesn't understand
13549 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13550 anywhere in the epilogue. Most of the insns below would in any case
13551 need special notes to explain where r11 is in relation to the stack. */
13554 rs6000_emit_epilogue (int sibcall
)
13556 rs6000_stack_t
*info
;
13557 int restoring_FPRs_inline
;
13558 int using_load_multiple
;
13559 int using_mfcr_multiple
;
13560 int use_backchain_to_restore_sp
;
13562 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
13563 rtx frame_reg_rtx
= sp_reg_rtx
;
13564 enum machine_mode reg_mode
= Pmode
;
13565 int reg_size
= TARGET_32BIT
? 4 : 8;
13568 info
= rs6000_stack_info ();
13570 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
13572 reg_mode
= V2SImode
;
13576 using_load_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
13577 && (!TARGET_SPE_ABI
13578 || info
->spe_64bit_regs_used
== 0)
13579 && info
->first_gp_reg_save
< 31);
13580 restoring_FPRs_inline
= (sibcall
13581 || current_function_calls_eh_return
13582 || info
->first_fp_reg_save
== 64
13583 || FP_SAVE_INLINE (info
->first_fp_reg_save
));
13584 use_backchain_to_restore_sp
= (frame_pointer_needed
13585 || current_function_calls_alloca
13586 || info
->total_size
> 32767);
13587 using_mfcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
13588 || rs6000_cpu
== PROCESSOR_PPC603
13589 || rs6000_cpu
== PROCESSOR_PPC750
13592 if (info
->world_save_p
)
13596 const char *alloc_rname
;
13599 /* eh_rest_world_r10 will return to the location saved in the LR
13600 stack slot (which is not likely to be our caller.)
13601 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13602 rest_world is similar, except any R10 parameter is ignored.
13603 The exception-handling stuff that was here in 2.95 is no
13604 longer necessary. */
13608 + 32 - info
->first_gp_reg_save
13609 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
13610 + 63 + 1 - info
->first_fp_reg_save
);
13612 strcpy (rname
, (current_function_calls_eh_return
) ?
13613 "*eh_rest_world_r10" : "*rest_world");
13614 alloc_rname
= ggc_strdup (rname
);
13617 RTVEC_ELT (p
, j
++) = gen_rtx_RETURN (VOIDmode
);
13618 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
13619 gen_rtx_REG (Pmode
,
13620 LINK_REGISTER_REGNUM
));
13622 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
13623 /* The instruction pattern requires a clobber here;
13624 it is shared with the restVEC helper. */
13626 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
13629 /* CR register traditionally saved as CR2. */
13630 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
13631 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13632 GEN_INT (info
->cr_save_offset
));
13633 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13634 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13636 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
13639 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13641 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
13642 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13643 GEN_INT (info
->gp_save_offset
13645 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13646 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13648 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
13650 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
13652 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
13653 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13654 GEN_INT (info
->altivec_save_offset
13656 rtx mem
= gen_rtx_MEM (V4SImode
, addr
);
13657 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13659 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
13661 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
13663 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
13664 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13665 GEN_INT (info
->fp_save_offset
13667 rtx mem
= gen_rtx_MEM (DFmode
, addr
);
13668 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13670 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
13673 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
13675 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
13677 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
13679 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
13681 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
13682 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13687 /* If we have a frame pointer, a call to alloca, or a large stack
13688 frame, restore the old stack pointer using the backchain. Otherwise,
13689 we know what size to update it with. */
13690 if (use_backchain_to_restore_sp
)
13692 /* Under V.4, don't reset the stack pointer until after we're done
13693 loading the saved registers. */
13694 if (DEFAULT_ABI
== ABI_V4
)
13695 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
13697 emit_move_insn (frame_reg_rtx
,
13698 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
13701 else if (info
->push_p
)
13703 if (DEFAULT_ABI
== ABI_V4
13704 || current_function_calls_eh_return
)
13705 sp_offset
= info
->total_size
;
13708 emit_insn (TARGET_32BIT
13709 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
13710 GEN_INT (info
->total_size
))
13711 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
13712 GEN_INT (info
->total_size
)));
13716 /* Restore AltiVec registers if needed. */
13717 if (TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
13721 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
13722 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
13724 rtx addr
, areg
, mem
;
13726 areg
= gen_rtx_REG (Pmode
, 0);
13728 (areg
, GEN_INT (info
->altivec_save_offset
13730 + 16 * (i
- info
->first_altivec_reg_save
)));
13732 /* AltiVec addressing mode is [reg+reg]. */
13733 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
13734 mem
= gen_rtx_MEM (V4SImode
, addr
);
13735 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13737 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
13741 /* Restore VRSAVE if needed. */
13742 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
13743 && info
->vrsave_mask
!= 0)
13745 rtx addr
, mem
, reg
;
13747 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13748 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
13749 mem
= gen_rtx_MEM (SImode
, addr
);
13750 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13751 reg
= gen_rtx_REG (SImode
, 12);
13752 emit_move_insn (reg
, mem
);
13754 emit_insn (generate_set_vrsave (reg
, info
, 1));
13757 /* Get the old lr if we saved it. */
13758 if (info
->lr_save_p
)
13760 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
13761 info
->lr_save_offset
+ sp_offset
);
13763 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13765 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
13768 /* Get the old cr if we saved it. */
13769 if (info
->cr_save_p
)
13771 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13772 GEN_INT (info
->cr_save_offset
+ sp_offset
));
13773 rtx mem
= gen_rtx_MEM (SImode
, addr
);
13775 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13777 emit_move_insn (gen_rtx_REG (SImode
, 12), mem
);
13780 /* Set LR here to try to overlap restores below. */
13781 if (info
->lr_save_p
)
13782 emit_move_insn (gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
),
13783 gen_rtx_REG (Pmode
, 0));
13785 /* Load exception handler data registers, if needed. */
13786 if (current_function_calls_eh_return
)
13788 unsigned int i
, regno
;
13792 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13793 GEN_INT (sp_offset
+ 5 * reg_size
));
13794 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13796 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13798 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
13805 regno
= EH_RETURN_DATA_REGNO (i
);
13806 if (regno
== INVALID_REGNUM
)
13809 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
13810 info
->ehrd_offset
+ sp_offset
13811 + reg_size
* (int) i
);
13812 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13814 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
13818 /* Restore GPRs. This is done as a PARALLEL if we are using
13819 the load-multiple instructions. */
13820 if (using_load_multiple
)
13823 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
13824 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13826 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13827 GEN_INT (info
->gp_save_offset
13830 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13832 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13835 gen_rtx_SET (VOIDmode
,
13836 gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
13839 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13842 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13843 if ((regs_ever_live
[info
->first_gp_reg_save
+i
]
13844 && (! call_used_regs
[info
->first_gp_reg_save
+i
]
13845 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
13846 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
13847 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
13848 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
13849 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))))
13851 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13852 GEN_INT (info
->gp_save_offset
13855 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13857 /* Restore 64-bit quantities for SPE. */
13858 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
13860 int offset
= info
->spe_gp_save_offset
+ sp_offset
+ 8 * i
;
13863 if (!SPE_CONST_OFFSET_OK (offset
))
13865 b
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
13866 emit_move_insn (b
, GEN_INT (offset
));
13869 b
= GEN_INT (offset
);
13871 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, b
);
13872 mem
= gen_rtx_MEM (V2SImode
, addr
);
13875 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13877 emit_move_insn (gen_rtx_REG (reg_mode
,
13878 info
->first_gp_reg_save
+ i
), mem
);
13881 /* Restore fpr's if we need to do it without calling a function. */
13882 if (restoring_FPRs_inline
)
13883 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
13884 if ((regs_ever_live
[info
->first_fp_reg_save
+i
]
13885 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
13888 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13889 GEN_INT (info
->fp_save_offset
13892 mem
= gen_rtx_MEM (DFmode
, addr
);
13893 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13895 emit_move_insn (gen_rtx_REG (DFmode
,
13896 info
->first_fp_reg_save
+ i
),
13900 /* If we saved cr, restore it here. Just those that were used. */
13901 if (info
->cr_save_p
)
13903 rtx r12_rtx
= gen_rtx_REG (SImode
, 12);
13906 if (using_mfcr_multiple
)
13908 for (i
= 0; i
< 8; i
++)
13909 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
13915 if (using_mfcr_multiple
&& count
> 1)
13920 p
= rtvec_alloc (count
);
13923 for (i
= 0; i
< 8; i
++)
13924 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
13926 rtvec r
= rtvec_alloc (2);
13927 RTVEC_ELT (r
, 0) = r12_rtx
;
13928 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
13929 RTVEC_ELT (p
, ndx
) =
13930 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
13931 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
13934 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13939 for (i
= 0; i
< 8; i
++)
13940 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
13942 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
13948 /* If this is V.4, unwind the stack pointer after all of the loads
13949 have been done. We need to emit a block here so that sched
13950 doesn't decide to move the sp change before the register restores
13951 (which may not have any obvious dependency on the stack). This
13952 doesn't hurt performance, because there is no scheduling that can
13953 be done after this point. */
13954 if (DEFAULT_ABI
== ABI_V4
13955 || current_function_calls_eh_return
)
13957 if (frame_reg_rtx
!= sp_reg_rtx
)
13958 rs6000_emit_stack_tie ();
13960 if (use_backchain_to_restore_sp
)
13962 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
13964 else if (sp_offset
!= 0)
13966 emit_insn (TARGET_32BIT
13967 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
13968 GEN_INT (sp_offset
))
13969 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
13970 GEN_INT (sp_offset
)));
13974 if (current_function_calls_eh_return
)
13976 rtx sa
= EH_RETURN_STACKADJ_RTX
;
13977 emit_insn (TARGET_32BIT
13978 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
, sa
)
13979 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
, sa
));
13985 if (! restoring_FPRs_inline
)
13986 p
= rtvec_alloc (3 + 64 - info
->first_fp_reg_save
);
13988 p
= rtvec_alloc (2);
13990 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
13991 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
13992 gen_rtx_REG (Pmode
,
13993 LINK_REGISTER_REGNUM
));
13995 /* If we have to restore more than two FP registers, branch to the
13996 restore function. It will return to our caller. */
13997 if (! restoring_FPRs_inline
)
14001 const char *alloc_rname
;
14003 sprintf (rname
, "%s%d%s", RESTORE_FP_PREFIX
,
14004 info
->first_fp_reg_save
- 32, RESTORE_FP_SUFFIX
);
14005 alloc_rname
= ggc_strdup (rname
);
14006 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
,
14007 gen_rtx_SYMBOL_REF (Pmode
,
14010 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14013 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
14014 GEN_INT (info
->fp_save_offset
+ 8*i
));
14015 mem
= gen_rtx_MEM (DFmode
, addr
);
14016 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14018 RTVEC_ELT (p
, i
+3) =
14019 gen_rtx_SET (VOIDmode
,
14020 gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
),
14025 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14029 /* Write function epilogue. */
14032 rs6000_output_function_epilogue (FILE *file
,
14033 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
14035 rs6000_stack_t
*info
= rs6000_stack_info ();
14037 if (! HAVE_epilogue
)
14039 rtx insn
= get_last_insn ();
14040 /* If the last insn was a BARRIER, we don't have to write anything except
14041 the trace table. */
14042 if (GET_CODE (insn
) == NOTE
)
14043 insn
= prev_nonnote_insn (insn
);
14044 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
14046 /* This is slightly ugly, but at least we don't have two
14047 copies of the epilogue-emitting code. */
14050 /* A NOTE_INSN_DELETED is supposed to be at the start
14051 and end of the "toplevel" insn chain. */
14052 emit_note (NOTE_INSN_DELETED
);
14053 rs6000_emit_epilogue (FALSE
);
14054 emit_note (NOTE_INSN_DELETED
);
14056 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14060 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
14062 INSN_ADDRESSES_NEW (insn
, addr
);
14067 if (TARGET_DEBUG_STACK
)
14068 debug_rtx_list (get_insns (), 100);
14069 final (get_insns (), file
, FALSE
, FALSE
);
14075 macho_branch_islands ();
14076 /* Mach-O doesn't support labels at the end of objects, so if
14077 it looks like we might want one, insert a NOP. */
14079 rtx insn
= get_last_insn ();
14082 && NOTE_LINE_NUMBER (insn
) != NOTE_INSN_DELETED_LABEL
)
14083 insn
= PREV_INSN (insn
);
14087 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_DELETED_LABEL
)))
14088 fputs ("\tnop\n", file
);
14092 /* Output a traceback table here. See /usr/include/sys/debug.h for info
14095 We don't output a traceback table if -finhibit-size-directive was
14096 used. The documentation for -finhibit-size-directive reads
14097 ``don't output a @code{.size} assembler directive, or anything
14098 else that would cause trouble if the function is split in the
14099 middle, and the two halves are placed at locations far apart in
14100 memory.'' The traceback table has this property, since it
14101 includes the offset from the start of the function to the
14102 traceback table itself.
14104 System V.4 Powerpc's (and the embedded ABI derived from it) use a
14105 different traceback table. */
14106 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
14107 && rs6000_traceback
!= traceback_none
)
14109 const char *fname
= NULL
;
14110 const char *language_string
= lang_hooks
.name
;
14111 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
14113 int optional_tbtab
;
14115 if (rs6000_traceback
== traceback_full
)
14116 optional_tbtab
= 1;
14117 else if (rs6000_traceback
== traceback_part
)
14118 optional_tbtab
= 0;
14120 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
14122 if (optional_tbtab
)
14124 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
14125 while (*fname
== '.') /* V.4 encodes . in the name */
14128 /* Need label immediately before tbtab, so we can compute
14129 its offset from the function start. */
14130 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
14131 ASM_OUTPUT_LABEL (file
, fname
);
14134 /* The .tbtab pseudo-op can only be used for the first eight
14135 expressions, since it can't handle the possibly variable
14136 length fields that follow. However, if you omit the optional
14137 fields, the assembler outputs zeros for all optional fields
14138 anyways, giving each variable length field is minimum length
14139 (as defined in sys/debug.h). Thus we can not use the .tbtab
14140 pseudo-op at all. */
14142 /* An all-zero word flags the start of the tbtab, for debuggers
14143 that have to find it by searching forward from the entry
14144 point or from the current pc. */
14145 fputs ("\t.long 0\n", file
);
14147 /* Tbtab format type. Use format type 0. */
14148 fputs ("\t.byte 0,", file
);
14150 /* Language type. Unfortunately, there does not seem to be any
14151 official way to discover the language being compiled, so we
14152 use language_string.
14153 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
14154 Java is 13. Objective-C is 14. */
14155 if (! strcmp (language_string
, "GNU C"))
14157 else if (! strcmp (language_string
, "GNU F77")
14158 || ! strcmp (language_string
, "GNU F95"))
14160 else if (! strcmp (language_string
, "GNU Pascal"))
14162 else if (! strcmp (language_string
, "GNU Ada"))
14164 else if (! strcmp (language_string
, "GNU C++"))
14166 else if (! strcmp (language_string
, "GNU Java"))
14168 else if (! strcmp (language_string
, "GNU Objective-C"))
14172 fprintf (file
, "%d,", i
);
14174 /* 8 single bit fields: global linkage (not set for C extern linkage,
14175 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
14176 from start of procedure stored in tbtab, internal function, function
14177 has controlled storage, function has no toc, function uses fp,
14178 function logs/aborts fp operations. */
14179 /* Assume that fp operations are used if any fp reg must be saved. */
14180 fprintf (file
, "%d,",
14181 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
14183 /* 6 bitfields: function is interrupt handler, name present in
14184 proc table, function calls alloca, on condition directives
14185 (controls stack walks, 3 bits), saves condition reg, saves
14187 /* The `function calls alloca' bit seems to be set whenever reg 31 is
14188 set up as a frame pointer, even when there is no alloca call. */
14189 fprintf (file
, "%d,",
14190 ((optional_tbtab
<< 6)
14191 | ((optional_tbtab
& frame_pointer_needed
) << 5)
14192 | (info
->cr_save_p
<< 1)
14193 | (info
->lr_save_p
)));
14195 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
14197 fprintf (file
, "%d,",
14198 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
14200 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
14201 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
14203 if (optional_tbtab
)
14205 /* Compute the parameter info from the function decl argument
14208 int next_parm_info_bit
= 31;
14210 for (decl
= DECL_ARGUMENTS (current_function_decl
);
14211 decl
; decl
= TREE_CHAIN (decl
))
14213 rtx parameter
= DECL_INCOMING_RTL (decl
);
14214 enum machine_mode mode
= GET_MODE (parameter
);
14216 if (GET_CODE (parameter
) == REG
)
14218 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
14224 if (mode
== SFmode
)
14226 else if (mode
== DFmode
|| mode
== TFmode
)
14231 /* If only one bit will fit, don't or in this entry. */
14232 if (next_parm_info_bit
> 0)
14233 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
14234 next_parm_info_bit
-= 2;
14238 fixed_parms
+= ((GET_MODE_SIZE (mode
)
14239 + (UNITS_PER_WORD
- 1))
14241 next_parm_info_bit
-= 1;
14247 /* Number of fixed point parameters. */
14248 /* This is actually the number of words of fixed point parameters; thus
14249 an 8 byte struct counts as 2; and thus the maximum value is 8. */
14250 fprintf (file
, "%d,", fixed_parms
);
14252 /* 2 bitfields: number of floating point parameters (7 bits), parameters
14254 /* This is actually the number of fp registers that hold parameters;
14255 and thus the maximum value is 13. */
14256 /* Set parameters on stack bit if parameters are not in their original
14257 registers, regardless of whether they are on the stack? Xlc
14258 seems to set the bit when not optimizing. */
14259 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
14261 if (! optional_tbtab
)
14264 /* Optional fields follow. Some are variable length. */
14266 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
14267 11 double float. */
14268 /* There is an entry for each parameter in a register, in the order that
14269 they occur in the parameter list. Any intervening arguments on the
14270 stack are ignored. If the list overflows a long (max possible length
14271 34 bits) then completely leave off all elements that don't fit. */
14272 /* Only emit this long if there was at least one parameter. */
14273 if (fixed_parms
|| float_parms
)
14274 fprintf (file
, "\t.long %d\n", parm_info
);
14276 /* Offset from start of code to tb table. */
14277 fputs ("\t.long ", file
);
14278 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
14280 RS6000_OUTPUT_BASENAME (file
, fname
);
14282 assemble_name (file
, fname
);
14284 rs6000_output_function_entry (file
, fname
);
14287 /* Interrupt handler mask. */
14288 /* Omit this long, since we never set the interrupt handler bit
14291 /* Number of CTL (controlled storage) anchors. */
14292 /* Omit this long, since the has_ctl bit is never set above. */
14294 /* Displacement into stack of each CTL anchor. */
14295 /* Omit this list of longs, because there are no CTL anchors. */
14297 /* Length of function name. */
14300 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
14302 /* Function name. */
14303 assemble_string (fname
, strlen (fname
));
14305 /* Register for alloca automatic storage; this is always reg 31.
14306 Only emit this if the alloca bit was set above. */
14307 if (frame_pointer_needed
)
14308 fputs ("\t.byte 31\n", file
);
14310 fputs ("\t.align 2\n", file
);
14314 /* A C compound statement that outputs the assembler code for a thunk
14315 function, used to implement C++ virtual function calls with
14316 multiple inheritance. The thunk acts as a wrapper around a virtual
14317 function, adjusting the implicit object parameter before handing
14318 control off to the real function.
14320 First, emit code to add the integer DELTA to the location that
14321 contains the incoming first argument. Assume that this argument
14322 contains a pointer, and is the one used to pass the `this' pointer
14323 in C++. This is the incoming argument *before* the function
14324 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14325 values of all other incoming arguments.
14327 After the addition, emit code to jump to FUNCTION, which is a
14328 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14329 not touch the return address. Hence returning from FUNCTION will
14330 return to whoever called the current `thunk'.
14332 The effect must be as if FUNCTION had been called directly with the
14333 adjusted first argument. This macro is responsible for emitting
14334 all of the code for a thunk function; output_function_prologue()
14335 and output_function_epilogue() are not invoked.
14337 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14338 been extracted from it.) It might possibly be useful on some
14339 targets, but probably not.
14341 If you do not define this macro, the target-independent code in the
14342 C++ frontend will generate a less efficient heavyweight thunk that
14343 calls FUNCTION instead of jumping to it. The generic approach does
14344 not support varargs. */
14347 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
14348 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
14351 rtx
this, insn
, funexp
;
14353 reload_completed
= 1;
14354 epilogue_completed
= 1;
14355 no_new_pseudos
= 1;
14356 reset_block_changes ();
14358 /* Mark the end of the (empty) prologue. */
14359 emit_note (NOTE_INSN_PROLOGUE_END
);
14361 /* Find the "this" pointer. If the function returns a structure,
14362 the structure return pointer is in r3. */
14363 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
14364 this = gen_rtx_REG (Pmode
, 4);
14366 this = gen_rtx_REG (Pmode
, 3);
14368 /* Apply the constant offset, if required. */
14371 rtx delta_rtx
= GEN_INT (delta
);
14372 emit_insn (TARGET_32BIT
14373 ? gen_addsi3 (this, this, delta_rtx
)
14374 : gen_adddi3 (this, this, delta_rtx
));
14377 /* Apply the offset from the vtable, if required. */
14380 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
14381 rtx tmp
= gen_rtx_REG (Pmode
, 12);
14383 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
14384 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
14386 emit_insn (TARGET_32BIT
14387 ? gen_addsi3 (tmp
, tmp
, vcall_offset_rtx
)
14388 : gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
14389 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
14393 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
14395 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
14397 emit_insn (TARGET_32BIT
14398 ? gen_addsi3 (this, this, tmp
)
14399 : gen_adddi3 (this, this, tmp
));
14402 /* Generate a tail call to the target function. */
14403 if (!TREE_USED (function
))
14405 assemble_external (function
);
14406 TREE_USED (function
) = 1;
14408 funexp
= XEXP (DECL_RTL (function
), 0);
14409 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
14412 if (MACHOPIC_INDIRECT
)
14413 funexp
= machopic_indirect_call_target (funexp
);
14416 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14417 generate sibcall RTL explicitly to avoid constraint abort. */
14418 insn
= emit_call_insn (
14419 gen_rtx_PARALLEL (VOIDmode
,
14421 gen_rtx_CALL (VOIDmode
,
14422 funexp
, const0_rtx
),
14423 gen_rtx_USE (VOIDmode
, const0_rtx
),
14424 gen_rtx_USE (VOIDmode
,
14425 gen_rtx_REG (SImode
,
14426 LINK_REGISTER_REGNUM
)),
14427 gen_rtx_RETURN (VOIDmode
))));
14428 SIBLING_CALL_P (insn
) = 1;
14431 /* Run just enough of rest_of_compilation to get the insns emitted.
14432 There's not really enough bulk here to make other passes such as
14433 instruction scheduling worth while. Note that use_thunk calls
14434 assemble_start_function and assemble_end_function. */
14435 insn
= get_insns ();
14436 insn_locators_initialize ();
14437 shorten_branches (insn
);
14438 final_start_function (insn
, file
, 1);
14439 final (insn
, file
, 1, 0);
14440 final_end_function ();
14442 reload_completed
= 0;
14443 epilogue_completed
= 0;
14444 no_new_pseudos
= 0;
14447 /* A quick summary of the various types of 'constant-pool tables'
14450 Target Flags Name One table per
14451 AIX (none) AIX TOC object file
14452 AIX -mfull-toc AIX TOC object file
14453 AIX -mminimal-toc AIX minimal TOC translation unit
14454 SVR4/EABI (none) SVR4 SDATA object file
14455 SVR4/EABI -fpic SVR4 pic object file
14456 SVR4/EABI -fPIC SVR4 PIC translation unit
14457 SVR4/EABI -mrelocatable EABI TOC function
14458 SVR4/EABI -maix AIX TOC object file
14459 SVR4/EABI -maix -mminimal-toc
14460 AIX minimal TOC translation unit
14462 Name Reg. Set by entries contains:
14463 made by addrs? fp? sum?
14465 AIX TOC 2 crt0 as Y option option
14466 AIX minimal TOC 30 prolog gcc Y Y option
14467 SVR4 SDATA 13 crt0 gcc N Y N
14468 SVR4 pic 30 prolog ld Y not yet N
14469 SVR4 PIC 30 prolog gcc Y option option
14470 EABI TOC 30 prolog gcc Y option option
14474 /* Hash functions for the hash table. */
14477 rs6000_hash_constant (rtx k
)
14479 enum rtx_code code
= GET_CODE (k
);
14480 enum machine_mode mode
= GET_MODE (k
);
14481 unsigned result
= (code
<< 3) ^ mode
;
14482 const char *format
;
14485 format
= GET_RTX_FORMAT (code
);
14486 flen
= strlen (format
);
14492 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
14495 if (mode
!= VOIDmode
)
14496 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
14508 for (; fidx
< flen
; fidx
++)
14509 switch (format
[fidx
])
14514 const char *str
= XSTR (k
, fidx
);
14515 len
= strlen (str
);
14516 result
= result
* 613 + len
;
14517 for (i
= 0; i
< len
; i
++)
14518 result
= result
* 613 + (unsigned) str
[i
];
14523 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
14527 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
14530 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
14531 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
14535 for (i
= 0; i
< sizeof(HOST_WIDE_INT
)/sizeof(unsigned); i
++)
14536 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
14550 toc_hash_function (const void *hash_entry
)
14552 const struct toc_hash_struct
*thc
=
14553 (const struct toc_hash_struct
*) hash_entry
;
14554 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
14557 /* Compare H1 and H2 for equivalence. */
14560 toc_hash_eq (const void *h1
, const void *h2
)
14562 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
14563 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
14565 if (((const struct toc_hash_struct
*) h1
)->key_mode
14566 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
14569 return rtx_equal_p (r1
, r2
);
14572 /* These are the names given by the C++ front-end to vtables, and
14573 vtable-like objects. Ideally, this logic should not be here;
14574 instead, there should be some programmatic way of inquiring as
14575 to whether or not an object is a vtable. */
14577 #define VTABLE_NAME_P(NAME) \
14578 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
14579 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14580 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
14581 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
14582 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
14585 rs6000_output_symbol_ref (FILE *file
, rtx x
)
14587 /* Currently C++ toc references to vtables can be emitted before it
14588 is decided whether the vtable is public or private. If this is
14589 the case, then the linker will eventually complain that there is
14590 a reference to an unknown section. Thus, for vtables only,
14591 we emit the TOC reference to reference the symbol and not the
14593 const char *name
= XSTR (x
, 0);
14595 if (VTABLE_NAME_P (name
))
14597 RS6000_OUTPUT_BASENAME (file
, name
);
14600 assemble_name (file
, name
);
14603 /* Output a TOC entry. We derive the entry name from what is being
14607 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
14610 const char *name
= buf
;
14611 const char *real_name
;
14618 /* When the linker won't eliminate them, don't output duplicate
14619 TOC entries (this happens on AIX if there is any kind of TOC,
14620 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14622 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
14624 struct toc_hash_struct
*h
;
14627 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
14628 time because GGC is not initialized at that point. */
14629 if (toc_hash_table
== NULL
)
14630 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
14631 toc_hash_eq
, NULL
);
14633 h
= ggc_alloc (sizeof (*h
));
14635 h
->key_mode
= mode
;
14636 h
->labelno
= labelno
;
14638 found
= htab_find_slot (toc_hash_table
, h
, 1);
14639 if (*found
== NULL
)
14641 else /* This is indeed a duplicate.
14642 Set this label equal to that label. */
14644 fputs ("\t.set ", file
);
14645 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
14646 fprintf (file
, "%d,", labelno
);
14647 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
14648 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
14654 /* If we're going to put a double constant in the TOC, make sure it's
14655 aligned properly when strict alignment is on. */
14656 if (GET_CODE (x
) == CONST_DOUBLE
14657 && STRICT_ALIGNMENT
14658 && GET_MODE_BITSIZE (mode
) >= 64
14659 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
14660 ASM_OUTPUT_ALIGN (file
, 3);
14663 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
14665 /* Handle FP constants specially. Note that if we have a minimal
14666 TOC, things we put here aren't actually in the TOC, so we can allow
14668 if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == TFmode
)
14670 REAL_VALUE_TYPE rv
;
14673 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
14674 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
14678 if (TARGET_MINIMAL_TOC
)
14679 fputs (DOUBLE_INT_ASM_OP
, file
);
14681 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14682 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
14683 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
14684 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
14685 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
14686 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
14691 if (TARGET_MINIMAL_TOC
)
14692 fputs ("\t.long ", file
);
14694 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14695 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
14696 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
14697 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14698 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
14699 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
14703 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
14705 REAL_VALUE_TYPE rv
;
14708 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
14709 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
14713 if (TARGET_MINIMAL_TOC
)
14714 fputs (DOUBLE_INT_ASM_OP
, file
);
14716 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
14717 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
14718 fprintf (file
, "0x%lx%08lx\n",
14719 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
14724 if (TARGET_MINIMAL_TOC
)
14725 fputs ("\t.long ", file
);
14727 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
14728 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
14729 fprintf (file
, "0x%lx,0x%lx\n",
14730 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
14734 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
14736 REAL_VALUE_TYPE rv
;
14739 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
14740 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
14744 if (TARGET_MINIMAL_TOC
)
14745 fputs (DOUBLE_INT_ASM_OP
, file
);
14747 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
14748 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
14753 if (TARGET_MINIMAL_TOC
)
14754 fputs ("\t.long ", file
);
14756 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
14757 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
14761 else if (GET_MODE (x
) == VOIDmode
14762 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
14764 unsigned HOST_WIDE_INT low
;
14765 HOST_WIDE_INT high
;
14767 if (GET_CODE (x
) == CONST_DOUBLE
)
14769 low
= CONST_DOUBLE_LOW (x
);
14770 high
= CONST_DOUBLE_HIGH (x
);
14773 #if HOST_BITS_PER_WIDE_INT == 32
14776 high
= (low
& 0x80000000) ? ~0 : 0;
14780 low
= INTVAL (x
) & 0xffffffff;
14781 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
14785 /* TOC entries are always Pmode-sized, but since this
14786 is a bigendian machine then if we're putting smaller
14787 integer constants in the TOC we have to pad them.
14788 (This is still a win over putting the constants in
14789 a separate constant pool, because then we'd have
14790 to have both a TOC entry _and_ the actual constant.)
14792 For a 32-bit target, CONST_INT values are loaded and shifted
14793 entirely within `low' and can be stored in one TOC entry. */
14795 if (TARGET_64BIT
&& POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
14796 abort ();/* It would be easy to make this work, but it doesn't now. */
14798 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
14800 #if HOST_BITS_PER_WIDE_INT == 32
14801 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
14802 POINTER_SIZE
, &low
, &high
, 0);
14805 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
14806 high
= (HOST_WIDE_INT
) low
>> 32;
14813 if (TARGET_MINIMAL_TOC
)
14814 fputs (DOUBLE_INT_ASM_OP
, file
);
14816 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
14817 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
14818 fprintf (file
, "0x%lx%08lx\n",
14819 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
14824 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
14826 if (TARGET_MINIMAL_TOC
)
14827 fputs ("\t.long ", file
);
14829 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
14830 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
14831 fprintf (file
, "0x%lx,0x%lx\n",
14832 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
14836 if (TARGET_MINIMAL_TOC
)
14837 fputs ("\t.long ", file
);
14839 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
14840 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
14846 if (GET_CODE (x
) == CONST
)
14848 if (GET_CODE (XEXP (x
, 0)) != PLUS
)
14851 base
= XEXP (XEXP (x
, 0), 0);
14852 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
14855 if (GET_CODE (base
) == SYMBOL_REF
)
14856 name
= XSTR (base
, 0);
14857 else if (GET_CODE (base
) == LABEL_REF
)
14858 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (base
, 0)));
14859 else if (GET_CODE (base
) == CODE_LABEL
)
14860 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
14864 real_name
= (*targetm
.strip_name_encoding
) (name
);
14865 if (TARGET_MINIMAL_TOC
)
14866 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
14869 fprintf (file
, "\t.tc %s", real_name
);
14872 fprintf (file
, ".N%d", - offset
);
14874 fprintf (file
, ".P%d", offset
);
14876 fputs ("[TC],", file
);
14879 /* Currently C++ toc references to vtables can be emitted before it
14880 is decided whether the vtable is public or private. If this is
14881 the case, then the linker will eventually complain that there is
14882 a TOC reference to an unknown section. Thus, for vtables only,
14883 we emit the TOC reference to reference the symbol and not the
14885 if (VTABLE_NAME_P (name
))
14887 RS6000_OUTPUT_BASENAME (file
, name
);
14889 fprintf (file
, "%d", offset
);
14890 else if (offset
> 0)
14891 fprintf (file
, "+%d", offset
);
14894 output_addr_const (file
, x
);
14898 /* Output an assembler pseudo-op to write an ASCII string of N characters
14899 starting at P to FILE.
14901 On the RS/6000, we have to do this using the .byte operation and
14902 write out special characters outside the quoted string.
14903 Also, the assembler is broken; very long strings are truncated,
14904 so we must artificially break them up early. */
14907 output_ascii (FILE *file
, const char *p
, int n
)
14910 int i
, count_string
;
14911 const char *for_string
= "\t.byte \"";
14912 const char *for_decimal
= "\t.byte ";
14913 const char *to_close
= NULL
;
14916 for (i
= 0; i
< n
; i
++)
14919 if (c
>= ' ' && c
< 0177)
14922 fputs (for_string
, file
);
14925 /* Write two quotes to get one. */
14933 for_decimal
= "\"\n\t.byte ";
14937 if (count_string
>= 512)
14939 fputs (to_close
, file
);
14941 for_string
= "\t.byte \"";
14942 for_decimal
= "\t.byte ";
14950 fputs (for_decimal
, file
);
14951 fprintf (file
, "%d", c
);
14953 for_string
= "\n\t.byte \"";
14954 for_decimal
= ", ";
14960 /* Now close the string if we have written one. Then end the line. */
14962 fputs (to_close
, file
);
14965 /* Generate a unique section name for FILENAME for a section type
14966 represented by SECTION_DESC. Output goes into BUF.
14968 SECTION_DESC can be any string, as long as it is different for each
14969 possible section type.
14971 We name the section in the same manner as xlc. The name begins with an
14972 underscore followed by the filename (after stripping any leading directory
14973 names) with the last period replaced by the string SECTION_DESC. If
14974 FILENAME does not contain a period, SECTION_DESC is appended to the end of
14978 rs6000_gen_section_name (char **buf
, const char *filename
,
14979 const char *section_desc
)
14981 const char *q
, *after_last_slash
, *last_period
= 0;
14985 after_last_slash
= filename
;
14986 for (q
= filename
; *q
; q
++)
14989 after_last_slash
= q
+ 1;
14990 else if (*q
== '.')
14994 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
14995 *buf
= (char *) xmalloc (len
);
15000 for (q
= after_last_slash
; *q
; q
++)
15002 if (q
== last_period
)
15004 strcpy (p
, section_desc
);
15005 p
+= strlen (section_desc
);
15009 else if (ISALNUM (*q
))
15013 if (last_period
== 0)
15014 strcpy (p
, section_desc
);
15019 /* Emit profile function. */
15022 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
15024 if (TARGET_PROFILE_KERNEL
)
15027 if (DEFAULT_ABI
== ABI_AIX
)
15029 #ifndef NO_PROFILE_COUNTERS
15030 # define NO_PROFILE_COUNTERS 0
15032 if (NO_PROFILE_COUNTERS
)
15033 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 0);
15037 const char *label_name
;
15040 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
15041 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
15042 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
15044 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 1,
15048 else if (DEFAULT_ABI
== ABI_DARWIN
)
15050 const char *mcount_name
= RS6000_MCOUNT
;
15051 int caller_addr_regno
= LINK_REGISTER_REGNUM
;
15053 /* Be conservative and always set this, at least for now. */
15054 current_function_uses_pic_offset_table
= 1;
15057 /* For PIC code, set up a stub and collect the caller's address
15058 from r0, which is where the prologue puts it. */
15059 if (MACHOPIC_INDIRECT
15060 && current_function_uses_pic_offset_table
)
15061 caller_addr_regno
= 0;
15063 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
15065 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
15069 /* Write function profiler code. */
15072 output_function_profiler (FILE *file
, int labelno
)
15077 switch (DEFAULT_ABI
)
15086 warning ("no profiling of 64-bit code for this ABI");
15089 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
15090 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
15093 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
15094 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
15095 reg_names
[0], save_lr
, reg_names
[1]);
15096 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
15097 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
15098 assemble_name (file
, buf
);
15099 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
15101 else if (flag_pic
> 1)
15103 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
15104 reg_names
[0], save_lr
, reg_names
[1]);
15105 /* Now, we need to get the address of the label. */
15106 fputs ("\tbl 1f\n\t.long ", file
);
15107 assemble_name (file
, buf
);
15108 fputs ("-.\n1:", file
);
15109 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
15110 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
15111 reg_names
[0], reg_names
[11]);
15112 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
15113 reg_names
[0], reg_names
[0], reg_names
[11]);
15117 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
15118 assemble_name (file
, buf
);
15119 fputs ("@ha\n", file
);
15120 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
15121 reg_names
[0], save_lr
, reg_names
[1]);
15122 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
15123 assemble_name (file
, buf
);
15124 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
15127 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
15128 fprintf (file
, "\tbl %s%s\n",
15129 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
15134 if (!TARGET_PROFILE_KERNEL
)
15136 /* Don't do anything, done in output_profile_hook (). */
15143 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
15144 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
15146 if (cfun
->static_chain_decl
!= NULL
)
15148 asm_fprintf (file
, "\tstd %s,24(%s)\n",
15149 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
15150 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
15151 asm_fprintf (file
, "\tld %s,24(%s)\n",
15152 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
15155 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
15162 /* Power4 load update and store update instructions are cracked into a
15163 load or store and an integer insn which are executed in the same cycle.
15164 Branches have their own dispatch slot which does not count against the
15165 GCC issue rate, but it changes the program flow so there are no other
15166 instructions to issue in this cycle. */
15169 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED
,
15170 int verbose ATTRIBUTE_UNUSED
,
15171 rtx insn
, int more
)
15173 if (GET_CODE (PATTERN (insn
)) == USE
15174 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
15177 if (rs6000_sched_groups
)
15179 if (is_microcoded_insn (insn
))
15181 else if (is_cracked_insn (insn
))
15182 return more
> 2 ? more
- 2 : 0;
15188 /* Adjust the cost of a scheduling dependency. Return the new cost of
15189 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
15192 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn ATTRIBUTE_UNUSED
,
15195 if (! recog_memoized (insn
))
15198 if (REG_NOTE_KIND (link
) != 0)
15201 if (REG_NOTE_KIND (link
) == 0)
15203 /* Data dependency; DEP_INSN writes a register that INSN reads
15204 some cycles later. */
15205 switch (get_attr_type (insn
))
15208 /* Tell the first scheduling pass about the latency between
15209 a mtctr and bctr (and mtlr and br/blr). The first
15210 scheduling pass will not know about this latency since
15211 the mtctr instruction, which has the latency associated
15212 to it, will be generated by reload. */
15213 return TARGET_POWER
? 5 : 4;
15215 /* Leave some extra cycles between a compare and its
15216 dependent branch, to inhibit expensive mispredicts. */
15217 if ((rs6000_cpu_attr
== CPU_PPC603
15218 || rs6000_cpu_attr
== CPU_PPC604
15219 || rs6000_cpu_attr
== CPU_PPC604E
15220 || rs6000_cpu_attr
== CPU_PPC620
15221 || rs6000_cpu_attr
== CPU_PPC630
15222 || rs6000_cpu_attr
== CPU_PPC750
15223 || rs6000_cpu_attr
== CPU_PPC7400
15224 || rs6000_cpu_attr
== CPU_PPC7450
15225 || rs6000_cpu_attr
== CPU_POWER4
15226 || rs6000_cpu_attr
== CPU_POWER5
)
15227 && recog_memoized (dep_insn
)
15228 && (INSN_CODE (dep_insn
) >= 0)
15229 && (get_attr_type (dep_insn
) == TYPE_CMP
15230 || get_attr_type (dep_insn
) == TYPE_COMPARE
15231 || get_attr_type (dep_insn
) == TYPE_DELAYED_COMPARE
15232 || get_attr_type (dep_insn
) == TYPE_IMUL_COMPARE
15233 || get_attr_type (dep_insn
) == TYPE_LMUL_COMPARE
15234 || get_attr_type (dep_insn
) == TYPE_FPCOMPARE
15235 || get_attr_type (dep_insn
) == TYPE_CR_LOGICAL
15236 || get_attr_type (dep_insn
) == TYPE_DELAYED_CR
))
15241 /* Fall out to return default cost. */
15247 /* The function returns a true if INSN is microcoded.
15248 Return false otherwise. */
15251 is_microcoded_insn (rtx insn
)
15253 if (!insn
|| !INSN_P (insn
)
15254 || GET_CODE (PATTERN (insn
)) == USE
15255 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
15258 if (rs6000_sched_groups
)
15260 enum attr_type type
= get_attr_type (insn
);
15261 if (type
== TYPE_LOAD_EXT_U
15262 || type
== TYPE_LOAD_EXT_UX
15263 || type
== TYPE_LOAD_UX
15264 || type
== TYPE_STORE_UX
15265 || type
== TYPE_MFCR
)
15272 /* The function returns a nonzero value if INSN can be scheduled only
15273 as the first insn in a dispatch group ("dispatch-slot restricted").
15274 In this case, the returned value indicates how many dispatch slots
15275 the insn occupies (at the beginning of the group).
15276 Return 0 otherwise. */
15279 is_dispatch_slot_restricted (rtx insn
)
15281 enum attr_type type
;
15283 if (!rs6000_sched_groups
)
15287 || insn
== NULL_RTX
15288 || GET_CODE (insn
) == NOTE
15289 || GET_CODE (PATTERN (insn
)) == USE
15290 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
15293 type
= get_attr_type (insn
);
15300 case TYPE_DELAYED_CR
:
15301 case TYPE_CR_LOGICAL
:
15309 if (rs6000_cpu
== PROCESSOR_POWER5
15310 && is_cracked_insn (insn
))
15316 /* The function returns true if INSN is cracked into 2 instructions
15317 by the processor (and therefore occupies 2 issue slots). */
15320 is_cracked_insn (rtx insn
)
15322 if (!insn
|| !INSN_P (insn
)
15323 || GET_CODE (PATTERN (insn
)) == USE
15324 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
15327 if (rs6000_sched_groups
)
15329 enum attr_type type
= get_attr_type (insn
);
15330 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
15331 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
15332 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
15333 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
15334 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
15335 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
15336 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
15337 || type
== TYPE_INSERT_WORD
)
15344 /* The function returns true if INSN can be issued only from
15345 the branch slot. */
15348 is_branch_slot_insn (rtx insn
)
15350 if (!insn
|| !INSN_P (insn
)
15351 || GET_CODE (PATTERN (insn
)) == USE
15352 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
15355 if (rs6000_sched_groups
)
15357 enum attr_type type
= get_attr_type (insn
);
15358 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
15366 /* A C statement (sans semicolon) to update the integer scheduling
15367 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15368 INSN earlier, reduce the priority to execute INSN later. Do not
15369 define this macro if you do not need to adjust the scheduling
15370 priorities of insns. */
15373 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
15375 /* On machines (like the 750) which have asymmetric integer units,
15376 where one integer unit can do multiply and divides and the other
15377 can't, reduce the priority of multiply/divide so it is scheduled
15378 before other integer operations. */
15381 if (! INSN_P (insn
))
15384 if (GET_CODE (PATTERN (insn
)) == USE
)
15387 switch (rs6000_cpu_attr
) {
15389 switch (get_attr_type (insn
))
15396 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
15397 priority
, priority
);
15398 if (priority
>= 0 && priority
< 0x01000000)
15405 if (is_dispatch_slot_restricted (insn
)
15406 && reload_completed
15407 && current_sched_info
->sched_max_insns_priority
15408 && rs6000_sched_restricted_insns_priority
)
15411 /* Prioritize insns that can be dispatched only in the first dispatch slot. */
15412 if (rs6000_sched_restricted_insns_priority
== 1)
15413 /* Attach highest priority to insn. This means that in
15414 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
15415 precede 'priority' (critical path) considerations. */
15416 return current_sched_info
->sched_max_insns_priority
;
15417 else if (rs6000_sched_restricted_insns_priority
== 2)
15418 /* Increase priority of insn by a minimal amount. This means that in
15419 haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations
15420 precede dispatch-slot restriction considerations. */
15421 return (priority
+ 1);
15427 /* Return how many instructions the machine can issue per cycle. */
15430 rs6000_issue_rate (void)
15432 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15433 if (!reload_completed
)
15436 switch (rs6000_cpu_attr
) {
15437 case CPU_RIOS1
: /* ? */
15439 case CPU_PPC601
: /* ? */
15462 /* Return how many instructions to look ahead for better insn
15466 rs6000_use_sched_lookahead (void)
15468 if (rs6000_cpu_attr
== CPU_PPC8540
)
15473 /* Determine is PAT refers to memory. */
15476 is_mem_ref (rtx pat
)
15482 if (GET_CODE (pat
) == MEM
)
15485 /* Recursively process the pattern. */
15486 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
15488 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
15491 ret
|= is_mem_ref (XEXP (pat
, i
));
15492 else if (fmt
[i
] == 'E')
15493 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
15494 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
15500 /* Determine if PAT is a PATTERN of a load insn. */
15503 is_load_insn1 (rtx pat
)
15505 if (!pat
|| pat
== NULL_RTX
)
15508 if (GET_CODE (pat
) == SET
)
15509 return is_mem_ref (SET_SRC (pat
));
15511 if (GET_CODE (pat
) == PARALLEL
)
15515 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
15516 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
15523 /* Determine if INSN loads from memory. */
15526 is_load_insn (rtx insn
)
15528 if (!insn
|| !INSN_P (insn
))
15531 if (GET_CODE (insn
) == CALL_INSN
)
15534 return is_load_insn1 (PATTERN (insn
));
15537 /* Determine if PAT is a PATTERN of a store insn. */
15540 is_store_insn1 (rtx pat
)
15542 if (!pat
|| pat
== NULL_RTX
)
15545 if (GET_CODE (pat
) == SET
)
15546 return is_mem_ref (SET_DEST (pat
));
15548 if (GET_CODE (pat
) == PARALLEL
)
15552 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
15553 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
15560 /* Determine if INSN stores to memory. */
15563 is_store_insn (rtx insn
)
15565 if (!insn
|| !INSN_P (insn
))
15568 return is_store_insn1 (PATTERN (insn
));
15571 /* Returns whether the dependence between INSN and NEXT is considered
15572 costly by the given target. */
15575 rs6000_is_costly_dependence (rtx insn
, rtx next
, rtx link
, int cost
, int distance
)
15577 /* If the flag is not enbled - no dependence is considered costly;
15578 allow all dependent insns in the same group.
15579 This is the most aggressive option. */
15580 if (rs6000_sched_costly_dep
== no_dep_costly
)
15583 /* If the flag is set to 1 - a dependence is always considered costly;
15584 do not allow dependent instructions in the same group.
15585 This is the most conservative option. */
15586 if (rs6000_sched_costly_dep
== all_deps_costly
)
15589 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
15590 && is_load_insn (next
)
15591 && is_store_insn (insn
))
15592 /* Prevent load after store in the same group. */
15595 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
15596 && is_load_insn (next
)
15597 && is_store_insn (insn
)
15598 && (!link
|| (int) REG_NOTE_KIND (link
) == 0))
15599 /* Prevent load after store in the same group if it is a true dependence. */
15602 /* The flag is set to X; dependences with latency >= X are considered costly,
15603 and will not be scheduled in the same group. */
15604 if (rs6000_sched_costly_dep
<= max_dep_latency
15605 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
15611 /* Return the next insn after INSN that is found before TAIL is reached,
15612 skipping any "non-active" insns - insns that will not actually occupy
15613 an issue slot. Return NULL_RTX if such an insn is not found. */
15616 get_next_active_insn (rtx insn
, rtx tail
)
15620 if (!insn
|| insn
== tail
)
15623 next_insn
= NEXT_INSN (insn
);
15626 && next_insn
!= tail
15627 && (GET_CODE(next_insn
) == NOTE
15628 || GET_CODE (PATTERN (next_insn
)) == USE
15629 || GET_CODE (PATTERN (next_insn
)) == CLOBBER
))
15631 next_insn
= NEXT_INSN (next_insn
);
15634 if (!next_insn
|| next_insn
== tail
)
15640 /* Return whether the presence of INSN causes a dispatch group termination
15641 of group WHICH_GROUP.
15643 If WHICH_GROUP == current_group, this function will return true if INSN
15644 causes the termination of the current group (i.e, the dispatch group to
15645 which INSN belongs). This means that INSN will be the last insn in the
15646 group it belongs to.
15648 If WHICH_GROUP == previous_group, this function will return true if INSN
15649 causes the termination of the previous group (i.e, the dispatch group that
15650 precedes the group to which INSN belongs). This means that INSN will be
15651 the first insn in the group it belongs to). */
15654 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
15656 enum attr_type type
;
15661 type
= get_attr_type (insn
);
15663 if (is_microcoded_insn (insn
))
15666 if (which_group
== current_group
)
15668 if (is_branch_slot_insn (insn
))
15672 else if (which_group
== previous_group
)
15674 if (is_dispatch_slot_restricted (insn
))
15682 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
15683 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15686 is_costly_group (rtx
*group_insns
, rtx next_insn
)
15691 int issue_rate
= rs6000_issue_rate ();
15693 for (i
= 0; i
< issue_rate
; i
++)
15695 rtx insn
= group_insns
[i
];
15698 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
15700 rtx next
= XEXP (link
, 0);
15701 if (next
== next_insn
)
15703 cost
= insn_cost (insn
, link
, next_insn
);
15704 if (rs6000_is_costly_dependence (insn
, next_insn
, link
, cost
, 0))
15713 /* Utility of the function redefine_groups.
15714 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15715 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15716 to keep it "far" (in a separate group) from GROUP_INSNS, following
15717 one of the following schemes, depending on the value of the flag
15718 -minsert_sched_nops = X:
15719 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
15720 in order to force NEXT_INSN into a separate group.
15721 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15722 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
15723 insertion (has a group just ended, how many vacant issue slots remain in the
15724 last group, and how many dispatch groups were encountered so far). */
15727 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
, rtx next_insn
,
15728 bool *group_end
, int can_issue_more
, int *group_count
)
15732 int issue_rate
= rs6000_issue_rate ();
15733 bool end
= *group_end
;
15736 if (next_insn
== NULL_RTX
)
15737 return can_issue_more
;
15739 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
15740 return can_issue_more
;
15742 force
= is_costly_group (group_insns
, next_insn
);
15744 return can_issue_more
;
15746 if (sched_verbose
> 6)
15747 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
15748 *group_count
,can_issue_more
);
15750 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
15753 can_issue_more
= 0;
15755 /* Since only a branch can be issued in the last issue_slot, it is
15756 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15757 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
15758 in this case the last nop will start a new group and the branch will be
15759 forced to the new group. */
15760 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
15763 while (can_issue_more
> 0)
15766 emit_insn_before (nop
, next_insn
);
15774 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
15776 int n_nops
= rs6000_sched_insert_nops
;
15778 /* Nops can't be issued from the branch slot, so the effective
15779 issue_rate for nops is 'issue_rate - 1'. */
15780 if (can_issue_more
== 0)
15781 can_issue_more
= issue_rate
;
15783 if (can_issue_more
== 0)
15785 can_issue_more
= issue_rate
- 1;
15788 for (i
= 0; i
< issue_rate
; i
++)
15790 group_insns
[i
] = 0;
15797 emit_insn_before (nop
, next_insn
);
15798 if (can_issue_more
== issue_rate
- 1) /* new group begins */
15801 if (can_issue_more
== 0)
15803 can_issue_more
= issue_rate
- 1;
15806 for (i
= 0; i
< issue_rate
; i
++)
15808 group_insns
[i
] = 0;
15814 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
15817 *group_end
= /* Is next_insn going to start a new group? */
15819 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
15820 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
15821 || (can_issue_more
< issue_rate
&&
15822 insn_terminates_group_p (next_insn
, previous_group
)));
15823 if (*group_end
&& end
)
15826 if (sched_verbose
> 6)
15827 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
15828 *group_count
, can_issue_more
);
15829 return can_issue_more
;
15832 return can_issue_more
;
15835 /* This function tries to synch the dispatch groups that the compiler "sees"
15836 with the dispatch groups that the processor dispatcher is expected to
15837 form in practice. It tries to achieve this synchronization by forcing the
15838 estimated processor grouping on the compiler (as opposed to the function
15839 'pad_goups' which tries to force the scheduler's grouping on the processor).
15841 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
15842 examines the (estimated) dispatch groups that will be formed by the processor
15843 dispatcher. It marks these group boundaries to reflect the estimated
15844 processor grouping, overriding the grouping that the scheduler had marked.
15845 Depending on the value of the flag '-minsert-sched-nops' this function can
15846 force certain insns into separate groups or force a certain distance between
15847 them by inserting nops, for example, if there exists a "costly dependence"
15850 The function estimates the group boundaries that the processor will form as
15851 folllows: It keeps track of how many vacant issue slots are available after
15852 each insn. A subsequent insn will start a new group if one of the following
15854 - no more vacant issue slots remain in the current dispatch group.
15855 - only the last issue slot, which is the branch slot, is vacant, but the next
15856 insn is not a branch.
15857 - only the last 2 or less issue slots, including the branch slot, are vacant,
15858 which means that a cracked insn (which occupies two issue slots) can't be
15859 issued in this group.
15860 - less than 'issue_rate' slots are vacant, and the next insn always needs to
15861 start a new group. */
15864 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
15866 rtx insn
, next_insn
;
15868 int can_issue_more
;
15871 int group_count
= 0;
15875 issue_rate
= rs6000_issue_rate ();
15876 group_insns
= alloca (issue_rate
* sizeof (rtx
));
15877 for (i
= 0; i
< issue_rate
; i
++)
15879 group_insns
[i
] = 0;
15881 can_issue_more
= issue_rate
;
15883 insn
= get_next_active_insn (prev_head_insn
, tail
);
15886 while (insn
!= NULL_RTX
)
15888 slot
= (issue_rate
- can_issue_more
);
15889 group_insns
[slot
] = insn
;
15891 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
15892 if (insn_terminates_group_p (insn
, current_group
))
15893 can_issue_more
= 0;
15895 next_insn
= get_next_active_insn (insn
, tail
);
15896 if (next_insn
== NULL_RTX
)
15897 return group_count
+ 1;
15899 group_end
= /* Is next_insn going to start a new group? */
15900 (can_issue_more
== 0
15901 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
15902 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
15903 || (can_issue_more
< issue_rate
&&
15904 insn_terminates_group_p (next_insn
, previous_group
)));
15906 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
15907 next_insn
, &group_end
, can_issue_more
, &group_count
);
15912 can_issue_more
= 0;
15913 for (i
= 0; i
< issue_rate
; i
++)
15915 group_insns
[i
] = 0;
15919 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
15920 PUT_MODE(next_insn
, VOIDmode
);
15921 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
15922 PUT_MODE (next_insn
, TImode
);
15925 if (can_issue_more
== 0)
15926 can_issue_more
= issue_rate
;
15929 return group_count
;
15932 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
15933 dispatch group boundaries that the scheduler had marked. Pad with nops
15934 any dispatch groups which have vacant issue slots, in order to force the
15935 scheduler's grouping on the processor dispatcher. The function
15936 returns the number of dispatch groups found. */
15939 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
15941 rtx insn
, next_insn
;
15944 int can_issue_more
;
15946 int group_count
= 0;
15948 /* Initialize issue_rate. */
15949 issue_rate
= rs6000_issue_rate ();
15950 can_issue_more
= issue_rate
;
15952 insn
= get_next_active_insn (prev_head_insn
, tail
);
15953 next_insn
= get_next_active_insn (insn
, tail
);
15955 while (insn
!= NULL_RTX
)
15958 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
15960 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
15962 if (next_insn
== NULL_RTX
)
15967 /* If the scheduler had marked group termination at this location
15968 (between insn and next_indn), and neither insn nor next_insn will
15969 force group termination, pad the group with nops to force group
15972 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
15973 && !insn_terminates_group_p (insn
, current_group
)
15974 && !insn_terminates_group_p (next_insn
, previous_group
))
15976 if (!is_branch_slot_insn(next_insn
))
15979 while (can_issue_more
)
15982 emit_insn_before (nop
, next_insn
);
15987 can_issue_more
= issue_rate
;
15992 next_insn
= get_next_active_insn (insn
, tail
);
15995 return group_count
;
15998 /* The following function is called at the end of scheduling BB.
15999 After reload, it inserts nops at insn group bundling. */
16002 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
16007 fprintf (dump
, "=== Finishing schedule.\n");
16009 if (reload_completed
&& rs6000_sched_groups
)
16011 if (rs6000_sched_insert_nops
== sched_finish_none
)
16014 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
16015 n_groups
= pad_groups (dump
, sched_verbose
,
16016 current_sched_info
->prev_head
,
16017 current_sched_info
->next_tail
);
16019 n_groups
= redefine_groups (dump
, sched_verbose
,
16020 current_sched_info
->prev_head
,
16021 current_sched_info
->next_tail
);
16023 if (sched_verbose
>= 6)
16025 fprintf (dump
, "ngroups = %d\n", n_groups
);
16026 print_rtl (dump
, current_sched_info
->prev_head
);
16027 fprintf (dump
, "Done finish_sched\n");
16032 /* Length in units of the trampoline for entering a nested function. */
16035 rs6000_trampoline_size (void)
16039 switch (DEFAULT_ABI
)
16045 ret
= (TARGET_32BIT
) ? 12 : 24;
16050 ret
= (TARGET_32BIT
) ? 40 : 48;
16057 /* Emit RTL insns to initialize the variable parts of a trampoline.
16058 FNADDR is an RTX for the address of the function's pure code.
16059 CXT is an RTX for the static chain value for the function. */
16062 rs6000_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
16064 enum machine_mode pmode
= Pmode
;
16065 int regsize
= (TARGET_32BIT
) ? 4 : 8;
16066 rtx ctx_reg
= force_reg (pmode
, cxt
);
16068 switch (DEFAULT_ABI
)
16073 /* Macros to shorten the code expansions below. */
16074 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
16075 #define MEM_PLUS(addr,offset) \
16076 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
16078 /* Under AIX, just build the 3 word function descriptor */
16081 rtx fn_reg
= gen_reg_rtx (pmode
);
16082 rtx toc_reg
= gen_reg_rtx (pmode
);
16083 emit_move_insn (fn_reg
, MEM_DEREF (fnaddr
));
16084 emit_move_insn (toc_reg
, MEM_PLUS (fnaddr
, regsize
));
16085 emit_move_insn (MEM_DEREF (addr
), fn_reg
);
16086 emit_move_insn (MEM_PLUS (addr
, regsize
), toc_reg
);
16087 emit_move_insn (MEM_PLUS (addr
, 2*regsize
), ctx_reg
);
16091 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
16094 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
16095 FALSE
, VOIDmode
, 4,
16097 GEN_INT (rs6000_trampoline_size ()), SImode
,
16107 /* Table of valid machine attributes. */
16109 const struct attribute_spec rs6000_attribute_table
[] =
16111 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
16112 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
},
16113 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
16114 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
16115 { NULL
, 0, 0, false, false, false, NULL
}
16118 /* Handle the "altivec" attribute. The attribute may have
16119 arguments as follows:
16121 __attribute__((altivec(vector__)))
16122 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
16123 __attribute__((altivec(bool__))) (always followed by 'unsigned')
16125 and may appear more than once (e.g., 'vector bool char') in a
16126 given declaration. */
16129 rs6000_handle_altivec_attribute (tree
*node
, tree name
, tree args
,
16130 int flags ATTRIBUTE_UNUSED
,
16131 bool *no_add_attrs
)
16133 tree type
= *node
, result
= NULL_TREE
;
16134 enum machine_mode mode
;
16137 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
16138 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
16139 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
16142 while (POINTER_TYPE_P (type
)
16143 || TREE_CODE (type
) == FUNCTION_TYPE
16144 || TREE_CODE (type
) == METHOD_TYPE
16145 || TREE_CODE (type
) == ARRAY_TYPE
)
16146 type
= TREE_TYPE (type
);
16148 mode
= TYPE_MODE (type
);
16150 if (rs6000_warn_altivec_long
16151 && (type
== long_unsigned_type_node
|| type
== long_integer_type_node
))
16152 warning ("use of 'long' in AltiVec types is deprecated; use 'int'");
16154 switch (altivec_type
)
16157 unsigned_p
= TYPE_UNSIGNED (type
);
16161 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
16164 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
16167 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
16169 case SFmode
: result
= V4SF_type_node
; break;
16170 /* If the user says 'vector int bool', we may be handed the 'bool'
16171 attribute _before_ the 'vector' attribute, and so select the proper
16172 type in the 'b' case below. */
16173 case V4SImode
: case V8HImode
: case V16QImode
: result
= type
;
16180 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
16181 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
16182 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
16189 case V8HImode
: result
= pixel_V8HI_type_node
;
16195 if (result
&& result
!= type
&& TYPE_READONLY (type
))
16196 result
= build_qualified_type (result
, TYPE_QUAL_CONST
);
16198 *no_add_attrs
= true; /* No need to hang on to the attribute. */
16201 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
16203 *node
= reconstruct_complex_type (*node
, result
);
16208 /* AltiVec defines four built-in scalar types that serve as vector
16209 elements; we must teach the compiler how to mangle them. */
16211 static const char *
16212 rs6000_mangle_fundamental_type (tree type
)
16214 if (type
== bool_char_type_node
) return "U6__boolc";
16215 if (type
== bool_short_type_node
) return "U6__bools";
16216 if (type
== pixel_type_node
) return "u7__pixel";
16217 if (type
== bool_int_type_node
) return "U6__booli";
16219 /* For all other types, use normal C++ mangling. */
16223 /* Handle a "longcall" or "shortcall" attribute; arguments as in
16224 struct attribute_spec.handler. */
16227 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
16228 tree args ATTRIBUTE_UNUSED
,
16229 int flags ATTRIBUTE_UNUSED
,
16230 bool *no_add_attrs
)
16232 if (TREE_CODE (*node
) != FUNCTION_TYPE
16233 && TREE_CODE (*node
) != FIELD_DECL
16234 && TREE_CODE (*node
) != TYPE_DECL
)
16236 warning ("`%s' attribute only applies to functions",
16237 IDENTIFIER_POINTER (name
));
16238 *no_add_attrs
= true;
16244 /* Set longcall attributes on all functions declared when
16245 rs6000_default_long_calls is true. */
16247 rs6000_set_default_type_attributes (tree type
)
16249 if (rs6000_default_long_calls
16250 && (TREE_CODE (type
) == FUNCTION_TYPE
16251 || TREE_CODE (type
) == METHOD_TYPE
))
16252 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
16254 TYPE_ATTRIBUTES (type
));
16257 /* Return a reference suitable for calling a function with the
16258 longcall attribute. */
16261 rs6000_longcall_ref (rtx call_ref
)
16263 const char *call_name
;
16266 if (GET_CODE (call_ref
) != SYMBOL_REF
)
16269 /* System V adds '.' to the internal name, so skip them. */
16270 call_name
= XSTR (call_ref
, 0);
16271 if (*call_name
== '.')
16273 while (*call_name
== '.')
16276 node
= get_identifier (call_name
);
16277 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
16280 return force_reg (Pmode
, call_ref
);
16283 #ifdef USING_ELFOS_H
16285 /* A C statement or statements to switch to the appropriate section
16286 for output of RTX in mode MODE. You can assume that RTX is some
16287 kind of constant in RTL. The argument MODE is redundant except in
16288 the case of a `const_int' rtx. Select the section by calling
16289 `text_section' or one of the alternatives for other sections.
16291 Do not define this macro if you put all constants in the read-only
16295 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
16296 unsigned HOST_WIDE_INT align
)
16298 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
16301 default_elf_select_rtx_section (mode
, x
, align
);
16304 /* A C statement or statements to switch to the appropriate
16305 section for output of DECL. DECL is either a `VAR_DECL' node
16306 or a constant of some sort. RELOC indicates whether forming
16307 the initial value of DECL requires link-time relocations. */
16310 rs6000_elf_select_section (tree decl
, int reloc
,
16311 unsigned HOST_WIDE_INT align
)
16313 /* Pretend that we're always building for a shared library when
16314 ABI_AIX, because otherwise we end up with dynamic relocations
16315 in read-only sections. This happens for function pointers,
16316 references to vtables in typeinfo, and probably other cases. */
16317 default_elf_select_section_1 (decl
, reloc
, align
,
16318 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
16321 /* A C statement to build up a unique section name, expressed as a
16322 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16323 RELOC indicates whether the initial value of EXP requires
16324 link-time relocations. If you do not define this macro, GCC will use
16325 the symbol name prefixed by `.' as the section name. Note - this
16326 macro can now be called for uninitialized data items as well as
16327 initialized data and functions. */
16330 rs6000_elf_unique_section (tree decl
, int reloc
)
16332 /* As above, pretend that we're always building for a shared library
16333 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
16334 default_unique_section_1 (decl
, reloc
,
16335 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
16338 /* For a SYMBOL_REF, set generic flags and then perform some
16339 target-specific processing.
16341 When the AIX ABI is requested on a non-AIX system, replace the
16342 function name with the real name (with a leading .) rather than the
16343 function descriptor name. This saves a lot of overriding code to
16344 read the prefixes. */
16347 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
16349 default_encode_section_info (decl
, rtl
, first
);
16352 && TREE_CODE (decl
) == FUNCTION_DECL
16354 && DEFAULT_ABI
== ABI_AIX
)
16356 rtx sym_ref
= XEXP (rtl
, 0);
16357 size_t len
= strlen (XSTR (sym_ref
, 0));
16358 char *str
= alloca (len
+ 2);
16360 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
16361 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
16366 rs6000_elf_in_small_data_p (tree decl
)
16368 if (rs6000_sdata
== SDATA_NONE
)
16371 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
16373 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
16374 if (strcmp (section
, ".sdata") == 0
16375 || strcmp (section
, ".sdata2") == 0
16376 || strcmp (section
, ".sbss") == 0
16377 || strcmp (section
, ".sbss2") == 0
16378 || strcmp (section
, ".PPC.EMB.sdata0") == 0
16379 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
16384 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
16387 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
16388 /* If it's not public, and we're not going to reference it there,
16389 there's no need to put it in the small data section. */
16390 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
16397 #endif /* USING_ELFOS_H */
16400 /* Return a REG that occurs in ADDR with coefficient 1.
16401 ADDR can be effectively incremented by incrementing REG.
16403 r0 is special and we must not select it as an address
16404 register by this routine since our caller will try to
16405 increment the returned register via an "la" instruction. */
16408 find_addr_reg (rtx addr
)
16410 while (GET_CODE (addr
) == PLUS
)
16412 if (GET_CODE (XEXP (addr
, 0)) == REG
16413 && REGNO (XEXP (addr
, 0)) != 0)
16414 addr
= XEXP (addr
, 0);
16415 else if (GET_CODE (XEXP (addr
, 1)) == REG
16416 && REGNO (XEXP (addr
, 1)) != 0)
16417 addr
= XEXP (addr
, 1);
16418 else if (CONSTANT_P (XEXP (addr
, 0)))
16419 addr
= XEXP (addr
, 1);
16420 else if (CONSTANT_P (XEXP (addr
, 1)))
16421 addr
= XEXP (addr
, 0);
16425 if (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0)
16431 rs6000_fatal_bad_address (rtx op
)
16433 fatal_insn ("bad address", op
);
16439 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
16440 reference and a constant. */
16443 symbolic_operand (rtx op
)
16445 switch (GET_CODE (op
))
16452 return (GET_CODE (op
) == SYMBOL_REF
||
16453 (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
16454 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
16455 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
16464 static tree branch_island_list
= 0;
16466 /* Remember to generate a branch island for far calls to the given
16470 add_compiler_branch_island (tree label_name
, tree function_name
, int line_number
)
16472 tree branch_island
= build_tree_list (function_name
, label_name
);
16473 TREE_TYPE (branch_island
) = build_int_cst (NULL_TREE
, line_number
);
16474 TREE_CHAIN (branch_island
) = branch_island_list
;
16475 branch_island_list
= branch_island
;
16478 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16479 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16480 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16481 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
16483 /* Generate far-jump branch islands for everything on the
16484 branch_island_list. Invoked immediately after the last instruction
16485 of the epilogue has been emitted; the branch-islands must be
16486 appended to, and contiguous with, the function body. Mach-O stubs
16487 are generated in machopic_output_stub(). */
16490 macho_branch_islands (void)
16493 tree branch_island
;
16495 for (branch_island
= branch_island_list
;
16497 branch_island
= TREE_CHAIN (branch_island
))
16499 const char *label
=
16500 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island
));
16502 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island
));
16503 char name_buf
[512];
16504 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16505 if (name
[0] == '*' || name
[0] == '&')
16506 strcpy (name_buf
, name
+1);
16510 strcpy (name_buf
+1, name
);
16512 strcpy (tmp_buf
, "\n");
16513 strcat (tmp_buf
, label
);
16514 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16515 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
16516 fprintf (asm_out_file
, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
16517 BRANCH_ISLAND_LINE_NUMBER(branch_island
));
16518 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16521 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
16522 strcat (tmp_buf
, label
);
16523 strcat (tmp_buf
, "_pic\n");
16524 strcat (tmp_buf
, label
);
16525 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
16527 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
16528 strcat (tmp_buf
, name_buf
);
16529 strcat (tmp_buf
, " - ");
16530 strcat (tmp_buf
, label
);
16531 strcat (tmp_buf
, "_pic)\n");
16533 strcat (tmp_buf
, "\tmtlr r0\n");
16535 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
16536 strcat (tmp_buf
, name_buf
);
16537 strcat (tmp_buf
, " - ");
16538 strcat (tmp_buf
, label
);
16539 strcat (tmp_buf
, "_pic)\n");
16541 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
16545 strcat (tmp_buf
, ":\nlis r12,hi16(");
16546 strcat (tmp_buf
, name_buf
);
16547 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
16548 strcat (tmp_buf
, name_buf
);
16549 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
16551 output_asm_insn (tmp_buf
, 0);
16552 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16553 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
16554 fprintf(asm_out_file
, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
16555 BRANCH_ISLAND_LINE_NUMBER (branch_island
));
16556 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16559 branch_island_list
= 0;
16562 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
16563 already there or not. */
16566 no_previous_def (tree function_name
)
16568 tree branch_island
;
16569 for (branch_island
= branch_island_list
;
16571 branch_island
= TREE_CHAIN (branch_island
))
16572 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
16577 /* GET_PREV_LABEL gets the label name from the previous definition of
16581 get_prev_label (tree function_name
)
16583 tree branch_island
;
16584 for (branch_island
= branch_island_list
;
16586 branch_island
= TREE_CHAIN (branch_island
))
16587 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
16588 return BRANCH_ISLAND_LABEL_NAME (branch_island
);
16592 /* INSN is either a function call or a millicode call. It may have an
16593 unconditional jump in its delay slot.
16595 CALL_DEST is the routine we are calling. */
16598 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
, int cookie_operand_number
)
16600 static char buf
[256];
16601 if (GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
16602 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
16605 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
16607 if (no_previous_def (funname
))
16609 int line_number
= 0;
16610 rtx label_rtx
= gen_label_rtx ();
16611 char *label_buf
, temp_buf
[256];
16612 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
16613 CODE_LABEL_NUMBER (label_rtx
));
16614 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
16615 labelname
= get_identifier (label_buf
);
16616 for (; insn
&& GET_CODE (insn
) != NOTE
; insn
= PREV_INSN (insn
));
16618 line_number
= NOTE_LINE_NUMBER (insn
);
16619 add_compiler_branch_island (labelname
, funname
, line_number
);
16622 labelname
= get_prev_label (funname
);
16624 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16625 instruction will reach 'foo', otherwise link as 'bl L42'".
16626 "L42" should be a 'branch island', that will do a far jump to
16627 'foo'. Branch islands are generated in
16628 macho_branch_islands(). */
16629 sprintf (buf
, "jbsr %%z%d,%.246s",
16630 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
16633 sprintf (buf
, "bl %%z%d", dest_operand_number
);
16637 #endif /* TARGET_MACHO */
16639 /* Generate PIC and indirect symbol stubs. */
16642 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
16644 unsigned int length
;
16645 char *symbol_name
, *lazy_ptr_name
;
16646 char *local_label_0
;
16647 static int label
= 0;
16649 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
16650 symb
= (*targetm
.strip_name_encoding
) (symb
);
16653 length
= strlen (symb
);
16654 symbol_name
= alloca (length
+ 32);
16655 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
16657 lazy_ptr_name
= alloca (length
+ 32);
16658 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
16661 machopic_picsymbol_stub1_section ();
16663 machopic_symbol_stub1_section ();
16667 fprintf (file
, "\t.align 5\n");
16669 fprintf (file
, "%s:\n", stub
);
16670 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
16673 local_label_0
= alloca (sizeof("\"L0000000000$spb\""));
16674 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
16676 fprintf (file
, "\tmflr r0\n");
16677 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
16678 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
16679 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
16680 lazy_ptr_name
, local_label_0
);
16681 fprintf (file
, "\tmtlr r0\n");
16682 fprintf (file
, "\tlwzu r12,lo16(%s-%s)(r11)\n",
16683 lazy_ptr_name
, local_label_0
);
16684 fprintf (file
, "\tmtctr r12\n");
16685 fprintf (file
, "\tbctr\n");
16689 fprintf (file
, "\t.align 4\n");
16691 fprintf (file
, "%s:\n", stub
);
16692 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
16694 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
16695 fprintf (file
, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name
);
16696 fprintf (file
, "\tmtctr r12\n");
16697 fprintf (file
, "\tbctr\n");
16700 machopic_lazy_symbol_ptr_section ();
16701 fprintf (file
, "%s:\n", lazy_ptr_name
);
16702 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
16703 fprintf (file
, "%sdyld_stub_binding_helper\n",
16704 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
16707 /* Legitimize PIC addresses. If the address is already
16708 position-independent, we return ORIG. Newly generated
16709 position-independent addresses go into a reg. This is REG if non
16710 zero, otherwise we allocate register(s) as necessary. */
16712 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
16715 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
16720 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
16721 reg
= gen_reg_rtx (Pmode
);
16723 if (GET_CODE (orig
) == CONST
)
16725 if (GET_CODE (XEXP (orig
, 0)) == PLUS
16726 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
16729 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
16731 /* Use a different reg for the intermediate value, as
16732 it will be marked UNCHANGING. */
16733 rtx reg_temp
= no_new_pseudos
? reg
: gen_reg_rtx (Pmode
);
16736 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
16739 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
16745 if (GET_CODE (offset
) == CONST_INT
)
16747 if (SMALL_INT (offset
))
16748 return plus_constant (base
, INTVAL (offset
));
16749 else if (! reload_in_progress
&& ! reload_completed
)
16750 offset
= force_reg (Pmode
, offset
);
16753 rtx mem
= force_const_mem (Pmode
, orig
);
16754 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
16757 return gen_rtx_PLUS (Pmode
, base
, offset
);
16760 /* Fall back on generic machopic code. */
16761 return machopic_legitimize_pic_address (orig
, mode
, reg
);
16764 /* This is just a placeholder to make linking work without having to
16765 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16766 ever needed for Darwin (not too likely!) this would have to get a
16767 real definition. */
16774 #endif /* TARGET_MACHO */
16777 static unsigned int
16778 rs6000_elf_section_type_flags (tree decl
, const char *name
, int reloc
)
16780 return default_section_type_flags_1 (decl
, name
, reloc
,
16781 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
16784 /* Record an element in the table of global constructors. SYMBOL is
16785 a SYMBOL_REF of the function to be called; PRIORITY is a number
16786 between 0 and MAX_INIT_PRIORITY.
16788 This differs from default_named_section_asm_out_constructor in
16789 that we have special handling for -mrelocatable. */
16792 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
16794 const char *section
= ".ctors";
16797 if (priority
!= DEFAULT_INIT_PRIORITY
)
16799 sprintf (buf
, ".ctors.%.5u",
16800 /* Invert the numbering so the linker puts us in the proper
16801 order; constructors are run from right to left, and the
16802 linker sorts in increasing order. */
16803 MAX_INIT_PRIORITY
- priority
);
16807 named_section_flags (section
, SECTION_WRITE
);
16808 assemble_align (POINTER_SIZE
);
16810 if (TARGET_RELOCATABLE
)
16812 fputs ("\t.long (", asm_out_file
);
16813 output_addr_const (asm_out_file
, symbol
);
16814 fputs (")@fixup\n", asm_out_file
);
16817 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
16821 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
16823 const char *section
= ".dtors";
16826 if (priority
!= DEFAULT_INIT_PRIORITY
)
16828 sprintf (buf
, ".dtors.%.5u",
16829 /* Invert the numbering so the linker puts us in the proper
16830 order; constructors are run from right to left, and the
16831 linker sorts in increasing order. */
16832 MAX_INIT_PRIORITY
- priority
);
16836 named_section_flags (section
, SECTION_WRITE
);
16837 assemble_align (POINTER_SIZE
);
16839 if (TARGET_RELOCATABLE
)
16841 fputs ("\t.long (", asm_out_file
);
16842 output_addr_const (asm_out_file
, symbol
);
16843 fputs (")@fixup\n", asm_out_file
);
16846 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
16850 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
16854 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
16855 ASM_OUTPUT_LABEL (file
, name
);
16856 fputs (DOUBLE_INT_ASM_OP
, file
);
16857 rs6000_output_function_entry (file
, name
);
16858 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
16861 fputs ("\t.size\t", file
);
16862 assemble_name (file
, name
);
16863 fputs (",24\n\t.type\t.", file
);
16864 assemble_name (file
, name
);
16865 fputs (",@function\n", file
);
16866 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
16868 fputs ("\t.globl\t.", file
);
16869 assemble_name (file
, name
);
16874 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
16875 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
16876 rs6000_output_function_entry (file
, name
);
16877 fputs (":\n", file
);
16881 if (TARGET_RELOCATABLE
16882 && (get_pool_size () != 0 || current_function_profile
)
16887 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
16889 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
16890 fprintf (file
, "\t.long ");
16891 assemble_name (file
, buf
);
16893 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
16894 assemble_name (file
, buf
);
16898 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
16899 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
16901 if (DEFAULT_ABI
== ABI_AIX
)
16903 const char *desc_name
, *orig_name
;
16905 orig_name
= (*targetm
.strip_name_encoding
) (name
);
16906 desc_name
= orig_name
;
16907 while (*desc_name
== '.')
16910 if (TREE_PUBLIC (decl
))
16911 fprintf (file
, "\t.globl %s\n", desc_name
);
16913 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
16914 fprintf (file
, "%s:\n", desc_name
);
16915 fprintf (file
, "\t.long %s\n", orig_name
);
16916 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
16917 if (DEFAULT_ABI
== ABI_AIX
)
16918 fputs ("\t.long 0\n", file
);
16919 fprintf (file
, "\t.previous\n");
16921 ASM_OUTPUT_LABEL (file
, name
);
16927 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
16929 fputs (GLOBAL_ASM_OP
, stream
);
16930 RS6000_OUTPUT_BASENAME (stream
, name
);
16931 putc ('\n', stream
);
16935 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
16936 tree decl ATTRIBUTE_UNUSED
)
16939 static const char * const suffix
[3] = { "PR", "RO", "RW" };
16941 if (flags
& SECTION_CODE
)
16943 else if (flags
& SECTION_WRITE
)
16948 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
16949 (flags
& SECTION_CODE
) ? "." : "",
16950 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
16954 rs6000_xcoff_select_section (tree decl
, int reloc
,
16955 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
16957 if (decl_readonly_section_1 (decl
, reloc
, 1))
16959 if (TREE_PUBLIC (decl
))
16960 read_only_data_section ();
16962 read_only_private_data_section ();
16966 if (TREE_PUBLIC (decl
))
16969 private_data_section ();
16974 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
16978 /* Use select_section for private and uninitialized data. */
16979 if (!TREE_PUBLIC (decl
)
16980 || DECL_COMMON (decl
)
16981 || DECL_INITIAL (decl
) == NULL_TREE
16982 || DECL_INITIAL (decl
) == error_mark_node
16983 || (flag_zero_initialized_in_bss
16984 && initializer_zerop (DECL_INITIAL (decl
))))
16987 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
16988 name
= (*targetm
.strip_name_encoding
) (name
);
16989 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
16992 /* Select section for constant in constant pool.
16994 On RS/6000, all constants are in the private read-only data area.
16995 However, if this is being placed in the TOC it must be output as a
16999 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
17000 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
17002 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
17005 read_only_private_data_section ();
17008 /* Remove any trailing [DS] or the like from the symbol name. */
17010 static const char *
17011 rs6000_xcoff_strip_name_encoding (const char *name
)
17016 len
= strlen (name
);
17017 if (name
[len
- 1] == ']')
17018 return ggc_alloc_string (name
, len
- 4);
17023 /* Section attributes. AIX is always PIC. */
17025 static unsigned int
17026 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
17028 unsigned int align
;
17029 unsigned int flags
= default_section_type_flags_1 (decl
, name
, reloc
, 1);
17031 /* Align to at least UNIT size. */
17032 if (flags
& SECTION_CODE
)
17033 align
= MIN_UNITS_PER_WORD
;
17035 /* Increase alignment of large objects if not already stricter. */
17036 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
17037 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
17038 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
17040 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
17043 /* Output at beginning of assembler file.
17045 Initialize the section names for the RS/6000 at this point.
17047 Specify filename, including full path, to assembler.
17049 We want to go into the TOC section so at least one .toc will be emitted.
17050 Also, in order to output proper .bs/.es pairs, we need at least one static
17051 [RW] section emitted.
17053 Finally, declare mcount when profiling to make the assembler happy. */
17056 rs6000_xcoff_file_start (void)
17058 rs6000_gen_section_name (&xcoff_bss_section_name
,
17059 main_input_filename
, ".bss_");
17060 rs6000_gen_section_name (&xcoff_private_data_section_name
,
17061 main_input_filename
, ".rw_");
17062 rs6000_gen_section_name (&xcoff_read_only_section_name
,
17063 main_input_filename
, ".ro_");
17065 fputs ("\t.file\t", asm_out_file
);
17066 output_quoted_string (asm_out_file
, main_input_filename
);
17067 fputc ('\n', asm_out_file
);
17069 if (write_symbols
!= NO_DEBUG
)
17070 private_data_section ();
17073 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
17074 rs6000_file_start ();
17077 /* Output at end of assembler file.
17078 On the RS/6000, referencing data should automatically pull in text. */
17081 rs6000_xcoff_file_end (void)
17084 fputs ("_section_.text:\n", asm_out_file
);
17086 fputs (TARGET_32BIT
17087 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
17090 #endif /* TARGET_XCOFF */
17093 /* Cross-module name binding. Darwin does not support overriding
17094 functions at dynamic-link time. */
17097 rs6000_binds_local_p (tree decl
)
17099 return default_binds_local_p_1 (decl
, 0);
17103 /* Compute a (partial) cost for rtx X. Return true if the complete
17104 cost has been computed, and false if subexpressions should be
17105 scanned. In either case, *TOTAL contains the cost result. */
17108 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
17110 enum machine_mode mode
= GET_MODE (x
);
17114 /* On the RS/6000, if it is valid in the insn, it is free. */
17116 if (((outer_code
== SET
17117 || outer_code
== PLUS
17118 || outer_code
== MINUS
)
17119 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
17120 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')))
17121 || ((outer_code
== IOR
|| outer_code
== XOR
)
17122 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
17123 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')))
17124 || ((outer_code
== DIV
|| outer_code
== UDIV
17125 || outer_code
== MOD
|| outer_code
== UMOD
)
17126 && exact_log2 (INTVAL (x
)) >= 0)
17127 || (outer_code
== AND
17128 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
17129 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')
17130 || mask_operand (x
, VOIDmode
)))
17131 || outer_code
== ASHIFT
17132 || outer_code
== ASHIFTRT
17133 || outer_code
== LSHIFTRT
17134 || outer_code
== ROTATE
17135 || outer_code
== ROTATERT
17136 || outer_code
== ZERO_EXTRACT
17137 || (outer_code
== MULT
17138 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I'))
17139 || (outer_code
== COMPARE
17140 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
17141 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K'))))
17146 else if ((outer_code
== PLUS
17147 && reg_or_add_cint64_operand (x
, VOIDmode
))
17148 || (outer_code
== MINUS
17149 && reg_or_sub_cint64_operand (x
, VOIDmode
))
17150 || ((outer_code
== SET
17151 || outer_code
== IOR
17152 || outer_code
== XOR
)
17154 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
17156 *total
= COSTS_N_INSNS (1);
17163 && ((outer_code
== AND
17164 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
17165 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')
17166 || mask64_operand (x
, DImode
)))
17167 || ((outer_code
== IOR
|| outer_code
== XOR
)
17168 && CONST_DOUBLE_HIGH (x
) == 0
17169 && (CONST_DOUBLE_LOW (x
)
17170 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)))
17175 else if (mode
== DImode
17176 && (outer_code
== SET
17177 || outer_code
== IOR
17178 || outer_code
== XOR
)
17179 && CONST_DOUBLE_HIGH (x
) == 0)
17181 *total
= COSTS_N_INSNS (1);
17190 /* When optimizing for size, MEM should be slightly more expensive
17191 than generating address, e.g., (plus (reg) (const)).
17192 L1 cache latency is about two instructions. */
17193 *total
= optimize_size
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
17201 if (mode
== DFmode
)
17203 if (GET_CODE (XEXP (x
, 0)) == MULT
)
17205 /* FNMA accounted in outer NEG. */
17206 if (outer_code
== NEG
)
17207 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
17209 *total
= rs6000_cost
->dmul
;
17212 *total
= rs6000_cost
->fp
;
17214 else if (mode
== SFmode
)
17216 /* FNMA accounted in outer NEG. */
17217 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
17220 *total
= rs6000_cost
->fp
;
17222 else if (GET_CODE (XEXP (x
, 0)) == MULT
)
17224 /* The rs6000 doesn't have shift-and-add instructions. */
17225 rs6000_rtx_costs (XEXP (x
, 0), MULT
, PLUS
, total
);
17226 *total
+= COSTS_N_INSNS (1);
17229 *total
= COSTS_N_INSNS (1);
17233 if (mode
== DFmode
)
17235 if (GET_CODE (XEXP (x
, 0)) == MULT
)
17237 /* FNMA accounted in outer NEG. */
17238 if (outer_code
== NEG
)
17241 *total
= rs6000_cost
->dmul
;
17244 *total
= rs6000_cost
->fp
;
17246 else if (mode
== SFmode
)
17248 /* FNMA accounted in outer NEG. */
17249 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
17252 *total
= rs6000_cost
->fp
;
17254 else if (GET_CODE (XEXP (x
, 0)) == MULT
)
17256 /* The rs6000 doesn't have shift-and-sub instructions. */
17257 rs6000_rtx_costs (XEXP (x
, 0), MULT
, MINUS
, total
);
17258 *total
+= COSTS_N_INSNS (1);
17261 *total
= COSTS_N_INSNS (1);
17265 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
17267 if (INTVAL (XEXP (x
, 1)) >= -256
17268 && INTVAL (XEXP (x
, 1)) <= 255)
17269 *total
= rs6000_cost
->mulsi_const9
;
17271 *total
= rs6000_cost
->mulsi_const
;
17273 /* FMA accounted in outer PLUS/MINUS. */
17274 else if ((mode
== DFmode
|| mode
== SFmode
)
17275 && (outer_code
== PLUS
|| outer_code
== MINUS
))
17277 else if (mode
== DFmode
)
17278 *total
= rs6000_cost
->dmul
;
17279 else if (mode
== SFmode
)
17280 *total
= rs6000_cost
->fp
;
17281 else if (mode
== DImode
)
17282 *total
= rs6000_cost
->muldi
;
17284 *total
= rs6000_cost
->mulsi
;
17289 if (FLOAT_MODE_P (mode
))
17291 *total
= mode
== DFmode
? rs6000_cost
->ddiv
17292 : rs6000_cost
->sdiv
;
17299 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
17300 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
17302 if (code
== DIV
|| code
== MOD
)
17304 *total
= COSTS_N_INSNS (2);
17307 *total
= COSTS_N_INSNS (1);
17311 if (GET_MODE (XEXP (x
, 1)) == DImode
)
17312 *total
= rs6000_cost
->divdi
;
17314 *total
= rs6000_cost
->divsi
;
17316 /* Add in shift and subtract for MOD. */
17317 if (code
== MOD
|| code
== UMOD
)
17318 *total
+= COSTS_N_INSNS (2);
17322 *total
= COSTS_N_INSNS (4);
17326 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
17337 *total
= COSTS_N_INSNS (1);
17345 /* Handle mul_highpart. */
17346 if (outer_code
== TRUNCATE
17347 && GET_CODE (XEXP (x
, 0)) == MULT
)
17349 if (mode
== DImode
)
17350 *total
= rs6000_cost
->muldi
;
17352 *total
= rs6000_cost
->mulsi
;
17355 else if (outer_code
== AND
)
17358 *total
= COSTS_N_INSNS (1);
17363 if (GET_CODE (XEXP (x
, 0)) == MEM
)
17366 *total
= COSTS_N_INSNS (1);
17372 if (!FLOAT_MODE_P (mode
))
17374 *total
= COSTS_N_INSNS (1);
17380 case UNSIGNED_FLOAT
:
17384 case FLOAT_TRUNCATE
:
17385 *total
= rs6000_cost
->fp
;
17389 switch (XINT (x
, 1))
17392 *total
= rs6000_cost
->fp
;
17404 *total
= COSTS_N_INSNS (1);
17407 else if (FLOAT_MODE_P (mode
)
17408 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
17410 *total
= rs6000_cost
->fp
;
17423 /* A C expression returning the cost of moving data from a register of class
17424 CLASS1 to one of CLASS2. */
17427 rs6000_register_move_cost (enum machine_mode mode
,
17428 enum reg_class from
, enum reg_class to
)
17430 /* Moves from/to GENERAL_REGS. */
17431 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
17432 || reg_classes_intersect_p (from
, GENERAL_REGS
))
17434 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
17437 if (from
== FLOAT_REGS
|| from
== ALTIVEC_REGS
)
17438 return (rs6000_memory_move_cost (mode
, from
, 0)
17439 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, 0));
17441 /* It's more expensive to move CR_REGS than CR0_REGS because of the shift.... */
17442 else if (from
== CR_REGS
)
17446 /* A move will cost one instruction per GPR moved. */
17447 return 2 * HARD_REGNO_NREGS (0, mode
);
17450 /* Moving between two similar registers is just one instruction. */
17451 else if (reg_classes_intersect_p (to
, from
))
17452 return mode
== TFmode
? 4 : 2;
17454 /* Everything else has to go through GENERAL_REGS. */
17456 return (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
17457 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
17460 /* A C expressions returning the cost of moving data of MODE from a register to
17464 rs6000_memory_move_cost (enum machine_mode mode
, enum reg_class
class,
17465 int in ATTRIBUTE_UNUSED
)
17467 if (reg_classes_intersect_p (class, GENERAL_REGS
))
17468 return 4 * HARD_REGNO_NREGS (0, mode
);
17469 else if (reg_classes_intersect_p (class, FLOAT_REGS
))
17470 return 4 * HARD_REGNO_NREGS (32, mode
);
17471 else if (reg_classes_intersect_p (class, ALTIVEC_REGS
))
17472 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO
, mode
);
17474 return 4 + rs6000_register_move_cost (mode
, class, GENERAL_REGS
);
17477 /* Return an RTX representing where to find the function value of a
17478 function returning MODE. */
17480 rs6000_complex_function_value (enum machine_mode mode
)
17482 unsigned int regno
;
17484 enum machine_mode inner
= GET_MODE_INNER (mode
);
17485 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
17487 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
17488 regno
= FP_ARG_RETURN
;
17491 regno
= GP_ARG_RETURN
;
17493 /* 32-bit is OK since it'll go in r3/r4. */
17494 if (TARGET_32BIT
&& inner_bytes
>= 4)
17495 return gen_rtx_REG (mode
, regno
);
17498 if (inner_bytes
>= 8)
17499 return gen_rtx_REG (mode
, regno
);
17501 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
17503 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
17504 GEN_INT (inner_bytes
));
17505 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
17508 /* Define how to find the value returned by a function.
17509 VALTYPE is the data type of the value (as a tree).
17510 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17511 otherwise, FUNC is 0.
17513 On the SPE, both FPs and vectors are returned in r3.
17515 On RS/6000 an integer value is in r3 and a floating-point value is in
17516 fp1, unless -msoft-float. */
17519 rs6000_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
17521 enum machine_mode mode
;
17522 unsigned int regno
;
17524 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
17526 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17527 return gen_rtx_PARALLEL (DImode
,
17529 gen_rtx_EXPR_LIST (VOIDmode
,
17530 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
17532 gen_rtx_EXPR_LIST (VOIDmode
,
17533 gen_rtx_REG (SImode
,
17534 GP_ARG_RETURN
+ 1),
17538 if ((INTEGRAL_TYPE_P (valtype
)
17539 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
17540 || POINTER_TYPE_P (valtype
))
17541 mode
= TARGET_32BIT
? SImode
: DImode
;
17543 mode
= TYPE_MODE (valtype
);
17545 if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
17546 regno
= FP_ARG_RETURN
;
17547 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
17548 && targetm
.calls
.split_complex_arg
)
17549 return rs6000_complex_function_value (mode
);
17550 else if (TREE_CODE (valtype
) == VECTOR_TYPE
17551 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
17552 && ALTIVEC_VECTOR_MODE(mode
))
17553 regno
= ALTIVEC_ARG_RETURN
;
17555 regno
= GP_ARG_RETURN
;
17557 return gen_rtx_REG (mode
, regno
);
17560 /* Define how to find the value returned by a library function
17561 assuming the value has mode MODE. */
17563 rs6000_libcall_value (enum machine_mode mode
)
17565 unsigned int regno
;
17567 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
17569 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17570 return gen_rtx_PARALLEL (DImode
,
17572 gen_rtx_EXPR_LIST (VOIDmode
,
17573 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
17575 gen_rtx_EXPR_LIST (VOIDmode
,
17576 gen_rtx_REG (SImode
,
17577 GP_ARG_RETURN
+ 1),
17581 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
17582 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
17583 regno
= FP_ARG_RETURN
;
17584 else if (ALTIVEC_VECTOR_MODE (mode
)
17585 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
17586 regno
= ALTIVEC_ARG_RETURN
;
17587 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
17588 return rs6000_complex_function_value (mode
);
17590 regno
= GP_ARG_RETURN
;
17592 return gen_rtx_REG (mode
, regno
);
17595 /* Define the offset between two registers, FROM to be eliminated and its
17596 replacement TO, at the start of a routine. */
17598 rs6000_initial_elimination_offset (int from
, int to
)
17600 rs6000_stack_t
*info
= rs6000_stack_info ();
17601 HOST_WIDE_INT offset
;
17603 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
17604 offset
= info
->push_p
? 0 : -info
->total_size
;
17605 else if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
17606 offset
= info
->total_size
;
17607 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
17608 offset
= info
->push_p
? info
->total_size
: 0;
17609 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
17617 /* Return true if TYPE is of type __ev64_opaque__. */
17620 is_ev64_opaque_type (tree type
)
17623 && (type
== opaque_V2SI_type_node
17624 || type
== opaque_V2SF_type_node
17625 || type
== opaque_p_V2SI_type_node
));
17629 rs6000_dwarf_register_span (rtx reg
)
17633 if (!TARGET_SPE
|| !SPE_VECTOR_MODE (GET_MODE (reg
)))
17636 regno
= REGNO (reg
);
17638 /* The duality of the SPE register size wreaks all kinds of havoc.
17639 This is a way of distinguishing r0 in 32-bits from r0 in
17642 gen_rtx_PARALLEL (VOIDmode
,
17645 gen_rtx_REG (SImode
, regno
+ 1200),
17646 gen_rtx_REG (SImode
, regno
))
17648 gen_rtx_REG (SImode
, regno
),
17649 gen_rtx_REG (SImode
, regno
+ 1200)));
17652 /* Map internal gcc register numbers to DWARF2 register numbers. */
17655 rs6000_dbx_register_number (unsigned int regno
)
17657 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
17659 if (regno
== MQ_REGNO
)
17661 if (regno
== LINK_REGISTER_REGNUM
)
17663 if (regno
== COUNT_REGISTER_REGNUM
)
17665 if (CR_REGNO_P (regno
))
17666 return regno
- CR0_REGNO
+ 86;
17667 if (regno
== XER_REGNO
)
17669 if (ALTIVEC_REGNO_P (regno
))
17670 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
17671 if (regno
== VRSAVE_REGNO
)
17673 if (regno
== VSCR_REGNO
)
17675 if (regno
== SPE_ACC_REGNO
)
17677 if (regno
== SPEFSCR_REGNO
)
17679 /* SPE high reg number. We get these values of regno from
17680 rs6000_dwarf_register_span. */
17681 if (regno
>= 1200 && regno
< 1232)
17687 /* target hook eh_return_filter_mode */
17688 static enum machine_mode
17689 rs6000_eh_return_filter_mode (void)
17691 return TARGET_32BIT
? SImode
: word_mode
;
17694 /* Target hook for vector_mode_supported_p. */
17696 rs6000_vector_mode_supported_p (enum machine_mode mode
)
17699 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
17702 else if (TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
17709 #include "gt-rs6000.h"