| blob | 61eb527951d20d65eb46021e26837490352c2a31 |
1 2024-04-02 Christophe Lyon <christophe.lyon@linaro.org>
3 * config/aarch64/aarch64-option-extensions.def: Fix comment.
5 2024-04-02 Tom Tromey <tromey@adacore.com>
7 * dwarf2out.cc (print_dw_val) <dw_val_class_loc>: Don't
8 print newline when not recursing.
10 2024-04-02 Iain Sandoe <iain@sandoe.co.uk>
12 * config/darwin.cc (darwin_override_options): Update the
13 clang major version value in the dsymutil check.
15 2024-04-02 Iain Sandoe <iain@sandoe.co.uk>
17 * config/darwin.cc (darwin_override_options): Reduce the debug
18 level to 2 if dsymutil cannot handle .macinfo sections.
20 2024-04-02 Yang Yujie <yangyujie@loongson.cn>
22 * config/loongarch/t-loongarch: Add loongarch-def-arrays.h
23 to OPTION_H_EXTRA.
25 2024-04-02 mengqinggang <mengqinggang@loongson.cn>
26 Lulu Cheng <chenglulu@loongson.cn>
27 Xi Ruoyao <xry111@xry111.site>
29 * config.gcc: Add --with-tls option to change TLS flavor.
30 * config/loongarch/genopts/loongarch.opt.in: Add -mtls-dialect to
31 configure TLS flavor.
32 * config/loongarch/loongarch-def.h (struct loongarch_target): Add
33 tls_dialect.
34 * config/loongarch/loongarch-driver.cc (la_driver_init): Add tls
35 flavor.
36 * config/loongarch/loongarch-opts.cc (loongarch_init_target): Add
37 tls_dialect.
38 (loongarch_config_target): Ditto.
39 (loongarch_update_gcc_opt_status): Ditto.
40 * config/loongarch/loongarch-opts.h (loongarch_init_target): Ditto.
41 (TARGET_TLS_DESC): New define.
42 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Add TLS
43 DESC instructions sequence length.
44 (loongarch_legitimize_tls_address): New TLS DESC instruction sequence.
45 (loongarch_option_override_internal): Add la_opt_tls_dialect.
46 (loongarch_option_restore): Add la_target.tls_dialect.
47 * config/loongarch/loongarch.md (@got_load_tls_desc<mode>): Normal
48 code model for TLS DESC.
49 (got_load_tls_desc_off64): Extreme cmode model for TLS DESC.
50 * config/loongarch/loongarch.opt: Regenerate.
51 * config/loongarch/loongarch.opt.urls: Ditto.
52 * doc/invoke.texi: Add a description of the compilation option
53 '-mtls-dialect={trad,desc}'.
55 2024-04-02 Lulu Cheng <chenglulu@loongson.cn>
57 * config/loongarch/loongarch.opt.urls: Regenerate.
59 2024-04-01 Yang Yujie <yangyujie@loongson.cn>
61 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]recip as
62 aliases to -mrecip={all,none}, respectively.
63 * config/loongarch/loongarch.opt: Regenerate.
64 * config/loongarch/loongarch-def.h (ABI_FPU_64): Rename to...
65 (ABI_FPU64_P): ...this.
66 (ABI_FPU_32): Rename to...
67 (ABI_FPU32_P): ...this.
68 (ABI_FPU_NONE): Rename to...
69 (ABI_NOFPU_P): ...this.
70 (ABI_LP64_P): Define.
71 * config/loongarch/loongarch.cc (loongarch_init_print_operand_punct):
72 Merged into loongarch_global_init.
73 (loongarch_cpu_option_override): Renamed to
74 loongarch_target_option_override.
75 (loongarch_option_override_internal): Move the work after
76 loongarch_config_target into loongarch_target_option_override.
77 (loongarch_global_init): Define.
78 (INIT_TARGET_FLAG): Move to loongarch-opts.cc.
79 (loongarch_option_override): Call loongarch_global_init
80 separately.
81 * config/loongarch/loongarch-opts.cc (loongarch_parse_mrecip_scheme):
82 Split the parsing of -mrecip=<string> from
83 loongarch_option_override_internal.
84 (loongarch_generate_mrecip_scheme): Define. Split from
85 loongarch_option_override_internal.
86 (loongarch_target_option_override): Define. Renamed from
87 loongarch_cpu_option_override.
88 (loongarch_init_misc_options): Define. Split from
89 loongarch_option_override_internal.
90 (INIT_TARGET_FLAG): Move from loongarch.cc.
91 * config/loongarch/loongarch-opts.h (loongarch_target_option_override):
92 New prototype.
93 (loongarch_parse_mrecip_scheme): New prototype.
94 (loongarch_init_misc_options): New prototype.
95 (TARGET_ABI_LP64): Simplify with ABI_LP64_P.
96 * config/loongarch/loongarch.h (TARGET_RECIP_DIV): Simplify.
97 Do not reference specific CPU architecture (LA664).
98 (TARGET_RECIP_SQRT): Same.
99 (TARGET_RECIP_RSQRT): Same.
100 (TARGET_RECIP_VEC_DIV): Same.
101 (TARGET_RECIP_VEC_SQRT): Same.
102 (TARGET_RECIP_VEC_RSQRT): Same.
104 2024-04-01 Lulu Cheng <chenglulu@loongson.cn>
106 * doc/invoke.texi: Add descriptions for the compilation
107 options.
109 2024-03-31 Jeff Law <jlaw@ventanamicro.com>
111 * config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret
112 and sfb_alu.
114 2024-03-31 Pan Li <pan2.li@intel.com>
116 * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
117 the term built-in over builtin.
119 2024-03-31 Pan Li <pan2.li@intel.com>
121 * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
122 Remove unused var decl.
124 2024-03-30 Xi Ruoyao <xry111@xry111.site>
126 PR target/114175
127 * config/mips/mips.cc (mips_setup_incoming_varargs): Only skip
128 mips_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
129 functions if arg.type is NULL.
131 2024-03-29 Andrew Pinski <quic_apinski@quicinc.com>
133 * lto-compress.cc (lto_end_uncompression): Use
134 fatal_error instead of internal_error when ZSTD
135 is not enabled.
137 2024-03-28 Jeff Law <jlaw@ventanamicro.com>
139 * config/h8300/extensions.md (zero_extendqihi*): Add output
140 template for reg->reg case where the regs don't match.
142 2024-03-28 Gaius Mulley <(no_default)>
144 PR modula2/114517
145 * doc/gm2.texi: Mention gm2 treats a # in the first column
146 as a preprocessor directive unless -fno-cpp is supplied.
148 2024-03-28 Jakub Jelinek <jakub@redhat.com>
150 * predict.cc (estimate_bb_frequencies): Fix comment typo,
151 scalling -> scaling.
153 2024-03-28 Jakub Jelinek <jakub@redhat.com>
155 PR tree-optimization/112303
156 * profile-count.h (profile_count::operator+): Perform
157 addition in uint64_t variable and set m_val to MIN of that
158 val and max_count.
159 (profile_count::operator+=): Likewise.
160 (profile_count::operator-=): Formatting fix.
161 (profile_count::apply_probability): Use safe_scale_64bit
162 even in the int overload.
164 2024-03-28 Jan Hubicka <jh@suse.cz>
166 PR middle-end/113907
167 * ipa-icf.cc (sem_function::init): Hash PHI operands
168 (sem_function::compare_phi_node): Add argument about preserving order
170 2024-03-28 Richard Biener <rguenther@suse.de>
172 PR middle-end/114480
173 * cfganal.cc (compute_idf): Use simpler bitmap iteration,
174 touch work_set only when phi_insertion_points changed.
176 2024-03-28 Palmer Dabbelt <palmer@rivosinc.com>
178 * config/riscv/riscv.h (REGISTER_NAMES): Add vxsat.
180 2024-03-27 Segher Boessenkool <segher@kernel.crashing.org>
182 PR rtl-optimization/101523
183 * combine.cc (try_combine): Don't do a 2-insn combination if
184 it does not in fact change I2.
186 2024-03-27 Jakub Jelinek <jakub@redhat.com>
188 * doc/invoke.texi (Spec Files): Use @var{S} instead of S,
189 @var{X} instead of X etc. for other placeholders.
191 2024-03-27 Richard Biener <rguenther@suse.de>
193 PR tree-optimization/114057
194 * tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): Mark
195 BB reduction remain defs as scalar uses.
197 2024-03-27 Victor Do Nascimento <victor.donascimento@arm.com>
199 * config/aarch64/aarch64-option-extensions.def (rcpc3):
200 Fix FEATURE_STRING field to "lrcpc3".
202 2024-03-27 Victor Do Nascimento <victor.donascimento@arm.com>
204 * config/aarch64/aarch64-option-extensions.def: Add LSE128
205 AARCH64_OPT_EXTENSION, adding it as a dependency for the D128
206 feature.
207 * doc/invoke.texi (AArch64 Options): Document +lse128.
209 2024-03-26 Richard Sandiford <richard.sandiford@arm.com>
211 * config/aarch64/aarch64-feature-deps.h: Use constexpr for
212 out-of-line statics.
214 2024-03-26 Cupertino Miranda <cupertino.miranda@oracle.com>
216 PR target/114431
217 * btfout.cc (get_name_for_datasec_entry): Add function.
218 (btf_asm_datasec_entry): Print label when possible.
220 2024-03-26 Richard Ball <richard.ball@arm.com>
222 PR target/114272
223 * config/aarch64/aarch64-cores.def (AARCH64_CORE):
224 Change SCHEDULER_IDENT from cortexa55 to cortexa53
225 for Cortex-A510 and Cortex-A520.
227 2024-03-26 Jakub Jelinek <jakub@redhat.com>
229 PR middle-end/111151
230 * fold-const.cc (extract_muldiv_1) <case MAX_EXPR>: Punt for
231 MULT_EXPR altogether, or for MAX_EXPR if c is -1.
233 2024-03-26 Jakub Jelinek <jakub@redhat.com>
235 PR sanitizer/111736
236 * tsan.cc (instrument_expr): Punt on non-generic address space
237 accesses.
239 2024-03-26 Richard Biener <rguenther@suse.de>
241 PR tree-optimization/114471
242 * tree-vect-stmts.cc (vectorizable_operation): Verify operand
243 types are compatible with the result type.
245 2024-03-26 Richard Biener <rguenther@suse.de>
247 PR tree-optimization/114464
248 * tree-vect-loop.cc (vectorizable_recurr): Verify the latch
249 vector type is compatible with what we chose for the recurrence.
251 2024-03-26 Jakub Jelinek <jakub@redhat.com>
253 * cfgloopmanip.cc (update_loop_exit_probability_scale_dom_bbs):
254 Fix comment typo - multple -> multiple.
255 * config/i386/x86-tune.def (X86_TUNE_ACCUMULATE_OUTGOING_ARGS):
256 Likewise.
258 2024-03-26 YunQiang Su <syq@gcc.gnu.org>
260 * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Predefine
261 __mips_strict_alignment if STRICT_ALIGNMENT.
263 2024-03-25 Richard Biener <rguenther@suse.de>
265 * config.gcc (amdgcn): Add gfx1036 entries.
266 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
267 (gcn_local_sym_hash): Likewise.
268 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
269 (TARGET_GFX1036): New macro.
270 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1036.
271 (gcn_omp_device_kind_arch_isa): Likewise.
272 (output_file_start): Likewise.
273 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1036__.
274 (TARGET_CPU_CPP_BUILTINS): Rename __gfx1030 to __gfx1030__.
275 * config/gcn/gcn.opt: Add gfx1036.
276 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1036): New.
277 (main): Handle gfx1036.
278 * config/gcn/t-omp-device: Add gfx1036 isa.
279 * doc/install.texi (amdgcn): Add gfx1036.
280 * doc/invoke.texi (-march): Likewise.
282 2024-03-25 Pan Li <pan2.li@intel.com>
284 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
285 when V is disabled and init the RVV types and intrinic APIs.
286 * config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
287 error if V ext is disabled.
288 * config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
289 Ditto.
290 (riscv_arguments_is_vector_type_p): Ditto.
291 (riscv_vector_cc_function_p): Ditto.
292 * config/riscv/riscv_vector.h: Remove error if V is disable.
294 2024-03-23 John David Anglin <danglin@gcc.gnu.org>
296 * config/pa/pa.cc (pa_output_global_address): Handle
297 UNSPEC_DLTIND14R addresses.
298 * config/pa/pa.h (PRINT_OPERAND_ADDRESS): Output "RT'" for
299 UNSPEC_DLTIND14R address.
301 2024-03-23 Jakub Jelinek <jakub@redhat.com>
303 PR tree-optimization/114433
304 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
305 m_bitfld_load check save_first rather than m_first.
307 2024-03-23 Jakub Jelinek <jakub@redhat.com>
309 PR tree-optimization/114425
310 * gimple-lower-bitint.cc (build_bitint_stmt_ssa_conflicts): Handle
311 _Complex large/huge _BitInt types like the large/huge _BitInt types.
313 2024-03-23 Jakub Jelinek <jakub@redhat.com>
315 PR middle-end/111683
316 * tree-predcom.cc (pcom_worker::suitable_component_p): If has_write
317 and comp_step is RS_NONZERO, return false if any reference in the
318 component doesn't have DR_STEP a multiple of access size.
320 2024-03-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
322 * config/xtensa/xtensa.md: Add new split pattern described above.
324 2024-03-22 Georg-Johann Lay <avr@gjlay.de>
326 * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic
327 for deprecated SIGNAL and INTERRUPT usage without respective header.
329 2024-03-22 Andrew Stubbs <ams@baylibre.com>
331 * config/gcn/gcn.md (*memory_barrier): Split into RDNA and !RDNA.
332 (atomic_load<mode>): Adjust RDNA cache settings.
333 (atomic_store<mode>): Likewise.
334 (atomic_exchange<mode>): Likewise.
336 2024-03-22 Andrew Stubbs <ams@baylibre.com>
338 * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on
339 RDNA devices.
341 2024-03-22 Andrew Stubbs <ams@baylibre.com>
343 * config.gcc (amdgcn): Add gfx1103 entries.
344 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
345 (gcn_local_sym_hash): Likewise.
346 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
347 (TARGET_GFX1103): New macro.
348 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1103.
349 (gcn_omp_device_kind_arch_isa): Likewise.
350 (output_file_start): Likewise.
351 (gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100.
352 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__.
353 * config/gcn/gcn.opt: Add gfx1103.
354 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New.
355 (main): Handle gfx1103.
356 * config/gcn/t-omp-device: Add gfx1103 isa.
357 * doc/install.texi (amdgcn): Add gfx1103.
358 * doc/invoke.texi (-march): Likewise.
360 2024-03-22 Andrew Stubbs <ams@baylibre.com>
362 * dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector
363 bitmasks.
364 (do_compare_and_jump): Remove now-redundant similar code.
365 * internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector
366 bitmasks.
367 (add_mask_and_len_args): Likewise.
369 2024-03-22 Pan Li <pan2.li@intel.com>
371 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
372 macro __riscv_v_fixed_vlen when zvl.
373 * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
374 New static func to take care of the RVV types decorated by
375 the attributes.
377 2024-03-22 Andrew Pinski <quic_apinski@quicinc.com>
379 PR c/109619
380 * builtins.cc (fold_builtin_1): Use error_operand_p
381 instead of checking against ERROR_MARK.
382 (fold_builtin_2): Likewise.
383 (fold_builtin_3): Likewise.
385 2024-03-22 Jakub Jelinek <jakub@redhat.com>
387 PR sanitizer/111736
388 * ubsan.cc (ubsan_expand_null_ifn, instrument_mem_ref): Avoid
389 SANITIZE_NULL instrumentation for non-generic address spaces
390 for which targetm.addr_space.zero_address_valid (as) is true.
392 2024-03-22 Jakub Jelinek <jakub@redhat.com>
394 PR tree-optimization/114405
395 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
396 Set rprec to limb_prec rather than 0 if tprec is divisible by
397 limb_prec. In the last bf_cur handling, set rprec to (tprec + bo_bit)
398 % limb_prec rather than tprec % limb_prec and use just rprec instead
399 of rprec + bo_bit. For build_bit_field_ref offset, divide
400 (tprec + bo_bit) by limb_prec rather than just tprec.
402 2024-03-22 Christoph Müllner <christoph.muellner@vrull.eu>
404 PR target/114194
405 * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC.
406 Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR.
408 2024-03-22 Jeff Law <jlaw@ventanamicro.com>
410 * config/riscv/riscv.cc (riscv_expand_prologue): Add missing stack
411 tie for scalable and final stack adjustment if needed.
412 Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
414 2024-03-22 Pan Li <pan2.li@intel.com>
416 PR target/114352
417 * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
418 New struct for func decl and target name.
419 (struct riscv_func_target_hasher): New hasher for hash table mapping
420 from the fn_decl to fn_target_name.
421 (riscv_func_decl_hash): New func to compute the hash for fn_decl.
422 (riscv_func_target_hasher::hash): New func to impl hash interface.
423 (riscv_func_target_hasher::equal): New func to impl equal interface.
424 (riscv_cmdline_subset_list): New static var for cmdline subset list.
425 (riscv_func_target_table_lazy_init): New func to lazy init the func
426 target hash table.
427 (riscv_func_target_get): New func to get target name from hash table.
428 (riscv_func_target_put): New func to put target name into hash table.
429 (riscv_func_target_remove_and_destory): New func to remove target
430 info from the hash table and destory it.
431 (riscv_parse_arch_string): Set the static var cmdline_subset_list.
432 * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
433 var for cmdline subset list.
434 (riscv_func_target_get): New func decl.
435 (riscv_func_target_put): Ditto.
436 (riscv_func_target_remove_and_destory): Ditto.
437 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
438 Take cmdline_subset_list instead of current_subset_list when clone.
439 (riscv_process_target_attr): Record the func target info to hash table.
440 (riscv_option_valid_attribute_p): Add new arg tree fndel.
441 * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
442 func target info and print the arch message.
444 2024-03-22 Pan Li <pan2.li@intel.com>
446 PR target/114352
447 * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
448 Replace implied, combine and check to func finalize.
449 (riscv_subset_list::finalize): New func impl to take care of
450 implied, combine ext and related checks.
451 * config/riscv/riscv-subset.h: Add func decl for finalize.
452 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
453 Finalize the ext before return succeed.
454 * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
455 machine mode before when set cur function.
457 2024-03-21 Andrew Stubbs <ams@baylibre.com>
459 * config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.
461 2024-03-21 Andrew Stubbs <ams@baylibre.com>
463 * config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.
465 2024-03-21 Andrew Stubbs <ams@baylibre.com>
467 * config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
468 device_malloc call.
470 2024-03-21 liuhongt <hongtao.liu@intel.com>
472 PR tree-optimization/114396
473 * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
474 and true to wi::from_mpz.
476 2024-03-21 Richard Biener <rguenther@suse.de>
478 PR tree-optimization/111736
479 * asan.cc (instrument_derefs): Do not instrument accesses
480 to non-generic address-spaces.
482 2024-03-21 Richard Biener <rguenther@suse.de>
484 PR tree-optimization/113727
485 * tree-sra.cc (analyze_access_subtree): Do not allow
486 replacements in subtrees when grp_partial_lhs.
488 2024-03-21 liuhongt <hongtao.liu@intel.com>
490 PR middle-end/114347
491 * doc/invoke.texi: Document -fexcess-precision=16.
493 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
495 * config/bpf/core-builtins.cc (bpf_core_get_index): Check if
496 field contains a DECL_NAME.
498 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
500 * config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
501 Add assert to validate the string is set.
502 * config/bpf/core-builtins.cc (cr_final): Make string struct
503 field as const.
504 (process_enum_value): Correct for field type change.
505 (process_type): Set access string to "0".
507 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
509 * config/bpf/core-builtins.cc (core_field_info): Add
510 support for POINTER_PLUS_EXPR in the root of the field expression.
511 (bpf_core_get_index): Likewise.
512 (pack_field_expr): Make the BTF type to point to the structure
513 related node, instead of its pointer type.
514 (make_core_safe_access_index): Correct to new code.
516 2024-03-20 Xi Ruoyao <xry111@xry111.site>
518 PR target/114407
519 * config/loongarch/loongarch-opts.cc (loongarch_config_target):
520 Fix typo in diagnostic message, enabing -> enabling.
522 2024-03-20 Jakub Jelinek <jakub@redhat.com>
524 PR target/114175
525 * config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
526 TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
527 if arg.type is NULL.
529 2024-03-20 Jakub Jelinek <jakub@redhat.com>
531 PR target/114175
532 * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
533 nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
534 if arg.type is NULL.
536 2024-03-20 Jakub Jelinek <jakub@redhat.com>
538 PR target/114175
539 * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
540 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
541 if arg.type is NULL.
543 2024-03-20 Jakub Jelinek <jakub@redhat.com>
545 PR target/114175
546 * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
547 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
548 if arg.type is NULL.
550 2024-03-20 Jakub Jelinek <jakub@redhat.com>
552 PR target/114175
553 * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
554 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
555 if arg.type is NULL.
557 2024-03-20 Jakub Jelinek <jakub@redhat.com>
559 PR target/114175
560 * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
561 skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
562 if arg.type is NULL.
564 2024-03-20 Jakub Jelinek <jakub@redhat.com>
566 PR target/114175
567 * config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
568 csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
569 if arg.type is NULL.
571 2024-03-20 Yury Khrustalev <yury.khrustalev@arm.com>
573 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
575 2024-03-20 Jakub Jelinek <jakub@redhat.com>
577 PR tree-optimization/114365
578 * gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
579 a PHI node, set iv2 to its result afterwards.
581 2024-03-20 Jakub Jelinek <jakub@redhat.com>
583 * tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
584 probabbility -> probability.
585 (ch_base::copy_headers): Fix comment typo: itrations -> iterations.
587 2024-03-20 Jakub Jelinek <jakub@redhat.com>
589 PR bootstrap/114369
590 * system.h (vec_step): Define to vec_step_ when compiling
591 with clang on PowerPC.
593 2024-03-20 demin.han <demin.han@starfivetech.com>
595 PR target/112651
596 * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
597 (enum rvv_max_lmul_enum): Ditto
598 (TARGET_MAX_LMUL): Ditto
599 * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
600 * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
601 (costs::better_main_loop_than_p): Ditto
602 * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul
604 2024-03-20 Richard Biener <rguenther@suse.de>
606 PR middle-end/113396
607 * tree-dfa.cc (get_ref_base_and_extent): Use index range
608 bounds only if they fit within the address-range constraints
609 of offset_int.
611 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
613 * config/loongarch/loongarch.cc
614 (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
615 UNITS_PER_FPREG macros.
616 (loongarch_hard_regno_nregs): Ditto.
617 (loongarch_class_max_nregs): Ditto.
618 (loongarch_get_separate_components): Ditto.
619 (loongarch_process_components): Ditto.
620 * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
621 (UNITS_PER_HWFPVALUE): Ditto.
622 (UNITS_PER_FPVALUE): Ditto.
624 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
626 * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
627 of loongarch_expand_vec_cmp()'s return value.
628 (vec_cmpu<ILASX:mode><mode256_i>): Ditto.
629 * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
630 (vec_cmpu<ILSX:mode><mode_i>): Ditto.
631 * config/loongarch/loongarch-protos.h
632 (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
633 type from bool to void.
634 * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
636 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
638 * config/loongarch/loongarch-protos.h
639 (loongarch_cfun_has_cprestore_slot_p): Delete.
640 (loongarch_adjust_insn_length): Delete.
641 (current_section_name): Delete.
642 (loongarch_split_symbol_type): Delete.
643 * config/loongarch/loongarch.cc
644 (loongarch_case_values_threshold): Delete.
645 (loongarch_spill_class): Delete.
646 (TARGET_OPTAB_SUPPORTED_P): Delete.
647 (TARGET_CASE_VALUES_THRESHOLD): Delete.
648 (TARGET_SPILL_CLASS): Delete.
650 2024-03-20 Lewis Hyatt <lhyatt@gmail.com>
652 PR c++/111918
653 * diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
654 * diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
655 Make use of DK_ANY to indicate a diagnostic was initially enabled.
656 (diagnostic_context::diagnostic_enabled): Do not change the type of
657 a diagnostic if the saved classification is type DK_ANY.
659 2024-03-19 Martin Jambor <mjambor@suse.cz>
661 PR ipa/108802
662 PR ipa/114254
663 * ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
664 at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
665 a pointer parameter.
666 (ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
667 parameter, also recognize the case when pfn pointer is loaded in its
668 own BB.
670 2024-03-19 Vladimir N. Makarov <vmakarov@redhat.com>
672 PR target/99829
673 * lra-constraints.cc (lra_constraints): Prevent removing insn
674 with reverse equivalence to memory if the memory was reloaded.
676 2024-03-19 David Malcolm <dmalcolm@redhat.com>
678 PR middle-end/114348
679 * diagnostic-format-json.cc
680 (json_stderr_output_format::machine_readable_stderr_p): New.
681 (json_file_output_format::machine_readable_stderr_p): New.
682 * diagnostic-format-sarif.cc
683 (sarif_stream_output_format::machine_readable_stderr_p): New.
684 (sarif_file_output_format::machine_readable_stderr_p): New.
685 * diagnostic.cc (diagnostic_context::action_after_output): Move
686 "fnotice" to before "finish" call, so that we still have the
687 diagnostic_context.
688 (fnotice): Bail out if the user requested one of the
689 machine-readable diagnostic output formats on stderr.
690 * diagnostic.h
691 (diagnostic_output_format::machine_readable_stderr_p): New pure
692 virtual function.
693 (diagnostic_text_output_format::machine_readable_stderr_p): New.
694 (diagnostic_context::get_output_format): New accessor.
696 2024-03-19 Edwin Lu <ewlu@rivosinc.com>
698 PR target/114175
699 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
700 riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
701 if arg.type is NULL
703 2024-03-19 Jonathan Wakely <jwakely@redhat.com>
705 * doc/install.texi (Prerequisites): Document use of autogen for
706 libstdc++.
708 2024-03-19 Richard Biener <rguenther@suse.de>
710 PR tree-optimization/114151
711 PR tree-optimization/114269
712 PR tree-optimization/114322
713 PR tree-optimization/114074
714 * tree-chrec.cc (chrec_fold_multiply): Restrict the use of
715 unsigned arithmetic when actual overflow on constant operands
716 is observed.
718 2024-03-19 Jakub Jelinek <jakub@redhat.com>
720 PR target/114175
721 * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
722 arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
723 if arg.type is NULL.
725 2024-03-19 Xi Ruoyao <xry111@xry111.site>
727 PR target/114175
728 * config/loongarch/loongarch.cc
729 (loongarch_setup_incoming_varargs): Only skip
730 loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
731 functions if arg.type is NULL.
733 2024-03-19 Christophe Lyon <christophe.lyon@linaro.org>
735 PR target/114323
736 * config/arm/arm-mve-builtins.cc
737 (function_instance::reads_global_state_p): Take CP_READ_MEMORY
738 into account.
740 2024-03-19 Jakub Jelinek <jakub@redhat.com>
742 PR target/114175
743 * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
744 function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
745 if arg.type is NULL.
747 2024-03-19 Jakub Jelinek <jakub@redhat.com>
749 PR target/114175
750 * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
751 rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
752 if arg.type is NULL.
754 2024-03-19 Richard Biener <rguenther@suse.de>
756 PR tree-optimization/114375
757 * tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
758 load permutation for masked loads but reject it when any
759 such is necessary.
760 * tree-vect-stmts.cc (vectorizable_load): Reject masked
761 VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
762 supported.
764 2024-03-19 Mary Bennett <mary.bennett@embecosm.com>
766 * common/config/riscv/riscv-common.cc: Create XCVbi extension
767 support.
768 * config/riscv/riscv.opt: Likewise.
769 * config/riscv/corev.md: Implement cv_branch<mode> pattern
770 for cv.beqimm and cv.bneimm.
771 * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
772 branch instruction pattern.
773 * config/riscv/constraints.md: Implement constraints
774 cv_bi_s5 - signed 5-bit immediate.
775 * config/riscv/predicates.md: Implement predicate
776 const_int5s_operand - signed 5 bit immediate.
777 * doc/sourcebuild.texi: Add XCVbi documentation.
779 2024-03-19 Chen Jiawei <jiawei@iscas.ac.cn>
781 * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
782 (RISCV_CORE): Ditto.
783 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
784 option.
785 * config/riscv/riscv.cc: New def.
786 * config/riscv/riscv.md: New include.
787 * config/riscv/xiangshan.md: New file.
789 2024-03-18 David Malcolm <dmalcolm@redhat.com>
791 PR analyzer/110902
792 PR analyzer/110928
793 PR analyzer/111305
794 PR analyzer/111441
795 * selftest.h (ASSERT_NE_AT): New macro.
797 2024-03-18 Uros Bizjak <ubizjak@gmail.com>
799 PR target/111822
800 * config/i386/i386-features.cc (smode_convert_cst): New function
801 to handle SImode, DImode and TImode immediates, generalized from
802 timode_convert_cst.
803 (timode_convert_cst): Remove.
804 (scalar_chain::convert_op): Unify from
805 general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
806 (general_scalar_chain::convert_op): Remove.
807 (timode_scalar_chain::convert_op): Remove.
808 (timode_scalar_chain::convert_insn): Update the call to
809 renamed timode_convert_cst.
810 * config/i386/i386-features.h (class scalar_chain):
811 Redeclare convert_op as protected class member.
812 (class general_calar_chain): Remove convert_op.
813 (class timode_scalar_chain): Ditto.
815 2024-03-18 Jan Hubicka <jh@suse.cz>
817 * config/i386/zn4zn5.md: Add file missed in the previous commit.
819 2024-03-18 Jan Hubicka <jh@suse.cz>
820 Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com>
822 * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
823 * common/config/i386/i386-common.cc (processor_names): Add znver5.
824 (processor_alias_table): Likewise.
825 * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
826 family.
827 (processor_subtypes): Add znver5.
828 * config.gcc (x86_64-*-* |...): Likewise.
829 * config/i386/driver-i386.cc (host_detect_local_cpu): Let
830 march=native detect znver5 cpu's.
831 * config/i386/i386-c.cc (ix86_target_macros_internal): Add
832 znver5.
833 * config/i386/i386-options.cc (m_ZNVER5): New definition
834 (processor_cost_table): Add znver5.
835 * config/i386/i386.cc (ix86_reassociation_width): Likewise.
836 * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
837 (PTA_ZNVER5): New definition.
838 * config/i386/i386.md (define_attr "cpu"): Add znver5.
839 (Scheduling descriptions) Add znver5.md.
840 * config/i386/x86-tune-costs.h (znver5_cost): New definition.
841 * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
842 (ix86_adjust_cost): Likewise.
843 * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
844 (avx512_store_by_pieces): Add m_ZNVER5.
845 * doc/extend.texi: Add znver5.
846 * doc/invoke.texi: Likewise.
847 * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.
849 2024-03-18 Georg-Johann Lay <avr@gjlay.de>
851 * config/avr/constraints.md (CX2, CX3, CX4): New constraints.
852 * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
853 * config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
854 * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
855 (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
856 (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
858 2024-03-18 liuhongt <hongtao.liu@intel.com>
860 PR target/114334
861 * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
862 (MODEF248): New mode iterator.
863 (ssevecmodesuffix): Hanlde BF and HF.
864 * config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
865 (<code><mode>3): Ditto.
867 2024-03-18 John David Anglin <danglin@gcc.gnu.org>
869 PR rtl-optimization/112415
870 * config/pa/pa.cc (pa_emit_move_sequence): Revise condition
871 for symbolic memory operands.
872 (pa_legitimate_address_p): Revise LO_SUM condition.
873 * config/pa/pa.h (INT14_OK_STRICT): Revise define. Move
874 comment about GNU linker to predicates.md.
875 * config/pa/predicates.md (floating_point_store_memory_operand):
876 Revise condition for symbolic memory operands. Update
877 comment.
879 2024-03-17 John David Anglin <danglin@gcc.gnu.org>
881 * config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.
883 2024-03-16 Jakub Jelinek <jakub@redhat.com>
885 PR target/114175
886 * config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
887 ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
888 if arg.type is NULL.
890 2024-03-16 Jakub Jelinek <jakub@redhat.com>
892 PR tree-optimization/114329
893 * gimple-lower-bitint.cc (struct bitint_large_huge): Declare
894 build_bit_field_ref method.
895 (bitint_large_huge::build_bit_field_ref): New method.
896 (bitint_large_huge::lower_mergeable_stmt): Use it.
898 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
900 * config/riscv/riscv.opt.urls: Regenerated.
901 * config/rs6000/sysv4.opt.urls: Likewise.
902 * config/xtensa/xtensa.opt.urls: Likewise.
904 2024-03-15 Jakub Jelinek <jakub@redhat.com>
906 * lower-subreg.cc (resolve_simple_move): Fix comment typo,
907 betwee -> between.
908 * edit-context.cc (class line_event): Fix comment typo,
909 betweeen -> between.
911 2024-03-15 Jakub Jelinek <jakub@redhat.com>
913 PR target/114339
914 * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
915 a pasto, compare code against LE rather than GE.
917 2024-03-15 Joe Ramsay <Joe.Ramsay@arm.com>
919 * match.pd: Fix truncation pattern for -fno-signed-zeroes
921 2024-03-15 Jakub Jelinek <jakub@redhat.com>
923 PR middle-end/114332
924 * expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.
926 2024-03-15 Jakub Jelinek <jakub@redhat.com>
928 PR tree-optimization/113466
929 * gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
930 member.
931 (bitint_large_huge::bitint_large_huge): Initialize it.
932 (bitint_large_huge::~bitint_large_huge): Release it.
933 (bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
934 before which at least one statement has been inserted.
935 (gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
936 calls to a different block and add corresponding PHIs.
938 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
940 * config/mips/mips.opt: Support -mstrict-align, and use
941 TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
942 as alias.
943 * config/mips/mips.h: Use TARGET_STRICT_ALIGN.
944 * config/mips/mips.opt.urls: Regenerate.
945 * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
947 2024-03-15 Tejas Belagod <tejas.belagod@arm.com>
949 PR middle-end/114108
950 * tree-vect-patterns.cc (vect_recog_abd_pattern): Call
951 vect_convert_output with the correct vecitype.
953 2024-03-15 Chenghui Pan <panchenghui@loongson.cn>
955 * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
956 Remove masking of operand 3.
958 2024-03-14 Jason Merrill <jason@redhat.com>
960 * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
961 comments.
963 2024-03-14 John David Anglin <danglin@gcc.gnu.org>
965 PR target/114288
966 * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
967 14-bit displacements before reload for modes that may use
968 a floating-point load or store.
970 2024-03-14 David Faust <david.faust@oracle.com>
972 * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
974 2024-03-14 Max Filippov <jcmvbkbc@gmail.com>
976 * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
977 patterns ahead of the l32i.n and s32i.n.
979 2024-03-14 Jakub Jelinek <jakub@redhat.com>
981 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
983 2024-03-14 Jakub Jelinek <jakub@redhat.com>
985 PR middle-end/113907
986 * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
987 SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
988 functions.
990 2024-03-14 Xi Ruoyao <xry111@xry111.site>
992 * config/loongarch/loongarch.md (any_ge): Remove.
993 (sge<u>_<X:mode><GPR:mode>): Remove.
995 2024-03-14 Jakub Jelinek <jakub@redhat.com>
997 PR target/114310
998 * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
999 TImode force newval into a register.
1001 2024-03-14 Chung-Lin Tang <cltang@baylibre.com>
1003 * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
1004 (OMP_CLAUSE__CACHE__READONLY): New macro.
1005 * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
1006 uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
1007 OMP_CLAUSE__CACHE__READONLY.
1008 * tree-pretty-print.cc (dump_omp_clause): Add support for printing
1009 OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
1011 2024-03-14 Andreas Krebbel <krebbel@linux.ibm.com>
1013 * config/s390/s390.cc (s390_encode_section_info): Adjust the check
1014 for misaligned symbols.
1015 * config/s390/s390.opt: Improve documentation.
1017 2024-03-14 Jakub Jelinek <jakub@redhat.com>
1019 * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
1020 flags and probability from ad_edge to e edge. If CDI_DOMINATORS
1021 are computed, recompute immediate dominator of other_edge->src
1022 and other_edge->dest.
1023 (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
1024 for the returns_twice call case to the gsi_for_stmt (stmt) to deal
1025 with update it for bb splitting.
1027 2024-03-14 liuhongt <hongtao.liu@intel.com>
1029 * config/i386/i386-features.cc
1030 (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
1031 (convert_scalars_to_vector): Ditto.
1032 * config/i386/i386-features.h (class scalar_chain): New
1033 memeber control_flow_insns.
1035 2024-03-13 Jakub Jelinek <jakub@redhat.com>
1037 PR middle-end/114319
1038 * gimple-ssa-store-merging.cc
1039 (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
1040 allow matching __builtin_bswap64 if there is bswapsi2 optab.
1042 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1044 * config/s390/s390.cc (s390_secondary_reload): Guard
1045 SYMBOL_FLAG_NOTALIGN2_P.
1047 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1049 * config/s390/s390-builtin-types.def: Update to reflect latest
1050 changes.
1051 * config/s390/s390-builtins.def: Streamline vector builtins with
1052 LLVM.
1054 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1056 * config/s390/s390-builtins.def (vec_permi): Deprecate.
1057 (vec_ctd): Deprecate.
1058 (vec_ctd_s64): Deprecate.
1059 (vec_ctd_u64): Deprecate.
1060 (vec_ctsl): Deprecate.
1061 (vec_ctul): Deprecate.
1062 (vec_ld2f): Deprecate.
1063 (vec_st2f): Deprecate.
1064 (vec_insert): Deprecate overloads with bool vectors.
1066 2024-03-13 Jakub Jelinek <jakub@redhat.com>
1068 PR middle-end/114313
1069 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
1070 TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
1071 (bitint_large_huge::handle_load): Pass NULL_TREE rather than
1072 rhs_type to limb_access for the bitfield load cases.
1073 (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
1074 lhs_type to limb_access if nlhs is non-NULL.
1076 2024-03-13 Jakub Jelinek <jakub@redhat.com>
1078 PR sanitizer/112709
1079 * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
1080 build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
1081 gsi_safe_insert_before instead of gsi_insert_before.
1083 2024-03-13 Jakub Jelinek <jakub@redhat.com>
1085 PR sanitizer/112709
1086 * gimple-iterator.h (gsi_safe_insert_before,
1087 gsi_safe_insert_seq_before): Declare.
1088 * gimple-iterator.cc: Include gimplify.h.
1089 (edge_before_returns_twice_call, adjust_before_returns_twice_call,
1090 gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
1091 * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
1092 instrument_nonnull_arg, instrument_nonnull_return): Use
1093 gsi_safe_insert_before instead of gsi_insert_before.
1094 (maybe_instrument_pointer_overflow): Use force_gimple_operand,
1095 gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
1096 instead of force_gimple_operand_gsi.
1097 (instrument_object_size): Likewise. Use gsi_safe_insert_before
1098 instead of gsi_insert_before.
1100 2024-03-12 Richard Biener <rguenther@suse.de>
1102 PR tree-optimization/114121
1103 * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
1104 converted operand properly.
1105 (chrec_fold_multiply): Likewise. Handle missed recursion.
1107 2024-03-12 Jakub Jelinek <jakub@redhat.com>
1109 PR sanitizer/112709
1110 * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
1111 stores on the caller side unless it is a call to a builtin or
1112 internal function or function doesn't return by hidden reference.
1113 (maybe_instrument_call): Likewise.
1114 (instrument_derefs): Instrument stores to RESULT_DECL if
1115 returning by hidden reference.
1117 2024-03-12 Jakub Jelinek <jakub@redhat.com>
1119 PR tree-optimization/114293
1120 * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
1121 max is smaller than min, set max to ~(size_t)0.
1123 2024-03-12 Pan Li <pan2.li@intel.com>
1125 * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
1126 code style greater than 80 chars.
1127 (riscv_cpu_cpp_builtins): Fix useless empty line, indent
1128 with 3 space(s) and argument unalignment.
1130 2024-03-12 Richard Biener <rguenther@suse.de>
1132 PR tree-optimization/114297
1133 * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
1134 live stmts SLP node to vect_create_epilog_for_reduction.
1136 2024-03-12 Andrew Pinski <quic_apinski@quicinc.com>
1138 PR driver/114314
1139 * common.opt (fmultiflags): Add RejectNegative.
1141 2024-03-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
1143 * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
1144 * config/aarch64/aarch64.opt: Likewise.
1145 * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
1146 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
1147 (aarch64_expand_epilogue): Likewise.
1148 (aarch64_post_cfi_startproc): Likewise.
1149 (aarch64_handle_no_branch_protection): Copy and rename.
1150 (aarch64_handle_standard_branch_protection): Likewise.
1151 (aarch64_handle_pac_ret_protection): Likewise.
1152 (aarch64_handle_pac_ret_leaf): Likewise.
1153 (aarch64_handle_pac_ret_b_key): Likewise.
1154 (aarch64_handle_bti_protection): Likewise.
1155 (aarch64_override_options): Update branch protection validation.
1156 (aarch64_handle_attr_branch_protection): Likewise.
1157 * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
1158 Pass branch protection type description as argument.
1159 (struct aarch_branch_protect_type): Move from aarch-common.h.
1160 * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
1161 Remove.
1162 (aarch_handle_standard_branch_protection): Remove.
1163 (aarch_handle_pac_ret_protection): Remove.
1164 (aarch_handle_pac_ret_leaf): Remove.
1165 (aarch_handle_pac_ret_b_key): Remove.
1166 (aarch_handle_bti_protection): Remove.
1167 (aarch_validate_mbranch_protection): Pass branch protection type
1168 description as argument.
1169 * config/arm/aarch-common.h (enum aarch_key_type): Remove.
1170 (struct aarch_branch_protect_type): Remove.
1171 * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
1172 * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
1173 (arm_handle_standard_branch_protection): Likewise.
1174 (arm_handle_pac_ret_protection): Likewise.
1175 (arm_handle_pac_ret_leaf): Likewise.
1176 (arm_handle_bti_protection): Likewise.
1177 (arm_configure_build_target): Update branch protection validation.
1178 * config/arm/arm.opt: Remove aarch_ra_sign_key.
1180 2024-03-11 Richard Biener <rguenther@suse.de>
1182 PR middle-end/114299
1183 * gimplify.cc (internal_get_tmp_var): When gimplification
1184 of VAL failed, return a decl.
1186 2024-03-11 Jakub Jelinek <jakub@redhat.com>
1188 PR tree-optimization/114278
1189 * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
1190 longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
1192 2024-03-11 Eric Botcazou <ebotcazou@adacore.com>
1194 PR debug/113519
1195 PR debug/113777
1196 * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
1197 generate the DIE with the same parent as in the regular case.
1199 2024-03-11 Andrew Pinski <quic_apinski@quicinc.com>
1201 PR middle-end/95351
1202 * fold-const.cc (merge_truthop_with_opposite_arm): Use
1203 the type of the operands of the comparison and not the type
1204 of the comparison.
1206 2024-03-10 jlaw <jeffreyalaw@gmail.com>
1208 PR tree-optimization/110199
1209 * tree-ssa-scopedtables.cc
1210 (avail_exprs_stack::simplify_binary_operation): Generalize handling
1211 of MIN_EXPR/MAX_EXPR to allow additional simplifications. Canonicalize
1212 comparison operands for other cases.
1214 2024-03-10 Pan Li <pan2.li@intel.com>
1216 * tree-vect-stmts.cc (vectorizable_store): Enable the assert
1217 during transform process.
1218 (vectorizable_load): Ditto.
1220 2024-03-10 jlaw <jeffreyalaw@gmail.com>
1222 PR target/102250
1223 * doc/install.texi: Document need for python when building
1224 RISC-V compilers.
1226 2024-03-10 jlaw <jeffreyalaw@gmail.com>
1228 PR target/111362
1229 * mode-switching.cc (optimize_mode_switching): Only process
1230 NONDEBUG insns.
1232 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
1234 * config/avr/avr.md: Fix typos in comment, indentation glitches
1235 and some other nits.
1237 2024-03-09 Jakub Jelinek <jakub@redhat.com>
1239 PR target/114284
1240 * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
1241 src containing MEMs unless prop.likely_profitable_p ().
1243 2024-03-09 Xi Ruoyao <xry111@xry111.site>
1245 * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
1246 Support 'Q' for R_LARCH_RELAX for TLS IE.
1247 (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
1248 IE.
1249 * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
1251 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
1253 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
1254 usum_widenqihi and add_zero_extend1.
1255 [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
1256 sub+sign_extend.
1257 * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
1258 Compute exact insn lengths.
1259 (*usum_widenqihi3): Allow input operands to commute.
1261 2024-03-09 Jakub Jelinek <jakub@redhat.com>
1263 * config/i386/i386.opt.urls: Regenerate.
1265 2024-03-09 Lulu Cheng <chenglulu@loongson.cn>
1267 * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
1268 In loongarch64, a sign extension operation is added when
1269 operands[2] is a register operand and the mode is SImode.
1271 2024-03-08 Martin Jambor <mjambor@suse.cz>
1273 PR ipa/113757
1274 * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
1275 id->killed_new_ssa_names.
1277 2024-03-08 Vladimir N. Makarov <vmakarov@redhat.com>
1279 PR target/113790
1280 * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
1281 for non-reload pseudo too.
1283 2024-03-08 David Faust <david.faust@oracle.com>
1285 * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
1286 not attempt inline expansion if size is above threshold.
1287 * config/bpf/bpf.opt (-minline-memops-threshold): New option.
1288 * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
1289 Document.
1291 2024-03-08 Richard Biener <rguenther@suse.de>
1293 PR tree-optimization/114269
1294 PR tree-optimization/114074
1295 * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
1296 in the third CASE_CONVERT case as well.
1297 (chrec_fold_multiply): Handle sign-conversions from unsigned
1298 by performing the operation in the unsigned type.
1300 2024-03-08 Georg-Johann Lay <avr@gjlay.de>
1302 * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
1303 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
1305 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1307 * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
1308 asm_noperands < 0 means it is not asm goto too.
1310 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1312 PR target/38534
1313 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
1314 option.
1315 * config/i386/i386-options.cc (ix86_set_func_type): Don't use
1316 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
1317 ix86_noreturn_no_callee_saved_registers is enabled.
1318 * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
1320 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1322 PR debug/113918
1323 * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
1324 on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
1326 2024-03-08 demin.han <demin.han@starfivetech.com>
1328 PR target/114264
1329 * config/riscv/riscv-vector-costs.cc: Fix ICE
1331 2024-03-08 Haochen Gui <guihaoc@gcc.gnu.org>
1333 * fwprop.cc (forward_propagate_into): Return false for volatile set
1334 source rtx.
1336 2024-03-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
1338 PR target/113618
1339 * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
1340 (aarch64_expand_cpymem): Emit single load/store only.
1341 (aarch64_set_one_block): Emit single stores only.
1343 2024-03-07 Robin Dapp <rdapp@ventanamicro.com>
1345 PR middle-end/114196
1346 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
1347 vectorization guards.
1349 2024-03-07 Jonathan Wakely <jwakely@redhat.com>
1351 * doc/cppopts.texi: Remove incorrect claim about -dD not
1352 outputting predefined macros.
1354 2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
1356 PR target/113950
1357 * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
1358 and simplify else if with else.
1360 2024-03-07 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
1362 * system.h: Include safe-ctype.h after C++ standard headers.
1364 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1366 PR rtl-optimization/110079
1367 * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
1368 asm goto.
1370 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1372 PR middle-end/105533
1373 * expmed.cc (choose_mult_variant): Only try the val - 1 variant
1374 if val is not HOST_WIDE_INT_MIN or if mode has exactly
1375 HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing
1376 val - 1.
1378 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1380 PR middle-end/105533
1381 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
1382 Multiple op->off by BITS_PER_UNIT instead of shifting it left by
1383 LOG2_BITS_PER_UNIT.
1385 2024-03-07 Yang Yujie <yangyujie@loongson.cn>
1387 * config.gcc: Add a case for loongarch*-*-linux-musl*.
1388 * config/loongarch/linux.h: Disable the multilib-compatible
1389 treatment for *musl* targets.
1390 * config/loongarch/musl.h: New file.
1392 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1394 PR tree-optimization/114009
1395 * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
1396 argument even for GENERIC, not just for GIMPLE.
1397 * match.pd (a * !a -> 0): New simplifications.
1399 2024-03-07 demin.han <demin.han@starfivetech.com>
1401 * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
1402 * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
1403 (expand_vec_cmp_float): Adapt arguments
1405 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
1407 PR target/114232
1408 * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
1409 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
1410 (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1411 (<plusminus:insn>v2qi3): Enable for optimize_size instead
1412 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
1413 (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1414 (<any_shift:insn>v2qi3): Enable for optimize_size instead
1415 of optimize_function_for_size_p.
1417 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
1419 PR target/114200
1420 PR target/114202
1421 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
1423 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
1425 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
1426 (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
1427 offset handling.
1428 (costs::add_stmt_cost): Also adjust cost for statements without
1429 stmt_info.
1430 * config/riscv/riscv-vector-costs.h: Define zero constant.
1432 2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
1434 PR target/113915
1435 * config/arm/arm.md (NOCOND): Improve comment.
1436 (arm_rev*) Add predicable.
1437 * config/arm/arm.cc (arm_final_prescan_insn): Add check for
1438 PREDICABLE_YES.
1440 2024-03-06 Jeff Law <jlaw@ventanamicro.com>
1442 PR target/113001
1443 PR target/112871
1444 * config/riscv/riscv.cc (expand_conditional_move): Do not swap
1445 operands when the comparison operand is the same as the false
1446 arm for a NE test.
1448 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
1450 * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
1451 Eliminate common code and use generic code instead.
1453 2024-03-06 Georg-Johann Lay <avr@gjlay.de>
1455 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
1456 rtx cost.
1458 2024-03-06 Richard Biener <rguenther@suse.de>
1460 PR tree-optimization/114239
1461 * tree-vect-loop.cc (vect_get_vect_def): Remove.
1462 (vect_create_epilog_for_reduction): The passed in stmt_info
1463 should now be the live stmt that produces the scalar reduction
1464 result. Revert PR114192 fix. Base reduction info off
1465 info_for_reduction. Remove special handling of
1466 early-break/peeled, restore original vector def gathering.
1467 Make sure to pick the correct exit PHIs.
1468 (vectorizable_live_operation): Pass in the proper stmt_info
1469 for early break exits.
1471 2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
1473 * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
1474 out-of-class definitions of static constants.
1476 2024-03-06 Richard Biener <rguenther@suse.de>
1478 PR tree-optimization/114249
1479 * tree-vect-slp.cc (vect_build_slp_instance): Move making
1480 a BB reduction lane number even ...
1481 (vect_slp_check_for_roots): ... here to avoid leaking
1482 pattern defs.
1484 2024-03-06 Richard Biener <rguenther@suse.de>
1486 PR tree-optimization/114246
1487 * tree-ssa-dse.cc (increment_start_addr): Strip useless
1488 type conversions from the adjusted address.
1490 2024-03-06 Jakub Jelinek <jakub@redhat.com>
1492 PR rtl-optimization/114190
1493 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
1494 Call df_remove_problem for df_note before calling df_analyze.
1496 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
1497 Indu Bhagat <indu.bhagat@oracle.com>
1499 PR debug/114186
1500 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
1501 in the correct order of the dimensions.
1502 (gen_ctf_subrange_type): Refactor out handling of
1503 DW_TAG_subrange_type DIE to here.
1505 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1507 PR sanitizer/97696
1508 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
1510 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1512 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
1513 and luti_strided.
1514 * config/aarch64/aarch64-sme.md
1515 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
1516 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
1517 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
1518 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
1519 (early_ra::maybe_convert_to_strided_access): Remove support for
1520 strided LUTI2 and LUTI4.
1522 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
1524 PR target/113510
1525 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
1526 low_register_operand.
1528 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
1530 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
1531 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
1532 to "X = Y, X o= CST".
1534 2024-03-05 Xi Ruoyao <xry111@xry111.site>
1536 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
1537 s9 as an alias of r22.
1539 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
1541 * config/avr/avr-protos.h (avr_out_insv): New proto.
1542 * config/avr/avr.cc (avr_out_insv): New function.
1543 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
1544 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
1545 * config/avr/avr.md (define_attr "adjust_len") Add insv.
1546 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
1547 Add constraint alternative where the 3rd operand is a power
1548 of 2, and the source register may differ from the destination.
1549 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
1550 instructions. Set attr "length" to "insv".
1551 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
1553 2024-03-05 Richard Biener <rguenther@suse.de>
1555 PR tree-optimization/114231
1556 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
1557 processing a BB SLP root.
1559 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1561 PR rtl-optimization/114211
1562 * lower-subreg.cc (resolve_simple_move): For double-word
1563 rotates by BITS_PER_WORD if there is overlap between source
1564 and destination use a temporary.
1566 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1568 PR middle-end/114157
1569 * gimple-lower-bitint.cc: Include stor-layout.h.
1570 (mergeable_op): Return true for BIT_FIELD_REF.
1571 (struct bitint_large_huge): Declare handle_bit_field_ref method.
1572 (bitint_large_huge::handle_bit_field_ref): New method.
1573 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
1575 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1577 PR target/114116
1578 * config/i386/i386.h (enum call_saved_registers_type): Add
1579 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
1580 * config/i386/i386-options.cc (ix86_set_func_type): Remove
1581 has_no_callee_saved_registers variable, add no_callee_saved_registers
1582 instead, initialize it depending on whether it is
1583 no_callee_saved_registers function or not. Don't set it if
1584 no_caller_saved_registers attribute is present. Adjust users.
1585 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
1586 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
1587 TYPE_NO_CALLEE_SAVED_REGISTERS.
1588 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
1590 2024-03-05 Pan Li <pan2.li@intel.com>
1592 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
1593 mode_size related code.
1595 2024-03-05 Patrick Palka <ppalka@redhat.com>
1597 * doc/invoke.texi (-Wno-global-module): Document.
1599 2024-03-04 David Faust <david.faust@oracle.com>
1601 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
1602 * config/bpf/bpf.cc (bpf_expand_setmem): New.
1603 * config/bpf/bpf.md (setmemdi): New define_expand.
1605 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1607 PR rtl-optimization/113010
1608 * combine.cc (simplify_comparison): Guard the
1609 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
1610 and initialize inner_mode.
1612 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1614 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1615 VMLALDAVAXQ_U cases.
1616 (VMLALDAVXQ): Remove iterator.
1617 (VMLALDAVXQ_P): Likewise.
1618 (VMLALDAVAXQ): Likewise.
1619 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
1620 mode iterator attribute with V4BI mode.
1621 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1622 VMLALDAVAXQ_U): Remove unused unspecs.
1624 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1626 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
1627 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
1628 attribute.
1629 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
1630 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
1631 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
1632 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
1633 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
1634 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
1635 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
1636 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
1637 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
1638 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
1640 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1642 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
1643 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
1644 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
1645 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
1646 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
1647 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
1648 (arm_vcx1q<a>v16qi): Likewise.
1649 (arm_vcx1qav16qi): Likewise.
1650 (arm_vcx1qv16qi): Likewise.
1651 (arm_vcx2q<a>_p_v16qi): Likewise.
1652 (arm_vcx2q<a>v16qi): Likewise.
1653 (arm_vcx2qav16qi): Likewise.
1654 (arm_vcx2qv16qi): Likewise.
1655 (arm_vcx3q<a>_p_v16qi): Likewise.
1656 (arm_vcx3q<a>v16qi): Likewise.
1657 (arm_vcx3qav16qi): Likewise.
1658 (arm_vcx3qv16qi): Likewise.
1659 (@mve_<mve_insn>q_<supf><mode>): Likewise.
1660 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
1661 (@mve_<mve_insn>q_<supf>v4si): Likewise.
1662 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
1663 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
1664 (@mve_<mve_insn>q_f<mode>): Likewise.
1665 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
1666 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
1667 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
1668 (@mve_<mve_insn>q_m_f<mode>): Likewise.
1669 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
1670 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
1671 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
1672 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
1673 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
1674 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
1675 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
1676 (mve_v<absneg_str>q_f<mode>): Likewise.
1677 (mve_<mve_addsubmul>q<mode>): Likewise.
1678 (mve_<mve_addsubmul>q_f<mode>): Likewise.
1679 (mve_vadciq_<supf>v4si): Likewise.
1680 (mve_vadciq_m_<supf>v4si): Likewise.
1681 (mve_vadcq_<supf>v4si): Likewise.
1682 (mve_vadcq_m_<supf>v4si): Likewise.
1683 (mve_vandq_<supf><mode>): Likewise.
1684 (mve_vandq_f<mode>): Likewise.
1685 (mve_vandq_m_<supf><mode>): Likewise.
1686 (mve_vandq_m_f<mode>): Likewise.
1687 (mve_vandq_s<mode>): Likewise.
1688 (mve_vandq_u<mode>): Likewise.
1689 (mve_vbicq_<supf><mode>): Likewise.
1690 (mve_vbicq_f<mode>): Likewise.
1691 (mve_vbicq_m_<supf><mode>): Likewise.
1692 (mve_vbicq_m_f<mode>): Likewise.
1693 (mve_vbicq_m_n_<supf><mode>): Likewise.
1694 (mve_vbicq_n_<supf><mode>): Likewise.
1695 (mve_vbicq_s<mode>): Likewise.
1696 (mve_vbicq_u<mode>): Likewise.
1697 (@mve_vclzq_s<mode>): Likewise.
1698 (mve_vclzq_u<mode>): Likewise.
1699 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
1700 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
1701 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
1702 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
1703 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
1704 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
1705 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
1706 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
1707 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
1708 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
1709 (mve_vcvtaq_<supf><mode>): Likewise.
1710 (mve_vcvtaq_m_<supf><mode>): Likewise.
1711 (mve_vcvtbq_f16_f32v8hf): Likewise.
1712 (mve_vcvtbq_f32_f16v4sf): Likewise.
1713 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
1714 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
1715 (mve_vcvtmq_<supf><mode>): Likewise.
1716 (mve_vcvtmq_m_<supf><mode>): Likewise.
1717 (mve_vcvtnq_<supf><mode>): Likewise.
1718 (mve_vcvtnq_m_<supf><mode>): Likewise.
1719 (mve_vcvtpq_<supf><mode>): Likewise.
1720 (mve_vcvtpq_m_<supf><mode>): Likewise.
1721 (mve_vcvtq_from_f_<supf><mode>): Likewise.
1722 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
1723 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
1724 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
1725 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
1726 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
1727 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
1728 (mve_vcvtq_to_f_<supf><mode>): Likewise.
1729 (mve_vcvttq_f16_f32v8hf): Likewise.
1730 (mve_vcvttq_f32_f16v4sf): Likewise.
1731 (mve_vcvttq_m_f16_f32v8hf): Likewise.
1732 (mve_vcvttq_m_f32_f16v4sf): Likewise.
1733 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
1734 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
1735 (mve_veorq_s><mode>): Likewise.
1736 (mve_veorq_u><mode>): Likewise.
1737 (mve_veorq_f<mode>): Likewise.
1738 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
1739 (mve_vidupq_u<mode>_insn): Likewise.
1740 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
1741 (mve_viwdupq_wb_u<mode>_insn): Likewise.
1742 (mve_vldrbq_<supf><mode>): Likewise.
1743 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
1744 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
1745 (mve_vldrbq_z_<supf><mode>): Likewise.
1746 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
1747 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
1748 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
1749 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
1750 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
1751 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
1752 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
1753 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
1754 (mve_vldrhq_<supf><mode>): Likewise.
1755 (mve_vldrhq_fv8hf): Likewise.
1756 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
1757 (mve_vldrhq_gather_offset_fv8hf): Likewise.
1758 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
1759 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
1760 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
1761 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
1762 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
1763 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
1764 (mve_vldrhq_z_<supf><mode>): Likewise.
1765 (mve_vldrhq_z_fv8hf): Likewise.
1766 (mve_vldrwq_<supf>v4si): Likewise.
1767 (mve_vldrwq_fv4sf): Likewise.
1768 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
1769 (mve_vldrwq_gather_base_fv4sf): Likewise.
1770 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
1771 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
1772 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
1773 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
1774 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
1775 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
1776 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
1777 (mve_vldrwq_gather_offset_fv4sf): Likewise.
1778 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
1779 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
1780 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
1781 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
1782 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
1783 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
1784 (mve_vldrwq_z_<supf>v4si): Likewise.
1785 (mve_vldrwq_z_fv4sf): Likewise.
1786 (mve_vmvnq_s<mode>): Likewise.
1787 (mve_vmvnq_u<mode>): Likewise.
1788 (mve_vornq_<supf><mode>): Likewise.
1789 (mve_vornq_f<mode>): Likewise.
1790 (mve_vornq_m_<supf><mode>): Likewise.
1791 (mve_vornq_m_f<mode>): Likewise.
1792 (mve_vornq_s<mode>): Likewise.
1793 (mve_vornq_u<mode>): Likewise.
1794 (mve_vorrq_<supf><mode>): Likewise.
1795 (mve_vorrq_f<mode>): Likewise.
1796 (mve_vorrq_m_<supf><mode>): Likewise.
1797 (mve_vorrq_m_f<mode>): Likewise.
1798 (mve_vorrq_m_n_<supf><mode>): Likewise.
1799 (mve_vorrq_n_<supf><mode>): Likewise.
1800 (mve_vorrq_s<mode>): Likewise.
1801 (mve_vorrq_s<mode>): Likewise.
1802 (mve_vsbciq_<supf>v4si): Likewise.
1803 (mve_vsbciq_m_<supf>v4si): Likewise.
1804 (mve_vsbcq_<supf>v4si): Likewise.
1805 (mve_vsbcq_m_<supf>v4si): Likewise.
1806 (mve_vshlcq_<supf><mode>): Likewise.
1807 (mve_vshlcq_m_<supf><mode>): Likewise.
1808 (mve_vshrq_m_n_<supf><mode>): Likewise.
1809 (mve_vshrq_n_<supf><mode>): Likewise.
1810 (mve_vstrbq_<supf><mode>): Likewise.
1811 (mve_vstrbq_p_<supf><mode>): Likewise.
1812 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
1813 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
1814 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
1815 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
1816 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
1817 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
1818 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
1819 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
1820 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
1821 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
1822 (mve_vstrhq_<supf><mode>): Likewise.
1823 (mve_vstrhq_fv8hf): Likewise.
1824 (mve_vstrhq_p_<supf><mode>): Likewise.
1825 (mve_vstrhq_p_fv8hf): Likewise.
1826 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
1827 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
1828 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
1829 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
1830 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
1831 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
1832 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
1833 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
1834 (mve_vstrwq_<supf>v4si): Likewise.
1835 (mve_vstrwq_fv4sf): Likewise.
1836 (mve_vstrwq_p_<supf>v4si): Likewise.
1837 (mve_vstrwq_p_fv4sf): Likewise.
1838 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
1839 (mve_vstrwq_scatter_base_fv4sf): Likewise.
1840 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
1841 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
1842 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
1843 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
1844 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
1845 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
1846 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
1847 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
1848 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
1849 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
1850 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
1851 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
1852 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
1853 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
1855 2024-03-04 Marek Polacek <polacek@redhat.com>
1857 * doc/extend.texi: Update [[gnu::no_dangling]].
1859 2024-03-04 Andrew Stubbs <ams@baylibre.com>
1861 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
1862 * expr.cc (store_constructor): Likewise.
1863 (do_store_flag): Likewise.
1865 2024-03-04 Mark Wielaard <mark@klomp.org>
1867 * common.opt.urls: Regenerate.
1868 * config/avr/avr.opt.urls: Likewise.
1869 * config/i386/i386.opt.urls: Likewise.
1870 * config/pru/pru.opt.urls: Likewise.
1871 * config/riscv/riscv.opt.urls: Likewise.
1872 * config/rs6000/rs6000.opt.urls: Likewise.
1874 2024-03-04 Richard Biener <rguenther@suse.de>
1876 PR tree-optimization/114197
1877 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
1878 there are volatile bitfield accesses.
1879 (pass_if_conversion::execute): Throw away result if the
1880 if-converted and original loops are not nested as expected.
1882 2024-03-04 Richard Biener <rguenther@suse.de>
1884 PR tree-optimization/114164
1885 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
1886 the code generated for mask argument setup is not supported.
1888 2024-03-04 Richard Biener <rguenther@suse.de>
1890 PR tree-optimization/114203
1891 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
1892 adjustment before making the result defined at zero.
1894 2024-03-04 Richard Biener <rguenther@suse.de>
1896 PR tree-optimization/114192
1897 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
1898 appropriate def for the live out stmt in case of an alternate
1899 exit.
1901 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1903 PR middle-end/114209
1904 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
1905 unshare_expr when creating a MEM_REF from MEM_REF.
1906 (bitint_large_huge::lower_stmt): Call unshare_expr.
1908 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1910 PR target/114184
1911 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
1912 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
1913 register.
1915 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
1917 PR target/114187
1918 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
1919 lowpart_subreg to perform type conversion, to avoid confusion
1920 over the offset to use in the call to simplify_reg_subreg.
1922 2024-03-03 Greg McGary <gkm@rivosinc.com>
1924 PR rtl-optimization/113010
1925 * combine.cc (simplify_comparison): Simplify a SUBREG on
1926 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
1927 MEM load.
1929 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1931 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
1932 Use bool in place of int for boolean logic (if possible).
1933 Move declarations to definitions (if possible).
1934 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
1935 * config/avr/avr-dimode.md: Same.
1936 * config/avr/constraints.md: Same.
1937 * config/avr/predicates.md: Same.
1939 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
1941 PR target/113720
1942 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
1943 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
1944 simplify insn RTX using UMUL_HIGHPART rtx_code.
1945 (*umuldi3_highpart_const): Remove.
1947 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1949 PR target/114100
1950 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
1951 * config/avr/avr.cc (_reg_unused_after): Make static. And
1952 add 3rd argument to skip the current insn.
1953 (reg_unused_after): Adjust call of reg_unused_after.
1954 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
1955 unneeded frame pointer adjustments.
1957 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1959 PR target/92729
1960 * config/avr/avr.md (define_attr "cc"): Remove.
1961 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
1962 from prototype.
1963 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
1964 its uses. Add insn argument.
1965 (avr_out_plus_symbol): Remove pcc argument and its uses.
1966 (avr_out_plus): Remove pcc argument and its uses.
1967 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
1968 (avr_out_round): Adjust call of avr_out_plus.
1970 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1972 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
1973 from r14-9273.
1975 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
1977 PR target/101737
1978 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
1979 is not an insn, but e.g. a code label.
1981 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1983 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
1984 * config/avr/avr.cc: Use them instead of magic numbers when it
1985 means a register number.
1987 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1989 * config/avr/avr.cc: Adjust some comments.
1991 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1993 PR target/114100
1994 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
1995 the low part of the frame pointer with 8-bit stack pointer.
1997 2024-03-01 Patrick Palka <ppalka@redhat.com>
1999 PR c++/104919
2000 PR c++/106009
2001 * tree-inline.cc (remap_decl): Handle copy_decl returning the
2002 original decl.
2003 (remap_decls): Handle remap_decl returning the original decl.
2004 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
2005 CONST_DECL.
2007 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
2009 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
2010 type attribute.
2011 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
2012 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
2013 (movhi_internal, movqi_internal): Likewise.
2014 (movsf_softfloat, movsf_hardfloat): Likewise.
2015 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
2016 (movdf_softfloat): Likewise.
2018 2024-03-01 Marek Polacek <polacek@redhat.com>
2020 PR c++/110358
2021 PR c++/109642
2022 * doc/extend.texi: Document gnu::no_dangling.
2023 * doc/invoke.texi: Mention that gnu::no_dangling disables
2024 -Wdangling-reference.
2026 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
2028 * config/avr/avr.opt: Overhaul help screen.
2030 2024-03-01 Jakub Jelinek <jakub@redhat.com>
2031 Tobias Burnus <tburnus@baylibre.com>
2033 PR c++/110347
2034 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
2035 lang_hooks.decls.omp_disregard_value_expr for
2036 (first)private in target regions.
2038 2024-03-01 Jakub Jelinek <jakub@redhat.com>
2040 PR middle-end/114136
2041 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
2042 n_named_args initially before INIT_CUMULATIVE_ARGS to
2043 structure_value_addr_parm rather than 0, after it don't modify
2044 it if strict_argument_naming and clear only if
2045 !pretend_outgoing_varargs_named.
2047 2024-03-01 Jakub Jelinek <jakub@redhat.com>
2049 PR debug/114015
2050 * dwarf2out.cc (should_move_die_to_comdat): Return false for
2051 aggregates without DW_AT_byte_size attribute or with non-constant
2052 DW_AT_byte_size.
2054 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
2056 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
2057 valid values for level.
2059 2024-03-01 Richard Biener <rguenther@suse.de>
2061 PR middle-end/114070
2062 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
2063 Allow the folding if before lowering and the current IL
2064 isn't supported with vcond_mask.
2066 2024-03-01 xuli <xuli1@eswincomputing.com>
2068 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
2069 attribute to riscv_attribute_table.
2070 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
2071 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
2072 * doc/extend.texi: Add riscv_vector_cc attribute description.
2074 2024-03-01 Pan Li <pan2.li@intel.com>
2076 PR target/112817
2077 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
2078 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
2079 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
2080 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
2081 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
2082 comments for option replacement.
2083 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
2084 riscv_autovec_preference to rvv_vector_bits.
2085 (vls_mode_valid_p): Ditto.
2086 (estimated_poly_value): Ditto.
2087 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
2088 vector chunks and honor new option mrvv-vector-bits.
2089 (riscv_override_options_internal): Update comments and rename the
2090 vector chunks.
2091 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
2092 internal option param=riscv-autovec-preference.
2094 2024-03-01 Jakub Jelinek <jakub@redhat.com>
2096 * function.cc (assign_parms): Only call assign_parms_setup_varargs
2097 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
2099 2024-03-01 Jakub Jelinek <jakub@redhat.com>
2101 PR middle-end/114156
2102 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
2103 rhs1 of a VCE to have no underlying variable if it is a load and
2104 handle that case.
2106 2024-02-29 David Malcolm <dmalcolm@redhat.com>
2108 PR analyzer/114159
2109 * function.cc (function_name): Make param const.
2110 * function.h (function_name): Likewise.
2112 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
2114 PR target/114100
2115 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
2116 * config/avr/avr.opt (-mfuse-add=): New target option.
2117 * common/config/avr/avr-common.cc (avr_option_optimization_table)
2118 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
2119 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
2120 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
2121 * config/avr/avr-protos.h (avr_split_tiny_move)
2122 (make_avr_pass_fuse_add): New protos.
2123 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
2124 avr_split_tiny_move to split indirect memory accesses.
2125 (gen_move_clobbercc): New define_expand helper.
2126 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
2127 (avr_pass_fuse_add): New class from rtl_opt_pass.
2128 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
2129 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
2130 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
2131 of PLUS addressing for AVR_TINY.
2132 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
2133 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
2134 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
2136 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
2138 PR target/114132
2139 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
2140 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
2141 (avr_function_arg): Set it.
2142 (avr_frame_pointer_required_p): Use it instead of .nregs.
2144 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
2146 PR target/108174
2147 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
2148 static and mark with GTY.
2150 2024-02-29 Xi Ruoyao <xry111@xry111.site>
2152 * config/loongarch/loongarch.md
2153 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
2155 2024-02-29 Xi Ruoyao <xry111@xry111.site>
2157 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
2158 (crc): New define_int_attr.
2159 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
2160 into ...
2161 (loongarch_<crc>_w_<size>_w): ... here.
2163 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
2165 PR target/114130
2166 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
2167 extend the expected value if needed.
2169 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2171 * config.gcc (target_gtfiles): Change coreout to btfext-out.
2172 (extra_objs): Change coreout to btfext-out.
2173 * config/bpf/coreout.cc: Rename to btfext-out.cc.
2174 * config/bpf/btfext-out.cc: Add.
2175 * config/bpf/coreout.h: Rename to btfext-out.h.
2176 * config/bpf/btfext-out.h: Add.
2177 * config/bpf/core-builtins.cc: Change include.
2178 * config/bpf/core-builtins.h: Change include.
2179 * config/bpf/t-bpf: Accomodate renamed files.
2181 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2183 PR target/113453
2184 * config/bpf/bpf.cc (bpf_function_prologue): Define target
2185 hook.
2186 * config/bpf/coreout.cc (brf_ext_info_section)
2187 (btf_ext_info): Move from coreout.h
2188 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
2189 (bpf_core_reloc): Rename to btf_ext_core_reloc.
2190 (btf_ext): Add static variable.
2191 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
2192 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
2193 (btf_ext_add_string, btf_funcinfo_type_callback)
2194 (btf_add_func_info_for, btf_validate_funcinfo)
2195 (btf_ext_info_len, output_btfext_func_info): Add function.
2196 (output_btfext_header, bpf_core_reloc_add)
2197 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
2198 Change to support new structs.
2199 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
2200 Move and change in coreout.cc.
2201 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
2203 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2205 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
2206 enabled by default for BPF.
2207 (bpf_file_end): Call BTF deallocation.
2208 (bpf_asm_init_sections): Correct condition.
2209 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
2210 deallocation.
2211 (ctf_debuf_finish): Correct condition for calling
2212 ctf_debug_finalize.
2214 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2216 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
2217 (traverse_btf_func_types): Define function.
2218 * ctfc.h (funcs_traverse_callback): Typedef for function
2219 prototype.
2220 (traverse_btf_func_types): Add prototype.
2222 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2224 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
2226 2024-02-28 Richard Biener <rguenther@suse.de>
2228 PR tree-optimization/113831
2229 PR tree-optimization/108355
2230 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
2231 PR113831 fix.
2233 2024-02-28 Richard Biener <rguenther@suse.de>
2235 PR tree-optimization/114121
2236 * tree-ssa-sccvn.h (vn_reference_s::offset,
2237 vn_reference_s::max_size): New fields.
2238 (vn_reference_insert_pieces): Adjust prototype.
2239 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
2240 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
2241 size, allow using "don't know" state.
2242 (vn_walk_cb_data::finish): Pass along offset/max_size.
2243 (vn_reference_lookup_or_insert_for_pieces): Take offset and
2244 max_size as argument and use it.
2245 (vn_reference_lookup_3): Properly adjust offset and max_size
2246 according to the adjusted ao_ref.
2247 (vn_reference_lookup_pieces): Initialize offset and max_size.
2248 (vn_reference_lookup): Likewise.
2249 (vn_reference_lookup_call): Likewise.
2250 (vn_reference_insert): Likewise.
2251 (visit_reference_op_call): Likewise.
2252 (vn_reference_insert_pieces): Take offset and max_size
2253 as argument and use it.
2255 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
2257 PR tree-optimization/114075
2258 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
2259 point vectors
2261 2024-02-28 Jakub Jelinek <jakub@redhat.com>
2263 PR tree-optimization/114041
2264 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
2265 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
2267 2024-02-28 Jakub Jelinek <jakub@redhat.com>
2269 PR tree-optimization/113988
2270 * stor-layout.h (bitwise_mode_for_size): Declare.
2271 * stor-layout.cc (bitwise_mode_for_size): New function.
2272 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
2273 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
2274 Use BITS_PER_UNIT instead of 8.
2276 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
2278 PR target/113871
2279 * config/i386/mmx.md (V248FI): Add V2BF mode.
2280 (V24FI_32): Ditto.
2282 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
2284 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
2285 if either ref->offset is not byte aligned or ref->size is not known
2286 to be equal to ref->max_size.
2287 (maybe_trim_complex_store): Fix description.
2288 (maybe_trim_constructor_store): Likewise.
2289 (maybe_trim_partially_dead_store): Likewise.
2291 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
2293 * config/arm/mmintrin.h: Warn if this header is included without
2294 defining __ENABLE_DEPRECATED_IWMMXT.
2296 2024-02-27 Richard Biener <rguenther@suse.de>
2298 PR tree-optimization/114074
2299 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
2300 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
2301 Handle poly vs. non-poly multiplication correctly with respect
2302 to undefined behavior on overflow.
2304 2024-02-27 Jakub Jelinek <jakub@redhat.com>
2306 PR rtl-optimization/114044
2307 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
2308 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
2309 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
2310 expand_PARITY): Declare.
2311 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
2312 expand_CTZ, expand_FFS, expand_PARITY): New functions.
2313 (expand_POPCOUNT): Use expand_bitquery.
2315 2024-02-27 Richard Biener <rguenther@suse.de>
2317 PR tree-optimization/114081
2318 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2319 Perform manual dominator update for prologue peeling.
2320 (vect_do_peeling): Properly update dominators after adding the
2321 prologue-around guard.
2323 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
2325 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
2326 (mstrict-X): Tag as "Optimization".
2328 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
2330 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
2331 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
2333 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2334 H.J. Lu <hjl.tools@gmail.com>
2336 PR rtl-optimization/113617
2337 * varasm.cc (default_elf_select_rtx_section): For
2338 references to private symbols in comdat sections
2339 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
2340 or .rodata.<comdat> comdat sections.
2342 2024-02-26 Richard Biener <rguenther@suse.de>
2344 PR tree-optimization/114099
2345 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2346 Create and fill in a needed virtual LC PHI for the alternate
2347 exits. Remove code dealing with that missing.
2349 2024-02-26 Richard Biener <rguenther@suse.de>
2351 PR tree-optimization/114068
2352 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
2353 New function.
2354 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
2355 on the main exit if needed. Remove band-aid for the case
2356 it was missing.
2358 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
2360 PR target/114097
2361 * config/i386/i386-options.cc (ix86_set_func_type): Check
2362 interrupt instead of noreturn attribute.
2364 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2366 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
2367 !TARGET_64BIT.
2369 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2371 PR tree-optimization/114090
2372 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
2373 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
2374 types.
2375 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
2377 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2379 PR middle-end/114084
2380 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
2381 if all subtrees of var0 come from one of the op0 or op1 operands
2382 and all subtrees of con0 come from the other one. Don't clear
2383 variables which are never used afterwards.
2385 2024-02-26 Richard Biener <rguenther@suse.de>
2387 PR middle-end/114070
2388 * genmatch.cc (parser::parse_c_expr): Do not record operand
2389 lists but only mark operators used.
2390 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
2391 Properly guard the case of tcc_comparison changing the VEC_COND
2392 value operand type.
2394 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2396 PR target/114094
2397 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
2398 to printed instruction.
2400 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
2402 PR target/114098
2403 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
2404 __builtin_ia32_ldtilecfg.
2405 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
2406 * config/i386/i386-builtin.def (BDESC): Add
2407 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
2408 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
2409 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
2410 * config/i386/i386.md (ldtilecfg): New pattern.
2411 (sttilecfg): Likewise.
2413 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
2415 PR tree-optimization/113205
2416 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
2417 the proposed layout if it does not allow a source partition with
2418 layout 2 to keep that layout.
2420 2024-02-24 Jakub Jelinek <jakub@redhat.com>
2422 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
2423 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
2424 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
2425 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
2426 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
2427 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
2428 macros.
2429 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
2430 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
2431 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
2432 HOST_WIDE_INT_UC macros.
2433 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
2434 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
2435 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
2436 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
2437 macros.
2438 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
2439 * config/i386/constraints.md (define_constraint "L"): Use
2440 HOST_WIDE_INT_C macro.
2441 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
2442 macro.
2443 (movl + movb peephole2): Likewise.
2444 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
2445 (const_32bit_mask): Likewise.
2447 2024-02-24 Jakub Jelinek <jakub@redhat.com>
2449 PR middle-end/114073
2450 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
2451 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
2452 types like vector or complex types.
2453 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
2454 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
2455 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
2457 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
2459 PR target/114028
2460 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
2461 Return false if inner mode is already Pmode.
2462 (rvv_builder::is_all_same_sequence): New function.
2463 (expand_vec_init): Emit broadcast if sequence is all same.
2465 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2467 PR target/113613
2468 * config/aarch64/aarch64-early-ra.cc
2469 (early_ra::m_current_region): New member variable.
2470 (early_ra::m_fpr_recency): Likewise.
2471 (early_ra::start_new_region): Bump m_current_region.
2472 (early_ra::allocate_colors): Prefer less recently used registers
2473 in the event of a tie. Add a comment to explain why we prefer(ed)
2474 higher-numbered registers.
2475 (early_ra::find_oldest_color): Prefer less recently used registers
2476 here too.
2477 (early_ra::finalize_allocation): Update recency information for
2478 allocated registers.
2479 (early_ra::process_blocks): Initialize m_current_region and
2480 m_fpr_recency.
2482 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2484 PR target/113295
2485 * config/aarch64/aarch64-early-ra.cc
2486 (early_ra::test_strictness): New enum.
2487 (early_ra::is_chain_candidate): Add a strictness parameter to
2488 control whether only correctness matters, or whether both correctness
2489 and heuristics should be used. Handle multiple levels of equivalence.
2490 (early_ra::find_related_start): Update call accordingly.
2491 (early_ra::strided_polarity_pref): Likewise.
2492 (early_ra::form_chains): Likewise.
2493 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
2494 correctness mode rather than trying to inline the test.
2496 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2498 PR target/113295
2499 * config/aarch64/aarch64-early-ra.cc
2500 (early_ra::find_related_start): Account for definitions by shared
2501 registers when testing for a single register definition.
2502 (early_ra::accumulate_defs): New function.
2503 (early_ra::record_copy): If A shares B's register, fold A's
2504 definition information into B's. Fold A's use information into B's.
2506 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
2508 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
2509 if R_X86_64_CODE_6_GOTTPOFF is supported.
2510 * config.in: Regenerated.
2511 * configure: Likewise.
2512 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
2513 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
2515 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
2517 PR target/108120
2518 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
2519 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
2521 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2523 PR rtl-optimization/114054
2524 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
2525 temp variable instead of target parameter for result.
2527 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2529 PR tree-optimization/114040
2530 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
2531 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
2532 probability from likely to unlikely. When handling the true true
2533 store, first cast to limb_access_type and then to l's type.
2535 2024-02-23 Richard Biener <rguenther@suse.de>
2537 PR target/90785
2538 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
2540 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2542 PR other/109668
2543 * config/riscv/arch-canonicalize: Move to python3
2544 * config/riscv/multilib-generator: Likewise
2546 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2548 * doc/invoke.texi: Document -mcpu.
2550 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
2552 * configure: Regenerate.
2553 * configure.ac: Add parameter "--fatal-warnings" to assemble
2554 when checking whether the assemble support conditional branch
2555 relaxation.
2557 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2559 PR c/114007
2560 * doc/extend.texi: (__extension__): Remove comments about scope
2561 tokens vs. two colons.
2563 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
2565 PR tree-optimization/109804
2566 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
2567 DEMANGLE_COMPONENT_UNNAMED_TYPE.
2569 2024-02-22 Richard Biener <rguenther@suse.de>
2571 PR tree-optimization/114048
2572 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
2573 can also produce -1 off.
2575 2024-02-22 Richard Biener <rguenther@suse.de>
2577 PR tree-optimization/114027
2578 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
2579 condition reduction classification only for single-element
2580 chains.
2582 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2584 PR ipa/111960
2585 * profile-count.h (profile_count::dump): Remove overload with
2586 char * first argument.
2587 * profile-count.cc (profile_count::dump): Change overload with char *
2588 first argument which uses sprintf into the overfload with FILE *
2589 first argument and use fprintf instead. Remove overload which wrapped
2590 it.
2592 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2594 PR tree-optimization/113993
2595 * tree-call-cdce.cc (get_no_error_domain): Handle
2596 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
2597 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
2598 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2599 the as the F128 suffixed cases, otherwise as non-suffixed ones.
2600 Handle BUILT_IN_{EXP,POW}10L for
2601 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2602 as (-inf, 4932).
2604 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2606 PR tree-optimization/114038
2607 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
2608 loop exit condition if end is divisible by limb_prec.
2610 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
2612 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
2613 problem of mabi=, mno-flush-func, mexplicit-relocs;
2614 add missing leading - of mbranch-cost option.
2615 * config/mips/mips.opt.urls: Regenerate.
2617 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
2619 PR target/109987
2620 * config/rs6000/constraints.md (we): Update internal doc without
2621 referring to option -mpower9-vector.
2622 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
2623 special handlings.
2624 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
2625 OTHER_P8_VECTOR_MASKS): Merge to ...
2626 (OTHER_VSX_VECTOR_MASKS): ... here.
2627 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
2628 some error message handlings and explicit option mask adjustments on
2629 explicit option power{8,9}-vector conflicting with other options.
2630 (rs6000_print_isa_options): Update comments.
2631 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
2632 related array items and handlings.
2633 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
2634 special handlings.
2635 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
2636 WarnRemoved.
2637 * doc/extend.texi: Remove documentation referring to option
2638 -mpower8-vector.
2639 * doc/invoke.texi: Remove documentation for option
2640 -mpower{8,9}-vector and adjust some documentation referring to them.
2641 * doc/md.texi: Update documentation for constraint we.
2642 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
2644 2024-02-22 Pan Li <pan2.li@intel.com>
2646 PR target/114017
2647 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
2648 the version to 0.12.
2650 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2652 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
2654 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2655 Robin Dapp <rdapp.gcc@gmail.com>
2657 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2658 (generic_ooo_vec_load): Ditto
2659 (generic_ooo_vec_store): Ditto
2660 (generic_ooo_vec_loadstore_seg): Ditto
2661 (generic_ooo_vec_alu): Ditto
2662 (generic_ooo_vec_fcmp): Ditto
2663 (generic_ooo_vec_imul): Ditto
2664 (generic_ooo_vec_fadd): Ditto
2665 (generic_ooo_vec_fmul): Ditto
2666 (generic_ooo_crypto): Ditto
2667 (generic_ooo_perm): Ditto
2668 (generic_ooo_vec_reduction): Ditto
2669 (generic_ooo_vec_ordered_reduction): Ditto
2670 (generic_ooo_vec_idiv): Ditto
2671 (generic_ooo_vec_float_divsqrt): Ditto
2672 (generic_ooo_vec_mask): Ditto
2673 (generic_ooo_vec_vesetvl): Ditto
2674 (generic_ooo_vec_setrm): Ditto
2675 (generic_ooo_vec_readlen): Ditto
2676 * config/riscv/riscv.md: Include generic-vector-ooo
2677 * config/riscv/generic-vector-ooo.md: New file. To here
2679 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2681 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2682 (generic_ooo_branch): Ditto
2683 * config/riscv/generic.md (generic_sfb_alu): Ditto
2684 (generic_fmul_half): Ditto
2685 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2686 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
2687 (sifive_7_popcount): Ditto
2688 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
2689 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
2690 * config/riscv/vector.md: Change rdfrm to fmove
2691 * config/riscv/zc.md: Change pushpop to load/store
2693 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
2695 * doc/invoke.texi (Warning Options): Fix typos.
2697 2024-02-21 David Faust <david.faust@oracle.com>
2699 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
2700 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
2701 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
2703 2024-02-21 Martin Jambor <mjambor@suse.cz>
2705 PR ipa/113476
2706 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
2707 initializers in the contructor.
2708 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
2709 * ipa-cp.h: New file.
2710 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
2711 (ipcp_value_source): Move to ipa-cp.h.
2712 (ipcp_value_base): Likewise.
2713 (ipcp_value): Likewise.
2714 (ipcp_lattice): Likewise.
2715 (ipcp_agg_lattice): Likewise.
2716 (ipcp_bits_lattice): Likewise.
2717 (ipcp_vr_lattice): Likewise.
2718 (ipcp_param_lattices): Likewise.
2719 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
2720 (ipa_value_from_jfunc): Adjust a check for empty lattices.
2721 (ipa_context_from_jfunc): Likewise.
2722 (ipa_agg_value_from_jfunc): Likewise.
2723 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
2724 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
2725 just in contiguous memory.
2726 (ipcp_store_vr_results): Adjust a check for empty lattices.
2727 * auto-profile.cc: Include sreal.h and ipa-cp.h.
2728 * cgraph.cc: Likewise.
2729 * cgraphclones.cc: Likewise.
2730 * cgraphunit.cc: Likewise.
2731 * config/aarch64/aarch64.cc: Likewise.
2732 * config/i386/i386-builtins.cc: Likewise.
2733 * config/i386/i386-expand.cc: Likewise.
2734 * config/i386/i386-features.cc: Likewise.
2735 * config/i386/i386-options.cc: Likewise.
2736 * config/i386/i386.cc: Likewise.
2737 * config/rs6000/rs6000.cc: Likewise.
2738 * config/s390/s390.cc: Likewise.
2739 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
2740 files to be included in gtype-desc.cc.
2741 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
2742 * ipa-devirt.cc: Likewise.
2743 * ipa-fnsummary.cc: Likewise.
2744 * ipa-icf.cc: Likewise.
2745 * ipa-inline-analysis.cc: Likewise.
2746 * ipa-inline-transform.cc: Likewise.
2747 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
2748 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
2749 * ipa-param-manipulation.cc: Likewise.
2750 * ipa-predicate.cc: Likewise.
2751 * ipa-profile.cc: Likewise.
2752 * ipa-prop.cc: Likewise.
2753 (ipa_node_params_t::duplicate): Assert new lattices remain empty
2754 instead of setting them to NULL.
2755 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
2756 * ipa-split.cc: Likewise.
2757 * ipa-sra.cc: Likewise.
2758 * ipa-strub.cc: Likewise.
2759 * ipa-utils.cc: Likewise.
2760 * ipa.cc: Likewise.
2761 * toplev.cc: Likewise.
2762 * tree-ssa-ccp.cc: Likewise.
2763 * tree-ssa-sccvn.cc: Likewise.
2764 * tree-vrp.cc: Likewise.
2766 2024-02-21 Tamar Christina <tamar.christina@arm.com>
2768 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
2769 Armv8.7-a.
2771 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2773 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2774 Use aarch64_gen_compare_zero_and_branch rather than emitting
2775 a CBZ directly.
2777 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2779 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
2780 Remove duplicated call.
2782 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2784 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
2785 Check that each individual piece of state is shared in the same
2786 way, rather than using an aggregate check for PSTATE.ZA.
2788 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2790 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2791 In the code that commits a lazy save, only zero ZA if the function
2792 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
2794 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2796 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
2797 directly inserting the associated sequence
2798 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2799 ...here instead.
2801 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2803 PR target/113995
2804 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
2805 fold the SVE allocation into the initial allocation if the
2806 initial allocation includes a VG save.
2808 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2810 PR target/113220
2811 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
2812 contain jumps even if called after initial RTL expansion.
2813 * mode-switching.cc: Include cfgbuild.h.
2814 (optimize_mode_switching): Allow the sequence returned by the
2815 emit hook to contain internal jumps. Record which blocks
2816 contain such jumps and split the blocks at the end.
2817 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
2818 non-debug insns when scanning the sequence.
2820 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
2822 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
2823 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
2825 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2827 * doc/invoke.texi (-mmcu): Add information about MCU specs.
2829 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2831 * doc/invoke.texi (-minrt): Clarify that main
2832 must take no arguments.
2834 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2836 * config/avr/builtins.def: Use function prototypes of given size
2837 and signedness.
2838 * config/avr/avr.cc (avr_init_builtins): Adjust types required
2839 by builtins.def.
2840 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
2842 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2844 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
2845 instead of @table.
2847 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
2849 * config/bpf/bpf.opt: Add help information for -mcpu.
2851 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
2853 PR target/113805
2854 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
2855 New pass.
2856 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
2857 Declare.
2858 * config/aarch64/aarch64.md (is_call): New attribute.
2859 (*and<mode>3nr_compare0): Rename to...
2860 (@aarch64_and<mode>3nr_compare0): ...this.
2861 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
2862 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
2863 * config/aarch64/aarch64-speculation.cc: Update file comment to
2864 describe the new late pass.
2865 (aarch64_do_track_speculation): Handle is_call insns like other calls.
2866 (pass_track_speculation): Add an is_late member variable.
2867 (pass_track_speculation::gate): Run the late pass for streaming-
2868 compatible functions and the early pass for other functions.
2869 (make_pass_track_speculation): Update accordingly.
2870 (make_pass_late_track_speculation): New function.
2871 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
2872 function.
2873 (aarch64_guard_switch_pstate_sm): Use it.
2875 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
2877 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
2878 Register these builtins with a pointer to uint64_t rather than unsigned
2879 DI mode.
2881 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2883 PR target/113615
2884 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
2885 Conditionalize on '!TARGET_RDNA2_PLUS'.
2886 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
2887 (gcn_expand_reduc_scalar):
2888 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
2890 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2892 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
2893 '__gfx90a__' target CPU definition. Add some safeguards for the future.
2895 2024-02-19 Richard Biener <rguenther@suse.de>
2897 PR rtl-optimization/54052
2898 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
2899 local defs by LR_OUT.
2901 2024-02-19 Jakub Jelinek <jakub@redhat.com>
2903 PR tree-optimization/113967
2904 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
2905 in condition that @rpos is multiple of vector element size.
2907 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2909 PR target/113696
2910 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
2911 Suppress vsetvl fusion.
2913 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
2915 PR target/113912
2916 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
2917 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
2918 (ix86_emit_save_regs): Don't generate push2 if
2919 ix86_can_use_push2pop2 return false.
2920 (ix86_expand_epilogue): Don't generate pop2 if
2921 ix86_can_use_push2pop2 return false.
2923 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2925 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
2926 Note on complete device support.
2928 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2930 * doc/extend.texi (AVR Function Attributes): Fuse description
2931 of "signal" and "interrupt" attribute. Link pseudo instruction.
2933 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2935 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
2936 symbol type conversions.
2937 (__cacop_d): Likewise.
2938 (__cpucfg): Likewise.
2939 (__asrtle_d): Likewise.
2940 (__asrtgt_d): Likewise.
2941 (__lddir_d): Likewise.
2942 (__ldpte_d): Likewise.
2943 (__crc_w_b_w): Likewise.
2944 (__crc_w_h_w): Likewise.
2945 (__crc_w_w_w): Likewise.
2946 (__crc_w_d_w): Likewise.
2947 (__crcc_w_b_w): Likewise.
2948 (__crcc_w_h_w): Likewise.
2949 (__crcc_w_w_w): Likewise.
2950 (__crcc_w_d_w): Likewise.
2951 (__csrrd_w): Likewise.
2952 (__csrwr_w): Likewise.
2953 (__csrxchg_w): Likewise.
2954 (__csrrd_d): Likewise.
2955 (__csrwr_d): Likewise.
2956 (__csrxchg_d): Likewise.
2957 (__iocsrrd_b): Likewise.
2958 (__iocsrrd_h): Likewise.
2959 (__iocsrrd_w): Likewise.
2960 (__iocsrrd_d): Likewise.
2961 (__iocsrwr_b): Likewise.
2962 (__iocsrwr_h): Likewise.
2963 (__iocsrwr_w): Likewise.
2964 (__iocsrwr_d): Likewise.
2965 (__frecipe_s): Likewise.
2966 (__frecipe_d): Likewise.
2967 (__frsqrte_s): Likewise.
2968 (__frsqrte_d): Likewise.
2970 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2972 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
2973 function return value type to unsigned short.
2975 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
2977 * doc/sourcebuild.texi: add scan-assembler-bound
2979 2024-02-16 Jason Merrill <jason@redhat.com>
2981 * gdbhooks.py: Fix regex syntax.
2983 2024-02-16 Richard Biener <rguenther@suse.de>
2985 PR tree-optimization/113895
2986 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
2987 consistency checking when there are out-of-bound array
2988 accesses. Allow -1 off when from an array reference with
2989 constant index.
2991 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2993 PR target/106543
2994 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
2995 pattern.
2997 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2999 * doc/sourcebuild.texi (Effective-Target Keywords, Other
3000 attribugs): Document linker_plugin.
3001 (Require Support): Document dg-require-linker-plugin.
3003 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
3005 PR target/109349
3006 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
3007 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
3008 (RISCV_MINOR_VERSION_BASE): Ditto.
3009 (RISCV_REVISION_VERSION_BASE): Ditto.
3010 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
3011 rather than magic number.
3012 * config/riscv/riscv.h (riscv_arch_help): New.
3013 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
3014 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
3015 --print-supported-extensions.
3016 * config/riscv/riscv.opt (march=help): New.
3017 (print-supported-extensions): New.
3018 (-print-supported-extensions): New.
3019 * doc/invoke.texi (RISC-V Options): Document -march=help.
3021 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
3023 PR target/113780
3024 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
3025 for indirect calls with 4 or more arguments in pac-enabled functions.
3027 2024-02-15 David Faust <david.faust@oracle.com>
3029 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
3030 use ldxb instead of ldxh.
3032 2024-02-15 Jakub Jelinek <jakub@redhat.com>
3034 PR middle-end/113921
3035 * cfgrtl.h (prepend_insn_to_edge): New declaration.
3036 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
3037 comment.
3038 (prepend_insn_to_edge): New function.
3039 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
3040 insert_insn_on_edge.
3042 2024-02-15 Richard Biener <rguenther@suse.de>
3044 PR tree-optimization/111156
3045 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
3046 at the pattern stmt if any.
3048 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
3050 PR target/113927
3051 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
3052 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
3053 * config/avr/avr.cc (avr_adiw_reg_p): New function.
3054 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
3055 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
3056 * config/avr/avr.md: Same.
3057 (attr "isa") <tiny, no_tiny>: Remove.
3058 <adiw, no_adiw>: Add.
3059 (define_insn, define_insn_and_split): When an alternative has
3060 constraint "w", then set attribute "isa" to "adiw".
3061 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
3062 Built-in define __AVR_HAVE_ADIW__.
3063 * doc/invoke.texi (AVR Options): Document it.
3065 2024-02-15 Andrew Stubbs <ams@baylibre.com>
3067 * config/gcn/gcn-valu.md
3068 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
3069 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
3070 details are supported on RDNA devices.
3072 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
3074 PR middle-end/113508
3075 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
3076 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
3077 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
3078 Add sentence about what the mode m is.
3080 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
3082 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
3083 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
3084 var.
3086 2024-02-15 Richard Biener <rguenther@suse.de>
3088 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
3089 stmts.
3091 2024-02-15 Jakub Jelinek <jakub@redhat.com>
3093 PR tree-optimization/113567
3094 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
3095 _BitInt multiplication, division or modulo with
3096 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
3097 force the affected inputs into a new SSA_NAME.
3099 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
3101 PR target/113871
3102 * config/i386/mmx.md (V248FI): New mode iterator.
3103 (V24FI_32): DItto.
3104 (vec_shl_<V248FI:mode>): New expander.
3105 (vec_shl_<V24FI_32:mode>): Ditto.
3106 (vec_shr_<V248FI:mode>): Ditto.
3107 (vec_shr_<V24FI_32:mode>): Ditto.
3108 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
3109 (vec_shr_<V248FI:mode>): Ditto.
3111 2024-02-14 Jan Hubicka <jh@suse.cz>
3113 PR tree-optimization/111054
3114 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
3116 2024-02-14 Tamar Christina <tamar.christina@arm.com>
3118 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
3120 2024-02-14 Richard Biener <rguenther@suse.de>
3122 PR tree-optimization/113910
3123 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
3124 the hashval_t hash.
3126 2024-02-14 Jakub Jelinek <jakub@redhat.com>
3128 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
3129 (pp_integer_with_precision): For unsigned ptrdiff_t printing
3130 with u, o or x print ptrdiff_t argument converted to
3131 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
3133 2024-02-14 Richard Biener <rguenther@suse.de>
3135 PR middle-end/113576
3136 * expr.cc (do_store_flag): For vector bool compares of vectors
3137 with padding zero that.
3138 * dojump.cc (do_compare_and_jump): Likewise.
3140 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
3142 * doc/install.texi (Prerequisites): Update gettext link.
3144 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
3146 PR target/113876
3147 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
3148 Return false if the incoming stack isn't 16-byte aligned.
3150 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
3152 PR middle-end/113904
3153 * omp-general.cc (struct omp_ts_info): Update for splitting of
3154 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
3155 * omp-selectors.h (enum omp_tp_type): Replace
3156 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
3158 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
3160 PR target/113742
3161 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
3162 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
3164 2024-02-13 Richard Biener <rguenther@suse.de>
3166 PR tree-optimization/113895
3167 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
3168 offset to discover constant array indices in bits, handle
3169 COMPONENT_REF to bitfields.
3171 2024-02-13 Richard Biener <rguenther@suse.de>
3173 PR tree-optimization/113831
3174 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
3175 typo in comment.
3177 2024-02-13 Richard Biener <rguenther@suse.de>
3179 PR tree-optimization/113902
3180 * tree-vect-loop.cc (move_early_exit_stmts): Track
3181 last_seen_vuse for VUSE updating.
3183 2024-02-13 Tamar Christina <tamar.christina@arm.com>
3185 PR tree-optimization/113734
3186 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
3187 an early break loop as partial.
3189 2024-02-13 Richard Biener <rguenther@suse.de>
3191 PR tree-optimization/113898
3192 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
3193 missing accumulated off adjustment.
3195 2024-02-13 Jakub Jelinek <jakub@redhat.com>
3197 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
3198 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
3199 it against UINT_MAX and ULONG_MAX.
3201 2024-02-13 David Malcolm <dmalcolm@redhat.com>
3203 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
3204 to...
3205 (emit_diagnostic_valist_meta): ...this.
3206 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
3207 (emit_diagnostic_valist_meta): ...this.
3209 2024-02-12 Jakub Jelinek <jakub@redhat.com>
3211 PR tree-optimization/113849
3212 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
3213 fast path for widening casts where !m_upwards_2limb and lhs_type
3214 has precision which is a multiple of limb_prec.
3216 2024-02-12 Jakub Jelinek <jakub@redhat.com>
3218 PR c++/113674
3219 * attribs.cc (extract_attribute_substring): Remove.
3220 (lookup_scoped_attribute_spec): Don't call it.
3222 2024-02-12 Jakub Jelinek <jakub@redhat.com>
3224 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
3225 and cast to fmt_size_t instead of %lu and cast to unsigned long.
3227 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
3229 * Makefile.in: Add no-info dependency.
3230 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
3231 available.
3232 * configure: Regenerate.
3234 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
3236 PR target/113855
3237 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
3238 available to all sub-targets.
3239 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
3240 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
3242 2024-02-12 Richard Biener <rguenther@suse.de>
3244 PR tree-optimization/113831
3245 PR tree-optimization/108355
3246 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
3247 we see variable array indices and get_ref_base_and_extent
3248 can resolve those to constants fix up the ops to constants
3249 as well.
3250 (ao_ref_init_from_vn_reference): Use 'off' member for
3251 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
3252 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
3254 2024-02-12 Pan Li <pan2.li@intel.com>
3256 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
3257 Replace args to arguments for misspelled term.
3259 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
3261 PR target/112944
3262 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
3263 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
3264 when not linked with -mrodata-in-ram.
3266 2024-02-12 Richard Biener <rguenther@suse.de>
3268 PR tree-optimization/113863
3269 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3270 Record crossed virtual PHIs.
3271 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
3272 virtual PHIs.
3274 2024-02-10 Marek Polacek <polacek@redhat.com>
3276 DR 2237
3277 PR c++/107126
3278 PR c++/97202
3279 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
3281 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3283 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
3284 computation of idx for i == 4 of bitint_prec_huge.
3286 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3288 PR middle-end/110754
3289 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
3290 decls create PARM_DECL with pointer to original type, set
3291 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
3292 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
3293 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
3294 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
3295 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
3296 of the var as argument.
3298 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3300 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
3301 size_t and precision 4 for ptrdiff_t. Formatting fix.
3302 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
3303 Formatting fixes.
3304 (test_pp_format): Test t and z modifiers.
3305 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
3307 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3309 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
3310 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
3311 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3312 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
3313 and casts to fmt_size_t instead of "%ld" and casts to long.
3314 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
3315 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
3316 instead of "%lu" and casts to unsigned long.
3317 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
3318 unsigned long.
3319 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3320 and casts to fmt_size_t instead of "%ld" and casts to long.
3321 * cfgexpand.cc (dump_stack_var_partition): Use
3322 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
3323 and casts to unsigned long.
3324 * gengtype.cc (adjust_field_rtx_def): Likewise.
3325 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3326 and casts to fmt_size_t instead of "%ld" and casts to long.
3327 * postreload-gcse.cc (dump_hash_table): Likewise.
3328 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
3329 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3330 (ggc_internal_alloc, ggc_free): Likewise.
3331 * genpreds.cc (write_lookup_constraint_1): Likewise.
3332 (write_insn_constraint_len): Likewise.
3333 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
3334 and casts to fmt_size_t instead of "%ld" and casts to long.
3335 * varasm.cc (output_constant_pool_contents): Use
3336 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
3337 * var-tracking.cc (dump_var): Likewise.
3339 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3341 PR tree-optimization/113783
3342 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
3343 through VIEW_CONVERT_EXPR for final cast checks. Handle
3344 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
3345 INTEGER_TYPEs.
3346 (gimple_lower_bitint): Don't merge mergeable operations or other
3347 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
3348 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
3349 mode is BLKmode.
3351 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3353 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
3354 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
3355 HOST_SIZE_T_PRINT_HEX_PURE): Define.
3356 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
3357 fixes.
3359 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3361 PR middle-end/113415
3362 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
3363 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
3364 of hand written loop with emit_insn of copy_insn and emit original
3365 after_rtl_seq on the last edge.
3367 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3369 PR tree-optimization/113818
3370 * gimple-lower-bitint.cc (add_eh_edge): New function.
3371 (bitint_large_huge::handle_load,
3372 bitint_large_huge::lower_mergeable_stmt,
3373 bitint_large_huge::lower_muldiv_stmt): Use it.
3375 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3377 PR tree-optimization/113774
3378 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
3379 emit any comparison if m_first and low + 1 is equal to
3380 m_upwards_2limb, simplify condition for that. If not
3381 single_comparison, not m_first and we can prove that the idx <= low
3382 comparison will be always true, emit instead of idx <= low
3383 comparison low <= low such that cfg cleanup will optimize it at
3384 the end of the pass.
3386 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
3388 PR tree-optimization/113735
3389 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
3390 limit_check().
3392 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3394 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
3395 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
3397 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
3399 PR target/113711
3400 PR target/113733
3401 * config/i386/constraints.md: List all constraints with j prefix.
3402 (j>): Change auto-dec to auto-inc in documentation.
3403 (je): Changed to a memory constraint with APX NDD TLS operand
3404 check.
3405 (jM): New memory constraint for APX NDD instructions.
3406 (jO): Likewise.
3407 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
3408 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
3409 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
3410 (*add<mode>_1[SWI48]): Use je and jM.
3411 (addsi_1_zext): Use jM.
3412 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
3413 (*sub<mode>_1[SWI]): Use jM.
3414 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
3415 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
3416 (*and<dwi>3_doubleword): Likewise.
3417 (*anddi_1): Use jM.
3418 (*andsi_1_zext): Likewise.
3419 (*and<mode>_1[SWI24]): Likewise.
3420 (*<code><dwi>3_doubleword[any_or]): Use rjO
3421 (*code<mode>_1[any_or SWI248]): Use jM.
3422 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
3423 * config/i386/predicates.md (apx_ndd_memory_operand): New.
3424 (apx_ndd_add_memory_operand): Likewise.
3426 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3428 PR target/113824
3429 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
3430 * doc/avr-mmcu.texi: Rebuild.
3432 2024-02-08 Tamar Christina <tamar.christina@arm.com>
3434 PR tree-optimization/113808
3435 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
3436 value cross iterations.
3438 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3440 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
3441 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
3443 2024-02-08 Richard Biener <rguenther@suse.de>
3445 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3446 Revert last change to dr_may_alias_p.
3448 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3450 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
3451 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
3452 Remove spec asm_misc.
3453 * config/avr/specs.h: Same.
3455 2024-02-08 Pan Li <pan2.li@intel.com>
3457 PR target/113766
3458 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
3459 sure the c.arg_num is >= 2 before checking.
3460 (struct build_frm_base): Ditto.
3461 (struct narrow_alu_def): Ditto.
3463 2024-02-07 Richard Biener <rguenther@suse.de>
3465 PR tree-optimization/113796
3466 * tree-if-conv.cc (combine_blocks): Wipe range-info before
3467 replacing PHIs and inserting predicates.
3469 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
3470 Uros Bizjak <ubizjak@gmail.com>
3472 PR target/113690
3473 * config/i386/i386-features.cc (timode_convert_cst): New helper
3474 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
3475 CONST_VECTOR.
3476 (timode_scalar_chain::convert_op): Use timode_convert_cst.
3477 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
3478 Use timode_convert_cst.
3480 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
3482 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
3483 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
3484 (AARCH64_FL_DEBUGv8p9): Likewise.
3485 (AARCH64_FL_FGT2): Likewise.Likewise.
3486 (AARCH64_FL_ITE): Likewise.
3487 (AARCH64_FL_PFAR): Likewise.
3488 (AARCH64_FL_PMUv3_ICNTR): Likewise.
3489 (AARCH64_FL_PMUv3_SS): Likewise.
3490 (AARCH64_FL_PMUv3p9): Likewise.
3491 (AARCH64_FL_RASv2): Likewise.
3492 (AARCH64_FL_S1PIE): Likewise.
3493 (AARCH64_FL_S1POE): Likewise.
3494 (AARCH64_FL_S2PIE): Likewise.
3495 (AARCH64_FL_S2POE): Likewise.
3496 (AARCH64_FL_SCTLR2): Likewise.
3497 (AARCH64_FL_SEBEP): Likewise.
3498 (AARCH64_FL_SPE_FDS): Likewise.
3499 (AARCH64_FL_TCR2): Likewise.
3501 2024-02-07 Richard Biener <rguenther@suse.de>
3503 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3504 Only check whether reads are in-bound in places that are not safe.
3505 Fix dependence check. Add missing newline. Clarify comments.
3507 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3509 PR tree-optimization/113750
3510 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
3511 for single predecessor when doing early break vect.
3512 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
3513 after labels.
3515 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3517 PR tree-optimization/113731
3518 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
3519 method.
3520 * gimple-iterator.h (gsi_move_before): Default new param to
3521 GSI_SAME_STMT.
3522 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
3523 GSI_NEW_STMT.
3525 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3527 PR tree-optimization/113756
3528 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
3529 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
3530 of lh_bits value and mask.
3532 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3534 PR tree-optimization/113753
3535 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
3536 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
3537 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
3538 so that they start with r[half_blocks_needed] lowest bit. Fix up
3539 computation of top mask for SIGNED.
3541 2024-02-07 Pan Li <pan2.li@intel.com>
3543 PR target/113766
3544 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
3545 the signature of func.
3546 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
3547 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
3548 overloaded func with empty args error.
3550 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
3552 PR target/113689
3553 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
3554 R10_REG after sorry.
3556 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
3558 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
3559 Move before new caller, and add ".default" suffix.
3560 (get_suffixed_assembler_name): New.
3561 (make_resolver_func): Use get_suffixed_assembler_name.
3562 (aarch64_generate_version_dispatcher_body): Redo name mangling.
3564 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3566 PR target/113763
3567 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
3568 element from std::pair<unsigned int, char> to an unnamed struct.
3569 Adjust uses of tile range variable.
3571 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3573 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
3574 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
3576 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3578 PR sanitizer/110676
3579 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
3580 reset maxlen to sizetype maximum.
3582 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3584 PR tree-optimization/113736
3585 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
3586 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
3588 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3590 PR tree-optimization/113759
3591 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
3592 or from_unsignedN differs from properties of typeN, update typeN
3593 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
3594 uselessly convertible to typeN, convert it using fold_convert or
3595 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
3596 (convert_plusminus_to_widen): Likewise.
3598 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
3600 PR target/112577
3601 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
3602 vector structure modes correctly.
3604 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
3606 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
3607 warning.
3609 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
3611 PR target/113689
3612 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
3613 (x86_function_profiler): Call x86_64_select_profile_regnum to
3614 get a scratch register for large model profiling.
3616 2024-02-05 Richard Ball <richard.ball@arm.com>
3618 * config/arm/arm.cc (arm_output_mi_thunk): Emit
3619 insn for bti_c when bti is enabled.
3621 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3623 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
3624 neg.
3626 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3628 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
3629 (neg<mode>2): Change the mode iterator from MSA to IMSA because
3630 in FP arithmetic we cannot use (0 - x) for -x.
3631 (neg<mode>2): New define_insn to implement FP vector negation,
3632 using a bnegi instruction to negate the sign bit.
3634 2024-02-05 Richard Biener <rguenther@suse.de>
3636 PR tree-optimization/113707
3637 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
3638 checking the avail set treat out-of-region defines as
3639 available.
3641 2024-02-05 Richard Biener <rguenther@suse.de>
3643 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
3644 the default mode when building a pointer.
3646 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3648 PR tree-optimization/113737
3649 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
3650 has just a single label, remove it and make single successor edge
3651 EDGE_FALLTHRU.
3653 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3655 PR target/113059
3656 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
3657 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
3658 df_analyze call.
3660 2024-02-05 Richard Biener <rguenther@suse.de>
3662 PR target/113255
3663 * config/i386/i386-expand.cc
3664 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
3665 Use a new pseudo for the skipped number of bytes.
3667 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3669 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
3670 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
3671 sifive-p670.
3673 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3675 * config/riscv/riscv.md: Include sifive-p400.md.
3676 * config/riscv/sifive-p400.md: New file.
3677 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3678 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3679 Add sifive_p400.
3680 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
3681 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3682 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
3684 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3686 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
3687 Add missing ":SI" to the match_operator.
3689 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3691 * config/xtensa/xtensa.md (SHI): New mode iterator.
3692 (2 split patterns related to constsynth):
3693 Change to also accept HImode operands.
3695 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
3697 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
3698 similarly.
3700 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3702 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
3703 incorrect expand.
3704 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
3705 (elmsgnbit): Likewise.
3706 (neg<mode:FVEC>2): New define_insn.
3707 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
3708 are now instantiated in simd.md.
3710 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3712 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
3713 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
3714 MAX_MACHINE_MODE.
3716 2024-02-04 Li Wei <liwei@loongson.cn>
3718 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
3719 (loongarch_expand_vselect_vconcat): Ditto.
3720 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
3721 all 128-bit constant permutation situations.
3722 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
3723 (loongarch_is_imm_set_shuffle): Renamed function name.
3724 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
3725 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
3726 extract-even and extract-odd permutations.
3727 (loongarch_is_odd_extraction): Delete.
3728 (loongarch_is_even_extraction): Ditto.
3729 (loongarch_expand_vec_perm_const): Adjust.
3731 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3733 PR middle-end/113722
3734 * wide-int.cc (wi::bswap_large): Rename third argument from
3735 len to xlen and adjust use in safe_uhwi. Add len variable, set
3736 it to BLOCKS_NEEDED (precision) and use it for clearing of val
3737 and as canonize argument. Clear val using memset instead of
3738 a loop.
3740 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3742 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
3743 mmi.preferred_base + mmi.size - sizeof (void *).
3745 2024-02-03 Xi Ruoyao <xry111@xry111.site>
3747 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
3748 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
3749 the ODR-violating locale declaration.
3751 2024-02-02 Tamar Christina <tamar.christina@arm.com>
3753 PR tree-optimization/113588
3754 PR tree-optimization/113467
3755 * tree-vect-data-refs.cc
3756 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
3757 (vect_analyze_early_break_dependences): Update comments.
3759 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
3761 PR target/59778
3762 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
3763 and PA_BUILTIN_SET_FPSR builtins.
3764 * (pa_builtins_icode): Declare.
3765 * (def_builtin, pa_fpu_init_builtins): New.
3766 * (pa_init_builtins): Initialize FPU builtins.
3767 * (pa_builtin_decl, pa_expand_builtin_1): New.
3768 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
3769 PA_BUILTIN_SET_FPSR builtins.
3770 * (pa_atomic_assign_expand_fenv): New.
3771 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
3772 UNSPECV constants.
3773 (get_fpsr, put_fpsr): New expanders.
3774 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
3775 insn patterns.
3777 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3779 PR target/113697
3780 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
3782 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
3784 * doc/extend.texi (Common Type Attributes): Fix typo in
3785 description of hardbool.
3787 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3789 PR tree-optimization/113692
3790 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
3791 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
3792 final_cast_p.
3794 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3796 PR middle-end/113699
3797 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
3798 uninitialized large/huge _BitInt SSA_NAME inputs.
3800 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3802 PR middle-end/113705
3803 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
3804 around wi::to_wide in order to compare value in prec precision.
3806 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
3808 Revert:
3809 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3811 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3813 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3815 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3817 2024-02-02 Pan Li <pan2.li@intel.com>
3819 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
3820 (riscv_pass_by_reference): Ditto.
3821 (riscv_fntype_abi): Ditto.
3823 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3825 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
3826 (pre_vsetvl::cleaup): Remove vsetvl_pre.
3827 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
3829 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
3831 * config/loongarch/larchintrin.h
3832 (__frecipe_s): Update function return type.
3833 (__frecipe_d): Ditto.
3834 (__frsqrte_s): Ditto.
3835 (__frsqrte_d): Ditto.
3837 2024-02-02 Li Wei <liwei@loongson.cn>
3839 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
3840 (loongarch_vector_costs::add_stmt_cost): Adjust.
3842 2024-02-02 Xi Ruoyao <xry111@xry111.site>
3844 * config/loongarch/loongarch.md (unspec): Add
3845 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
3846 (la_pcrel64_two_parts): New define_insn.
3847 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
3848 typo in the comment.
3849 (loongarch_call_tls_get_addr): If -mcmodel=extreme
3850 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
3851 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
3852 note to allow CSE addressing __tls_get_addr.
3853 (loongarch_legitimize_tls_address): If -mcmodel=extreme
3854 -mexplicit-relocs={always,auto}, address TLS IE symbols with
3855 la_pcrel64_two_parts.
3856 (loongarch_split_symbol): If -mcmodel=extreme
3857 -mexplicit-relocs={always,auto}, address symbols with
3858 la_pcrel64_two_parts.
3859 (loongarch_output_mi_thunk): Clean up unreachable code. If
3860 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
3861 thunks with la_pcrel64_two_parts.
3863 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3865 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
3866 Add support for call36.
3868 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3870 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3871 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
3872 the macro instruction loading symbol address is not applicable.
3873 (loongarch_call_tls_get_addr): Adjust code.
3874 (loongarch_legitimize_tls_address): Likewise.
3876 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3878 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
3879 Add function declaration.
3880 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3881 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
3882 is not allowed
3883 (loongarch_load_tls): Added macro support in extreme mode.
3884 (loongarch_call_tls_get_addr): Likewise.
3885 (loongarch_legitimize_tls_address): Likewise.
3886 (loongarch_force_address): Likewise.
3887 (loongarch_legitimize_move): Likewise.
3888 (loongarch_output_mi_thunk): Likewise.
3889 (loongarch_option_override_internal): Remove the code that detects
3890 explicit relocs status.
3891 (loongarch_handle_model_attribute): Likewise.
3892 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
3893 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
3894 (symbolic_off64_or_reg_operand): Likewise.
3896 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3898 * config/loongarch/loongarch.cc (loongarch_load_tls):
3899 Load all types of tls symbols through one function.
3900 (loongarch_got_load_tls_gd): Delete.
3901 (loongarch_got_load_tls_ld): Delete.
3902 (loongarch_got_load_tls_ie): Delete.
3903 (loongarch_got_load_tls_le): Delete.
3904 (loongarch_call_tls_get_addr): Modify the called function name.
3905 (loongarch_legitimize_tls_address): Likewise.
3906 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
3907 (@load_tls<mode>): New template.
3908 (@got_load_tls_ld<mode>): Delete.
3909 (@got_load_tls_le<mode>): Delete.
3910 (@got_load_tls_ie<mode>): Delete.
3912 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3914 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
3915 (loongarch_legitimize_address): Add logical transformation code.
3917 2024-02-01 Marek Polacek <polacek@redhat.com>
3919 * doc/invoke.texi: Update -Wdangling-reference documentation.
3921 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
3923 PR target/113701
3924 * config/i386/i386.md (*cmp<dwi>_doubleword):
3925 Do not force SUBREG pieces to pseudos.
3927 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
3929 * config/pa/pa.md (atomic_storedi_1): Fix bug in
3930 alternative 1.
3932 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
3934 * config/avr/avr.cc: Tabify.
3936 2024-02-01 Richard Ball <richard.ball@arm.com>
3938 PR tree-optimization/111268
3939 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
3940 Add variable-length check for vector input arguments
3941 to a function.
3943 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3945 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
3946 hard-code number of SGPR/VGPR/AVGPR registers.
3947 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
3948 SGPR/VGPR/AVGPR registers.
3950 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3952 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
3953 attribute, and include sifive-p600.md.
3954 * config/riscv/generic-ooo.md: Update type attribute.
3955 * config/riscv/generic.md: Update type attribute.
3956 * config/riscv/sifive-7.md: Update type attribute.
3957 * config/riscv/sifive-p600.md: New file.
3958 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3959 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3960 Add sifive_p600.
3961 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
3962 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3963 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
3965 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3967 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
3968 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
3969 * config/riscv/riscv.opt: New macro for 7 new unprivileged
3970 extensions.
3971 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
3972 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
3974 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3976 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
3977 -static-libasan. Add missing whitespace.
3979 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3981 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
3982 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
3983 Don't 'define_constants'.
3985 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3987 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
3989 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3991 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
3992 [TARGET_RDNA3]: Adjust.
3994 2024-02-01 Richard Biener <rguenther@suse.de>
3996 PR tree-optimization/113693
3997 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
3998 data when available.
4000 2024-02-01 Jakub Jelinek <jakub@redhat.com>
4001 Jason Merrill <jason@redhat.com>
4003 PR c++/113531
4004 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
4005 on variables which were promoted to TREE_STATIC.
4007 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
4008 Richard Biener <rguenther@suse.de>
4010 PR target/113560
4011 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
4012 information via tree_non_zero_bits to check if this operand
4013 is suitably extended for a widening (or highpart) multiplication.
4014 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
4015 isn't already of the claimed type.
4017 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4019 Revert:
4020 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4022 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
4023 (generic_ooo_branch): ditto
4024 * config/riscv/generic.md (generic_sfb_alu): ditto
4025 (generic_fmul_half): ditto
4026 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
4027 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
4028 (sifive_7_popcount): ditto
4029 * config/riscv/vector.md: change rdfrm to fmove
4030 * config/riscv/zc.md: change pushpop to load/store
4032 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4034 Revert:
4035 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4036 Robin Dapp <rdapp.gcc@gmail.com>
4038 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
4039 (generic_ooo_vec_load): ditto
4040 (generic_ooo_vec_store): ditto
4041 (generic_ooo_vec_loadstore_seg): ditto
4042 (generic_ooo_vec_alu): ditto
4043 (generic_ooo_vec_fcmp): ditto
4044 (generic_ooo_vec_imul): ditto
4045 (generic_ooo_vec_fadd): ditto
4046 (generic_ooo_vec_fmul): ditto
4047 (generic_ooo_crypto): ditto
4048 (generic_ooo_perm): ditto
4049 (generic_ooo_vec_reduction): ditto
4050 (generic_ooo_vec_ordered_reduction): ditto
4051 (generic_ooo_vec_idiv): ditto
4052 (generic_ooo_vec_float_divsqrt): ditto
4053 (generic_ooo_vec_mask): ditto
4054 (generic_ooo_vec_vesetvl): ditto
4055 (generic_ooo_vec_setrm): ditto
4056 (generic_ooo_vec_readlen): ditto
4057 * config/riscv/riscv.md: include generic-vector-ooo
4058 * config/riscv/generic-vector-ooo.md: New file. to here
4060 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4062 Revert:
4063 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4065 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
4067 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4069 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
4071 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4072 Robin Dapp <rdapp.gcc@gmail.com>
4074 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
4075 (generic_ooo_vec_load): ditto
4076 (generic_ooo_vec_store): ditto
4077 (generic_ooo_vec_loadstore_seg): ditto
4078 (generic_ooo_vec_alu): ditto
4079 (generic_ooo_vec_fcmp): ditto
4080 (generic_ooo_vec_imul): ditto
4081 (generic_ooo_vec_fadd): ditto
4082 (generic_ooo_vec_fmul): ditto
4083 (generic_ooo_crypto): ditto
4084 (generic_ooo_perm): ditto
4085 (generic_ooo_vec_reduction): ditto
4086 (generic_ooo_vec_ordered_reduction): ditto
4087 (generic_ooo_vec_idiv): ditto
4088 (generic_ooo_vec_float_divsqrt): ditto
4089 (generic_ooo_vec_mask): ditto
4090 (generic_ooo_vec_vesetvl): ditto
4091 (generic_ooo_vec_setrm): ditto
4092 (generic_ooo_vec_readlen): ditto
4093 * config/riscv/riscv.md: include generic-vector-ooo
4094 * config/riscv/generic-vector-ooo.md: New file. to here
4096 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4098 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
4099 (generic_ooo_branch): ditto
4100 * config/riscv/generic.md (generic_sfb_alu): ditto
4101 (generic_fmul_half): ditto
4102 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
4103 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
4104 (sifive_7_popcount): ditto
4105 * config/riscv/vector.md: change rdfrm to fmove
4106 * config/riscv/zc.md: change pushpop to load/store
4108 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
4110 PR target/113657
4111 * config/aarch64/aarch64-simd.md (split for movv8di):
4112 For strict aligned mode, use DImode instead of TImode.
4114 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
4116 PR middle-end/113607
4117 * match.pd: Make sure else values match when folding a
4118 vec_cond into a conditional operation.
4120 2024-01-31 Marek Polacek <polacek@redhat.com>
4122 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
4124 2024-01-31 Tamar Christina <tamar.christina@arm.com>
4125 Matthew Malcomson <matthew.malcomson@arm.com>
4127 PR sanitizer/112644
4128 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
4129 memcmp.
4130 * builtins.cc (expand_builtin): Include HWASAN when checking for
4131 builtin inlining.
4133 2024-01-31 Richard Biener <rguenther@suse.de>
4135 PR middle-end/110176
4136 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
4137 to match INTEGER_CST only without outstanding conversion.
4139 2024-01-31 Alex Coplan <alex.coplan@arm.com>
4141 PR target/111677
4142 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
4143 V16QImode for the full 16-byte FPR saves in the vector PCS case.
4145 2024-01-31 Richard Biener <rguenther@suse.de>
4147 PR tree-optimization/111444
4148 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
4149 vn_reference_lookup_2 when optimistically skipping may-defs.
4151 2024-01-31 Richard Biener <rguenther@suse.de>
4153 PR tree-optimization/113630
4154 * tree-ssa-pre.cc (compute_avail): Avoid registering a
4155 reference with a representation with not matching base
4156 access size.
4158 2024-01-31 Jakub Jelinek <jakub@redhat.com>
4160 PR rtl-optimization/113656
4161 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
4162 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
4164 2024-01-31 Jakub Jelinek <jakub@redhat.com>
4166 PR debug/113637
4167 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
4168 with BLKmode are larger than DWARF2_ADDR_SIZE.
4170 2024-01-31 Jakub Jelinek <jakub@redhat.com>
4172 PR tree-optimization/113639
4173 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
4174 For VIEW_CONVERT_EXPR set rhs1 to its operand.
4176 2024-01-31 Richard Biener <rguenther@suse.de>
4178 PR tree-optimization/113670
4179 * tree-vect-data-refs.cc (vect_check_gather_scatter):
4180 Make sure we can take the address of the reference base.
4182 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
4184 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
4185 ATA5835, ATtiny64AUTO, ATA5700M322.
4186 * doc/avr-mmcu.texi: Rebuild.
4188 2024-01-31 Alexandre Oliva <oliva@adacore.com>
4190 PR debug/113394
4191 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
4192 caller.
4194 2024-01-31 Alexandre Oliva <oliva@adacore.com>
4196 PR middle-end/112917
4197 PR middle-end/113100
4198 * builtins.cc (expand_builtin_stack_address): Use
4199 STACK_ADDRESS_OFFSET.
4200 * doc/extend.texi (__builtin_stack_address): Adjust.
4201 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
4202 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
4203 * doc/tm.texi: Rebuilt.
4205 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4207 PR target/113495
4208 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
4209 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
4210 (pre_vsetvl::compute_transparent): New function.
4211 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
4213 2024-01-30 Fangrui Song <maskray@google.com>
4215 PR target/105576
4216 * config/i386/constraints.md: Define constraint "Ws".
4217 * doc/md.texi: Document it.
4219 2024-01-30 Marek Polacek <polacek@redhat.com>
4221 PR c++/110358
4222 PR c++/109640
4223 * doc/invoke.texi: Update -Wdangling-reference description.
4225 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
4227 * config/xtensa/constraints.md (R, T, U):
4228 Change define_constraint to define_memory_constraint.
4229 * config/xtensa/predicates.md (move_operand): Don't check that a
4230 constant pool operand size is a multiple of UNITS_PER_WORD.
4231 * config/xtensa/xtensa.cc
4232 (xtensa_lra_p, TARGET_LRA_P): Remove.
4233 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
4234 clause as it can no longer be true.
4235 (fixup_subreg_mem): Drop function.
4236 (xtensa_output_integer_literal_parts): Consider 16-bit wide
4237 constants.
4238 (xtensa_legitimate_constant_p): Add short-circuit path for
4239 integer load instructions. Don't check that mode size is
4240 at least UNITS_PER_WORD.
4241 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
4242 rather reload_in_progress and reload_completed.
4243 (doloop_end): Drop operand 2.
4244 (movhi_internal): Add alternative loading constant from a
4245 literal pool.
4246 (define_split for DI register_operand): Don't limit to
4247 !TARGET_AUTO_LITPOOLS.
4248 * config/xtensa/xtensa.opt (mlra): Change to no effect.
4250 2024-01-30 Pan Li <pan2.li@intel.com>
4252 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
4253 calculate the gpr count required by vls mode.
4254 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
4255 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
4256 for vls mode.
4257 (riscv_get_arg_info): Add vls mode handling.
4258 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
4260 2024-01-30 Richard Biener <rguenther@suse.de>
4262 PR tree-optimization/113659
4263 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4264 Handle main exit without virtual use.
4266 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
4268 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
4270 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
4272 PR libgcc/113403
4273 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
4274 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
4275 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
4276 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
4277 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
4278 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
4280 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
4282 PR target/113623
4283 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
4284 Mark all registers that occur in addresses as needing a GPR.
4286 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
4288 PR target/113636
4289 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
4290 the containing insn as an extra parameter. Reset debug instructions
4291 if they reference a register that is no longer used by real insns.
4292 (early_ra::apply_allocation): Update calls accordingly.
4294 2024-01-30 Jakub Jelinek <jakub@redhat.com>
4296 PR tree-optimization/113603
4297 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
4298 count_nonzero_bytes call refetch si using get_strinfo in case it
4299 has been unshared in the meantime.
4301 2024-01-30 Jakub Jelinek <jakub@redhat.com>
4303 PR middle-end/101195
4304 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
4305 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
4307 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
4309 * config/riscv/thead.cc (th_print_operand_address): Change %ld
4310 to %lld.
4312 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
4313 Manolis Tsamis <manolis.tsamis@vrull.eu>
4314 Philipp Tomsich <philipp.tomsich@vrull.eu>
4316 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
4317 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
4318 Likewise.
4319 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
4320 Call on framework moved later.
4322 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
4324 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
4325 instruction in naked function epilogues.
4327 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
4329 PR target/113655
4330 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
4331 gcc_cv_as_mips_explicit_relocs.
4332 * configure: Regnerated.
4334 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
4336 PR target/108933
4337 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
4338 Correct generated RTL.
4339 (arm_rev16si2_alt1): Correctly handle conditional execution.
4340 (arm_rev16si2_alt2): Likewise.
4342 2024-01-29 Richard Biener <rguenther@suse.de>
4344 PR middle-end/113622
4345 * expr.cc (expand_assignment): Spill hard registers if
4346 we index them with a variable offset.
4348 2024-01-29 Richard Biener <rguenther@suse.de>
4350 PR middle-end/113622
4351 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
4352 Also allow DECL_HARD_REGISTER variables.
4354 2024-01-29 Alex Coplan <alex.coplan@arm.com>
4356 PR target/113616
4357 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
4358 Use iterate_safely when iterating over debug uses.
4359 (fixup_debug_uses): Likewise.
4360 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
4361 over nondebug insns instead of manually maintaining the next insn.
4362 * iterator-utils.h (class safe_iterator): New.
4363 (iterate_safely): New.
4365 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
4367 PR target/38534
4368 * config/i386/i386-options.cc (ix86_set_func_type): Save
4369 callee-saved registers in noreturn functions for -O0/-Og.
4371 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4373 PR target/113615
4374 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
4375 define for !TARGET_RDNA2_PLUS.
4377 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
4379 PR target/113281
4380 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
4381 workaround for right shifts.
4382 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
4383 (vect_determine_precisions_from_range): Be more selective about
4384 which codes can be narrowed based on their input and output ranges.
4385 For shifts, require at least one more bit of precision than the
4386 maximum shift amount.
4388 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4390 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
4392 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4394 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
4395 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
4396 LLVM 13.0.1+.
4398 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4400 PR other/111966
4401 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
4402 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
4403 (SET_SRAM_ECC_UNSET): ... this.
4404 (copy_early_debug_info): Remove gfx900 special case, now handled as
4405 part of the generic handling.
4406 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
4408 2024-01-29 Jakub Jelinek <jakub@redhat.com>
4410 PR tree-optimization/110603
4411 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
4412 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
4413 overwritten anyway). Avoid creating invalid range with minlen
4414 larger than maxlen. Formatting fix.
4416 2024-01-29 Richard Biener <rguenther@suse.de>
4418 PR debug/103047
4419 * tree-inline.cc (initialize_inlined_parameters): Reverse
4420 the decl chain of inlined parameters.
4422 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
4424 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
4425 alignment of CFString constants by setting DECL_USER_ALIGN.
4427 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
4428 Jakub Jelinek <jakub@redhat.com>
4430 PR libgcc/113402
4431 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
4432 and BUILT_IN_GCC_NESTED_PTR_DELETED.
4433 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
4434 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
4435 rename the library fallbacks to __gcc_nested_func_ptr_created and
4436 __gcc_nested_func_ptr_deleted.
4437 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
4438 and __gcc_nested_func_ptr_deleted.
4439 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
4440 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
4441 * tree.cc (build_common_builtin_nodes): Build the
4442 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
4443 builtins only for non-explicit.
4445 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
4447 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
4449 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4451 PR target/38534
4452 * config/i386/i386-options.cc (ix86_set_func_type): Don't
4453 save and restore callee saved registers for a noreturn function
4454 with nothrow or compiled with -fno-exceptions.
4456 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4458 PR target/103503
4459 PR target/113312
4460 * config/i386/i386-expand.cc (ix86_expand_call): Replace
4461 no_caller_saved_registers check with call_saved_registers check.
4462 Clobber all registers that are not used by the callee with
4463 no_callee_saved_registers attribute.
4464 * config/i386/i386-options.cc (ix86_set_func_type): Set
4465 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
4466 noreturn function. Disallow no_callee_saved_registers with
4467 interrupt or no_caller_saved_registers attributes together.
4468 (ix86_set_current_function): Replace no_caller_saved_registers
4469 check with call_saved_registers check.
4470 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
4471 (ix86_handle_call_saved_registers_attribute): This.
4472 (ix86_gnu_attributes): Add
4473 ix86_handle_call_saved_registers_attribute.
4474 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
4475 no_caller_saved_registers check with call_saved_registers check.
4476 (ix86_function_ok_for_sibcall): Don't allow callee with
4477 no_callee_saved_registers attribute when the calling function
4478 has callee-saved registers.
4479 (ix86_comp_type_attributes): Also check
4480 no_callee_saved_registers.
4481 (ix86_epilogue_uses): Replace no_caller_saved_registers check
4482 with call_saved_registers check.
4483 (ix86_hard_regno_scratch_ok): Likewise.
4484 (ix86_save_reg): Replace no_caller_saved_registers check with
4485 call_saved_registers check. Don't save any registers for
4486 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
4487 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
4488 no_callee_saved_registers attribute is called.
4489 (find_drap_reg): Replace no_caller_saved_registers check with
4490 call_saved_registers check.
4491 * config/i386/i386.h (call_saved_registers_type): New enum.
4492 (machine_function): Replace no_caller_saved_registers with
4493 call_saved_registers.
4494 * doc/extend.texi: Document no_callee_saved_registers attribute.
4496 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4498 PR tree-optimization/113614
4499 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
4500 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
4501 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
4503 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4505 PR tree-optimization/113568
4506 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
4507 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
4508 in the widening extension checks.
4510 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4512 * gimple-lower-bitint.cc (gimple_lower_bitint): For
4513 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
4515 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
4517 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
4518 the warning for an attribute-always_inline without inline declaration.
4520 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
4522 PR other/113575
4523 * genopinit.cc (main): Split init_all_optabs into functions
4524 of 1000 patterns each.
4526 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4528 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
4529 TM_MULTILIB_CONFIG.
4530 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
4531 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
4532 -march/-mtune.
4534 2024-01-26 Andrew Stubbs <ams@baylibre.com>
4536 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
4537 * config/gcn/gcn-valu.md (all_convert): New iterator.
4538 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
4539 define_expand, and rename the old one to ...
4540 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
4541 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
4542 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
4543 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
4544 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
4545 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
4546 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
4547 (<u>mulqihi3_scalar): Likewise.
4549 2024-01-26 Richard Biener <rguenther@suse.de>
4551 PR tree-optimization/113602
4552 * tree-data-ref.cc (dr_analyze_innermost): Fail when
4553 the base object isn't addressable.
4555 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4557 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
4558 "--amdhsa-code-object-version=" argument.
4559 (ASM_SPEC): Use it; replace previous version of it.
4561 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4563 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
4564 (pre_vsetvl::emit_vsetvl): Ditto.
4566 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4568 * config/loongarch/lasx.md (vec_extract<mode>_0):
4569 New define_insn_and_split patten.
4571 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4573 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
4575 2024-01-26 Li Wei <liwei@loongson.cn>
4577 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
4579 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4581 PR target/113469
4582 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
4584 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
4586 PR target/100212
4587 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
4588 undefined shift after the call to exact_log2.
4590 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
4592 PR target/100204
4593 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
4594 before taking the negative of it.
4596 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
4598 PR target/113526
4599 * lra-constraints.cc (curr_insn_transform): Change class even for
4600 spilled pseudo successfully matched with with NO_REGS.
4602 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
4604 PR target/113601
4605 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
4607 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
4609 PR target/112987
4610 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
4611 (aarch64_expand_epilogue): Use the new function.
4612 (aarch64_split_compare_and_swap): Likewise.
4613 (aarch64_split_atomic_op): Likewise.
4615 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
4617 PR middle-end/112971
4618 * fold-const.cc (simplify_const_binop): New function for binop
4619 simplification of two constant vectors when element-wise
4620 handling is not necessary.
4621 (const_binop): Call new function.
4623 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
4625 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
4626 * config/riscv/constraints.md: Likewise.
4627 * config/riscv/corev.def: Likewise.
4628 * config/riscv/corev.md: Likewise.
4629 * config/riscv/predicates.md: Likewise.
4630 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
4631 * config/riscv/riscv-ftypes.def: Likewise.
4632 * config/riscv/riscv.opt: Likewise.
4633 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
4634 * doc/extend.texi: Add XCVbitmanip builtin documentation.
4635 * doc/sourcebuild.texi: Likewise.
4637 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
4639 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
4641 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
4643 PR target/113538
4644 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
4645 (riscv_fntype_abi): Ditto.
4646 * config/riscv/riscv.opt: Ditto.
4648 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4650 PR middle-end/113574
4651 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
4652 count against TYPE_PRECISION rather than TYPE_SIZE.
4654 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4656 PR target/113572
4657 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
4658 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
4660 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4662 PR target/113550
4663 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
4664 whether each split instruction is a load that clobbers the source
4665 address. Emit that instruction last if so.
4667 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4669 PR target/113485
4670 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
4671 pattern.
4672 (<optab><Vnarrowq><mode>2): Use it instead of generating a
4673 paradoxical subreg for the input.
4675 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4677 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
4678 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
4679 predecessors dump information.
4681 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4683 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
4684 redundant full available computation.
4685 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4687 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4689 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
4690 * doc/rtl.texi (CONST_VECTOR): Likewise.
4692 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4694 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
4695 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
4696 (pass_vsetvl::execute): Ditto.
4697 * config/riscv/riscv.opt: Ditto.
4699 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
4701 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
4702 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
4704 2024-01-25 Richard Biener <rguenther@suse.de>
4706 PR tree-optimization/113576
4707 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
4708 exits with may_be_zero niters when its the last one.
4710 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
4712 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
4713 For symbols of type tls, non-zero Offset is not generated.
4715 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
4717 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
4718 P9 with m32 and mpowerpc64.
4720 2024-01-25 liuhongt <hongtao.liu@intel.com>
4722 * config/i386/i386-options.cc (ix86_option_override_internal):
4723 Enable -mlam=u57 by default when compiled with
4724 -fsanitize=hwaddress.
4726 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
4728 * common/config/riscv/riscv-common.cc (riscv_implied_info):
4729 Remove {"ztso", "a"}.
4731 2024-01-24 Martin Jambor <mjambor@suse.cz>
4733 PR ipa/108007
4734 PR ipa/112616
4735 * cgraph.h (cgraph_edge): Add a parameter to
4736 redirect_call_stmt_to_callee.
4737 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
4738 parameter to modify_call.
4739 (ipa_release_ssas_in_hash): Declare.
4740 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
4741 parameter killed_ssas, pass it to padjs->modify_call.
4742 * ipa-param-manipulation.cc (purge_all_uses): New function.
4743 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
4744 Instead of substituting uses, invoke purge_all_uses. If
4745 hash of killed SSAs has not been provided, create a temporary one
4746 and release SSAs that have been added to it.
4747 (compare_ssa_versions): New function.
4748 (ipa_release_ssas_in_hash): Likewise.
4749 * tree-inline.cc (redirect_all_calls): Create
4750 id->killed_new_ssa_names earlier, pass it to edge redirection,
4751 adjust a comment.
4752 (copy_body): Release SSAs in id->killed_new_ssa_names.
4754 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
4756 PR target/113486
4757 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
4758 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
4760 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
4762 PR target/113095
4763 * config/riscv/sfb.md: New splitters to rewrite single bit
4764 sign extension as the condition to SFB instructions.
4766 2024-01-24 Jan Hubicka <jh@suse.cz>
4768 PR middle-end/88345
4769 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
4770 (fmin-function-alignment): New parameter.
4771 * doc/invoke.texi: (-fmin-function-alignment): Document.
4772 (-falign-functions,-falign-loops,-falign-labels): Mention that
4773 aglinments are ignored in cold code.
4774 * varasm.cc (assemble_start_function): Handle min-function-alignment.
4776 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4778 PR target/109636
4779 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
4780 mulv2di3): Remove.
4781 * config/aarch64/iterators.md (VQDIV): Remove.
4782 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
4783 SVE_I_SIMD_DI): New.
4784 (VPRED, sve_lane_con): Add V4SI and V2DI.
4785 * config/aarch64/aarch64-sve.md (<optab><mode>3,
4786 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
4787 (mul<mode>3): New, split from <optab><mode>3.
4788 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
4789 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
4790 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
4791 SVE_FULL_HSDI_SIMD_DI.
4793 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4795 PR tree-optimization/113552
4796 * config/aarch64/aarch64.cc
4797 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
4799 2024-01-24 Martin Jambor <mjambor@suse.cz>
4801 PR ipa/113490
4802 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
4803 count is equal or greater than the limit. Use the limit from the
4804 callee.
4806 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
4808 * configure.ac: Detect the explicit relocs support for
4809 mips, and define C macro MIPS_EXPLICIT_RELOCS.
4810 * config.in: Regenerated.
4811 * configure: Regenerated.
4812 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
4813 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
4814 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
4815 !TARGET_EXPLICIT_RELOCS instead of just set it.
4816 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
4817 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
4818 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
4819 and define -m(no-)explicit-relocs as aliases.
4821 2024-01-24 Alex Coplan <alex.coplan@arm.com>
4823 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4824 to 1.
4825 (-mlate-ldp-fusion): Likewise.
4827 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4829 * tree-vect-loop.cc (vect_get_vect_def,
4830 vect_create_epilog_for_reduction): Rename main_exit_p to
4831 last_val_reduc_p.
4833 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4835 PR tree-optimization/113364
4836 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
4837 early exits then we must reduce from the first offset for all of them.
4839 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4841 PR target/113495
4842 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
4843 (get_regno): Ditto.
4844 (get_bb_index): Ditto.
4845 (pre_vsetvl::compute_avl_def_data): Ditto.
4846 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
4847 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4849 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
4850 Richard Sandiford <richard.sandiford@arm.com>
4852 PR target/100942
4853 * ccmp.cc (ccmp_candidate_p): Add outer argument.
4854 Allow if the outer is true and the lhs is used more
4855 than once.
4856 (expand_ccmp_expr): Update call to ccmp_candidate_p.
4857 * expr.h (expand_expr_real_gassign): Declare.
4858 * expr.cc (expand_expr_real_gassign): New function, split out from...
4859 (expand_expr_real_1): ...here.
4860 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
4862 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4864 PR target/113089
4865 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
4866 (fixup_debug_use): New.
4867 (fixup_debug_uses_trailing_add): New.
4868 (fixup_debug_uses): New. Use it ...
4869 (ldp_bb_info::fuse_pair): ... here.
4870 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
4871 fix up debug uses of the base register that are affected by
4872 folding in the trailing add insn.
4874 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4876 PR target/113089
4877 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
4878 Update trailing nondebug uses of the base register in the case
4879 of cancelling writeback.
4881 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4883 PR target/113089
4884 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
4885 (debug_insn_use_iterator): New.
4886 (set_info::first_debug_insn_use): New.
4887 (set_info::debug_insn_uses): New.
4888 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
4889 (set_info::first_debug_insn_use): New.
4890 (set_info::debug_insn_uses): New.
4892 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4894 PR target/113356
4895 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
4896 Don't record hazards against the opposite insn in the pair.
4898 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4900 PR target/113070
4901 * config/aarch64/aarch64-ldp-fusion.cc
4902 (struct stp_change_builder): New.
4903 (decide_stp_strategy): Reanme to ...
4904 (try_repurpose_store): ... this.
4905 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
4906 construct stp changes. Fix up uses when inserting new stp insns.
4908 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4910 PR target/113070
4911 * rtl-ssa.h: Include hash-set.h.
4912 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
4913 new_sets parameter and use it to keep track of new user-created sets.
4914 (function_info::apply_changes_to_insn): Also call add_def on new sets.
4915 (function_info::change_insns): Add hash_set to keep track of new
4916 user-created defs. Plumb it through.
4917 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
4918 apply_changes_to_insn.
4920 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4922 PR target/113070
4923 * rtl-ssa/accesses.cc (function_info::create_use): New.
4924 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
4925 Ensure new uses end up referring to permanent defs.
4926 * rtl-ssa/functions.h (function_info::create_use): Declare.
4928 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4930 PR target/113070
4931 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
4932 to finalize_new_accesses from the backwards placement loop, run it
4933 forwards in a separate loop.
4935 2024-01-23 Richard Biener <rguenther@suse.de>
4937 PR tree-optimization/113552
4938 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
4939 floor_log2 instead of exact_log2 on the number of calls.
4941 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
4942 Jakub Jelinek <jakub@redhat.com>
4944 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
4945 decl.
4947 2024-01-23 Richard Biener <rguenther@suse.de>
4949 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4950 Separate single and multi-exit case when creating PHIs between
4951 the main and epilogue.
4953 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
4955 PR target/112989
4956 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
4957 MODE_single variants of functions that don't take tuple arguments.
4959 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4961 PR target/113114
4962 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
4963 Don't assert recog success, just punt if the writeback pair
4964 isn't recognized.
4966 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4968 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
4969 ATTRIBUTE_UNUSED to decl.
4971 2024-01-23 Richard Biener <rguenther@suse.de>
4973 PR debug/107058
4974 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
4975 handle unexpected but bogus DIE contexts when not checking
4976 enabled.
4978 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4980 PR tree-optimization/113462
4981 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
4982 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
4983 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
4984 sizes between 129 and 8192 bytes.
4986 2024-01-23 Xi Ruoyao <xry111@xry111.site>
4988 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
4989 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
4990 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
4991 (loongarch_call_tls_get_addr): Do not split symbols of
4992 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
4993 EXPLICIT_RELOCS_AUTO.
4995 2024-01-23 Richard Biener <rguenther@suse.de>
4997 * alias.cc (known_base_value_p): Remove.
4998 (find_base_value): Remove PLUS/MINUS handling
4999 when both operands are not CONST_INT_P.
5001 2024-01-23 Richard Biener <rguenther@suse.de>
5003 PR rtl-optimization/113255
5004 * alias.cc (find_base_term): Remove PLUS/MINUS handling
5005 when both operands are not CONST_INT_P.
5007 2024-01-23 Richard Biener <rguenther@suse.de>
5009 PR debug/112718
5010 * dwarf2out.cc (dwarf2out_finish): Reset all type units
5011 for the fat part of an LTO compile.
5013 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
5015 * doc/sourcebuild.texi: Add attributes for keywords.
5017 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
5019 PR c++/90463
5020 * doc/invoke.texi (Warning Options): Correct lists of options
5021 enabled by -Wall and -Wextra by checking against common.opt
5022 and c-family/c.opt.
5024 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
5026 PR target/113030
5027 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
5028 instead of cpu_optaliases.
5029 (check_arch): Use arch_opt_alias instead of arch_optaliases.
5031 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5033 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
5034 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
5035 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
5037 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5039 PR target/109092
5040 * config/riscv/riscv.md: Use reg instead of subreg.
5042 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
5044 PR other/111966
5045 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
5046 to match the compiler default.
5047 (simple_object_copy_lto_debug_sections): Never unlink the outfile
5048 on error as the caller does so.
5049 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
5050 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
5052 2024-01-22 Richard Biener <rguenther@suse.de>
5054 PR tree-optimization/113373
5055 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5056 Create LC PHIs in the exit blocks where necessary.
5057 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
5058 to handle missing LC PHIs.
5059 (find_connected_edge): Remove.
5060 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
5062 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5064 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
5066 2024-01-22 xuli <xuli1@eswincomputing.com>
5068 PR target/113420
5069 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
5070 (registered_function::overloaded_hash):refactor.
5071 (resolve_overloaded_builtin):avoid internal ICE.
5073 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
5075 PR target/82420
5076 PR target/111279
5077 * calls.cc (emit_library_call_value_1): Pass valid TYPE
5078 to emit_push_insn.
5079 * expr.cc (emit_push_insn): Likewise.
5081 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
5083 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
5084 correcction version of last change.
5086 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
5088 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
5089 fix bugs in signature.
5091 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
5092 Richard Biener <rguenther@suse.de>
5094 PR rtl-optimization/111267
5095 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
5096 profitable_p method to likely_profitable_p.
5097 (try_fwprop_subst_node): Update call to likely_profitable_p.
5098 Only bail-out early when !prop.likely_profitable_p for instructions
5099 that are not single sets. When comparing costs, bail-out if the
5100 cost is unchanged and !prop.likely_profitable_p.
5102 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
5104 PR c++/90464
5105 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
5106 isn't enabled by -Wunused unless -Wextra is provided, and that
5107 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
5108 -Wunused doesn't enable -Wunused-* options documented as behaving
5109 otherwise, and list them explicitly.
5111 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
5113 PR c/109708
5114 * doc/invoke.texi (Warning Options): Fix broken example and
5115 clean up/reorganize the others. Also describe what the short-form
5116 options mean.
5118 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
5120 PR c/102998
5121 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
5122 (Warning Options): Correct/edit discussion of -Warray-parameter
5123 to make the first example less confusing, and fill in missing info.
5125 2024-01-20 Jakub Jelinek <jakub@redhat.com>
5127 PR tree-optimization/113462
5128 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
5129 Handle rhs1 INTEGER_CST like SSA_NAME.
5131 2024-01-20 Jakub Jelinek <jakub@redhat.com>
5133 PR tree-optimization/113491
5134 * tree-switch-conversion.cc (switch_conversion::build_constructors):
5135 If elt.index has precision higher than sizetype, fold_convert it to
5136 sizetype.
5137 (switch_conversion::array_value_type): Return type if type is
5138 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
5139 (switch_conversion::build_arrays): Use unsigned_type_for rather than
5140 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
5141 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
5142 higher than sizetype, use sizetype as tidx type and fold_convert the
5143 subtraction to sizetype.
5145 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5147 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
5148 (riscv_vector_mode_supported_any_target_p): Ditto.
5150 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
5152 PR target/110934
5153 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
5154 (TARGET_ZERO_CALL_USED_REGS): Define.
5156 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
5158 PR target/108640
5159 * config/m68k/m68k.cc (output_andsi3): Use QImode for
5160 address adjusted for 1-byte RMW access.
5161 (output_iorsi3): Likewise.
5162 (output_xorsi3): Likewise.
5164 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5166 * doc/invoke.texi (RISC-V Options): Add list of supported
5167 extensions.
5169 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5171 PR target/113495
5172 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
5173 (RVV_VUNDEF): Ditto.
5174 * config/riscv/riscv-vsetvl.cc: Add timevar.
5176 2024-01-19 Richard Biener <rguenther@suse.de>
5178 PR debug/113488
5179 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
5180 an early DIE but there should be, do not pretend there is.
5182 2024-01-19 Richard Biener <rguenther@suse.de>
5184 PR tree-optimization/113494
5185 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5186 Handle endless loop on exit. Handle re-allocated PHI.
5188 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5190 PR tree-optimization/113464
5191 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
5192 optimize loads into GIMPLE_ASM stmts.
5194 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5196 PR tree-optimization/113463
5197 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
5198 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
5199 lhs.
5201 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5203 PR tree-optimization/113459
5204 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
5205 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
5206 of SCALAR_INT_TYPE_MODE if type has BLKmode.
5207 (vn_reference_lookup_3): Likewise. Formatting fix.
5209 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5210 Richard Biener <rguenther@suse.de>
5212 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
5213 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
5214 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
5215 but adjust_address also for BLKmode mode and MEM op0.
5217 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
5219 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
5220 extensions.
5222 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5224 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
5226 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5228 * common/config/riscv/riscv-common.cc
5229 (riscv_subset_list::parse_std_ext): Remove.
5230 (riscv_subset_list::parse_multiletter_ext): Remove.
5231 * config/riscv/riscv-subset.h
5232 (riscv_subset_list::parse_std_ext): Remove.
5233 (riscv_subset_list::parse_multiletter_ext): Remove.
5235 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5237 * common/config/riscv/riscv-common.cc
5238 (riscv_subset_list::parse_single_std_ext): New parameter.
5239 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
5240 (riscv_subset_list::parse_single_ext): Ditto.
5241 (riscv_subset_list::parse): Relax the order for the input of ISA
5242 string.
5243 * config/riscv/riscv-subset.h
5244 (riscv_subset_list::parse_single_std_ext): New parameter.
5245 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
5246 (riscv_subset_list::parse_single_ext): Ditto.
5248 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5250 * common/config/riscv/riscv-common.cc
5251 (riscv_subset_list::parse_base_ext): New.
5252 (riscv_subset_list::parse): Extract part of logic into
5253 riscv_subset_list::parse_base_ext.
5254 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
5255 New.
5257 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5259 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
5260 sorry message.
5262 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
5264 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
5265 UNSPEC_CLMUL_VC.
5267 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
5269 PR c/110029
5270 * doc/extend.texi (Common Variable Attributes): Explain what
5271 happens when multiple variables with cleanups are in the same scope.
5273 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5275 PR ipa/108470
5276 * doc/extend.texi (Common Function Attributes): Document that
5277 noinline also disables some interprocedural optimizations and
5278 improve flow to the part about using inline asm instead to
5279 disable calls from being optimized away completely. Remove the
5280 sentence that says noipa is mainly for internal compiler testing.
5282 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
5284 PR tree-optimization/69807
5285 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
5287 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
5289 PR target/108521
5290 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
5291 from x86 Windows Options.
5293 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5295 PR c/107942
5296 * doc/extend.texi (C Extensions): Add new section to menu.
5297 (Function Attributes): Move dangling index entries to....
5298 (Const and Volatile Functions): New section.
5300 2024-01-18 David Malcolm <dmalcolm@redhat.com>
5302 PR middle-end/112684
5303 * toplev.cc (toplev::main): Don't ICE in
5304 -fdiagnostics-generate-patch when exiting after options,
5305 since no edit context will have been created.
5307 2024-01-18 Richard Biener <rguenther@suse.de>
5309 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
5310 operands vector.
5312 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5314 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
5315 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
5317 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5318 Jin Ma <jinma@linux.alibaba.com>
5319 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5320 Christoph Müllner <christoph.muellner@vrull.eu>
5322 * config/riscv/thead.cc
5323 (th_asm_output_opcode): Rewrite some instructions.
5325 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5326 Jin Ma <jinma@linux.alibaba.com>
5327 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5328 Christoph Müllner <christoph.muellner@vrull.eu>
5330 * config/riscv/riscv.md (none,thv,rvv): New attribute.
5331 (no,yes): Add an attribute to disable alternative
5332 for xtheadvector or RVV1.0.
5333 * config/riscv/vector.md:
5334 Disable alternatives that destination register overlaps
5335 source register group for xtheadvector.
5337 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5338 Jin Ma <jinma@linux.alibaba.com>
5339 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5340 Christoph Müllner <christoph.muellner@vrull.eu>
5342 * config/riscv/riscv-vector-builtins-bases.cc
5343 (class th_loadstore_width): Define new builtin bases.
5344 (class th_extract): Define new builtin bases.
5345 (BASE): Define new builtin bases.
5346 * config/riscv/riscv-vector-builtins-bases.h:
5347 Define new builtin class.
5348 * config/riscv/riscv-vector-builtins-shapes.cc
5349 (struct th_loadstore_width_def): Define new builtin shapes.
5350 (struct th_indexed_loadstore_width_def):
5351 Define new builtin shapes.
5352 (struct th_extract_def): Define new builtin shapes.
5353 (SHAPE): Define new builtin shapes.
5354 * config/riscv/riscv-vector-builtins-shapes.h:
5355 Define new builtin shapes.
5356 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
5357 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
5358 * config/riscv/riscv-vector-builtins.h
5359 (enum required_ext): Add new XTheadVector member.
5360 (struct function_group_info): Likewise.
5361 * config/riscv/t-riscv:
5362 Add thead-vector-builtins-functions.def
5363 * config/riscv/thead-vector.md
5364 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
5365 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
5366 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
5367 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
5368 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
5369 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
5370 (@pred_th_extract<mode>): Likewise.
5371 (*pred_th_extract<mode>): Likewise.
5372 * config/riscv/thead-vector-builtins-functions.def: New file.
5374 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5375 Jin Ma <jinma@linux.alibaba.com>
5376 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5377 Christoph Müllner <christoph.muellner@vrull.eu>
5379 * config.gcc: Add files for XTheadVector intrinsics.
5380 * config/riscv/autovec.md: Guard XTheadVector.
5381 * config/riscv/predicates.md: Disable immediate vl
5382 for XTheadVector.
5383 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
5384 Add pragma for XTheadVector.
5385 * config/riscv/riscv-string.cc (riscv_expand_block_move):
5386 Guard XTheadVector.
5387 * config/riscv/riscv-v.cc (vls_mode_valid_p):
5388 Avoid autovec.
5389 * config/riscv/riscv-vector-builtins-bases.cc:
5390 Do not normalize vsetvl instructions for XTheadVector.
5391 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
5392 New check type function.
5393 (build_one): Adjust for XTheadVector.
5394 * config/riscv/riscv-vector-switch.def (ENTRY):
5395 Disable fractional mode for the XTheadVector extension.
5396 (TUPLE_ENTRY): Likewise.
5397 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
5398 Guard XTheadVector.
5399 (riscv_preferred_simd_mode): Likewsie.
5400 (riscv_autovectorize_vector_modes): Likewise.
5401 (riscv_vector_mode_supported_any_target_p): Likewise.
5402 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
5403 * config/riscv/thead.cc (th_asm_output_opcode):
5404 Rewrite vsetvl instructions.
5405 * config/riscv/vector.md:
5406 Include thead-vector.md and change fractional LMUL
5407 into 1 for vbool.
5408 * config/riscv/riscv_th_vector.h: New file.
5409 * config/riscv/thead-vector.md: New file.
5411 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5412 Jin Ma <jinma@linux.alibaba.com>
5413 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5414 Christoph Müllner <christoph.muellner@vrull.eu>
5416 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
5417 Add new function to add assembler insn code prefix/suffix.
5418 (th_asm_output_opcode):
5419 Add Thead function to add assembler insn code prefix/suffix.
5420 * config/riscv/riscv.cc (riscv_asm_output_opcode):
5421 Implement function to add assembler insn code prefix/suffix.
5422 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
5423 Add new function to add assembler insn code prefix/suffix.
5424 * config/riscv/thead.cc (th_asm_output_opcode):
5425 Implement Thead function to add assembler insn code
5426 prefix/suffix.
5428 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5429 Jin Ma <jinma@linux.alibaba.com>
5430 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5431 Christoph Müllner <christoph.muellner@vrull.eu>
5433 * common/config/riscv/riscv-common.cc
5434 (riscv_subset_list::parse): Add new vendor extension.
5435 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
5436 Add test marco.
5437 * config/riscv/riscv.opt: Add new mask.
5439 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5441 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
5442 to be conditional on macosx-version-min.
5444 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5446 * config/darwin.cc (darwin_objc1_section): Use the correct
5447 meta-data version for constant strings.
5448 (machopic_select_section): Assert if we fail to handle CFString
5449 sections as Obejctive-C meta-data or drectly.
5451 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5453 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
5454 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
5455 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
5456 versions when the object format is Mach-O.
5458 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5460 PR target/105522
5461 * config/darwin.cc (machopic_select_section): Handle C and C++
5462 CFStrings.
5463 (darwin_rename_builtins): Move this out of the CFString code.
5464 (darwin_libc_has_function): Likewise.
5465 (darwin_build_constant_cfstring): Create an anonymous var to
5466 hold each CFString.
5467 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
5468 CFstrings.
5470 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5472 PR bootstrap/113445
5473 * haifa-sched.cc (dep_list_size): Make global.
5474 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
5475 * sched-int.h (dep_list_size): Declare.
5477 2024-01-18 Martin Jambor <mjambor@suse.cz>
5479 PR tree-optimization/110422
5480 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
5481 gotos.
5483 2024-01-18 Richard Biener <rguenther@suse.de>
5485 PR tree-optimization/113475
5486 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
5487 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
5488 (phi_analyzer::~phi_analyzer): Deallocate and free collected
5489 phi_grous.
5490 (phi_analyzer::process_phi): Record allocated phi_groups.
5492 2024-01-18 Richard Biener <rguenther@suse.de>
5494 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
5495 storage for gvec_oprnds elements.
5497 2024-01-18 Richard Biener <rguenther@suse.de>
5499 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
5500 prefer all later exits we can handle.
5501 (vect_analyze_loop_form): Free the allocated loop body.
5502 Adjust comments.
5504 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5506 * config/avr/avr-log.cc: Tabify.
5508 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5510 * config/riscv/autovec.md: Support vi variant.
5512 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5514 * config/avr/avr-devices.cc: Tabify.
5516 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5518 * config/avr/avr-c.cc: Tabify.
5520 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5522 * config/avr/driver-avr.cc: Tabify.
5524 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5526 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
5528 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5530 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
5532 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5534 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
5535 minline-strcmp, minline-strncmp, minline-strlen,
5536 -param=riscv-vector-abi): Remove Bool keywords.
5538 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5540 PR target/113122
5541 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
5542 support. Add missing space after , in emitted assembly in some
5543 cases. Formatting fixes.
5545 2024-01-18 Xi Ruoyao <xry111@xry111.site>
5547 * config/loongarch/loongarch.md (movsi_internal): Remove
5548 constraint z.
5550 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5552 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
5553 in the diagnostic, and capitalize the device name.
5554 (print_mcu): Generate specs such that:
5555 <*check_rodata_in_ram>: New.
5556 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
5557 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
5558 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
5560 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5562 PR other/113399
5563 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
5564 Common and Optimization.
5566 2024-01-18 Richard Biener <rguenther@suse.de>
5568 PR tree-optimization/113431
5569 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
5570 When there is an invariant load we might not preserve
5571 scalar order.
5573 2024-01-18 Richard Biener <rguenther@suse.de>
5575 PR tree-optimization/113374
5576 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
5577 * tree-vect-loop.cc (move_early_exit_stmts): Update
5578 virtual LC PHIs.
5579 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5580 Refactor. Preserve virtual LC PHIs on all exits.
5582 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
5584 * config/loongarch/loongarch.cc (loongarch_split_symbol):
5585 Assign the '/u' attribute to the mem.
5587 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5589 PR middle-end/110847
5590 * doc/invoke.texi (Option Summary): Document negative forms of
5591 -Wtsan and -Wxor-used-as-pow.
5592 (Warning Options): Likewise.
5594 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5596 PR target/113429
5597 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
5599 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5601 * doc/extend.texi (Common Function Attributes): Re-alphabetize
5602 the table.
5603 (Common Variable Attributes): Likewise.
5604 (Common Type Attributes): Likewise.
5606 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5608 PR middle-end/111659
5609 * doc/extend.texi (Common Variable Attributes): Fix long lines
5610 in documentation of strict_flex_array + other minor copy-editing.
5611 Add a cross-reference to -Wstrict-flex-arrays.
5612 * doc/invoke.texi (Option Summary): Fix whitespace in tables
5613 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
5614 (C Dialect Options): Combine the docs for the two
5615 -fstrict-flex-arrays forms into a single entry. Note this option
5616 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
5617 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
5618 Minor copy-editing. Add cross references to the strict_flex_array
5619 attribute and -fstrict-flex-arrays option. Add note that this
5620 option depends on -ftree-vrp.
5622 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
5624 PR target/113221
5625 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
5626 only allow REG operands instead of allowing all.
5628 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5630 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
5631 Remove redundant checks in else condition for readablity.
5632 (earliest_fuse_vsetvl_info) Print iteration count in debug
5633 prints.
5634 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
5635 dump details in certain cases.
5637 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5639 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
5640 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
5641 * config/riscv/riscv-vsetvl.cc
5642 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
5643 (pass_vsetvl::execute): Use vsetvl_strategy.
5645 2024-01-17 Jan Hubicka <jh@suse.cz>
5647 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
5648 accidental hack reseting offset.
5650 2024-01-17 Jan Hubicka <jh@suse.cz>
5652 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
5653 handling of X86_TUNE_AVOID_512FMA_CHAINS.
5655 2024-01-17 Jan Hubicka <jh@suse.cz>
5656 Jakub Jelinek <jakub@redhat.com>
5658 PR tree-optimization/110852
5659 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
5660 binary operations
5661 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
5662 PRED_COMBINED_VALUE_PREDICTIONS_PHI
5663 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
5664 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
5666 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5668 PR tree-optimization/113421
5669 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
5670 comment.
5671 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
5672 formatting. Start at vop rather than cvop even if stmt is a store
5673 and needs_operand_addr.
5675 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5677 PR middle-end/113410
5678 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
5679 If access_nelts is integral with larger precision than sizetype,
5680 fold_convert it to sizetype.
5682 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5684 PR tree-optimization/113408
5685 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
5686 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
5687 to handle_cast.
5689 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5691 PR middle-end/113406
5692 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
5693 regardless of whether is_gimple_reg_type (restype) or not.
5695 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5697 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
5698 funcions -> functions, and use were instead of was.
5699 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
5700 and guaranteee -> guarantee.
5701 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
5703 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5705 PR middle-end/113409
5706 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
5707 INTEGER_TYPE.
5708 (omp_extract_for_data): Use build_bitint_type rather than
5709 build_nonstandard_integer_type if either iter_type or loop->v type
5710 is BITINT_TYPE.
5711 * omp-expand.cc (expand_omp_for_generic,
5712 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
5713 BITINT_TYPE like INTEGER_TYPE.
5715 2024-01-17 Richard Biener <rguenther@suse.de>
5717 PR tree-optimization/113371
5718 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
5719 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5720 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
5721 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5723 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5725 PR rtl-optimization/96388
5726 PR rtl-optimization/111554
5727 * sched-deps.cc (find_inc): Avoid exponential behavior.
5729 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5731 PR c/111693
5732 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
5733 from C++ Language Options to Warning Options. Add entry for
5734 -Wuse-after-free.
5735 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
5736 from here....
5737 (Warning Options): ...to here. Minor copy-editing to fix typo
5738 and grammar.
5740 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
5742 * config/mips/mips.cc (mips_compute_frame_info): If another
5743 register is used as global_pointer, mark $GP live false.
5745 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5747 PR target/112973
5748 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
5749 give the section a light copy-editing pass.
5751 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5753 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
5754 * config/aarch64/aarch64-tune.md: Regenerated.
5755 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
5757 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5759 PR target/112573
5760 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
5761 badly formed CONST expressions.
5763 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5765 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
5767 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5769 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
5770 * config/sparc/sync.md (membar_storeload): Turn into named insn
5771 and add GR712RC errata workaround.
5772 (membar_v8): Add GR712RC errata workaround.
5774 2024-01-16 Andreas Larsson <andreas@gaisler.com>
5776 * config/sparc/sync.md (*membar_storeload_leon3): Remove
5777 (*membar_storeload): Enable for LEON
5779 2024-01-16 Jakub Jelinek <jakub@redhat.com>
5781 PR tree-optimization/113372
5782 PR middle-end/90348
5783 PR middle-end/110115
5784 PR middle-end/111422
5785 * cfgexpand.cc (add_scope_conflicts_2): New function.
5786 (add_scope_conflicts_1): Use it.
5788 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
5790 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
5791 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
5792 * doc/avr-mmcu.texi: Regenerate.
5794 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
5796 PR tree-optimization/113091
5797 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
5798 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
5799 scalar use with new function.
5800 (vect_bb_slp_mark_live_stmts): New function as entry to existing
5801 overriden functions with same name.
5802 (vect_slp_analyze_operations): Call new entry function to mark
5803 live statements.
5805 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5807 PR target/113404
5808 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
5809 for RVV in big-endian mode.
5811 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
5813 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
5814 (riscv_pass_in_vector_p): Delete.
5815 (riscv_init_cumulative_args): Delete the checking.
5816 (riscv_get_arg_info): Delete the checking.
5817 (riscv_function_value): Delete the checking.
5818 * config/riscv/riscv.h: Delete the member for checking.
5820 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5822 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
5824 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5826 * config.gcc: Include riscv_bitmanip.h.
5827 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
5828 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
5829 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
5830 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
5831 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
5832 * config/riscv/riscv-ftypes.def (2): New ftypes.
5833 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
5834 (RISCV_BUILTIN_NO_PREFIX): Likewise.
5835 * config/riscv/riscv_bitmanip.h: New file.
5837 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5839 * config.gcc: Include riscv_crypto.h.
5840 * config/riscv/riscv_crypto.h: New file.
5842 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
5844 PR middle-end/113354
5845 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
5846 in the insn if the corresponding operand does not require hard
5847 register anymore.
5849 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5851 PR target/107201
5852 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
5853 * config/avr/driver-avr.cc (avr_no_devlib): New function.
5854 (avr_devicespecs_file): Use it to remove -nodevicelib from the
5855 options for cores only.
5856 * config/avr/avr-arch.h (avr_get_parch): New prototype.
5857 * config/avr/avr-devices.cc (avr_get_parch): New function.
5859 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5861 PR target/113247
5862 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
5863 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
5864 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
5866 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5868 PR target/113281
5869 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
5870 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
5871 * config/riscv/riscv-vector-costs.h: New function.
5873 2024-01-15 Richard Biener <rguenther@suse.de>
5875 PR tree-optimization/113385
5876 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5877 First redirect, then split the exit edge.
5879 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5881 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
5882 Remove m_num_vector_iterations.
5883 * config/riscv/riscv-vector-costs.h: Ditto.
5885 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
5887 PR target/113156
5888 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
5889 (-mbranch-cost): Set "Optimization" flag.
5891 2024-01-15 Jakub Jelinek <jakub@redhat.com>
5893 PR tree-optimization/113370
5894 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
5895 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
5896 set it to just prec % limb_prec.
5898 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5900 PR target/113393
5901 * config/riscv/vector.md: Fix ternary attributes.
5903 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
5905 PR target/112944
5906 * configure.ac [target=avr]: Check availability of emulations
5907 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
5908 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
5909 * configure: Regenerate.
5910 * config.in: Regenerate.
5911 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
5912 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
5913 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
5914 * config/avr/avr-arch.h (enum avr_device_specific_features):
5915 Add AVR_ISA_FLMAP.
5916 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
5917 AVR_ISA_FLMAP.
5918 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
5919 (avr_set_core_architecture): Set avr_arch_index.
5920 (have_avrxmega2_flmap, have_avrxmega4_flmap)
5921 (have_avrxmega3_rodata_in_flash): Set new static const bool according
5922 to configure results.
5923 (avr_rodata_in_flash_p): New function using them.
5924 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
5925 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
5926 (avr_asm_named_section): Track avr_has_rodata_p.
5927 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
5928 and not avr_rodata_in_flash_p ().
5929 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
5930 (LINK_SPEC): Add %(link_rodata_in_ram).
5931 (LINK_ARCH_SPEC): Remove.
5932 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
5933 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
5934 const bool according to configure results.
5935 (diagnose_mrodata_in_ram): New function.
5936 (print_mcu): Generate specs with the following changes:
5937 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
5938 need to extend avr/specs.h each time we add a new bell or whistle.
5939 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
5940 -m[no-]rodata-in-ram.
5941 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
5942 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
5943 <*cpp>: Add %(cpp_rodata_in_ram).
5944 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
5945 requested.
5946 <*self_spec>: Add -mflmap or %<mflmap as needed.
5948 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
5950 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
5951 not the GPR iterator. Adjust pattern name and mode attribute
5952 accordingly.
5954 2024-01-13 Jakub Jelinek <jakub@redhat.com>
5956 PR tree-optimization/113361
5957 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
5958 Fix up determination of the type for > limb_prec constants.
5960 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5962 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
5963 Add web-link to the avr-gcc wiki.
5965 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5967 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
5968 documentation for a version without argument, which is not supported.
5970 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5972 * config/arm/arm_neon.h
5973 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
5974 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
5975 (vld1_f16_x4, vld1_f32_x4): New.
5976 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
5977 (vld1_bf16_x4): New.
5978 (vld1q_types_x4): Updated to use vld1q_x4
5979 from arm_neon_builtins.def
5980 * config/arm/arm_neon_builtins.def
5981 (vld1_x4): Updated entries.
5982 (vld1q_x4): New entries, but comes from the old vld1_x4
5983 * config/arm/neon.md
5984 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
5986 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5988 * config/arm/arm_neon.h
5989 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
5990 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
5991 (vld1_f16_x3, vld1_f32_x3): New.
5992 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
5993 (vld1_bf16_x3): New.
5994 (vld1q_types_x3): Updated to use vld1q_x3 from
5995 arm_neon_builtins.def
5996 * config/arm/arm_neon_builtins.def
5997 (vld1_x3): Updated entries.
5998 (vld1q_x3): New entries, but comes from the old vld1_x2
5999 * config/arm/neon.md
6000 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
6002 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6004 * config/arm/arm_neon.h
6005 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
6006 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
6007 (vld1_f16_x2, vld1_f32_x2): New.
6008 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
6009 (vld1_bf16_x2): New.
6010 (vld1q_types_x2): Updated to use vld1q_x2 from
6011 arm_neon_builtins.def
6012 * config/arm/arm_neon_builtins.def
6013 (vld1_x2): Updated entries.
6014 (vld1q_x2): New entries, but comes from the old vld1_x2
6015 * config/arm/neon.md
6016 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
6017 neon_vld1_x2<mode>.
6019 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6021 * config/arm/arm_neon.h
6022 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
6023 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
6024 (vst1q_f16_x4, vst1q_f32_x4): New.
6025 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
6026 (vst1q_bf16_x4): New.
6027 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
6028 * config/arm/neon.md
6029 (neon_vst1q_x4<mode>): New.
6030 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
6031 * config/arm/unspecs.md
6032 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
6034 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6036 * config/arm/arm_neon.h
6037 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
6038 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
6039 (vst1q_f16_x3, vst1q_f32_x3): New.
6040 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
6041 (vst1q_bf16_x3): New.
6042 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
6043 * config/arm/neon.md
6044 (neon_vst1q_x3<mode>): New.
6045 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
6046 * config/arm/unspecs.md
6047 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
6049 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6051 * config/arm/arm_neon.h
6052 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
6053 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
6054 (vst1q_f16_x2, vst1q_f32_x2): New.
6055 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
6056 (vst1q_bf16_x2): New.
6057 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
6058 * config/arm/neon.md
6059 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
6060 neon_vst1_x2<mode>.
6061 * config/arm/iterators.md
6062 (VMEMX2): New mode iterator.
6063 (VMEMX2_q): New mode attribute.
6065 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6067 * config/arm/arm_neon.h
6068 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
6069 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
6070 (vst1_f16_x4, vst1_f32_x4): New.
6071 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
6072 (vst1_bf16_x4): New.
6073 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
6074 * config/arm/neon.md (vst1_x4<mode>): New.
6076 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6078 * config/arm/arm_neon.h
6079 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
6080 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
6081 (vst1_f16_x3, vst1_f32_x3): New.
6082 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
6083 (vst1_bf16_x3): New.
6084 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
6085 * config/arm/neon.md (vst1_x3<mode>): New.
6087 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6089 * config/arm/arm_neon.h
6090 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
6091 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
6092 (vst1_f16_x2, vst1_f32_x2): New.
6093 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
6094 (vst1_bf16_x2): New.
6095 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
6096 * config/arm/neon.md (vst1_x2<mode>): New.
6098 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6100 * config/arm/arm_neon.h
6101 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
6102 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
6103 (vld1q_f16_x4, vld1q_f32_x4): New.
6104 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
6105 (vld1q_bf16_x4): New.
6106 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
6107 * config/arm/neon.md
6108 (neon_vld1_x4<mode>): New.
6109 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
6110 * config/arm/unspecs.md
6111 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
6113 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6115 * config/arm/arm_neon.h
6116 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
6117 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
6118 (vld1q_f16_x3, vld1q_f32_x3): New.
6119 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
6120 (vld1q_bf16_x3): New.
6121 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
6122 * config/arm/neon.md
6123 (neon_vld1_x3<mode>): New.
6124 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
6125 * config/arm/unspecs.md
6126 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
6128 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6130 * config/arm/arm_neon.h
6131 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
6132 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
6133 (vld1q_f16_x2, vld1q_f32_x2): New.
6134 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
6135 (vld1q_bf16_x2): New.
6136 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
6137 * config/arm/neon.md (vld1_x2<mode>): New.
6139 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6141 PR tree-optimization/113287
6142 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
6144 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6146 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
6147 * tree-vect-loop.cc (vect_transform_loop): Likewise.
6149 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6151 PR tree-optimization/113178
6152 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
6153 alternate exits.
6155 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6157 PR tree-optimization/113237
6158 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
6159 existing LCSSA variable for exit when all exits are early break.
6161 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6163 PR tree-optimization/113137
6164 PR tree-optimization/113136
6165 PR tree-optimization/113172
6166 PR tree-optimization/113178
6167 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6168 Maintain PHIs on inverted loops.
6169 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
6170 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
6171 latch.
6172 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
6174 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6176 PR tree-optimization/113135
6177 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
6178 dependency analysis.
6180 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
6182 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
6183 diagnostics class member name for abort of error.
6185 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
6187 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
6188 format string to %s argument.
6190 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
6191 Jakub Jelinek <jakub@redhat.com>
6193 PR middle-end/113182
6194 * varasm.cc (process_pending_assemble_externals,
6195 assemble_external_libcall): Use targetm.strip_name_encoding
6196 before calling get_identifier.
6198 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6200 PR target/113196
6201 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
6202 New member variable.
6203 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
6204 Declare.
6205 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
6206 * config/aarch64/aarch64-simd.md
6207 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
6208 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
6209 zip2 for zero-extends to...
6210 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
6211 instruction. Fix big-endian handling.
6212 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
6213 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
6214 zip1 for zero-extends to...
6215 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
6216 Fix big-endian handling.
6217 (*aarch64_zip1_uxtl): New pattern.
6218 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
6219 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
6220 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
6221 (aarch64_gen_shareable_zero): Use it.
6222 (aarch64_split_simd_shift_p): New function.
6224 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6226 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
6227 (function_beg_insn): New macro.
6228 * function.cc (expand_function_start): Initialize function_beg_insn.
6230 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6232 PR target/112989
6233 * config/aarch64/aarch64-sve-builtins.h
6234 (function_builder::m_overload_names): Replace with...
6235 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
6236 new global.
6237 (add_overloaded_function): Update accordingly, using get_identifier
6238 to get a GGC-friendly record of the name.
6240 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6242 PR target/112989
6243 * config/aarch64/aarch64-sve-builtins.def: Don't include
6244 aarch64-sve-builtins-sme.def.
6245 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
6246 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
6247 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
6248 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
6249 requires AARCH64_FL_SME2.
6250 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
6251 AARCH64_FL_SME adjustment here.
6252 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
6253 include SME intrinsics.
6254 (sme_function_groups): New array.
6255 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
6256 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
6258 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6260 PR target/113281
6261 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
6262 (struct cpu_vector_cost): Add regmove struct.
6263 (get_vector_costs): Export as global.
6264 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
6265 (costs::add_stmt_cost): Ditto.
6266 * config/riscv/riscv.cc (get_common_costs): Export global function.
6268 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6270 PR tree-optimization/113334
6271 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
6272 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
6273 to determine if number should be extended by all ones rather than zero
6274 extended.
6276 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6278 PR tree-optimization/113330
6279 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
6280 too large size.
6282 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6284 PR tree-optimization/113323
6285 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
6286 check for lhs being large/huge _BitInt not in m_names.
6288 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6290 PR tree-optimization/113316
6291 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
6292 uninitialized large/huge _BitInt arguments to calls.
6294 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6296 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
6297 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
6298 CEIL (TYPE_PRECISION (t), limb_prec).
6299 (bitint_large_huge::handle_cast): Likewise.
6301 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
6303 PR sanitizer/113284
6304 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6305 Use assemble_function_label_final () for Power ELF V1 ABI.
6306 * output.h (assemble_function_label_final): New function.
6307 * varasm.cc (assemble_function_label_raw): Use
6308 assemble_function_label_final ().
6309 (assemble_function_label_final): New function.
6311 2024-01-12 Richard Biener <rguenther@suse.de>
6313 PR middle-end/113344
6314 * match.pd ((double)float CMP (double)float -> float CMP float):
6315 Perform result type check only for vectors.
6316 * fold-const.cc (fold_binary_loc): Likewise.
6318 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
6320 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
6321 (usdot_prod<mode>): Ditto.
6322 (sdot_prod<mode>): Ditto.
6323 (udot_prod<mode>): Ditto.
6325 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
6327 PR target/113288
6328 * config/i386/i386-c.cc (ix86_target_macros_internal):
6329 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
6331 2024-01-12 Richard Biener <rguenther@suse.de>
6333 PR target/112280
6334 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
6335 Do not generate code when d.testing_p.
6337 2024-01-12 liuhongt <hongtao.liu@intel.com>
6339 PR target/113039
6340 * doc/invoke.texi (fcf-protection=): Update documents.
6342 2024-01-12 Pan Li <pan2.li@intel.com>
6344 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
6345 comments of predicate func riscv_v_ext_mode_p.
6347 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
6349 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
6350 Modify ABI-name length of vfloat16m8_t
6352 2024-01-12 Li Wei <liwei@loongson.cn>
6354 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
6355 Adjust.
6357 2024-01-12 Li Wei <liwei@loongson.cn>
6359 * config/loongarch/loongarch.md (add<mode>3): Removed.
6360 (*addsi3): New.
6361 (addsi3): Ditto.
6362 (adddi3): Ditto.
6363 (*addsi3_extended): Removed.
6364 (addsi3_extended): New.
6366 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
6368 * config/riscv/thead.md: Add limits for splits.
6370 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
6372 PR middle-end/113322
6373 * expr.cc (do_store_flag): Don't try single bit tests with
6374 comparison on vector types.
6376 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
6378 PR tree-optimization/113301
6379 * match.pd (`1/x`): Delay signed case until late.
6381 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
6383 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
6384 and -msp8 to...
6385 (AVR Internal Options): ...this new @subsubsection.
6387 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
6389 PR rtl-optimization/112918
6390 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
6391 (in_class_p): Restrict condition for narrowing class in case of
6392 allow_all_reload_class_changes_p.
6393 (process_alt_operands): Try to match operand without and with
6394 narrowing reg class. Discourage narrowing the class. Finish insn
6395 matching only if there is no class narrowing.
6396 (curr_insn_transform): Pass true to in_class_p for reg operand win.
6398 2024-01-11 Richard Biener <rguenther@suse.de>
6400 PR tree-optimization/112505
6401 * tree-vect-loop.cc (vectorizable_induction): Reject
6402 bit-precision induction.
6404 2024-01-11 Richard Biener <rguenther@suse.de>
6406 PR tree-optimization/113126
6407 * match.pd ((double)float CMP (double)float -> float CMP float):
6408 Make sure the boolean type is the same.
6409 * fold-const.cc (fold_binary_loc): Likewise.
6411 2024-01-11 Richard Biener <rguenther@suse.de>
6413 PR tree-optimization/112636
6414 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
6415 estimate_numbers_of_iterations before querying
6416 get_max_loop_iterations_int.
6417 (pass_ch::execute): Initialize SCEV and loops appropriately.
6419 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
6421 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
6422 Reduced Tiny.
6423 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
6424 * doc/extend.texi (AVR Variable Attributes): Improve documentation
6425 of io, io_low and address attributes.
6426 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
6427 * doc/avr-mmcu.texi: Rebuild.
6429 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
6431 PR target/113233
6432 * config/loongarch/genopts/loongarch.opt.in: Mark options with
6433 the "Save" property.
6434 * config/loongarch/loongarch.opt: Same.
6435 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
6436 according to la_target.
6437 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
6438 RESTORE} for the la_target structure; Rename option conditions
6439 to have the same "la_" prefix.
6440 * config/loongarch/loongarch.h: Same.
6442 2024-01-11 Pan Li <pan2.li@intel.com>
6444 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
6445 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
6447 2024-01-11 Alex Coplan <alex.coplan@arm.com>
6449 PR target/113077
6450 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
6451 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
6452 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
6453 synthesize these if needed. Update caller ...
6454 (ldp_bb_info::fuse_pair): ... here.
6455 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
6456 and either insn is frame-related.
6457 (find_trailing_add): Punt on frame-related insns.
6458 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
6459 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
6461 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
6463 * config/mips/mips.cc (mips_start_function_definition):
6464 Add ATTRIBUTE_UNUSED.
6466 2024-01-11 Richard Biener <rguenther@suse.de>
6468 PR middle-end/112740
6469 * expr.cc (store_constructor): Check the integer vector
6470 mask has a single bit per element before using sign-extension
6471 to expand an uniform vector.
6473 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6475 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
6476 preempt VLS on unknown NITERS loop.
6478 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
6480 * doc/invoke.texi: Add -mevex512.
6482 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
6484 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
6485 (*nor<mode>3): Likewise.
6486 (nor<mode>3): Likewise.
6487 (*negsi2_extended): New template.
6488 (*<optab>si3_internal): Likewise.
6489 (*one_cmplsi2_internal): Likewise.
6490 (*norsi3_internal): Likewise.
6491 (*<optab>nsi_internal): Likewise.
6492 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
6493 modified bit operation to make the optimization work.
6495 2024-01-11 liuhongt <hongtao.liu@intel.com>
6497 PR target/104401
6498 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
6500 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6502 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
6503 (get_vector_costs): Ditto.
6504 (riscv_builtin_vectorization_cost): Ditto.
6506 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6508 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
6510 2024-01-10 Antoni Boucher <bouanto@zoho.com>
6512 PR jit/111396
6513 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
6514 ipa_free_size_summary.
6515 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
6516 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
6517 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
6518 * ipa-prop.h (ipa_prop_cc_finalize): New function.
6519 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
6520 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
6521 ipa_sra_cc_finalize): New functions.
6522 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
6523 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
6524 ipa_sra_cc_finalize
6525 Include ipa-utils.h.
6527 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
6529 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
6530 (th_int_get_save_adjustment): Likewise.
6531 (th_int_adjust_cfi_prologue): Likewise.
6532 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
6533 (TH_INT_INTERRUPT): New macro.
6534 (riscv_expand_prologue): Add the processing of XTheadInt.
6535 (riscv_expand_epilogue): Likewise.
6536 * config/riscv/riscv.h (BITSET_P): Moved to here.
6537 * config/riscv/riscv.md: New unspec.
6538 * config/riscv/thead.cc (th_int_get_mask): New function.
6539 (th_int_get_save_adjustment): Likewise.
6540 (th_int_adjust_cfi_prologue): Likewise.
6541 * config/riscv/thead.md (th_int_push): New pattern.
6542 (th_int_pop): new pattern.
6544 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6546 PR tree-optimization/112468
6547 * doc/sourcebuild.texi: Document ifn_copysign.
6548 * match.pd: Only apply transformation if target supports the IFN.
6550 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
6552 PR tree-optimization/112581
6553 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
6554 mark_ssa_maybe_undefs.
6555 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
6556 variables can not be reassociated.
6557 (init_range_entry): Check for uninitialized variables too.
6558 (init_reassoc): Call mark_ssa_maybe_undefs.
6560 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
6562 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
6563 Also handle sign extension.
6565 2024-01-10 Alex Coplan <alex.coplan@arm.com>
6567 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
6568 to 0.
6569 (-mlate-ldp-fusion): Likewise.
6571 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6573 PR tree-optimization/113287
6574 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
6575 instead of using BRANCH_EDGE to determine true edge.
6577 2024-01-10 Richard Biener <rguenther@suse.de>
6579 PR tree-optimization/113078
6580 * tree-vect-loop.cc (check_reduction_path): Canonicalize
6581 .COND_SUB to .COND_ADD.
6583 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6585 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
6586 Handle prefix mappings before calling find_opt.
6587 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
6588 "-fno-"-prefixed command-line option.
6589 * opts-common.cc (get_option_prefix_remapping): New.
6590 * opts.h (get_option_prefix_remapping): New decl.
6592 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6594 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
6595 m_urlifier to pp_output_formatted_text.
6596 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
6597 (obstack_append_string): New overload, taking a length.
6598 (urlify_quoted_string): Pass in an obstack ptr, rather than using
6599 that of the pp's buffer. Generalize to handle trailing text in
6600 the buffer beyond the run of quoted text.
6601 (class quoting_info): New.
6602 (on_begin_quote): New.
6603 (on_end_quote): New.
6604 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
6605 it to calls to on_begin_quote and on_end_quote.
6606 (struct auto_obstack): New.
6607 (quoting_info::handle_phase_3): New.
6608 (pp_output_formatted_text): Add urlifier param. Use it if there
6609 is deferred urlification. Delete m_quotes.
6610 (selftest::pp_printf_with_urlifier): Pass urlifier to
6611 pp_output_formatted_text.
6612 (selftest::test_urlification): Update results for the existing
6613 case of quoted text stradding chunks; add more such test cases.
6614 * pretty-print.h (class quoting_info): New forward decl.
6615 (chunk_info::m_quotes): New field.
6616 (pp_output_formatted_text): Add optional urlifier param.
6618 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6620 * pretty-print.cc (selftest::test_pp_format): Add selftest
6621 coverage for numbered args.
6623 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6625 PR tree-optimization/113144
6626 PR tree-optimization/113145
6627 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6628 Update all BB that the original exits dominated.
6630 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
6632 * dwarf2out.cc (modified_type_die): Extend the support of reverse
6633 storage order to enumeration types if -gstrict-dwarf is not passed.
6634 (gen_enumeration_type_die): Add REVERSE parameter and generate the
6635 DIE immediately after the existing one if it is true.
6636 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
6637 call to gen_enumeration_type_die.
6638 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
6639 first recursive call as well as the call to gen_tagged_type_die.
6640 (gen_type_die): Add REVERSE parameter and pass it in the call to
6641 gen_type_die_with_usage.
6643 2024-01-10 Jakub Jelinek <jakub@redhat.com>
6645 PR tree-optimization/113120
6646 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
6647 with root->size TYPE_PRECISION don't build anything new.
6648 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
6649 rather than build_nonstandard_integer_type.
6651 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
6653 * config/i386/i386.opt: Adjust document.
6654 * doc/invoke.texi: Add description for
6655 -mapx-inline-asm-use-gpr32.
6657 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6659 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
6660 (avg<v_double_trunc>3_floor): New pattern.
6661 (<u>avg<v_double_trunc>3_ceil): Remove.
6662 (avg<v_double_trunc>3_ceil): New pattern.
6663 (uavg<mode>3_floor): Ditto.
6664 (uavg<mode>3_ceil): Ditto.
6665 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
6666 (enum insn_type): Ditto.
6667 * config/riscv/riscv-v.cc: Ditto.
6668 * config/riscv/vector-iterators.md (ashiftrt): Remove.
6669 (ASHIFTRT): Ditto.
6670 * config/riscv/vector.md: Add VLS modes.
6672 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6674 PR target/111480
6675 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
6676 (vczlsbb_char): New int attribute.
6677 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
6678 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
6679 (*vctzlsbb_zext_<mode>): Rename to ...
6680 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
6681 cover vclzlsbb.
6683 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6685 PR target/112606
6686 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
6687 of the last argument from altivec_register_operand to any_operand. If
6688 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
6689 otherwise if it doesn't satisfy altivec_register_operand, force it to
6690 REG using copy_to_mode_reg.
6692 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6694 PR middle-end/113100
6695 * builtins.cc (expand_builtin_stack_address): Guard stack point
6696 adjustment with SPARC_STACK_BOUNDARY_HACK.
6698 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6700 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
6701 argument string definitions.
6702 * config/loongarch/loongarch-str.h: Same.
6703 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
6704 as aliases to -mexplicit-relocs={always,none}
6705 * config/loongarch/loongarch.opt: Regenerate.
6706 * config/loongarch/loongarch.cc: Same.
6708 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6710 * config/loongarch/loongarch-def.h: Define constants with
6711 enums instead of Macros.
6713 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6715 * config/loongarch/genopts/loongarch-strings: Rename.
6716 * config/loongarch/genopts/loongarch.opt.in: Same.
6717 * config/loongarch/loongarch-cpu.cc: Same.
6718 * config/loongarch/loongarch-def.cc: Same.
6719 * config/loongarch/loongarch-def.h: Same.
6720 * config/loongarch/loongarch-opts.cc: Same.
6721 * config/loongarch/loongarch-opts.h: Same.
6722 * config/loongarch/loongarch-str.h: Same.
6723 * config/loongarch/loongarch.opt: Same.
6725 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6727 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
6728 variable with the common la_ prefix.
6729 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
6730 flags as saved using TargetVariable.
6731 * config/loongarch/loongarch.opt: Same.
6732 * config/loongarch/loongarch-def.h: Define evolution_set to
6733 mark changes to the -march default.
6734 * config/loongarch/loongarch-driver.cc: Same.
6735 * config/loongarch/loongarch-opts.cc: Same.
6736 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
6737 conditions around the la_target structure.
6738 * config/loongarch/loongarch.cc: Same.
6739 * config/loongarch/loongarch.md: Same.
6740 * config/loongarch/loongarch-builtins.cc: Same.
6741 * config/loongarch/loongarch-c.cc: Same.
6742 * config/loongarch/lasx.md: Same.
6743 * config/loongarch/lsx.md: Same.
6744 * config/loongarch/sync.md: Same.
6746 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
6748 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
6749 no less.
6751 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
6753 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
6755 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6757 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
6758 restart_loop.
6759 (vectorizable_live_operation): Likewise.
6761 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6763 PR tree-optimization/113199
6764 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
6765 BIT_FIELD_REF.
6767 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6769 PR target/113270
6770 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
6771 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
6772 GTY(()) declaration before the definition, drop GTY(()) drom the
6773 definition.
6775 2024-01-09 Richard Biener <rguenther@suse.de>
6777 PR tree-optimization/113026
6778 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
6779 redundant and wrong niter bound setting. Move niter
6780 bound adjustment down.
6782 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6784 PR middle-end/113163
6785 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
6786 Reject non-linear inductions that aren't supported.
6788 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6790 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
6791 left shift implementation strategies.
6792 (arc_shift_info): Type for each entry of the shift strategy table.
6793 (arc_shift_context_idx): Return a integer value for each code
6794 generation context, used as an index
6795 (arc_ashl_alg): Table indexed by context and shifted bit count.
6796 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
6797 left shift implementation.
6798 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
6799 provide accurate costs, when optimizing for speed or size.
6801 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6803 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
6805 2024-01-09 Julian Brown <julian@codesourcery.com>
6807 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
6808 processed out before gimplification.
6809 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
6810 * tree.def (OMP_ARRAY_SECTION): New tree code.
6812 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6814 PR tree-optimization/113210
6815 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
6816 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
6817 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
6818 minus 1.
6820 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
6822 PR rtl-optimization/113140
6823 * reorg.cc (fill_slots_from_thread): If we are to branch after the
6824 last instruction of the function, create an end label.
6826 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6827 Hongtao Liu <hongtao.liu@intel.com>
6829 PR target/112992
6830 * config/i386/i386-expand.cc
6831 (ix86_convert_const_wide_int_to_broadcast): Allow call to
6832 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
6833 (ix86_broadcast_from_constant): Revert recent change; Return a
6834 suitable MEMREF independently of mode/target combinations.
6835 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
6836 to decide whether expansion is possible/preferrable. Only try
6837 forcing DImode constants to memory (and trying again) if calling
6838 ix86_expand_vector_init_duplicate fails with an DImode immediate
6839 constant.
6840 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
6841 V4SImode for suitable immediate constants.
6842 <case E_V4DImode>: Try using V8SImode for suitable constants.
6843 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
6844 <case E_V2HImode>: Likewise.
6845 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
6846 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
6847 <label widen>: Handle CONT_INTs via simplify_binary_operation.
6848 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
6849 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
6850 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
6851 (ix86_expand_vector_init): Move try using a broadcast for all_same
6852 with ix86_expand_vector_init_duplicate before using constant pool.
6854 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6856 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
6858 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6860 * config/arm/arm-cpus.in (cortex-m52): New cpu.
6861 * config/arm/arm-tables.opt: Regenerate.
6862 * config/arm/arm-tune.md: Regenerate.
6864 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
6866 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
6867 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
6868 (@vec_concatz<mode>): New insn pattern.
6869 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
6870 Handle VALS containing two vectors.
6872 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6874 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
6875 (vundefined): Ditto.
6877 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
6879 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6880 Add new function_base for crypto vector.
6881 (class bitmanip): Ditto.
6882 (class b_reverse):Ditto.
6883 (class vwsll): Ditto.
6884 (class clmul): Ditto.
6885 (class vg_nhab): Ditto.
6886 (class crypto_vv):Ditto.
6887 (class crypto_vi):Ditto.
6888 (class vaeskf2_vsm3c):Ditto.
6889 (class vsm3me): Ditto.
6890 (BASE): Add BASE declaration for crypto vector.
6891 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6892 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6893 Add crypto vector intrinsic definition.
6894 (vbrev): Ditto.
6895 (vclz): Ditto.
6896 (vctz): Ditto.
6897 (vwsll): Ditto.
6898 (vandn): Ditto.
6899 (vbrev8): Ditto.
6900 (vrev8): Ditto.
6901 (vrol): Ditto.
6902 (vror): Ditto.
6903 (vclmul): Ditto.
6904 (vclmulh): Ditto.
6905 (vghsh): Ditto.
6906 (vgmul): Ditto.
6907 (vaesef): Ditto.
6908 (vaesem): Ditto.
6909 (vaesdf): Ditto.
6910 (vaesdm): Ditto.
6911 (vaesz): Ditto.
6912 (vaeskf1): Ditto.
6913 (vaeskf2): Ditto.
6914 (vsha2ms): Ditto.
6915 (vsha2ch): Ditto.
6916 (vsha2cl): Ditto.
6917 (vsm4k): Ditto.
6918 (vsm4r): Ditto.
6919 (vsm3me): Ditto.
6920 (vsm3c): Ditto.
6921 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6922 Add new function_shape for crypto vector.
6923 (struct crypto_vi_def): Ditto.
6924 (struct crypto_vv_no_op_type_def): Ditto.
6925 (SHAPE): Add SHAPE declaration of crypto vector.
6926 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6927 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6928 Add new data type for crypto vector.
6929 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6930 (vuint32mf2_t): Ditto.
6931 (vuint32m1_t): Ditto.
6932 (vuint32m2_t): Ditto.
6933 (vuint32m4_t): Ditto.
6934 (vuint32m8_t): Ditto.
6935 (vuint64m1_t): Ditto.
6936 (vuint64m2_t): Ditto.
6937 (vuint64m4_t): Ditto.
6938 (vuint64m8_t): Ditto.
6939 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6940 Add new data struct for crypto vector.
6941 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6942 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6943 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6945 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
6947 PR sanitizer/113251
6948 * varasm.cc (assemble_function_label_raw): Do not call
6949 asan_function_start () without the current function.
6951 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6953 PR target/113225
6954 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
6955 extern and kernel_helper attributed function decls.
6957 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6959 * btfout.cc (output_btf_strs): Changed.
6961 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6963 * config/gcn/mkoffload.cc (main): Handle gfx1100
6964 when setting the default XNACK.
6966 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6968 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
6969 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
6970 (ASM_SPEC): Handle gfx1100.
6971 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
6972 (enum gcn_isa): Add ISA_RDNA3.
6973 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
6974 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6975 * config/gcn/gcn.cc (gcn_option_override,
6976 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
6977 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
6978 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6979 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
6980 with gfx1100.
6981 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
6982 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
6983 __gfx1100__.
6984 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6985 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
6986 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
6987 (isa_has_combined_avgprs, main): Handle gfx1100.
6988 * config/gcn/t-omp-device (isa): Add gfx1100.
6990 2024-01-08 Richard Biener <rguenther@suse.de>
6992 * doc/invoke.texi (-mmovbe): Clarify.
6994 2024-01-08 Richard Biener <rguenther@suse.de>
6996 PR tree-optimization/113026
6997 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
6998 Avoid an epilog in more cases.
6999 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
7000 epilogues niter upper bounds and estimates.
7002 2024-01-08 Jakub Jelinek <jakub@redhat.com>
7004 PR tree-optimization/113228
7005 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
7007 2024-01-08 Jakub Jelinek <jakub@redhat.com>
7009 PR tree-optimization/113120
7010 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
7011 large _BitInt zero INTEGER_CST PHI argument.
7013 2024-01-08 Jakub Jelinek <jakub@redhat.com>
7015 PR tree-optimization/113119
7016 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
7017 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
7018 is before REALPART_EXPR.
7020 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
7022 PR target/112952
7023 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
7024 range when diagnosing attribute "io" and "io_low" are out of range.
7025 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
7026 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
7027 in contexts other than static storage.
7028 (avr_asm_output_aligned_decl_common): Move output of decls with
7029 attribute "address", "io", and "io_low" to...
7030 (avr_output_addr_attrib): ...this new function.
7031 (avr_asm_asm_output_aligned_bss): Remove output for decls with
7032 attribute "address", "io", and "io_low".
7033 (avr_encode_section_info): Rectify handling of decls with attribute
7034 "address", "io", and "io_low".
7036 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
7038 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
7039 (elf_flags): Remove XNACK from the default value.
7040 (main): Set a default XNACK according to the arch.
7042 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
7044 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
7045 (process_asm): Don't count avgprs.
7047 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
7049 * config/i386/i386.opt: Add supported sub-features.
7050 * doc/extend.texi: Add description for target attribute.
7052 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
7054 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
7056 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
7057 Uros Bizjak <ubizjak@gmail.com>
7059 PR target/113231
7060 * config/i386/i386-features.cc (compute_convert_gain): Include
7061 the overhead of explicit load and store (movd) instructions when
7062 converting non-store scalar operations with memory destinations.
7063 Various indentation whitespace fixes.
7065 2024-01-07 Tamar Christina <tamar.christina@arm.com>
7067 * config/arm/neon.md (cbranch<mode>4): New.
7069 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7071 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
7073 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
7075 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
7077 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7079 PR target/113248
7080 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
7081 Update the MAX_SEW.
7083 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7085 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
7086 (variable_vectorized_p): Teach loop invariant.
7087 (has_unexpected_spills_p): Ditto.
7089 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7091 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
7092 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
7093 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
7095 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
7097 PR target/113104
7098 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
7099 (aarch64-vect-compare-costs): ...this.
7100 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
7101 Replace with...
7102 (-param=aarch64-vect-compare-costs=): ...this new param.
7103 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
7104 Don't disable it when vectorizing for Advanced SIMD only.
7105 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
7106 whenever aarch64_vect_compare_costs is true.
7108 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
7110 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
7111 Modify the method of determining the memory offset of [x]vld/[x]vst.
7112 (lasx_mxst_<lasxfmt_f>): Likewise.
7113 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
7114 (loongarch_address_insns): Likewise.
7115 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
7116 (lsx_st_<lsxfmt_f>): Likewise.
7117 * config/loongarch/predicates.md (aq10b_operand): Likewise.
7118 (aq10h_operand): Likewise.
7119 (aq10w_operand): Likewise.
7120 (aq10d_operand): Likewise.
7122 2024-01-05 Alex Coplan <alex.coplan@arm.com>
7124 PR target/113217
7125 * config/aarch64/aarch64-ldp-fusion.cc
7126 (ldp_bb_info::try_fuse_pair): If the second access can throw,
7127 narrow the move range to exactly that insn.
7129 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
7131 * asan.cc (asan_function_start): Drop switch_to_section ().
7132 (asan_emit_stack_protection): Set .LASANPC alignment.
7133 * config/i386/i386.cc: Use assemble_function_label_raw ()
7134 instead of ASM_OUTPUT_LABEL ().
7135 * config/s390/s390.cc (s390_asm_output_function_label):
7136 Likewise.
7137 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
7138 * final.cc (final_start_function_1): Drop
7139 asan_function_start ().
7140 * output.h (assemble_function_label_raw): New function.
7141 * varasm.cc (assemble_function_label_raw): Likewise.
7143 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
7145 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
7146 Use ASM_OUTPUT_FUNCTION_LABEL ().
7147 * config/alpha/alpha.cc (alpha_start_function): Likewise.
7148 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
7149 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
7150 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
7151 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
7152 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
7153 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
7154 * config/ia64/ia64.cc (ia64_start_function): Likewise.
7155 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
7156 Likewise.
7157 * config/microblaze/microblaze.cc (microblaze_function_prologue):
7158 Likewise.
7159 * config/mips/mips.cc (mips_start_unique_function): Return the
7160 tree.
7161 (mips_start_function_definition): Use
7162 ASM_OUTPUT_FUNCTION_LABEL ().
7163 (mips_finish_stub): Pass the tree to
7164 mips_start_function_definition ().
7165 (mips16_build_function_stub): Likewise.
7166 (mips16_build_call_stub): Likewise.
7167 (mips_output_function_prologue): Likewise.
7168 * config/pa/pa.cc (pa_output_function_label): Use
7169 ASM_OUTPUT_FUNCTION_LABEL ().
7170 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
7171 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
7172 Likewise.
7173 (rs6000_xcoff_declare_function_name): Likewise.
7175 2024-01-05 Jakub Jelinek <jakub@redhat.com>
7177 PR tree-optimization/113201
7178 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
7179 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
7181 2024-01-05 Jakub Jelinek <jakub@redhat.com>
7183 PR tree-optimization/90693
7184 * tree-ssa-math-opts.cc (match_single_bit_test): If
7185 tree_expr_nonzero_p (arg), remember it in the second argument to
7186 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
7187 arg ^ (arg - 1) > arg - 1.
7188 * internal-fn.cc (expand_POPCOUNT): If second argument to
7189 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
7190 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
7192 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
7194 * config/riscv/riscv-v.cc (expand_load_store):
7195 Remove `value`.
7196 (expand_cond_len_op): Ditto.
7197 (expand_gather_scatter): Ditto.
7198 (expand_lanes_load_store): Ditto.
7199 (expand_fold_extract_last): Ditto.
7201 2024-01-05 Pan Li <pan2.li@intel.com>
7203 Revert:
7204 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
7206 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
7207 Add new function_base for crypto vector.
7208 (class bitmanip): Ditto.
7209 (class b_reverse):Ditto.
7210 (class vwsll): Ditto.
7211 (class clmul): Ditto.
7212 (class vg_nhab): Ditto.
7213 (class crypto_vv):Ditto.
7214 (class crypto_vi):Ditto.
7215 (class vaeskf2_vsm3c):Ditto.
7216 (class vsm3me): Ditto.
7217 (BASE): Add BASE declaration for crypto vector.
7218 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
7219 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
7220 Add crypto vector intrinsic definition.
7221 (vbrev): Ditto.
7222 (vclz): Ditto.
7223 (vctz): Ditto.
7224 (vwsll): Ditto.
7225 (vandn): Ditto.
7226 (vbrev8): Ditto.
7227 (vrev8): Ditto.
7228 (vrol): Ditto.
7229 (vror): Ditto.
7230 (vclmul): Ditto.
7231 (vclmulh): Ditto.
7232 (vghsh): Ditto.
7233 (vgmul): Ditto.
7234 (vaesef): Ditto.
7235 (vaesem): Ditto.
7236 (vaesdf): Ditto.
7237 (vaesdm): Ditto.
7238 (vaesz): Ditto.
7239 (vaeskf1): Ditto.
7240 (vaeskf2): Ditto.
7241 (vsha2ms): Ditto.
7242 (vsha2ch): Ditto.
7243 (vsha2cl): Ditto.
7244 (vsm4k): Ditto.
7245 (vsm4r): Ditto.
7246 (vsm3me): Ditto.
7247 (vsm3c): Ditto.
7248 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
7249 Add new function_shape for crypto vector.
7250 (struct crypto_vi_def): Ditto.
7251 (struct crypto_vv_no_op_type_def): Ditto.
7252 (SHAPE): Add SHAPE declaration of crypto vector.
7253 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
7254 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7255 Add new data type for crypto vector.
7256 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7257 (vuint32mf2_t): Ditto.
7258 (vuint32m1_t): Ditto.
7259 (vuint32m2_t): Ditto.
7260 (vuint32m4_t): Ditto.
7261 (vuint32m8_t): Ditto.
7262 (vuint64m1_t): Ditto.
7263 (vuint64m2_t): Ditto.
7264 (vuint64m4_t): Ditto.
7265 (vuint64m8_t): Ditto.
7266 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7267 Add new data struct for crypto vector.
7268 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7269 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7270 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7272 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
7274 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
7275 Add new function_base for crypto vector.
7276 (class bitmanip): Ditto.
7277 (class b_reverse):Ditto.
7278 (class vwsll): Ditto.
7279 (class clmul): Ditto.
7280 (class vg_nhab): Ditto.
7281 (class crypto_vv):Ditto.
7282 (class crypto_vi):Ditto.
7283 (class vaeskf2_vsm3c):Ditto.
7284 (class vsm3me): Ditto.
7285 (BASE): Add BASE declaration for crypto vector.
7286 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
7287 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
7288 Add crypto vector intrinsic definition.
7289 (vbrev): Ditto.
7290 (vclz): Ditto.
7291 (vctz): Ditto.
7292 (vwsll): Ditto.
7293 (vandn): Ditto.
7294 (vbrev8): Ditto.
7295 (vrev8): Ditto.
7296 (vrol): Ditto.
7297 (vror): Ditto.
7298 (vclmul): Ditto.
7299 (vclmulh): Ditto.
7300 (vghsh): Ditto.
7301 (vgmul): Ditto.
7302 (vaesef): Ditto.
7303 (vaesem): Ditto.
7304 (vaesdf): Ditto.
7305 (vaesdm): Ditto.
7306 (vaesz): Ditto.
7307 (vaeskf1): Ditto.
7308 (vaeskf2): Ditto.
7309 (vsha2ms): Ditto.
7310 (vsha2ch): Ditto.
7311 (vsha2cl): Ditto.
7312 (vsm4k): Ditto.
7313 (vsm4r): Ditto.
7314 (vsm3me): Ditto.
7315 (vsm3c): Ditto.
7316 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
7317 Add new function_shape for crypto vector.
7318 (struct crypto_vi_def): Ditto.
7319 (struct crypto_vv_no_op_type_def): Ditto.
7320 (SHAPE): Add SHAPE declaration of crypto vector.
7321 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
7322 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7323 Add new data type for crypto vector.
7324 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7325 (vuint32mf2_t): Ditto.
7326 (vuint32m1_t): Ditto.
7327 (vuint32m2_t): Ditto.
7328 (vuint32m4_t): Ditto.
7329 (vuint32m8_t): Ditto.
7330 (vuint64m1_t): Ditto.
7331 (vuint64m2_t): Ditto.
7332 (vuint64m4_t): Ditto.
7333 (vuint64m8_t): Ditto.
7334 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7335 Add new data struct for crypto vector.
7336 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7337 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7338 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7340 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7342 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7344 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
7346 PR tree-optimization/113186
7347 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
7348 Match `^` with the `==` for 1bit integral types.
7349 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
7350 integral types.
7352 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7354 * toplev.cc (general_init): Pass lang_mask to urlifier.
7356 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7358 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
7359 param.
7360 (diagnostic_context::make_option_url): Update for lang_mask param.
7361 * gcc-urlifier.cc: Include "opts.h" and "options.h".
7362 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
7363 (gcc_urlifier::m_lang_mask): New field.
7364 (doc_urls): Make static.
7365 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
7366 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7367 Look for an option by name before trying a binary search in
7368 doc_urls.
7369 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7370 (gcc_urlifier::get_url_suffix_for_option): New.
7371 (make_gcc_urlifier): Add lang_mask param.
7372 (selftest::gcc_urlifier_cc_tests): Update for above changes.
7373 Verify that a URL is found for "-fpack-struct".
7374 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
7375 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
7376 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
7377 to make_gcc_urlifier.
7378 * opts-diagnostic.h (get_option_url): Add lang_mask param.
7379 * opts.cc (get_option_html_page): Remove special-casing for
7380 analyzer and LTO.
7381 (get_option_url_suffix): New.
7382 (get_option_url): Reimplement.
7383 (selftest::test_get_option_html_page): Rename to...
7384 (selftest::test_get_option_url_suffix): ...this and update for
7385 above changes.
7386 (selftest::opts_cc_tests): Update for renaming.
7387 * opts.h: Include "rich-location.h".
7388 (get_option_url_suffix): New decl.
7390 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7392 * Makefile.in (ALL_OPT_URL_FILES): New.
7393 (GCC_OBJS): Add options-urls.o.
7394 (OBJS): Likewise.
7395 (OBJS-libcommon): Likewise.
7396 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
7397 inputs to opt-gather.awk.
7398 (options-urls.cc): New Makefile target.
7399 * opt-functions.awk (url_suffix): New function.
7400 (lang_url_suffix): New function.
7401 * options-urls-cc-gen.awk: New file.
7402 * opts.h (get_opt_url_suffix): New decl.
7404 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7406 * params.opt.urls: New file, autogenerated by
7407 regenerate-opt-urls.py.
7409 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7411 * common.opt.urls: New file, autogenerated by
7412 regenerate-opt-urls.py.
7413 * config/aarch64/aarch64.opt.urls: Likewise.
7414 * config/alpha/alpha.opt.urls: Likewise.
7415 * config/alpha/elf.opt.urls: Likewise.
7416 * config/arc/arc-tables.opt.urls: Likewise.
7417 * config/arc/arc.opt.urls: Likewise.
7418 * config/arm/arm-tables.opt.urls: Likewise.
7419 * config/arm/arm.opt.urls: Likewise.
7420 * config/arm/vxworks.opt.urls: Likewise.
7421 * config/avr/avr.opt.urls: Likewise.
7422 * config/bpf/bpf.opt.urls: Likewise.
7423 * config/c6x/c6x-tables.opt.urls: Likewise.
7424 * config/c6x/c6x.opt.urls: Likewise.
7425 * config/cris/cris.opt.urls: Likewise.
7426 * config/cris/elf.opt.urls: Likewise.
7427 * config/csky/csky.opt.urls: Likewise.
7428 * config/csky/csky_tables.opt.urls: Likewise.
7429 * config/darwin.opt.urls: Likewise.
7430 * config/dragonfly.opt.urls: Likewise.
7431 * config/epiphany/epiphany.opt.urls: Likewise.
7432 * config/fr30/fr30.opt.urls: Likewise.
7433 * config/freebsd.opt.urls: Likewise.
7434 * config/frv/frv.opt.urls: Likewise.
7435 * config/ft32/ft32.opt.urls: Likewise.
7436 * config/fused-madd.opt.urls: Likewise.
7437 * config/g.opt.urls: Likewise.
7438 * config/gcn/gcn.opt.urls: Likewise.
7439 * config/gnu-user.opt.urls: Likewise.
7440 * config/h8300/h8300.opt.urls: Likewise.
7441 * config/hpux11.opt.urls: Likewise.
7442 * config/i386/cygming.opt.urls: Likewise.
7443 * config/i386/cygwin.opt.urls: Likewise.
7444 * config/i386/djgpp.opt.urls: Likewise.
7445 * config/i386/i386.opt.urls: Likewise.
7446 * config/i386/mingw-w64.opt.urls: Likewise.
7447 * config/i386/mingw.opt.urls: Likewise.
7448 * config/i386/nto.opt.urls: Likewise.
7449 * config/ia64/ia64.opt.urls: Likewise.
7450 * config/ia64/ilp32.opt.urls: Likewise.
7451 * config/ia64/vms.opt.urls: Likewise.
7452 * config/iq2000/iq2000.opt.urls: Likewise.
7453 * config/linux-android.opt.urls: Likewise.
7454 * config/linux.opt.urls: Likewise.
7455 * config/lm32/lm32.opt.urls: Likewise.
7456 * config/loongarch/loongarch.opt.urls: Likewise.
7457 * config/lynx.opt.urls: Likewise.
7458 * config/m32c/m32c.opt.urls: Likewise.
7459 * config/m32r/m32r.opt.urls: Likewise.
7460 * config/m68k/ieee.opt.urls: Likewise.
7461 * config/m68k/m68k-tables.opt.urls: Likewise.
7462 * config/m68k/m68k.opt.urls: Likewise.
7463 * config/m68k/uclinux.opt.urls: Likewise.
7464 * config/mcore/mcore.opt.urls: Likewise.
7465 * config/microblaze/microblaze.opt.urls: Likewise.
7466 * config/mips/mips-tables.opt.urls: Likewise.
7467 * config/mips/mips.opt.urls: Likewise.
7468 * config/mips/sde.opt.urls: Likewise.
7469 * config/mmix/mmix.opt.urls: Likewise.
7470 * config/mn10300/mn10300.opt.urls: Likewise.
7471 * config/moxie/moxie.opt.urls: Likewise.
7472 * config/msp430/msp430.opt.urls: Likewise.
7473 * config/nds32/nds32-elf.opt.urls: Likewise.
7474 * config/nds32/nds32-linux.opt.urls: Likewise.
7475 * config/nds32/nds32.opt.urls: Likewise.
7476 * config/netbsd-elf.opt.urls: Likewise.
7477 * config/netbsd.opt.urls: Likewise.
7478 * config/nios2/elf.opt.urls: Likewise.
7479 * config/nios2/nios2.opt.urls: Likewise.
7480 * config/nvptx/nvptx-gen.opt.urls: Likewise.
7481 * config/nvptx/nvptx.opt.urls: Likewise.
7482 * config/openbsd.opt.urls: Likewise.
7483 * config/or1k/elf.opt.urls: Likewise.
7484 * config/or1k/or1k.opt.urls: Likewise.
7485 * config/pa/pa-hpux.opt.urls: Likewise.
7486 * config/pa/pa-hpux1010.opt.urls: Likewise.
7487 * config/pa/pa-hpux1111.opt.urls: Likewise.
7488 * config/pa/pa-hpux1131.opt.urls: Likewise.
7489 * config/pa/pa.opt.urls: Likewise.
7490 * config/pa/pa64-hpux.opt.urls: Likewise.
7491 * config/pdp11/pdp11.opt.urls: Likewise.
7492 * config/pru/pru.opt.urls: Likewise.
7493 * config/riscv/riscv.opt.urls: Likewise.
7494 * config/rl78/rl78.opt.urls: Likewise.
7495 * config/rpath.opt.urls: Likewise.
7496 * config/rs6000/476.opt.urls: Likewise.
7497 * config/rs6000/aix64.opt.urls: Likewise.
7498 * config/rs6000/darwin.opt.urls: Likewise.
7499 * config/rs6000/linux64.opt.urls: Likewise.
7500 * config/rs6000/rs6000-tables.opt.urls: Likewise.
7501 * config/rs6000/rs6000.opt.urls: Likewise.
7502 * config/rs6000/sysv4.opt.urls: Likewise.
7503 * config/rtems.opt.urls: Likewise.
7504 * config/rx/elf.opt.urls: Likewise.
7505 * config/rx/rx.opt.urls: Likewise.
7506 * config/s390/s390.opt.urls: Likewise.
7507 * config/s390/tpf.opt.urls: Likewise.
7508 * config/sh/sh.opt.urls: Likewise.
7509 * config/sh/superh.opt.urls: Likewise.
7510 * config/sol2.opt.urls: Likewise.
7511 * config/sparc/long-double-switch.opt.urls: Likewise.
7512 * config/sparc/sparc.opt.urls: Likewise.
7513 * config/stormy16/stormy16.opt.urls: Likewise.
7514 * config/v850/v850.opt.urls: Likewise.
7515 * config/vax/elf.opt.urls: Likewise.
7516 * config/vax/vax.opt.urls: Likewise.
7517 * config/visium/visium.opt.urls: Likewise.
7518 * config/vms/vms.opt.urls: Likewise.
7519 * config/vxworks-smp.opt.urls: Likewise.
7520 * config/vxworks.opt.urls: Likewise.
7521 * config/xtensa/elf.opt.urls: Likewise.
7522 * config/xtensa/uclinux.opt.urls: Likewise.
7523 * config/xtensa/xtensa.opt.urls: Likewise.
7524 * config/bfin/bfin.opt.urls: New file.
7526 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7528 * Makefile.in (OPT_URLS_HTML_DEPS): New.
7529 (regenerate-opt-urls): New target.
7530 (regenerate-opt-urls-unit-test): New target.
7531 * doc/options.texi (Option properties): Add UrlSuffix and
7532 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
7533 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
7534 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
7535 and Makefile.in's OPT_URLS_HTML_DEPS.
7536 (Anatomy of a Target Back End): Add
7537 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
7538 * regenerate-opt-urls.py: New file.
7540 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7542 * diagnostic-format-sarif.cc
7543 (sarif_builder::make_logical_location_object): Convert to...
7544 (make_sarif_logical_location_object): ...this.
7545 (sarif_builder::set_any_logical_locs_arr): Update for above
7546 change.
7547 (sarif_builder::make_thread_flow_location_object): Call
7548 maybe_add_sarif_properties on each diagnostic_event.
7549 * diagnostic-format-sarif.h (class logical_location): New forward
7550 decl.
7551 (make_sarif_logical_location_object): New decl.
7552 * diagnostic-path.h (class sarif_object): New forward decl.
7553 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
7555 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
7556 Patrick Lin <patrick@andestech.com>
7557 Rufus Chen <rufus@andestech.com>
7558 Monk Chiang <monk.chiang@sifive.com>
7560 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
7561 with Nan-boxing value.
7562 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
7564 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
7565 Jeff Law <jlaw@ventanamicro.com>
7567 PR rtl-optimization/104914
7568 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
7569 a sign or zero extension is only required if the modified field
7570 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
7571 targets, don't refer to the temporarily incorrectly extended value
7572 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
7574 2024-01-04 Pan Li <pan2.li@intel.com>
7576 Revert:
7577 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7579 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7581 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7583 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7585 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
7587 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
7588 offset of fcsr.
7590 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7592 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
7593 (compute_nregs_for_mode): Refine LMUL.
7594 (max_number_of_live_regs): Ditto.
7595 (compute_estimated_lmul): Ditto.
7596 (has_unexpected_spills_p): Ditto.
7598 2024-01-04 Li Wei <liwei@loongson.cn>
7600 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
7601 Remove useless forward declaration.
7602 (loongarch_is_even_extraction): Remove useless forward declaration.
7603 (loongarch_try_expand_lsx_vshuf_const): Removed.
7604 (loongarch_expand_vec_perm_const_1): Merged.
7605 (loongarch_is_double_duplicate): Removed.
7606 (loongarch_is_center_extraction): Ditto.
7607 (loongarch_is_reversing_permutation): Ditto.
7608 (loongarch_is_di_misalign_extract): Ditto.
7609 (loongarch_is_si_misalign_extract): Ditto.
7610 (loongarch_is_lasx_lowpart_extract): Ditto.
7611 (loongarch_is_op_reverse_perm): Ditto.
7612 (loongarch_is_single_op_perm): Ditto.
7613 (loongarch_is_divisible_perm): Ditto.
7614 (loongarch_is_triple_stride_extract): Ditto.
7615 (loongarch_expand_vec_perm_const_2): Merged.
7616 (loongarch_expand_vec_perm_const): New.
7617 (loongarch_vectorize_vec_perm_const): Adjust.
7619 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
7621 * omp-general.cc: Fix comment typos and misplaced/confusing
7622 comments. Delete redundant include of omp-general.h.
7624 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7626 PR rtl-optimization/104914
7627 * config/mips/mips.md (insqisi_extended): New patterns.
7628 (inshisi_extended): Ditto.
7630 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7632 * config/mips/mips.cc (mips_insn_cost): New function.
7634 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7636 * config/mips/mips.md (perf_ratio): New attribute.
7638 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7640 PR target/113206
7641 PR target/113209
7642 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
7643 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
7644 blocks belong to infinite loop.
7645 (pre_vsetvl::emit_vsetvl): Remove fake edges.
7646 * config/riscv/t-riscv: Add a new include file.
7648 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7650 * config/riscv/vector.md: Fix indent.
7652 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7654 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
7655 OMP_CLAUSE__SIMDUID_.
7656 * tree.cc (omp_clause_num_ops): Update position of entry for
7657 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
7658 (omp_clause_code_name): Likewise.
7660 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7662 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
7663 printing of FUNC_MAP/IND_FUNC_MAP labels.
7665 2024-01-03 Jakub Jelinek <jakub@redhat.com>
7667 * gcc.cc (process_command): Update copyright notice dates.
7668 * gcov-dump.cc (print_version): Ditto.
7669 * gcov.cc (print_version): Ditto.
7670 * gcov-tool.cc (print_version): Ditto.
7671 * gengtype.cc (create_file): Ditto.
7672 * doc/cpp.texi: Bump @copying's copyright year.
7673 * doc/cppinternals.texi: Ditto.
7674 * doc/gcc.texi: Ditto.
7675 * doc/gccint.texi: Ditto.
7676 * doc/gcov.texi: Ditto.
7677 * doc/install.texi: Ditto.
7678 * doc/invoke.texi: Ditto.
7680 2024-01-03 Xi Ruoyao <xry111@xry111.site>
7682 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
7683 (fmin<mode>3): Likewise.
7684 (reduc_fmax_scal_<mode>3): New define_expand.
7685 (reduc_fmin_scal_<mode>3): Likewise.
7687 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7689 PR target/113112
7690 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
7691 (max_number_of_live_regs): Ditto.
7692 (has_unexpected_spills_p): Ditto.
7694 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
7695 Jin Ma <jinma@linux.alibaba.com>
7696 Xianmiao Qu <cooper.qu@linux.alibaba.com>
7697 Christoph Müllner <christoph.muellner@vrull.eu>
7699 * config/riscv/vector.md:
7700 Use vector_length_operand for vsetvl patterns.
7702 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7704 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
7705 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
7707 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
7709 * config/aarch64/aarch64-tuning-flags.def
7710 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
7711 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
7712 * config/aarch64/aarch64.cc
7713 (aarch64_override_options_internal): Set
7714 param_fully_pipelined_fma according to tuning option.
7715 * config/aarch64/tuning_models/ampere1.h: Add
7716 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
7717 * config/aarch64/tuning_models/ampere1a.h: Likewise.
7718 * config/aarch64/tuning_models/ampere1b.h: Likewise.
7720 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7722 * config/riscv/vector-crypto.md: Modify copyright year.
7724 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7726 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
7728 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
7730 * config.in: Regenerate.
7731 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
7732 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
7733 Added TLS Le Relax support.
7734 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
7735 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
7736 * configure: Regenerate.
7737 * configure.ac: Check if binutils supports TLS le relax.
7739 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7741 * config/riscv/iterators.md: Add rotate insn name.
7742 * config/riscv/riscv.md: Add new insns name for crypto vector.
7743 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
7744 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
7745 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
7747 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7749 PR target/113112
7750 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
7751 pointer type liveness count.
7752 \f
7753 Copyright (C) 2024 Free Software Foundation, Inc.
7755 Copying and distribution of this file, with or without modification,
7756 are permitted in any medium without royalty provided the copyright
7757 notice and this notice are preserved.