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* config/sh/sh-protos.h (sh_function_arg): Delete.
[official-gcc.git] / gcc / config / sh / sh.h
blobcb78667d8f0b31f16e4646aaaeb06c6115b8d0b6
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #include "config/vxworks-dummy.h"
28
29 #define TARGET_VERSION \
30 fputs (" (Hitachi SH)", stderr);
31
32 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
33 include it here, because bconfig.h is also included by gencodes.c . */
34 /* ??? No longer true. */
35 extern int code_for_indirect_jump_scratch;
36
37 #define TARGET_CPU_CPP_BUILTINS() \
38 do { \
39 builtin_define ("__sh__"); \
40 builtin_assert ("cpu=sh"); \
41 builtin_assert ("machine=sh"); \
42 switch ((int) sh_cpu) \
43 { \
44 case PROCESSOR_SH1: \
45 builtin_define ("__sh1__"); \
46 break; \
47 case PROCESSOR_SH2: \
48 builtin_define ("__sh2__"); \
49 break; \
50 case PROCESSOR_SH2E: \
51 builtin_define ("__SH2E__"); \
52 break; \
53 case PROCESSOR_SH2A: \
54 builtin_define ("__SH2A__"); \
55 builtin_define (TARGET_SH2A_DOUBLE \
56 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
57 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
58 : "__SH2A_NOFPU__"); \
59 break; \
60 case PROCESSOR_SH3: \
61 builtin_define ("__sh3__"); \
62 builtin_define ("__SH3__"); \
63 if (TARGET_HARD_SH4) \
64 builtin_define ("__SH4_NOFPU__"); \
65 break; \
66 case PROCESSOR_SH3E: \
67 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
68 break; \
69 case PROCESSOR_SH4: \
70 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
71 break; \
72 case PROCESSOR_SH4A: \
73 builtin_define ("__SH4A__"); \
74 builtin_define (TARGET_SH4 \
75 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
76 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
77 : "__SH4_NOFPU__"); \
78 break; \
79 case PROCESSOR_SH5: \
80 { \
81 builtin_define_with_value ("__SH5__", \
82 TARGET_SHMEDIA64 ? "64" : "32", 0); \
83 builtin_define_with_value ("__SHMEDIA__", \
84 TARGET_SHMEDIA ? "1" : "0", 0); \
85 if (! TARGET_FPU_DOUBLE) \
86 builtin_define ("__SH4_NOFPU__"); \
87 } \
88 } \
89 if (TARGET_FPU_ANY) \
90 builtin_define ("__SH_FPU_ANY__"); \
91 if (TARGET_FPU_DOUBLE) \
92 builtin_define ("__SH_FPU_DOUBLE__"); \
93 if (TARGET_HITACHI) \
94 builtin_define ("__HITACHI__"); \
95 if (TARGET_FMOVD) \
96 builtin_define ("__FMOVD_ENABLED__"); \
97 builtin_define (TARGET_LITTLE_ENDIAN \
98 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
99 } while (0)
100
101 #define CAN_DEBUG_WITHOUT_FP
102
103 /* Value should be nonzero if functions must have frame pointers.
104 Zero means the frame pointer need not be set up (and parms may be accessed
105 via the stack pointer) in functions that seem suitable. */
106
107 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
108 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
109 #endif
110
111 #define CONDITIONAL_REGISTER_USAGE do \
112 { \
113 int regno; \
114 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
115 if (! VALID_REGISTER_P (regno)) \
116 fixed_regs[regno] = call_used_regs[regno] = 1; \
117 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
118 if (TARGET_SH5) \
119 { \
120 call_used_regs[FIRST_GENERAL_REG + 8] \
121 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
122 call_really_used_regs[FIRST_GENERAL_REG + 8] \
123 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
124 } \
125 if (TARGET_SHMEDIA) \
126 { \
127 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
128 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
129 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
130 } \
131 if (flag_pic) \
132 { \
133 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
134 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
135 } \
136 /* Renesas saves and restores mac registers on call. */ \
137 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
138 { \
139 call_really_used_regs[MACH_REG] = 0; \
140 call_really_used_regs[MACL_REG] = 0; \
141 } \
142 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
143 regno <= LAST_FP_REG; regno += 2) \
144 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
145 if (TARGET_SHMEDIA) \
146 { \
147 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
148 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
149 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
150 } \
151 else \
152 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
153 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
154 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
155 } while (0)
156 \f
157 /* Nonzero if this is an ELF target - compile time only */
158 #define TARGET_ELF 0
159
160 /* Nonzero if we should generate code using type 2E insns. */
161 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
162
163 /* Nonzero if we should generate code using type 2A insns. */
164 #define TARGET_SH2A TARGET_HARD_SH2A
165 /* Nonzero if we should generate code using type 2A SF insns. */
166 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
167 /* Nonzero if we should generate code using type 2A DF insns. */
168 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
169
170 /* Nonzero if we should generate code using type 3E insns. */
171 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
172
173 /* Nonzero if the cache line size is 32. */
174 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
175
176 /* Nonzero if we schedule for a superscalar implementation. */
177 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
178
179 /* Nonzero if the target has separate instruction and data caches. */
180 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
181
182 /* Nonzero if a double-precision FPU is available. */
183 #define TARGET_FPU_DOUBLE \
184 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
185
186 /* Nonzero if an FPU is available. */
187 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
188
189 /* Nonzero if we should generate code using type 4 insns. */
190 #undef TARGET_SH4
191 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
192
193 /* Nonzero if we're generating code for the common subset of
194 instructions present on both SH4a and SH4al-dsp. */
195 #define TARGET_SH4A_ARCH TARGET_SH4A
196
197 /* Nonzero if we're generating code for SH4a, unless the use of the
198 FPU is disabled (which makes it compatible with SH4al-dsp). */
199 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
200
201 /* Nonzero if we should generate code using the SHcompact instruction
202 set and 32-bit ABI. */
203 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
204
205 /* Nonzero if we should generate code using the SHmedia instruction
206 set and ABI. */
207 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
208
209 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
210 ABI. */
211 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
212
213 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
214 ABI. */
215 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
216
217 /* Nonzero if we should generate code using SHmedia FPU instructions. */
218 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
219
220 /* This is not used by the SH2E calling convention */
221 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
222 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
223 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
224
225 #ifndef TARGET_CPU_DEFAULT
226 #define TARGET_CPU_DEFAULT SELECT_SH1
227 #define SUPPORT_SH1 1
228 #define SUPPORT_SH2E 1
229 #define SUPPORT_SH4 1
230 #define SUPPORT_SH4_SINGLE 1
231 #define SUPPORT_SH2A 1
232 #define SUPPORT_SH2A_SINGLE 1
233 #endif
234
235 #define TARGET_DIVIDE_INV \
236 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
237 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
238 || sh_div_strategy == SH_DIV_INV_CALL \
239 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
240 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
241 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
242 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
243 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
244 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
245 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
246 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
247 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
248 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
249 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
250 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
251
252 #define SELECT_SH1 (MASK_SH1)
253 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
254 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
255 | MASK_FPU_SINGLE)
256 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
257 | MASK_HARD_SH2A_DOUBLE \
258 | MASK_SH2 | MASK_SH1)
259 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
260 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
261 | MASK_SH1 | MASK_FPU_SINGLE)
262 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
263 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
264 | MASK_SH2 | MASK_SH1)
265 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
266 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
267 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
268 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
269 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
270 | SELECT_SH3)
271 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
272 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
273 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
274 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
275 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
276 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
277 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
278 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
279 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
280 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
281 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
282
283 #if SUPPORT_SH1
284 #define SUPPORT_SH2 1
285 #endif
286 #if SUPPORT_SH2
287 #define SUPPORT_SH3 1
288 #define SUPPORT_SH2A_NOFPU 1
289 #endif
290 #if SUPPORT_SH3
291 #define SUPPORT_SH4_NOFPU 1
292 #endif
293 #if SUPPORT_SH4_NOFPU
294 #define SUPPORT_SH4A_NOFPU 1
295 #define SUPPORT_SH4AL 1
296 #endif
297
298 #if SUPPORT_SH2E
299 #define SUPPORT_SH3E 1
300 #define SUPPORT_SH2A_SINGLE_ONLY 1
301 #endif
302 #if SUPPORT_SH3E
303 #define SUPPORT_SH4_SINGLE_ONLY 1
304 #endif
305 #if SUPPORT_SH4_SINGLE_ONLY
306 #define SUPPORT_SH4A_SINGLE_ONLY 1
307 #endif
308
309 #if SUPPORT_SH4
310 #define SUPPORT_SH4A 1
311 #endif
312
313 #if SUPPORT_SH4_SINGLE
314 #define SUPPORT_SH4A_SINGLE 1
315 #endif
316
317 #if SUPPORT_SH5_COMPAT
318 #define SUPPORT_SH5_32MEDIA 1
319 #endif
320
321 #if SUPPORT_SH5_COMPACT_NOFPU
322 #define SUPPORT_SH5_32MEDIA_NOFPU 1
323 #endif
324
325 #define SUPPORT_ANY_SH5_32MEDIA \
326 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
327 #define SUPPORT_ANY_SH5_64MEDIA \
328 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
329 #define SUPPORT_ANY_SH5 \
330 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
331
332 /* Reset all target-selection flags. */
333 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
334 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
335 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
336
337 /* This defaults us to big-endian. */
338 #ifndef TARGET_ENDIAN_DEFAULT
339 #define TARGET_ENDIAN_DEFAULT 0
340 #endif
341
342 #ifndef TARGET_OPT_DEFAULT
343 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
344 #endif
345
346 #define TARGET_DEFAULT \
347 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
348
349 #ifndef SH_MULTILIB_CPU_DEFAULT
350 #define SH_MULTILIB_CPU_DEFAULT "m1"
351 #endif
352
353 #if TARGET_ENDIAN_DEFAULT
354 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
355 #else
356 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
357 #endif
358
359 #define CPP_SPEC " %(subtarget_cpp_spec) "
360
361 #ifndef SUBTARGET_CPP_SPEC
362 #define SUBTARGET_CPP_SPEC ""
363 #endif
364
365 #ifndef SUBTARGET_EXTRA_SPECS
366 #define SUBTARGET_EXTRA_SPECS
367 #endif
368
369 #define EXTRA_SPECS \
370 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
371 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
372 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
373 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
374 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
375 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
376 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
377 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
378 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
379 SUBTARGET_EXTRA_SPECS
380
381 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
382 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
383 #else
384 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
385 #endif
386
387 #define SH_ASM_SPEC \
388 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
389 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
390 %{m2a:--isa=sh2a} \
391 %{m2a-single:--isa=sh2a} \
392 %{m2a-single-only:--isa=sh2a} \
393 %{m2a-nofpu:--isa=sh2a-nofpu} \
394 %{m5-compact*:--isa=SHcompact} \
395 %{m5-32media*:--isa=SHmedia --abi=32} \
396 %{m5-64media*:--isa=SHmedia --abi=64} \
397 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
398
399 #define ASM_SPEC SH_ASM_SPEC
400
401 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
402 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
403 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
404 #else
405 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
406 #endif
407 #endif
408
409 #if STRICT_NOFPU == 1
410 /* Strict nofpu means that the compiler should tell the assembler
411 to reject FPU instructions. E.g. from ASM inserts. */
412 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
413 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
414 #else
415 /* If there were an -isa option for sh5-nofpu then it would also go here. */
416 #define SUBTARGET_ASM_ISA_SPEC \
417 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
418 #endif
419 #else /* ! STRICT_NOFPU */
420 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
421 #endif
422
423 #ifndef SUBTARGET_ASM_SPEC
424 #define SUBTARGET_ASM_SPEC ""
425 #endif
426
427 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
428 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
429 #else
430 #define LINK_EMUL_PREFIX "sh%{ml:l}"
431 #endif
432
433 #if TARGET_CPU_DEFAULT & MASK_SH5
434 #if TARGET_CPU_DEFAULT & MASK_SH_E
435 #define LINK_DEFAULT_CPU_EMUL "32"
436 #if TARGET_CPU_DEFAULT & MASK_SH1
437 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
438 #else
439 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
440 #endif /* MASK_SH1 */
441 #else /* !MASK_SH_E */
442 #define LINK_DEFAULT_CPU_EMUL "64"
443 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
444 #endif /* MASK_SH_E */
445 #define ASM_ISA_DEFAULT_SPEC \
446 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
447 #else /* !MASK_SH5 */
448 #define LINK_DEFAULT_CPU_EMUL ""
449 #define ASM_ISA_DEFAULT_SPEC ""
450 #endif /* MASK_SH5 */
451
452 #define SUBTARGET_LINK_EMUL_SUFFIX ""
453 #define SUBTARGET_LINK_SPEC ""
454
455 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
456 so that we can undo the damage without code replication. */
457 #define LINK_SPEC SH_LINK_SPEC
458
459 #define SH_LINK_SPEC "\
460 -m %(link_emul_prefix)\
461 %{m5-compact*|m5-32media*:32}\
462 %{m5-64media*:64}\
463 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
464 %(subtarget_link_emul_suffix) \
465 %{mrelax:-relax} %(subtarget_link_spec)"
466
467 #ifndef SH_DIV_STR_FOR_SIZE
468 #define SH_DIV_STR_FOR_SIZE "call"
469 #endif
470
471 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
472
473 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) sh_optimization_options (LEVEL, SIZE)
474
475 #define ASSEMBLER_DIALECT assembler_dialect
476
477 extern int assembler_dialect;
478
479 enum sh_divide_strategy_e {
480 /* SH5 strategies. */
481 SH_DIV_CALL,
482 SH_DIV_CALL2,
483 SH_DIV_FP, /* We could do this also for SH4. */
484 SH_DIV_INV,
485 SH_DIV_INV_MINLAT,
486 SH_DIV_INV20U,
487 SH_DIV_INV20L,
488 SH_DIV_INV_CALL,
489 SH_DIV_INV_CALL2,
490 SH_DIV_INV_FP,
491 /* SH1 .. SH4 strategies. Because of the small number of registers
492 available, the compiler uses knowledge of the actual set of registers
493 being clobbered by the different functions called. */
494 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
495 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
496 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
497 SH_DIV_INTRINSIC
498 };
499
500 extern enum sh_divide_strategy_e sh_div_strategy;
501
502 #ifndef SH_DIV_STRATEGY_DEFAULT
503 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
504 #endif
505
506 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
507
508 extern const char *sh_fixed_range_str;
509
510 #define OVERRIDE_OPTIONS sh_override_options ()
511
512 \f
513 /* Target machine storage layout. */
514
515 /* Define this if most significant bit is lowest numbered
516 in instructions that operate on numbered bit-fields. */
517
518 #define BITS_BIG_ENDIAN 0
519
520 /* Define this if most significant byte of a word is the lowest numbered. */
521 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
522
523 /* Define this if most significant word of a multiword number is the lowest
524 numbered. */
525 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
526
527 /* Define this to set the endianness to use in libgcc2.c, which can
528 not depend on target_flags. */
529 #if defined(__LITTLE_ENDIAN__)
530 #define LIBGCC2_WORDS_BIG_ENDIAN 0
531 #else
532 #define LIBGCC2_WORDS_BIG_ENDIAN 1
533 #endif
534
535 #define MAX_BITS_PER_WORD 64
536
537 /* Width in bits of an `int'. We want just 32-bits, even if words are
538 longer. */
539 #define INT_TYPE_SIZE 32
540
541 /* Width in bits of a `long'. */
542 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
543
544 /* Width in bits of a `long long'. */
545 #define LONG_LONG_TYPE_SIZE 64
546
547 /* Width in bits of a `long double'. */
548 #define LONG_DOUBLE_TYPE_SIZE 64
549
550 /* Width of a word, in units (bytes). */
551 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
552 #define MIN_UNITS_PER_WORD 4
553
554 /* Scaling factor for Dwarf data offsets for CFI information.
555 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
556 SHmedia; however, since we do partial register saves for the registers
557 visible to SHcompact, and for target registers for SHMEDIA32, we have
558 to allow saves that are only 4-byte aligned. */
559 #define DWARF_CIE_DATA_ALIGNMENT -4
560
561 /* Width in bits of a pointer.
562 See also the macro `Pmode' defined below. */
563 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
564
565 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
566 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
567
568 /* Boundary (in *bits*) on which stack pointer should be aligned. */
569 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
570
571 /* The log (base 2) of the cache line size, in bytes. Processors prior to
572 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
573 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
574 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
575
576 /* ABI given & required minimum allocation boundary (in *bits*) for the
577 code of a function. */
578 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
579
580 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
581 the vbit must go into the delta field of
582 pointers-to-member-functions. */
583 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
584 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
585
586 /* Alignment of field after `int : 0' in a structure. */
587 #define EMPTY_FIELD_BOUNDARY 32
588
589 /* No data type wants to be aligned rounder than this. */
590 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
591
592 /* The best alignment to use in cases where we have a choice. */
593 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
594
595 /* Make strings word-aligned so strcpy from constants will be faster. */
596 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
597 ((TREE_CODE (EXP) == STRING_CST \
598 && (ALIGN) < FASTEST_ALIGNMENT) \
599 ? FASTEST_ALIGNMENT : (ALIGN))
600
601 /* get_mode_alignment assumes complex values are always held in multiple
602 registers, but that is not the case on the SH; CQImode and CHImode are
603 held in a single integer register. SH5 also holds CSImode and SCmode
604 values in integer registers. This is relevant for argument passing on
605 SHcompact as we use a stack temp in order to pass CSImode by reference. */
606 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
607 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
608 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
609 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
610 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
611
612 /* Make arrays of chars word-aligned for the same reasons. */
613 #define DATA_ALIGNMENT(TYPE, ALIGN) \
614 (TREE_CODE (TYPE) == ARRAY_TYPE \
615 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
616 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
617
618 /* Number of bits which any structure or union's size must be a
619 multiple of. Each structure or union's size is rounded up to a
620 multiple of this. */
621 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
622
623 /* Set this nonzero if move instructions will actually fail to work
624 when given unaligned data. */
625 #define STRICT_ALIGNMENT 1
626
627 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
628 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
629 barrier_align (LABEL_AFTER_BARRIER)
630
631 #define LOOP_ALIGN(A_LABEL) \
632 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
633 ? 0 : sh_loop_align (A_LABEL))
634
635 #define LABEL_ALIGN(A_LABEL) \
636 ( \
637 (PREV_INSN (A_LABEL) \
638 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
639 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
640 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
641 /* explicit alignment insn in constant tables. */ \
642 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
643 : 0)
644
645 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
646 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
647
648 /* The base two logarithm of the known minimum alignment of an insn length. */
649 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
650 (NONJUMP_INSN_P (A_INSN) \
651 ? 1 << TARGET_SHMEDIA \
652 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
653 ? 1 << TARGET_SHMEDIA \
654 : CACHE_LOG)
655 \f
656 /* Standard register usage. */
657
658 /* Register allocation for the Renesas calling convention:
659
660 r0 arg return
661 r1..r3 scratch
662 r4..r7 args in
663 r8..r13 call saved
664 r14 frame pointer/call saved
665 r15 stack pointer
666 ap arg pointer (doesn't really exist, always eliminated)
667 pr subroutine return address
668 t t bit
669 mach multiply/accumulate result, high part
670 macl multiply/accumulate result, low part.
671 fpul fp/int communication register
672 rap return address pointer register
673 fr0 fp arg return
674 fr1..fr3 scratch floating point registers
675 fr4..fr11 fp args in
676 fr12..fr15 call saved floating point registers */
677
678 #define MAX_REGISTER_NAME_LENGTH 5
679 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
680
681 #define SH_REGISTER_NAMES_INITIALIZER \
682 { \
683 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
684 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
685 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
686 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
687 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
688 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
689 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
690 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
691 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
692 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
693 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
694 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
695 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
696 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
697 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
698 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
699 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
700 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
701 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
702 "rap", "sfp" \
703 }
704
705 #define REGNAMES_ARR_INDEX_1(index) \
706 (sh_register_names[index])
707 #define REGNAMES_ARR_INDEX_2(index) \
708 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
709 #define REGNAMES_ARR_INDEX_4(index) \
710 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
711 #define REGNAMES_ARR_INDEX_8(index) \
712 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
713 #define REGNAMES_ARR_INDEX_16(index) \
714 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
715 #define REGNAMES_ARR_INDEX_32(index) \
716 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
717 #define REGNAMES_ARR_INDEX_64(index) \
718 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
719
720 #define REGISTER_NAMES \
721 { \
722 REGNAMES_ARR_INDEX_64 (0), \
723 REGNAMES_ARR_INDEX_64 (64), \
724 REGNAMES_ARR_INDEX_8 (128), \
725 REGNAMES_ARR_INDEX_8 (136), \
726 REGNAMES_ARR_INDEX_8 (144), \
727 REGNAMES_ARR_INDEX_2 (152) \
728 }
729
730 #define ADDREGNAMES_SIZE 32
731 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
732 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
733 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
734
735 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
736 { \
737 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
738 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
739 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
740 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
741 }
742
743 #define ADDREGNAMES_REGNO(index) \
744 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
745 : (-1))
746
747 #define ADDREGNAMES_ARR_INDEX_1(index) \
748 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
749 #define ADDREGNAMES_ARR_INDEX_2(index) \
750 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
751 #define ADDREGNAMES_ARR_INDEX_4(index) \
752 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
753 #define ADDREGNAMES_ARR_INDEX_8(index) \
754 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
755 #define ADDREGNAMES_ARR_INDEX_16(index) \
756 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
757 #define ADDREGNAMES_ARR_INDEX_32(index) \
758 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
759
760 #define ADDITIONAL_REGISTER_NAMES \
761 { \
762 ADDREGNAMES_ARR_INDEX_32 (0) \
763 }
764
765 /* Number of actual hardware registers.
766 The hardware registers are assigned numbers for the compiler
767 from 0 to just below FIRST_PSEUDO_REGISTER.
768 All registers that the compiler knows about must be given numbers,
769 even those that are not normally considered general registers. */
770
771 /* There are many other relevant definitions in sh.md's md_constants. */
772
773 #define FIRST_GENERAL_REG R0_REG
774 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
775 #define FIRST_FP_REG DR0_REG
776 #define LAST_FP_REG (FIRST_FP_REG + \
777 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
778 #define FIRST_XD_REG XD0_REG
779 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
780 #define FIRST_TARGET_REG TR0_REG
781 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
782
783 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
784
785 #define FIRST_BANKED_REG R0_REG
786 #define LAST_BANKED_REG R7_REG
787
788 #define BANKED_REGISTER_P(REGNO) \
789 IN_RANGE ((REGNO), \
790 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
791 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
792
793 #define GENERAL_REGISTER_P(REGNO) \
794 IN_RANGE ((REGNO), \
795 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
796 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
797
798 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
799 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
800 || ((REGNO) == FRAME_POINTER_REGNUM))
801
802 #define FP_REGISTER_P(REGNO) \
803 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
804
805 #define XD_REGISTER_P(REGNO) \
806 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
807
808 #define FP_OR_XD_REGISTER_P(REGNO) \
809 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
810
811 #define FP_ANY_REGISTER_P(REGNO) \
812 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
813
814 #define SPECIAL_REGISTER_P(REGNO) \
815 ((REGNO) == GBR_REG || (REGNO) == T_REG \
816 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
817
818 #define TARGET_REGISTER_P(REGNO) \
819 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
820
821 #define SHMEDIA_REGISTER_P(REGNO) \
822 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
823 || TARGET_REGISTER_P (REGNO))
824
825 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
826 that should be fixed. */
827 #define VALID_REGISTER_P(REGNO) \
828 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
829 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
830 || (REGNO) == FRAME_POINTER_REGNUM \
831 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
832 || (TARGET_SH2E && (REGNO) == FPUL_REG))
833
834 /* The mode that should be generally used to store a register by
835 itself in the stack, or to load it back. */
836 #define REGISTER_NATURAL_MODE(REGNO) \
837 (FP_REGISTER_P (REGNO) ? SFmode \
838 : XD_REGISTER_P (REGNO) ? DFmode \
839 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
840 ? DImode \
841 : SImode)
842
843 #define FIRST_PSEUDO_REGISTER 154
844
845 /* Don't count soft frame pointer. */
846 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
847
848 /* 1 for registers that have pervasive standard uses
849 and are not available for the register allocator.
850
851 Mach register is fixed 'cause it's only 10 bits wide for SH1.
852 It is 32 bits wide for SH2. */
853
854 #define FIXED_REGISTERS \
855 { \
856 /* Regular registers. */ \
857 0, 0, 0, 0, 0, 0, 0, 0, \
858 0, 0, 0, 0, 0, 0, 0, 1, \
859 /* r16 is reserved, r18 is the former pr. */ \
860 1, 0, 0, 0, 0, 0, 0, 0, \
861 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
862 /* r26 is a global variable data pointer; r27 is for constants. */ \
863 1, 1, 1, 1, 0, 0, 0, 0, \
864 0, 0, 0, 0, 0, 0, 0, 0, \
865 0, 0, 0, 0, 0, 0, 0, 0, \
866 0, 0, 0, 0, 0, 0, 0, 0, \
867 0, 0, 0, 0, 0, 0, 0, 1, \
868 /* FP registers. */ \
869 0, 0, 0, 0, 0, 0, 0, 0, \
870 0, 0, 0, 0, 0, 0, 0, 0, \
871 0, 0, 0, 0, 0, 0, 0, 0, \
872 0, 0, 0, 0, 0, 0, 0, 0, \
873 0, 0, 0, 0, 0, 0, 0, 0, \
874 0, 0, 0, 0, 0, 0, 0, 0, \
875 0, 0, 0, 0, 0, 0, 0, 0, \
876 0, 0, 0, 0, 0, 0, 0, 0, \
877 /* Branch target registers. */ \
878 0, 0, 0, 0, 0, 0, 0, 0, \
879 /* XD registers. */ \
880 0, 0, 0, 0, 0, 0, 0, 0, \
881 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
882 1, 1, 1, 1, 1, 1, 0, 1, \
883 /*"rap", "sfp" */ \
884 1, 1, \
885 }
886
887 /* 1 for registers not available across function calls.
888 These must include the FIXED_REGISTERS and also any
889 registers that can be used without being saved.
890 The latter must include the registers where values are returned
891 and the register where structure-value addresses are passed.
892 Aside from that, you can include as many other registers as you like. */
893
894 #define CALL_USED_REGISTERS \
895 { \
896 /* Regular registers. */ \
897 1, 1, 1, 1, 1, 1, 1, 1, \
898 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
899 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
900 across SH5 function calls. */ \
901 0, 0, 0, 0, 0, 0, 0, 1, \
902 1, 1, 1, 1, 1, 1, 1, 1, \
903 1, 1, 1, 1, 0, 0, 0, 0, \
904 0, 0, 0, 0, 1, 1, 1, 1, \
905 1, 1, 1, 1, 0, 0, 0, 0, \
906 0, 0, 0, 0, 0, 0, 0, 0, \
907 0, 0, 0, 0, 1, 1, 1, 1, \
908 /* FP registers. */ \
909 1, 1, 1, 1, 1, 1, 1, 1, \
910 1, 1, 1, 1, 0, 0, 0, 0, \
911 1, 1, 1, 1, 1, 1, 1, 1, \
912 1, 1, 1, 1, 1, 1, 1, 1, \
913 1, 1, 1, 1, 0, 0, 0, 0, \
914 0, 0, 0, 0, 0, 0, 0, 0, \
915 0, 0, 0, 0, 0, 0, 0, 0, \
916 0, 0, 0, 0, 0, 0, 0, 0, \
917 /* Branch target registers. */ \
918 1, 1, 1, 1, 1, 0, 0, 0, \
919 /* XD registers. */ \
920 1, 1, 1, 1, 1, 1, 0, 0, \
921 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
922 1, 1, 1, 1, 1, 1, 1, 1, \
923 /*"rap", "sfp" */ \
924 1, 1, \
925 }
926
927 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
928 fixed, like PIC_OFFSET_TABLE_REGNUM. */
929 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
930
931 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
932 across SHcompact function calls. We can't tell whether a called
933 function is SHmedia or SHcompact, so we assume it may be when
934 compiling SHmedia code with the 32-bit ABI, since that's the only
935 ABI that can be linked with SHcompact code. */
936 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
937 (TARGET_SHMEDIA32 \
938 && GET_MODE_SIZE (MODE) > 4 \
939 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
940 && (REGNO) <= FIRST_GENERAL_REG + 15) \
941 || TARGET_REGISTER_P (REGNO) \
942 || (REGNO) == PR_MEDIA_REG))
943
944 /* Return number of consecutive hard regs needed starting at reg REGNO
945 to hold something of mode MODE.
946 This is ordinarily the length in words of a value of mode MODE
947 but can be less for certain modes in special long registers.
948
949 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
950
951 #define HARD_REGNO_NREGS(REGNO, MODE) \
952 (XD_REGISTER_P (REGNO) \
953 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
954 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
955 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
956 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
957
958 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
959
960 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
961 sh_hard_regno_mode_ok ((REGNO), (MODE))
962
963 /* Value is 1 if it is a good idea to tie two pseudo registers
964 when one has mode MODE1 and one has mode MODE2.
965 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
966 for any hard reg, then this must be 0 for correct output.
967 That's the case for xd registers: we don't hold SFmode values in
968 them, so we can't tie an SFmode pseudos with one in another
969 floating-point mode. */
970
971 #define MODES_TIEABLE_P(MODE1, MODE2) \
972 ((MODE1) == (MODE2) \
973 || (TARGET_SHMEDIA \
974 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
975 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
976 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
977 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
978 && (GET_MODE_SIZE (MODE2) <= 4)) \
979 : ((MODE1) != SFmode && (MODE2) != SFmode))))
980
981 /* A C expression that is nonzero if hard register NEW_REG can be
982 considered for use as a rename register for OLD_REG register */
983
984 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
985 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
986
987 /* Specify the registers used for certain standard purposes.
988 The values of these macros are register numbers. */
989
990 /* Define this if the program counter is overloaded on a register. */
991 /* #define PC_REGNUM 15*/
992
993 /* Register to use for pushing function arguments. */
994 #define STACK_POINTER_REGNUM SP_REG
995
996 /* Base register for access to local variables of the function. */
997 #define HARD_FRAME_POINTER_REGNUM FP_REG
998
999 /* Base register for access to local variables of the function. */
1000 #define FRAME_POINTER_REGNUM 153
1001
1002 /* Fake register that holds the address on the stack of the
1003 current function's return address. */
1004 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1005
1006 /* Register to hold the addressing base for position independent
1007 code access to data items. */
1008 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1009
1010 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1011
1012 /* Definitions for register eliminations.
1013
1014 We have three registers that can be eliminated on the SH. First, the
1015 frame pointer register can often be eliminated in favor of the stack
1016 pointer register. Secondly, the argument pointer register can always be
1017 eliminated; it is replaced with either the stack or frame pointer.
1018 Third, there is the return address pointer, which can also be replaced
1019 with either the stack or the frame pointer. */
1020
1021 /* This is an array of structures. Each structure initializes one pair
1022 of eliminable registers. The "from" register number is given first,
1023 followed by "to". Eliminations of the same "from" register are listed
1024 in order of preference. */
1025
1026 /* If you add any registers here that are not actually hard registers,
1027 and that have any alternative of elimination that doesn't always
1028 apply, you need to amend calc_live_regs to exclude it, because
1029 reload spills all eliminable registers where it sees an
1030 can_eliminate == 0 entry, thus making them 'live' .
1031 If you add any hard registers that can be eliminated in different
1032 ways, you have to patch reload to spill them only when all alternatives
1033 of elimination fail. */
1034
1035 #define ELIMINABLE_REGS \
1036 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1037 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1038 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1039 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1040 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1041 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1042 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1043
1044 /* Define the offset between two registers, one to be eliminated, and the other
1045 its replacement, at the start of a routine. */
1046
1047 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1048 OFFSET = initial_elimination_offset ((FROM), (TO))
1049
1050 /* Base register for access to arguments of the function. */
1051 #define ARG_POINTER_REGNUM AP_REG
1052
1053 /* Register in which the static-chain is passed to a function. */
1054 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1055
1056 /* Don't default to pcc-struct-return, because we have already specified
1057 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1058 target hook. */
1059
1060 #define DEFAULT_PCC_STRUCT_RETURN 0
1061
1062 #define SHMEDIA_REGS_STACK_ADJUST() \
1063 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1064 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1065 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1066 : 0)
1067
1068 \f
1069 /* Define the classes of registers for register constraints in the
1070 machine description. Also define ranges of constants.
1071
1072 One of the classes must always be named ALL_REGS and include all hard regs.
1073 If there is more than one class, another class must be named NO_REGS
1074 and contain no registers.
1075
1076 The name GENERAL_REGS must be the name of a class (or an alias for
1077 another name such as ALL_REGS). This is the class of registers
1078 that is allowed by "g" or "r" in a register constraint.
1079 Also, registers outside this class are allocated only when
1080 instructions express preferences for them.
1081
1082 The classes must be numbered in nondecreasing order; that is,
1083 a larger-numbered class must never be contained completely
1084 in a smaller-numbered class.
1085
1086 For any two classes, it is very desirable that there be another
1087 class that represents their union. */
1088
1089 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1090 be used as the destination of some of the arithmetic ops. There are
1091 also some special purpose registers; the T bit register, the
1092 Procedure Return Register and the Multiply Accumulate Registers. */
1093 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1094 reg_class_subunion. We don't want to have an actual union class
1095 of these, because it would only be used when both classes are calculated
1096 to give the same cost, but there is only one FPUL register.
1097 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1098 applying to the actual instruction alternative considered. E.g., the
1099 y/r alternative of movsi_ie is considered to have no more cost that
1100 the r/r alternative, which is patently untrue. */
1101
1102 enum reg_class
1103 {
1104 NO_REGS,
1105 R0_REGS,
1106 PR_REGS,
1107 T_REGS,
1108 MAC_REGS,
1109 FPUL_REGS,
1110 SIBCALL_REGS,
1111 GENERAL_REGS,
1112 FP0_REGS,
1113 FP_REGS,
1114 DF_HI_REGS,
1115 DF_REGS,
1116 FPSCR_REGS,
1117 GENERAL_FP_REGS,
1118 GENERAL_DF_REGS,
1119 TARGET_REGS,
1120 ALL_REGS,
1121 LIM_REG_CLASSES
1122 };
1123
1124 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1125
1126 /* Give names of register classes as strings for dump file. */
1127 #define REG_CLASS_NAMES \
1128 { \
1129 "NO_REGS", \
1130 "R0_REGS", \
1131 "PR_REGS", \
1132 "T_REGS", \
1133 "MAC_REGS", \
1134 "FPUL_REGS", \
1135 "SIBCALL_REGS", \
1136 "GENERAL_REGS", \
1137 "FP0_REGS", \
1138 "FP_REGS", \
1139 "DF_HI_REGS", \
1140 "DF_REGS", \
1141 "FPSCR_REGS", \
1142 "GENERAL_FP_REGS", \
1143 "GENERAL_DF_REGS", \
1144 "TARGET_REGS", \
1145 "ALL_REGS", \
1146 }
1147
1148 /* Define which registers fit in which classes.
1149 This is an initializer for a vector of HARD_REG_SET
1150 of length N_REG_CLASSES. */
1151
1152 #define REG_CLASS_CONTENTS \
1153 { \
1154 /* NO_REGS: */ \
1155 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1156 /* R0_REGS: */ \
1157 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1158 /* PR_REGS: */ \
1159 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1160 /* T_REGS: */ \
1161 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1162 /* MAC_REGS: */ \
1163 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1164 /* FPUL_REGS: */ \
1165 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1166 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1167 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1168 /* GENERAL_REGS: */ \
1169 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1170 /* FP0_REGS: */ \
1171 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1172 /* FP_REGS: */ \
1173 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1174 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1175 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1176 /* DF_REGS: */ \
1177 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1178 /* FPSCR_REGS: */ \
1179 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1180 /* GENERAL_FP_REGS: */ \
1181 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1182 /* GENERAL_DF_REGS: */ \
1183 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1184 /* TARGET_REGS: */ \
1185 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1186 /* ALL_REGS: */ \
1187 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1188 }
1189
1190 /* The same information, inverted:
1191 Return the class number of the smallest class containing
1192 reg number REGNO. This could be a conditional expression
1193 or could index an array. */
1194
1195 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1196 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1197
1198 /* The following macro defines cover classes for Integrated Register
1199 Allocator. Cover classes is a set of non-intersected register
1200 classes covering all hard registers used for register allocation
1201 purpose. Any move between two registers of a cover class should be
1202 cheaper than load or store of the registers. The macro value is
1203 array of register classes with LIM_REG_CLASSES used as the end
1204 marker. */
1205
1206 #define IRA_COVER_CLASSES \
1207 { \
1208 GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \
1209 FPUL_REGS, LIM_REG_CLASSES \
1210 }
1211
1212 /* When this hook returns true for MODE, the compiler allows
1213 registers explicitly used in the rtl to be used as spill registers
1214 but prevents the compiler from extending the lifetime of these
1215 registers. */
1216 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1217 sh_small_register_classes_for_mode_p
1218
1219 /* The order in which register should be allocated. */
1220 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1221 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1222 spilled or used otherwise, we better have the FP_REGS allocated first. */
1223 #define REG_ALLOC_ORDER \
1224 {/* Caller-saved FPRs */ \
1225 65, 66, 67, 68, 69, 70, 71, 64, \
1226 72, 73, 74, 75, 80, 81, 82, 83, \
1227 84, 85, 86, 87, 88, 89, 90, 91, \
1228 92, 93, 94, 95, 96, 97, 98, 99, \
1229 /* Callee-saved FPRs */ \
1230 76, 77, 78, 79,100,101,102,103, \
1231 104,105,106,107,108,109,110,111, \
1232 112,113,114,115,116,117,118,119, \
1233 120,121,122,123,124,125,126,127, \
1234 136,137,138,139,140,141,142,143, \
1235 /* FPSCR */ 151, \
1236 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1237 1, 2, 3, 7, 6, 5, 4, 0, \
1238 8, 9, 17, 19, 20, 21, 22, 23, \
1239 36, 37, 38, 39, 40, 41, 42, 43, \
1240 60, 61, 62, \
1241 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1242 10, 11, 12, 13, 14, 18, \
1243 /* SH5 callee-saved GPRs */ \
1244 28, 29, 30, 31, 32, 33, 34, 35, \
1245 44, 45, 46, 47, 48, 49, 50, 51, \
1246 52, 53, 54, 55, 56, 57, 58, 59, \
1247 /* FPUL */ 150, \
1248 /* SH5 branch target registers */ \
1249 128,129,130,131,132,133,134,135, \
1250 /* Fixed registers */ \
1251 15, 16, 24, 25, 26, 27, 63,144, \
1252 145,146,147,148,149,152,153 }
1253
1254 /* The class value for index registers, and the one for base regs. */
1255 #define INDEX_REG_CLASS \
1256 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1257 #define BASE_REG_CLASS GENERAL_REGS
1258 \f
1259 /* Defines for sh.md and constraints.md. */
1260
1261 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1262 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1263 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1264 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1265 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1266 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1267 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1268 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1269
1270 #define CONST_OK_FOR_J16(VALUE) \
1271 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1272 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1273
1274 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1275 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1276
1277 /* Given an rtx X being reloaded into a reg required to be
1278 in class CLASS, return the class of reg to actually use.
1279 In general this is just CLASS; but on some machines
1280 in some cases it is preferable to use a more restrictive class. */
1281
1282 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1283 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1284 && (GET_CODE (X) == CONST_DOUBLE \
1285 || GET_CODE (X) == SYMBOL_REF \
1286 || PIC_ADDR_P (X)) \
1287 ? GENERAL_REGS \
1288 : (CLASS)) \
1289
1290 #if 0
1291 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1292 ((((REGCLASS_HAS_FP_REG (CLASS) \
1293 && (REG_P (X) \
1294 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1295 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1296 && TARGET_FMOVD)))) \
1297 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1298 && REG_P (X) \
1299 && FP_REGISTER_P (REGNO (X)))) \
1300 && ! TARGET_SHMEDIA \
1301 && ((MODE) == SFmode || (MODE) == SImode)) \
1302 ? FPUL_REGS \
1303 : (((CLASS) == FPUL_REGS \
1304 || (REGCLASS_HAS_FP_REG (CLASS) \
1305 && ! TARGET_SHMEDIA && MODE == SImode)) \
1306 && (MEM_P (X) \
1307 || (REG_P (X) \
1308 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1309 || REGNO (X) == T_REG \
1310 || system_reg_operand (X, VOIDmode))))) \
1311 ? GENERAL_REGS \
1312 : (((CLASS) == TARGET_REGS \
1313 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1314 && !satisfies_constraint_Csy (X) \
1315 && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
1316 ? GENERAL_REGS \
1317 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1318 && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
1319 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1320 ? GENERAL_REGS \
1321 : ((CLASS) != GENERAL_REGS && REG_P (X) \
1322 && TARGET_REGISTER_P (REGNO (X))) \
1323 ? GENERAL_REGS : (ELSE))
1324
1325 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1326 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1327
1328 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1329 ((REGCLASS_HAS_FP_REG (CLASS) \
1330 && ! TARGET_SHMEDIA \
1331 && immediate_operand ((X), (MODE)) \
1332 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1333 && (MODE) == SFmode && fldi_ok ())) \
1334 ? R0_REGS \
1335 : ((CLASS) == FPUL_REGS \
1336 && ((REG_P (X) \
1337 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1338 || REGNO (X) == T_REG)) \
1339 || GET_CODE (X) == PLUS)) \
1340 ? GENERAL_REGS \
1341 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1342 ? (satisfies_constraint_I08 (X) \
1343 ? GENERAL_REGS \
1344 : R0_REGS) \
1345 : ((CLASS) == FPSCR_REGS \
1346 && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1347 || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
1348 ? GENERAL_REGS \
1349 : (REGCLASS_HAS_FP_REG (CLASS) \
1350 && TARGET_SHMEDIA \
1351 && immediate_operand ((X), (MODE)) \
1352 && (X) != CONST0_RTX (GET_MODE (X)) \
1353 && GET_MODE (X) != V4SFmode) \
1354 ? GENERAL_REGS \
1355 : (((MODE) == QImode || (MODE) == HImode) \
1356 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1357 ? GENERAL_REGS \
1358 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1359 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
1360 ? TARGET_REGS \
1361 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1362 #endif
1363
1364 /* Return the maximum number of consecutive registers
1365 needed to represent mode MODE in a register of class CLASS.
1366
1367 If TARGET_SHMEDIA, we need two FP registers per word.
1368 Otherwise we will need at most one register per word. */
1369 #define CLASS_MAX_NREGS(CLASS, MODE) \
1370 (TARGET_SHMEDIA \
1371 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1372 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1373 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1374
1375 /* If defined, gives a class of registers that cannot be used as the
1376 operand of a SUBREG that changes the mode of the object illegally. */
1377 /* ??? We need to renumber the internal numbers for the frnn registers
1378 when in little endian in order to allow mode size changes. */
1379
1380 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1381 sh_cannot_change_mode_class (FROM, TO, CLASS)
1382 \f
1383 /* Stack layout; function entry, exit and calling. */
1384
1385 /* Define the number of registers that can hold parameters.
1386 These macros are used only in other macro definitions below. */
1387
1388 #define NPARM_REGS(MODE) \
1389 (TARGET_FPU_ANY && (MODE) == SFmode \
1390 ? (TARGET_SH5 ? 12 : 8) \
1391 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1392 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1393 ? (TARGET_SH5 ? 12 : 8) \
1394 : (TARGET_SH5 ? 8 : 4))
1395
1396 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1397 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1398
1399 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1400 #define FIRST_FP_RET_REG FIRST_FP_REG
1401
1402 /* Define this if pushing a word on the stack
1403 makes the stack pointer a smaller address. */
1404 #define STACK_GROWS_DOWNWARD
1405
1406 /* Define this macro to nonzero if the addresses of local variable slots
1407 are at negative offsets from the frame pointer. */
1408 #define FRAME_GROWS_DOWNWARD 1
1409
1410 /* Offset from the frame pointer to the first local variable slot to
1411 be allocated. */
1412 #define STARTING_FRAME_OFFSET 0
1413
1414 /* If we generate an insn to push BYTES bytes,
1415 this says how many the stack pointer really advances by. */
1416 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1417 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1418 do correct alignment. */
1419 #if 0
1420 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1421 #endif
1422
1423 /* Offset of first parameter from the argument pointer register value. */
1424 #define FIRST_PARM_OFFSET(FNDECL) 0
1425
1426 /* Value is the number of bytes of arguments automatically popped when
1427 calling a subroutine.
1428 CUM is the accumulated argument list.
1429
1430 On SHcompact, the call trampoline pops arguments off the stack. */
1431 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1432
1433 /* Some subroutine macros specific to this machine. */
1434
1435 #define BASE_RETURN_VALUE_REG(MODE) \
1436 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1437 ? FIRST_FP_RET_REG \
1438 : TARGET_FPU_ANY && (MODE) == SCmode \
1439 ? FIRST_FP_RET_REG \
1440 : (TARGET_FPU_DOUBLE \
1441 && ((MODE) == DFmode || (MODE) == SFmode \
1442 || (MODE) == DCmode || (MODE) == SCmode )) \
1443 ? FIRST_FP_RET_REG \
1444 : FIRST_RET_REG)
1445
1446 #define BASE_ARG_REG(MODE) \
1447 ((TARGET_SH2E && ((MODE) == SFmode)) \
1448 ? FIRST_FP_PARM_REG \
1449 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1450 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1451 ? FIRST_FP_PARM_REG \
1452 : FIRST_PARM_REG)
1453
1454 #define FUNCTION_VALUE_REGNO_P(REGNO) sh_function_value_regno_p (REGNO)
1455
1456 /* 1 if N is a possible register number for function argument passing. */
1457 /* ??? There are some callers that pass REGNO as int, and others that pass
1458 it as unsigned. We get warnings unless we do casts everywhere. */
1459 #define FUNCTION_ARG_REGNO_P(REGNO) \
1460 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1461 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1462 || (TARGET_FPU_ANY \
1463 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1464 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1465 + NPARM_REGS (SFmode))))
1466 \f
1467 /* Define a data type for recording info about an argument list
1468 during the scan of that argument list. This data type should
1469 hold all necessary information about the function itself
1470 and about the args processed so far, enough to enable macros
1471 such as FUNCTION_ARG to determine where the next arg should go.
1472
1473 On SH, this is a single integer, which is a number of words
1474 of arguments scanned so far (including the invisible argument,
1475 if any, which holds the structure-value-address).
1476 Thus NARGREGS or more means all following args should go on the stack. */
1477
1478 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1479 struct sh_args {
1480 int arg_count[2];
1481 int force_mem;
1482 /* Nonzero if a prototype is available for the function. */
1483 int prototype_p;
1484 /* The number of an odd floating-point register, that should be used
1485 for the next argument of type float. */
1486 int free_single_fp_reg;
1487 /* Whether we're processing an outgoing function call. */
1488 int outgoing;
1489 /* The number of general-purpose registers that should have been
1490 used to pass partial arguments, that are passed totally on the
1491 stack. On SHcompact, a call trampoline will pop them off the
1492 stack before calling the actual function, and, if the called
1493 function is implemented in SHcompact mode, the incoming arguments
1494 decoder will push such arguments back onto the stack. For
1495 incoming arguments, STACK_REGS also takes into account other
1496 arguments passed by reference, that the decoder will also push
1497 onto the stack. */
1498 int stack_regs;
1499 /* The number of general-purpose registers that should have been
1500 used to pass arguments, if the arguments didn't have to be passed
1501 by reference. */
1502 int byref_regs;
1503 /* Set as by shcompact_byref if the current argument is to be passed
1504 by reference. */
1505 int byref;
1506
1507 /* call_cookie is a bitmask used by call expanders, as well as
1508 function prologue and epilogues, to allow SHcompact to comply
1509 with the SH5 32-bit ABI, that requires 64-bit registers to be
1510 used even though only the lower 32-bit half is visible in
1511 SHcompact mode. The strategy is to call SHmedia trampolines.
1512
1513 The alternatives for each of the argument-passing registers are
1514 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1515 contents from the address in it; (d) add 8 to it, storing the
1516 result in the next register, then (c); (e) copy it from some
1517 floating-point register,
1518
1519 Regarding copies from floating-point registers, r2 may only be
1520 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1521 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1522 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1523 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1524 dr10.
1525
1526 The bit mask is structured as follows:
1527
1528 - 1 bit to tell whether to set up a return trampoline.
1529
1530 - 3 bits to count the number consecutive registers to pop off the
1531 stack.
1532
1533 - 4 bits for each of r9, r8, r7 and r6.
1534
1535 - 3 bits for each of r5, r4, r3 and r2.
1536
1537 - 3 bits set to 0 (the most significant ones)
1538
1539 3 2 1 0
1540 1098 7654 3210 9876 5432 1098 7654 3210
1541 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1542 2223 3344 4555 6666 7777 8888 9999 SSS-
1543
1544 - If F is set, the register must be copied from an FP register,
1545 whose number is encoded in the remaining bits.
1546
1547 - Else, if L is set, the register must be loaded from the address
1548 contained in it. If the P bit is *not* set, the address of the
1549 following dword should be computed first, and stored in the
1550 following register.
1551
1552 - Else, if P is set, the register alone should be popped off the
1553 stack.
1554
1555 - After all this processing, the number of registers represented
1556 in SSS will be popped off the stack. This is an optimization
1557 for pushing/popping consecutive registers, typically used for
1558 varargs and large arguments partially passed in registers.
1559
1560 - If T is set, a return trampoline will be set up for 64-bit
1561 return values to be split into 2 32-bit registers. */
1562 long call_cookie;
1563
1564 /* This is set to nonzero when the call in question must use the Renesas ABI,
1565 even without the -mrenesas option. */
1566 int renesas_abi;
1567 };
1568
1569 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1570 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1571 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1572 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1573 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1574 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1575 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1576 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1577 #define CALL_COOKIE_INT_REG(REG, VAL) \
1578 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1579 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1580 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1581
1582 #define CUMULATIVE_ARGS struct sh_args
1583
1584 #define GET_SH_ARG_CLASS(MODE) \
1585 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1586 ? SH_ARG_FLOAT \
1587 /* There's no mention of complex float types in the SH5 ABI, so we
1588 should presumably handle them as aggregate types. */ \
1589 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1590 ? SH_ARG_INT \
1591 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1592 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1593 ? SH_ARG_FLOAT : SH_ARG_INT)
1594
1595 #define ROUND_ADVANCE(SIZE) \
1596 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1597
1598 /* Round a register number up to a proper boundary for an arg of mode
1599 MODE.
1600
1601 The SH doesn't care about double alignment, so we only
1602 round doubles to even regs when asked to explicitly. */
1603
1604 #define ROUND_REG(CUM, MODE) \
1605 (((TARGET_ALIGN_DOUBLE \
1606 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1607 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1608 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1609 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1610 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1611 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1612
1613 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1614 for a call to a function whose data type is FNTYPE.
1615 For a library call, FNTYPE is 0.
1616
1617 On SH, the offset always starts at 0: the first parm reg is always
1618 the same reg for a given argument class.
1619
1620 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1621
1622 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1623 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1624
1625 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1626 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1627
1628 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1629 This macro is only used in this file. */
1630
1631 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1632 (((TYPE) == 0 \
1633 || (! TREE_ADDRESSABLE ((TYPE)) \
1634 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1635 || ! (AGGREGATE_TYPE_P (TYPE) \
1636 || (!TARGET_FPU_ANY \
1637 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1638 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1639 && ! (CUM).force_mem \
1640 && (TARGET_SH2E \
1641 ? ((MODE) == BLKmode \
1642 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1643 + int_size_in_bytes (TYPE)) \
1644 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1645 : ((ROUND_REG((CUM), (MODE)) \
1646 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1647 <= NPARM_REGS (MODE))) \
1648 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1649
1650 /* By accident we got stuck with passing SCmode on SH4 little endian
1651 in two registers that are nominally successive - which is different from
1652 two single SFmode values, where we take endianness translation into
1653 account. That does not work at all if an odd number of registers is
1654 already in use, so that got fixed, but library functions are still more
1655 likely to use complex numbers without mixing them with SFmode arguments
1656 (which in C would have to be structures), so for the sake of ABI
1657 compatibility the way SCmode values are passed when an even number of
1658 FP registers is in use remains different from a pair of SFmode values for
1659 now.
1660 I.e.:
1661 foo (double); a: fr5,fr4
1662 foo (float a, float b); a: fr5 b: fr4
1663 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1664 this should be the other way round...
1665 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1666 #define FUNCTION_ARG_SCmode_WART 1
1667
1668 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1669 register in SHcompact mode, it must be padded in the most
1670 significant end. This means that passing it by reference wouldn't
1671 pad properly on a big-endian machine. In this particular case, we
1672 pass this argument on the stack, in a way that the call trampoline
1673 will load its value into the appropriate register. */
1674 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1675 ((MODE) == BLKmode \
1676 && TARGET_SHCOMPACT \
1677 && ! TARGET_LITTLE_ENDIAN \
1678 && int_size_in_bytes (TYPE) > 4 \
1679 && int_size_in_bytes (TYPE) < 8)
1680
1681 /* Minimum alignment for an argument to be passed by callee-copy
1682 reference. We need such arguments to be aligned to 8 byte
1683 boundaries, because they'll be loaded using quad loads. */
1684 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1685
1686 /* The SH5 ABI requires floating-point arguments to be passed to
1687 functions without a prototype in both an FP register and a regular
1688 register or the stack. When passing the argument in both FP and
1689 general-purpose registers, list the FP register first. */
1690 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1691 (gen_rtx_PARALLEL \
1692 ((MODE), \
1693 gen_rtvec (2, \
1694 gen_rtx_EXPR_LIST \
1695 (VOIDmode, \
1696 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1697 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1698 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1699 : NULL_RTX), \
1700 const0_rtx), \
1701 gen_rtx_EXPR_LIST \
1702 (VOIDmode, \
1703 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1704 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1705 + (CUM).arg_count[(int) SH_ARG_INT]) \
1706 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1707 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1708 const0_rtx))))
1709
1710 /* The SH5 ABI requires regular registers or stack slots to be
1711 reserved for floating-point arguments. Registers are taken care of
1712 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1713 Unfortunately, there's no way to just reserve a stack slot, so
1714 we'll end up needlessly storing a copy of the argument in the
1715 stack. For incoming arguments, however, the PARALLEL will be
1716 optimized to the register-only form, and the value in the stack
1717 slot won't be used at all. */
1718 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1719 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1720 ? gen_rtx_REG ((MODE), (REG)) \
1721 : gen_rtx_PARALLEL ((MODE), \
1722 gen_rtvec (2, \
1723 gen_rtx_EXPR_LIST \
1724 (VOIDmode, NULL_RTX, \
1725 const0_rtx), \
1726 gen_rtx_EXPR_LIST \
1727 (VOIDmode, gen_rtx_REG ((MODE), \
1728 (REG)), \
1729 const0_rtx))))
1730
1731 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1732 (TARGET_SH5 \
1733 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1734 || (MODE) == DCmode) \
1735 && ((CUM).arg_count[(int) SH_ARG_INT] \
1736 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1737 : GET_MODE_SIZE (MODE)) \
1738 + 7) / 8) > NPARM_REGS (SImode))
1739
1740 /* Perform any needed actions needed for a function that is receiving a
1741 variable number of arguments. */
1742
1743 /* Call the function profiler with a given profile label.
1744 We use two .aligns, so as to make sure that both the .long is aligned
1745 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1746 from the trapa instruction. */
1747
1748 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1749 { \
1750 if (TARGET_SHMEDIA) \
1751 { \
1752 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1753 fprintf((STREAM), "\ttrapa\tr0\n"); \
1754 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1755 } \
1756 else \
1757 { \
1758 fprintf((STREAM), "\t.align\t2\n"); \
1759 fprintf((STREAM), "\ttrapa\t#33\n"); \
1760 fprintf((STREAM), "\t.align\t2\n"); \
1761 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1762 } \
1763 }
1764
1765 /* Define this macro if the code for function profiling should come
1766 before the function prologue. Normally, the profiling code comes
1767 after. */
1768
1769 #define PROFILE_BEFORE_PROLOGUE
1770
1771 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1772 the stack pointer does not matter. The value is tested only in
1773 functions that have frame pointers.
1774 No definition is equivalent to always zero. */
1775
1776 #define EXIT_IGNORE_STACK 1
1777
1778 /*
1779 On the SH, the trampoline looks like
1780 2 0002 D202 mov.l l2,r2
1781 1 0000 D301 mov.l l1,r3
1782 3 0004 422B jmp @r2
1783 4 0006 0009 nop
1784 5 0008 00000000 l1: .long area
1785 6 000c 00000000 l2: .long function */
1786
1787 /* Length in units of the trampoline for entering a nested function. */
1788 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1789
1790 /* Alignment required for a trampoline in bits . */
1791 #define TRAMPOLINE_ALIGNMENT \
1792 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
1793 : TARGET_SHMEDIA ? 256 : 64)
1794
1795 /* A C expression whose value is RTL representing the value of the return
1796 address for the frame COUNT steps up from the current frame.
1797 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1798 can ignore COUNT. */
1799
1800 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1801 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
1802
1803 /* A C expression whose value is RTL representing the location of the
1804 incoming return address at the beginning of any function, before the
1805 prologue. This RTL is either a REG, indicating that the return
1806 value is saved in REG, or a MEM representing a location in
1807 the stack. */
1808 #define INCOMING_RETURN_ADDR_RTX \
1809 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1810 \f
1811 /* Addressing modes, and classification of registers for them. */
1812 #define HAVE_POST_INCREMENT TARGET_SH1
1813 #define HAVE_PRE_DECREMENT TARGET_SH1
1814
1815 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1816 ? 0 : TARGET_SH1)
1817 #define USE_LOAD_PRE_DECREMENT(mode) 0
1818 #define USE_STORE_POST_INCREMENT(mode) 0
1819 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1820 ? 0 : TARGET_SH1)
1821
1822 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1823 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1824 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1825
1826 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1827 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1828 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1829
1830 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1831
1832 /* Macros to check register numbers against specific register classes. */
1833
1834 /* These assume that REGNO is a hard or pseudo reg number.
1835 They give nonzero only if REGNO is a hard reg of the suitable class
1836 or a pseudo reg currently allocated to a suitable hard reg.
1837 Since they use reg_renumber, they are safe only once reg_renumber
1838 has been allocated, which happens in local-alloc.c. */
1839
1840 #define REGNO_OK_FOR_BASE_P(REGNO) \
1841 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1842 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1843 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1844 (TARGET_SHMEDIA \
1845 ? (GENERAL_REGISTER_P (REGNO) \
1846 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1847 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1848
1849 /* Maximum number of registers that can appear in a valid memory
1850 address. */
1851
1852 #define MAX_REGS_PER_ADDRESS 2
1853
1854 /* Recognize any constant value that is a valid address. */
1855
1856 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1857
1858 /* Nonzero if the constant value X is a legitimate general operand. */
1859 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
1860
1861 #define LEGITIMATE_CONSTANT_P(X) \
1862 (TARGET_SHMEDIA \
1863 ? ((GET_MODE (X) != DFmode \
1864 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
1865 || (X) == CONST0_RTX (GET_MODE (X)) \
1866 || ! TARGET_SHMEDIA_FPU \
1867 || TARGET_SHMEDIA64) \
1868 : (GET_CODE (X) != CONST_DOUBLE \
1869 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1870 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
1871
1872 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1873 and check its validity for a certain class.
1874 The suitable hard regs are always accepted and all pseudo regs
1875 are also accepted if STRICT is not set. */
1876
1877 /* Nonzero if X is a reg that can be used as a base reg. */
1878 #define REG_OK_FOR_BASE_P(X, STRICT) \
1879 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1880 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1881
1882 /* Nonzero if X is a reg that can be used as an index. */
1883 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1884 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1885 : REGNO (X) == R0_REG) \
1886 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1887
1888 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1889 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1890 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1891 : REGNO (X) == R0_REG && OFFSET == 0) \
1892 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1893
1894 /* Macros for extra constraints. */
1895
1896 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1897 ((GET_CODE ((OP)) == LABEL_REF) \
1898 || (GET_CODE ((OP)) == CONST \
1899 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1900 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1901 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1902
1903 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1904 (CONSTANT_P (OP) \
1905 && !CONST_INT_P (OP) \
1906 && GET_CODE (OP) != CONST_DOUBLE \
1907 && (!flag_pic \
1908 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1909 && !PIC_ADDR_P (OP) \
1910 && GET_CODE (OP) != LABEL_REF)))
1911
1912 /* Check whether OP is a datalabel unspec. */
1913 #define DATALABEL_REF_NO_CONST_P(OP) \
1914 (GET_CODE (OP) == UNSPEC \
1915 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1916 && XVECLEN ((OP), 0) == 1 \
1917 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1918
1919 #define GOT_ENTRY_P(OP) \
1920 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1921 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1922
1923 #define GOTPLT_ENTRY_P(OP) \
1924 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1925 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1926
1927 #define UNSPEC_GOTOFF_P(OP) \
1928 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1929
1930 #define GOTOFF_P(OP) \
1931 (GET_CODE (OP) == CONST \
1932 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1933 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1934 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1935 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1936
1937 #define PIC_ADDR_P(OP) \
1938 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1939 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1940
1941 #define PCREL_SYMOFF_P(OP) \
1942 (GET_CODE (OP) == CONST \
1943 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1944 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1945
1946 #define NON_PIC_REFERENCE_P(OP) \
1947 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1948 || (GET_CODE (OP) == CONST \
1949 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1950 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
1951 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
1952 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1953 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1954 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1955 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
1956 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1957
1958 #define PIC_REFERENCE_P(OP) \
1959 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1960 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1961
1962 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
1963 (flag_pic \
1964 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
1965 || PCREL_SYMOFF_P (OP)) \
1966 : NON_PIC_REFERENCE_P (OP))
1967 \f
1968 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1969 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1970 || (GET_CODE (X) == SUBREG \
1971 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1972 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1973 && REG_P (SUBREG_REG (X)) \
1974 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1975
1976 /* Since this must be r0, which is a single register class, we must check
1977 SUBREGs more carefully, to be sure that we don't accept one that extends
1978 outside the class. */
1979 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1980 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1981 || (GET_CODE (X) == SUBREG \
1982 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1983 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1984 && REG_P (SUBREG_REG (X)) \
1985 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1986
1987 #ifdef REG_OK_STRICT
1988 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1989 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1990 #else
1991 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1992 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1993 #endif
1994
1995 #define ALLOW_INDEXED_ADDRESS \
1996 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
1997
1998 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, WIN) \
1999 do { \
2000 if (sh_legitimate_index_p ((MODE), (OP))) \
2001 goto WIN; \
2002 } while (0)
2003 \f
2004 /* A C compound statement that attempts to replace X, which is an address
2005 that needs reloading, with a valid memory address for an operand of
2006 mode MODE. WIN is a C statement label elsewhere in the code. */
2007
2008 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2009 do { \
2010 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
2011 goto WIN; \
2012 } while (0)
2013 \f
2014 /* Specify the machine mode that this machine uses
2015 for the index in the tablejump instruction. */
2016 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2017
2018 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2019 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2020 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2021 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2022 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2023 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2024 : SImode)
2025
2026 /* Define as C expression which evaluates to nonzero if the tablejump
2027 instruction expects the table to contain offsets from the address of the
2028 table.
2029 Do not define this if the table should contain absolute addresses. */
2030 #define CASE_VECTOR_PC_RELATIVE 1
2031
2032 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2033 #define FLOAT_TYPE_SIZE 32
2034
2035 /* Since the SH2e has only `float' support, it is desirable to make all
2036 floating point types equivalent to `float'. */
2037 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2038
2039 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH2A_SINGLE_ONLY__) || defined( __SH4_SINGLE_ONLY__)
2040 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2041 #else
2042 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2043 #endif
2044
2045 /* 'char' is signed by default. */
2046 #define DEFAULT_SIGNED_CHAR 1
2047
2048 /* The type of size_t unsigned int. */
2049 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2050
2051 #undef PTRDIFF_TYPE
2052 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2053
2054 #define WCHAR_TYPE "short unsigned int"
2055 #define WCHAR_TYPE_SIZE 16
2056
2057 #define SH_ELF_WCHAR_TYPE "long int"
2058
2059 /* Max number of bytes we can move from memory to memory
2060 in one reasonably fast instruction. */
2061 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2062
2063 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2064 MOVE_MAX is not a compile-time constant. */
2065 #define MAX_MOVE_MAX 8
2066
2067 /* Max number of bytes we want move_by_pieces to be able to copy
2068 efficiently. */
2069 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2070
2071 /* Define if operations between registers always perform the operation
2072 on the full register even if a narrower mode is specified. */
2073 #define WORD_REGISTER_OPERATIONS
2074
2075 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2076 will either zero-extend or sign-extend. The value of this macro should
2077 be the code that says which one of the two operations is implicitly
2078 done, UNKNOWN if none. */
2079 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2080 /* FP registers can load SImode values, but don't implicitly sign-extend
2081 them to DImode. */
2082 #define LOAD_EXTEND_OP(MODE) \
2083 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2084 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2085
2086 /* Define if loading short immediate values into registers sign extends. */
2087 #define SHORT_IMMEDIATES_SIGN_EXTEND
2088
2089 /* Nonzero if access to memory by bytes is no faster than for words. */
2090 #define SLOW_BYTE_ACCESS 1
2091
2092 /* Immediate shift counts are truncated by the output routines (or was it
2093 the assembler?). Shift counts in a register are truncated by SH. Note
2094 that the native compiler puts too large (> 32) immediate shift counts
2095 into a register and shifts by the register, letting the SH decide what
2096 to do instead of doing that itself. */
2097 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2098 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2099 expects - the sign bit is significant - so it appears that we need to
2100 leave this zero for correct SH3 code. */
2101 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2102
2103 /* All integers have the same format so truncation is easy. */
2104 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2105 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2106 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2107
2108 /* Define this if addresses of constant functions
2109 shouldn't be put through pseudo regs where they can be cse'd.
2110 Desirable on machines where ordinary constants are expensive
2111 but a CALL with constant address is cheap. */
2112 /*#define NO_FUNCTION_CSE 1*/
2113
2114 /* The machine modes of pointers and functions. */
2115 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2116 #define FUNCTION_MODE Pmode
2117
2118 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2119 are actually function calls with some special constraints on arguments
2120 and register usage.
2121
2122 These macros tell reorg that the references to arguments and
2123 register clobbers for insns of type sfunc do not appear to happen
2124 until after the millicode call. This allows reorg to put insns
2125 which set the argument registers into the delay slot of the millicode
2126 call -- thus they act more like traditional CALL_INSNs.
2127
2128 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2129 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2130 in particular. */
2131
2132 #define INSN_SETS_ARE_DELAYED(X) \
2133 ((NONJUMP_INSN_P (X) \
2134 && GET_CODE (PATTERN (X)) != SEQUENCE \
2135 && GET_CODE (PATTERN (X)) != USE \
2136 && GET_CODE (PATTERN (X)) != CLOBBER \
2137 && get_attr_is_sfunc (X)))
2138
2139 #define INSN_REFERENCES_ARE_DELAYED(X) \
2140 ((NONJUMP_INSN_P (X) \
2141 && GET_CODE (PATTERN (X)) != SEQUENCE \
2142 && GET_CODE (PATTERN (X)) != USE \
2143 && GET_CODE (PATTERN (X)) != CLOBBER \
2144 && get_attr_is_sfunc (X)))
2145
2146 \f
2147 /* Position Independent Code. */
2148
2149 /* We can't directly access anything that contains a symbol,
2150 nor can we indirect via the constant pool. */
2151 #define LEGITIMATE_PIC_OPERAND_P(X) \
2152 ((! nonpic_symbol_mentioned_p (X) \
2153 && (GET_CODE (X) != SYMBOL_REF \
2154 || ! CONSTANT_POOL_ADDRESS_P (X) \
2155 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2156 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2157
2158 #define SYMBOLIC_CONST_P(X) \
2159 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2160 && nonpic_symbol_mentioned_p (X))
2161 \f
2162 /* Compute extra cost of moving data between one register class
2163 and another. */
2164
2165 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2166 uses this information. Hence, the general register <-> floating point
2167 register information here is not used for SFmode. */
2168
2169 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2170 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2171 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2172
2173 #define REGCLASS_HAS_FP_REG(CLASS) \
2174 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2175 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2176
2177 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2178 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2179
2180 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2181 would be so that people with slow memory systems could generate
2182 different code that does fewer memory accesses. */
2183
2184 /* A C expression for the cost of a branch instruction. A value of 1
2185 is the default; other values are interpreted relative to that.
2186 The SH1 does not have delay slots, hence we get a pipeline stall
2187 at every branch. The SH4 is superscalar, so the single delay slot
2188 is not sufficient to keep both pipelines filled. */
2189 #define BRANCH_COST(speed_p, predictable_p) \
2190 (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2191 \f
2192 /* Assembler output control. */
2193
2194 /* A C string constant describing how to begin a comment in the target
2195 assembler language. The compiler assumes that the comment will end at
2196 the end of the line. */
2197 #define ASM_COMMENT_START "!"
2198
2199 #define ASM_APP_ON ""
2200 #define ASM_APP_OFF ""
2201 #define FILE_ASM_OP "\t.file\n"
2202 #define SET_ASM_OP "\t.set\t"
2203
2204 /* How to change between sections. */
2205
2206 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2207 #define DATA_SECTION_ASM_OP "\t.data"
2208
2209 #if defined CRT_BEGIN || defined CRT_END
2210 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2211 # undef TEXT_SECTION_ASM_OP
2212 # if __SHMEDIA__ == 1 && __SH5__ == 32
2213 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2214 # else
2215 # define TEXT_SECTION_ASM_OP "\t.text"
2216 # endif
2217 #endif
2218
2219
2220 /* If defined, a C expression whose value is a string containing the
2221 assembler operation to identify the following data as
2222 uninitialized global data. If not defined, and neither
2223 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2224 uninitialized global data will be output in the data section if
2225 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2226 used. */
2227 #ifndef BSS_SECTION_ASM_OP
2228 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2229 #endif
2230
2231 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2232 separate, explicit argument. If you define this macro, it is used
2233 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2234 handling the required alignment of the variable. The alignment is
2235 specified as the number of bits.
2236
2237 Try to use function `asm_output_aligned_bss' defined in file
2238 `varasm.c' when defining this macro. */
2239 #ifndef ASM_OUTPUT_ALIGNED_BSS
2240 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2241 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2242 #endif
2243
2244 /* Define this so that jump tables go in same section as the current function,
2245 which could be text or it could be a user defined section. */
2246 #define JUMP_TABLES_IN_TEXT_SECTION 1
2247
2248 #undef DO_GLOBAL_CTORS_BODY
2249 #define DO_GLOBAL_CTORS_BODY \
2250 { \
2251 typedef void (*pfunc) (void); \
2252 extern pfunc __ctors[]; \
2253 extern pfunc __ctors_end[]; \
2254 pfunc *p; \
2255 for (p = __ctors_end; p > __ctors; ) \
2256 { \
2257 (*--p)(); \
2258 } \
2259 }
2260
2261 #undef DO_GLOBAL_DTORS_BODY
2262 #define DO_GLOBAL_DTORS_BODY \
2263 { \
2264 typedef void (*pfunc) (void); \
2265 extern pfunc __dtors[]; \
2266 extern pfunc __dtors_end[]; \
2267 pfunc *p; \
2268 for (p = __dtors; p < __dtors_end; p++) \
2269 { \
2270 (*p)(); \
2271 } \
2272 }
2273
2274 #define ASM_OUTPUT_REG_PUSH(file, v) \
2275 { \
2276 if (TARGET_SHMEDIA) \
2277 { \
2278 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2279 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2280 } \
2281 else \
2282 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2283 }
2284
2285 #define ASM_OUTPUT_REG_POP(file, v) \
2286 { \
2287 if (TARGET_SHMEDIA) \
2288 { \
2289 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2290 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2291 } \
2292 else \
2293 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2294 }
2295
2296 /* DBX register number for a given compiler register number. */
2297 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2298 to match gdb. */
2299 /* svr4.h undefines this macro, yet we really want to use the same numbers
2300 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2301 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2302 register exists, so we should return -1 for invalid register numbers. */
2303 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2304
2305 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2306 used to use the encodings 245..260, but that doesn't make sense:
2307 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2308 the FP registers stay the same when switching between compact and media
2309 mode. Hence, we also need to use the same dwarf frame columns.
2310 Likewise, we need to support unwind information for SHmedia registers
2311 even in compact code. */
2312 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2313 (IN_RANGE ((REGNO), \
2314 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2315 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2316 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2317 : ((int) (REGNO) >= FIRST_FP_REG \
2318 && ((int) (REGNO) \
2319 <= (FIRST_FP_REG + \
2320 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2321 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2322 + (TARGET_SH5 ? 77 : 25)) \
2323 : XD_REGISTER_P (REGNO) \
2324 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2325 : TARGET_REGISTER_P (REGNO) \
2326 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2327 : (REGNO) == PR_REG \
2328 ? (TARGET_SH5 ? 18 : 17) \
2329 : (REGNO) == PR_MEDIA_REG \
2330 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2331 : (REGNO) == GBR_REG \
2332 ? (TARGET_SH5 ? 238 : 18) \
2333 : (REGNO) == MACH_REG \
2334 ? (TARGET_SH5 ? 239 : 20) \
2335 : (REGNO) == MACL_REG \
2336 ? (TARGET_SH5 ? 240 : 21) \
2337 : (REGNO) == T_REG \
2338 ? (TARGET_SH5 ? 242 : 22) \
2339 : (REGNO) == FPUL_REG \
2340 ? (TARGET_SH5 ? 244 : 23) \
2341 : (REGNO) == FPSCR_REG \
2342 ? (TARGET_SH5 ? 243 : 24) \
2343 : (unsigned) -1)
2344
2345 /* This is how to output a reference to a symbol_ref. On SH5,
2346 references to non-code symbols must be preceded by `datalabel'. */
2347 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2348 do \
2349 { \
2350 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2351 fputs ("datalabel ", (FILE)); \
2352 assemble_name ((FILE), XSTR ((SYM), 0)); \
2353 } \
2354 while (0)
2355
2356 /* This is how to output an assembler line
2357 that says to advance the location counter
2358 to a multiple of 2**LOG bytes. */
2359
2360 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2361 if ((LOG) != 0) \
2362 fprintf ((FILE), "\t.align %d\n", (LOG))
2363
2364 /* Globalizing directive for a label. */
2365 #define GLOBAL_ASM_OP "\t.global\t"
2366
2367 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2368
2369 /* Output a relative address table. */
2370
2371 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2372 switch (GET_MODE (BODY)) \
2373 { \
2374 case SImode: \
2375 if (TARGET_SH5) \
2376 { \
2377 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2378 (VALUE), (REL)); \
2379 break; \
2380 } \
2381 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2382 break; \
2383 case HImode: \
2384 if (TARGET_SH5) \
2385 { \
2386 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2387 (VALUE), (REL)); \
2388 break; \
2389 } \
2390 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2391 break; \
2392 case QImode: \
2393 if (TARGET_SH5) \
2394 { \
2395 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2396 (VALUE), (REL)); \
2397 break; \
2398 } \
2399 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2400 break; \
2401 default: \
2402 break; \
2403 }
2404
2405 /* Output an absolute table element. */
2406
2407 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2408 if (! optimize || TARGET_BIGTABLE) \
2409 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2410 else \
2411 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2412
2413 \f
2414 /* A C statement to be executed just prior to the output of
2415 assembler code for INSN, to modify the extracted operands so
2416 they will be output differently.
2417
2418 Here the argument OPVEC is the vector containing the operands
2419 extracted from INSN, and NOPERANDS is the number of elements of
2420 the vector which contain meaningful data for this insn.
2421 The contents of this vector are what will be used to convert the insn
2422 template into assembler code, so you can change the assembler output
2423 by changing the contents of the vector. */
2424
2425 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2426 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2427
2428 /* Recognize machine-specific patterns that may appear within
2429 constants. Used for PIC-specific UNSPECs. */
2430 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2431 do \
2432 if (GET_CODE (X) == UNSPEC) \
2433 { \
2434 switch (XINT ((X), 1)) \
2435 { \
2436 case UNSPEC_DATALABEL: \
2437 fputs ("datalabel ", (STREAM)); \
2438 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2439 break; \
2440 case UNSPEC_PIC: \
2441 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
2442 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2443 break; \
2444 case UNSPEC_GOT: \
2445 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2446 fputs ("@GOT", (STREAM)); \
2447 break; \
2448 case UNSPEC_GOTOFF: \
2449 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2450 fputs ("@GOTOFF", (STREAM)); \
2451 break; \
2452 case UNSPEC_PLT: \
2453 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2454 fputs ("@PLT", (STREAM)); \
2455 break; \
2456 case UNSPEC_GOTPLT: \
2457 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2458 fputs ("@GOTPLT", (STREAM)); \
2459 break; \
2460 case UNSPEC_DTPOFF: \
2461 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2462 fputs ("@DTPOFF", (STREAM)); \
2463 break; \
2464 case UNSPEC_GOTTPOFF: \
2465 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2466 fputs ("@GOTTPOFF", (STREAM)); \
2467 break; \
2468 case UNSPEC_TPOFF: \
2469 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2470 fputs ("@TPOFF", (STREAM)); \
2471 break; \
2472 case UNSPEC_CALLER: \
2473 { \
2474 char name[32]; \
2475 /* LPCS stands for Label for PIC Call Site. */ \
2476 ASM_GENERATE_INTERNAL_LABEL \
2477 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
2478 assemble_name ((STREAM), name); \
2479 } \
2480 break; \
2481 case UNSPEC_EXTRACT_S16: \
2482 case UNSPEC_EXTRACT_U16: \
2483 { \
2484 rtx val, shift; \
2485 \
2486 val = XVECEXP (X, 0, 0); \
2487 shift = XVECEXP (X, 0, 1); \
2488 fputc ('(', STREAM); \
2489 if (shift != const0_rtx) \
2490 fputc ('(', STREAM); \
2491 if (GET_CODE (val) == CONST \
2492 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) \
2493 { \
2494 fputc ('(', STREAM); \
2495 output_addr_const (STREAM, val); \
2496 fputc (')', STREAM); \
2497 } \
2498 else \
2499 output_addr_const (STREAM, val); \
2500 if (shift != const0_rtx) \
2501 { \
2502 fputs (" >> ", STREAM); \
2503 output_addr_const (STREAM, shift); \
2504 fputc (')', STREAM); \
2505 } \
2506 fputs (" & 65535)", STREAM); \
2507 } \
2508 break; \
2509 case UNSPEC_SYMOFF: \
2510 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2511 fputc ('-', STREAM); \
2512 if (GET_CODE (XVECEXP (X, 0, 1)) == CONST) \
2513 { \
2514 fputc ('(', STREAM); \
2515 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2516 fputc (')', STREAM); \
2517 } \
2518 else \
2519 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2520 break; \
2521 case UNSPEC_PCREL_SYMOFF: \
2522 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2523 fputs ("-(", STREAM); \
2524 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2525 fputs ("-.)", STREAM); \
2526 break; \
2527 default: \
2528 goto FAIL; \
2529 } \
2530 break; \
2531 } \
2532 else \
2533 goto FAIL; \
2534 while (0)
2535
2536 \f
2537 extern struct rtx_def *sh_compare_op0;
2538 extern struct rtx_def *sh_compare_op1;
2539
2540 /* Which processor to schedule for. The elements of the enumeration must
2541 match exactly the cpu attribute in the sh.md file. */
2542
2543 enum processor_type {
2544 PROCESSOR_SH1,
2545 PROCESSOR_SH2,
2546 PROCESSOR_SH2E,
2547 PROCESSOR_SH2A,
2548 PROCESSOR_SH3,
2549 PROCESSOR_SH3E,
2550 PROCESSOR_SH4,
2551 PROCESSOR_SH4A,
2552 PROCESSOR_SH5
2553 };
2554
2555 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2556 extern enum processor_type sh_cpu;
2557
2558 extern int optimize; /* needed for gen_casesi. */
2559
2560 enum mdep_reorg_phase_e
2561 {
2562 SH_BEFORE_MDEP_REORG,
2563 SH_INSERT_USES_LABELS,
2564 SH_SHORTEN_BRANCHES0,
2565 SH_FIXUP_PCLOAD,
2566 SH_SHORTEN_BRANCHES1,
2567 SH_AFTER_MDEP_REORG
2568 };
2569
2570 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2571
2572 /* Handle Renesas compiler's pragmas. */
2573 #define REGISTER_TARGET_PRAGMAS() do { \
2574 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2575 c_register_pragma (0, "trapa", sh_pr_trapa); \
2576 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2577 } while (0)
2578
2579 extern tree sh_deferred_function_attributes;
2580 extern tree *sh_deferred_function_attributes_tail;
2581
2582 /* Set when processing a function with interrupt attribute. */
2583
2584 extern int current_function_interrupt;
2585
2586 \f
2587 /* Instructions with unfilled delay slots take up an
2588 extra two bytes for the nop in the delay slot.
2589 sh-dsp parallel processing insns are four bytes long. */
2590
2591 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2592 (LENGTH) += sh_insn_length_adjustment (X);
2593 \f
2594 /* Define this macro if it is advisable to hold scalars in registers
2595 in a wider mode than that declared by the program. In such cases,
2596 the value is constrained to be within the bounds of the declared
2597 type, but kept valid in the wider mode. The signedness of the
2598 extension may differ from that of the type.
2599
2600 Leaving the unsignedp unchanged gives better code than always setting it
2601 to 0. This is despite the fact that we have only signed char and short
2602 load instructions. */
2603 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2604 if (GET_MODE_CLASS (MODE) == MODE_INT \
2605 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2606 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2607 (MODE) = (TARGET_SH1 ? SImode \
2608 : TARGET_SHMEDIA32 ? SImode : DImode);
2609
2610 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2611
2612 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
2613
2614 /* Better to allocate once the maximum space for outgoing args in the
2615 prologue rather than duplicate around each call. */
2616 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
2617
2618 #define SH_DYNAMIC_SHIFT_COST \
2619 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
2620
2621
2622 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2623
2624 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2625
2626 #define ACTUAL_NORMAL_MODE(ENTITY) \
2627 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2628
2629 #define NORMAL_MODE(ENTITY) \
2630 (sh_cfun_interrupt_handler_p () \
2631 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2632 : ACTUAL_NORMAL_MODE (ENTITY))
2633
2634 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
2635
2636 #define MODE_EXIT(ENTITY) \
2637 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
2638
2639 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2640 && (REGNO) == FPSCR_REG)
2641
2642 #define MODE_NEEDED(ENTITY, INSN) \
2643 (recog_memoized (INSN) >= 0 \
2644 ? get_attr_fp_mode (INSN) \
2645 : FP_MODE_NONE)
2646
2647 #define MODE_AFTER(MODE, INSN) \
2648 (TARGET_HITACHI \
2649 && recog_memoized (INSN) >= 0 \
2650 && get_attr_fp_set (INSN) != FP_SET_NONE \
2651 ? (int) get_attr_fp_set (INSN) \
2652 : (MODE))
2653
2654 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2655 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2656
2657 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2658 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2659
2660 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2661 sh_can_redirect_branch ((INSN), (SEQ))
2662
2663 #define DWARF_FRAME_RETURN_COLUMN \
2664 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2665
2666 #define EH_RETURN_DATA_REGNO(N) \
2667 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2668
2669 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2670 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2671
2672 /* We have to distinguish between code and data, so that we apply
2673 datalabel where and only where appropriate. Use sdataN for data. */
2674 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2675 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2676 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2677 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2678
2679 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2680 indirect are handled automatically. */
2681 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2682 do { \
2683 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2684 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2685 { \
2686 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2687 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2688 if (0) goto DONE; \
2689 } \
2690 } while (0)
2691
2692 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2693 /* SH constant pool breaks the devices in crtstuff.c to control section
2694 in where code resides. We have to write it as asm code. */
2695 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2696 asm (SECTION_OP "\n\
2697 mov.l 1f,r1\n\
2698 mova 2f,r0\n\
2699 braf r1\n\
2700 lds r0,pr\n\
2701 0: .p2align 2\n\
2702 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2703 2:\n" TEXT_SECTION_ASM_OP);
2704 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2705
2706 /* FIXME: middle-end support for highpart optimizations is missing. */
2707 #define high_life_started reload_in_progress
2708
2709 #endif /* ! GCC_SH_H */
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