1 # Copyright
(C
) 1999-2024 Free Software Foundation
, Inc.
3 # This
program is free software
; you can redistribute it and
/or modify
4 # it under the terms of the GNU General Public License as published by
5 # the Free Software Foundation
; either version
3 of the License
, or
6 #
(at your option
) any later version.
8 # This
program is distributed in the hope that it will be useful
,
9 # but WITHOUT
ANY WARRANTY
; without even the implied warranty of
10 # MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the
11 # GNU General Public License
for more details.
13 # You should have received a copy of the GNU General Public License
14 # along with GCC
; see the file COPYING3.
If not see
15 #
<http
://www.gnu.org
/licenses
/>.
17 # Please email
any bugs
, comments
, and
/or additions to this file to
:
18 # gcc
-patches@gcc.gnu.org
20 # This file defines procs
for determining features supported by the target.
22 # Try to
compile the code given by CONTENTS into an output file of
23 # type TYPE
, where TYPE is as
for target_compile.
Return a list
24 # whose first element contains the compiler messages and whose
25 # second element is the
name of the output file.
27 # BASENAME is a prefix to use
for source and output files.
28 #
If ARGS is not empty
, its first element is a string that
29 # should be added to the command line.
31 # Assume by default that CONTENTS is C code.
32 # Otherwise
, code should contain
:
33 #
"/* Assembly" for assembly code,
36 #
"! Fortran" for Fortran code,
38 #
"// ObjC++" for ObjC++
41 # and
"(* Modula-2" for Modula-2
42 #
If the tool is ObjC
/ObjC
++ then we overide the extension to .m
/.mm to
43 # allow
for ObjC
/ObjC
++ specific flags.
45 proc check_compile
{basename type contents
args} {
47 verbose
"check_compile tool: $tool for $basename"
49 # Save additional_sources to avoid compiling testsuite
's sources
50 # against check_compile's source.
51 global additional_sources
52 if [info exists additional_sources
] {
53 set tmp_additional_sources
"$additional_sources"
54 set additional_sources
""
57 if { [llength $
args] > 0 } {
58 set options
[list
"additional_flags=[lindex $args 0]"]
62 # Silence
"command-line option [...] is valid for [...] but not for [...]"
63 # that we may easily run into here
, if more than one language is involved.
64 lappend options additional_flags
=-Wno
-complain
-wrong
-lang
66 switch -glob
-- $contents
{
67 "*/\\* Assembly*" { set src ${basename}[pid].S }
68 "*! Fortran*" { set src ${basename}[pid].f90 }
69 "*// C++*" { set src ${basename}[pid].cc }
70 "*// D*" { set src ${basename}[pid].d }
71 "*// ObjC++*" { set src ${basename}[pid].mm }
72 "*/\\* ObjC*" { set src ${basename}[pid].m }
73 "*// Go*" { set src ${basename}[pid].go }
74 "*// Rust*" { set src ${basename}[pid].rs }
75 "*(\\* Modula-2*" { set src ${basename}[pid].mod }
78 "objc" { set src ${basename}[pid].m }
79 "obj-c++" { set src ${basename}[pid].mm }
80 default
{ set src $
{basename
}[pid
].c
}
85 set compile_type $type
87 assembly
{ set output $
{basename
}[pid
].s
}
88 object
{ set output $
{basename
}[pid
].o
}
89 executable
{ set output $
{basename
}[pid
].exe
}
92 set output $
{basename
}[pid
].s
93 lappend options
"additional_flags=-fdump-$type"
94 set compile_type assembly
100 global compiler_flags
101 set save_compiler_flags $compiler_flags
102 set lines
[$
{tool
}_target_compile $src $output $compile_type
"$options"]
103 set compiler_flags $save_compiler_flags
106 set scan_output $output
107 # Don
't try folding this into the switch above; calling "glob" before the
108 # file is created won't work.
109 if [regexp
"rtl-(.*)" $type dummy rtl_type] {
110 set scan_output
"[glob $src.\[0-9\]\[0-9\]\[0-9\]r.$rtl_type]"
112 } elseif
[regexp
"tree-(.*)" $type dummy tree_type] {
113 set scan_output
"[glob $src.\[0-9\]\[0-9\]\[0-9\]t.$tree_type]"
117 # Restore additional_sources.
118 if [info exists additional_sources
] {
119 set additional_sources
"$tmp_additional_sources"
122 return [list $lines $scan_output
]
125 proc current_target_name
{ } {
127 if [info exists target_info
(target
,name)] {
128 set answer $target_info
(target
,name)
135 # Implement an effective
-target check
for property PROP by invoking
136 # the Tcl command
ARGS and seeing
if it returns true.
138 proc check_cached_effective_target
{ prop
args } {
141 set target
[current_target_name
]
142 if {![info exists et_cache
($prop
,$target
)]} {
143 verbose
"check_cached_effective_target $prop: checking $target" 2
144 if {[string is true
-strict $
args] ||
[string is false
-strict $
args]} {
145 error
{check_cached_effective_target condition already evaluated
; did you pass
[...
] instead of the expected
{...
}?
}
147 set code
[catch
{uplevel eval $
args} result
]
148 if {$code
!= 0 && $code
!= 2} {
149 return -code $code $result
151 set et_cache
($prop
,$target
) $result
154 set value $et_cache
($prop
,$target
)
155 verbose
"check_cached_effective_target $prop: returning $value for $target" 2
159 # Implements a version of check_cached_effective_target that also takes et_index
160 # into account when creating the
key for the
cache.
161 proc check_cached_effective_target_indexed
{ prop
args } {
163 set key "$et_index $prop"
164 verbose
"check_cached_effective_target_index $prop: returning $key" 2
166 return [check_cached_effective_target $
key [list uplevel eval $
args]]
169 # Clear effective
-target
cache. This is useful after testing
170 # effective
-target features and overriding TEST_ALWAYS_FLAGS and
/or
172 #
If one changes ALWAYS_CXXFLAGS or TEST_ALWAYS_FLAGS
then they should
173 #
do a clear_effective_target_cache at the end as the target
cache can
174 # make decisions based upon the flags
, and those decisions need to be
175 # redone when the flags change. An example of this is the
176 # asan_init
/asan_finish pair.
178 proc clear_effective_target_cache
{ } {
183 # Like check_compile
, but
delete the output file and
return true
if the
184 # compiler printed no messages.
185 proc check_no_compiler_messages_nocache
{args} {
186 set result
[eval check_compile $
args]
187 set lines
[lindex $result
0]
188 set output
[lindex $result
1]
189 remote_file build
delete $output
190 return [string match
"" $lines]
193 # Like check_no_compiler_messages_nocache
, but
cache the result.
194 # PROP is the
property we
're checking, and doubles as a prefix for
195 # temporary filenames.
196 proc check_no_compiler_messages {prop args} {
197 return [check_cached_effective_target $prop {
198 eval [list check_no_compiler_messages_nocache $prop] $args
202 # Like check_compile, but return true if the compiler printed no
203 # messages and if the contents of the output file satisfy PATTERN.
204 # If PATTERN has the form "!REGEXP", the contents satisfy it if they
205 # don't match regular expression REGEXP
, otherwise they satisfy it
206 #
if they
do match regular expression PATTERN.
(PATTERN can start
207 # with something like
"[!]" if the regular expression needs to match
208 #
"!" as the first character.)
210 #
Delete the output file before returning. The other arguments are
211 # as
for check_compile.
212 proc check_no_messages_and_pattern_nocache
{basename pattern
args} {
215 set result
[eval
[list check_compile $basename
] $
args]
216 set lines
[lindex $result
0]
217 set output
[lindex $result
1]
220 if { [string match
"" $lines] } {
221 set chan
[open
"$output"]
222 set invert
[regexp
{^
!(.
*)} $pattern dummy pattern
]
223 set ok
[expr
{ [regexp $pattern
[read $chan
]] != $invert
}]
227 remote_file build
delete $output
231 # Like check_no_messages_and_pattern_nocache
, but
cache the result.
232 # PROP is the
property we
're checking, and doubles as a prefix for
233 # temporary filenames.
234 proc check_no_messages_and_pattern {prop pattern args} {
235 return [check_cached_effective_target $prop {
236 eval [list check_no_messages_and_pattern_nocache $prop $pattern] $args
240 # Try to compile and run an executable from code CONTENTS. Return true
241 # if the compiler reports no messages and if execution "passes" in the
242 # usual DejaGNU sense. The arguments are as for check_compile, with
243 # TYPE implicitly being "executable".
244 proc check_runtime_nocache {basename contents args} {
247 set result [eval [list check_compile $basename executable $contents] $args]
248 set lines [lindex $result 0]
249 set output [lindex $result 1]
252 if { [string match "" $lines] } {
253 # No error messages, everything is OK.
254 set result [remote_load target "./$output" "" ""]
255 set status [lindex $result 0]
256 verbose "check_runtime_nocache $basename: status is <$status>" 2
257 if { $status == "pass" } {
261 remote_file build delete $output
265 # Like check_runtime_nocache, but cache the result. PROP is the
266 # property we're checking
, and doubles as a prefix
for temporary
268 proc check_runtime
{prop
args} {
271 return [check_cached_effective_target $prop
{
272 eval
[list check_runtime_nocache $prop
] $
args
276 #
Return 1 if GCC was configured with $pattern.
277 proc check_configured_with
{ pattern
} {
280 set options
[list
"additional_flags=-v"]
281 set gcc_output
[$
{tool
}_target_compile
"" "" "none" $options]
282 if { [ regexp
"Configured with: \[^\n\]*$pattern" $gcc_output ] } {
283 verbose
"Matched: $pattern" 2
287 verbose
"Failed to match: $pattern" 2
291 ###############################
292 # proc check_weak_available
{ }
293 ###############################
295 # weak symbols are only supported in some configs
/object formats
296 # this proc returns
1 if they
're supported, 0 if they're not
, or
-1 if unsure
298 proc check_weak_available
{ } {
301 # All mips targets should support it
303 if { [ string first
"mips" $target_cpu ] >= 0 } {
307 # All AIX targets should support it
309 if { [istarget
*-*-aix
*] } {
313 # All solaris2 targets should support it
315 if { [istarget
*-*-solaris2
*] } {
319 # Windows targets Cygwin and MingW32 support it
321 if { [istarget
*-*-cygwin
*] ||
[istarget
*-*-mingw
*] } {
325 # nvptx
(nearly
) supports it
327 if { [istarget nvptx
-*-*] } {
331 # pdp11 doesn
't support it
333 if { [istarget pdp11*-*-*] } {
337 # VxWorks hardly supports it (vx7 RTPs only)
339 if { [istarget *-*-vxworks*] } {
343 # ELF and ECOFF support it. a.out does with gas/gld but may also with
344 # other linkers, so we should try it
346 set objformat [gcc_target_object_format]
354 unknown { return -1 }
359 # return options to add to enable weak undefined symbols.
361 proc add_options_for_weak_undefined { flags } {
362 if { [istarget *-*-darwin*] } {
363 lappend flags "-Wl,-undefined,dynamic_lookup"
364 if { [istarget *-*-darwin\[89\]*] } {
365 lappend flags "-Wl,-flat_namespace"
371 # return 1 if weak undefined symbols are supported.
373 proc check_effective_target_weak_undefined { } {
374 if { [istarget hppa*-*-hpux*] } {
377 return [check_runtime weak_undefined {
378 extern void foo () __attribute__((weak));
379 int main (void) { if (foo) return 1; return 0; }
380 } [add_options_for_weak_undefined ""]]
383 ###############################
384 # proc check_weak_override_available { }
385 ###############################
387 # Like check_weak_available, but return 0 if weak symbol definitions
388 # cannot be overridden.
390 proc check_weak_override_available { } {
391 if { [istarget *-*-mingw*] } {
394 return [check_weak_available]
397 # Return 1 if VMA is equal to LMA for the .data section, 0
398 # otherwise. Cache the result.
400 proc check_effective_target_vma_equals_lma { } {
403 return [check_cached_effective_target vma_equals_lma {
404 set src vma_equals_lma[pid].c
405 set exe vma_equals_lma[pid].exe
406 verbose "check_effective_target_vma_equals_lma compiling testfile $src" 2
407 set f [open $src "w"]
408 puts $f "#ifdef __cplusplus\nextern \"C\"\n#endif\n"
409 puts $f "int foo = 42; void main() {}"
411 set lines [${tool}_target_compile $src $exe executable ""]
414 if [string match "" $lines] then {
417 set objdump_name [find_binutils_prog objdump]
418 set output [remote_exec host "$objdump_name" "--section-headers --section=.data $exe"]
419 set output [lindex $output 1]
421 remote_file build delete $exe
423 # Example output of objdump:
424 #vma_equals_lma9059.exe: file format elf32-littlearm
427 #Idx Name Size VMA LMA File off Algn
428 # 6 .data 00000558 20000000 08002658 00020000 2**3
429 # CONTENTS, ALLOC, LOAD, DATA
431 # Capture LMA and VMA columns for .data section
432 if ![ regexp {\d*\d+\s+\.data\s+\d+\s+(\d+)\s+(\d+)} $output dummy vma lma ] {
433 verbose "Could not parse objdump output" 2
436 return [string equal $vma $lma]
439 remote_file build delete $exe
440 verbose "Could not determine if VMA is equal to LMA. Assuming not equal." 2
446 # The "noinit" attribute is only supported by some targets.
447 # This proc returns 1 if it's supported
, 0 if it
's not.
449 proc check_effective_target_noinit { } {
450 if { [istarget arm*-*-eabi]
451 || [istarget msp430-*-*] } {
458 # The "persistent" attribute is only supported by some targets.
459 # This proc returns 1 if it's supported
, 0 if it
's not.
461 proc check_effective_target_persistent { } {
462 if { [istarget arm*-*-eabi]
463 || [istarget msp430-*-*] } {
470 ###############################
471 # proc check_visibility_available { what_kind }
472 ###############################
474 # The visibility attribute is only support in some object formats
475 # This proc returns 1 if it is supported, 0 if not.
476 # The argument is the kind of visibility, default/protected/hidden/internal.
478 proc check_visibility_available { what_kind } {
479 if [string match "" $what_kind] { set what_kind "hidden" }
481 return [check_no_compiler_messages visibility_available_$what_kind object "
482 void f() __attribute__((visibility(\"$what_kind\")));
487 ###############################
488 # proc check_alias_available { }
489 ###############################
491 # Determine if the target toolchain supports the alias attribute.
493 # Returns 2 if the target supports aliases. Returns 1 if the target
494 # only supports weak aliased. Returns 0 if the target does not
495 # support aliases at all. Returns -1 if support for aliases could not
498 proc check_alias_available { } {
501 return [check_cached_effective_target alias_available {
504 verbose "check_alias_available compiling testfile $src" 2
505 set f [open $src "w"]
506 # Compile a small test program. The definition of "g" is
507 # necessary to keep the Solaris assembler from complaining
509 puts $f "#ifdef __cplusplus\nextern \"C\"\n#endif\n"
510 puts $f "void g() {} void f() __attribute__((alias(\"g\")));"
512 set lines [${tool}_target_compile $src $obj object ""]
514 remote_file build delete $obj
516 if [string match "" $lines] then {
517 # No error messages, everything is OK.
520 if [regexp "alias definitions not supported" $lines] {
521 verbose "check_alias_available target does not support aliases" 2
523 set objformat [gcc_target_object_format]
525 if { $objformat == "elf" } {
526 verbose "check_alias_available but target uses ELF format, so it ought to" 2
532 if [regexp "only weak aliases are supported" $lines] {
533 verbose "check_alias_available target supports only weak aliases" 2
543 # Returns 1 if the target toolchain supports strong aliases, 0 otherwise.
545 proc check_effective_target_alias { } {
546 if { [check_alias_available] < 2 } {
553 # Returns 1 if the target uses the ELF object format, 0 otherwise.
555 proc check_effective_target_elf { } {
556 if { [gcc_target_object_format] == "elf" } {
563 # Returns 1 if the target toolchain supports ifunc, 0 otherwise.
565 proc check_ifunc_available { } {
566 return [check_no_compiler_messages ifunc_available object {
571 typedef void F (void);
572 F* g (void) { return &f_; }
573 void f () __attribute__ ((ifunc ("g")));
580 # Returns true if --gc-sections is supported on the target.
582 proc check_gc_sections_available { } {
585 return [check_cached_effective_target gc_sections_available {
586 # Some targets don't support gc
-sections despite whatever
's
587 # advertised by ld's options.
588 if { [istarget alpha
*-*-*]
589 ||
[istarget ia64
-*-*] } {
593 # elf2flt uses
-q
(--emit
-relocs
), which is incompatible with
595 if { [board_info target
exists ldflags
]
596 && [regexp
" -elf2flt\[ =\]" " [board_info target ldflags] "] } {
600 # VxWorks kernel modules are relocatable objects linked with
-r
,
601 #
while RTP executables are linked with
-q
(--emit
-relocs
).
602 # Both of these options are incompatible with
--gc
-sections.
603 if { [istarget
*-*-vxworks
*] } {
607 # Check
if the
ld used by gcc supports
--gc
-sections.
608 set options
[list
"additional_flags=-print-prog-name=ld"]
609 set gcc_ld
[lindex
[$
{tool
}_target_compile
"" "" "none" $options] 0]
610 set ld_output
[remote_exec host
"$gcc_ld" "--help"]
611 if { [ string first
"--gc-sections" $ld_output ] >= 0 } {
619 # Returns
1 if "dot" is supported on the host.
621 proc check_dot_available
{ } {
622 verbose
"check_dot_available" 2
624 set status [remote_exec host
"dot" "-V"]
625 verbose
" status: $status" 2
626 if { [lindex $
status 0] != 0 } {
632 #
Return 1 if according to target_info struct and explicit target list
633 # target is supposed to support trampolines.
635 proc check_effective_target_trampolines
{ } {
636 if [target_info
exists gcc
,no_trampolines
] {
639 if { [istarget avr
-*-*]
640 ||
[istarget msp430
-*-*]
641 ||
[istarget nvptx
-*-*]
642 ||
[istarget pru
-*-*]
643 ||
[istarget bpf
-*-*] } {
649 #
Return 1 if target has limited stack size.
651 proc check_effective_target_stack_size
{ } {
652 #
For nvptx target
, stack size limits are relevant
for execution only.
653 if { [istarget nvptx
-*-*] } {
654 # Find
'dg-do-what' in an outer frame.
657 upvar $level dg
-do-what dg
-do-what
658 if [info exists dg
-do-what
] then break
661 verbose
"check_effective_target_stack_size: found dg-do-what at level $level" 2
663 if { ![string equal
[lindex $
{dg
-do-what
} 0] run
] } {
668 if [target_info
exists gcc
,stack_size
] {
674 #
Return the value attribute of an effective target
, otherwise
return 0.
676 proc dg
-effective
-target
-value
{ effective_target
} {
677 if { "$effective_target" == "stack_size" } {
678 if [check_effective_target_stack_size
] {
679 return [target_info gcc
,stack_size
]
686 #
Return 1 if signal.h is supported.
688 proc check_effective_target_signal
{ } {
689 if [target_info
exists gcc
,signal_suppress
] {
695 #
Return 1 if according to target_info struct and explicit target list
696 # target disables
-fdelete
-null
-pointer
-checks. Targets should
return 0
697 #
if they simply default to
-fno
-delete-null
-pointer
-checks but obey
698 #
-fdelete
-null
-pointer
-checks when passed explicitly
(and tests that
699 # depend
on this option should
do that
).
701 proc check_effective_target_keeps_null_pointer_checks
{ } {
702 if [target_info
exists keeps_null_pointer_checks
] {
705 if { [istarget msp430
-*-*]
706 ||
[istarget avr
-*-*] } {
712 #
Return the autofdo profile wrapper
714 # Linux by default allows
516KB of perf event buffers
715 # in
/proc
/sys
/kernel
/perf_event_mlock_kb
716 # Each individual perf tries to grab it
717 # This causes problems with parallel test suite runs. Instead
718 #
limit us to
8 pages
(32K
), which should be good enough
719 #
for the small test programs. With the default settings
720 # this allows parallelism of
16 and higher of parallel gcc
-auto
-profile
721 proc profopt
-perf
-wrapper
{ } {
723 return "$srcdir/../config/i386/gcc-auto-profile --all -m8 "
726 #
Return true
if profiling is supported
on the target.
728 proc check_profiling_available
{ test_what
} {
729 verbose
"Profiling argument is <$test_what>" 1
731 # These conditions depend
on the
argument so examine them before
732 # looking at the
cache variable.
734 # Tree profiling requires TLS runtime support.
735 if { $test_what
== "-fprofile-generate" } {
736 if { ![check_effective_target_tls_runtime
] } {
741 if { $test_what
== "-fauto-profile" } {
742 if { !([istarget i?
86-*-linux
*] ||
[istarget x86_64
-*-linux
*]) } {
743 verbose
"autofdo only supported on linux"
746 # not cross compiling?
748 verbose
"autofdo not supported for non native builds"
751 set event
[profopt
-perf
-wrapper
]
753 verbose
"autofdo not supported"
757 set status [remote_exec host
"$srcdir/../config/i386/gcc-auto-profile" "-m8 true -v >/dev/null"]
758 if { [lindex $
status 0] != 0 } {
759 verbose
"autofdo not supported because perf does not work"
763 # no good way to check this in advance
-- check later instead.
764 #
set status [remote_exec host
"create_gcov" "2>/dev/null"]
765 #
if { [lindex $
status 0] != 255 } {
766 # verbose
"autofdo not supported due to missing create_gcov"
771 # Support
for -p
on solaris2 relies
on mcrt1.o which comes with the
772 # vendor compiler. We cannot reliably predict the directory where the
773 # vendor compiler
(and thus mcrt1.o
) is installed so we can
't
774 # necessarily find mcrt1.o even if we have it.
775 if { [istarget *-*-solaris2*] && $test_what == "-p" } {
779 # We don't yet support profiling
for MIPS16.
780 if { [istarget mips
*-*-*]
781 && ![check_effective_target_nomips16
]
782 && ($test_what
== "-p" || $test_what == "-pg") } {
786 # MinGW does not support
-p.
787 if { [istarget
*-*-mingw
*] && $test_what
== "-p" } {
791 # cygwin does not support
-p.
792 if { [istarget
*-*-cygwin
*] && $test_what
== "-p" } {
796 # uClibc does not have gcrt1.o.
797 if { [check_effective_target_uclibc
]
798 && ($test_what
== "-p" || $test_what == "-pg") } {
802 # Now examine the
cache variable.
803 set profiling_working \
804 [check_cached_effective_target profiling_available
{
805 # Some targets don
't have any implementation of __bb_init_func or are
806 # missing other needed machinery.
807 if {[istarget aarch64*-*-elf]
808 || [istarget am3*-*-linux*]
809 || [istarget amdgcn-*-*]
810 || [istarget arm*-*-eabi*]
811 || [istarget arm*-*-elf]
812 || [istarget arm*-*-symbianelf*]
813 || [istarget avr-*-*]
814 || [istarget bfin-*-*]
815 || [istarget cris-*-*]
816 || [istarget csky-*-elf*]
817 || [istarget fido-*-elf]
818 || [istarget h8300-*-*]
819 || [istarget lm32-*-*]
820 || [istarget m32c-*-elf]
821 || [istarget m68k-*-elf]
822 || [istarget m68k-*-uclinux*]
823 || [istarget mips*-*-elf*]
824 || [istarget mmix-*-*]
825 || [istarget mn10300-*-elf*]
826 || [istarget moxie-*-elf*]
827 || [istarget msp430-*-*]
828 || [istarget nds32*-*-elf]
829 || [istarget nios2-*-elf]
830 || [istarget nvptx-*-*]
831 || [istarget powerpc-*-eabi*]
832 || [istarget powerpc-*-elf]
833 || [istarget pru-*-*]
835 || [istarget tic6x-*-elf]
836 || [istarget visium-*-*]
837 || [istarget xstormy16-*]
838 || [istarget xtensa*-*-elf]
839 || [istarget *-*-rtems*]
840 || [istarget *-*-vxworks*] } {
847 # -pg link test result can't be cached since it may change between
849 if { $profiling_working
== 1
850 && ![check_no_compiler_messages_nocache profiling executable
{
851 int main
() { return 0; } } "-pg"] } {
852 set profiling_working
0
855 return $profiling_working
858 # Check to see
if a target is
"freestanding". This is as per the definition
859 # in Section
4 of C99 standard. Effectively
, it is a target which supports no
860 # extra headers or libraries other than what is considered essential.
861 proc check_effective_target_freestanding
{ } {
862 if { [istarget nvptx
-*-*] } {
868 # Check to see that file I
/O functions are available.
869 proc check_effective_target_fileio
{ } {
870 return [check_no_compiler_messages fileio_available executable
{
873 char
*n
= tmpnam
(NULL
);
874 FILE
*f
= fopen
(n
, "w");
881 #
Return 1 if target has packed layout of structure members by
882 # default
, 0 otherwise. Note that this is slightly different than
883 # whether the target has
"natural alignment": both attributes may be
886 proc check_effective_target_default_packed
{ } {
887 return [check_no_compiler_messages default_packed assembly
{
888 struct x
{ char a
; long b
; } c
;
889 int s
[sizeof
(c
) == sizeof
(char
) + sizeof
(long
) ?
1 : -1];
893 #
Return 1 if target has PCC_BITFIELD_TYPE_MATTERS defined. See
894 # documentation
, where the test also comes from.
896 proc check_effective_target_pcc_bitfield_type_matters
{ } {
897 # PCC_BITFIELD_TYPE_MATTERS isn
't just about unnamed or empty
898 # bitfields, but let's stick to the example code from the docs.
899 return [check_no_compiler_messages pcc_bitfield_type_matters assembly
{
900 struct foo1
{ char x
; char
:0; char y
; };
901 struct foo2
{ char x
; int :0; char y
; };
902 int s
[sizeof
(struct foo1
) != sizeof
(struct foo2
) ?
1 : -1];
906 # Add to FLAGS all the target
-specific flags needed to use thread
-local storage.
908 proc add_options_for_tls
{ flags
} {
909 #
On AIX
, __tls_get_addr
/___tls_get_addr only lives in
910 # libthread
, so always pass
-pthread
for native TLS.
911 # Need to duplicate native TLS check from
912 # check_effective_target_tls_native to avoid recursion.
913 if { ([istarget powerpc
-ibm
-aix
*]) &&
914 [check_no_messages_and_pattern tls_native
"!emutls" assembly {
916 int f
(void
) { return i
; }
917 void g
(int j
) { i
= j
; }
919 return "-pthread [g++_link_flags [get_multilibs "-pthread"] ] $flags "
924 #
Return 1 if indirect jumps are supported
, 0 otherwise.
926 proc check_effective_target_indirect_jumps
{} {
927 if { [istarget nvptx
-*-*] ||
[istarget bpf
-*-*] } {
933 #
Return 1 if nonlocal
goto is supported
, 0 otherwise.
935 proc check_effective_target_nonlocal_goto
{} {
936 if { [istarget nvptx
-*-*] ||
[istarget bpf
-*-*] } {
942 #
Return 1 if global constructors are supported
, 0 otherwise.
944 proc check_effective_target_global_constructor
{} {
945 if { [istarget nvptx
-*-*]
946 ||
[istarget bpf
-*-*] } {
952 #
Return 1 if taking label
values is supported
, 0 otherwise.
954 proc check_effective_target_label_values
{} {
955 if { [istarget nvptx
-*-*] ||
[target_info
exists gcc
,no_label_values
] } {
962 #
Return 1 if builtin_return_address and builtin_frame_address are
963 # supported
, 0 otherwise.
965 proc check_effective_target_return_address
{} {
966 if { [istarget nvptx
-*-*] } {
969 # No notion of
return address in eBPF.
970 if { [istarget bpf
-*-*] } {
973 # It could be supported
on amdgcn
, but isn
't yet.
974 if { [istarget amdgcn*-*-*] } {
980 # Return 1 if the assembler does not verify function types against
981 # calls, 0 otherwise. Such verification will typically show up problems
982 # with K&R C function declarations.
984 proc check_effective_target_untyped_assembly {} {
985 if { [istarget nvptx-*-*] } {
991 # Return 1 if alloca is supported, 0 otherwise.
993 proc check_effective_target_alloca {} {
994 if { [istarget bpf-*-*] } {
997 if { [istarget nvptx-*-*] } {
998 return [check_no_compiler_messages alloca assembly {
1000 void g (int n) { f (__builtin_alloca (n)); }
1006 # Return 1 if thread local storage (TLS) is supported, 0 otherwise.
1008 proc check_effective_target_tls {} {
1009 return [check_no_compiler_messages tls assembly {
1011 int f (void) { return i; }
1012 void g (int j) { i = j; }
1016 # Return 1 if *native* thread local storage (TLS) is supported, 0 otherwise.
1018 proc check_effective_target_tls_native {} {
1019 # VxWorks uses emulated TLS machinery, but with non-standard helper
1020 # functions, so we fail to automatically detect it.
1021 if { [istarget *-*-vxworks*] } {
1025 return [check_no_messages_and_pattern tls_native "!emutls" assembly {
1027 int f (void) { return i; }
1028 void g (int j) { i = j; }
1032 # Return 1 if *emulated* thread local storage (TLS) is supported, 0 otherwise.
1034 proc check_effective_target_tls_emulated {} {
1035 # VxWorks uses emulated TLS machinery, but with non-standard helper
1036 # functions, so we fail to automatically detect it.
1037 if { [istarget *-*-vxworks*] } {
1041 return [check_no_messages_and_pattern tls_emulated "emutls" assembly {
1043 int f (void) { return i; }
1044 void g (int j) { i = j; }
1048 # Return 1 if TLS executables can run correctly, 0 otherwise.
1050 proc check_effective_target_tls_runtime {} {
1051 return [check_runtime tls_runtime {
1052 __thread int thr __attribute__((tls_model("global-dynamic"))) = 0;
1053 int main (void) { return thr; }
1054 } [add_options_for_tls ""]]
1057 # Return 1 if atomic compare-and-swap is supported on 'int'
1059 proc check_effective_target_cas_char {} {
1060 return [check_no_compiler_messages cas_char assembly {
1061 #ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
1067 proc check_effective_target_cas_int {} {
1068 return [check_no_compiler_messages cas_int assembly {
1069 #if __INT_MAX__ == 0x7fff && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
1071 #elif __INT_MAX__ == 0x7fffffff && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
1079 # Return 1 if -ffunction-sections is supported, 0 otherwise.
1081 proc check_effective_target_function_sections {} {
1082 # Darwin has its own scheme and silently accepts -ffunction-sections.
1083 if { [istarget *-*-darwin*] } {
1087 return [check_no_compiler_messages functionsections assembly {
1089 } "-ffunction-sections"]
1092 # Return 1 if instruction scheduling is available, 0 otherwise.
1094 proc check_effective_target_scheduling {} {
1095 return [check_no_compiler_messages scheduling object {
1097 } "-fschedule-insns"]
1100 # Return 1 if trapping arithmetic is available, 0 otherwise.
1102 proc check_effective_target_trapping {} {
1103 return [check_no_compiler_messages trapping object {
1104 int add (int a, int b) { return a + b; }
1108 # Return 1 if compilation with -fgraphite is error-free for trivial
1109 # code, 0 otherwise.
1111 proc check_effective_target_fgraphite {} {
1112 return [check_no_compiler_messages fgraphite object {
1117 # Return 1 if compiled with --enable-offload-targets=
1118 # This affects host compilation as ENABLE_OFFLOAD then evaluates to true.
1119 proc check_effective_target_offloading_enabled {} {
1120 return [check_configured_with "--enable-offload-targets"]
1123 # Return 1 if compilation with -fopenacc is error-free for trivial
1124 # code, 0 otherwise.
1126 proc check_effective_target_fopenacc {} {
1127 # nvptx/amdgcn can be built with the device-side bits of openacc, but it
1128 # does not make sense to test it as an openacc host.
1129 if [istarget nvptx-*-*] { return 0 }
1130 if [istarget amdgcn-*-*] { return 0 }
1132 return [check_no_compiler_messages fopenacc object {
1137 # Return 1 if compilation with -fopenmp is error-free for trivial
1138 # code, 0 otherwise.
1140 proc check_effective_target_fopenmp {} {
1141 # nvptx/amdgcn can be built with the device-side bits of libgomp, but it
1142 # does not make sense to test it as an openmp host.
1143 if [istarget nvptx-*-*] { return 0 }
1144 if [istarget amdgcn-*-*] { return 0 }
1146 return [check_no_compiler_messages fopenmp object {
1151 # Return 1 if compilation with -fgnu-tm is error-free for trivial
1152 # code, 0 otherwise.
1154 proc check_effective_target_fgnu_tm {} {
1155 return [check_no_compiler_messages fgnu_tm object {
1160 # Return 1 if the target supports mmap, 0 otherwise.
1162 proc check_effective_target_mmap {} {
1163 return [check_function_available "mmap"]
1166 # Return 1 if the target supports sysconf, 0 otherwise.
1168 proc check_effective_target_sysconf {} {
1169 # VxWorks has sysconf in rtp mode only, but our way to test can't
1170 # tell kernel
mode doesn
't, as we're doing partial links
for
1171 # kernel modules. We can tell by checking
for a declaration
, or
1172 #
for some sysconf parm
, because configurations that don
't offer
1173 # sysconf don't have either.
1174 if { [istarget
*-*-vxworks
*] } {
1175 return [check_no_compiler_messages sysconfdecl assembly
{
1177 int f
() { return sysconf
(_SC_PAGESIZE
); }
1180 return [check_function_available
"sysconf"]
1183 #
Return 1 if the target supports dlopen
, 0 otherwise.
1184 proc check_effective_target_dlopen
{} {
1185 return [check_no_compiler_messages dlopen executable
{
1187 int main
(void
) { dlopen
("dummy.so", RTLD_NOW); }
1188 } [add_options_for_dlopen
""]]
1191 proc add_options_for_dlopen
{ flags
} {
1192 return "$flags -ldl"
1195 #
Return 1 if the target supports clone
, 0 otherwise.
1196 proc check_effective_target_clone
{} {
1197 return [check_function_available
"clone"]
1200 #
Return 1 if the target supports posix_memalign
, 0 otherwise.
1201 proc check_effective_target_posix_memalign
{} {
1202 if { [istarget
*-*-vxworks
*] } {
1203 # VxWorks doesn
't have posix_memalign but our way to test
1204 # can't tell as we
're doing partial links for kernel modules.
1207 return [check_function_available "posix_memalign"]
1210 # Return 1 if the target supports setrlimit, 0 otherwise.
1211 proc check_effective_target_setrlimit {} {
1212 # Darwin has non-posix compliant RLIMIT_AS
1213 if { [istarget *-*-darwin*] } {
1216 return [check_function_available "setrlimit"]
1219 # Return 1 if the target supports gettimeofday, 0 otherwise.
1220 proc check_effective_target_gettimeofday {} {
1221 return [check_function_available "gettimeofday"]
1224 # Return 1 if the target supports swapcontext, 0 otherwise.
1225 proc check_effective_target_swapcontext {} {
1226 return [check_no_compiler_messages swapcontext executable {
1227 #include <ucontext.h>
1230 ucontext_t orig_context,child_context;
1231 if (swapcontext(&child_context, &orig_context) < 0) { }
1236 # Return 1 if the target supports POSIX threads, 0 otherwise.
1237 proc check_effective_target_pthread {} {
1238 return [check_no_compiler_messages pthread object {
1239 #include <pthread.h>
1244 # Return 1 if the target supports both Unix and internet sockets, 0 otherwise.
1245 proc check_effective_target_sockets {} {
1246 return [check_no_compiler_messages socket executable {
1247 #include <sys/socket.h>
1249 #include <netinet/in.h>
1251 socket(AF_UNIX, SOCK_STREAM, 0);
1252 socket(AF_INET, SOCK_DGRAM, 0);
1258 # Return 1 if compilation with -mpe-aligned-commons is error-free
1259 # for trivial code, 0 otherwise.
1261 proc check_effective_target_pe_aligned_commons {} {
1262 if { [istarget *-*-cygwin*] || [istarget *-*-mingw*] } {
1263 return [check_no_compiler_messages pe_aligned_commons object {
1265 } "-mpe-aligned-commons"]
1270 # Return 1 if the target supports -static
1271 proc check_effective_target_static {} {
1272 if { [istarget arm*-*-uclinuxfdpiceabi] } {
1275 return [check_no_compiler_messages static executable {
1276 int main (void) { return 0; }
1280 # Return 1 if the target supports -fstack-protector
1281 proc check_effective_target_fstack_protector {} {
1282 if { [istarget hppa*-*-*] } {
1285 return [check_runtime fstack_protector {
1287 int main (int argc, char *argv[]) {
1289 return !strcpy (buf, strrchr (argv[0], '/'));
1291 } "-fstack-protector"]
1294 # Return 1 if the target supports -fstack-check or -fstack-check=$stack_kind
1295 proc check_stack_check_available { stack_kind } {
1296 if [string match "" $stack_kind] then {
1297 set stack_opt "-fstack-check"
1298 } else { set stack_opt "-fstack-check=$stack_kind" }
1300 return [check_no_compiler_messages stack_check_$stack_kind executable {
1301 int main (void) { return 0; }
1305 # Return 1 if the target supports stack scrubbing.
1306 proc check_effective_target_strub {} {
1307 return [check_no_compiler_messages strub assembly {
1308 void __attribute__ ((__strub__)) fn (void) {}
1312 # Return 1 if compilation with -freorder-blocks-and-partition is error-free
1313 # for trivial code, 0 otherwise. As some targets (ARM for example) only
1314 # warn when -fprofile-use is also supplied we test that combination too.
1316 proc check_effective_target_freorder {} {
1317 if { [check_no_compiler_messages freorder object {
1319 } "-freorder-blocks-and-partition"]
1320 && [check_no_compiler_messages fprofile_use_freorder object {
1322 } "-fprofile-use -freorder-blocks-and-partition -Wno-missing-profile"] } {
1328 # Return 1 if -fpic and -fPIC are supported, as in no warnings or errors
1329 # emitted, 0 otherwise. Whether a shared library can actually be built is
1330 # out of scope for this test.
1332 proc check_effective_target_fpic { } {
1333 # Note that M68K has a multilib that supports -fpic but not
1334 # -fPIC, so we need to check both. We test with a program that
1335 # requires GOT references.
1336 foreach arg {fpic fPIC} {
1337 if [check_no_compiler_messages $arg object {
1338 extern int foo (void); extern int bar;
1339 int baz (void) { return foo () + bar; }
1347 # On AArch64, if -fpic is not supported, then we will fall back to -fPIC
1348 # silently. So, we can't rely
on above
"check_effective_target_fpic" as it
1349 # assumes compiler will give warning
if -fpic not supported. Here we check
1350 # whether binutils supports those new
-fpic relocation modifiers
, and assume
1351 #
-fpic is supported
if there is binutils support. GCC configuration will
1352 # enable
-fpic
for AArch64 in this case.
1354 #
"check_effective_target_aarch64_small_fpic" is dedicated for checking small
1355 # memory
model -fpic relocation types.
1357 proc check_effective_target_aarch64_small_fpic
{ } {
1358 if { [istarget aarch64
*-*-*] } {
1359 return [check_no_compiler_messages aarch64_small_fpic object
{
1360 void foo
(void
) { asm
("ldr x0, [x2, #:gotpage_lo15:globalsym]"); }
1367 #
On AArch64
, instruction sequence
for TLS LE under
-mtls
-size
=32 will utilize
1368 # the relocation modifier
"tprel_g0_nc" together with MOVK, it's only supported
1369 # in binutils since
2015-03-04 as PR gas
/17843.
1371 # This test directive make sure binutils support all features needed by TLS LE
1372 # under
-mtls
-size
=32 on AArch64.
1374 proc check_effective_target_aarch64_tlsle32
{ } {
1375 if { [istarget aarch64
*-*-*] } {
1376 return [check_no_compiler_messages aarch64_tlsle32 object
{
1377 void foo
(void
) { asm
("movk x1,#:tprel_g0_nc:t1"); }
1384 #
Return 1 if -shared is supported
, as in no warnings or errors
1385 # emitted
, 0 otherwise.
1387 proc check_effective_target_shared
{ } {
1388 # Darwin
's linker defaults to error on undefined (which makes it look as
1389 #Â if we do not support shared) but we can tell it to allow the symbols used
1390 # here to be undefined.
1392 if { [istarget *-*-darwin\[912\]*] } {
1393 set extra_flags "-Wl,-U,_foo,-U,_bar,-U,__Z3foov"
1395 # Note that M68K has a multilib that supports -fpic but not
1396 # -fPIC, so we need to check both. We test with a program that
1397 # requires GOT references, and with a libc symbol that would
1398 # bring in significant parts of a static-only libc. Absent a
1399 # shared libc, this would make -shared tests fail, so we don't
1400 # want to enable the shared effective target
then.
1401 return [check_no_compiler_messages shared executable
{
1403 extern
int foo
(void
); extern
int bar
;
1405 return foo
() + (char
*) malloc
(bar
);
1407 } "-shared -fpic $extra_flags"]
1410 #
Return 1 if -pie
, -fpie and
-fPIE are supported
, 0 otherwise.
1412 proc check_effective_target_pie
{ } {
1413 if { [istarget
*-*-darwin\
[912\
]*]
1414 ||
[istarget
*-*-dragonfly
*]
1415 ||
[istarget
*-*-freebsd
*]
1416 ||
[istarget
*-*-linux
*]
1417 ||
[istarget arm
*-*-uclinuxfdpiceabi
]
1418 ||
[istarget
*-*-solaris2
*]
1419 ||
[istarget
*-*-gnu
*]
1420 ||
[istarget
*-*-amdhsa
]} {
1426 #
Return true
if the target supports
-mpaired
-single
(as used
on MIPS
).
1428 proc check_effective_target_mpaired_single
{ args } {
1429 return [check_no_compiler_messages mpaired_single object
{
1434 #
Return true
if the target has access to FPU instructions.
1436 proc check_effective_target_hard_float
{ } {
1437 # This should work
on cores that only have single
-precision
,
1438 # and should also correctly handle legacy cores that had thumb1 and
1439 # lacked FP support
for that
, but had it in Arm state.
1440 if { [istarget arm
*-*-*] } {
1441 return [check_no_compiler_messages hard_float assembly
{
1443 #error __arm_soft_float
1448 if { [istarget loongarch
*-*-*] } {
1449 return [check_no_compiler_messages hard_float assembly
{
1450 #
if (defined __loongarch_soft_float
)
1451 #error __loongarch_soft_float
1456 if { [istarget mips
*-*-*] } {
1457 return [check_no_compiler_messages hard_float assembly
{
1458 #
if (defined __mips_soft_float || defined __mips16
)
1459 #error __mips_soft_float || __mips16
1464 # This proc is actually checking the availabilty of FPU
1465 # support
for doubles
, so
on the RX we must fail
if the
1466 #
64-bit double multilib has been selected.
1467 if { [istarget rx
-*-*] } {
1469 #
return [check_no_compiler_messages hard_float assembly
{
1470 #
if defined __RX_64_BIT_DOUBLES__
1471 #error __RX_64_BIT_DOUBLES__
1476 # The generic test doesn
't work for C-SKY because some cores have
1477 # hard float for single precision only.
1478 if { [istarget csky*-*-*] } {
1479 return [check_no_compiler_messages hard_float assembly {
1480 #if defined __csky_soft_float__
1481 #error __csky_soft_float__
1486 # The generic test equates hard_float with "no call for adding doubles".
1487 return [check_no_messages_and_pattern hard_float "!\\(call" rtl-expand {
1488 double a (double b, double c) { return b + c; }
1492 # Return true if the target is a 64-bit MIPS target.
1494 proc check_effective_target_mips64 { } {
1495 return [check_no_compiler_messages mips64 assembly {
1502 # Return true if the target is a MIPS target that does not produce
1505 proc check_effective_target_nomips16 { } {
1506 return [check_no_compiler_messages nomips16 object {
1510 /* A cheap way of testing for -mflip-mips16. */
1511 void foo (void) { asm ("addiu $20,$20,1"); }
1512 void bar (void) { asm ("addiu $20,$20,1"); }
1517 # Add the options needed for MIPS16 function attributes. At the moment,
1518 # we don't support MIPS16 PIC.
1520 proc add_options_for_mips16_attribute
{ flags
} {
1521 return "$flags -mno-abicalls -fno-pic -DMIPS16=__attribute__((mips16))"
1524 #
Return true
if we can force a
mode that allows MIPS16 code generation.
1525 # We don
't support MIPS16 PIC, and only support MIPS16 -mhard-float
1528 proc check_effective_target_mips16_attribute { } {
1529 return [check_no_compiler_messages mips16_attribute assembly {
1533 #if defined __mips_hard_float \
1534 && (!defined _ABIO32 || _MIPS_SIM != _ABIO32) \
1535 && (!defined _ABIO64 || _MIPS_SIM != _ABIO64)
1536 #error __mips_hard_float && (!_ABIO32 || !_ABIO64)
1538 } [add_options_for_mips16_attribute ""]]
1541 # Return 1 if the target supports long double larger than double when
1542 # using the new ABI, 0 otherwise.
1544 proc check_effective_target_mips_newabi_large_long_double { } {
1545 return [check_no_compiler_messages mips_newabi_large_long_double object {
1546 int dummy[sizeof(long double) > sizeof(double) ? 1 : -1];
1550 # Return true if the target is a MIPS target that has access
1551 # to the LL and SC instructions.
1553 proc check_effective_target_mips_llsc { } {
1554 if { ![istarget mips*-*-*] } {
1557 # Assume that these instructions are always implemented for
1558 # non-elf* targets, via emulation if necessary.
1559 if { ![istarget *-*-elf*] } {
1562 # Otherwise assume LL/SC support for everything but MIPS I.
1563 return [check_no_compiler_messages mips_llsc assembly {
1570 # Return true if the target is a MIPS target that uses in-place relocations.
1572 proc check_effective_target_mips_rel { } {
1573 if { ![istarget mips*-*-*] } {
1576 return [check_no_compiler_messages mips_rel object {
1577 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1578 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1579 #error _ABIN32 && (_ABIN32 || _ABI64)
1584 # Return true if the target is a MIPS target that uses the EABI.
1586 proc check_effective_target_mips_eabi { } {
1587 if { ![istarget mips*-*-*] } {
1590 return [check_no_compiler_messages mips_eabi object {
1597 # Return 1 if the current multilib does not generate PIC by default.
1599 proc check_effective_target_nonpic { } {
1600 return [check_no_compiler_messages nonpic assembly {
1607 # Return 1 if the current multilib generates PIE by default.
1609 proc check_effective_target_pie_enabled { } {
1610 return [check_no_compiler_messages pie_enabled assembly {
1617 # Return 1 if the target generates -fstack-protector by default.
1619 proc check_effective_target_fstack_protector_enabled {} {
1620 return [ check_no_compiler_messages fstack_protector_enabled assembly {
1621 #if !defined(__SSP__) && !defined(__SSP_ALL__) && \
1622 !defined(__SSP_STRONG__) && !defined(__SSP_EXPICIT__)
1628 # Return 1 if the target does not use a status wrapper.
1630 proc check_effective_target_unwrapped { } {
1631 if { [target_info needs_status_wrapper] != "" \
1632 && [target_info needs_status_wrapper] != "0" } {
1638 # Return true if iconv is supported on the target. In particular IBM1047.
1640 proc check_iconv_available { test_what } {
1643 # If the tool configuration file has not set libiconv, try "-liconv"
1644 if { ![info exists libiconv] } {
1645 set libiconv "-liconv"
1647 set test_what [lindex $test_what 1]
1648 return [check_runtime_nocache $test_what [subst {
1654 cd = iconv_open ("$test_what", "UTF-8");
1655 if (cd == (iconv_t) -1)
1662 # Return true if the atomic library is supported on the target.
1663 proc check_effective_target_libatomic_available { } {
1664 return [check_no_compiler_messages libatomic_available executable {
1665 int main (void) { return 0; }
1669 # Return 1 if an ASCII locale is supported on this host, 0 otherwise.
1671 proc check_ascii_locale_available { } {
1675 # Return true if named sections are supported on this target.
1677 proc check_named_sections_available { } {
1678 return [check_no_compiler_messages named_sections assembly {
1679 int __attribute__ ((section("whatever"))) foo;
1683 # Return true if the "naked" function attribute is supported on this target.
1685 proc check_effective_target_naked_functions { } {
1686 return [check_no_compiler_messages naked_functions assembly {
1687 void f() __attribute__((naked));
1691 # Return 1 if the target supports Fortran real kinds larger than real(8),
1694 # When the target name changes, replace the cached result.
1696 proc check_effective_target_fortran_large_real { } {
1697 return [check_no_compiler_messages fortran_large_real executable {
1699 integer,parameter :: k = selected_real_kind (precision (0.0_8) + 1)
1706 # Return 1 if the target supports Fortran real kind real(16),
1707 # 0 otherwise. Contrary to check_effective_target_fortran_large_real
1708 # this checks for Real(16) only; the other returned real(10) if
1709 # both real(10) and real(16) are available.
1711 # When the target name changes, replace the cached result.
1713 proc check_effective_target_fortran_real_16 { } {
1714 return [check_no_compiler_messages fortran_real_16 executable {
1722 # Return 1 if the target supports Fortran real kind 10,
1723 # 0 otherwise. Contrary to check_effective_target_fortran_large_real
1724 # this checks for real(10) only.
1726 # When the target name changes, replace the cached result.
1728 proc check_effective_target_fortran_real_10 { } {
1729 return [check_no_compiler_messages fortran_real_10 executable {
1737 # Return 1 if the target supports Fortran real kind C_FLOAT128,
1738 # 0 otherwise. This differs from check_effective_target_fortran_real_16
1739 # because _Float128 has the additional requirement that it be the
1740 # 128-bit IEEE encoding; even if _Float128 is available in C, it may not
1741 # have a corresponding Fortran kind on targets (PowerPC) that use some
1742 # other encoding for long double/TFmode/real(16).
1743 proc check_effective_target_fortran_real_c_float128 { } {
1744 return [check_no_compiler_messages fortran_real_c_float128 executable {
1747 real(kind=c_float128) :: x
1753 # Return 1 if the target supports Fortran's IEEE modules
,
1756 # When the target
name changes
, replace the cached result.
1758 proc check_effective_target_fortran_ieee
{ flags
} {
1759 return [check_no_compiler_messages fortran_ieee executable
{
1761 use
, intrinsic
:: ieee_features
1767 #
Return 1 if the target supports
SQRT for the
largest floating
-point
1768 # type.
(Some targets lack the libm support
for this FP type.
)
1769 #
On most targets
, this check effectively checks either whether sqrtl is
1770 # available or
on __float128 systems whether libquadmath is installed
,
1771 # which provides sqrtq.
1773 # When the target
name changes
, replace the cached result.
1775 proc check_effective_target_fortran_largest_fp_has_sqrt
{ } {
1776 return [check_no_compiler_messages fortran_largest_fp_has_sqrt executable
{
1778 use iso_fortran_env
, only
: real_kinds
1779 integer,parameter
:: maxFP
= real_kinds
(ubound
(real_kinds
,dim
=1))
1780 real
(kind
=maxFP
), volatile
:: x
1788 #
Return 1 if the target supports Fortran
integer kinds larger than
1789 #
integer(8), 0 otherwise.
1791 # When the target
name changes
, replace the cached result.
1793 proc check_effective_target_fortran_large_int
{ } {
1794 return [check_no_compiler_messages fortran_large_int executable
{
1796 integer,parameter
:: k
= selected_int_kind
(range
(0_8
) + 1)
1797 integer(kind
=k
) :: i
1802 #
Return 1 if the target supports Fortran
integer(16), 0 otherwise.
1804 # When the target
name changes
, replace the cached result.
1806 proc check_effective_target_fortran_integer_16
{ } {
1807 return [check_no_compiler_messages fortran_integer_16 executable
{
1814 #
Return 1 if we can statically link libgfortran
, 0 otherwise.
1816 # When the target
name changes
, replace the cached result.
1818 proc check_effective_target_static_libgfortran
{ } {
1819 return [check_no_compiler_messages static_libgfortran executable
{
1826 #
Return 1 if we can use the
-rdynamic option
, 0 otherwise.
1828 proc check_effective_target_rdynamic
{ } {
1829 return [check_no_compiler_messages rdynamic executable
{
1830 int main
() { return 0; }
1834 proc check_linker_plugin_available
{ } {
1835 return [check_no_compiler_messages_nocache linker_plugin executable
{
1836 int main
() { return 0; }
1837 } "-flto -fuse-linker-plugin"]
1840 #
Return 1 if the target is RV32
, 0 otherwise.
Cache the result.
1842 proc check_effective_target_rv32
{ } {
1843 # Check that we are compiling
for RV32 by checking the xlen size.
1844 return [check_no_compiler_messages riscv_rv32 assembly
{
1845 #
if !defined
(__riscv_xlen
)
1846 #error
"__riscv_xlen not defined!"
1848 #
if __riscv_xlen
!= 32
1855 #
Return 1 if the target is RV64
, 0 otherwise.
Cache the result.
1857 proc check_effective_target_rv64
{ } {
1858 # Check that we are compiling
for RV64 by checking the xlen size.
1859 return [check_no_compiler_messages riscv_rv64 assembly
{
1860 #
if !defined
(__riscv_xlen
)
1861 #error
"__riscv_xlen not defined!"
1863 #
if __riscv_xlen
!= 64
1870 #
Return 1 if the target abi is __riscv_float_abi_soft
, 0 otherwise.
1873 proc check_effective_target_rv_float_abi_soft
{ } {
1874 # Check that we are compiling
for RV64 by checking the xlen size.
1875 return [check_no_compiler_messages riscv_riscv_float_abi_soft assembly
{
1876 #ifndef __riscv_float_abi_soft
1877 #error
"Not __riscv_float_abi_soft"
1882 #
Return 1 if the target arch supports the atomic extension
, 0 otherwise.
1885 proc check_effective_target_riscv_a
{ } {
1886 return [check_no_compiler_messages riscv_ext_a assembly
{
1888 #error
"Not __riscv_a"
1893 #
Return 1 if the target arch supports the double precision floating point
1894 # extension
, 0 otherwise.
Cache the result.
1896 proc check_effective_target_riscv_d
{ } {
1897 return [check_no_compiler_messages riscv_ext_d assembly
{
1899 #error
"Not __riscv_d"
1904 #
Return 1 if the target arch supports the vector extension
, 0 otherwise.
1907 proc check_effective_target_riscv_v
{ } {
1908 return [check_no_compiler_messages riscv_ext_v assembly
{
1910 #error
"Not __riscv_v"
1915 #
Return 1 if the target arch supports the Zvfh extension
, 0 otherwise.
1918 proc check_effective_target_riscv_zvfh
{ } {
1919 return [check_no_compiler_messages riscv_ext_zvfh assembly
{
1920 #ifndef __riscv_zvfh
1921 #error
"Not __riscv_zvfh"
1926 #
Return 1 if the target arch supports half float
, 0 otherwise.
1927 # Note
, this differs from the test performed by
1928 #
/* dg
-skip
-if "" { *-*-* } { "*" } { "-march=rv*zfh*" } */
1929 # in that it takes default behaviour into account.
1932 proc check_effective_target_riscv_zfh
{ } {
1933 return [check_no_compiler_messages riscv_ext_zfh assembly
{
1935 #error
"Not __riscv_zfh"
1940 #
Return 1 if the target arch supports the TSO memory ordering extension
,
1941 #
0 otherwise.
Cache the result.
1943 proc check_effective_target_riscv_ztso
{ } {
1944 return [check_no_compiler_messages riscv_ext_ztso assembly
{
1945 #ifndef __riscv_ztso
1946 #error
"Not __riscv_ztso"
1951 #
Return 1 if the target arch supports the Zbb extension
, 0 otherwise.
1954 proc check_effective_target_riscv_zbb
{ } {
1955 return [check_no_compiler_messages riscv_ext_zbb assembly
{
1957 #error
"Not __riscv_zbb"
1962 #
Return 1 if the target arch supports the XTheadVector extension
, 0 otherwise.
1965 proc check_effective_target_riscv_xtheadvector
{ } {
1966 return [check_no_compiler_messages riscv_ext_xtheadvector assembly
{
1967 #ifndef __riscv_xtheadvector
1968 #error
"Not __riscv_xtheadvector"
1974 #
Return 1 if we can
execute code when using dg
-add
-options riscv_v
1976 proc check_effective_target_riscv_v_ok
{ } {
1977 #
If the target already supports v without
any added options
,
1978 # we may assume we can
execute just fine.
1979 if { [check_effective_target_riscv_v
] } {
1983 # check
if we can
execute vector insns with the given hardware or
1985 set gcc_march
[regsub
{[[:alnum
:]]*} [riscv_get_arch
] &v
]
1986 if { [check_runtime $
{gcc_march
}_exec
{
1987 int main
() { asm
("vsetivli t0, 9, e8, m1, tu, ma"); return 0; } } "-march=${gcc_march}"] } {
1991 # Possible future extensions
: If the target is a simulator
, dg
-add
-options
1992 # might change its config to make it allow vector insns
, or we might use
1993 # options to
set special elf flags
/ sections to effect that.
1998 #
Return 1 if we can
execute code when using dg
-add
-options riscv_zfh
2000 proc check_effective_target_riscv_zfh_ok
{ } {
2001 #
If the target already supports zfh without
any added options
,
2002 # we may assume we can
execute just fine.
2003 # ??? Other cases we should
consider:
2004 #
- target
/ simulator already supports zfh extension
- test
for that.
2005 #
- target is a simulator
, and dg
-add
-options knows how to enable zfh support in that simulator
2006 if { [check_effective_target_riscv_zfh
] } {
2010 # check
if we can
execute zfh insns with the given hardware or
2012 set gcc_march
[riscv_get_arch
]
2013 if { [check_runtime $
{gcc_march
}_zfh_exec
{
2014 int main
() { asm
("feq.h a3,fa5,fa4"); return 0; } } "-march=${gcc_march}_zfh"] } {
2018 # Possible future extensions
: If the target is a simulator
, dg
-add
-options
2019 # might change its config to make it allow half float insns
, or we might
2020 # use options to
set special elf flags
/ sections to effect that.
2025 #
Return 1 if we can
execute code when using dg
-add
-options riscv_zvfh
2027 proc check_effective_target_riscv_zvfh_ok
{ } {
2028 #
If the target already supports v without
any added options
,
2029 # we may assume we can
execute just fine.
2030 if { [check_effective_target_riscv_zvfh
] } {
2034 # check
if we can
execute vector insns with the given hardware or
2036 set gcc_march
[regsub
{[[:alnum
:]]*} [riscv_get_arch
] &v
]
2037 if { [check_runtime $
{gcc_march
}_exec
{
2040 asm
("vsetivli zero,8,e16,m1,ta,ma");
2041 asm
("vfadd.vv v8,v8,v16" : : : "v8");
2043 } } "-march=${gcc_march}"] } {
2050 proc riscv_get_arch
{ } {
2052 # ???
do we neeed to add more extensions to the list below?
2053 foreach ext
{ i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvfh ztso
} {
2054 if { [check_no_compiler_messages riscv_ext_$ext assembly
[string map
[list DEF __riscv_$ext
] {
2059 if { [string length $ext
] > 1 } {
2062 set gcc_march $gcc_march$ext
2064 if { [string equal $gcc_march
"imafd"] } {
2068 if { [check_effective_target_rv32
] } {
2069 set gcc_march rv32$gcc_march
2070 } elseif
{ [check_effective_target_rv64
] } {
2071 set gcc_march rv64$gcc_march
2078 proc add_options_for_riscv_a
{ flags
} {
2079 if { [lsearch $flags
-march
=*] >= 0 } {
2080 #
If there are multiple
-march flags
, we have to adjust all of them.
2081 set expanded_flags
[regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*)g
+} $flags
\\1imafd
]
2082 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*[b
-eg
-rt
-wy
]*)a
*} $expanded_flags
\\1a
]
2084 if { [check_effective_target_riscv_a
] } {
2087 return "$flags -march=[regsub {(rv[[:digit:]]*[b-eg-rt-wy]*)a*} [riscv_get_arch] &a]"
2090 proc add_options_for_riscv_d
{ flags
} {
2091 if { [lsearch $flags
-march
=*] >= 0 } {
2092 #
If there are multiple
-march flags
, we have to adjust all of them.
2093 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*[a
-ce
-rt
-wy
]*)d
*} $flags
\\1d
]
2095 if { [check_effective_target_riscv_d
] } {
2098 return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &d]"
2101 proc add_options_for_riscv_v
{ flags
} {
2102 if { [lsearch $flags
-march
=*] >= 0 } {
2103 #
If there are multiple
-march flags
, we have to adjust all of them.
2104 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*[a
-rt
-uwy
]*)v
*} $flags
\\1v
]
2106 if { [check_effective_target_riscv_v
] } {
2109 return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]"
2112 proc add_options_for_riscv_zfh
{ flags
} {
2113 if { [lsearch $flags
-march
=*] >= 0 } {
2114 #
If there are multiple
-march flags
, we have to adjust all of them.
2115 set flags
[regsub
-all
-- {(?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*} $flags
&_zfh
]
2116 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*_zfh
[[:alnum
:]_.
]*)_zfh
} $flags
\\1 ]
2118 if { [check_effective_target_riscv_zfh
] } {
2121 return "$flags -march=[riscv_get_arch]_zfh"
2124 proc add_options_for_riscv_ztso
{ flags
} {
2125 if { [lsearch $flags
-march
=*] >= 0 } {
2126 #
If there are multiple
-march flags
, we have to adjust all of them.
2127 set flags
[regsub
-all
-- {(?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*} $flags
&_ztso
]
2128 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*_ztso
[[:alnum
:]_.
]*)_ztso
} $flags
\\1 ]
2130 if { [check_effective_target_riscv_ztso
] } {
2133 return "$flags -march=[riscv_get_arch]_ztso"
2136 proc add_options_for_riscv_zvfh
{ flags
} {
2137 if { [lsearch $flags
-march
=*] >= 0 } {
2138 #
If there are multiple
-march flags
, we have to adjust all of them.
2139 set flags
[regsub
-all
-- {(?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*} $flags
&_zvfh
]
2140 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*_zvfh
[[:alnum
:]_.
]*)_zvfh
} $flags
\\1 ]
2142 if { [check_effective_target_riscv_zvfh
] } {
2145 return "$flags -march=[riscv_get_arch]_zvfh"
2148 #
Return 1 if the target OS supports running SSE executables
, 0
2149 # otherwise.
Cache the result.
2151 proc check_sse_os_support_available
{ } {
2152 return [check_cached_effective_target sse_os_support_available
{
2153 #
If this is not the right target
then we can skip the test.
2154 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2162 #
Return 1 if the target OS supports running AVX executables
, 0
2163 # otherwise.
Cache the result.
2165 proc check_avx_os_support_available
{ } {
2166 return [check_cached_effective_target avx_os_support_available
{
2167 #
If this is not the right target
then we can skip the test.
2168 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2171 # Check that OS has AVX and SSE saving enabled.
2172 check_runtime_nocache avx_os_support_available
{
2175 unsigned
int eax
, edx
;
2177 asm
("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
2178 return (eax
& 0x06) != 0x06;
2185 #
Return 1 if the target OS supports running AVX executables
, 0
2186 # otherwise.
Cache the result.
2188 proc check_avx512_os_support_available
{ } {
2189 return [check_cached_effective_target avx512_os_support_available
{
2190 #
If this is not the right target
then we can skip the test.
2191 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2194 # Check that OS has AVX512
, AVX and SSE saving enabled.
2195 check_runtime_nocache avx512_os_support_available
{
2198 unsigned
int eax
, edx
;
2200 asm
("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
2201 return (eax
& 0xe6) != 0xe6;
2208 #
Return 1 if the target supports executing SSE instructions
, 0
2209 # otherwise.
Cache the result.
2211 proc check_sse_hw_available
{ } {
2212 return [check_cached_effective_target sse_hw_available
{
2213 #
If this is not the right target
then we can skip the test.
2214 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2217 check_runtime_nocache sse_hw_available
{
2221 unsigned
int eax
, ebx
, ecx
, edx
;
2222 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2225 return !(edx
& bit_SSE
);
2232 #
Return 1 if the target supports executing SSE2 instructions
, 0
2233 # otherwise.
Cache the result.
2235 proc check_sse2_hw_available
{ } {
2236 return [check_cached_effective_target sse2_hw_available
{
2237 #
If this is not the right target
then we can skip the test.
2238 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2241 check_runtime_nocache sse2_hw_available
{
2245 unsigned
int eax
, ebx
, ecx
, edx
;
2246 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2249 return !(edx
& bit_SSE2
);
2256 #
Return 1 if the target supports executing SSE4 instructions
, 0
2257 # otherwise.
Cache the result.
2259 proc check_sse4_hw_available
{ } {
2260 return [check_cached_effective_target sse4_hw_available
{
2261 #
If this is not the right target
then we can skip the test.
2262 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2265 check_runtime_nocache sse4_hw_available
{
2269 unsigned
int eax
, ebx
, ecx
, edx
;
2270 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2273 return !(ecx
& bit_SSE4_2
);
2280 #
Return 1 if the target supports executing AVX instructions
, 0
2281 # otherwise.
Cache the result.
2283 proc check_avx_hw_available
{ } {
2284 return [check_cached_effective_target avx_hw_available
{
2285 #
If this is not the right target
then we can skip the test.
2286 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2289 check_runtime_nocache avx_hw_available
{
2293 unsigned
int eax
, ebx
, ecx
, edx
;
2294 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2297 return ((ecx
& (bit_AVX | bit_OSXSAVE
))
2298 != (bit_AVX | bit_OSXSAVE
));
2305 #
Return 1 if the target supports executing AVX2 instructions
, 0
2306 # otherwise.
Cache the result.
2308 proc check_avx2_hw_available
{ } {
2309 return [check_cached_effective_target avx2_hw_available
{
2310 #
If this is not the right target
then we can skip the test.
2311 if { !([istarget x86_64
-*-*] ||
[istarget i?
86-*-*]) } {
2314 check_runtime_nocache avx2_hw_available
{
2319 unsigned
int eax
, ebx
, ecx
, edx
;
2321 if (__get_cpuid_max
(0, NULL
) < 7)
2324 __cpuid
(1, eax
, ebx
, ecx
, edx
);
2326 if (!(ecx
& bit_OSXSAVE
))
2329 __cpuid_count
(7, 0, eax
, ebx
, ecx
, edx
);
2331 return !(ebx
& bit_AVX2
);
2338 #
Return 1 if the target supports executing AVX512 foundation instructions
, 0
2339 # otherwise.
Cache the result.
2341 proc check_avx512f_hw_available
{ } {
2342 return [check_cached_effective_target avx512f_hw_available
{
2343 #
If this is not the right target
then we can skip the test.
2344 if { !([istarget x86_64
-*-*] ||
[istarget i?
86-*-*]) } {
2347 check_runtime_nocache avx512f_hw_available
{
2352 unsigned
int eax
, ebx
, ecx
, edx
;
2354 if (__get_cpuid_max
(0, NULL
) < 7)
2357 __cpuid
(1, eax
, ebx
, ecx
, edx
);
2359 if (!(ecx
& bit_OSXSAVE
))
2362 __cpuid_count
(7, 0, eax
, ebx
, ecx
, edx
);
2364 return !(ebx
& bit_AVX512F
);
2371 #
Return 1 if the target supports running SSE executables
, 0 otherwise.
2373 proc check_effective_target_sse_runtime
{ } {
2374 if { [check_effective_target_sse
]
2375 && [check_sse_hw_available
]
2376 && [check_sse_os_support_available
] } {
2382 #
Return 1 if the target supports running SSE2 executables
, 0 otherwise.
2384 proc check_effective_target_sse2_runtime
{ } {
2385 if { [check_effective_target_sse2
]
2386 && [check_sse2_hw_available
]
2387 && [check_sse_os_support_available
] } {
2393 #
Return 1 if the target supports running SSE4 executables
, 0 otherwise.
2395 proc check_effective_target_sse4_runtime
{ } {
2396 if { [check_effective_target_sse4
]
2397 && [check_sse4_hw_available
]
2398 && [check_sse_os_support_available
] } {
2404 #
Return 1 if the target supports running AVX executables
, 0 otherwise.
2406 proc check_effective_target_avx_runtime
{ } {
2407 if { [check_effective_target_avx
]
2408 && [check_avx_hw_available
]
2409 && [check_avx_os_support_available
] } {
2415 #
Return 1 if the target supports running AVX2 executables
, 0 otherwise.
2417 proc check_effective_target_avx2_runtime
{ } {
2418 if { [check_effective_target_avx2
]
2419 && [check_avx2_hw_available
]
2420 && [check_avx_os_support_available
] } {
2426 #
Return 1 if the target supports running AVX512f executables
, 0 otherwise.
2428 proc check_effective_target_avx512f_runtime
{ } {
2429 if { [check_effective_target_avx512f
]
2430 && [check_avx512f_hw_available
]
2431 && [check_avx512_os_support_available
] } {
2437 #
Return 1 if bmi2 instructions can be compiled.
2438 proc check_effective_target_bmi2
{ } {
2439 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2442 return [check_no_compiler_messages bmi2 object
{
2444 _bzhi_u32
(unsigned
int __X
, unsigned
int __Y
)
2446 return __builtin_ia32_bzhi_si
(__X
, __Y
);
2451 #
Return 1 if the target supports executing MIPS Paired
-Single instructions
,
2452 #
0 otherwise.
Cache the result.
2454 proc check_mpaired_single_hw_available
{ } {
2455 return [check_cached_effective_target mpaired_single_hw_available
{
2456 #
If this is not the right target
then we can skip the test.
2457 if { !([istarget mips
*-*-*]) } {
2460 check_runtime_nocache mpaired_single_hw_available
{
2463 asm volatile
("pll.ps $f2,$f4,$f6");
2471 #
Return 1 if the target supports executing Loongson vector instructions
,
2472 #
0 otherwise.
Cache the result.
2474 proc check_mips_loongson_mmi_hw_available
{ } {
2475 return [check_cached_effective_target mips_loongson_mmi_hw_available
{
2476 #
If this is not the right target
then we can skip the test.
2477 if { !([istarget mips
*-*-*]) } {
2480 check_runtime_nocache mips_loongson_mmi_hw_available
{
2481 #
include <loongson
-mmiintrin.h
>
2484 asm volatile
("paddw $f2,$f4,$f6");
2492 #
Return 1 if the target supports executing MIPS MSA instructions
, 0
2493 # otherwise.
Cache the result.
2495 proc check_mips_msa_hw_available
{ } {
2496 return [check_cached_effective_target mips_msa_hw_available
{
2497 #
If this is not the right target
then we can skip the test.
2498 if { !([istarget mips
*-*-*]) } {
2501 check_runtime_nocache mips_msa_hw_available
{
2502 #
if !defined
(__mips_msa
)
2503 #error
"MSA NOT AVAIL"
2505 #
if !(((__mips
== 64) ||
(__mips
== 32)) && (__mips_isa_rev
>= 2))
2506 #error
"MSA NOT AVAIL FOR ISA REV < 2"
2508 #
if !defined
(__mips_hard_float
)
2509 #error
"MSA HARD_FLOAT REQUIRED"
2511 #
if __mips_fpr
!= 64
2512 #error
"MSA 64-bit FPR REQUIRED"
2518 v8i16 v
= __builtin_msa_ldi_h
(0);
2528 #
Return 1 if the target supports running MIPS Paired
-Single
2529 # executables
, 0 otherwise.
2531 proc check_effective_target_mpaired_single_runtime
{ } {
2532 if { [check_effective_target_mpaired_single
"-mpaired-single"]
2533 && [check_mpaired_single_hw_available
] } {
2539 #
Return 1 if the target supports running Loongson executables
, 0 otherwise.
2541 proc check_effective_target_mips_loongson_mmi_runtime
{ } {
2542 if { [check_effective_target_mips_loongson_mmi
"-mloongson-mmi"]
2543 && [check_mips_loongson_mmi_hw_available
] } {
2549 #
Return 1 if the target supports running MIPS MSA executables
, 0 otherwise.
2551 proc check_effective_target_mips_msa_runtime
{ } {
2552 if { [check_effective_target_mips_msa
"-mmsa"]
2553 && [check_mips_msa_hw_available
] } {
2559 #
Return 1 if we are compiling
for 64-bit PowerPC but we
do not use direct
2560 #
move instructions
for moves from GPR to FPR.
2562 proc check_effective_target_powerpc64_no_dm
{ } {
2563 # The
"mulld" checks if we are generating PowerPC64 code. The "lfd"
2564 # checks
if we
do not use direct moves
, but use the old
-fashioned
2565 # slower
move-via
-the
-stack.
2566 return [check_no_messages_and_pattern powerpc64_no_dm \
2567 {\mmulld\M.
*\mlfd
} assembly
{
2568 double f
(long long x
) { return x
*x
; }
2572 #
Return 1 if the target supports the __builtin_cpu_supports built
-in
,
2573 # including having a new enough library to support the test.
Cache the result.
2574 # Require at least a power7 to run
on.
2576 proc check_ppc_cpu_supports_hw_available
{ } {
2577 return [check_cached_effective_target ppc_cpu_supports_hw_available
{
2578 # Some simulators are known to not support VSX
/power8 instructions.
2579 #
For now
, disable
on Darwin
2580 if { [istarget powerpc
-*-eabi
]
2581 ||
[istarget powerpc
*-*-eabispe
]
2582 ||
[istarget
*-*-darwin
*]} {
2586 check_runtime_nocache ppc_cpu_supports_hw_available
{
2590 asm volatile
("xxlor vs0,vs0,vs0");
2592 asm volatile
("xxlor 0,0,0");
2594 if (!__builtin_cpu_supports
("vsx"))
2603 #
Return 1 if the target supports executing
750CL paired
-single instructions
, 0
2604 # otherwise.
Cache the result.
2606 proc check_750cl_hw_available
{ } {
2607 return [check_cached_effective_target
750cl_hw_available
{
2608 #
If this is not the right target
then we can skip the test.
2609 if { ![istarget powerpc
-*paired
*] } {
2612 check_runtime_nocache
750cl_hw_available
{
2616 asm volatile
("ps_mul v0,v0,v0");
2618 asm volatile
("ps_mul 0,0,0");
2627 #
Return 1 if the target supports executing power8 vector instructions
, 0
2628 # otherwise.
Cache the result.
2630 proc check_p8vector_hw_available
{ } {
2631 return [check_cached_effective_target p8vector_hw_available
{
2632 # Some simulators are known to not support VSX
/power8 instructions.
2633 #
For now
, disable
on Darwin
2634 if { [istarget powerpc
-*-eabi
]
2635 ||
[istarget powerpc
*-*-eabispe
]
2636 ||
[istarget
*-*-darwin
*]} {
2639 set options
"-mcpu=power8"
2640 check_runtime_nocache p8vector_hw_available
{
2644 asm volatile
("xxlorc vs0,vs0,vs0");
2646 asm volatile
("xxlorc 0,0,0");
2655 #
Return 1 if the target supports executing power9 vector instructions
, 0
2656 # otherwise.
Cache the result.
2658 proc check_p9vector_hw_available
{ } {
2659 return [check_cached_effective_target p9vector_hw_available
{
2660 # Some simulators are known to not support VSX
/power8
/power9
2661 # instructions.
For now
, disable
on Darwin.
2662 if { [istarget powerpc
-*-eabi
]
2663 ||
[istarget powerpc
*-*-eabispe
]
2664 ||
[istarget
*-*-darwin
*]} {
2667 set options
"-mcpu=power9"
2668 check_runtime_nocache p9vector_hw_available
{
2672 vector double v
= (vector double
) { 0.0, 0.0 };
2673 asm
("xsxexpdp %0,%1" : "+r" (e) : "wa" (v));
2681 #
Return 1 if the PowerPC target generates PC
-relative instructions
2682 # automatically
for targets that support PC
-relative instructions.
2683 proc check_effective_target_powerpc_pcrel
{ } {
2684 return [check_no_messages_and_pattern powerpc_pcrel \
2685 {\mpla\M
} assembly
{
2686 static unsigned short s
;
2687 unsigned short
*p_foo
(void
) { return &s
; }
2688 } {-O2
-mcpu
=power10
}]
2691 #
Return 1 if the PowerPC target generates prefixed instructions automatically
2692 #
for targets that support prefixed instructions.
2693 proc check_effective_target_powerpc_prefixed_addr
{ } {
2694 return [check_no_messages_and_pattern powerpc_prefixed_addr \
2695 {\mplwz\M
} assembly
{
2696 unsigned
int foo
(unsigned
int *p
) { return p
[0x12345]; }
2697 } {-O2
-mcpu
=power10
}]
2700 #
Return 1 if the target supports executing power9 modulo instructions
, 0
2701 # otherwise.
Cache the result.
2703 proc check_p9modulo_hw_available
{ } {
2704 return [check_cached_effective_target p9modulo_hw_available
{
2705 # Some simulators are known to not support VSX
/power8
/power9
2706 # instructions.
For now
, disable
on Darwin.
2707 if { [istarget powerpc
-*-eabi
]
2708 ||
[istarget powerpc
*-*-eabispe
]
2709 ||
[istarget
*-*-darwin
*]} {
2712 set options
"-mmodulo"
2713 check_runtime_nocache p9modulo_hw_available
{
2716 int i
= 5, j
= 3, r
= -1;
2717 asm
("modsw %0,%1,%2" : "+r" (r) : "r" (i), "r" (j));
2726 #
Return 1 if the target supports executing power10 instructions
, 0 otherwise.
2727 #
Cache the result. It is assumed that
if a simulator does not support the
2728 # power10 instructions
, that it will generate an error and this test will fail.
2730 proc check_power10_hw_available
{ } {
2731 return [check_cached_effective_target power10_hw_available
{
2732 check_runtime_nocache power10_hw_available
{
2735 /* Set e first and use
+r to check
if pli actually works.
*/
2737 asm
("pli %0,%1" : "+r" (e) : "n" (0x12345));
2746 #
Return 1 if the target supports executing MMA instructions
, 0 otherwise.
2747 #
Cache the result. It is assumed that
if a simulator does not support the
2748 # MMA instructions
, that it will generate an error and this test will fail.
2750 proc check_ppc_mma_hw_available
{ } {
2751 return [check_cached_effective_target ppc_mma_hw_available
{
2752 check_runtime_nocache ppc_mma_hw_available
{
2753 #
include <altivec.h
>
2754 typedef double v4sf_t __attribute__
((vector_size
(16)));
2761 __builtin_mma_xxsetaccz
(&acc0
);
2762 __builtin_mma_disassemble_acc
(result
, &acc0
);
2763 if (result
[0][0] != 0.0)
2771 #
Return 1 if the target supports executing __float128
on PowerPC via software
2772 # emulation
, 0 otherwise.
Cache the result.
2774 proc check_ppc_float128_sw_available
{ } {
2775 return [check_cached_effective_target ppc_float128_sw_available
{
2776 # Some simulators are known to not support VSX
/power8
/power9
2777 # instructions.
For now
, disable
on Darwin and VxWorks.
2778 if { [istarget
*-*-vxworks
*]
2779 ||
[istarget powerpc
-*-eabi
]
2780 ||
[istarget powerpc
*-*-eabispe
]
2781 ||
[istarget
*-*-darwin
*]} {
2784 set options
"-mfloat128 -mvsx"
2785 check_runtime_nocache ppc_float128_sw_available
{
2786 volatile __float128 x
= 1.0q
;
2787 volatile __float128 y
= 2.0q
;
2790 __float128 z
= x
+ y
;
2798 #
Return 1 if the target supports executing __float128
on PowerPC via power9
2799 # hardware instructions
, 0 otherwise.
Cache the result.
2801 proc check_ppc_float128_hw_available
{ } {
2802 return [check_cached_effective_target ppc_float128_hw_available
{
2803 # Some simulators are known to not support VSX
/power8
/power9
2804 # instructions.
For now
, disable
on Darwin.
2805 if { [istarget
*-*-vxworks
*]
2806 ||
[istarget powerpc
-*-eabi
]
2807 ||
[istarget powerpc
*-*-eabispe
]
2808 ||
[istarget
*-*-darwin
*]} {
2811 set options
"-mfloat128 -mvsx -mfloat128-hardware -mcpu=power9"
2812 check_runtime_nocache ppc_float128_hw_available
{
2813 volatile __float128 x
= 1.0q
;
2814 volatile __float128 y
= 2.0q
;
2817 __float128 z
= x
+ y
;
2818 __float128 w
= -1.0q
;
2820 __asm__
("xsaddqp %0,%1,%2" : "+v" (w) : "v" (x), "v" (y));
2821 return ((z
!= 3.0q
) ||
(z
!= w
));
2828 # See
if the __ieee128 keyword is understood.
2829 proc check_effective_target_ppc_ieee128_ok
{ } {
2830 return [check_cached_effective_target ppc_ieee128_ok
{
2831 # disable
on AIX and VxWorks.
2832 if { [istarget
*-*-aix
*]
2833 ||
[istarget
*-*-vxworks
*]} {
2836 set options
"-mfloat128"
2837 check_runtime_nocache ppc_ieee128_ok
{
2848 # Check
if GCC and GLIBC supports explicitly specifying that the long double
2849 # format uses the IBM
128-bit extended double format. Under little endian
2850 # PowerPC Linux
, you need GLIBC
2.32 or later to be able to use a different
2851 # long double format
for running a
program than the
system default.
2853 proc check_effective_target_long_double_ibm128
{ } {
2854 return [check_runtime_nocache long_double_ibm128
{
2857 /* use volatile to prevent optimization.
*/
2858 volatile __ibm128 a
= (__ibm128
) 3.0;
2859 volatile long double one
= 1.0L;
2860 volatile long double two
= 2.0L;
2861 volatile long double b
;
2867 if (sizeof
(long double
) != 16)
2870 /* eliminate removing volatile cast warning.
*/
2873 if (memcmp
(&a2
, &b2
, 16) != 0)
2875 sprintf
(buffer
, "%lg", b);
2876 return strcmp
(buffer
, "3") != 0;
2878 } [add_options_for_long_double_ibm128
""]]
2881 #
Return the appropriate options to specify that long double uses the IBM
2882 #
128-bit format
on PowerPC.
2884 proc add_options_for_long_double_ibm128
{ flags
} {
2885 if { [istarget powerpc
*-*-*] } {
2886 return "$flags -mlong-double-128 -Wno-psabi -mabi=ibmlongdouble"
2891 # Check
if GCC and GLIBC supports explicitly specifying that the long double
2892 # format uses the IEEE
128-bit format. Under little endian PowerPC Linux
, you
2893 # need GLIBC
2.32 or later to be able to use a different long double format
for
2894 # running a
program than the
system default.
2896 proc check_effective_target_long_double_ieee128
{ } {
2897 return [check_runtime_nocache long_double_ieee128
{
2900 /* use volatile to prevent optimization.
*/
2901 volatile _Float128 a
= 3.0f128
;
2902 volatile long double one
= 1.0L;
2903 volatile long double two
= 2.0L;
2904 volatile long double b
;
2910 if (sizeof
(long double
) != 16)
2913 /* eliminate removing volatile cast warning.
*/
2916 if (memcmp
(&a2
, &b2
, 16) != 0)
2918 sprintf
(buffer
, "%lg", b);
2919 return strcmp
(buffer
, "3") != 0;
2921 } [add_options_for_long_double_ieee128
""]]
2924 #
Return the appropriate options to specify that long double uses the IBM
2925 #
128-bit format
on PowerPC.
2926 proc add_options_for_long_double_ieee128
{ flags
} {
2927 if { [istarget powerpc
*-*-*] } {
2928 return "$flags -mlong-double-128 -Wno-psabi -mabi=ieeelongdouble"
2933 # Check
if GCC and GLIBC supports explicitly specifying that the long double
2934 # format uses the IEEE
64-bit. Under little endian PowerPC Linux
, you need
2935 # GLIBC
2.32 or later to be able to use a different long double format
for
2936 # running a
program than the
system default.
2938 proc check_effective_target_long_double_64bit
{ } {
2939 return [check_runtime_nocache long_double_64bit
{
2942 /* use volatile to prevent optimization.
*/
2943 volatile double a
= 3.0;
2944 volatile long double one
= 1.0L;
2945 volatile long double two
= 2.0L;
2946 volatile long double b
;
2952 if (sizeof
(long double
) != 8)
2955 /* eliminate removing volatile cast warning.
*/
2958 if (memcmp
(&a2
, &b2
, 16) != 0)
2960 sprintf
(buffer
, "%lg", b);
2961 return strcmp
(buffer
, "3") != 0;
2963 } [add_options_for_ppc_long_double_override_64bit
""]]
2966 #
Return the appropriate options to specify that long double uses the IEEE
2967 #
64-bit format
on PowerPC.
2969 proc add_options_for_long_double_64bit
{ flags
} {
2970 if { [istarget powerpc
*-*-*] } {
2971 return "$flags -mlong-double-64"
2976 #
Return 1 if the target supports executing VSX instructions
, 0
2977 # otherwise.
Cache the result.
2979 proc check_vsx_hw_available
{ } {
2980 return [check_cached_effective_target vsx_hw_available
{
2981 # Some simulators are known to not support VSX instructions.
2982 #
For now
, disable
on Darwin
2983 if { [istarget powerpc
-*-eabi
]
2984 ||
[istarget powerpc
*-*-eabispe
]
2985 ||
[istarget
*-*-darwin
*]} {
2989 check_runtime_nocache vsx_hw_available
{
2993 asm volatile
("xxlor vs0,vs0,vs0");
2995 asm volatile
("xxlor 0,0,0");
3004 #
Return 1 if the target supports executing AltiVec instructions
, 0
3005 # otherwise.
Cache the result.
3007 proc check_vmx_hw_available
{ } {
3008 return [check_cached_effective_target vmx_hw_available
{
3009 # Some simulators are known to not support VMX instructions.
3010 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] } {
3013 # Most targets don
't require special flags for this test case, but
3014 # Darwin does. Just to be sure, make sure VSX is not enabled for
3015 # the altivec tests.
3016 if { [istarget *-*-darwin*]
3017 || [istarget *-*-aix*] } {
3018 set options "-maltivec -mno-vsx"
3020 set options "-mno-vsx"
3022 check_runtime_nocache vmx_hw_available {
3026 asm volatile ("vor v0,v0,v0");
3028 asm volatile ("vor 0,0,0");
3037 proc check_ppc_recip_hw_available { } {
3038 return [check_cached_effective_target ppc_recip_hw_available {
3039 # Some simulators may not support FRE/FRES/FRSQRTE/FRSQRTES
3040 # For now, disable on Darwin
3041 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
3044 set options "-mpowerpc-gfxopt -mpowerpc-gpopt -mpopcntb"
3045 check_runtime_nocache ppc_recip_hw_available {
3046 volatile double d_recip, d_rsqrt, d_four = 4.0;
3047 volatile float f_recip, f_rsqrt, f_four = 4.0f;
3050 asm volatile ("fres %0,%1" : "=f" (f_recip) : "f" (f_four));
3051 asm volatile ("fre %0,%1" : "=d" (d_recip) : "d" (d_four));
3052 asm volatile ("frsqrtes %0,%1" : "=f" (f_rsqrt) : "f" (f_four));
3053 asm volatile ("frsqrte %0,%1" : "=f" (d_rsqrt) : "d" (d_four));
3061 # Return 1 if the target supports executing AltiVec and Cell PPU
3062 # instructions, 0 otherwise. Cache the result.
3064 proc check_effective_target_cell_hw { } {
3065 return [check_cached_effective_target cell_hw_available {
3066 # Some simulators are known to not support VMX and PPU instructions.
3067 if { [istarget powerpc-*-eabi*] } {
3070 # Most targets don't require special flags
for this test
3071 # case
, but Darwin and AIX
do.
3072 if { [istarget
*-*-darwin
*]
3073 ||
[istarget
*-*-aix
*] } {
3074 set options
"-maltivec -mcpu=cell"
3076 set options
"-mcpu=cell"
3078 check_runtime_nocache cell_hw_available
{
3082 asm volatile
("vor v0,v0,v0");
3083 asm volatile
("lvlx v0,r0,r0");
3085 asm volatile
("vor 0,0,0");
3086 asm volatile
("lvlx 0,0,0");
3095 #
Return 1 if the target supports executing
64-bit instructions
, 0
3096 # otherwise.
Cache the result.
3098 proc check_effective_target_powerpc64
{ } {
3099 global powerpc64_available_saved
3102 if [info exists powerpc64_available_saved
] {
3103 verbose
"check_effective_target_powerpc64 returning saved $powerpc64_available_saved" 2
3105 set powerpc64_available_saved
0
3107 # Some simulators are known to not support powerpc64 instructions.
3108 if { [istarget powerpc
-*-eabi
*] ||
[istarget powerpc
-ibm
-aix
*] } {
3109 verbose
"check_effective_target_powerpc64 returning 0" 2
3110 return $powerpc64_available_saved
3113 #
Set up
, compile, and
execute a test
program containing a
64-bit
3114 # instruction.
Include the current process ID in the file
3115 # names to prevent conflicts with invocations
for multiple
3120 set f
[open $src
"w"]
3121 puts $f
"int main() {"
3122 puts $f
"#ifdef __MACH__"
3123 puts $f
" asm volatile (\"extsw r0,r0\");"
3125 puts $f
" asm volatile (\"extsw 0,0\");"
3127 puts $f
" return 0; }"
3130 set opts
"additional_flags=-mcpu=G5"
3132 verbose
"check_effective_target_powerpc64 compiling testfile $src" 2
3133 set lines
[$
{tool
}_target_compile $src $exe executable
"$opts"]
3136 if [string match
"" $lines] then {
3137 # No error message
, compilation succeeded.
3138 set result
[$
{tool
}_load
"./$exe" "" ""]
3139 set status [lindex $result
0]
3140 remote_file build
delete $exe
3141 verbose
"check_effective_target_powerpc64 testfile status is <$status>" 2
3143 if { $
status == "pass" } then {
3144 set powerpc64_available_saved
1
3147 verbose
"check_effective_target_powerpc64 testfile compilation failed" 2
3151 return $powerpc64_available_saved
3154 # GCC
3.4.0 for powerpc64
-*-linux
* included an ABI fix
for passing
3155 # complex float arguments. This affects gfortran tests that
call cabsf
3156 # in libm built by an earlier compiler.
Return 0 if libm uses the same
3157 #
argument passing as the compiler under test
, 1 otherwise.
3159 proc check_effective_target_broken_cplxf_arg
{ } {
3160 # Skip the work
for targets known not to be affected.
3161 if { ![istarget powerpc
*-*-linux
*] ||
![is
-effective
-target lp64
] } {
3165 return [check_cached_effective_target broken_cplxf_arg
{
3166 check_runtime_nocache broken_cplxf_arg
{
3167 #
include <complex.h
>
3168 extern void abort
(void
);
3169 float fabsf
(float
);
3170 float cabsf
(_Complex float
);
3177 if (fabsf
(f
- 5.0) > 0.0001)
3178 /* Yes
, it
's broken. */
3180 /* All fine, not broken. */
3187 # Return 1 is this is a TI C6X target supporting C67X instructions
3188 proc check_effective_target_ti_c67x { } {
3189 return [check_no_compiler_messages ti_c67x assembly {
3190 #if !defined(_TMS320C6700)
3191 #error !_TMS320C6700
3196 # Return 1 is this is a TI C6X target supporting C64X+ instructions
3197 proc check_effective_target_ti_c64xp { } {
3198 return [check_no_compiler_messages ti_c64xp assembly {
3199 #if !defined(_TMS320C6400_PLUS)
3200 #error !_TMS320C6400_PLUS
3205 # Check if a -march=... option is given, as part of (earlier) options.
3206 proc check_effective_target_march_option { } {
3207 return [check-flags [list "" { *-*-* } { "-march=*" } { "" } ]]
3210 proc check_alpha_max_hw_available { } {
3211 return [check_runtime alpha_max_hw_available {
3212 int main() { return __builtin_alpha_amask(1<<8) != 0; }
3216 # Returns true iff the FUNCTION is available on the target system.
3217 # (This is essentially a Tcl implementation of Autoconf's
3220 proc check_function_available
{ function
} {
3221 return [check_no_compiler_messages $
{function
}_available \
3227 int main
() { $function
(); }
3231 # Returns true iff
"fork" is available on the target system.
3233 proc check_fork_available
{} {
3234 if { [istarget
*-*-vxworks
*] } {
3235 # VxWorks doesn
't have fork but our way to test can't
3236 # tell as we
're doing partial links for kernel modules.
3239 if { [istarget cris-*-*] } {
3240 # Compiling and linking works, and an executable running e.g.
3241 # gcc.dg/torture/ftrapv-1.c works on now-historical hardware,
3242 # but the GNU simulator emits an error for the fork syscall.
3243 return [check_effective_target_hw]
3245 return [check_function_available "fork"]
3248 # Returns true iff "mkfifo" is available on the target system.
3250 proc check_mkfifo_available {} {
3251 if { [istarget *-*-cygwin*] } {
3252 # Cygwin has mkfifo, but support is incomplete.
3256 return [check_function_available "mkfifo"]
3259 # Returns true iff "__cxa_atexit" is used on the target system.
3261 proc check_cxa_atexit_available { } {
3262 return [check_cached_effective_target cxa_atexit_available {
3263 if { [istarget *-*-vxworks] } {
3264 # vxworks doesn't have __cxa_atexit but subsequent test passes.
3267 check_runtime_nocache cxa_atexit_available
{
3270 static unsigned
int count;
3287 Y
() { f
(); count = 2; }
3296 int main
() { return 0; }
3302 proc check_effective_target_objc2
{ } {
3303 return [check_no_compiler_messages objc2 object
{
3312 proc check_effective_target_next_runtime
{ } {
3313 return [check_no_compiler_messages objc2 object
{
3314 #ifdef __NEXT_RUNTIME__
3317 #error
!__NEXT_RUNTIME__
3322 #
Return 1 if we
're generating code for big-endian memory order.
3324 proc check_effective_target_be { } {
3325 return [check_no_compiler_messages be object {
3326 int dummy[__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ? 1 : -1];
3330 # Return 1 if we're generating code
for little
-endian memory order.
3332 proc check_effective_target_le
{ } {
3333 return [check_no_compiler_messages le object
{
3334 int dummy
[__BYTE_ORDER__
== __ORDER_LITTLE_ENDIAN__ ?
1 : -1];
3338 #
Return 1 if we can link a
program with
2+GB of data.
3340 proc check_effective_target_two_plus_gigs
{ } {
3341 return [check_no_compiler_messages two_plus_gigs executable
{
3342 char dummy
[0x80000000];
3343 int main
() { return 0; }
3347 #
Return 1 if we
're generating 32-bit code using default options, 0
3350 proc check_effective_target_ilp32 { } {
3351 return [check_no_compiler_messages ilp32 object {
3352 int dummy[sizeof (int) == 4
3353 && sizeof (void *) == 4
3354 && sizeof (long) == 4 ? 1 : -1];
3358 # Return 1 if we're generating ia32 code using default options
, 0
3361 proc check_effective_target_ia32
{ } {
3362 return [check_no_compiler_messages ia32 object
{
3363 int dummy
[sizeof
(int) == 4
3364 && sizeof
(void
*) == 4
3365 && sizeof
(long
) == 4 ?
1 : -1] = { __i386__
};
3369 #
Return 1 if we
're generating x32 code using default options, 0
3372 proc check_effective_target_x32 { } {
3373 return [check_no_compiler_messages x32 object {
3374 int dummy[sizeof (int) == 4
3375 && sizeof (void *) == 4
3376 && sizeof (long) == 4 ? 1 : -1] = { __x86_64__ };
3380 # Return 1 if we're generating
32-bit integers using default
3381 # options
, 0 otherwise.
3383 proc check_effective_target_int32
{ } {
3384 return [check_no_compiler_messages int32 object
{
3385 int dummy
[sizeof
(int) == 4 ?
1 : -1];
3389 #
Return 1 if we
're generating 32-bit or larger integers using default
3390 # options, 0 otherwise.
3392 proc check_effective_target_int32plus { } {
3393 return [check_no_compiler_messages int32plus object {
3394 int dummy[sizeof (int) >= 4 ? 1 : -1];
3398 # Return 1 if we're generating
64-bit long long using default options
,
3401 proc check_effective_target_longlong64
{ } {
3402 return [check_no_compiler_messages longlong64 object
{
3403 int dummy
[sizeof
(long long
) == 8 ?
1 : -1];
3407 #
Return 1 if we
're generating 32-bit or larger pointers using default
3408 # options, 0 otherwise.
3410 proc check_effective_target_ptr32plus { } {
3411 # The msp430 has 16-bit or 20-bit pointers. The 20-bit pointer is stored
3412 # in a 32-bit slot when in memory, so sizeof(void *) returns 4, but it
3413 # cannot really hold a 32-bit address, so we always return false here.
3414 if { [istarget msp430-*-*] } {
3418 return [check_no_compiler_messages ptr32plus object {
3419 int dummy[sizeof (void *) >= 4 ? 1 : -1];
3423 # Return 1 if we support 16-bit or larger array and structure sizes
3424 # using default options, 0 otherwise.
3425 # This implies at least a 20-bit address space, as no targets have an address
3426 # space between 16 and 20 bits.
3428 proc check_effective_target_size20plus { } {
3429 return [check_no_compiler_messages size20plus object {
3434 # Return 1 if target supports function pointers, 0 otherwise.
3436 proc check_effective_target_function_pointers { } {
3437 if { [istarget pru-*-*] } {
3438 return [check_no_compiler_messages func_ptr_avail assembly {
3439 #ifdef __PRU_EABI_GNU__
3447 # Return 1 if target supports arbitrarily large return values, 0 otherwise.
3449 proc check_effective_target_large_return_values { } {
3450 if { [istarget pru-*-*] } {
3451 return [check_no_compiler_messages large_return_values assembly {
3452 #ifdef __PRU_EABI_GNU__
3459 # Return 1 if we support 20-bit or larger array and structure sizes
3460 # using default options, 0 otherwise.
3461 # This implies at least a 24-bit address space, as no targets have an address
3462 # space between 20 and 24 bits.
3464 proc check_effective_target_size24plus { } {
3465 return [check_no_compiler_messages size24plus object {
3466 char dummy[524289L];
3470 # Return 1 if we support 24-bit or larger array and structure sizes
3471 # using default options, 0 otherwise.
3472 # This implies at least a 32-bit address space, as no targets have an address
3473 # space between 24 and 32 bits.
3475 proc check_effective_target_size32plus { } {
3476 return [check_no_compiler_messages size32plus object {
3477 char dummy[16777217L];
3481 # Returns 1 if we're generating
16-bit or smaller integers with the
3482 # default options
, 0 otherwise.
3484 proc check_effective_target_int16
{ } {
3485 return [check_no_compiler_messages int16 object
{
3486 int dummy
[sizeof
(int) < 4 ?
1 : -1];
3490 #
Return 1 if we
're generating 64-bit code using default options, 0
3493 proc check_effective_target_lp64 { } {
3494 return [check_no_compiler_messages lp64 object {
3495 int dummy[sizeof (int) == 4
3496 && sizeof (void *) == 8
3497 && sizeof (long) == 8 ? 1 : -1];
3501 # Return 1 if we're generating
64-bit code using default llp64 options
,
3504 proc check_effective_target_llp64
{ } {
3505 return [check_no_compiler_messages llp64 object
{
3506 int dummy
[sizeof
(int) == 4
3507 && sizeof
(void
*) == 8
3508 && sizeof
(long long
) == 8
3509 && sizeof
(long
) == 4 ?
1 : -1];
3513 #
Return 1 if long and
int have different sizes
,
3516 proc check_effective_target_long_neq_int
{ } {
3517 return [check_no_compiler_messages long_ne_int object
{
3518 int dummy
[sizeof
(int) != sizeof
(long
) ?
1 : -1];
3522 #
Return 1 if int size is equal to float size
,
3525 proc check_effective_target_int_eq_float
{ } {
3526 return [check_no_compiler_messages int_eq_float object
{
3527 int dummy
[sizeof
(int) >= sizeof
(float
) ?
1 : -1];
3531 #
Return 1 if short size is equal to
int size
,
3534 proc check_effective_target_short_eq_int
{ } {
3535 return [check_no_compiler_messages short_eq_int object
{
3536 int dummy
[sizeof
(short
) == sizeof
(int) ?
1 : -1];
3540 #
Return 1 if pointer size is equal to short size
,
3543 proc check_effective_target_ptr_eq_short
{ } {
3544 return [check_no_compiler_messages ptr_eq_short object
{
3545 int dummy
[sizeof
(void
*) == sizeof
(short
) ?
1 : -1];
3549 #
Return 1 if pointer size is equal to long size
,
3552 proc check_effective_target_ptr_eq_long
{ } {
3553 # sizeof
(void
*) == 4 for msp430
-elf
-mlarge which is equal to
3554 # sizeof
(long
). Avoid false positive.
3555 if { [istarget msp430
-*-*] } {
3558 return [check_no_compiler_messages ptr_eq_long object
{
3559 int dummy
[sizeof
(void
*) == sizeof
(long
) ?
1 : -1];
3563 #
Return 1 if the target supports long double larger than double
,
3566 proc check_effective_target_large_long_double
{ } {
3567 return [check_no_compiler_messages large_long_double object
{
3568 int dummy
[sizeof
(long double
) > sizeof
(double
) ?
1 : -1];
3572 #
Return 1 if the target supports double larger than float
,
3575 proc check_effective_target_large_double
{ } {
3576 return [check_no_compiler_messages large_double object
{
3577 int dummy
[sizeof
(double
) > sizeof
(float
) ?
1 : -1];
3581 #
Return 1 if the target supports long double of
128 bits
,
3584 proc check_effective_target_longdouble128
{ } {
3585 return [check_no_compiler_messages longdouble128 object
{
3586 int dummy
[sizeof
(long double
) == 16 ?
1 : -1];
3590 #
Return 1 if the target supports long double of
64 bits
,
3593 proc check_effective_target_longdouble64
{ } {
3594 return [check_no_compiler_messages longdouble64 object
{
3595 int dummy
[sizeof
(long double
) == 8 ?
1 : -1];
3599 #
Return 1 if the target supports double of
64 bits
,
3602 proc check_effective_target_double64
{ } {
3603 return [check_no_compiler_messages double64 object
{
3604 int dummy
[sizeof
(double
) == 8 ?
1 : -1];
3608 #
Return 1 if the target supports double of at least
64 bits
,
3611 proc check_effective_target_double64plus
{ } {
3612 return [check_no_compiler_messages double64plus object
{
3613 int dummy
[sizeof
(double
) >= 8 ?
1 : -1];
3617 #
Return 1 if the target supports
'w' suffix
on floating constant
3620 proc check_effective_target_has_w_floating_suffix
{ } {
3622 if [check_effective_target_c
++] {
3623 append opts
"-std=gnu++03"
3625 return [check_no_compiler_messages w_fp_suffix object
{
3630 #
Return 1 if the target supports
'q' suffix
on floating constant
3633 proc check_effective_target_has_q_floating_suffix
{ } {
3635 if [check_effective_target_c
++] {
3636 append opts
"-std=gnu++03"
3638 return [check_no_compiler_messages q_fp_suffix object
{
3643 #
Return 1 if the target supports the _FloatN
/ _FloatNx type
3644 # indicated in the function
name, 0 otherwise.
3646 proc check_effective_target_float16
{} {
3647 return [check_no_compiler_messages_nocache float16 object
{
3648 _Float16 foo
(_Float16 x
) { return x
; }
3649 } [add_options_for_float16
""]]
3652 proc check_effective_target_float32
{} {
3653 return [check_no_compiler_messages_nocache float32 object
{
3655 } [add_options_for_float32
""]]
3658 proc check_effective_target_float64
{} {
3659 return [check_no_compiler_messages_nocache float64 object
{
3661 } [add_options_for_float64
""]]
3664 proc check_effective_target_float128
{} {
3665 return [check_no_compiler_messages_nocache float128 object
{
3667 } [add_options_for_float128
""]]
3670 proc check_effective_target_float32x
{} {
3671 return [check_no_compiler_messages_nocache float32x object
{
3673 } [add_options_for_float32x
""]]
3676 proc check_effective_target_float64x
{} {
3677 return [check_no_compiler_messages_nocache float64x object
{
3679 } [add_options_for_float64x
""]]
3682 proc check_effective_target_float128x
{} {
3683 return [check_no_compiler_messages_nocache float128x object
{
3685 } [add_options_for_float128x
""]]
3688 # Likewise
, but runtime support
for any special options used as well
3689 # as
compile-time support is required.
3691 proc check_effective_target_float16_runtime
{} {
3692 return [check_effective_target_float16
]
3695 proc check_effective_target_float32_runtime
{} {
3696 return [check_effective_target_float32
]
3699 proc check_effective_target_float64_runtime
{} {
3700 return [check_effective_target_float64
]
3703 proc check_effective_target_float128_runtime
{} {
3704 if { ![check_effective_target_float128
] } {
3707 if { [istarget powerpc
*-*-*] } {
3708 return [check_effective_target_base_quadfloat_support
]
3713 proc check_effective_target_float32x_runtime
{} {
3714 return [check_effective_target_float32x
]
3717 proc check_effective_target_float64x_runtime
{} {
3718 if { ![check_effective_target_float64x
] } {
3721 if { [istarget powerpc
*-*-*] } {
3722 return [check_effective_target_base_quadfloat_support
]
3727 proc check_effective_target_float128x_runtime
{} {
3728 return [check_effective_target_float128x
]
3731 #
Return 1 if the target hardware supports
any options added
for
3732 # _FloatN and _FloatNx types
, 0 otherwise.
3734 proc check_effective_target_floatn_nx_runtime
{} {
3735 if { [istarget powerpc
*-*-aix
*] } {
3738 if { [istarget powerpc
*-*-*] } {
3739 return [check_effective_target_base_quadfloat_support
]
3744 # Add options needed to use the _FloatN
/ _FloatNx type indicated in
3745 # the function
name.
3747 proc add_options_for_float16
{ flags
} {
3748 if { [istarget arm
*-*-*] } {
3749 return "$flags -mfp16-format=ieee"
3751 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*] } {
3752 return "$flags -msse2"
3757 proc add_options_for_float32
{ flags
} {
3761 proc add_options_for_float64
{ flags
} {
3765 proc add_options_for_float128
{ flags
} {
3766 return [add_options_for___float128
"$flags"]
3769 proc add_options_for_float32x
{ flags
} {
3773 proc add_options_for_float64x
{ flags
} {
3774 return [add_options_for___float128
"$flags"]
3777 proc add_options_for_float128x
{ flags
} {
3781 #
Return 1 if the target supports __float128
,
3784 proc check_effective_target___float128
{ } {
3785 if { [istarget powerpc
*-*-*] } {
3786 return [check_ppc_float128_sw_available
]
3788 if { [istarget ia64
-*-*]
3789 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*] } {
3795 proc add_options_for___float128
{ flags
} {
3796 if { [istarget powerpc
*-*-linux
*] } {
3797 return "$flags -mfloat128 -mvsx"
3802 #
Return 1 if the target supports
any special run
-time requirements
3803 #
for __float128 or _Float128
,
3806 proc check_effective_target_base_quadfloat_support
{ } {
3807 if { [istarget powerpc
*-*-*] } {
3808 return [check_vsx_hw_available
]
3813 #
Return 1 if the target supports the __bf16 type
, 0 otherwise.
3815 proc check_effective_target_bfloat16
{} {
3816 return [check_no_compiler_messages_nocache bfloat16 object
{
3817 __bf16 foo
(__bf16 x
) { return x
+ x
; }
3818 } [add_options_for_bfloat16
""]]
3821 proc check_effective_target_bfloat16_runtime
{} {
3822 return [check_effective_target_bfloat16
]
3825 proc add_options_for_bfloat16
{ flags
} {
3826 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*] } {
3827 return "$flags -msse2"
3832 #
Return 1 if the target supports all four forms of fused multiply
-add
3833 #
(fma
, fms
, fnma
, and fnms
) for both float and double.
3835 proc check_effective_target_scalar_all_fma
{ } {
3836 if { [istarget aarch64
*-*-*]
3837 ||
[istarget loongarch
*-*-*]} {
3843 #
Return 1 if the target supports compiling fixed
-point
,
3846 proc check_effective_target_fixed_point
{ } {
3847 return [check_no_compiler_messages fixed_point object
{
3848 _Sat _Fract x
; _Sat _Accum y
;
3852 #
Return 1 if the target supports _BitInt
(N
), 0 otherwise.
3854 proc check_effective_target_bitint
{ } {
3855 return [check_no_compiler_messages bitint object
{
3856 _BitInt
(2) a
= 1wb
;
3857 unsigned _BitInt
(__BITINT_MAXWIDTH__
) b
= 0uwb
;
3861 #
Return 1 if the target supports _BitInt
(128), 0 otherwise.
3863 proc check_effective_target_bitint128
{ } {
3864 return [check_no_compiler_messages bitint128 object
{
3865 _BitInt
(2) a
= 1wb
;
3866 unsigned _BitInt
(128) b
= 0uwb
;
3870 #
Return 1 if the target supports _BitInt
(575), 0 otherwise.
3872 proc check_effective_target_bitint575
{ } {
3873 return [check_no_compiler_messages bitint575 object
{
3874 _BitInt
(2) a
= 1wb
;
3875 unsigned _BitInt
(575) b
= 0uwb
;
3879 #
Return 1 if the target supports _BitInt
(65535), 0 otherwise.
3881 proc check_effective_target_bitint65535
{ } {
3882 return [check_no_compiler_messages bitint65535 object
{
3883 _BitInt
(2) a
= 1wb
;
3884 unsigned _BitInt
(65535) b
= 0uwb
;
3888 #
Return 1 if the target supports compiling decimal floating point
,
3891 proc check_effective_target_dfp_nocache
{ } {
3892 verbose
"check_effective_target_dfp_nocache: compiling source" 2
3893 set ret
[check_no_compiler_messages_nocache dfp object
{
3894 float x __attribute__
((mode(DD
)));
3896 verbose
"check_effective_target_dfp_nocache: returning $ret" 2
3900 proc check_effective_target_dfprt_nocache
{ } {
3901 return [check_runtime_nocache dfprt
{
3902 typedef float d64 __attribute__
((mode(DD
)));
3903 d64 x
= 1.2df
, y
= 2.3dd
, z
;
3904 int main
() { z
= x
+ y
; return 0; }
3908 #
Return 1 if the target supports compiling Decimal Floating Point
,
3911 # This won
't change for different subtargets so cache the result.
3913 proc check_effective_target_dfp { } {
3914 return [check_cached_effective_target dfp {
3915 check_effective_target_dfp_nocache
3919 # Return 1 if the target supports linking and executing Decimal Floating
3920 # Point, 0 otherwise.
3922 # This won't change
for different subtargets so
cache the result.
3924 proc check_effective_target_dfprt
{ } {
3925 return [check_cached_effective_target dfprt
{
3926 check_effective_target_dfprt_nocache
3930 #
Return 1 if the target uses the BID format
for Decimal Floating
3931 # Point
, 0 otherwise.
3933 proc check_effective_target_dfp_bid
{ } {
3934 if { [istarget aarch64
*-*-*]
3935 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]} {
3941 #
Return 1 iff target has unsigned plain
'char' by default.
3943 proc check_effective_target_unsigned_char
{} {
3944 return [check_no_compiler_messages unsigned_char assembly
{
3949 proc check_effective_target_powerpc_popcntb_ok
{ } {
3950 return [check_cached_effective_target powerpc_popcntb_ok
{
3952 # Disable
on Darwin.
3953 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] ||
[istarget
*-*-darwin
*]} {
3956 check_runtime_nocache powerpc_popcntb_ok
{
3958 volatile
int a
= 0x12345678;
3961 asm volatile
("popcntb %0,%1" : "=r" (r) : "r" (a));
3969 #
Return 1 if the target supports executing DFP hardware instructions
,
3970 #
0 otherwise.
Cache the result.
3972 proc check_dfp_hw_available
{ } {
3973 return [check_cached_effective_target dfp_hw_available
{
3974 #
For now
, disable
on Darwin
3975 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] ||
[istarget
*-*-darwin
*]} {
3978 check_runtime_nocache dfp_hw_available
{
3979 volatile _Decimal64 r
;
3980 volatile _Decimal64 a
= 4.0DD
;
3981 volatile _Decimal64 b
= 2.0DD
;
3984 asm volatile
("dadd %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3985 asm volatile
("dsub %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3986 asm volatile
("dmul %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3987 asm volatile
("ddiv %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3990 } "-mcpu=power6 -mhard-float"
3995 #
Return 1 if the target supports compiling and assembling UCN
, 0 otherwise.
3997 proc check_effective_target_ucn_nocache
{ } {
3998 #
-std
=c99 is only valid
for C
3999 if [check_effective_target_c
] {
4000 set ucnopts
"-std=c99"
4004 verbose
"check_effective_target_ucn_nocache: compiling source" 2
4005 set ret
[check_no_compiler_messages_nocache ucn object
{
4008 verbose
"check_effective_target_ucn_nocache: returning $ret" 2
4012 #
Return 1 if the target supports compiling and assembling UCN
, 0 otherwise.
4014 # This won
't change for different subtargets, so cache the result.
4016 proc check_effective_target_ucn { } {
4017 return [check_cached_effective_target ucn {
4018 check_effective_target_ucn_nocache
4022 # Return 1 if the target needs a command line argument to enable a SIMD
4025 proc check_effective_target_vect_cmdline_needed { } {
4026 global et_vect_cmdline_needed_target_name
4028 if { ![info exists et_vect_cmdline_needed_target_name] } {
4029 set et_vect_cmdline_needed_target_name ""
4032 # If the target has changed since we set the cached value, clear it.
4033 set current_target [current_target_name]
4034 if { $current_target != $et_vect_cmdline_needed_target_name } {
4035 verbose "check_effective_target_vect_cmdline_needed: `$et_vect_cmdline_needed_target_name' `$current_target
'" 2
4036 set et_vect_cmdline_needed_target_name $current_target
4037 if { [info exists et_vect_cmdline_needed_saved] } {
4038 verbose "check_effective_target_vect_cmdline_needed: removing cached result" 2
4039 unset et_vect_cmdline_needed_saved
4043 return [check_cached_effective_target vect_cmdline_needed {
4044 if { [istarget alpha*-*-*]
4045 || [istarget ia64-*-*]
4046 || (([istarget i?86-*-*] || [istarget x86_64-*-*])
4047 && ![is-effective-target ia32])
4048 || ([istarget powerpc*-*-*]
4049 && ([check_effective_target_powerpc_spe]
4050 || [check_effective_target_powerpc_altivec]))
4051 || ([istarget sparc*-*-*] && [check_effective_target_sparc_vis])
4052 || ([istarget arm*-*-*] && [check_effective_target_arm_neon])
4053 || [istarget aarch64*-*-*]
4054 || [istarget amdgcn*-*-*]
4055 || [istarget riscv*-*-*]} {
4062 # Return 1 if the target supports hardware vectors of int, 0 otherwise.
4064 # This won't change
for different subtargets so
cache the result.
4066 proc check_effective_target_vect_int
{ } {
4067 return [check_cached_effective_target_indexed vect_int
{
4069 [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
4070 ||
([istarget powerpc
*-*-*]
4071 && ![istarget powerpc
-*-linux
*paired
*])
4072 ||
[istarget amdgcn
-*-*]
4073 ||
[istarget sparc
*-*-*]
4074 ||
[istarget alpha
*-*-*]
4075 ||
[istarget ia64
-*-*]
4076 ||
[istarget aarch64
*-*-*]
4077 ||
[is
-effective
-target arm_neon
]
4078 ||
([istarget mips
*-*-*]
4079 && ([et
-is
-effective
-target mips_loongson_mmi
]
4080 ||
[et
-is
-effective
-target mips_msa
]))
4081 ||
([istarget s390
*-*-*]
4082 && [check_effective_target_s390_vx
])
4083 ||
([istarget riscv
*-*-*]
4084 && [check_effective_target_riscv_v
])
4085 ||
([istarget loongarch
*-*-*]
4086 && [check_effective_target_loongarch_sx
])
4090 #
Return 1 if the target supports vectorization of early breaks
,
4093 # This won
't change for different subtargets so cache the result.
4095 proc check_effective_target_vect_early_break { } {
4096 return [check_cached_effective_target_indexed vect_early_break {
4098 [istarget aarch64*-*-*]
4099 || [check_effective_target_arm_v8_neon_ok]
4100 || [check_effective_target_sse4]
4101 || [istarget amdgcn-*-*]
4105 # Return 1 if the target supports hardware execution of early breaks,
4108 # This won't change
for different subtargets so
cache the result.
4110 proc check_effective_target_vect_early_break_hw
{ } {
4111 return [check_cached_effective_target_indexed vect_early_break_hw
{
4113 [istarget aarch64
*-*-*]
4114 ||
[check_effective_target_arm_v8_neon_hw
]
4115 ||
[check_sse4_hw_available
]
4116 ||
[istarget amdgcn
-*-*]
4120 proc add_options_for_vect_early_break
{ flags
} {
4121 if { ! [check_effective_target_vect_early_break
] } {
4125 if { [check_effective_target_arm_v8_neon_ok
] } {
4126 global et_arm_v8_neon_flags
4127 return "$flags $et_arm_v8_neon_flags -march=armv8-a"
4130 if { [check_effective_target_sse4
] } {
4131 return "$flags -msse4.1"
4137 #
Return 1 if the target supports hardware vectorization of complex additions of
4138 # byte
, 0 otherwise.
4140 # This won
't change for different subtargets so cache the result.
4142 proc check_effective_target_vect_complex_add_byte { } {
4143 return [check_cached_effective_target_indexed vect_complex_add_byte {
4145 ([check_effective_target_aarch64_sve2]
4146 && [check_effective_target_aarch64_little_endian])
4147 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4148 && [check_effective_target_arm_little_endian])
4152 # Return 1 if the target supports hardware vectorization of complex additions of
4153 # short, 0 otherwise.
4155 # This won't change
for different subtargets so
cache the result.
4157 proc check_effective_target_vect_complex_add_short
{ } {
4158 return [check_cached_effective_target_indexed vect_complex_add_short
{
4160 ([check_effective_target_aarch64_sve2
]
4161 && [check_effective_target_aarch64_little_endian
])
4162 ||
([check_effective_target_arm_v8_1m_mve_fp_ok
]
4163 && [check_effective_target_arm_little_endian
])
4167 #
Return 1 if the target supports hardware vectorization of complex additions of
4170 # This won
't change for different subtargets so cache the result.
4172 proc check_effective_target_vect_complex_add_int { } {
4173 return [check_cached_effective_target_indexed vect_complex_add_int {
4175 ([check_effective_target_aarch64_sve2]
4176 && [check_effective_target_aarch64_little_endian])
4177 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4178 && [check_effective_target_arm_little_endian])
4182 # Return 1 if the target supports hardware vectorization of complex additions of
4183 # long, 0 otherwise.
4185 # This won't change
for different subtargets so
cache the result.
4187 proc check_effective_target_vect_complex_add_long
{ } {
4188 return [check_cached_effective_target_indexed vect_complex_add_long
{
4190 ([check_effective_target_aarch64_sve2
]
4191 && [check_effective_target_aarch64_little_endian
])
4192 ||
([check_effective_target_arm_v8_1m_mve_fp_ok
]
4193 && [check_effective_target_arm_little_endian
])
4197 #
Return 1 if the target supports hardware vectorization of complex additions of
4198 # half
, 0 otherwise.
4200 # This won
't change for different subtargets so cache the result.
4202 proc check_effective_target_vect_complex_add_half { } {
4203 return [check_cached_effective_target_indexed vect_complex_add_half {
4205 ([check_effective_target_arm_v8_3a_fp16_complex_neon_ok]
4206 && ([check_effective_target_aarch64_little_endian]
4207 || [check_effective_target_arm_little_endian]))
4208 || ([check_effective_target_aarch64_sve2]
4209 && [check_effective_target_aarch64_little_endian])
4210 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4211 && [check_effective_target_arm_little_endian])
4215 # Return 1 if the target supports hardware vectorization of complex additions of
4216 # float, 0 otherwise.
4218 # This won't change
for different subtargets so
cache the result.
4220 proc check_effective_target_vect_complex_add_float
{ } {
4221 return [check_cached_effective_target_indexed vect_complex_add_float
{
4223 ([check_effective_target_arm_v8_3a_complex_neon_ok
]
4224 && ([check_effective_target_aarch64_little_endian
]
4225 ||
[check_effective_target_arm_little_endian
]))
4226 ||
([check_effective_target_aarch64_sve2
]
4227 && [check_effective_target_aarch64_little_endian
])
4228 ||
([check_effective_target_arm_v8_1m_mve_fp_ok
]
4229 && [check_effective_target_arm_little_endian
])
4233 #
Return 1 if the target supports hardware vectorization of complex additions of
4234 # double
, 0 otherwise.
4236 # This won
't change for different subtargets so cache the result.
4238 proc check_effective_target_vect_complex_add_double { } {
4239 return [check_cached_effective_target_indexed vect_complex_add_double {
4241 (([check_effective_target_arm_v8_3a_complex_neon_ok]
4242 && [check_effective_target_aarch64_little_endian])
4243 || ([check_effective_target_aarch64_sve2]
4244 && [check_effective_target_aarch64_little_endian]))
4248 # Return 1 if the target supports signed int->float conversion
4251 proc check_effective_target_vect_intfloat_cvt { } {
4252 return [check_cached_effective_target_indexed vect_intfloat_cvt {
4253 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
4254 || ([istarget powerpc*-*-*]
4255 && ![istarget powerpc-*-linux*paired*])
4256 || [is-effective-target arm_neon]
4257 || ([istarget mips*-*-*]
4258 && [et-is-effective-target mips_msa])
4259 || [istarget amdgcn-*-*]
4260 || ([istarget s390*-*-*]
4261 && [check_effective_target_s390_vxe2])
4262 || ([istarget riscv*-*-*]
4263 && [check_effective_target_riscv_v])
4264 || ([istarget loongarch*-*-*]
4265 && [check_effective_target_loongarch_sx]) }}]
4268 # Return 1 if the target supports signed double->int conversion
4271 proc check_effective_target_vect_doubleint_cvt { } {
4272 return [check_cached_effective_target_indexed vect_doubleint_cvt {
4273 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4274 && [check_no_compiler_messages vect_doubleint_cvt assembly {
4275 #ifdef __tune_atom__
4276 # error No double vectorizer support.
4279 || [istarget aarch64*-*-*]
4280 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
4281 || ([istarget mips*-*-*]
4282 && [et-is-effective-target mips_msa])
4283 || ([istarget s390*-*-*]
4284 && [check_effective_target_s390_vx])
4285 || ([istarget riscv*-*-*]
4286 && [check_effective_target_riscv_v])
4287 || ([istarget loongarch*-*-*]
4288 && [check_effective_target_loongarch_sx]) }}]
4291 # Return 1 if the target supports signed int->double conversion
4294 proc check_effective_target_vect_intdouble_cvt { } {
4295 return [check_cached_effective_target_indexed vect_intdouble_cvt {
4296 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4297 && [check_no_compiler_messages vect_intdouble_cvt assembly {
4298 #ifdef __tune_atom__
4299 # error No double vectorizer support.
4302 || [istarget aarch64*-*-*]
4303 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
4304 || ([istarget mips*-*-*]
4305 && [et-is-effective-target mips_msa])
4306 || ([istarget s390*-*-*]
4307 && [check_effective_target_s390_vx])
4308 || ([istarget riscv*-*-*]
4309 && [check_effective_target_riscv_v])
4310 || ([istarget loongarch*-*-*]
4311 && [check_effective_target_loongarch_sx]) }}]
4314 #Return 1 if we're supporting __int128
for target
, 0 otherwise.
4316 proc check_effective_target_int128
{ } {
4317 return [check_no_compiler_messages int128 object
{
4319 #ifndef __SIZEOF_INT128__
4328 #
Return 1 if the target supports unsigned
int->float conversion
4331 proc check_effective_target_vect_uintfloat_cvt
{ } {
4332 return [check_cached_effective_target_indexed vect_uintfloat_cvt
{
4333 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
4334 ||
([istarget powerpc
*-*-*]
4335 && ![istarget powerpc
-*-linux
*paired
*])
4336 ||
[istarget aarch64
*-*-*]
4337 ||
[is
-effective
-target arm_neon
]
4338 ||
([istarget mips
*-*-*]
4339 && [et
-is
-effective
-target mips_msa
])
4340 ||
[istarget amdgcn
-*-*]
4341 ||
([istarget s390
*-*-*]
4342 && [check_effective_target_s390_vxe2
])
4343 ||
([istarget riscv
*-*-*]
4344 && [check_effective_target_riscv_v
])
4345 ||
([istarget loongarch
*-*-*]
4346 && [check_effective_target_loongarch_sx
]) }}]
4350 #
Return 1 if the target supports signed float
->int conversion
4353 proc check_effective_target_vect_floatint_cvt
{ } {
4354 return [check_cached_effective_target_indexed vect_floatint_cvt
{
4355 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
4356 ||
([istarget powerpc
*-*-*]
4357 && ![istarget powerpc
-*-linux
*paired
*])
4358 ||
[is
-effective
-target arm_neon
]
4359 ||
([istarget mips
*-*-*]
4360 && [et
-is
-effective
-target mips_msa
])
4361 ||
[istarget amdgcn
-*-*]
4362 ||
([istarget s390
*-*-*]
4363 && [check_effective_target_s390_vxe2
])
4364 ||
([istarget riscv
*-*-*]
4365 && [check_effective_target_riscv_v
])
4366 ||
([istarget loongarch
*-*-*]
4367 && [check_effective_target_loongarch_sx
]) }}]
4370 #
Return 1 if the target supports unsigned float
->int conversion
4373 proc check_effective_target_vect_floatuint_cvt
{ } {
4374 return [check_cached_effective_target_indexed vect_floatuint_cvt
{
4375 expr
{ ([istarget powerpc
*-*-*]
4376 && ![istarget powerpc
-*-linux
*paired
*])
4377 ||
[is
-effective
-target arm_neon
]
4378 ||
([istarget mips
*-*-*]
4379 && [et
-is
-effective
-target mips_msa
])
4380 ||
[istarget amdgcn
-*-*]
4381 ||
([istarget s390
*-*-*]
4382 && [check_effective_target_s390_vxe2
])
4383 ||
([istarget riscv
*-*-*]
4384 && [check_effective_target_riscv_v
])
4385 ||
([istarget loongarch
*-*-*]
4386 && [check_effective_target_loongarch_sx
]) }}]
4389 #
Return 1 if the target supports vector
integer char
-> long long extend optab
4392 proc check_effective_target_vect_ext_char_longlong
{ } {
4393 return [check_cached_effective_target_indexed vect_ext_char_longlong
{
4394 expr
{ ([istarget riscv
*-*-*]
4395 && [check_effective_target_riscv_v
])
4396 ||
([istarget loongarch
*-*-*]
4397 && [check_effective_target_loongarch_sx
]) }}]
4400 #
Return 1 if peeling
for alignment might be profitable
on the target
4403 proc check_effective_target_vect_peeling_profitable
{ } {
4404 return [check_cached_effective_target_indexed vect_peeling_profitable
{
4405 expr
{ ([istarget s390
*-*-*]
4406 && [check_effective_target_s390_vx
])
4407 ||
[check_effective_target_vect_element_align_preferred
] }}]
4410 #
Return 1 if the target supports #pragma omp declare simd
, 0 otherwise.
4412 # This won
't change for different subtargets so cache the result.
4414 proc check_effective_target_vect_simd_clones { } {
4415 # On i?86/x86_64 #pragma omp declare simd builds a sse2, avx,
4416 # avx2 and avx512f clone. Only the right clone for the
4417 # specified arch will be chosen, but still we need to at least
4418 # be able to assemble avx512f.
4419 return [check_cached_effective_target_indexed vect_simd_clones {
4420 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4421 && [check_effective_target_avx512f])
4422 || [istarget amdgcn-*-*]
4423 || [istarget aarch64*-*-*] }}]
4426 # Return 1 if this is a AArch64 target supporting big endian
4427 proc check_effective_target_aarch64_big_endian { } {
4428 return [check_no_compiler_messages aarch64_big_endian assembly {
4429 #if !defined(__aarch64__) || !defined(__AARCH64EB__)
4430 #error !__aarch64__ || !__AARCH64EB__
4435 # Return 1 if this is a AArch64 target supporting little endian
4436 proc check_effective_target_aarch64_little_endian { } {
4437 if { ![istarget aarch64*-*-*] } {
4441 return [check_no_compiler_messages aarch64_little_endian assembly {
4442 #if !defined(__aarch64__) || defined(__AARCH64EB__)
4448 # Return 1 if this is an AArch64 target supporting SVE.
4449 proc check_effective_target_aarch64_sve { } {
4450 if { ![istarget aarch64*-*-*] } {
4453 return [check_no_compiler_messages aarch64_sve assembly {
4454 #if !defined (__ARM_FEATURE_SVE)
4460 # Return 1 if this is an AArch64 target supporting SVE2.
4461 proc check_effective_target_aarch64_sve2 { } {
4462 if { ![istarget aarch64*-*-*] } {
4465 return [check_no_compiler_messages aarch64_sve2 assembly {
4466 #if !defined (__ARM_FEATURE_SVE2)
4472 # Return 1 if this is an AArch64 target only supporting SVE (not SVE2).
4473 proc check_effective_target_aarch64_sve1_only { } {
4474 return [expr { [check_effective_target_aarch64_sve]
4475 && ![check_effective_target_aarch64_sve2] }]
4478 # Return the size in bits of an SVE vector, or 0 if the size is variable.
4479 proc aarch64_sve_bits { } {
4480 return [check_cached_effective_target aarch64_sve_bits {
4483 set src dummy[pid].c
4484 set f [open $src "w"]
4485 puts $f "int bits = __ARM_FEATURE_SVE_BITS;"
4487 set output [${tool}_target_compile $src "" preprocess ""]
4490 regsub {.*bits = ([^;]*);.*} $output {\1} bits
4495 # Return 1 if this is an AArch64 target that generates instructions for SME.
4496 proc check_effective_target_aarch64_sme { } {
4497 if { ![istarget aarch64*-*-*] } {
4500 return [check_no_compiler_messages aarch64_sme assembly {
4501 #if !defined (__ARM_FEATURE_SME)
4507 # Return 1 if this is an AArch64 target that generates instructions for SME.
4508 proc check_effective_target_aarch64_sme2 { } {
4509 if { ![istarget aarch64*-*-*] } {
4512 return [check_no_compiler_messages aarch64_sme2 assembly {
4513 #if !defined (__ARM_FEATURE_SME2)
4519 # Return 1 if this is a compiler supporting ARC atomic operations
4520 proc check_effective_target_arc_atomic { } {
4521 return [check_no_compiler_messages arc_atomic assembly {
4522 #if !defined(__ARC_ATOMIC__)
4528 # Return 1 if this is an arm target using 32-bit instructions
4529 proc check_effective_target_arm32 { } {
4530 if { ![istarget arm*-*-*] } {
4534 return [check_no_compiler_messages arm32 assembly {
4535 #if !defined(__arm__) || (defined(__thumb__) && !defined(__thumb2__))
4536 #error !__arm || __thumb__ && !__thumb2__
4541 # Return 1 if this is an arm target not using Thumb
4542 proc check_effective_target_arm_nothumb { } {
4543 if { ![istarget arm*-*-*] } {
4547 return [check_no_compiler_messages arm_nothumb assembly {
4548 #if !defined(__arm__) || (defined(__thumb__) || defined(__thumb2__))
4549 #error !__arm__ || __thumb || __thumb2__
4554 # Return 1 if this is a little-endian ARM target
4555 proc check_effective_target_arm_little_endian { } {
4556 if { ![istarget arm*-*-*] } {
4560 return [check_no_compiler_messages arm_little_endian assembly {
4561 #if !defined(__arm__) || !defined(__ARMEL__)
4562 #error !__arm__ || !__ARMEL__
4567 # Return 1 if this is an ARM target that only supports aligned vector accesses
4568 proc check_effective_target_arm_vect_no_misalign { } {
4569 if { ![istarget arm*-*-*] } {
4573 return [check_no_compiler_messages arm_vect_no_misalign assembly {
4574 #if !defined(__arm__) \
4575 || (defined(__ARM_FEATURE_UNALIGNED) \
4576 && defined(__ARMEL__))
4577 #error !__arm__ || (__ARMEL__ && __ARM_FEATURE_UNALIGNED)
4583 # Return 1 if this is an ARM target supporting -mfloat-abi=soft. Some
4584 # multilibs may be incompatible with this option.
4586 proc check_effective_target_arm_soft_ok { } {
4587 return [check_no_compiler_messages arm_soft_ok object {
4590 int main (void) { return 0; }
4591 } "-mfloat-abi=soft"]
4594 # Return 1 if this is an ARM target supporting -mfloat-abi=soft even
4595 # for linking. Some multilibs may be incompatible with this option,
4596 # and some linkers may reject incompatible options.
4598 proc check_effective_target_arm_soft_ok_link { } {
4599 return [check_no_compiler_messages arm_soft_ok_link executable {
4602 int main (void) { return 0; }
4603 } "-mfloat-abi=soft"]
4606 # Return 1 if this is an ARM target supporting -mfpu=vfp with an
4609 proc check_effective_target_arm_vfp_ok_nocache { } {
4610 global et_arm_vfp_flags
4611 set et_arm_vfp_flags ""
4612 if { [check_effective_target_arm32] } {
4613 foreach flags {"-mfpu=vfp" "-mfpu=vfp -mfloat-abi=softfp" "-mfpu=vfp -mfloat-abi=hard"} {
4614 if { [check_no_compiler_messages_nocache arm_vfp_ok object {
4616 #error __ARM_FP not defined
4619 set et_arm_vfp_flags $flags
4628 proc check_effective_target_arm_vfp_ok { } {
4629 return [check_cached_effective_target arm_vfp_ok \
4630 check_effective_target_arm_vfp_ok_nocache]
4633 # Add the options needed to compile code with -mfpu=vfp. We need either
4634 # -mfloat-abi=softfp or -mfloat-abi=hard, but if one is already
4635 # specified by the multilib, use it.
4637 proc add_options_for_arm_vfp { flags } {
4638 if { ! [check_effective_target_arm_vfp_ok] } {
4641 global et_arm_vfp_flags
4642 return "$flags $et_arm_vfp_flags"
4645 # Return 1 if this is an ARM target supporting -mfpu=vfp3
4646 # -mfloat-abi=softfp.
4648 proc check_effective_target_arm_vfp3_ok { } {
4649 if { [check_effective_target_arm32] } {
4650 return [check_no_compiler_messages arm_vfp3_ok object {
4652 } "-mfpu=vfp3 -mfloat-abi=softfp"]
4658 # Return 1 if this is an ARM target supporting -mfpu=fp-armv8
4659 # -mfloat-abi=softfp.
4660 proc check_effective_target_arm_v8_vfp_ok {} {
4661 if { [check_effective_target_arm32] } {
4662 return [check_no_compiler_messages arm_v8_vfp_ok object {
4665 __asm__ volatile ("vrinta.f32.f32 s0, s0");
4668 } "-mfpu=fp-armv8 -mfloat-abi=softfp"]
4674 # Return 1 if this is an ARM target supporting -mfpu=vfp
4675 # -mfloat-abi=hard. Some multilibs may be incompatible with these
4678 proc check_effective_target_arm_hard_vfp_ok { } {
4679 if { [check_effective_target_arm32]
4680 && ! [check-flags [list "" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" }]] } {
4681 return [check_no_compiler_messages arm_hard_vfp_ok executable {
4682 int main() { return 0;}
4683 } "-mfpu=vfp -mfloat-abi=hard"]
4689 # Return 1 if this is an ARM target defining __ARM_FP. We may need
4690 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4691 # incompatible with these options. Also set et_arm_fp_flags to the
4692 # best options to add.
4694 proc check_effective_target_arm_fp_ok_nocache { } {
4695 global et_arm_fp_flags
4696 set et_arm_fp_flags ""
4697 if { [check_effective_target_arm32] } {
4698 foreach flags {"" "-mfloat-abi=softfp" "-mfloat-abi=hard"} {
4699 if { [check_no_compiler_messages_nocache arm_fp_ok object {
4701 #error __ARM_FP not defined
4704 set et_arm_fp_flags $flags
4713 proc check_effective_target_arm_fp_ok { } {
4714 return [check_cached_effective_target arm_fp_ok \
4715 check_effective_target_arm_fp_ok_nocache]
4718 # Add the options needed to define __ARM_FP. We need either
4719 # -mfloat-abi=softfp or -mfloat-abi=hard, but if one is already
4720 # specified by the multilib, use it.
4722 proc add_options_for_arm_fp { flags } {
4723 if { ! [check_effective_target_arm_fp_ok] } {
4726 global et_arm_fp_flags
4727 return "$flags $et_arm_fp_flags"
4730 # Return 1 if this is an ARM target defining __ARM_FP with
4731 # double-precision support. We may need -mfloat-abi=softfp or
4732 # equivalent options. Some multilibs may be incompatible with these
4733 # options. Also set et_arm_fp_dp_flags to the best options to add.
4735 proc check_effective_target_arm_fp_dp_ok_nocache { } {
4736 global et_arm_fp_dp_flags
4737 set et_arm_fp_dp_flags ""
4738 if { [check_effective_target_arm32] } {
4739 foreach flags {"" "-mfloat-abi=softfp" "-mfloat-abi=hard"} {
4740 if { [check_no_compiler_messages_nocache arm_fp_dp_ok object {
4742 #error __ARM_FP not defined
4744 #if ((__ARM_FP & 8) == 0)
4745 #error __ARM_FP indicates that double-precision is not supported
4748 set et_arm_fp_dp_flags $flags
4757 proc check_effective_target_arm_fp_dp_ok { } {
4758 return [check_cached_effective_target arm_fp_dp_ok \
4759 check_effective_target_arm_fp_dp_ok_nocache]
4762 # Add the options needed to define __ARM_FP with double-precision
4763 # support. We need either -mfloat-abi=softfp or -mfloat-abi=hard, but
4764 # if one is already specified by the multilib, use it.
4766 proc add_options_for_arm_fp_dp { flags } {
4767 if { ! [check_effective_target_arm_fp_dp_ok] } {
4770 global et_arm_fp_dp_flags
4771 return "$flags $et_arm_fp_dp_flags"
4774 # Return 1 if this is an ARM target that supports DSP multiply with
4775 # current multilib flags.
4777 proc check_effective_target_arm_dsp { } {
4778 return [check_no_compiler_messages arm_dsp assembly {
4779 #ifndef __ARM_FEATURE_DSP
4782 #include <arm_acle.h>
4787 # Return 1 if this is an ARM target that supports unaligned word/halfword
4788 # load/store instructions.
4790 proc check_effective_target_arm_unaligned { } {
4791 return [check_no_compiler_messages arm_unaligned assembly {
4792 #ifndef __ARM_FEATURE_UNALIGNED
4793 #error no unaligned support
4799 # Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
4800 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4801 # incompatible with these options. Also set et_arm_crypto_flags to the
4802 # best options to add.
4804 proc check_effective_target_arm_crypto_ok_nocache { } {
4805 global et_arm_crypto_flags
4806 set et_arm_crypto_flags ""
4807 if { [check_effective_target_arm_v8_neon_ok] } {
4808 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=crypto-neon-fp-armv8" "-mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp"} {
4809 if { [check_no_compiler_messages_nocache arm_crypto_ok object {
4810 #include "arm_neon.h"
4812 foo (uint8x16_t a, uint8x16_t b)
4814 return vaeseq_u8 (a, b);
4817 set et_arm_crypto_flags $flags
4826 # Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
4828 proc check_effective_target_arm_crypto_ok { } {
4829 return [check_cached_effective_target arm_crypto_ok \
4830 check_effective_target_arm_crypto_ok_nocache]
4833 # Add options for crypto extensions.
4834 proc add_options_for_arm_crypto { flags } {
4835 if { ! [check_effective_target_arm_crypto_ok] } {
4838 global et_arm_crypto_flags
4839 return "$flags $et_arm_crypto_flags"
4842 # Add the options needed for NEON. We need either -mfloat-abi=softfp
4843 # or -mfloat-abi=hard, but if one is already specified by the
4844 # multilib, use it. Similarly, if a -mfpu option already enables
4845 # NEON, do not add -mfpu=neon.
4847 proc add_options_for_arm_neon { flags } {
4848 if { ! [check_effective_target_arm_neon_ok] } {
4851 global et_arm_neon_flags
4852 return "$flags $et_arm_neon_flags"
4855 proc add_options_for_arm_v8_vfp { flags } {
4856 if { ! [check_effective_target_arm_v8_vfp_ok] } {
4859 return "$flags -mfpu=fp-armv8 -mfloat-abi=softfp"
4862 proc add_options_for_arm_v8_neon { flags } {
4863 if { ! [check_effective_target_arm_v8_neon_ok] } {
4866 global et_arm_v8_neon_flags
4867 return "$flags $et_arm_v8_neon_flags -march=armv8-a"
4870 # Add the options needed for ARMv8.1 Adv.SIMD. Also adds the ARMv8 NEON
4871 # options for AArch64 and for ARM.
4873 proc add_options_for_arm_v8_1a_neon { flags } {
4874 if { ! [check_effective_target_arm_v8_1a_neon_ok] } {
4877 global et_arm_v8_1a_neon_flags
4878 return "$flags $et_arm_v8_1a_neon_flags"
4881 # Add the options needed for ARMv8.2 with the scalar FP16 extension.
4882 # Also adds the ARMv8 FP options for ARM and for AArch64.
4884 proc add_options_for_arm_v8_2a_fp16_scalar { flags } {
4885 if { ! [check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
4888 global et_arm_v8_2a_fp16_scalar_flags
4889 return "$flags $et_arm_v8_2a_fp16_scalar_flags"
4892 # Add the options needed for ARMv8.2 with the FP16 extension. Also adds
4893 # the ARMv8 NEON options for ARM and for AArch64.
4895 proc add_options_for_arm_v8_2a_fp16_neon { flags } {
4896 if { ! [check_effective_target_arm_v8_2a_fp16_neon_ok] } {
4899 global et_arm_v8_2a_fp16_neon_flags
4900 return "$flags $et_arm_v8_2a_fp16_neon_flags"
4903 proc add_options_for_arm_crc { flags } {
4904 if { ! [check_effective_target_arm_crc_ok] } {
4907 global et_arm_crc_flags
4908 return "$flags $et_arm_crc_flags"
4911 # Add the options needed for NEON. We need either -mfloat-abi=softfp
4912 # or -mfloat-abi=hard, but if one is already specified by the
4913 # multilib, use it. Similarly, if a -mfpu option already enables
4914 # NEON, do not add -mfpu=neon.
4916 proc add_options_for_arm_neonv2 { flags } {
4917 if { ! [check_effective_target_arm_neonv2_ok] } {
4920 global et_arm_neonv2_flags
4921 return "$flags $et_arm_neonv2_flags"
4924 # Add the options needed for vfp3.
4925 proc add_options_for_arm_vfp3 { flags } {
4926 if { ! [check_effective_target_arm_vfp3_ok] } {
4929 return "$flags -mfpu=vfp3 -mfloat-abi=softfp"
4932 # Return 1 if this is an ARM target supporting -mfpu=neon
4933 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4934 # incompatible with these options. Also set et_arm_neon_flags to the
4935 # best options to add.
4937 proc check_effective_target_arm_neon_ok_nocache { } {
4938 global et_arm_neon_flags
4939 set et_arm_neon_flags ""
4940 if { [check_effective_target_arm32] } {
4941 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp" "-mfpu=neon -mfloat-abi=softfp -march=armv7-a" "-mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard -march=armv7-a"} {
4942 if { [check_no_compiler_messages_nocache arm_neon_ok object {
4943 #include <arm_neon.h>
4945 #ifndef __ARM_NEON__
4948 /* Avoid the case where a test adds -mfpu=neon, but the toolchain is
4949 configured for -mcpu=arm926ej-s, for example. */
4950 #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M
'
4951 #error Architecture does not support NEON.
4954 set et_arm_neon_flags $flags
4963 proc check_effective_target_arm_neon_ok { } {
4964 return [check_cached_effective_target arm_neon_ok \
4965 check_effective_target_arm_neon_ok_nocache]
4969 # Return 1 if this is an ARM target supporting the SIMD32 intrinsics
4970 # from arm_acle.h. Some multilibs may be incompatible with these options.
4971 # Also set et_arm_simd32_flags to the best options to add.
4972 # arm_acle.h includes stdint.h which can cause trouble with incompatible
4973 # -mfloat-abi= options.
4975 proc check_effective_target_arm_simd32_ok_nocache { } {
4976 global et_arm_simd32_flags
4977 set et_arm_simd32_flags ""
4978 foreach flags {"" "-march=armv6" "-march=armv6 -mfloat-abi=softfp" "-march=armv6 -mfloat-abi=hard"} {
4979 if { [check_no_compiler_messages_nocache arm_simd32_ok object {
4980 #include <arm_acle.h>
4982 #ifndef __ARM_FEATURE_SIMD32
4986 set et_arm_simd32_flags $flags
4994 proc check_effective_target_arm_simd32_ok { } {
4995 return [check_cached_effective_target arm_simd32_ok \
4996 check_effective_target_arm_simd32_ok_nocache]
4999 proc add_options_for_arm_simd32 { flags } {
5000 if { ! [check_effective_target_arm_simd32_ok] } {
5003 global et_arm_simd32_flags
5004 return "$flags $et_arm_simd32_flags"
5007 # Return 1 if this is an ARM target supporting the __ssat and __usat
5008 # saturation intrinsics from arm_acle.h. Some multilibs may be
5009 # incompatible with these options. Also set et_arm_sat_flags to the
5010 # best options to add. arm_acle.h includes stdint.h which can cause
5011 # trouble with incompatible -mfloat-abi= options.
5013 proc check_effective_target_arm_sat_ok_nocache { } {
5014 global et_arm_sat_flags
5015 set et_arm_sat_flags ""
5016 foreach flags {"" "-march=armv6" "-march=armv6 -mfloat-abi=softfp" "-march=armv6 -mfloat-abi=hard -mfpu=vfp"} {
5017 if { [check_no_compiler_messages_nocache et_arm_sat_flags object {
5018 #include <arm_acle.h>
5020 #ifndef __ARM_FEATURE_SAT
5024 set et_arm_sat_flags $flags
5032 proc check_effective_target_arm_sat_ok { } {
5033 return [check_cached_effective_target et_arm_sat_flags \
5034 check_effective_target_arm_sat_ok_nocache]
5037 proc add_options_for_arm_sat { flags } {
5038 if { ! [check_effective_target_arm_sat_ok] } {
5041 global et_arm_sat_flags
5042 return "$flags $et_arm_sat_flags"
5045 # Return 1 if this is an ARM target supporting the DSP intrinsics from
5046 # arm_acle.h. Some multilibs may be incompatible with these options.
5047 # Also set et_arm_dsp_flags to the best options to add.
5048 # arm_acle.h includes stdint.h which can cause trouble with incompatible
5049 # -mfloat-abi= options.
5050 # check_effective_target_arm_dsp also exists, which checks the current
5051 # multilib, without trying other options.
5053 proc check_effective_target_arm_dsp_ok_nocache { } {
5054 global et_arm_dsp_flags
5055 set et_arm_dsp_flags ""
5056 foreach flags {"" "-march=armv5te" "-march=armv5te -mfloat-abi=softfp" "-march=armv5te -mfloat-abi=hard"} {
5057 if { [check_no_compiler_messages_nocache et_arm_dsp_ok object {
5058 #include <arm_acle.h>
5060 #ifndef __ARM_FEATURE_DSP
5064 set et_arm_dsp_flags $flags
5072 proc check_effective_target_arm_dsp_ok { } {
5073 return [check_cached_effective_target et_arm_dsp_flags \
5074 check_effective_target_arm_dsp_ok_nocache]
5077 proc add_options_for_arm_dsp { flags } {
5078 if { ! [check_effective_target_arm_dsp_ok] } {
5081 global et_arm_dsp_flags
5082 return "$flags $et_arm_dsp_flags"
5085 # Return 1 if this is an ARM target supporting -mfpu=neon without any
5086 # -mfloat-abi= option. Useful in tests where add_options is not
5087 # supported (such as lto tests).
5089 proc check_effective_target_arm_neon_ok_no_float_abi_nocache { } {
5090 if { [check_effective_target_arm32] } {
5091 foreach flags {"-mfpu=neon"} {
5092 if { [check_no_compiler_messages_nocache arm_neon_ok_no_float_abi object {
5093 #include <arm_neon.h>
5095 #ifndef __ARM_NEON__
5098 /* Avoid the case where a test adds -mfpu=neon, but the toolchain is
5099 configured for -mcpu=arm926ej-s, for example. */
5100 #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M
'
5101 #error Architecture does not support NEON.
5112 proc check_effective_target_arm_neon_ok_no_float_abi { } {
5113 return [check_cached_effective_target arm_neon_ok_no_float_abi \
5114 check_effective_target_arm_neon_ok_no_float_abi_nocache]
5117 proc check_effective_target_arm_crc_ok_nocache { } {
5118 global et_arm_crc_flags
5119 set et_arm_crc_flags "-march=armv8-a+crc"
5120 return [check_no_compiler_messages_nocache arm_crc_ok object {
5121 #if !defined (__ARM_FEATURE_CRC32)
5124 #include <arm_acle.h>
5125 } "$et_arm_crc_flags"]
5128 proc check_effective_target_arm_crc_ok { } {
5129 return [check_cached_effective_target arm_crc_ok \
5130 check_effective_target_arm_crc_ok_nocache]
5133 # Return 1 if this is an ARM target supporting -mfpu=neon-fp16
5134 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5135 # incompatible with these options. Also set et_arm_neon_fp16_flags to
5136 # the best options to add.
5138 proc check_effective_target_arm_neon_fp16_ok_nocache { } {
5139 global et_arm_neon_fp16_flags
5140 global et_arm_neon_flags
5141 set et_arm_neon_fp16_flags ""
5142 if { [check_effective_target_arm32]
5143 && [check_effective_target_arm_neon_ok] } {
5144 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5145 "-mfpu=neon-fp16 -mfloat-abi=softfp"
5146 "-mfp16-format=ieee"
5147 "-mfloat-abi=softfp -mfp16-format=ieee"
5148 "-mfpu=neon-fp16 -mfp16-format=ieee"
5149 "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
5150 if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object {
5151 #include "arm_neon.h"
5153 foo (float32x4_t arg)
5155 return vcvt_f16_f32 (arg);
5157 } "$et_arm_neon_flags $flags"] } {
5158 set et_arm_neon_fp16_flags [concat $et_arm_neon_flags $flags]
5167 proc check_effective_target_arm_neon_fp16_ok { } {
5168 return [check_cached_effective_target arm_neon_fp16_ok \
5169 check_effective_target_arm_neon_fp16_ok_nocache]
5172 # Return 1 if this is an ARM target supporting -mfpu=neon-fp16
5173 # and -mfloat-abi=softfp together. Some multilibs may be
5174 # incompatible with these options. Also set et_arm_neon_softfp_fp16_flags to
5175 # the best options to add.
5177 proc check_effective_target_arm_neon_softfp_fp16_ok_nocache { } {
5178 global et_arm_neon_softfp_fp16_flags
5179 global et_arm_neon_flags
5180 set et_arm_neon_softfp_fp16_flags ""
5181 if { [check_effective_target_arm32]
5182 && [check_effective_target_arm_neon_ok] } {
5183 foreach flags {"-mfpu=neon-fp16 -mfloat-abi=softfp"
5184 "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
5185 if { [check_no_compiler_messages_nocache arm_neon_softfp_fp16_ok object {
5186 #include "arm_neon.h"
5188 foo (float32x4_t arg)
5190 return vcvt_f16_f32 (arg);
5192 } "$et_arm_neon_flags $flags"] } {
5193 set et_arm_neon_softfp_fp16_flags [concat $et_arm_neon_flags $flags]
5202 proc check_effective_target_arm_neon_softfp_fp16_ok { } {
5203 return [check_cached_effective_target arm_neon_softfp_fp16_ok \
5204 check_effective_target_arm_neon_softfp_fp16_ok_nocache]
5209 proc check_effective_target_arm_neon_fp16_hw { } {
5210 if {! [check_effective_target_arm_neon_fp16_ok] } {
5213 global et_arm_neon_fp16_flags
5214 check_runtime arm_neon_fp16_hw {
5216 main (int argc, char **argv)
5218 asm ("vcvt.f32.f16 q1, d0");
5221 } $et_arm_neon_fp16_flags
5224 proc add_options_for_arm_neon_fp16 { flags } {
5225 if { ! [check_effective_target_arm_neon_fp16_ok] } {
5228 global et_arm_neon_fp16_flags
5229 return "$flags $et_arm_neon_fp16_flags"
5232 proc add_options_for_arm_neon_softfp_fp16 { flags } {
5233 if { ! [check_effective_target_arm_neon_softfp_fp16_ok] } {
5236 global et_arm_neon_softfp_fp16_flags
5237 return "$flags $et_arm_neon_softfp_fp16_flags"
5240 proc add_options_for_aarch64_sve { flags } {
5241 if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } {
5244 return "$flags -march=armv8.2-a+sve"
5247 # Return 1 if this is an ARM target supporting the FP16 alternative
5248 # format. Some multilibs may be incompatible with the options needed. Also
5249 # set et_arm_fp16_alternative_flags to the best options to add.
5251 proc check_effective_target_arm_fp16_alternative_ok_nocache { } {
5252 if { [istarget *-*-vxworks7*] } {
5253 # Not supported by the target system.
5256 global et_arm_fp16_alternative_flags
5257 set et_arm_fp16_alternative_flags ""
5258 if { [check_effective_target_arm32] } {
5259 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5260 "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
5261 if { [check_no_compiler_messages_nocache \
5262 arm_fp16_alternative_ok object {
5263 #if !defined (__ARM_FP16_FORMAT_ALTERNATIVE) || ! (__ARM_FP & 2)
5264 #error __ARM_FP16_FORMAT_ALTERNATIVE not defined
5266 } "$flags -mfp16-format=alternative"] } {
5267 set et_arm_fp16_alternative_flags "$flags -mfp16-format=alternative"
5276 proc check_effective_target_arm_fp16_alternative_ok { } {
5277 return [check_cached_effective_target arm_fp16_alternative_ok \
5278 check_effective_target_arm_fp16_alternative_ok_nocache]
5281 # Return 1 if this is an ARM target supports specifying the FP16 none
5282 # format. Some multilibs may be incompatible with the options needed.
5284 proc check_effective_target_arm_fp16_none_ok_nocache { } {
5285 if { [check_effective_target_arm32] } {
5286 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5287 "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
5288 if { [check_no_compiler_messages_nocache \
5289 arm_fp16_none_ok object {
5290 #if defined (__ARM_FP16_FORMAT_ALTERNATIVE)
5291 #error __ARM_FP16_FORMAT_ALTERNATIVE defined
5293 #if defined (__ARM_FP16_FORMAT_IEEE)
5294 #error __ARM_FP16_FORMAT_IEEE defined
5296 } "$flags -mfp16-format=none"] } {
5305 proc check_effective_target_arm_fp16_none_ok { } {
5306 return [check_cached_effective_target arm_fp16_none_ok \
5307 check_effective_target_arm_fp16_none_ok_nocache]
5310 # Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8
5311 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5312 # incompatible with these options. Also set et_arm_v8_neon_flags to the
5313 # best options to add.
5315 proc check_effective_target_arm_v8_neon_ok_nocache { } {
5316 global et_arm_v8_neon_flags
5317 set et_arm_v8_neon_flags ""
5318 if { [check_effective_target_arm32] } {
5319 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp-armv8" "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
5320 if { [check_no_compiler_messages_nocache arm_v8_neon_ok object {
5322 #error not armv8 or later
5324 #include "arm_neon.h"
5328 __asm__ volatile ("vrintn.f32 q0, q0");
5330 } "$flags -march=armv8-a"] } {
5331 set et_arm_v8_neon_flags $flags
5340 proc check_effective_target_arm_v8_neon_ok { } {
5341 return [check_cached_effective_target arm_v8_neon_ok \
5342 check_effective_target_arm_v8_neon_ok_nocache]
5345 # Return 1 if this is an ARM target supporting -mfpu=neon-vfpv4
5346 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5347 # incompatible with these options. Also set et_arm_neonv2_flags to the
5348 # best options to add.
5350 proc check_effective_target_arm_neonv2_ok_nocache { } {
5351 global et_arm_neonv2_flags
5352 global et_arm_neon_flags
5353 set et_arm_neonv2_flags ""
5354 if { [check_effective_target_arm32]
5355 && [check_effective_target_arm_neon_ok] } {
5356 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
5357 if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
5358 #include "arm_neon.h"
5360 foo (float32x2_t a, float32x2_t b, float32x2_t c)
5362 return vfma_f32 (a, b, c);
5364 } "$et_arm_neon_flags $flags"] } {
5365 set et_arm_neonv2_flags [concat $et_arm_neon_flags $flags]
5374 proc check_effective_target_arm_neonv2_ok { } {
5375 return [check_cached_effective_target arm_neonv2_ok \
5376 check_effective_target_arm_neonv2_ok_nocache]
5379 # Add the options needed for VFP FP16 support. We need either
5380 # -mfloat-abi=softfp or -mfloat-abi=hard. If one is already specified by
5381 # the multilib, use it.
5383 proc add_options_for_arm_fp16 { flags } {
5384 if { ! [check_effective_target_arm_fp16_ok] } {
5387 global et_arm_fp16_flags
5388 return "$flags $et_arm_fp16_flags"
5391 # Add the options needed to enable support for IEEE format
5392 # half-precision support. This is valid for ARM targets.
5394 proc add_options_for_arm_fp16_ieee { flags } {
5395 if { ! [check_effective_target_arm_fp16_ok] } {
5398 global et_arm_fp16_flags
5399 return "$flags $et_arm_fp16_flags -mfp16-format=ieee"
5402 # Add the options needed to enable support for ARM Alternative format
5403 # half-precision support. This is valid for ARM targets.
5405 proc add_options_for_arm_fp16_alternative { flags } {
5406 if { ! [check_effective_target_arm_fp16_alternative_ok] } {
5409 global et_arm_fp16_alternative_flags
5410 return "$flags $et_arm_fp16_alternative_flags"
5413 # Return 1 if this is an ARM target that can support a VFP fp16 variant.
5414 # Skip multilibs that are incompatible with these options and set
5415 # et_arm_fp16_flags to the best options to add. This test is valid for
5418 proc check_effective_target_arm_fp16_ok_nocache { } {
5419 global et_arm_fp16_flags
5420 set et_arm_fp16_flags ""
5421 if { ! [check_effective_target_arm32] } {
5425 [list "" { *-*-* } { "-mfpu=*" } \
5426 { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" \
5427 "-mfpu=*fpv[1-9][0-9]*" "-mfpu=*fp-armv8*" } ]] {
5428 # Multilib flags would override -mfpu.
5431 if [check-flags [list "" { *-*-* } { "-mfloat-abi=soft" } { "" } ]] {
5432 # Must generate floating-point instructions.
5435 if [check_effective_target_arm_hf_eabi] {
5436 # Use existing float-abi and force an fpu which supports fp16
5437 set et_arm_fp16_flags "-mfpu=vfpv4"
5440 if [check-flags [list "" { *-*-* } { "-mfpu=*" } { "" } ]] {
5441 # The existing -mfpu value is OK; use it, but add softfp.
5442 set et_arm_fp16_flags "-mfloat-abi=softfp"
5445 # Add -mfpu for a VFP fp16 variant since there is no preprocessor
5446 # macro to check for this support.
5447 set flags "-mfpu=vfpv4 -mfloat-abi=softfp"
5448 if { [check_no_compiler_messages_nocache arm_fp16_ok assembly {
5451 set et_arm_fp16_flags "$flags"
5458 proc check_effective_target_arm_fp16_ok { } {
5459 return [check_cached_effective_target arm_fp16_ok \
5460 check_effective_target_arm_fp16_ok_nocache]
5463 # Return 1 if the target supports executing VFP FP16 instructions, 0
5464 # otherwise. This test is valid for ARM only.
5466 proc check_effective_target_arm_fp16_hw { } {
5467 if {! [check_effective_target_arm_fp16_ok] } {
5470 global et_arm_fp16_flags
5471 check_runtime arm_fp16_hw {
5473 main (int argc, char **argv)
5477 asm ("vcvtb.f32.f16 %0, %1"
5478 : "=w" (r) : "w" (a)
5479 : /* No clobbers. */);
5480 return (r == 1.0) ? 0 : 1;
5482 } "$et_arm_fp16_flags -mfp16-format=ieee"
5485 # Creates a series of routines that return 1 if the given architecture
5486 # can be selected and a routine to give the flags to select that architecture
5487 # Note: Extra flags may be added to disable options from newer compilers
5488 # (Thumb in particular - but others may be added in the future).
5489 # Warning: Do not use check_effective_target_arm_arch_*_ok for architecture
5490 # extension (eg. ARMv8.1-A) since there is no macro defined for them. See
5491 # how only __ARM_ARCH_8A__ is checked for ARMv8.1-A.
5492 # Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
5493 # /* { dg-add-options arm_arch_v5t } */
5494 # /* { dg-require-effective-target arm_arch_v5t_multilib } */
5495 foreach { armfunc armflag armdefs } {
5496 v4 "-march=armv4 -marm" __ARM_ARCH_4__
5497 v4t "-march=armv4t -mfloat-abi=softfp" __ARM_ARCH_4T__
5498 v4t_arm "-march=armv4t -marm" "__ARM_ARCH_4T__ && !__thumb__"
5499 v4t_thumb "-march=armv4t -mthumb -mfloat-abi=softfp" "__ARM_ARCH_4T__ && __thumb__"
5500 v5t "-march=armv5t -mfloat-abi=softfp" __ARM_ARCH_5T__
5501 v5t_arm "-march=armv5t -marm" "__ARM_ARCH_5T__ && !__thumb__"
5502 v5t_thumb "-march=armv5t -mthumb -mfloat-abi=softfp" "__ARM_ARCH_5T__ && __thumb__"
5503 v5te "-march=armv5te+fp -mfloat-abi=softfp" __ARM_ARCH_5TE__
5504 v5te_arm "-march=armv5te+fp -marm" "__ARM_ARCH_5TE__ && !__thumb__"
5505 v5te_thumb "-march=armv5te+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_5TE__ && __thumb__"
5506 xscale_arm "-mcpu=xscale -mfloat-abi=soft -marm" "__XSCALE__ && !__thumb__"
5507 v6 "-march=armv6+fp -mfloat-abi=softfp" __ARM_ARCH_6__
5508 v6_arm "-march=armv6+fp -marm" "__ARM_ARCH_6__ && !__thumb__"
5509 v6_thumb "-march=armv6+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6__ && __thumb__"
5510 v6k "-march=armv6k+fp -mfloat-abi=softfp" __ARM_ARCH_6K__
5511 v6k_arm "-march=armv6k+fp -marm" "__ARM_ARCH_6K__ && !__thumb__"
5512 v6k_thumb "-march=armv6k+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6K__ && __thumb__"
5513 v6t2 "-march=armv6t2+fp" __ARM_ARCH_6T2__
5514 v6z "-march=armv6z+fp -mfloat-abi=softfp" __ARM_ARCH_6Z__
5515 v6z_arm "-march=armv6z+fp -marm" "__ARM_ARCH_6Z__ && !__thumb__"
5516 v6z_thumb "-march=armv6z+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6Z__ && __thumb__"
5517 v6m "-march=armv6-m -mthumb -mfloat-abi=soft" __ARM_ARCH_6M__
5518 v7a "-march=armv7-a+fp" __ARM_ARCH_7A__
5519 v7a_arm "-march=armv7-a+fp -marm" "__ARM_ARCH_7A__ && !__thumb__"
5520 v7a_neon "-march=armv7-a+simd -mfpu=auto -mfloat-abi=softfp" "__ARM_ARCH_7A__ && __ARM_NEON__"
5521 v7r "-march=armv7-r+fp" __ARM_ARCH_7R__
5522 v7m "-march=armv7-m -mthumb -mfloat-abi=soft" __ARM_ARCH_7M__
5523 v7em "-march=armv7e-m+fp -mthumb" __ARM_ARCH_7EM__
5524 v7ve "-march=armv7ve+fp -marm"
5525 "__ARM_ARCH_7A__ && __ARM_FEATURE_IDIV"
5526 v8a "-march=armv8-a+simd" __ARM_ARCH_8A__
5527 v8a_hard "-march=armv8-a+simd -mfpu=auto -mfloat-abi=hard" __ARM_ARCH_8A__
5528 v8_1a "-march=armv8.1-a+simd" __ARM_ARCH_8A__
5529 v8_2a "-march=armv8.2-a+simd" __ARM_ARCH_8A__
5530 v8r "-march=armv8-r+fp.sp" __ARM_ARCH_8R__
5531 v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
5532 __ARM_ARCH_8M_BASE__
5533 v8m_main "-march=armv8-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
5534 v8_1m_main "-march=armv8.1-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
5535 v8_1m_main_pacbti "-march=armv8.1-m.main+pacbti+fp -mthumb"
5536 "__ARM_ARCH_8M_MAIN__ && __ARM_FEATURE_BTI && __ARM_FEATURE_PAUTH"
5537 v9a "-march=armv9-a+simd" __ARM_ARCH_9A__ } {
5538 eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
5539 proc check_effective_target_arm_arch_FUNC_ok { } {
5540 return [check_no_compiler_messages arm_arch_FUNC_ok assembly {
5552 proc add_options_for_arm_arch_FUNC { flags } {
5553 return "$flags FLAG"
5556 proc check_effective_target_arm_arch_FUNC_link { } {
5557 return [check_no_compiler_messages arm_arch_FUNC_link executable {
5560 int main (void) { return 0; }
5561 } [add_options_for_arm_arch_FUNC ""]]
5564 proc check_effective_target_arm_arch_FUNC_multilib { } {
5565 return [check_runtime arm_arch_FUNC_multilib {
5571 } [add_options_for_arm_arch_FUNC ""]]
5576 # Return 1 if GCC was configured with --with-mode=
5577 proc check_effective_target_default_mode { } {
5579 return [check_configured_with "with-mode="]
5582 # Return 1 if this is an ARM target where -marm causes ARM to be
5585 proc check_effective_target_arm_arm_ok { } {
5586 return [check_no_compiler_messages arm_arm_ok assembly {
5587 #if !defined (__arm__) || defined (__thumb__) || defined (__thumb2__)
5588 #error !__arm__ || __thumb__ || __thumb2__
5594 # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
5597 proc check_effective_target_arm_thumb1_ok { } {
5598 return [check_no_compiler_messages arm_thumb1_ok assembly {
5599 #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
5600 #error !__arm__ || !__thumb__ || __thumb2__
5602 int foo (int i) { return i; }
5606 # Return 1 is this is an ARM target where -mthumb causes Thumb-2 to be
5609 proc check_effective_target_arm_thumb2_ok { } {
5610 return [check_no_compiler_messages arm_thumb2_ok assembly {
5611 #if !defined(__thumb2__)
5614 int foo (int i) { return i; }
5618 # Return 1 if this is an ARM target where Thumb-1 is used without options
5619 # added by the test.
5621 proc check_effective_target_arm_thumb1 { } {
5622 return [check_no_compiler_messages arm_thumb1 assembly {
5623 #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
5624 #error !__arm__ || !__thumb__ || __thumb2__
5630 # Return 1 if this is an ARM target where Thumb-2 is used without options
5631 # added by the test.
5633 proc check_effective_target_arm_thumb2 { } {
5634 return [check_no_compiler_messages arm_thumb2 assembly {
5635 #if !defined(__thumb2__)
5642 # Return 1 if this is an ARM target where conditional execution is available.
5644 proc check_effective_target_arm_cond_exec { } {
5645 return [check_no_compiler_messages arm_cond_exec assembly {
5646 #if defined(__arm__) && defined(__thumb__) && !defined(__thumb2__)
5653 # Return 1 if this is an ARM cortex-M profile cpu
5655 proc check_effective_target_arm_cortex_m { } {
5656 if { ![istarget arm*-*-*] } {
5659 return [check_no_compiler_messages arm_cortex_m assembly {
5660 #if defined(__ARM_ARCH_ISA_ARM)
5661 #error __ARM_ARCH_ISA_ARM is defined
5667 # Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
5668 # used and MOVT/MOVW instructions to be available.
5670 proc check_effective_target_arm_thumb1_movt_ok {} {
5671 if [check_effective_target_arm_thumb1_ok] {
5672 return [check_no_compiler_messages arm_movt object {
5676 asm ("movt r0, #42");
5684 # Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
5685 # used and CBZ and CBNZ instructions are available.
5687 proc check_effective_target_arm_thumb1_cbz_ok {} {
5688 if [check_effective_target_arm_thumb1_ok] {
5689 return [check_no_compiler_messages arm_cbz object {
5693 asm ("cbz r0, 2f\n2:");
5701 # Return 1 if this is an Arm target which supports the Armv6t2 extensions.
5702 # This can be either in Arm state or in Thumb state.
5704 proc check_effective_target_arm_arch_v6t2_hw {} {
5705 if [check_effective_target_arm_arch_v6t2_ok] {
5706 return [check_runtime arm_arch_v6t2 {
5710 asm ("bfc r0, #1, #2");
5713 } [add_options_for_arm_arch_v6t2 ""]]
5719 # Return 1 if this is an ARM target where ARMv8-M Security Extensions is
5722 proc check_effective_target_arm_cmse_ok {} {
5723 return [check_no_compiler_messages arm_cmse object {
5732 # Return 1 if the target supports executing CMSE instructions, 0
5733 # otherwise. Cache the result.
5735 proc check_effective_target_arm_cmse_hw { } {
5736 return [check_runtime arm_cmse_hw_available {
5740 asm ("ldr\t%0, =0xe000ed44\n" \
5742 "sg" : "=l" (id_pfr1));
5743 /* Exit with code 0 iff security extension is available. */
5744 return !(id_pfr1 & 0xf0);
5749 # Return 1 if the target supports executing MVE instructions, 0
5752 proc check_effective_target_arm_mve_hw {} {
5753 return [check_runtime arm_mve_hw_available {
5759 asm ("sqrshrl %Q1, %R1, #64, %2"
5761 : "0" (a), "r" (b));
5764 } [add_options_for_arm_v8_1m_mve_fp ""]]
5767 # Return 1 if this is an ARM target where ARMv8-M Security Extensions with
5768 # clearing instructions (clrm, vscclrm, vstr/vldr with FPCXT) is available.
5770 proc check_effective_target_arm_cmse_clear_ok {} {
5771 return [check_no_compiler_messages arm_cmse_clear object {
5775 asm ("clrm {r1, r2}");
5780 # Return 1 if this is an ARM target supporting
5781 # -mbranch-protection=standard, 0 otherwise.
5783 proc check_effective_target_mbranch_protection_ok {} {
5785 return [check_no_compiler_messages mbranch_protection_ok object {
5786 int main (void) { return 0; }
5787 } "-mbranch-protection=standard"]
5790 # Return 1 if the target supports executing PACBTI instructions, 0
5793 proc check_effective_target_arm_pacbti_hw {} {
5794 return [check_runtime arm_pacbti_hw_available {
5795 __attribute__ ((naked)) int
5798 asm ("pac r12, lr, sp");
5800 asm ("autg r12, lr, sp");
5803 } "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard -mthumb -mfloat-abi=hard"]
5806 # Return 1 if this compilation turns on string_ops_prefer_neon on.
5808 proc check_effective_target_arm_tune_string_ops_prefer_neon { } {
5809 return [check_no_messages_and_pattern arm_tune_string_ops_prefer_neon "@string_ops_prefer_neon:\t1" assembly {
5810 int foo (void) { return 0; }
5811 } "-O2 -mprint-tune-info" ]
5814 # Return 1 if the target supports executing NEON instructions, 0
5815 # otherwise. Cache the result.
5817 proc check_effective_target_arm_neon_hw { } {
5818 return [check_runtime arm_neon_hw_available {
5822 long long a = 0, b = 1;
5823 asm ("vorr %P0, %P1, %P2"
5825 : "0" (a), "w" (b));
5828 } [add_options_for_arm_neon ""]]
5831 # Return true if this is an AArch64 target that can run SVE code.
5833 proc check_effective_target_aarch64_sve_hw { } {
5834 if { ![istarget aarch64*-*-*] } {
5837 return [check_runtime aarch64_sve_hw_available {
5841 asm volatile ("ptrue p0.b");
5844 } [add_options_for_aarch64_sve ""]]
5847 # Return true if this is an AArch64 target that can run SVE2 code.
5849 proc check_effective_target_aarch64_sve2_hw { } {
5850 if { ![istarget aarch64*-*-*] } {
5853 return [check_runtime aarch64_sve2_hw_available {
5857 asm volatile ("addp z0.b, p0/m, z0.b, z1.b");
5863 # Return true if this is an AArch64 target that can run SVE code and
5864 # if its SVE vectors have exactly BITS bits.
5866 proc aarch64_sve_hw_bits { bits } {
5867 if { ![check_effective_target_aarch64_sve_hw] } {
5870 return [check_runtime aarch64_sve${bits}_hw [subst {
5875 asm volatile ("cntd %0" : "=r" (res));
5876 if (res * 64 != $bits)
5880 }] [add_options_for_aarch64_sve ""]]
5883 # Return true if this is an AArch64 target that can run SVE code and
5884 # if its SVE vectors have exactly 256 bits.
5886 foreach N { 128 256 512 1024 2048 } {
5887 eval [string map [list N $N] {
5888 proc check_effective_target_aarch64_sveN_hw { } {
5889 return [aarch64_sve_hw_bits N]
5894 proc check_effective_target_arm_neonv2_hw { } {
5895 return [check_runtime arm_neon_hwv2_available {
5896 #include "arm_neon.h"
5900 float32x2_t a, b, c;
5901 asm ("vfma.f32 %P0, %P1, %P2"
5903 : "w" (b), "w" (c));
5906 } [add_options_for_arm_neonv2 ""]]
5909 # ID_AA64PFR1_EL1.BT using bits[3:0] == 1 implies BTI implimented.
5910 proc check_effective_target_aarch64_bti_hw { } {
5911 if { ![istarget aarch64*-*-*] } {
5914 return [check_runtime aarch64_bti_hw_available {
5919 asm volatile ("mrs %0, id_aa64pfr1_el1" : "=r" (a));
5920 return !((a & 0xf) == 1);
5925 # Return 1 if the target supports executing the armv8.3-a FJCVTZS
5927 proc check_effective_target_aarch64_fjcvtzs_hw { } {
5928 if { ![istarget aarch64*-*-*] } {
5931 return [check_runtime aarch64_fjcvtzs_hw_available {
5937 asm volatile ("fjcvtzs %w0, %d1"
5940 : /* No clobbers. */);
5943 } "-march=armv8.3-a" ]
5946 # Return 1 if GCC was configured with --enable-standard-branch-protection
5947 proc check_effective_target_default_branch_protection { } {
5948 return [check_configured_with "enable-standard-branch-protection"]
5951 # Return 1 if this is an ARM target supporting -mfloat-abi=softfp.
5953 proc check_effective_target_arm_softfp_ok { } {
5954 return [check_no_compiler_messages arm_softfp_ok object {
5957 int main (void) { return 0; }
5958 } "-mfloat-abi=softfp"]
5961 # Return 1 if this is an ARM target supporting -mfloat-abi=hard.
5963 proc check_effective_target_arm_hard_ok { } {
5964 return [check_no_compiler_messages arm_hard_ok object {
5967 int main (void) { return 0; }
5968 } "-mfloat-abi=hard"]
5971 # Return 1 if this is an ARM target supporting MVE.
5972 proc check_effective_target_arm_mve { } {
5973 if { ![istarget arm*-*-*] } {
5976 return [check_no_compiler_messages arm_mve assembly {
5977 #if !defined (__ARM_FEATURE_MVE)
5983 # Return 1 if the target supports ARMv8.1-M MVE with floating point
5984 # instructions, 0 otherwise. The test is valid for ARM.
5985 # Record the command line options needed.
5987 proc check_effective_target_arm_v8_1m_mve_fp_ok_nocache { } {
5988 global et_arm_v8_1m_mve_fp_flags
5989 set et_arm_v8_1m_mve_fp_flags ""
5991 if { ![istarget arm*-*-*] } {
5995 # Iterate through sets of options to find the compiler flags that
5996 # need to be added to the -march option.
5997 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve.fp" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve.fp"} {
5998 if { [check_no_compiler_messages_nocache \
5999 arm_v8_1m_mve_fp_ok object {
6000 #include <arm_mve.h>
6001 #if !(__ARM_FEATURE_MVE & 2)
6002 #error "__ARM_FEATURE_MVE for floating point not defined"
6004 #if __ARM_BIG_ENDIAN
6005 #error "MVE intrinsics are not supported in Big-Endian mode."
6007 } "$flags -mthumb"] } {
6008 set et_arm_v8_1m_mve_fp_flags "$flags -mthumb --save-temps"
6016 proc check_effective_target_arm_v8_1m_mve_fp_ok { } {
6017 return [check_cached_effective_target arm_v8_1m_mve_fp_ok \
6018 check_effective_target_arm_v8_1m_mve_fp_ok_nocache]
6021 proc add_options_for_arm_v8_1m_mve_fp { flags } {
6022 if { ! [check_effective_target_arm_v8_1m_mve_fp_ok] } {
6025 global et_arm_v8_1m_mve_fp_flags
6026 return "$flags $et_arm_v8_1m_mve_fp_flags"
6029 # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
6030 # otherwise. The test is valid for AArch64 and ARM. Record the command
6031 # line options needed.
6033 proc check_effective_target_arm_v8_1a_neon_ok_nocache { } {
6034 global et_arm_v8_1a_neon_flags
6035 set et_arm_v8_1a_neon_flags ""
6037 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6041 # Iterate through sets of options to find the compiler flags that
6042 # need to be added to the -march option. Start with the empty set
6043 # since AArch64 only needs the -march setting.
6044 foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
6045 "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
6046 foreach arches { "-march=armv8-a+rdma" "-march=armv8.1-a" } {
6047 if { [check_no_compiler_messages_nocache arm_v8_1a_neon_ok object {
6048 #if !defined (__ARM_FEATURE_QRDMX)
6049 #error "__ARM_FEATURE_QRDMX not defined"
6051 } "$flags $arches"] } {
6052 set et_arm_v8_1a_neon_flags "$flags $arches"
6061 proc check_effective_target_arm_v8_1a_neon_ok { } {
6062 return [check_cached_effective_target arm_v8_1a_neon_ok \
6063 check_effective_target_arm_v8_1a_neon_ok_nocache]
6066 # Return 1 if the target supports ARMv8.2 scalar FP16 arithmetic
6067 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6068 # Record the command line options needed.
6070 proc check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache { } {
6071 global et_arm_v8_2a_fp16_scalar_flags
6072 set et_arm_v8_2a_fp16_scalar_flags ""
6074 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6078 # Iterate through sets of options to find the compiler flags that
6079 # need to be added to the -march option.
6080 foreach flags {"" "-mfpu=fp-armv8" "-mfloat-abi=softfp" \
6081 "-mfpu=fp-armv8 -mfloat-abi=softfp"} {
6082 if { [check_no_compiler_messages_nocache \
6083 arm_v8_2a_fp16_scalar_ok object {
6084 #if !defined (__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
6085 #error "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC not defined"
6087 } "$flags -march=armv8.2-a+fp16"] } {
6088 set et_arm_v8_2a_fp16_scalar_flags "$flags -march=armv8.2-a+fp16"
6096 proc check_effective_target_arm_v8_2a_fp16_scalar_ok { } {
6097 return [check_cached_effective_target arm_v8_2a_fp16_scalar_ok \
6098 check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache]
6101 # Return 1 if the target supports ARMv8.2 Adv.SIMD FP16 arithmetic
6102 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6103 # Record the command line options needed.
6105 proc check_effective_target_arm_v8_2a_fp16_neon_ok_nocache { } {
6106 global et_arm_v8_2a_fp16_neon_flags
6107 set et_arm_v8_2a_fp16_neon_flags ""
6109 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6113 # Iterate through sets of options to find the compiler flags that
6114 # need to be added to the -march option.
6115 foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
6116 "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
6117 if { [check_no_compiler_messages_nocache \
6118 arm_v8_2a_fp16_neon_ok object {
6119 #if !defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
6120 #error "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC not defined"
6122 } "$flags -march=armv8.2-a+fp16"] } {
6123 set et_arm_v8_2a_fp16_neon_flags "$flags -march=armv8.2-a+fp16"
6131 proc check_effective_target_arm_v8_2a_fp16_neon_ok { } {
6132 return [check_cached_effective_target arm_v8_2a_fp16_neon_ok \
6133 check_effective_target_arm_v8_2a_fp16_neon_ok_nocache]
6136 # Return 1 if the target supports ARMv8.2 Adv.SIMD Dot Product
6137 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6138 # Record the command line options needed.
6140 proc check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache { } {
6141 global et_arm_v8_2a_dotprod_neon_flags
6142 set et_arm_v8_2a_dotprod_neon_flags ""
6144 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6148 # Iterate through sets of options to find the compiler flags that
6149 # need to be added to the -march option.
6150 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8"} {
6151 if { [check_no_compiler_messages_nocache \
6152 arm_v8_2a_dotprod_neon_ok object {
6154 #if !defined (__ARM_FEATURE_DOTPROD)
6155 #error "__ARM_FEATURE_DOTPROD not defined"
6157 } "$flags -march=armv8.2-a+dotprod"] } {
6158 set et_arm_v8_2a_dotprod_neon_flags "$flags -march=armv8.2-a+dotprod"
6166 # Return 1 if the target supports ARMv8.1-M MVE
6167 # instructions, 0 otherwise. The test is valid for ARM.
6168 # Record the command line options needed.
6170 proc check_effective_target_arm_v8_1m_mve_ok_nocache { } {
6171 global et_arm_v8_1m_mve_flags
6172 set et_arm_v8_1m_mve_flags ""
6174 if { ![istarget arm*-*-*] } {
6178 # Iterate through sets of options to find the compiler flags that
6179 # need to be added to the -march option.
6180 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve"} {
6181 if { [check_no_compiler_messages_nocache \
6182 arm_v8_1m_mve_ok object {
6183 #if !defined (__ARM_FEATURE_MVE)
6184 #error "__ARM_FEATURE_MVE not defined"
6186 #if __ARM_BIG_ENDIAN
6187 #error "MVE intrinsics are not supported in Big-Endian mode."
6189 #include <arm_mve.h>
6190 } "$flags -mthumb"] } {
6191 set et_arm_v8_1m_mve_flags "$flags -mthumb --save-temps"
6199 proc check_effective_target_arm_v8_1m_mve_ok { } {
6200 return [check_cached_effective_target arm_v8_1m_mve_ok \
6201 check_effective_target_arm_v8_1m_mve_ok_nocache]
6204 proc add_options_for_arm_v8_1m_mve { flags } {
6205 if { ! [check_effective_target_arm_v8_1m_mve_ok] } {
6208 global et_arm_v8_1m_mve_flags
6209 return "$flags $et_arm_v8_1m_mve_flags"
6212 proc check_effective_target_arm_v8_2a_dotprod_neon_ok { } {
6213 return [check_cached_effective_target arm_v8_2a_dotprod_neon_ok \
6214 check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache]
6217 proc add_options_for_arm_v8_2a_dotprod_neon { flags } {
6218 if { ! [check_effective_target_arm_v8_2a_dotprod_neon_ok] } {
6221 global et_arm_v8_2a_dotprod_neon_flags
6222 return "$flags $et_arm_v8_2a_dotprod_neon_flags"
6225 # Return 1 if the target supports ARMv8.2+i8mm Adv.SIMD Dot Product
6226 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6227 # Record the command line options needed.
6229 proc check_effective_target_arm_v8_2a_i8mm_ok_nocache { } {
6230 global et_arm_v8_2a_i8mm_flags
6231 set et_arm_v8_2a_i8mm_flags ""
6233 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6237 # Iterate through sets of options to find the compiler flags that
6238 # need to be added to the -march option.
6239 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } {
6240 if { [check_no_compiler_messages_nocache \
6241 arm_v8_2a_i8mm_ok object {
6242 #include <arm_neon.h>
6243 #if !defined (__ARM_FEATURE_MATMUL_INT8)
6244 #error "__ARM_FEATURE_MATMUL_INT8 not defined"
6246 } "$flags -march=armv8.2-a+i8mm"] } {
6247 set et_arm_v8_2a_i8mm_flags "$flags -march=armv8.2-a+i8mm"
6255 proc check_effective_target_arm_v8_2a_i8mm_ok { } {
6256 return [check_cached_effective_target arm_v8_2a_i8mm_ok \
6257 check_effective_target_arm_v8_2a_i8mm_ok_nocache]
6260 proc add_options_for_arm_v8_2a_i8mm { flags } {
6261 if { ! [check_effective_target_arm_v8_2a_i8mm_ok] } {
6264 global et_arm_v8_2a_i8mm_flags
6265 return "$flags $et_arm_v8_2a_i8mm_flags"
6268 # Return 1 if the target supports FP16 VFMAL and VFMSL
6269 # instructions, 0 otherwise.
6270 # Record the command line options needed.
6272 proc check_effective_target_arm_fp16fml_neon_ok_nocache { } {
6273 global et_arm_fp16fml_neon_flags
6274 set et_arm_fp16fml_neon_flags ""
6276 if { ![istarget arm*-*-*] } {
6280 # Iterate through sets of options to find the compiler flags that
6281 # need to be added to the -march option.
6282 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8"} {
6283 if { [check_no_compiler_messages_nocache \
6284 arm_fp16fml_neon_ok assembly {
6285 #include <arm_neon.h>
6287 foo (float32x2_t r, float16x4_t a, float16x4_t b)
6289 return vfmlal_high_f16 (r, a, b);
6291 } "$flags -march=armv8.2-a+fp16fml"] } {
6292 set et_arm_fp16fml_neon_flags "$flags -march=armv8.2-a+fp16fml"
6300 proc check_effective_target_arm_fp16fml_neon_ok { } {
6301 return [check_cached_effective_target arm_fp16fml_neon_ok \
6302 check_effective_target_arm_fp16fml_neon_ok_nocache]
6305 proc add_options_for_arm_fp16fml_neon { flags } {
6306 if { ! [check_effective_target_arm_fp16fml_neon_ok] } {
6309 global et_arm_fp16fml_neon_flags
6310 return "$flags $et_arm_fp16fml_neon_flags"
6313 # Return 1 if the target supports BFloat16 SIMD instructions, 0 otherwise.
6314 # The test is valid for ARM and for AArch64.
6316 proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
6317 global et_arm_v8_2a_bf16_neon_flags
6318 set et_arm_v8_2a_bf16_neon_flags ""
6320 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6324 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } {
6325 if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
6326 #include <arm_neon.h>
6327 #if !defined (__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)
6328 #error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC not defined"
6330 } "$flags -march=armv8.2-a+bf16"] } {
6331 set et_arm_v8_2a_bf16_neon_flags "$flags -march=armv8.2-a+bf16"
6339 proc check_effective_target_arm_v8_2a_bf16_neon_ok { } {
6340 return [check_cached_effective_target arm_v8_2a_bf16_neon_ok \
6341 check_effective_target_arm_v8_2a_bf16_neon_ok_nocache]
6344 proc add_options_for_arm_v8_2a_bf16_neon { flags } {
6345 if { ! [check_effective_target_arm_v8_2a_bf16_neon_ok] } {
6348 global et_arm_v8_2a_bf16_neon_flags
6349 return "$flags $et_arm_v8_2a_bf16_neon_flags"
6352 # A series of routines are created to 1) check if a given architecture is
6353 # effective (check_effective_target_*_ok) and then 2) give the corresponding
6354 # flags that enable the architecture (add_options_for_*).
6355 # The series includes:
6356 # arm_v8m_main_cde: Armv8-m CDE (Custom Datapath Extension).
6357 # arm_v8m_main_cde_fp: Armv8-m CDE with FP registers.
6358 # arm_v8_1m_main_cde_mve: Armv8.1-m CDE with MVE.
6359 # arm_v8_1m_main_cde_mve_fp: Armv8.1-m CDE with MVE with FP support.
6361 # /* { dg-require-effective-target arm_v8m_main_cde_ok } */
6362 # /* { dg-add-options arm_v8m_main_cde } */
6363 # The tests are valid for Arm.
6365 foreach { armfunc armflag armdef arminc } {
6367 "-march=armv8-m.main+cdecp0+cdecp6 -mthumb"
6368 "defined (__ARM_FEATURE_CDE)"
6371 "-march=armv8-m.main+fp+cdecp0+cdecp6 -mthumb -mfpu=auto"
6372 "defined (__ARM_FEATURE_CDE) && defined (__ARM_FP)"
6374 arm_v8_1m_main_cde_mve
6375 "-march=armv8.1-m.main+mve+cdecp0+cdecp6 -mthumb -mfpu=auto"
6376 "defined (__ARM_FEATURE_CDE) && defined (__ARM_FEATURE_MVE)"
6377 "#include <arm_mve.h>"
6378 arm_v8_1m_main_cde_mve_fp
6379 "-march=armv8.1-m.main+mve.fp+cdecp0+cdecp6 -mthumb -mfpu=auto"
6380 "defined (__ARM_FEATURE_CDE) || __ARM_FEATURE_MVE == 3"
6381 "#include <arm_mve.h>"
6383 eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef INC $arminc ] {
6384 proc check_effective_target_FUNC_ok_nocache { } {
6385 global et_FUNC_flags
6386 set et_FUNC_flags ""
6388 if { ![istarget arm*-*-*] } {
6392 if { [check_no_compiler_messages_nocache FUNC_ok assembly {
6396 #include <arm_cde.h>
6399 set et_FUNC_flags "FLAG"
6406 proc check_effective_target_FUNC_ok { } {
6407 return [check_cached_effective_target FUNC_ok \
6408 check_effective_target_FUNC_ok_nocache]
6411 proc add_options_for_FUNC { flags } {
6412 if { ! [check_effective_target_FUNC_ok] } {
6415 global et_FUNC_flags
6416 return "$flags $et_FUNC_flags"
6419 proc check_effective_target_FUNC_link { } {
6420 if { ! [check_effective_target_FUNC_ok] } {
6423 return [check_no_compiler_messages FUNC_link executable {
6427 #include <arm_cde.h>
6434 } [add_options_for_FUNC ""]]
6437 proc check_effective_target_FUNC_multilib { } {
6438 if { ! [check_effective_target_FUNC_ok] } {
6441 return [check_runtime FUNC_multilib {
6445 #include <arm_cde.h>
6452 } [add_options_for_FUNC ""]]
6457 # Return 1 if the target supports executing ARMv8 NEON instructions, 0
6460 proc check_effective_target_arm_v8_neon_hw { } {
6461 return [check_runtime arm_v8_neon_hw_available {
6462 #include "arm_neon.h"
6466 float32x2_t a = { 1.0f, 2.0f };
6467 #ifdef __ARM_ARCH_ISA_A64
6468 asm ("frinta %0.2s, %1.2s"
6472 asm ("vrinta.f32 %P0, %P1"
6476 return a[0] == 2.0f;
6478 } [add_options_for_arm_v8_neon ""]]
6481 # Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
6482 # otherwise. The test is valid for AArch64 and ARM.
6484 proc check_effective_target_arm_v8_1a_neon_hw { } {
6485 if { ![check_effective_target_arm_v8_1a_neon_ok] } {
6488 return [check_runtime arm_v8_1a_neon_hw_available {
6492 #ifdef __ARM_ARCH_ISA_A64
6493 __Int32x2_t a = {0, 1};
6494 __Int32x2_t b = {0, 2};
6497 asm ("sqrdmlah %0.2s, %1.2s, %2.2s"
6500 : /* No clobbers. */);
6504 __simd64_int32_t a = {0, 1};
6505 __simd64_int32_t b = {0, 2};
6506 __simd64_int32_t result;
6508 asm ("vqrdmlah.s32 %P0, %P1, %P2"
6511 : /* No clobbers. */);
6516 } [add_options_for_arm_v8_1a_neon ""]]
6519 # Return 1 if the target supports executing floating point instructions from
6520 # ARMv8.2 with the FP16 extension, 0 otherwise. The test is valid for ARM and
6523 proc check_effective_target_arm_v8_2a_fp16_scalar_hw { } {
6524 if { ![check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
6527 return [check_runtime arm_v8_2a_fp16_scalar_hw_available {
6534 #ifdef __ARM_ARCH_ISA_A64
6536 asm ("fabs %h0, %h1"
6539 : /* No clobbers. */);
6543 asm ("vabs.f16 %0, %1"
6546 : /* No clobbers. */);
6550 return (result == 1.0) ? 0 : 1;
6552 } [add_options_for_arm_v8_2a_fp16_scalar ""]]
6555 # Return 1 if the target supports executing Adv.SIMD instructions from ARMv8.2
6556 # with the FP16 extension, 0 otherwise. The test is valid for ARM and for
6559 proc check_effective_target_arm_v8_2a_fp16_neon_hw { } {
6560 if { ![check_effective_target_arm_v8_2a_fp16_neon_ok] } {
6563 return [check_runtime arm_v8_2a_fp16_neon_hw_available {
6567 #ifdef __ARM_ARCH_ISA_A64
6569 __Float16x4_t a = {1.0, -1.0, 1.0, -1.0};
6570 __Float16x4_t result;
6572 asm ("fabs %0.4h, %1.4h"
6575 : /* No clobbers. */);
6579 __simd64_float16_t a = {1.0, -1.0, 1.0, -1.0};
6580 __simd64_float16_t result;
6582 asm ("vabs.f16 %P0, %P1"
6585 : /* No clobbers. */);
6589 return (result[0] == 1.0) ? 0 : 1;
6591 } [add_options_for_arm_v8_2a_fp16_neon ""]]
6594 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2
6595 # with the Dot Product extension, 0 otherwise. The test is valid for ARM and for
6598 proc check_effective_target_arm_v8_2a_dotprod_neon_hw { } {
6599 if { ![check_effective_target_arm_v8_2a_dotprod_neon_ok] } {
6602 return [check_runtime arm_v8_2a_dotprod_neon_hw_available {
6603 #include "arm_neon.h"
6608 uint32x2_t results = {0,0};
6609 uint8x8_t a = {1,1,1,1,2,2,2,2};
6610 uint8x8_t b = {2,2,2,2,3,3,3,3};
6612 #ifdef __ARM_ARCH_ISA_A64
6613 asm ("udot %0.2s, %1.8b, %2.8b"
6616 : /* No clobbers. */);
6619 asm ("vudot.u8 %P0, %P1, %P2"
6622 : /* No clobbers. */);
6625 return (results[0] == 8 && results[1] == 24) ? 1 : 0;
6627 } [add_options_for_arm_v8_2a_dotprod_neon ""]]
6630 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2
6631 # with the i8mm extension, 0 otherwise. The test is valid for ARM and for
6634 proc check_effective_target_arm_v8_2a_i8mm_neon_hw { } {
6635 if { ![check_effective_target_arm_v8_2a_i8mm_ok] } {
6638 return [check_runtime arm_v8_2a_i8mm_neon_hw_available {
6639 #include "arm_neon.h"
6644 uint32x2_t results = {0,0};
6645 uint8x8_t a = {1,1,1,1,2,2,2,2};
6646 int8x8_t b = {2,2,2,2,3,3,3,3};
6648 #ifdef __ARM_ARCH_ISA_A64
6649 asm ("usdot %0.2s, %1.8b, %2.8b"
6652 : /* No clobbers. */);
6655 asm ("vusdot.u8 %P0, %P1, %P2"
6658 : /* No clobbers. */);
6661 return (vget_lane_u32 (results, 0) == 8
6662 && vget_lane_u32 (results, 1) == 24) ? 1 : 0;
6664 } [add_options_for_arm_v8_2a_i8mm ""]]
6667 # Return 1 if this is a ARM target with NEON enabled.
6669 proc check_effective_target_arm_neon { } {
6670 if { [check_effective_target_arm32] } {
6671 return [check_no_compiler_messages arm_neon object {
6672 #ifndef __ARM_NEON__
6683 proc check_effective_target_arm_neonv2 { } {
6684 if { [check_effective_target_arm32] } {
6685 return [check_no_compiler_messages arm_neon object {
6686 #ifndef __ARM_NEON__
6689 #ifndef __ARM_FEATURE_FMA
6701 # Return 1 if this is an ARM target with load acquire and store release
6702 # instructions for 8-, 16- and 32-bit types.
6704 proc check_effective_target_arm_acq_rel { } {
6705 return [check_no_compiler_messages arm_acq_rel object {
6707 load_acquire_store_release (void)
6709 asm ("lda r0, [r1]\n\t"
6715 : : : "r0", "memory");
6720 # Add the options needed for MIPS Paired-Single.
6722 proc add_options_for_mpaired_single { flags } {
6723 if { ! [check_effective_target_mpaired_single "-mpaired-single"] } {
6726 return "$flags -mpaired-single"
6729 # Add the options needed for MIPS SIMD Architecture.
6731 proc add_options_for_mips_msa { flags } {
6732 if { ! [check_effective_target_mips_msa "-mmsa"] } {
6735 return "$flags -mmsa"
6738 # Add the options needed for MIPS Loongson MMI Architecture.
6740 proc add_options_for_mips_loongson_mmi { flags } {
6741 if { ! [check_effective_target_mips_loongson_mmi "-mloongson-mmi"] } {
6744 return "$flags -mloongson-mmi"
6748 # Return 1 if this a Loongson-2E or -2F target using an ABI that supports
6749 # the Loongson vector modes.
6751 proc check_effective_target_mips_loongson_mmi { args } {
6752 return [check_no_compiler_messages loongson assembly {
6753 #if !defined(__mips_loongson_mmi)
6754 #error !__mips_loongson_mmi
6756 #if !defined(__mips_loongson_vector_rev)
6757 #error !__mips_loongson_vector_rev
6762 # Return 1 if this is a MIPS target that supports the legacy NAN.
6764 proc check_effective_target_mips_nanlegacy { } {
6765 return [check_no_compiler_messages nanlegacy assembly {
6767 int main () { return 0; }
6771 # Return 1 if an MSA program can be compiled to object
6773 proc check_effective_target_mips_msa { args } {
6774 if ![check_effective_target_nomips16] {
6777 return [check_no_compiler_messages msa object {
6778 #if !defined(__mips_msa)
6779 #error "MSA NOT AVAIL"
6781 #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2))
6782 #error "MSA NOT AVAIL FOR ISA REV < 2"
6784 #if !defined(__mips_hard_float)
6785 #error "MSA HARD_FLOAT REQUIRED"
6787 #if __mips_fpr != 64
6788 #error "MSA 64-bit FPR REQUIRED"
6794 v8i16 v = __builtin_msa_ldi_h (1);
6802 # Return 1 if this is an ARM target that adheres to the ABI for the ARM
6805 proc check_effective_target_arm_eabi { } {
6806 return [check_no_compiler_messages arm_eabi object {
6807 #ifndef __ARM_EABI__
6815 # Return 1 if this is an ARM target that adheres to the hard-float variant of
6816 # the ABI for the ARM Architecture (e.g. -mfloat-abi=hard).
6818 proc check_effective_target_arm_hf_eabi { } {
6819 return [check_no_compiler_messages arm_hf_eabi object {
6820 #if !defined(__ARM_EABI__) || !defined(__ARM_PCS_VFP)
6821 #error not hard-float EABI
6828 # Return 1 if this is an ARM target uses emulated floating point
6831 proc check_effective_target_arm_softfloat { } {
6832 return [check_no_compiler_messages arm_softfloat object {
6833 #if !defined(__SOFTFP__)
6834 #error not soft-float EABI
6841 # Return 1 if this is an ARM target supporting -mcpu=iwmmxt.
6842 # Some multilibs may be incompatible with this option.
6844 proc check_effective_target_arm_iwmmxt_ok { } {
6845 if { [check_effective_target_arm32] } {
6846 return [check_no_compiler_messages arm_iwmmxt_ok object {
6854 # Return true if LDRD/STRD instructions are prefered over LDM/STM instructions
6855 # for an ARM target.
6856 proc check_effective_target_arm_prefer_ldrd_strd { } {
6857 if { ![check_effective_target_arm32] } {
6861 return [check_no_messages_and_pattern arm_prefer_ldrd_strd "strd\tr" assembly {
6862 void foo (void) { __asm__ ("" ::: "r4", "r5"); }
6866 # Return true if LDRD/STRD instructions are available on this target.
6867 proc check_effective_target_arm_ldrd_strd_ok { } {
6868 if { ![check_effective_target_arm32] } {
6872 return [check_no_compiler_messages arm_ldrd_strd_ok object {
6875 __UINT64_TYPE__ a = 1, b = 10;
6876 __UINT64_TYPE__ *c = &b;
6877 // `a` will be in a valid register since it's a DImode quantity.
6886 #
Return 1 if this is a PowerPC target supporting
-meabi.
6888 proc check_effective_target_powerpc_eabi_ok
{ } {
6889 if { [istarget powerpc
*-*-*] } {
6890 return [check_no_compiler_messages powerpc_eabi_ok object
{
6898 #
Return 1 if this is a PowerPC target with floating
-point registers.
6900 proc check_effective_target_powerpc_fprs
{ } {
6901 if { [istarget powerpc
*-*-*]
6902 ||
[istarget rs6000
-*-*] } {
6903 return [check_no_compiler_messages powerpc_fprs object
{
6915 #
Return 1 if this is a PowerPC target with hardware double
-precision
6918 proc check_effective_target_powerpc_hard_double
{ } {
6919 if { [istarget powerpc
*-*-*]
6920 ||
[istarget rs6000
-*-*] } {
6921 return [check_no_compiler_messages powerpc_hard_double object
{
6933 #
Return 1 if this is a PowerPC target with hardware floating point
sqrt.
6935 proc check_effective_target_powerpc_sqrt
{ } {
6936 # We need to be PowerPC
, and we need to have hardware fp enabled.
6937 if {![check_effective_target_powerpc_fprs
]} {
6941 return [check_no_compiler_messages powerpc_sqrt object
{
6945 #error _ARCH_PPCSQ is not defined
6951 #
Return 1 if this is a PowerPC target supporting
-maltivec.
6953 proc check_effective_target_powerpc_altivec_ok
{ } {
6954 # Not PowerPC
, then not ok
6955 if { !([istarget powerpc
*-*-*] ||
[istarget rs6000
-*-*]) } { return 0 }
6957 # Paired Single
, then not ok
6958 if { [istarget powerpc
-*-linux
*paired
*] } { return 0 }
6960 # AltiVec is not supported
on AIX before
5.3.
6961 if { [istarget powerpc
*-*-aix4
*]
6962 ||
[istarget powerpc
*-*-aix5.1
*]
6963 ||
[istarget powerpc
*-*-aix5.2
*] } { return 0 }
6965 #
Return true iff compiling with
-maltivec does not error.
6966 return [check_no_compiler_messages powerpc_altivec_ok object
{
6971 #
Return 1 if this is a PowerPC target supporting
-mmodulo
6973 proc check_effective_target_powerpc_p9modulo_ok
{ } {
6974 if { ([istarget powerpc
*-*-*]
6975 && ![istarget powerpc
-*-linux
*paired
*])
6976 ||
[istarget rs6000
-*-*] } {
6977 # AltiVec is not supported
on AIX before
5.3.
6978 if { [istarget powerpc
*-*-aix4
*]
6979 ||
[istarget powerpc
*-*-aix5.1
*]
6980 ||
[istarget powerpc
*-*-aix5.2
*] } {
6983 return [check_no_compiler_messages powerpc_p9modulo_ok object
{
6985 int i
= 5, j
= 3, r
= -1;
6986 asm
("modsw %0,%1,%2" : "+r" (r) : "r" (i), "r" (j));
6995 #
return 1 if our compiler returns the ARCH_PWR defines with the options
6996 # as provided by the test.
6997 proc check_effective_target_has_arch_pwr5
{ } {
6998 return [check_no_compiler_messages_nocache arch_pwr5 assembly
{
7002 #error does not have power5 support.
7004 /* "has power5 support" */
7007 } [current_compiler_flags
]]
7010 proc check_effective_target_has_arch_pwr6
{ } {
7011 return [check_no_compiler_messages_nocache arch_pwr6 assembly
{
7015 #error does not have power6 support.
7017 /* "has power6 support" */
7020 } [current_compiler_flags
]]
7023 proc check_effective_target_has_arch_pwr7
{ } {
7024 return [check_no_compiler_messages_nocache arch_pwr7 assembly
{
7028 #error does not have power7 support.
7030 /* "has power7 support" */
7033 } [current_compiler_flags
]]
7036 proc check_effective_target_has_arch_pwr8
{ } {
7037 return [check_no_compiler_messages_nocache arch_pwr8 assembly
{
7041 #error does not have power8 support.
7043 /* "has power8 support" */
7046 } [current_compiler_flags
]]
7049 proc check_effective_target_has_arch_pwr9
{ } {
7050 return [check_no_compiler_messages_nocache arch_pwr9 assembly
{
7054 #error does not have power9 support.
7056 /* "has power9 support" */
7059 } [current_compiler_flags
]]
7062 proc check_effective_target_has_arch_pwr10
{ } {
7063 return [check_no_compiler_messages_nocache arch_pwr10 assembly
{
7067 #error does not have power10 support.
7069 /* "has power10 support" */
7072 } [current_compiler_flags
]]
7075 proc check_effective_target_has_arch_ppc64
{ } {
7076 return [check_no_compiler_messages_nocache arch_ppc64 assembly
{
7080 #error does not have ppc64 support.
7082 /* "has ppc64 support" */
7085 } [current_compiler_flags
]]
7088 #
Return 1 if this is a PowerPC target supporting
-mcpu
=power10.
7089 #
Limit this to
64-bit linux systems
for now until other targets support
7092 proc check_effective_target_power10_ok
{ } {
7093 if { ([istarget powerpc64
*-*-linux
*]) } {
7094 return [check_no_compiler_messages power10_ok object
{
7097 asm
("pli %0,%1" : "=r" (e) : "n" (0x12345));
7106 #
Return 1 if this is a PowerPC target supporting
-mfloat128 via either
7107 # software emulation
on power7
/power8 systems or hardware support
on power9.
7109 proc check_effective_target_powerpc_float128_sw_ok
{ } {
7110 if { ([istarget powerpc
*-*-*]
7111 && ![istarget powerpc
-*-linux
*paired
*])
7112 ||
[istarget rs6000
-*-*] } {
7113 # AltiVec is not supported
on AIX before
5.3.
7114 if { [istarget powerpc
*-*-aix4
*]
7115 ||
[istarget powerpc
*-*-aix5.1
*]
7116 ||
[istarget powerpc
*-*-aix5.2
*] } {
7119 # Darwin doesn
't have VSX, so no soft support for float128.
7120 if { [istarget *-*-darwin*] } {
7123 return [check_no_compiler_messages powerpc_float128_sw_ok object {
7124 volatile __float128 x = 1.0q;
7125 volatile __float128 y = 2.0q;
7127 __float128 z = x + y;
7130 } "-mfloat128 -mvsx"]
7136 # Return 1 if this is a PowerPC target supporting -mfloat128 via hardware
7137 # support on power9.
7139 proc check_effective_target_powerpc_float128_hw_ok { } {
7140 if { ([istarget powerpc*-*-*]
7141 && ![istarget powerpc-*-linux*paired*])
7142 || [istarget rs6000-*-*] } {
7143 # AltiVec is not supported on AIX before 5.3.
7144 if { [istarget powerpc*-*-aix4*]
7145 || [istarget powerpc*-*-aix5.1*]
7146 || [istarget powerpc*-*-aix5.2*] } {
7149 # Darwin doesn't run
on any machine with float128 h
/w so far.
7150 if { [istarget
*-*-darwin
*] } {
7153 return [check_no_compiler_messages powerpc_float128_hw_ok object
{
7154 volatile __float128 x
= 1.0q
;
7155 volatile __float128 y
= 2.0q
;
7158 __asm__
("xsaddqp %0,%1,%2" : "=v" (z) : "v" (x), "v" (y));
7161 } "-mfloat128-hardware"]
7167 #
Return 1 if current options
define float128
, 0 otherwise.
7169 proc check_effective_target_ppc_float128
{ } {
7170 return [check_no_compiler_messages_nocache ppc_float128 object
{
7173 #ifndef __FLOAT128__
7180 #
Return 1 if current options generate float128 insns
, 0 otherwise.
7182 proc check_effective_target_ppc_float128_insns
{ } {
7183 return [check_no_compiler_messages_nocache ppc_float128 object
{
7186 #ifndef __FLOAT128_HARDWARE__
7193 #
Return 1 if current options generate VSX instructions
, 0 otherwise.
7195 proc check_effective_target_powerpc_vsx
{ } {
7196 return [check_no_compiler_messages_nocache powerpc_vsx object
{
7206 #
Return 1 if this is a PowerPC target supporting
-mvsx
7208 proc check_effective_target_powerpc_vsx_ok
{ } {
7209 if { ([istarget powerpc
*-*-*]
7210 && ![istarget powerpc
-*-linux
*paired
*])
7211 ||
[istarget rs6000
-*-*] } {
7212 # VSX is not supported
on AIX before
7.1.
7213 if { [istarget powerpc
*-*-aix4
*]
7214 ||
[istarget powerpc
*-*-aix5
*]
7215 ||
[istarget powerpc
*-*-aix6
*] } {
7218 # Darwin doesn
't have VSX, even if it's used with an assembler
7219 # which recognises the insns.
7220 if { [istarget
*-*-darwin
*] } {
7223 return [check_no_compiler_messages powerpc_vsx_ok object
{
7225 asm volatile
("xxlor 0,0,0");
7234 #
Return 1 if this is a PowerPC target supporting
-mhtm
7236 proc check_effective_target_powerpc_htm_ok
{ } {
7237 if { ([istarget powerpc
*-*-*]
7238 && ![istarget powerpc
-*-linux
*paired
*])
7239 ||
[istarget rs6000
-*-*] } {
7240 # HTM is not supported
on AIX yet.
7241 if { [istarget powerpc
*-*-aix
*] } {
7244 return [check_no_compiler_messages powerpc_htm_ok object
{
7246 asm volatile
("tbegin. 0");
7255 #
Return 1 if the target supports executing HTM hardware instructions
,
7256 #
0 otherwise.
Cache the result.
7258 proc check_htm_hw_available
{ } {
7259 return [check_cached_effective_target htm_hw_available
{
7260 #
For now
, disable
on Darwin
7261 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] ||
[istarget
*-*-darwin
*]} {
7264 check_runtime_nocache htm_hw_available
{
7274 #
Return 1 if this is a PowerPC target supporting
-mcpu
=cell.
7276 proc check_effective_target_powerpc_ppu_ok
{ } {
7277 if [check_effective_target_powerpc_altivec_ok
] {
7278 return [check_no_compiler_messages cell_asm_available object
{
7281 asm volatile
("lvlx v0,v0,v0");
7283 asm volatile
("lvlx 0,0,0");
7293 #
Return 1 if this is a PowerPC target that supports SPU.
7295 proc check_effective_target_powerpc_spu
{ } {
7296 if { [istarget powerpc
*-*-linux
*] } {
7297 return [check_effective_target_powerpc_altivec_ok
]
7303 #
Return 1 if this is a PowerPC SPE target. The check includes options
7304 # specified by dg
-options
for this test
, so don
't cache the result.
7306 proc check_effective_target_powerpc_spe_nocache { } {
7307 if { [istarget powerpc*-*-*] } {
7308 return [check_no_compiler_messages_nocache powerpc_spe object {
7314 } [current_compiler_flags]]
7320 # Return 1 if this is a PowerPC target with SPE enabled.
7322 proc check_effective_target_powerpc_spe { } {
7323 if { [istarget powerpc*-*-*] } {
7324 return [check_no_compiler_messages powerpc_spe object {
7336 # Return 1 if this is a PowerPC target with Altivec enabled.
7338 proc check_effective_target_powerpc_altivec { } {
7339 if { [istarget powerpc*-*-*] } {
7340 return [check_no_compiler_messages powerpc_altivec object {
7352 # Return 1 if this is a PowerPC 405 target. The check includes options
7353 # specified by dg-options for this test, so don't
cache the result.
7355 proc check_effective_target_powerpc_405_nocache
{ } {
7356 if { [istarget powerpc
*-*-*] ||
[istarget rs6000
-*-*] } {
7357 return [check_no_compiler_messages_nocache powerpc_405 object
{
7363 } [current_compiler_flags
]]
7369 #
Return 1 if this is a PowerPC target using the ELFv2 ABI.
7371 proc check_effective_target_powerpc_elfv2
{ } {
7372 if { [istarget powerpc
*-*-*] } {
7373 return [check_no_compiler_messages powerpc_elfv2 object
{
7375 #error not ELF v2 ABI
7385 #
Return 1 if this is a PowerPC target supporting
-mrop
-protect
7387 proc check_effective_target_rop_ok
{ } {
7388 return [check_effective_target_power10_ok
] && [check_effective_target_powerpc_elfv2
]
7391 # The VxWorks SPARC simulator accepts only EM_SPARC executables and
7392 # chokes
on EM_SPARC32PLUS or EM_SPARCV9 executables.
Return 1 if the
7393 # test environment appears to run executables
on such a simulator.
7395 proc check_effective_target_ultrasparc_hw
{ } {
7396 return [check_runtime ultrasparc_hw
{
7397 int main
() { return 0; }
7398 } "-mcpu=ultrasparc"]
7401 #
Return 1 if the test environment supports executing UltraSPARC VIS2
7402 # instructions. We check this by attempting
: "bmask %g0, %g0, %g0"
7404 proc check_effective_target_ultrasparc_vis2_hw
{ } {
7405 return [check_runtime ultrasparc_vis2_hw
{
7406 int main
() { __asm__
(".word 0x81b00320"); return 0; }
7407 } "-mcpu=ultrasparc3"]
7410 #
Return 1 if the test environment supports executing UltraSPARC VIS3
7411 # instructions. We check this by attempting
: "addxc %g0, %g0, %g0"
7413 proc check_effective_target_ultrasparc_vis3_hw
{ } {
7414 return [check_runtime ultrasparc_vis3_hw
{
7415 int main
() { __asm__
(".word 0x81b00220"); return 0; }
7419 #
Return 1 if this is a SPARC
-V9 target.
7421 proc check_effective_target_sparc_v9
{ } {
7422 if { [istarget sparc
*-*-*] } {
7423 return [check_no_compiler_messages sparc_v9 object
{
7425 asm volatile
("return %i7+8");
7434 #
Return 1 if this is a SPARC target with VIS enabled.
7436 proc check_effective_target_sparc_vis
{ } {
7437 if { [istarget sparc
*-*-*] } {
7438 return [check_no_compiler_messages sparc_vis object
{
7450 #
Return 1 if the target supports hardware vector shift operation.
7452 proc check_effective_target_vect_shift
{ } {
7453 return [check_cached_effective_target_indexed vect_shift
{
7454 expr
{([istarget powerpc
*-*-*]
7455 && ![istarget powerpc
-*-linux
*paired
*])
7456 ||
[istarget ia64
-*-*]
7457 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7458 ||
[istarget aarch64
*-*-*]
7459 ||
[is
-effective
-target arm_neon
]
7460 ||
([istarget mips
*-*-*]
7461 && ([et
-is
-effective
-target mips_msa
]
7462 ||
[et
-is
-effective
-target mips_loongson_mmi
]))
7463 ||
([istarget s390
*-*-*]
7464 && [check_effective_target_s390_vx
])
7465 ||
[istarget amdgcn
-*-*]
7466 ||
([istarget riscv
*-*-*]
7467 && [check_effective_target_riscv_v
])
7468 ||
([istarget loongarch
*-*-*]
7469 && [check_effective_target_loongarch_sx
]) }}]
7472 #
Return 1 if the target supports hardware vector shift by register operation.
7474 proc check_effective_target_vect_var_shift
{ } {
7475 return [check_cached_effective_target_indexed vect_var_shift
{
7476 expr
{(([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
7477 && [check_avx2_available
])
7478 ||
[istarget aarch64
*-*-*]
7479 ||
([istarget riscv
*-*-*]
7480 && [check_effective_target_riscv_v
])
7481 ||
([istarget loongarch
*-*-*]
7482 && [check_effective_target_loongarch_sx
])
7486 proc check_effective_target_whole_vector_shift
{ } {
7487 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7488 ||
[istarget ia64
-*-*]
7489 ||
[istarget aarch64
*-*-*]
7490 ||
[istarget powerpc64
*-*-*]
7491 ||
([is
-effective
-target arm_neon
]
7492 && [check_effective_target_arm_little_endian
])
7493 ||
([istarget mips
*-*-*]
7494 && [et
-is
-effective
-target mips_loongson_mmi
])
7495 ||
([istarget s390
*-*-*]
7496 && [check_effective_target_s390_vx
])
7497 ||
[istarget amdgcn
-*-*]
7498 ||
([istarget riscv
*-*-*]
7499 && [check_effective_target_riscv_v
])
7500 ||
([istarget loongarch
*-*-*]
7501 && [check_effective_target_loongarch_sx
]) } {
7507 verbose
"check_effective_target_vect_long: returning $answer" 2
7511 #
Return 1 if the target supports vector bswap operations.
7513 proc check_effective_target_vect_bswap
{ } {
7514 return [check_cached_effective_target_indexed vect_bswap
{
7515 expr
{ ([istarget aarch64
*-*-*]
7516 ||
[is
-effective
-target arm_neon
]
7517 ||
[istarget amdgcn
-*-*])
7518 ||
[istarget loongarch
*-*-*]
7519 ||
([istarget s390
*-*-*]
7520 && [check_effective_target_s390_vx
]) }}]
7523 #
Return 1 if the target supports comparison of
bool vectors
for at
7524 # least one vector length.
7526 proc check_effective_target_vect_bool_cmp
{ } {
7527 return [check_cached_effective_target_indexed vect_bool_cmp
{
7528 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7529 ||
[istarget aarch64
*-*-*]
7530 ||
[is
-effective
-target arm_neon
]
7531 ||
([istarget riscv
*-*-*]
7532 && [check_effective_target_riscv_v
])
7533 ||
([istarget loongarch
*-*-*]
7534 && [check_effective_target_loongarch_sx
]) }}]
7537 #
Return 1 if the target supports addition of char vectors
for at least
7538 # one vector length.
7540 proc check_effective_target_vect_char_add
{ } {
7541 return [check_cached_effective_target_indexed vect_char_add
{
7543 [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7544 ||
([istarget powerpc
*-*-*]
7545 && ![istarget powerpc
-*-linux
*paired
*])
7546 ||
[istarget amdgcn
-*-*]
7547 ||
[istarget ia64
-*-*]
7548 ||
[istarget aarch64
*-*-*]
7549 ||
[is
-effective
-target arm_neon
]
7550 ||
([istarget mips
*-*-*]
7551 && ([et
-is
-effective
-target mips_loongson_mmi
]
7552 ||
[et
-is
-effective
-target mips_msa
]))
7553 ||
([istarget s390
*-*-*]
7554 && [check_effective_target_s390_vx
])
7555 ||
([istarget riscv
*-*-*]
7556 && [check_effective_target_riscv_v
])
7557 ||
([istarget loongarch
*-*-*]
7558 && [check_effective_target_loongarch_sx
])
7562 #
Return 1 if the target supports hardware vector shift operation
for char.
7564 proc check_effective_target_vect_shift_char
{ } {
7565 return [check_cached_effective_target_indexed vect_shift_char
{
7566 expr
{ ([istarget powerpc
*-*-*]
7567 && ![istarget powerpc
-*-linux
*paired
*])
7568 ||
[is
-effective
-target arm_neon
]
7569 ||
([istarget mips
*-*-*]
7570 && [et
-is
-effective
-target mips_msa
])
7571 ||
([istarget s390
*-*-*]
7572 && [check_effective_target_s390_vx
])
7573 ||
[istarget amdgcn
-*-*]
7574 ||
([istarget riscv
*-*-*]
7575 && [check_effective_target_riscv_v
])
7576 ||
([istarget loongarch
*-*-*]
7577 && [check_effective_target_loongarch_sx
]) }}]
7580 #
Return 1 if the target supports hardware vectors of long
, 0 otherwise.
7582 # This can change
for different subtargets so
do not
cache the result.
7584 proc check_effective_target_vect_long
{ } {
7585 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7586 ||
(([istarget powerpc
*-*-*]
7587 && ![istarget powerpc
-*-linux
*paired
*])
7588 && [check_effective_target_ilp32
])
7589 ||
[is
-effective
-target arm_neon
]
7590 ||
([istarget sparc
*-*-*] && [check_effective_target_ilp32
])
7591 ||
[istarget aarch64
*-*-*]
7592 ||
([istarget mips
*-*-*]
7593 && [et
-is
-effective
-target mips_msa
])
7594 ||
([istarget s390
*-*-*]
7595 && [check_effective_target_s390_vx
])
7596 ||
[istarget amdgcn
-*-*]
7597 ||
([istarget riscv
*-*-*]
7598 && [check_effective_target_riscv_v
])
7599 ||
([istarget loongarch
*-*-*]
7600 && [check_effective_target_loongarch_sx
]) } {
7606 verbose
"check_effective_target_vect_long: returning $answer" 2
7610 #
Return 1 if the target supports hardware vectors of float when
7611 #
-funsafe
-math
-optimizations is enabled
, 0 otherwise.
7613 # This won
't change for different subtargets so cache the result.
7615 proc check_effective_target_vect_float { } {
7616 return [check_cached_effective_target_indexed vect_float {
7617 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7618 || [istarget powerpc*-*-*]
7619 || [istarget mips-sde-elf]
7620 || [istarget mipsisa64*-*-*]
7621 || [istarget ia64-*-*]
7622 || [istarget aarch64*-*-*]
7623 || ([istarget mips*-*-*]
7624 && [et-is-effective-target mips_msa])
7625 || [is-effective-target arm_neon]
7626 || ([istarget s390*-*-*]
7627 && [check_effective_target_s390_vxe])
7628 || [istarget amdgcn-*-*]
7629 || ([istarget riscv*-*-*]
7630 && [check_effective_target_riscv_v])
7631 || ([istarget loongarch*-*-*]
7632 && [check_effective_target_loongarch_sx]) }}]
7635 # Return 1 if the target supports hardware vectors of float without
7636 # -funsafe-math-optimizations being enabled, 0 otherwise.
7638 proc check_effective_target_vect_float_strict { } {
7639 return [expr { [check_effective_target_vect_float]
7640 && ![istarget arm*-*-*] }]
7643 # Return 1 if the target supports hardware vectors of double, 0 otherwise.
7645 # This won't change
for different subtargets so
cache the result.
7647 proc check_effective_target_vect_double
{ } {
7648 return [check_cached_effective_target_indexed vect_double
{
7649 expr
{ (([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
7650 && [check_no_compiler_messages vect_double assembly
{
7651 #ifdef __tune_atom__
7652 # error No double vectorizer support.
7655 ||
[istarget aarch64
*-*-*]
7656 ||
([istarget powerpc
*-*-*] && [check_vsx_hw_available
])
7657 ||
([istarget mips
*-*-*]
7658 && [et
-is
-effective
-target mips_msa
])
7659 ||
([istarget s390
*-*-*]
7660 && [check_effective_target_s390_vx
])
7661 ||
[istarget amdgcn
-*-*]
7662 ||
([istarget riscv
*-*-*]
7663 && [check_effective_target_riscv_v
])
7664 ||
([istarget loongarch
*-*-*]
7665 && [check_effective_target_loongarch_sx
]) }}]
7668 #
Return 1 if the target supports conditional addition
, subtraction
,
7669 # multiplication
, division
, minimum and maximum
on vectors of double
,
7670 # via the cond_ optabs.
Return 0 otherwise.
7672 proc check_effective_target_vect_double_cond_arith
{ } {
7673 return [expr
{ [check_effective_target_aarch64_sve
]
7674 ||
[check_effective_target_riscv_v
] }]
7677 #
Return 1 if the target supports hardware vectors of long long
, 0 otherwise.
7679 # This won
't change for different subtargets so cache the result.
7681 proc check_effective_target_vect_long_long { } {
7682 return [check_cached_effective_target_indexed vect_long_long {
7683 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7684 || ([istarget mips*-*-*]
7685 && [et-is-effective-target mips_msa])
7686 || ([istarget s390*-*-*]
7687 && [check_effective_target_s390_vx])
7688 || ([istarget powerpc*-*-*]
7689 && ![istarget powerpc-*-linux*paired*]
7690 && [check_effective_target_has_arch_pwr8])
7691 || [istarget aarch64*-*-*]
7692 || ([istarget riscv*-*-*]
7693 && [check_effective_target_riscv_v])
7694 || ([istarget loongarch*-*-*]
7695 && [check_effective_target_loongarch_sx])
7696 || [istarget amdgcn-*-*] }}]
7700 # Return 1 if the target plus current options does not support a vector
7701 # max instruction on "int", 0 otherwise.
7703 # This won't change
for different subtargets so
cache the result.
7705 proc check_effective_target_vect_no_int_min_max
{ } {
7706 return [check_cached_effective_target_indexed vect_no_int_min_max
{
7707 expr
{ [istarget sparc
*-*-*]
7708 ||
[istarget alpha
*-*-*]
7709 ||
([istarget mips
*-*-*]
7710 && [et
-is
-effective
-target mips_loongson_mmi
]) }}]
7713 #
Return 1 if the target plus current options does not support a vector
7714 # add instruction
on "int", 0 otherwise.
7716 # This won
't change for different subtargets so cache the result.
7718 proc check_effective_target_vect_no_int_add { } {
7719 # Alpha only supports vector add on V8QI and V4HI.
7720 return [check_cached_effective_target_indexed vect_no_int_add {
7721 expr { [istarget alpha*-*-*] }}]
7724 # Return 1 if the target plus current options does not support vector
7725 # bitwise instructions, 0 otherwise.
7727 # This won't change
for different subtargets so
cache the result.
7729 proc check_effective_target_vect_no_bitwise
{ } {
7730 return [check_cached_effective_target_indexed vect_no_bitwise
{ return 0 }]
7733 #
Return 1 if the target plus current options supports vector permutation
,
7736 # This won
't change for different subtargets so cache the result.
7738 proc check_effective_target_vect_perm { } {
7739 return [check_cached_effective_target_indexed vect_perm {
7740 expr { [is-effective-target arm_neon]
7741 || [istarget aarch64*-*-*]
7742 || [istarget powerpc*-*-*]
7743 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7744 || ([istarget mips*-*-*]
7745 && ([et-is-effective-target mpaired_single]
7746 || [et-is-effective-target mips_msa]))
7747 || ([istarget s390*-*-*]
7748 && [check_effective_target_s390_vx])
7749 || [istarget amdgcn-*-*]
7750 || ([istarget riscv*-*-*]
7751 && [check_effective_target_riscv_v])
7752 || ([istarget loongarch*-*-*]
7753 && [check_effective_target_loongarch_sx]) }}]
7756 # Return 1 if, for some VF:
7758 # - the target's default vector size is VF
* ELEMENT_BITS bits
7760 #
- it is possible to implement the equivalent of
:
7762 #
int<ELEMENT_BITS
>_t s1
[COUNT][COUNT * VF
], s2
[COUNT * VF
];
7763 #
for (int i
= 0; i
< COUNT; ++i
)
7764 #
for (int j
= 0; j
< COUNT * VF
; ++j
)
7765 # s1
[i
][j
] = s2
[j
- j
% COUNT + i
]
7767 # using only a single
2-vector permute
for each vector in s1.
7769 # E.g.
for COUNT == 3 and vector length
4, the two arrays would be
:
7771 # s2 | a0 a1 a2 a3 | b0 b1 b2 b3 | c0 c1 c2 c3
7772 #
------+-------------+-------------+------------
7773 # s1
[0] | a0 a0 a0 a3 | a3 a3 b2 b2 | b2 c1 c1 c1
7774 # s1
[1] | a1 a1 a1 b0 | b0 b0 b3 b3 | b3 c2 c2 c2
7775 # s1
[2] | a2 a2 a2 b1 | b1 b1 c0 c0 | c0 c3 c3 c3
7777 # Each s1 permute requires only two of a
, b and c.
7779 # The distance between the start of vector n in s1
[0] and the start
7780 # of vector n in s2 is
:
7782 # A
= (n
* VF
) % COUNT
7784 # The corresponding value
for the end of vector n is
:
7786 # B
= (n
* VF
+ VF
- 1) % COUNT
7788 # Subtracting i from each value gives the corresponding difference
7789 #
for s1
[i
]. The condition being tested by this function is false
7790 # iff A
- i
> 0 and B
- i
< 0 for some i and n
, such that the first
7791 # element
for s1
[i
] comes from vector n
- 1 of s2 and the last element
7792 # comes from vector n
+ 1 of s2. The condition is therefore true iff
7793 # A
<= B
for all n. This is turn means the condition is true iff
:
7795 #
(n
* VF
) % COUNT + (VF
- 1) % COUNT < COUNT
7797 #
for all n.
COUNT - (n
* VF
) % COUNT is bounded by gcd
(VF
, COUNT),
7798 # and will be that value
for at least one n in
[0, COUNT), so we want
:
7800 #
(VF
- 1) % COUNT < gcd
(VF
, COUNT)
7802 proc vect_perm_supported
{ count element_bits
} {
7803 set vector_bits
[lindex
[available_vector_sizes
] 0]
7804 # The number of vectors has to be a power of
2 when permuting
7805 #
variable-length vectors.
7806 if { $vector_bits
<= 0 && ($
count & -$
count) != $
count } {
7809 set vf
[expr
{ $vector_bits
/ $element_bits
}]
7811 # Compute gcd
(VF
, COUNT).
7814 while { $temp1
> 0 } {
7815 set temp2
[expr
{ $gcd
% $temp1
}]
7819 return [expr
{ ($vf
- 1) % $
count < $gcd
}]
7822 #
Return 1 if the target supports SLP permutation of
3 vectors when each
7823 # element has
32 bits.
7825 proc check_effective_target_vect_perm3_int
{ } {
7826 return [expr
{ [check_effective_target_vect_perm
]
7827 && [vect_perm_supported
3 32] }]
7830 #
Return 1 if the target plus current options supports vector permutation
7831 #
on byte
-sized elements
, 0 otherwise.
7833 # This won
't change for different subtargets so cache the result.
7835 proc check_effective_target_vect_perm_byte { } {
7836 return [check_cached_effective_target_indexed vect_perm_byte {
7837 expr { ([is-effective-target arm_neon]
7838 && [is-effective-target arm_little_endian])
7839 || ([istarget aarch64*-*-*]
7840 && [is-effective-target aarch64_little_endian])
7841 || [istarget powerpc*-*-*]
7842 || ([istarget mips-*.*]
7843 && [et-is-effective-target mips_msa])
7844 || ([istarget s390*-*-*]
7845 && [check_effective_target_s390_vx])
7846 || [istarget amdgcn-*-*]
7847 || ([istarget riscv*-*-*]
7848 && [check_effective_target_riscv_v])
7849 || ([istarget loongarch*-*-*]
7850 && [check_effective_target_loongarch_sx]) }}]
7853 # Return 1 if the target supports SLP permutation of 3 vectors when each
7854 # element has 8 bits.
7856 proc check_effective_target_vect_perm3_byte { } {
7857 return [expr { [check_effective_target_vect_perm_byte]
7858 && [vect_perm_supported 3 8] }]
7861 # Return 1 if the target plus current options supports vector permutation
7862 # on short-sized elements, 0 otherwise.
7864 # This won't change
for different subtargets so
cache the result.
7866 proc check_effective_target_vect_perm_short
{ } {
7867 return [check_cached_effective_target_indexed vect_perm_short
{
7868 expr
{ ([is
-effective
-target arm_neon
]
7869 && [is
-effective
-target arm_little_endian
])
7870 ||
([istarget aarch64
*-*-*]
7871 && [is
-effective
-target aarch64_little_endian
])
7872 ||
[istarget powerpc
*-*-*]
7873 ||
(([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
7874 && [check_ssse3_available
])
7875 ||
([istarget mips
*-*-*]
7876 && [et
-is
-effective
-target mips_msa
])
7877 ||
([istarget s390
*-*-*]
7878 && [check_effective_target_s390_vx
])
7879 ||
[istarget amdgcn
-*-*]
7880 ||
([istarget riscv
*-*-*]
7881 && [check_effective_target_riscv_v
])
7882 ||
([istarget loongarch
*-*-*]
7883 && [check_effective_target_loongarch_sx
]) }}]
7886 #
Return 1 if the target supports SLP permutation of
3 vectors when each
7887 # element has
16 bits.
7889 proc check_effective_target_vect_perm3_short
{ } {
7890 return [expr
{ [check_effective_target_vect_perm_short
]
7891 && [vect_perm_supported
3 16] }]
7894 #
Return 1 if the target plus current options supports folding of
7895 # copysign into XORSIGN.
7897 # This won
't change for different subtargets so cache the result.
7899 proc check_effective_target_xorsign { } {
7900 return [check_cached_effective_target_indexed xorsign {
7901 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7902 || [istarget aarch64*-*-*] || [istarget arm*-*-*] }}]
7905 # Return 1 if the target plus current options supports folding of
7906 # copysign into IFN_COPYSIGN.
7908 # This won't change
for different subtargets so
cache the result.
7910 proc check_effective_target_ifn_copysign
{ } {
7911 return [check_cached_effective_target_indexed ifn_copysign
{
7913 (([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
7914 && [is
-effective
-target sse
])
7915 ||
([istarget loongarch
*-*-*]
7916 && [check_effective_target_hard_float
])
7917 ||
([istarget powerpc
*-*-*]
7918 && ![istarget powerpc
-*-linux
*paired
*])
7919 ||
[istarget alpha
*-*-*]
7920 ||
[istarget aarch64
*-*-*]
7921 ||
[is
-effective
-target arm_neon
]
7922 ||
([istarget s390
*-*-*]
7923 && [check_effective_target_s390_vx
])
7924 ||
([istarget riscv
*-*-*]
7925 && [check_effective_target_hard_float
])
7929 #
Return 1 if the target plus current options supports a vector
7930 # widening summation of
*short
* args into
*int* result
, 0 otherwise.
7932 # This won
't change for different subtargets so cache the result.
7934 proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } {
7935 return [check_cached_effective_target_indexed vect_widen_sum_hi_to_si_pattern {
7936 expr { [istarget powerpc*-*-*]
7937 || ([istarget aarch64*-*-*]
7938 && ![check_effective_target_aarch64_sve])
7939 || [is-effective-target arm_neon]
7940 || [istarget ia64-*-*] }}]
7943 # Return 1 if the target plus current options supports a vector
7944 # widening summation of *short* args into *int* result, 0 otherwise.
7945 # A target can also support this widening summation if it can support
7946 # promotion (unpacking) from shorts to ints.
7948 # This won't change
for different subtargets so
cache the result.
7950 proc check_effective_target_vect_widen_sum_hi_to_si
{ } {
7951 return [check_cached_effective_target_indexed vect_widen_sum_hi_to_si
{
7952 expr
{ [check_effective_target_vect_unpack
]
7953 ||
[istarget powerpc
*-*-*]
7954 ||
[istarget ia64
-*-*]
7955 ||
[istarget loongarch
*-*-*]
7956 ||
[istarget riscv
*-*-*] }}]
7959 #
Return 1 if the target plus current options supports a vector
7960 # widening summation of
*char
* args into
*short
* result
, 0 otherwise.
7961 # A target can also support this widening summation
if it can support
7962 # promotion
(unpacking
) from chars to shorts.
7964 # This won
't change for different subtargets so cache the result.
7966 proc check_effective_target_vect_widen_sum_qi_to_hi { } {
7967 return [check_cached_effective_target_indexed vect_widen_sum_qi_to_hi {
7968 expr { [check_effective_target_vect_unpack]
7969 || [is-effective-target arm_neon]
7970 || [istarget ia64-*-*]
7971 || [istarget riscv*-*-*]
7972 || [istarget loongarch*-*-*] }}]
7975 # Return 1 if the target plus current options supports a vector
7976 # widening summation of *char* args into *int* result, 0 otherwise.
7978 # This won't change
for different subtargets so
cache the result.
7980 proc check_effective_target_vect_widen_sum_qi_to_si
{ } {
7981 return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si
{
7982 expr
{ [istarget powerpc
*-*-*]
7983 ||
[istarget loongarch
*-*-*]
7984 ||
[istarget riscv
*-*-*] }}]
7987 #
Return 1 if the target plus current options supports a vector
7988 # widening multiplication of
*char
* args into
*short
* result
, 0 otherwise.
7989 # A target can also support this widening multplication
if it can support
7990 # promotion
(unpacking
) from chars to shorts
, and vect_short_mult
(non
-widening
7991 # multiplication of shorts
).
7993 # This won
't change for different subtargets so cache the result.
7996 proc check_effective_target_vect_widen_mult_qi_to_hi { } {
7997 return [check_cached_effective_target_indexed vect_widen_mult_qi_to_hi {
7998 expr { ([check_effective_target_vect_unpack]
7999 && [check_effective_target_vect_short_mult])
8000 || ([istarget powerpc*-*-*]
8001 || ([istarget aarch64*-*-*]
8002 && ![check_effective_target_aarch64_sve])
8003 || [is-effective-target arm_neon]
8004 || ([istarget s390*-*-*]
8005 && [check_effective_target_s390_vx]))
8006 || [istarget amdgcn-*-*] }}]
8009 # Return 1 if the target plus current options supports a vector
8010 # widening multiplication of *short* args into *int* result, 0 otherwise.
8011 # A target can also support this widening multplication if it can support
8012 # promotion (unpacking) from shorts to ints, and vect_int_mult (non-widening
8013 # multiplication of ints).
8015 # This won't change
for different subtargets so
cache the result.
8018 proc check_effective_target_vect_widen_mult_hi_to_si
{ } {
8019 return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si
{
8020 expr
{ ([check_effective_target_vect_unpack
]
8021 && [check_effective_target_vect_int_mult
])
8022 ||
([istarget powerpc
*-*-*]
8023 ||
[istarget ia64
-*-*]
8024 ||
([istarget aarch64
*-*-*]
8025 && ![check_effective_target_aarch64_sve
])
8026 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8027 ||
[is
-effective
-target arm_neon
]
8028 ||
([istarget s390
*-*-*]
8029 && [check_effective_target_s390_vx
]))
8030 ||
[istarget amdgcn
-*-*] }}]
8033 #
Return 1 if the target plus current options supports a vector
8034 # widening multiplication of
*char
* args into
*short
* result
, 0 otherwise.
8036 # This won
't change for different subtargets so cache the result.
8038 proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } {
8039 return [check_cached_effective_target_indexed vect_widen_mult_qi_to_hi_pattern {
8040 expr { [istarget powerpc*-*-*]
8041 || ([is-effective-target arm_neon]
8042 && [check_effective_target_arm_little_endian])
8043 || ([istarget s390*-*-*]
8044 && [check_effective_target_s390_vx])
8045 || [istarget loongarch*-*-*]
8046 || [istarget amdgcn-*-*] }}]
8049 # Return 1 if the target plus current options supports a vector
8050 # widening multiplication of *short* args into *int* result, 0 otherwise.
8052 # This won't change
for different subtargets so
cache the result.
8054 proc check_effective_target_vect_widen_mult_hi_to_si_pattern
{ } {
8055 return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si_pattern
{
8056 expr
{ [istarget powerpc
*-*-*]
8057 ||
[istarget ia64
-*-*]
8058 ||
[istarget loongarch
*-*-*]
8059 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8060 ||
([is
-effective
-target arm_neon
]
8061 && [check_effective_target_arm_little_endian
])
8062 ||
([istarget s390
*-*-*]
8063 && [check_effective_target_s390_vx
])
8064 ||
[istarget amdgcn
-*-*] }}]
8067 #
Return 1 if the target plus current options supports a vector
8068 # widening multiplication of
*int* args into
*long
* result
, 0 otherwise.
8070 # This won
't change for different subtargets so cache the result.
8072 proc check_effective_target_vect_widen_mult_si_to_di_pattern { } {
8073 return [check_cached_effective_target_indexed vect_widen_mult_si_to_di_pattern {
8074 expr { [istarget ia64-*-*]
8075 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8076 || [istarget loongarch*-*-*]
8077 || ([istarget s390*-*-*]
8078 && [check_effective_target_s390_vx]) }}]
8081 # Return 1 if the target plus current options supports a vector
8082 # widening shift, 0 otherwise.
8084 # This won't change
for different subtargets so
cache the result.
8086 proc check_effective_target_vect_widen_shift
{ } {
8087 return [check_cached_effective_target_indexed vect_widen_shift
{
8088 expr
{ [is
-effective
-target arm_neon
] }}]
8091 #
Return 1 if the target plus current options supports a vector
8092 # dot
-product of signed chars
, 0 otherwise.
8094 # This won
't change for different subtargets so cache the result.
8096 proc check_effective_target_vect_sdot_qi { } {
8097 return [check_cached_effective_target_indexed vect_sdot_qi {
8098 expr { [istarget ia64-*-*]
8099 || [istarget aarch64*-*-*]
8100 || [istarget arm*-*-*]
8101 || ([istarget mips*-*-*]
8102 && [et-is-effective-target mips_msa])
8103 || ([istarget riscv*-*-*]
8104 && [check_effective_target_riscv_v])
8105 || ([istarget loongarch*-*-*]
8106 && [check_effective_target_loongarch_sx]) }}]
8109 # Return 1 if the target plus current options supports a vector
8110 # dot-product of unsigned chars, 0 otherwise.
8112 # This won't change
for different subtargets so
cache the result.
8114 proc check_effective_target_vect_udot_qi
{ } {
8115 return [check_cached_effective_target_indexed vect_udot_qi
{
8116 expr
{ [istarget powerpc
*-*-*]
8117 ||
[istarget aarch64
*-*-*]
8118 ||
[istarget arm
*-*-*]
8119 ||
[istarget ia64
-*-*]
8120 ||
([istarget mips
*-*-*]
8121 && [et
-is
-effective
-target mips_msa
])
8122 ||
([istarget riscv
*-*-*]
8123 && [check_effective_target_riscv_v
])
8124 ||
([istarget loongarch
*-*-*]
8125 && [check_effective_target_loongarch_sx
]) }}]
8128 #
Return 1 if the target plus current options supports a vector
8129 # dot
-product where one operand of the multiply is signed char
8130 # and the other unsigned chars
, 0 otherwise.
8132 # This won
't change for different subtargets so cache the result.
8134 proc check_effective_target_vect_usdot_qi { } {
8135 return [check_cached_effective_target_indexed vect_usdot_qi {
8136 expr { [istarget aarch64*-*-*]
8137 || [istarget arm*-*-*] }}]
8141 # Return 1 if the target plus current options supports a vector
8142 # dot-product of signed shorts, 0 otherwise.
8144 # This won't change
for different subtargets so
cache the result.
8146 proc check_effective_target_vect_sdot_hi
{ } {
8147 return [check_cached_effective_target_indexed vect_sdot_hi
{
8148 expr
{ ([istarget powerpc
*-*-*] && ![istarget powerpc
-*-linux
*paired
*])
8149 ||
[istarget ia64
-*-*]
8150 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8151 ||
([istarget mips
*-*-*]
8152 && [et
-is
-effective
-target mips_msa
])
8153 ||
([istarget riscv
*-*-*]
8154 && [check_effective_target_riscv_v
])
8155 ||
([istarget loongarch
*-*-*]
8156 && [check_effective_target_loongarch_sx
]) }}]
8159 #
Return 1 if the target plus current options supports a vector
8160 # dot
-product of unsigned shorts
, 0 otherwise.
8162 # This won
't change for different subtargets so cache the result.
8164 proc check_effective_target_vect_udot_hi { } {
8165 return [check_cached_effective_target_indexed vect_udot_hi {
8166 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8167 || ([istarget mips*-*-*]
8168 && [et-is-effective-target mips_msa])
8169 || ([istarget riscv*-*-*]
8170 && [check_effective_target_riscv_v])
8171 || ([istarget loongarch*-*-*]
8172 && [check_effective_target_loongarch_sx]) }}]
8175 # Return 1 if the target plus current options supports a vector
8176 # sad operation of unsigned chars, 0 otherwise.
8178 # This won't change
for different subtargets so
cache the result.
8180 proc check_effective_target_vect_usad_char
{ } {
8181 return [check_cached_effective_target_indexed vect_usad_char
{
8182 expr
{ [istarget i?
86-*-*]
8183 ||
[istarget x86_64
-*-*]
8184 ||
([istarget aarch64
*-*-*]
8185 && ![check_effective_target_aarch64_sve
])
8186 ||
([istarget powerpc
*-*-*]
8187 && [check_p9vector_hw_available
])
8188 ||
([istarget riscv
*-*-*]
8189 && [check_effective_target_riscv_v
])
8190 ||
([istarget loongarch
*-*-*]
8191 && [check_effective_target_loongarch_sx
]) }}]
8194 #
Return 1 if the target plus current options supports both signed
8195 # and unsigned
average operations
on vectors of bytes.
8197 proc check_effective_target_vect_avg_qi
{} {
8198 return [expr
{ ([istarget aarch64
*-*-*]
8199 && ![check_effective_target_aarch64_sve1_only
])
8200 ||
([istarget riscv
*-*-*]
8201 && [check_effective_target_riscv_v
])
8202 ||
([istarget loongarch
*-*-*]
8203 && [check_effective_target_loongarch_sx
]) }]
8206 #
Return 1 if the target plus current options supports both signed
8207 # and unsigned multiply
-high
-with
-round-and
-scale operations
8208 #
on vectors of half
-words.
8210 proc check_effective_target_vect_mulhrs_hi
{} {
8211 return [expr
{ [istarget aarch64
*-*-*]
8212 && [check_effective_target_aarch64_sve2
] }]
8215 #
Return 1 if the target plus current options supports signed division
8216 # by power
-of
-2 operations
on vectors of
4-byte integers.
8218 proc check_effective_target_vect_sdiv_pow2_si
{} {
8219 return [expr
{ ([istarget aarch64
*-*-*]
8220 && [check_effective_target_aarch64_sve
]) }]
8223 #
Return 1 if the target plus current options supports a vector
8224 # demotion
(packing
) of shorts
(to chars
) and ints
(to shorts
)
8225 # using modulo arithmetic
, 0 otherwise.
8227 # This won
't change for different subtargets so cache the result.
8229 proc check_effective_target_vect_pack_trunc { } {
8230 return [check_cached_effective_target_indexed vect_pack_trunc {
8231 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8232 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8233 || [istarget aarch64*-*-*]
8234 || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]
8235 && [check_effective_target_arm_little_endian])
8236 || ([istarget mips*-*-*]
8237 && [et-is-effective-target mips_msa])
8238 || ([istarget s390*-*-*]
8239 && [check_effective_target_s390_vx])
8240 || [istarget amdgcn*-*-*]
8241 || ([istarget riscv*-*-*]
8242 && [check_effective_target_riscv_v])
8243 || ([istarget loongarch*-*-*]
8244 && [check_effective_target_loongarch_sx]) }}]
8247 # Return 1 if the target plus current options supports a vector
8248 # promotion (unpacking) of chars (to shorts) and shorts (to ints), 0 otherwise.
8250 # This won't change
for different subtargets so
cache the result.
8252 proc check_effective_target_vect_unpack
{ } {
8253 return [check_cached_effective_target_indexed vect_unpack
{
8254 expr
{ ([istarget powerpc
*-*-*] && ![istarget powerpc
-*paired
*])
8255 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8256 ||
[istarget ia64
-*-*]
8257 ||
[istarget aarch64
*-*-*]
8258 ||
([istarget mips
*-*-*]
8259 && [et
-is
-effective
-target mips_msa
])
8260 ||
([istarget arm
*-*-*] && [check_effective_target_arm_neon_ok
]
8261 && [check_effective_target_arm_little_endian
])
8262 ||
([istarget s390
*-*-*]
8263 && [check_effective_target_s390_vx
])
8264 ||
[istarget amdgcn
*-*-*]
8265 ||
([istarget riscv
*-*-*]
8266 && [check_effective_target_riscv_v
])
8267 ||
([istarget loongarch
*-*-*]
8268 && [check_effective_target_loongarch_sx
]) }}]
8271 #
Return 1 if the target plus current options does not guarantee
8272 # that its STACK_BOUNDARY is
>= the reguired vector alignment.
8274 # This won
't change for different subtargets so cache the result.
8276 proc check_effective_target_unaligned_stack { } {
8277 return [check_cached_effective_target_indexed unaligned_stack { expr 0 }]
8280 # Return 1 if the target plus current options does not support a vector
8281 # alignment mechanism, 0 otherwise.
8283 # This won't change
for different subtargets so
cache the result.
8285 proc check_effective_target_vect_no_align
{ } {
8286 return [check_cached_effective_target_indexed vect_no_align
{
8287 expr
{ [istarget mipsisa64
*-*-*]
8288 ||
[istarget mips
-sde
-elf
]
8289 ||
[istarget sparc
*-*-*]
8290 ||
[istarget ia64
-*-*]
8291 ||
[check_effective_target_arm_vect_no_misalign
]
8292 ||
([istarget powerpc
*-*-*] && [check_p8vector_hw_available
])
8293 ||
([istarget mips
*-*-*]
8294 && [et
-is
-effective
-target mips_loongson_mmi
]) }}]
8297 #
Return 1 if the target supports a vector misalign access
, 0 otherwise.
8299 # This won
't change for different subtargets so cache the result.
8301 proc check_effective_target_vect_hw_misalign { } {
8302 return [check_cached_effective_target_indexed vect_hw_misalign {
8303 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
8304 || ([istarget powerpc*-*-*] && [check_p8vector_hw_available])
8305 || [istarget aarch64*-*-*]
8306 || ([istarget mips*-*-*] && [et-is-effective-target mips_msa])
8307 || ([istarget s390*-*-*]
8308 && [check_effective_target_s390_vx])
8309 || ([istarget riscv*-*-*])
8310 || ([istarget loongarch*-*-*])
8311 || [istarget amdgcn*-*-*] } {
8314 if { [istarget arm*-*-*]
8315 && ![check_effective_target_arm_vect_no_misalign] } {
8323 # Return 1 if arrays are aligned to the vector alignment
8324 # boundary, 0 otherwise.
8326 proc check_effective_target_vect_aligned_arrays { } {
8327 set et_vect_aligned_arrays 0
8328 if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
8329 && !([is-effective-target ia32]
8330 || ([check_avx_available] && ![check_prefer_avx128]))) } {
8331 set et_vect_aligned_arrays 1
8334 verbose "check_effective_target_vect_aligned_arrays:\
8335 returning $et_vect_aligned_arrays" 2
8336 return $et_vect_aligned_arrays
8339 # Return 1 if the biggest alignment required by target is 1 * BITS_PER_UNIT.
8340 # In such case the target does not impose any alignment constraints.
8342 proc check_effective_target_no_alignment_constraints { } {
8343 return [check_runtime_nocache no_alignment_constraints {
8347 return __BIGGEST_ALIGNMENT__ == 1 ? 0 : 1;
8352 # Return 1 if types of size 32 bit or less are naturally aligned
8353 # (aligned to their type-size), 0 otherwise.
8355 # This won't change
for different subtargets so
cache the result.
8357 proc check_effective_target_natural_alignment_32
{ } {
8358 # FIXME
: 32bit powerpc
: guaranteed only
if MASK_ALIGN_NATURAL
/POWER.
8359 # FIXME
: m68k has
-malign
-int
8360 return [check_cached_effective_target_indexed natural_alignment_32
{
8361 if { ([istarget
*-*-darwin
*] && [is
-effective
-target lp64
])
8362 ||
[istarget avr
-*-*]
8363 ||
[istarget m68k
-*-linux
*]
8364 ||
[istarget pru
-*-*]
8365 ||
[istarget stormy16
-*-*]
8366 ||
[istarget rl78
-*-*]
8367 ||
[istarget pdp11
-*-*]
8368 ||
[istarget msp430
-*-*]
8369 ||
[istarget m32c
-*-*]
8370 ||
[istarget cris
-*-*] } {
8378 #
Return 1 if types of size
64 bit or less are naturally aligned
(aligned to their
8379 # type
-size
), 0 otherwise.
8381 # This won
't change for different subtargets so cache the result.
8383 proc check_effective_target_natural_alignment_64 { } {
8384 return [check_cached_effective_target_indexed natural_alignment_64 {
8385 expr { [is-effective-target natural_alignment_32]
8386 && [is-effective-target lp64] && ![istarget *-*-darwin*] }
8390 # Return 1 if all vector types are naturally aligned (aligned to their
8391 # type-size), 0 otherwise.
8393 proc check_effective_target_vect_natural_alignment { } {
8394 set et_vect_natural_alignment 1
8395 if { [check_effective_target_arm_eabi]
8396 || [istarget nvptx-*-*]
8397 || [istarget s390*-*-*]
8398 || [istarget amdgcn-*-*] } {
8399 set et_vect_natural_alignment 0
8401 verbose "check_effective_target_vect_natural_alignment:\
8402 returning $et_vect_natural_alignment" 2
8403 return $et_vect_natural_alignment
8406 # Return true if the target supports the check_raw_ptrs and check_war_ptrs
8407 # optabs on vectors.
8409 proc check_effective_target_vect_check_ptrs { } {
8410 return [check_effective_target_aarch64_sve2]
8413 # Return true if fully-masked loops are supported.
8415 proc check_effective_target_vect_fully_masked { } {
8416 return [expr { [check_effective_target_aarch64_sve]
8417 || [istarget amdgcn*-*-*]
8418 || [check_effective_target_riscv_v] }]
8421 # Return true if the target supports the @code{len_load} and
8422 # @code{len_store} optabs.
8424 proc check_effective_target_vect_len_load_store { } {
8425 return [expr { [check_effective_target_has_arch_pwr9]
8426 || [check_effective_target_s390_vx]
8427 || [check_effective_target_riscv_v] }]
8430 # Return the value of parameter vect-partial-vector-usage specified for
8431 # target by checking the output of "-Q --help=params". Return zero if
8432 # the desirable pattern isn't found.
8434 proc check_vect_partial_vector_usage
{ } {
8437 return [check_cached_effective_target vect_partial_vector_usage
{
8438 set result
[check_compile vect_partial_vector_usage assembly
{
8440 } "-Q --help=params" ]
8442 #
Get compiler emitted messages and
delete generated file.
8443 set lines
[lindex $result
0]
8444 set output
[lindex $result
1]
8445 remote_file build
delete $output
8447 set pattern
{=vect
-partial
-vector
-usage
=<0,2>\s
+([0-2])}
8448 # Capture the usage value to val
, set it to zero
if not found.
8449 if { ![regexp $pattern $lines whole val
] } then {
8457 #
Return true
if the target supports loop vectorization with partial vectors
8458 # and @code
{vect
-partial
-vector
-usage
} is
set to
1.
8460 proc check_effective_target_vect_partial_vectors_usage_1
{ } {
8461 return [expr
{ ([check_effective_target_vect_fully_masked
]
8462 ||
[check_effective_target_vect_len_load_store
])
8463 && [check_vect_partial_vector_usage
] == 1 }]
8466 #
Return true
if the target supports loop vectorization with partial vectors
8467 # and @code
{vect
-partial
-vector
-usage
} is
set to
2.
8469 proc check_effective_target_vect_partial_vectors_usage_2
{ } {
8470 return [expr
{ ([check_effective_target_vect_fully_masked
]
8471 ||
[check_effective_target_vect_len_load_store
])
8472 && [check_vect_partial_vector_usage
] == 2 }]
8475 #
Return true
if the target supports loop vectorization with partial vectors
8476 # and @code
{vect
-partial
-vector
-usage
} is nonzero.
8478 proc check_effective_target_vect_partial_vectors
{ } {
8479 return [expr
{ ([check_effective_target_vect_fully_masked
]
8480 ||
[check_effective_target_vect_len_load_store
])
8481 && [check_vect_partial_vector_usage
] != 0 }]
8484 #
Return 1 if the target doesn
't prefer any alignment beyond element
8485 # alignment during vectorization.
8487 proc check_effective_target_vect_element_align_preferred { } {
8488 return [expr { ([check_effective_target_aarch64_sve]
8489 && [check_effective_target_vect_variable_length])
8490 || [check_effective_target_riscv_v] }]
8493 # Return true if vectorization of v2qi/v4qi/v8qi/v16qi/v2hi store is enabed.
8494 # Return zero if the desirable pattern isn't found.
8495 # It
's used by Warray-bounds/Wstringop-overflow testcases which are
8496 # regressed by O2 vectorization, refer to PR102697/PR102462/PR102706
8497 proc check_vect_slp_store_usage { pattern macro } {
8500 set result [check_compile slp_aligned_store_usage assembly {
8501 extern void sink (void* );
8502 #define Ac8 (AC8){ 0, 1, 2, 3, 4, 5, 6, 7 }
8503 #define Ac16 (AC16){ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }
8505 typedef struct AC16 { char a[16]; } AC16;
8506 extern char a16[16];
8513 typedef struct AC8 { char a[8]; } AC8;
8527 extern void sink (void*);
8531 struct A1 a = { 0, { } };
8548 #define Ac4 (AC4){ 0, 1, 2, 3 }
8549 typedef struct AC4 { char a[4]; } AC4;
8597 *(short*) (b + 2) = 1;
8606 foo4_2 (struct Ax *p)
8612 struct A { int i; };
8613 struct B { int j; struct A a[4]; };
8620 char cbuf2[2 * sizeof (struct C)] = { };
8624 struct C *p = (struct C*)&cbuf2;
8631 struct A { int i; };
8632 struct B { int j; struct A a[2]; };
8639 char cbuf2[2 * sizeof (struct C)] = { };
8643 struct C *p = (struct C*)&cbuf2;
8649 } "-O2 -fopt-info-all -D$macro" ]
8651 # Get compiler emitted messages and delete generated file.
8652 set lines [lindex $result 0]
8653 set output [lindex $result 1]
8654 remote_file build delete $output
8656 # Check pattern exits in lines, set it to zero if not found.
8657 if { [regexp $pattern $lines] } then {
8664 # Return the true if target support vectorization of 2-byte char stores
8665 # with 2-byte aligned address at plain O2.
8666 # NB: This target should be removed after real issues are fixed for
8667 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8668 # this target since tests in check_vect_slp_store_usage
8669 # is the exact match of relative testcases
8670 proc check_effective_target_vect_slp_v2qi_store_align { } {
8671 set pattern {add new stmt: MEM <vector\(2\) char>}
8672 set macro "TEST_V2QI"
8673 return [check_cached_effective_target vect_slp_v2qi_store_align {
8674 expr [check_vect_slp_store_usage $pattern $macro] }]
8677 # Return the true if target support vectorization of 2-byte char stores
8678 # with unaligned address at plain O2.
8679 proc check_effective_target_vect_slp_v2qi_store_unalign { } {
8680 set pattern {add new stmt: MEM <vector\(2\) char>}
8681 set macro "TEST_V2QI_2"
8682 return [check_cached_effective_target vect_slp_v2qi_store_unalign {
8683 expr [check_vect_slp_store_usage $pattern $macro ] }]
8686 # Return the true if target support vectorization of 4-byte char stores
8687 # with 4-byte aligned address at plain O2.
8688 # NB: This target should be removed after real issues are fixed for
8689 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8690 # this target since tests in check_vect_slp_store_usage
8691 # is the exact match of relative testcases
8692 proc check_effective_target_vect_slp_v4qi_store_align { } {
8693 set pattern {add new stmt: MEM <vector\(4\) char>}
8694 set macro "TEST_V4QI"
8695 return [check_cached_effective_target vect_slp_v4qi_store_align {
8696 expr [check_vect_slp_store_usage $pattern $macro ] }]
8699 # Return the true if target support vectorization of 4-byte char stores
8700 # with unaligned address at plain O2.
8701 proc check_effective_target_vect_slp_v4qi_store_unalign { } {
8702 set pattern {add new stmt: MEM <vector\(4\) char>}
8703 set macro "TEST_V4QI_2"
8704 return [check_cached_effective_target vect_slp_v4qi_store_unalign {
8705 expr [check_vect_slp_store_usage $pattern $macro ] }]
8708 # Return the true if target support block move for
8709 # 8-byte aligned 4-byte size struct initialization.
8710 proc check_effective_target_struct_4char_block_move { } {
8711 set pattern {not vectorized: more than one data ref in stmt:}
8712 set macro "TEST_V4QI_3"
8713 return [check_cached_effective_target struct_4char_block_move {
8714 expr [check_vect_slp_store_usage $pattern $macro ] }]
8717 # Return the true if target support vectorization of 4-byte char stores
8718 # with unaligned address or store them with a constant pool at plain O2.
8719 proc check_effective_target_vect_slp_v4qi_store_unalign_1 { } {
8720 set pattern {add new stmt: MEM <vector\(4\) char>}
8721 set macro "TEST_V4QI_3"
8722 return [check_cached_effective_target vect_slp_v4qi_store_unalign_1 {
8723 expr { [check_vect_slp_store_usage $pattern $macro ]
8724 || [check_effective_target_struct_4char_block_move] } }]
8727 # Return the true if target support block move for
8728 # 8-byte aligned 8-byte size struct initialization.
8729 proc check_effective_target_struct_8char_block_move { } {
8730 set pattern {not vectorized: more than one data ref in stmt:}
8731 set macro "TEST_V8QI"
8732 return [check_cached_effective_target struct_8char_block_move {
8733 expr [check_vect_slp_store_usage $pattern $macro ] }]
8736 # Return the true if target support vectorization of 8-byte char stores
8737 # with unaligned address or store them with a constant pool at plain O2.
8738 # NB: This target should be removed after real issues are fixed for
8739 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8740 # this target since tests in check_vect_slp_store_usage
8741 # is the exact match of relative testcases
8742 proc check_effective_target_vect_slp_v8qi_store_unalign_1 { } {
8743 set pattern {add new stmt: MEM <vector\(8\) char>}
8744 set macro "TEST_V8QI"
8745 return [check_cached_effective_target vect_slp_v8qi_store_unalign_1 {
8746 expr { [check_vect_slp_store_usage $pattern $macro ]
8747 || [check_effective_target_struct_8char_block_move] } }]
8750 # Return the true if target support block move for
8751 # 8-byte aligned 16-byte size struct initialization.
8752 proc check_effective_target_struct_16char_block_move { } {
8753 set pattern {not vectorized: more than one data ref in stmt:}
8754 set macro "TEST_V16QI"
8755 return [check_cached_effective_target struct_16char_block_move {
8756 expr [check_vect_slp_store_usage $pattern $macro ] }]
8759 # Return the true if target support vectorization of 16-byte char stores
8760 # with unaligned address or store them with a constant pool at plain O2.
8761 # NB: This target should be removed after real issues are fixed for
8762 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8763 # this target since tests in check_vect_slp_store_usage
8764 # is the exact match of relative testcases
8765 proc check_effective_target_vect_slp_v16qi_store_unalign_1 { } {
8766 set pattern {add new stmt: MEM <vector\(16\) char>}
8767 set macro "TEST_V16QI"
8768 return [check_cached_effective_target vect_slp_v16qi_store_unalign_1 {
8769 expr { [check_vect_slp_store_usage $pattern $macro ]
8770 || [check_effective_target_struct_16char_block_move] } }]
8773 # Return the true if target support vectorization of 4-byte short stores
8774 # with unaligned address at plain O2.
8775 # NB: This target should be removed after real issues are fixed for
8776 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8777 # this target since tests in check_vect_slp_store_usage
8778 # is the exact match of relative testcases
8779 proc check_effective_target_vect_slp_v2hi_store_unalign { } {
8780 set pattern {add new stmt: MEM <vector\(2\) short int>}
8781 set macro "TEST_V2HI"
8782 return [check_cached_effective_target vect_slp_v2hi_store_unalign {
8783 expr [check_vect_slp_store_usage $pattern $macro ] }]
8786 # Return the true if target support vectorization of 4-byte short stores
8787 # with 4-byte aligned address at plain O2.
8788 proc check_effective_target_vect_slp_v2hi_store_align { } {
8789 set pattern {add new stmt: MEM <vector\(2\) short int>}
8790 set macro "TEST_V2HI_2"
8791 return [check_cached_effective_target vect_slp_v2hi_store_align {
8792 expr [check_vect_slp_store_usage $pattern $macro ] }]
8795 # Return the true if target support vectorization of 8-byte short stores
8796 # with unaligned address at plain O2.
8797 # NB: This target should be removed after real issues are fixed for
8798 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8799 # this target since tests in check_vect_slp_store_usage
8800 # is the exact match of relative testcases
8801 proc check_effective_target_vect_slp_v4hi_store_unalign { } {
8802 set pattern {add new stmt: MEM <vector\(4\) short int>}
8803 set macro "TEST_V4HI"
8804 return [check_cached_effective_target vect_slp_v4hi_store_unalign {
8805 expr [check_vect_slp_store_usage $pattern $macro ] }]
8808 # Return the true if target support vectorization of 8-byte int stores
8809 # with 8-byte aligned address at plain O2.
8810 # NB: This target should be removed after real issues are fixed for
8811 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8812 # this target since tests in check_vect_slp_store_usage
8813 # is the exact match of relative testcases
8814 proc check_effective_target_vect_slp_v2si_store_align { } {
8815 set pattern {add new stmt: MEM <vector\(2\) int>}
8816 set macro "TEST_V2SI"
8817 return [check_cached_effective_target vect_slp_v2si_store_align {
8818 expr [check_vect_slp_store_usage $pattern $macro ] }]
8821 # Return the true if target support vectorization of 16-byte int stores
8822 # with unaligned address at plain O2.
8823 # NB: This target should be removed after real issues are fixed for
8824 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8825 # this target since tests in check_vect_slp_store_usage
8826 # is the exact match of relative testcases
8827 proc check_effective_target_vect_slp_v4si_store_unalign { } {
8828 set pattern {add new stmt: MEM <vector\(4\) int>}
8829 set macro "TEST_V4SI"
8830 return [check_cached_effective_target vect_slp_v4si_store_unalign {
8831 expr [check_vect_slp_store_usage $pattern $macro ] }]
8834 # Return 1 if we can align stack data to the preferred vector alignment.
8836 proc check_effective_target_vect_align_stack_vars { } {
8837 if { [check_effective_target_aarch64_sve] } {
8838 return [check_effective_target_vect_variable_length]
8843 # Return 1 if vector alignment (for types of size 32 bit or less) is reachable, 0 otherwise.
8845 proc check_effective_target_vector_alignment_reachable { } {
8846 set et_vector_alignment_reachable 0
8847 if { [check_effective_target_vect_aligned_arrays]
8848 || [check_effective_target_natural_alignment_32] } {
8849 set et_vector_alignment_reachable 1
8851 verbose "check_effective_target_vector_alignment_reachable:\
8852 returning $et_vector_alignment_reachable" 2
8853 return $et_vector_alignment_reachable
8856 # Return 1 if vector alignment for 64 bit is reachable, 0 otherwise.
8858 proc check_effective_target_vector_alignment_reachable_for_64bit { } {
8859 set et_vector_alignment_reachable_for_64bit 0
8860 if { [check_effective_target_vect_aligned_arrays]
8861 || [check_effective_target_natural_alignment_64] } {
8862 set et_vector_alignment_reachable_for_64bit 1
8864 verbose "check_effective_target_vector_alignment_reachable_for_64bit:\
8865 returning $et_vector_alignment_reachable_for_64bit" 2
8866 return $et_vector_alignment_reachable_for_64bit
8869 # Return 1 if the target only requires element alignment for vector accesses
8871 proc check_effective_target_vect_element_align { } {
8872 return [check_cached_effective_target_indexed vect_element_align {
8873 expr { ([istarget arm*-*-*]
8874 && ![check_effective_target_arm_vect_no_misalign])
8875 || [check_effective_target_vect_hw_misalign] }}]
8878 # Return 1 if we expect to see unaligned accesses in at least some
8881 proc check_effective_target_vect_unaligned_possible { } {
8882 return [expr { ![check_effective_target_vect_element_align_preferred]
8883 && (![check_effective_target_vect_no_align]
8884 || [check_effective_target_vect_hw_misalign]) }]
8887 # Return 1 if the target supports vector LOAD_LANES operations, 0 otherwise.
8889 proc check_effective_target_vect_load_lanes { } {
8890 # We don't support load_lanes correctly
on big
-endian arm.
8891 return [check_cached_effective_target vect_load_lanes
{
8892 expr
{ ([check_effective_target_arm_little_endian
]
8893 && [check_effective_target_arm_neon_ok
])
8894 ||
[istarget aarch64
*-*-*]
8895 ||
[istarget riscv
*-*-*] }}]
8898 #
Return 1 if the target supports vector masked loads.
8900 proc check_effective_target_vect_masked_load
{ } {
8901 return [expr
{ [check_avx_available
]
8902 ||
[check_effective_target_aarch64_sve
]
8903 ||
[istarget amdgcn
*-*-*]
8904 ||
[check_effective_target_riscv_v
] } ]
8907 #
Return 1 if the target supports vector masked stores.
8909 proc check_effective_target_vect_masked_store
{ } {
8910 return [expr
{ [check_avx_available
]
8911 ||
[check_effective_target_aarch64_sve
]
8912 ||
[istarget amdgcn
*-*-*]
8913 ||
[check_effective_target_riscv_v
] }]
8916 #
Return 1 if the target supports vector gather loads via internal functions.
8918 proc check_effective_target_vect_gather_load_ifn
{ } {
8919 return [expr
{ [check_effective_target_aarch64_sve
]
8920 ||
[istarget amdgcn
*-*-*]
8921 ||
[check_effective_target_riscv_v
] }]
8924 #
Return 1 if the target supports vector scatter stores.
8926 proc check_effective_target_vect_scatter_store
{ } {
8927 return [expr
{ [check_effective_target_aarch64_sve
]
8928 ||
[istarget amdgcn
*-*-*]
8929 ||
[check_effective_target_riscv_v
]
8930 ||
[check_effective_target_loongarch_sx
] }]
8933 #
Return 1 if the target supports vector conditional operations
, 0 otherwise.
8935 proc check_effective_target_vect_condition
{ } {
8936 return [check_cached_effective_target_indexed vect_condition
{
8937 expr
{ [istarget aarch64
*-*-*]
8938 ||
[istarget powerpc
*-*-*]
8939 ||
[istarget ia64
-*-*]
8940 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8941 ||
([istarget mips
*-*-*]
8942 && [et
-is
-effective
-target mips_msa
])
8943 ||
([istarget arm
*-*-*]
8944 && [check_effective_target_arm_neon_ok
])
8945 ||
([istarget s390
*-*-*]
8946 && [check_effective_target_s390_vx
])
8947 ||
[istarget amdgcn
-*-*]
8948 ||
([istarget riscv
*-*-*]
8949 && [check_effective_target_riscv_v
])
8950 ||
([istarget loongarch
*-*-*]
8951 && [check_effective_target_loongarch_sx
]) }}]
8954 #
Return 1 if the target supports vector conditional operations where
8955 # the comparison has different type from the lhs
, 0 otherwise.
8957 proc check_effective_target_vect_cond_mixed
{ } {
8958 return [check_cached_effective_target_indexed vect_cond_mixed
{
8959 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8960 ||
[istarget aarch64
*-*-*]
8961 ||
[istarget powerpc
*-*-*]
8962 ||
([istarget arm
*-*-*]
8963 && [check_effective_target_arm_neon_ok
])
8964 ||
([istarget mips
*-*-*]
8965 && [et
-is
-effective
-target mips_msa
])
8966 ||
([istarget s390
*-*-*]
8967 && [check_effective_target_s390_vx
])
8968 ||
[istarget amdgcn
-*-*]
8969 ||
([istarget riscv
*-*-*]
8970 && [check_effective_target_riscv_v
])
8971 ||
([istarget loongarch
*-*-*]
8972 && [check_effective_target_loongarch_sx
]) }}]
8975 #
Return 1 if the target supports vector char multiplication
, 0 otherwise.
8977 proc check_effective_target_vect_char_mult
{ } {
8978 return [check_cached_effective_target_indexed vect_char_mult
{
8979 expr
{ [istarget aarch64
*-*-*]
8980 ||
[istarget ia64
-*-*]
8981 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8982 ||
[check_effective_target_arm32
]
8983 ||
[check_effective_target_powerpc_altivec
]
8984 ||
([istarget mips
*-*-*]
8985 && [et
-is
-effective
-target mips_msa
])
8986 ||
([istarget s390
*-*-*]
8987 && [check_effective_target_s390_vx
])
8988 ||
[istarget amdgcn
-*-*]
8989 ||
([istarget riscv
*-*-*]
8990 && [check_effective_target_riscv_v
])
8991 ||
([istarget loongarch
*-*-*]
8992 && [check_effective_target_loongarch_sx
]) }}]
8995 #
Return 1 if the target supports vector short multiplication
, 0 otherwise.
8997 proc check_effective_target_vect_short_mult
{ } {
8998 return [check_cached_effective_target_indexed vect_short_mult
{
8999 expr
{ [istarget ia64
-*-*]
9000 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9001 ||
[istarget powerpc
*-*-*]
9002 ||
[istarget aarch64
*-*-*]
9003 ||
[check_effective_target_arm32
]
9004 ||
([istarget mips
*-*-*]
9005 && ([et
-is
-effective
-target mips_msa
]
9006 ||
[et
-is
-effective
-target mips_loongson_mmi
]))
9007 ||
([istarget s390
*-*-*]
9008 && [check_effective_target_s390_vx
])
9009 ||
[istarget amdgcn
-*-*]
9010 ||
([istarget riscv
*-*-*]
9011 && [check_effective_target_riscv_v
])
9012 ||
([istarget loongarch
*-*-*]
9013 && [check_effective_target_loongarch_sx
]) }}]
9016 #
Return 1 if the target supports vector
int multiplication
, 0 otherwise.
9018 proc check_effective_target_vect_int_mult
{ } {
9019 return [check_cached_effective_target_indexed vect_int_mult
{
9020 expr
{ ([istarget powerpc
*-*-*] && ![istarget powerpc
-*-linux
*paired
*])
9021 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9022 ||
[istarget ia64
-*-*]
9023 ||
[istarget aarch64
*-*-*]
9024 ||
([istarget mips
*-*-*]
9025 && [et
-is
-effective
-target mips_msa
])
9026 ||
[check_effective_target_arm32
]
9027 ||
([istarget s390
*-*-*]
9028 && [check_effective_target_s390_vx
])
9029 ||
[istarget amdgcn
-*-*]
9030 ||
([istarget riscv
*-*-*]
9031 && [check_effective_target_riscv_v
])
9032 ||
([istarget loongarch
*-*-*]
9033 && [check_effective_target_loongarch_sx
]) }}]
9036 #
Return 1 if the target supports
64 bit hardware vector
9037 # multiplication of long operands with a long result
, 0 otherwise.
9039 # This can change
for different subtargets so
do not
cache the result.
9041 proc check_effective_target_vect_long_mult
{ } {
9042 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9043 ||
([istarget powerpc
*-*-*]
9044 && ([check_effective_target_ilp32
]
9045 ||
([check_effective_target_powerpc_vsx_ok
]
9046 && [check_effective_target_has_arch_pwr10
])))
9047 ||
[is
-effective
-target arm_neon
]
9048 ||
([istarget sparc
*-*-*] && [check_effective_target_ilp32
])
9049 ||
([istarget aarch64
*-*-*]
9050 && ([check_effective_target_ilp32
]
9051 ||
[check_effective_target_aarch64_sve
]))
9052 ||
([istarget mips
*-*-*]
9053 && [et
-is
-effective
-target mips_msa
])
9054 ||
([istarget riscv
*-*-*]
9055 && [check_effective_target_riscv_v
])
9056 ||
([istarget loongarch
*-*-*]
9057 && [check_effective_target_loongarch_sx
])
9058 ||
[istarget amdgcn
-*-*] } {
9064 verbose
"check_effective_target_vect_long_mult: returning $answer" 2
9068 #
Return 1 if the target supports vector even
/odd elements extraction
, 0 otherwise.
9070 proc check_effective_target_vect_extract_even_odd
{ } {
9071 return [check_cached_effective_target_indexed extract_even_odd
{
9072 expr
{ [istarget aarch64
*-*-*]
9073 ||
[istarget powerpc
*-*-*]
9074 ||
[is
-effective
-target arm_neon
]
9075 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9076 ||
[istarget ia64
-*-*]
9077 ||
([istarget mips
*-*-*]
9078 && ([et
-is
-effective
-target mips_msa
]
9079 ||
[et
-is
-effective
-target mpaired_single
]))
9080 ||
([istarget s390
*-*-*]
9081 && [check_effective_target_s390_vx
])
9082 ||
([istarget riscv
*-*-*]
9083 && [check_effective_target_riscv_v
])
9084 ||
([istarget loongarch
*-*-*]
9085 && [check_effective_target_loongarch_sx
]) }}]
9088 #
Return 1 if the target supports vector interleaving
, 0 otherwise.
9090 proc check_effective_target_vect_interleave
{ } {
9091 return [check_cached_effective_target_indexed vect_interleave
{
9092 expr
{ [istarget aarch64
*-*-*]
9093 ||
[istarget powerpc
*-*-*]
9094 ||
[is
-effective
-target arm_neon
]
9095 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9096 ||
[istarget ia64
-*-*]
9097 ||
([istarget mips
*-*-*]
9098 && ([et
-is
-effective
-target mpaired_single
]
9099 ||
[et
-is
-effective
-target mips_msa
]))
9100 ||
([istarget s390
*-*-*]
9101 && [check_effective_target_s390_vx
])
9102 ||
([istarget riscv
*-*-*]
9103 && [check_effective_target_riscv_v
])
9104 ||
([istarget loongarch
*-*-*]
9105 && [check_effective_target_loongarch_sx
]) }}]
9108 foreach N
{2 3 4 5 6 7 8} {
9109 eval
[string map
[list N $N
] {
9110 #
Return 1 if the target supports
2-vector interleaving
9111 proc check_effective_target_vect_stridedN
{ } {
9112 return [check_cached_effective_target_indexed vect_stridedN
{
9114 && [check_effective_target_vect_interleave
]
9115 && [check_effective_target_vect_extract_even_odd
] } {
9118 if { ([istarget arm
*-*-*]
9119 ||
[istarget aarch64
*-*-*]) && N
>= 2 && N
<= 4 } {
9122 if { ([istarget riscv
*-*-*]) && N
>= 2 && N
<= 8 } {
9125 if [check_effective_target_vect_fully_masked
] {
9134 #
Return the list of vector sizes
(in bits
) that each target supports.
9135 # A vector length of
"0" indicates variable-length vectors.
9137 proc available_vector_sizes
{ } {
9139 if { [istarget aarch64
*-*-*] } {
9140 if { [check_effective_target_aarch64_sve
] } {
9141 lappend result
[aarch64_sve_bits
]
9143 lappend result
128 64
9144 } elseif
{ [istarget arm
*-*-*]
9145 && [check_effective_target_arm_neon_ok
] } {
9146 lappend result
128 64
9147 } elseif
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*] } {
9148 if { [check_avx_available
] && ![check_prefer_avx128
] } {
9152 if { ![is
-effective
-target ia32
] } {
9156 } elseif
{ [istarget sparc
*-*-*] } {
9158 } elseif
{ [istarget amdgcn
*-*-*] } {
9159 #
6 different lane counts
, and
4 element sizes
9160 lappend result
4096 2048 1024 512 256 128 64 32 16 8 4 2
9161 } elseif
{ [istarget riscv
*-*-*] } {
9162 if { [check_effective_target_riscv_v
] } {
9163 lappend result
0 32 64 128
9167 # The traditional default asumption.
9173 #
Return 1 if the target supports multiple vector sizes
9175 proc check_effective_target_vect_multiple_sizes
{ } {
9176 return [expr
{ [llength
[available_vector_sizes
]] > 1 }]
9179 #
Return true
if variable-length vectors are supported.
9181 proc check_effective_target_vect_variable_length
{ } {
9182 return [expr
{ [lindex
[available_vector_sizes
] 0] == 0 }]
9185 #
Return 1 if the target supports vectors of
1024 bits.
9187 proc check_effective_target_vect1024
{ } {
9188 return [expr
{ [lsearch
-exact
[available_vector_sizes
] 1024] >= 0 }]
9191 #
Return 1 if the target supports vectors of
512 bits.
9193 proc check_effective_target_vect512
{ } {
9194 return [expr
{ [lsearch
-exact
[available_vector_sizes
] 512] >= 0 }]
9197 #
Return 1 if the target supports vectors of
256 bits.
9199 proc check_effective_target_vect256
{ } {
9200 return [expr
{ [lsearch
-exact
[available_vector_sizes
] 256] >= 0 }]
9203 #
Return 1 if the target supports vectors of
128 bits.
9205 proc check_effective_target_vect128
{ } {
9206 return [expr
{ [lsearch
-exact
[available_vector_sizes
] 128] >= 0 }]
9209 #
Return 1 if the target supports vectors of
64 bits.
9211 proc check_effective_target_vect64
{ } {
9212 return [expr
{ [lsearch
-exact
[available_vector_sizes
] 64] >= 0 }]
9215 #
Return 1 if the target supports vectors of
32 bits.
9217 proc check_effective_target_vect32
{ } {
9218 return [expr
{ [lsearch
-exact
[available_vector_sizes
] 32] >= 0 }]
9221 #
Return 1 if the target supports vector copysignf calls.
9223 proc check_effective_target_vect_call_copysignf
{ } {
9224 return [check_cached_effective_target_indexed vect_call_copysignf
{
9225 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9226 ||
[istarget powerpc
*-*-*]
9227 ||
[istarget aarch64
*-*-*]
9228 ||
[istarget amdgcn
-*-*]
9229 ||
([istarget riscv
*-*-*]
9230 && [check_effective_target_riscv_v
])
9231 ||
([istarget loongarch
*-*-*]
9232 && [check_effective_target_loongarch_sx
]) }}]
9235 #
Return 1 if the target supports hardware square root instructions.
9237 proc check_effective_target_sqrt_insn
{ } {
9238 return [check_cached_effective_target sqrt_insn
{
9239 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9240 ||
[check_effective_target_powerpc_sqrt
]
9241 ||
[istarget aarch64
*-*-*]
9242 ||
([istarget arm
*-*-*] && [check_effective_target_arm_vfp_ok
])
9243 ||
([istarget s390
*-*-*]
9244 && [check_effective_target_s390_vx
])
9245 ||
[istarget amdgcn
-*-*] }}]
9248 #
Return any additional options to enable square root intructions.
9250 proc add_options_for_sqrt_insn
{ flags
} {
9251 if { [istarget amdgcn
*-*-*] } {
9252 return "$flags -ffast-math"
9254 if { [istarget arm
*-*-*] } {
9255 return [add_options_for_arm_vfp
"$flags"]
9260 #
Return 1 if the target supports vector sqrtf calls.
9262 proc check_effective_target_vect_call_sqrtf
{ } {
9263 return [check_cached_effective_target_indexed vect_call_sqrtf
{
9264 expr
{ [istarget aarch64
*-*-*]
9265 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9266 ||
([istarget powerpc
*-*-*] && [check_vsx_hw_available
])
9267 ||
([istarget s390
*-*-*]
9268 && [check_effective_target_s390_vx
])
9269 ||
[istarget amdgcn
-*-*]
9270 ||
([istarget riscv
*-*-*]
9271 && [check_effective_target_riscv_v
])
9272 ||
([istarget loongarch
*-*-*]
9273 && [check_effective_target_loongarch_sx
]) }}]
9276 #
Return 1 if the target supports vector lrint calls.
9278 proc check_effective_target_vect_call_lrint
{ } {
9279 set et_vect_call_lrint
0
9280 if { (([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
9281 && [check_effective_target_ilp32
])
9282 ||
[istarget amdgcn
-*-*]
9283 ||
[istarget loongarch
*-*-*] } {
9284 set et_vect_call_lrint
1
9287 verbose
"check_effective_target_vect_call_lrint: returning $et_vect_call_lrint" 2
9288 return $et_vect_call_lrint
9291 #
Return 1 if the target supports vector btrunc calls.
9293 proc check_effective_target_vect_call_btrunc
{ } {
9294 return [check_cached_effective_target_indexed vect_call_btrunc
{
9295 expr
{ [istarget aarch64
*-*-*]
9296 ||
[istarget amdgcn
-*-*]
9297 ||
[istarget loongarch
*-*-*] }}]
9300 #
Return 1 if the target supports vector btruncf calls.
9302 proc check_effective_target_vect_call_btruncf
{ } {
9303 return [check_cached_effective_target_indexed vect_call_btruncf
{
9304 expr
{ [istarget aarch64
*-*-*]
9305 ||
[istarget amdgcn
-*-*]
9306 ||
[istarget loongarch
*-*-*] }}]
9309 #
Return 1 if the target supports vector ceil calls.
9311 proc check_effective_target_vect_call_ceil
{ } {
9312 return [check_cached_effective_target_indexed vect_call_ceil
{
9313 expr
{ [istarget aarch64
*-*-*]
9314 ||
[istarget amdgcn
-*-*]
9315 ||
[istarget loongarch
*-*-*] }}]
9318 #
Return 1 if the target supports vector ceilf calls.
9320 proc check_effective_target_vect_call_ceilf
{ } {
9321 return [check_cached_effective_target_indexed vect_call_ceilf
{
9322 expr
{ [istarget aarch64
*-*-*]
9323 ||
[istarget amdgcn
-*-*]
9324 ||
[istarget loongarch
*-*-*] }}]
9327 #
Return 1 if the target supports vector floor calls.
9329 proc check_effective_target_vect_call_floor
{ } {
9330 return [check_cached_effective_target_indexed vect_call_floor
{
9331 expr
{ [istarget aarch64
*-*-*]
9332 ||
[istarget amdgcn
-*-*]
9333 ||
[istarget loongarch
*-*-*] }}]
9336 #
Return 1 if the target supports vector floorf calls.
9338 proc check_effective_target_vect_call_floorf
{ } {
9339 return [check_cached_effective_target_indexed vect_call_floorf
{
9340 expr
{ [istarget aarch64
*-*-*]
9341 ||
[istarget amdgcn
-*-*]
9342 ||
[istarget loongarch
*-*-*] }}]
9345 #
Return 1 if the target supports vector lceil calls.
9347 proc check_effective_target_vect_call_lceil
{ } {
9348 return [check_cached_effective_target_indexed vect_call_lceil
{
9349 expr
{ [istarget aarch64
*-*-*]
9350 ||
[istarget loongarch
*-*-*] }}]
9353 #
Return 1 if the target supports vector lfloor calls.
9355 proc check_effective_target_vect_call_lfloor
{ } {
9356 return [check_cached_effective_target_indexed vect_call_lfloor
{
9357 expr
{ [istarget aarch64
*-*-*]
9358 ||
[istarget loongarch
*-*-*] }}]
9361 #
Return 1 if the target supports vector nearbyint calls.
9363 proc check_effective_target_vect_call_nearbyint
{ } {
9364 return [check_cached_effective_target_indexed vect_call_nearbyint
{
9365 expr
{ [istarget aarch64
*-*-*] }}]
9368 #
Return 1 if the target supports vector nearbyintf calls.
9370 proc check_effective_target_vect_call_nearbyintf
{ } {
9371 return [check_cached_effective_target_indexed vect_call_nearbyintf
{
9372 expr
{ [istarget aarch64
*-*-*] }}]
9375 #
Return 1 if the target supports vector
round calls.
9377 proc check_effective_target_vect_call_round
{ } {
9378 return [check_cached_effective_target_indexed vect_call_round
{
9379 expr
{ [istarget aarch64
*-*-*] }}]
9382 #
Return 1 if the target supports vector roundf calls.
9384 proc check_effective_target_vect_call_roundf
{ } {
9385 return [check_cached_effective_target_indexed vect_call_roundf
{
9386 expr
{ [istarget aarch64
*-*-*] }}]
9389 #
Return 1 if the target supports AND
, OR and XOR reduction.
9391 proc check_effective_target_vect_logical_reduc
{ } {
9392 return [expr
{ [check_effective_target_aarch64_sve
]
9393 ||
[istarget amdgcn
-*-*]
9394 ||
[check_effective_target_riscv_v
]
9395 ||
[check_effective_target_loongarch_sx
]
9396 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]}]
9399 #
Return 1 if the target supports the fold_extract_last optab.
9401 proc check_effective_target_vect_fold_extract_last
{ } {
9402 return [expr
{ [check_effective_target_aarch64_sve
]
9403 ||
[istarget amdgcn
*-*-*]
9404 ||
[check_effective_target_riscv_v
] }]
9407 #
Return 1 if the target supports section
-anchors
9409 proc check_effective_target_section_anchors
{ } {
9410 return [check_cached_effective_target section_anchors
{
9411 expr
{ [istarget powerpc
*-*-*]
9412 ||
[istarget arm
*-*-*]
9413 ||
[istarget aarch64
*-*-*]
9414 ||
[istarget loongarch
*-*-*] }}]
9417 #
Return 1 if the target supports atomic operations
on "int_128" values.
9419 proc check_effective_target_sync_int_128
{ } {
9423 #
Return 1 if the target supports atomic operations
on "int_128" values
9424 # and can
execute them.
9425 # This requires support
for both compare
-and
-swap and true atomic loads.
9427 proc check_effective_target_sync_int_128_runtime
{ } {
9431 #
Return 1 if the target supports atomic operations
on "long long".
9433 # Note
: 32bit x86 targets require
-march
=pentium in dg
-options.
9434 # Note
: 32bit s390 targets require
-mzarch in dg
-options.
9436 proc check_effective_target_sync_long_long
{ } {
9437 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9438 ||
[istarget aarch64
*-*-*]
9439 ||
[istarget arm
*-*-*]
9440 ||
[istarget alpha
*-*-*]
9441 ||
([istarget sparc
*-*-*] && [check_effective_target_lp64
])
9442 ||
[istarget s390
*-*-*] } {
9449 #
Return 1 if the target supports popcount
on long.
9451 proc check_effective_target_popcountl
{ } {
9452 return [check_no_messages_and_pattern popcountl
"!\\(call" rtl-expand {
9455 return __builtin_popcountl
(b
);
9460 #
Return 1 if the target supports popcount
on long long.
9462 proc check_effective_target_popcountll
{ } {
9463 return [check_no_messages_and_pattern popcountll
"!\\(call" rtl-expand {
9464 int foo
(long long b
)
9466 return __builtin_popcountll
(b
);
9472 #
Return 1 if the target supports popcount
on int.
9474 proc check_effective_target_popcount
{ } {
9475 return [check_no_messages_and_pattern popcount
"!\\(call" rtl-expand {
9478 return __builtin_popcount
(b
);
9483 #
Return 1 if the target supports clz
on int.
9485 proc check_effective_target_clz
{ } {
9486 return [check_no_messages_and_pattern clz
"!\\(call" rtl-expand {
9489 return __builtin_clz
(b
);
9494 #
Return 1 if the target supports clz
on long.
9496 proc check_effective_target_clzl
{ } {
9497 return [check_no_messages_and_pattern clzl
"!\\(call" rtl-expand {
9500 return __builtin_clzl
(b
);
9505 #
Return 1 if the target supports clz
on long long.
9507 proc check_effective_target_clzll
{ } {
9508 return [check_no_messages_and_pattern clzll
"!\\(call" rtl-expand {
9509 int foo
(long long b
)
9511 return __builtin_clzll
(b
);
9516 #
Return 1 if the target supports ctz
on int.
9518 proc check_effective_target_ctz
{ } {
9519 return [check_no_messages_and_pattern ctz
"!\\(call" rtl-expand {
9522 return __builtin_ctz
(b
);
9527 #
Return 1 if the target supports ctz
on long.
9529 proc check_effective_target_ctzl
{ } {
9530 return [check_no_messages_and_pattern ctzl
"!\\(call" rtl-expand {
9533 return __builtin_ctzl
(b
);
9538 #
Return 1 if the target supports ctz
on long long.
9540 proc check_effective_target_ctzll
{ } {
9541 return [check_no_messages_and_pattern ctzll
"!\\(call" rtl-expand {
9542 int foo
(long long b
)
9544 return __builtin_ctzll
(b
);
9549 #
Return 1 if the target supports atomic operations
on "long long"
9550 # and can
execute them.
9552 # Note
: 32bit x86 targets require
-march
=pentium in dg
-options.
9554 proc check_effective_target_sync_long_long_runtime
{ } {
9555 if { (([istarget x86_64
-*-*] ||
[istarget i?
86-*-*])
9556 && [check_cached_effective_target sync_long_long_available
{
9557 check_runtime_nocache sync_long_long_available
{
9561 unsigned
int eax
, ebx
, ecx
, edx
;
9562 if (__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
9563 return !(edx
& bit_CMPXCHG8B
);
9568 ||
[istarget aarch64
*-*-*]
9569 ||
[istarget arm
*-*-uclinuxfdpiceabi
]
9570 ||
([istarget arm
*-*-linux
-*]
9571 && [check_runtime sync_longlong_runtime
{
9577 if (sizeof
(long long
) != 8)
9580 /* Just check
for native
;
9581 checking
for kernel fallback is tricky.
*/
9582 asm volatile
("ldrexd r0,r1, [%0]"
9583 : : "r" (&l1) : "r0", "r1");
9587 ||
[istarget alpha
*-*-*]
9588 ||
([istarget sparc
*-*-*]
9589 && [check_effective_target_lp64
]
9590 && [check_effective_target_ultrasparc_hw
])
9591 ||
([istarget powerpc
*-*-*] && [check_effective_target_lp64
]) } {
9598 #
Return 1 if the target supports byte swap instructions.
9600 proc check_effective_target_bswap
{ } {
9601 return [check_cached_effective_target bswap
{
9602 expr
{ [istarget aarch64
*-*-*]
9603 ||
[istarget alpha
*-*-*]
9604 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9605 ||
[istarget m68k
-*-*]
9606 ||
[istarget powerpc
*-*-*]
9607 ||
[istarget rs6000
-*-*]
9608 ||
[istarget s390
*-*-*]
9609 ||
([istarget riscv
*-*-*]
9610 && [check_no_compiler_messages_nocache riscv_zbb object
{
9611 #
if __riscv_zbb
<= 0
9612 #error ZBB is not enabled
9616 ||
([istarget arm
*-*-*]
9617 && [check_no_compiler_messages_nocache arm_v6_or_later object
{
9619 #error not armv6 or later
9625 #
Return 1 if the target supports atomic operations
on "int" and "long".
9627 proc check_effective_target_sync_int_long
{ } {
9628 # This is intentionally powerpc but not rs6000
, rs6000 doesn
't have the
9629 # load-reserved/store-conditional instructions.
9630 return [check_cached_effective_target sync_int_long {
9631 expr { [istarget ia64-*-*]
9632 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9633 || [istarget aarch64*-*-*]
9634 || [istarget alpha*-*-*]
9635 || [istarget arm*-*-linux-*]
9636 || [istarget arm*-*-uclinuxfdpiceabi]
9637 || ([istarget arm*-*-*]
9638 && [check_effective_target_arm_acq_rel])
9639 || [istarget bfin*-*linux*]
9640 || [istarget hppa*-*linux*]
9641 || [istarget s390*-*-*]
9642 || [istarget powerpc*-*-*]
9643 || [istarget cris-*-*]
9644 || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
9645 || ([istarget arc*-*-*] && [check_effective_target_arc_atomic])
9646 || [check_effective_target_mips_llsc]
9647 || [istarget nvptx*-*-*]
9651 # Return 1 if the target supports atomic operations on "int" and "long" on
9654 proc check_effective_target_sync_int_long_stack { } {
9655 return [check_cached_effective_target sync_int_long_stack {
9656 expr { ![istarget nvptx*-*-*]
9657 && [check_effective_target_sync_int_long]
9661 # Return 1 if the target supports atomic operations on "char" and "short".
9663 proc check_effective_target_sync_char_short { } {
9664 # This is intentionally powerpc but not rs6000, rs6000 doesn't have the
9665 #
load-reserved/store
-conditional instructions.
9666 return [check_cached_effective_target sync_char_short
{
9667 expr
{ [istarget aarch64
*-*-*]
9668 ||
[istarget ia64
-*-*]
9669 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9670 ||
[istarget alpha
*-*-*]
9671 ||
[istarget arm
*-*-linux
-*]
9672 ||
[istarget arm
*-*-uclinuxfdpiceabi
]
9673 ||
([istarget arm
*-*-*]
9674 && [check_effective_target_arm_acq_rel
])
9675 ||
[istarget hppa
*-*linux
*]
9676 ||
[istarget s390
*-*-*]
9677 ||
[istarget powerpc
*-*-*]
9678 ||
[istarget cris
-*-*]
9679 ||
([istarget sparc
*-*-*] && [check_effective_target_sparc_v9
])
9680 ||
([istarget arc
*-*-*] && [check_effective_target_arc_atomic
])
9681 ||
[istarget loongarch
*-*-*]
9682 ||
[check_effective_target_mips_llsc
] }}]
9685 #
Return 1 if thread_fence does not rely
on __sync_synchronize
9688 proc check_effective_target_thread_fence
{} {
9689 return [check_no_compiler_messages thread_fence executable
{
9691 __atomic_thread_fence
(__ATOMIC_SEQ_CST
);
9697 #
Return 1 if the target uses a ColdFire FPU.
9699 proc check_effective_target_coldfire_fpu
{ } {
9700 return [check_no_compiler_messages coldfire_fpu assembly
{
9707 #
Return true
if this is a uClibc target.
9709 proc check_effective_target_uclibc
{} {
9710 return [check_no_compiler_messages uclibc object
{
9711 #
include <features.h
>
9712 #
if !defined
(__UCLIBC__
)
9718 #
Return true
if this is a uclibc target and
if the uclibc feature
9719 # described by __$feature__ is not present.
9721 proc check_missing_uclibc_feature
{feature
} {
9722 return [check_no_compiler_messages $feature object
"
9723 #
include <features.h
>
9724 #
if !defined
(__UCLIBC
) || defined
(__$
{feature
}__
)
9730 #
Return true
if this is a Newlib target.
9732 proc check_effective_target_newlib
{} {
9733 return [check_no_compiler_messages newlib object
{
9738 #
Return true
if GCC was configured with
--enable
-newlib
-nano
-formatted
-io
9739 proc check_effective_target_newlib_nano_io
{ } {
9740 return [check_configured_with
"--enable-newlib-nano-formatted-io"]
9743 # Some newlib versions don
't provide a frexpl and instead depend
9744 # on frexp to implement long double conversions in their printf-like
9745 # functions. This leads to broken results. Detect such versions here.
9747 proc check_effective_target_newlib_broken_long_double_io {} {
9748 if { [is-effective-target newlib] && ![is-effective-target frexpl] } {
9754 # Return true if this is NOT a Bionic target.
9756 proc check_effective_target_non_bionic {} {
9757 return [check_no_compiler_messages non_bionic object {
9759 #if defined (__BIONIC__)
9765 # Return true if this target has error.h header.
9767 proc check_effective_target_error_h {} {
9768 return [check_no_compiler_messages error_h object {
9773 # Return true if this target has tgmath.h header.
9775 proc check_effective_target_tgmath_h {} {
9776 return [check_no_compiler_messages tgmath_h object {
9781 # Return true if target's libc supports complex functions.
9783 proc check_effective_target_libc_has_complex_functions
{} {
9784 return [check_no_compiler_messages libc_has_complex_functions object
{
9785 #
include <complex.h
>
9790 #
(a
) an error of a few ULP is expected in string to floating
-point
9791 # conversion functions
; and
9792 #
(b
) overflow is not always detected correctly by those functions.
9794 proc check_effective_target_lax_strtofp
{} {
9795 # By default
, assume that all uClibc targets suffer from this.
9796 return [check_effective_target_uclibc
]
9799 #
Return 1 if this is a target
for which wcsftime is a dummy
9800 # function that always returns
0.
9802 proc check_effective_target_dummy_wcsftime
{} {
9803 # By default
, assume that all uClibc targets suffer from this.
9804 return [check_effective_target_uclibc
]
9807 #
Return 1 if constructors with initialization priority arguments are
9808 # supposed
on this target.
9810 proc check_effective_target_init_priority
{} {
9811 return [check_no_compiler_messages init_priority assembly
"
9812 void f
() __attribute__
((constructor
(1000)));
9817 #
Return 1 if the target matches the effective target
'arg', 0 otherwise.
9818 # This can be used with
any check_
* proc that takes no
argument and
9819 # returns only
1 or
0. It could be used with check_
* procs that take
9820 # arguments with keywords that pass particular arguments.
9822 proc is
-effective
-target
{ arg } {
9825 if { ![info exists et_index
] } {
9826 # Initialize the effective target index that is used in some
9827 # check_effective_target_
* procs.
9830 if { [info procs check_effective_target_$
{arg}] != [list
] } {
9831 set selected
[check_effective_target_$
{arg}]
9834 "vmx_hw" { set selected [check_vmx_hw_available] }
9835 "vsx_hw" { set selected [check_vsx_hw_available] }
9836 "p8vector_hw" { set selected [check_p8vector_hw_available] }
9837 "p9vector_hw" { set selected [check_p9vector_hw_available] }
9838 "p9modulo_hw" { set selected [check_p9modulo_hw_available] }
9839 "power10_hw" { set selected [check_power10_hw_available] }
9840 "ppc_float128_sw" { set selected [check_ppc_float128_sw_available] }
9841 "ppc_float128_hw" { set selected [check_ppc_float128_hw_available] }
9842 "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] }
9843 "ppc_cpu_supports_hw" { set selected [check_ppc_cpu_supports_hw_available] }
9844 "ppc_mma_hw" { set selected [check_ppc_mma_hw_available] }
9845 "dfp_hw" { set selected [check_dfp_hw_available] }
9846 "htm_hw" { set selected [check_htm_hw_available] }
9847 "named_sections" { set selected [check_named_sections_available] }
9848 "gc_sections" { set selected [check_gc_sections_available] }
9849 "linker_plugin" { set selected [check_linker_plugin_available] }
9850 "cxa_atexit" { set selected [check_cxa_atexit_available] }
9851 default
{ error
"unknown effective target keyword `$arg'" }
9855 verbose
"is-effective-target: $arg $selected" 2
9859 #
Return 1 if the
argument is an effective
-target keyword
, 0 otherwise.
9861 proc is
-effective
-target
-keyword
{ arg } {
9862 if { [info procs check_effective_target_$
{arg}] != [list
] } {
9865 # These have different names
for their check_
* procs.
9867 "vmx_hw" { return 1 }
9868 "vsx_hw" { return 1 }
9869 "p8vector_hw" { return 1 }
9870 "p9vector_hw" { return 1 }
9871 "p9modulo_hw" { return 1 }
9872 "power10_hw" { return 1 }
9873 "ppc_float128_sw" { return 1 }
9874 "ppc_float128_hw" { return 1 }
9875 "ppc_recip_hw" { return 1 }
9876 "ppc_mma_hw" { return 1 }
9877 "dfp_hw" { return 1 }
9878 "htm_hw" { return 1 }
9879 "named_sections" { return 1 }
9880 "gc_sections" { return 1 }
9881 "cxa_atexit" { return 1 }
9882 "ppc_cpu_supports_hw" { return 1 }
9883 default
{ return 0 }
9888 #
Execute tests
for all targets in EFFECTIVE_TARGETS list.
Set et_index to
9889 # indicate what target is currently being processed. This is
for
9890 # the vectorizer tests
, e.g. vect_int
, to keep track what target supports
9893 proc et
-dg
-runtest
{ runtest testcases flags default
-extra
-flags
} {
9894 global dg
-do-what
-default
9895 global EFFECTIVE_TARGETS
9898 if { [llength $EFFECTIVE_TARGETS
] > 0 } {
9899 foreach target $EFFECTIVE_TARGETS
{
9900 set target_flags $flags
9901 set dg
-do-what
-default
compile
9902 set et_index
[lsearch
-exact $EFFECTIVE_TARGETS $target
]
9903 if { [info procs add_options_for_$
{target
}] != [list
] } {
9904 set target_flags
[add_options_for_$
{target
} "$flags"]
9906 if { [info procs check_effective_target_$
{target
}_runtime
]
9907 != [list
] && [check_effective_target_$
{target
}_runtime
] } {
9908 set dg
-do-what
-default run
9910 $runtest $testcases $target_flags $
{default
-extra
-flags
}
9914 $runtest $testcases $flags $
{default
-extra
-flags
}
9918 #
Return 1 if a target matches the target in EFFECTIVE_TARGETS at index
9919 # et_index
, 0 otherwise.
9921 proc et
-is
-effective
-target
{ target
} {
9922 global EFFECTIVE_TARGETS
9925 if { [info exists EFFECTIVE_TARGETS
] } {
9926 if { [llength $EFFECTIVE_TARGETS
] > $et_index
9927 && [lindex $EFFECTIVE_TARGETS $et_index
] == $target
} {
9933 return [check_effective_target_$
{target
}]
9937 #
Return 1 if target default to short enums
9939 proc check_effective_target_short_enums
{ } {
9940 return [check_no_compiler_messages short_enums assembly
{
9942 int s
[sizeof
(enum foo
) == 1 ?
1 : -1];
9946 #
Return 1 if target supports merging string constants at link time.
9948 proc check_effective_target_string_merging
{ } {
9949 return [check_no_messages_and_pattern string_merging \
9950 "rodata\\.str" assembly {
9951 const char
*var
= "String";
9955 #
Return 1 if target has the basic signed and unsigned types in
9956 #
<stdint.h
>, 0 otherwise. This will be obsolete when GCC ensures a
9957 # working
<stdint.h
> for all targets.
9959 proc check_effective_target_stdint_types
{ } {
9960 return [check_no_compiler_messages stdint_types assembly
{
9962 int8_t a
; int16_t b
; int32_t c
; int64_t d
;
9963 uint8_t e
; uint16_t f
; uint32_t g
; uint64_t h
;
9967 # Like check_effective_target_stdint_types
, but test what happens when
9968 #
-mbig
-endian is passed. This test only makes sense
on targets that
9969 # support
-mbig
-endian
; it will fail elsewhere.
9971 proc check_effective_target_stdint_types_mbig_endian
{ } {
9972 return [check_no_compiler_messages stdint_types_mbig_endian assembly
{
9974 int8_t a
; int16_t b
; int32_t c
; int64_t d
;
9975 uint8_t e
; uint16_t f
; uint32_t g
; uint64_t h
;
9979 #
Return 1 if target has the basic signed and unsigned types in
9980 #
<inttypes.h
>, 0 otherwise. This is
for tests that GCC
's notions of
9981 # these types agree with those in the header, as some systems have
9982 # only <inttypes.h>.
9984 proc check_effective_target_inttypes_types { } {
9985 return [check_no_compiler_messages inttypes_types assembly {
9986 #include <inttypes.h>
9987 int8_t a; int16_t b; int32_t c; int64_t d;
9988 uint8_t e; uint16_t f; uint32_t g; uint64_t h;
9992 # Return 1 if programs are intended to be run on a simulator
9993 # (i.e. slowly) rather than hardware (i.e. fast).
9995 proc check_effective_target_simulator { } {
9997 # All "src/sim" simulators set this one.
9998 if [board_info target exists is_simulator] {
9999 return [board_info target is_simulator]
10002 # The "sid" simulators don't
set that one
, but at least they
set
10004 if [board_info target
exists slow_simulator
] {
10005 return [board_info target slow_simulator
]
10011 #
Return 1 if programs are intended to be run
on hardware rather than
10014 proc check_effective_target_hw
{ } {
10016 # All
"src/sim" simulators set this one.
10017 if [board_info target
exists is_simulator
] {
10018 if [board_info target is_simulator
] {
10025 # The
"sid" simulators don't set that one, but at least they set
10027 if [board_info target
exists slow_simulator
] {
10028 if [board_info target slow_simulator
] {
10038 #
Return 1 if the target is a VxWorks kernel.
10040 proc check_effective_target_vxworks_kernel
{ } {
10041 return [check_no_compiler_messages vxworks_kernel assembly
{
10042 #
if !defined __vxworks || defined __RTP__
10048 #
Return 1 if the target is a VxWorks RTP.
10050 proc check_effective_target_vxworks_rtp
{ } {
10051 return [check_no_compiler_messages vxworks_rtp assembly
{
10052 #
if !defined __vxworks ||
!defined __RTP__
10058 #
Return 1 if the target is expected to provide wide character support.
10060 proc check_effective_target_wchar
{ } {
10061 if {[check_missing_uclibc_feature UCLIBC_HAS_WCHAR
]} {
10064 return [check_no_compiler_messages wchar assembly
{
10069 #
Return 1 if the target has
<pthread.h
>.
10071 proc check_effective_target_pthread_h
{ } {
10072 return [check_no_compiler_messages pthread_h assembly
{
10073 #
include <pthread.h
>
10077 #
Return 1 if the target can truncate a file from a file
-descriptor
,
10078 # as used by libgfortran
/io
/unix.c
:fd_truncate
; i.e. ftruncate or
10079 # chsize. We test
for a trivially functional truncation
; no stubs.
10080 # As libgfortran uses _FILE_OFFSET_BITS
64, we
do too
; it
'll cause a
10081 # different function to be used.
10083 proc check_effective_target_fd_truncate { } {
10085 #define _FILE_OFFSET_BITS 64
10086 #include <unistd.h>
10088 #include <stdlib.h>
10089 #include <string.h>
10092 FILE *f = fopen ("tst.tmp", "wb");
10094 const char t[] = "test writing more than ten characters";
10098 write (fd, t, sizeof (t) - 1);
10100 if (ftruncate (fd, 10) != 0)
10106 unlink ("tst.tmp");
10109 f = fopen ("tst.tmp", "rb");
10110 if (fread (s, 1, sizeof (s), f) != 10 || strncmp (s, t, 10) != 0)
10113 unlink ("tst.tmp");
10118 if { [check_runtime ftruncate $prog] } {
10122 regsub "ftruncate" $prog "chsize" prog
10123 return [check_runtime chsize $prog]
10126 # Add to FLAGS all the target-specific flags needed to enable
10127 # full IEEE compliance mode.
10129 proc add_options_for_ieee { flags } {
10130 if { [istarget alpha*-*-*]
10131 || [istarget sh*-*-*] } {
10132 return "$flags -mieee"
10134 if { [istarget rx-*-*] } {
10135 return "$flags -mnofpu"
10140 if {![info exists flags_to_postpone]} {
10141 set flags_to_postpone ""
10144 # Add to FLAGS the flags needed to enable functions to bind locally
10145 # when using pic/PIC passes in the testsuite.
10146 proc add_options_for_bind_pic_locally { flags } {
10147 global flags_to_postpone
10149 # Instead of returning 'flags
' with the -fPIE or -fpie appended, we save it
10150 # in 'flags_to_postpone
' and append it later in gcc_target_compile procedure in
10151 # order to make sure that the multilib_flags doesn't override this.
10153 if {[check_no_compiler_messages using_pic2 assembly
{
10155 #error __PIC__
!= 2
10158 set flags_to_postpone
"-fPIE"
10161 if {[check_no_compiler_messages using_pic1 assembly
{
10163 #error __PIC__
!= 1
10166 set flags_to_postpone
"-fpie"
10172 # Add to FLAGS the flags needed to enable
64-bit vectors.
10174 proc add_options_for_double_vectors
{ flags
} {
10175 if [is
-effective
-target arm_neon_ok
] {
10176 return "$flags -mvectorize-with-neon-double"
10182 # Add to FLAGS the flags needed to
define the STACK_SIZE macro.
10184 proc add_options_for_stack_size
{ flags
} {
10185 if [is
-effective
-target stack_size
] {
10186 set stack_size
[dg
-effective
-target
-value stack_size
]
10187 return "$flags -DSTACK_SIZE=$stack_size"
10193 #
Return 1 if the target provides a full C99 runtime.
10195 proc check_effective_target_c99_runtime
{ } {
10196 return [check_cached_effective_target c99_runtime
{
10199 set file
[open
"$srcdir/gcc.dg/builtins-config.h"]
10200 set contents
[read $file
]
10203 #ifndef HAVE_C99_RUNTIME
10204 #error
!HAVE_C99_RUNTIME
10207 check_no_compiler_messages_nocache c99_runtime assembly $contents
10211 #
Return 1 if the target supports DWARF CFI directives.
10213 proc check_effective_target_cfi
{ } {
10214 return [check_no_compiler_messages cfi assembly
{
10215 #ifdef __GCC_HAVE_DWARF2_CFI_ASM
10223 #
Return 1 if the target provides the D runtime.
10225 proc check_effective_target_d_runtime
{ } {
10226 return [check_no_compiler_messages d_runtime executable
{
10230 extern
(C
) int main
() {
10236 #
Return 1 if the target provides the D standard library.
10238 proc check_effective_target_d_runtime_has_std_library
{ } {
10239 return [check_no_compiler_messages d_runtime_has_std_library executable
{
10243 extern
(C
) int main
() {
10245 real function
(real
) pcos
= &cos;
10251 #
Return 1 if target wchar_t is at least
4 bytes.
10253 proc check_effective_target_4byte_wchar_t
{ } {
10254 return [check_no_compiler_messages
4byte_wchar_t object
{
10255 int dummy
[sizeof
(__WCHAR_TYPE__
) >= 4 ?
1 : -1];
10259 #
Return 1 if the target supports automatic stack alignment.
10261 proc check_effective_target_automatic_stack_alignment
{ } {
10262 # Ordinarily x86 supports automatic stack alignment ...
10263 if { [istarget i?
86*-*-*] ||
[istarget x86_64
-*-*] } then {
10264 if { [istarget
*-*-mingw
*] ||
[istarget
*-*-cygwin
*] } {
10265 # ... except Win64 SEH doesn
't. Succeed for Win32 though.
10266 return [check_effective_target_ilp32];
10273 # Return true if we are compiling for AVX target.
10275 proc check_avx_available { } {
10276 if { [check_no_compiler_messages avx_available assembly {
10286 # Return true if we are compiling for AVX2 target.
10288 proc check_avx2_available { } {
10289 if { [check_no_compiler_messages avx2_available assembly {
10299 # Return true if we are compiling for SSSE3 target.
10301 proc check_ssse3_available { } {
10302 if { [check_no_compiler_messages sse3a_available assembly {
10312 # Return true if 32- and 16-bytes vectors are available.
10314 proc check_effective_target_vect_sizes_32B_16B { } {
10315 return [expr { [available_vector_sizes] == [list 256 128] }]
10318 # Return true if 16- and 8-bytes vectors are available.
10320 proc check_effective_target_vect_sizes_16B_8B { } {
10321 if { [check_avx_available]
10322 || [is-effective-target arm_neon]
10323 || [istarget aarch64*-*-*]
10324 || [check_effective_target_riscv_v] } {
10332 # Return true if 128-bits vectors are preferred even if 256-bits vectors
10335 proc check_prefer_avx128 { } {
10336 if ![check_avx_available] {
10339 return [check_no_messages_and_pattern avx_explicit "xmm" assembly {
10340 float a[1024],b[1024],c[1024];
10341 void foo (void) { int i; for (i = 0; i < 1024; i++) a[i]=b[i]+c[i];}
10342 } "-O2 -ftree-vectorize"]
10346 # Return 1 if avx512fp16 instructions can be compiled.
10348 proc check_effective_target_avx512fp16 { } {
10349 return [check_no_compiler_messages avx512fp16 object {
10352 asm volatile ("vmovw %edi, %xmm0");
10353 asm volatile ("vfcmulcph %xmm1, %xmm2, %xmm3{%k1}");
10355 } "-O2 -mavx512fp16" ]
10358 # Return 1 if avx512f instructions can be compiled.
10360 proc check_effective_target_avx512f { } {
10361 return [check_no_compiler_messages avx512f object {
10362 typedef double __m512d __attribute__ ((__vector_size__ (64)));
10363 typedef double __m128d __attribute__ ((__vector_size__ (16)));
10365 __m512d _mm512_add (__m512d a)
10367 return __builtin_ia32_addpd512_mask (a, a, a, 1, 4);
10370 __m128d _mm128_add (__m128d a)
10372 return __builtin_ia32_addsd_round (a, a, 8);
10375 __m128d _mm128_getmant (__m128d a)
10377 return __builtin_ia32_getmantsd_round (a, a, 0, 8);
10379 } "-O2 -mavx512f" ]
10382 # Return 1 if avx instructions can be compiled.
10384 proc check_effective_target_avx { } {
10385 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
10388 return [check_no_compiler_messages avx object {
10389 void _mm256_zeroall (void)
10391 __builtin_ia32_vzeroall ();
10396 # Return 1 if avx2 instructions can be compiled.
10397 proc check_effective_target_avx2 { } {
10398 return [check_no_compiler_messages avx2 object {
10399 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10401 mm256_is32_andnotsi256 (__v4di __X, __v4di __Y)
10403 return __builtin_ia32_andnotsi256 (__X, __Y);
10408 # Return 1 if avxvnni instructions can be compiled.
10409 proc check_effective_target_avxvnni { } {
10410 return [check_no_compiler_messages avxvnni object {
10411 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10413 _mm256_dpbusd_epi32 (__v8si __A, __v8si __B, __v8si __C)
10415 return __builtin_ia32_vpdpbusd_v8si (__A, __B, __C);
10420 # Return 1 if avxifma instructions can be compiled.
10421 proc check_effective_target_avxifma { } {
10422 return [check_no_compiler_messages avxifma object {
10423 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10425 _mm256_maddlo_epu64 (__v4di __A, __v4di __B, __v4di __C)
10427 return __builtin_ia32_vpmadd52luq256 (__A, __B, __C);
10429 } "-O0 -mavxifma" ]
10432 # Return 1 if avxvnniint8 instructions can be compiled.
10433 proc check_effective_target_avxvnniint8 { } {
10434 return [check_no_compiler_messages avxvnniint8 object {
10435 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10437 _mm256_dpbssd_epi32 (__v8si __A, __v8si __B, __v8si __C)
10439 return __builtin_ia32_vpdpbssd256 (__A, __B, __C);
10441 } "-O0 -mavxvnniint8" ]
10444 # Return 1 if avxneconvert instructions can be compiled.
10445 proc check_effective_target_avxneconvert { } {
10446 return [check_no_compiler_messages avxneconvert object {
10447 typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
10449 _mm_bcstnebf16_ps (const void *__P)
10451 return (__m128) __builtin_ia32_vbcstnebf162ps128 ((const __bf16 *) __P);
10453 } "-O0 -mavxneconvert" ]
10456 # Return 1 if cmpccxadd instructions can be compiled.
10457 proc check_effective_target_cmpccxadd { } {
10458 return [check_no_compiler_messages cmpccxadd object {
10459 int _cmpccxadd_epi32 (int *__A, int __B, int __C, const int __D)
10461 return (int)__builtin_ia32_cmpccxadd (__A, __B, __C, 1);
10466 # Return 1 if raoint instructions can be compiled.
10467 proc check_effective_target_raoint { } {
10468 return [check_no_compiler_messages raoint object {
10470 _aadd_si32 (int *__A, int __B)
10472 return __builtin_ia32_aadd32((int *)__A, __B);
10477 # Return 1 if amx-complex instructions can be compiled.
10478 proc check_effective_target_amx_complex { } {
10479 return [check_no_compiler_messages amx_complex object {
10483 __asm__ volatile ("tcmmimfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
10485 } "-mamx-complex" ]
10488 # Return 1 if avxvnniint16 instructions can be compiled.
10489 proc check_effective_target_avxvnniint16 { } {
10490 return [check_no_compiler_messages avxvnniint16 object {
10491 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10493 _mm256_dpwsud_avx_epi32 (__v8si __A, __v8si __B, __v8si __C)
10495 return __builtin_ia32_vpdpwsud256 (__A, __B, __C);
10497 } "-O0 -mavxvnniint16" ]
10500 # Return 1 if sm3 instructions can be compiled.
10501 proc check_effective_target_sm3 { } {
10502 return [check_no_compiler_messages sm3 object {
10503 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10504 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10506 _mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C)
10508 return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A,
10515 # Return 1 if sha512 instructions can be compiled.
10516 proc check_effective_target_sha512 { } {
10517 return [check_no_compiler_messages sha512 object {
10518 typedef long long __m256i __attribute__ ((__vector_size__ (32)));
10519 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10521 _mm256_sha512msg2_epi64 (__m256i __A, __m256i __B)
10523 return (__m256i) __builtin_ia32_vsha512msg2 ((__v4di) __A,
10529 # Return 1 if sm4 instructions can be compiled.
10530 proc check_effective_target_sm4 { } {
10531 return [check_no_compiler_messages sm4 object {
10532 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10533 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10535 _mm_sm4key4_epi32 (__m128i __A, __m128i __B)
10537 return (__m128i) __builtin_ia32_vsm4key4128 ((__v4si) __A,
10543 proc check_effective_target_apxf { } {
10544 return [check_no_compiler_messages apxf object {
10548 __asm__ volatile ("add\t%%r16, %%r31" ::);
10553 # Return 1 if sse instructions can be compiled.
10554 proc check_effective_target_sse { } {
10555 return [check_no_compiler_messages sse object {
10558 __builtin_ia32_stmxcsr ();
10564 # Return 1 if sse2 instructions can be compiled.
10565 proc check_effective_target_sse2 { } {
10566 return [check_no_compiler_messages sse2 object {
10567 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10569 __m128i _mm_srli_si128 (__m128i __A, int __N)
10571 return (__m128i)__builtin_ia32_psrldqi128 (__A, 8);
10576 # Return 1 if sse4.1 instructions can be compiled.
10577 proc check_effective_target_sse4 { } {
10578 return [check_no_compiler_messages sse4.1 object {
10579 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10580 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10582 __m128i _mm_mullo_epi32 (__m128i __X, __m128i __Y)
10584 return (__m128i) __builtin_ia32_pmulld128 ((__v4si)__X,
10590 # Return 1 if F16C instructions can be compiled.
10592 proc check_effective_target_f16c { } {
10593 return [check_no_compiler_messages f16c object {
10594 #include "immintrin.h"
10596 foo (unsigned short val)
10598 return _cvtsh_ss (val);
10603 proc check_effective_target_ms_hook_prologue { } {
10604 if { [check_no_compiler_messages ms_hook_prologue object {
10605 void __attribute__ ((__ms_hook_prologue__)) foo ();
10613 # Return 1 if 3dnow instructions can be compiled.
10614 proc check_effective_target_3dnow { } {
10615 return [check_no_compiler_messages 3dnow object {
10616 typedef int __m64 __attribute__ ((__vector_size__ (8)));
10617 typedef float __v2sf __attribute__ ((__vector_size__ (8)));
10619 __m64 _m_pfadd (__m64 __A, __m64 __B)
10621 return (__m64) __builtin_ia32_pfadd ((__v2sf)__A, (__v2sf)__B);
10626 # Return 1 if sse3 instructions can be compiled.
10627 proc check_effective_target_sse3 { } {
10628 return [check_no_compiler_messages sse3 object {
10629 typedef double __m128d __attribute__ ((__vector_size__ (16)));
10630 typedef double __v2df __attribute__ ((__vector_size__ (16)));
10632 __m128d _mm_addsub_pd (__m128d __X, __m128d __Y)
10634 return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y);
10639 # Return 1 if ssse3 instructions can be compiled.
10640 proc check_effective_target_ssse3 { } {
10641 return [check_no_compiler_messages ssse3 object {
10642 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10643 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10645 __m128i _mm_abs_epi32 (__m128i __X)
10647 return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X);
10652 # Return 1 if aes instructions can be compiled.
10653 proc check_effective_target_aes { } {
10654 return [check_no_compiler_messages aes object {
10655 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10656 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10658 __m128i _mm_aesimc_si128 (__m128i __X)
10660 return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
10665 # Return 1 if vaes instructions can be compiled.
10666 proc check_effective_target_vaes { } {
10667 return [check_no_compiler_messages vaes object {
10668 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10669 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10671 __m128i _mm_aesimc_si128 (__m128i __X)
10673 return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
10675 } "-O2 -maes -mavx" ]
10678 # Return 1 if pclmul instructions can be compiled.
10679 proc check_effective_target_pclmul { } {
10680 return [check_no_compiler_messages pclmul object {
10681 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10682 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10684 __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
10686 return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
10693 # Return 1 if vpclmul instructions can be compiled.
10694 proc check_effective_target_vpclmul { } {
10695 return [check_no_compiler_messages vpclmul object {
10696 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10697 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10699 __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
10701 return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
10705 } "-O2 -mpclmul -mavx" ]
10708 # Return 1 if sse4a instructions can be compiled.
10709 proc check_effective_target_sse4a { } {
10710 return [check_no_compiler_messages sse4a object {
10711 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10712 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10714 __m128i _mm_insert_si64 (__m128i __X,__m128i __Y)
10716 return (__m128i) __builtin_ia32_insertq ((__v2di)__X, (__v2di)__Y);
10721 # Return 1 if fma4 instructions can be compiled.
10722 proc check_effective_target_fma4 { } {
10723 return [check_no_compiler_messages fma4 object {
10724 typedef float __m128 __attribute__ ((__vector_size__ (16)));
10725 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10726 __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
10728 return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
10735 # Return 1 if fma instructions can be compiled.
10736 proc check_effective_target_fma { } {
10737 return [check_no_compiler_messages fma object {
10738 typedef float __m128 __attribute__ ((__vector_size__ (16)));
10739 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10740 __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
10742 return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
10749 # Return 1 if xop instructions can be compiled.
10750 proc check_effective_target_xop { } {
10751 return [check_no_compiler_messages xop object {
10752 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10753 typedef short __v8hi __attribute__ ((__vector_size__ (16)));
10754 __m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C)
10756 return (__m128i) __builtin_ia32_vpmacssww ((__v8hi)__A,
10763 # Return 1 if lzcnt instruction can be compiled.
10764 proc check_effective_target_lzcnt { } {
10765 return [check_no_compiler_messages lzcnt object {
10766 unsigned short _lzcnt (unsigned short __X)
10768 return __builtin_clzs (__X);
10773 # Return 1 if bmi instructions can be compiled.
10774 proc check_effective_target_bmi { } {
10775 return [check_no_compiler_messages bmi object {
10776 unsigned int __bextr_u32 (unsigned int __X, unsigned int __Y)
10778 return __builtin_ia32_bextr_u32 (__X, __Y);
10783 # Return 1 if ADX instructions can be compiled.
10784 proc check_effective_target_adx { } {
10785 return [check_no_compiler_messages adx object {
10787 _adxcarry_u32 (unsigned char __CF, unsigned int __X,
10788 unsigned int __Y, unsigned int *__P)
10790 return __builtin_ia32_addcarryx_u32 (__CF, __X, __Y, __P);
10795 # Return 1 if rtm instructions can be compiled.
10796 proc check_effective_target_rtm { } {
10797 return [check_no_compiler_messages rtm object {
10801 return __builtin_ia32_xend ();
10806 # Return 1 if avx512vl instructions can be compiled.
10807 proc check_effective_target_avx512vl { } {
10808 return [check_no_compiler_messages avx512vl object {
10809 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10811 mm256_and_epi64 (__v4di __X, __v4di __Y)
10814 return __builtin_ia32_pandq256_mask (__X, __Y, __W, -1);
10819 # Return 1 if avx512cd instructions can be compiled.
10820 proc check_effective_target_avx512cd { } {
10821 return [check_no_compiler_messages avx512cd_trans object {
10822 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10824 _mm512_conflict_epi64 (__v8di __W, __v8di __A)
10826 return (__v8di) __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A,
10830 } "-Wno-psabi -mavx512cd" ]
10833 # Return 1 if avx512er instructions can be compiled.
10834 proc check_effective_target_avx512er { } {
10835 return [check_no_compiler_messages avx512er_trans object {
10836 typedef float __v16sf __attribute__ ((__vector_size__ (64)));
10838 mm512_exp2a23_ps (__v16sf __X)
10840 return __builtin_ia32_exp2ps_mask (__X, __X, -1, 4);
10842 } "-Wno-psabi -mavx512er" ]
10845 # Return 1 if sha instructions can be compiled.
10846 proc check_effective_target_sha { } {
10847 return [check_no_compiler_messages sha object {
10848 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10849 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10851 __m128i _mm_sha1msg1_epu32 (__m128i __X, __m128i __Y)
10853 return (__m128i) __builtin_ia32_sha1msg1 ((__v4si)__X,
10859 # Return 1 if avx512dq instructions can be compiled.
10860 proc check_effective_target_avx512dq { } {
10861 return [check_no_compiler_messages avx512dq object {
10862 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10864 _mm512_mask_mullo_epi64 (__v8di __W, __v8di __A, __v8di __B)
10866 return (__v8di) __builtin_ia32_pmullq512_mask ((__v8di) __A,
10874 # Return 1 if avx512bw instructions can be compiled.
10875 proc check_effective_target_avx512bw { } {
10876 return [check_no_compiler_messages avx512bw object {
10877 typedef short __v32hi __attribute__ ((__vector_size__ (64)));
10879 _mm512_mask_mulhrs_epi16 (__v32hi __W, __v32hi __A, __v32hi __B)
10881 return (__v32hi) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A,
10889 # Return 1 if -Wa,-march=+noavx512bw is supported.
10890 proc check_effective_target_assembler_march_noavx512bw {} {
10891 if { [istarget i?86*-*-*] || [istarget x86_64*-*-*] } {
10892 return [check_no_compiler_messages assembler_march_noavx512bw object {
10894 } "-mno-avx512bw -Wa,-march=+noavx512bw"]
10899 # Return 1 if avx512vp2intersect instructions can be compiled.
10900 proc check_effective_target_avx512vp2intersect { } {
10901 return [check_no_compiler_messages avx512vp2intersect object {
10902 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10903 typedef short __mmask16;
10905 _mm512_2intersect_epi32 (__v16si __A, __v16si __B, __mmask16 *__U,
10908 __builtin_ia32_2intersectd512 (__U, __M, (__v16si) __A, (__v16si) __B);
10910 } "-mavx512vp2intersect" ]
10913 # Return 1 if avx512ifma instructions can be compiled.
10914 proc check_effective_target_avx512ifma { } {
10915 return [check_no_compiler_messages avx512ifma object {
10916 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10918 _mm512_madd52lo_epu64 (__v8di __X, __v8di __Y, __v8di __Z)
10920 return (__v8di) __builtin_ia32_vpmadd52luq512_mask ((__v8di) __X,
10928 # Return 1 if avx512vbmi instructions can be compiled.
10929 proc check_effective_target_avx512vbmi { } {
10930 return [check_no_compiler_messages avx512vbmi object {
10931 typedef char __v64qi __attribute__ ((__vector_size__ (64)));
10933 _mm512_multishift_epi64_epi8 (__v64qi __X, __v64qi __Y)
10935 return (__v64qi) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X,
10943 # Return 1 if avx512_4fmaps instructions can be compiled.
10944 proc check_effective_target_avx5124fmaps { } {
10945 return [check_no_compiler_messages avx5124fmaps object {
10946 typedef float __v16sf __attribute__ ((__vector_size__ (64)));
10947 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10950 _mm512_mask_4fmadd_ps (__v16sf __DEST, __v16sf __A, __v16sf __B, __v16sf __C,
10951 __v16sf __D, __v16sf __E, __v4sf *__F)
10953 return (__v16sf) __builtin_ia32_4fmaddps_mask ((__v16sf) __A,
10958 (const __v4sf *) __F,
10962 } "-mavx5124fmaps" ]
10965 # Return 1 if avx512_4vnniw instructions can be compiled.
10966 proc check_effective_target_avx5124vnniw { } {
10967 return [check_no_compiler_messages avx5124vnniw object {
10968 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10969 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10972 _mm512_4dpwssd_epi32 (__v16si __A, __v16si __B, __v16si __C,
10973 __v16si __D, __v16si __E, __v4si *__F)
10975 return (__v16si) __builtin_ia32_vp4dpwssd ((__v16si) __B,
10980 (const __v4si *) __F);
10982 } "-mavx5124vnniw" ]
10985 # Return 1 if avx512_vpopcntdq instructions can be compiled.
10986 proc check_effective_target_avx512vpopcntdq { } {
10987 return [check_no_compiler_messages avx512vpopcntdq object {
10988 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10991 _mm512_popcnt_epi32 (__v16si __A)
10993 return (__v16si) __builtin_ia32_vpopcountd_v16si ((__v16si) __A);
10995 } "-mavx512vpopcntdq" ]
10998 # Return 1 if 128 or 256-bit avx512_vpopcntdq instructions can be compiled.
10999 proc check_effective_target_avx512vpopcntdqvl { } {
11000 return [check_no_compiler_messages avx512vpopcntdqvl object {
11001 typedef int __v8si __attribute__ ((__vector_size__ (32)));
11004 _mm256_popcnt_epi32 (__v8si __A)
11006 return (__v8si) __builtin_ia32_vpopcountd_v8si ((__v8si) __A);
11008 } "-mavx512vpopcntdq -mavx512vl" ]
11011 # Return 1 if gfni instructions can be compiled.
11012 proc check_effective_target_gfni { } {
11013 return [check_no_compiler_messages gfni object {
11014 typedef char __v16qi __attribute__ ((__vector_size__ (16)));
11017 _mm_gf2p8affineinv_epi64_epi8 (__v16qi __A, __v16qi __B, const int __C)
11019 return (__v16qi) __builtin_ia32_vgf2p8affineinvqb_v16qi ((__v16qi) __A,
11026 # Return 1 if avx512vbmi2 instructions can be compiled.
11027 proc check_effective_target_avx512vbmi2 { } {
11028 return [check_no_compiler_messages avx512vbmi2 object {
11029 typedef char __v16qi __attribute__ ((__vector_size__ (16)));
11030 typedef unsigned long long __mmask16;
11033 _mm_mask_compress_epi8 (__v16qi __A, __mmask16 __B, __v16qi __C)
11035 return (__v16qi) __builtin_ia32_compressqi128_mask((__v16qi)__C,
11039 } "-mavx512vbmi2 -mavx512vl" ]
11042 # Return 1 if avx512vbmi2 instructions can be compiled.
11043 proc check_effective_target_avx512vnni { } {
11044 return [check_no_compiler_messages avx512vnni object {
11045 typedef int __v16si __attribute__ ((__vector_size__ (64)));
11048 _mm_mask_compress_epi8 (__v16si __A, __v16si __B, __v16si __C)
11050 return (__v16si) __builtin_ia32_vpdpbusd_v16si ((__v16si)__A,
11054 } "-mavx512vnni -mavx512f" ]
11057 # Return 1 if vaes instructions can be compiled.
11058 proc check_effective_target_avx512vaes { } {
11059 return [check_no_compiler_messages avx512vaes object {
11061 typedef int __v16si __attribute__ ((__vector_size__ (64)));
11064 _mm256_aesdec_epi128 (__v32qi __A, __v32qi __B)
11066 return (__v32qi)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B);
11071 # Return 1 if amx-tile instructions can be compiled.
11072 proc check_effective_target_amx_tile { } {
11073 return [check_no_compiler_messages amx_tile object {
11077 __asm__ volatile ("tilerelease" ::);
11082 # Return 1 if amx-int8 instructions can be compiled.
11083 proc check_effective_target_amx_int8 { } {
11084 return [check_no_compiler_messages amx_int8 object {
11088 __asm__ volatile ("tdpbssd\t%%tmm1, %%tmm2, %%tmm3" ::);
11093 # Return 1 if amx-bf16 instructions can be compiled.
11094 proc check_effective_target_amx_bf16 { } {
11095 return [check_no_compiler_messages amx_bf16 object {
11099 __asm__ volatile ("tdpbf16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
11104 # Return 1 if amx-fp16 instructions can be compiled.
11105 proc check_effective_target_amx_fp16 { } {
11106 return [check_no_compiler_messages amx_fp16 object {
11110 __asm__ volatile ("tdpfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
11115 # Return 1 if vpclmulqdq instructions can be compiled.
11116 proc check_effective_target_vpclmulqdq { } {
11117 return [check_no_compiler_messages vpclmulqdq object {
11118 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
11121 _mm256_clmulepi64_epi128 (__v4di __A, __v4di __B)
11123 return (__v4di) __builtin_ia32_vpclmulqdq_v4di (__A, __B, 0);
11125 } "-mvpclmulqdq -mavx512vl" ]
11128 # Return 1 if avx512_bitalg instructions can be compiled.
11129 proc check_effective_target_avx512bitalg { } {
11130 return [check_no_compiler_messages avx512bitalg object {
11131 typedef short int __v32hi __attribute__ ((__vector_size__ (64)));
11134 _mm512_popcnt_epi16 (__v32hi __A)
11136 return (__v32hi) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A);
11138 } "-mavx512bitalg" ]
11141 # Return 1 if C wchar_t type is compatible with char16_t.
11143 proc check_effective_target_wchar_t_char16_t_compatible { } {
11144 return [check_no_compiler_messages wchar_t_char16_t object {
11146 __CHAR16_TYPE__ *p16 = &wc;
11147 char t[(((__CHAR16_TYPE__) -1) < 0 == ((__WCHAR_TYPE__) -1) < 0) ? 1 : -1];
11151 # Return 1 if C wchar_t type is compatible with char32_t.
11153 proc check_effective_target_wchar_t_char32_t_compatible { } {
11154 return [check_no_compiler_messages wchar_t_char32_t object {
11156 __CHAR32_TYPE__ *p32 = &wc;
11157 char t[(((__CHAR32_TYPE__) -1) < 0 == ((__WCHAR_TYPE__) -1) < 0) ? 1 : -1];
11161 # Return 1 if pow10 function exists.
11163 proc check_effective_target_pow10 { } {
11164 return [check_runtime pow10 {
11174 # Return 1 if frexpl function exists.
11176 proc check_effective_target_frexpl { } {
11177 return [check_runtime frexpl {
11182 x = frexpl (5.0, &y);
11189 # Return 1 if issignaling function exists.
11190 proc check_effective_target_issignaling {} {
11191 return [check_runtime issignaling {
11192 #define _GNU_SOURCE
11196 return issignaling (0.0);
11201 # Return 1 if current options generate DFP instructions, 0 otherwise.
11202 proc check_effective_target_hard_dfp {} {
11203 return [check_no_messages_and_pattern hard_dfp "!adddd3" assembly {
11204 typedef float d64 __attribute__((mode(DD)));
11206 void foo (void) { z = x + y; }
11210 # Return 1 if string.h and wchar.h headers provide C++ requires overloads
11211 # for strchr etc. functions.
11213 proc check_effective_target_correct_iso_cpp_string_wchar_protos { } {
11214 return [check_no_compiler_messages correct_iso_cpp_string_wchar_protos assembly {
11215 #include <string.h>
11217 #if !defined(__cplusplus) \
11218 || !defined(__CORRECT_ISO_CPP_STRING_H_PROTO) \
11219 || !defined(__CORRECT_ISO_CPP_WCHAR_H_PROTO)
11220 ISO C++ correct string.h and wchar.h protos not supported.
11227 # Return 1 if GNU as is used.
11229 proc check_effective_target_gas { } {
11230 global use_gas_saved
11233 if {![info exists use_gas_saved]} {
11234 # Check if the as used by gcc is GNU as.
11235 set options [list "additional_flags=-print-prog-name=as"]
11236 set gcc_as [lindex [${tool}_target_compile "" "" "none" $options] 0]
11237 # Provide /dev/null as input, otherwise gas times out reading from
11239 set status [remote_exec host "$gcc_as" "-v /dev/null"]
11240 set as_output [lindex $status 1]
11241 if { [ string first "GNU" $as_output ] >= 0 } {
11242 # Some Darwin versions have an assembler which is based on an old
11243 # version of GAS (and reports GNU assembler in its -v output) but
11244 # but doesn't support many of the modern GAS features.
11245 if { [ string first
"cctools" $as_output ] >= 0 } {
11246 set use_gas_saved
0
11248 set use_gas_saved
1
11251 set use_gas_saved
0
11254 return $use_gas_saved
11257 #
Return 1 if GNU
ld is used.
11259 proc check_effective_target_gld
{ } {
11260 global use_gld_saved
11263 if {![info exists use_gld_saved
]} {
11264 # Check
if the
ld used by gcc is GNU
ld.
11265 set options
[list
"additional_flags=-print-prog-name=ld"]
11266 set gcc_ld
[lindex
[$
{tool
}_target_compile
"" "" "none" $options] 0]
11267 set status [remote_exec host
"$gcc_ld" "--version"]
11268 set ld_output
[lindex $
status 1]
11269 if { [ string first
"GNU" $ld_output ] >= 0 } {
11270 set use_gld_saved
1
11272 set use_gld_saved
0
11275 return $use_gld_saved
11278 #
Return 1 if the compiler has been configure with link
-time optimization
11281 proc check_effective_target_lto
{ } {
11282 if { [istarget
*-*-vxworks
*] } {
11283 # No LTO
on VxWorks
, with kernel modules
11284 # built with partial links
11287 if { [istarget nvptx
-*-*]
11288 ||
[istarget amdgcn
-*-*] } {
11291 return [check_no_compiler_messages lto object
{
11292 void foo
(void
) { }
11296 #
Return 1 if the compiler and linker support incremental link
-time
11299 proc check_effective_target_lto_incremental
{ } {
11300 if ![check_effective_target_lto
] {
11303 return [check_no_compiler_messages lto_incremental executable
{
11304 int main
() { return 0; }
11305 } "-flto -r -nostdlib"]
11308 #
Return 1 if the compiler has been configured with analyzer support.
11310 proc check_effective_target_analyzer
{ } {
11311 return [check_no_compiler_messages analyzer object
{
11312 void foo
(void
) { }
11316 #
Return 1 if -mx32
-maddress
-mode=short can
compile, 0 otherwise.
11318 proc check_effective_target_maybe_x32
{ } {
11319 return [check_no_compiler_messages maybe_x32 object
{
11321 } "-mx32 -maddress-mode=short"]
11324 #
Return 1 if this target supports the
-fsplit
-stack option
, 0
11327 proc check_effective_target_split_stack
{} {
11328 return [check_no_compiler_messages split_stack object
{
11329 void foo
(void
) { }
11333 #
Return 1 if this target supports the
-masm
=intel option
, 0
11336 proc check_effective_target_masm_intel
{} {
11337 return [check_no_compiler_messages masm_intel object
{
11338 extern void abort
(void
);
11342 #
Return 1 if the language
for the compiler under test is C.
11344 proc check_effective_target_c
{ } {
11346 if [string match $tool
"gcc"] {
11352 #
Return 1 if the language
for the compiler under test is C
++.
11354 proc check_effective_target_c
++ { } {
11356 if { [string match $tool
"g++"] || [string match $tool "libstdc++"] } {
11362 set cxx_default
"c++17"
11363 # Check whether the current active language standard supports the features
11364 # of C
++11/C
++14 by checking
for the presence of one of the
-std flags.
11365 # This assumes that the default
for the compiler is $cxx_default
, and that
11366 # there will never be multiple
-std
= arguments
on the command line.
11367 proc check_effective_target_c
++11_only
{ } {
11369 if ![check_effective_target_c
++] {
11372 if [check
-flags
{ { } { } { -std
=c
++0x
-std
=gnu
++0x
-std
=c
++11 -std
=gnu
++11 } }] {
11375 if { $cxx_default
== "c++11" && [check-flags { { } { } { } { -std=* } }] } {
11380 proc check_effective_target_c
++11 { } {
11381 if [check_effective_target_c
++11_only
] {
11384 return [check_effective_target_c
++14]
11386 proc check_effective_target_c
++11_down
{ } {
11387 if ![check_effective_target_c
++] {
11390 return [expr
![check_effective_target_c
++14] ]
11393 proc check_effective_target_c
++14_only
{ } {
11395 if ![check_effective_target_c
++] {
11398 if [check
-flags
{ { } { } { -std
=c
++14 -std
=gnu
++14 -std
=c
++14 -std
=gnu
++14 } }] {
11401 if { $cxx_default
== "c++14" && [check-flags { { } { } { } { -std=* } }] } {
11407 proc check_effective_target_c
++14 { } {
11408 if [check_effective_target_c
++14_only
] {
11411 return [check_effective_target_c
++17]
11413 proc check_effective_target_c
++14_down
{ } {
11414 if ![check_effective_target_c
++] {
11417 return [expr
![check_effective_target_c
++17] ]
11420 proc check_effective_target_c
++98_only
{ } {
11422 if ![check_effective_target_c
++] {
11425 if [check
-flags
{ { } { } { -std
=c
++98 -std
=gnu
++98 -std
=c
++03 -std
=gnu
++03 } }] {
11428 if { $cxx_default
== "c++98" && [check-flags { { } { } { } { -std=* } }] } {
11434 proc check_effective_target_c
++17_only
{ } {
11436 if ![check_effective_target_c
++] {
11439 if [check
-flags
{ { } { } { -std
=c
++17 -std
=gnu
++17 -std
=c
++1z
-std
=gnu
++1z
} }] {
11442 if { $cxx_default
== "c++17" && [check-flags { { } { } { } { -std=* } }] } {
11448 proc check_effective_target_c
++17 { } {
11449 if [check_effective_target_c
++17_only
] {
11452 return [check_effective_target_c
++2a
]
11454 proc check_effective_target_c
++17_down
{ } {
11455 if ![check_effective_target_c
++] {
11458 return [expr
![check_effective_target_c
++2a
] ]
11461 proc check_effective_target_c
++2a_only
{ } {
11463 if ![check_effective_target_c
++] {
11466 if [check
-flags
{ { } { } { -std
=c
++2a
-std
=gnu
++2a
-std
=c
++20 -std
=gnu
++20 } }] {
11469 if { $cxx_default
== "c++20" && [check-flags { { } { } { } { -std=* } }] } {
11474 proc check_effective_target_c
++2a
{ } {
11475 if [check_effective_target_c
++2a_only
] {
11478 return [check_effective_target_c
++23]
11481 proc check_effective_target_c
++20_only
{ } {
11482 return [check_effective_target_c
++2a_only
]
11485 proc check_effective_target_c
++20 { } {
11486 return [check_effective_target_c
++2a
]
11488 proc check_effective_target_c
++20_down
{ } {
11489 if ![check_effective_target_c
++] {
11492 return [expr
![check_effective_target_c
++23] ]
11495 proc check_effective_target_c
++23_only
{ } {
11497 if ![check_effective_target_c
++] {
11500 if [check
-flags
{ { } { } { -std
=c
++23 -std
=gnu
++23 -std
=c
++2b
-std
=gnu
++2b
} }] {
11503 if { $cxx_default
== "c++23" && [check-flags { { } { } { } { -std=* } }] } {
11508 proc check_effective_target_c
++23 { } {
11509 if [check_effective_target_c
++23_only
] {
11512 return [check_effective_target_c
++26]
11515 proc check_effective_target_c
++23_down
{ } {
11516 if ![check_effective_target_c
++] {
11519 return [expr
![check_effective_target_c
++26] ]
11522 proc check_effective_target_c
++26_only
{ } {
11524 if ![check_effective_target_c
++] {
11527 if [check
-flags
{ { } { } { -std
=c
++26 -std
=gnu
++26 -std
=c
++2c
-std
=gnu
++2c
} }] {
11530 if { $cxx_default
== "c++26" && [check-flags { { } { } { } { -std=* } }] } {
11536 proc check_effective_target_c
++26 { } {
11537 return [check_effective_target_c
++26_only
]
11540 # Check
for C
++ Concepts support
, i.e.
-fconcepts flag.
11541 proc check_effective_target_concepts
{ } {
11542 if [check_effective_target_c
++2a
] {
11545 return [check
-flags
{ "" { } { -fconcepts } }]
11548 proc check_effective_target_implicit_constexpr
{ } {
11549 return [check
-flags
{ "" { } { -fimplicit-constexpr } }]
11552 #
Return 1 if expensive testcases should be run.
11554 proc check_effective_target_run_expensive_tests
{ } {
11555 if { [getenv GCC_TEST_RUN_EXPENSIVE
] != "" } {
11561 # Returns
1 if "mempcpy" is available on the target system.
11563 proc check_effective_target_mempcpy
{} {
11564 if { [istarget
*-*-vxworks
*] } {
11565 # VxWorks doesn
't have mempcpy but our way to test fails
11566 # to detect as we're doing partial links
for kernel modules.
11569 return [check_function_available
"mempcpy"]
11572 # Returns
1 if "stpcpy" is available on the target system.
11574 proc check_effective_target_stpcpy
{} {
11575 return [check_function_available
"stpcpy"]
11578 # Returns
1 if "strndup" is available on the target system.
11580 proc check_effective_target_strndup
{} {
11581 if { [istarget
*-*-vxworks
*] } {
11582 # VxWorks doesn
't have strndup but our way to test fails
11583 # to detect as we're doing partial links
for kernel modules.
11586 return [check_function_available
"strndup"]
11589 # Returns
1 if "sigsetjmp" is available on the target system.
11590 # Also check
if "__sigsetjmp" is defined since that's what glibc
11593 proc check_effective_target_sigsetjmp
{} {
11594 if { [check_function_available
"sigsetjmp"]
11595 ||
[check_function_available
"__sigsetjmp"] } {
11601 # Check whether the vectorizer tests are supported by the target and
11602 # append additional target
-dependent
compile flags to DEFAULT_VECTCFLAGS.
11603 #
If a port wants to
execute the tests more than once it should append
11604 # the supported target to EFFECTIVE_TARGETS instead
, and the
compile flags
11605 # will be added by a
call to add_options_for_
<target
>.
11606 #
Set dg
-do-what
-default to either
compile or run
, depending
on target
11607 # capabilities.
Do not
set this
if the supported target is appended to
11608 # EFFECTIVE_TARGETS. Flags and this
variable will be
set by et
-dg
-runtest
11609 # automatically.
Return the number of effective targets
if vectorizer tests
11610 # are supported
, 0 otherwise.
11612 proc check_vect_support_and_set_flags
{ } {
11613 global DEFAULT_VECTCFLAGS
11614 global dg
-do-what
-default
11615 global EFFECTIVE_TARGETS
11617 if [istarget powerpc
-*paired
*] {
11618 lappend DEFAULT_VECTCFLAGS
"-mpaired"
11619 if [check_750cl_hw_available
] {
11620 set dg
-do-what
-default run
11622 set dg
-do-what
-default
compile
11624 } elseif
[istarget powerpc
*-*-*] {
11625 # Skip targets not supporting
-maltivec.
11626 if ![is
-effective
-target powerpc_altivec_ok
] {
11630 lappend DEFAULT_VECTCFLAGS
"-maltivec"
11631 if [check_p9vector_hw_available
] {
11632 #
For power10 and up
, don
't specify -mcpu=power9, so that we
11633 # can have more testing coverage with higher cpu types.
11634 if ![check_power10_hw_available] {
11635 lappend DEFAULT_VECTCFLAGS "-mcpu=power9"
11637 } elseif [check_p8vector_hw_available] {
11638 lappend DEFAULT_VECTCFLAGS "-mcpu=power8"
11639 } elseif [check_vsx_hw_available] {
11640 lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
11643 if [check_vmx_hw_available] {
11644 set dg-do-what-default run
11646 if [is-effective-target ilp32] {
11647 # Specify a cpu that supports VMX for compile-only tests.
11648 # Place -mcpu=970 first to avoid possible overriding on
11649 # some other cpu type specified above.
11650 set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0 "-mcpu=970"]
11652 set dg-do-what-default compile
11654 } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
11655 lappend DEFAULT_VECTCFLAGS "-msse2"
11656 if { [check_effective_target_sse2_runtime] } {
11657 set dg-do-what-default run
11659 set dg-do-what-default compile
11661 } elseif { [istarget mips*-*-*]
11662 && [check_effective_target_nomips16] } {
11663 if { [check_effective_target_mpaired_single "-mpaired-single"] } {
11664 lappend EFFECTIVE_TARGETS mpaired_single
11666 if { [check_effective_target_mips_loongson_mmi "-mloongson-mmi"] } {
11667 lappend EFFECTIVE_TARGETS mips_loongson_mmi
11669 if { [check_effective_target_mips_msa "-mmsa"] } {
11670 lappend EFFECTIVE_TARGETS mips_msa
11672 return [llength $EFFECTIVE_TARGETS]
11673 } elseif [istarget sparc*-*-*] {
11674 lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
11675 if [check_effective_target_ultrasparc_hw] {
11676 set dg-do-what-default run
11678 set dg-do-what-default compile
11680 } elseif [istarget alpha*-*-*] {
11681 # Alpha's vectorization capabilities are extremely limited.
11682 # It
's more effort than its worth disabling all of the tests
11683 # that it cannot pass. But if you actually want to see what
11684 # does work, command out the return.
11687 lappend DEFAULT_VECTCFLAGS "-mmax"
11688 if [check_alpha_max_hw_available] {
11689 set dg-do-what-default run
11691 set dg-do-what-default compile
11693 } elseif [istarget ia64-*-*] {
11694 set dg-do-what-default run
11695 } elseif [is-effective-target arm_neon_ok] {
11696 eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
11697 # NEON does not support denormals, so is not used for vectorization by
11698 # default to avoid loss of precision. We must pass -ffast-math to test
11699 # vectorization of float operations.
11700 lappend DEFAULT_VECTCFLAGS "-ffast-math"
11701 if [is-effective-target arm_neon_hw] {
11702 set dg-do-what-default run
11704 set dg-do-what-default compile
11706 } elseif [istarget aarch64*-*-*] {
11707 set dg-do-what-default run
11708 } elseif [istarget s390*-*-*] {
11709 # The S/390 backend set a default of 2 for that value.
11710 # Override it to have the same situation as with other
11712 lappend DEFAULT_VECTCFLAGS "--param" "min-vect-loop-bound=1"
11713 lappend DEFAULT_VECTCFLAGS "--param" "max-unrolled-insns=200"
11714 lappend DEFAULT_VECTCFLAGS "--param" "max-unroll-times=8"
11715 lappend DEFAULT_VECTCFLAGS "--param" "max-completely-peeled-insns=200"
11716 lappend DEFAULT_VECTCFLAGS "--param" "max-completely-peel-times=16"
11717 if [check_effective_target_s390_vxe2] {
11718 lappend DEFAULT_VECTCFLAGS "-march=z15" "-mzarch"
11719 set dg-do-what-default run
11720 } elseif [check_effective_target_s390_vxe] {
11721 lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
11722 set dg-do-what-default run
11723 } elseif [check_effective_target_s390_vx] {
11724 lappend DEFAULT_VECTCFLAGS "-march=z13" "-mzarch"
11725 set dg-do-what-default run
11727 lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
11728 set dg-do-what-default compile
11730 } elseif [istarget amdgcn-*-*] {
11731 set dg-do-what-default run
11732 } elseif [istarget riscv*-*-*] {
11733 if [check_effective_target_riscv_v] {
11734 set dg-do-what-default run
11736 foreach item [add_options_for_riscv_v ""] {
11737 lappend DEFAULT_VECTCFLAGS $item
11739 set dg-do-what-default compile
11741 } elseif [istarget loongarch*-*-*] {
11742 # Set the default vectorization option to "-mlsx" due to the problem
11743 # of non-aligned memory access when using 256-bit vectorization.
11744 lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlsx"
11745 if [check_effective_target_loongarch_sx_hw] {
11746 set dg-do-what-default run
11748 set dg-do-what-default compile
11757 # Return 1 if the target does *not* require strict alignment.
11759 proc check_effective_target_non_strict_align {} {
11761 # On ARM, the default is to use STRICT_ALIGNMENT, but there
11762 # are interfaces defined for misaligned access and thus
11763 # depending on the architecture levels unaligned access is
11765 if [istarget "arm*-*-*"] {
11766 return [check_effective_target_arm_unaligned]
11769 return [check_no_compiler_messages non_strict_align assembly {
11771 typedef char __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))) c;
11773 void foo(void) { z = (c *) y; }
11777 # Return 1 if the target supports -mstrict-align (and -mno-strict-align).
11779 proc check_effective_target_opt_mstrict_align {} {
11780 return [check_no_compiler_messages opt_mstrict_align assembly {
11782 } "-mstrict-align -mno-strict-align"]
11785 # Return 1 if the target has <ucontext.h>.
11787 proc check_effective_target_ucontext_h { } {
11788 return [check_no_compiler_messages ucontext_h assembly {
11789 #include <ucontext.h>
11793 proc check_effective_target_aarch64_tiny { } {
11794 if { [istarget aarch64*-*-*] } {
11795 return [check_no_compiler_messages aarch64_tiny object {
11796 #ifdef __AARCH64_CMODEL_TINY__
11799 #error target not AArch64 tiny code model
11807 # Create functions to check that the AArch64 assembler supports the
11808 # various architecture extensions via the .arch_extension pseudo-op.
11810 foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve"
11811 "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64"
11812 "sme" "sme-i16i64" "sme2" } {
11813 eval [string map [list FUNC $aarch64_ext] {
11814 proc check_effective_target_aarch64_asm_FUNC_ok { } {
11815 if { [istarget aarch64*-*-*] } {
11816 return [check_no_compiler_messages aarch64_FUNC_assembler object {
11817 __asm__ (".arch_extension FUNC");
11818 } "-march=armv8-a+FUNC"]
11826 proc check_effective_target_aarch64_small { } {
11827 if { [istarget aarch64*-*-*] } {
11828 return [check_no_compiler_messages aarch64_small object {
11829 #ifdef __AARCH64_CMODEL_SMALL__
11832 #error target not AArch64 small code model
11840 proc check_effective_target_aarch64_large { } {
11841 if { [istarget aarch64*-*-*] } {
11842 return [check_no_compiler_messages aarch64_large object {
11843 #ifdef __AARCH64_CMODEL_LARGE__
11846 #error target not AArch64 large code model
11854 # Return 1 if the assembler accepts the aarch64 .variant_pcs directive.
11856 proc check_effective_target_aarch64_variant_pcs { } {
11857 if { [istarget aarch64*-*-*] } {
11858 return [check_no_compiler_messages aarch64_variant_pcs object {
11859 __asm__ (".variant_pcs foo");
11866 # Return 1 if this is a reduced AVR Tiny core. Such cores have different
11867 # register set, instruction set, addressing capabilities and ABI.
11869 proc check_effective_target_avr_tiny { } {
11870 if { [istarget avr*-*-*] } {
11871 return [check_no_compiler_messages avr_tiny object {
11872 #ifdef __AVR_TINY__
11875 #error target not a reduced AVR Tiny core
11883 # Return 1 if <fenv.h> is available.
11885 proc check_effective_target_fenv {} {
11886 return [check_no_compiler_messages fenv object {
11888 } [add_options_for_ieee "-std=gnu99"]]
11891 # Return 1 if <fenv.h> is available with all the standard IEEE
11892 # exceptions and floating-point exceptions are raised by arithmetic
11893 # operations. (If the target requires special options for "inexact"
11894 # exceptions, those need to be specified in the testcases.)
11896 proc check_effective_target_fenv_exceptions {} {
11897 return [check_runtime fenv_exceptions {
11899 #include <stdlib.h>
11900 #ifndef FE_DIVBYZERO
11901 # error Missing FE_DIVBYZERO
11904 # error Missing FE_INEXACT
11907 # error Missing FE_INVALID
11909 #ifndef FE_OVERFLOW
11910 # error Missing FE_OVERFLOW
11912 #ifndef FE_UNDERFLOW
11913 # error Missing FE_UNDERFLOW
11915 volatile float a = 0.0f, r;
11920 if (fetestexcept (FE_INVALID))
11925 } [add_options_for_ieee "-std=gnu99"]]
11928 # Return 1 if <fenv.h> is available with all the standard IEEE
11929 # exceptions and floating-point exceptions are raised by arithmetic
11930 # operations for decimal floating point. (If the target requires
11931 # special options for "inexact" exceptions, those need to be specified
11932 # in the testcases.)
11934 proc check_effective_target_fenv_exceptions_dfp {} {
11935 return [check_runtime fenv_exceptions_dfp {
11937 #include <stdlib.h>
11938 #ifndef FE_DIVBYZERO
11939 # error Missing FE_DIVBYZERO
11942 # error Missing FE_INEXACT
11945 # error Missing FE_INVALID
11947 #ifndef FE_OVERFLOW
11948 # error Missing FE_OVERFLOW
11950 #ifndef FE_UNDERFLOW
11951 # error Missing FE_UNDERFLOW
11953 volatile _Decimal64 a = 0.0DD, r;
11958 if (fetestexcept (FE_INVALID))
11963 } [add_options_for_ieee "-std=gnu99"]]
11966 # Return 1 if <fenv.h> is available with all the standard IEEE
11967 # exceptions and floating-point exceptions are raised by arithmetic
11968 # operations. (If the target requires special options for "inexact"
11969 # exceptions, those need to be specified in the testcases.)
11971 proc check_effective_target_fenv_exceptions_double {} {
11972 return [check_runtime fenv_exceptions_double {
11974 #include <stdlib.h>
11975 #ifndef FE_DIVBYZERO
11976 # error Missing FE_DIVBYZERO
11979 # error Missing FE_INEXACT
11982 # error Missing FE_INVALID
11984 #ifndef FE_OVERFLOW
11985 # error Missing FE_OVERFLOW
11987 #ifndef FE_UNDERFLOW
11988 # error Missing FE_UNDERFLOW
11990 volatile double a = 0.0f, r;
11995 if (fetestexcept (FE_INVALID))
12000 } [add_options_for_ieee "-std=gnu99"]]
12003 # Return 1 if <fenv.h> is available with all the standard IEEE
12004 # exceptions and floating-point exceptions are raised by arithmetic
12005 # operations. (If the target requires special options for "inexact"
12006 # exceptions, those need to be specified in the testcases.)
12008 proc check_effective_target_fenv_exceptions_long_double {} {
12009 return [check_runtime fenv_exceptions_long_double {
12011 #include <stdlib.h>
12012 #ifndef FE_DIVBYZERO
12013 # error Missing FE_DIVBYZERO
12016 # error Missing FE_INEXACT
12019 # error Missing FE_INVALID
12021 #ifndef FE_OVERFLOW
12022 # error Missing FE_OVERFLOW
12024 #ifndef FE_UNDERFLOW
12025 # error Missing FE_UNDERFLOW
12027 volatile long double a = 0.0f, r;
12032 if (fetestexcept (FE_INVALID))
12037 } [add_options_for_ieee "-std=gnu99"]]
12040 # Return 1 if -fexceptions is supported.
12042 proc check_effective_target_exceptions {} {
12043 if { [istarget amdgcn*-*-*] } {
12049 # Used to check if the testing configuration supports exceptions.
12050 # Returns 0 if exceptions are unsupported or disabled (e.g. by passing
12051 # -fno-exceptions). Returns 1 if exceptions are enabled.
12052 proc check_effective_target_exceptions_enabled {} {
12053 return [check_cached_effective_target exceptions_enabled {
12054 if { [check_effective_target_exceptions] } {
12055 return [check_no_compiler_messages exceptions_enabled assembly {
12063 # If exceptions aren't supported
, then they
're not enabled.
12069 proc check_effective_target_tiny {} {
12070 return [check_cached_effective_target tiny {
12071 if { [istarget aarch64*-*-*]
12072 && [check_effective_target_aarch64_tiny] } {
12075 if { [istarget avr-*-*]
12076 && [check_effective_target_avr_tiny] } {
12079 # PRU Program Counter is 16-bits, and trampolines are not supported.
12080 # Hence directly declare as a tiny target.
12081 if [istarget pru-*-*] {
12088 # Return 1 if the target supports -mbranch-cost=N option.
12090 proc check_effective_target_branch_cost {} {
12091 if { [ istarget arm*-*-*]
12092 || [istarget avr*-*-*]
12093 || [istarget csky*-*-*]
12094 || [istarget epiphany*-*-*]
12095 || [istarget frv*-*-*]
12096 || [istarget i?86-*-*] || [istarget x86_64-*-*]
12097 || [istarget loongarch*-*-*]
12098 || [istarget mips*-*-*]
12099 || [istarget s390*-*-*]
12100 || [istarget riscv*-*-*]
12101 || [istarget sh*-*-*] } {
12107 # Record that dg-final test TEST requires convential compilation.
12109 proc set_required_options_for { test } {
12110 if { [info proc $test] == "" } {
12111 perror "$test does not exist"
12114 proc ${test}_required_options {} {
12115 global gcc_set_required_options
12116 upvar 1 extra_tool_flags extra_tool_flags
12117 if {[regexp -- "^scan-assembler" [info level 0]]
12118 && ![string match "*-fident*" $extra_tool_flags]} {
12119 # Do not let .ident confuse assembler scan tests
12120 return [list $gcc_set_required_options "-fno-ident"]
12122 return $gcc_set_required_options
12126 # Record that dg-final test scan-ltrans-tree-dump* requires -flto-partition=one
12127 # in order to force a single partition, allowing scan-ltrans-tree-dump* to scan
12128 # a dump file *.exe.ltrans0.*.
12130 proc scan-ltrans-tree-dump_required_options {} {
12131 return "-flto-partition=one"
12133 proc scan-ltrans-tree-dump-times_required_options {} {
12134 return "-flto-partition=one"
12136 proc scan-ltrans-tree-dump-not_required_options {} {
12137 return "-flto-partition=one"
12139 proc scan-ltrans-tree-dump-dem_required_options {} {
12140 return "-flto-partition=one"
12142 proc scan-ltrans-tree-dump-dem-not_required_options {} {
12143 return "-flto-partition=one"
12146 # Return 1 if the x86-64 target supports PIE with copy reloc, 0
12147 # otherwise. Cache the result.
12149 proc check_effective_target_pie_copyreloc { } {
12151 global GCC_UNDER_TEST
12153 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12157 # Need auto-host.h to check linker support.
12158 if { ![file exists ../../auto-host.h ] } {
12162 return [check_cached_effective_target pie_copyreloc {
12163 # Set up and compile to see if linker supports PIE with copy
12164 # reloc. Include the current process ID in the file names to
12165 # prevent conflicts with invocations for multiple testsuites.
12170 set f [open $src "w"]
12171 puts $f "#include \"../../auto-host.h\""
12172 puts $f "#if HAVE_LD_PIE_COPYRELOC == 0"
12173 puts $f "# error Linker does not support PIE with copy reloc."
12177 verbose "check_effective_target_pie_copyreloc compiling testfile $src" 2
12178 set lines [${tool}_target_compile $src $obj object ""]
12183 if [string match "" $lines] then {
12184 verbose "check_effective_target_pie_copyreloc testfile compilation passed" 2
12187 verbose "check_effective_target_pie_copyreloc testfile compilation failed" 2
12193 # Return 1 if the x86-64 target supports R_X86_64_CODE_6_GOTTPOFF
12194 # relocation, 0 otherwise. Cache the result.
12196 proc check_effective_target_code_6_gottpoff_reloc { } {
12198 global GCC_UNDER_TEST
12200 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12204 # Need auto-host.h to check linker support.
12205 if { ![file exists ../../auto-host.h ] } {
12209 return [check_cached_effective_target code_6_gottpoff_reloc {
12210 # Include the current process ID in the file names to prevent
12211 # conflicts with invocations for multiple testsuites.
12213 set src code_6_gottpoff[pid].c
12214 set obj code_6_gottpoff[pid].o
12216 set f [open $src "w"]
12217 puts $f "#include \"../../auto-host.h\""
12218 puts $f "#if HAVE_AS_R_X86_64_CODE_6_GOTTPOFF == 0"
12219 puts $f "# error Assembler does not support R_X86_64_CODE_6_GOTTPOFF."
12223 verbose "check_effective_target_code_6_gottpoff_reloc compiling testfile $src" 2
12224 set lines [${tool}_target_compile $src $obj object ""]
12229 if [string match "" $lines] then {
12230 verbose "check_effective_target_code_6_gottpoff_reloc testfile compilation passed" 2
12233 verbose "check_effective_target_code_6_gottpoff_reloc testfile compilation failed" 2
12238 return $code_6_gottpoff_reloc_available_saved
12241 # Return 1 if the x86 target supports R_386_GOT32X relocation, 0
12242 # otherwise. Cache the result.
12244 proc check_effective_target_got32x_reloc { } {
12246 global GCC_UNDER_TEST
12248 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12252 # Need auto-host.h to check linker support.
12253 if { ![file exists ../../auto-host.h ] } {
12257 return [check_cached_effective_target got32x_reloc {
12258 # Include the current process ID in the file names to prevent
12259 # conflicts with invocations for multiple testsuites.
12261 set src got32x[pid].c
12262 set obj got32x[pid].o
12264 set f [open $src "w"]
12265 puts $f "#include \"../../auto-host.h\""
12266 puts $f "#if HAVE_AS_IX86_GOT32X == 0"
12267 puts $f "# error Assembler does not support R_386_GOT32X."
12271 verbose "check_effective_target_got32x_reloc compiling testfile $src" 2
12272 set lines [${tool}_target_compile $src $obj object ""]
12277 if [string match "" $lines] then {
12278 verbose "check_effective_target_got32x_reloc testfile compilation passed" 2
12281 verbose "check_effective_target_got32x_reloc testfile compilation failed" 2
12286 return $got32x_reloc_available_saved
12289 # Return 1 if the x86 target supports calling ___tls_get_addr via GOT,
12290 # 0 otherwise. Cache the result.
12292 proc check_effective_target_tls_get_addr_via_got { } {
12294 global GCC_UNDER_TEST
12296 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12300 # Need auto-host.h to check linker support.
12301 if { ![file exists ../../auto-host.h ] } {
12305 return [check_cached_effective_target tls_get_addr_via_got {
12306 # Include the current process ID in the file names to prevent
12307 # conflicts with invocations for multiple testsuites.
12309 set src tls_get_addr_via_got[pid].c
12310 set obj tls_get_addr_via_got[pid].o
12312 set f [open $src "w"]
12313 puts $f "#include \"../../auto-host.h\""
12314 puts $f "#if HAVE_AS_IX86_TLS_GET_ADDR_GOT == 0"
12315 puts $f "# error Assembler/linker do not support calling ___tls_get_addr via GOT."
12319 verbose "check_effective_target_tls_get_addr_via_got compiling testfile $src" 2
12320 set lines [${tool}_target_compile $src $obj object ""]
12325 if [string match "" $lines] then {
12326 verbose "check_effective_target_tls_get_addr_via_got testfile compilation passed" 2
12329 verbose "check_effective_target_tls_get_addr_via_got testfile compilation failed" 2
12335 # Return 1 if the target uses comdat groups.
12337 proc check_effective_target_comdat_group {} {
12338 return [check_no_messages_and_pattern comdat_group "\.section\[^\n\r]*,comdat|\.group\[^\n\r]*,#comdat" assembly {
12340 inline int foo () { return 1; }
12341 int (*fn) () = foo;
12345 # Return 1 if target supports __builtin_eh_return
12346 proc check_effective_target_builtin_eh_return { } {
12347 return [check_no_compiler_messages builtin_eh_return object {
12348 void test (long l, void *p)
12350 __builtin_eh_return (l, p);
12355 # Return 1 if the target supports max reduction for vectors.
12357 proc check_effective_target_vect_max_reduc { } {
12358 if { [istarget aarch64*-*-*] || [is-effective-target arm_neon]
12359 || [check_effective_target_riscv_v]
12360 || [check_effective_target_loongarch_sx] } {
12366 # Return 1 if the compiler has been configured with nvptx offloading.
12368 proc check_effective_target_offload_nvptx { } {
12369 return [check_no_compiler_messages offload_nvptx assembly {
12370 int main () {return 0;}
12371 } "-foffload=nvptx-none" ]
12374 # Return 1 if the compiler has been configured with gcn offloading.
12376 proc check_effective_target_offload_gcn { } {
12377 return [check_no_compiler_messages offload_gcn assembly {
12378 int main () {return 0;}
12379 } "-foffload=amdgcn-amdhsa" ]
12382 # Return 1 if the target support -fprofile-update=atomic
12383 proc check_effective_target_profile_update_atomic {} {
12384 return [check_no_compiler_messages profile_update_atomic assembly {
12385 int main (void) { return 0; }
12386 } "-fprofile-update=atomic -fprofile-generate"]
12389 # Return 1 if the target has a vector facility.
12390 proc check_effective_target_s390_mvx { } {
12391 if ![istarget s390*-*-*] then {
12395 return [check_no_compiler_messages_nocache s390_mvx assembly {
12396 #if !defined __VX__
12397 #error no vector facility.
12400 } [current_compiler_flags]]
12403 # Return 1 if vector (va - vector add) instructions are understood by
12404 # the assembler and can be executed. This also covers checking for
12405 # the VX kernel feature. A kernel without that feature does not
12406 # enable the vector facility and the following check will die with a
12408 proc check_effective_target_s390_vx { } {
12409 if ![istarget s390*-*-*] then {
12413 return [check_runtime s390_check_vx {
12416 asm ("va %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28");
12419 } "-march=z13 -mzarch" ]
12422 # Same as above but for the z14 vector enhancement facility. Test
12423 # is performed with the vector nand instruction.
12424 proc check_effective_target_s390_vxe { } {
12425 if ![istarget s390*-*-*] then {
12429 return [check_runtime s390_check_vxe {
12432 asm ("vnn %%v24, %%v26, %%v28" : : : "v24", "v26", "v28");
12435 } "-march=z14 -mzarch" ]
12438 # Same as above but for the arch13 vector enhancement facility. Test
12439 # is performed with the vector shift left double by bit instruction.
12440 proc check_effective_target_s390_vxe2 { } {
12441 if ![istarget s390*-*-*] then {
12445 return [check_runtime s390_check_vxe2 {
12448 asm ("vsld %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28");
12451 } "-march=arch13 -mzarch" ]
12454 # Same as above but for the arch14 NNPA facility.
12455 proc check_effective_target_s390_nnpa { } {
12456 if ![istarget s390*-*-*] then {
12460 return [check_runtime s390_check_nnpa {
12463 asm ("vzero %%v24\n\t"
12464 "vcrnf %%v24,%%v24,%%v24,0,2" : : : "v24");
12467 } "-march=arch14 -mzarch" ]
12470 #For versions of ARM architectures that have hardware div insn,
12471 #disable the divmod transform
12473 proc check_effective_target_arm_divmod_simode { } {
12474 return [check_no_compiler_messages arm_divmod assembly {
12475 #ifdef __ARM_ARCH_EXT_IDIV__
12476 #error has div insn
12482 # Return 1 if target supports divmod hardware insn or divmod libcall.
12484 proc check_effective_target_divmod { } {
12485 #TODO: Add checks for all targets that have either hardware divmod insn
12486 # or define libfunc for divmod.
12487 if { [istarget arm*-*-*]
12488 || [istarget i?86-*-*] || [istarget x86_64-*-*]
12489 || [istarget amdgcn-*-*] } {
12495 # Return 1 if target supports divmod for SImode. The reason for
12496 # separating this from check_effective_target_divmod is that
12497 # some versions of ARM architecture define div instruction
12498 # only for simode, and for these archs, we do not want to enable
12499 # divmod transform for simode.
12501 proc check_effective_target_divmod_simode { } {
12502 if { [istarget arm*-*-*] } {
12503 return [check_effective_target_arm_divmod_simode]
12506 return [check_effective_target_divmod]
12509 # Return 1 if store merging optimization is applicable for target.
12510 # Store merging is not profitable for targets like the avr which
12511 # can load/store only one byte at a time. Use int size as a proxy
12512 # for the number of bytes the target can write, and skip for targets
12513 # with a smallish (< 32) size.
12515 proc check_effective_target_store_merge { } {
12516 if { [is-effective-target non_strict_align ] && [is-effective-target int32plus] } {
12523 # Return 1 if we're able to assemble rdrand
12525 proc check_effective_target_rdrand
{ } {
12526 return [check_no_compiler_messages_nocache rdrand object
{
12531 __builtin_ia32_rdrand32_step
(&val
);
12537 #
Return 1 if the target supports coprocessor instructions
: cdp
, ldc
, ldcl
,
12538 # stc
, stcl
, mcr and mrc.
12539 proc check_effective_target_arm_coproc1_ok_nocache
{ } {
12540 if { ![istarget arm
*-*-*] } {
12543 return [check_no_compiler_messages_nocache arm_coproc1_ok assembly
{
12544 #
if (__thumb__
&& !__thumb2__
) || __ARM_ARCH
< 4
12547 #
include <arm_acle.h
>
12551 proc check_effective_target_arm_coproc1_ok
{ } {
12552 return [check_cached_effective_target arm_coproc1_ok \
12553 check_effective_target_arm_coproc1_ok_nocache
]
12556 #
Return 1 if the target supports all coprocessor instructions checked by
12557 # check_effective_target_arm_coproc1_ok in addition to the following
: cdp2
,
12558 # ldc2
, ldc2l
, stc2
, stc2l
, mcr2 and mrc2.
12559 proc check_effective_target_arm_coproc2_ok_nocache
{ } {
12560 if { ![check_effective_target_arm_coproc1_ok
] } {
12563 return [check_no_compiler_messages_nocache arm_coproc2_ok assembly
{
12564 #
if (__thumb__
&& !__thumb2__
) || __ARM_ARCH
< 5
12567 #
include <arm_acle.h
>
12571 proc check_effective_target_arm_coproc2_ok
{ } {
12572 return [check_cached_effective_target arm_coproc2_ok \
12573 check_effective_target_arm_coproc2_ok_nocache
]
12576 #
Return 1 if the target supports all coprocessor instructions checked by
12577 # check_effective_target_arm_coproc2_ok in addition the following
: mcrr and
12579 proc check_effective_target_arm_coproc3_ok_nocache
{ } {
12580 if { ![check_effective_target_arm_coproc2_ok
] } {
12583 return [check_no_compiler_messages_nocache arm_coproc3_ok assembly
{
12584 #
if (__thumb__
&& !__thumb2__
) \
12585 ||
(__ARM_ARCH
< 6 && !defined
(__ARM_ARCH_5TE__
))
12588 #
include <arm_acle.h
>
12592 proc check_effective_target_arm_coproc3_ok
{ } {
12593 return [check_cached_effective_target arm_coproc3_ok \
12594 check_effective_target_arm_coproc3_ok_nocache
]
12597 #
Return 1 if the target supports all coprocessor instructions checked by
12598 # check_effective_target_arm_coproc3_ok in addition the following
: mcrr2 and
12600 proc check_effective_target_arm_coproc4_ok_nocache
{ } {
12601 if { ![check_effective_target_arm_coproc3_ok
] } {
12604 return [check_no_compiler_messages_nocache arm_coproc4_ok assembly
{
12605 #
if (__thumb__
&& !__thumb2__
) || __ARM_ARCH
< 6
12608 #
include <arm_acle.h
>
12612 proc check_effective_target_arm_coproc4_ok
{ } {
12613 return [check_cached_effective_target arm_coproc4_ok \
12614 check_effective_target_arm_coproc4_ok_nocache
]
12617 #
Return 1 if the target supports the auto_inc_dec optimization pass.
12618 proc check_effective_target_autoincdec
{ } {
12619 if { ![check_no_compiler_messages auto_incdec assembly
{ void f
() { }
12620 } "-O2 -fdump-rtl-auto_inc_dec" ] } {
12624 set dumpfile
[glob
-nocomplain
"auto_incdec[pid].c.\[0-9\]\[0-9\]\[0-9\]r.auto_inc_dec"]
12625 if { [file
exists $dumpfile
] } {
12626 file
delete $dumpfile
12632 #
Return 1 if the target has support
for stack probing designed
12633 # to avoid stack
-clash style attacks.
12635 # This is used to restrict the stack
-clash mitigation tests to
12636 # just those targets that have been explicitly supported.
12638 # In addition to the prologue work
on those targets
, each target
's
12639 # properties should be described in the functions below so that
12640 # tests do not become a mess of unreadable target conditions.
12642 proc check_effective_target_supports_stack_clash_protection { } {
12644 if { [istarget x86_64-*-*] || [istarget i?86-*-*]
12645 || [istarget powerpc*-*-*] || [istarget rs6000*-*-*]
12646 || [istarget aarch64*-**] || [istarget s390*-*-*]
12647 || [istarget loongarch64*-**] } {
12653 # Return 1 if the target creates a frame pointer for non-leaf functions
12654 # Note we ignore cases where we apply tail call optimization here.
12655 proc check_effective_target_frame_pointer_for_non_leaf { } {
12656 # Solaris/x86 defaults to -fno-omit-frame-pointer.
12657 if { [istarget i?86-*-solaris*] || [istarget x86_64-*-solaris*] } {
12664 # Return 1 if the target can perform tail-call optimizations of the
12665 # most trivial type.
12666 proc check_effective_target_tail_call { } {
12667 return [check_no_messages_and_pattern tail_call ",SIBCALL" rtl-expand {
12668 __attribute__((__noipa__)) void foo (void) { }
12669 __attribute__((__noipa__)) void bar (void) { foo(); }
12670 } {-O2 -fdump-rtl-expand-all}] ;# The "SIBCALL" note requires a detailed dump.
12673 # Return 1 if the target's calling sequence or its ABI
12674 # create implicit stack probes at or prior to function entry.
12675 proc check_effective_target_caller_implicit_probes
{ } {
12677 #
On x86
/x86_64 the
call instruction itself pushes the
return
12678 # address onto the stack. That is an implicit probe of
*sp.
12679 if { [istarget x86_64
-*-*] ||
[istarget i?
86-*-*] } {
12683 #
On PPC
, the ABI mandates that the address of the outer
12684 # frame be stored at
*sp. Thus each allocation of stack
12685 # space is itself an implicit probe of
*sp.
12686 if { [istarget powerpc
*-*-*] ||
[istarget rs6000
*-*-*] } {
12690 # s390
's ABI has a register save area allocated by the
12691 # caller for use by the callee. The mere existence does
12692 # not constitute a probe by the caller, but when the slots
12693 # used by the callee those stores are implicit probes.
12694 if { [istarget s390*-*-*] } {
12698 # Not strictly true on aarch64, but we have agreed that we will
12699 # consider any function that pushes SP more than 3kbytes into
12700 # the guard page as broken. This essentially means that we can
12701 # consider the aarch64 as having a caller implicit probe at
12703 if { [istarget aarch64*-*-*] } {
12707 if { [istarget loongarch64*-*-*] } {
12714 # Targets that potentially realign the stack pointer often cause residual
12715 # stack allocations and make it difficult to elimination loops or residual
12716 # allocations for dynamic stack allocations
12717 proc check_effective_target_callee_realigns_stack { } {
12718 if { [istarget x86_64-*-*] || [istarget i?86-*-*] } {
12724 # Return 1 if CET instructions can be compiled.
12725 proc check_effective_target_cet { } {
12726 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12729 return [check_no_compiler_messages cet object {
12734 } "-O2 -fcf-protection" ]
12737 # Return 1 if target supports floating point "infinite"
12738 proc check_effective_target_inf { } {
12739 return [check_no_compiler_messages supports_inf assembly {
12740 const double pinf = __builtin_inf ();
12744 # Return 1 if target supports floating point "infinite" for float.
12745 proc check_effective_target_inff { } {
12746 return [check_no_compiler_messages supports_inff assembly {
12747 const float pinf = __builtin_inff ();
12751 # Return 1 if the target supports ARMv8.3 Adv.SIMD Complex instructions
12752 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
12753 # Record the command line options needed.
12755 proc check_effective_target_arm_v8_3a_complex_neon_ok_nocache { } {
12756 global et_arm_v8_3a_complex_neon_flags
12757 set et_arm_v8_3a_complex_neon_flags ""
12759 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
12763 # Iterate through sets of options to find the compiler flags that
12764 # need to be added to the -march option.
12765 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
12766 if { [check_no_compiler_messages_nocache \
12767 arm_v8_3a_complex_neon_ok assembly {
12768 #if !defined (__ARM_FEATURE_COMPLEX)
12769 #error "__ARM_FEATURE_COMPLEX not defined"
12771 } "$flags -march=armv8.3-a"] } {
12772 set et_arm_v8_3a_complex_neon_flags "$flags -march=armv8.3-a"
12780 proc check_effective_target_arm_v8_3a_complex_neon_ok { } {
12781 return [check_cached_effective_target arm_v8_3a_complex_neon_ok \
12782 check_effective_target_arm_v8_3a_complex_neon_ok_nocache]
12785 proc add_options_for_arm_v8_3a_complex_neon { flags } {
12786 if { ! [check_effective_target_arm_v8_3a_complex_neon_ok] } {
12789 global et_arm_v8_3a_complex_neon_flags
12790 return "$flags $et_arm_v8_3a_complex_neon_flags"
12793 # Return 1 if the target supports ARMv8.3 Adv.SIMD + FP16 Complex instructions
12794 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
12795 # Record the command line options needed.
12797 proc check_effective_target_arm_v8_3a_fp16_complex_neon_ok_nocache { } {
12798 global et_arm_v8_3a_fp16_complex_neon_flags
12799 set et_arm_v8_3a_fp16_complex_neon_flags ""
12801 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
12805 # Iterate through sets of options to find the compiler flags that
12806 # need to be added to the -march option.
12807 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
12808 if { [check_no_compiler_messages_nocache \
12809 arm_v8_3a_fp16_complex_neon_ok assembly {
12810 #if !defined (__ARM_FEATURE_COMPLEX)
12811 #error "__ARM_FEATURE_COMPLEX not defined"
12813 } "$flags -march=armv8.3-a+fp16"] } {
12814 set et_arm_v8_3a_fp16_complex_neon_flags \
12815 "$flags -march=armv8.3-a+fp16"
12823 proc check_effective_target_arm_v8_3a_fp16_complex_neon_ok { } {
12824 return [check_cached_effective_target arm_v8_3a_fp16_complex_neon_ok \
12825 check_effective_target_arm_v8_3a_fp16_complex_neon_ok_nocache]
12828 proc add_options_for_arm_v8_3a_fp16_complex_neon { flags } {
12829 if { ! [check_effective_target_arm_v8_3a_fp16_complex_neon_ok] } {
12832 global et_arm_v8_3a_fp16_complex_neon_flags
12833 return "$flags $et_arm_v8_3a_fp16_complex_neon_flags"
12837 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.3
12838 # with the complex instruction extension, 0 otherwise. The test is valid for
12839 # ARM and for AArch64.
12841 proc check_effective_target_arm_v8_3a_complex_neon_hw { } {
12842 if { ![check_effective_target_arm_v8_3a_complex_neon_ok] } {
12845 return [check_runtime arm_v8_3a_complex_neon_hw_available {
12846 #include "arm_neon.h"
12851 float32x2_t results = {-4.0,5.0};
12852 float32x2_t a = {1.0,3.0};
12853 float32x2_t b = {2.0,5.0};
12855 #ifdef __ARM_ARCH_ISA_A64
12856 asm ("fcadd %0.2s, %1.2s, %2.2s, #90"
12859 : /* No clobbers. */);
12862 asm ("vcadd.f32 %P0, %P1, %P2, #90"
12865 : /* No clobbers. */);
12868 return (results[0] == 8 && results[1] == 24) ? 0 : 1;
12870 } [add_options_for_arm_v8_3a_complex_neon ""]]
12873 # Return 1 if the assembler supports assembling the Armv8.3 pointer authentication B key directive
12874 proc check_effective_target_arm_v8_3a_bkey_directive { } {
12875 return [check_no_compiler_messages cet object {
12877 asm (".cfi_b_key_frame");
12883 # Return 1 if the target supports executing the Armv8.1-M Mainline Low
12884 # Overhead Loop, 0 otherwise. The test is valid for ARM.
12886 proc check_effective_target_arm_v8_1_lob_ok { } {
12887 if { ![check_effective_target_arm_cortex_m] } {
12890 return [check_runtime arm_v8_1_lob_hw_available {
12894 asm ("movw r3, #10\n\t" /* movs? */
12895 "dls lr, r3" : : : "r3", "lr");
12898 asm goto ("le lr, %l0" : : : "lr" : loop);
12901 } "-march=armv8.1-m.main -mthumb" ]
12905 # Return 1 if this is an ARM target where Thumb-2 is used without
12906 # options added by the test and the target does not support executing
12907 # the Armv8.1-M Mainline Low Overhead Loop, 0 otherwise. The test is
12910 proc check_effective_target_arm_thumb2_no_arm_v8_1_lob { } {
12911 if { [check_effective_target_arm_thumb2]
12912 && ![check_effective_target_arm_v8_1_lob_ok] } {
12918 # Return 1 if this is an ARM target where -mthumb causes Thumb-2 to be
12919 # used and the target does not support executing the Armv8.1-M
12920 # Mainline Low Overhead Loop, 0 otherwise. The test is valid for ARM.
12922 proc check_effective_target_arm_thumb2_ok_no_arm_v8_1_lob { } {
12923 if { [check_effective_target_arm_thumb2_ok]
12924 && ![check_effective_target_arm_v8_1_lob_ok] } {
12930 # Returns 1 if the target is using glibc, 0 otherwise.
12932 proc check_effective_target_glibc { } {
12933 return [check_no_compiler_messages glibc_object assembly {
12934 #include <stdlib.h>
12935 #if !defined(__GLIBC__)
12941 # Return 1 if the target plus current options supports a vector
12942 # complex addition with rotate of half and single float modes, 0 otherwise.
12944 # This won't change
for different subtargets so
cache the result.
12946 foreach N
{hf sf
} {
12947 eval
[string map
[list N $N
] {
12948 proc check_effective_target_vect_complex_rot_N
{ } {
12949 return [check_cached_effective_target_indexed vect_complex_rot_N
{
12950 expr
{ [istarget aarch64
*-*-*]
12951 ||
[istarget arm
*-*-*] }}]
12956 #
Return 1 if the target plus current options supports a vector
12957 # complex addition with rotate of double float modes
, 0 otherwise.
12959 # This won
't change for different subtargets so cache the result.
12962 eval [string map [list N $N] {
12963 proc check_effective_target_vect_complex_rot_N { } {
12964 return [check_cached_effective_target_indexed vect_complex_rot_N {
12965 expr { [istarget aarch64*-*-*] }}]
12970 # Return 1 if this target uses an LLVM assembler and/or linker
12971 proc check_effective_target_llvm_binutils { } {
12972 return [check_cached_effective_target llvm_binutils {
12973 expr { [istarget amdgcn*-*-*]
12974 || [check_effective_target_offload_gcn] }}]
12977 # Return 1 if the compiler supports '-mfentry
'.
12979 proc check_effective_target_mfentry { } {
12980 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12983 return [check_no_compiler_messages mfentry object {
12984 void foo (void) { }
12988 # Return 1 if this target supports indirect calls
12989 proc check_effective_target_indirect_calls { } {
12990 if { [istarget bpf-*-*] } {
12996 # Return 1 if we can use the -lgccjit option, 0 otherwise.
12998 proc check_effective_target_lgccjit { } {
12999 if { [info procs jit_target_compile] == "" } then {
13000 global GCC_UNDER_TEST
13001 if ![info exists GCC_UNDER_TEST] {
13002 set GCC_UNDER_TEST "[find_gcc]"
13004 proc jit_target_compile { source dest type options } [info body gcc_target_compile]
13006 return [check_no_compiler_messages lgccjit executable {
13007 int main() { return 0; }
13011 # Return 1 if the MSP430 small memory model is in use.
13012 proc check_effective_target_msp430_small {} {
13013 return [check_no_compiler_messages msp430_small assembly {
13014 #if (!defined __MSP430__ || defined __MSP430X_LARGE__)
13015 #error !msp430 || __MSP430X_LARGE__
13020 # Return 1 if the MSP430 large memory model is in use.
13021 proc check_effective_target_msp430_large {} {
13022 return [check_no_compiler_messages msp430_large assembly {
13023 #ifndef __MSP430X_LARGE__
13024 #error __MSP430X_LARGE__
13029 # Return 1 if GCC was configured with --with-tune=cortex-a76
13030 proc check_effective_target_tune_cortex_a76 { } {
13031 return [check_configured_with "with-tune=cortex-a76"]
13034 # Return 1 if the target has an efficient means to encode large initializers
13037 proc check_effective_target_large_initializer { } {
13038 if { [istarget nvptx*-*-*] } {
13045 # Return 1 if the target allows function prototype mismatches
13048 proc check_effective_target_non_strict_prototype { } {
13049 if { [istarget nvptx*-*-*] } {
13056 # Returns 1 if the target toolchain supports extended
13057 # syntax of .symver directive, 0 otherwise.
13059 proc check_symver_available { } {
13060 return [check_no_compiler_messages symver_available object {
13061 int foo(void) { return 0; }
13063 asm volatile (".symver foo,foo@VER_1, local");
13069 # Return 1 if emitted assembly contains .ident directive.
13071 proc check_effective_target_ident_directive {} {
13072 return [check_no_messages_and_pattern ident_directive \
13073 "(?n)^\[\t\]+\\.ident" assembly {
13078 # Return 1 if we're able to assemble movdiri and movdir64b
13080 proc check_effective_target_movdir
{ } {
13081 return [check_no_compiler_messages movdir object
{
13083 foo
(unsigned
int *d
, unsigned
int s
)
13085 __builtin_ia32_directstoreu_u32
(d
, s
);
13088 bar
(void
*d
, const void
*s
)
13090 __builtin_ia32_movdir64b
(d
, s
);
13092 } "-mmovdiri -mmovdir64b" ]
13095 #
Return 1 if the target does not support address sanitizer
, 0 otherwise
13097 proc check_effective_target_no_fsanitize_address
{} {
13098 if ![check_no_compiler_messages fsanitize_address executable
{
13099 int main
(void
) { return 0; }
13100 } "-fsanitize=address" ] {
13107 #
Return 1 if this target supports
'R' flag in .section directive
, 0
13108 # otherwise.
Cache the result.
13110 proc check_effective_target_R_flag_in_section
{ } {
13112 global GCC_UNDER_TEST
13114 # Need auto
-host.h to check linker support.
13115 if { ![file
exists ..
/..
/auto
-host.h
] } {
13119 return [check_cached_effective_target R_flag_in_section
{
13124 set f
[open $src
"w"]
13125 puts $f
"#include \"../../auto-host.h\""
13126 puts $f
"#if HAVE_GAS_SHF_GNU_RETAIN == 0 || HAVE_INITFINI_ARRAY_SUPPORT == 0"
13127 puts $f
"# error Assembler does not support 'R' flag in .section directive."
13131 verbose
"check_effective_target_R_flag_in_section compiling testfile $src" 2
13132 set lines
[$
{tool
}_target_compile $src $
obj assembly
""]
13137 if [string match
"" $lines] then {
13138 verbose
"check_effective_target_R_flag_in_section testfile compilation passed" 2
13141 verbose
"check_effective_target_R_flag_in_section testfile compilation failed" 2
13147 #
Return 1 if this target supports
'o' flag in .section directive
, 0
13148 # otherwise.
Cache the result.
13150 proc check_effective_target_o_flag_in_section
{ } {
13152 global GCC_UNDER_TEST
13154 # Need auto
-host.h to check linker support.
13155 if { ![file
exists ..
/..
/auto
-host.h
] } {
13159 return [check_cached_effective_target o_flag_in_section
{
13164 set f
[open $src
"w"]
13165 puts $f
"#include \"../../auto-host.h\""
13166 puts $f
"#if HAVE_GAS_SECTION_LINK_ORDER == 0"
13167 puts $f
"# error Assembler does not support 'o' flag in .section directive."
13171 verbose
"check_effective_target_o_flag_in_section compiling testfile $src" 2
13172 set lines
[$
{tool
}_target_compile $src $
obj object
""]
13177 if [string match
"" $lines] then {
13178 verbose
"check_effective_target_o_flag_in_section testfile compilation passed" 2
13181 verbose
"check_effective_target_o_flag_in_section testfile compilation failed" 2
13187 #
Return 1 if the given assembler supports hardware transactional memory
13188 # instructions with machine type Power10
, 0 otherwise.
Cache the result.
13190 proc check_effective_target_powerpc_as_p10_htm
{ } {
13192 global GCC_UNDER_TEST
13194 # Need auto
-host.h to check linker support.
13195 if { ![file
exists ..
/..
/auto
-host.h
] } {
13199 return [check_cached_effective_target powerpc_as_p10_htm
{
13204 set f
[open $src
"w"]
13205 puts $f
"#include \"../../auto-host.h\""
13206 puts $f
"#if HAVE_AS_POWER10_HTM == 0"
13207 puts $f
"# error Assembler does not support htm insns with power10."
13211 verbose
"check_effective_target_powerpc_as_p10_htm compiling testfile $src" 2
13212 set lines
[$
{tool
}_target_compile $src $
obj object
""]
13217 if [string match
"" $lines] then {
13218 verbose
"check_effective_target_powerpc_as_p10_htm testfile compilation passed" 2
13221 verbose
"check_effective_target_powerpc_as_p10_htm testfile compilation failed" 2
13227 #
Return 1 if LRA is supported. This must not be called
(results in ERROR
) for
13228 # targets that don
't do register allocation, and therefore neither use nor
13231 proc check_effective_target_lra
{ } {
13232 # Start with heavily used targets which are known to always use LRA.
13233 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
13234 ||
[istarget aarch64
*-*-*] ||
[istarget arm
*-*-*]
13235 ||
[istarget powerpc
*-*-*] ||
[istarget riscv
*-*-*] } {
13239 # Otherwise check the reload dump
for messages emitted solely by LRA.
13240 return [check_no_messages_and_pattern lra
"\\\*{9} Local #1: \\\*{9}" rtl-reload {
13242 } {-O2
-fdump
-rtl
-reload
-details
}] ;# LRA notes requires a detailed dump.
13245 #
Return 1 if 'asm goto' with outputs is supported
, 0 otherwise.
13247 proc check_effective_target_asm_goto_with_outputs
{ } {
13248 if { [istarget nvptx
-*-*] } {
13251 return [check_effective_target_lra
]
13254 # Test whether optimizations are enabled
('__OPTIMIZE__') per the
13255 #
'current_compiler_flags' (thus don
't cache).
13257 proc check_effective_target___OPTIMIZE__ {} {
13258 return [check_no_compiler_messages_nocache __OPTIMIZE__ assembly {
13259 #ifndef __OPTIMIZE__
13262 /* Avoid pedwarn about empty TU. */
13264 } [current_compiler_flags]]
13267 # Return 1 if python3 (>= 3.6) is available.
13269 proc check_effective_target_recent_python3 { } {
13270 set result [remote_exec host "python3 -c \"import sys; assert sys.version_info >= (3, 6)\""]
13271 set status [lindex $result 0]
13272 if { $status == 0 } then {
13279 # Return 1 if python3 contains a module
13281 proc check_effective_target_python3_module { module } {
13282 set result [remote_exec host "python3 -c \"import $module\""]
13283 set status [lindex $result 0]
13284 if { $status == 0 } then {
13291 # Return 1 if pytest module is available for python3.
13293 proc check_effective_target_pytest3 { } {
13294 set result [remote_exec host "python3 -m pytest --color=no -rap -s --tb=no --version"]
13295 set status [lindex $result 0]
13296 if { $status == 0 } then {
13303 proc check_effective_target_property_1_needed { } {
13304 return [check_no_compiler_messages property_1_needed executable {
13305 /* Assembly code */
13307 # define __PROPERTY_ALIGN 3
13309 # define __PROPERTY_ALIGN 2
13312 .section ".note.gnu.property", "a"
13313 .p2align __PROPERTY_ALIGN
13314 .long 1f - 0f /* name length. */
13315 .long 4f - 1f /* data length. */
13316 /* NT_GNU_PROPERTY_TYPE_0. */
13317 .long 5 /* note type. */
13319 .asciz "GNU" /* vendor name. */
13321 .p2align __PROPERTY_ALIGN
13322 /* GNU_PROPERTY_1_NEEDED. */
13323 .long 0xb0008000 /* pr_type. */
13324 .long 3f - 2f /* pr_datasz. */
13326 /* GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS. */
13329 .p2align __PROPERTY_ALIGN
13338 # Return 1 if this target has prog named "$prog", 0 otherwise.
13340 proc check_is_prog_name_available { prog } {
13343 set options [list "additional_flags=-print-prog-name=$prog"]
13344 set output [lindex [${tool}_target_compile "" "" "none" $options] 0]
13346 if { $output == $prog } {
13353 # returns 1 if target does selects a readonly section for const volatile variables.
13354 proc check_effective_target_const_volatile_readonly_section { } {
13356 if { [istarget powerpc-*-*]
13357 || [check-flags { "" { powerpc64-*-* } { -m32 } }] } {
13363 # Return 1 if the CORE-V MAC extension is available.
13364 proc check_effective_target_cv_mac { } {
13365 if { !([istarget riscv*-*-*]) } {
13368 return [check_no_compiler_messages cv_mac object {
13371 asm ("cv.mac t0, t1, t2");
13373 } "-march=rv32i_xcvmac" ]
13376 # Return 1 if the CORE-V ALU extension is available.
13377 proc check_effective_target_cv_alu { } {
13378 if { !([istarget riscv*-*-*]) } {
13381 return [check_no_compiler_messages cv_alu object {
13384 asm ("cv.addn t0, t1, t2, 0");
13386 } "-march=rv32i_xcvalu" ]
13389 # Return 1 if the CORE-V ELW extension is available.
13390 proc check_effective_target_cv_elw { } {
13391 if { !([istarget riscv*-*-*]) } {
13394 return [check_no_compiler_messages cv_elw object {
13397 asm ("cv.elw x0, 0(x0)");
13399 } "-march=rv32i_xcvelw" ]
13402 # Return 1 if the CORE-V SIMD extension is available.
13403 proc check_effective_target_cv_simd { } {
13404 if { !([istarget riscv*-*-*]) } {
13407 return [check_no_compiler_messages cv_simd object {
13410 asm ("cv.add.sc.b x0, x0, x0");
13412 } "-march=rv32i_xcvsimd" ]
13415 # Return 1 if the CORE-V BI extension is available
13416 proc check_effective_target_cv_bi { } {
13417 if { !([istarget riscv*-*-*]) } {
13420 return [check_no_compiler_messages cv_bi object {
13423 asm ("cv.beqimm t0, -16, foo");
13425 } "-march=rv32i_xcvbi" ]
13428 proc check_effective_target_loongarch_sx { } {
13429 return [check_no_compiler_messages loongarch_lsx assembly {
13430 #if !defined(__loongarch_sx)
13431 #error "LSX not defined"
13436 proc check_effective_target_loongarch_sx_as { } {
13437 return [check_no_compiler_messages loongarch_sx_as object {
13438 #include <lsxintrin.h>
13442 c = __lsx_vand_v (a, b);
13448 proc check_effective_target_loongarch_sx_hw { } {
13449 return [check_runtime loongarch_sx_hw {
13450 #include <lsxintrin.h>
13454 c = __lsx_vand_v (a, b);
13460 proc check_effective_target_loongarch_asx { } {
13461 return [check_no_compiler_messages loongarch_asx assembly {
13462 #if !defined(__loongarch_asx)
13463 #error "LASX not defined"
13468 proc check_effective_target_loongarch_asx_hw { } {
13469 return [check_runtime loongarch_asx_hw {
13470 #include <lasxintrin.h>
13474 c = __lasx_xvand_v (a, b);
13480 # Check whether LoongArch binutils supports call36 relocation.
13481 proc check_effective_target_loongarch_call36_support { } {
13482 return [check_no_compiler_messages loongarch_call36_support object {
13483 /* Assembly code */
13484 pcaddu18i $r1,%call36(a)
13489 # Returns 1 if binutils supports TLS le Relax, 0 otherwise.
13490 proc check_effective_target_tls_le_relax { } {
13491 if [check_effective_target_tls_native] {
13492 return [check_no_compiler_messages loongarch_tls_le_relax object {
13493 /* Assembly code */
13494 lu12i.w $r12, %le_hi20_r(a)
13501 # Appends necessary Python flags to extra-tool-flags if Python.h is supported.
13502 # Otherwise, modifies dg-do-what.
13503 proc dg-require-python-h { args } {
13504 upvar dg-extra-tool-flags extra-tool-flags
13506 verbose "ENTER dg-require-python-h" 2
13509 set result [remote_exec host "python3-config --includes"]
13510 set status [lindex $result 0]
13511 if { $status == 0 } {
13512 # Remove trailing newline from python3-config output.
13513 set python_flags [string trim [lindex $result 1]]
13514 if [check_no_compiler_messages python_h assembly {
13515 #include <Python.h>
13516 int main (void) { return 0; }
13522 if { $supported == 0 } {
13523 verbose "Python.h not supported" 2
13524 upvar dg-do-what dg-do-what
13525 set dg-do-what [list [lindex ${dg-do-what} 0] "N" "P"]
13529 verbose "Python flags are: $python_flags" 2
13531 verbose "Before appending, extra-tool-flags: ${extra-tool-flags}" 3
13532 eval lappend extra-tool-flags $python_flags
13533 verbose "After appending, extra-tool-flags: ${extra-tool-flags}" 3
13536 # Return 1 if the target supports heap-trampoline, 0 otherwise.
13537 proc check_effective_target_heap_trampoline {} {
13538 if { [istarget aarch64*-*-linux*]
13539 || [istarget i?86-*-darwin*]
13540 || [istarget x86_64-*-darwin*]
13541 || [istarget i?86-*-linux*]
13542 || [istarget x86_64-*-linux*] } {