gcc/config/aarch64/aarch64-builtins.h

   1 /* Builtins' description for AArch64 SIMD architecture.
   2    Copyright (C) 2023-2024 Free Software Foundation, Inc.
   3    This file is part of GCC.
   4
   5    GCC is free software; you can redistribute it and/or modify it
   6    under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 3, or (at your option)
   8    any later version.
   9
  10    GCC is distributed in the hope that it will be useful, but
  11    WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with GCC; see the file COPYING3.  If not see
  17    <http://www.gnu.org/licenses/>.  */
  18 #ifndef GCC_AARCH64_BUILTINS_H
  19 #define GCC_AARCH64_BUILTINS_H
  20
  21 enum aarch64_type_qualifiers
  22 {
  23   /* T foo.  */
  24   qualifier_none = 0x0,
  25   /* unsigned T foo.  */
  26   qualifier_unsigned = 0x1, /* 1 << 0  */
  27   /* const T foo.  */
  28   qualifier_const = 0x2, /* 1 << 1  */
  29   /* T *foo.  */
  30   qualifier_pointer = 0x4, /* 1 << 2  */
  31   /* Used when expanding arguments if an operand could
  32      be an immediate.  */
  33   qualifier_immediate = 0x8, /* 1 << 3  */
  34   qualifier_maybe_immediate = 0x10, /* 1 << 4  */
  35   /* void foo (...).  */
  36   qualifier_void = 0x20, /* 1 << 5  */
  37   /* 1 << 6 is now unused */
  38   /* Some builtins should use the T_*mode* encoded in a simd_builtin_datum
  39      rather than using the type of the operand.  */
  40   qualifier_map_mode = 0x80, /* 1 << 7  */
  41   /* qualifier_pointer | qualifier_map_mode  */
  42   qualifier_pointer_map_mode = 0x84,
  43   /* qualifier_const | qualifier_pointer | qualifier_map_mode  */
  44   qualifier_const_pointer_map_mode = 0x86,
  45   /* Polynomial types.  */
  46   qualifier_poly = 0x100,
  47   /* Lane indices - must be in range, and flipped for bigendian.  */
  48   qualifier_lane_index = 0x200,
  49   /* Lane indices for single lane structure loads and stores.  */
  50   qualifier_struct_load_store_lane_index = 0x400,
  51   /* Lane indices selected in pairs. - must be in range, and flipped for
  52      bigendian.  */
  53   qualifier_lane_pair_index = 0x800,
  54   /* Lane indices selected in quadtuplets. - must be in range, and flipped for
  55      bigendian.  */
  56   qualifier_lane_quadtup_index = 0x1000,
  57 };
  58
  59 #define ENTRY(E, M, Q, G) E,
  60 enum aarch64_simd_type
  61 {
  62 #include "aarch64-simd-builtin-types.def"
  63   ARM_NEON_H_TYPES_LAST
  64 };
  65 #undef ENTRY
  66
  67 struct GTY(()) aarch64_simd_type_info
  68 {
  69   enum aarch64_simd_type type;
  70
  71   /* Internal type name.  */
  72   const char *name;
  73
  74   /* Internal type name(mangled).  The mangled names conform to the
  75      AAPCS64 (see "Procedure Call Standard for the ARM 64-bit Architecture",
  76      Appendix A).  To qualify for emission with the mangled names defined in
  77      that document, a vector type must not only be of the correct mode but also
  78      be of the correct internal AdvSIMD vector type (e.g. __Int8x8_t); these
  79      types are registered by aarch64_init_simd_builtin_types ().  In other
  80      words, vector types defined in other ways e.g. via vector_size attribute
  81      will get default mangled names.  */
  82   const char *mangle;
  83
  84   /* Internal type.  */
  85   tree itype;
  86
  87   /* Element type.  */
  88   tree eltype;
  89
  90   /* Machine mode the internal type maps to.  */
  91   enum machine_mode mode;
  92
  93   /* Qualifiers.  */
  94   enum aarch64_type_qualifiers q;
  95 };
  96
  97 extern aarch64_simd_type_info aarch64_simd_types[];
  98
  99 #endif