gcc/config/mips/mips-dspr2.md

   1 ;; Copyright (C) 2007 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18 ;;
  19 ; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
  20
  21 (define_c_enum "unspec" [
  22   UNSPEC_ABSQ_S_QB
  23   UNSPEC_ADDU_PH
  24   UNSPEC_ADDU_S_PH
  25   UNSPEC_ADDUH_QB
  26   UNSPEC_ADDUH_R_QB
  27   UNSPEC_APPEND
  28   UNSPEC_BALIGN
  29   UNSPEC_CMPGDU_EQ_QB
  30   UNSPEC_CMPGDU_LT_QB
  31   UNSPEC_CMPGDU_LE_QB
  32   UNSPEC_DPA_W_PH
  33   UNSPEC_DPS_W_PH
  34   UNSPEC_MADD
  35   UNSPEC_MADDU
  36   UNSPEC_MSUB
  37   UNSPEC_MSUBU
  38   UNSPEC_MUL_PH
  39   UNSPEC_MUL_S_PH
  40   UNSPEC_MULQ_RS_W
  41   UNSPEC_MULQ_S_PH
  42   UNSPEC_MULQ_S_W
  43   UNSPEC_MULSA_W_PH
  44   UNSPEC_MULT
  45   UNSPEC_MULTU
  46   UNSPEC_PRECR_QB_PH
  47   UNSPEC_PRECR_SRA_PH_W
  48   UNSPEC_PRECR_SRA_R_PH_W
  49   UNSPEC_PREPEND
  50   UNSPEC_SHRA_QB
  51   UNSPEC_SHRA_R_QB
  52   UNSPEC_SHRL_PH
  53   UNSPEC_SUBU_PH
  54   UNSPEC_SUBU_S_PH
  55   UNSPEC_SUBUH_QB
  56   UNSPEC_SUBUH_R_QB
  57   UNSPEC_ADDQH_PH
  58   UNSPEC_ADDQH_R_PH
  59   UNSPEC_ADDQH_W
  60   UNSPEC_ADDQH_R_W
  61   UNSPEC_SUBQH_PH
  62   UNSPEC_SUBQH_R_PH
  63   UNSPEC_SUBQH_W
  64   UNSPEC_SUBQH_R_W
  65   UNSPEC_DPAX_W_PH
  66   UNSPEC_DPSX_W_PH
  67   UNSPEC_DPAQX_S_W_PH
  68   UNSPEC_DPAQX_SA_W_PH
  69   UNSPEC_DPSQX_S_W_PH
  70   UNSPEC_DPSQX_SA_W_PH
  71 ])
  72
  73 (define_insn "mips_absq_s_qb"
  74   [(parallel
  75     [(set (match_operand:V4QI 0 "register_operand" "=d")
  76           (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
  77                        UNSPEC_ABSQ_S_QB))
  78      (set (reg:CCDSP CCDSP_OU_REGNUM)
  79           (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
  80   "ISA_HAS_DSPR2"
  81   "absq_s.qb\t%0,%z1"
  82   [(set_attr "type"     "arith")
  83    (set_attr "mode"     "SI")])
  84
  85 (define_insn "mips_addu_ph"
  86   [(parallel
  87     [(set (match_operand:V2HI 0 "register_operand" "=d")
  88           (plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
  89                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
  90      (set (reg:CCDSP CCDSP_OU_REGNUM)
  91           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
  92   "ISA_HAS_DSPR2"
  93   "addu.ph\t%0,%z1,%z2"
  94   [(set_attr "type"     "arith")
  95    (set_attr "mode"     "SI")])
  96
  97 (define_insn "mips_addu_s_ph"
  98   [(parallel
  99     [(set (match_operand:V2HI 0 "register_operand" "=d")
 100           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 101                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 102                        UNSPEC_ADDU_S_PH))
 103      (set (reg:CCDSP CCDSP_OU_REGNUM)
 104           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
 105   "ISA_HAS_DSPR2"
 106   "addu_s.ph\t%0,%z1,%z2"
 107   [(set_attr "type"     "arith")
 108    (set_attr "mode"     "SI")])
 109
 110 (define_insn "mips_adduh_qb"
 111   [(set (match_operand:V4QI 0 "register_operand" "=d")
 112         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 113                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 114                      UNSPEC_ADDUH_QB))]
 115   "ISA_HAS_DSPR2"
 116   "adduh.qb\t%0,%z1,%z2"
 117   [(set_attr "type"     "arith")
 118    (set_attr "mode"     "SI")])
 119
 120 (define_insn "mips_adduh_r_qb"
 121   [(set (match_operand:V4QI 0 "register_operand" "=d")
 122         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 123                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 124                      UNSPEC_ADDUH_R_QB))]
 125   "ISA_HAS_DSPR2"
 126   "adduh_r.qb\t%0,%z1,%z2"
 127   [(set_attr "type"     "arith")
 128    (set_attr "mode"     "SI")])
 129
 130 (define_insn "mips_append"
 131   [(set (match_operand:SI 0 "register_operand" "=d")
 132         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
 133                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
 134                     (match_operand:SI 3 "const_int_operand" "n")]
 135                    UNSPEC_APPEND))]
 136   "ISA_HAS_DSPR2"
 137 {
 138   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
 139     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
 140   return "append\t%0,%z2,%3";
 141 }
 142   [(set_attr "type"     "arith")
 143    (set_attr "mode"     "SI")])
 144
 145 (define_insn "mips_balign"
 146   [(set (match_operand:SI 0 "register_operand" "=d")
 147         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
 148                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
 149                     (match_operand:SI 3 "const_int_operand" "n")]
 150                    UNSPEC_BALIGN))]
 151   "ISA_HAS_DSPR2"
 152 {
 153   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
 154     operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
 155   return "balign\t%0,%z2,%3";
 156 }
 157   [(set_attr "type"     "arith")
 158    (set_attr "mode"     "SI")])
 159
 160 (define_insn "mips_cmpgdu_eq_qb"
 161   [(parallel
 162     [(set (match_operand:SI 0 "register_operand" "=d")
 163           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 164                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 165                      UNSPEC_CMPGDU_EQ_QB))
 166      (set (reg:CCDSP CCDSP_CC_REGNUM)
 167           (unspec:CCDSP [(match_dup 1) (match_dup 2)
 168                          (reg:CCDSP CCDSP_CC_REGNUM)]
 169                         UNSPEC_CMPGDU_EQ_QB))])]
 170   "ISA_HAS_DSPR2"
 171   "cmpgdu.eq.qb\t%0,%z1,%z2"
 172   [(set_attr "type"     "arith")
 173    (set_attr "mode"     "SI")])
 174
 175 (define_insn "mips_cmpgdu_lt_qb"
 176   [(parallel
 177     [(set (match_operand:SI 0 "register_operand" "=d")
 178           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 179                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 180                      UNSPEC_CMPGDU_LT_QB))
 181      (set (reg:CCDSP CCDSP_CC_REGNUM)
 182           (unspec:CCDSP [(match_dup 1) (match_dup 2)
 183                          (reg:CCDSP CCDSP_CC_REGNUM)]
 184                         UNSPEC_CMPGDU_LT_QB))])]
 185   "ISA_HAS_DSPR2"
 186   "cmpgdu.lt.qb\t%0,%z1,%z2"
 187   [(set_attr "type"     "arith")
 188    (set_attr "mode"     "SI")])
 189
 190 (define_insn "mips_cmpgdu_le_qb"
 191   [(parallel
 192     [(set (match_operand:SI 0 "register_operand" "=d")
 193           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 194                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 195                      UNSPEC_CMPGDU_LE_QB))
 196      (set (reg:CCDSP CCDSP_CC_REGNUM)
 197           (unspec:CCDSP [(match_dup 1) (match_dup 2)
 198                          (reg:CCDSP CCDSP_CC_REGNUM)]
 199                         UNSPEC_CMPGDU_LE_QB))])]
 200   "ISA_HAS_DSPR2"
 201   "cmpgdu.le.qb\t%0,%z1,%z2"
 202   [(set_attr "type"     "arith")
 203    (set_attr "mode"     "SI")])
 204
 205 (define_insn "mips_dpa_w_ph"
 206   [(set (match_operand:DI 0 "register_operand" "=a")
 207         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 208                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 209                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 210                    UNSPEC_DPA_W_PH))]
 211   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 212   "dpa.w.ph\t%q0,%z2,%z3"
 213   [(set_attr "type"     "imadd")
 214    (set_attr "mode"     "SI")])
 215
 216 (define_insn "mips_dps_w_ph"
 217   [(set (match_operand:DI 0 "register_operand" "=a")
 218         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 219                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 220                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 221                    UNSPEC_DPS_W_PH))]
 222   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 223   "dps.w.ph\t%q0,%z2,%z3"
 224   [(set_attr "type"     "imadd")
 225    (set_attr "mode"     "SI")])
 226
 227 (define_expand "mips_madd<u>"
 228   [(set (match_operand:DI 0 "register_operand")
 229         (plus:DI
 230          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
 231                   (any_extend:DI (match_operand:SI 3 "register_operand")))
 232          (match_operand:DI 1 "register_operand")))]
 233   "ISA_HAS_DSPR2 && !TARGET_64BIT")
 234
 235 (define_expand "mips_msub<u>"
 236   [(set (match_operand:DI 0 "register_operand")
 237         (minus:DI
 238          (match_operand:DI 1 "register_operand")
 239          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
 240                   (any_extend:DI (match_operand:SI 3 "register_operand")))))]
 241   "ISA_HAS_DSPR2 && !TARGET_64BIT")
 242
 243 (define_insn "mulv2hi3"
 244   [(parallel
 245     [(set (match_operand:V2HI 0 "register_operand" "=d")
 246           (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
 247                      (match_operand:V2HI 2 "register_operand" "d")))
 248      (set (reg:CCDSP CCDSP_OU_REGNUM)
 249           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
 250      (clobber (match_scratch:DI 3 "=x"))])]
 251   "ISA_HAS_DSPR2"
 252   "mul.ph\t%0,%1,%2"
 253   [(set_attr "type"     "imul3")
 254    (set_attr "mode"     "SI")])
 255
 256 (define_insn "mips_mul_s_ph"
 257   [(parallel
 258     [(set (match_operand:V2HI 0 "register_operand" "=d")
 259           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 260                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 261                        UNSPEC_MUL_S_PH))
 262      (set (reg:CCDSP CCDSP_OU_REGNUM)
 263           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
 264      (clobber (match_scratch:DI 3 "=x"))])]
 265   "ISA_HAS_DSPR2"
 266   "mul_s.ph\t%0,%z1,%z2"
 267   [(set_attr "type"     "imul3")
 268    (set_attr "mode"     "SI")])
 269
 270 (define_insn "mips_mulq_rs_w"
 271   [(parallel
 272     [(set (match_operand:SI 0 "register_operand" "=d")
 273           (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 274                       (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 275                      UNSPEC_MULQ_RS_W))
 276      (set (reg:CCDSP CCDSP_OU_REGNUM)
 277           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
 278      (clobber (match_scratch:DI 3 "=x"))])]
 279   "ISA_HAS_DSPR2"
 280   "mulq_rs.w\t%0,%z1,%z2"
 281   [(set_attr "type"     "imul3")
 282    (set_attr "mode"     "SI")])
 283
 284 (define_insn "mips_mulq_s_ph"
 285   [(parallel
 286     [(set (match_operand:V2HI 0 "register_operand" "=d")
 287           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 288                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 289                        UNSPEC_MULQ_S_PH))
 290      (set (reg:CCDSP CCDSP_OU_REGNUM)
 291           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
 292      (clobber (match_scratch:DI 3 "=x"))])]
 293   "ISA_HAS_DSPR2"
 294   "mulq_s.ph\t%0,%z1,%z2"
 295   [(set_attr "type"     "imul3")
 296    (set_attr "mode"     "SI")])
 297
 298 (define_insn "mips_mulq_s_w"
 299   [(parallel
 300     [(set (match_operand:SI 0 "register_operand" "=d")
 301           (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 302                       (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 303                      UNSPEC_MULQ_S_W))
 304      (set (reg:CCDSP CCDSP_OU_REGNUM)
 305           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
 306      (clobber (match_scratch:DI 3 "=x"))])]
 307   "ISA_HAS_DSPR2"
 308   "mulq_s.w\t%0,%z1,%z2"
 309   [(set_attr "type"     "imul3")
 310    (set_attr "mode"     "SI")])
 311
 312 (define_insn "mips_mulsa_w_ph"
 313   [(set (match_operand:DI 0 "register_operand" "=a")
 314         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 315                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 316                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 317                    UNSPEC_MULSA_W_PH))]
 318   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 319   "mulsa.w.ph\t%q0,%z2,%z3"
 320   [(set_attr "type"     "imadd")
 321    (set_attr "mode"     "SI")])
 322
 323 (define_insn "mips_mult"
 324   [(set (match_operand:DI 0 "register_operand" "=a")
 325         (mult:DI
 326          (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
 327          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
 328   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 329   "mult\t%q0,%1,%2"
 330   [(set_attr "type"     "imul")
 331    (set_attr "mode"     "SI")])
 332
 333 (define_insn "mips_multu"
 334   [(set (match_operand:DI 0 "register_operand" "=a")
 335         (mult:DI
 336          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
 337          (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
 338   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 339   "multu\t%q0,%1,%2"
 340   [(set_attr "type"     "imul")
 341    (set_attr "mode"     "SI")])
 342
 343 (define_insn "mips_precr_qb_ph"
 344   [(set (match_operand:V4QI 0 "register_operand" "=d")
 345         (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 346                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 347                      UNSPEC_PRECR_QB_PH))]
 348   "ISA_HAS_DSPR2"
 349   "precr.qb.ph\t%0,%z1,%z2"
 350   [(set_attr "type"     "arith")
 351    (set_attr "mode"     "SI")])
 352
 353 (define_insn "mips_precr_sra_ph_w"
 354   [(set (match_operand:V2HI 0 "register_operand" "=d")
 355         (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
 356                       (match_operand:SI 2 "reg_or_0_operand" "dJ")
 357                       (match_operand:SI 3 "const_int_operand" "n")]
 358                      UNSPEC_PRECR_SRA_PH_W))]
 359   "ISA_HAS_DSPR2"
 360 {
 361   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
 362     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
 363   return "precr_sra.ph.w\t%0,%z2,%3";
 364 }
 365   [(set_attr "type"     "arith")
 366    (set_attr "mode"     "SI")])
 367
 368 (define_insn "mips_precr_sra_r_ph_w"
 369   [(set (match_operand:V2HI 0 "register_operand" "=d")
 370         (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
 371                       (match_operand:SI 2 "reg_or_0_operand" "dJ")
 372                       (match_operand:SI 3 "const_int_operand" "n")]
 373                      UNSPEC_PRECR_SRA_R_PH_W))]
 374   "ISA_HAS_DSPR2"
 375 {
 376   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
 377     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
 378   return "precr_sra_r.ph.w\t%0,%z2,%3";
 379 }
 380   [(set_attr "type"     "arith")
 381    (set_attr "mode"     "SI")])
 382
 383 (define_insn "mips_prepend"
 384   [(set (match_operand:SI 0 "register_operand" "=d")
 385         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
 386                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
 387                     (match_operand:SI 3 "const_int_operand" "n")]
 388                    UNSPEC_PREPEND))]
 389   "ISA_HAS_DSPR2"
 390 {
 391   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
 392     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
 393   return "prepend\t%0,%z2,%3";
 394 }
 395   [(set_attr "type"     "arith")
 396    (set_attr "mode"     "SI")])
 397
 398 (define_insn "mips_shra_qb"
 399   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 400         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
 401                       (match_operand:SI 2 "arith_operand" "I,d")]
 402                      UNSPEC_SHRA_QB))]
 403   "ISA_HAS_DSPR2"
 404 {
 405   if (which_alternative == 0)
 406     {
 407       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
 408         operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
 409       return "shra.qb\t%0,%z1,%2";
 410     }
 411   return "shrav.qb\t%0,%z1,%2";
 412 }
 413   [(set_attr "type"     "shift")
 414    (set_attr "mode"     "SI")])
 415
 416
 417 (define_insn "mips_shra_r_qb"
 418   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 419         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
 420                       (match_operand:SI 2 "arith_operand" "I,d")]
 421                      UNSPEC_SHRA_R_QB))]
 422   "ISA_HAS_DSPR2"
 423 {
 424   if (which_alternative == 0)
 425     {
 426       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
 427         operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
 428       return "shra_r.qb\t%0,%z1,%2";
 429     }
 430   return "shrav_r.qb\t%0,%z1,%2";
 431 }
 432   [(set_attr "type"     "shift")
 433    (set_attr "mode"     "SI")])
 434
 435 (define_insn "mips_shrl_ph"
 436   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
 437         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
 438                       (match_operand:SI 2 "arith_operand" "I,d")]
 439                      UNSPEC_SHRL_PH))]
 440   "ISA_HAS_DSPR2"
 441 {
 442   if (which_alternative == 0)
 443     {
 444       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 15)
 445         operands[2] = GEN_INT (INTVAL (operands[2]) & 15);
 446       return "shrl.ph\t%0,%z1,%2";
 447     }
 448   return "shrlv.ph\t%0,%z1,%2";
 449 }
 450   [(set_attr "type"     "shift")
 451    (set_attr "mode"     "SI")])
 452
 453 (define_insn "mips_subu_ph"
 454   [(parallel
 455     [(set (match_operand:V2HI 0 "register_operand" "=d")
 456           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 457                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 458                        UNSPEC_SUBU_PH))
 459      (set (reg:CCDSP CCDSP_OU_REGNUM)
 460           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
 461   "ISA_HAS_DSPR2"
 462   "subu.ph\t%0,%z1,%z2"
 463   [(set_attr "type"     "arith")
 464    (set_attr "mode"     "SI")])
 465
 466 (define_insn "mips_subu_s_ph"
 467   [(parallel
 468     [(set (match_operand:V2HI 0 "register_operand" "=d")
 469           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 470                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 471                        UNSPEC_SUBU_S_PH))
 472      (set (reg:CCDSP CCDSP_OU_REGNUM)
 473           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
 474   "ISA_HAS_DSPR2"
 475   "subu_s.ph\t%0,%z1,%z2"
 476   [(set_attr "type"     "arith")
 477    (set_attr "mode"     "SI")])
 478
 479 (define_insn "mips_subuh_qb"
 480   [(set (match_operand:V4QI 0 "register_operand" "=d")
 481         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 482                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 483                      UNSPEC_SUBUH_QB))]
 484   "ISA_HAS_DSPR2"
 485   "subuh.qb\t%0,%z1,%z2"
 486   [(set_attr "type"     "arith")
 487    (set_attr "mode"     "SI")])
 488
 489 (define_insn "mips_subuh_r_qb"
 490   [(set (match_operand:V4QI 0 "register_operand" "=d")
 491         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 492                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 493                      UNSPEC_SUBUH_R_QB))]
 494   "ISA_HAS_DSPR2"
 495   "subuh_r.qb\t%0,%z1,%z2"
 496   [(set_attr "type"     "arith")
 497    (set_attr "mode"     "SI")])
 498
 499 (define_insn "mips_addqh_ph"
 500   [(set (match_operand:V2HI 0 "register_operand" "=d")
 501         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 502                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 503                      UNSPEC_ADDQH_PH))]
 504   "ISA_HAS_DSPR2"
 505   "addqh.ph\t%0,%z1,%z2"
 506   [(set_attr "type"     "arith")
 507    (set_attr "mode"     "SI")])
 508
 509 (define_insn "mips_addqh_r_ph"
 510   [(set (match_operand:V2HI 0 "register_operand" "=d")
 511         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 512                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 513                      UNSPEC_ADDQH_R_PH))]
 514   "ISA_HAS_DSPR2"
 515   "addqh_r.ph\t%0,%z1,%z2"
 516   [(set_attr "type"     "arith")
 517    (set_attr "mode"     "SI")])
 518
 519 (define_insn "mips_addqh_w"
 520   [(set (match_operand:SI 0 "register_operand" "=d")
 521         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 522                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 523                    UNSPEC_ADDQH_W))]
 524   "ISA_HAS_DSPR2"
 525   "addqh.w\t%0,%z1,%z2"
 526   [(set_attr "type"     "arith")
 527    (set_attr "mode"     "SI")])
 528
 529 (define_insn "mips_addqh_r_w"
 530   [(set (match_operand:SI 0 "register_operand" "=d")
 531         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 532                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 533                    UNSPEC_ADDQH_R_W))]
 534   "ISA_HAS_DSPR2"
 535   "addqh_r.w\t%0,%z1,%z2"
 536   [(set_attr "type"     "arith")
 537    (set_attr "mode"     "SI")])
 538
 539 (define_insn "mips_subqh_ph"
 540   [(set (match_operand:V2HI 0 "register_operand" "=d")
 541         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 542                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 543                      UNSPEC_SUBQH_PH))]
 544   "ISA_HAS_DSPR2"
 545   "subqh.ph\t%0,%z1,%z2"
 546   [(set_attr "type"     "arith")
 547    (set_attr "mode"     "SI")])
 548
 549 (define_insn "mips_subqh_r_ph"
 550   [(set (match_operand:V2HI 0 "register_operand" "=d")
 551         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 552                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 553                      UNSPEC_SUBQH_R_PH))]
 554   "ISA_HAS_DSPR2"
 555   "subqh_r.ph\t%0,%z1,%z2"
 556   [(set_attr "type"     "arith")
 557    (set_attr "mode"     "SI")])
 558
 559 (define_insn "mips_subqh_w"
 560   [(set (match_operand:SI 0 "register_operand" "=d")
 561         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 562                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 563                    UNSPEC_SUBQH_W))]
 564   "ISA_HAS_DSPR2"
 565   "subqh.w\t%0,%z1,%z2"
 566   [(set_attr "type"     "arith")
 567    (set_attr "mode"     "SI")])
 568
 569 (define_insn "mips_subqh_r_w"
 570   [(set (match_operand:SI 0 "register_operand" "=d")
 571         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 572                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 573                    UNSPEC_SUBQH_R_W))]
 574   "ISA_HAS_DSPR2"
 575   "subqh_r.w\t%0,%z1,%z2"
 576   [(set_attr "type"     "arith")
 577    (set_attr "mode"     "SI")])
 578
 579 (define_insn "mips_dpax_w_ph"
 580   [(set (match_operand:DI 0 "register_operand" "=a")
 581         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 582                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 583                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 584                    UNSPEC_DPAX_W_PH))]
 585   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 586   "dpax.w.ph\t%q0,%z2,%z3"
 587   [(set_attr "type"     "imadd")
 588    (set_attr "mode"     "SI")])
 589
 590 (define_insn "mips_dpsx_w_ph"
 591   [(set (match_operand:DI 0 "register_operand" "=a")
 592         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 593                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 594                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 595                    UNSPEC_DPSX_W_PH))]
 596   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 597   "dpsx.w.ph\t%q0,%z2,%z3"
 598   [(set_attr "type"     "imadd")
 599    (set_attr "mode"     "SI")])
 600
 601 (define_insn "mips_dpaqx_s_w_ph"
 602   [(parallel
 603     [(set (match_operand:DI 0 "register_operand" "=a")
 604           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 605                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 606                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 607                      UNSPEC_DPAQX_S_W_PH))
 608      (set (reg:CCDSP CCDSP_OU_REGNUM)
 609           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 610                         UNSPEC_DPAQX_S_W_PH))])]
 611   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 612   "dpaqx_s.w.ph\t%q0,%z2,%z3"
 613   [(set_attr "type"     "imadd")
 614    (set_attr "mode"     "SI")])
 615
 616 (define_insn "mips_dpaqx_sa_w_ph"
 617   [(parallel
 618     [(set (match_operand:DI 0 "register_operand" "=a")
 619           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 620                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 621                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 622                      UNSPEC_DPAQX_SA_W_PH))
 623      (set (reg:CCDSP CCDSP_OU_REGNUM)
 624           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 625                         UNSPEC_DPAQX_SA_W_PH))])]
 626   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 627   "dpaqx_sa.w.ph\t%q0,%z2,%z3"
 628   [(set_attr "type"     "imadd")
 629    (set_attr "mode"     "SI")])
 630
 631 (define_insn "mips_dpsqx_s_w_ph"
 632   [(parallel
 633     [(set (match_operand:DI 0 "register_operand" "=a")
 634           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 635                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 636                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 637                      UNSPEC_DPSQX_S_W_PH))
 638      (set (reg:CCDSP CCDSP_OU_REGNUM)
 639           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 640                         UNSPEC_DPSQX_S_W_PH))])]
 641   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 642   "dpsqx_s.w.ph\t%q0,%z2,%z3"
 643   [(set_attr "type"     "imadd")
 644    (set_attr "mode"     "SI")])
 645
 646 (define_insn "mips_dpsqx_sa_w_ph"
 647   [(parallel
 648     [(set (match_operand:DI 0 "register_operand" "=a")
 649           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 650                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 651                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 652                      UNSPEC_DPSQX_SA_W_PH))
 653      (set (reg:CCDSP CCDSP_OU_REGNUM)
 654           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 655                         UNSPEC_DPSQX_SA_W_PH))])]
 656   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 657   "dpsqx_sa.w.ph\t%q0,%z2,%z3"
 658   [(set_attr "type"     "imadd")
 659    (set_attr "mode"     "SI")])