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* builtins.c, config/arm/arm.c, config/i386/cygwin.h,
[official-gcc.git] / gcc / config / sh / sh.h
blobc61c357ec36c3f39e7aa0df44f60431af13a905a
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
29
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
34
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
43 builtin_define ("__sh1__"); \
44 break; \
45 case PROCESSOR_SH2: \
46 builtin_define ("__sh2__"); \
47 break; \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
50 break; \
51 case PROCESSOR_SH2A: \
52 builtin_define ("__SH2A__"); \
53 builtin_define (TARGET_SH2A_DOUBLE \
54 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
55 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
56 : "__SH2A_NOFPU__"); \
57 break; \
58 case PROCESSOR_SH3: \
59 builtin_define ("__sh3__"); \
60 builtin_define ("__SH3__"); \
61 if (TARGET_HARD_SH4) \
62 builtin_define ("__SH4_NOFPU__"); \
63 break; \
64 case PROCESSOR_SH3E: \
65 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
66 break; \
67 case PROCESSOR_SH4: \
68 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
69 break; \
70 case PROCESSOR_SH4A: \
71 builtin_define ("__SH4A__"); \
72 builtin_define (TARGET_SH4 \
73 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
74 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
75 : "__SH4_NOFPU__"); \
76 break; \
77 case PROCESSOR_SH5: \
78 { \
79 builtin_define_with_value ("__SH5__", \
80 TARGET_SHMEDIA64 ? "64" : "32", 0); \
81 builtin_define_with_value ("__SHMEDIA__", \
82 TARGET_SHMEDIA ? "1" : "0", 0); \
83 if (! TARGET_FPU_DOUBLE) \
84 builtin_define ("__SH4_NOFPU__"); \
85 } \
86 } \
87 if (TARGET_FPU_ANY) \
88 builtin_define ("__SH_FPU_ANY__"); \
89 if (TARGET_FPU_DOUBLE) \
90 builtin_define ("__SH_FPU_DOUBLE__"); \
91 if (TARGET_HITACHI) \
92 builtin_define ("__HITACHI__"); \
93 builtin_define (TARGET_LITTLE_ENDIAN \
94 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
95 } while (0)
96
97 /* We can not debug without a frame pointer. */
98 /* #define CAN_DEBUG_WITHOUT_FP */
99
100 #define CONDITIONAL_REGISTER_USAGE do \
101 { \
102 int regno; \
103 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
104 if (! VALID_REGISTER_P (regno)) \
105 fixed_regs[regno] = call_used_regs[regno] = 1; \
106 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
107 if (TARGET_SH5) \
108 { \
109 call_used_regs[FIRST_GENERAL_REG + 8] \
110 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
111 call_really_used_regs[FIRST_GENERAL_REG + 8] \
112 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
113 } \
114 if (TARGET_SHMEDIA) \
115 { \
116 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
117 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
118 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
119 } \
120 if (flag_pic) \
121 { \
122 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
123 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 } \
125 /* Renesas saves and restores mac registers on call. */ \
126 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
127 { \
128 call_really_used_regs[MACH_REG] = 0; \
129 call_really_used_regs[MACL_REG] = 0; \
130 } \
131 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
132 regno <= LAST_FP_REG; regno += 2) \
133 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
134 if (TARGET_SHMEDIA) \
135 { \
136 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
137 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
138 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
139 } \
140 else \
141 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
142 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
143 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
144 } while (0)
145 \f
146 /* Nonzero if this is an ELF target - compile time only */
147 #define TARGET_ELF 0
148
149 /* Nonzero if we should generate code using type 2E insns. */
150 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
151
152 /* Nonzero if we should generate code using type 2A insns. */
153 #define TARGET_SH2A TARGET_HARD_SH2A
154 /* Nonzero if we should generate code using type 2A SF insns. */
155 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
156 /* Nonzero if we should generate code using type 2A DF insns. */
157 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
158
159 /* Nonzero if we should generate code using type 3E insns. */
160 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
161
162 /* Nonzero if the cache line size is 32. */
163 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
164
165 /* Nonzero if we schedule for a superscalar implementation. */
166 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
167
168 /* Nonzero if the target has separate instruction and data caches. */
169 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
170
171 /* Nonzero if a double-precision FPU is available. */
172 #define TARGET_FPU_DOUBLE \
173 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
174
175 /* Nonzero if an FPU is available. */
176 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
177
178 /* Nonzero if we should generate code using type 4 insns. */
179 #undef TARGET_SH4
180 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
181
182 /* Nonzero if we're generating code for the common subset of
183 instructions present on both SH4a and SH4al-dsp. */
184 #define TARGET_SH4A_ARCH TARGET_SH4A
185
186 /* Nonzero if we're generating code for SH4a, unless the use of the
187 FPU is disabled (which makes it compatible with SH4al-dsp). */
188 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
189
190 /* Nonzero if we should generate code using the SHcompact instruction
191 set and 32-bit ABI. */
192 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
193
194 /* Nonzero if we should generate code using the SHmedia instruction
195 set and ABI. */
196 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
197
198 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
199 ABI. */
200 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
201
202 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
203 ABI. */
204 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
205
206 /* Nonzero if we should generate code using SHmedia FPU instructions. */
207 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
208
209 /* This is not used by the SH2E calling convention */
210 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
211 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
212 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
213
214 #ifndef TARGET_CPU_DEFAULT
215 #define TARGET_CPU_DEFAULT SELECT_SH1
216 #define SUPPORT_SH1 1
217 #define SUPPORT_SH2E 1
218 #define SUPPORT_SH4 1
219 #define SUPPORT_SH4_SINGLE 1
220 #define SUPPORT_SH2A 1
221 #define SUPPORT_SH2A_SINGLE 1
222 #endif
223
224 #define TARGET_DIVIDE_INV \
225 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
226 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
227 || sh_div_strategy == SH_DIV_INV_CALL \
228 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
229 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
230 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
231 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
232 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
233 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
234 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
235 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
236 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
237 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
238 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
239 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
240
241 #define SELECT_SH1 (MASK_SH1)
242 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
243 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
244 | MASK_FPU_SINGLE)
245 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
246 | MASK_HARD_SH2A_DOUBLE \
247 | MASK_SH2 | MASK_SH1)
248 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
249 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
250 | MASK_SH1 | MASK_FPU_SINGLE)
251 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
252 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
253 | MASK_SH2 | MASK_SH1)
254 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
255 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
256 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
257 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
258 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
259 | SELECT_SH3)
260 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
261 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
262 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
263 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
264 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
265 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
266 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
267 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
268 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
269 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
270 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
271
272 #if SUPPORT_SH1
273 #define SUPPORT_SH2 1
274 #endif
275 #if SUPPORT_SH2
276 #define SUPPORT_SH3 1
277 #endif
278 #if SUPPORT_SH3
279 #define SUPPORT_SH4_NOFPU 1
280 #endif
281 #if SUPPORT_SH4_NOFPU
282 #define SUPPORT_SH4A_NOFPU 1
283 #define SUPPORT_SH4AL 1
284 #define SUPPORT_SH2A_NOFPU 1
285 #endif
286
287 #if SUPPORT_SH2E
288 #define SUPPORT_SH3E 1
289 #endif
290 #if SUPPORT_SH3E
291 #define SUPPORT_SH4_SINGLE_ONLY 1
292 #define SUPPORT_SH4A_SINGLE_ONLY 1
293 #define SUPPORT_SH2A_SINGLE_ONLY 1
294 #endif
295
296 #if SUPPORT_SH4
297 #define SUPPORT_SH4A 1
298 #endif
299
300 #if SUPPORT_SH4_SINGLE
301 #define SUPPORT_SH4A_SINGLE 1
302 #endif
303
304 #if SUPPORT_SH5_COMPAT
305 #define SUPPORT_SH5_32MEDIA 1
306 #endif
307
308 #if SUPPORT_SH5_COMPACT_NOFPU
309 #define SUPPORT_SH5_32MEDIA_NOFPU 1
310 #endif
311
312 #define SUPPORT_ANY_SH5_32MEDIA \
313 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
314 #define SUPPORT_ANY_SH5_64MEDIA \
315 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
316 #define SUPPORT_ANY_SH5 \
317 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
318
319 /* Reset all target-selection flags. */
320 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
321 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
322 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
323
324 /* This defaults us to big-endian. */
325 #ifndef TARGET_ENDIAN_DEFAULT
326 #define TARGET_ENDIAN_DEFAULT 0
327 #endif
328
329 #ifndef TARGET_OPT_DEFAULT
330 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
331 #endif
332
333 #define TARGET_DEFAULT \
334 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
335
336 #ifndef SH_MULTILIB_CPU_DEFAULT
337 #define SH_MULTILIB_CPU_DEFAULT "m1"
338 #endif
339
340 #if TARGET_ENDIAN_DEFAULT
341 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
342 #else
343 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
344 #endif
345
346 #define CPP_SPEC " %(subtarget_cpp_spec) "
347
348 #ifndef SUBTARGET_CPP_SPEC
349 #define SUBTARGET_CPP_SPEC ""
350 #endif
351
352 #ifndef SUBTARGET_EXTRA_SPECS
353 #define SUBTARGET_EXTRA_SPECS
354 #endif
355
356 #define EXTRA_SPECS \
357 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
358 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
359 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
360 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
361 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
362 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
363 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
364 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
365 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
366 SUBTARGET_EXTRA_SPECS
367
368 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
369 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
370 #else
371 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
372 #endif
373
374 #define SH_ASM_SPEC \
375 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
376 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
377 %{m2a:--isa=sh2a} \
378 %{m2a-single:--isa=sh2a} \
379 %{m2a-single-only:--isa=sh2a} \
380 %{m2a-nofpu:--isa=sh2a-nofpu} \
381 %{m5-compact*:--isa=SHcompact} \
382 %{m5-32media*:--isa=SHmedia --abi=32} \
383 %{m5-64media*:--isa=SHmedia --abi=64} \
384 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
385
386 #define ASM_SPEC SH_ASM_SPEC
387
388 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
389 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
390 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
391 #else
392 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
393 #endif
394 #endif
395
396 #if STRICT_NOFPU == 1
397 /* Strict nofpu means that the compiler should tell the assembler
398 to reject FPU instructions. E.g. from ASM inserts. */
399 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
400 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
401 #else
402 /* If there were an -isa option for sh5-nofpu then it would also go here. */
403 #define SUBTARGET_ASM_ISA_SPEC \
404 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
405 #endif
406 #else /* ! STRICT_NOFPU */
407 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
408 #endif
409
410 #ifndef SUBTARGET_ASM_SPEC
411 #define SUBTARGET_ASM_SPEC ""
412 #endif
413
414 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
415 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
416 #else
417 #define LINK_EMUL_PREFIX "sh%{ml:l}"
418 #endif
419
420 #if TARGET_CPU_DEFAULT & MASK_SH5
421 #if TARGET_CPU_DEFAULT & MASK_SH_E
422 #define LINK_DEFAULT_CPU_EMUL "32"
423 #if TARGET_CPU_DEFAULT & MASK_SH1
424 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
425 #else
426 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
427 #endif /* MASK_SH1 */
428 #else /* !MASK_SH_E */
429 #define LINK_DEFAULT_CPU_EMUL "64"
430 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
431 #endif /* MASK_SH_E */
432 #define ASM_ISA_DEFAULT_SPEC \
433 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
434 #else /* !MASK_SH5 */
435 #define LINK_DEFAULT_CPU_EMUL ""
436 #define ASM_ISA_DEFAULT_SPEC ""
437 #endif /* MASK_SH5 */
438
439 #define SUBTARGET_LINK_EMUL_SUFFIX ""
440 #define SUBTARGET_LINK_SPEC ""
441
442 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
443 so that we can undo the damage without code replication. */
444 #define LINK_SPEC SH_LINK_SPEC
445
446 #define SH_LINK_SPEC "\
447 -m %(link_emul_prefix)\
448 %{m5-compact*|m5-32media*:32}\
449 %{m5-64media*:64}\
450 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
451 %(subtarget_link_emul_suffix) \
452 %{mrelax:-relax} %(subtarget_link_spec)"
453
454 #ifndef SH_DIV_STR_FOR_SIZE
455 #define SH_DIV_STR_FOR_SIZE "call"
456 #endif
457
458 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
459 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
460 do { \
461 if (LEVEL) \
462 { \
463 flag_omit_frame_pointer = -1; \
464 if (! SIZE) \
465 sh_div_str = "inv:minlat"; \
466 } \
467 if (SIZE) \
468 { \
469 target_flags |= MASK_SMALLCODE; \
470 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
471 } \
472 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
473 haven't been parsed yet, hence we'd read only the default. \
474 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
475 it's OK to always set flag_branch_target_load_optimize. */ \
476 if (LEVEL > 1) \
477 { \
478 flag_branch_target_load_optimize = 1; \
479 if (! (SIZE)) \
480 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
481 } \
482 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
483 here, so leave it to OVERRIDE_OPTIONS to set \
484 flag_finite_math_only. We set it to 2 here so we know if the user \
485 explicitly requested this to be on or off. */ \
486 flag_finite_math_only = 2; \
487 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
488 the user explicitly requested this to be on or off. */ \
489 if (flag_schedule_insns > 0) \
490 flag_schedule_insns = 2; \
491 } while (0)
492
493 #define ASSEMBLER_DIALECT assembler_dialect
494
495 extern int assembler_dialect;
496
497 enum sh_divide_strategy_e {
498 /* SH5 strategies. */
499 SH_DIV_CALL,
500 SH_DIV_CALL2,
501 SH_DIV_FP, /* We could do this also for SH4. */
502 SH_DIV_INV,
503 SH_DIV_INV_MINLAT,
504 SH_DIV_INV20U,
505 SH_DIV_INV20L,
506 SH_DIV_INV_CALL,
507 SH_DIV_INV_CALL2,
508 SH_DIV_INV_FP,
509 /* SH1 .. SH4 strategies. Because of the small number of registers
510 available, the compiler uses knowledge of the actual set of registers
511 being clobbered by the different functions called. */
512 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
513 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
514 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
515 SH_DIV_INTRINSIC
516 };
517
518 extern enum sh_divide_strategy_e sh_div_strategy;
519
520 #ifndef SH_DIV_STRATEGY_DEFAULT
521 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
522 #endif
523
524 #define OVERRIDE_OPTIONS \
525 do { \
526 int regno; \
527 \
528 if (flag_finite_math_only == 2) \
529 flag_finite_math_only \
530 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
531 if (TARGET_SH2E && !flag_finite_math_only) \
532 target_flags |= MASK_IEEE; \
533 sh_cpu = CPU_SH1; \
534 assembler_dialect = 0; \
535 if (TARGET_SH2) \
536 sh_cpu = CPU_SH2; \
537 if (TARGET_SH2E) \
538 sh_cpu = CPU_SH2E; \
539 if (TARGET_SH2A) \
540 { \
541 sh_cpu = CPU_SH2A; \
542 if (TARGET_SH2A_DOUBLE) \
543 target_flags |= MASK_FMOVD; \
544 } \
545 if (TARGET_SH3) \
546 sh_cpu = CPU_SH3; \
547 if (TARGET_SH3E) \
548 sh_cpu = CPU_SH3E; \
549 if (TARGET_SH4) \
550 { \
551 assembler_dialect = 1; \
552 sh_cpu = CPU_SH4; \
553 } \
554 if (TARGET_SH4A_ARCH) \
555 { \
556 assembler_dialect = 1; \
557 sh_cpu = CPU_SH4A; \
558 } \
559 if (TARGET_SH5) \
560 { \
561 sh_cpu = CPU_SH5; \
562 target_flags |= MASK_ALIGN_DOUBLE; \
563 if (TARGET_SHMEDIA_FPU) \
564 target_flags |= MASK_FMOVD; \
565 if (TARGET_SHMEDIA) \
566 { \
567 /* There are no delay slots on SHmedia. */ \
568 flag_delayed_branch = 0; \
569 /* Relaxation isn't yet supported for SHmedia */ \
570 target_flags &= ~MASK_RELAX; \
571 /* After reload, if conversion does little good but can cause \
572 ICEs: \
573 - find_if_block doesn't do anything for SH because we don't\
574 have conditional execution patterns. (We use conditional\
575 move patterns, which are handled differently, and only \
576 before reload). \
577 - find_cond_trap doesn't do anything for the SH because we \
578 don't have conditional traps. \
579 - find_if_case_1 uses redirect_edge_and_branch_force in \
580 the only path that does an optimization, and this causes \
581 an ICE when branch targets are in registers. \
582 - find_if_case_2 doesn't do anything for the SHmedia after \
583 reload except when it can redirect a tablejump - and \
584 that's rather rare. */ \
585 flag_if_conversion2 = 0; \
586 if (! strcmp (sh_div_str, "call")) \
587 sh_div_strategy = SH_DIV_CALL; \
588 else if (! strcmp (sh_div_str, "call2")) \
589 sh_div_strategy = SH_DIV_CALL2; \
590 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
591 sh_div_strategy = SH_DIV_FP; \
592 else if (! strcmp (sh_div_str, "inv")) \
593 sh_div_strategy = SH_DIV_INV; \
594 else if (! strcmp (sh_div_str, "inv:minlat")) \
595 sh_div_strategy = SH_DIV_INV_MINLAT; \
596 else if (! strcmp (sh_div_str, "inv20u")) \
597 sh_div_strategy = SH_DIV_INV20U; \
598 else if (! strcmp (sh_div_str, "inv20l")) \
599 sh_div_strategy = SH_DIV_INV20L; \
600 else if (! strcmp (sh_div_str, "inv:call2")) \
601 sh_div_strategy = SH_DIV_INV_CALL2; \
602 else if (! strcmp (sh_div_str, "inv:call")) \
603 sh_div_strategy = SH_DIV_INV_CALL; \
604 else if (! strcmp (sh_div_str, "inv:fp")) \
605 { \
606 if (TARGET_FPU_ANY) \
607 sh_div_strategy = SH_DIV_INV_FP; \
608 else \
609 sh_div_strategy = SH_DIV_INV; \
610 } \
611 } \
612 /* -fprofile-arcs needs a working libgcov . In unified tree \
613 configurations with newlib, this requires to configure with \
614 --with-newlib --with-headers. But there is no way to check \
615 here we have a working libgcov, so just assume that we have. */\
616 if (profile_flag) \
617 warning (0, "profiling is still experimental for this target");\
618 } \
619 else \
620 { \
621 /* Only the sh64-elf assembler fully supports .quad properly. */\
622 targetm.asm_out.aligned_op.di = NULL; \
623 targetm.asm_out.unaligned_op.di = NULL; \
624 } \
625 if (TARGET_SH1) \
626 { \
627 if (! strcmp (sh_div_str, "call-div1")) \
628 sh_div_strategy = SH_DIV_CALL_DIV1; \
629 else if (! strcmp (sh_div_str, "call-fp") \
630 && (TARGET_FPU_DOUBLE \
631 || (TARGET_HARD_SH4 && TARGET_SH2E) \
632 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
633 sh_div_strategy = SH_DIV_CALL_FP; \
634 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH3) \
635 sh_div_strategy = SH_DIV_CALL_TABLE; \
636 else \
637 /* Pick one that makes most sense for the target in general. \
638 It is not much good to use different functions depending \
639 on -Os, since then we'll end up with two different functions \
640 when some of the code is compiled for size, and some for \
641 speed. */ \
642 \
643 /* SH4 tends to emphasize speed. */ \
644 if (TARGET_HARD_SH4) \
645 sh_div_strategy = SH_DIV_CALL_TABLE; \
646 /* These have their own way of doing things. */ \
647 else if (TARGET_SH2A) \
648 sh_div_strategy = SH_DIV_INTRINSIC; \
649 /* ??? Should we use the integer SHmedia function instead? */ \
650 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
651 sh_div_strategy = SH_DIV_CALL_FP; \
652 /* SH1 .. SH3 cores often go into small-footprint systems, so \
653 default to the smallest implementation available. */ \
654 else \
655 sh_div_strategy = SH_DIV_CALL_DIV1; \
656 } \
657 if (!TARGET_SH1) \
658 TARGET_PRETEND_CMOVE = 0; \
659 if (sh_divsi3_libfunc[0]) \
660 ; /* User supplied - leave it alone. */ \
661 else if (TARGET_DIVIDE_CALL_FP) \
662 sh_divsi3_libfunc = "__sdivsi3_i4"; \
663 else if (TARGET_DIVIDE_CALL_TABLE) \
664 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
665 else if (TARGET_SH5) \
666 sh_divsi3_libfunc = "__sdivsi3_1"; \
667 else \
668 sh_divsi3_libfunc = "__sdivsi3"; \
669 if (TARGET_FMOVD) \
670 reg_class_from_letter['e' - 'a'] = NO_REGS; \
671 \
672 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
673 if (! VALID_REGISTER_P (regno)) \
674 sh_register_names[regno][0] = '\0'; \
675 \
676 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
677 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
678 sh_additional_register_names[regno][0] = '\0'; \
679 \
680 if (flag_omit_frame_pointer < 0) \
681 { \
682 /* The debugging information is sufficient, \
683 but gdb doesn't implement this yet */ \
684 if (0) \
685 flag_omit_frame_pointer \
686 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
687 else \
688 flag_omit_frame_pointer = 0; \
689 } \
690 \
691 if ((flag_pic && ! TARGET_PREFERGOT) \
692 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
693 flag_no_function_cse = 1; \
694 \
695 if (SMALL_REGISTER_CLASSES) \
696 { \
697 /* Never run scheduling before reload, since that can \
698 break global alloc, and generates slower code anyway due \
699 to the pressure on R0. */ \
700 /* Enable sched1 for SH4; ready queue will be reordered by \
701 the target hooks when pressure is high. We can not do this for \
702 SH3 and lower as they give spill failures for R0. */ \
703 if (!TARGET_HARD_SH4) \
704 flag_schedule_insns = 0; \
705 /* ??? Current exception handling places basic block boundaries \
706 after call_insns. It causes the high pressure on R0 and gives \
707 spill failures for R0 in reload. See PR 22553 and the thread \
708 on gcc-patches \
709 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
710 else if (flag_exceptions) \
711 { \
712 if (flag_schedule_insns == 1) \
713 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
714 flag_schedule_insns = 0; \
715 } \
716 } \
717 \
718 if (align_loops == 0) \
719 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
720 if (align_jumps == 0) \
721 align_jumps = 1 << CACHE_LOG; \
722 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
723 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
724 \
725 /* Allocation boundary (in *bytes*) for the code of a function. \
726 SH1: 32 bit alignment is faster, because instructions are always \
727 fetched as a pair from a longword boundary. \
728 SH2 .. SH5 : align to cache line start. */ \
729 if (align_functions == 0) \
730 align_functions \
731 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
732 /* The linker relaxation code breaks when a function contains \
733 alignments that are larger than that at the start of a \
734 compilation unit. */ \
735 if (TARGET_RELAX) \
736 { \
737 int min_align \
738 = align_loops > align_jumps ? align_loops : align_jumps; \
739 \
740 /* Also take possible .long constants / mova tables int account. */\
741 if (min_align < 4) \
742 min_align = 4; \
743 if (align_functions < min_align) \
744 align_functions = min_align; \
745 } \
746 } while (0)
747 \f
748 /* Target machine storage layout. */
749
750 /* Define this if most significant bit is lowest numbered
751 in instructions that operate on numbered bit-fields. */
752
753 #define BITS_BIG_ENDIAN 0
754
755 /* Define this if most significant byte of a word is the lowest numbered. */
756 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
757
758 /* Define this if most significant word of a multiword number is the lowest
759 numbered. */
760 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
761
762 /* Define this to set the endianness to use in libgcc2.c, which can
763 not depend on target_flags. */
764 #if defined(__LITTLE_ENDIAN__)
765 #define LIBGCC2_WORDS_BIG_ENDIAN 0
766 #else
767 #define LIBGCC2_WORDS_BIG_ENDIAN 1
768 #endif
769
770 #define MAX_BITS_PER_WORD 64
771
772 /* Width in bits of an `int'. We want just 32-bits, even if words are
773 longer. */
774 #define INT_TYPE_SIZE 32
775
776 /* Width in bits of a `long'. */
777 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
778
779 /* Width in bits of a `long long'. */
780 #define LONG_LONG_TYPE_SIZE 64
781
782 /* Width in bits of a `long double'. */
783 #define LONG_DOUBLE_TYPE_SIZE 64
784
785 /* Width of a word, in units (bytes). */
786 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
787 #define MIN_UNITS_PER_WORD 4
788
789 /* Scaling factor for Dwarf data offsets for CFI information.
790 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
791 SHmedia; however, since we do partial register saves for the registers
792 visible to SHcompact, and for target registers for SHMEDIA32, we have
793 to allow saves that are only 4-byte aligned. */
794 #define DWARF_CIE_DATA_ALIGNMENT -4
795
796 /* Width in bits of a pointer.
797 See also the macro `Pmode' defined below. */
798 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
799
800 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
801 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
802
803 /* Boundary (in *bits*) on which stack pointer should be aligned. */
804 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
805
806 /* The log (base 2) of the cache line size, in bytes. Processors prior to
807 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
808 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
809 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
810
811 /* ABI given & required minimum allocation boundary (in *bits*) for the
812 code of a function. */
813 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
814
815 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
816 the vbit must go into the delta field of
817 pointers-to-member-functions. */
818 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
819 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
820
821 /* Alignment of field after `int : 0' in a structure. */
822 #define EMPTY_FIELD_BOUNDARY 32
823
824 /* No data type wants to be aligned rounder than this. */
825 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
826
827 /* The best alignment to use in cases where we have a choice. */
828 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
829
830 /* Make strings word-aligned so strcpy from constants will be faster. */
831 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
832 ((TREE_CODE (EXP) == STRING_CST \
833 && (ALIGN) < FASTEST_ALIGNMENT) \
834 ? FASTEST_ALIGNMENT : (ALIGN))
835
836 /* get_mode_alignment assumes complex values are always held in multiple
837 registers, but that is not the case on the SH; CQImode and CHImode are
838 held in a single integer register. SH5 also holds CSImode and SCmode
839 values in integer registers. This is relevant for argument passing on
840 SHcompact as we use a stack temp in order to pass CSImode by reference. */
841 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
842 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
843 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
844 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
845 : (unsigned) ALIGN)
846
847 /* Make arrays of chars word-aligned for the same reasons. */
848 #define DATA_ALIGNMENT(TYPE, ALIGN) \
849 (TREE_CODE (TYPE) == ARRAY_TYPE \
850 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
851 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
852
853 /* Number of bits which any structure or union's size must be a
854 multiple of. Each structure or union's size is rounded up to a
855 multiple of this. */
856 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
857
858 /* Set this nonzero if move instructions will actually fail to work
859 when given unaligned data. */
860 #define STRICT_ALIGNMENT 1
861
862 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
863 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
864 barrier_align (LABEL_AFTER_BARRIER)
865
866 #define LOOP_ALIGN(A_LABEL) \
867 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
868 ? 0 : sh_loop_align (A_LABEL))
869
870 #define LABEL_ALIGN(A_LABEL) \
871 ( \
872 (PREV_INSN (A_LABEL) \
873 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
874 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
875 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
876 /* explicit alignment insn in constant tables. */ \
877 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
878 : 0)
879
880 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
881 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
882
883 /* The base two logarithm of the known minimum alignment of an insn length. */
884 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
885 (GET_CODE (A_INSN) == INSN \
886 ? 1 << TARGET_SHMEDIA \
887 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
888 ? 1 << TARGET_SHMEDIA \
889 : CACHE_LOG)
890 \f
891 /* Standard register usage. */
892
893 /* Register allocation for the Renesas calling convention:
894
895 r0 arg return
896 r1..r3 scratch
897 r4..r7 args in
898 r8..r13 call saved
899 r14 frame pointer/call saved
900 r15 stack pointer
901 ap arg pointer (doesn't really exist, always eliminated)
902 pr subroutine return address
903 t t bit
904 mach multiply/accumulate result, high part
905 macl multiply/accumulate result, low part.
906 fpul fp/int communication register
907 rap return address pointer register
908 fr0 fp arg return
909 fr1..fr3 scratch floating point registers
910 fr4..fr11 fp args in
911 fr12..fr15 call saved floating point registers */
912
913 #define MAX_REGISTER_NAME_LENGTH 5
914 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
915
916 #define SH_REGISTER_NAMES_INITIALIZER \
917 { \
918 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
919 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
920 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
921 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
922 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
923 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
924 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
925 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
926 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
927 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
928 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
929 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
930 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
931 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
932 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
933 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
934 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
935 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
936 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
937 "rap", "sfp" \
938 }
939
940 #define REGNAMES_ARR_INDEX_1(index) \
941 (sh_register_names[index])
942 #define REGNAMES_ARR_INDEX_2(index) \
943 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
944 #define REGNAMES_ARR_INDEX_4(index) \
945 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
946 #define REGNAMES_ARR_INDEX_8(index) \
947 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
948 #define REGNAMES_ARR_INDEX_16(index) \
949 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
950 #define REGNAMES_ARR_INDEX_32(index) \
951 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
952 #define REGNAMES_ARR_INDEX_64(index) \
953 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
954
955 #define REGISTER_NAMES \
956 { \
957 REGNAMES_ARR_INDEX_64 (0), \
958 REGNAMES_ARR_INDEX_64 (64), \
959 REGNAMES_ARR_INDEX_8 (128), \
960 REGNAMES_ARR_INDEX_8 (136), \
961 REGNAMES_ARR_INDEX_8 (144), \
962 REGNAMES_ARR_INDEX_2 (152) \
963 }
964
965 #define ADDREGNAMES_SIZE 32
966 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
967 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
968 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
969
970 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
971 { \
972 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
973 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
974 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
975 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
976 }
977
978 #define ADDREGNAMES_REGNO(index) \
979 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
980 : (-1))
981
982 #define ADDREGNAMES_ARR_INDEX_1(index) \
983 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
984 #define ADDREGNAMES_ARR_INDEX_2(index) \
985 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
986 #define ADDREGNAMES_ARR_INDEX_4(index) \
987 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
988 #define ADDREGNAMES_ARR_INDEX_8(index) \
989 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
990 #define ADDREGNAMES_ARR_INDEX_16(index) \
991 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
992 #define ADDREGNAMES_ARR_INDEX_32(index) \
993 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
994
995 #define ADDITIONAL_REGISTER_NAMES \
996 { \
997 ADDREGNAMES_ARR_INDEX_32 (0) \
998 }
999
1000 /* Number of actual hardware registers.
1001 The hardware registers are assigned numbers for the compiler
1002 from 0 to just below FIRST_PSEUDO_REGISTER.
1003 All registers that the compiler knows about must be given numbers,
1004 even those that are not normally considered general registers. */
1005
1006 /* There are many other relevant definitions in sh.md's md_constants. */
1007
1008 #define FIRST_GENERAL_REG R0_REG
1009 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1010 #define FIRST_FP_REG DR0_REG
1011 #define LAST_FP_REG (FIRST_FP_REG + \
1012 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1013 #define FIRST_XD_REG XD0_REG
1014 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1015 #define FIRST_TARGET_REG TR0_REG
1016 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1017
1018 #define GENERAL_REGISTER_P(REGNO) \
1019 IN_RANGE ((REGNO), \
1020 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1021 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1022
1023 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1024 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
1025 || ((REGNO) == FRAME_POINTER_REGNUM))
1026
1027 #define FP_REGISTER_P(REGNO) \
1028 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1029
1030 #define XD_REGISTER_P(REGNO) \
1031 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1032
1033 #define FP_OR_XD_REGISTER_P(REGNO) \
1034 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1035
1036 #define FP_ANY_REGISTER_P(REGNO) \
1037 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1038
1039 #define SPECIAL_REGISTER_P(REGNO) \
1040 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1041 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1042
1043 #define TARGET_REGISTER_P(REGNO) \
1044 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1045
1046 #define SHMEDIA_REGISTER_P(REGNO) \
1047 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1048 || TARGET_REGISTER_P (REGNO))
1049
1050 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1051 that should be fixed. */
1052 #define VALID_REGISTER_P(REGNO) \
1053 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1054 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1055 || (REGNO) == FRAME_POINTER_REGNUM \
1056 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1057 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1058
1059 /* The mode that should be generally used to store a register by
1060 itself in the stack, or to load it back. */
1061 #define REGISTER_NATURAL_MODE(REGNO) \
1062 (FP_REGISTER_P (REGNO) ? SFmode \
1063 : XD_REGISTER_P (REGNO) ? DFmode \
1064 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1065 ? DImode \
1066 : SImode)
1067
1068 #define FIRST_PSEUDO_REGISTER 154
1069
1070 /* Don't count soft frame pointer. */
1071 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1072
1073 /* 1 for registers that have pervasive standard uses
1074 and are not available for the register allocator.
1075
1076 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1077 It is 32 bits wide for SH2. */
1078
1079 #define FIXED_REGISTERS \
1080 { \
1081 /* Regular registers. */ \
1082 0, 0, 0, 0, 0, 0, 0, 0, \
1083 0, 0, 0, 0, 0, 0, 0, 1, \
1084 /* r16 is reserved, r18 is the former pr. */ \
1085 1, 0, 0, 0, 0, 0, 0, 0, \
1086 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1087 /* r26 is a global variable data pointer; r27 is for constants. */ \
1088 1, 1, 1, 1, 0, 0, 0, 0, \
1089 0, 0, 0, 0, 0, 0, 0, 0, \
1090 0, 0, 0, 0, 0, 0, 0, 0, \
1091 0, 0, 0, 0, 0, 0, 0, 0, \
1092 0, 0, 0, 0, 0, 0, 0, 1, \
1093 /* FP registers. */ \
1094 0, 0, 0, 0, 0, 0, 0, 0, \
1095 0, 0, 0, 0, 0, 0, 0, 0, \
1096 0, 0, 0, 0, 0, 0, 0, 0, \
1097 0, 0, 0, 0, 0, 0, 0, 0, \
1098 0, 0, 0, 0, 0, 0, 0, 0, \
1099 0, 0, 0, 0, 0, 0, 0, 0, \
1100 0, 0, 0, 0, 0, 0, 0, 0, \
1101 0, 0, 0, 0, 0, 0, 0, 0, \
1102 /* Branch target registers. */ \
1103 0, 0, 0, 0, 0, 0, 0, 0, \
1104 /* XD registers. */ \
1105 0, 0, 0, 0, 0, 0, 0, 0, \
1106 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1107 1, 1, 1, 1, 1, 1, 0, 1, \
1108 /*"rap", "sfp" */ \
1109 1, 1, \
1110 }
1111
1112 /* 1 for registers not available across function calls.
1113 These must include the FIXED_REGISTERS and also any
1114 registers that can be used without being saved.
1115 The latter must include the registers where values are returned
1116 and the register where structure-value addresses are passed.
1117 Aside from that, you can include as many other registers as you like. */
1118
1119 #define CALL_USED_REGISTERS \
1120 { \
1121 /* Regular registers. */ \
1122 1, 1, 1, 1, 1, 1, 1, 1, \
1123 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1124 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1125 across SH5 function calls. */ \
1126 0, 0, 0, 0, 0, 0, 0, 1, \
1127 1, 1, 1, 1, 1, 1, 1, 1, \
1128 1, 1, 1, 1, 0, 0, 0, 0, \
1129 0, 0, 0, 0, 1, 1, 1, 1, \
1130 1, 1, 1, 1, 0, 0, 0, 0, \
1131 0, 0, 0, 0, 0, 0, 0, 0, \
1132 0, 0, 0, 0, 1, 1, 1, 1, \
1133 /* FP registers. */ \
1134 1, 1, 1, 1, 1, 1, 1, 1, \
1135 1, 1, 1, 1, 0, 0, 0, 0, \
1136 1, 1, 1, 1, 1, 1, 1, 1, \
1137 1, 1, 1, 1, 1, 1, 1, 1, \
1138 1, 1, 1, 1, 0, 0, 0, 0, \
1139 0, 0, 0, 0, 0, 0, 0, 0, \
1140 0, 0, 0, 0, 0, 0, 0, 0, \
1141 0, 0, 0, 0, 0, 0, 0, 0, \
1142 /* Branch target registers. */ \
1143 1, 1, 1, 1, 1, 0, 0, 0, \
1144 /* XD registers. */ \
1145 1, 1, 1, 1, 1, 1, 0, 0, \
1146 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1147 1, 1, 1, 1, 1, 1, 1, 1, \
1148 /*"rap", "sfp" */ \
1149 1, 1, \
1150 }
1151
1152 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1153 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1154 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1155
1156 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1157 across SHcompact function calls. We can't tell whether a called
1158 function is SHmedia or SHcompact, so we assume it may be when
1159 compiling SHmedia code with the 32-bit ABI, since that's the only
1160 ABI that can be linked with SHcompact code. */
1161 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1162 (TARGET_SHMEDIA32 \
1163 && GET_MODE_SIZE (MODE) > 4 \
1164 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1165 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1166 || TARGET_REGISTER_P (REGNO) \
1167 || (REGNO) == PR_MEDIA_REG))
1168
1169 /* Return number of consecutive hard regs needed starting at reg REGNO
1170 to hold something of mode MODE.
1171 This is ordinarily the length in words of a value of mode MODE
1172 but can be less for certain modes in special long registers.
1173
1174 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1175
1176 #define HARD_REGNO_NREGS(REGNO, MODE) \
1177 (XD_REGISTER_P (REGNO) \
1178 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1179 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1180 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1181 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1182
1183 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1184 We can allow any mode in any general register. The special registers
1185 only allow SImode. Don't allow any mode in the PR. */
1186
1187 /* We cannot hold DCmode values in the XD registers because alter_reg
1188 handles subregs of them incorrectly. We could work around this by
1189 spacing the XD registers like the DR registers, but this would require
1190 additional memory in every compilation to hold larger register vectors.
1191 We could hold SFmode / SCmode values in XD registers, but that
1192 would require a tertiary reload when reloading from / to memory,
1193 and a secondary reload to reload from / to general regs; that
1194 seems to be a loosing proposition. */
1195 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1196 it won't be ferried through GP registers first. */
1197 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1198 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1199 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1200 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1201 ? 1 \
1202 : (MODE) == V2SFmode \
1203 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1204 || GENERAL_REGISTER_P (REGNO)) \
1205 : (MODE) == V4SFmode \
1206 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1207 || GENERAL_REGISTER_P (REGNO)) \
1208 : (MODE) == V16SFmode \
1209 ? (TARGET_SHMEDIA \
1210 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1211 : (REGNO) == FIRST_XD_REG) \
1212 : FP_REGISTER_P (REGNO) \
1213 ? ((MODE) == SFmode || (MODE) == SImode \
1214 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1215 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1216 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1217 || (MODE) == V2SFmode || (MODE) == TImode))) \
1218 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1219 || ((TARGET_SH4 || TARGET_SHMEDIA) \
1220 && (MODE) == TImode \
1221 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1222 : XD_REGISTER_P (REGNO) \
1223 ? (MODE) == DFmode \
1224 : TARGET_REGISTER_P (REGNO) \
1225 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1226 : (REGNO) == PR_REG ? (MODE) == SImode \
1227 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1228 : 1)
1229
1230 /* Value is 1 if it is a good idea to tie two pseudo registers
1231 when one has mode MODE1 and one has mode MODE2.
1232 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1233 for any hard reg, then this must be 0 for correct output.
1234 That's the case for xd registers: we don't hold SFmode values in
1235 them, so we can't tie an SFmode pseudos with one in another
1236 floating-point mode. */
1237
1238 #define MODES_TIEABLE_P(MODE1, MODE2) \
1239 ((MODE1) == (MODE2) \
1240 || (TARGET_SHMEDIA \
1241 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1242 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1243 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1244 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1245 && (GET_MODE_SIZE (MODE2) <= 4)) \
1246 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1247
1248 /* A C expression that is nonzero if hard register NEW_REG can be
1249 considered for use as a rename register for OLD_REG register */
1250
1251 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1252 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1253
1254 /* Specify the registers used for certain standard purposes.
1255 The values of these macros are register numbers. */
1256
1257 /* Define this if the program counter is overloaded on a register. */
1258 /* #define PC_REGNUM 15*/
1259
1260 /* Register to use for pushing function arguments. */
1261 #define STACK_POINTER_REGNUM SP_REG
1262
1263 /* Base register for access to local variables of the function. */
1264 #define HARD_FRAME_POINTER_REGNUM FP_REG
1265
1266 /* Base register for access to local variables of the function. */
1267 #define FRAME_POINTER_REGNUM 153
1268
1269 /* Fake register that holds the address on the stack of the
1270 current function's return address. */
1271 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1272
1273 /* Register to hold the addressing base for position independent
1274 code access to data items. */
1275 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1276
1277 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1278
1279 /* Value should be nonzero if functions must have frame pointers.
1280 Zero means the frame pointer need not be set up (and parms may be accessed
1281 via the stack pointer) in functions that seem suitable. */
1282
1283 #define FRAME_POINTER_REQUIRED 0
1284
1285 /* Definitions for register eliminations.
1286
1287 We have three registers that can be eliminated on the SH. First, the
1288 frame pointer register can often be eliminated in favor of the stack
1289 pointer register. Secondly, the argument pointer register can always be
1290 eliminated; it is replaced with either the stack or frame pointer.
1291 Third, there is the return address pointer, which can also be replaced
1292 with either the stack or the frame pointer. */
1293
1294 /* This is an array of structures. Each structure initializes one pair
1295 of eliminable registers. The "from" register number is given first,
1296 followed by "to". Eliminations of the same "from" register are listed
1297 in order of preference. */
1298
1299 /* If you add any registers here that are not actually hard registers,
1300 and that have any alternative of elimination that doesn't always
1301 apply, you need to amend calc_live_regs to exclude it, because
1302 reload spills all eliminable registers where it sees an
1303 can_eliminate == 0 entry, thus making them 'live' .
1304 If you add any hard registers that can be eliminated in different
1305 ways, you have to patch reload to spill them only when all alternatives
1306 of elimination fail. */
1307
1308 #define ELIMINABLE_REGS \
1309 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1310 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1311 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1312 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1313 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1314 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1315 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1316
1317 /* Given FROM and TO register numbers, say whether this elimination
1318 is allowed. */
1319 #define CAN_ELIMINATE(FROM, TO) \
1320 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1321
1322 /* Define the offset between two registers, one to be eliminated, and the other
1323 its replacement, at the start of a routine. */
1324
1325 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1326 OFFSET = initial_elimination_offset ((FROM), (TO))
1327
1328 /* Base register for access to arguments of the function. */
1329 #define ARG_POINTER_REGNUM AP_REG
1330
1331 /* Register in which the static-chain is passed to a function. */
1332 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1333
1334 /* Don't default to pcc-struct-return, because we have already specified
1335 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1336 target hook. */
1337
1338 #define DEFAULT_PCC_STRUCT_RETURN 0
1339
1340 #define SHMEDIA_REGS_STACK_ADJUST() \
1341 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1342 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1343 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1344 : 0)
1345
1346 \f
1347 /* Define the classes of registers for register constraints in the
1348 machine description. Also define ranges of constants.
1349
1350 One of the classes must always be named ALL_REGS and include all hard regs.
1351 If there is more than one class, another class must be named NO_REGS
1352 and contain no registers.
1353
1354 The name GENERAL_REGS must be the name of a class (or an alias for
1355 another name such as ALL_REGS). This is the class of registers
1356 that is allowed by "g" or "r" in a register constraint.
1357 Also, registers outside this class are allocated only when
1358 instructions express preferences for them.
1359
1360 The classes must be numbered in nondecreasing order; that is,
1361 a larger-numbered class must never be contained completely
1362 in a smaller-numbered class.
1363
1364 For any two classes, it is very desirable that there be another
1365 class that represents their union. */
1366
1367 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1368 be used as the destination of some of the arithmetic ops. There are
1369 also some special purpose registers; the T bit register, the
1370 Procedure Return Register and the Multiply Accumulate Registers. */
1371 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1372 reg_class_subunion. We don't want to have an actual union class
1373 of these, because it would only be used when both classes are calculated
1374 to give the same cost, but there is only one FPUL register.
1375 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1376 applying to the actual instruction alternative considered. E.g., the
1377 y/r alternative of movsi_ie is considered to have no more cost that
1378 the r/r alternative, which is patently untrue. */
1379
1380 enum reg_class
1381 {
1382 NO_REGS,
1383 R0_REGS,
1384 PR_REGS,
1385 T_REGS,
1386 MAC_REGS,
1387 FPUL_REGS,
1388 SIBCALL_REGS,
1389 GENERAL_REGS,
1390 FP0_REGS,
1391 FP_REGS,
1392 DF_HI_REGS,
1393 DF_REGS,
1394 FPSCR_REGS,
1395 GENERAL_FP_REGS,
1396 GENERAL_DF_REGS,
1397 TARGET_REGS,
1398 ALL_REGS,
1399 LIM_REG_CLASSES
1400 };
1401
1402 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1403
1404 /* Give names of register classes as strings for dump file. */
1405 #define REG_CLASS_NAMES \
1406 { \
1407 "NO_REGS", \
1408 "R0_REGS", \
1409 "PR_REGS", \
1410 "T_REGS", \
1411 "MAC_REGS", \
1412 "FPUL_REGS", \
1413 "SIBCALL_REGS", \
1414 "GENERAL_REGS", \
1415 "FP0_REGS", \
1416 "FP_REGS", \
1417 "DF_HI_REGS", \
1418 "DF_REGS", \
1419 "FPSCR_REGS", \
1420 "GENERAL_FP_REGS", \
1421 "GENERAL_DF_REGS", \
1422 "TARGET_REGS", \
1423 "ALL_REGS", \
1424 }
1425
1426 /* Define which registers fit in which classes.
1427 This is an initializer for a vector of HARD_REG_SET
1428 of length N_REG_CLASSES. */
1429
1430 #define REG_CLASS_CONTENTS \
1431 { \
1432 /* NO_REGS: */ \
1433 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1434 /* R0_REGS: */ \
1435 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1436 /* PR_REGS: */ \
1437 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1438 /* T_REGS: */ \
1439 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1440 /* MAC_REGS: */ \
1441 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1442 /* FPUL_REGS: */ \
1443 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1444 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1445 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1446 /* GENERAL_REGS: */ \
1447 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1448 /* FP0_REGS: */ \
1449 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1450 /* FP_REGS: */ \
1451 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1452 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1453 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1454 /* DF_REGS: */ \
1455 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1456 /* FPSCR_REGS: */ \
1457 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1458 /* GENERAL_FP_REGS: */ \
1459 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1460 /* GENERAL_DF_REGS: */ \
1461 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1462 /* TARGET_REGS: */ \
1463 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1464 /* ALL_REGS: */ \
1465 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1466 }
1467
1468 /* The same information, inverted:
1469 Return the class number of the smallest class containing
1470 reg number REGNO. This could be a conditional expression
1471 or could index an array. */
1472
1473 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1474 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1475
1476 /* When defined, the compiler allows registers explicitly used in the
1477 rtl to be used as spill registers but prevents the compiler from
1478 extending the lifetime of these registers. */
1479
1480 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1481
1482 /* The order in which register should be allocated. */
1483 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1484 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1485 spilled or used otherwise, we better have the FP_REGS allocated first. */
1486 #define REG_ALLOC_ORDER \
1487 {/* Caller-saved FPRs */ \
1488 65, 66, 67, 68, 69, 70, 71, 64, \
1489 72, 73, 74, 75, 80, 81, 82, 83, \
1490 84, 85, 86, 87, 88, 89, 90, 91, \
1491 92, 93, 94, 95, 96, 97, 98, 99, \
1492 /* Callee-saved FPRs */ \
1493 76, 77, 78, 79,100,101,102,103, \
1494 104,105,106,107,108,109,110,111, \
1495 112,113,114,115,116,117,118,119, \
1496 120,121,122,123,124,125,126,127, \
1497 136,137,138,139,140,141,142,143, \
1498 /* FPSCR */ 151, \
1499 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1500 1, 2, 3, 7, 6, 5, 4, 0, \
1501 8, 9, 17, 19, 20, 21, 22, 23, \
1502 36, 37, 38, 39, 40, 41, 42, 43, \
1503 60, 61, 62, \
1504 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1505 10, 11, 12, 13, 14, 18, \
1506 /* SH5 callee-saved GPRs */ \
1507 28, 29, 30, 31, 32, 33, 34, 35, \
1508 44, 45, 46, 47, 48, 49, 50, 51, \
1509 52, 53, 54, 55, 56, 57, 58, 59, \
1510 /* FPUL */ 150, \
1511 /* SH5 branch target registers */ \
1512 128,129,130,131,132,133,134,135, \
1513 /* Fixed registers */ \
1514 15, 16, 24, 25, 26, 27, 63,144, \
1515 145,146,147,148,149,152,153 }
1516
1517 /* The class value for index registers, and the one for base regs. */
1518 #define INDEX_REG_CLASS \
1519 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1520 #define BASE_REG_CLASS GENERAL_REGS
1521
1522 /* Get reg_class from a letter such as appears in the machine
1523 description. */
1524 extern enum reg_class reg_class_from_letter[];
1525
1526 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1527 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1528 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1529 \f
1530 /* Overview of uppercase letter constraints:
1531 A: Addresses (constraint len == 3)
1532 Ac4: sh4 cache operations
1533 Ac5: sh5 cache operations
1534 Bxx: miscellaneous constraints
1535 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1536 fldi0 / fldi0 cases
1537 C: Constants other than only CONST_INT (constraint len == 3)
1538 Css: signed 16 bit constant, literal or symbolic
1539 Csu: unsigned 16 bit constant, literal or symbolic
1540 Csy: label or symbol
1541 Cpg: non-explicit constants that can be directly loaded into a general
1542 purpose register in PIC code. like 's' except we don't allow
1543 PIC_DIRECT_ADDR_P
1544 IJKLMNOP: CONT_INT constants
1545 Ixx: signed xx bit
1546 J16: 0xffffffff00000000 | 0x00000000ffffffff
1547 Kxx: unsigned xx bit
1548 M: 1
1549 N: 0
1550 P27: 1 | 2 | 8 | 16
1551 Q: pc relative load operand
1552 Rxx: reserved for exotic register classes.
1553 S: extra memory (storage) constraints (constraint len == 3)
1554 Sua: unaligned memory operations
1555 W: vector
1556 Z: zero in any mode
1557
1558 unused CONST_INT constraint letters: LO
1559 unused EXTRA_CONSTRAINT letters: D T U Y */
1560
1561 #define CONSTRAINT_LEN(C,STR) \
1562 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1563 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1564 || (C) == 'R' || (C) == 'S') \
1565 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1566
1567 /* The letters I, J, K, L and M in a register constraint string
1568 can be used to stand for particular ranges of immediate operands.
1569 This macro defines what the ranges are.
1570 C is the letter, and VALUE is a constant value.
1571 Return 1 if VALUE is in the range specified by C.
1572 I08: arithmetic operand -127..128, as used in add, sub, etc
1573 I16: arithmetic operand -32768..32767, as used in SHmedia movi
1574 K16: arithmetic operand 0..65535, as used in SHmedia shori
1575 P27: shift operand 1,2,8 or 16
1576 K08: logical operand 0..255, as used in and, or, etc.
1577 M: constant 1
1578 N: constant 0
1579 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1580 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1581 */
1582
1583 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1584 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1585 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1586 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1587 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1588 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1589 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1590 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1591 #define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
1592 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
1593 && TARGET_SH2A)
1594 #define CONST_OK_FOR_I(VALUE, STR) \
1595 ((STR)[1] == '0' && (STR)[2] == '6' ? CONST_OK_FOR_I06 (VALUE) \
1596 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1597 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1598 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1599 : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
1600 : 0)
1601
1602 #define CONST_OK_FOR_J16(VALUE) \
1603 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1604 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1605 #define CONST_OK_FOR_J(VALUE, STR) \
1606 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1607 : 0)
1608
1609 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1610 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1611 #define CONST_OK_FOR_K16(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1612 && ((HOST_WIDE_INT)(VALUE)) <= 65535)
1613 #define CONST_OK_FOR_K(VALUE, STR) \
1614 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1615 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_K16 (VALUE) \
1616 : 0)
1617 #define CONST_OK_FOR_P27(VALUE) \
1618 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1619 #define CONST_OK_FOR_P(VALUE, STR) \
1620 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1621 : 0)
1622 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1623 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1624 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1625 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1626 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1627 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1628 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1629 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1630 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1631 : 0)
1632
1633 /* Similar, but for floating constants, and defining letters G and H.
1634 Here VALUE is the CONST_DOUBLE rtx itself. */
1635
1636 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1637 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1638 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1639 : (C) == 'F')
1640
1641 /* Given an rtx X being reloaded into a reg required to be
1642 in class CLASS, return the class of reg to actually use.
1643 In general this is just CLASS; but on some machines
1644 in some cases it is preferable to use a more restrictive class. */
1645
1646 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1647 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1648 && (GET_CODE (X) == CONST_DOUBLE \
1649 || GET_CODE (X) == SYMBOL_REF \
1650 || PIC_DIRECT_ADDR_P (X)) \
1651 ? GENERAL_REGS \
1652 : (CLASS)) \
1653
1654 #if 0
1655 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1656 ((((REGCLASS_HAS_FP_REG (CLASS) \
1657 && (GET_CODE (X) == REG \
1658 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1659 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1660 && TARGET_FMOVD)))) \
1661 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1662 && GET_CODE (X) == REG \
1663 && FP_REGISTER_P (REGNO (X)))) \
1664 && ! TARGET_SHMEDIA \
1665 && ((MODE) == SFmode || (MODE) == SImode)) \
1666 ? FPUL_REGS \
1667 : (((CLASS) == FPUL_REGS \
1668 || (REGCLASS_HAS_FP_REG (CLASS) \
1669 && ! TARGET_SHMEDIA && MODE == SImode)) \
1670 && (GET_CODE (X) == MEM \
1671 || (GET_CODE (X) == REG \
1672 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1673 || REGNO (X) == T_REG \
1674 || system_reg_operand (X, VOIDmode))))) \
1675 ? GENERAL_REGS \
1676 : (((CLASS) == TARGET_REGS \
1677 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1678 && !EXTRA_CONSTRAINT_Csy (X) \
1679 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1680 ? GENERAL_REGS \
1681 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1682 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1683 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1684 ? GENERAL_REGS \
1685 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1686 && TARGET_REGISTER_P (REGNO (X))) \
1687 ? GENERAL_REGS : (ELSE))
1688
1689 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1690 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1691
1692 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1693 ((REGCLASS_HAS_FP_REG (CLASS) \
1694 && ! TARGET_SHMEDIA \
1695 && immediate_operand ((X), (MODE)) \
1696 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1697 && (MODE) == SFmode && fldi_ok ())) \
1698 ? R0_REGS \
1699 : ((CLASS) == FPUL_REGS \
1700 && ((GET_CODE (X) == REG \
1701 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1702 || REGNO (X) == T_REG)) \
1703 || GET_CODE (X) == PLUS)) \
1704 ? GENERAL_REGS \
1705 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1706 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1707 ? GENERAL_REGS \
1708 : R0_REGS) \
1709 : ((CLASS) == FPSCR_REGS \
1710 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1711 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1712 ? GENERAL_REGS \
1713 : (REGCLASS_HAS_FP_REG (CLASS) \
1714 && TARGET_SHMEDIA \
1715 && immediate_operand ((X), (MODE)) \
1716 && (X) != CONST0_RTX (GET_MODE (X)) \
1717 && GET_MODE (X) != V4SFmode) \
1718 ? GENERAL_REGS \
1719 : (((MODE) == QImode || (MODE) == HImode) \
1720 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1721 ? GENERAL_REGS \
1722 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1723 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
1724 ? TARGET_REGS \
1725 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1726 #else
1727 #define HAVE_SECONDARY_RELOADS
1728 #endif
1729
1730 /* Return the maximum number of consecutive registers
1731 needed to represent mode MODE in a register of class CLASS.
1732
1733 If TARGET_SHMEDIA, we need two FP registers per word.
1734 Otherwise we will need at most one register per word. */
1735 #define CLASS_MAX_NREGS(CLASS, MODE) \
1736 (TARGET_SHMEDIA \
1737 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1738 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1739 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1740
1741 /* If defined, gives a class of registers that cannot be used as the
1742 operand of a SUBREG that changes the mode of the object illegally. */
1743 /* ??? We need to renumber the internal numbers for the frnn registers
1744 when in little endian in order to allow mode size changes. */
1745
1746 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1747 sh_cannot_change_mode_class (FROM, TO, CLASS)
1748 \f
1749 /* Stack layout; function entry, exit and calling. */
1750
1751 /* Define the number of registers that can hold parameters.
1752 These macros are used only in other macro definitions below. */
1753
1754 #define NPARM_REGS(MODE) \
1755 (TARGET_FPU_ANY && (MODE) == SFmode \
1756 ? (TARGET_SH5 ? 12 : 8) \
1757 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1758 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1759 ? (TARGET_SH5 ? 12 : 8) \
1760 : (TARGET_SH5 ? 8 : 4))
1761
1762 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1763 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1764
1765 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1766 #define FIRST_FP_RET_REG FIRST_FP_REG
1767
1768 /* Define this if pushing a word on the stack
1769 makes the stack pointer a smaller address. */
1770 #define STACK_GROWS_DOWNWARD
1771
1772 /* Define this macro to nonzero if the addresses of local variable slots
1773 are at negative offsets from the frame pointer. */
1774 #define FRAME_GROWS_DOWNWARD 1
1775
1776 /* Offset from the frame pointer to the first local variable slot to
1777 be allocated. */
1778 #define STARTING_FRAME_OFFSET 0
1779
1780 /* If we generate an insn to push BYTES bytes,
1781 this says how many the stack pointer really advances by. */
1782 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1783 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1784 do correct alignment. */
1785 #if 0
1786 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1787 #endif
1788
1789 /* Offset of first parameter from the argument pointer register value. */
1790 #define FIRST_PARM_OFFSET(FNDECL) 0
1791
1792 /* Value is the number of byte of arguments automatically
1793 popped when returning from a subroutine call.
1794 FUNDECL is the declaration node of the function (as a tree),
1795 FUNTYPE is the data type of the function (as a tree),
1796 or for a library call it is an identifier node for the subroutine name.
1797 SIZE is the number of bytes of arguments passed on the stack.
1798
1799 On the SH, the caller does not pop any of its arguments that were passed
1800 on the stack. */
1801 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1802
1803 /* Value is the number of bytes of arguments automatically popped when
1804 calling a subroutine.
1805 CUM is the accumulated argument list.
1806
1807 On SHcompact, the call trampoline pops arguments off the stack. */
1808 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1809
1810 /* Some subroutine macros specific to this machine. */
1811
1812 #define BASE_RETURN_VALUE_REG(MODE) \
1813 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1814 ? FIRST_FP_RET_REG \
1815 : TARGET_FPU_ANY && (MODE) == SCmode \
1816 ? FIRST_FP_RET_REG \
1817 : (TARGET_FPU_DOUBLE \
1818 && ((MODE) == DFmode || (MODE) == SFmode \
1819 || (MODE) == DCmode || (MODE) == SCmode )) \
1820 ? FIRST_FP_RET_REG \
1821 : FIRST_RET_REG)
1822
1823 #define BASE_ARG_REG(MODE) \
1824 ((TARGET_SH2E && ((MODE) == SFmode)) \
1825 ? FIRST_FP_PARM_REG \
1826 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1827 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1828 ? FIRST_FP_PARM_REG \
1829 : FIRST_PARM_REG)
1830
1831 /* Define how to find the value returned by a function.
1832 VALTYPE is the data type of the value (as a tree).
1833 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1834 otherwise, FUNC is 0.
1835 For the SH, this is like LIBCALL_VALUE, except that we must change the
1836 mode like PROMOTE_MODE does.
1837 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1838 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1839
1840 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1841 gen_rtx_REG ( \
1842 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1843 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1844 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1845 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1846 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1847 || TREE_CODE (VALTYPE) == REAL_TYPE \
1848 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1849 && sh_promote_prototypes (VALTYPE) \
1850 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1851 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1852
1853 /* Define how to find the value returned by a library function
1854 assuming the value has mode MODE. */
1855 #define LIBCALL_VALUE(MODE) \
1856 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1857
1858 /* 1 if N is a possible register number for a function value. */
1859 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1860 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1861 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1862
1863 /* 1 if N is a possible register number for function argument passing. */
1864 /* ??? There are some callers that pass REGNO as int, and others that pass
1865 it as unsigned. We get warnings unless we do casts everywhere. */
1866 #define FUNCTION_ARG_REGNO_P(REGNO) \
1867 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1868 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1869 || (TARGET_FPU_ANY \
1870 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1871 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1872 + NPARM_REGS (SFmode))))
1873 \f
1874 /* Define a data type for recording info about an argument list
1875 during the scan of that argument list. This data type should
1876 hold all necessary information about the function itself
1877 and about the args processed so far, enough to enable macros
1878 such as FUNCTION_ARG to determine where the next arg should go.
1879
1880 On SH, this is a single integer, which is a number of words
1881 of arguments scanned so far (including the invisible argument,
1882 if any, which holds the structure-value-address).
1883 Thus NARGREGS or more means all following args should go on the stack. */
1884
1885 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1886 struct sh_args {
1887 int arg_count[2];
1888 int force_mem;
1889 /* Nonzero if a prototype is available for the function. */
1890 int prototype_p;
1891 /* The number of an odd floating-point register, that should be used
1892 for the next argument of type float. */
1893 int free_single_fp_reg;
1894 /* Whether we're processing an outgoing function call. */
1895 int outgoing;
1896 /* The number of general-purpose registers that should have been
1897 used to pass partial arguments, that are passed totally on the
1898 stack. On SHcompact, a call trampoline will pop them off the
1899 stack before calling the actual function, and, if the called
1900 function is implemented in SHcompact mode, the incoming arguments
1901 decoder will push such arguments back onto the stack. For
1902 incoming arguments, STACK_REGS also takes into account other
1903 arguments passed by reference, that the decoder will also push
1904 onto the stack. */
1905 int stack_regs;
1906 /* The number of general-purpose registers that should have been
1907 used to pass arguments, if the arguments didn't have to be passed
1908 by reference. */
1909 int byref_regs;
1910 /* Set as by shcompact_byref if the current argument is to be passed
1911 by reference. */
1912 int byref;
1913
1914 /* call_cookie is a bitmask used by call expanders, as well as
1915 function prologue and epilogues, to allow SHcompact to comply
1916 with the SH5 32-bit ABI, that requires 64-bit registers to be
1917 used even though only the lower 32-bit half is visible in
1918 SHcompact mode. The strategy is to call SHmedia trampolines.
1919
1920 The alternatives for each of the argument-passing registers are
1921 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1922 contents from the address in it; (d) add 8 to it, storing the
1923 result in the next register, then (c); (e) copy it from some
1924 floating-point register,
1925
1926 Regarding copies from floating-point registers, r2 may only be
1927 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1928 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1929 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1930 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1931 dr10.
1932
1933 The bit mask is structured as follows:
1934
1935 - 1 bit to tell whether to set up a return trampoline.
1936
1937 - 3 bits to count the number consecutive registers to pop off the
1938 stack.
1939
1940 - 4 bits for each of r9, r8, r7 and r6.
1941
1942 - 3 bits for each of r5, r4, r3 and r2.
1943
1944 - 3 bits set to 0 (the most significant ones)
1945
1946 3 2 1 0
1947 1098 7654 3210 9876 5432 1098 7654 3210
1948 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1949 2223 3344 4555 6666 7777 8888 9999 SSS-
1950
1951 - If F is set, the register must be copied from an FP register,
1952 whose number is encoded in the remaining bits.
1953
1954 - Else, if L is set, the register must be loaded from the address
1955 contained in it. If the P bit is *not* set, the address of the
1956 following dword should be computed first, and stored in the
1957 following register.
1958
1959 - Else, if P is set, the register alone should be popped off the
1960 stack.
1961
1962 - After all this processing, the number of registers represented
1963 in SSS will be popped off the stack. This is an optimization
1964 for pushing/popping consecutive registers, typically used for
1965 varargs and large arguments partially passed in registers.
1966
1967 - If T is set, a return trampoline will be set up for 64-bit
1968 return values to be split into 2 32-bit registers. */
1969 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1970 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1971 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1972 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1973 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1974 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1975 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1976 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1977 #define CALL_COOKIE_INT_REG(REG, VAL) \
1978 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1979 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1980 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1981 long call_cookie;
1982
1983 /* This is set to nonzero when the call in question must use the Renesas ABI,
1984 even without the -mrenesas option. */
1985 int renesas_abi;
1986 };
1987
1988 #define CUMULATIVE_ARGS struct sh_args
1989
1990 #define GET_SH_ARG_CLASS(MODE) \
1991 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1992 ? SH_ARG_FLOAT \
1993 /* There's no mention of complex float types in the SH5 ABI, so we
1994 should presumably handle them as aggregate types. */ \
1995 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1996 ? SH_ARG_INT \
1997 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1998 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1999 ? SH_ARG_FLOAT : SH_ARG_INT)
2000
2001 #define ROUND_ADVANCE(SIZE) \
2002 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2003
2004 /* Round a register number up to a proper boundary for an arg of mode
2005 MODE.
2006
2007 The SH doesn't care about double alignment, so we only
2008 round doubles to even regs when asked to explicitly. */
2009
2010 #define ROUND_REG(CUM, MODE) \
2011 (((TARGET_ALIGN_DOUBLE \
2012 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
2013 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
2014 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
2015 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
2016 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
2017 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
2018
2019 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2020 for a call to a function whose data type is FNTYPE.
2021 For a library call, FNTYPE is 0.
2022
2023 On SH, the offset always starts at 0: the first parm reg is always
2024 the same reg for a given argument class.
2025
2026 For TARGET_HITACHI, the structure value pointer is passed in memory. */
2027
2028 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
2029 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
2030
2031 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
2032 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
2033
2034 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2035 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
2036 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2037 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
2038
2039 /* Return boolean indicating arg of mode MODE will be passed in a reg.
2040 This macro is only used in this file. */
2041
2042 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2043 (((TYPE) == 0 \
2044 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2045 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2046 || ! (AGGREGATE_TYPE_P (TYPE) \
2047 || (!TARGET_FPU_ANY \
2048 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2049 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2050 && ! (CUM).force_mem \
2051 && (TARGET_SH2E \
2052 ? ((MODE) == BLKmode \
2053 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2054 + int_size_in_bytes (TYPE)) \
2055 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2056 : ((ROUND_REG((CUM), (MODE)) \
2057 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2058 <= NPARM_REGS (MODE))) \
2059 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2060
2061 /* By accident we got stuck with passing SCmode on SH4 little endian
2062 in two registers that are nominally successive - which is different from
2063 two single SFmode values, where we take endianness translation into
2064 account. That does not work at all if an odd number of registers is
2065 already in use, so that got fixed, but library functions are still more
2066 likely to use complex numbers without mixing them with SFmode arguments
2067 (which in C would have to be structures), so for the sake of ABI
2068 compatibility the way SCmode values are passed when an even number of
2069 FP registers is in use remains different from a pair of SFmode values for
2070 now.
2071 I.e.:
2072 foo (double); a: fr5,fr4
2073 foo (float a, float b); a: fr5 b: fr4
2074 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2075 this should be the other way round...
2076 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2077 #define FUNCTION_ARG_SCmode_WART 1
2078
2079 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2080 register in SHcompact mode, it must be padded in the most
2081 significant end. This means that passing it by reference wouldn't
2082 pad properly on a big-endian machine. In this particular case, we
2083 pass this argument on the stack, in a way that the call trampoline
2084 will load its value into the appropriate register. */
2085 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2086 ((MODE) == BLKmode \
2087 && TARGET_SHCOMPACT \
2088 && ! TARGET_LITTLE_ENDIAN \
2089 && int_size_in_bytes (TYPE) > 4 \
2090 && int_size_in_bytes (TYPE) < 8)
2091
2092 /* Minimum alignment for an argument to be passed by callee-copy
2093 reference. We need such arguments to be aligned to 8 byte
2094 boundaries, because they'll be loaded using quad loads. */
2095 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2096
2097 /* The SH5 ABI requires floating-point arguments to be passed to
2098 functions without a prototype in both an FP register and a regular
2099 register or the stack. When passing the argument in both FP and
2100 general-purpose registers, list the FP register first. */
2101 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2102 (gen_rtx_PARALLEL \
2103 ((MODE), \
2104 gen_rtvec (2, \
2105 gen_rtx_EXPR_LIST \
2106 (VOIDmode, \
2107 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2108 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2109 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2110 : NULL_RTX), \
2111 const0_rtx), \
2112 gen_rtx_EXPR_LIST \
2113 (VOIDmode, \
2114 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2115 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2116 + (CUM).arg_count[(int) SH_ARG_INT]) \
2117 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2118 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2119 const0_rtx))))
2120
2121 /* The SH5 ABI requires regular registers or stack slots to be
2122 reserved for floating-point arguments. Registers are taken care of
2123 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2124 Unfortunately, there's no way to just reserve a stack slot, so
2125 we'll end up needlessly storing a copy of the argument in the
2126 stack. For incoming arguments, however, the PARALLEL will be
2127 optimized to the register-only form, and the value in the stack
2128 slot won't be used at all. */
2129 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2130 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2131 ? gen_rtx_REG ((MODE), (REG)) \
2132 : gen_rtx_PARALLEL ((MODE), \
2133 gen_rtvec (2, \
2134 gen_rtx_EXPR_LIST \
2135 (VOIDmode, NULL_RTX, \
2136 const0_rtx), \
2137 gen_rtx_EXPR_LIST \
2138 (VOIDmode, gen_rtx_REG ((MODE), \
2139 (REG)), \
2140 const0_rtx))))
2141
2142 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2143 (TARGET_SH5 \
2144 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2145 || (MODE) == DCmode) \
2146 && ((CUM).arg_count[(int) SH_ARG_INT] \
2147 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2148 : GET_MODE_SIZE (MODE)) \
2149 + 7) / 8) > NPARM_REGS (SImode))
2150
2151 /* Perform any needed actions needed for a function that is receiving a
2152 variable number of arguments. */
2153
2154 /* Implement `va_start' for varargs and stdarg. */
2155 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2156 sh_va_start (valist, nextarg)
2157
2158 /* Call the function profiler with a given profile label.
2159 We use two .aligns, so as to make sure that both the .long is aligned
2160 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2161 from the trapa instruction. */
2162
2163 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2164 { \
2165 if (TARGET_SHMEDIA) \
2166 { \
2167 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2168 fprintf((STREAM), "\ttrapa\tr0\n"); \
2169 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2170 } \
2171 else \
2172 { \
2173 fprintf((STREAM), "\t.align\t2\n"); \
2174 fprintf((STREAM), "\ttrapa\t#33\n"); \
2175 fprintf((STREAM), "\t.align\t2\n"); \
2176 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2177 } \
2178 }
2179
2180 /* Define this macro if the code for function profiling should come
2181 before the function prologue. Normally, the profiling code comes
2182 after. */
2183
2184 #define PROFILE_BEFORE_PROLOGUE
2185
2186 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2187 the stack pointer does not matter. The value is tested only in
2188 functions that have frame pointers.
2189 No definition is equivalent to always zero. */
2190
2191 #define EXIT_IGNORE_STACK 1
2192
2193 /*
2194 On the SH, the trampoline looks like
2195 2 0002 D202 mov.l l2,r2
2196 1 0000 D301 mov.l l1,r3
2197 3 0004 422B jmp @r2
2198 4 0006 0009 nop
2199 5 0008 00000000 l1: .long area
2200 6 000c 00000000 l2: .long function */
2201
2202 /* Length in units of the trampoline for entering a nested function. */
2203 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2204
2205 /* Alignment required for a trampoline in bits . */
2206 #define TRAMPOLINE_ALIGNMENT \
2207 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2208 : TARGET_SHMEDIA ? 256 : 64)
2209
2210 /* Emit RTL insns to initialize the variable parts of a trampoline.
2211 FNADDR is an RTX for the address of the function's pure code.
2212 CXT is an RTX for the static chain value for the function. */
2213
2214 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2215 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2216
2217 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2218
2219 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2220 { \
2221 if (TARGET_SHMEDIA) \
2222 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2223 gen_reg_rtx (Pmode), 0, \
2224 OPTAB_LIB_WIDEN); \
2225 } while (0)
2226
2227 /* A C expression whose value is RTL representing the value of the return
2228 address for the frame COUNT steps up from the current frame.
2229 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2230 can ignore COUNT. */
2231
2232 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2233 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2234
2235 /* A C expression whose value is RTL representing the location of the
2236 incoming return address at the beginning of any function, before the
2237 prologue. This RTL is either a REG, indicating that the return
2238 value is saved in REG, or a MEM representing a location in
2239 the stack. */
2240 #define INCOMING_RETURN_ADDR_RTX \
2241 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2242 \f
2243 /* Addressing modes, and classification of registers for them. */
2244 #define HAVE_POST_INCREMENT TARGET_SH1
2245 #define HAVE_PRE_DECREMENT TARGET_SH1
2246
2247 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2248 ? 0 : TARGET_SH1)
2249 #define USE_LOAD_PRE_DECREMENT(mode) 0
2250 #define USE_STORE_POST_INCREMENT(mode) 0
2251 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2252 ? 0 : TARGET_SH1)
2253
2254 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2255 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2256 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2257
2258 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2259 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2260 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2261
2262 /* Macros to check register numbers against specific register classes. */
2263
2264 /* These assume that REGNO is a hard or pseudo reg number.
2265 They give nonzero only if REGNO is a hard reg of the suitable class
2266 or a pseudo reg currently allocated to a suitable hard reg.
2267 Since they use reg_renumber, they are safe only once reg_renumber
2268 has been allocated, which happens in local-alloc.c. */
2269
2270 #define REGNO_OK_FOR_BASE_P(REGNO) \
2271 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2272 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2273 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2274 (TARGET_SHMEDIA \
2275 ? (GENERAL_REGISTER_P (REGNO) \
2276 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2277 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2278
2279 /* Maximum number of registers that can appear in a valid memory
2280 address. */
2281
2282 #define MAX_REGS_PER_ADDRESS 2
2283
2284 /* Recognize any constant value that is a valid address. */
2285
2286 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2287
2288 /* Nonzero if the constant value X is a legitimate general operand. */
2289
2290 #define LEGITIMATE_CONSTANT_P(X) \
2291 (TARGET_SHMEDIA \
2292 ? ((GET_MODE (X) != DFmode \
2293 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2294 || (X) == CONST0_RTX (GET_MODE (X)) \
2295 || ! TARGET_SHMEDIA_FPU \
2296 || TARGET_SHMEDIA64) \
2297 : (GET_CODE (X) != CONST_DOUBLE \
2298 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2299 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2300
2301 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2302 and check its validity for a certain class.
2303 We have two alternate definitions for each of them.
2304 The usual definition accepts all pseudo regs; the other rejects
2305 them unless they have been allocated suitable hard regs.
2306 The symbol REG_OK_STRICT causes the latter definition to be used. */
2307
2308 #ifndef REG_OK_STRICT
2309
2310 /* Nonzero if X is a hard reg that can be used as a base reg
2311 or if it is a pseudo reg. */
2312 #define REG_OK_FOR_BASE_P(X) \
2313 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2314
2315 /* Nonzero if X is a hard reg that can be used as an index
2316 or if it is a pseudo reg. */
2317 #define REG_OK_FOR_INDEX_P(X) \
2318 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2319 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2320
2321 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2322 or if X is a pseudo reg. */
2323 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2324 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2325 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2326
2327 #else
2328
2329 /* Nonzero if X is a hard reg that can be used as a base reg. */
2330 #define REG_OK_FOR_BASE_P(X) \
2331 REGNO_OK_FOR_BASE_P (REGNO (X))
2332
2333 /* Nonzero if X is a hard reg that can be used as an index. */
2334 #define REG_OK_FOR_INDEX_P(X) \
2335 REGNO_OK_FOR_INDEX_P (REGNO (X))
2336
2337 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2338 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2339 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2340
2341 #endif
2342
2343 /* The 'Q' constraint is a pc relative load operand. */
2344 #define EXTRA_CONSTRAINT_Q(OP) \
2345 (GET_CODE (OP) == MEM \
2346 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2347 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2348 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2349 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2350 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2351
2352 /* Extra address constraints. */
2353 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2354
2355 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2356 operand is not SCRATCH (i.e. REG) then R0 is probably being
2357 used, hence mova is being used, hence do not select this pattern */
2358 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2359 #define EXTRA_CONSTRAINT_B(OP, STR) \
2360 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2361 : 0)
2362
2363 /* The `Css' constraint is a signed 16-bit constant, literal or symbolic. */
2364 #define EXTRA_CONSTRAINT_Css(OP) \
2365 (GET_CODE (OP) == CONST \
2366 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2367 && (GET_MODE (XEXP ((OP), 0)) == DImode \
2368 || GET_MODE (XEXP ((OP), 0)) == SImode) \
2369 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2370 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2371 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2372 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2373 && (MOVI_SHORI_BASE_OPERAND_P \
2374 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2375 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2376 1)) == CONST_INT)))
2377
2378 /* The `Csu' constraint is an unsigned 16-bit constant, literal or symbolic. */
2379 #define EXTRA_CONSTRAINT_Csu(OP) \
2380 (GET_CODE (OP) == CONST \
2381 && GET_CODE (XEXP ((OP), 0)) == ZERO_EXTEND \
2382 && (GET_MODE (XEXP ((OP), 0)) == DImode \
2383 || GET_MODE (XEXP ((OP), 0)) == SImode) \
2384 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2385 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2386 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2387 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2388 && (MOVI_SHORI_BASE_OPERAND_P \
2389 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2390 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2391 1)) == CONST_INT)))
2392
2393 /* Check whether OP is a datalabel unspec. */
2394 #define DATALABEL_REF_NO_CONST_P(OP) \
2395 (GET_CODE (OP) == UNSPEC \
2396 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2397 && XVECLEN ((OP), 0) == 1 \
2398 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2399
2400 #define GOT_ENTRY_P(OP) \
2401 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2402 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2403
2404 #define GOTPLT_ENTRY_P(OP) \
2405 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2406 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2407
2408 #define UNSPEC_GOTOFF_P(OP) \
2409 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2410
2411 #define GOTOFF_P(OP) \
2412 (GET_CODE (OP) == CONST \
2413 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2414 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2415 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2416 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2417
2418 #define PIC_ADDR_P(OP) \
2419 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2420 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2421
2422 #define PIC_OFFSET_P(OP) \
2423 (PIC_ADDR_P (OP) \
2424 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2425 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2426
2427 #define PIC_DIRECT_ADDR_P(OP) \
2428 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2429
2430 #define NON_PIC_REFERENCE_P(OP) \
2431 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2432 || (GET_CODE (OP) == CONST \
2433 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2434 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2435 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2436 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2437 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2438 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2439 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2440 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2441
2442 #define PIC_REFERENCE_P(OP) \
2443 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2444 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2445
2446 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2447 (flag_pic \
2448 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2449 || PIC_OFFSET_P (OP)) \
2450 : NON_PIC_REFERENCE_P (OP))
2451
2452 /* The `Csy' constraint is a label or a symbol. */
2453 #define EXTRA_CONSTRAINT_Csy(OP) \
2454 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2455
2456 /* A zero in any shape or form. */
2457 #define EXTRA_CONSTRAINT_Z(OP) \
2458 ((OP) == CONST0_RTX (GET_MODE (OP)))
2459
2460 /* Any vector constant we can handle. */
2461 #define EXTRA_CONSTRAINT_W(OP) \
2462 (GET_CODE (OP) == CONST_VECTOR \
2463 && (sh_rep_vec ((OP), VOIDmode) \
2464 || (HOST_BITS_PER_WIDE_INT >= 64 \
2465 ? sh_const_vec ((OP), VOIDmode) \
2466 : sh_1el_vec ((OP), VOIDmode))))
2467
2468 /* A non-explicit constant that can be loaded directly into a general purpose
2469 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2470 #define EXTRA_CONSTRAINT_Cpg(OP) \
2471 (CONSTANT_P (OP) \
2472 && GET_CODE (OP) != CONST_INT \
2473 && GET_CODE (OP) != CONST_DOUBLE \
2474 && (!flag_pic \
2475 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2476 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2477 && GET_CODE (OP) != LABEL_REF)))
2478 #define EXTRA_CONSTRAINT_C(OP, STR) \
2479 ((STR)[1] == 's' && (STR)[2] == 's' ? EXTRA_CONSTRAINT_Css (OP) \
2480 : (STR)[1] == 's' && (STR)[2] == 'u' ? EXTRA_CONSTRAINT_Csu (OP) \
2481 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2482 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2483 : 0)
2484
2485 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2486 #define EXTRA_CONSTRAINT_Sr0(OP) \
2487 (memory_operand((OP), GET_MODE (OP)) \
2488 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2489 #define EXTRA_CONSTRAINT_Sua(OP) \
2490 (memory_operand((OP), GET_MODE (OP)) \
2491 && GET_CODE (XEXP (OP, 0)) != PLUS)
2492 #define EXTRA_CONSTRAINT_S(OP, STR) \
2493 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2494 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2495 : 0)
2496
2497 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2498 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2499 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2500 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2501 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2502 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2503 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2504 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2505 : 0)
2506 \f
2507 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2508 that is a valid memory address for an instruction.
2509 The MODE argument is the machine mode for the MEM expression
2510 that wants to use this address. */
2511
2512 #define MODE_DISP_OK_4(X,MODE) \
2513 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2514 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2515
2516 #define MODE_DISP_OK_8(X,MODE) \
2517 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2518 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2519
2520 #undef MODE_DISP_OK_4
2521 #define MODE_DISP_OK_4(X,MODE) \
2522 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2523 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2524 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2525 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2526
2527 #undef MODE_DISP_OK_8
2528 #define MODE_DISP_OK_8(X,MODE) \
2529 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2530 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2531 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2532 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2533
2534 #define BASE_REGISTER_RTX_P(X) \
2535 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2536 || (GET_CODE (X) == SUBREG \
2537 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2538 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2539 && GET_CODE (SUBREG_REG (X)) == REG \
2540 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2541
2542 /* Since this must be r0, which is a single register class, we must check
2543 SUBREGs more carefully, to be sure that we don't accept one that extends
2544 outside the class. */
2545 #define INDEX_REGISTER_RTX_P(X) \
2546 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2547 || (GET_CODE (X) == SUBREG \
2548 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2549 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2550 && GET_CODE (SUBREG_REG (X)) == REG \
2551 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2552
2553 /* Jump to LABEL if X is a valid address RTX. This must also take
2554 REG_OK_STRICT into account when deciding about valid registers, but it uses
2555 the above macros so we are in luck.
2556
2557 Allow REG
2558 REG+disp
2559 REG+r0
2560 REG++
2561 --REG */
2562
2563 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2564 into the FRx registers. We implement this by setting the maximum offset
2565 to zero when the value is SFmode. This also restricts loading of SFmode
2566 values into the integer registers, but that can't be helped. */
2567
2568 /* The SH allows a displacement in a QI or HI amode, but only when the
2569 other operand is R0. GCC doesn't handle this very well, so we forgo
2570 all of that.
2571
2572 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2573 DI can be any number 0..60. */
2574
2575 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2576 do { \
2577 if (GET_CODE (OP) == CONST_INT) \
2578 { \
2579 if (TARGET_SHMEDIA) \
2580 { \
2581 int MODE_SIZE; \
2582 /* Check if this the address of an unaligned load / store. */\
2583 if ((MODE) == VOIDmode) \
2584 { \
2585 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2586 goto LABEL; \
2587 break; \
2588 } \
2589 MODE_SIZE = GET_MODE_SIZE (MODE); \
2590 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2591 && INTVAL (OP) >= -512 * MODE_SIZE \
2592 && INTVAL (OP) < 512 * MODE_SIZE) \
2593 goto LABEL; \
2594 else \
2595 break; \
2596 } \
2597 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2598 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2599 } \
2600 } while(0)
2601
2602 #define ALLOW_INDEXED_ADDRESS \
2603 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2604
2605 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2606 { \
2607 if (BASE_REGISTER_RTX_P (X)) \
2608 goto LABEL; \
2609 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2610 && ! TARGET_SHMEDIA \
2611 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2612 goto LABEL; \
2613 else if (GET_CODE (X) == PLUS \
2614 && ((MODE) != PSImode || reload_completed)) \
2615 { \
2616 rtx xop0 = XEXP ((X), 0); \
2617 rtx xop1 = XEXP ((X), 1); \
2618 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2619 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2620 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2621 || ((xop0 == stack_pointer_rtx \
2622 || xop0 == hard_frame_pointer_rtx) \
2623 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2624 || ((xop1 == stack_pointer_rtx \
2625 || xop1 == hard_frame_pointer_rtx) \
2626 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2627 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2628 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2629 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2630 && TARGET_FMOVD && MODE == DFmode))) \
2631 { \
2632 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2633 goto LABEL; \
2634 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2635 goto LABEL; \
2636 } \
2637 } \
2638 }
2639 \f
2640 /* Try machine-dependent ways of modifying an illegitimate address
2641 to be legitimate. If we find one, return the new, valid address.
2642 This macro is used in only one place: `memory_address' in explow.c.
2643
2644 OLDX is the address as it was before break_out_memory_refs was called.
2645 In some cases it is useful to look at this to decide what needs to be done.
2646
2647 MODE and WIN are passed so that this macro can use
2648 GO_IF_LEGITIMATE_ADDRESS.
2649
2650 It is always safe for this macro to do nothing. It exists to recognize
2651 opportunities to optimize the output.
2652
2653 For the SH, if X is almost suitable for indexing, but the offset is
2654 out of range, convert it into a normal form so that cse has a chance
2655 of reducing the number of address registers used. */
2656
2657 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2658 { \
2659 if (flag_pic) \
2660 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2661 if (GET_CODE (X) == PLUS \
2662 && (GET_MODE_SIZE (MODE) == 4 \
2663 || GET_MODE_SIZE (MODE) == 8) \
2664 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2665 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2666 && ! TARGET_SHMEDIA \
2667 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2668 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2669 { \
2670 rtx index_rtx = XEXP ((X), 1); \
2671 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2672 rtx sum; \
2673 \
2674 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2675 /* On rare occasions, we might get an unaligned pointer \
2676 that is indexed in a way to give an aligned address. \
2677 Therefore, keep the lower two bits in offset_base. */ \
2678 /* Instead of offset_base 128..131 use 124..127, so that \
2679 simple add suffices. */ \
2680 if (offset > 127) \
2681 { \
2682 offset_base = ((offset + 4) & ~60) - 4; \
2683 } \
2684 else \
2685 offset_base = offset & ~60; \
2686 /* Sometimes the normal form does not suit DImode. We \
2687 could avoid that by using smaller ranges, but that \
2688 would give less optimized code when SImode is \
2689 prevalent. */ \
2690 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2691 { \
2692 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2693 GEN_INT (offset_base), NULL_RTX, 0, \
2694 OPTAB_LIB_WIDEN); \
2695 \
2696 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2697 goto WIN; \
2698 } \
2699 } \
2700 }
2701
2702 /* A C compound statement that attempts to replace X, which is an address
2703 that needs reloading, with a valid memory address for an operand of
2704 mode MODE. WIN is a C statement label elsewhere in the code.
2705
2706 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2707 of the address. That will allow inheritance of the address reloads. */
2708
2709 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2710 { \
2711 if (GET_CODE (X) == PLUS \
2712 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2713 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2714 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2715 && ! TARGET_SHMEDIA \
2716 && ! (TARGET_SH4 && (MODE) == DFmode) \
2717 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2718 && (ALLOW_INDEXED_ADDRESS \
2719 || XEXP ((X), 0) == stack_pointer_rtx \
2720 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2721 { \
2722 rtx index_rtx = XEXP (X, 1); \
2723 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2724 rtx sum; \
2725 \
2726 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2727 { \
2728 push_reload (X, NULL_RTX, &X, NULL, \
2729 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2730 (TYPE)); \
2731 goto WIN; \
2732 } \
2733 if (TARGET_SH2E && MODE == SFmode) \
2734 { \
2735 X = copy_rtx (X); \
2736 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2737 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2738 (TYPE)); \
2739 goto WIN; \
2740 } \
2741 /* Instead of offset_base 128..131 use 124..127, so that \
2742 simple add suffices. */ \
2743 if (offset > 127) \
2744 { \
2745 offset_base = ((offset + 4) & ~60) - 4; \
2746 } \
2747 else \
2748 offset_base = offset & ~60; \
2749 /* Sometimes the normal form does not suit DImode. We \
2750 could avoid that by using smaller ranges, but that \
2751 would give less optimized code when SImode is \
2752 prevalent. */ \
2753 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2754 { \
2755 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2756 GEN_INT (offset_base)); \
2757 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2758 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2759 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2760 (TYPE)); \
2761 goto WIN; \
2762 } \
2763 } \
2764 /* We must re-recognize what we created before. */ \
2765 else if (GET_CODE (X) == PLUS \
2766 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2767 && GET_CODE (XEXP (X, 0)) == PLUS \
2768 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2769 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2770 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2771 && ! TARGET_SHMEDIA \
2772 && ! (TARGET_SH2E && MODE == SFmode)) \
2773 { \
2774 /* Because this address is so complex, we know it must have \
2775 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2776 it is already unshared, and needs no further unsharing. */ \
2777 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2778 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2779 goto WIN; \
2780 } \
2781 }
2782
2783 /* Go to LABEL if ADDR (a legitimate address expression)
2784 has an effect that depends on the machine mode it is used for.
2785
2786 ??? Strictly speaking, we should also include all indexed addressing,
2787 because the index scale factor is the length of the operand.
2788 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2789 high if we did that. So we rely on reload to fix things up. */
2790
2791 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2792 { \
2793 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2794 goto LABEL; \
2795 }
2796 \f
2797 /* Specify the machine mode that this machine uses
2798 for the index in the tablejump instruction. */
2799 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2800
2801 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2802 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2803 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2804 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2805 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2806 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2807 : SImode)
2808
2809 /* Define as C expression which evaluates to nonzero if the tablejump
2810 instruction expects the table to contain offsets from the address of the
2811 table.
2812 Do not define this if the table should contain absolute addresses. */
2813 #define CASE_VECTOR_PC_RELATIVE 1
2814
2815 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2816 #define FLOAT_TYPE_SIZE 32
2817
2818 /* Since the SH2e has only `float' support, it is desirable to make all
2819 floating point types equivalent to `float'. */
2820 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2821
2822 /* 'char' is signed by default. */
2823 #define DEFAULT_SIGNED_CHAR 1
2824
2825 /* The type of size_t unsigned int. */
2826 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2827
2828 #undef PTRDIFF_TYPE
2829 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2830
2831 #define WCHAR_TYPE "short unsigned int"
2832 #define WCHAR_TYPE_SIZE 16
2833
2834 #define SH_ELF_WCHAR_TYPE "long int"
2835
2836 /* Max number of bytes we can move from memory to memory
2837 in one reasonably fast instruction. */
2838 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2839
2840 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2841 MOVE_MAX is not a compile-time constant. */
2842 #define MAX_MOVE_MAX 8
2843
2844 /* Max number of bytes we want move_by_pieces to be able to copy
2845 efficiently. */
2846 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2847
2848 /* Define if operations between registers always perform the operation
2849 on the full register even if a narrower mode is specified. */
2850 #define WORD_REGISTER_OPERATIONS
2851
2852 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2853 will either zero-extend or sign-extend. The value of this macro should
2854 be the code that says which one of the two operations is implicitly
2855 done, UNKNOWN if none. */
2856 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2857 /* FP registers can load SImode values, but don't implicitly sign-extend
2858 them to DImode. */
2859 #define LOAD_EXTEND_OP(MODE) \
2860 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2861 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2862
2863 /* Define if loading short immediate values into registers sign extends. */
2864 #define SHORT_IMMEDIATES_SIGN_EXTEND
2865
2866 /* Nonzero if access to memory by bytes is no faster than for words. */
2867 #define SLOW_BYTE_ACCESS 1
2868
2869 /* Immediate shift counts are truncated by the output routines (or was it
2870 the assembler?). Shift counts in a register are truncated by SH. Note
2871 that the native compiler puts too large (> 32) immediate shift counts
2872 into a register and shifts by the register, letting the SH decide what
2873 to do instead of doing that itself. */
2874 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2875 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2876 expects - the sign bit is significant - so it appears that we need to
2877 leave this zero for correct SH3 code. */
2878 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2879
2880 /* All integers have the same format so truncation is easy. */
2881 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2882 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2883 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2884
2885 /* Define this if addresses of constant functions
2886 shouldn't be put through pseudo regs where they can be cse'd.
2887 Desirable on machines where ordinary constants are expensive
2888 but a CALL with constant address is cheap. */
2889 /*#define NO_FUNCTION_CSE 1*/
2890
2891 /* The machine modes of pointers and functions. */
2892 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2893 #define FUNCTION_MODE Pmode
2894
2895 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2896 are actually function calls with some special constraints on arguments
2897 and register usage.
2898
2899 These macros tell reorg that the references to arguments and
2900 register clobbers for insns of type sfunc do not appear to happen
2901 until after the millicode call. This allows reorg to put insns
2902 which set the argument registers into the delay slot of the millicode
2903 call -- thus they act more like traditional CALL_INSNs.
2904
2905 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2906 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2907 in particular. */
2908
2909 #define INSN_SETS_ARE_DELAYED(X) \
2910 ((GET_CODE (X) == INSN \
2911 && GET_CODE (PATTERN (X)) != SEQUENCE \
2912 && GET_CODE (PATTERN (X)) != USE \
2913 && GET_CODE (PATTERN (X)) != CLOBBER \
2914 && get_attr_is_sfunc (X)))
2915
2916 #define INSN_REFERENCES_ARE_DELAYED(X) \
2917 ((GET_CODE (X) == INSN \
2918 && GET_CODE (PATTERN (X)) != SEQUENCE \
2919 && GET_CODE (PATTERN (X)) != USE \
2920 && GET_CODE (PATTERN (X)) != CLOBBER \
2921 && get_attr_is_sfunc (X)))
2922
2923 \f
2924 /* Position Independent Code. */
2925
2926 /* We can't directly access anything that contains a symbol,
2927 nor can we indirect via the constant pool. */
2928 #define LEGITIMATE_PIC_OPERAND_P(X) \
2929 ((! nonpic_symbol_mentioned_p (X) \
2930 && (GET_CODE (X) != SYMBOL_REF \
2931 || ! CONSTANT_POOL_ADDRESS_P (X) \
2932 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2933 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2934
2935 #define SYMBOLIC_CONST_P(X) \
2936 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2937 && nonpic_symbol_mentioned_p (X))
2938 \f
2939 /* Compute extra cost of moving data between one register class
2940 and another. */
2941
2942 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2943 uses this information. Hence, the general register <-> floating point
2944 register information here is not used for SFmode. */
2945
2946 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2947 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2948 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2949
2950 #define REGCLASS_HAS_FP_REG(CLASS) \
2951 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2952 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2953
2954 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2955 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2956
2957 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2958 would be so that people with slow memory systems could generate
2959 different code that does fewer memory accesses. */
2960
2961 /* A C expression for the cost of a branch instruction. A value of 1
2962 is the default; other values are interpreted relative to that.
2963 The SH1 does not have delay slots, hence we get a pipeline stall
2964 at every branch. The SH4 is superscalar, so the single delay slot
2965 is not sufficient to keep both pipelines filled. */
2966 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2967 \f
2968 /* Assembler output control. */
2969
2970 /* A C string constant describing how to begin a comment in the target
2971 assembler language. The compiler assumes that the comment will end at
2972 the end of the line. */
2973 #define ASM_COMMENT_START "!"
2974
2975 #define ASM_APP_ON ""
2976 #define ASM_APP_OFF ""
2977 #define FILE_ASM_OP "\t.file\n"
2978 #define SET_ASM_OP "\t.set\t"
2979
2980 /* How to change between sections. */
2981
2982 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2983 #define DATA_SECTION_ASM_OP "\t.data"
2984
2985 #if defined CRT_BEGIN || defined CRT_END
2986 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2987 # undef TEXT_SECTION_ASM_OP
2988 # if __SHMEDIA__ == 1 && __SH5__ == 32
2989 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2990 # else
2991 # define TEXT_SECTION_ASM_OP "\t.text"
2992 # endif
2993 #endif
2994
2995
2996 /* If defined, a C expression whose value is a string containing the
2997 assembler operation to identify the following data as
2998 uninitialized global data. If not defined, and neither
2999 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
3000 uninitialized global data will be output in the data section if
3001 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
3002 used. */
3003 #ifndef BSS_SECTION_ASM_OP
3004 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
3005 #endif
3006
3007 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
3008 separate, explicit argument. If you define this macro, it is used
3009 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
3010 handling the required alignment of the variable. The alignment is
3011 specified as the number of bits.
3012
3013 Try to use function `asm_output_aligned_bss' defined in file
3014 `varasm.c' when defining this macro. */
3015 #ifndef ASM_OUTPUT_ALIGNED_BSS
3016 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3017 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
3018 #endif
3019
3020 /* Define this so that jump tables go in same section as the current function,
3021 which could be text or it could be a user defined section. */
3022 #define JUMP_TABLES_IN_TEXT_SECTION 1
3023
3024 #undef DO_GLOBAL_CTORS_BODY
3025 #define DO_GLOBAL_CTORS_BODY \
3026 { \
3027 typedef (*pfunc)(); \
3028 extern pfunc __ctors[]; \
3029 extern pfunc __ctors_end[]; \
3030 pfunc *p; \
3031 for (p = __ctors_end; p > __ctors; ) \
3032 { \
3033 (*--p)(); \
3034 } \
3035 }
3036
3037 #undef DO_GLOBAL_DTORS_BODY
3038 #define DO_GLOBAL_DTORS_BODY \
3039 { \
3040 typedef (*pfunc)(); \
3041 extern pfunc __dtors[]; \
3042 extern pfunc __dtors_end[]; \
3043 pfunc *p; \
3044 for (p = __dtors; p < __dtors_end; p++) \
3045 { \
3046 (*p)(); \
3047 } \
3048 }
3049
3050 #define ASM_OUTPUT_REG_PUSH(file, v) \
3051 { \
3052 if (TARGET_SHMEDIA) \
3053 { \
3054 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
3055 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
3056 } \
3057 else \
3058 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
3059 }
3060
3061 #define ASM_OUTPUT_REG_POP(file, v) \
3062 { \
3063 if (TARGET_SHMEDIA) \
3064 { \
3065 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
3066 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
3067 } \
3068 else \
3069 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
3070 }
3071
3072 /* DBX register number for a given compiler register number. */
3073 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3074 to match gdb. */
3075 /* svr4.h undefines this macro, yet we really want to use the same numbers
3076 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3077 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3078 register exists, so we should return -1 for invalid register numbers. */
3079 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3080
3081 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3082 used to use the encodings 245..260, but that doesn't make sense:
3083 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3084 the FP registers stay the same when switching between compact and media
3085 mode. Hence, we also need to use the same dwarf frame columns.
3086 Likewise, we need to support unwind information for SHmedia registers
3087 even in compact code. */
3088 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3089 (IN_RANGE ((REGNO), \
3090 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3091 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3092 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3093 : ((int) (REGNO) >= FIRST_FP_REG \
3094 && ((int) (REGNO) \
3095 <= (FIRST_FP_REG + \
3096 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3097 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3098 + (TARGET_SH5 ? 77 : 25)) \
3099 : XD_REGISTER_P (REGNO) \
3100 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3101 : TARGET_REGISTER_P (REGNO) \
3102 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3103 : (REGNO) == PR_REG \
3104 ? (TARGET_SH5 ? 18 : 17) \
3105 : (REGNO) == PR_MEDIA_REG \
3106 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3107 : (REGNO) == T_REG \
3108 ? (TARGET_SH5 ? 242 : 18) \
3109 : (REGNO) == GBR_REG \
3110 ? (TARGET_SH5 ? 238 : 19) \
3111 : (REGNO) == MACH_REG \
3112 ? (TARGET_SH5 ? 239 : 20) \
3113 : (REGNO) == MACL_REG \
3114 ? (TARGET_SH5 ? 240 : 21) \
3115 : (REGNO) == FPUL_REG \
3116 ? (TARGET_SH5 ? 244 : 23) \
3117 : (unsigned) -1)
3118
3119 /* This is how to output a reference to a symbol_ref. On SH5,
3120 references to non-code symbols must be preceded by `datalabel'. */
3121 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3122 do \
3123 { \
3124 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3125 fputs ("datalabel ", (FILE)); \
3126 assemble_name ((FILE), XSTR ((SYM), 0)); \
3127 } \
3128 while (0)
3129
3130 /* This is how to output an assembler line
3131 that says to advance the location counter
3132 to a multiple of 2**LOG bytes. */
3133
3134 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3135 if ((LOG) != 0) \
3136 fprintf ((FILE), "\t.align %d\n", (LOG))
3137
3138 /* Globalizing directive for a label. */
3139 #define GLOBAL_ASM_OP "\t.global\t"
3140
3141 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3142
3143 /* Output a relative address table. */
3144
3145 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3146 switch (GET_MODE (BODY)) \
3147 { \
3148 case SImode: \
3149 if (TARGET_SH5) \
3150 { \
3151 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3152 (VALUE), (REL)); \
3153 break; \
3154 } \
3155 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3156 break; \
3157 case HImode: \
3158 if (TARGET_SH5) \
3159 { \
3160 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3161 (VALUE), (REL)); \
3162 break; \
3163 } \
3164 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3165 break; \
3166 case QImode: \
3167 if (TARGET_SH5) \
3168 { \
3169 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3170 (VALUE), (REL)); \
3171 break; \
3172 } \
3173 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3174 break; \
3175 default: \
3176 break; \
3177 }
3178
3179 /* Output an absolute table element. */
3180
3181 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3182 if (! optimize || TARGET_BIGTABLE) \
3183 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3184 else \
3185 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3186
3187 \f
3188 /* A C statement to be executed just prior to the output of
3189 assembler code for INSN, to modify the extracted operands so
3190 they will be output differently.
3191
3192 Here the argument OPVEC is the vector containing the operands
3193 extracted from INSN, and NOPERANDS is the number of elements of
3194 the vector which contain meaningful data for this insn.
3195 The contents of this vector are what will be used to convert the insn
3196 template into assembler code, so you can change the assembler output
3197 by changing the contents of the vector. */
3198
3199 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3200 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3201
3202 /* Print operand X (an rtx) in assembler syntax to file FILE.
3203 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3204 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3205
3206 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3207
3208 /* Print a memory address as an operand to reference that memory location. */
3209
3210 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3211
3212 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3213 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3214 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3215
3216 /* Recognize machine-specific patterns that may appear within
3217 constants. Used for PIC-specific UNSPECs. */
3218 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3219 do \
3220 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3221 { \
3222 switch (XINT ((X), 1)) \
3223 { \
3224 case UNSPEC_DATALABEL: \
3225 fputs ("datalabel ", (STREAM)); \
3226 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3227 break; \
3228 case UNSPEC_PIC: \
3229 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3230 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3231 break; \
3232 case UNSPEC_GOT: \
3233 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3234 fputs ("@GOT", (STREAM)); \
3235 break; \
3236 case UNSPEC_GOTOFF: \
3237 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3238 fputs ("@GOTOFF", (STREAM)); \
3239 break; \
3240 case UNSPEC_PLT: \
3241 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3242 fputs ("@PLT", (STREAM)); \
3243 break; \
3244 case UNSPEC_GOTPLT: \
3245 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3246 fputs ("@GOTPLT", (STREAM)); \
3247 break; \
3248 case UNSPEC_DTPOFF: \
3249 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3250 fputs ("@DTPOFF", (STREAM)); \
3251 break; \
3252 case UNSPEC_GOTTPOFF: \
3253 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3254 fputs ("@GOTTPOFF", (STREAM)); \
3255 break; \
3256 case UNSPEC_TPOFF: \
3257 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3258 fputs ("@TPOFF", (STREAM)); \
3259 break; \
3260 case UNSPEC_CALLER: \
3261 { \
3262 char name[32]; \
3263 /* LPCS stands for Label for PIC Call Site. */ \
3264 ASM_GENERATE_INTERNAL_LABEL \
3265 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3266 assemble_name ((STREAM), name); \
3267 } \
3268 break; \
3269 default: \
3270 goto FAIL; \
3271 } \
3272 break; \
3273 } \
3274 else \
3275 goto FAIL; \
3276 while (0)
3277
3278 \f
3279 extern struct rtx_def *sh_compare_op0;
3280 extern struct rtx_def *sh_compare_op1;
3281
3282 /* Which processor to schedule for. The elements of the enumeration must
3283 match exactly the cpu attribute in the sh.md file. */
3284
3285 enum processor_type {
3286 PROCESSOR_SH1,
3287 PROCESSOR_SH2,
3288 PROCESSOR_SH2E,
3289 PROCESSOR_SH2A,
3290 PROCESSOR_SH3,
3291 PROCESSOR_SH3E,
3292 PROCESSOR_SH4,
3293 PROCESSOR_SH4A,
3294 PROCESSOR_SH5
3295 };
3296
3297 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3298 extern enum processor_type sh_cpu;
3299
3300 extern int optimize; /* needed for gen_casesi. */
3301
3302 enum mdep_reorg_phase_e
3303 {
3304 SH_BEFORE_MDEP_REORG,
3305 SH_INSERT_USES_LABELS,
3306 SH_SHORTEN_BRANCHES0,
3307 SH_FIXUP_PCLOAD,
3308 SH_SHORTEN_BRANCHES1,
3309 SH_AFTER_MDEP_REORG
3310 };
3311
3312 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3313
3314 /* Handle Renesas compiler's pragmas. */
3315 #define REGISTER_TARGET_PRAGMAS() do { \
3316 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3317 c_register_pragma (0, "trapa", sh_pr_trapa); \
3318 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3319 } while (0)
3320
3321 extern tree sh_deferred_function_attributes;
3322 extern tree *sh_deferred_function_attributes_tail;
3323
3324 /* Set when processing a function with interrupt attribute. */
3325
3326 extern int current_function_interrupt;
3327
3328 \f
3329 /* Instructions with unfilled delay slots take up an
3330 extra two bytes for the nop in the delay slot.
3331 sh-dsp parallel processing insns are four bytes long. */
3332
3333 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3334 (LENGTH) += sh_insn_length_adjustment (X);
3335 \f
3336 /* Define this macro if it is advisable to hold scalars in registers
3337 in a wider mode than that declared by the program. In such cases,
3338 the value is constrained to be within the bounds of the declared
3339 type, but kept valid in the wider mode. The signedness of the
3340 extension may differ from that of the type.
3341
3342 Leaving the unsignedp unchanged gives better code than always setting it
3343 to 0. This is despite the fact that we have only signed char and short
3344 load instructions. */
3345 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3346 if (GET_MODE_CLASS (MODE) == MODE_INT \
3347 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3348 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3349 (MODE) = (TARGET_SH1 ? SImode \
3350 : TARGET_SHMEDIA32 ? SImode : DImode);
3351
3352 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3353
3354 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3355
3356 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3357 and popping arguments. However, we do have push/pop instructions, and
3358 rather limited offsets (4 bits) in load/store instructions, so it isn't
3359 clear if this would give better code. If implemented, should check for
3360 compatibility problems. */
3361
3362 #define SH_DYNAMIC_SHIFT_COST \
3363 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3364
3365
3366 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3367
3368 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3369
3370 #define ACTUAL_NORMAL_MODE(ENTITY) \
3371 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3372
3373 #define NORMAL_MODE(ENTITY) \
3374 (sh_cfun_interrupt_handler_p () \
3375 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3376 : ACTUAL_NORMAL_MODE (ENTITY))
3377
3378 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3379
3380 #define MODE_EXIT(ENTITY) \
3381 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3382
3383 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3384 && (REGNO) == FPSCR_REG)
3385
3386 #define MODE_NEEDED(ENTITY, INSN) \
3387 (recog_memoized (INSN) >= 0 \
3388 ? get_attr_fp_mode (INSN) \
3389 : FP_MODE_NONE)
3390
3391 #define MODE_AFTER(MODE, INSN) \
3392 (TARGET_HITACHI \
3393 && recog_memoized (INSN) >= 0 \
3394 && get_attr_fp_set (INSN) != FP_SET_NONE \
3395 ? (int) get_attr_fp_set (INSN) \
3396 : (MODE))
3397
3398 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3399 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3400
3401 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3402 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3403
3404 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3405 sh_can_redirect_branch ((INSN), (SEQ))
3406
3407 #define DWARF_FRAME_RETURN_COLUMN \
3408 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3409
3410 #define EH_RETURN_DATA_REGNO(N) \
3411 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3412
3413 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3414 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3415
3416 /* We have to distinguish between code and data, so that we apply
3417 datalabel where and only where appropriate. Use sdataN for data. */
3418 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3419 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3420 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3421 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3422
3423 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3424 indirect are handled automatically. */
3425 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3426 do { \
3427 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3428 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3429 { \
3430 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3431 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3432 if (0) goto DONE; \
3433 } \
3434 } while (0)
3435
3436 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3437 /* SH constant pool breaks the devices in crtstuff.c to control section
3438 in where code resides. We have to write it as asm code. */
3439 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3440 asm (SECTION_OP "\n\
3441 mov.l 1f,r1\n\
3442 mova 2f,r0\n\
3443 braf r1\n\
3444 lds r0,pr\n\
3445 0: .p2align 2\n\
3446 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3447 2:\n" TEXT_SECTION_ASM_OP);
3448 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3449
3450 #define SIMULTANEOUS_PREFETCHES 2
3451
3452 /* FIXME: middle-end support for highpart optimizations is missing. */
3453 #define high_life_started reload_in_progress
3454
3455 #endif /* ! GCC_SH_H */
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