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1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992-2016 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Instruction reorganization pass.
24 This pass runs after register allocation and final jump
25 optimization. It should be the last pass to run before peephole.
26 It serves primarily to fill delay slots of insns, typically branch
27 and call insns. Other insns typically involve more complicated
28 interactions of data dependencies and resource constraints, and
29 are better handled by scheduling before register allocation (by the
30 function `schedule_insns').
32 The Branch Penalty is the number of extra cycles that are needed to
33 execute a branch insn. On an ideal machine, branches take a single
34 cycle, and the Branch Penalty is 0. Several RISC machines approach
35 branch delays differently:
37 The MIPS has a single branch delay slot. Most insns
38 (except other branches) can be used to fill this slot. When the
39 slot is filled, two insns execute in two cycles, reducing the
40 branch penalty to zero.
42 The SPARC always has a branch delay slot, but its effects can be
43 annulled when the branch is not taken. This means that failing to
44 find other sources of insns, we can hoist an insn from the branch
45 target that would only be safe to execute knowing that the branch
46 is taken.
48 The HP-PA always has a branch delay slot. For unconditional branches
49 its effects can be annulled when the branch is taken. The effects
50 of the delay slot in a conditional branch can be nullified for forward
51 taken branches, or for untaken backward branches. This means
52 we can hoist insns from the fall-through path for forward branches or
53 steal insns from the target of backward branches.
55 The TMS320C3x and C4x have three branch delay slots. When the three
56 slots are filled, the branch penalty is zero. Most insns can fill the
57 delay slots except jump insns.
59 Three techniques for filling delay slots have been implemented so far:
61 (1) `fill_simple_delay_slots' is the simplest, most efficient way
62 to fill delay slots. This pass first looks for insns which come
63 from before the branch and which are safe to execute after the
64 branch. Then it searches after the insn requiring delay slots or,
65 in the case of a branch, for insns that are after the point at
66 which the branch merges into the fallthrough code, if such a point
67 exists. When such insns are found, the branch penalty decreases
68 and no code expansion takes place.
70 (2) `fill_eager_delay_slots' is more complicated: it is used for
71 scheduling conditional jumps, or for scheduling jumps which cannot
72 be filled using (1). A machine need not have annulled jumps to use
73 this strategy, but it helps (by keeping more options open).
74 `fill_eager_delay_slots' tries to guess the direction the branch
75 will go; if it guesses right 100% of the time, it can reduce the
76 branch penalty as much as `fill_simple_delay_slots' does. If it
77 guesses wrong 100% of the time, it might as well schedule nops. When
78 `fill_eager_delay_slots' takes insns from the fall-through path of
79 the jump, usually there is no code expansion; when it takes insns
80 from the branch target, there is code expansion if it is not the
81 only way to reach that target.
83 (3) `relax_delay_slots' uses a set of rules to simplify code that
84 has been reorganized by (1) and (2). It finds cases where
85 conditional test can be eliminated, jumps can be threaded, extra
86 insns can be eliminated, etc. It is the job of (1) and (2) to do a
87 good job of scheduling locally; `relax_delay_slots' takes care of
88 making the various individual schedules work well together. It is
89 especially tuned to handle the control flow interactions of branch
90 insns. It does nothing for insns with delay slots that do not
91 branch.
93 On machines that use CC0, we are very conservative. We will not make
94 a copy of an insn involving CC0 since we want to maintain a 1-1
95 correspondence between the insn that sets and uses CC0. The insns are
96 allowed to be separated by placing an insn that sets CC0 (but not an insn
97 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
98 delay slot. In that case, we point each insn at the other with REG_CC_USER
99 and REG_CC_SETTER notes. Note that these restrictions affect very few
100 machines because most RISC machines with delay slots will not use CC0
101 (the RT is the only known exception at this point). */
121 \f
122 /* First, some functions that were used before GCC got a control flow graph.
123 These functions are now only used here in reorg.c, and have therefore
124 been moved here to avoid inadvertent misuse elsewhere in the compiler. */
126 /* Return the last label to mark the same position as LABEL. Return LABEL
127 itself if it is null or any return rtx. */
129 static rtx
131 {
144 }
146 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
147 and REG_CC_USER notes so we can find it. */
149 static void
151 {
159 }
160 \f
161 /* Insns which have delay slots that have not yet been filled. */
166 /* Define macros to refer to the first and last slot containing unfilled
167 insns. These are used because the list may move and its address
168 should be recomputed at each use. */
170 #define unfilled_slots_base \
171 ((rtx_insn **) obstack_base (&unfilled_slots_obstack))
173 #define unfilled_slots_next \
174 ((rtx_insn **) obstack_next_free (&unfilled_slots_obstack))
176 /* Points to the label before the end of the function, or before a
177 return insn. */
179 /* Likewise for a simple_return. */
182 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
183 not always monotonically increase. */
186 /* Highest valid index in `uid_to_ruid'. */
214 rtx *);
236 \f
237 /* A wrapper around next_active_insn which takes care to return ret_rtx
238 unchanged. */
240 static rtx
242 {
246 }
247 \f
248 /* Return true iff INSN is a simplejump, or any kind of return insn. */
250 static bool
252 {
256 }
257 \f
258 /* Return TRUE if this insn should stop the search for insn to fill delay
259 slots. LABELS_P indicates that labels should terminate the search.
260 In all cases, jumps terminate the search. */
262 static int
264 {
268 /* If the insn can throw an exception that is caught within the function,
269 it may effectively perform a jump from the viewpoint of the function.
270 Therefore act like for a jump. */
275 {
288 /* OK unless it contains a delay slot or is an `asm' insn of some type.
289 We don't know anything about these. */
296 }
297 }
298 \f
299 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
300 resource set contains a volatile memory reference. Otherwise, return FALSE. */
302 static int
304 {
310 }
312 /* Return TRUE if any resource marked in RES, a `struct resources', is
313 referenced by INSN. If INCLUDE_DELAYED_EFFECTS is set, return if the called
314 routine is using those resources.
316 We compute this by computing all the resources referenced by INSN and
317 seeing if this conflicts with RES. It might be faster to directly check
318 ourselves, and this is the way it used to work, but it means duplicating
319 a large block of complex code. */
321 static int
324 {
330 }
332 /* Return TRUE if INSN modifies resources that are marked in RES.
333 INCLUDE_DELAYED_EFFECTS is set if the actions of that routine should be
334 included. CC0 is only modified if it is explicitly set; see comments
335 in front of mark_set_resources for details. */
337 static int
340 {
345 (include_delayed_effects
346 ? MARK_SRC_DEST_CALL
349 }
350 \f
351 /* Find a label at the end of the function or before a RETURN. If there
352 is none, try to make one. If that fails, returns 0.
354 The property of such a label is that it is placed just before the
355 epilogue or a bare RETURN insn, so that another bare RETURN can be
356 turned into a jump to the label unconditionally. In particular, the
357 label cannot be placed before a RETURN insn with a filled delay slot.
359 ??? There may be a problem with the current implementation. Suppose
360 we start with a bare RETURN insn and call find_end_label. It may set
361 function_return_label just before the RETURN. Suppose the machinery
362 is able to fill the delay slot of the RETURN insn afterwards. Then
363 function_return_label is no longer valid according to the property
364 described above and find_end_label will still return it unmodified.
365 Note that this is probably mitigated by the following observation:
366 once function_return_label is made, it is very likely the target of
367 a jump, so filling the delay slot of the RETURN will be much more
368 difficult.
369 KIND is either simple_return_rtx or ret_rtx, indicating which type of
370 return we're looking for. */
374 {
380 else
381 {
384 }
386 /* If we found one previously, return it. */
390 /* Otherwise, see if there is a label at the end of the function. If there
391 is, it must be that RETURN insns aren't needed, so that is our return
392 label and we don't have to do anything else. */
401 /* When a target threads its epilogue we might already have a
402 suitable return insn. If so put a label before it for the
403 function_return_label. */
407 {
412 /* Put the label before any USE insns that may precede the RETURN
413 insn. */
419 }
423 else
424 {
427 /* If the basic block reorder pass moves the return insn to
428 some other place try to locate it again and put our
429 function_return_label there. */
433 {
436 /* Put the label before any USE insns that may precede the
437 RETURN insn. */
442 }
443 else
444 {
446 /* The RETURN insn has its delay slot filled so we cannot
447 emit the label just before it. Since we already have
448 an epilogue and cannot emit a new RETURN, we cannot
449 emit the label at all. */
452 /* Otherwise, make a new label and emit a RETURN and BARRIER,
453 if needed. */
456 {
457 /* The return we make may have delay slots too. */
464 }
465 }
467 }
469 /* Show one additional use for this label so it won't go away until
470 we are done. */
474 }
475 \f
476 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
477 the pattern of INSN with the SEQUENCE.
479 Returns the insn containing the SEQUENCE that replaces INSN. */
483 {
484 /* Allocate the rtvec to hold the insns and the SEQUENCE. */
489 /* If DELAY_INSN has a location, use it for SEQ_INSN. If DELAY_INSN does
490 not have a location, but one of the delayed insns does, we pick up a
491 location from there later. */
494 /* Unlink INSN from the insn chain, so that we can put it into
495 the SEQUENCE. Remember where we want to emit SEQUENCE in AFTER. */
500 /* Build our SEQUENCE and rebuild the insn chain. */
507 {
511 /* Show that this copy of the insn isn't deleted. */
514 /* Unlink insn from its original place, and re-emit it into
515 the sequence. */
519 /* SPARC assembler, for instance, emit warning when debug info is output
520 into the delay slot. */
526 {
529 {
531 /* Remove any REG_DEAD notes because we can't rely on them now
532 that the insn has been moved. */
538 /* Keep the label reference count up to date. */
545 }
546 }
547 }
550 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
554 }
556 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
557 be in the order in which the insns are to be executed. */
559 static void
561 {
562 /* If INSN has its block number recorded, clear it since we may
563 be moving the insn to a new block. */
566 }
567 \f
568 /* Delete INSN from the delay slot of the insn that it is in, which may
569 produce an insn with no delay slots. Return the new insn. */
573 {
579 /* We first must find the insn containing the SEQUENCE with INSN in its
580 delay slot. Do this by finding an insn, TRIAL, where
581 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
586 ;
594 /* Create a delay list consisting of all the insns other than the one
595 we are deleting (unless we were the only one). */
602 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
603 list, and rebuild the delay list if non-empty. */
609 /* If there was a barrier after the old SEQUENCE, remit it. */
613 /* If there are any delay insns, remit them. Otherwise clear the
614 annul flag. */
622 /* Show we need to fill this insn again. */
626 }
627 \f
628 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
629 the insn that sets CC0 for it and delete it too. */
631 static void
633 {
634 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
635 delete the insn that sets the condition code, but it is hard to find it.
636 Since this case is rare anyway, don't bother trying; there would likely
637 be other insns that became dead anyway, which we wouldn't know to
638 delete. */
641 {
644 /* If a reg-note was found, it points to an insn to set CC0. This
645 insn is in the delay list of some other insn. So delete it from
646 the delay list it was in. */
648 {
652 }
653 else
654 {
655 /* The insn setting CC0 is our previous insn, but it may be in
656 a delay slot. It will be the last insn in the delay slot, if
657 it is. */
666 else
668 }
669 }
672 }
673 \f
674 /* Counters for delay-slot filling. */
676 #define NUM_REORG_FUNCTIONS 2
677 #define MAX_DELAY_HISTOGRAM 3
678 #define MAX_REORG_PASSES 2
686 static void
688 {
693 }
694 \f
695 /* Optimize the following cases:
697 1. When a conditional branch skips over only one instruction,
698 use an annulling branch and put that insn in the delay slot.
699 Use either a branch that annuls when the condition if true or
700 invert the test with a branch that annuls when the condition is
701 false. This saves insns, since otherwise we must copy an insn
702 from the L1 target.
704 (orig) (skip) (otherwise)
705 Bcc.n L1 Bcc',a L1 Bcc,a L1'
706 insn insn insn2
707 L1: L1: L1:
708 insn2 insn2 insn2
709 insn3 insn3 L1':
710 insn3
712 2. When a conditional branch skips over only one instruction,
713 and after that, it unconditionally branches somewhere else,
714 perform the similar optimization. This saves executing the
715 second branch in the case where the inverted condition is true.
717 Bcc.n L1 Bcc',a L2
718 insn insn
719 L1: L1:
720 Bra L2 Bra L2
722 INSN is a JUMP_INSN.
724 This should be expanded to skip over N insns, where N is the number
725 of delay slots required. */
727 static void
729 {
746 /* There are two cases where we are just executing one insn (we assume
747 here that a branch requires only one insn; this should be generalized
748 at some point): Where the branch goes around a single insn or where
749 we have one insn followed by a branch to the same label we branch to.
750 In both of these cases, inverting the jump and annulling the delay
751 slot give the same effect in fewer insns. */
756 {
758 {
763 }
770 /* Also, if we are targeting an unconditional
771 branch, thread our jump to the target of that branch. Don't
772 change this into a RETURN here, because it may not accept what
773 we have in the delay slot. We'll fix this up later. */
775 {
781 {
782 /* Recompute the flags based on TARGET_LABEL since threading
783 the jump to TARGET_LABEL may change the direction of the
784 jump (which may change the circumstances in which the
785 delay slot is nullified). */
789 }
790 }
793 }
794 }
795 \f
796 /* Encode and return branch direction and prediction information for
797 INSN assuming it will jump to LABEL.
799 Non conditional branches return no direction information and
800 are predicted as very likely taken. */
802 static int
804 {
807 /* get_jump_flags can be passed any insn with delay slots, these may
808 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
809 direction information, and only if they are conditional jumps.
811 If LABEL is a return, then there is no way to determine the branch
812 direction. */
818 flags
821 /* No valid direction information. */
822 else
826 }
828 /* Return truth value of the statement that this branch
829 is mostly taken. If we think that the branch is extremely likely
830 to be taken, we return 2. If the branch is slightly more likely to be
831 taken, return 1. If the branch is slightly less likely to be taken,
832 return 0 and if the branch is highly unlikely to be taken, return -1. */
834 static int
836 {
837 /* If branch probabilities are available, then use that number since it
838 always gives a correct answer. */
841 {
850 else
852 }
854 /* If there is no note, assume branches are not taken.
855 This should be rare. */
857 }
859 /* Return the condition under which INSN will branch to TARGET. If TARGET
860 is zero, return the condition under which INSN will return. If INSN is
861 an unconditional branch, return const_true_rtx. If INSN isn't a simple
862 type of jump, or it doesn't go to TARGET, return 0. */
864 static rtx
866 {
868 rtx src;
895 {
902 }
905 }
907 /* Return nonzero if CONDITION is more strict than the condition of
908 INSN, i.e., if INSN will always branch if CONDITION is true. */
910 static int
912 {
931 }
933 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
934 any insns already in the delay slot of JUMP. */
936 static int
938 {
942 /* Make sure all the delay slots of this jump would still
943 be valid after threading the jump. If they are still
944 valid, then return nonzero. */
949 #if ANNUL_IFFALSE_SLOTS
953 #endif
954 #if ANNUL_IFTRUE_SLOTS
958 #endif
963 }
965 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
966 any insns we wish to place in the delay slot of JUMP. */
968 static int
971 {
972 /* Make sure all the insns in DELAY_LIST would still be
973 valid after threading the jump. If they are still
974 valid, then return nonzero. */
981 #if ANNUL_IFFALSE_SLOTS
985 #endif
986 #if ANNUL_IFTRUE_SLOTS
990 #endif
995 }
997 /* DELAY_LIST is a list of insns that have already been placed into delay
998 slots. See if all of them have the same annulling status as ANNUL_TRUE_P.
999 If not, return 0; otherwise return 1. */
1001 static int
1004 {
1013 }
1014 \f
1015 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1016 the condition tested by INSN is CONDITION and the resources shown in
1017 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1018 from SEQ's delay list, in addition to whatever insns it may execute
1019 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1020 needed while searching for delay slot insns. Return the concatenated
1021 delay list if possible, otherwise, return 0.
1023 SLOTS_TO_FILL is the total number of slots required by INSN, and
1024 PSLOTS_FILLED points to the number filled so far (also the number of
1025 insns in DELAY_LIST). It is updated with the number that have been
1026 filled from the SEQUENCE, if any.
1028 PANNUL_P points to a nonzero value if we already know that we need
1029 to annul INSN. If this routine determines that annulling is needed,
1030 it may set that value nonzero.
1032 PNEW_THREAD points to a location that is to receive the place at which
1033 execution should continue. */
1035 static void
1042 {
1052 /* We can't do anything if there are more delay slots in SEQ than we
1053 can handle, or if we don't know that it will be a taken branch.
1054 We know that it will be a taken branch if it is either an unconditional
1055 branch or a conditional branch with a stricter branch condition.
1057 Also, exit if the branch has more than one set, since then it is computing
1058 other results that can't be ignored, e.g. the HPPA mov&branch instruction.
1059 ??? It may be possible to move other sets into INSN in addition to
1060 moving the instructions in the delay slots.
1062 We can not steal the delay list if one of the instructions in the
1063 current delay_list modifies the condition codes and the jump in the
1064 sequence is a conditional jump. We can not do this because we can
1065 not change the direction of the jump because the condition codes
1066 will effect the direction of the jump in the sequence. */
1072 {
1076 }
1083 /* On some targets, branches with delay slots can have a limited
1084 displacement. Give the back end a chance to tell us we can't do
1085 this. */
1091 {
1098 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1099 delay list. */
1101 /* If TRIAL is from the fallthrough code of an annulled branch insn
1102 in SEQ, we cannot use it. */
1107 /* If this insn was already done (usually in a previous delay slot),
1108 pretend we put it in our delay slot. */
1113 /* We will end up re-vectoring this branch, so compute flags
1114 based on jumping to the new label. */
1128 {
1130 {
1131 /* Frame related instructions cannot go into annulled delay
1132 slots, it messes up the dwarf info. */
1136 }
1140 total_slots_filled++;
1144 }
1145 else
1147 }
1149 /* Record the effect of the instructions that were redundant and which
1150 we therefore decided not to copy. */
1155 /* Show the place to which we will be branching. */
1158 /* Add any new insns to the delay list and update the count of the
1159 number of slots filled. */
1167 }
1168 \f
1169 /* Similar to steal_delay_list_from_target except that SEQ is on the
1170 fallthrough path of INSN. Here we only do something if the delay insn
1171 of SEQ is an unconditional branch. In that case we steal its delay slot
1172 for INSN since unconditional branches are much easier to fill. */
1174 static void
1183 {
1191 /* We can't do anything if SEQ's delay insn isn't an
1192 unconditional branch. */
1198 {
1201 /* If TRIAL sets CC0, stealing it will move it too far from the use
1202 of CC0. */
1210 /* If this insn was already done, we don't need it. */
1212 {
1216 }
1226 {
1234 }
1235 else
1237 }
1241 }
1242 \f
1243 /* Try merging insns starting at THREAD which match exactly the insns in
1244 INSN's delay list.
1246 If all insns were matched and the insn was previously annulling, the
1247 annul bit will be cleared.
1249 For each insn that is merged, if the branch is or will be non-annulling,
1250 we delete the merged insn. */
1252 static void
1254 {
1270 /* If this is not an annulling branch, take into account anything needed in
1271 INSN's delay slot. This prevents two increments from being incorrectly
1272 folded into one. If we are annulling, this would be the correct
1273 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1274 will essentially disable this optimization. This method is somewhat of
1275 a kludge, but I don't see a better way.) */
1283 {
1289 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1295 /* We can't share an insn that sets cc0. */
1301 /* Update next_trial, in case try_split succeeded. */
1303 /* Likewise THREAD. */
1306 /* Have to test this condition if annul condition is different
1307 from (and less restrictive than) non-annulling one. */
1309 {
1312 {
1319 }
1320 else
1327 }
1331 }
1333 /* See if we stopped on a filled insn. If we did, try to see if its
1334 delay slots match. */
1340 {
1344 /* Account for resources set/needed by the filled insn. */
1349 {
1353 /* Account for resources set by the insn following NEXT_TO_MATCH
1354 inside INSN's delay list. */
1358 /* Account for resources set by the insn before DTRIAL and inside
1359 TRIAL's delay list. */
1368 /* Check that DTRIAL and NEXT_TO_MATCH does not reference a
1369 resource modified between them (only dtrial is checked because
1370 next_to_match and dtrial shall to be equal in order to hit
1371 this line) */
1374 {
1376 {
1384 }
1385 else
1393 }
1394 else
1395 {
1396 /* Keep track of the set/referenced resources for the delay
1397 slots of any trial insns we encounter. */
1400 }
1401 }
1402 }
1404 /* If all insns in the delay slot have been matched and we were previously
1405 annulling the branch, we need not any more. In that case delete all the
1406 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn in
1407 the delay list so that we know that it isn't only being used at the
1408 target. */
1410 {
1414 {
1419 }
1420 else
1421 {
1424 }
1430 }
1431 }
1432 \f
1433 /* See if INSN is redundant with an insn in front of TARGET. Often this
1434 is called when INSN is a candidate for a delay slot of TARGET.
1435 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1436 of INSN. Often INSN will be redundant with an insn in a delay slot of
1437 some previous insn. This happens when we have a series of branches to the
1438 same label; in that case the first insn at the target might want to go
1439 into each of the delay slots.
1441 If we are not careful, this routine can take up a significant fraction
1442 of the total compilation time (4%), but only wins rarely. Hence we
1443 speed this routine up by making two passes. The first pass goes back
1444 until it hits a label and sees if it finds an insn with an identical
1445 pattern. Only in this (relatively rare) event does it check for
1446 data conflicts.
1448 We do not split insns we encounter. This could cause us not to find a
1449 redundant insn, but the cost of splitting seems greater than the possible
1450 gain in rare cases. */
1454 {
1458 rtx pat;
1463 /* If INSN has any REG_UNUSED notes, it can't match anything since we
1464 are allowed to not actually assign to such a register. */
1468 /* Scan backwards looking for a match. */
1473 {
1474 /* (use (insn))s can come immediately after a barrier if the
1475 label that used to precede them has been deleted as dead.
1476 See delete_related_insns. */
1489 {
1490 /* Stop for a CALL and its delay slots because it is difficult to
1491 track its resource needs correctly. */
1495 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
1496 slots because it is difficult to track its resource needs
1497 correctly. */
1505 /* See if any of the insns in the delay slot match, updating
1506 resource requirements as we go. */
1513 /* If found a match, exit this loop early. */
1516 }
1521 }
1523 /* If we didn't find an insn that matches, return 0. */
1527 /* See what resources this insn sets and needs. If they overlap, or
1528 if this insn references CC0, it can't be redundant. */
1535 /* If TARGET is a SEQUENCE, get the main insn. */
1541 /* The insn requiring the delay may not set anything needed or set by
1542 INSN. */
1547 /* Insns we pass may not set either NEEDED or SET, so merge them for
1548 simpler tests. */
1552 /* This insn isn't redundant if it conflicts with an insn that either is
1553 or will be in a delay slot of TARGET. */
1567 /* Scan backwards until we reach a label or an insn that uses something
1568 INSN sets or sets something insn uses or sets. */
1574 {
1584 {
1588 /* If this is a CALL_INSN and its delay slots, it is hard to track
1589 the resource needs properly, so give up. */
1593 /* If this is an INSN or JUMP_INSN with delayed effects, it
1594 is hard to track the resource needs properly, so give up. */
1605 /* See if any of the insns in the delay slot match, updating
1606 resource requirements as we go. */
1608 {
1611 /* If an insn will be annulled if the branch is false, it isn't
1612 considered as a possible duplicate insn. */
1615 {
1616 /* Show that this insn will be used in the sequel. */
1619 }
1621 /* Unless this is an annulled insn from the target of a branch,
1622 we must stop if it sets anything needed or set by INSN. */
1626 }
1628 /* If the insn requiring the delay slot conflicts with INSN, we
1629 must stop. */
1632 }
1633 else
1634 {
1635 /* See if TRIAL is the same as INSN. */
1640 /* Can't go any further if TRIAL conflicts with INSN. */
1643 }
1644 }
1647 }
1648 \f
1649 /* Return 1 if THREAD can only be executed in one way. If LABEL is nonzero,
1650 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
1651 is nonzero, we are allowed to fall into this thread; otherwise, we are
1652 not.
1654 If LABEL is used more than one or we pass a label other than LABEL before
1655 finding an active insn, we do not own this thread. */
1657 static int
1659 {
1663 /* We don't own the function end. */
1667 /* We have a non-NULL insn. */
1670 /* Get the first active insn, or THREAD_INSN, if it is an active insn. */
1681 /* Ensure that we reach a BARRIER before any insn or label. */
1693 }
1694 \f
1695 /* Called when INSN is being moved from a location near the target of a jump.
1696 We leave a marker of the form (use (INSN)) immediately in front
1697 of WHERE for mark_target_live_regs. These markers will be deleted when
1698 reorg finishes.
1700 We used to try to update the live status of registers if WHERE is at
1701 the start of a basic block, but that can't work since we may remove a
1702 BARRIER in relax_delay_slots. */
1704 static void
1706 {
1707 /* Ignore if this was in a delay slot and it came from the target of
1708 a branch. */
1714 /* INSN might be making a value live in a block where it didn't use to
1715 be. So recompute liveness information for this block. */
1718 }
1720 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
1721 the basic block containing the jump. */
1723 static int
1725 {
1728 }
1730 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
1731 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
1732 that reference values used in INSN. If we find one, then we move the
1733 REG_DEAD note to INSN.
1735 This is needed to handle the case where a later insn (after INSN) has a
1736 REG_DEAD note for a register used by INSN, and this later insn subsequently
1737 gets moved before a CODE_LABEL because it is a redundant insn. In this
1738 case, mark_target_live_regs may be confused into thinking the register
1739 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
1741 static void
1743 {
1750 {
1758 {
1759 /* Move the REG_DEAD note from P to INSN. */
1763 }
1764 }
1765 }
1767 /* Called when an insn redundant with start_insn is deleted. If there
1768 is a REG_DEAD note for the target of start_insn between start_insn
1769 and stop_insn, then the REG_DEAD note needs to be deleted since the
1770 value no longer dies there.
1772 If the REG_DEAD note isn't deleted, then mark_target_live_regs may be
1773 confused into thinking the register is dead. */
1775 static void
1777 {
1784 {
1792 {
1795 }
1796 }
1797 }
1799 /* Delete any REG_UNUSED notes that exist on INSN but not on REDUNDANT_INSN.
1801 This handles the case of udivmodXi4 instructions which optimize their
1802 output depending on whether any REG_UNUSED notes are present.
1803 we must make sure that INSN calculates as many results as REDUNDANT_INSN
1804 does. */
1806 static void
1808 {
1812 {
1822 }
1823 }
1824 \f
1827 /* Return the label before INSN, or put a new label there. If SIBLING is
1828 non-zero, it is another label associated with the new label (if any),
1829 typically the former target of the jump that will be redirected to
1830 the new label. */
1834 {
1837 /* Find an existing label at this point
1838 or make a new one if there is none. */
1842 {
1849 {
1852 }
1853 }
1855 }
1857 /* Scan a function looking for insns that need a delay slot and find insns to
1858 put into the delay slot.
1860 NON_JUMPS_P is nonzero if we are to only try to fill non-jump insns (such
1861 as calls). We do these first since we don't want jump insns (that are
1862 easier to fill) to get the only insns that could be used for non-jump insns.
1863 When it is zero, only try to fill JUMP_INSNs.
1865 When slots are filled in this manner, the insns (including the
1866 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
1867 it is possible to tell whether a delay slot has really been filled
1868 or not. `final' knows how to deal with this, by communicating
1869 through FINAL_SEQUENCE. */
1871 static void
1873 {
1875 rtx pat;
1883 {
1885 /* Get the next insn to fill. If it has already had any slots assigned,
1886 we can't do anything with it. Maybe we'll improve this later. */
1897 /* It may have been that this insn used to need delay slots, but
1898 now doesn't; ignore in that case. This can happen, for example,
1899 on the HP PA RISC, where the number of delay slots depends on
1900 what insns are nearby. */
1903 /* Some machine description have defined instructions to have
1904 delay slots only in certain circumstances which may depend on
1905 nearby insns (which change due to reorg's actions).
1907 For example, the PA port normally has delay slots for unconditional
1908 jumps.
1910 However, the PA port claims such jumps do not have a delay slot
1911 if they are immediate successors of certain CALL_INSNs. This
1912 allows the port to favor filling the delay slot of the call with
1913 the unconditional jump. */
1917 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
1918 says how many. After initialization, first try optimizing
1920 call _foo call _foo
1921 nop add %o7,.-L1,%o7
1922 b,a L1
1923 nop
1925 If this case applies, the delay slot of the call is filled with
1926 the unconditional jump. This is done first to avoid having the
1927 delay slot of the call filled in the backward scan. Also, since
1928 the unconditional jump is likely to also have a delay slot, that
1929 insn must exist when it is subsequently scanned.
1931 This is tried on each insn with delay slots as some machines
1932 have insns which perform calls, but are not represented as
1933 CALL_INSNs. */
1940 else
1949 {
1951 slots_filled++;
1954 /* TRIAL may have had its delay slot filled, then unfilled. When
1955 the delay slot is unfilled, TRIAL is placed back on the unfilled
1956 slots obstack. Unfortunately, it is placed on the end of the
1957 obstack, not in its original location. Therefore, we must search
1958 from entry i + 1 to the end of the unfilled slots obstack to
1959 try and find TRIAL. */
1962 tmp++;
1964 /* Remove the unconditional jump from consideration for delay slot
1965 filling and unthread it. */
1968 {
1975 }
1976 }
1978 /* Now, scan backwards from the insn to search for a potential
1979 delay-slot candidate. Stop searching when a label or jump is hit.
1981 For each candidate, if it is to go into the delay slot (moved
1982 forward in execution sequence), it must not need or set any resources
1983 that were set by later insns and must not set any resources that
1984 are needed for those insns.
1986 The delay slot insn itself sets resources unless it is a call
1987 (in which case the called routine, not the insn itself, is doing
1988 the setting). */
1991 {
1992 /* If the flags register is dead after the insn, then we want to be
1993 able to accept a candidate that clobbers it. For this purpose,
1994 we need to filter the flags register during life analysis, so
1995 that it doesn't create RAW and WAW dependencies, while still
1996 creating the necessary WAR dependencies. */
1997 bool filter_flags
2006 {
2009 }
2014 {
2017 /* This must be an INSN or CALL_INSN. */
2020 /* Stand-alone USE and CLOBBER are just for flow. */
2024 /* Check for resource conflict first, to avoid unnecessary
2025 splitting. */
2031 /* Can't separate set of cc0 from its use. */
2034 {
2038 {
2039 /* In this case, we are searching backward, so if we
2040 find insns to put on the delay list, we want
2041 to put them at the head, rather than the
2042 tail, of the list. */
2051 }
2052 }
2056 {
2058 /* If the flags register is set, then it doesn't create RAW
2059 dependencies any longer and it also doesn't create WAW
2060 dependencies since it's dead after the original insn. */
2062 {
2065 }
2066 }
2068 }
2069 }
2071 /* If all needed slots haven't been filled, we come here. */
2073 /* Try to optimize case of jumping around a single insn. */
2080 {
2084 }
2086 /* Try to get insns from beyond the insn needing the delay slot.
2087 These insns can neither set or reference resources set in insns being
2088 skipped, cannot set resources in the insn being skipped, and, if this
2089 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
2090 call might not return).
2092 There used to be code which continued past the target label if
2093 we saw all uses of the target label. This code did not work,
2094 because it failed to account for some instructions which were
2095 both annulled and marked as from the target. This can happen as a
2096 result of optimize_skip. Since this code was redundant with
2097 fill_eager_delay_slots anyways, it was just deleted. */
2100 /* If this instruction could throw an exception which is
2101 caught in the same function, then it's not safe to fill
2102 the delay slot with an instruction from beyond this
2103 point. For example, consider:
2105 int i = 2;
2107 try {
2108 f();
2109 i = 3;
2110 } catch (...) {}
2112 return i;
2114 Even though `i' is a local variable, we must be sure not
2115 to put `i = 3' in the delay slot if `f' might throw an
2116 exception.
2118 Presumably, we should also check to see if we could get
2119 back to this function via `setjmp'. */
2122 {
2136 {
2139 /* This must be an INSN or CALL_INSN. */
2142 /* Stand-alone USE and CLOBBER are just for flow. */
2146 /* If this already has filled delay slots, get the insn needing
2147 the delay slots. */
2150 else
2153 /* Stop our search when seeing a jump. */
2157 /* See if we have a resource problem before we try to split. */
2167 {
2177 }
2182 /* Ensure we don't put insns between the setting of cc and the
2183 comparison by moving a setting of cc into an earlier delay
2184 slot since these insns could clobber the condition code. */
2187 /* If this is a call, we might not get here. */
2190 }
2192 /* If there are slots left to fill and our search was stopped by an
2193 unconditional branch, try the insn at the branch target. We can
2194 redirect the branch if it works.
2196 Don't do this if the insn at the branch target is a branch. */
2198 && trial
2213 {
2214 /* See comment in relax_delay_slots about necessity of using
2215 next_real_insn here. */
2220 else
2224 {
2227 slots_filled++;
2229 new_label);
2230 }
2231 }
2232 }
2234 /* If this is an unconditional jump, then try to get insns from the
2235 target of the jump. */
2254 }
2255 }
2256 \f
2257 /* Follow any unconditional jump at LABEL, for the purpose of redirecting JUMP;
2258 return the ultimate label reached by any such chain of jumps.
2259 Return a suitable return rtx if the chain ultimately leads to a
2260 return instruction.
2261 If LABEL is not followed by a jump, return LABEL.
2262 If the chain loops or we can't find end, return LABEL,
2263 since that tells caller to avoid changing the insn.
2264 If the returned label is obtained by following a crossing jump,
2265 set *CROSSING to true, otherwise set it to false. */
2267 static rtx
2269 {
2289 depth++)
2290 {
2293 /* If we have found a cycle, make the insn jump to itself. */
2297 /* Cannot follow returns and cannot look through tablejumps. */
2311 }
2315 }
2317 /* Try to find insns to place in delay slots.
2319 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
2320 or is an unconditional branch if CONDITION is const_true_rtx.
2321 *PSLOTS_FILLED is updated with the number of slots that we have filled.
2323 THREAD is a flow-of-control, either the insns to be executed if the
2324 branch is true or if the branch is false, THREAD_IF_TRUE says which.
2326 OPPOSITE_THREAD is the thread in the opposite direction. It is used
2327 to see if any potential delay slot insns set things needed there.
2329 LIKELY is nonzero if it is extremely likely that the branch will be
2330 taken and THREAD_IF_TRUE is set. This is used for the branch at the
2331 end of a loop back up to the top.
2333 OWN_THREAD and OWN_OPPOSITE_THREAD are true if we are the only user of the
2334 thread. I.e., it is the fallthrough code of our jump or the target of the
2335 jump when we are the only jump going there.
2337 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
2338 case, we can only take insns from the head of the thread for our delay
2339 slot. We then adjust the jump to point after the insns we have taken. */
2341 static void
2346 {
2347 rtx new_thread;
2354 /* Validate our arguments. */
2360 /* If our thread is the end of subroutine, we can't get any delay
2361 insns from that. */
2367 /* If this is an unconditional branch, nothing is needed at the
2368 opposite thread. Otherwise, compute what is needed there. */
2371 else
2374 /* If the insn at THREAD can be split, do it here to avoid having to
2375 update THREAD and NEW_THREAD if it is done in the loop below. Also
2376 initialize NEW_THREAD. */
2380 /* Scan insns at THREAD. We are looking for an insn that can be removed
2381 from THREAD (it neither sets nor references resources that were set
2382 ahead of it and it doesn't set anything needs by the insns ahead of
2383 it) and that either can be placed in an annulling insn or aren't
2384 needed at OPPOSITE_THREAD. */
2389 /* If we do not own this thread, we must stop as soon as we find
2390 something that we can't put in a delay slot, since all we can do
2391 is branch into THREAD at a later point. Therefore, labels stop
2392 the search if this is not the `true' thread. */
2397 {
2400 /* If we have passed a label, we no longer own this thread. */
2402 {
2405 }
2411 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
2412 don't separate or copy insns that set and use CC0. */
2419 {
2422 /* If TRIAL is redundant with some insn before INSN, we don't
2423 actually need to add it to the delay list; we can merely pretend
2424 we did. */
2426 {
2429 {
2432 {
2436 }
2439 }
2440 else
2441 {
2444 }
2447 }
2449 /* There are two ways we can win: If TRIAL doesn't set anything
2450 needed at the opposite thread and can't trap, or if it can
2451 go into an annulled delay slot. But we want neither to copy
2452 nor to speculate frame-related insns. */
2459 {
2469 }
2473 {
2486 {
2490 winner:
2495 /* If we own this thread, delete the insn. If this is the
2496 destination of a branch, show that a basic block status
2497 may have been updated. In any case, mark the new
2498 starting point of this thread. */
2500 {
2501 rtx note;
2505 {
2509 }
2511 /* We are moving this insn, not deleting it. We must
2512 temporarily increment the use count on any referenced
2513 label lest it be deleted by delete_related_insns. */
2519 {
2520 /* REG_LABEL_OPERAND could be
2521 NOTE_INSN_DELETED_LABEL too. */
2524 else
2527 }
2538 {
2539 /* REG_LABEL_OPERAND could be
2540 NOTE_INSN_DELETED_LABEL too. */
2543 else
2546 }
2549 }
2550 else
2560 {
2561 /* Even though we have filled all the slots, we
2562 may be branching to a location that has a
2563 redundant insn. Skip any if so. */
2570 && (prior_insn
2573 {
2574 /* We know we do not own the thread, so no need
2575 to call update_block and delete_insn. */
2578 new_thread
2580 }
2582 }
2585 }
2586 }
2587 }
2589 /* This insn can't go into a delay slot. */
2594 /* Ensure we don't put insns between the setting of cc and the comparison
2595 by moving a setting of cc into an earlier delay slot since these insns
2596 could clobber the condition code. */
2599 /* If this insn is a register-register copy and the next insn has
2600 a use of our destination, change it to use our source. That way,
2601 it will become a candidate for our delay slot the next time
2602 through this loop. This case occurs commonly in loops that
2603 scan a list.
2605 We could check for more complex cases than those tested below,
2606 but it doesn't seem worth it. It might also be a good idea to try
2607 to swap the two insns. That might do better.
2609 We can't do this if the next insn modifies our destination, because
2610 that would make the replacement into the insn invalid. We also can't
2611 do this if it modifies our source, because it might be an earlyclobber
2612 operand. This latter test also prevents updating the contents of
2613 a PRE_INC. We also can't do this if there's overlap of source and
2614 destination. Overlap may happen for larger-than-register-size modes. */
2620 {
2630 }
2631 }
2633 /* If we stopped on a branch insn that has delay slots, see if we can
2634 steal some of the insns in those slots. */
2638 {
2640 /* If this is the `true' thread, we will want to follow the jump,
2641 so we can only do this if we have taken everything up to here. */
2643 {
2649 /* If we owned the thread and are told that it branched
2650 elsewhere, make sure we own the thread at the new location. */
2653 }
2659 }
2661 /* If we haven't found anything for this delay slot and it is very
2662 likely that the branch will be taken, see if the insn at our target
2663 increments or decrements a register with an increment that does not
2664 depend on the destination register. If so, try to place the opposite
2665 arithmetic insn after the jump insn and put the arithmetic insn in the
2666 delay slot. If we can't do this, return. */
2673 {
2675 rtx dest;
2676 rtx src;
2678 /* We know "new_thread" is an insn due to NONJUMP_INSN_P (new_thread)
2679 above. */
2696 {
2698 rtx new_arith;
2701 /* If this is a constant adjustment, use the same code with
2702 the negated constant. Otherwise, reverse the sense of the
2703 arithmetic. */
2707 else
2716 {
2719 }
2722 {
2725 {
2729 }
2731 }
2732 else
2741 }
2742 }
2747 /* If we are to branch into the middle of this thread, find an appropriate
2748 label or make a new one if none, and redirect INSN to it. If we hit the
2749 end of the function, use the end-of-function label. */
2751 {
2752 rtx label;
2768 else
2773 {
2777 }
2778 }
2779 }
2780 \f
2781 /* Make another attempt to find insns to place in delay slots.
2783 We previously looked for insns located in front of the delay insn
2784 and, for non-jump delay insns, located behind the delay insn.
2786 Here only try to schedule jump insns and try to move insns from either
2787 the target or the following insns into the delay slot. If annulling is
2788 supported, we will be likely to do this. Otherwise, we can do this only
2789 if safe. */
2791 static void
2793 {
2799 {
2800 rtx condition;
2817 /* Some machine description have defined instructions to have
2818 delay slots only in certain circumstances which may depend on
2819 nearby insns (which change due to reorg's actions).
2821 For example, the PA port normally has delay slots for unconditional
2822 jumps.
2824 However, the PA port claims such jumps do not have a delay slot
2825 if they are immediate successors of certain CALL_INSNs. This
2826 allows the port to favor filling the delay slot of the call with
2827 the unconditional jump. */
2838 /* Get the next active fallthrough and target insns and see if we own
2839 them. Then see whether the branch is likely true. We don't need
2840 to do a lot of this for unconditional branches. */
2846 {
2850 }
2851 else
2852 {
2856 }
2858 /* If this insn is expected to branch, first try to get insns from our
2859 target, then our fallthrough insns. If it is not expected to branch,
2860 try the other order. */
2863 {
2866 own_target,
2870 {
2871 /* Even though we didn't find anything for delay slots,
2872 we might have found a redundant insn which we deleted
2873 from the thread that was filled. So we have to recompute
2874 the next insn at the target. */
2882 }
2883 }
2884 else
2885 {
2895 }
2905 }
2906 }
2907 \f
2910 /* Recursively delete prior insns that compute the value (used only by INSN
2911 which the caller is deleting) stored in the register mentioned by NOTE
2912 which is a REG_DEAD note associated with INSN. */
2914 static void
2916 {
2924 {
2927 /* If we reach a CALL which is not calling a const function
2928 or the callee pops the arguments, then give up. */
2934 /* If we reach a SEQUENCE, it is too complex to try to
2935 do anything with it, so give up. We can be run during
2936 and after reorg, so SEQUENCE rtl can legitimately show
2937 up here. */
2943 /* reorg creates USEs that look like this. We leave them
2944 alone because reorg needs them for its own purposes. */
2948 {
2953 {
2954 /* If we find a SET of something else, we can't
2955 delete the insn. */
2960 {
2966 }
2970 }
2973 {
2983 /* We may have a multi-word hard register and some, but not
2984 all, of the words of the register are needed in subsequent
2985 insns. Write REG_UNUSED notes for those parts that were not
2986 needed. */
2989 {
3000 }
3001 }
3004 }
3006 /* If PAT references the register that dies here, it is an
3007 additional use. Hence any prior SET isn't dead. However, this
3008 insn becomes the new place for the REG_DEAD note. */
3010 {
3014 }
3015 }
3016 }
3018 /* Delete INSN and recursively delete insns that compute values used only
3019 by INSN. This uses the REG_DEAD notes computed during flow analysis.
3021 Look at all our REG_DEAD notes. If a previous insn does nothing other
3022 than set a register that dies in this insn, we can delete that insn
3023 as well.
3025 On machines with CC0, if CC0 is used in this insn, we may be able to
3026 delete the insn that set it. */
3028 static void
3030 {
3034 {
3036 /* We assume that at this stage
3037 CC's are always set explicitly
3038 and always immediately before the jump that
3039 will use them. So if the previous insn
3040 exists to set the CC's, delete it
3041 (unless it performs auto-increments, etc.). */
3044 {
3048 else
3049 /* Otherwise, show that cc0 won't be used. */
3051 }
3052 }
3055 {
3059 /* Verify that the REG_NOTE is legitimate. */
3064 }
3067 }
3069 /* If all INSN does is set the pc, delete it,
3070 and delete the insn that set the condition codes for it
3071 if that's what the previous thing was. */
3073 static void
3075 {
3080 }
3084 {
3087 {
3093 }
3095 }
3097 /* Return TRUE if there is a NOTE_INSN_SWITCH_TEXT_SECTIONS note in between
3098 BEG and END. */
3100 static bool
3102 {
3108 }
3110 \f
3111 /* Once we have tried two ways to fill a delay slot, make a pass over the
3112 code to try to improve the results and to do such things as more jump
3113 threading. */
3115 static void
3117 {
3120 rtx trial;
3122 rtx target_label;
3124 /* Look at every JUMP_INSN and see if we can improve it. */
3126 {
3132 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3133 the next insn, or jumps to a label that is not the last of a
3134 group of consecutive labels. */
3138 {
3140 target_label
3150 {
3153 }
3156 {
3160 }
3162 /* See if this jump conditionally branches around an unconditional
3163 jump. If so, invert this jump and point it to the target of the
3164 second jump. Check if it's possible on the target. */
3167 && target_label
3172 {
3175 /* Be careful how we do this to avoid deleting code or
3176 labels that are momentarily dead. See similar optimization
3177 in jump.c.
3179 We also need to ensure we properly handle the case when
3180 invert_jump fails. */
3187 {
3190 }
3199 }
3200 }
3202 /* If this is an unconditional jump and the previous insn is a
3203 conditional jump, try reversing the condition of the previous
3204 insn and swapping our targets. The next pass might be able to
3205 fill the slots.
3207 Don't do this if we expect the conditional branch to be true, because
3208 we would then be making the more common case longer. */
3215 {
3221 }
3223 /* Now look only at cases where we have a filled delay slot. */
3230 /* See if the first insn in the delay slot is redundant with some
3231 previous insn. Remove it from the delay slot if so; then set up
3232 to reprocess this insn. */
3234 {
3239 }
3241 /* See if we have a RETURN insn with a filled delay slot followed
3242 by a RETURN insn with an unfilled a delay slot. If so, we can delete
3243 the first RETURN (but not its delay insn). This gives the same
3244 effect in fewer instructions.
3246 Only do so if optimizing for size since this results in slower, but
3247 smaller code. */
3250 && next
3253 {
3257 /* Delete the RETURN and just execute the delay list insns.
3259 We do this by deleting the INSN containing the SEQUENCE, then
3260 re-emitting the insns separately, and then deleting the RETURN.
3261 This allows the count of the jump target to be properly
3262 decremented.
3264 Note that we need to change the INSN_UID of the re-emitted insns
3265 since it is used to hash the insns for mark_target_live_regs and
3266 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3268 Clear the from target bit, since these insns are no longer
3269 in delay slots. */
3282 }
3284 /* Now look only at the cases where we have a filled JUMP_INSN. */
3295 /* If this jump goes to another unconditional jump, thread it, but
3296 don't convert a jump into a RETURN here. */
3298 delay_jump_insn,
3305 {
3310 }
3312 /* If the first insn at TARGET_LABEL is redundant with a previous
3313 insn, redirect the jump to the following insn and process again.
3314 We use next_real_insn instead of next_active_insn so we
3315 don't skip USE-markers, or we'll end up with incorrect
3316 liveness info. */
3321 {
3322 /* Figure out where to emit the special USE insn so we don't
3323 later incorrectly compute register live/death info. */
3329 {
3330 /* Insert the special USE insn and update dataflow info.
3331 We know "trial" is an insn here as it is the output of
3332 next_real_insn () above. */
3335 /* Now emit a label before the special USE insn, and
3336 redirect our jump to the new label. */
3341 }
3342 }
3344 /* Similarly, if it is an unconditional jump with one insn in its
3345 delay list and that insn is redundant, thread the jump. */
3353 {
3361 {
3366 }
3367 }
3369 /* See if we have a simple (conditional) jump that is useless. */
3374 /* If the last insn in the delay slot sets CC0 for some insn,
3375 various code assumes that it is in a delay slot. We could
3376 put it back where it belonged and delete the register notes,
3377 but it doesn't seem worthwhile in this uncommon case. */
3378 && (!HAVE_cc0
3381 {
3385 /* All this insn does is execute its delay list and jump to the
3386 following insn. So delete the jump and just execute the delay
3387 list insns.
3389 We do this by deleting the INSN containing the SEQUENCE, then
3390 re-emitting the insns separately, and then deleting the jump.
3391 This allows the count of the jump target to be properly
3392 decremented.
3394 Note that we need to change the INSN_UID of the re-emitted insns
3395 since it is used to hash the insns for mark_target_live_regs and
3396 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3398 Clear the from target bit, since these insns are no longer
3399 in delay slots. */
3412 }
3414 /* See if this is an unconditional jump around a single insn which is
3415 identical to the one in its delay slot. In this case, we can just
3416 delete the branch and the insn in its delay slot. */
3422 {
3425 }
3427 /* See if this jump (with its delay slots) conditionally branches
3428 around an unconditional jump (without delay slots). If so, invert
3429 this jump and point it to the target of the second jump. We cannot
3430 do this for annulled jumps, though. Again, don't convert a jump to
3431 a RETURN here. */
3438 {
3445 /* find_end_label can generate a new label. Check this first. */
3450 {
3451 /* Be careful how we do this to avoid deleting code or labels
3452 that are momentarily dead. See similar optimization in
3453 jump.c */
3458 {
3461 /* Must update the INSN_FROM_TARGET_P bits now that
3462 the branch is reversed, so that mark_target_live_regs
3463 will handle the delay slot insn correctly. */
3465 {
3468 }
3472 }
3477 }
3478 }
3480 /* If we own the thread opposite the way this insn branches, see if we
3481 can merge its delay slots with following insns. */
3490 /* If we get here, we haven't deleted INSN. But we may have deleted
3491 NEXT, so recompute it. */
3493 }
3494 }
3495 \f
3497 /* Look for filled jumps to the end of function label. We can try to convert
3498 them into RETURN insns if the insns in the delay slot are valid for the
3499 RETURN as well. */
3501 static void
3503 {
3510 /* See if there is a RETURN insn in the function other than the one we
3511 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
3512 into a RETURN to jump to it. */
3515 {
3519 else
3522 }
3524 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
3525 was equal to END_OF_FUNCTION_LABEL. */
3531 /* Clear the list of insns to fill so we can use it. */
3535 {
3539 /* Only look at filled JUMP_INSNs that go to the end of function
3540 label. */
3553 {
3556 }
3558 {
3561 }
3562 else
3567 /* If we can't make the jump into a RETURN, try to redirect it to the best
3568 RETURN and go on to the next insn. */
3570 {
3571 /* Make sure redirecting the jump will not invalidate the delay
3572 slot insns. */
3576 }
3578 /* See if this RETURN can accept the insns current in its delay slot.
3579 It can if it has more or an equal number of slots and the contents
3580 of each is valid. */
3585 {
3588 #if ANNUL_IFFALSE_SLOTS
3593 #endif
3594 #if ANNUL_IFTRUE_SLOTS
3599 #endif
3603 }
3604 else
3610 /* We have to do something with this insn. If it is an unconditional
3611 RETURN, delete the SEQUENCE and output the individual insns,
3612 followed by the RETURN. Then set things up so we try to find
3613 insns for its delay slots, if it needs some. */
3615 {
3627 }
3628 else
3629 /* It is probably more efficient to keep this with its current
3630 delay slot as a branch to a RETURN. */
3632 }
3634 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
3635 new delay slots we have created. */
3644 }
3645 \f
3646 /* Try to find insns to place in delay slots. */
3648 static void
3650 {
3655 /* If the current function has no insns other than the prologue and
3656 epilogue, then do not try to fill any delay slots. */
3660 /* Find the highest INSN_UID and allocate and initialize our map from
3661 INSN_UID's to position in code. */
3663 {
3669 }
3675 /* Initialize the list of insns that need filling. */
3677 {
3680 }
3683 {
3684 rtx target;
3686 /* Skip vector tables. We can't get attributes for them. */
3697 /* Ensure all jumps go to the last of a set of consecutive labels. */
3704 }
3708 /* Show we haven't computed an end-of-function label yet. */
3711 /* Initialize the statistics for this function. */
3715 /* Now do the delay slot filling. Try everything twice in case earlier
3716 changes make more slots fillable. */
3720 reorg_pass_number++)
3721 {
3727 }
3729 /* If we made an end of function label, indicate that it is now
3730 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
3731 If it is now unused, delete it. */
3745 /* Delete any USE insns made by update_block; subsequent passes don't need
3746 them or know how to deal with them. */
3748 {
3754 }
3758 /* It is not clear why the line below is needed, but it does seem to be. */
3762 {
3769 reorg_pass_number++)
3770 {
3773 {
3782 {
3788 }
3790 }
3791 }
3795 {
3800 {
3802 {
3803 rtx control;
3810 else
3812 }
3815 }
3816 }
3820 {
3822 {
3827 }
3828 }
3832 {
3836 {
3838 {
3843 }
3844 }
3846 }
3849 }
3852 {
3855 }
3860 }
3861 \f
3862 /* Run delay slot optimization. */
3863 static unsigned int
3865 {
3870 }
3875 {
3885 };
3888 {
3892 {}
3894 /* opt_pass methods: */
3897 {
3899 }
3903 bool
3905 {
3906 /* At -O0 dataflow info isn't updated after RA. */
3911 }
3915 rtl_opt_pass *
3917 {
3919 }
3921 /* Machine dependent reorg pass. */
3926 {
3936 };
3939 {
3943 {}
3945 /* opt_pass methods: */
3947 {
3949 }
3952 {
3955 }
3961 rtl_opt_pass *
3963 {
3965 }