gcc/emit-rtl.c

   1 /* Emit RTL for the GNU C-Compiler expander.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000 Free Software Foundation, Inc.
   4
   5 This file is part of GNU CC.
   6
   7 GNU CC is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 GNU CC is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GNU CC; see the file COPYING.  If not, write to
  19 the Free Software Foundation, 59 Temple Place - Suite 330,
  20 Boston, MA 02111-1307, USA.  */
  21
  22
  23 /* Middle-to-low level generation of rtx code and insns.
  24
  25    This file contains the functions `gen_rtx', `gen_reg_rtx'
  26    and `gen_label_rtx' that are the usual ways of creating rtl
  27    expressions for most purposes.
  28
  29    It also has the functions for creating insns and linking
  30    them in the doubly-linked chain.
  31
  32    The patterns of the insns are created by machine-dependent
  33    routines in insn-emit.c, which is generated automatically from
  34    the machine description.  These routines use `gen_rtx' to make
  35    the individual rtx's of the pattern; what is machine dependent
  36    is the kind of rtx's they make and what arguments they use.  */
  37
  38 #include "config.h"
  39 #include "system.h"
  40 #include "toplev.h"
  41 #include "rtl.h"
  42 #include "tree.h"
  43 #include "tm_p.h"
  44 #include "flags.h"
  45 #include "function.h"
  46 #include "expr.h"
  47 #include "regs.h"
  48 #include "hard-reg-set.h"
  49 #include "insn-config.h"
  50 #include "recog.h"
  51 #include "real.h"
  52 #include "obstack.h"
  53 #include "bitmap.h"
  54 #include "basic-block.h"
  55 #include "ggc.h"
  56
  57 /* Commonly used modes.  */
  58
  59 enum machine_mode byte_mode;    /* Mode whose width is BITS_PER_UNIT.  */
  60 enum machine_mode word_mode;    /* Mode whose width is BITS_PER_WORD.  */
  61 enum machine_mode double_mode;  /* Mode whose width is DOUBLE_TYPE_SIZE.  */
  62 enum machine_mode ptr_mode;     /* Mode whose width is POINTER_SIZE.  */
  63
  64
  65 /* This is *not* reset after each function.  It gives each CODE_LABEL
  66    in the entire compilation a unique label number.  */
  67
  68 static int label_num = 1;
  69
  70 /* Highest label number in current function.
  71    Zero means use the value of label_num instead.
  72    This is nonzero only when belatedly compiling an inline function.  */
  73
  74 static int last_label_num;
  75
  76 /* Value label_num had when set_new_first_and_last_label_number was called.
  77    If label_num has not changed since then, last_label_num is valid.  */
  78
  79 static int base_label_num;
  80
  81 /* Nonzero means do not generate NOTEs for source line numbers.  */
  82
  83 static int no_line_numbers;
  84
  85 /* Commonly used rtx's, so that we only need space for one copy.
  86    These are initialized once for the entire compilation.
  87    All of these except perhaps the floating-point CONST_DOUBLEs
  88    are unique; no other rtx-object will be equal to any of these.  */
  89
  90 rtx global_rtl[GR_MAX];
  91
  92 /* We record floating-point CONST_DOUBLEs in each floating-point mode for
  93    the values of 0, 1, and 2.  For the integer entries and VOIDmode, we
  94    record a copy of const[012]_rtx.  */
  95
  96 rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE];
  97
  98 rtx const_true_rtx;
  99
 100 REAL_VALUE_TYPE dconst0;
 101 REAL_VALUE_TYPE dconst1;
 102 REAL_VALUE_TYPE dconst2;
 103 REAL_VALUE_TYPE dconstm1;
 104
 105 /* All references to the following fixed hard registers go through
 106    these unique rtl objects.  On machines where the frame-pointer and
 107    arg-pointer are the same register, they use the same unique object.
 108
 109    After register allocation, other rtl objects which used to be pseudo-regs
 110    may be clobbered to refer to the frame-pointer register.
 111    But references that were originally to the frame-pointer can be
 112    distinguished from the others because they contain frame_pointer_rtx.
 113
 114    When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little
 115    tricky: until register elimination has taken place hard_frame_pointer_rtx
 116    should be used if it is being set, and frame_pointer_rtx otherwise.  After
 117    register elimination hard_frame_pointer_rtx should always be used.
 118    On machines where the two registers are same (most) then these are the
 119    same.
 120
 121    In an inline procedure, the stack and frame pointer rtxs may not be
 122    used for anything else.  */
 123 rtx struct_value_rtx;           /* (REG:Pmode STRUCT_VALUE_REGNUM) */
 124 rtx struct_value_incoming_rtx;  /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */
 125 rtx static_chain_rtx;           /* (REG:Pmode STATIC_CHAIN_REGNUM) */
 126 rtx static_chain_incoming_rtx;  /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */
 127 rtx pic_offset_table_rtx;       /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */
 128
 129 /* This is used to implement __builtin_return_address for some machines.
 130    See for instance the MIPS port.  */
 131 rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */
 132
 133 /* We make one copy of (const_int C) where C is in
 134    [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT]
 135    to save space during the compilation and simplify comparisons of
 136    integers.  */
 137
 138 rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1];
 139
 140 /* start_sequence and gen_sequence can make a lot of rtx expressions which are
 141    shortly thrown away.  We use two mechanisms to prevent this waste:
 142
 143    For sizes up to 5 elements, we keep a SEQUENCE and its associated
 144    rtvec for use by gen_sequence.  One entry for each size is
 145    sufficient because most cases are calls to gen_sequence followed by
 146    immediately emitting the SEQUENCE.  Reuse is safe since emitting a
 147    sequence is destructive on the insn in it anyway and hence can't be
 148    redone.
 149
 150    We do not bother to save this cached data over nested function calls.
 151    Instead, we just reinitialize them.  */
 152
 153 #define SEQUENCE_RESULT_SIZE 5
 154
 155 static rtx sequence_result[SEQUENCE_RESULT_SIZE];
 156
 157 /* During RTL generation, we also keep a list of free INSN rtl codes.  */
 158 static rtx free_insn;
 159
 160 #define first_insn (cfun->emit->x_first_insn)
 161 #define last_insn (cfun->emit->x_last_insn)
 162 #define cur_insn_uid (cfun->emit->x_cur_insn_uid)
 163 #define last_linenum (cfun->emit->x_last_linenum)
 164 #define last_filename (cfun->emit->x_last_filename)
 165 #define first_label_num (cfun->emit->x_first_label_num)
 166
 167 /* This is where the pointer to the obstack being used for RTL is stored.  */
 168 extern struct obstack *rtl_obstack;
 169
 170 static rtx make_jump_insn_raw           PARAMS ((rtx));
 171 static rtx make_call_insn_raw           PARAMS ((rtx));
 172 static rtx find_line_note               PARAMS ((rtx));
 173 static void mark_sequence_stack         PARAMS ((struct sequence_stack *));
 174 static void unshare_all_rtl_1           PARAMS ((rtx));
 175 \f
 176 /* There are some RTL codes that require special attention; the generation
 177    functions do the raw handling.  If you add to this list, modify
 178    special_rtx in gengenrtl.c as well.  */
 179
 180 rtx
 181 gen_rtx_CONST_INT (mode, arg)
 182      enum machine_mode mode;
 183      HOST_WIDE_INT arg;
 184 {
 185   if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT)
 186     return const_int_rtx[arg + MAX_SAVED_CONST_INT];
 187
 188 #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1
 189   if (const_true_rtx && arg == STORE_FLAG_VALUE)
 190     return const_true_rtx;
 191 #endif
 192
 193   return gen_rtx_raw_CONST_INT (mode, arg);
 194 }
 195
 196 /* CONST_DOUBLEs needs special handling because its length is known
 197    only at run-time.  */
 198 rtx
 199 gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2)
 200      enum machine_mode mode;
 201      rtx arg0;
 202      HOST_WIDE_INT arg1, arg2;
 203 {
 204   rtx r = rtx_alloc (CONST_DOUBLE);
 205   int i;
 206
 207   PUT_MODE (r, mode);
 208   XEXP (r, 0) = arg0;
 209   X0EXP (r, 1) = NULL_RTX;
 210   XWINT (r, 2) = arg1;
 211   XWINT (r, 3) = arg2;
 212
 213   for (i = GET_RTX_LENGTH (CONST_DOUBLE) - 1; i > 3; --i)
 214     XWINT (r, i) = 0;
 215
 216   return r;
 217 }
 218
 219 rtx
 220 gen_rtx_REG (mode, regno)
 221      enum machine_mode mode;
 222      int regno;
 223 {
 224   /* In case the MD file explicitly references the frame pointer, have
 225      all such references point to the same frame pointer.  This is
 226      used during frame pointer elimination to distinguish the explicit
 227      references to these registers from pseudos that happened to be
 228      assigned to them.
 229
 230      If we have eliminated the frame pointer or arg pointer, we will
 231      be using it as a normal register, for example as a spill
 232      register.  In such cases, we might be accessing it in a mode that
 233      is not Pmode and therefore cannot use the pre-allocated rtx.
 234
 235      Also don't do this when we are making new REGs in reload, since
 236      we don't want to get confused with the real pointers.  */
 237
 238   if (mode == Pmode && !reload_in_progress)
 239     {
 240       if (regno == FRAME_POINTER_REGNUM)
 241         return frame_pointer_rtx;
 242 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
 243       if (regno == HARD_FRAME_POINTER_REGNUM)
 244         return hard_frame_pointer_rtx;
 245 #endif
 246 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
 247       if (regno == ARG_POINTER_REGNUM)
 248         return arg_pointer_rtx;
 249 #endif
 250 #ifdef RETURN_ADDRESS_POINTER_REGNUM
 251       if (regno == RETURN_ADDRESS_POINTER_REGNUM)
 252         return return_address_pointer_rtx;
 253 #endif
 254       if (regno == STACK_POINTER_REGNUM)
 255         return stack_pointer_rtx;
 256     }
 257
 258   return gen_rtx_raw_REG (mode, regno);
 259 }
 260
 261 rtx
 262 gen_rtx_MEM (mode, addr)
 263      enum machine_mode mode;
 264      rtx addr;
 265 {
 266   rtx rt = gen_rtx_raw_MEM (mode, addr);
 267
 268   /* This field is not cleared by the mere allocation of the rtx, so
 269      we clear it here.  */
 270   MEM_ALIAS_SET (rt) = 0;
 271
 272   return rt;
 273 }
 274 \f
 275 /* rtx gen_rtx (code, mode, [element1, ..., elementn])
 276 **
 277 **          This routine generates an RTX of the size specified by
 278 **      <code>, which is an RTX code.   The RTX structure is initialized
 279 **      from the arguments <element1> through <elementn>, which are
 280 **      interpreted according to the specific RTX type's format.   The
 281 **      special machine mode associated with the rtx (if any) is specified
 282 **      in <mode>.
 283 **
 284 **          gen_rtx can be invoked in a way which resembles the lisp-like
 285 **      rtx it will generate.   For example, the following rtx structure:
 286 **
 287 **            (plus:QI (mem:QI (reg:SI 1))
 288 **                     (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3))))
 289 **
 290 **              ...would be generated by the following C code:
 291 **
 292 **              gen_rtx (PLUS, QImode,
 293 **                  gen_rtx (MEM, QImode,
 294 **                      gen_rtx (REG, SImode, 1)),
 295 **                  gen_rtx (MEM, QImode,
 296 **                      gen_rtx (PLUS, SImode,
 297 **                          gen_rtx (REG, SImode, 2),
 298 **                          gen_rtx (REG, SImode, 3)))),
 299 */
 300
 301 /*VARARGS2*/
 302 rtx
 303 gen_rtx VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
 304 {
 305 #ifndef ANSI_PROTOTYPES
 306   enum rtx_code code;
 307   enum machine_mode mode;
 308 #endif
 309   va_list p;
 310   register int i;               /* Array indices...                     */
 311   register const char *fmt;     /* Current rtx's format...              */
 312   register rtx rt_val;          /* RTX to return to caller...           */
 313
 314   VA_START (p, mode);
 315
 316 #ifndef ANSI_PROTOTYPES
 317   code = va_arg (p, enum rtx_code);
 318   mode = va_arg (p, enum machine_mode);
 319 #endif
 320
 321   switch (code)
 322     {
 323     case CONST_INT:
 324       rt_val = gen_rtx_CONST_INT (mode, va_arg (p, HOST_WIDE_INT));
 325       break;
 326
 327     case CONST_DOUBLE:
 328       {
 329         rtx arg0 = va_arg (p, rtx);
 330         HOST_WIDE_INT arg1 = va_arg (p, HOST_WIDE_INT);
 331         HOST_WIDE_INT arg2 = va_arg (p, HOST_WIDE_INT);
 332         rt_val = gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2);
 333       }
 334       break;
 335
 336     case REG:
 337       rt_val = gen_rtx_REG (mode, va_arg (p, int));
 338       break;
 339
 340     case MEM:
 341       rt_val = gen_rtx_MEM (mode, va_arg (p, rtx));
 342       break;
 343
 344     default:
 345       rt_val = rtx_alloc (code);        /* Allocate the storage space.  */
 346       rt_val->mode = mode;              /* Store the machine mode...  */
 347
 348       fmt = GET_RTX_FORMAT (code);      /* Find the right format...  */
 349       for (i = 0; i < GET_RTX_LENGTH (code); i++)
 350         {
 351           switch (*fmt++)
 352             {
 353             case '0':           /* Unused field.  */
 354               break;
 355
 356             case 'i':           /* An integer?  */
 357               XINT (rt_val, i) = va_arg (p, int);
 358               break;
 359
 360             case 'w':           /* A wide integer? */
 361               XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT);
 362               break;
 363
 364             case 's':           /* A string?  */
 365               XSTR (rt_val, i) = va_arg (p, char *);
 366               break;
 367
 368             case 'e':           /* An expression?  */
 369             case 'u':           /* An insn?  Same except when printing.  */
 370               XEXP (rt_val, i) = va_arg (p, rtx);
 371               break;
 372
 373             case 'E':           /* An RTX vector?  */
 374               XVEC (rt_val, i) = va_arg (p, rtvec);
 375               break;
 376
 377             case 'b':           /* A bitmap? */
 378               XBITMAP (rt_val, i) = va_arg (p, bitmap);
 379               break;
 380
 381             case 't':           /* A tree? */
 382               XTREE (rt_val, i) = va_arg (p, tree);
 383               break;
 384
 385             default:
 386               abort ();
 387             }
 388         }
 389       break;
 390     }
 391
 392   va_end (p);
 393   return rt_val;
 394 }
 395
 396 /* gen_rtvec (n, [rt1, ..., rtn])
 397 **
 398 **          This routine creates an rtvec and stores within it the
 399 **      pointers to rtx's which are its arguments.
 400 */
 401
 402 /*VARARGS1*/
 403 rtvec
 404 gen_rtvec VPARAMS ((int n, ...))
 405 {
 406 #ifndef ANSI_PROTOTYPES
 407   int n;
 408 #endif
 409   int i;
 410   va_list p;
 411   rtx *vector;
 412
 413   VA_START (p, n);
 414
 415 #ifndef ANSI_PROTOTYPES
 416   n = va_arg (p, int);
 417 #endif
 418
 419   if (n == 0)
 420     return NULL_RTVEC;          /* Don't allocate an empty rtvec...     */
 421
 422   vector = (rtx *) alloca (n * sizeof (rtx));
 423
 424   for (i = 0; i < n; i++)
 425     vector[i] = va_arg (p, rtx);
 426   va_end (p);
 427
 428   return gen_rtvec_v (n, vector);
 429 }
 430
 431 rtvec
 432 gen_rtvec_v (n, argp)
 433      int n;
 434      rtx *argp;
 435 {
 436   register int i;
 437   register rtvec rt_val;
 438
 439   if (n == 0)
 440     return NULL_RTVEC;          /* Don't allocate an empty rtvec...     */
 441
 442   rt_val = rtvec_alloc (n);     /* Allocate an rtvec...                 */
 443
 444   for (i = 0; i < n; i++)
 445     rt_val->elem[i] = *argp++;
 446
 447   return rt_val;
 448 }
 449
 450 \f
 451 /* Generate a REG rtx for a new pseudo register of mode MODE.
 452    This pseudo is assigned the next sequential register number.  */
 453
 454 rtx
 455 gen_reg_rtx (mode)
 456      enum machine_mode mode;
 457 {
 458   struct function *f = cfun;
 459   register rtx val;
 460
 461   /* Don't let anything called after initial flow analysis create new
 462      registers.  */
 463   if (no_new_pseudos)
 464     abort ();
 465
 466   if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
 467       || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
 468     {
 469       /* For complex modes, don't make a single pseudo.
 470          Instead, make a CONCAT of two pseudos.
 471          This allows noncontiguous allocation of the real and imaginary parts,
 472          which makes much better code.  Besides, allocating DCmode
 473          pseudos overstrains reload on some machines like the 386.  */
 474       rtx realpart, imagpart;
 475       int size = GET_MODE_UNIT_SIZE (mode);
 476       enum machine_mode partmode
 477         = mode_for_size (size * BITS_PER_UNIT,
 478                          (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
 479                           ? MODE_FLOAT : MODE_INT),
 480                          0);
 481
 482       realpart = gen_reg_rtx (partmode);
 483       imagpart = gen_reg_rtx (partmode);
 484       return gen_rtx_CONCAT (mode, realpart, imagpart);
 485     }
 486
 487   /* Make sure regno_pointer_flag and regno_reg_rtx are large
 488      enough to have an element for this pseudo reg number.  */
 489
 490   if (reg_rtx_no == f->emit->regno_pointer_flag_length)
 491     {
 492       int old_size = f->emit->regno_pointer_flag_length;
 493       rtx *new1;
 494       char *new;
 495       new = xrealloc (f->emit->regno_pointer_flag, old_size * 2);
 496       memset (new + old_size, 0, old_size);
 497       f->emit->regno_pointer_flag = new;
 498
 499       new = xrealloc (f->emit->regno_pointer_align, old_size * 2);
 500       memset (new + old_size, 0, old_size);
 501       f->emit->regno_pointer_align = new;
 502
 503       new1 = (rtx *) xrealloc (f->emit->x_regno_reg_rtx,
 504                                old_size * 2 * sizeof (rtx));
 505       memset (new1 + old_size, 0, old_size * sizeof (rtx));
 506       regno_reg_rtx = new1;
 507
 508       f->emit->regno_pointer_flag_length = old_size * 2;
 509     }
 510
 511   val = gen_rtx_raw_REG (mode, reg_rtx_no);
 512   regno_reg_rtx[reg_rtx_no++] = val;
 513   return val;
 514 }
 515
 516 /* Identify REG (which may be a CONCAT) as a user register.  */
 517
 518 void
 519 mark_user_reg (reg)
 520      rtx reg;
 521 {
 522   if (GET_CODE (reg) == CONCAT)
 523     {
 524       REG_USERVAR_P (XEXP (reg, 0)) = 1;
 525       REG_USERVAR_P (XEXP (reg, 1)) = 1;
 526     }
 527   else if (GET_CODE (reg) == REG)
 528     REG_USERVAR_P (reg) = 1;
 529   else
 530     abort ();
 531 }
 532
 533 /* Identify REG as a probable pointer register and show its alignment
 534    as ALIGN, if nonzero.  */
 535
 536 void
 537 mark_reg_pointer (reg, align)
 538      rtx reg;
 539      int align;
 540 {
 541   if (! REGNO_POINTER_FLAG (REGNO (reg)))
 542     {
 543       REGNO_POINTER_FLAG (REGNO (reg)) = 1;
 544
 545       if (align)
 546         REGNO_POINTER_ALIGN (REGNO (reg)) = align;
 547     }
 548   else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg)))
 549     /* We can no-longer be sure just how aligned this pointer is */
 550     REGNO_POINTER_ALIGN (REGNO (reg)) = align;
 551 }
 552
 553 /* Return 1 plus largest pseudo reg number used in the current function.  */
 554
 555 int
 556 max_reg_num ()
 557 {
 558   return reg_rtx_no;
 559 }
 560
 561 /* Return 1 + the largest label number used so far in the current function.  */
 562
 563 int
 564 max_label_num ()
 565 {
 566   if (last_label_num && label_num == base_label_num)
 567     return last_label_num;
 568   return label_num;
 569 }
 570
 571 /* Return first label number used in this function (if any were used).  */
 572
 573 int
 574 get_first_label_num ()
 575 {
 576   return first_label_num;
 577 }
 578 \f
 579 /* Return a value representing some low-order bits of X, where the number
 580    of low-order bits is given by MODE.  Note that no conversion is done
 581    between floating-point and fixed-point values, rather, the bit
 582    representation is returned.
 583
 584    This function handles the cases in common between gen_lowpart, below,
 585    and two variants in cse.c and combine.c.  These are the cases that can
 586    be safely handled at all points in the compilation.
 587
 588    If this is not a case we can handle, return 0.  */
 589
 590 rtx
 591 gen_lowpart_common (mode, x)
 592      enum machine_mode mode;
 593      register rtx x;
 594 {
 595   int word = 0;
 596
 597   if (GET_MODE (x) == mode)
 598     return x;
 599
 600   /* MODE must occupy no more words than the mode of X.  */
 601   if (GET_MODE (x) != VOIDmode
 602       && ((GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD
 603           > ((GET_MODE_SIZE (GET_MODE (x)) + (UNITS_PER_WORD - 1))
 604              / UNITS_PER_WORD)))
 605     return 0;
 606
 607   if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
 608     word = ((GET_MODE_SIZE (GET_MODE (x))
 609              - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
 610             / UNITS_PER_WORD);
 611
 612   if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
 613       && (GET_MODE_CLASS (mode) == MODE_INT
 614           || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT))
 615     {
 616       /* If we are getting the low-order part of something that has been
 617          sign- or zero-extended, we can either just use the object being
 618          extended or make a narrower extension.  If we want an even smaller
 619          piece than the size of the object being extended, call ourselves
 620          recursively.
 621
 622          This case is used mostly by combine and cse.  */
 623
 624       if (GET_MODE (XEXP (x, 0)) == mode)
 625         return XEXP (x, 0);
 626       else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
 627         return gen_lowpart_common (mode, XEXP (x, 0));
 628       else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x)))
 629         return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0));
 630     }
 631   else if (GET_CODE (x) == SUBREG
 632            && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
 633                || GET_MODE_SIZE (mode) == GET_MODE_UNIT_SIZE (GET_MODE (x))))
 634     return (GET_MODE (SUBREG_REG (x)) == mode && SUBREG_WORD (x) == 0
 635             ? SUBREG_REG (x)
 636             : gen_rtx_SUBREG (mode, SUBREG_REG (x), SUBREG_WORD (x) + word));
 637   else if (GET_CODE (x) == REG)
 638     {
 639       /* Let the backend decide how many registers to skip.  This is needed
 640          in particular for Sparc64 where fp regs are smaller than a word.  */
 641       /* ??? Note that subregs are now ambiguous, in that those against
 642          pseudos are sized by the Word Size, while those against hard
 643          regs are sized by the underlying register size.  Better would be
 644          to always interpret the subreg offset parameter as bytes or bits.  */
 645
 646       if (WORDS_BIG_ENDIAN && REGNO (x) < FIRST_PSEUDO_REGISTER)
 647         word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x))
 648                 - HARD_REGNO_NREGS (REGNO (x), mode));
 649
 650       /* If the register is not valid for MODE, return 0.  If we don't
 651          do this, there is no way to fix up the resulting REG later.
 652          But we do do this if the current REG is not valid for its
 653          mode.  This latter is a kludge, but is required due to the
 654          way that parameters are passed on some machines, most
 655          notably Sparc.  */
 656       if (REGNO (x) < FIRST_PSEUDO_REGISTER
 657           && ! HARD_REGNO_MODE_OK (REGNO (x) + word, mode)
 658           && HARD_REGNO_MODE_OK (REGNO (x), GET_MODE (x)))
 659         return 0;
 660       else if (REGNO (x) < FIRST_PSEUDO_REGISTER
 661                /* integrate.c can't handle parts of a return value register. */
 662                && (! REG_FUNCTION_VALUE_P (x)
 663                    || ! rtx_equal_function_value_matters)
 664 #ifdef CLASS_CANNOT_CHANGE_SIZE
 665                && ! (GET_MODE_SIZE (mode) != GET_MODE_SIZE (GET_MODE (x))
 666                      && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_INT
 667                      && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_FLOAT
 668                      && (TEST_HARD_REG_BIT
 669                          (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
 670                           REGNO (x))))
 671 #endif
 672                /* We want to keep the stack, frame, and arg pointers
 673                   special.  */
 674                && x != frame_pointer_rtx
 675 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
 676                && x != arg_pointer_rtx
 677 #endif
 678                && x != stack_pointer_rtx)
 679         return gen_rtx_REG (mode, REGNO (x) + word);
 680       else
 681         return gen_rtx_SUBREG (mode, x, word);
 682     }
 683   /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits
 684      from the low-order part of the constant.  */
 685   else if ((GET_MODE_CLASS (mode) == MODE_INT
 686             || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
 687            && GET_MODE (x) == VOIDmode
 688            && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
 689     {
 690       /* If MODE is twice the host word size, X is already the desired
 691          representation.  Otherwise, if MODE is wider than a word, we can't
 692          do this.  If MODE is exactly a word, return just one CONST_INT.
 693          If MODE is smaller than a word, clear the bits that don't belong
 694          in our mode, unless they and our sign bit are all one.  So we get
 695          either a reasonable negative value or a reasonable unsigned value
 696          for this mode.  */
 697
 698       if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT)
 699         return x;
 700       else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
 701         return 0;
 702       else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT)
 703         return (GET_CODE (x) == CONST_INT ? x
 704                 : GEN_INT (CONST_DOUBLE_LOW (x)));
 705       else
 706         {
 707           /* MODE must be narrower than HOST_BITS_PER_WIDE_INT.  */
 708           int width = GET_MODE_BITSIZE (mode);
 709           HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x)
 710                                : CONST_DOUBLE_LOW (x));
 711
 712           /* Sign extend to HOST_WIDE_INT.  */
 713           val = val << (HOST_BITS_PER_WIDE_INT - width) >> (HOST_BITS_PER_WIDE_INT - width);
 714
 715           return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x
 716                   : GEN_INT (val));
 717         }
 718     }
 719
 720   /* If X is an integral constant but we want it in floating-point, it
 721      must be the case that we have a union of an integer and a floating-point
 722      value.  If the machine-parameters allow it, simulate that union here
 723      and return the result.  The two-word and single-word cases are
 724      different.  */
 725
 726   else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
 727              && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
 728             || flag_pretend_float)
 729            && GET_MODE_CLASS (mode) == MODE_FLOAT
 730            && GET_MODE_SIZE (mode) == UNITS_PER_WORD
 731            && GET_CODE (x) == CONST_INT
 732            && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT)
 733 #ifdef REAL_ARITHMETIC
 734     {
 735       REAL_VALUE_TYPE r;
 736       HOST_WIDE_INT i;
 737
 738       i = INTVAL (x);
 739       r = REAL_VALUE_FROM_TARGET_SINGLE (i);
 740       return CONST_DOUBLE_FROM_REAL_VALUE (r, mode);
 741     }
 742 #else
 743     {
 744       union {HOST_WIDE_INT i; float d; } u;
 745
 746       u.i = INTVAL (x);
 747       return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode);
 748     }
 749 #endif
 750   else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
 751              && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
 752             || flag_pretend_float)
 753            && GET_MODE_CLASS (mode) == MODE_FLOAT
 754            && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD
 755            && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
 756            && GET_MODE (x) == VOIDmode
 757            && (sizeof (double) * HOST_BITS_PER_CHAR
 758                == 2 * HOST_BITS_PER_WIDE_INT))
 759 #ifdef REAL_ARITHMETIC
 760     {
 761       REAL_VALUE_TYPE r;
 762       HOST_WIDE_INT i[2];
 763       HOST_WIDE_INT low, high;
 764
 765       if (GET_CODE (x) == CONST_INT)
 766         low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1);
 767       else
 768         low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x);
 769
 770       /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the
 771          target machine.  */
 772       if (WORDS_BIG_ENDIAN)
 773         i[0] = high, i[1] = low;
 774       else
 775         i[0] = low, i[1] = high;
 776
 777       r = REAL_VALUE_FROM_TARGET_DOUBLE (i);
 778       return CONST_DOUBLE_FROM_REAL_VALUE (r, mode);
 779     }
 780 #else
 781     {
 782       union {HOST_WIDE_INT i[2]; double d; } u;
 783       HOST_WIDE_INT low, high;
 784
 785       if (GET_CODE (x) == CONST_INT)
 786         low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1);
 787       else
 788         low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x);
 789
 790 #ifdef HOST_WORDS_BIG_ENDIAN
 791       u.i[0] = high, u.i[1] = low;
 792 #else
 793       u.i[0] = low, u.i[1] = high;
 794 #endif
 795
 796       return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode);
 797     }
 798 #endif
 799
 800   /* We need an extra case for machines where HOST_BITS_PER_WIDE_INT is the
 801      same as sizeof (double) or when sizeof (float) is larger than the
 802      size of a word on the target machine.  */
 803 #ifdef REAL_ARITHMETIC
 804   else if (mode == SFmode && GET_CODE (x) == CONST_INT)
 805     {
 806       REAL_VALUE_TYPE r;
 807       HOST_WIDE_INT i;
 808
 809       i = INTVAL (x);
 810       r = REAL_VALUE_FROM_TARGET_SINGLE (i);
 811       return CONST_DOUBLE_FROM_REAL_VALUE (r, mode);
 812     }
 813   else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
 814              && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
 815             || flag_pretend_float)
 816            && GET_MODE_CLASS (mode) == MODE_FLOAT
 817            && GET_MODE_SIZE (mode) == UNITS_PER_WORD
 818            && GET_CODE (x) == CONST_INT
 819            && (sizeof (double) * HOST_BITS_PER_CHAR
 820                == HOST_BITS_PER_WIDE_INT))
 821     {
 822       REAL_VALUE_TYPE r;
 823       HOST_WIDE_INT i;
 824
 825       i = INTVAL (x);
 826       r = REAL_VALUE_FROM_TARGET_DOUBLE (&i);
 827       return CONST_DOUBLE_FROM_REAL_VALUE (r, mode);
 828     }
 829 #endif
 830
 831   /* Similarly, if this is converting a floating-point value into a
 832      single-word integer.  Only do this is the host and target parameters are
 833      compatible.  */
 834
 835   else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
 836              && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
 837             || flag_pretend_float)
 838            && (GET_MODE_CLASS (mode) == MODE_INT
 839                || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
 840            && GET_CODE (x) == CONST_DOUBLE
 841            && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT
 842            && GET_MODE_BITSIZE (mode) == BITS_PER_WORD)
 843     return operand_subword (x, word, 0, GET_MODE (x));
 844
 845   /* Similarly, if this is converting a floating-point value into a
 846      two-word integer, we can do this one word at a time and make an
 847      integer.  Only do this is the host and target parameters are
 848      compatible.  */
 849
 850   else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
 851              && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
 852             || flag_pretend_float)
 853            && (GET_MODE_CLASS (mode) == MODE_INT
 854                || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
 855            && GET_CODE (x) == CONST_DOUBLE
 856            && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT
 857            && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD)
 858     {
 859       rtx lowpart
 860         = operand_subword (x, word + WORDS_BIG_ENDIAN, 0, GET_MODE (x));
 861       rtx highpart
 862         = operand_subword (x, word + ! WORDS_BIG_ENDIAN, 0, GET_MODE (x));
 863
 864       if (lowpart && GET_CODE (lowpart) == CONST_INT
 865           && highpart && GET_CODE (highpart) == CONST_INT)
 866         return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode);
 867     }
 868
 869   /* Otherwise, we can't do this.  */
 870   return 0;
 871 }
 872 \f
 873 /* Return the real part (which has mode MODE) of a complex value X.
 874    This always comes at the low address in memory.  */
 875
 876 rtx
 877 gen_realpart (mode, x)
 878      enum machine_mode mode;
 879      register rtx x;
 880 {
 881   if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode)
 882     return XEXP (x, 0);
 883   else if (WORDS_BIG_ENDIAN
 884            && GET_MODE_BITSIZE (mode) < BITS_PER_WORD
 885            && REG_P (x)
 886            && REGNO (x) < FIRST_PSEUDO_REGISTER)
 887     fatal ("Unable to access real part of complex value in a hard register on this target");
 888   else if (WORDS_BIG_ENDIAN)
 889     return gen_highpart (mode, x);
 890   else
 891     return gen_lowpart (mode, x);
 892 }
 893
 894 /* Return the imaginary part (which has mode MODE) of a complex value X.
 895    This always comes at the high address in memory.  */
 896
 897 rtx
 898 gen_imagpart (mode, x)
 899      enum machine_mode mode;
 900      register rtx x;
 901 {
 902   if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode)
 903     return XEXP (x, 1);
 904   else if (WORDS_BIG_ENDIAN)
 905     return gen_lowpart (mode, x);
 906   else if (!WORDS_BIG_ENDIAN
 907            && GET_MODE_BITSIZE (mode) < BITS_PER_WORD
 908            && REG_P (x)
 909            && REGNO (x) < FIRST_PSEUDO_REGISTER)
 910     fatal ("Unable to access imaginary part of complex value in a hard register on this target");
 911   else
 912     return gen_highpart (mode, x);
 913 }
 914
 915 /* Return 1 iff X, assumed to be a SUBREG,
 916    refers to the real part of the complex value in its containing reg.
 917    Complex values are always stored with the real part in the first word,
 918    regardless of WORDS_BIG_ENDIAN.  */
 919
 920 int
 921 subreg_realpart_p (x)
 922      rtx x;
 923 {
 924   if (GET_CODE (x) != SUBREG)
 925     abort ();
 926
 927   return SUBREG_WORD (x) * UNITS_PER_WORD < GET_MODE_UNIT_SIZE (GET_MODE (SUBREG_REG (x)));
 928 }
 929 \f
 930 /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value,
 931    return an rtx (MEM, SUBREG, or CONST_INT) that refers to the
 932    least-significant part of X.
 933    MODE specifies how big a part of X to return;
 934    it usually should not be larger than a word.
 935    If X is a MEM whose address is a QUEUED, the value may be so also.  */
 936
 937 rtx
 938 gen_lowpart (mode, x)
 939      enum machine_mode mode;
 940      register rtx x;
 941 {
 942   rtx result = gen_lowpart_common (mode, x);
 943
 944   if (result)
 945     return result;
 946   else if (GET_CODE (x) == REG)
 947     {
 948       /* Must be a hard reg that's not valid in MODE.  */
 949       result = gen_lowpart_common (mode, copy_to_reg (x));
 950       if (result == 0)
 951         abort ();
 952       return result;
 953     }
 954   else if (GET_CODE (x) == MEM)
 955     {
 956       /* The only additional case we can do is MEM.  */
 957       register int offset = 0;
 958       if (WORDS_BIG_ENDIAN)
 959         offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
 960                   - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
 961
 962       if (BYTES_BIG_ENDIAN)
 963         /* Adjust the address so that the address-after-the-data
 964            is unchanged.  */
 965         offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
 966                    - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
 967
 968       return change_address (x, mode, plus_constant (XEXP (x, 0), offset));
 969     }
 970   else if (GET_CODE (x) == ADDRESSOF)
 971     return gen_lowpart (mode, force_reg (GET_MODE (x), x));
 972   else
 973     abort ();
 974 }
 975
 976 /* Like `gen_lowpart', but refer to the most significant part.
 977    This is used to access the imaginary part of a complex number.  */
 978
 979 rtx
 980 gen_highpart (mode, x)
 981      enum machine_mode mode;
 982      register rtx x;
 983 {
 984   /* This case loses if X is a subreg.  To catch bugs early,
 985      complain if an invalid MODE is used even in other cases.  */
 986   if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
 987       && GET_MODE_SIZE (mode) != GET_MODE_UNIT_SIZE (GET_MODE (x)))
 988     abort ();
 989   if (GET_CODE (x) == CONST_DOUBLE
 990 #if !(TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT || defined (REAL_IS_NOT_DOUBLE))
 991       && GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT
 992 #endif
 993       )
 994     return GEN_INT (CONST_DOUBLE_HIGH (x) & GET_MODE_MASK (mode));
 995   else if (GET_CODE (x) == CONST_INT)
 996     {
 997       if (HOST_BITS_PER_WIDE_INT <= BITS_PER_WORD)
 998         return const0_rtx;
 999       return GEN_INT (INTVAL (x) >> (HOST_BITS_PER_WIDE_INT - BITS_PER_WORD));
1000     }
1001   else if (GET_CODE (x) == MEM)
1002     {
1003       register int offset = 0;
1004       if (! WORDS_BIG_ENDIAN)
1005         offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
1006                   - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
1007
1008       if (! BYTES_BIG_ENDIAN
1009           && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
1010         offset -= (GET_MODE_SIZE (mode)
1011                    - MIN (UNITS_PER_WORD,
1012                           GET_MODE_SIZE (GET_MODE (x))));
1013
1014       return change_address (x, mode, plus_constant (XEXP (x, 0), offset));
1015     }
1016   else if (GET_CODE (x) == SUBREG)
1017     {
1018       /* The only time this should occur is when we are looking at a
1019          multi-word item with a SUBREG whose mode is the same as that of the
1020          item.  It isn't clear what we would do if it wasn't.  */
1021       if (SUBREG_WORD (x) != 0)
1022         abort ();
1023       return gen_highpart (mode, SUBREG_REG (x));
1024     }
1025   else if (GET_CODE (x) == REG)
1026     {
1027       int word;
1028
1029       /* Let the backend decide how many registers to skip.  This is needed
1030          in particular for sparc64 where fp regs are smaller than a word.  */
1031       /* ??? Note that subregs are now ambiguous, in that those against
1032          pseudos are sized by the word size, while those against hard
1033          regs are sized by the underlying register size.  Better would be
1034          to always interpret the subreg offset parameter as bytes or bits.  */
1035
1036       if (WORDS_BIG_ENDIAN)
1037         word = 0;
1038       else if (REGNO (x) < FIRST_PSEUDO_REGISTER)
1039         word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x))
1040                 - HARD_REGNO_NREGS (REGNO (x), mode));
1041       else
1042         word = ((GET_MODE_SIZE (GET_MODE (x))
1043                  - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
1044                 / UNITS_PER_WORD);
1045
1046       if (REGNO (x) < FIRST_PSEUDO_REGISTER
1047           /* integrate.c can't handle parts of a return value register.  */
1048           && (! REG_FUNCTION_VALUE_P (x)
1049               || ! rtx_equal_function_value_matters)
1050           /* We want to keep the stack, frame, and arg pointers special.  */
1051           && x != frame_pointer_rtx
1052 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1053           && x != arg_pointer_rtx
1054 #endif
1055           && x != stack_pointer_rtx)
1056         return gen_rtx_REG (mode, REGNO (x) + word);
1057       else
1058         return gen_rtx_SUBREG (mode, x, word);
1059     }
1060   else
1061     abort ();
1062 }
1063
1064 /* Return 1 iff X, assumed to be a SUBREG,
1065    refers to the least significant part of its containing reg.
1066    If X is not a SUBREG, always return 1 (it is its own low part!).  */
1067
1068 int
1069 subreg_lowpart_p (x)
1070      rtx x;
1071 {
1072   if (GET_CODE (x) != SUBREG)
1073     return 1;
1074   else if (GET_MODE (SUBREG_REG (x)) == VOIDmode)
1075     return 0;
1076
1077   if (WORDS_BIG_ENDIAN
1078       && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD)
1079     return (SUBREG_WORD (x)
1080             == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
1081                  - MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD))
1082                 / UNITS_PER_WORD));
1083
1084   return SUBREG_WORD (x) == 0;
1085 }
1086 \f
1087 /* Return subword I of operand OP.
1088    The word number, I, is interpreted as the word number starting at the
1089    low-order address.  Word 0 is the low-order word if not WORDS_BIG_ENDIAN,
1090    otherwise it is the high-order word.
1091
1092    If we cannot extract the required word, we return zero.  Otherwise, an
1093    rtx corresponding to the requested word will be returned.
1094
1095    VALIDATE_ADDRESS is nonzero if the address should be validated.  Before
1096    reload has completed, a valid address will always be returned.  After
1097    reload, if a valid address cannot be returned, we return zero.
1098
1099    If VALIDATE_ADDRESS is zero, we simply form the required address; validating
1100    it is the responsibility of the caller.
1101
1102    MODE is the mode of OP in case it is a CONST_INT.  */
1103
1104 rtx
1105 operand_subword (op, i, validate_address, mode)
1106      rtx op;
1107      int i;
1108      int validate_address;
1109      enum machine_mode mode;
1110 {
1111   HOST_WIDE_INT val;
1112   int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD;
1113
1114   if (mode == VOIDmode)
1115     mode = GET_MODE (op);
1116
1117   if (mode == VOIDmode)
1118     abort ();
1119
1120   /* If OP is narrower than a word, fail. */
1121   if (mode != BLKmode
1122       && (GET_MODE_SIZE (mode) < UNITS_PER_WORD))
1123     return 0;
1124
1125   /* If we want a word outside OP, return zero. */
1126   if (mode != BLKmode
1127       && (i + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode))
1128     return const0_rtx;
1129
1130   /* If OP is already an integer word, return it.  */
1131   if (GET_MODE_CLASS (mode) == MODE_INT
1132       && GET_MODE_SIZE (mode) == UNITS_PER_WORD)
1133     return op;
1134
1135   /* If OP is a REG or SUBREG, we can handle it very simply.  */
1136   if (GET_CODE (op) == REG)
1137     {
1138       /* ??? There is a potential problem with this code.  It does not
1139          properly handle extractions of a subword from a hard register
1140          that is larger than word_mode.  Presumably the check for
1141          HARD_REGNO_MODE_OK catches these most of these cases.  */
1142
1143       /* If OP is a hard register, but OP + I is not a hard register,
1144          then extracting a subword is impossible.
1145
1146          For example, consider if OP is the last hard register and it is
1147          larger than word_mode.  If we wanted word N (for N > 0) because a
1148          part of that hard register was known to contain a useful value,
1149          then OP + I would refer to a pseudo, not the hard register we
1150          actually wanted.  */
1151       if (REGNO (op) < FIRST_PSEUDO_REGISTER
1152           && REGNO (op) + i >= FIRST_PSEUDO_REGISTER)
1153         return 0;
1154
1155       /* If the register is not valid for MODE, return 0.  Note we
1156          have to check both OP and OP + I since they may refer to
1157          different parts of the register file.
1158
1159          Consider if OP refers to the last 96bit FP register and we want
1160          subword 3 because that subword is known to contain a value we
1161          needed.  */
1162       if (REGNO (op) < FIRST_PSEUDO_REGISTER
1163           && (! HARD_REGNO_MODE_OK (REGNO (op), word_mode)
1164               || ! HARD_REGNO_MODE_OK (REGNO (op) + i, word_mode)))
1165         return 0;
1166       else if (REGNO (op) >= FIRST_PSEUDO_REGISTER
1167                || (REG_FUNCTION_VALUE_P (op)
1168                    && rtx_equal_function_value_matters)
1169                /* We want to keep the stack, frame, and arg pointers
1170                   special.  */
1171                || op == frame_pointer_rtx
1172 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1173                || op == arg_pointer_rtx
1174 #endif
1175                || op == stack_pointer_rtx)
1176         return gen_rtx_SUBREG (word_mode, op, i);
1177       else
1178         return gen_rtx_REG (word_mode, REGNO (op) + i);
1179     }
1180   else if (GET_CODE (op) == SUBREG)
1181     return gen_rtx_SUBREG (word_mode, SUBREG_REG (op), i + SUBREG_WORD (op));
1182   else if (GET_CODE (op) == CONCAT)
1183     {
1184       int partwords = GET_MODE_UNIT_SIZE (GET_MODE (op)) / UNITS_PER_WORD;
1185       if (i < partwords)
1186         return operand_subword (XEXP (op, 0), i, validate_address, mode);
1187       return operand_subword (XEXP (op, 1), i - partwords,
1188                               validate_address, mode);
1189     }
1190
1191   /* Form a new MEM at the requested address.  */
1192   if (GET_CODE (op) == MEM)
1193     {
1194       rtx addr = plus_constant (XEXP (op, 0), i * UNITS_PER_WORD);
1195       rtx new;
1196
1197       if (validate_address)
1198         {
1199           if (reload_completed)
1200             {
1201               if (! strict_memory_address_p (word_mode, addr))
1202                 return 0;
1203             }
1204           else
1205             addr = memory_address (word_mode, addr);
1206         }
1207
1208       new = gen_rtx_MEM (word_mode, addr);
1209
1210       MEM_COPY_ATTRIBUTES (new, op);
1211       RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op);
1212       MEM_ALIAS_SET (new) = MEM_ALIAS_SET (op);
1213
1214       return new;
1215     }
1216
1217   /* The only remaining cases are when OP is a constant.  If the host and
1218      target floating formats are the same, handling two-word floating
1219      constants are easy.  Note that REAL_VALUE_TO_TARGET_{SINGLE,DOUBLE}
1220      are defined as returning one or two 32 bit values, respectively,
1221      and not values of BITS_PER_WORD bits.  */
1222 #ifdef REAL_ARITHMETIC
1223   /* The output is some bits, the width of the target machine's word.
1224      A wider-word host can surely hold them in a CONST_INT. A narrower-word
1225      host can't.  */
1226   if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD
1227       && GET_MODE_CLASS (mode) == MODE_FLOAT
1228       && GET_MODE_BITSIZE (mode) == 64
1229       && GET_CODE (op) == CONST_DOUBLE)
1230     {
1231       long k[2];
1232       REAL_VALUE_TYPE rv;
1233
1234       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1235       REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1236
1237       /* We handle 32-bit and >= 64-bit words here.  Note that the order in
1238          which the words are written depends on the word endianness.
1239          ??? This is a potential portability problem and should
1240          be fixed at some point.
1241
1242          We must excercise caution with the sign bit.  By definition there
1243          are 32 significant bits in K; there may be more in a HOST_WIDE_INT.
1244          Consider a host with a 32-bit long and a 64-bit HOST_WIDE_INT.
1245          So we explicitly mask and sign-extend as necessary.  */
1246       if (BITS_PER_WORD == 32)
1247         {
1248           val = k[i];
1249           val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
1250           return GEN_INT (val);
1251         }
1252 #if HOST_BITS_PER_WIDE_INT >= 64
1253       else if (BITS_PER_WORD >= 64 && i == 0)
1254         {
1255           val = k[! WORDS_BIG_ENDIAN];
1256           val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32;
1257           val |= (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN] & 0xffffffff;
1258           return GEN_INT (val);
1259         }
1260 #endif
1261       else if (BITS_PER_WORD == 16)
1262         {
1263           val = k[i >> 1];
1264           if ((i & 1) == !WORDS_BIG_ENDIAN)
1265             val >>= 16;
1266           val &= 0xffff;
1267           return GEN_INT (val);
1268         }
1269       else
1270         abort ();
1271     }
1272   else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD
1273            && GET_MODE_CLASS (mode) == MODE_FLOAT
1274            && GET_MODE_BITSIZE (mode) > 64
1275            && GET_CODE (op) == CONST_DOUBLE)
1276     {
1277       long k[4];
1278       REAL_VALUE_TYPE rv;
1279
1280       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1281       REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
1282
1283       if (BITS_PER_WORD == 32)
1284         {
1285           val = k[i];
1286           val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
1287           return GEN_INT (val);
1288         }
1289 #if HOST_BITS_PER_WIDE_INT >= 64
1290       else if (BITS_PER_WORD >= 64 && i <= 1)
1291         {
1292           val = k[i*2 + ! WORDS_BIG_ENDIAN];
1293           val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32;
1294           val |= (HOST_WIDE_INT) k[i*2 + WORDS_BIG_ENDIAN] & 0xffffffff;
1295           return GEN_INT (val);
1296         }
1297 #endif
1298       else
1299         abort ();
1300     }
1301 #else /* no REAL_ARITHMETIC */
1302   if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
1303         && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1304        || flag_pretend_float)
1305       && GET_MODE_CLASS (mode) == MODE_FLOAT
1306       && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD
1307       && GET_CODE (op) == CONST_DOUBLE)
1308     {
1309       /* The constant is stored in the host's word-ordering,
1310          but we want to access it in the target's word-ordering.  Some
1311          compilers don't like a conditional inside macro args, so we have two
1312          copies of the return.  */
1313 #ifdef HOST_WORDS_BIG_ENDIAN
1314       return GEN_INT (i == WORDS_BIG_ENDIAN
1315                       ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op));
1316 #else
1317       return GEN_INT (i != WORDS_BIG_ENDIAN
1318                       ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op));
1319 #endif
1320     }
1321 #endif /* no REAL_ARITHMETIC */
1322
1323   /* Single word float is a little harder, since single- and double-word
1324      values often do not have the same high-order bits.  We have already
1325      verified that we want the only defined word of the single-word value.  */
1326 #ifdef REAL_ARITHMETIC
1327   if (GET_MODE_CLASS (mode) == MODE_FLOAT
1328       && GET_MODE_BITSIZE (mode) == 32
1329       && GET_CODE (op) == CONST_DOUBLE)
1330     {
1331       long l;
1332       REAL_VALUE_TYPE rv;
1333
1334       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1335       REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1336
1337       /* Sign extend from known 32-bit value to HOST_WIDE_INT.  */
1338       val = l;
1339       val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
1340
1341       if (BITS_PER_WORD == 16)
1342         {
1343           if ((i & 1) == !WORDS_BIG_ENDIAN)
1344             val >>= 16;
1345           val &= 0xffff;
1346         }
1347
1348       return GEN_INT (val);
1349     }
1350 #else
1351   if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
1352         && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1353        || flag_pretend_float)
1354       && sizeof (float) * 8 == HOST_BITS_PER_WIDE_INT
1355       && GET_MODE_CLASS (mode) == MODE_FLOAT
1356       && GET_MODE_SIZE (mode) == UNITS_PER_WORD
1357       && GET_CODE (op) == CONST_DOUBLE)
1358     {
1359       double d;
1360       union {float f; HOST_WIDE_INT i; } u;
1361
1362       REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1363
1364       u.f = d;
1365       return GEN_INT (u.i);
1366     }
1367   if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
1368         && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1369        || flag_pretend_float)
1370       && sizeof (double) * 8 == HOST_BITS_PER_WIDE_INT
1371       && GET_MODE_CLASS (mode) == MODE_FLOAT
1372       && GET_MODE_SIZE (mode) == UNITS_PER_WORD
1373       && GET_CODE (op) == CONST_DOUBLE)
1374     {
1375       double d;
1376       union {double d; HOST_WIDE_INT i; } u;
1377
1378       REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1379
1380       u.d = d;
1381       return GEN_INT (u.i);
1382     }
1383 #endif /* no REAL_ARITHMETIC */
1384
1385   /* The only remaining cases that we can handle are integers.
1386      Convert to proper endianness now since these cases need it.
1387      At this point, i == 0 means the low-order word.
1388
1389      We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT
1390      in general.  However, if OP is (const_int 0), we can just return
1391      it for any word.  */
1392
1393   if (op == const0_rtx)
1394     return op;
1395
1396   if (GET_MODE_CLASS (mode) != MODE_INT
1397       || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE)
1398       || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT)
1399     return 0;
1400
1401   if (WORDS_BIG_ENDIAN)
1402     i = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - i;
1403
1404   /* Find out which word on the host machine this value is in and get
1405      it from the constant.  */
1406   val = (i / size_ratio == 0
1407          ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op))
1408          : (GET_CODE (op) == CONST_INT
1409             ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op)));
1410
1411   /* Get the value we want into the low bits of val.  */
1412   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT)
1413     val = ((val >> ((i % size_ratio) * BITS_PER_WORD)));
1414
1415   val = trunc_int_for_mode (val, word_mode);
1416
1417   return GEN_INT (val);
1418 }
1419
1420 /* Similar to `operand_subword', but never return 0.  If we can't extract
1421    the required subword, put OP into a register and try again.  If that fails,
1422    abort.  We always validate the address in this case.  It is not valid
1423    to call this function after reload; it is mostly meant for RTL
1424    generation.
1425
1426    MODE is the mode of OP, in case it is CONST_INT.  */
1427
1428 rtx
1429 operand_subword_force (op, i, mode)
1430      rtx op;
1431      int i;
1432      enum machine_mode mode;
1433 {
1434   rtx result = operand_subword (op, i, 1, mode);
1435
1436   if (result)
1437     return result;
1438
1439   if (mode != BLKmode && mode != VOIDmode)
1440     {
1441       /* If this is a register which can not be accessed by words, copy it
1442          to a pseudo register.  */
1443       if (GET_CODE (op) == REG)
1444         op = copy_to_reg (op);
1445       else
1446         op = force_reg (mode, op);
1447     }
1448
1449   result = operand_subword (op, i, 1, mode);
1450   if (result == 0)
1451     abort ();
1452
1453   return result;
1454 }
1455 \f
1456 /* Given a compare instruction, swap the operands.
1457    A test instruction is changed into a compare of 0 against the operand.  */
1458
1459 void
1460 reverse_comparison (insn)
1461      rtx insn;
1462 {
1463   rtx body = PATTERN (insn);
1464   rtx comp;
1465
1466   if (GET_CODE (body) == SET)
1467     comp = SET_SRC (body);
1468   else
1469     comp = SET_SRC (XVECEXP (body, 0, 0));
1470
1471   if (GET_CODE (comp) == COMPARE)
1472     {
1473       rtx op0 = XEXP (comp, 0);
1474       rtx op1 = XEXP (comp, 1);
1475       XEXP (comp, 0) = op1;
1476       XEXP (comp, 1) = op0;
1477     }
1478   else
1479     {
1480       rtx new = gen_rtx_COMPARE (VOIDmode,
1481                                  CONST0_RTX (GET_MODE (comp)), comp);
1482       if (GET_CODE (body) == SET)
1483         SET_SRC (body) = new;
1484       else
1485         SET_SRC (XVECEXP (body, 0, 0)) = new;
1486     }
1487 }
1488 \f
1489 /* Return a memory reference like MEMREF, but with its mode changed
1490    to MODE and its address changed to ADDR.
1491    (VOIDmode means don't change the mode.
1492    NULL for ADDR means don't change the address.)  */
1493
1494 rtx
1495 change_address (memref, mode, addr)
1496      rtx memref;
1497      enum machine_mode mode;
1498      rtx addr;
1499 {
1500   rtx new;
1501
1502   if (GET_CODE (memref) != MEM)
1503     abort ();
1504   if (mode == VOIDmode)
1505     mode = GET_MODE (memref);
1506   if (addr == 0)
1507     addr = XEXP (memref, 0);
1508
1509   /* If reload is in progress or has completed, ADDR must be valid.
1510      Otherwise, we can call memory_address to make it valid.  */
1511   if (reload_completed || reload_in_progress)
1512     {
1513       if (! memory_address_p (mode, addr))
1514         abort ();
1515     }
1516   else
1517     addr = memory_address (mode, addr);
1518
1519   if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref))
1520     return memref;
1521
1522   new = gen_rtx_MEM (mode, addr);
1523   RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (memref);
1524   MEM_COPY_ATTRIBUTES (new, memref);
1525   MEM_ALIAS_SET (new) = MEM_ALIAS_SET (memref);
1526   return new;
1527 }
1528 \f
1529 /* Return a newly created CODE_LABEL rtx with a unique label number.  */
1530
1531 rtx
1532 gen_label_rtx ()
1533 {
1534   register rtx label;
1535
1536   label = gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX,
1537                               NULL_RTX, label_num++, NULL_PTR, NULL_PTR);
1538
1539   LABEL_NUSES (label) = 0;
1540   LABEL_ALTERNATE_NAME (label) = NULL;
1541   return label;
1542 }
1543 \f
1544 /* For procedure integration.  */
1545
1546 /* Install new pointers to the first and last insns in the chain.
1547    Also, set cur_insn_uid to one higher than the last in use.
1548    Used for an inline-procedure after copying the insn chain.  */
1549
1550 void
1551 set_new_first_and_last_insn (first, last)
1552      rtx first, last;
1553 {
1554   rtx insn;
1555
1556   first_insn = first;
1557   last_insn = last;
1558   cur_insn_uid = 0;
1559
1560   for (insn = first; insn; insn = NEXT_INSN (insn))
1561     cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn));
1562
1563   cur_insn_uid++;
1564 }
1565
1566 /* Set the range of label numbers found in the current function.
1567    This is used when belatedly compiling an inline function.  */
1568
1569 void
1570 set_new_first_and_last_label_num (first, last)
1571      int first, last;
1572 {
1573   base_label_num = label_num;
1574   first_label_num = first;
1575   last_label_num = last;
1576 }
1577
1578 /* Set the last label number found in the current function.
1579    This is used when belatedly compiling an inline function.  */
1580
1581 void
1582 set_new_last_label_num (last)
1583      int last;
1584 {
1585   base_label_num = label_num;
1586   last_label_num = last;
1587 }
1588 \f
1589 /* Restore all variables describing the current status from the structure *P.
1590    This is used after a nested function.  */
1591
1592 void
1593 restore_emit_status (p)
1594      struct function *p ATTRIBUTE_UNUSED;
1595 {
1596   last_label_num = 0;
1597   clear_emit_caches ();
1598 }
1599
1600 /* Clear out all parts of the state in F that can safely be discarded
1601    after the function has been compiled, to let garbage collection
1602    reclaim the memory.  */
1603
1604 void
1605 free_emit_status (f)
1606      struct function *f;
1607 {
1608   free (f->emit->x_regno_reg_rtx);
1609   free (f->emit->regno_pointer_flag);
1610   free (f->emit->regno_pointer_align);
1611   free (f->emit);
1612   f->emit = NULL;
1613 }
1614 \f
1615 /* Go through all the RTL insn bodies and copy any invalid shared
1616    structure.  This routine should only be called once.  */
1617
1618 void
1619 unshare_all_rtl (fndecl, insn)
1620      tree fndecl;
1621      rtx insn;
1622 {
1623   tree decl;
1624
1625   /* Make sure that virtual parameters are not shared.  */
1626   for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl))
1627     {
1628       copy_rtx_if_shared (DECL_RTL (decl));
1629     }
1630
1631   /* Unshare just about everything else.  */
1632   unshare_all_rtl_1 (insn);
1633
1634   /* Make sure the addresses of stack slots found outside the insn chain
1635      (such as, in DECL_RTL of a variable) are not shared
1636      with the insn chain.
1637
1638      This special care is necessary when the stack slot MEM does not
1639      actually appear in the insn chain.  If it does appear, its address
1640      is unshared from all else at that point.  */
1641   copy_rtx_if_shared (stack_slot_list);
1642 }
1643
1644 /* Go through all the RTL insn bodies and copy any invalid shared
1645    structure, again.  This is a fairly expensive thing to do so it
1646    should be done sparingly.  */
1647
1648 void
1649 unshare_all_rtl_again (insn)
1650      rtx insn;
1651 {
1652   rtx p;
1653   for (p = insn; p; p = NEXT_INSN (p))
1654     if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
1655       {
1656         reset_used_flags (PATTERN (p));
1657         reset_used_flags (REG_NOTES (p));
1658         reset_used_flags (LOG_LINKS (p));
1659       }
1660   unshare_all_rtl_1 (insn);
1661 }
1662
1663 /* Go through all the RTL insn bodies and copy any invalid shared structure.
1664    Assumes the mark bits are cleared at entry.  */
1665
1666 static void
1667 unshare_all_rtl_1 (insn)
1668      rtx insn;
1669 {
1670   for (; insn; insn = NEXT_INSN (insn))
1671     if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1672       {
1673         PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn));
1674         REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn));
1675         LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn));
1676       }
1677 }
1678
1679 /* Mark ORIG as in use, and return a copy of it if it was already in use.
1680    Recursively does the same for subexpressions.  */
1681
1682 rtx
1683 copy_rtx_if_shared (orig)
1684      rtx orig;
1685 {
1686   register rtx x = orig;
1687   register int i;
1688   register enum rtx_code code;
1689   register const char *format_ptr;
1690   int copied = 0;
1691
1692   if (x == 0)
1693     return 0;
1694
1695   code = GET_CODE (x);
1696
1697   /* These types may be freely shared.  */
1698
1699   switch (code)
1700     {
1701     case REG:
1702     case QUEUED:
1703     case CONST_INT:
1704     case CONST_DOUBLE:
1705     case SYMBOL_REF:
1706     case CODE_LABEL:
1707     case PC:
1708     case CC0:
1709     case SCRATCH:
1710       /* SCRATCH must be shared because they represent distinct values.  */
1711       return x;
1712
1713     case CONST:
1714       /* CONST can be shared if it contains a SYMBOL_REF.  If it contains
1715          a LABEL_REF, it isn't sharable.  */
1716       if (GET_CODE (XEXP (x, 0)) == PLUS
1717           && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1718           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
1719         return x;
1720       break;
1721
1722     case INSN:
1723     case JUMP_INSN:
1724     case CALL_INSN:
1725     case NOTE:
1726     case BARRIER:
1727       /* The chain of insns is not being copied.  */
1728       return x;
1729
1730     case MEM:
1731       /* A MEM is allowed to be shared if its address is constant.
1732
1733          We used to allow sharing of MEMs which referenced
1734          virtual_stack_vars_rtx or virtual_incoming_args_rtx, but
1735          that can lose.  instantiate_virtual_regs will not unshare
1736          the MEMs, and combine may change the structure of the address
1737          because it looks safe and profitable in one context, but
1738          in some other context it creates unrecognizable RTL.  */
1739       if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
1740         return x;
1741
1742       break;
1743
1744     default:
1745       break;
1746     }
1747
1748   /* This rtx may not be shared.  If it has already been seen,
1749      replace it with a copy of itself.  */
1750
1751   if (x->used)
1752     {
1753       register rtx copy;
1754
1755       copy = rtx_alloc (code);
1756       bcopy ((char *) x, (char *) copy,
1757              (sizeof (*copy) - sizeof (copy->fld)
1758               + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code)));
1759       x = copy;
1760       copied = 1;
1761     }
1762   x->used = 1;
1763
1764   /* Now scan the subexpressions recursively.
1765      We can store any replaced subexpressions directly into X
1766      since we know X is not shared!  Any vectors in X
1767      must be copied if X was copied.  */
1768
1769   format_ptr = GET_RTX_FORMAT (code);
1770
1771   for (i = 0; i < GET_RTX_LENGTH (code); i++)
1772     {
1773       switch (*format_ptr++)
1774         {
1775         case 'e':
1776           XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i));
1777           break;
1778
1779         case 'E':
1780           if (XVEC (x, i) != NULL)
1781             {
1782               register int j;
1783               int len = XVECLEN (x, i);
1784
1785               if (copied && len > 0)
1786                 XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem);
1787               for (j = 0; j < len; j++)
1788                 XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j));
1789             }
1790           break;
1791         }
1792     }
1793   return x;
1794 }
1795
1796 /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used
1797    to look for shared sub-parts.  */
1798
1799 void
1800 reset_used_flags (x)
1801      rtx x;
1802 {
1803   register int i, j;
1804   register enum rtx_code code;
1805   register const char *format_ptr;
1806
1807   if (x == 0)
1808     return;
1809
1810   code = GET_CODE (x);
1811
1812   /* These types may be freely shared so we needn't do any resetting
1813      for them.  */
1814
1815   switch (code)
1816     {
1817     case REG:
1818     case QUEUED:
1819     case CONST_INT:
1820     case CONST_DOUBLE:
1821     case SYMBOL_REF:
1822     case CODE_LABEL:
1823     case PC:
1824     case CC0:
1825       return;
1826
1827     case INSN:
1828     case JUMP_INSN:
1829     case CALL_INSN:
1830     case NOTE:
1831     case LABEL_REF:
1832     case BARRIER:
1833       /* The chain of insns is not being copied.  */
1834       return;
1835
1836     default:
1837       break;
1838     }
1839
1840   x->used = 0;
1841
1842   format_ptr = GET_RTX_FORMAT (code);
1843   for (i = 0; i < GET_RTX_LENGTH (code); i++)
1844     {
1845       switch (*format_ptr++)
1846         {
1847         case 'e':
1848           reset_used_flags (XEXP (x, i));
1849           break;
1850
1851         case 'E':
1852           for (j = 0; j < XVECLEN (x, i); j++)
1853             reset_used_flags (XVECEXP (x, i, j));
1854           break;
1855         }
1856     }
1857 }
1858 \f
1859 /* Copy X if necessary so that it won't be altered by changes in OTHER.
1860    Return X or the rtx for the pseudo reg the value of X was copied into.
1861    OTHER must be valid as a SET_DEST.  */
1862
1863 rtx
1864 make_safe_from (x, other)
1865      rtx x, other;
1866 {
1867   while (1)
1868     switch (GET_CODE (other))
1869       {
1870       case SUBREG:
1871         other = SUBREG_REG (other);
1872         break;
1873       case STRICT_LOW_PART:
1874       case SIGN_EXTEND:
1875       case ZERO_EXTEND:
1876         other = XEXP (other, 0);
1877         break;
1878       default:
1879         goto done;
1880       }
1881  done:
1882   if ((GET_CODE (other) == MEM
1883        && ! CONSTANT_P (x)
1884        && GET_CODE (x) != REG
1885        && GET_CODE (x) != SUBREG)
1886       || (GET_CODE (other) == REG
1887           && (REGNO (other) < FIRST_PSEUDO_REGISTER
1888               || reg_mentioned_p (other, x))))
1889     {
1890       rtx temp = gen_reg_rtx (GET_MODE (x));
1891       emit_move_insn (temp, x);
1892       return temp;
1893     }
1894   return x;
1895 }
1896 \f
1897 /* Emission of insns (adding them to the doubly-linked list).  */
1898
1899 /* Return the first insn of the current sequence or current function.  */
1900
1901 rtx
1902 get_insns ()
1903 {
1904   return first_insn;
1905 }
1906
1907 /* Return the last insn emitted in current sequence or current function.  */
1908
1909 rtx
1910 get_last_insn ()
1911 {
1912   return last_insn;
1913 }
1914
1915 /* Specify a new insn as the last in the chain.  */
1916
1917 void
1918 set_last_insn (insn)
1919      rtx insn;
1920 {
1921   if (NEXT_INSN (insn) != 0)
1922     abort ();
1923   last_insn = insn;
1924 }
1925
1926 /* Return the last insn emitted, even if it is in a sequence now pushed.  */
1927
1928 rtx
1929 get_last_insn_anywhere ()
1930 {
1931   struct sequence_stack *stack;
1932   if (last_insn)
1933     return last_insn;
1934   for (stack = seq_stack; stack; stack = stack->next)
1935     if (stack->last != 0)
1936       return stack->last;
1937   return 0;
1938 }
1939
1940 /* Return a number larger than any instruction's uid in this function.  */
1941
1942 int
1943 get_max_uid ()
1944 {
1945   return cur_insn_uid;
1946 }
1947
1948 /* Renumber instructions so that no instruction UIDs are wasted.  */
1949
1950 void
1951 renumber_insns (stream)
1952      FILE *stream;
1953 {
1954   rtx insn;
1955
1956   /* If we're not supposed to renumber instructions, don't.  */
1957   if (!flag_renumber_insns)
1958     return;
1959
1960   /* If there aren't that many instructions, then it's not really
1961      worth renumbering them.  */
1962   if (flag_renumber_insns == 1 && get_max_uid () < 25000)
1963     return;
1964
1965   cur_insn_uid = 1;
1966
1967   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1968     {
1969       if (stream)
1970         fprintf (stream, "Renumbering insn %d to %d\n",
1971                  INSN_UID (insn), cur_insn_uid);
1972       INSN_UID (insn) = cur_insn_uid++;
1973     }
1974 }
1975 \f
1976 /* Return the next insn.  If it is a SEQUENCE, return the first insn
1977    of the sequence.  */
1978
1979 rtx
1980 next_insn (insn)
1981      rtx insn;
1982 {
1983   if (insn)
1984     {
1985       insn = NEXT_INSN (insn);
1986       if (insn && GET_CODE (insn) == INSN
1987           && GET_CODE (PATTERN (insn)) == SEQUENCE)
1988         insn = XVECEXP (PATTERN (insn), 0, 0);
1989     }
1990
1991   return insn;
1992 }
1993
1994 /* Return the previous insn.  If it is a SEQUENCE, return the last insn
1995    of the sequence.  */
1996
1997 rtx
1998 previous_insn (insn)
1999      rtx insn;
2000 {
2001   if (insn)
2002     {
2003       insn = PREV_INSN (insn);
2004       if (insn && GET_CODE (insn) == INSN
2005           && GET_CODE (PATTERN (insn)) == SEQUENCE)
2006         insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1);
2007     }
2008
2009   return insn;
2010 }
2011
2012 /* Return the next insn after INSN that is not a NOTE.  This routine does not
2013    look inside SEQUENCEs.  */
2014
2015 rtx
2016 next_nonnote_insn (insn)
2017      rtx insn;
2018 {
2019   while (insn)
2020     {
2021       insn = NEXT_INSN (insn);
2022       if (insn == 0 || GET_CODE (insn) != NOTE)
2023         break;
2024     }
2025
2026   return insn;
2027 }
2028
2029 /* Return the previous insn before INSN that is not a NOTE.  This routine does
2030    not look inside SEQUENCEs.  */
2031
2032 rtx
2033 prev_nonnote_insn (insn)
2034      rtx insn;
2035 {
2036   while (insn)
2037     {
2038       insn = PREV_INSN (insn);
2039       if (insn == 0 || GET_CODE (insn) != NOTE)
2040         break;
2041     }
2042
2043   return insn;
2044 }
2045
2046 /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN;
2047    or 0, if there is none.  This routine does not look inside
2048    SEQUENCEs.  */
2049
2050 rtx
2051 next_real_insn (insn)
2052      rtx insn;
2053 {
2054   while (insn)
2055     {
2056       insn = NEXT_INSN (insn);
2057       if (insn == 0 || GET_CODE (insn) == INSN
2058           || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
2059         break;
2060     }
2061
2062   return insn;
2063 }
2064
2065 /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN;
2066    or 0, if there is none.  This routine does not look inside
2067    SEQUENCEs.  */
2068
2069 rtx
2070 prev_real_insn (insn)
2071      rtx insn;
2072 {
2073   while (insn)
2074     {
2075       insn = PREV_INSN (insn);
2076       if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
2077           || GET_CODE (insn) == JUMP_INSN)
2078         break;
2079     }
2080
2081   return insn;
2082 }
2083
2084 /* Find the next insn after INSN that really does something.  This routine
2085    does not look inside SEQUENCEs.  Until reload has completed, this is the
2086    same as next_real_insn.  */
2087
2088 int
2089 active_insn_p (insn)
2090      rtx insn;
2091 {
2092   return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN
2093           || (GET_CODE (insn) == INSN
2094               && (! reload_completed
2095                   || (GET_CODE (PATTERN (insn)) != USE
2096                       && GET_CODE (PATTERN (insn)) != CLOBBER))));
2097 }
2098
2099 rtx
2100 next_active_insn (insn)
2101      rtx insn;
2102 {
2103   while (insn)
2104     {
2105       insn = NEXT_INSN (insn);
2106       if (insn == 0 || active_insn_p (insn))
2107         break;
2108     }
2109
2110   return insn;
2111 }
2112
2113 /* Find the last insn before INSN that really does something.  This routine
2114    does not look inside SEQUENCEs.  Until reload has completed, this is the
2115    same as prev_real_insn.  */
2116
2117 rtx
2118 prev_active_insn (insn)
2119      rtx insn;
2120 {
2121   while (insn)
2122     {
2123       insn = PREV_INSN (insn);
2124       if (insn == 0 || active_insn_p (insn))
2125         break;
2126     }
2127
2128   return insn;
2129 }
2130
2131 /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none.  */
2132
2133 rtx
2134 next_label (insn)
2135      rtx insn;
2136 {
2137   while (insn)
2138     {
2139       insn = NEXT_INSN (insn);
2140       if (insn == 0 || GET_CODE (insn) == CODE_LABEL)
2141         break;
2142     }
2143
2144   return insn;
2145 }
2146
2147 /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none.  */
2148
2149 rtx
2150 prev_label (insn)
2151      rtx insn;
2152 {
2153   while (insn)
2154     {
2155       insn = PREV_INSN (insn);
2156       if (insn == 0 || GET_CODE (insn) == CODE_LABEL)
2157         break;
2158     }
2159
2160   return insn;
2161 }
2162 \f
2163 #ifdef HAVE_cc0
2164 /* INSN uses CC0 and is being moved into a delay slot.  Set up REG_CC_SETTER
2165    and REG_CC_USER notes so we can find it.  */
2166
2167 void
2168 link_cc0_insns (insn)
2169      rtx insn;
2170 {
2171   rtx user = next_nonnote_insn (insn);
2172
2173   if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE)
2174     user = XVECEXP (PATTERN (user), 0, 0);
2175
2176   REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn,
2177                                         REG_NOTES (user));
2178   REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn));
2179 }
2180
2181 /* Return the next insn that uses CC0 after INSN, which is assumed to
2182    set it.  This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter
2183    applied to the result of this function should yield INSN).
2184
2185    Normally, this is simply the next insn.  However, if a REG_CC_USER note
2186    is present, it contains the insn that uses CC0.
2187
2188    Return 0 if we can't find the insn.  */
2189
2190 rtx
2191 next_cc0_user (insn)
2192      rtx insn;
2193 {
2194   rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX);
2195
2196   if (note)
2197     return XEXP (note, 0);
2198
2199   insn = next_nonnote_insn (insn);
2200   if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
2201     insn = XVECEXP (PATTERN (insn), 0, 0);
2202
2203   if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2204       && reg_mentioned_p (cc0_rtx, PATTERN (insn)))
2205     return insn;
2206
2207   return 0;
2208 }
2209
2210 /* Find the insn that set CC0 for INSN.  Unless INSN has a REG_CC_SETTER
2211    note, it is the previous insn.  */
2212
2213 rtx
2214 prev_cc0_setter (insn)
2215      rtx insn;
2216 {
2217   rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
2218
2219   if (note)
2220     return XEXP (note, 0);
2221
2222   insn = prev_nonnote_insn (insn);
2223   if (! sets_cc0_p (PATTERN (insn)))
2224     abort ();
2225
2226   return insn;
2227 }
2228 #endif
2229 \f
2230 /* Try splitting insns that can be split for better scheduling.
2231    PAT is the pattern which might split.
2232    TRIAL is the insn providing PAT.
2233    LAST is non-zero if we should return the last insn of the sequence produced.
2234
2235    If this routine succeeds in splitting, it returns the first or last
2236    replacement insn depending on the value of LAST.  Otherwise, it
2237    returns TRIAL.  If the insn to be returned can be split, it will be.  */
2238
2239 rtx
2240 try_split (pat, trial, last)
2241      rtx pat, trial;
2242      int last;
2243 {
2244   rtx before = PREV_INSN (trial);
2245   rtx after = NEXT_INSN (trial);
2246   rtx seq = split_insns (pat, trial);
2247   int has_barrier = 0;
2248   rtx tem;
2249
2250   /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER.
2251      We may need to handle this specially.  */
2252   if (after && GET_CODE (after) == BARRIER)
2253     {
2254       has_barrier = 1;
2255       after = NEXT_INSN (after);
2256     }
2257
2258   if (seq)
2259     {
2260       /* SEQ can either be a SEQUENCE or the pattern of a single insn.
2261          The latter case will normally arise only when being done so that
2262          it, in turn, will be split (SFmode on the 29k is an example).  */
2263       if (GET_CODE (seq) == SEQUENCE)
2264         {
2265           /* If we are splitting a JUMP_INSN, look for the JUMP_INSN in
2266              SEQ and copy our JUMP_LABEL to it.  If JUMP_LABEL is non-zero,
2267              increment the usage count so we don't delete the label.  */
2268           int i;
2269
2270           if (GET_CODE (trial) == JUMP_INSN)
2271             for (i = XVECLEN (seq, 0) - 1; i >= 0; i--)
2272               if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN)
2273                 {
2274                   JUMP_LABEL (XVECEXP (seq, 0, i)) = JUMP_LABEL (trial);
2275
2276                   if (JUMP_LABEL (trial))
2277                     LABEL_NUSES (JUMP_LABEL (trial))++;
2278                 }
2279
2280           tem = emit_insn_after (seq, before);
2281
2282           delete_insn (trial);
2283           if (has_barrier)
2284             emit_barrier_after (tem);
2285
2286           /* Recursively call try_split for each new insn created; by the
2287              time control returns here that insn will be fully split, so
2288              set LAST and continue from the insn after the one returned.
2289              We can't use next_active_insn here since AFTER may be a note.
2290              Ignore deleted insns, which can be occur if not optimizing.  */
2291           for (tem = NEXT_INSN (before); tem != after;
2292                tem = NEXT_INSN (tem))
2293             if (! INSN_DELETED_P (tem)
2294                 && GET_RTX_CLASS (GET_CODE (tem)) == 'i')
2295               tem = try_split (PATTERN (tem), tem, 1);
2296         }
2297       /* Avoid infinite loop if the result matches the original pattern.  */
2298       else if (rtx_equal_p (seq, pat))
2299         return trial;
2300       else
2301         {
2302           PATTERN (trial) = seq;
2303           INSN_CODE (trial) = -1;
2304           try_split (seq, trial, last);
2305         }
2306
2307       /* Return either the first or the last insn, depending on which was
2308          requested.  */
2309       return last
2310                 ? (after ? prev_active_insn (after) : last_insn)
2311                 : next_active_insn (before);
2312     }
2313
2314   return trial;
2315 }
2316 \f
2317 /* Make and return an INSN rtx, initializing all its slots.
2318    Store PATTERN in the pattern slots.  */
2319
2320 rtx
2321 make_insn_raw (pattern)
2322      rtx pattern;
2323 {
2324   register rtx insn;
2325
2326   /* If in RTL generation phase, see if FREE_INSN can be used.  */
2327   if (!ggc_p && free_insn != 0 && rtx_equal_function_value_matters)
2328     {
2329       insn = free_insn;
2330       free_insn = NEXT_INSN (free_insn);
2331       PUT_CODE (insn, INSN);
2332     }
2333   else
2334     insn = rtx_alloc (INSN);
2335
2336   INSN_UID (insn) = cur_insn_uid++;
2337   PATTERN (insn) = pattern;
2338   INSN_CODE (insn) = -1;
2339   LOG_LINKS (insn) = NULL;
2340   REG_NOTES (insn) = NULL;
2341
2342 #ifdef ENABLE_RTL_CHECKING
2343   if (insn
2344       && GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2345       && (returnjump_p (insn)
2346           || (GET_CODE (insn) == SET
2347               && SET_DEST (insn) == pc_rtx)))
2348     {
2349       warning ("ICE: emit_insn used where emit_jump_insn needed:\n");
2350       debug_rtx (insn);
2351     }
2352 #endif
2353
2354   return insn;
2355 }
2356
2357 /* Like `make_insn' but make a JUMP_INSN instead of an insn.  */
2358
2359 static rtx
2360 make_jump_insn_raw (pattern)
2361      rtx pattern;
2362 {
2363   register rtx insn;
2364
2365   insn = rtx_alloc (JUMP_INSN);
2366   INSN_UID (insn) = cur_insn_uid++;
2367
2368   PATTERN (insn) = pattern;
2369   INSN_CODE (insn) = -1;
2370   LOG_LINKS (insn) = NULL;
2371   REG_NOTES (insn) = NULL;
2372   JUMP_LABEL (insn) = NULL;
2373
2374   return insn;
2375 }
2376
2377 /* Like `make_insn' but make a CALL_INSN instead of an insn.  */
2378
2379 static rtx
2380 make_call_insn_raw (pattern)
2381      rtx pattern;
2382 {
2383   register rtx insn;
2384
2385   insn = rtx_alloc (CALL_INSN);
2386   INSN_UID (insn) = cur_insn_uid++;
2387
2388   PATTERN (insn) = pattern;
2389   INSN_CODE (insn) = -1;
2390   LOG_LINKS (insn) = NULL;
2391   REG_NOTES (insn) = NULL;
2392   CALL_INSN_FUNCTION_USAGE (insn) = NULL;
2393
2394   return insn;
2395 }
2396 \f
2397 /* Add INSN to the end of the doubly-linked list.
2398    INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE.  */
2399
2400 void
2401 add_insn (insn)
2402      register rtx insn;
2403 {
2404   PREV_INSN (insn) = last_insn;
2405   NEXT_INSN (insn) = 0;
2406
2407   if (NULL != last_insn)
2408     NEXT_INSN (last_insn) = insn;
2409
2410   if (NULL == first_insn)
2411     first_insn = insn;
2412
2413   last_insn = insn;
2414 }
2415
2416 /* Add INSN into the doubly-linked list after insn AFTER.  This and
2417    the next should be the only functions called to insert an insn once
2418    delay slots have been filled since only they know how to update a
2419    SEQUENCE.  */
2420
2421 void
2422 add_insn_after (insn, after)
2423      rtx insn, after;
2424 {
2425   rtx next = NEXT_INSN (after);
2426
2427   if (optimize && INSN_DELETED_P (after))
2428     abort ();
2429
2430   NEXT_INSN (insn) = next;
2431   PREV_INSN (insn) = after;
2432
2433   if (next)
2434     {
2435       PREV_INSN (next) = insn;
2436       if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE)
2437         PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn;
2438     }
2439   else if (last_insn == after)
2440     last_insn = insn;
2441   else
2442     {
2443       struct sequence_stack *stack = seq_stack;
2444       /* Scan all pending sequences too.  */
2445       for (; stack; stack = stack->next)
2446         if (after == stack->last)
2447           {
2448             stack->last = insn;
2449             break;
2450           }
2451
2452       if (stack == 0)
2453         abort ();
2454     }
2455
2456   NEXT_INSN (after) = insn;
2457   if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE)
2458     {
2459       rtx sequence = PATTERN (after);
2460       NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn;
2461     }
2462 }
2463
2464 /* Add INSN into the doubly-linked list before insn BEFORE.  This and
2465    the previous should be the only functions called to insert an insn once
2466    delay slots have been filled since only they know how to update a
2467    SEQUENCE.  */
2468
2469 void
2470 add_insn_before (insn, before)
2471      rtx insn, before;
2472 {
2473   rtx prev = PREV_INSN (before);
2474
2475   if (optimize && INSN_DELETED_P (before))
2476     abort ();
2477
2478   PREV_INSN (insn) = prev;
2479   NEXT_INSN (insn) = before;
2480
2481   if (prev)
2482     {
2483       NEXT_INSN (prev) = insn;
2484       if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE)
2485         {
2486           rtx sequence = PATTERN (prev);
2487           NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn;
2488         }
2489     }
2490   else if (first_insn == before)
2491     first_insn = insn;
2492   else
2493     {
2494       struct sequence_stack *stack = seq_stack;
2495       /* Scan all pending sequences too.  */
2496       for (; stack; stack = stack->next)
2497         if (before == stack->first)
2498           {
2499             stack->first = insn;
2500             break;
2501           }
2502
2503       if (stack == 0)
2504         abort ();
2505     }
2506
2507   PREV_INSN (before) = insn;
2508   if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE)
2509     PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn;
2510 }
2511
2512 /* Remove an insn from its doubly-linked list.  This function knows how
2513    to handle sequences.  */
2514 void
2515 remove_insn (insn)
2516      rtx insn;
2517 {
2518   rtx next = NEXT_INSN (insn);
2519   rtx prev = PREV_INSN (insn);
2520   if (prev)
2521     {
2522       NEXT_INSN (prev) = next;
2523       if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE)
2524         {
2525           rtx sequence = PATTERN (prev);
2526           NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next;
2527         }
2528     }
2529   else if (first_insn == insn)
2530     first_insn = next;
2531   else
2532     {
2533       struct sequence_stack *stack = seq_stack;
2534       /* Scan all pending sequences too.  */
2535       for (; stack; stack = stack->next)
2536         if (insn == stack->first)
2537           {
2538             stack->first = next;
2539             break;
2540           }
2541
2542       if (stack == 0)
2543         abort ();
2544     }
2545
2546   if (next)
2547     {
2548       PREV_INSN (next) = prev;
2549       if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE)
2550         PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev;
2551     }
2552   else if (last_insn == insn)
2553     last_insn = prev;
2554   else
2555     {
2556       struct sequence_stack *stack = seq_stack;
2557       /* Scan all pending sequences too.  */
2558       for (; stack; stack = stack->next)
2559         if (insn == stack->last)
2560           {
2561             stack->last = prev;
2562             break;
2563           }
2564
2565       if (stack == 0)
2566         abort ();
2567     }
2568 }
2569
2570 /* Delete all insns made since FROM.
2571    FROM becomes the new last instruction.  */
2572
2573 void
2574 delete_insns_since (from)
2575      rtx from;
2576 {
2577   if (from == 0)
2578     first_insn = 0;
2579   else
2580     NEXT_INSN (from) = 0;
2581   last_insn = from;
2582 }
2583
2584 /* This function is deprecated, please use sequences instead.
2585
2586    Move a consecutive bunch of insns to a different place in the chain.
2587    The insns to be moved are those between FROM and TO.
2588    They are moved to a new position after the insn AFTER.
2589    AFTER must not be FROM or TO or any insn in between.
2590
2591    This function does not know about SEQUENCEs and hence should not be
2592    called after delay-slot filling has been done.  */
2593
2594 void
2595 reorder_insns (from, to, after)
2596      rtx from, to, after;
2597 {
2598   /* Splice this bunch out of where it is now.  */
2599   if (PREV_INSN (from))
2600     NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to);
2601   if (NEXT_INSN (to))
2602     PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from);
2603   if (last_insn == to)
2604     last_insn = PREV_INSN (from);
2605   if (first_insn == from)
2606     first_insn = NEXT_INSN (to);
2607
2608   /* Make the new neighbors point to it and it to them.  */
2609   if (NEXT_INSN (after))
2610     PREV_INSN (NEXT_INSN (after)) = to;
2611
2612   NEXT_INSN (to) = NEXT_INSN (after);
2613   PREV_INSN (from) = after;
2614   NEXT_INSN (after) = from;
2615   if (after == last_insn)
2616     last_insn = to;
2617 }
2618
2619 /* Return the line note insn preceding INSN.  */
2620
2621 static rtx
2622 find_line_note (insn)
2623      rtx insn;
2624 {
2625   if (no_line_numbers)
2626     return 0;
2627
2628   for (; insn; insn = PREV_INSN (insn))
2629     if (GET_CODE (insn) == NOTE
2630         && NOTE_LINE_NUMBER (insn) >= 0)
2631       break;
2632
2633   return insn;
2634 }
2635
2636 /* Like reorder_insns, but inserts line notes to preserve the line numbers
2637    of the moved insns when debugging.  This may insert a note between AFTER
2638    and FROM, and another one after TO.  */
2639
2640 void
2641 reorder_insns_with_line_notes (from, to, after)
2642      rtx from, to, after;
2643 {
2644   rtx from_line = find_line_note (from);
2645   rtx after_line = find_line_note (after);
2646
2647   reorder_insns (from, to, after);
2648
2649   if (from_line == after_line)
2650     return;
2651
2652   if (from_line)
2653     emit_line_note_after (NOTE_SOURCE_FILE (from_line),
2654                           NOTE_LINE_NUMBER (from_line),
2655                           after);
2656   if (after_line)
2657     emit_line_note_after (NOTE_SOURCE_FILE (after_line),
2658                           NOTE_LINE_NUMBER (after_line),
2659                           to);
2660 }
2661
2662 /* Remove unncessary notes from the instruction stream.  */
2663
2664 void
2665 remove_unncessary_notes ()
2666 {
2667   rtx insn;
2668   rtx next;
2669
2670   /* Remove NOTE_INSN_DELETED notes.  We must not remove the first
2671      instruction in the function because the compiler depends on the
2672      first instruction being a note.  */
2673   for (insn = NEXT_INSN (get_insns ()); insn; insn = next)
2674     {
2675       /* Remember what's next.  */
2676       next = NEXT_INSN (insn);
2677
2678       /* We're only interested in notes.  */
2679       if (GET_CODE (insn) != NOTE)
2680         continue;
2681
2682       if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
2683         remove_insn (insn);
2684       else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END)
2685         {
2686           /* Scan back to see if there are any non-note instructions
2687              between INSN and the beginning of this block.  If not,
2688              then there is no PC range in the generated code that will
2689              actually be in this block, so there's no point in
2690              remembering the existence of the block.  */
2691           rtx prev;
2692
2693           for (prev = PREV_INSN (insn); prev; prev = PREV_INSN (prev))
2694             {
2695               /* This block contains a real instruction.  Note that we
2696                  don't include labels; if the only thing in the block
2697                  is a label, then there are still no PC values that
2698                  lie within the block.  */
2699               if (GET_RTX_CLASS (GET_CODE (prev)) == 'i')
2700                 break;
2701
2702               /* We're only interested in NOTEs.  */
2703               if (GET_CODE (prev) != NOTE)
2704                 continue;
2705
2706               if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_BEG)
2707                 {
2708                   /* If the BLOCKs referred to by these notes don't
2709                      match, then something is wrong with our BLOCK
2710                      nesting structure.  */
2711                   if (NOTE_BLOCK (prev) != NOTE_BLOCK (insn))
2712                     abort ();
2713
2714                   /* Never delete the BLOCK for the outermost scope
2715                      of the function; we can refer to names from
2716                      that scope even if the block notes are messed up.  */
2717                   if (! is_body_block (NOTE_BLOCK (insn)))
2718                     {
2719                       debug_ignore_block (NOTE_BLOCK (insn));
2720
2721                       remove_insn (prev);
2722                       remove_insn (insn);
2723                     }
2724                   break;
2725                 }
2726               else if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_END)
2727                 /* There's a nested block.  We need to leave the
2728                    current block in place since otherwise the debugger
2729                    wouldn't be able to show symbols from our block in
2730                    the nested block.  */
2731                 break;
2732             }
2733         }
2734     }
2735 }
2736
2737 \f
2738 /* Emit an insn of given code and pattern
2739    at a specified place within the doubly-linked list.  */
2740
2741 /* Make an instruction with body PATTERN
2742    and output it before the instruction BEFORE.  */
2743
2744 rtx
2745 emit_insn_before (pattern, before)
2746      register rtx pattern, before;
2747 {
2748   register rtx insn = before;
2749
2750   if (GET_CODE (pattern) == SEQUENCE)
2751     {
2752       register int i;
2753
2754       for (i = 0; i < XVECLEN (pattern, 0); i++)
2755         {
2756           insn = XVECEXP (pattern, 0, i);
2757           add_insn_before (insn, before);
2758         }
2759       if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE)
2760         sequence_result[XVECLEN (pattern, 0)] = pattern;
2761     }
2762   else
2763     {
2764       insn = make_insn_raw (pattern);
2765       add_insn_before (insn, before);
2766     }
2767
2768   return insn;
2769 }
2770
2771 /* Similar to emit_insn_before, but update basic block boundaries as well.  */
2772
2773 rtx
2774 emit_block_insn_before (pattern, before, block)
2775      rtx pattern, before;
2776      basic_block block;
2777 {
2778   rtx prev = PREV_INSN (before);
2779   rtx r = emit_insn_before (pattern, before);
2780   if (block && block->head == before)
2781     block->head = NEXT_INSN (prev);
2782   return r;
2783 }
2784
2785 /* Make an instruction with body PATTERN and code JUMP_INSN
2786    and output it before the instruction BEFORE.  */
2787
2788 rtx
2789 emit_jump_insn_before (pattern, before)
2790      register rtx pattern, before;
2791 {
2792   register rtx insn;
2793
2794   if (GET_CODE (pattern) == SEQUENCE)
2795     insn = emit_insn_before (pattern, before);
2796   else
2797     {
2798       insn = make_jump_insn_raw (pattern);
2799       add_insn_before (insn, before);
2800     }
2801
2802   return insn;
2803 }
2804
2805 /* Make an instruction with body PATTERN and code CALL_INSN
2806    and output it before the instruction BEFORE.  */
2807
2808 rtx
2809 emit_call_insn_before (pattern, before)
2810      register rtx pattern, before;
2811 {
2812   register rtx insn;
2813
2814   if (GET_CODE (pattern) == SEQUENCE)
2815     insn = emit_insn_before (pattern, before);
2816   else
2817     {
2818       insn = make_call_insn_raw (pattern);
2819       add_insn_before (insn, before);
2820       PUT_CODE (insn, CALL_INSN);
2821     }
2822
2823   return insn;
2824 }
2825
2826 /* Make an insn of code BARRIER
2827    and output it before the insn BEFORE.  */
2828
2829 rtx
2830 emit_barrier_before (before)
2831      register rtx before;
2832 {
2833   register rtx insn = rtx_alloc (BARRIER);
2834
2835   INSN_UID (insn) = cur_insn_uid++;
2836
2837   add_insn_before (insn, before);
2838   return insn;
2839 }
2840
2841 /* Emit the label LABEL before the insn BEFORE.  */
2842
2843 rtx
2844 emit_label_before (label, before)
2845      rtx label, before;
2846 {
2847   /* This can be called twice for the same label as a result of the
2848      confusion that follows a syntax error!  So make it harmless.  */
2849   if (INSN_UID (label) == 0)
2850     {
2851       INSN_UID (label) = cur_insn_uid++;
2852       add_insn_before (label, before);
2853     }
2854
2855   return label;
2856 }
2857
2858 /* Emit a note of subtype SUBTYPE before the insn BEFORE.  */
2859
2860 rtx
2861 emit_note_before (subtype, before)
2862      int subtype;
2863      rtx before;
2864 {
2865   register rtx note = rtx_alloc (NOTE);
2866   INSN_UID (note) = cur_insn_uid++;
2867   NOTE_SOURCE_FILE (note) = 0;
2868   NOTE_LINE_NUMBER (note) = subtype;
2869
2870   add_insn_before (note, before);
2871   return note;
2872 }
2873 \f
2874 /* Make an insn of code INSN with body PATTERN
2875    and output it after the insn AFTER.  */
2876
2877 rtx
2878 emit_insn_after (pattern, after)
2879      register rtx pattern, after;
2880 {
2881   register rtx insn = after;
2882
2883   if (GET_CODE (pattern) == SEQUENCE)
2884     {
2885       register int i;
2886
2887       for (i = 0; i < XVECLEN (pattern, 0); i++)
2888         {
2889           insn = XVECEXP (pattern, 0, i);
2890           add_insn_after (insn, after);
2891           after = insn;
2892         }
2893       if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE)
2894         sequence_result[XVECLEN (pattern, 0)] = pattern;
2895     }
2896   else
2897     {
2898       insn = make_insn_raw (pattern);
2899       add_insn_after (insn, after);
2900     }
2901
2902   return insn;
2903 }
2904
2905 /* Similar to emit_insn_after, except that line notes are to be inserted so
2906    as to act as if this insn were at FROM.  */
2907
2908 void
2909 emit_insn_after_with_line_notes (pattern, after, from)
2910      rtx pattern, after, from;
2911 {
2912   rtx from_line = find_line_note (from);
2913   rtx after_line = find_line_note (after);
2914   rtx insn = emit_insn_after (pattern, after);
2915
2916   if (from_line)
2917     emit_line_note_after (NOTE_SOURCE_FILE (from_line),
2918                           NOTE_LINE_NUMBER (from_line),
2919                           after);
2920
2921   if (after_line)
2922     emit_line_note_after (NOTE_SOURCE_FILE (after_line),
2923                           NOTE_LINE_NUMBER (after_line),
2924                           insn);
2925 }
2926
2927 /* Similar to emit_insn_after, but update basic block boundaries as well.  */
2928
2929 rtx
2930 emit_block_insn_after (pattern, after, block)
2931      rtx pattern, after;
2932      basic_block block;
2933 {
2934   rtx r = emit_insn_after (pattern, after);
2935   if (block && block->end == after)
2936     block->end = r;
2937   return r;
2938 }
2939
2940 /* Make an insn of code JUMP_INSN with body PATTERN
2941    and output it after the insn AFTER.  */
2942
2943 rtx
2944 emit_jump_insn_after (pattern, after)
2945      register rtx pattern, after;
2946 {
2947   register rtx insn;
2948
2949   if (GET_CODE (pattern) == SEQUENCE)
2950     insn = emit_insn_after (pattern, after);
2951   else
2952     {
2953       insn = make_jump_insn_raw (pattern);
2954       add_insn_after (insn, after);
2955     }
2956
2957   return insn;
2958 }
2959
2960 /* Make an insn of code BARRIER
2961    and output it after the insn AFTER.  */
2962
2963 rtx
2964 emit_barrier_after (after)
2965      register rtx after;
2966 {
2967   register rtx insn = rtx_alloc (BARRIER);
2968
2969   INSN_UID (insn) = cur_insn_uid++;
2970
2971   add_insn_after (insn, after);
2972   return insn;
2973 }
2974
2975 /* Emit the label LABEL after the insn AFTER.  */
2976
2977 rtx
2978 emit_label_after (label, after)
2979      rtx label, after;
2980 {
2981   /* This can be called twice for the same label
2982      as a result of the confusion that follows a syntax error!
2983      So make it harmless.  */
2984   if (INSN_UID (label) == 0)
2985     {
2986       INSN_UID (label) = cur_insn_uid++;
2987       add_insn_after (label, after);
2988     }
2989
2990   return label;
2991 }
2992
2993 /* Emit a note of subtype SUBTYPE after the insn AFTER.  */
2994
2995 rtx
2996 emit_note_after (subtype, after)
2997      int subtype;
2998      rtx after;
2999 {
3000   register rtx note = rtx_alloc (NOTE);
3001   INSN_UID (note) = cur_insn_uid++;
3002   NOTE_SOURCE_FILE (note) = 0;
3003   NOTE_LINE_NUMBER (note) = subtype;
3004   add_insn_after (note, after);
3005   return note;
3006 }
3007
3008 /* Emit a line note for FILE and LINE after the insn AFTER.  */
3009
3010 rtx
3011 emit_line_note_after (file, line, after)
3012      const char *file;
3013      int line;
3014      rtx after;
3015 {
3016   register rtx note;
3017
3018   if (no_line_numbers && line > 0)
3019     {
3020       cur_insn_uid++;
3021       return 0;
3022     }
3023
3024   note  = rtx_alloc (NOTE);
3025   INSN_UID (note) = cur_insn_uid++;
3026   NOTE_SOURCE_FILE (note) = file;
3027   NOTE_LINE_NUMBER (note) = line;
3028   add_insn_after (note, after);
3029   return note;
3030 }
3031 \f
3032 /* Make an insn of code INSN with pattern PATTERN
3033    and add it to the end of the doubly-linked list.
3034    If PATTERN is a SEQUENCE, take the elements of it
3035    and emit an insn for each element.
3036
3037    Returns the last insn emitted.  */
3038
3039 rtx
3040 emit_insn (pattern)
3041      rtx pattern;
3042 {
3043   rtx insn = last_insn;
3044
3045   if (GET_CODE (pattern) == SEQUENCE)
3046     {
3047       register int i;
3048
3049       for (i = 0; i < XVECLEN (pattern, 0); i++)
3050         {
3051           insn = XVECEXP (pattern, 0, i);
3052           add_insn (insn);
3053         }
3054       if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE)
3055         sequence_result[XVECLEN (pattern, 0)] = pattern;
3056     }
3057   else
3058     {
3059       insn = make_insn_raw (pattern);
3060       add_insn (insn);
3061     }
3062
3063   return insn;
3064 }
3065
3066 /* Emit the insns in a chain starting with INSN.
3067    Return the last insn emitted.  */
3068
3069 rtx
3070 emit_insns (insn)
3071      rtx insn;
3072 {
3073   rtx last = 0;
3074
3075   while (insn)
3076     {
3077       rtx next = NEXT_INSN (insn);
3078       add_insn (insn);
3079       last = insn;
3080       insn = next;
3081     }
3082
3083   return last;
3084 }
3085
3086 /* Emit the insns in a chain starting with INSN and place them in front of
3087    the insn BEFORE.  Return the last insn emitted.  */
3088
3089 rtx
3090 emit_insns_before (insn, before)
3091      rtx insn;
3092      rtx before;
3093 {
3094   rtx last = 0;
3095
3096   while (insn)
3097     {
3098       rtx next = NEXT_INSN (insn);
3099       add_insn_before (insn, before);
3100       last = insn;
3101       insn = next;
3102     }
3103
3104   return last;
3105 }
3106
3107 /* Emit the insns in a chain starting with FIRST and place them in back of
3108    the insn AFTER.  Return the last insn emitted.  */
3109
3110 rtx
3111 emit_insns_after (first, after)
3112      register rtx first;
3113      register rtx after;
3114 {
3115   register rtx last;
3116   register rtx after_after;
3117
3118   if (!after)
3119     abort ();
3120
3121   if (!first)
3122     return first;
3123
3124   for (last = first; NEXT_INSN (last); last = NEXT_INSN (last))
3125     continue;
3126
3127   after_after = NEXT_INSN (after);
3128
3129   NEXT_INSN (after) = first;
3130   PREV_INSN (first) = after;
3131   NEXT_INSN (last) = after_after;
3132   if (after_after)
3133     PREV_INSN (after_after) = last;
3134
3135   if (after == last_insn)
3136     last_insn = last;
3137   return last;
3138 }
3139
3140 /* Make an insn of code JUMP_INSN with pattern PATTERN
3141    and add it to the end of the doubly-linked list.  */
3142
3143 rtx
3144 emit_jump_insn (pattern)
3145      rtx pattern;
3146 {
3147   if (GET_CODE (pattern) == SEQUENCE)
3148     return emit_insn (pattern);
3149   else
3150     {
3151       register rtx insn = make_jump_insn_raw (pattern);
3152       add_insn (insn);
3153       return insn;
3154     }
3155 }
3156
3157 /* Make an insn of code CALL_INSN with pattern PATTERN
3158    and add it to the end of the doubly-linked list.  */
3159
3160 rtx
3161 emit_call_insn (pattern)
3162      rtx pattern;
3163 {
3164   if (GET_CODE (pattern) == SEQUENCE)
3165     return emit_insn (pattern);
3166   else
3167     {
3168       register rtx insn = make_call_insn_raw (pattern);
3169       add_insn (insn);
3170       PUT_CODE (insn, CALL_INSN);
3171       return insn;
3172     }
3173 }
3174
3175 /* Add the label LABEL to the end of the doubly-linked list.  */
3176
3177 rtx
3178 emit_label (label)
3179      rtx label;
3180 {
3181   /* This can be called twice for the same label
3182      as a result of the confusion that follows a syntax error!
3183      So make it harmless.  */
3184   if (INSN_UID (label) == 0)
3185     {
3186       INSN_UID (label) = cur_insn_uid++;
3187       add_insn (label);
3188     }
3189   return label;
3190 }
3191
3192 /* Make an insn of code BARRIER
3193    and add it to the end of the doubly-linked list.  */
3194
3195 rtx
3196 emit_barrier ()
3197 {
3198   register rtx barrier = rtx_alloc (BARRIER);
3199   INSN_UID (barrier) = cur_insn_uid++;
3200   add_insn (barrier);
3201   return barrier;
3202 }
3203
3204 /* Make an insn of code NOTE
3205    with data-fields specified by FILE and LINE
3206    and add it to the end of the doubly-linked list,
3207    but only if line-numbers are desired for debugging info.  */
3208
3209 rtx
3210 emit_line_note (file, line)
3211      const char *file;
3212      int line;
3213 {
3214   set_file_and_line_for_stmt (file, line);
3215
3216 #if 0
3217   if (no_line_numbers)
3218     return 0;
3219 #endif
3220
3221   return emit_note (file, line);
3222 }
3223
3224 /* Make an insn of code NOTE
3225    with data-fields specified by FILE and LINE
3226    and add it to the end of the doubly-linked list.
3227    If it is a line-number NOTE, omit it if it matches the previous one.  */
3228
3229 rtx
3230 emit_note (file, line)
3231      const char *file;
3232      int line;
3233 {
3234   register rtx note;
3235
3236   if (line > 0)
3237     {
3238       if (file && last_filename && !strcmp (file, last_filename)
3239           && line == last_linenum)
3240         return 0;
3241       last_filename = file;
3242       last_linenum = line;
3243     }
3244
3245   if (no_line_numbers && line > 0)
3246     {
3247       cur_insn_uid++;
3248       return 0;
3249     }
3250
3251   note = rtx_alloc (NOTE);
3252   INSN_UID (note) = cur_insn_uid++;
3253   NOTE_SOURCE_FILE (note) = file;
3254   NOTE_LINE_NUMBER (note) = line;
3255   add_insn (note);
3256   return note;
3257 }
3258
3259 /* Emit a NOTE, and don't omit it even if LINE is the previous note.  */
3260
3261 rtx
3262 emit_line_note_force (file, line)
3263      const char *file;
3264      int line;
3265 {
3266   last_linenum = -1;
3267   return emit_line_note (file, line);
3268 }
3269
3270 /* Cause next statement to emit a line note even if the line number
3271    has not changed.  This is used at the beginning of a function.  */
3272
3273 void
3274 force_next_line_note ()
3275 {
3276   last_linenum = -1;
3277 }
3278
3279 /* Place a note of KIND on insn INSN with DATUM as the datum. If a
3280    note of this type already exists, remove it first. */
3281
3282 void
3283 set_unique_reg_note (insn, kind, datum)
3284      rtx insn;
3285      enum reg_note kind;
3286      rtx datum;
3287 {
3288   rtx note = find_reg_note (insn, kind, NULL_RTX);
3289
3290   /* First remove the note if there already is one.  */
3291   if (note)
3292     remove_note (insn, note);
3293
3294   REG_NOTES (insn) = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn));
3295 }
3296 \f
3297 /* Return an indication of which type of insn should have X as a body.
3298    The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN.  */
3299
3300 enum rtx_code
3301 classify_insn (x)
3302      rtx x;
3303 {
3304   if (GET_CODE (x) == CODE_LABEL)
3305     return CODE_LABEL;
3306   if (GET_CODE (x) == CALL)
3307     return CALL_INSN;
3308   if (GET_CODE (x) == RETURN)
3309     return JUMP_INSN;
3310   if (GET_CODE (x) == SET)
3311     {
3312       if (SET_DEST (x) == pc_rtx)
3313         return JUMP_INSN;
3314       else if (GET_CODE (SET_SRC (x)) == CALL)
3315         return CALL_INSN;
3316       else
3317         return INSN;
3318     }
3319   if (GET_CODE (x) == PARALLEL)
3320     {
3321       register int j;
3322       for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
3323         if (GET_CODE (XVECEXP (x, 0, j)) == CALL)
3324           return CALL_INSN;
3325         else if (GET_CODE (XVECEXP (x, 0, j)) == SET
3326                  && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx)
3327           return JUMP_INSN;
3328         else if (GET_CODE (XVECEXP (x, 0, j)) == SET
3329                  && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL)
3330           return CALL_INSN;
3331     }
3332   return INSN;
3333 }
3334
3335 /* Emit the rtl pattern X as an appropriate kind of insn.
3336    If X is a label, it is simply added into the insn chain.  */
3337
3338 rtx
3339 emit (x)
3340      rtx x;
3341 {
3342   enum rtx_code code = classify_insn (x);
3343
3344   if (code == CODE_LABEL)
3345     return emit_label (x);
3346   else if (code == INSN)
3347     return emit_insn (x);
3348   else if (code == JUMP_INSN)
3349     {
3350       register rtx insn = emit_jump_insn (x);
3351       if (simplejump_p (insn) || GET_CODE (x) == RETURN)
3352         return emit_barrier ();
3353       return insn;
3354     }
3355   else if (code == CALL_INSN)
3356     return emit_call_insn (x);
3357   else
3358     abort ();
3359 }
3360 \f
3361 /* Begin emitting insns to a sequence which can be packaged in an
3362    RTL_EXPR.  If this sequence will contain something that might cause
3363    the compiler to pop arguments to function calls (because those
3364    pops have previously been deferred; see INHIBIT_DEFER_POP for more
3365    details), use do_pending_stack_adjust before calling this function.
3366    That will ensure that the deferred pops are not accidentally
3367    emitted in the middel of this sequence.  */
3368
3369 void
3370 start_sequence ()
3371 {
3372   struct sequence_stack *tem;
3373
3374   tem = (struct sequence_stack *) xmalloc (sizeof (struct sequence_stack));
3375
3376   tem->next = seq_stack;
3377   tem->first = first_insn;
3378   tem->last = last_insn;
3379   tem->sequence_rtl_expr = seq_rtl_expr;
3380
3381   seq_stack = tem;
3382
3383   first_insn = 0;
3384   last_insn = 0;
3385 }
3386
3387 /* Similarly, but indicate that this sequence will be placed in T, an
3388    RTL_EXPR.  See the documentation for start_sequence for more
3389    information about how to use this function.  */
3390
3391 void
3392 start_sequence_for_rtl_expr (t)
3393      tree t;
3394 {
3395   start_sequence ();
3396
3397   seq_rtl_expr = t;
3398 }
3399
3400 /* Set up the insn chain starting with FIRST as the current sequence,
3401    saving the previously current one.  See the documentation for
3402    start_sequence for more information about how to use this function.  */
3403
3404 void
3405 push_to_sequence (first)
3406      rtx first;
3407 {
3408   rtx last;
3409
3410   start_sequence ();
3411
3412   for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last));
3413
3414   first_insn = first;
3415   last_insn = last;
3416 }
3417
3418 /* Set up the outer-level insn chain
3419    as the current sequence, saving the previously current one.  */
3420
3421 void
3422 push_topmost_sequence ()
3423 {
3424   struct sequence_stack *stack, *top = NULL;
3425
3426   start_sequence ();
3427
3428   for (stack = seq_stack; stack; stack = stack->next)
3429     top = stack;
3430
3431   first_insn = top->first;
3432   last_insn = top->last;
3433   seq_rtl_expr = top->sequence_rtl_expr;
3434 }
3435
3436 /* After emitting to the outer-level insn chain, update the outer-level
3437    insn chain, and restore the previous saved state.  */
3438
3439 void
3440 pop_topmost_sequence ()
3441 {
3442   struct sequence_stack *stack, *top = NULL;
3443
3444   for (stack = seq_stack; stack; stack = stack->next)
3445     top = stack;
3446
3447   top->first = first_insn;
3448   top->last = last_insn;
3449   /* ??? Why don't we save seq_rtl_expr here?  */
3450
3451   end_sequence ();
3452 }
3453
3454 /* After emitting to a sequence, restore previous saved state.
3455
3456    To get the contents of the sequence just made, you must call
3457    `gen_sequence' *before* calling here.
3458
3459    If the compiler might have deferred popping arguments while
3460    generating this sequence, and this sequence will not be immediately
3461    inserted into the instruction stream, use do_pending_stack_adjust
3462    before calling gen_sequence.  That will ensure that the deferred
3463    pops are inserted into this sequence, and not into some random
3464    location in the instruction stream.  See INHIBIT_DEFER_POP for more
3465    information about deferred popping of arguments.  */
3466
3467 void
3468 end_sequence ()
3469 {
3470   struct sequence_stack *tem = seq_stack;
3471
3472   first_insn = tem->first;
3473   last_insn = tem->last;
3474   seq_rtl_expr = tem->sequence_rtl_expr;
3475   seq_stack = tem->next;
3476
3477   free (tem);
3478 }
3479
3480 /* Return 1 if currently emitting into a sequence.  */
3481
3482 int
3483 in_sequence_p ()
3484 {
3485   return seq_stack != 0;
3486 }
3487
3488 /* Generate a SEQUENCE rtx containing the insns already emitted
3489    to the current sequence.
3490
3491    This is how the gen_... function from a DEFINE_EXPAND
3492    constructs the SEQUENCE that it returns.  */
3493
3494 rtx
3495 gen_sequence ()
3496 {
3497   rtx result;
3498   rtx tem;
3499   int i;
3500   int len;
3501
3502   /* Count the insns in the chain.  */
3503   len = 0;
3504   for (tem = first_insn; tem; tem = NEXT_INSN (tem))
3505     len++;
3506
3507   /* If only one insn, return it rather than a SEQUENCE.
3508      (Now that we cache SEQUENCE expressions, it isn't worth special-casing
3509      the case of an empty list.)
3510      We only return the pattern of an insn if its code is INSN and it
3511      has no notes.  This ensures that no information gets lost.  */
3512   if (len == 1
3513       && ! RTX_FRAME_RELATED_P (first_insn)
3514       && GET_CODE (first_insn) == INSN
3515       /* Don't throw away any reg notes. */
3516       && REG_NOTES (first_insn) == 0)
3517     {
3518       if (!ggc_p)
3519         {
3520           NEXT_INSN (first_insn) = free_insn;
3521           free_insn = first_insn;
3522         }
3523       return PATTERN (first_insn);
3524     }
3525
3526   /* Put them in a vector.  See if we already have a SEQUENCE of the
3527      appropriate length around.  */
3528   if (!ggc_p && len < SEQUENCE_RESULT_SIZE
3529       && (result = sequence_result[len]) != 0)
3530     sequence_result[len] = 0;
3531   else
3532     {
3533       /* Ensure that this rtl goes in saveable_obstack, since we may
3534          cache it.  */
3535       push_obstacks_nochange ();
3536       rtl_in_saveable_obstack ();
3537       result = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (len));
3538       pop_obstacks ();
3539     }
3540
3541   for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++)
3542     XVECEXP (result, 0, i) = tem;
3543
3544   return result;
3545 }
3546 \f
3547 /* Put the various virtual registers into REGNO_REG_RTX.  */
3548
3549 void
3550 init_virtual_regs (es)
3551      struct emit_status *es;
3552 {
3553   rtx *ptr = es->x_regno_reg_rtx;
3554   ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx;
3555   ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx;
3556   ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx;
3557   ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx;
3558   ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx;
3559 }
3560
3561 void
3562 clear_emit_caches ()
3563 {
3564   int i;
3565
3566   /* Clear the start_sequence/gen_sequence cache.  */
3567   for (i = 0; i < SEQUENCE_RESULT_SIZE; i++)
3568     sequence_result[i] = 0;
3569   free_insn = 0;
3570 }
3571 \f
3572 /* Used by copy_insn_1 to avoid copying SCRATCHes more than once.  */
3573 static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS];
3574 static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS];
3575 static int copy_insn_n_scratches;
3576
3577 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
3578    copied an ASM_OPERANDS.
3579    In that case, it is the original input-operand vector.  */
3580 static rtvec orig_asm_operands_vector;
3581
3582 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
3583    copied an ASM_OPERANDS.
3584    In that case, it is the copied input-operand vector.  */
3585 static rtvec copy_asm_operands_vector;
3586
3587 /* Likewise for the constraints vector.  */
3588 static rtvec orig_asm_constraints_vector;
3589 static rtvec copy_asm_constraints_vector;
3590
3591 /* Recursively create a new copy of an rtx for copy_insn.
3592    This function differs from copy_rtx in that it handles SCRATCHes and
3593    ASM_OPERANDs properly.
3594    Normally, this function is not used directly; use copy_insn as front end.
3595    However, you could first copy an insn pattern with copy_insn and then use
3596    this function afterwards to properly copy any REG_NOTEs containing
3597    SCRATCHes.  */
3598
3599 rtx
3600 copy_insn_1 (orig)
3601      register rtx orig;
3602 {
3603   register rtx copy;
3604   register int i, j;
3605   register RTX_CODE code;
3606   register const char *format_ptr;
3607
3608   code = GET_CODE (orig);
3609
3610   switch (code)
3611     {
3612     case REG:
3613     case QUEUED:
3614     case CONST_INT:
3615     case CONST_DOUBLE:
3616     case SYMBOL_REF:
3617     case CODE_LABEL:
3618     case PC:
3619     case CC0:
3620     case ADDRESSOF:
3621       return orig;
3622
3623     case SCRATCH:
3624       for (i = 0; i < copy_insn_n_scratches; i++)
3625         if (copy_insn_scratch_in[i] == orig)
3626           return copy_insn_scratch_out[i];
3627       break;
3628
3629     case CONST:
3630       /* CONST can be shared if it contains a SYMBOL_REF.  If it contains
3631          a LABEL_REF, it isn't sharable.  */
3632       if (GET_CODE (XEXP (orig, 0)) == PLUS
3633           && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
3634           && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
3635         return orig;
3636       break;
3637
3638       /* A MEM with a constant address is not sharable.  The problem is that
3639          the constant address may need to be reloaded.  If the mem is shared,
3640          then reloading one copy of this mem will cause all copies to appear
3641          to have been reloaded.  */
3642
3643     default:
3644       break;
3645     }
3646
3647   copy = rtx_alloc (code);
3648
3649   /* Copy the various flags, and other information.  We assume that
3650      all fields need copying, and then clear the fields that should
3651      not be copied.  That is the sensible default behavior, and forces
3652      us to explicitly document why we are *not* copying a flag.  */
3653   memcpy (copy, orig, sizeof (struct rtx_def) - sizeof (rtunion));
3654
3655   /* We do not copy the USED flag, which is used as a mark bit during
3656      walks over the RTL.  */
3657   copy->used = 0;
3658
3659   /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs.  */
3660   if (GET_RTX_CLASS (code) == 'i')
3661     {
3662       copy->jump = 0;
3663       copy->call = 0;
3664       copy->frame_related = 0;
3665     }
3666
3667   format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
3668
3669   for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
3670     {
3671       copy->fld[i] = orig->fld[i];
3672       switch (*format_ptr++)
3673         {
3674         case 'e':
3675           if (XEXP (orig, i) != NULL)
3676             XEXP (copy, i) = copy_insn_1 (XEXP (orig, i));
3677           break;
3678
3679         case 'E':
3680         case 'V':
3681           if (XVEC (orig, i) == orig_asm_constraints_vector)
3682             XVEC (copy, i) = copy_asm_constraints_vector;
3683           else if (XVEC (orig, i) == orig_asm_operands_vector)
3684             XVEC (copy, i) = copy_asm_operands_vector;
3685           else if (XVEC (orig, i) != NULL)
3686             {
3687               XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
3688               for (j = 0; j < XVECLEN (copy, i); j++)
3689                 XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j));
3690             }
3691           break;
3692
3693         case 'b':
3694           {
3695             bitmap new_bits = BITMAP_OBSTACK_ALLOC (rtl_obstack);
3696             bitmap_copy (new_bits, XBITMAP (orig, i));
3697             XBITMAP (copy, i) = new_bits;
3698             break;
3699           }
3700
3701         case 't':
3702         case 'w':
3703         case 'i':
3704         case 's':
3705         case 'S':
3706         case 'u':
3707         case '0':
3708           /* These are left unchanged.  */
3709           break;
3710
3711         default:
3712           abort ();
3713         }
3714     }
3715
3716   if (code == SCRATCH)
3717     {
3718       i = copy_insn_n_scratches++;
3719       if (i >= MAX_RECOG_OPERANDS)
3720         abort ();
3721       copy_insn_scratch_in[i] = orig;
3722       copy_insn_scratch_out[i] = copy;
3723     }
3724   else if (code == ASM_OPERANDS)
3725     {
3726       orig_asm_operands_vector = XVEC (orig, 3);
3727       copy_asm_operands_vector = XVEC (copy, 3);
3728       orig_asm_constraints_vector = XVEC (orig, 4);
3729       copy_asm_constraints_vector = XVEC (copy, 4);
3730     }
3731
3732   return copy;
3733 }
3734
3735 /* Create a new copy of an rtx.
3736    This function differs from copy_rtx in that it handles SCRATCHes and
3737    ASM_OPERANDs properly.
3738    INSN doesn't really have to be a full INSN; it could be just the
3739    pattern.  */
3740 rtx
3741 copy_insn (insn)
3742      rtx insn;
3743 {
3744   copy_insn_n_scratches = 0;
3745   orig_asm_operands_vector = 0;
3746   orig_asm_constraints_vector = 0;
3747   copy_asm_operands_vector = 0;
3748   copy_asm_constraints_vector = 0;
3749   return copy_insn_1 (insn);
3750 }
3751
3752 /* Initialize data structures and variables in this file
3753    before generating rtl for each function.  */
3754
3755 void
3756 init_emit ()
3757 {
3758   struct function *f = cfun;
3759
3760   f->emit = (struct emit_status *) xmalloc (sizeof (struct emit_status));
3761   first_insn = NULL;
3762   last_insn = NULL;
3763   seq_rtl_expr = NULL;
3764   cur_insn_uid = 1;
3765   reg_rtx_no = LAST_VIRTUAL_REGISTER + 1;
3766   last_linenum = 0;
3767   last_filename = 0;
3768   first_label_num = label_num;
3769   last_label_num = 0;
3770   seq_stack = NULL;
3771
3772   clear_emit_caches ();
3773
3774   /* Init the tables that describe all the pseudo regs.  */
3775
3776   f->emit->regno_pointer_flag_length = LAST_VIRTUAL_REGISTER + 101;
3777
3778   f->emit->regno_pointer_flag
3779     = (char *) xcalloc (f->emit->regno_pointer_flag_length, sizeof (char));
3780
3781   f->emit->regno_pointer_align
3782     = (char *) xcalloc (f->emit->regno_pointer_flag_length,
3783                         sizeof (char));
3784
3785   regno_reg_rtx
3786     = (rtx *) xcalloc (f->emit->regno_pointer_flag_length * sizeof (rtx),
3787                        sizeof (rtx));
3788
3789   /* Put copies of all the virtual register rtx into regno_reg_rtx.  */
3790   init_virtual_regs (f->emit);
3791
3792   /* Indicate that the virtual registers and stack locations are
3793      all pointers.  */
3794   REGNO_POINTER_FLAG (STACK_POINTER_REGNUM) = 1;
3795   REGNO_POINTER_FLAG (FRAME_POINTER_REGNUM) = 1;
3796   REGNO_POINTER_FLAG (HARD_FRAME_POINTER_REGNUM) = 1;
3797   REGNO_POINTER_FLAG (ARG_POINTER_REGNUM) = 1;
3798
3799   REGNO_POINTER_FLAG (VIRTUAL_INCOMING_ARGS_REGNUM) = 1;
3800   REGNO_POINTER_FLAG (VIRTUAL_STACK_VARS_REGNUM) = 1;
3801   REGNO_POINTER_FLAG (VIRTUAL_STACK_DYNAMIC_REGNUM) = 1;
3802   REGNO_POINTER_FLAG (VIRTUAL_OUTGOING_ARGS_REGNUM) = 1;
3803   REGNO_POINTER_FLAG (VIRTUAL_CFA_REGNUM) = 1;
3804
3805 #ifdef STACK_BOUNDARY
3806   REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY / BITS_PER_UNIT;
3807   REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY / BITS_PER_UNIT;
3808   REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM)
3809     = STACK_BOUNDARY / BITS_PER_UNIT;
3810   REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY / BITS_PER_UNIT;
3811
3812   REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM)
3813     = STACK_BOUNDARY / BITS_PER_UNIT;
3814   REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM)
3815     = STACK_BOUNDARY / BITS_PER_UNIT;
3816   REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM)
3817     = STACK_BOUNDARY / BITS_PER_UNIT;
3818   REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM)
3819     = STACK_BOUNDARY / BITS_PER_UNIT;
3820   REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = UNITS_PER_WORD;
3821 #endif
3822
3823 #ifdef INIT_EXPANDERS
3824   INIT_EXPANDERS;
3825 #endif
3826 }
3827
3828 /* Mark SS for GC.  */
3829
3830 static void
3831 mark_sequence_stack (ss)
3832      struct sequence_stack *ss;
3833 {
3834   while (ss)
3835     {
3836       ggc_mark_rtx (ss->first);
3837       ggc_mark_tree (ss->sequence_rtl_expr);
3838       ss = ss->next;
3839     }
3840 }
3841
3842 /* Mark ES for GC.  */
3843
3844 void
3845 mark_emit_status (es)
3846      struct emit_status *es;
3847 {
3848   rtx *r;
3849   int i;
3850
3851   if (es == 0)
3852     return;
3853
3854   for (i = es->regno_pointer_flag_length, r = es->x_regno_reg_rtx;
3855        i > 0; --i, ++r)
3856     ggc_mark_rtx (*r);
3857
3858   mark_sequence_stack (es->sequence_stack);
3859   ggc_mark_tree (es->sequence_rtl_expr);
3860   ggc_mark_rtx (es->x_first_insn);
3861 }
3862
3863 /* Create some permanent unique rtl objects shared between all functions.
3864    LINE_NUMBERS is nonzero if line numbers are to be generated.  */
3865
3866 void
3867 init_emit_once (line_numbers)
3868      int line_numbers;
3869 {
3870   int i;
3871   enum machine_mode mode;
3872   enum machine_mode double_mode;
3873
3874   no_line_numbers = ! line_numbers;
3875
3876   /* Compute the word and byte modes.  */
3877
3878   byte_mode = VOIDmode;
3879   word_mode = VOIDmode;
3880   double_mode = VOIDmode;
3881
3882   for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
3883        mode = GET_MODE_WIDER_MODE (mode))
3884     {
3885       if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT
3886           && byte_mode == VOIDmode)
3887         byte_mode = mode;
3888
3889       if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD
3890           && word_mode == VOIDmode)
3891         word_mode = mode;
3892     }
3893
3894 #ifndef DOUBLE_TYPE_SIZE
3895 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
3896 #endif
3897
3898   for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode;
3899        mode = GET_MODE_WIDER_MODE (mode))
3900     {
3901       if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE
3902           && double_mode == VOIDmode)
3903         double_mode = mode;
3904     }
3905
3906   ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0);
3907
3908   /* Assign register numbers to the globally defined register rtx.
3909      This must be done at runtime because the register number field
3910      is in a union and some compilers can't initialize unions.  */
3911
3912   pc_rtx = gen_rtx (PC, VOIDmode);
3913   cc0_rtx = gen_rtx (CC0, VOIDmode);
3914   stack_pointer_rtx = gen_rtx_raw_REG (Pmode, STACK_POINTER_REGNUM);
3915   frame_pointer_rtx = gen_rtx_raw_REG (Pmode, FRAME_POINTER_REGNUM);
3916   if (hard_frame_pointer_rtx == 0)
3917     hard_frame_pointer_rtx = gen_rtx_raw_REG (Pmode,
3918                                               HARD_FRAME_POINTER_REGNUM);
3919   if (arg_pointer_rtx == 0)
3920     arg_pointer_rtx = gen_rtx_raw_REG (Pmode, ARG_POINTER_REGNUM);
3921   virtual_incoming_args_rtx =
3922     gen_rtx_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM);
3923   virtual_stack_vars_rtx =
3924     gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM);
3925   virtual_stack_dynamic_rtx =
3926     gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM);
3927   virtual_outgoing_args_rtx =
3928     gen_rtx_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM);
3929   virtual_cfa_rtx = gen_rtx_raw_REG (Pmode, VIRTUAL_CFA_REGNUM);
3930
3931   /* These rtx must be roots if GC is enabled.  */
3932   if (ggc_p)
3933     ggc_add_rtx_root (global_rtl, GR_MAX);
3934
3935 #ifdef INIT_EXPANDERS
3936   /* This is to initialize save_machine_status and restore_machine_status before
3937      the first call to push_function_context_to.  This is needed by the Chill
3938      front end which calls push_function_context_to before the first cal to
3939      init_function_start.  */
3940   INIT_EXPANDERS;
3941 #endif
3942
3943   /* Create the unique rtx's for certain rtx codes and operand values.  */
3944
3945   /* Don't use gen_rtx here since gen_rtx in this case
3946      tries to use these variables.  */
3947   for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++)
3948     const_int_rtx[i + MAX_SAVED_CONST_INT] =
3949       gen_rtx_raw_CONST_INT (VOIDmode, i);
3950   if (ggc_p)
3951     ggc_add_rtx_root (const_int_rtx, 2 * MAX_SAVED_CONST_INT + 1);
3952
3953   if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT
3954       && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT)
3955     const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT];
3956   else
3957     const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE);
3958
3959   dconst0 = REAL_VALUE_ATOF ("0", double_mode);
3960   dconst1 = REAL_VALUE_ATOF ("1", double_mode);
3961   dconst2 = REAL_VALUE_ATOF ("2", double_mode);
3962   dconstm1 = REAL_VALUE_ATOF ("-1", double_mode);
3963
3964   for (i = 0; i <= 2; i++)
3965     {
3966       for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode;
3967            mode = GET_MODE_WIDER_MODE (mode))
3968         {
3969           rtx tem = rtx_alloc (CONST_DOUBLE);
3970           union real_extract u;
3971
3972           bzero ((char *) &u, sizeof u);  /* Zero any holes in a structure.  */
3973           u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2;
3974
3975           bcopy ((char *) &u, (char *) &CONST_DOUBLE_LOW (tem), sizeof u);
3976           CONST_DOUBLE_MEM (tem) = cc0_rtx;
3977           PUT_MODE (tem, mode);
3978
3979           const_tiny_rtx[i][(int) mode] = tem;
3980         }
3981
3982       const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i);
3983
3984       for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
3985            mode = GET_MODE_WIDER_MODE (mode))
3986         const_tiny_rtx[i][(int) mode] = GEN_INT (i);
3987
3988       for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT);
3989            mode != VOIDmode;
3990            mode = GET_MODE_WIDER_MODE (mode))
3991         const_tiny_rtx[i][(int) mode] = GEN_INT (i);
3992     }
3993
3994   for (mode = CCmode; mode < MAX_MACHINE_MODE; ++mode)
3995     if (GET_MODE_CLASS (mode) == MODE_CC)
3996       const_tiny_rtx[0][(int) mode] = const0_rtx;
3997
3998   ggc_add_rtx_root (&const_tiny_rtx[0][0], sizeof(const_tiny_rtx)/sizeof(rtx));
3999   ggc_add_rtx_root (&const_true_rtx, 1);
4000
4001 #ifdef RETURN_ADDRESS_POINTER_REGNUM
4002   return_address_pointer_rtx
4003     = gen_rtx_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM);
4004 #endif
4005
4006 #ifdef STRUCT_VALUE
4007   struct_value_rtx = STRUCT_VALUE;
4008 #else
4009   struct_value_rtx = gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM);
4010 #endif
4011
4012 #ifdef STRUCT_VALUE_INCOMING
4013   struct_value_incoming_rtx = STRUCT_VALUE_INCOMING;
4014 #else
4015 #ifdef STRUCT_VALUE_INCOMING_REGNUM
4016   struct_value_incoming_rtx
4017     = gen_rtx_REG (Pmode, STRUCT_VALUE_INCOMING_REGNUM);
4018 #else
4019   struct_value_incoming_rtx = struct_value_rtx;
4020 #endif
4021 #endif
4022
4023 #ifdef STATIC_CHAIN_REGNUM
4024   static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
4025
4026 #ifdef STATIC_CHAIN_INCOMING_REGNUM
4027   if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM)
4028     static_chain_incoming_rtx
4029       = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM);
4030   else
4031 #endif
4032     static_chain_incoming_rtx = static_chain_rtx;
4033 #endif
4034
4035 #ifdef STATIC_CHAIN
4036   static_chain_rtx = STATIC_CHAIN;
4037
4038 #ifdef STATIC_CHAIN_INCOMING
4039   static_chain_incoming_rtx = STATIC_CHAIN_INCOMING;
4040 #else
4041   static_chain_incoming_rtx = static_chain_rtx;
4042 #endif
4043 #endif
4044
4045 #ifdef PIC_OFFSET_TABLE_REGNUM
4046   pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
4047 #endif
4048
4049   ggc_add_rtx_root (&pic_offset_table_rtx, 1);
4050   ggc_add_rtx_root (&struct_value_rtx, 1);
4051   ggc_add_rtx_root (&struct_value_incoming_rtx, 1);
4052   ggc_add_rtx_root (&static_chain_rtx, 1);
4053   ggc_add_rtx_root (&static_chain_incoming_rtx, 1);
4054   ggc_add_rtx_root (&return_address_pointer_rtx, 1);
4055 }
4056 \f
4057 /* Query and clear/ restore no_line_numbers.  This is used by the
4058    switch / case handling in stmt.c to give proper line numbers in
4059    warnings about unreachable code.  */
4060
4061 int
4062 force_line_numbers ()
4063 {
4064   int old = no_line_numbers;
4065
4066   no_line_numbers = 0;
4067   if (old)
4068     force_next_line_note ();
4069   return old;
4070 }
4071
4072 void
4073 restore_line_number_status (old_value)
4074      int old_value;
4075 {
4076   no_line_numbers = old_value;
4077 }