1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Define an insn type attribute. This is used in function unit delay
27 (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
28 (const_string "integer"))
31 (define_attr "length" ""
32 (if_then_else (eq_attr "type" "branch")
33 (if_then_else (and (ge (minus (pc) (match_dup 0))
35 (lt (minus (pc) (match_dup 0))
41 ;; Processor type -- this attribute must exactly match the processor_type
42 ;; enumeration in rs6000.h.
44 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"
45 (const (symbol_ref "rs6000_cpu_attr")))
47 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
48 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
50 ; Load/Store Unit -- pure PowerPC only
51 ; (POWER and 601 use Integer Unit)
52 (define_function_unit "lsu" 1 0
53 (and (eq_attr "type" "load")
54 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
57 (define_function_unit "lsu" 1 0
58 (and (eq_attr "type" "store,fpstore")
59 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
62 (define_function_unit "lsu" 1 0
63 (and (eq_attr "type" "fpload")
64 (eq_attr "cpu" "mpccore,ppc603,ppc750"))
67 (define_function_unit "lsu" 1 0
68 (and (eq_attr "type" "fpload")
69 (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630"))
72 (define_function_unit "iu" 1 0
73 (and (eq_attr "type" "load")
74 (eq_attr "cpu" "rios1,ppc403,ppc601"))
77 (define_function_unit "iu" 1 0
78 (and (eq_attr "type" "store,fpstore")
79 (eq_attr "cpu" "rios1,ppc403,ppc601"))
82 (define_function_unit "fpu" 1 0
83 (and (eq_attr "type" "fpstore")
84 (eq_attr "cpu" "rios1,ppc601"))
87 (define_function_unit "iu" 1 0
88 (and (eq_attr "type" "fpload")
89 (eq_attr "cpu" "rios1"))
92 (define_function_unit "iu" 1 0
93 (and (eq_attr "type" "fpload")
94 (eq_attr "cpu" "ppc601"))
97 (define_function_unit "iu2" 2 0
98 (and (eq_attr "type" "load,fpload")
99 (eq_attr "cpu" "rios2"))
102 (define_function_unit "iu2" 2 0
103 (and (eq_attr "type" "store,fpstore")
104 (eq_attr "cpu" "rios2"))
107 ; Integer Unit (RIOS1, PPC601, PPC603, RS64a)
108 (define_function_unit "iu" 1 0
109 (and (eq_attr "type" "integer")
110 (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603"))
113 (define_function_unit "iu" 1 0
114 (and (eq_attr "type" "imul")
115 (eq_attr "cpu" "ppc403"))
118 (define_function_unit "iu" 1 0
119 (and (eq_attr "type" "imul")
120 (eq_attr "cpu" "rios1,ppc601,ppc603"))
123 (define_function_unit "iu" 1 0
124 (and (eq_attr "type" "imul")
125 (eq_attr "cpu" "rs64a"))
128 (define_function_unit "iu" 1 0
129 (and (eq_attr "type" "lmul")
130 (eq_attr "cpu" "rs64a"))
133 (define_function_unit "iu" 1 0
134 (and (eq_attr "type" "idiv")
135 (eq_attr "cpu" "rios1"))
138 (define_function_unit "iu" 1 0
139 (and (eq_attr "type" "idiv")
140 (eq_attr "cpu" "rs64a"))
143 (define_function_unit "iu" 1 0
144 (and (eq_attr "type" "ldiv")
145 (eq_attr "cpu" "rs64a"))
148 (define_function_unit "iu" 1 0
149 (and (eq_attr "type" "idiv")
150 (eq_attr "cpu" "ppc403"))
153 (define_function_unit "iu" 1 0
154 (and (eq_attr "type" "idiv")
155 (eq_attr "cpu" "ppc601"))
158 (define_function_unit "iu" 1 0
159 (and (eq_attr "type" "idiv")
160 (eq_attr "cpu" "ppc603"))
163 ; RIOS2 has two integer units: a primary one which can perform all
164 ; operations and a secondary one which is fed in lock step with the first
165 ; and can perform "simple" integer operations.
166 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
167 ; for the complex insns.
168 (define_function_unit "iu2" 2 0
169 (and (eq_attr "type" "integer")
170 (eq_attr "cpu" "rios2"))
173 (define_function_unit "iu2" 2 0
174 (and (eq_attr "type" "imul")
175 (eq_attr "cpu" "rios2"))
178 (define_function_unit "iu2" 2 0
179 (and (eq_attr "type" "idiv")
180 (eq_attr "cpu" "rios2"))
183 (define_function_unit "imuldiv" 1 0
184 (and (eq_attr "type" "imul")
185 (eq_attr "cpu" "rios2"))
188 (define_function_unit "imuldiv" 1 0
189 (and (eq_attr "type" "idiv")
190 (eq_attr "cpu" "rios2"))
193 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
194 ; Divide latency varies greatly from 2-11, use 6 as average
195 (define_function_unit "imuldiv" 1 0
196 (and (eq_attr "type" "imul")
197 (eq_attr "cpu" "mpccore"))
200 (define_function_unit "imuldiv" 1 0
201 (and (eq_attr "type" "idiv")
202 (eq_attr "cpu" "mpccore"))
205 ; PPC604{,e} has two units that perform integer operations
206 ; and one unit for divide/multiply operations (and move
208 (define_function_unit "iu2" 2 0
209 (and (eq_attr "type" "integer")
210 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
213 (define_function_unit "imuldiv" 1 0
214 (and (eq_attr "type" "imul")
215 (eq_attr "cpu" "ppc604"))
218 (define_function_unit "imuldiv" 1 0
219 (and (eq_attr "type" "imul")
220 (eq_attr "cpu" "ppc620,ppc630"))
223 (define_function_unit "imuldiv" 1 0
224 (and (eq_attr "type" "lmul")
225 (eq_attr "cpu" "ppc620,ppc630"))
228 (define_function_unit "imuldiv" 1 0
229 (and (eq_attr "type" "imul")
230 (eq_attr "cpu" "ppc604e"))
233 (define_function_unit "imuldiv" 1 0
234 (and (eq_attr "type" "idiv")
235 (eq_attr "cpu" "ppc604,ppc604e"))
238 (define_function_unit "imuldiv" 1 0
239 (and (eq_attr "type" "idiv")
240 (eq_attr "cpu" "ppc620"))
243 (define_function_unit "imuldiv" 1 0
244 (and (eq_attr "type" "idiv")
245 (eq_attr "cpu" "ppc630"))
248 (define_function_unit "imuldiv" 1 0
249 (and (eq_attr "type" "ldiv")
250 (eq_attr "cpu" "ppc620,ppc630"))
253 ; PPC750 has two integer units: a primary one which can perform all
254 ; operations and a secondary one which is fed in lock step with the first
255 ; and can perform "simple" integer operations.
256 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
257 ; for the complex insns.
258 (define_function_unit "iu2" 2 0
259 (and (eq_attr "type" "integer")
260 (eq_attr "cpu" "ppc750"))
263 (define_function_unit "iu2" 2 0
264 (and (eq_attr "type" "imul")
265 (eq_attr "cpu" "ppc750"))
268 (define_function_unit "imuldiv" 1 0
269 (and (eq_attr "type" "imul")
270 (eq_attr "cpu" "ppc750"))
273 (define_function_unit "imuldiv" 1 0
274 (and (eq_attr "type" "idiv")
275 (eq_attr "cpu" "ppc750"))
278 ; compare is done on integer unit, but feeds insns which
279 ; execute on the branch unit.
280 (define_function_unit "iu" 1 0
281 (and (eq_attr "type" "compare")
282 (eq_attr "cpu" "rios1"))
285 (define_function_unit "iu" 1 0
286 (and (eq_attr "type" "delayed_compare")
287 (eq_attr "cpu" "rios1"))
290 (define_function_unit "iu" 1 0
291 (and (eq_attr "type" "compare,delayed_compare")
292 (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
295 (define_function_unit "iu2" 2 0
296 (and (eq_attr "type" "compare,delayed_compare")
297 (eq_attr "cpu" "rios2"))
300 (define_function_unit "iu2" 2 0
301 (and (eq_attr "type" "compare,delayed_compare")
302 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750"))
305 ; fp compare uses fp unit
306 (define_function_unit "fpu" 1 0
307 (and (eq_attr "type" "fpcompare")
308 (eq_attr "cpu" "rios1"))
311 ; rios1 and rios2 have different fpcompare delays
312 (define_function_unit "fpu2" 2 0
313 (and (eq_attr "type" "fpcompare")
314 (eq_attr "cpu" "rios2,ppc630"))
317 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
319 ; here we do not define delays, just occupy the unit. The dependencies
320 ; will be assigned by the fpcompare definition in the fpu.
321 (define_function_unit "iu" 1 0
322 (and (eq_attr "type" "fpcompare")
323 (eq_attr "cpu" "ppc601,ppc603"))
326 ; fp compare uses fp unit
327 (define_function_unit "fpu" 1 0
328 (and (eq_attr "type" "fpcompare")
329 (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
332 (define_function_unit "fpu" 1 0
333 (and (eq_attr "type" "fpcompare")
334 (eq_attr "cpu" "mpccore"))
337 (define_function_unit "bpu" 1 0
338 (and (eq_attr "type" "mtjmpr")
339 (eq_attr "cpu" "rios1,rios2,rs64a"))
342 (define_function_unit "bpu" 1 0
343 (and (eq_attr "type" "mtjmpr")
344 (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
347 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
348 (define_function_unit "bpu" 1 0
349 (eq_attr "type" "jmpreg")
352 (define_function_unit "bpu" 1 0
353 (eq_attr "type" "branch")
356 ; Floating Point Unit
357 (define_function_unit "fpu" 1 0
358 (and (eq_attr "type" "fp,dmul")
359 (eq_attr "cpu" "rios1"))
362 (define_function_unit "fpu" 1 0
363 (and (eq_attr "type" "fp")
364 (eq_attr "cpu" "rs64a,mpccore"))
367 (define_function_unit "fpu" 1 0
368 (and (eq_attr "type" "fp")
369 (eq_attr "cpu" "ppc601"))
372 (define_function_unit "fpu" 1 0
373 (and (eq_attr "type" "fp")
374 (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620"))
377 (define_function_unit "fpu" 1 0
378 (and (eq_attr "type" "dmul")
379 (eq_attr "cpu" "rs64a"))
382 (define_function_unit "fpu" 1 0
383 (and (eq_attr "type" "dmul")
384 (eq_attr "cpu" "mpccore"))
387 (define_function_unit "fpu" 1 0
388 (and (eq_attr "type" "dmul")
389 (eq_attr "cpu" "ppc601"))
393 (define_function_unit "fpu" 1 0
394 (and (eq_attr "type" "dmul")
395 (eq_attr "cpu" "ppc603,ppc750"))
398 (define_function_unit "fpu" 1 0
399 (and (eq_attr "type" "dmul")
400 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
403 (define_function_unit "fpu" 1 0
404 (and (eq_attr "type" "sdiv,ddiv")
405 (eq_attr "cpu" "rios1"))
408 (define_function_unit "fpu" 1 0
409 (and (eq_attr "type" "sdiv")
410 (eq_attr "cpu" "rs64a"))
413 (define_function_unit "fpu" 1 0
414 (and (eq_attr "type" "sdiv")
415 (eq_attr "cpu" "ppc601"))
418 (define_function_unit "fpu" 1 0
419 (and (eq_attr "type" "sdiv")
420 (eq_attr "cpu" "mpccore"))
423 (define_function_unit "fpu" 1 0
424 (and (eq_attr "type" "sdiv")
425 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620"))
428 (define_function_unit "fpu" 1 0
429 (and (eq_attr "type" "ddiv")
430 (eq_attr "cpu" "mpccore"))
433 (define_function_unit "fpu" 1 0
434 (and (eq_attr "type" "ddiv")
435 (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620"))
438 (define_function_unit "fpu" 1 0
439 (and (eq_attr "type" "ddiv")
440 (eq_attr "cpu" "ppc603"))
443 (define_function_unit "fpu" 1 0
444 (and (eq_attr "type" "ssqrt")
445 (eq_attr "cpu" "ppc620"))
448 (define_function_unit "fpu" 1 0
449 (and (eq_attr "type" "dsqrt")
450 (eq_attr "cpu" "ppc620"))
453 ; RIOS2 has two symmetric FPUs.
454 (define_function_unit "fpu2" 2 0
455 (and (eq_attr "type" "fp")
456 (eq_attr "cpu" "rios2"))
459 (define_function_unit "fpu2" 2 0
460 (and (eq_attr "type" "fp")
461 (eq_attr "cpu" "ppc630"))
464 (define_function_unit "fpu2" 2 0
465 (and (eq_attr "type" "dmul")
466 (eq_attr "cpu" "rios2"))
469 (define_function_unit "fpu2" 2 0
470 (and (eq_attr "type" "dmul")
471 (eq_attr "cpu" "ppc630"))
474 (define_function_unit "fpu2" 2 0
475 (and (eq_attr "type" "sdiv,ddiv")
476 (eq_attr "cpu" "rios2"))
479 (define_function_unit "fpu2" 2 0
480 (and (eq_attr "type" "sdiv")
481 (eq_attr "cpu" "ppc630"))
484 (define_function_unit "fpu2" 2 0
485 (and (eq_attr "type" "ddiv")
486 (eq_attr "cpu" "ppc630"))
489 (define_function_unit "fpu2" 2 0
490 (and (eq_attr "type" "ssqrt,dsqrt")
491 (eq_attr "cpu" "rios2"))
494 (define_function_unit "fpu2" 2 0
495 (and (eq_attr "type" "ssqrt")
496 (eq_attr "cpu" "ppc630"))
499 (define_function_unit "fpu2" 2 0
500 (and (eq_attr "type" "dsqrt")
501 (eq_attr "cpu" "ppc630"))
505 ;; Start with fixed-point load and store insns. Here we put only the more
506 ;; complex forms. Basic data transfer is done later.
508 (define_expand "zero_extendqidi2"
509 [(set (match_operand:DI 0 "gpc_reg_operand" "")
510 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
515 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
516 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
521 [(set_attr "type" "load,*")])
524 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
525 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
527 (clobber (match_scratch:DI 2 "=r"))]
530 [(set_attr "type" "compare")])
533 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
534 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
536 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
537 (zero_extend:DI (match_dup 1)))]
540 [(set_attr "type" "compare")])
542 (define_insn "extendqidi2"
543 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
544 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
549 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
550 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
552 (clobber (match_scratch:DI 2 "=r"))]
555 [(set_attr "type" "compare")])
558 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
559 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
561 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
562 (sign_extend:DI (match_dup 1)))]
565 [(set_attr "type" "compare")])
567 (define_expand "zero_extendhidi2"
568 [(set (match_operand:DI 0 "gpc_reg_operand" "")
569 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
574 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
575 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
580 [(set_attr "type" "load,*")])
583 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
584 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
586 (clobber (match_scratch:DI 2 "=r"))]
589 [(set_attr "type" "compare")])
592 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
593 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
595 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
596 (zero_extend:DI (match_dup 1)))]
599 [(set_attr "type" "compare")])
601 (define_expand "extendhidi2"
602 [(set (match_operand:DI 0 "gpc_reg_operand" "")
603 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
608 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
609 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
614 [(set_attr "type" "load,*")])
617 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
618 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
620 (clobber (match_scratch:DI 2 "=r"))]
623 [(set_attr "type" "compare")])
626 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
627 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
629 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
630 (sign_extend:DI (match_dup 1)))]
633 [(set_attr "type" "compare")])
635 (define_expand "zero_extendsidi2"
636 [(set (match_operand:DI 0 "gpc_reg_operand" "")
637 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
642 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
643 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
648 [(set_attr "type" "load,*")])
651 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
652 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
654 (clobber (match_scratch:DI 2 "=r"))]
657 [(set_attr "type" "compare")])
660 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
661 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
663 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
664 (zero_extend:DI (match_dup 1)))]
667 [(set_attr "type" "compare")])
669 (define_expand "extendsidi2"
670 [(set (match_operand:DI 0 "gpc_reg_operand" "")
671 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
676 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
677 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
682 [(set_attr "type" "load,*")])
685 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
686 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
688 (clobber (match_scratch:DI 2 "=r"))]
691 [(set_attr "type" "compare")])
694 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
695 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
697 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
698 (sign_extend:DI (match_dup 1)))]
701 [(set_attr "type" "compare")])
703 (define_expand "zero_extendqisi2"
704 [(set (match_operand:SI 0 "gpc_reg_operand" "")
705 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
710 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
711 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
715 {rlinm|rlwinm} %0,%1,0,0xff"
716 [(set_attr "type" "load,*")])
719 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
720 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
722 (clobber (match_scratch:SI 2 "=r"))]
724 "{andil.|andi.} %2,%1,0xff"
725 [(set_attr "type" "compare")])
728 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
729 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
731 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
732 (zero_extend:SI (match_dup 1)))]
734 "{andil.|andi.} %0,%1,0xff"
735 [(set_attr "type" "compare")])
737 (define_expand "extendqisi2"
738 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
739 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
744 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
745 else if (TARGET_POWER)
746 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
748 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
752 (define_insn "extendqisi2_ppc"
753 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
754 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
759 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
760 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
762 (clobber (match_scratch:SI 2 "=r"))]
765 [(set_attr "type" "compare")])
768 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
769 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
771 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
772 (sign_extend:SI (match_dup 1)))]
775 [(set_attr "type" "compare")])
777 (define_expand "extendqisi2_power"
778 [(parallel [(set (match_dup 2)
779 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
781 (clobber (scratch:SI))])
782 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
783 (ashiftrt:SI (match_dup 2)
785 (clobber (scratch:SI))])]
788 { operands[1] = gen_lowpart (SImode, operands[1]);
789 operands[2] = gen_reg_rtx (SImode); }")
791 (define_expand "extendqisi2_no_power"
793 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
795 (set (match_operand:SI 0 "gpc_reg_operand" "")
796 (ashiftrt:SI (match_dup 2)
798 "! TARGET_POWER && ! TARGET_POWERPC"
800 { operands[1] = gen_lowpart (SImode, operands[1]);
801 operands[2] = gen_reg_rtx (SImode); }")
803 (define_expand "zero_extendqihi2"
804 [(set (match_operand:HI 0 "gpc_reg_operand" "")
805 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
810 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
811 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
815 {rlinm|rlwinm} %0,%1,0,0xff"
816 [(set_attr "type" "load,*")])
819 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
820 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
822 (clobber (match_scratch:HI 2 "=r"))]
824 "{andil.|andi.} %2,%1,0xff"
825 [(set_attr "type" "compare")])
828 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
829 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
831 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
832 (zero_extend:HI (match_dup 1)))]
834 "{andil.|andi.} %0,%1,0xff"
835 [(set_attr "type" "compare")])
837 (define_expand "extendqihi2"
838 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
839 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
844 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
845 else if (TARGET_POWER)
846 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
848 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
852 (define_insn "extendqihi2_ppc"
853 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
854 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
859 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
860 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
862 (clobber (match_scratch:HI 2 "=r"))]
865 [(set_attr "type" "compare")])
868 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
869 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
871 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
872 (sign_extend:HI (match_dup 1)))]
875 [(set_attr "type" "compare")])
877 (define_expand "extendqihi2_power"
878 [(parallel [(set (match_dup 2)
879 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
881 (clobber (scratch:SI))])
882 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
883 (ashiftrt:SI (match_dup 2)
885 (clobber (scratch:SI))])]
888 { operands[0] = gen_lowpart (SImode, operands[0]);
889 operands[1] = gen_lowpart (SImode, operands[1]);
890 operands[2] = gen_reg_rtx (SImode); }")
892 (define_expand "extendqihi2_no_power"
894 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
896 (set (match_operand:HI 0 "gpc_reg_operand" "")
897 (ashiftrt:SI (match_dup 2)
899 "! TARGET_POWER && ! TARGET_POWERPC"
901 { operands[0] = gen_lowpart (SImode, operands[0]);
902 operands[1] = gen_lowpart (SImode, operands[1]);
903 operands[2] = gen_reg_rtx (SImode); }")
905 (define_expand "zero_extendhisi2"
906 [(set (match_operand:SI 0 "gpc_reg_operand" "")
907 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
912 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
913 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
917 {rlinm|rlwinm} %0,%1,0,0xffff"
918 [(set_attr "type" "load,*")])
921 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
922 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
924 (clobber (match_scratch:SI 2 "=r"))]
926 "{andil.|andi.} %2,%1,0xffff"
927 [(set_attr "type" "compare")])
930 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
931 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
933 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
934 (zero_extend:SI (match_dup 1)))]
936 "{andil.|andi.} %0,%1,0xffff"
937 [(set_attr "type" "compare")])
939 (define_expand "extendhisi2"
940 [(set (match_operand:SI 0 "gpc_reg_operand" "")
941 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
947 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
952 [(set_attr "type" "load,*")])
955 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
956 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
958 (clobber (match_scratch:SI 2 "=r"))]
960 "{exts.|extsh.} %2,%1"
961 [(set_attr "type" "compare")])
964 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
965 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
967 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
968 (sign_extend:SI (match_dup 1)))]
970 "{exts.|extsh.} %0,%1"
971 [(set_attr "type" "compare")])
973 ;; Fixed-point arithmetic insns.
975 ;; Discourage ai/addic because of carry but provide it in an alternative
976 ;; allowing register zero as source.
977 (define_expand "addsi3"
978 [(set (match_operand:SI 0 "gpc_reg_operand" "")
979 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
980 (match_operand:SI 2 "reg_or_cint_operand" "")))]
984 if (GET_CODE (operands[2]) == CONST_INT
985 && ! add_operand (operands[2], SImode))
987 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
988 ? operands[0] : gen_reg_rtx (SImode));
990 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
991 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
994 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
996 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high)));
997 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1002 (define_insn "*addsi3_internal1"
1003 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1004 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1005 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1009 {cal %0,%2(%1)|addi %0,%1,%2}
1011 {cau|addis} %0,%1,%v2"
1012 [(set_attr "length" "4,4,4,4")])
1014 (define_insn "*addsi3_internal2"
1015 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1016 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1017 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1019 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1020 "! TARGET_POWERPC64"
1022 {cax.|add.} %3,%1,%2
1023 {ai.|addic.} %3,%1,%2
1026 [(set_attr "type" "compare")
1027 (set_attr "length" "4,4,8,8")])
1030 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1031 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1032 (match_operand:SI 2 "reg_or_short_operand" ""))
1034 (clobber (match_scratch:SI 3 ""))]
1035 "! TARGET_POWERPC64 && reload_completed"
1037 (plus:SI (match_dup 1)
1040 (compare:CC (match_dup 3)
1044 (define_insn "*addsi3_internal3"
1045 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1046 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1047 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1049 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1050 (plus:SI (match_dup 1)
1052 "! TARGET_POWERPC64"
1054 {cax.|add.} %0,%1,%2
1055 {ai.|addic.} %0,%1,%2
1058 [(set_attr "type" "compare")
1059 (set_attr "length" "4,4,8,8")])
1062 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1063 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1064 (match_operand:SI 2 "reg_or_short_operand" ""))
1066 (set (match_operand:SI 0 "gpc_reg_operand" "")
1067 (plus:SI (match_dup 1) (match_dup 2)))]
1068 "! TARGET_POWERPC64 && reload_completed"
1070 (plus:SI (match_dup 1)
1073 (compare:CC (match_dup 0)
1077 ;; Split an add that we can't do in one insn into two insns, each of which
1078 ;; does one 16-bit part. This is used by combine. Note that the low-order
1079 ;; add should be last in case the result gets used in an address.
1082 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1083 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1084 (match_operand:SI 2 "non_add_cint_operand" "")))]
1086 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1087 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1090 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
1091 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
1094 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
1096 operands[3] = GEN_INT (high);
1097 operands[4] = GEN_INT (low);
1100 (define_insn "one_cmplsi2"
1101 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1102 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1107 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1108 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1110 (clobber (match_scratch:SI 2 "=r,r"))]
1111 "! TARGET_POWERPC64"
1115 [(set_attr "type" "compare")
1116 (set_attr "length" "4,8")])
1119 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1120 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1122 (clobber (match_scratch:SI 2 ""))]
1123 "! TARGET_POWERPC64 && reload_completed"
1125 (not:SI (match_dup 1)))
1127 (compare:CC (match_dup 2)
1132 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1133 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1135 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1136 (not:SI (match_dup 1)))]
1137 "! TARGET_POWERPC64"
1141 [(set_attr "type" "compare")
1142 (set_attr "length" "4,8")])
1145 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1146 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1148 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1149 (not:SI (match_dup 1)))]
1150 "! TARGET_POWERPC64 && reload_completed"
1152 (not:SI (match_dup 1)))
1154 (compare:CC (match_dup 0)
1159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1160 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1161 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1163 "{sf%I1|subf%I1c} %0,%2,%1")
1166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1167 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1168 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1175 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1176 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1177 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1179 (clobber (match_scratch:SI 3 "=r,r"))]
1182 {sf.|subfc.} %3,%2,%1
1184 [(set_attr "type" "compare")
1185 (set_attr "length" "4,8")])
1188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1189 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1190 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1192 (clobber (match_scratch:SI 3 "=r,r"))]
1193 "TARGET_POWERPC && ! TARGET_POWERPC64"
1197 [(set_attr "type" "compare")
1198 (set_attr "length" "4,8")])
1201 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1202 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1203 (match_operand:SI 2 "gpc_reg_operand" ""))
1205 (clobber (match_scratch:SI 3 ""))]
1206 "! TARGET_POWERPC64 && reload_completed"
1208 (minus:SI (match_dup 1)
1211 (compare:CC (match_dup 3)
1216 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1217 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1218 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1220 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1221 (minus:SI (match_dup 1) (match_dup 2)))]
1224 {sf.|subfc.} %0,%2,%1
1226 [(set_attr "type" "compare")
1227 (set_attr "length" "4,8")])
1230 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1231 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1232 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1234 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1235 (minus:SI (match_dup 1)
1237 "TARGET_POWERPC && ! TARGET_POWERPC64"
1241 [(set_attr "type" "compare")
1242 (set_attr "length" "4,8")])
1245 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1246 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1247 (match_operand:SI 2 "gpc_reg_operand" ""))
1249 (set (match_operand:SI 0 "gpc_reg_operand" "")
1250 (minus:SI (match_dup 1)
1252 "! TARGET_POWERPC64 && reload_completed"
1254 (minus:SI (match_dup 1)
1257 (compare:CC (match_dup 0)
1261 (define_expand "subsi3"
1262 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1263 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1264 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1268 if (GET_CODE (operands[2]) == CONST_INT)
1270 emit_insn (gen_addsi3 (operands[0], operands[1],
1271 negate_rtx (SImode, operands[2])));
1276 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1277 ;; instruction and some auxiliary computations. Then we just have a single
1278 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1281 (define_expand "sminsi3"
1283 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1284 (match_operand:SI 2 "reg_or_short_operand" ""))
1286 (minus:SI (match_dup 2) (match_dup 1))))
1287 (set (match_operand:SI 0 "gpc_reg_operand" "")
1288 (minus:SI (match_dup 2) (match_dup 3)))]
1291 { operands[3] = gen_reg_rtx (SImode); }")
1294 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1295 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1296 (match_operand:SI 2 "reg_or_short_operand" "")))
1297 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1300 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1302 (minus:SI (match_dup 2) (match_dup 1))))
1303 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1306 (define_expand "smaxsi3"
1308 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1309 (match_operand:SI 2 "reg_or_short_operand" ""))
1311 (minus:SI (match_dup 2) (match_dup 1))))
1312 (set (match_operand:SI 0 "gpc_reg_operand" "")
1313 (plus:SI (match_dup 3) (match_dup 1)))]
1316 { operands[3] = gen_reg_rtx (SImode); }")
1319 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1320 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1321 (match_operand:SI 2 "reg_or_short_operand" "")))
1322 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1325 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1327 (minus:SI (match_dup 2) (match_dup 1))))
1328 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1331 (define_expand "uminsi3"
1332 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1334 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1336 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1338 (minus:SI (match_dup 4) (match_dup 3))))
1339 (set (match_operand:SI 0 "gpc_reg_operand" "")
1340 (minus:SI (match_dup 2) (match_dup 3)))]
1344 operands[3] = gen_reg_rtx (SImode);
1345 operands[4] = gen_reg_rtx (SImode);
1346 operands[5] = GEN_INT (-2147483647 - 1);
1349 (define_expand "umaxsi3"
1350 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1352 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1354 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1356 (minus:SI (match_dup 4) (match_dup 3))))
1357 (set (match_operand:SI 0 "gpc_reg_operand" "")
1358 (plus:SI (match_dup 3) (match_dup 1)))]
1362 operands[3] = gen_reg_rtx (SImode);
1363 operands[4] = gen_reg_rtx (SImode);
1364 operands[5] = GEN_INT (-2147483647 - 1);
1368 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1369 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1370 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1372 (minus:SI (match_dup 2) (match_dup 1))))]
1377 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1379 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1380 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1382 (minus:SI (match_dup 2) (match_dup 1)))
1384 (clobber (match_scratch:SI 3 "=r"))]
1387 [(set_attr "type" "delayed_compare")])
1390 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1392 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1393 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1395 (minus:SI (match_dup 2) (match_dup 1)))
1397 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1398 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1400 (minus:SI (match_dup 2) (match_dup 1))))]
1403 [(set_attr "type" "delayed_compare")])
1405 ;; We don't need abs with condition code because such comparisons should
1407 (define_expand "abssi2"
1408 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1409 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1415 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1420 (define_insn "abssi2_power"
1421 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1422 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1426 (define_insn "abssi2_nopower"
1427 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1428 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1429 (clobber (match_scratch:SI 2 "=&r,&r"))]
1433 return (TARGET_POWERPC)
1434 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
1435 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
1437 [(set_attr "length" "12")])
1440 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1441 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1442 (clobber (match_scratch:SI 2 "=&r,&r"))]
1443 "! TARGET_POWER && reload_completed"
1444 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1445 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1446 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1449 (define_insn "*nabs_power"
1450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1451 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1455 (define_insn "*nabs_no_power"
1456 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1457 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1458 (clobber (match_scratch:SI 2 "=&r,&r"))]
1462 return (TARGET_POWERPC)
1463 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
1464 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
1466 [(set_attr "length" "12")])
1469 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1470 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1471 (clobber (match_scratch:SI 2 "=&r,&r"))]
1472 "! TARGET_POWER && reload_completed"
1473 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1474 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1475 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1478 (define_insn "negsi2"
1479 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1480 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1485 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1486 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1488 (clobber (match_scratch:SI 2 "=r"))]
1489 "! TARGET_POWERPC64"
1491 [(set_attr "type" "compare")])
1494 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1495 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1497 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1498 (neg:SI (match_dup 1)))]
1499 "! TARGET_POWERPC64"
1501 [(set_attr "type" "compare")])
1503 (define_insn "ffssi2"
1504 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1505 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1507 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
1508 [(set_attr "length" "16")])
1510 (define_expand "mulsi3"
1511 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1512 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1513 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1518 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1520 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1524 (define_insn "mulsi3_mq"
1525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1526 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1527 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1528 (clobber (match_scratch:SI 3 "=q,q"))]
1531 {muls|mullw} %0,%1,%2
1532 {muli|mulli} %0,%1,%2"
1533 [(set_attr "type" "imul")])
1535 (define_insn "mulsi3_no_mq"
1536 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1537 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1538 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1541 {muls|mullw} %0,%1,%2
1542 {muli|mulli} %0,%1,%2"
1543 [(set_attr "type" "imul")])
1546 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1547 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1548 (match_operand:SI 2 "gpc_reg_operand" "r"))
1550 (clobber (match_scratch:SI 3 "=r"))
1551 (clobber (match_scratch:SI 4 "=q"))]
1553 "{muls.|mullw.} %3,%1,%2"
1554 [(set_attr "type" "delayed_compare")])
1557 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1558 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1559 (match_operand:SI 2 "gpc_reg_operand" "r"))
1561 (clobber (match_scratch:SI 3 "=r"))]
1563 "{muls.|mullw.} %3,%1,%2"
1564 [(set_attr "type" "delayed_compare")])
1567 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1568 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1569 (match_operand:SI 2 "gpc_reg_operand" "r"))
1571 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1572 (mult:SI (match_dup 1) (match_dup 2)))
1573 (clobber (match_scratch:SI 4 "=q"))]
1575 "{muls.|mullw.} %0,%1,%2"
1576 [(set_attr "type" "delayed_compare")])
1579 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1580 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1581 (match_operand:SI 2 "gpc_reg_operand" "r"))
1583 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1584 (mult:SI (match_dup 1) (match_dup 2)))]
1586 "{muls.|mullw.} %0,%1,%2"
1587 [(set_attr "type" "delayed_compare")])
1589 ;; Operand 1 is divided by operand 2; quotient goes to operand
1590 ;; 0 and remainder to operand 3.
1591 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1593 (define_expand "divmodsi4"
1594 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1595 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1596 (match_operand:SI 2 "gpc_reg_operand" "")))
1597 (set (match_operand:SI 3 "gpc_reg_operand" "")
1598 (mod:SI (match_dup 1) (match_dup 2)))])]
1599 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1602 if (! TARGET_POWER && ! TARGET_POWERPC)
1604 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1605 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1606 emit_insn (gen_divss_call ());
1607 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1608 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1614 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1615 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1616 (match_operand:SI 2 "gpc_reg_operand" "r")))
1617 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
1618 (mod:SI (match_dup 1) (match_dup 2)))]
1621 [(set_attr "type" "idiv")])
1623 (define_expand "udivsi3"
1624 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1625 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1626 (match_operand:SI 2 "gpc_reg_operand" "")))]
1627 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1630 if (! TARGET_POWER && ! TARGET_POWERPC)
1632 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1633 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1634 emit_insn (gen_quous_call ());
1635 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1638 else if (TARGET_POWER)
1640 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1645 (define_insn "udivsi3_mq"
1646 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1647 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1648 (match_operand:SI 2 "gpc_reg_operand" "r")))
1649 (clobber (match_scratch:SI 3 "=q"))]
1650 "TARGET_POWERPC && TARGET_POWER"
1652 [(set_attr "type" "idiv")])
1654 (define_insn "*udivsi3_no_mq"
1655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1656 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1657 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1658 "TARGET_POWERPC && ! TARGET_POWER"
1660 [(set_attr "type" "idiv")])
1662 ;; For powers of two we can do srai/aze for divide and then adjust for
1663 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1664 ;; used; for PowerPC, force operands into register and do a normal divide;
1665 ;; for AIX common-mode, use quoss call on register operands.
1666 (define_expand "divsi3"
1667 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1668 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1669 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1673 if (GET_CODE (operands[2]) == CONST_INT
1674 && exact_log2 (INTVAL (operands[2])) >= 0)
1676 else if (TARGET_POWERPC)
1678 operands[2] = force_reg (SImode, operands[2]);
1681 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1685 else if (TARGET_POWER)
1689 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1690 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1691 emit_insn (gen_quoss_call ());
1692 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1697 (define_insn "divsi3_mq"
1698 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1699 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1700 (match_operand:SI 2 "gpc_reg_operand" "r")))
1701 (clobber (match_scratch:SI 3 "=q"))]
1702 "TARGET_POWERPC && TARGET_POWER"
1704 [(set_attr "type" "idiv")])
1706 (define_insn "*divsi3_no_mq"
1707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1708 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1709 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1710 "TARGET_POWERPC && ! TARGET_POWER"
1712 [(set_attr "type" "idiv")])
1714 (define_expand "modsi3"
1715 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1716 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1717 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1725 if (GET_CODE (operands[2]) != CONST_INT)
1728 i = exact_log2 (INTVAL (operands[2]));
1733 temp1 = gen_reg_rtx (SImode);
1734 temp2 = gen_reg_rtx (SImode);
1736 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1737 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1738 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1743 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1744 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1745 (match_operand:SI 2 "const_int_operand" "N")))]
1746 "exact_log2 (INTVAL (operands[2])) >= 0"
1747 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1748 [(set_attr "length" "8")])
1751 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1752 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1753 (match_operand:SI 2 "const_int_operand" "N"))
1755 (clobber (match_scratch:SI 3 "=r"))]
1756 "exact_log2 (INTVAL (operands[2])) >= 0"
1757 "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3"
1758 [(set_attr "type" "compare")
1759 (set_attr "length" "8")])
1762 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1763 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1764 (match_operand:SI 2 "const_int_operand" "N"))
1766 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1767 (div:SI (match_dup 1) (match_dup 2)))]
1768 "exact_log2 (INTVAL (operands[2])) >= 0"
1769 "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0"
1770 [(set_attr "type" "compare")
1771 (set_attr "length" "8")])
1774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1777 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1779 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
1780 (match_operand:SI 3 "gpc_reg_operand" "r")))
1781 (set (match_operand:SI 2 "register_operand" "=*q")
1784 (zero_extend:DI (match_dup 1)) (const_int 32))
1785 (zero_extend:DI (match_dup 4)))
1789 [(set_attr "type" "idiv")])
1791 ;; To do unsigned divide we handle the cases of the divisor looking like a
1792 ;; negative number. If it is a constant that is less than 2**31, we don't
1793 ;; have to worry about the branches. So make a few subroutines here.
1795 ;; First comes the normal case.
1796 (define_expand "udivmodsi4_normal"
1797 [(set (match_dup 4) (const_int 0))
1798 (parallel [(set (match_operand:SI 0 "" "")
1799 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1801 (zero_extend:DI (match_operand:SI 1 "" "")))
1802 (match_operand:SI 2 "" "")))
1803 (set (match_operand:SI 3 "" "")
1804 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1806 (zero_extend:DI (match_dup 1)))
1810 { operands[4] = gen_reg_rtx (SImode); }")
1812 ;; This handles the branches.
1813 (define_expand "udivmodsi4_tests"
1814 [(set (match_operand:SI 0 "" "") (const_int 0))
1815 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
1816 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
1817 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
1818 (label_ref (match_operand:SI 4 "" "")) (pc)))
1819 (set (match_dup 0) (const_int 1))
1820 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
1821 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
1822 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
1823 (label_ref (match_dup 4)) (pc)))]
1826 { operands[5] = gen_reg_rtx (CCUNSmode);
1827 operands[6] = gen_reg_rtx (CCmode);
1830 (define_expand "udivmodsi4"
1831 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1832 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1833 (match_operand:SI 2 "reg_or_cint_operand" "")))
1834 (set (match_operand:SI 3 "gpc_reg_operand" "")
1835 (umod:SI (match_dup 1) (match_dup 2)))])]
1843 if (! TARGET_POWERPC)
1845 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1846 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1847 emit_insn (gen_divus_call ());
1848 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1849 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1856 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
1858 operands[2] = force_reg (SImode, operands[2]);
1859 label = gen_label_rtx ();
1860 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
1861 operands[3], label));
1864 operands[2] = force_reg (SImode, operands[2]);
1866 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
1874 ;; AIX architecture-independent common-mode multiply (DImode),
1875 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
1876 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
1877 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
1878 ;; assumed unused if generating common-mode, so ignore.
1879 (define_insn "mulh_call"
1882 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
1883 (sign_extend:DI (reg:SI 4)))
1885 (clobber (match_scratch:SI 0 "=l"))]
1886 "! TARGET_POWER && ! TARGET_POWERPC"
1888 [(set_attr "type" "imul")])
1890 (define_insn "mull_call"
1892 (mult:DI (sign_extend:DI (reg:SI 3))
1893 (sign_extend:DI (reg:SI 4))))
1894 (clobber (match_scratch:SI 0 "=l"))
1895 (clobber (reg:SI 0))]
1896 "! TARGET_POWER && ! TARGET_POWERPC"
1898 [(set_attr "type" "imul")])
1900 (define_insn "divss_call"
1902 (div:SI (reg:SI 3) (reg:SI 4)))
1904 (mod:SI (reg:SI 3) (reg:SI 4)))
1905 (clobber (match_scratch:SI 0 "=l"))
1906 (clobber (reg:SI 0))]
1907 "! TARGET_POWER && ! TARGET_POWERPC"
1909 [(set_attr "type" "idiv")])
1911 (define_insn "divus_call"
1913 (udiv:SI (reg:SI 3) (reg:SI 4)))
1915 (umod:SI (reg:SI 3) (reg:SI 4)))
1916 (clobber (match_scratch:SI 0 "=l"))
1917 (clobber (reg:SI 0))
1918 (clobber (match_scratch:CC 1 "=x"))
1919 (clobber (reg:CC 69))]
1920 "! TARGET_POWER && ! TARGET_POWERPC"
1922 [(set_attr "type" "idiv")])
1924 (define_insn "quoss_call"
1926 (div:SI (reg:SI 3) (reg:SI 4)))
1927 (clobber (match_scratch:SI 0 "=l"))]
1928 "! TARGET_POWER && ! TARGET_POWERPC"
1930 [(set_attr "type" "idiv")])
1932 (define_insn "quous_call"
1934 (udiv:SI (reg:SI 3) (reg:SI 4)))
1935 (clobber (match_scratch:SI 0 "=l"))
1936 (clobber (reg:SI 0))
1937 (clobber (match_scratch:CC 1 "=x"))
1938 (clobber (reg:CC 69))]
1939 "! TARGET_POWER && ! TARGET_POWERPC"
1941 [(set_attr "type" "idiv")])
1943 ;; Logical instructions
1944 (define_insn "andsi3"
1945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1946 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1947 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
1948 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1952 {rlinm|rlwinm} %0,%1,0,%m2,%M2
1953 {andil.|andi.} %0,%1,%b2
1954 {andiu.|andis.} %0,%1,%u2"
1955 [(set_attr "length" "4")])
1957 ;; Note to set cr's other than cr0 we do the and immediate and then
1958 ;; the test again -- this avoids a mcrf which on the higher end
1959 ;; machines causes an execution serialization
1961 (define_insn "*andsi3_internal2"
1962 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
1963 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
1964 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1966 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
1967 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
1968 "! TARGET_POWERPC64"
1971 {andil.|andi.} %3,%1,%b2
1972 {andiu.|andis.} %3,%1,%u2
1973 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
1978 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
1979 (set_attr "length" "4,4,4,4,8,8,8,8")])
1982 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1983 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
1984 (match_operand:SI 2 "and_operand" ""))
1986 (clobber (match_scratch:SI 3 ""))
1987 (clobber (match_scratch:CC 4 ""))]
1988 "! TARGET_POWERPC64 && reload_completed"
1989 [(parallel [(set (match_dup 3)
1990 (and:SI (match_dup 1)
1992 (clobber (match_dup 4))])
1994 (compare:CC (match_dup 3)
1998 (define_insn "*andsi3_internal3"
1999 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2000 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2001 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2003 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2004 (and:SI (match_dup 1)
2006 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2007 "! TARGET_POWERPC64"
2010 {andil.|andi.} %0,%1,%b2
2011 {andiu.|andis.} %0,%1,%u2
2012 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2017 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2018 (set_attr "length" "4,4,4,4,8,8,8,8")])
2021 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2022 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2023 (match_operand:SI 2 "and_operand" ""))
2025 (set (match_operand:SI 0 "gpc_reg_operand" "")
2026 (and:SI (match_dup 1)
2028 (clobber (match_scratch:CC 4 ""))]
2029 "! TARGET_POWERPC64 && reload_completed"
2030 [(parallel [(set (match_dup 0)
2031 (and:SI (match_dup 1)
2033 (clobber (match_dup 4))])
2035 (compare:CC (match_dup 0)
2039 (define_expand "iorsi3"
2040 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2041 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2042 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2046 if (GET_CODE (operands[2]) == CONST_INT
2047 && ! logical_operand (operands[2], SImode))
2049 HOST_WIDE_INT value = INTVAL (operands[2]);
2050 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2051 ? operands[0] : gen_reg_rtx (SImode));
2053 emit_insn (gen_iorsi3 (tmp, operands[1],
2054 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2055 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2060 (define_insn "*iorsi3_internal1"
2061 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2062 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2063 (match_operand:SI 2 "logical_operand" "r,K,L")))]
2067 {oril|ori} %0,%1,%b2
2068 {oriu|oris} %0,%1,%u2"
2069 [(set_attr "length" "4,4,4")])
2071 (define_insn "*iorsi3_internal2"
2072 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2073 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2074 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2076 (clobber (match_scratch:SI 3 "=r,r"))]
2077 "! TARGET_POWERPC64"
2081 [(set_attr "type" "compare")
2082 (set_attr "length" "4,8")])
2085 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2086 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2087 (match_operand:SI 2 "gpc_reg_operand" ""))
2089 (clobber (match_scratch:SI 3 ""))]
2090 "! TARGET_POWERPC64 && reload_completed"
2092 (ior:SI (match_dup 1)
2095 (compare:CC (match_dup 3)
2099 (define_insn "*iorsi3_internal3"
2100 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2101 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2102 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2104 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2105 (ior:SI (match_dup 1)
2107 "! TARGET_POWERPC64"
2111 [(set_attr "type" "compare")
2112 (set_attr "length" "4,8")])
2115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2116 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2117 (match_operand:SI 2 "gpc_reg_operand" ""))
2119 (set (match_operand:SI 0 "gpc_reg_operand" "")
2120 (ior:SI (match_dup 1) (match_dup 2)))]
2121 "! TARGET_POWERPC64 && reload_completed"
2123 (ior:SI (match_dup 1)
2126 (compare:CC (match_dup 0)
2130 ;; Split an IOR that we can't do in one insn into two insns, each of which
2131 ;; does one 16-bit part. This is used by combine.
2134 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2135 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2136 (match_operand:SI 2 "non_logical_cint_operand" "")))]
2138 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
2139 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
2142 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2143 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
2146 (define_expand "xorsi3"
2147 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2148 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2149 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2153 if (GET_CODE (operands[2]) == CONST_INT
2154 && ! logical_operand (operands[2], SImode))
2156 HOST_WIDE_INT value = INTVAL (operands[2]);
2157 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2158 ? operands[0] : gen_reg_rtx (SImode));
2160 emit_insn (gen_xorsi3 (tmp, operands[1],
2161 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2162 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2167 (define_insn "*xorsi3_internal1"
2168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2169 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2170 (match_operand:SI 2 "logical_operand" "r,K,L")))]
2174 {xoril|xori} %0,%1,%b2
2175 {xoriu|xoris} %0,%1,%u2"
2176 [(set_attr "length" "4,4,4")])
2178 (define_insn "*xorsi3_internal2"
2179 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2180 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2181 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2183 (clobber (match_scratch:SI 3 "=r,r"))]
2184 "! TARGET_POWERPC64"
2188 [(set_attr "type" "compare")
2189 (set_attr "length" "4,8")])
2192 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2193 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2194 (match_operand:SI 2 "gpc_reg_operand" ""))
2196 (clobber (match_scratch:SI 3 ""))]
2197 "! TARGET_POWERPC64 && reload_completed"
2199 (xor:SI (match_dup 1)
2202 (compare:CC (match_dup 3)
2206 (define_insn "*xorsi3_internal3"
2207 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2208 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2209 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2211 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2212 (xor:SI (match_dup 1)
2214 "! TARGET_POWERPC64"
2218 [(set_attr "type" "compare")
2219 (set_attr "length" "4,8")])
2222 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2223 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2224 (match_operand:SI 2 "gpc_reg_operand" ""))
2226 (set (match_operand:SI 0 "gpc_reg_operand" "")
2227 (xor:SI (match_dup 1) (match_dup 2)))]
2228 "! TARGET_POWERPC64 && reload_completed"
2230 (xor:SI (match_dup 1)
2233 (compare:CC (match_dup 0)
2237 ;; Split an XOR that we can't do in one insn into two insns, each of which
2238 ;; does one 16-bit part. This is used by combine.
2241 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2242 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2243 (match_operand:SI 2 "non_logical_cint_operand" "")))]
2245 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
2246 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
2249 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2250 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
2253 (define_insn "*eqvsi3_internal1"
2254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2255 (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
2256 (match_operand:SI 2 "gpc_reg_operand" "r"))))]
2260 (define_insn "*eqvsi3_internal2"
2261 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2262 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2263 (match_operand:SI 2 "gpc_reg_operand" "r,r")))
2265 (clobber (match_scratch:SI 3 "=r,r"))]
2266 "! TARGET_POWERPC64"
2270 [(set_attr "type" "compare")
2271 (set_attr "length" "4,8")])
2274 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2275 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2276 (match_operand:SI 2 "gpc_reg_operand" "")))
2278 (clobber (match_scratch:SI 3 ""))]
2279 "! TARGET_POWERPC64 && reload_completed"
2281 (not:SI (xor:SI (match_dup 1)
2284 (compare:CC (match_dup 3)
2288 (define_insn "*eqvsi3_internal3"
2289 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2290 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2291 (match_operand:SI 2 "gpc_reg_operand" "r,r")))
2293 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2294 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
2295 "! TARGET_POWERPC64"
2299 [(set_attr "type" "compare")
2300 (set_attr "length" "4,8")])
2303 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2304 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2305 (match_operand:SI 2 "reg_or_short_operand" "")))
2307 (set (match_operand:SI 0 "gpc_reg_operand" "")
2308 (not:SI (xor:SI (match_dup 1)
2310 "! TARGET_POWERPC64 && reload_completed"
2312 (not:SI (xor:SI (match_dup 1)
2315 (compare:CC (match_dup 0)
2319 (define_insn "*andcsi3_internal1"
2320 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2321 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2322 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2326 (define_insn "*andcsi3_internal2"
2327 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2328 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2329 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2331 (clobber (match_scratch:SI 3 "=r,r"))]
2332 "! TARGET_POWERPC64"
2336 [(set_attr "type" "compare")
2337 (set_attr "length" "4,8")])
2340 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2341 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2342 (match_operand:SI 2 "gpc_reg_operand" ""))
2344 (clobber (match_scratch:SI 3 ""))]
2345 "! TARGET_POWERPC64 && reload_completed"
2347 (and:SI (not:SI (match_dup 1))
2350 (compare:CC (match_dup 3)
2354 (define_insn "*andcsi3_internal3"
2355 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2356 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2357 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2359 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2360 (and:SI (not:SI (match_dup 1))
2362 "! TARGET_POWERPC64"
2366 [(set_attr "type" "compare")
2367 (set_attr "length" "4,8")])
2370 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2371 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2372 (match_operand:SI 2 "gpc_reg_operand" ""))
2374 (set (match_operand:SI 0 "gpc_reg_operand" "")
2375 (and:SI (not:SI (match_dup 1))
2377 "! TARGET_POWERPC64 && reload_completed"
2379 (and:SI (not:SI (match_dup 1))
2382 (compare:CC (match_dup 0)
2386 (define_insn "*iorcsi3_internal1"
2387 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2388 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2389 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2393 (define_insn "*iorcsi3_internal2"
2394 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2395 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2396 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2398 (clobber (match_scratch:SI 3 "=r,r"))]
2399 "! TARGET_POWERPC64"
2403 [(set_attr "type" "compare")
2404 (set_attr "length" "4,8")])
2407 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2408 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2409 (match_operand:SI 2 "gpc_reg_operand" ""))
2411 (clobber (match_scratch:SI 3 ""))]
2412 "! TARGET_POWERPC64 && reload_completed"
2414 (ior:SI (not:SI (match_dup 1))
2417 (compare:CC (match_dup 3)
2421 (define_insn "*iorcsi3_internal3"
2422 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2423 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2424 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2426 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2427 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
2428 "! TARGET_POWERPC64"
2432 [(set_attr "type" "compare")])
2435 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2436 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2437 (match_operand:SI 2 "gpc_reg_operand" ""))
2439 (set (match_operand:SI 0 "gpc_reg_operand" "")
2440 (ior:SI (not:SI (match_dup 1))
2442 "! TARGET_POWERPC64 && reload_completed"
2444 (ior:SI (not:SI (match_dup 1))
2447 (compare:CC (match_dup 0)
2451 (define_insn "*nandsi3_internal1"
2452 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2453 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
2454 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
2458 (define_insn "*nandsi3_internal2"
2459 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2460 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2461 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
2463 (clobber (match_scratch:SI 3 "=r,r"))]
2464 "! TARGET_POWERPC64"
2468 [(set_attr "type" "compare")
2469 (set_attr "length" "4,8")])
2472 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2473 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2474 (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
2476 (clobber (match_scratch:SI 3 ""))]
2477 "! TARGET_POWERPC64 && reload_completed"
2479 (ior:SI (not:SI (match_dup 1))
2480 (not:SI (match_dup 2))))
2482 (compare:CC (match_dup 3)
2486 (define_insn "*nandsi3_internal3"
2487 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2488 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2489 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
2491 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2492 (ior:SI (not:SI (match_dup 1))
2493 (not:SI (match_dup 2))))]
2494 "! TARGET_POWERPC64"
2498 [(set_attr "type" "compare")
2499 (set_attr "length" "4,8")])
2502 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2503 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2504 (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
2506 (set (match_operand:SI 0 "gpc_reg_operand" "")
2507 (ior:SI (not:SI (match_dup 1))
2508 (not:SI (match_dup 2))))]
2509 "! TARGET_POWERPC64 && reload_completed"
2511 (ior:SI (not:SI (match_dup 1))
2512 (not:SI (match_dup 2))))
2514 (compare:CC (match_dup 0)
2518 (define_insn "*norsi3_internal1"
2519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2520 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
2521 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
2525 (define_insn "*norsi3_internal2"
2526 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2527 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2528 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
2530 (clobber (match_scratch:SI 3 "=r,r"))]
2531 "! TARGET_POWERPC64"
2535 [(set_attr "type" "compare")
2536 (set_attr "length" "4,8")])
2539 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2540 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2541 (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
2543 (clobber (match_scratch:SI 3 ""))]
2544 "! TARGET_POWERPC64 && reload_completed"
2546 (and:SI (not:SI (match_dup 1))
2547 (not:SI (match_dup 2))))
2549 (compare:CC (match_dup 3)
2553 (define_insn "*norsi3_internal3"
2554 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2555 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2556 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
2558 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2559 (and:SI (not:SI (match_dup 1))
2560 (not:SI (match_dup 2))))]
2561 "! TARGET_POWERPC64"
2565 [(set_attr "type" "compare")
2566 (set_attr "length" "4,8")])
2569 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2570 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2571 (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
2573 (set (match_operand:SI 0 "gpc_reg_operand" "")
2574 (and:SI (not:SI (match_dup 1))
2575 (not:SI (match_dup 2))))]
2576 "! TARGET_POWERPC64 && reload_completed"
2578 (and:SI (not:SI (match_dup 1))
2579 (not:SI (match_dup 2))))
2581 (compare:CC (match_dup 0)
2585 ;; maskir insn. We need four forms because things might be in arbitrary
2586 ;; orders. Don't define forms that only set CR fields because these
2587 ;; would modify an input register.
2589 (define_insn "*maskir_internal1"
2590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2591 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2592 (match_operand:SI 1 "gpc_reg_operand" "0"))
2593 (and:SI (match_dup 2)
2594 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2598 (define_insn "*maskir_internal2"
2599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2600 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2601 (match_operand:SI 1 "gpc_reg_operand" "0"))
2602 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2607 (define_insn "*maskir_internal3"
2608 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2609 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2610 (match_operand:SI 3 "gpc_reg_operand" "r"))
2611 (and:SI (not:SI (match_dup 2))
2612 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2616 (define_insn "*maskir_internal4"
2617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2618 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2619 (match_operand:SI 2 "gpc_reg_operand" "r"))
2620 (and:SI (not:SI (match_dup 2))
2621 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2625 (define_insn "*maskir_internal5"
2626 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2628 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2629 (match_operand:SI 1 "gpc_reg_operand" "0"))
2630 (and:SI (match_dup 2)
2631 (match_operand:SI 3 "gpc_reg_operand" "r")))
2633 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2634 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2635 (and:SI (match_dup 2) (match_dup 3))))]
2638 [(set_attr "type" "compare")])
2640 (define_insn "*maskir_internal6"
2641 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2643 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2644 (match_operand:SI 1 "gpc_reg_operand" "0"))
2645 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2648 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2649 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2650 (and:SI (match_dup 3) (match_dup 2))))]
2653 [(set_attr "type" "compare")])
2655 (define_insn "*maskir_internal7"
2656 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2658 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2659 (match_operand:SI 3 "gpc_reg_operand" "r"))
2660 (and:SI (not:SI (match_dup 2))
2661 (match_operand:SI 1 "gpc_reg_operand" "0")))
2663 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2664 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2665 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2668 [(set_attr "type" "compare")])
2670 (define_insn "*maskir_internal8"
2671 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2673 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2674 (match_operand:SI 2 "gpc_reg_operand" "r"))
2675 (and:SI (not:SI (match_dup 2))
2676 (match_operand:SI 1 "gpc_reg_operand" "0")))
2678 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2679 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2680 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2683 [(set_attr "type" "compare")])
2685 ;; Rotate and shift insns, in all their variants. These support shifts,
2686 ;; field inserts and extracts, and various combinations thereof.
2687 (define_expand "insv"
2688 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2689 (match_operand:SI 1 "const_int_operand" "")
2690 (match_operand:SI 2 "const_int_operand" ""))
2691 (match_operand 3 "gpc_reg_operand" ""))]
2695 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2696 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2697 compiler if the address of the structure is taken later. */
2698 if (GET_CODE (operands[0]) == SUBREG
2699 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2702 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2703 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2705 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2709 (define_insn "insvsi"
2710 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2711 (match_operand:SI 1 "const_int_operand" "i")
2712 (match_operand:SI 2 "const_int_operand" "i"))
2713 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2717 int start = INTVAL (operands[2]) & 31;
2718 int size = INTVAL (operands[1]) & 31;
2720 operands[4] = GEN_INT (32 - start - size);
2721 operands[1] = GEN_INT (start + size - 1);
2722 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2725 (define_insn "*insvsi_internal1"
2726 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2727 (match_operand:SI 1 "const_int_operand" "i")
2728 (match_operand:SI 2 "const_int_operand" "i"))
2729 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2730 (match_operand:SI 4 "const_int_operand" "i")))]
2731 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2734 int shift = INTVAL (operands[4]) & 31;
2735 int start = INTVAL (operands[2]) & 31;
2736 int size = INTVAL (operands[1]) & 31;
2738 operands[4] = GEN_INT (shift - start - size);
2739 operands[1] = GEN_INT (start + size - 1);
2740 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2743 (define_insn "*insvsi_internal2"
2744 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2745 (match_operand:SI 1 "const_int_operand" "i")
2746 (match_operand:SI 2 "const_int_operand" "i"))
2747 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2748 (match_operand:SI 4 "const_int_operand" "i")))]
2749 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2752 int shift = INTVAL (operands[4]) & 31;
2753 int start = INTVAL (operands[2]) & 31;
2754 int size = INTVAL (operands[1]) & 31;
2756 operands[4] = GEN_INT (32 - shift - start - size);
2757 operands[1] = GEN_INT (start + size - 1);
2758 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2761 (define_insn "*insvsi_internal3"
2762 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2763 (match_operand:SI 1 "const_int_operand" "i")
2764 (match_operand:SI 2 "const_int_operand" "i"))
2765 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2766 (match_operand:SI 4 "const_int_operand" "i")))]
2767 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2770 int shift = INTVAL (operands[4]) & 31;
2771 int start = INTVAL (operands[2]) & 31;
2772 int size = INTVAL (operands[1]) & 31;
2774 operands[4] = GEN_INT (32 - shift - start - size);
2775 operands[1] = GEN_INT (start + size - 1);
2776 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2779 (define_insn "*insvsi_internal4"
2780 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2781 (match_operand:SI 1 "const_int_operand" "i")
2782 (match_operand:SI 2 "const_int_operand" "i"))
2783 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2784 (match_operand:SI 4 "const_int_operand" "i")
2785 (match_operand:SI 5 "const_int_operand" "i")))]
2786 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2789 int extract_start = INTVAL (operands[5]) & 31;
2790 int extract_size = INTVAL (operands[4]) & 31;
2791 int insert_start = INTVAL (operands[2]) & 31;
2792 int insert_size = INTVAL (operands[1]) & 31;
2794 /* Align extract field with insert field */
2795 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
2796 operands[1] = GEN_INT (insert_start + insert_size - 1);
2797 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2800 (define_insn "insvdi"
2801 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
2802 (match_operand:SI 1 "const_int_operand" "i")
2803 (match_operand:SI 2 "const_int_operand" "i"))
2804 (match_operand:DI 3 "gpc_reg_operand" "r"))]
2808 int start = INTVAL (operands[2]) & 63;
2809 int size = INTVAL (operands[1]) & 63;
2811 operands[1] = GEN_INT (64 - start - size);
2812 return \"rldimi %0,%3,%H1,%H2\";
2815 (define_expand "extzv"
2816 [(set (match_operand 0 "gpc_reg_operand" "")
2817 (zero_extract (match_operand 1 "gpc_reg_operand" "")
2818 (match_operand:SI 2 "const_int_operand" "")
2819 (match_operand:SI 3 "const_int_operand" "")))]
2823 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2824 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2825 compiler if the address of the structure is taken later. */
2826 if (GET_CODE (operands[0]) == SUBREG
2827 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2830 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
2831 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
2833 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
2837 (define_insn "extzvsi"
2838 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2839 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2840 (match_operand:SI 2 "const_int_operand" "i")
2841 (match_operand:SI 3 "const_int_operand" "i")))]
2845 int start = INTVAL (operands[3]) & 31;
2846 int size = INTVAL (operands[2]) & 31;
2848 if (start + size >= 32)
2849 operands[3] = const0_rtx;
2851 operands[3] = GEN_INT (start + size);
2852 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
2855 (define_insn "*extzvsi_internal1"
2856 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2857 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2858 (match_operand:SI 2 "const_int_operand" "i")
2859 (match_operand:SI 3 "const_int_operand" "i"))
2861 (clobber (match_scratch:SI 4 "=r"))]
2862 "! TARGET_POWERPC64"
2865 int start = INTVAL (operands[3]) & 31;
2866 int size = INTVAL (operands[2]) & 31;
2868 /* If the bitfield being tested fits in the upper or lower half of a
2869 word, it is possible to use andiu. or andil. to test it. This is
2870 useful because the condition register set-use delay is smaller for
2871 andi[ul]. than for rlinm. This doesn't work when the starting bit
2872 position is 0 because the LT and GT bits may be set wrong. */
2874 if ((start > 0 && start + size <= 16) || start >= 16)
2876 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
2877 - (1 << (16 - (start & 15) - size))));
2879 return \"{andiu.|andis.} %4,%1,%3\";
2881 return \"{andil.|andi.} %4,%1,%3\";
2884 if (start + size >= 32)
2885 operands[3] = const0_rtx;
2887 operands[3] = GEN_INT (start + size);
2888 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
2890 [(set_attr "type" "compare")])
2892 (define_insn "*extzvsi_internal2"
2893 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2894 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2895 (match_operand:SI 2 "const_int_operand" "i")
2896 (match_operand:SI 3 "const_int_operand" "i"))
2898 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2899 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
2900 "! TARGET_POWERPC64"
2903 int start = INTVAL (operands[3]) & 31;
2904 int size = INTVAL (operands[2]) & 31;
2906 if (start >= 16 && start + size == 32)
2908 operands[3] = GEN_INT ((1 << (32 - start)) - 1);
2909 return \"{andil.|andi.} %0,%1,%3\";
2912 if (start + size >= 32)
2913 operands[3] = const0_rtx;
2915 operands[3] = GEN_INT (start + size);
2916 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
2918 [(set_attr "type" "delayed_compare")])
2920 (define_insn "extzvdi"
2921 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2922 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2923 (match_operand:SI 2 "const_int_operand" "i")
2924 (match_operand:SI 3 "const_int_operand" "i")))]
2928 int start = INTVAL (operands[3]) & 63;
2929 int size = INTVAL (operands[2]) & 63;
2931 if (start + size >= 64)
2932 operands[3] = const0_rtx;
2934 operands[3] = GEN_INT (start + size);
2935 operands[2] = GEN_INT (64 - size);
2936 return \"rldicl %0,%1,%3,%2\";
2939 (define_insn "*extzvdi_internal1"
2940 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
2941 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2942 (match_operand:SI 2 "const_int_operand" "i")
2943 (match_operand:SI 3 "const_int_operand" "i"))
2945 (clobber (match_scratch:DI 4 "=r"))]
2949 int start = INTVAL (operands[3]) & 63;
2950 int size = INTVAL (operands[2]) & 63;
2952 if (start + size >= 64)
2953 operands[3] = const0_rtx;
2955 operands[3] = GEN_INT (start + size);
2956 operands[2] = GEN_INT (64 - size);
2957 return \"rldicl. %4,%1,%3,%2\";
2960 (define_insn "*extzvdi_internal2"
2961 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
2962 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2963 (match_operand:SI 2 "const_int_operand" "i")
2964 (match_operand:SI 3 "const_int_operand" "i"))
2966 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
2967 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
2971 int start = INTVAL (operands[3]) & 63;
2972 int size = INTVAL (operands[2]) & 63;
2974 if (start + size >= 64)
2975 operands[3] = const0_rtx;
2977 operands[3] = GEN_INT (start + size);
2978 operands[2] = GEN_INT (64 - size);
2979 return \"rldicl. %0,%1,%3,%2\";
2982 (define_insn "rotlsi3"
2983 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2984 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2985 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2987 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
2989 (define_insn "*rotlsi3_internal2"
2990 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2991 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2992 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2994 (clobber (match_scratch:SI 3 "=r"))]
2995 "! TARGET_POWERPC64"
2996 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
2997 [(set_attr "type" "delayed_compare")])
2999 (define_insn "*rotlsi3_internal3"
3000 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3001 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3002 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3004 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3005 (rotate:SI (match_dup 1) (match_dup 2)))]
3006 "! TARGET_POWERPC64"
3007 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff"
3008 [(set_attr "type" "delayed_compare")])
3010 (define_insn "*rotlsi3_internal4"
3011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3012 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3013 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3014 (match_operand:SI 3 "mask_operand" "T")))]
3016 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3018 (define_insn "*rotlsi3_internal5"
3019 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3021 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3022 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3023 (match_operand:SI 3 "mask_operand" "T"))
3025 (clobber (match_scratch:SI 4 "=r"))]
3026 "! TARGET_POWERPC64"
3027 "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3"
3028 [(set_attr "type" "delayed_compare")])
3030 (define_insn "*rotlsi3_internal6"
3031 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3033 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3034 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3035 (match_operand:SI 3 "mask_operand" "T"))
3037 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3038 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3039 "! TARGET_POWERPC64"
3040 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3"
3041 [(set_attr "type" "delayed_compare")])
3043 (define_insn "*rotlsi3_internal7"
3044 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3047 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3048 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3050 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3052 (define_insn "*rotlsi3_internal8"
3053 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3054 (compare:CC (zero_extend:SI
3056 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3057 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
3059 (clobber (match_scratch:SI 3 "=r"))]
3061 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff"
3062 [(set_attr "type" "delayed_compare")])
3064 (define_insn "*rotlsi3_internal9"
3065 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3066 (compare:CC (zero_extend:SI
3068 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3069 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
3071 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3072 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3074 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff"
3075 [(set_attr "type" "delayed_compare")])
3077 (define_insn "*rotlsi3_internal10"
3078 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3081 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3082 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3084 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3086 (define_insn "*rotlsi3_internal11"
3087 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3088 (compare:CC (zero_extend:SI
3090 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3091 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
3093 (clobber (match_scratch:SI 3 "=r"))]
3095 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff"
3096 [(set_attr "type" "delayed_compare")])
3098 (define_insn "*rotlsi3_internal12"
3099 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3100 (compare:CC (zero_extend:SI
3102 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3103 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
3105 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3106 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3108 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff"
3109 [(set_attr "type" "delayed_compare")])
3111 ;; Note that we use "sle." instead of "sl." so that we can set
3112 ;; SHIFT_COUNT_TRUNCATED.
3114 (define_expand "ashlsi3"
3115 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3116 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3117 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3122 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3124 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3128 (define_insn "ashlsi3_power"
3129 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3130 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3131 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3132 (clobber (match_scratch:SI 3 "=q,X"))]
3136 {sli|slwi} %0,%1,%h2"
3137 [(set_attr "length" "8")])
3139 (define_insn "ashlsi3_no_power"
3140 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3141 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3142 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3144 "{sl|slw}%I2 %0,%1,%h2"
3145 [(set_attr "length" "8")])
3148 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3149 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3150 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3152 (clobber (match_scratch:SI 3 "=r,r"))
3153 (clobber (match_scratch:SI 4 "=q,X"))]
3157 {sli.|slwi.} %3,%1,%h2"
3158 [(set_attr "type" "delayed_compare")])
3161 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3162 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3163 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3165 (clobber (match_scratch:SI 3 "=r"))]
3166 "! TARGET_POWER && ! TARGET_POWERPC64"
3167 "{sl|slw}%I2. %3,%1,%h2"
3168 [(set_attr "type" "delayed_compare")])
3171 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3172 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3173 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3175 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3176 (ashift:SI (match_dup 1) (match_dup 2)))
3177 (clobber (match_scratch:SI 4 "=q,X"))]
3181 {sli.|slwi.} %0,%1,%h2"
3182 [(set_attr "type" "delayed_compare")])
3185 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3186 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3187 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3189 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3190 (ashift:SI (match_dup 1) (match_dup 2)))]
3191 "! TARGET_POWER && ! TARGET_POWERPC64"
3192 "{sl|slw}%I2. %0,%1,%h2"
3193 [(set_attr "type" "delayed_compare")])
3196 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3197 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3198 (match_operand:SI 2 "const_int_operand" "i"))
3199 (match_operand:SI 3 "mask_operand" "T")))]
3200 "includes_lshift_p (operands[2], operands[3])"
3201 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3204 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3206 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3207 (match_operand:SI 2 "const_int_operand" "i"))
3208 (match_operand:SI 3 "mask_operand" "T"))
3210 (clobber (match_scratch:SI 4 "=r"))]
3211 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
3212 "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
3213 [(set_attr "type" "delayed_compare")])
3216 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3218 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3219 (match_operand:SI 2 "const_int_operand" "i"))
3220 (match_operand:SI 3 "mask_operand" "T"))
3222 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3223 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3224 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
3225 "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
3226 [(set_attr "type" "delayed_compare")])
3228 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3230 (define_expand "lshrsi3"
3231 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3232 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3233 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3238 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3240 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3244 (define_insn "lshrsi3_power"
3245 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3246 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3247 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3248 (clobber (match_scratch:SI 3 "=q,X,X"))]
3253 {s%A2i|s%A2wi} %0,%1,%h2")
3255 (define_insn "lshrsi3_no_power"
3256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3257 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3258 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3262 {sr|srw}%I2 %0,%1,%h2")
3265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
3266 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3267 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
3269 (clobber (match_scratch:SI 3 "=r,X,r"))
3270 (clobber (match_scratch:SI 4 "=q,X,X"))]
3275 {s%A2i.|s%A2wi.} %3,%1,%h2"
3276 [(set_attr "type" "delayed_compare")])
3279 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3280 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3281 (match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
3283 (clobber (match_scratch:SI 3 "=X,r"))]
3284 "! TARGET_POWER && ! TARGET_POWERPC64"
3287 {sr|srw}%I2. %3,%1,%h2"
3288 [(set_attr "type" "delayed_compare")])
3291 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x")
3292 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3293 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
3295 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3296 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3297 (clobber (match_scratch:SI 4 "=q,X,X"))]
3302 {s%A2i.|s%A2wi.} %0,%1,%h2"
3303 [(set_attr "type" "delayed_compare")])
3306 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3307 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3308 (match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
3310 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3311 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3312 "! TARGET_POWER && ! TARGET_POWERPC64"
3315 {sr|srw}%I2. %0,%1,%h2"
3316 [(set_attr "type" "delayed_compare")])
3319 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3320 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3321 (match_operand:SI 2 "const_int_operand" "i"))
3322 (match_operand:SI 3 "mask_operand" "T")))]
3323 "includes_rshift_p (operands[2], operands[3])"
3324 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3327 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3329 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3330 (match_operand:SI 2 "const_int_operand" "i"))
3331 (match_operand:SI 3 "mask_operand" "T"))
3333 (clobber (match_scratch:SI 4 "=r"))]
3334 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
3335 "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3"
3336 [(set_attr "type" "delayed_compare")])
3339 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3341 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3342 (match_operand:SI 2 "const_int_operand" "i"))
3343 (match_operand:SI 3 "mask_operand" "T"))
3345 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3346 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3347 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
3348 "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3"
3349 [(set_attr "type" "delayed_compare")])
3352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3355 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3356 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
3357 "includes_rshift_p (operands[2], GEN_INT (255))"
3358 "{rlinm|rlwinm} %0,%1,%s2,0xff")
3361 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3365 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3366 (match_operand:SI 2 "const_int_operand" "i")) 0))
3368 (clobber (match_scratch:SI 3 "=r"))]
3369 "includes_rshift_p (operands[2], GEN_INT (255))"
3370 "{rlinm.|rlwinm.} %3,%1,%s2,0xff"
3371 [(set_attr "type" "delayed_compare")])
3374 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3378 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3379 (match_operand:SI 2 "const_int_operand" "i")) 0))
3381 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3382 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
3383 "includes_rshift_p (operands[2], GEN_INT (255))"
3384 "{rlinm.|rlwinm.} %0,%1,%s2,0xff"
3385 [(set_attr "type" "delayed_compare")])
3388 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3391 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3392 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
3393 "includes_rshift_p (operands[2], GEN_INT (65535))"
3394 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
3397 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3401 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3402 (match_operand:SI 2 "const_int_operand" "i")) 0))
3404 (clobber (match_scratch:SI 3 "=r"))]
3405 "includes_rshift_p (operands[2], GEN_INT (65535))"
3406 "{rlinm.|rlwinm.} %3,%1,%s2,0xffff"
3407 [(set_attr "type" "delayed_compare")])
3410 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3414 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3415 (match_operand:SI 2 "const_int_operand" "i")) 0))
3417 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3418 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
3419 "includes_rshift_p (operands[2], GEN_INT (65535))"
3420 "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
3421 [(set_attr "type" "delayed_compare")])
3424 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3426 (match_operand:SI 1 "gpc_reg_operand" "r"))
3427 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3433 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3435 (match_operand:SI 1 "gpc_reg_operand" "r"))
3436 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3442 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3444 (match_operand:SI 1 "gpc_reg_operand" "r"))
3445 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3451 (define_expand "ashrsi3"
3452 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3453 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3454 (match_operand:SI 2 "reg_or_cint_operand" "")))]
3459 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
3461 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
3465 (define_insn "ashrsi3_power"
3466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3467 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3468 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3469 (clobber (match_scratch:SI 3 "=q,X"))]
3473 {srai|srawi} %0,%1,%h2")
3475 (define_insn "ashrsi3_no_power"
3476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3477 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3478 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3480 "{sra|sraw}%I2 %0,%1,%h2")
3483 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3484 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3485 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3487 (clobber (match_scratch:SI 3 "=r,r"))
3488 (clobber (match_scratch:SI 4 "=q,X"))]
3492 {srai.|srawi.} %3,%1,%h2"
3493 [(set_attr "type" "delayed_compare")])
3496 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3497 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3498 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3500 (clobber (match_scratch:SI 3 "=r"))]
3502 "{sra|sraw}%I2. %3,%1,%h2"
3503 [(set_attr "type" "delayed_compare")])
3506 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3507 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3508 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3510 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3511 (ashiftrt:SI (match_dup 1) (match_dup 2)))
3512 (clobber (match_scratch:SI 4 "=q,X"))]
3516 {srai.|srawi.} %0,%1,%h2"
3517 [(set_attr "type" "delayed_compare")])
3520 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3521 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3522 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3524 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
3525 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
3527 "{sra|sraw}%I2. %0,%1,%h2"
3528 [(set_attr "type" "delayed_compare")])
3530 ;; Floating-point insns, excluding normal data motion.
3532 ;; PowerPC has a full set of single-precision floating point instructions.
3534 ;; For the POWER architecture, we pretend that we have both SFmode and
3535 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
3536 ;; The only conversions we will do will be when storing to memory. In that
3537 ;; case, we will use the "frsp" instruction before storing.
3539 ;; Note that when we store into a single-precision memory location, we need to
3540 ;; use the frsp insn first. If the register being stored isn't dead, we
3541 ;; need a scratch register for the frsp. But this is difficult when the store
3542 ;; is done by reload. It is not incorrect to do the frsp on the register in
3543 ;; this case, we just lose precision that we would have otherwise gotten but
3544 ;; is not guaranteed. Perhaps this should be tightened up at some point.
3546 (define_insn "extendsfdf2"
3547 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3548 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3552 if (REGNO (operands[0]) == REGNO (operands[1]))
3555 return \"fmr %0,%1\";
3557 [(set_attr "type" "fp")])
3559 (define_insn "truncdfsf2"
3560 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3561 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3564 [(set_attr "type" "fp")])
3566 (define_insn "aux_truncdfsf2"
3567 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3568 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
3569 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3571 [(set_attr "type" "fp")])
3573 (define_insn "negsf2"
3574 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3575 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3578 [(set_attr "type" "fp")])
3580 (define_insn "abssf2"
3581 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3582 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3585 [(set_attr "type" "fp")])
3588 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3589 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
3592 [(set_attr "type" "fp")])
3594 (define_expand "addsf3"
3595 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3596 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
3597 (match_operand:SF 2 "gpc_reg_operand" "")))]
3602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3603 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3604 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3605 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3607 [(set_attr "type" "fp")])
3610 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3611 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3612 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3613 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3614 "{fa|fadd} %0,%1,%2"
3615 [(set_attr "type" "fp")])
3617 (define_expand "subsf3"
3618 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3619 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
3620 (match_operand:SF 2 "gpc_reg_operand" "")))]
3625 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3626 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3627 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3628 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3630 [(set_attr "type" "fp")])
3633 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3634 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3635 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3636 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3637 "{fs|fsub} %0,%1,%2"
3638 [(set_attr "type" "fp")])
3640 (define_expand "mulsf3"
3641 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3642 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
3643 (match_operand:SF 2 "gpc_reg_operand" "")))]
3648 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3649 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3650 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3651 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3653 [(set_attr "type" "fp")])
3656 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3657 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3658 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3659 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3660 "{fm|fmul} %0,%1,%2"
3661 [(set_attr "type" "dmul")])
3663 (define_expand "divsf3"
3664 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3665 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
3666 (match_operand:SF 2 "gpc_reg_operand" "")))]
3671 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3672 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3673 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3674 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3676 [(set_attr "type" "sdiv")])
3679 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3680 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3681 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3682 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3683 "{fd|fdiv} %0,%1,%2"
3684 [(set_attr "type" "ddiv")])
3687 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3688 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3689 (match_operand:SF 2 "gpc_reg_operand" "f"))
3690 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3691 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3692 "fmadds %0,%1,%2,%3"
3693 [(set_attr "type" "fp")])
3696 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3697 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3698 (match_operand:SF 2 "gpc_reg_operand" "f"))
3699 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3700 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3701 "{fma|fmadd} %0,%1,%2,%3"
3702 [(set_attr "type" "dmul")])
3705 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3706 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3707 (match_operand:SF 2 "gpc_reg_operand" "f"))
3708 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3709 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3710 "fmsubs %0,%1,%2,%3"
3711 [(set_attr "type" "fp")])
3714 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3715 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3716 (match_operand:SF 2 "gpc_reg_operand" "f"))
3717 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3718 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3719 "{fms|fmsub} %0,%1,%2,%3"
3720 [(set_attr "type" "dmul")])
3723 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3724 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3725 (match_operand:SF 2 "gpc_reg_operand" "f"))
3726 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3727 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3728 "fnmadds %0,%1,%2,%3"
3729 [(set_attr "type" "fp")])
3732 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3733 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3734 (match_operand:SF 2 "gpc_reg_operand" "f"))
3735 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3736 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3737 "{fnma|fnmadd} %0,%1,%2,%3"
3738 [(set_attr "type" "dmul")])
3741 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3742 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3743 (match_operand:SF 2 "gpc_reg_operand" "f"))
3744 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3745 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3746 "fnmsubs %0,%1,%2,%3"
3747 [(set_attr "type" "fp")])
3750 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3751 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3752 (match_operand:SF 2 "gpc_reg_operand" "f"))
3753 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3754 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3755 "{fnms|fnmsub} %0,%1,%2,%3"
3756 [(set_attr "type" "dmul")])
3758 (define_expand "sqrtsf2"
3759 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3760 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
3761 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3765 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3766 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3767 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
3769 [(set_attr "type" "ssqrt")])
3772 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3773 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3774 "TARGET_POWER2 && TARGET_HARD_FLOAT"
3776 [(set_attr "type" "dsqrt")])
3778 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3779 ;; fsel instruction and some auxiliary computations. Then we just have a
3780 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3782 (define_expand "maxsf3"
3784 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
3785 (match_operand:SF 2 "gpc_reg_operand" "")))
3786 (set (match_operand:SF 0 "gpc_reg_operand" "")
3787 (if_then_else:SF (ge (match_dup 3)
3791 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3793 { operands[3] = gen_reg_rtx (SFmode); }")
3796 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3797 (smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
3798 (match_operand:SF 2 "gpc_reg_operand" "")))
3799 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
3800 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3802 (minus:SF (match_dup 1) (match_dup 2)))
3804 (if_then_else:SF (ge (match_dup 3)
3810 (define_expand "minsf3"
3812 (minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
3813 (match_operand:SF 1 "gpc_reg_operand" "")))
3814 (set (match_operand:SF 0 "gpc_reg_operand" "")
3815 (if_then_else:SF (ge (match_dup 3)
3819 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3821 { operands[3] = gen_reg_rtx (SFmode); }")
3824 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3825 (smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
3826 (match_operand:SF 2 "gpc_reg_operand" "")))
3827 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
3828 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3830 (minus:SF (match_dup 2) (match_dup 1)))
3832 (if_then_else:SF (ge (match_dup 3)
3838 (define_expand "movsfcc"
3839 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3840 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3841 (match_operand:SF 2 "gpc_reg_operand" "")
3842 (match_operand:SF 3 "gpc_reg_operand" "")))]
3843 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3847 enum rtx_code code = GET_CODE (operands[1]);
3848 if (! rs6000_compare_fp_p)
3852 case GE: case EQ: case NE:
3853 op0 = rs6000_compare_op0;
3854 op1 = rs6000_compare_op1;
3857 op0 = rs6000_compare_op1;
3858 op1 = rs6000_compare_op0;
3859 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3862 op0 = rs6000_compare_op1;
3863 op1 = rs6000_compare_op0;
3866 op0 = rs6000_compare_op0;
3867 op1 = rs6000_compare_op1;
3868 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3873 if (GET_MODE (rs6000_compare_op0) == DFmode)
3875 temp = gen_reg_rtx (DFmode);
3876 emit_insn (gen_subdf3 (temp, op0, op1));
3877 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
3880 emit_insn (gen_negdf2 (temp, temp));
3881 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3]));
3883 else if (code == NE)
3885 emit_insn (gen_negdf2 (temp, temp));
3886 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0]));
3891 temp = gen_reg_rtx (SFmode);
3892 emit_insn (gen_subsf3 (temp, op0, op1));
3893 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
3896 emit_insn (gen_negsf2 (temp, temp));
3897 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3]));
3899 else if (code == NE)
3901 emit_insn (gen_negsf2 (temp, temp));
3902 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0]));
3908 (define_insn "fselsfsf4"
3909 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3910 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3912 (match_operand:SF 2 "gpc_reg_operand" "f")
3913 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3914 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3916 [(set_attr "type" "fp")])
3918 (define_insn "fseldfsf4"
3919 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3920 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3922 (match_operand:SF 2 "gpc_reg_operand" "f")
3923 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3924 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3926 [(set_attr "type" "fp")])
3928 (define_insn "negdf2"
3929 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3930 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3933 [(set_attr "type" "fp")])
3935 (define_insn "absdf2"
3936 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3937 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3940 [(set_attr "type" "fp")])
3943 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3944 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3947 [(set_attr "type" "fp")])
3949 (define_insn "adddf3"
3950 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3951 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3952 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3954 "{fa|fadd} %0,%1,%2"
3955 [(set_attr "type" "fp")])
3957 (define_insn "subdf3"
3958 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3959 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3960 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3962 "{fs|fsub} %0,%1,%2"
3963 [(set_attr "type" "fp")])
3965 (define_insn "muldf3"
3966 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3967 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3968 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3970 "{fm|fmul} %0,%1,%2"
3971 [(set_attr "type" "dmul")])
3973 (define_insn "divdf3"
3974 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3975 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3976 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3978 "{fd|fdiv} %0,%1,%2"
3979 [(set_attr "type" "ddiv")])
3982 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3983 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3984 (match_operand:DF 2 "gpc_reg_operand" "f"))
3985 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3986 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3987 "{fma|fmadd} %0,%1,%2,%3"
3988 [(set_attr "type" "dmul")])
3991 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3992 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3993 (match_operand:DF 2 "gpc_reg_operand" "f"))
3994 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3995 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3996 "{fms|fmsub} %0,%1,%2,%3"
3997 [(set_attr "type" "dmul")])
4000 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4001 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4002 (match_operand:DF 2 "gpc_reg_operand" "f"))
4003 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4004 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4005 "{fnma|fnmadd} %0,%1,%2,%3"
4006 [(set_attr "type" "dmul")])
4009 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4010 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4011 (match_operand:DF 2 "gpc_reg_operand" "f"))
4012 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4013 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4014 "{fnms|fnmsub} %0,%1,%2,%3"
4015 [(set_attr "type" "dmul")])
4017 (define_insn "sqrtdf2"
4018 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4019 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4020 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
4022 [(set_attr "type" "dsqrt")])
4024 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4025 ;; fsel instruction and some auxiliary computations. Then we just have a
4026 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4029 (define_expand "maxdf3"
4031 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4032 (match_operand:DF 2 "gpc_reg_operand" "")))
4033 (set (match_operand:DF 0 "gpc_reg_operand" "")
4034 (if_then_else:DF (ge (match_dup 3)
4038 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4040 { operands[3] = gen_reg_rtx (DFmode); }")
4043 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4044 (smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
4045 (match_operand:DF 2 "gpc_reg_operand" "")))
4046 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
4047 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4049 (minus:DF (match_dup 1) (match_dup 2)))
4051 (if_then_else:DF (ge (match_dup 3)
4057 (define_expand "mindf3"
4059 (minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
4060 (match_operand:DF 1 "gpc_reg_operand" "")))
4061 (set (match_operand:DF 0 "gpc_reg_operand" "")
4062 (if_then_else:DF (ge (match_dup 3)
4066 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4068 { operands[3] = gen_reg_rtx (DFmode); }")
4071 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4072 (smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
4073 (match_operand:DF 2 "gpc_reg_operand" "")))
4074 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
4075 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4077 (minus:DF (match_dup 2) (match_dup 1)))
4079 (if_then_else:DF (ge (match_dup 3)
4085 (define_expand "movdfcc"
4086 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4087 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4088 (match_operand:DF 2 "gpc_reg_operand" "")
4089 (match_operand:DF 3 "gpc_reg_operand" "")))]
4090 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4094 enum rtx_code code = GET_CODE (operands[1]);
4095 if (! rs6000_compare_fp_p)
4099 case GE: case EQ: case NE:
4100 op0 = rs6000_compare_op0;
4101 op1 = rs6000_compare_op1;
4104 op0 = rs6000_compare_op1;
4105 op1 = rs6000_compare_op0;
4106 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
4109 op0 = rs6000_compare_op1;
4110 op1 = rs6000_compare_op0;
4113 op0 = rs6000_compare_op0;
4114 op1 = rs6000_compare_op1;
4115 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
4120 if (GET_MODE (rs6000_compare_op0) == DFmode)
4122 temp = gen_reg_rtx (DFmode);
4123 emit_insn (gen_subdf3 (temp, op0, op1));
4124 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
4127 emit_insn (gen_negdf2 (temp, temp));
4128 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3]));
4130 else if (code == NE)
4132 emit_insn (gen_negdf2 (temp, temp));
4133 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0]));
4138 temp = gen_reg_rtx (SFmode);
4139 emit_insn (gen_subsf3 (temp, op0, op1));
4140 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
4143 emit_insn (gen_negsf2 (temp, temp));
4144 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3]));
4146 else if (code == NE)
4148 emit_insn (gen_negsf2 (temp, temp));
4149 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0]));
4155 (define_insn "fseldfdf4"
4156 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4157 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4159 (match_operand:DF 2 "gpc_reg_operand" "f")
4160 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4161 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4163 [(set_attr "type" "fp")])
4165 (define_insn "fselsfdf4"
4166 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4167 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4169 (match_operand:DF 2 "gpc_reg_operand" "f")
4170 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4173 [(set_attr "type" "fp")])
4175 ;; Conversions to and from floating-point.
4177 (define_expand "floatsidf2"
4178 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4179 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4182 (clobber (match_dup 4))
4183 (clobber (match_dup 5))
4184 (clobber (reg:DF 76))])]
4185 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
4188 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
4189 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
4190 operands[4] = gen_reg_rtx (SImode);
4191 operands[5] = gen_reg_rtx (Pmode);
4194 (define_insn "*floatsidf2_internal"
4195 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
4196 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
4197 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
4198 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
4199 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
4200 (clobber (match_operand 5 "gpc_reg_operand" "=b"))
4201 (clobber (reg:DF 76))]
4202 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
4204 [(set_attr "length" "24")])
4207 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4208 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4209 (use (match_operand:SI 2 "gpc_reg_operand" ""))
4210 (use (match_operand:DF 3 "gpc_reg_operand" ""))
4211 (clobber (match_operand:SI 4 "gpc_reg_operand" ""))
4212 (clobber (match_operand 5 "gpc_reg_operand" ""))
4213 (clobber (reg:DF 76))]
4214 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
4216 (xor:SI (match_dup 1)
4219 (unspec [(const_int 0)] 11))
4221 (unspec [(match_dup 4)
4222 (match_dup 5)] 12)) ;; low word
4224 (unspec [(match_dup 2)
4226 (match_dup 7)] 13)) ;; high word
4228 (unspec [(match_dup 7)
4231 (minus:DF (match_dup 0)
4235 operands[6] = GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff);
4236 operands[7] = gen_rtx_REG (DFmode, FPMEM_REGNUM);
4239 (define_expand "floatunssidf2"
4240 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4241 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4244 (clobber (match_dup 4))
4245 (clobber (reg:DF 76))])]
4246 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
4249 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
4250 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
4251 operands[4] = gen_reg_rtx (Pmode);
4254 (define_insn "*floatunssidf2_internal"
4255 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
4256 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
4257 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
4258 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
4259 (clobber (match_operand 4 "gpc_reg_operand" "=b"))
4260 (clobber (reg:DF 76))]
4261 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
4263 [(set_attr "length" "20")])
4266 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4267 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4268 (use (match_operand:SI 2 "gpc_reg_operand" ""))
4269 (use (match_operand:DF 3 "gpc_reg_operand" ""))
4270 (clobber (match_operand 4 "gpc_reg_operand" ""))
4271 (clobber (reg:DF 76))]
4272 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
4274 (unspec [(const_int 0)] 11))
4276 (unspec [(match_dup 1)
4277 (match_dup 4)] 12)) ;; low word
4279 (unspec [(match_dup 2)
4281 (match_dup 5)] 13)) ;; high word
4283 (unspec [(match_dup 5)
4286 (minus:DF (match_dup 0)
4288 "operands[5] = gen_rtx_REG (DFmode, FPMEM_REGNUM);")
4290 ;; Load up scratch register with base address + offset if needed
4291 (define_insn "*floatsidf2_loadaddr"
4292 [(set (match_operand 0 "gpc_reg_operand" "=b")
4293 (unspec [(const_int 0)] 11))]
4297 if (rs6000_fpmem_offset > 32760)
4301 xop[0] = operands[0];
4302 xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx;
4303 xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16) + ((rs6000_fpmem_offset & 0x8000) >> 15));
4304 output_asm_insn (\"{cau|addis} %0,%1,%2\", xop);
4309 [(set_attr "length" "4")])
4311 (define_insn "*floatsidf2_store1"
4313 (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
4314 (match_operand 1 "gpc_reg_operand" "b")] 12))]
4320 if (rs6000_fpmem_offset > 32760)
4322 else if (frame_pointer_needed)
4323 indx = frame_pointer_rtx;
4325 indx = stack_pointer_rtx;
4328 = gen_rtx_MEM (SImode,
4329 plus_constant (indx,
4330 (((rs6000_fpmem_offset & 0xffff) ^ 0x8000)
4332 + ((WORDS_BIG_ENDIAN != 0) * 4)));
4334 return \"{st|stw} %0,%2\";
4336 [(set_attr "type" "store")])
4338 (define_insn "*floatsidf2_store2"
4340 (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
4341 (match_operand 1 "gpc_reg_operand" "b")
4348 if (rs6000_fpmem_offset > 32760)
4350 else if (frame_pointer_needed)
4351 indx = frame_pointer_rtx;
4353 indx = stack_pointer_rtx;
4356 = gen_rtx_MEM (SImode,
4357 plus_constant (indx,
4358 (((rs6000_fpmem_offset & 0xffff) ^ 0x8000)
4360 + ((WORDS_BIG_ENDIAN == 0) * 4)));
4362 return \"{st|stw} %0,%2\";
4364 [(set_attr "type" "store")])
4366 (define_insn "*floatsidf2_load"
4367 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4368 (unspec [(reg:DF 76)
4369 (match_operand 1 "gpc_reg_operand" "b")] 14))]
4374 HOST_WIDE_INT offset = rs6000_fpmem_offset;
4376 if (rs6000_fpmem_offset > 32760)
4379 offset = (((offset & 0xffff) ^ 0x8000) - 0x8000);
4381 else if (frame_pointer_needed)
4382 indx = frame_pointer_rtx;
4384 indx = stack_pointer_rtx;
4386 operands[2] = gen_rtx_MEM (SImode, plus_constant (indx, offset));
4388 return \"lfd %0,%2\";
4390 [(set_attr "type" "fpload")])
4392 (define_expand "fix_truncdfsi2"
4393 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
4394 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
4395 (clobber (match_dup 2))
4396 (clobber (match_dup 3))
4397 (clobber (match_dup 4))])]
4401 if (! TARGET_POWER2 && ! TARGET_POWERPC)
4403 emit_insn (gen_trunc_call (operands[0], operands[1],
4404 gen_rtx_SYMBOL_REF (Pmode, RS6000_ITRUNC)));
4408 operands[2] = gen_reg_rtx (DImode);
4409 operands[3] = gen_reg_rtx (Pmode);
4410 operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);
4413 (define_insn "*fix_truncdfsi2_internal"
4414 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4415 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
4416 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
4417 (clobber (match_operand 3 "gpc_reg_operand" "=b"))
4418 (clobber (reg:DI 76))]
4421 [(set_attr "length" "12")])
4424 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4425 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
4426 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
4427 (clobber (match_operand 3 "gpc_reg_operand" ""))
4428 (clobber (reg:DI 76))]
4430 [(clobber (match_dup 2))
4431 (set (subreg:SI (match_dup 2) 0)
4432 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
4434 (unspec [(const_int 0)] 11))
4436 (unspec [(match_dup 2)
4438 (set (match_operand:SI 0 "gpc_reg_operand" "")
4439 (unspec [(match_dup 4)
4440 (match_dup 3)] 16))]
4441 "operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);")
4443 (define_insn "*fix_truncdfsi2_store"
4445 (unspec [(match_operand:DI 0 "gpc_reg_operand" "f")
4446 (match_operand 1 "gpc_reg_operand" "b")] 15))]
4447 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
4452 if (rs6000_fpmem_offset > 32760)
4454 else if (frame_pointer_needed)
4455 indx = frame_pointer_rtx;
4457 indx = stack_pointer_rtx;
4459 operands[2] = gen_rtx_MEM (DFmode,
4460 plus_constant (indx,
4461 (((rs6000_fpmem_offset & 0xffff)
4462 ^ 0x8000) - 0x8000)));
4464 return \"stfd %0,%2\";
4466 [(set_attr "type" "fpstore")])
4468 (define_insn "*fix_truncdfsi2_load"
4469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4470 (unspec [(reg:DI 76)
4471 (match_operand 1 "gpc_reg_operand" "b")] 16))]
4472 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
4477 if (rs6000_fpmem_offset > 32760)
4479 else if (frame_pointer_needed)
4480 indx = frame_pointer_rtx;
4482 indx = stack_pointer_rtx;
4485 = gen_rtx_MEM (DFmode,
4486 plus_constant (indx,
4487 (((rs6000_fpmem_offset & 0xffff) ^ 0x8000)
4489 + ((WORDS_BIG_ENDIAN) ? 4 : 0)));
4491 return \"{l|lwz} %0,%2\";
4493 [(set_attr "type" "load")])
4495 (define_expand "fixuns_truncdfsi2"
4496 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4497 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
4498 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
4501 emit_insn (gen_trunc_call (operands[0], operands[1],
4502 gen_rtx_SYMBOL_REF (Pmode, RS6000_UITRUNC)));
4506 (define_expand "trunc_call"
4507 [(parallel [(set (match_operand:SI 0 "" "")
4508 (fix:SI (match_operand:DF 1 "" "")))
4509 (use (match_operand:SI 2 "" ""))])]
4513 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
4514 rtx first = XVECEXP (insns, 0, 0);
4515 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
4517 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
4519 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
4525 (define_expand "trunc_call_rtl"
4526 [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
4528 (parallel [(set (reg:SI 3)
4529 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
4531 (clobber (scratch:SI))])
4532 (set (match_operand:SI 0 "gpc_reg_operand" "")
4537 rs6000_trunc_used = 1;
4540 (define_insn "*fctiwz"
4541 [(set (subreg:SI (match_operand:DI 0 "gpc_reg_operand" "=f") 0)
4542 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))]
4543 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
4544 "{fcirz|fctiwz} %0,%1"
4545 [(set_attr "type" "fp")])
4547 (define_insn "floatdidf2"
4548 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4549 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
4550 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
4552 [(set_attr "type" "fp")])
4554 (define_insn "fix_truncdfdi2"
4555 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
4556 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
4557 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
4559 [(set_attr "type" "fp")])
4561 ;; Define the DImode operations that can be done in a small number
4562 ;; of instructions. The & constraints are to prevent the register
4563 ;; allocator from allocating registers that overlap with the inputs
4564 ;; (for example, having an input in 7,8 and an output in 6,7). We
4565 ;; also allow for the output being the same as one of the inputs.
4567 (define_insn "*adddi3_noppc64"
4568 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
4569 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
4570 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
4571 "! TARGET_POWERPC64"
4574 if (WORDS_BIG_ENDIAN)
4575 return (GET_CODE (operands[2])) != CONST_INT
4576 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
4577 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
4579 return (GET_CODE (operands[2])) != CONST_INT
4580 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
4581 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
4583 [(set_attr "length" "8")])
4585 (define_insn "*subdi3_noppc64"
4586 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
4587 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
4588 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
4589 "! TARGET_POWERPC64"
4592 if (WORDS_BIG_ENDIAN)
4593 return (GET_CODE (operands[1]) != CONST_INT)
4594 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
4595 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
4597 return (GET_CODE (operands[1]) != CONST_INT)
4598 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
4599 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
4601 [(set_attr "length" "8")])
4603 (define_insn "*negdi2_noppc64"
4604 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4605 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
4606 "! TARGET_POWERPC64"
4609 return (WORDS_BIG_ENDIAN)
4610 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
4611 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
4613 [(set_attr "length" "8")])
4615 (define_expand "mulsidi3"
4616 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4617 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4618 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4619 "! TARGET_POWERPC64"
4622 if (! TARGET_POWER && ! TARGET_POWERPC)
4624 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
4625 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
4626 emit_insn (gen_mull_call ());
4627 if (WORDS_BIG_ENDIAN)
4628 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
4631 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
4632 gen_rtx_REG (SImode, 3));
4633 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
4634 gen_rtx_REG (SImode, 4));
4638 else if (TARGET_POWER)
4640 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
4645 (define_insn "mulsidi3_mq"
4646 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4647 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4648 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
4649 (clobber (match_scratch:SI 3 "=q"))]
4651 "mul %0,%1,%2\;mfmq %L0"
4652 [(set_attr "type" "imul")
4653 (set_attr "length" "8")])
4655 (define_insn "*mulsidi3_no_mq"
4656 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4657 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4658 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
4659 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
4662 return (WORDS_BIG_ENDIAN)
4663 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
4664 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
4666 [(set_attr "type" "imul")
4667 (set_attr "length" "8")])
4670 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4671 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4672 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4673 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
4676 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
4677 (sign_extend:DI (match_dup 2)))
4680 (mult:SI (match_dup 1)
4684 int endian = (WORDS_BIG_ENDIAN == 0);
4685 operands[3] = operand_subword (operands[0], endian, 0, DImode);
4686 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
4689 (define_expand "umulsidi3"
4690 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4691 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4692 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4693 "TARGET_POWERPC && ! TARGET_POWERPC64"
4698 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
4703 (define_insn "umulsidi3_mq"
4704 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4705 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4706 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
4707 (clobber (match_scratch:SI 3 "=q"))]
4708 "TARGET_POWERPC && TARGET_POWER"
4711 return (WORDS_BIG_ENDIAN)
4712 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
4713 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
4715 [(set_attr "type" "imul")
4716 (set_attr "length" "8")])
4718 (define_insn "*umulsidi3_no_mq"
4719 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4720 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4721 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
4722 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
4725 return (WORDS_BIG_ENDIAN)
4726 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
4727 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
4729 [(set_attr "type" "imul")
4730 (set_attr "length" "8")])
4733 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4734 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4735 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4736 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
4739 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
4740 (zero_extend:DI (match_dup 2)))
4743 (mult:SI (match_dup 1)
4747 int endian = (WORDS_BIG_ENDIAN == 0);
4748 operands[3] = operand_subword (operands[0], endian, 0, DImode);
4749 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
4752 (define_expand "smulsi3_highpart"
4753 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4755 (lshiftrt:DI (mult:DI (sign_extend:DI
4756 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4758 (match_operand:SI 2 "gpc_reg_operand" "r")))
4763 if (! TARGET_POWER && ! TARGET_POWERPC)
4765 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
4766 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
4767 emit_insn (gen_mulh_call ());
4768 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
4771 else if (TARGET_POWER)
4773 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
4778 (define_insn "smulsi3_highpart_mq"
4779 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4781 (lshiftrt:DI (mult:DI (sign_extend:DI
4782 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4784 (match_operand:SI 2 "gpc_reg_operand" "r")))
4786 (clobber (match_scratch:SI 3 "=q"))]
4789 [(set_attr "type" "imul")])
4791 (define_insn "*smulsi3_highpart_no_mq"
4792 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4794 (lshiftrt:DI (mult:DI (sign_extend:DI
4795 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4797 (match_operand:SI 2 "gpc_reg_operand" "r")))
4799 "TARGET_POWERPC && ! TARGET_POWER"
4801 [(set_attr "type" "imul")])
4803 (define_expand "umulsi3_highpart"
4804 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4806 (lshiftrt:DI (mult:DI (zero_extend:DI
4807 (match_operand:SI 1 "gpc_reg_operand" ""))
4809 (match_operand:SI 2 "gpc_reg_operand" "")))
4816 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
4821 (define_insn "umulsi3_highpart_mq"
4822 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4824 (lshiftrt:DI (mult:DI (zero_extend:DI
4825 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4827 (match_operand:SI 2 "gpc_reg_operand" "r")))
4829 (clobber (match_scratch:SI 3 "=q"))]
4830 "TARGET_POWERPC && TARGET_POWER"
4832 [(set_attr "type" "imul")])
4834 (define_insn "*umulsi3_highpart_no_mq"
4835 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4837 (lshiftrt:DI (mult:DI (zero_extend:DI
4838 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4840 (match_operand:SI 2 "gpc_reg_operand" "r")))
4842 "TARGET_POWERPC && ! TARGET_POWER"
4844 [(set_attr "type" "imul")])
4846 ;; If operands 0 and 2 are in the same register, we have a problem. But
4847 ;; operands 0 and 1 (the usual case) can be in the same register. That's
4848 ;; why we have the strange constraints below.
4849 (define_insn "ashldi3_power"
4850 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
4851 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
4852 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
4853 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
4856 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
4857 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
4858 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
4859 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
4860 [(set_attr "length" "8")])
4862 (define_insn "lshrdi3_power"
4863 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
4864 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
4865 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
4866 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
4869 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
4870 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
4871 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
4872 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
4873 [(set_attr "length" "8")])
4875 ;; Shift by a variable amount is too complex to be worth open-coding. We
4876 ;; just handle shifts by constants.
4877 (define_insn "ashrdi3_power"
4878 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4879 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
4880 (match_operand:SI 2 "const_int_operand" "M,i")))
4881 (clobber (match_scratch:SI 3 "=X,q"))]
4884 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
4885 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
4886 [(set_attr "length" "8")])
4888 ;; PowerPC64 DImode operations.
4890 (define_expand "adddi3"
4891 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4892 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
4893 (match_operand:DI 2 "reg_or_cint_operand" "")))]
4897 if (! TARGET_POWERPC64)
4899 if (non_short_cint_operand (operands[2], DImode))
4903 if (GET_CODE (operands[2]) == CONST_INT
4904 && ! add_operand (operands[2], DImode))
4906 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
4907 ? operands[0] : gen_reg_rtx (DImode));
4909 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
4910 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
4913 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
4915 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high)));
4916 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
4921 ;; Discourage ai/addic because of carry but provide it in an alternative
4922 ;; allowing register zero as source.
4924 (define_insn "*adddi3_internal1"
4925 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
4926 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
4927 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
4935 (define_insn "*adddi3_internal2"
4936 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4937 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
4938 (match_operand:DI 2 "reg_or_short_operand" "r,I"))
4940 (clobber (match_scratch:DI 3 "=r,r"))]
4945 [(set_attr "type" "compare")])
4947 (define_insn "*adddi3_internal3"
4948 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4949 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
4950 (match_operand:DI 2 "reg_or_short_operand" "r,I"))
4952 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4953 (plus:DI (match_dup 1) (match_dup 2)))]
4958 [(set_attr "type" "compare")])
4960 ;; Split an add that we can't do in one insn into two insns, each of which
4961 ;; does one 16-bit part. This is used by combine. Note that the low-order
4962 ;; add should be last in case the result gets used in an address.
4965 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4966 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
4967 (match_operand:DI 2 "non_add_cint_operand" "")))]
4969 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
4970 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
4973 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
4974 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
4977 high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
4979 operands[3] = GEN_INT (high);
4980 operands[4] = GEN_INT (low);
4983 (define_insn "one_cmpldi2"
4984 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4985 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4990 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4991 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4993 (clobber (match_scratch:DI 2 "=r"))]
4996 [(set_attr "type" "compare")])
4999 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
5000 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5002 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5003 (not:DI (match_dup 1)))]
5006 [(set_attr "type" "compare")])
5009 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5010 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5011 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5018 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5019 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5020 (match_operand:DI 2 "gpc_reg_operand" "r"))
5022 (clobber (match_scratch:DI 3 "=r"))]
5025 [(set_attr "type" "compare")])
5028 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5029 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5030 (match_operand:DI 2 "gpc_reg_operand" "r"))
5032 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5033 (minus:DI (match_dup 1) (match_dup 2)))]
5036 [(set_attr "type" "compare")])
5038 (define_expand "subdi3"
5039 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5040 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5041 (match_operand:DI 2 "reg_or_cint_operand" "")))]
5045 if (GET_CODE (operands[2]) == CONST_INT)
5047 emit_insn (gen_adddi3 (operands[0], operands[1],
5048 negate_rtx (DImode, operands[2])));
5053 (define_insn "absdi2"
5054 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5055 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5056 (clobber (match_scratch:DI 2 "=&r,&r"))]
5058 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0"
5059 [(set_attr "length" "12")])
5062 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5063 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5064 (clobber (match_scratch:DI 2 "=&r,&r"))]
5065 "TARGET_POWERPC64 && reload_completed"
5066 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5067 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5068 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5071 (define_insn "*nabsdi2"
5072 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5073 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5074 (clobber (match_scratch:DI 2 "=&r,&r"))]
5076 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2"
5077 [(set_attr "length" "12")])
5080 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5081 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5082 (clobber (match_scratch:DI 2 "=&r,&r"))]
5083 "TARGET_POWERPC64 && reload_completed"
5084 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5085 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5086 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5089 (define_expand "negdi2"
5090 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5091 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5096 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5097 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5102 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5103 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5105 (clobber (match_scratch:DI 2 "=r"))]
5108 [(set_attr "type" "compare")])
5111 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
5112 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5114 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5115 (neg:DI (match_dup 1)))]
5118 [(set_attr "type" "compare")])
5120 (define_insn "ffsdi2"
5121 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5122 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5124 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
5125 [(set_attr "length" "16")])
5127 (define_insn "muldi3"
5128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5129 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5130 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5133 [(set_attr "type" "lmul")])
5135 (define_insn "smuldi3_highpart"
5136 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5138 (lshiftrt:TI (mult:TI (sign_extend:TI
5139 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5141 (match_operand:DI 2 "gpc_reg_operand" "r")))
5145 [(set_attr "type" "lmul")])
5147 (define_insn "umuldi3_highpart"
5148 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5150 (lshiftrt:TI (mult:TI (zero_extend:TI
5151 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5153 (match_operand:DI 2 "gpc_reg_operand" "r")))
5157 [(set_attr "type" "lmul")])
5159 (define_expand "divdi3"
5160 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5161 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
5162 (match_operand:DI 2 "reg_or_cint_operand" "")))]
5166 if (GET_CODE (operands[2]) == CONST_INT
5167 && exact_log2 (INTVAL (operands[2])) >= 0)
5170 operands[2] = force_reg (DImode, operands[2]);
5173 (define_expand "moddi3"
5174 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
5175 (use (match_operand:DI 1 "gpc_reg_operand" ""))
5176 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
5180 int i = exact_log2 (INTVAL (operands[2]));
5184 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
5187 temp1 = gen_reg_rtx (DImode);
5188 temp2 = gen_reg_rtx (DImode);
5190 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
5191 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
5192 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
5197 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5198 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5199 (match_operand:DI 2 "const_int_operand" "N")))]
5200 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
5201 "sradi %0,%1,%p2\;addze %0,%0"
5202 [(set_attr "length" "8")])
5205 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5206 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5207 (match_operand:DI 2 "const_int_operand" "N"))
5209 (clobber (match_scratch:DI 3 "=r"))]
5210 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
5211 "sradi %3,%1,%p2\;addze. %3,%3"
5212 [(set_attr "type" "compare")
5213 (set_attr "length" "8")])
5216 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5217 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5218 (match_operand:DI 2 "const_int_operand" "N"))
5220 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5221 (div:DI (match_dup 1) (match_dup 2)))]
5222 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
5223 "sradi %0,%1,%p2\;addze. %0,%0"
5224 [(set_attr "type" "compare")
5225 (set_attr "length" "8")])
5228 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5229 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5230 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5233 [(set_attr "type" "ldiv")])
5235 (define_insn "udivdi3"
5236 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5237 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5238 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5241 [(set_attr "type" "ldiv")])
5243 (define_insn "rotldi3"
5244 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5245 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5246 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
5248 "rld%I2cl %0,%1,%H2,0")
5250 (define_insn "*rotldi3_internal2"
5251 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5252 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5253 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
5255 (clobber (match_scratch:DI 3 "=r"))]
5257 "rld%I2cl. %3,%1,%H2,0"
5258 [(set_attr "type" "delayed_compare")])
5260 (define_insn "*rotldi3_internal3"
5261 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5262 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5263 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
5265 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5266 (rotate:DI (match_dup 1) (match_dup 2)))]
5268 "rld%I2cl. %0,%1,%H2,0"
5269 [(set_attr "type" "delayed_compare")])
5271 (define_insn "*rotldi3_internal4"
5272 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5273 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5274 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
5275 (match_operand:DI 3 "mask64_operand" "S")))]
5277 "rld%I2c%B3 %0,%1,%H2,%S3")
5279 (define_insn "*rotldi3_internal5"
5280 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5282 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5283 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
5284 (match_operand:DI 3 "mask64_operand" "S"))
5286 (clobber (match_scratch:DI 4 "=r"))]
5288 "rld%I2c%B3. %4,%1,%H2,%S3"
5289 [(set_attr "type" "delayed_compare")])
5291 (define_insn "*rotldi3_internal6"
5292 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
5294 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5295 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
5296 (match_operand:DI 3 "mask64_operand" "S"))
5298 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5299 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5301 "rld%I2c%B3. %0,%1,%H2,%S3"
5302 [(set_attr "type" "delayed_compare")])
5304 (define_insn "*rotldi3_internal7"
5305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5308 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5309 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
5311 "rld%I2cl %0,%1,%H2,56")
5313 (define_insn "*rotldi3_internal8"
5314 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5315 (compare:CC (zero_extend:DI
5317 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5318 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
5320 (clobber (match_scratch:DI 3 "=r"))]
5322 "rld%I2cl. %3,%1,%H2,56"
5323 [(set_attr "type" "delayed_compare")])
5325 (define_insn "*rotldi3_internal9"
5326 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5327 (compare:CC (zero_extend:DI
5329 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5330 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
5332 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5333 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
5335 "rld%I2cl. %0,%1,%H2,56"
5336 [(set_attr "type" "delayed_compare")])
5338 (define_insn "*rotldi3_internal10"
5339 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5342 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5343 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
5345 "rld%I2cl %0,%1,%H2,48")
5347 (define_insn "*rotldi3_internal11"
5348 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5349 (compare:CC (zero_extend:DI
5351 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5352 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
5354 (clobber (match_scratch:DI 3 "=r"))]
5356 "rld%I2cl. %3,%1,%H2,48"
5357 [(set_attr "type" "delayed_compare")])
5359 (define_insn "*rotldi3_internal12"
5360 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5361 (compare:CC (zero_extend:DI
5363 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5364 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
5366 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5367 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
5369 "rld%I2cl. %0,%1,%H2,48"
5370 [(set_attr "type" "delayed_compare")])
5372 (define_insn "*rotldi3_internal13"
5373 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5376 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5377 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
5379 "rld%I2cl %0,%1,%H2,32")
5381 (define_insn "*rotldi3_internal14"
5382 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5383 (compare:CC (zero_extend:DI
5385 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5386 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
5388 (clobber (match_scratch:DI 3 "=r"))]
5390 "rld%I2cl. %3,%1,%H2,32"
5391 [(set_attr "type" "delayed_compare")])
5393 (define_insn "*rotldi3_internal15"
5394 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5395 (compare:CC (zero_extend:DI
5397 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5398 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
5400 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5401 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
5403 "rld%I2cl. %0,%1,%H2,32"
5404 [(set_attr "type" "delayed_compare")])
5406 (define_expand "ashldi3"
5407 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5408 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
5409 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5410 "TARGET_POWERPC64 || TARGET_POWER"
5413 if (TARGET_POWERPC64)
5415 else if (TARGET_POWER)
5417 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
5425 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5426 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5427 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
5430 [(set_attr "length" "8")])
5433 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5434 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5435 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
5437 (clobber (match_scratch:DI 3 "=r"))]
5440 [(set_attr "type" "delayed_compare")])
5443 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5444 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5445 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
5447 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5448 (ashift:DI (match_dup 1) (match_dup 2)))]
5451 [(set_attr "type" "delayed_compare")])
5454 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5455 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5456 (match_operand:SI 2 "const_int_operand" "i"))
5457 (match_operand:DI 3 "mask64_operand" "S")))]
5458 "((GET_CODE (operands[3]) == CONST_INT
5459 ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
5460 "rldic %0,%1,%H2,%S3")
5463 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5465 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5466 (match_operand:SI 2 "const_int_operand" "i"))
5467 (match_operand:DI 3 "mask64_operand" "S"))
5469 (clobber (match_scratch:DI 4 "=r"))]
5470 "((GET_CODE (operands[3]) == CONST_INT
5471 ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
5472 "rldic. %0,%1,%H2,%S3"
5473 [(set_attr "type" "delayed_compare")])
5476 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
5478 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5479 (match_operand:SI 2 "const_int_operand" "i"))
5480 (match_operand:DI 3 "mask64_operand" "S"))
5482 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5483 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5484 "((GET_CODE (operands[3]) == CONST_INT
5485 ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
5486 "rldic. %0,%1,%H2,%S3"
5487 [(set_attr "type" "delayed_compare")])
5489 (define_expand "lshrdi3"
5490 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5491 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
5492 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5493 "TARGET_POWERPC64 || TARGET_POWER"
5496 if (TARGET_POWERPC64)
5498 else if (TARGET_POWER)
5500 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
5508 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5509 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5510 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
5515 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5516 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5517 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
5519 (clobber (match_scratch:DI 3 "=r"))]
5522 [(set_attr "type" "delayed_compare")])
5525 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5526 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5527 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
5529 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5530 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
5533 [(set_attr "type" "delayed_compare")])
5535 (define_expand "ashrdi3"
5536 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5537 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
5538 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5539 "TARGET_POWERPC64 || TARGET_POWER"
5542 if (TARGET_POWERPC64)
5544 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
5546 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
5554 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5555 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5556 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
5558 "srad%I2 %0,%1,%H2")
5561 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5562 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5563 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
5565 (clobber (match_scratch:DI 3 "=r"))]
5567 "srad%I2. %3,%1,%H2"
5568 [(set_attr "type" "delayed_compare")])
5571 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5572 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5573 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
5575 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5576 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5578 "srad%I2. %0,%1,%H2"
5579 [(set_attr "type" "delayed_compare")])
5581 (define_insn "anddi3"
5582 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5583 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5584 (match_operand:DI 2 "and64_operand" "?r,S,K,J")))
5585 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
5589 rldic%B2 %0,%1,0,%S2
5593 (define_insn "*anddi3_internal2"
5594 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
5595 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5596 (match_operand:DI 2 "and64_operand" "r,K,J,S"))
5598 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5604 rldic%B2. %3,%1,0,%S2"
5605 [(set_attr "type" "compare,compare,compare,delayed_compare")])
5607 (define_insn "*anddi3_internal3"
5608 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
5609 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5610 (match_operand:DI 2 "and64_operand" "r,K,J,S"))
5612 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5613 (and:DI (match_dup 1) (match_dup 2)))]
5619 rldic%B2. %0,%1,0,%S2"
5620 [(set_attr "type" "compare,compare,compare,delayed_compare")])
5622 (define_expand "iordi3"
5623 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5624 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
5625 (match_operand:DI 2 "reg_or_cint_operand" "")))]
5629 if (GET_CODE (operands[2]) == CONST_INT
5630 && ! logical_operand (operands[2], DImode))
5632 HOST_WIDE_INT value = INTVAL (operands[2]);
5633 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5634 ? operands[0] : gen_reg_rtx (DImode));
5636 emit_insn (gen_iordi3 (tmp, operands[1],
5637 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
5638 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
5643 (define_insn "*iordi3_internal1"
5644 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
5645 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
5646 (match_operand:DI 2 "logical_operand" "r,K,J")))]
5653 (define_insn "*iordi3_internal2"
5654 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5655 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5656 (match_operand:DI 2 "gpc_reg_operand" "r"))
5658 (clobber (match_scratch:DI 3 "=r"))]
5661 [(set_attr "type" "compare")])
5663 (define_insn "*iordi3_internal3"
5664 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5665 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5666 (match_operand:DI 2 "gpc_reg_operand" "r"))
5668 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5669 (ior:DI (match_dup 1) (match_dup 2)))]
5672 [(set_attr "type" "compare")])
5674 ;; Split an IOR that we can't do in one insn into two insns, each of which
5675 ;; does one 16-bit part. This is used by combine.
5678 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5679 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
5680 (match_operand:DI 2 "non_logical_cint_operand" "")))]
5682 [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3)))
5683 (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))]
5686 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
5687 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
5690 (define_expand "xordi3"
5691 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5692 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
5693 (match_operand:DI 2 "reg_or_cint_operand" "")))]
5697 if (GET_CODE (operands[2]) == CONST_INT
5698 && ! logical_operand (operands[2], DImode))
5700 HOST_WIDE_INT value = INTVAL (operands[2]);
5701 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5702 ? operands[0] : gen_reg_rtx (DImode));
5704 emit_insn (gen_xordi3 (tmp, operands[1],
5705 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
5706 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
5711 (define_insn "*xordi3_internal1"
5712 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
5713 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
5714 (match_operand:DI 2 "logical_operand" "r,K,J")))]
5721 (define_insn "*xordi3_internal2"
5722 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5723 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5724 (match_operand:DI 2 "gpc_reg_operand" "r"))
5726 (clobber (match_scratch:DI 3 "=r"))]
5729 [(set_attr "type" "compare")])
5731 (define_insn "*xordi3_internal3"
5732 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5733 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5734 (match_operand:DI 2 "gpc_reg_operand" "r"))
5736 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5737 (xor:DI (match_dup 1) (match_dup 2)))]
5740 [(set_attr "type" "compare")])
5742 ;; Split an XOR that we can't do in one insn into two insns, each of which
5743 ;; does one 16-bit part. This is used by combine.
5746 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5747 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
5748 (match_operand:DI 2 "non_logical_cint_operand" "")))]
5750 [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3)))
5751 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))]
5754 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
5755 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
5758 (define_insn "*eqvdi3_internal1"
5759 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5760 (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5761 (match_operand:DI 2 "gpc_reg_operand" "r"))))]
5765 (define_insn "*eqvdi3_internal2"
5766 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5767 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5768 (match_operand:DI 2 "gpc_reg_operand" "r")))
5770 (clobber (match_scratch:DI 3 "=r"))]
5773 [(set_attr "type" "compare")])
5775 (define_insn "*eqvdi3_internal3"
5776 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5777 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5778 (match_operand:DI 2 "gpc_reg_operand" "r")))
5780 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5781 (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
5784 [(set_attr "type" "compare")])
5786 (define_insn "*andcdi3_internal1"
5787 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5788 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5789 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5793 (define_insn "*andcdi3_internal2"
5794 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5795 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5796 (match_operand:DI 2 "gpc_reg_operand" "r"))
5798 (clobber (match_scratch:DI 3 "=r"))]
5801 [(set_attr "type" "compare")])
5803 (define_insn "*andcdi3_internal3"
5804 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5805 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5806 (match_operand:DI 2 "gpc_reg_operand" "r"))
5808 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5809 (and:DI (not:DI (match_dup 1)) (match_dup 2)))]
5812 [(set_attr "type" "compare")])
5814 (define_insn "*iorcdi3_internal1"
5815 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5816 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5817 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5821 (define_insn "*iorcdi3_inernal2"
5822 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5823 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5824 (match_operand:DI 2 "gpc_reg_operand" "r"))
5826 (clobber (match_scratch:DI 3 "=r"))]
5829 [(set_attr "type" "compare")])
5831 (define_insn "*iorcdi3_internal3"
5832 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5833 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5834 (match_operand:DI 2 "gpc_reg_operand" "r"))
5836 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5837 (ior:DI (not:DI (match_dup 1)) (match_dup 2)))]
5840 [(set_attr "type" "compare")])
5842 (define_insn "*nanddi3_internal1"
5843 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5844 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5845 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
5849 (define_insn "*nanddi3_internal2"
5850 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5851 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5852 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5854 (clobber (match_scratch:DI 3 "=r"))]
5857 [(set_attr "type" "compare")])
5859 (define_insn "*nanddi3_internal3"
5860 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5861 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5862 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5864 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5865 (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
5868 [(set_attr "type" "compare")])
5870 (define_insn "*nordi3_internal1"
5871 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5872 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5873 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
5877 (define_insn "*nordi3_internal2"
5878 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5879 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5880 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5882 (clobber (match_scratch:DI 3 "=r"))]
5885 [(set_attr "type" "compare")])
5887 (define_insn "*nordi3_internal3"
5888 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5889 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5890 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5892 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5893 (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
5896 [(set_attr "type" "compare")])
5898 ;; Now define ways of moving data around.
5900 ;; Elf specific ways of loading addresses for non-PIC code.
5901 ;; The output of this could be r0, but we limit it to base
5902 ;; registers, since almost all uses of this will need it
5903 ;; in a base register shortly.
5904 (define_insn "elf_high"
5905 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
5906 (high:SI (match_operand 1 "" "")))]
5907 "TARGET_ELF && ! TARGET_64BIT"
5908 "{liu|lis} %0,%1@ha")
5910 (define_insn "elf_low"
5911 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5912 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
5913 (match_operand 2 "" "")))]
5914 "TARGET_ELF && ! TARGET_64BIT"
5915 "{cal|la} %0,%2@l(%1)")
5917 ;; Set up a register with a value from the GOT table
5919 (define_expand "movsi_got"
5920 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5921 (unspec [(match_operand:SI 1 "got_operand" "")
5923 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
5926 if (GET_CODE (operands[1]) == CONST)
5928 rtx offset = const0_rtx;
5929 HOST_WIDE_INT value;
5931 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
5932 value = INTVAL (offset);
5935 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
5936 emit_insn (gen_movsi_got (tmp, operands[1]));
5937 emit_insn (gen_addsi3 (operands[0], tmp, offset));
5942 operands[2] = rs6000_got_register (operands[1]);
5945 (define_insn "*movsi_got_internal"
5946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5947 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
5948 (match_operand:SI 2 "gpc_reg_operand" "b")] 8))]
5949 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
5950 "{l|lwz} %0,%a1@got(%2)"
5951 [(set_attr "type" "load")])
5953 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
5954 ;; didn't get allocated to a hard register.
5956 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5957 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
5958 (match_operand:SI 2 "memory_operand" "m")] 8))]
5959 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5961 && (reload_in_progress || reload_completed)"
5962 [(set (match_dup 0) (match_dup 2))
5963 (set (match_dup 0) (unspec [(match_dup 1)(match_dup 0)] 8))]
5966 ;; For SI, we special-case integers that can't be loaded in one insn. We
5967 ;; do the load 16-bits at a time. We could do this by loading from memory,
5968 ;; and this is even supposed to be faster, but it is simpler not to get
5969 ;; integers in the TOC.
5970 (define_expand "movsi"
5971 [(set (match_operand:SI 0 "general_operand" "")
5972 (match_operand:SI 1 "any_operand" ""))]
5976 if (GET_CODE (operands[0]) != REG)
5977 operands[1] = force_reg (SImode, operands[1]);
5979 /* Convert a move of a CONST_DOUBLE into a CONST_INT */
5980 if (GET_CODE (operands[1]) == CONST_DOUBLE)
5981 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5983 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
5984 if (GET_CODE (operands[1]) == CONSTANT_P_RTX)
5986 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
5990 /* Use default pattern for address of ELF small data */
5992 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5993 && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
5994 && small_data_operand (operands[1], SImode))
5996 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
6000 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6001 && flag_pic == 1 && got_operand (operands[1], SImode))
6003 emit_insn (gen_movsi_got (operands[0], operands[1]));
6007 if (TARGET_ELF && TARGET_NO_TOC && ! TARGET_64BIT
6009 && CONSTANT_P (operands[1])
6010 && GET_CODE (operands[1]) != HIGH
6011 && GET_CODE (operands[1]) != CONST_INT)
6013 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (SImode));
6015 /* If this is a function address on -mcall-aixdesc or -mcall-nt,
6016 convert it to the address of the descriptor. */
6017 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
6018 && GET_CODE (operands[1]) == SYMBOL_REF
6019 && XSTR (operands[1], 0)[0] == '.')
6021 const char *name = XSTR (operands[1], 0);
6023 while (*name == '.')
6025 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
6026 CONSTANT_POOL_ADDRESS_P (new_ref)
6027 = CONSTANT_POOL_ADDRESS_P (operands[1]);
6028 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
6029 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
6030 operands[1] = new_ref;
6033 emit_insn (gen_elf_high (target, operands[1]));
6034 emit_insn (gen_elf_low (operands[0], target, operands[1]));
6038 if (GET_CODE (operands[1]) == CONST
6039 && DEFAULT_ABI == ABI_NT
6040 && ! side_effects_p (operands[0]))
6042 rtx const_term = const0_rtx;
6043 rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term);
6044 if (sym && GET_CODE (const_term) == CONST_INT
6045 && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
6047 unsigned HOST_WIDE_INT value = INTVAL (const_term);
6048 int new_reg_p = (flag_expensive_optimizations && ! no_new_pseudos);
6049 rtx tmp1 = ((new_reg_p && value != 0)
6050 ? gen_reg_rtx (SImode) : operands[0]);
6052 emit_insn (gen_movsi (tmp1, sym));
6053 if (INTVAL (const_term) != 0)
6054 emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value)));
6058 rs6000_fatal_bad_address (operands[1]);
6061 if ((! TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
6062 && CONSTANT_P (operands[1])
6063 && GET_CODE (operands[1]) != CONST_INT
6064 && GET_CODE (operands[1]) != HIGH
6065 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
6067 /* Emit a USE operation so that the constant isn't deleted if
6068 expensive optimizations are turned on because nobody
6069 references it. This should only be done for operands that
6070 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
6071 This should not be done for operands that contain LABEL_REFs.
6072 For now, we just handle the obvious case. */
6073 if (GET_CODE (operands[1]) != LABEL_REF)
6074 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
6076 /* If we are to limit the number of things we put in the TOC and
6077 this is a symbol plus a constant we can add in one insn,
6078 just put the symbol in the TOC and add the constant. Don't do
6079 this if reload is in progress. */
6080 if (GET_CODE (operands[1]) == CONST
6081 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
6082 && GET_CODE (XEXP (operands[1], 0)) == PLUS
6083 && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
6084 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
6085 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
6086 && ! side_effects_p (operands[0]))
6088 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
6089 rtx other = XEXP (XEXP (operands[1], 0), 1);
6091 emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
6095 operands[1] = force_const_mem (SImode, operands[1]);
6096 if (! memory_address_p (SImode, XEXP (operands[1], 0))
6097 && ! reload_in_progress)
6098 operands[1] = change_address (operands[1], SImode,
6099 XEXP (operands[1], 0));
6104 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
6105 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
6106 "gpc_reg_operand (operands[0], SImode)
6107 || gpc_reg_operand (operands[1], SImode)"
6111 {l%U1%X1|lwz%U1%X1} %0,%1
6112 {st%U0%X0|stw%U0%X0} %1,%0
6121 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*")
6122 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
6124 ;; Split a load of a large constant into the appropriate two-insn
6128 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6129 (match_operand:SI 1 "const_int_operand" ""))]
6130 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
6131 && (INTVAL (operands[1]) & 0xffff) != 0"
6135 (ior:SI (match_dup 0)
6139 operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff));
6140 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
6144 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
6145 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
6147 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
6148 "! TARGET_POWERPC64"
6150 [(set_attr "type" "compare")])
6152 (define_expand "movhi"
6153 [(set (match_operand:HI 0 "general_operand" "")
6154 (match_operand:HI 1 "any_operand" ""))]
6158 if (GET_CODE (operands[0]) != REG)
6159 operands[1] = force_reg (HImode, operands[1]);
6161 if (CONSTANT_P (operands[1])
6162 && GET_CODE (operands[1]) != CONST_INT)
6164 operands[1] = force_const_mem (HImode, operands[1]);
6165 if (! memory_address_p (HImode, XEXP (operands[1], 0))
6166 && ! reload_in_progress)
6167 operands[1] = change_address (operands[1], HImode,
6168 XEXP (operands[1], 0));
6173 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
6174 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
6175 "gpc_reg_operand (operands[0], HImode)
6176 || gpc_reg_operand (operands[1], HImode)"
6186 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
6188 (define_expand "movqi"
6189 [(set (match_operand:QI 0 "general_operand" "")
6190 (match_operand:QI 1 "any_operand" ""))]
6194 if (GET_CODE (operands[0]) != REG)
6195 operands[1] = force_reg (QImode, operands[1]);
6197 if (CONSTANT_P (operands[1])
6198 && GET_CODE (operands[1]) != CONST_INT)
6200 operands[1] = force_const_mem (QImode, operands[1]);
6201 if (! memory_address_p (QImode, XEXP (operands[1], 0))
6202 && ! reload_in_progress)
6203 operands[1] = change_address (operands[1], QImode,
6204 XEXP (operands[1], 0));
6209 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
6210 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
6211 "gpc_reg_operand (operands[0], QImode)
6212 || gpc_reg_operand (operands[1], QImode)"
6222 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
6224 ;; Here is how to move condition codes around. When we store CC data in
6225 ;; an integer register or memory, we store just the high-order 4 bits.
6226 ;; This lets us not shift in the most common case of CR0.
6227 (define_expand "movcc"
6228 [(set (match_operand:CC 0 "nonimmediate_operand" "")
6229 (match_operand:CC 1 "nonimmediate_operand" ""))]
6234 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
6235 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
6236 "register_operand (operands[0], CCmode)
6237 || register_operand (operands[1], CCmode)"
6241 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
6243 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
6245 {l%U1%X1|lwz%U1%X1} %0,%1
6246 {st%U0%U1|stw%U0%U1} %1,%0"
6247 [(set_attr "type" "*,*,*,compare,*,*,load,store")
6248 (set_attr "length" "*,*,12,*,8,*,*,*")])
6250 ;; For floating-point, we normally deal with the floating-point registers
6251 ;; unless -msoft-float is used. The sole exception is that parameter passing
6252 ;; can produce floating-point values in fixed-point registers. Unless the
6253 ;; value is a simple constant or already in memory, we deal with this by
6254 ;; allocating memory and copying the value explicitly via that memory location.
6255 (define_expand "movsf"
6256 [(set (match_operand:SF 0 "nonimmediate_operand" "")
6257 (match_operand:SF 1 "any_operand" ""))]
6261 /* If we are called from reload, we might be getting a SUBREG of a hard
6262 reg. So expand it. */
6263 if (GET_CODE (operands[0]) == SUBREG
6264 && GET_CODE (SUBREG_REG (operands[0])) == REG
6265 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER
6266 && (! REG_FUNCTION_VALUE_P (SUBREG_REG (operands[0]))
6267 || ! rtx_equal_function_value_matters))
6268 operands[0] = alter_subreg (operands[0]);
6269 if (GET_CODE (operands[1]) == SUBREG
6270 && GET_CODE (SUBREG_REG (operands[1])) == REG
6271 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
6272 operands[1] = alter_subreg (operands[1]);
6274 if (GET_CODE (operands[0]) == MEM)
6276 /* If operands[1] is a register, it may have double-precision data
6277 in it, so truncate it to single precision. We need not do
6278 this for POWERPC. */
6279 if (! TARGET_POWERPC && TARGET_HARD_FLOAT
6280 && GET_CODE (operands[1]) == REG
6281 && (FP_REGNO_P (REGNO (operands[1]))
6282 || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
6284 rtx newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (SFmode));
6285 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
6286 operands[1] = newreg;
6289 operands[1] = force_reg (SFmode, operands[1]);
6292 if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT
6293 && ! easy_fp_constant (operands[1], SFmode))
6295 operands[1] = force_const_mem (SFmode, operands[1]);
6296 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
6297 && ! reload_in_progress)
6298 operands[1] = change_address (operands[1], SFmode,
6299 XEXP (operands[1], 0));
6304 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6305 (match_operand:SF 1 "const_double_operand" ""))]
6307 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
6308 || (GET_CODE (operands[0]) == SUBREG
6309 && GET_CODE (SUBREG_REG (operands[0])) == REG
6310 && REGNO (SUBREG_REG (operands[0])) <= 31))"
6311 [(set (match_dup 2) (match_dup 3))]
6317 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
6318 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
6320 if (! TARGET_POWERPC64)
6321 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
6323 operands[2] = gen_lowpart (SImode, operands[0]);
6325 operands[3] = GEN_INT(l);
6328 (define_insn "*movsf_hardfloat"
6329 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r")
6330 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))]
6331 "(gpc_reg_operand (operands[0], SFmode)
6332 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
6335 {l%U1%X1|lwz%U1%X1} %0,%1
6336 {st%U0%X0|stw%U0%X0} %1,%0
6342 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*")
6343 (set_attr "length" "4,4,4,4,4,4,4,8")])
6345 (define_insn "*movsf_softfloat"
6346 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
6347 (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))]
6348 "(gpc_reg_operand (operands[0], SFmode)
6349 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
6352 {l%U1%X1|lwz%U1%X1} %0,%1
6353 {st%U0%X0|stw%U0%X0} %1,%0
6359 [(set_attr "type" "*,load,store,*,*,*,*,*")
6360 (set_attr "length" "4,4,4,4,4,4,4,8")])
6363 (define_expand "movdf"
6364 [(set (match_operand:DF 0 "nonimmediate_operand" "")
6365 (match_operand:DF 1 "any_operand" ""))]
6369 if (GET_CODE (operands[0]) != REG)
6370 operands[1] = force_reg (DFmode, operands[1]);
6372 if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
6374 operands[1] = force_const_mem (DFmode, operands[1]);
6375 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
6376 && ! reload_in_progress)
6377 operands[1] = change_address (operands[1], DFmode,
6378 XEXP (operands[1], 0));
6383 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6384 (match_operand:DF 1 "const_int_operand" ""))]
6385 "! TARGET_POWERPC64 && reload_completed
6386 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
6387 || (GET_CODE (operands[0]) == SUBREG
6388 && GET_CODE (SUBREG_REG (operands[0])) == REG
6389 && REGNO (SUBREG_REG (operands[0])) <= 31))"
6390 [(set (match_dup 2) (match_dup 4))
6391 (set (match_dup 3) (match_dup 1))]
6394 int endian = (WORDS_BIG_ENDIAN == 0);
6395 HOST_WIDE_INT value = INTVAL (operands[1]);
6397 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
6398 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
6399 #if HOST_BITS_PER_WIDE_INT == 32
6400 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
6402 operands[4] = GEN_INT (value >> 32);
6403 operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
6408 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6409 (match_operand:DF 1 "const_double_operand" ""))]
6410 "! TARGET_POWERPC64 && reload_completed
6411 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
6412 || (GET_CODE (operands[0]) == SUBREG
6413 && GET_CODE (SUBREG_REG (operands[0])) == REG
6414 && REGNO (SUBREG_REG (operands[0])) <= 31))"
6415 [(set (match_dup 2) (match_dup 4))
6416 (set (match_dup 3) (match_dup 5))]
6419 int endian = (WORDS_BIG_ENDIAN == 0);
6423 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
6424 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
6426 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
6427 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
6428 operands[4] = GEN_INT (l[endian]);
6429 operands[5] = GEN_INT (l[1 - endian]);
6433 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6434 (match_operand:DF 1 "easy_fp_constant" ""))]
6435 "TARGET_POWERPC64 && reload_completed
6436 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
6437 || (GET_CODE (operands[0]) == SUBREG
6438 && GET_CODE (SUBREG_REG (operands[0])) == REG
6439 && REGNO (SUBREG_REG (operands[0])) <= 31))"
6440 [(set (match_dup 2) (match_dup 3))]
6443 int endian = (WORDS_BIG_ENDIAN == 0);
6447 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
6448 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
6450 operands[2] = gen_lowpart (DImode, operands[0]);
6451 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
6452 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
6455 ;; Don't have reload use general registers to load a constant. First,
6456 ;; it might not work if the output operand is the equivalent of
6457 ;; a non-offsettable memref, but also it is less efficient than loading
6458 ;; the constant into an FP register, since it will probably be used there.
6459 ;; The "??" is a kludge until we can figure out a more reasonable way
6460 ;; of handling these non-offsettable values.
6461 (define_insn "*movdf_hardfloat32"
6462 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
6463 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
6464 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
6465 && (gpc_reg_operand (operands[0], DFmode)
6466 || gpc_reg_operand (operands[1], DFmode))"
6469 switch (which_alternative)
6474 /* We normally copy the low-numbered register first. However, if
6475 the first register operand 0 is the same as the second register
6476 of operand 1, we must copy in the opposite order. */
6477 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
6478 return \"mr %L0,%L1\;mr %0,%1\";
6480 return \"mr %0,%1\;mr %L0,%L1\";
6482 if (offsettable_memref_p (operands[1])
6483 || (GET_CODE (operands[1]) == MEM
6484 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
6485 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
6486 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
6488 /* If the low-address word is used in the address, we must load
6489 it last. Otherwise, load it first. Note that we cannot have
6490 auto-increment in that case since the address register is
6491 known to be dead. */
6492 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6494 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
6496 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
6502 addreg = find_addr_reg (XEXP (operands[1], 0));
6503 if (refers_to_regno_p (REGNO (operands[0]),
6504 REGNO (operands[0]) + 1,
6507 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
6508 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
6509 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
6510 return \"{lx|lwzx} %0,%1\";
6514 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
6515 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
6516 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
6517 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
6522 if (offsettable_memref_p (operands[0])
6523 || (GET_CODE (operands[0]) == MEM
6524 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
6525 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
6526 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
6527 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
6532 addreg = find_addr_reg (XEXP (operands[0], 0));
6533 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
6534 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
6535 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
6536 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
6544 return \"fmr %0,%1\";
6546 return \"lfd%U1%X1 %0,%1\";
6548 return \"stfd%U0%X0 %1,%0\";
6551 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
6552 (set_attr "length" "8,16,16,8,12,16,*,*,*")])
6554 (define_insn "*movdf_softfloat32"
6555 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
6556 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
6557 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
6558 && (gpc_reg_operand (operands[0], DFmode)
6559 || gpc_reg_operand (operands[1], DFmode))"
6562 switch (which_alternative)
6567 /* We normally copy the low-numbered register first. However, if
6568 the first register operand 0 is the same as the second register of
6569 operand 1, we must copy in the opposite order. */
6570 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
6571 return \"mr %L0,%L1\;mr %0,%1\";
6573 return \"mr %0,%1\;mr %L0,%L1\";
6575 /* If the low-address word is used in the address, we must load
6576 it last. Otherwise, load it first. Note that we cannot have
6577 auto-increment in that case since the address register is
6578 known to be dead. */
6579 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6581 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
6583 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
6585 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
6592 [(set_attr "type" "*,load,store,*,*,*")
6593 (set_attr "length" "8,8,8,8,12,16")])
6595 (define_insn "*movdf_hardfloat64"
6596 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
6597 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
6598 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
6599 && (gpc_reg_operand (operands[0], DFmode)
6600 || gpc_reg_operand (operands[1], DFmode))"
6611 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
6612 (set_attr "length" "4,4,4,8,12,16,4,4,4")])
6614 (define_insn "*movdf_softfloat64"
6615 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
6616 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
6617 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
6618 && (gpc_reg_operand (operands[0], DFmode)
6619 || gpc_reg_operand (operands[1], DFmode))"
6627 [(set_attr "type" "*,load,store,*,*,*")
6628 (set_attr "length" "*,*,*,8,12,16")])
6630 ;; Next come the multi-word integer load and store and the load and store
6632 (define_expand "movdi"
6633 [(set (match_operand:DI 0 "general_operand" "")
6634 (match_operand:DI 1 "any_operand" ""))]
6638 if (GET_CODE (operands[0]) != REG)
6639 operands[1] = force_reg (DImode, operands[1]);
6641 /* Convert a move of a CONST_DOUBLE into a CONST_INT
6642 only if sign-extended lower-half for 32-bit host. */
6643 if (GET_CODE (operands[1]) == CONST_DOUBLE
6644 #if HOST_BITS_PER_WIDE_INT == 32
6645 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
6646 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
6647 || (CONST_DOUBLE_HIGH (operands[1]) == (HOST_WIDE_INT) 0xffffffff
6648 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))
6651 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6653 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
6654 if (GET_CODE (operands[1]) == CONSTANT_P_RTX)
6656 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
6661 && CONSTANT_P (operands[1])
6662 #if HOST_BITS_PER_WIDE_INT == 32
6663 && GET_CODE (operands[1]) != CONST_INT
6665 && ! easy_fp_constant (operands[1], DImode)
6666 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
6668 /* Emit a USE operation so that the constant isn't deleted if
6669 expensive optimizations are turned on because nobody
6670 references it. This should only be done for operands that
6671 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
6672 This should not be done for operands that contain LABEL_REFs.
6673 For now, we just handle the obvious case. */
6674 if (GET_CODE (operands[1]) != LABEL_REF)
6675 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
6677 /* If we are to limit the number of things we put in the TOC and
6678 this is a symbol plus a constant we can add in one insn,
6679 just put the symbol in the TOC and add the constant. Don't do
6680 this if reload is in progress. */
6681 if (GET_CODE (operands[1]) == CONST
6682 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
6683 && GET_CODE (XEXP (operands[1], 0)) == PLUS
6684 && add_operand (XEXP (XEXP (operands[1], 0), 1), DImode)
6685 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
6686 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
6687 && ! side_effects_p (operands[0]))
6689 rtx sym = force_const_mem (DImode, XEXP (XEXP (operands[1], 0), 0));
6690 rtx other = XEXP (XEXP (operands[1], 0), 1);
6692 emit_insn (gen_adddi3 (operands[0], force_reg (DImode, sym), other));
6696 operands[1] = force_const_mem (DImode, operands[1]);
6697 if (! memory_address_p (DImode, XEXP (operands[1], 0))
6698 && ! reload_in_progress)
6699 operands[1] = change_address (operands[1], DImode,
6700 XEXP (operands[1], 0));
6704 (define_insn "*movdi_32"
6705 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
6706 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
6708 && (gpc_reg_operand (operands[0], DImode)
6709 || gpc_reg_operand (operands[1], DImode))"
6712 switch (which_alternative)
6717 /* We normally copy the low-numbered register first. However, if
6718 the first register operand 0 is the same as the second register of
6719 operand 1, we must copy in the opposite order. */
6720 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
6721 return \"mr %L0,%L1\;mr %0,%1\";
6723 return \"mr %0,%1\;mr %L0,%L1\";
6725 /* If the low-address word is used in the address, we must load it
6726 last. Otherwise, load it first. Note that we cannot have
6727 auto-increment in that case since the address register is known to be
6729 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6731 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
6733 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
6735 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
6737 return \"fmr %0,%1\";
6739 return \"lfd%U1%X1 %0,%1\";
6741 return \"stfd%U0%X0 %1,%0\";
6750 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
6751 (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
6754 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6755 (match_operand:DI 1 "const_int_operand" ""))]
6756 "! TARGET_POWERPC64 && reload_completed"
6757 [(set (match_dup 2) (match_dup 4))
6758 (set (match_dup 3) (match_dup 1))]
6761 HOST_WIDE_INT value = INTVAL (operands[1]);
6762 operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
6763 operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
6764 #if HOST_BITS_PER_WIDE_INT == 32
6765 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
6767 operands[4] = GEN_INT (value >> 32);
6768 operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
6773 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6774 (match_operand:DI 1 "const_double_operand" ""))]
6775 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
6776 [(set (match_dup 2) (match_dup 4))
6777 (set (match_dup 3) (match_dup 5))]
6780 operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
6781 operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
6782 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6783 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6786 (define_insn "*movdi_64"
6787 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
6788 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
6790 && (gpc_reg_operand (operands[0], DImode)
6791 || gpc_reg_operand (operands[1], DImode))"
6806 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
6807 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
6809 ;; immediate value valid for a single instruction hiding in a const_double
6811 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6812 (match_operand:DI 1 "const_double_operand" "F"))]
6813 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
6814 && GET_CODE (operands[1]) == CONST_DOUBLE
6815 && num_insns_constant (operands[1], DImode) == 1"
6818 return ((unsigned HOST_WIDE_INT)
6819 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
6820 ? \"li %0,%1\" : \"lis %0,%v1\";
6823 ;; sign-extended 32-bit value
6825 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6826 (match_operand:DI 1 "const_int_operand" ""))]
6827 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
6828 && num_insns_constant (operands[1], DImode) > 1"
6832 (ior:DI (match_dup 0)
6836 operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
6837 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
6841 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6842 (match_operand:DI 1 "const_double_operand" ""))]
6843 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
6844 && GET_CODE (operands[1]) == CONST_DOUBLE
6845 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
6846 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
6847 || (CONST_DOUBLE_HIGH (operands[1]) == -1
6848 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))"
6852 (ior:DI (match_dup 0)
6856 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff0000);
6857 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff);
6861 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6862 (match_operand:DI 1 "const_int_operand" ""))]
6863 "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
6864 && GET_CODE (operands[1]) == CONST_INT
6865 && (((INTVAL (operands[1]) >> 32) == 0
6866 && (INTVAL (operands[1]) & 0x80000000) == 0)
6867 || ((INTVAL (operands[1]) >> 32) == -1
6868 && (INTVAL (operands[1]) & 0x80000000) != 0))
6869 && num_insns_constant (operands[1], DImode) > 1"
6873 (ior:DI (match_dup 0)
6877 operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
6878 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
6881 ;; zero-extended 32-bit value
6883 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6884 (match_operand:DI 1 "const_double_operand" ""))]
6885 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
6886 && GET_CODE (operands[1]) == CONST_DOUBLE
6887 && CONST_DOUBLE_HIGH (operands[1]) == 0
6888 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0"
6892 (zero_extend:DI (subreg:SI (match_dup 0) 0)))]
6894 { operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); }")
6897 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6898 (match_operand:DI 1 "const_int_operand" ""))]
6899 "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
6900 && GET_CODE (operands[1]) == CONST_INT
6901 && INTVAL (operands[1]) >> 32 == 0
6902 && (INTVAL (operands[1]) & 0x80000000) != 0
6903 && num_insns_constant (operands[1], DImode) > 1"
6907 (zero_extend:DI (subreg:SI (match_dup 0) 0)))]
6909 { operands[2] = GEN_INT ((INTVAL (operands[1]) << 32) >> 32); }")
6911 ;; 32-bit value in upper half of doubleword
6913 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6914 (match_operand:DI 1 "const_double_operand" ""))]
6915 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
6916 && GET_CODE (operands[1]) == CONST_DOUBLE
6917 && CONST_DOUBLE_LOW (operands[1]) == 0"
6921 (ashift:DI (match_dup 0)
6924 { operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }")
6927 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6928 (match_operand:DI 1 "const_int_operand" ""))]
6929 "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
6930 && GET_CODE (operands[1]) == CONST_INT
6931 && INTVAL (operands[1]) & 0xffffffff == 0"
6935 (ashift:DI (match_dup 0)
6938 { operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); }")
6940 ;; Generate all one-bits and clear left or right.
6941 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
6943 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6944 (match_operand:DI 1 "mask64_operand" ""))]
6945 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
6946 [(set (match_dup 0) (const_int -1))
6948 (and:DI (rotate:DI (match_dup 0)
6953 ;; Split a load of a large constant into the appropriate five-instruction
6954 ;; sequence. Handle anything in a constant number of insns.
6955 ;; When non-easy constants can go in the TOC, this should use
6956 ;; easy_fp_constant predicate.
6958 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6959 (match_operand:DI 1 "const_double_operand" ""))]
6960 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
6961 && num_insns_constant (operands[1], DImode) > 1"
6965 (ashift:DI (match_dup 0)
6968 (ior:DI (match_dup 0)
6972 if (GET_CODE (operands[1]) == CONST_DOUBLE)
6974 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6975 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6979 HOST_WIDE_INT value = INTVAL (operands[1]);
6980 operands[2] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
6981 operands[3] = operands[1];
6986 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6987 (match_operand:DI 1 "const_int_operand" ""))]
6988 "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
6989 && num_insns_constant (operands[1], DImode) > 1"
6993 (ashift:DI (match_dup 0)
6996 (ior:DI (match_dup 0)
7000 HOST_WIDE_INT value = INTVAL (operands[1]);
7001 operands[2] = GEN_INT (value >> 32);
7002 operands[3] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
7006 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
7007 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
7009 (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
7012 [(set_attr "type" "compare")])
7014 ;; TImode is similar, except that we usually want to compute the address into
7015 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
7016 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
7017 (define_expand "movti"
7018 [(parallel [(set (match_operand:TI 0 "general_operand" "")
7019 (match_operand:TI 1 "general_operand" ""))
7020 (clobber (scratch:SI))])]
7021 "TARGET_STRING || TARGET_POWERPC64"
7024 if (GET_CODE (operands[0]) == MEM)
7025 operands[1] = force_reg (TImode, operands[1]);
7027 if (GET_CODE (operands[0]) == MEM
7028 && GET_CODE (XEXP (operands[0], 0)) != REG
7029 && ! reload_in_progress)
7030 operands[0] = change_address (operands[0], TImode,
7031 copy_addr_to_reg (XEXP (operands[0], 0)));
7033 if (GET_CODE (operands[1]) == MEM
7034 && GET_CODE (XEXP (operands[1], 0)) != REG
7035 && ! reload_in_progress)
7036 operands[1] = change_address (operands[1], TImode,
7037 copy_addr_to_reg (XEXP (operands[1], 0)));
7040 ;; We say that MQ is clobbered in the last alternative because the first
7041 ;; alternative would never get used otherwise since it would need a reload
7042 ;; while the 2nd alternative would not. We put memory cases first so they
7043 ;; are preferred. Otherwise, we'd try to reload the output instead of
7044 ;; giving the SCRATCH mq.
7045 (define_insn "*movti_power"
7046 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
7047 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
7048 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
7049 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
7050 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
7053 switch (which_alternative)
7059 return \"{stsi|stswi} %1,%P0,16\";
7062 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
7065 /* Normally copy registers with lowest numbered register copied first.
7066 But copy in the other order if the first register of the output
7067 is the second, third, or fourth register in the input. */
7068 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
7069 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
7070 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
7072 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
7074 /* If the address is not used in the output, we can use lsi. Otherwise,
7075 fall through to generating four loads. */
7076 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
7077 return \"{lsi|lswi} %0,%P1,16\";
7078 /* ... fall through ... */
7080 /* If the address register is the same as the register for the lowest-
7081 addressed word, load it last. Similarly for the next two words.
7082 Otherwise load lowest address to highest. */
7083 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7085 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
7086 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
7087 REGNO (operands[0]) + 2, operands[1], 0))
7088 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
7089 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
7090 REGNO (operands[0]) + 3, operands[1], 0))
7091 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
7093 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
7096 [(set_attr "type" "store,store,*,load,load")
7097 (set_attr "length" "*,16,16,*,16")])
7099 (define_insn "*movti_string"
7100 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
7101 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
7102 (clobber (match_scratch:SI 2 "=X,X,X"))]
7103 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7104 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
7107 switch (which_alternative)
7113 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
7116 /* Normally copy registers with lowest numbered register copied first.
7117 But copy in the other order if the first register of the output
7118 is the second, third, or fourth register in the input. */
7119 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
7120 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
7121 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
7123 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
7125 /* If the address register is the same as the register for the lowest-
7126 addressed word, load it last. Similarly for the next two words.
7127 Otherwise load lowest address to highest. */
7128 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7130 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
7131 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
7132 REGNO (operands[0]) + 2, operands[1], 0))
7133 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
7134 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
7135 REGNO (operands[0]) + 3, operands[1], 0))
7136 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
7138 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
7141 [(set_attr "type" "store,*,load")
7142 (set_attr "length" "16,16,16")])
7144 (define_insn "*movti_ppc64"
7145 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
7146 (match_operand:TI 1 "input_operand" "r,m,r"))]
7147 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
7148 || gpc_reg_operand (operands[1], TImode))"
7151 switch (which_alternative)
7156 /* We normally copy the low-numbered register first. However, if
7157 the first register operand 0 is the same as the second register of
7158 operand 1, we must copy in the opposite order. */
7159 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7160 return \"mr %L0,%L1\;mr %0,%1\";
7162 return \"mr %0,%1\;mr %L0,%L1\";
7164 /* If the low-address word is used in the address, we must load it
7165 last. Otherwise, load it first. Note that we cannot have
7166 auto-increment in that case since the address register is known to be
7168 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7170 return \"ld %L0,%L1\;ld %0,%1\";
7172 return \"ld%U1 %0,%1\;ld %L0,%L1\";
7174 return \"std%U0 %1,%0\;std %L1,%L0\";
7177 [(set_attr "type" "*,load,store")
7178 (set_attr "length" "8,8,8")])
7180 (define_expand "load_multiple"
7181 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
7182 (match_operand:SI 1 "" ""))
7183 (use (match_operand:SI 2 "" ""))])]
7192 /* Support only loading a constant number of fixed-point registers from
7193 memory and only bother with this if more than two; the machine
7194 doesn't support more than eight. */
7195 if (GET_CODE (operands[2]) != CONST_INT
7196 || INTVAL (operands[2]) <= 2
7197 || INTVAL (operands[2]) > 8
7198 || GET_CODE (operands[1]) != MEM
7199 || GET_CODE (operands[0]) != REG
7200 || REGNO (operands[0]) >= 32)
7203 count = INTVAL (operands[2]);
7204 regno = REGNO (operands[0]);
7206 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7207 from = force_reg (SImode, XEXP (operands[1], 0));
7209 for (i = 0; i < count; i++)
7210 XVECEXP (operands[3], 0, i)
7211 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7212 change_address (operands[1], SImode,
7213 plus_constant (from, i * 4)));
7217 [(match_parallel 0 "load_multiple_operation"
7218 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7219 (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])]
7223 /* We have to handle the case where the pseudo used to contain the address
7224 is assigned to one of the output registers. */
7226 int words = XVECLEN (operands[0], 0);
7229 if (XVECLEN (operands[0], 0) == 1)
7230 return \"{l|lwz} %1,0(%2)\";
7232 for (i = 0; i < words; i++)
7233 if (refers_to_regno_p (REGNO (operands[1]) + i,
7234 REGNO (operands[1]) + i + 1, operands[2], 0))
7238 xop[0] = operands[1];
7239 xop[1] = operands[2];
7240 xop[2] = GEN_INT (4 * (words-1));
7241 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
7246 xop[0] = operands[1];
7247 xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7248 xop[2] = GEN_INT (4 * (words-1));
7249 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
7254 for (j = 0; j < words; j++)
7257 xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j);
7258 xop[1] = operands[2];
7259 xop[2] = GEN_INT (j * 4);
7260 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
7262 xop[0] = operands[2];
7263 xop[1] = GEN_INT (i * 4);
7264 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
7269 return \"{lsi|lswi} %1,%2,%N0\";
7271 [(set_attr "type" "load")
7272 (set_attr "length" "32")])
7275 (define_expand "store_multiple"
7276 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
7277 (match_operand:SI 1 "" ""))
7278 (clobber (scratch:SI))
7279 (use (match_operand:SI 2 "" ""))])]
7288 /* Support only storing a constant number of fixed-point registers to
7289 memory and only bother with this if more than two; the machine
7290 doesn't support more than eight. */
7291 if (GET_CODE (operands[2]) != CONST_INT
7292 || INTVAL (operands[2]) <= 2
7293 || INTVAL (operands[2]) > 8
7294 || GET_CODE (operands[0]) != MEM
7295 || GET_CODE (operands[1]) != REG
7296 || REGNO (operands[1]) >= 32)
7299 count = INTVAL (operands[2]);
7300 regno = REGNO (operands[1]);
7302 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
7303 to = force_reg (SImode, XEXP (operands[0], 0));
7305 XVECEXP (operands[3], 0, 0)
7306 = gen_rtx_SET (VOIDmode, change_address (operands[0], SImode, to),
7308 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
7309 gen_rtx_SCRATCH (SImode));
7311 for (i = 1; i < count; i++)
7312 XVECEXP (operands[3], 0, i + 1)
7313 = gen_rtx_SET (VOIDmode,
7314 change_address (operands[0], SImode,
7315 plus_constant (to, i * 4)),
7316 gen_rtx_REG (SImode, regno + i));
7320 [(match_parallel 0 "store_multiple_operation"
7321 [(set (match_operand:SI 1 "indirect_operand" "=Q")
7322 (match_operand:SI 2 "gpc_reg_operand" "r"))
7323 (clobber (match_scratch:SI 3 "=q"))])]
7324 "TARGET_STRING && TARGET_POWER"
7325 "{stsi|stswi} %2,%P1,%O0"
7326 [(set_attr "type" "store")])
7329 [(match_parallel 0 "store_multiple_operation"
7330 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
7331 (match_operand:SI 2 "gpc_reg_operand" "r"))
7332 (clobber (match_scratch:SI 3 "X"))])]
7333 "TARGET_STRING && ! TARGET_POWER"
7334 "{stsi|stswi} %2,%1,%O0"
7335 [(set_attr "type" "store")])
7338 ;; String/block move insn.
7339 ;; Argument 0 is the destination
7340 ;; Argument 1 is the source
7341 ;; Argument 2 is the length
7342 ;; Argument 3 is the alignment
7344 (define_expand "movstrsi"
7345 [(parallel [(set (match_operand:BLK 0 "" "")
7346 (match_operand:BLK 1 "" ""))
7347 (use (match_operand:SI 2 "" ""))
7348 (use (match_operand:SI 3 "" ""))])]
7352 if (expand_block_move (operands))
7358 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
7359 ;; register allocator doesn't have a clue about allocating 8 word registers.
7360 ;; rD/rS = r5 is preferred, efficient form.
7361 (define_expand "movstrsi_8reg"
7362 [(parallel [(set (match_operand 0 "" "")
7363 (match_operand 1 "" ""))
7364 (use (match_operand 2 "" ""))
7365 (use (match_operand 3 "" ""))
7366 (clobber (reg:SI 5))
7367 (clobber (reg:SI 6))
7368 (clobber (reg:SI 7))
7369 (clobber (reg:SI 8))
7370 (clobber (reg:SI 9))
7371 (clobber (reg:SI 10))
7372 (clobber (reg:SI 11))
7373 (clobber (reg:SI 12))
7374 (clobber (match_scratch:SI 4 ""))])]
7379 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
7380 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
7381 (use (match_operand:SI 2 "immediate_operand" "i"))
7382 (use (match_operand:SI 3 "immediate_operand" "i"))
7383 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7384 (clobber (reg:SI 6))
7385 (clobber (reg:SI 7))
7386 (clobber (reg:SI 8))
7387 (clobber (reg:SI 9))
7388 (clobber (reg:SI 10))
7389 (clobber (reg:SI 11))
7390 (clobber (reg:SI 12))
7391 (clobber (match_scratch:SI 5 "=q"))]
7392 "TARGET_STRING && TARGET_POWER
7393 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
7394 || INTVAL (operands[2]) == 0)
7395 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
7396 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
7397 && REGNO (operands[4]) == 5"
7398 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7399 [(set_attr "type" "load")
7400 (set_attr "length" "8")])
7403 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
7404 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
7405 (use (match_operand:SI 2 "immediate_operand" "i"))
7406 (use (match_operand:SI 3 "immediate_operand" "i"))
7407 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7408 (clobber (reg:SI 6))
7409 (clobber (reg:SI 7))
7410 (clobber (reg:SI 8))
7411 (clobber (reg:SI 9))
7412 (clobber (reg:SI 10))
7413 (clobber (reg:SI 11))
7414 (clobber (reg:SI 12))
7415 (clobber (match_scratch:SI 5 "X"))]
7416 "TARGET_STRING && ! TARGET_POWER
7417 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
7418 || INTVAL (operands[2]) == 0)
7419 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
7420 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
7421 && REGNO (operands[4]) == 5"
7422 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7423 [(set_attr "type" "load")
7424 (set_attr "length" "8")])
7426 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
7427 ;; register allocator doesn't have a clue about allocating 6 word registers.
7428 ;; rD/rS = r5 is preferred, efficient form.
7429 (define_expand "movstrsi_6reg"
7430 [(parallel [(set (match_operand 0 "" "")
7431 (match_operand 1 "" ""))
7432 (use (match_operand 2 "" ""))
7433 (use (match_operand 3 "" ""))
7434 (clobber (reg:SI 5))
7435 (clobber (reg:SI 6))
7436 (clobber (reg:SI 7))
7437 (clobber (reg:SI 8))
7438 (clobber (reg:SI 9))
7439 (clobber (reg:SI 10))
7440 (clobber (match_scratch:SI 4 ""))])]
7445 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
7446 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
7447 (use (match_operand:SI 2 "immediate_operand" "i"))
7448 (use (match_operand:SI 3 "immediate_operand" "i"))
7449 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7450 (clobber (reg:SI 6))
7451 (clobber (reg:SI 7))
7452 (clobber (reg:SI 8))
7453 (clobber (reg:SI 9))
7454 (clobber (reg:SI 10))
7455 (clobber (match_scratch:SI 5 "=q"))]
7456 "TARGET_STRING && TARGET_POWER
7457 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
7458 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
7459 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
7460 && REGNO (operands[4]) == 5"
7461 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7462 [(set_attr "type" "load")
7463 (set_attr "length" "8")])
7466 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
7467 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
7468 (use (match_operand:SI 2 "immediate_operand" "i"))
7469 (use (match_operand:SI 3 "immediate_operand" "i"))
7470 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7471 (clobber (reg:SI 6))
7472 (clobber (reg:SI 7))
7473 (clobber (reg:SI 8))
7474 (clobber (reg:SI 9))
7475 (clobber (reg:SI 10))
7476 (clobber (match_scratch:SI 5 "X"))]
7477 "TARGET_STRING && ! TARGET_POWER
7478 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
7479 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
7480 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
7481 && REGNO (operands[4]) == 5"
7482 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7483 [(set_attr "type" "load")
7484 (set_attr "length" "8")])
7486 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
7487 ;; problems with TImode.
7488 ;; rD/rS = r5 is preferred, efficient form.
7489 (define_expand "movstrsi_4reg"
7490 [(parallel [(set (match_operand 0 "" "")
7491 (match_operand 1 "" ""))
7492 (use (match_operand 2 "" ""))
7493 (use (match_operand 3 "" ""))
7494 (clobber (reg:SI 5))
7495 (clobber (reg:SI 6))
7496 (clobber (reg:SI 7))
7497 (clobber (reg:SI 8))
7498 (clobber (match_scratch:SI 4 ""))])]
7503 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
7504 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
7505 (use (match_operand:SI 2 "immediate_operand" "i"))
7506 (use (match_operand:SI 3 "immediate_operand" "i"))
7507 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7508 (clobber (reg:SI 6))
7509 (clobber (reg:SI 7))
7510 (clobber (reg:SI 8))
7511 (clobber (match_scratch:SI 5 "=q"))]
7512 "TARGET_STRING && TARGET_POWER
7513 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
7514 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
7515 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
7516 && REGNO (operands[4]) == 5"
7517 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7518 [(set_attr "type" "load")
7519 (set_attr "length" "8")])
7522 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
7523 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
7524 (use (match_operand:SI 2 "immediate_operand" "i"))
7525 (use (match_operand:SI 3 "immediate_operand" "i"))
7526 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7527 (clobber (reg:SI 6))
7528 (clobber (reg:SI 7))
7529 (clobber (reg:SI 8))
7530 (clobber (match_scratch:SI 5 "X"))]
7531 "TARGET_STRING && ! TARGET_POWER
7532 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
7533 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
7534 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
7535 && REGNO (operands[4]) == 5"
7536 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7537 [(set_attr "type" "load")
7538 (set_attr "length" "8")])
7540 ;; Move up to 8 bytes at a time.
7541 (define_expand "movstrsi_2reg"
7542 [(parallel [(set (match_operand 0 "" "")
7543 (match_operand 1 "" ""))
7544 (use (match_operand 2 "" ""))
7545 (use (match_operand 3 "" ""))
7546 (clobber (match_scratch:DI 4 ""))
7547 (clobber (match_scratch:SI 5 ""))])]
7548 "TARGET_STRING && ! TARGET_POWERPC64"
7552 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
7553 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
7554 (use (match_operand:SI 2 "immediate_operand" "i"))
7555 (use (match_operand:SI 3 "immediate_operand" "i"))
7556 (clobber (match_scratch:DI 4 "=&r"))
7557 (clobber (match_scratch:SI 5 "=q"))]
7558 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
7559 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
7560 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7561 [(set_attr "type" "load")
7562 (set_attr "length" "8")])
7565 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
7566 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
7567 (use (match_operand:SI 2 "immediate_operand" "i"))
7568 (use (match_operand:SI 3 "immediate_operand" "i"))
7569 (clobber (match_scratch:DI 4 "=&r"))
7570 (clobber (match_scratch:SI 5 "X"))]
7571 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7572 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
7573 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7574 [(set_attr "type" "load")
7575 (set_attr "length" "8")])
7577 ;; Move up to 4 bytes at a time.
7578 (define_expand "movstrsi_1reg"
7579 [(parallel [(set (match_operand 0 "" "")
7580 (match_operand 1 "" ""))
7581 (use (match_operand 2 "" ""))
7582 (use (match_operand 3 "" ""))
7583 (clobber (match_scratch:SI 4 ""))
7584 (clobber (match_scratch:SI 5 ""))])]
7589 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
7590 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
7591 (use (match_operand:SI 2 "immediate_operand" "i"))
7592 (use (match_operand:SI 3 "immediate_operand" "i"))
7593 (clobber (match_scratch:SI 4 "=&r"))
7594 (clobber (match_scratch:SI 5 "=q"))]
7595 "TARGET_STRING && TARGET_POWER
7596 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
7597 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7598 [(set_attr "type" "load")
7599 (set_attr "length" "8")])
7602 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
7603 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
7604 (use (match_operand:SI 2 "immediate_operand" "i"))
7605 (use (match_operand:SI 3 "immediate_operand" "i"))
7606 (clobber (match_scratch:SI 4 "=&r"))
7607 (clobber (match_scratch:SI 5 "X"))]
7608 "TARGET_STRING && ! TARGET_POWER
7609 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
7610 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7611 [(set_attr "type" "load")
7612 (set_attr "length" "8")])
7615 ;; Define insns that do load or store with update. Some of these we can
7616 ;; get by using pre-decrement or pre-increment, but the hardware can also
7617 ;; do cases where the increment is not the size of the object.
7619 ;; In all these cases, we use operands 0 and 1 for the register being
7620 ;; incremented because those are the operands that local-alloc will
7621 ;; tie and these are the pair most likely to be tieable (and the ones
7622 ;; that will benefit the most).
7624 (define_insn "*movdi_update1"
7625 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
7626 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
7627 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
7628 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
7629 (plus:DI (match_dup 1) (match_dup 2)))]
7630 "TARGET_POWERPC64 && TARGET_UPDATE"
7634 [(set_attr "type" "load")])
7636 (define_insn "*movdi_update2"
7637 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
7639 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
7640 (match_operand:DI 2 "gpc_reg_operand" "r")))))
7641 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
7642 (plus:DI (match_dup 1) (match_dup 2)))]
7645 [(set_attr "type" "load")])
7647 (define_insn "movdi_update"
7648 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
7649 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
7650 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
7651 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
7652 (plus:DI (match_dup 1) (match_dup 2)))]
7653 "TARGET_POWERPC64 && TARGET_UPDATE"
7657 [(set_attr "type" "store")])
7659 (define_insn "*movsi_update1"
7660 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
7661 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7662 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7663 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7664 (plus:SI (match_dup 1) (match_dup 2)))]
7667 {lux|lwzux} %3,%0,%2
7668 {lu|lwzu} %3,%2(%0)"
7669 [(set_attr "type" "load")])
7671 (define_insn "movsi_update"
7672 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7673 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7674 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
7675 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7676 (plus:SI (match_dup 1) (match_dup 2)))]
7679 {stux|stwux} %3,%0,%2
7680 {stu|stwu} %3,%2(%0)"
7681 [(set_attr "type" "store")])
7683 (define_insn "*movhi_update"
7684 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
7685 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7686 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7687 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7688 (plus:SI (match_dup 1) (match_dup 2)))]
7693 [(set_attr "type" "load")])
7695 (define_insn "*movhi_update2"
7696 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
7698 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7699 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
7700 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7701 (plus:SI (match_dup 1) (match_dup 2)))]
7706 [(set_attr "type" "load")])
7708 (define_insn "*movhi_update3"
7709 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
7711 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7712 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
7713 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7714 (plus:SI (match_dup 1) (match_dup 2)))]
7719 [(set_attr "type" "load")])
7721 (define_insn "*movhi_update4"
7722 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7723 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7724 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
7725 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7726 (plus:SI (match_dup 1) (match_dup 2)))]
7731 [(set_attr "type" "store")])
7733 (define_insn "*movqi_update1"
7734 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
7735 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7736 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7737 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7738 (plus:SI (match_dup 1) (match_dup 2)))]
7743 [(set_attr "type" "load")])
7745 (define_insn "*movqi_update2"
7746 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
7748 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7749 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
7750 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7751 (plus:SI (match_dup 1) (match_dup 2)))]
7756 [(set_attr "type" "load")])
7758 (define_insn "*movqi_update3"
7759 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7760 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7761 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
7762 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7763 (plus:SI (match_dup 1) (match_dup 2)))]
7768 [(set_attr "type" "store")])
7770 (define_insn "*movsf_update1"
7771 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
7772 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7773 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7774 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7775 (plus:SI (match_dup 1) (match_dup 2)))]
7776 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7780 [(set_attr "type" "fpload")])
7782 (define_insn "*movsf_update2"
7783 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7784 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7785 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
7786 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7787 (plus:SI (match_dup 1) (match_dup 2)))]
7788 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7792 [(set_attr "type" "fpstore")])
7794 (define_insn "*movsf_update3"
7795 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
7796 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7797 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7798 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7799 (plus:SI (match_dup 1) (match_dup 2)))]
7800 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
7802 {lux|lwzux} %3,%0,%2
7803 {lu|lwzu} %3,%2(%0)"
7804 [(set_attr "type" "load")])
7806 (define_insn "*movsf_update4"
7807 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7808 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7809 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
7810 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7811 (plus:SI (match_dup 1) (match_dup 2)))]
7812 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
7814 {stux|stwux} %3,%0,%2
7815 {stu|stwu} %3,%2(%0)"
7816 [(set_attr "type" "store")])
7818 (define_insn "*movdf_update1"
7819 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
7820 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7821 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7822 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7823 (plus:SI (match_dup 1) (match_dup 2)))]
7824 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7828 [(set_attr "type" "fpload")])
7830 (define_insn "*movdf_update2"
7831 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7832 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7833 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
7834 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7835 (plus:SI (match_dup 1) (match_dup 2)))]
7836 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7840 [(set_attr "type" "fpstore")])
7842 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
7845 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7846 (match_operand:DF 1 "memory_operand" ""))
7847 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
7848 (match_operand:DF 3 "memory_operand" ""))]
7850 && TARGET_HARD_FLOAT
7851 && registers_ok_for_quad_peep (operands[0], operands[2])
7852 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
7853 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
7857 [(set (match_operand:DF 0 "memory_operand" "")
7858 (match_operand:DF 1 "gpc_reg_operand" "f"))
7859 (set (match_operand:DF 2 "memory_operand" "")
7860 (match_operand:DF 3 "gpc_reg_operand" "f"))]
7862 && TARGET_HARD_FLOAT
7863 && registers_ok_for_quad_peep (operands[1], operands[3])
7864 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
7865 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
7868 ;; Next come insns related to the calling sequence.
7870 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7871 ;; We move the back-chain and decrement the stack pointer.
7873 (define_expand "allocate_stack"
7874 [(set (match_operand 0 "gpc_reg_operand" "=r")
7875 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
7877 (minus (reg 1) (match_dup 1)))]
7880 { rtx chain = gen_reg_rtx (Pmode);
7881 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7884 emit_move_insn (chain, stack_bot);
7886 /* Check stack bounds if necessary. */
7887 if (current_function_limit_stack)
7890 available = expand_binop (Pmode, sub_optab,
7891 stack_pointer_rtx, stack_limit_rtx,
7892 NULL_RTX, 1, OPTAB_WIDEN);
7893 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
7896 /* Under Windows NT, we need to add stack probes for large/variable
7897 allocations, so do it via a call to the external function alloca
7898 instead of doing it inline. */
7899 if (DEFAULT_ABI == ABI_NT
7900 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 4096))
7902 rtx tmp = gen_reg_rtx (Pmode);
7903 emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode,
7904 \"__allocate_stack\"),
7905 tmp, 0, Pmode, 1, operands[1], Pmode);
7906 emit_insn (gen_set_sp (tmp));
7907 emit_move_insn (operands[0], tmp);
7911 if (GET_CODE (operands[1]) != CONST_INT
7912 || INTVAL (operands[1]) < -32767
7913 || INTVAL (operands[1]) > 32768)
7915 neg_op0 = gen_reg_rtx (Pmode);
7917 emit_insn (gen_negsi2 (neg_op0, operands[1]));
7919 emit_insn (gen_negdi2 (neg_op0, operands[1]));
7922 neg_op0 = GEN_INT (- INTVAL (operands[1]));
7925 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
7926 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
7930 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
7931 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
7932 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
7935 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7939 ;; Marker to indicate that the stack pointer was changed under NT in
7940 ;; ways not known to the compiler
7942 (define_insn "set_sp"
7944 (unspec [(match_operand:SI 0 "register_operand" "r")] 7))]
7947 [(set_attr "length" "0")])
7949 ;; These patterns say how to save and restore the stack pointer. We need not
7950 ;; save the stack pointer at function level since we are careful to
7951 ;; preserve the backchain. At block level, we have to restore the backchain
7952 ;; when we restore the stack pointer.
7954 ;; For nonlocal gotos, we must save both the stack pointer and its
7955 ;; backchain and restore both. Note that in the nonlocal case, the
7956 ;; save area is a memory location.
7958 (define_expand "save_stack_function"
7959 [(match_operand 0 "any_operand" "")
7960 (match_operand 1 "any_operand" "")]
7964 (define_expand "restore_stack_function"
7965 [(match_operand 0 "any_operand" "")
7966 (match_operand 1 "any_operand" "")]
7970 (define_expand "restore_stack_block"
7971 [(use (match_operand 0 "register_operand" ""))
7972 (set (match_dup 2) (match_dup 3))
7973 (set (match_dup 0) (match_operand 1 "register_operand" ""))
7974 (set (match_dup 3) (match_dup 2))]
7978 operands[2] = gen_reg_rtx (Pmode);
7979 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
7982 (define_expand "save_stack_nonlocal"
7983 [(match_operand 0 "memory_operand" "")
7984 (match_operand 1 "register_operand" "")]
7988 rtx temp = gen_reg_rtx (Pmode);
7990 /* Copy the backchain to the first word, sp to the second. */
7991 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
7992 emit_move_insn (operand_subword (operands[0], 0, 0,
7993 (TARGET_32BIT ? DImode : TImode)),
7995 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
8000 (define_expand "restore_stack_nonlocal"
8001 [(match_operand 0 "register_operand" "")
8002 (match_operand 1 "memory_operand" "")]
8006 rtx temp = gen_reg_rtx (Pmode);
8008 /* Restore the backchain from the first word, sp from the second. */
8009 emit_move_insn (temp,
8010 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
8011 emit_move_insn (operands[0],
8012 operand_subword (operands[1], 1, 0,
8013 (TARGET_32BIT ? DImode : TImode)));
8014 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
8018 ;; If we have -mminimal-toc, we need to reload r30 after a nonlocal goto.
8020 (define_insn "nonlocal_goto_receiver"
8021 [(unspec_volatile [(const_int 0)] 1)]
8022 "TARGET_TOC && TARGET_MINIMAL_TOC"
8025 rs6000_output_load_toc_table (asm_out_file, 30);
8028 [(set_attr "type" "load")])
8030 ;; A function pointer under AIX is a pointer to a data area whose first word
8031 ;; contains the actual address of the function, whose second word contains a
8032 ;; pointer to its TOC, and whose third word contains a value to place in the
8033 ;; static chain register (r11). Note that if we load the static chain, our
8034 ;; "trampoline" need not have any executable code.
8036 ;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address)
8037 ;; operands[1] is the stack size to clean up
8038 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX)
8039 ;; operands[3] is location to store the TOC
8040 ;; operands[4] is the TOC register
8041 ;; operands[5] is the static chain register
8043 ;; We do not break this into separate insns, so that the scheduler will not try
8044 ;; to move the load of the new TOC before any loads from the TOC.
8046 (define_insn "call_indirect_aix32"
8047 [(call (mem:SI (match_operand:SI 0 "gpc_reg_operand" "b"))
8048 (match_operand 1 "const_int_operand" "n"))
8049 (use (match_operand 2 "const_int_operand" "n"))
8050 (use (match_operand 3 "offsettable_mem_operand" "o"))
8051 (use (match_operand 4 "gpc_reg_operand" "r"))
8052 (clobber (match_operand 5 "gpc_reg_operand" "=r"))
8053 (clobber (match_scratch:SI 6 "=&r"))
8054 (clobber (match_scratch:SI 7 "=l"))]
8055 "DEFAULT_ABI == ABI_AIX
8056 && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
8057 "{st|stw} %4,%3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%3"
8058 [(set_attr "type" "load")
8059 (set_attr "length" "28")])
8061 (define_insn "call_indirect_aix64"
8062 [(call (mem:SI (match_operand:DI 0 "gpc_reg_operand" "b"))
8063 (match_operand 1 "const_int_operand" "n"))
8064 (use (match_operand 2 "const_int_operand" "n"))
8065 (use (match_operand 3 "offsettable_mem_operand" "o"))
8066 (use (match_operand 4 "gpc_reg_operand" "r"))
8067 (clobber (match_operand 5 "gpc_reg_operand" "=r"))
8068 (clobber (match_scratch:SI 6 "=&r"))
8069 (clobber (match_scratch:SI 7 "=l"))]
8070 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX
8071 && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
8072 "std %4,%3\;ld %6,0(%0)\;ld %4,8(%0)\;mt%7 %6\;ld %5,16(%0)\;blrl\;ld %4,%3"
8073 [(set_attr "type" "load")
8074 (set_attr "length" "28")])
8076 (define_insn "call_value_indirect_aix32"
8077 [(set (match_operand 0 "" "")
8078 (call (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8079 (match_operand 2 "const_int_operand" "n")))
8080 (use (match_operand 3 "const_int_operand" "n"))
8081 (use (match_operand 4 "offsettable_mem_operand" "o"))
8082 (use (match_operand 5 "gpc_reg_operand" "r"))
8083 (clobber (match_operand 6 "gpc_reg_operand" "=r"))
8084 (clobber (match_scratch:SI 7 "=&r"))
8085 (clobber (match_scratch:SI 8 "=l"))]
8086 "DEFAULT_ABI == ABI_AIX
8087 && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
8088 "{st|stw} %5,%4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1)\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%4"
8089 [(set_attr "type" "load")
8090 (set_attr "length" "28")])
8092 (define_insn "call_value_indirect_aix64"
8093 [(set (match_operand 0 "" "")
8094 (call (mem:SI (match_operand:DI 1 "gpc_reg_operand" "b"))
8095 (match_operand 2 "const_int_operand" "n")))
8096 (use (match_operand 3 "const_int_operand" "n"))
8097 (use (match_operand 4 "offsettable_mem_operand" "o"))
8098 (use (match_operand 5 "gpc_reg_operand" "r"))
8099 (clobber (match_operand 6 "gpc_reg_operand" "=r"))
8100 (clobber (match_scratch:SI 7 "=&r"))
8101 (clobber (match_scratch:SI 8 "=l"))]
8102 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX
8103 && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
8104 "std %5,%4\;ld %7,0(%1)\;ld %5,8(%1)\;mt%8 %7\;ld %6,16(%1)\;blrl\;ld %5,%4"
8105 [(set_attr "type" "load")
8106 (set_attr "length" "28")])
8108 ;; A function pointer undef NT is a pointer to a data area whose first word
8109 ;; contains the actual address of the function, whose second word contains a
8110 ;; pointer to its TOC. The static chain is not stored under NT, which means
8111 ;; that we need a trampoline.
8113 ;; operands[0] is an SImode pseudo in which we place the address of the function.
8114 ;; operands[1] is the stack size to clean up
8115 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for NT)
8116 ;; operands[3] is location to store the TOC
8117 ;; operands[4] is the TOC register
8119 ;; We do not break this into separate insns, so that the scheduler will not try
8120 ;; to move the load of the new TOC before any loads from the TOC.
8122 (define_insn "call_indirect_nt"
8123 [(call (mem:SI (match_operand:SI 0 "gpc_reg_operand" "b"))
8124 (match_operand 1 "const_int_operand" "n"))
8125 (use (match_operand 2 "const_int_operand" "n"))
8126 (use (match_operand 3 "offsettable_mem_operand" "o"))
8127 (use (match_operand 4 "gpc_reg_operand" "r"))
8128 (clobber (match_scratch:SI 5 "=&r"))
8129 (clobber (match_scratch:SI 6 "=l"))]
8130 "DEFAULT_ABI == ABI_NT
8131 && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
8132 "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3"
8133 [(set_attr "type" "load")
8134 (set_attr "length" "24")])
8136 (define_insn "call_value_indirect_nt"
8137 [(set (match_operand 0 "" "")
8138 (call (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8139 (match_operand 2 "const_int_operand" "n")))
8140 (use (match_operand 3 "const_int_operand" "n"))
8141 (use (match_operand 4 "offsettable_mem_operand" "o"))
8142 (use (match_operand 5 "gpc_reg_operand" "r"))
8143 (clobber (match_scratch:SI 6 "=&r"))
8144 (clobber (match_scratch:SI 7 "=l"))]
8145 "DEFAULT_ABI == ABI_NT
8146 && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
8147 "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4"
8148 [(set_attr "type" "load")
8149 (set_attr "length" "24")])
8151 ;; A function pointer under System V is just a normal pointer
8152 ;; operands[0] is the function pointer
8153 ;; operands[1] is the stack size to clean up
8154 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1
8156 (define_insn "call_indirect_sysv"
8157 [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l"))
8158 (match_operand 1 "const_int_operand" "n,n"))
8159 (use (match_operand 2 "const_int_operand" "O,n"))
8160 (clobber (match_scratch:SI 3 "=l,l"))]
8161 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
8164 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
8165 output_asm_insn (\"crxor 6,6,6\", operands);
8167 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
8168 output_asm_insn (\"creqv 6,6,6\", operands);
8170 return \"{brl|blrl}\";
8172 [(set_attr "type" "jmpreg")
8173 (set_attr "length" "4,8")])
8175 (define_insn "call_value_indirect_sysv"
8176 [(set (match_operand 0 "register_operand" "=fg,fg")
8177 (call (mem:SI (match_operand:SI 1 "register_operand" "l,l"))
8178 (match_operand 2 "const_int_operand" "n,n")))
8179 (use (match_operand 3 "const_int_operand" "O,n"))
8180 (clobber (match_scratch:SI 4 "=l,l"))]
8181 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
8184 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
8185 output_asm_insn (\"crxor 6,6,6\", operands);
8187 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
8188 output_asm_insn (\"creqv 6,6,6\", operands);
8190 return \"{brl|blrl}\";
8192 [(set_attr "type" "jmpreg")
8193 (set_attr "length" "4,8")])
8195 ;; Now the definitions for the call and call_value insns
8196 (define_expand "call"
8197 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
8198 (match_operand 1 "" ""))
8199 (use (match_operand 2 "" ""))
8200 (clobber (scratch:SI))])]
8204 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
8207 operands[0] = XEXP (operands[0], 0);
8209 /* Convert NT DLL imports into an indirect call. */
8210 if (GET_CODE (operands[0]) == SYMBOL_REF
8211 && (INTVAL (operands[2]) & CALL_NT_DLLIMPORT) != 0)
8213 operands[0] = rs6000_dll_import_ref (operands[0]);
8214 operands[2] = GEN_INT ((int)CALL_NORMAL);
8217 if (GET_CODE (operands[0]) != SYMBOL_REF
8218 || (INTVAL (operands[2]) & CALL_LONG) != 0)
8220 if (INTVAL (operands[2]) & CALL_LONG)
8221 operands[0] = rs6000_longcall_ref (operands[0]);
8223 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
8224 emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]),
8225 operands[1], operands[2]));
8228 rtx toc_reg = gen_rtx_REG (Pmode, 2);
8229 rtx toc_addr = RS6000_SAVE_TOC;
8231 if (DEFAULT_ABI == ABI_AIX)
8233 /* AIX function pointers are really pointers to a three word
8235 rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
8236 emit_call_insn (TARGET_32BIT
8237 ? gen_call_indirect_aix32 (force_reg (Pmode, operands[0]),
8238 operands[1], operands[2],
8239 toc_addr, toc_reg, static_chain)
8240 : gen_call_indirect_aix64 (force_reg (Pmode, operands[0]),
8241 operands[1], operands[2],
8242 toc_addr, toc_reg, static_chain));
8244 else if (DEFAULT_ABI == ABI_NT)
8246 /* NT function pointers are really pointers to a two word area */
8247 emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[0]),
8248 operands[1], operands[2],
8249 toc_addr, toc_reg));
8258 (define_expand "call_value"
8259 [(parallel [(set (match_operand 0 "" "")
8260 (call (mem:SI (match_operand 1 "address_operand" ""))
8261 (match_operand 2 "" "")))
8262 (use (match_operand 3 "" ""))
8263 (clobber (scratch:SI))])]
8267 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
8270 operands[1] = XEXP (operands[1], 0);
8272 /* Convert NT DLL imports into an indirect call. */
8273 if (GET_CODE (operands[1]) == SYMBOL_REF
8274 && (INTVAL (operands[3]) & CALL_NT_DLLIMPORT) != 0)
8276 operands[1] = rs6000_dll_import_ref (operands[1]);
8277 operands[3] = GEN_INT ((int)CALL_NORMAL);
8280 if (GET_CODE (operands[1]) != SYMBOL_REF
8281 || (INTVAL (operands[3]) & CALL_LONG) != 0)
8283 if (INTVAL (operands[3]) & CALL_LONG)
8284 operands[1] = rs6000_longcall_ref (operands[1]);
8286 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
8287 emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1],
8288 operands[2], operands[3]));
8291 rtx toc_reg = gen_rtx_REG (Pmode, 2);
8292 rtx toc_addr = RS6000_SAVE_TOC;
8294 if (DEFAULT_ABI == ABI_AIX)
8296 /* AIX function pointers are really pointers to a three word
8298 rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
8299 emit_call_insn (TARGET_32BIT
8300 ? gen_call_value_indirect_aix32 (operands[0],
8301 force_reg (Pmode, operands[1]),
8302 operands[2], operands[3],
8303 toc_addr, toc_reg, static_chain)
8304 : gen_call_value_indirect_aix64 (operands[0],
8305 force_reg (Pmode, operands[1]),
8306 operands[2], operands[3],
8307 toc_addr, toc_reg, static_chain));
8309 else if (DEFAULT_ABI == ABI_NT)
8311 /* NT function pointers are really pointers to a two word area */
8312 emit_call_insn (gen_call_value_indirect_nt (operands[0],
8313 force_reg (Pmode, operands[1]),
8314 operands[2], operands[3],
8315 toc_addr, toc_reg));
8324 ;; Call to function in current module. No TOC pointer reload needed.
8325 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
8326 ;; either the function was not prototyped, or it was prototyped as a
8327 ;; variable argument function. It is > 0 if FP registers were passed
8328 ;; and < 0 if they were not.
8330 (define_insn "*call_local32"
8331 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
8332 (match_operand 1 "" "g,g"))
8333 (use (match_operand:SI 2 "immediate_operand" "O,n"))
8334 (clobber (match_scratch:SI 3 "=l,l"))]
8335 "(INTVAL (operands[2]) & CALL_LONG) == 0"
8338 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
8339 output_asm_insn (\"crxor 6,6,6\", operands);
8341 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
8342 output_asm_insn (\"creqv 6,6,6\", operands);
8344 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
8346 [(set_attr "type" "branch")
8347 (set_attr "length" "4,8")])
8349 (define_insn "*call_local64"
8350 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
8351 (match_operand 1 "" "g,g"))
8352 (use (match_operand:SI 2 "immediate_operand" "O,n"))
8353 (clobber (match_scratch:SI 3 "=l,l"))]
8354 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
8357 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
8358 output_asm_insn (\"crxor 6,6,6\", operands);
8360 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
8361 output_asm_insn (\"creqv 6,6,6\", operands);
8363 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
8365 [(set_attr "type" "branch")
8366 (set_attr "length" "4,8")])
8368 (define_insn "*ret_call_local32"
8369 [(set (match_operand 0 "" "=fg,fg")
8370 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
8371 (match_operand 2 "" "g,g")))
8372 (use (match_operand:SI 3 "immediate_operand" "O,n"))
8373 (clobber (match_scratch:SI 4 "=l,l"))]
8374 "(INTVAL (operands[3]) & CALL_LONG) == 0"
8377 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
8378 output_asm_insn (\"crxor 6,6,6\", operands);
8380 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
8381 output_asm_insn (\"creqv 6,6,6\", operands);
8383 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
8385 [(set_attr "type" "branch")
8386 (set_attr "length" "4,8")])
8389 (define_insn "*ret_call_local64"
8390 [(set (match_operand 0 "" "=fg,fg")
8391 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
8392 (match_operand 2 "" "g,g")))
8393 (use (match_operand:SI 3 "immediate_operand" "O,n"))
8394 (clobber (match_scratch:SI 4 "=l,l"))]
8395 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
8398 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
8399 output_asm_insn (\"crxor 6,6,6\", operands);
8401 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
8402 output_asm_insn (\"creqv 6,6,6\", operands);
8404 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
8406 [(set_attr "type" "branch")
8407 (set_attr "length" "4,8")])
8409 ;; Call to function which may be in another module. Restore the TOC
8410 ;; pointer (r2) after the call unless this is System V.
8411 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
8412 ;; either the function was not prototyped, or it was prototyped as a
8413 ;; variable argument function. It is > 0 if FP registers were passed
8414 ;; and < 0 if they were not.
8416 (define_insn "*call_nonlocal_aix32"
8417 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
8418 (match_operand 1 "" "fg,fg"))
8419 (use (match_operand:SI 2 "immediate_operand" "O,n"))
8420 (clobber (match_scratch:SI 3 "=l,l"))]
8421 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
8422 && (INTVAL (operands[2]) & CALL_LONG) == 0"
8425 /* Indirect calls should go through call_indirect */
8426 if (GET_CODE (operands[0]) == REG)
8429 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
8430 output_asm_insn (\"crxor 6,6,6\", operands);
8432 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
8433 output_asm_insn (\"creqv 6,6,6\", operands);
8435 return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
8437 [(set_attr "type" "branch")
8438 (set_attr "length" "8,12")])
8440 (define_insn "*call_nonlocal_aix64"
8441 [(call (mem:SI (match_operand:DI 0 "call_operand" "s,s"))
8442 (match_operand 1 "" "fg,fg"))
8443 (use (match_operand:SI 2 "immediate_operand" "O,n"))
8444 (clobber (match_scratch:SI 3 "=l,l"))]
8445 "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
8446 && (INTVAL (operands[2]) & CALL_LONG) == 0"
8449 /* Indirect calls should go through call_indirect */
8450 if (GET_CODE (operands[0]) == REG)
8453 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
8454 output_asm_insn (\"crxor 6,6,6\", operands);
8456 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
8457 output_asm_insn (\"creqv 6,6,6\", operands);
8459 return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
8461 [(set_attr "type" "branch")
8462 (set_attr "length" "8,12")])
8464 (define_insn "*call_nonlocal_sysv"
8465 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
8466 (match_operand 1 "" "fg,fg"))
8467 (use (match_operand:SI 2 "immediate_operand" "O,n"))
8468 (clobber (match_scratch:SI 3 "=l,l"))]
8469 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
8470 && (INTVAL (operands[2]) & CALL_LONG) == 0"
8473 /* Indirect calls should go through call_indirect */
8474 if (GET_CODE (operands[0]) == REG)
8477 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
8478 output_asm_insn (\"crxor 6,6,6\", operands);
8480 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
8481 output_asm_insn (\"creqv 6,6,6\", operands);
8483 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\";
8485 [(set_attr "type" "branch")
8486 (set_attr "length" "4,8")])
8488 (define_insn "*ret_call_nonlocal_aix32"
8489 [(set (match_operand 0 "" "=fg,fg")
8490 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
8491 (match_operand 2 "" "fg,fg")))
8492 (use (match_operand:SI 3 "immediate_operand" "O,n"))
8493 (clobber (match_scratch:SI 4 "=l,l"))]
8494 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
8495 && (INTVAL (operands[3]) & CALL_LONG) == 0"
8498 /* This should be handled by call_value_indirect */
8499 if (GET_CODE (operands[1]) == REG)
8502 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
8503 output_asm_insn (\"crxor 6,6,6\", operands);
8505 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
8506 output_asm_insn (\"creqv 6,6,6\", operands);
8508 return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
8510 [(set_attr "type" "branch")
8511 (set_attr "length" "8,12")])
8513 (define_insn "*ret_call_nonlocal_aix64"
8514 [(set (match_operand 0 "" "=fg,fg")
8515 (call (mem:SI (match_operand:DI 1 "call_operand" "s,s"))
8516 (match_operand 2 "" "fg,fg")))
8517 (use (match_operand:SI 3 "immediate_operand" "O,n"))
8518 (clobber (match_scratch:SI 4 "=l,l"))]
8519 "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
8520 && (INTVAL (operands[3]) & CALL_LONG) == 0"
8523 /* This should be handled by call_value_indirect */
8524 if (GET_CODE (operands[1]) == REG)
8527 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
8528 output_asm_insn (\"crxor 6,6,6\", operands);
8530 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
8531 output_asm_insn (\"creqv 6,6,6\", operands);
8533 return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
8535 [(set_attr "type" "branch")
8536 (set_attr "length" "8,12")])
8538 (define_insn "*ret_call_nonlocal_sysv"
8539 [(set (match_operand 0 "" "=fg,fg")
8540 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
8541 (match_operand 2 "" "fg,fg")))
8542 (use (match_operand:SI 3 "immediate_operand" "O,n"))
8543 (clobber (match_scratch:SI 4 "=l,l"))]
8544 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
8545 && (INTVAL (operands[3]) & CALL_LONG) == 0"
8548 /* This should be handled by call_value_indirect */
8549 if (GET_CODE (operands[1]) == REG)
8552 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
8553 output_asm_insn (\"crxor 6,6,6\", operands);
8555 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
8556 output_asm_insn (\"creqv 6,6,6\", operands);
8558 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\";
8560 [(set_attr "type" "branch")
8561 (set_attr "length" "4,8")])
8563 ;; Call subroutine returning any type.
8564 (define_expand "untyped_call"
8565 [(parallel [(call (match_operand 0 "" "")
8567 (match_operand 1 "" "")
8568 (match_operand 2 "" "")])]
8574 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
8576 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8578 rtx set = XVECEXP (operands[2], 0, i);
8579 emit_move_insn (SET_DEST (set), SET_SRC (set));
8582 /* The optimizer does not know that the call sets the function value
8583 registers we stored in the result block. We avoid problems by
8584 claiming that all hard registers are used and clobbered at this
8586 emit_insn (gen_blockage ());
8591 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8592 ;; all of memory. This blocks insns from being moved across this point.
8594 (define_insn "blockage"
8595 [(unspec_volatile [(const_int 0)] 0)]
8599 ;; V.4 specific code to initialize the PIC register
8601 (define_insn "init_v4_pic"
8602 [(set (match_operand:SI 0 "register_operand" "=l")
8603 (unspec [(const_int 0)] 7))]
8604 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS"
8605 "bl _GLOBAL_OFFSET_TABLE_@local-4"
8606 [(set_attr "type" "branch")
8607 (set_attr "length" "4")])
8610 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
8611 ;; signed & unsigned, and one type of branch.
8613 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
8614 ;; insns, and branches. We store the operands of compares until we see
8616 (define_expand "cmpsi"
8618 (compare (match_operand:SI 0 "gpc_reg_operand" "")
8619 (match_operand:SI 1 "reg_or_short_operand" "")))]
8623 /* Take care of the possibility that operands[1] might be negative but
8624 this might be a logical operation. That insn doesn't exist. */
8625 if (GET_CODE (operands[1]) == CONST_INT
8626 && INTVAL (operands[1]) < 0)
8627 operands[1] = force_reg (SImode, operands[1]);
8629 rs6000_compare_op0 = operands[0];
8630 rs6000_compare_op1 = operands[1];
8631 rs6000_compare_fp_p = 0;
8635 (define_expand "cmpdi"
8637 (compare (match_operand:DI 0 "gpc_reg_operand" "")
8638 (match_operand:DI 1 "reg_or_short_operand" "")))]
8642 /* Take care of the possibility that operands[1] might be negative but
8643 this might be a logical operation. That insn doesn't exist. */
8644 if (GET_CODE (operands[1]) == CONST_INT
8645 && INTVAL (operands[1]) < 0)
8646 operands[1] = force_reg (DImode, operands[1]);
8648 rs6000_compare_op0 = operands[0];
8649 rs6000_compare_op1 = operands[1];
8650 rs6000_compare_fp_p = 0;
8654 (define_expand "cmpsf"
8655 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
8656 (match_operand:SF 1 "gpc_reg_operand" "")))]
8660 rs6000_compare_op0 = operands[0];
8661 rs6000_compare_op1 = operands[1];
8662 rs6000_compare_fp_p = 1;
8666 (define_expand "cmpdf"
8667 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
8668 (match_operand:DF 1 "gpc_reg_operand" "")))]
8672 rs6000_compare_op0 = operands[0];
8673 rs6000_compare_op1 = operands[1];
8674 rs6000_compare_fp_p = 1;
8678 (define_expand "beq"
8679 [(set (match_dup 2) (match_dup 1))
8681 (if_then_else (eq (match_dup 2)
8683 (label_ref (match_operand 0 "" ""))
8687 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8688 operands[1] = gen_rtx_COMPARE (mode,
8689 rs6000_compare_op0, rs6000_compare_op1);
8690 operands[2] = gen_reg_rtx (mode);
8693 (define_expand "bne"
8694 [(set (match_dup 2) (match_dup 1))
8696 (if_then_else (ne (match_dup 2)
8698 (label_ref (match_operand 0 "" ""))
8702 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8703 operands[1] = gen_rtx_COMPARE (mode,
8704 rs6000_compare_op0, rs6000_compare_op1);
8705 operands[2] = gen_reg_rtx (mode);
8708 (define_expand "blt"
8709 [(set (match_dup 2) (match_dup 1))
8711 (if_then_else (lt (match_dup 2)
8713 (label_ref (match_operand 0 "" ""))
8717 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8718 operands[1] = gen_rtx_COMPARE (mode,
8719 rs6000_compare_op0, rs6000_compare_op1);
8720 operands[2] = gen_reg_rtx (mode);
8723 (define_expand "bgt"
8724 [(set (match_dup 2) (match_dup 1))
8726 (if_then_else (gt (match_dup 2)
8728 (label_ref (match_operand 0 "" ""))
8732 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8733 operands[1] = gen_rtx_COMPARE (mode,
8734 rs6000_compare_op0, rs6000_compare_op1);
8735 operands[2] = gen_reg_rtx (mode);
8738 (define_expand "ble"
8739 [(set (match_dup 2) (match_dup 1))
8741 (if_then_else (le (match_dup 2)
8743 (label_ref (match_operand 0 "" ""))
8747 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8748 operands[1] = gen_rtx_COMPARE (mode,
8749 rs6000_compare_op0, rs6000_compare_op1);
8750 operands[2] = gen_reg_rtx (mode);
8753 (define_expand "bge"
8754 [(set (match_dup 2) (match_dup 1))
8756 (if_then_else (ge (match_dup 2)
8758 (label_ref (match_operand 0 "" ""))
8762 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8763 operands[1] = gen_rtx_COMPARE (mode,
8764 rs6000_compare_op0, rs6000_compare_op1);
8765 operands[2] = gen_reg_rtx (mode);
8768 (define_expand "bgtu"
8769 [(set (match_dup 2) (match_dup 1))
8771 (if_then_else (gtu (match_dup 2)
8773 (label_ref (match_operand 0 "" ""))
8777 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8778 rs6000_compare_op0, rs6000_compare_op1);
8779 operands[2] = gen_reg_rtx (CCUNSmode);
8782 (define_expand "bltu"
8783 [(set (match_dup 2) (match_dup 1))
8785 (if_then_else (ltu (match_dup 2)
8787 (label_ref (match_operand 0 "" ""))
8791 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8792 rs6000_compare_op0, rs6000_compare_op1);
8793 operands[2] = gen_reg_rtx (CCUNSmode);
8796 (define_expand "bgeu"
8797 [(set (match_dup 2) (match_dup 1))
8799 (if_then_else (geu (match_dup 2)
8801 (label_ref (match_operand 0 "" ""))
8805 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8806 rs6000_compare_op0, rs6000_compare_op1);
8807 operands[2] = gen_reg_rtx (CCUNSmode);
8810 (define_expand "bleu"
8811 [(set (match_dup 2) (match_dup 1))
8813 (if_then_else (leu (match_dup 2)
8815 (label_ref (match_operand 0 "" ""))
8819 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8820 rs6000_compare_op0, rs6000_compare_op1);
8821 operands[2] = gen_reg_rtx (CCUNSmode);
8824 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
8825 ;; For SEQ, likewise, except that comparisons with zero should be done
8826 ;; with an scc insns. However, due to the order that combine see the
8827 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
8828 ;; the cases we don't want to handle.
8829 (define_expand "seq"
8830 [(set (match_dup 2) (match_dup 1))
8831 (set (match_operand:SI 0 "gpc_reg_operand" "")
8832 (eq:SI (match_dup 2) (const_int 0)))]
8835 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8836 operands[1] = gen_rtx_COMPARE (mode,
8837 rs6000_compare_op0, rs6000_compare_op1);
8838 operands[2] = gen_reg_rtx (mode);
8841 (define_expand "sne"
8842 [(set (match_dup 2) (match_dup 1))
8843 (set (match_operand:SI 0 "gpc_reg_operand" "")
8844 (ne:SI (match_dup 2) (const_int 0)))]
8847 { if (! rs6000_compare_fp_p)
8850 operands[1] = gen_rtx_COMPARE (CCFPmode,
8851 rs6000_compare_op0, rs6000_compare_op1);
8852 operands[2] = gen_reg_rtx (CCFPmode);
8855 ;; A > 0 is best done using the portable sequence, so fail in that case.
8856 (define_expand "sgt"
8857 [(set (match_dup 2) (match_dup 1))
8858 (set (match_operand:SI 0 "gpc_reg_operand" "")
8859 (gt:SI (match_dup 2) (const_int 0)))]
8862 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8864 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
8867 operands[1] = gen_rtx_COMPARE (mode,
8868 rs6000_compare_op0, rs6000_compare_op1);
8869 operands[2] = gen_reg_rtx (mode);
8872 ;; A < 0 is best done in the portable way for A an integer.
8873 (define_expand "slt"
8874 [(set (match_dup 2) (match_dup 1))
8875 (set (match_operand:SI 0 "gpc_reg_operand" "")
8876 (lt:SI (match_dup 2) (const_int 0)))]
8879 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8881 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
8884 operands[1] = gen_rtx_COMPARE (mode,
8885 rs6000_compare_op0, rs6000_compare_op1);
8886 operands[2] = gen_reg_rtx (mode);
8889 (define_expand "sge"
8890 [(set (match_dup 2) (match_dup 1))
8891 (set (match_operand:SI 0 "gpc_reg_operand" "")
8892 (ge:SI (match_dup 2) (const_int 0)))]
8895 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8896 operands[1] = gen_rtx_COMPARE (mode,
8897 rs6000_compare_op0, rs6000_compare_op1);
8898 operands[2] = gen_reg_rtx (mode);
8901 ;; A <= 0 is best done the portable way for A an integer.
8902 (define_expand "sle"
8903 [(set (match_dup 2) (match_dup 1))
8904 (set (match_operand:SI 0 "gpc_reg_operand" "")
8905 (le:SI (match_dup 2) (const_int 0)))]
8908 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8910 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
8913 operands[1] = gen_rtx_COMPARE (mode,
8914 rs6000_compare_op0, rs6000_compare_op1);
8915 operands[2] = gen_reg_rtx (mode);
8918 (define_expand "sgtu"
8919 [(set (match_dup 2) (match_dup 1))
8920 (set (match_operand:SI 0 "gpc_reg_operand" "")
8921 (gtu:SI (match_dup 2) (const_int 0)))]
8924 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8925 rs6000_compare_op0, rs6000_compare_op1);
8926 operands[2] = gen_reg_rtx (CCUNSmode);
8929 (define_expand "sltu"
8930 [(set (match_dup 2) (match_dup 1))
8931 (set (match_operand:SI 0 "gpc_reg_operand" "")
8932 (ltu:SI (match_dup 2) (const_int 0)))]
8935 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8936 rs6000_compare_op0, rs6000_compare_op1);
8937 operands[2] = gen_reg_rtx (CCUNSmode);
8940 (define_expand "sgeu"
8941 [(set (match_dup 2) (match_dup 1))
8942 (set (match_operand:SI 0 "gpc_reg_operand" "")
8943 (geu:SI (match_dup 2) (const_int 0)))]
8946 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8947 rs6000_compare_op0, rs6000_compare_op1);
8948 operands[2] = gen_reg_rtx (CCUNSmode);
8951 (define_expand "sleu"
8952 [(set (match_dup 2) (match_dup 1))
8953 (set (match_operand:SI 0 "gpc_reg_operand" "")
8954 (leu:SI (match_dup 2) (const_int 0)))]
8957 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8958 rs6000_compare_op0, rs6000_compare_op1);
8959 operands[2] = gen_reg_rtx (CCUNSmode);
8962 ;; Here are the actual compare insns.
8964 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
8965 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
8966 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
8968 "{cmp%I2|cmpw%I2} %0,%1,%2"
8969 [(set_attr "type" "compare")])
8972 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
8973 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
8974 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
8977 [(set_attr "type" "compare")])
8979 ;; If we are comparing a register for equality with a large constant,
8980 ;; we can do this with an XOR followed by a compare. But we need a scratch
8981 ;; register for the result of the XOR.
8984 [(set (match_operand:CC 0 "cc_reg_operand" "")
8985 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
8986 (match_operand:SI 2 "non_short_cint_operand" "")))
8987 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
8988 "find_single_use (operands[0], insn, 0)
8989 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
8990 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
8991 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
8992 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
8995 /* Get the constant we are comparing against, C, and see what it looks like
8996 sign-extended to 16 bits. Then see what constant could be XOR'ed
8997 with C to get the sign-extended value. */
8999 HOST_WIDE_INT c = INTVAL (operands[2]);
9000 HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000);
9001 HOST_WIDE_INT xorv = c ^ sextc;
9003 operands[4] = GEN_INT (xorv);
9004 operands[5] = GEN_INT (sextc);
9008 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
9009 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9010 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
9012 "{cmpl%I2|cmplw%I2} %0,%1,%W2"
9013 [(set_attr "type" "compare")])
9016 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
9017 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9018 (match_operand:DI 2 "reg_or_u_short_operand" "rI")))]
9020 "cmpld%I2 %0,%1,%W2"
9021 [(set_attr "type" "compare")])
9023 ;; The following two insns don't exist as single insns, but if we provide
9024 ;; them, we can swap an add and compare, which will enable us to overlap more
9025 ;; of the required delay between a compare and branch. We generate code for
9026 ;; them by splitting.
9029 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
9030 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
9031 (match_operand:SI 2 "short_cint_operand" "i")))
9032 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9033 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
9036 [(set_attr "length" "8")])
9039 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
9040 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9041 (match_operand:SI 2 "u_short_cint_operand" "i")))
9042 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9043 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
9046 [(set_attr "length" "8")])
9049 [(set (match_operand:CC 3 "cc_reg_operand" "")
9050 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
9051 (match_operand:SI 2 "short_cint_operand" "")))
9052 (set (match_operand:SI 0 "gpc_reg_operand" "")
9053 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
9055 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
9056 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
9059 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
9060 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
9061 (match_operand:SI 2 "u_short_cint_operand" "")))
9062 (set (match_operand:SI 0 "gpc_reg_operand" "")
9063 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
9065 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
9066 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
9069 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
9070 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
9071 (match_operand:SF 2 "gpc_reg_operand" "f")))]
9074 [(set_attr "type" "fpcompare")])
9077 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
9078 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
9079 (match_operand:DF 2 "gpc_reg_operand" "f")))]
9082 [(set_attr "type" "fpcompare")])
9084 ;; Now we have the scc insns. We can do some combinations because of the
9085 ;; way the machine works.
9087 ;; Note that this is probably faster if we can put an insn between the
9088 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
9089 ;; cases the insns below which don't use an intermediate CR field will
9092 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9093 (match_operator:SI 1 "scc_comparison_operator"
9094 [(match_operand 2 "cc_reg_operand" "y")
9097 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
9098 [(set_attr "length" "12")])
9101 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9102 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9103 [(match_operand 2 "cc_reg_operand" "y")
9106 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
9107 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
9108 "! TARGET_POWERPC64"
9109 "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
9110 [(set_attr "type" "delayed_compare")
9111 (set_attr "length" "12")])
9114 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9115 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9116 [(match_operand 2 "cc_reg_operand" "y")
9118 (match_operand:SI 3 "const_int_operand" "n")))]
9122 int is_bit = ccr_bit (operands[1], 1);
9123 int put_bit = 31 - (INTVAL (operands[3]) & 31);
9126 if (is_bit >= put_bit)
9127 count = is_bit - put_bit;
9129 count = 32 - (put_bit - is_bit);
9131 operands[4] = GEN_INT (count);
9132 operands[5] = GEN_INT (put_bit);
9134 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
9136 [(set_attr "length" "12")])
9139 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9141 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9142 [(match_operand 2 "cc_reg_operand" "y")
9144 (match_operand:SI 3 "const_int_operand" "n"))
9146 (set (match_operand:SI 4 "gpc_reg_operand" "=r")
9147 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
9152 int is_bit = ccr_bit (operands[1], 1);
9153 int put_bit = 31 - (INTVAL (operands[3]) & 31);
9156 if (is_bit >= put_bit)
9157 count = is_bit - put_bit;
9159 count = 32 - (put_bit - is_bit);
9161 operands[5] = GEN_INT (count);
9162 operands[6] = GEN_INT (put_bit);
9164 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
9166 [(set_attr "type" "delayed_compare")
9167 (set_attr "length" "12")])
9169 ;; If we are comparing the result of two comparisons, this can be done
9170 ;; using creqv or crxor.
9173 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
9174 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
9175 [(match_operand 2 "cc_reg_operand" "y")
9177 (match_operator 3 "scc_comparison_operator"
9178 [(match_operand 4 "cc_reg_operand" "y")
9180 "REGNO (operands[2]) != REGNO (operands[4])"
9183 enum rtx_code code1, code2;
9185 code1 = GET_CODE (operands[1]);
9186 code2 = GET_CODE (operands[3]);
9188 if ((code1 == EQ || code1 == LT || code1 == GT
9189 || code1 == LTU || code1 == GTU
9190 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
9192 (code2 == EQ || code2 == LT || code2 == GT
9193 || code2 == LTU || code2 == GTU
9194 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
9195 return \"%C1%C3crxor %E0,%j1,%j3\";
9197 return \"%C1%C3creqv %E0,%j1,%j3\";
9199 [(set_attr "length" "12")])
9201 ;; There is a 3 cycle delay between consecutive mfcr instructions
9202 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
9205 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9206 (match_operator:SI 1 "scc_comparison_operator"
9207 [(match_operand 2 "cc_reg_operand" "y")
9209 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
9210 (match_operator:SI 4 "scc_comparison_operator"
9211 [(match_operand 5 "cc_reg_operand" "y")
9213 "REGNO (operands[2]) != REGNO (operands[5])"
9214 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
9215 [(set_attr "length" "20")])
9217 ;; There are some scc insns that can be done directly, without a compare.
9218 ;; These are faster because they don't involve the communications between
9219 ;; the FXU and branch units. In fact, we will be replacing all of the
9220 ;; integer scc insns here or in the portable methods in emit_store_flag.
9222 ;; Also support (neg (scc ..)) since that construct is used to replace
9223 ;; branches, (plus (scc ..) ..) since that construct is common and
9224 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
9225 ;; cases where it is no more expensive than (neg (scc ..)).
9227 ;; Have reload force a constant into a register for the simple insns that
9228 ;; otherwise won't accept constants. We do this because it is faster than
9229 ;; the cmp/mfcr sequence we would otherwise generate.
9232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
9233 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
9234 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
9235 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
9236 "! TARGET_POWERPC64"
9238 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
9239 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
9240 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
9241 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
9242 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
9243 [(set_attr "length" "12,8,12,12,12")])
9246 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
9247 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
9248 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
9249 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
9252 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
9253 subfic %3,%1,0\;adde %0,%3,%1
9254 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
9255 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
9256 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
9257 [(set_attr "length" "12,8,12,12,12")])
9260 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
9262 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
9263 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
9265 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
9266 (eq:SI (match_dup 1) (match_dup 2)))
9267 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
9268 "! TARGET_POWERPC64"
9270 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
9271 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
9272 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
9273 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
9274 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0"
9275 [(set_attr "type" "compare")
9276 (set_attr "length" "12,8,12,12,12")])
9279 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
9281 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
9282 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))
9284 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
9285 (eq:DI (match_dup 1) (match_dup 2)))
9286 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
9289 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
9290 subfic %3,%1,0\;adde. %0,%3,%1
9291 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
9292 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
9293 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0"
9294 [(set_attr "type" "compare")
9295 (set_attr "length" "12,8,12,12,12")])
9297 ;; We have insns of the form shown by the first define_insn below. If
9298 ;; there is something inside the comparison operation, we must split it.
9300 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9301 (plus:SI (match_operator 1 "comparison_operator"
9302 [(match_operand:SI 2 "" "")
9304 "reg_or_cint_operand" "")])
9305 (match_operand:SI 4 "gpc_reg_operand" "")))
9306 (clobber (match_operand:SI 5 "register_operand" ""))]
9307 "! gpc_reg_operand (operands[2], SImode)"
9308 [(set (match_dup 5) (match_dup 2))
9309 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
9313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
9314 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
9315 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
9316 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
9317 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
9318 "! TARGET_POWERPC64"
9320 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
9321 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
9322 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
9323 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
9324 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
9325 [(set_attr "length" "12,8,12,12,12")])
9328 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
9331 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
9332 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
9333 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
9335 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
9336 "! TARGET_POWERPC64"
9338 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9339 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
9340 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9341 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9342 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
9343 [(set_attr "type" "compare")
9344 (set_attr "length" "12,8,12,12,12")])
9347 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
9350 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
9351 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
9352 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
9354 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
9355 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9356 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
9357 "! TARGET_POWERPC64"
9359 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
9360 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
9361 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
9362 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
9363 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
9364 [(set_attr "type" "compare")
9365 (set_attr "length" "12,8,12,12,12")])
9368 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
9369 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
9370 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
9371 "! TARGET_POWERPC64"
9373 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
9374 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
9375 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
9376 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
9377 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
9378 [(set_attr "length" "12,8,12,12,12")])
9380 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
9381 ;; since it nabs/sr is just as fast.
9383 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
9384 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
9386 (clobber (match_scratch:SI 2 "=&r"))]
9388 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
9389 [(set_attr "length" "8")])
9392 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9393 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
9395 (clobber (match_scratch:DI 2 "=&r"))]
9397 "addic %2,%1,-1\;subfe %0,%2,%1"
9398 [(set_attr "length" "8")])
9400 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
9402 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9403 (plus:SI (lshiftrt:SI
9404 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
9406 (match_operand:SI 2 "gpc_reg_operand" "r")))
9407 (clobber (match_scratch:SI 3 "=&r"))]
9408 "! TARGET_POWERPC64"
9409 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
9410 [(set_attr "length" "8")])
9413 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9414 (plus:DI (lshiftrt:DI
9415 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
9417 (match_operand:DI 2 "gpc_reg_operand" "r")))
9418 (clobber (match_scratch:DI 3 "=&r"))]
9420 "addic %3,%1,-1\;addze %0,%2"
9421 [(set_attr "length" "8")])
9424 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9426 (plus:SI (lshiftrt:SI
9427 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
9429 (match_operand:SI 2 "gpc_reg_operand" "r"))
9431 (clobber (match_scratch:SI 3 "=&r"))]
9432 "! TARGET_POWERPC64"
9433 "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"
9434 [(set_attr "type" "compare")
9435 (set_attr "length" "8")])
9438 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9440 (plus:DI (lshiftrt:DI
9441 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
9443 (match_operand:DI 2 "gpc_reg_operand" "r"))
9445 (clobber (match_scratch:DI 3 "=&r"))]
9447 "addic %3,%1,-1\;addze. %3,%2"
9448 [(set_attr "type" "compare")
9449 (set_attr "length" "8")])
9452 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
9454 (plus:SI (lshiftrt:SI
9455 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
9457 (match_operand:SI 2 "gpc_reg_operand" "r"))
9459 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9460 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
9462 (clobber (match_scratch:SI 3 "=&r"))]
9463 "! TARGET_POWERPC64"
9464 "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"
9465 [(set_attr "type" "compare")
9466 (set_attr "length" "8")])
9469 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
9471 (plus:DI (lshiftrt:DI
9472 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
9474 (match_operand:DI 2 "gpc_reg_operand" "r"))
9476 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
9477 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
9479 (clobber (match_scratch:DI 3 "=&r"))]
9481 "addic %3,%1,-1\;addze. %0,%2"
9482 [(set_attr "type" "compare")
9483 (set_attr "length" "8")])
9486 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9487 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9488 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
9489 (clobber (match_scratch:SI 3 "=r,X"))]
9492 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
9493 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
9494 [(set_attr "length" "12")])
9497 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
9499 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9500 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
9502 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9503 (le:SI (match_dup 1) (match_dup 2)))
9504 (clobber (match_scratch:SI 3 "=r,X"))]
9507 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9508 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
9509 [(set_attr "type" "compare,delayed_compare")
9510 (set_attr "length" "12")])
9513 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9514 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9515 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
9516 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
9517 (clobber (match_scratch:SI 4 "=&r,&r"))]
9520 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
9521 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
9522 [(set_attr "length" "12")])
9525 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
9527 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9528 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
9529 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9531 (clobber (match_scratch:SI 4 "=&r,&r"))]
9534 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9535 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3"
9536 [(set_attr "type" "compare")
9537 (set_attr "length" "12")])
9540 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
9542 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9543 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
9544 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9546 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9547 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9548 (clobber (match_scratch:SI 4 "=&r,&r"))]
9551 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
9552 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3"
9553 [(set_attr "type" "compare")
9554 (set_attr "length" "12")])
9557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9558 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9559 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
9562 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
9563 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
9564 [(set_attr "length" "12")])
9567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9568 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9569 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
9570 "! TARGET_POWERPC64"
9571 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
9572 [(set_attr "length" "12")])
9575 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9576 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
9577 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
9579 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
9580 [(set_attr "length" "12")])
9583 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9585 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
9586 (match_operand:DI 2 "reg_or_short_operand" "rI"))
9588 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
9589 (leu:DI (match_dup 1) (match_dup 2)))]
9591 "subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0"
9592 [(set_attr "type" "compare")
9593 (set_attr "length" "12")])
9596 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9598 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9599 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9601 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9602 (leu:SI (match_dup 1) (match_dup 2)))]
9603 "! TARGET_POWERPC64"
9604 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
9605 [(set_attr "type" "compare")
9606 (set_attr "length" "12")])
9609 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9611 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
9612 (match_operand:DI 2 "reg_or_short_operand" "rI"))
9614 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
9615 (leu:DI (match_dup 1) (match_dup 2)))]
9617 "subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0"
9618 [(set_attr "type" "compare")
9619 (set_attr "length" "12")])
9622 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9623 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9624 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9625 (match_operand:SI 3 "gpc_reg_operand" "r")))
9626 (clobber (match_scratch:SI 4 "=&r"))]
9627 "! TARGET_POWERPC64"
9628 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
9629 [(set_attr "length" "8")])
9632 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9634 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9635 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9636 (match_operand:SI 3 "gpc_reg_operand" "r"))
9638 (clobber (match_scratch:SI 4 "=&r"))]
9639 "! TARGET_POWERPC64"
9640 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"
9641 [(set_attr "type" "compare")
9642 (set_attr "length" "8")])
9645 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
9647 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9648 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9649 (match_operand:SI 3 "gpc_reg_operand" "r"))
9651 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9652 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9653 (clobber (match_scratch:SI 4 "=&r"))]
9654 "! TARGET_POWERPC64"
9655 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"
9656 [(set_attr "type" "compare")
9657 (set_attr "length" "8")])
9660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9661 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9662 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
9663 "! TARGET_POWERPC64"
9664 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
9665 [(set_attr "length" "12")])
9668 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9670 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9671 (match_operand:SI 2 "reg_or_short_operand" "rI")))
9672 (match_operand:SI 3 "gpc_reg_operand" "r")))
9673 (clobber (match_scratch:SI 4 "=&r"))]
9674 "! TARGET_POWERPC64"
9675 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
9676 [(set_attr "length" "12")])
9679 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9682 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9683 (match_operand:SI 2 "reg_or_short_operand" "rI")))
9684 (match_operand:SI 3 "gpc_reg_operand" "r"))
9686 (clobber (match_scratch:SI 4 "=&r"))]
9687 "! TARGET_POWERPC64"
9688 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
9689 [(set_attr "type" "compare")
9690 (set_attr "length" "12")])
9693 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
9696 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9697 (match_operand:SI 2 "reg_or_short_operand" "rI")))
9698 (match_operand:SI 3 "gpc_reg_operand" "r"))
9700 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9701 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
9702 (clobber (match_scratch:SI 4 "=&r"))]
9703 "! TARGET_POWERPC64"
9704 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
9705 [(set_attr "type" "compare")
9706 (set_attr "length" "12")])
9709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9710 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9711 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
9713 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
9714 [(set_attr "length" "12")])
9717 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9719 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9720 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9722 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9723 (lt:SI (match_dup 1) (match_dup 2)))]
9725 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
9726 [(set_attr "type" "delayed_compare")
9727 (set_attr "length" "12")])
9730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9731 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9732 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9733 (match_operand:SI 3 "gpc_reg_operand" "r")))
9734 (clobber (match_scratch:SI 4 "=&r"))]
9736 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
9737 [(set_attr "length" "12")])
9740 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9742 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9743 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9744 (match_operand:SI 3 "gpc_reg_operand" "r"))
9746 (clobber (match_scratch:SI 4 "=&r"))]
9748 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
9749 [(set_attr "type" "compare")
9750 (set_attr "length" "12")])
9753 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
9755 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9756 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9757 (match_operand:SI 3 "gpc_reg_operand" "r"))
9759 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9760 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9761 (clobber (match_scratch:SI 4 "=&r"))]
9763 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
9764 [(set_attr "type" "compare")
9765 (set_attr "length" "12")])
9768 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9769 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9770 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
9772 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
9773 [(set_attr "length" "12")])
9776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9777 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9778 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
9779 "! TARGET_POWERPC64"
9781 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
9782 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
9783 [(set_attr "length" "12")])
9786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
9788 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9789 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9792 (ltu:SI (match_dup 1) (match_dup 2)))]
9793 "! TARGET_POWERPC64"
9795 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
9796 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
9797 [(set_attr "type" "compare")
9798 (set_attr "length" "12")])
9801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9802 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9803 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9804 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))
9805 (clobber (match_scratch:SI 4 "=&r,&r"))]
9806 "! TARGET_POWERPC64"
9808 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
9809 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
9810 [(set_attr "length" "12")])
9813 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
9815 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9816 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9817 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9819 (clobber (match_scratch:SI 4 "=&r,&r"))]
9820 "! TARGET_POWERPC64"
9822 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
9823 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
9824 [(set_attr "type" "compare")
9825 (set_attr "length" "12")])
9828 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
9830 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9831 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9832 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9835 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9836 (clobber (match_scratch:SI 4 "=&r,&r"))]
9837 "! TARGET_POWERPC64"
9839 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
9840 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
9841 [(set_attr "type" "compare")
9842 (set_attr "length" "12")])
9845 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9846 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9847 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
9848 "! TARGET_POWERPC64"
9850 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
9851 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
9852 [(set_attr "length" "8")])
9855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9856 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9857 (match_operand:SI 2 "reg_or_short_operand" "rI")))
9858 (clobber (match_scratch:SI 3 "=r"))]
9860 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
9861 [(set_attr "length" "12")])
9864 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
9866 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9867 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9869 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9870 (ge:SI (match_dup 1) (match_dup 2)))
9871 (clobber (match_scratch:SI 3 "=r"))]
9873 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3"
9874 [(set_attr "type" "compare")
9875 (set_attr "length" "12")])
9878 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9879 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9880 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9881 (match_operand:SI 3 "gpc_reg_operand" "r")))
9882 (clobber (match_scratch:SI 4 "=&r"))]
9884 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
9885 [(set_attr "length" "12")])
9888 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9890 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9891 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9892 (match_operand:SI 3 "gpc_reg_operand" "r"))
9894 (clobber (match_scratch:SI 4 "=&r"))]
9896 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
9897 [(set_attr "type" "compare")
9898 (set_attr "length" "12")])
9901 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
9903 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9904 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9905 (match_operand:SI 3 "gpc_reg_operand" "r"))
9907 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9908 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9909 (clobber (match_scratch:SI 4 "=&r"))]
9911 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
9912 [(set_attr "type" "compare")
9913 (set_attr "length" "12")])
9916 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9917 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9918 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
9920 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
9921 [(set_attr "length" "12")])
9923 ;; This is (and (neg (ge X (const_int 0))) Y).
9924 ;; srawi sign-extends, so these patterrns are 64-bit safe.
9926 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9929 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
9931 (match_operand:SI 2 "gpc_reg_operand" "r")))
9932 (clobber (match_scratch:SI 3 "=&r"))]
9934 "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
9935 [(set_attr "length" "8")])
9938 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9941 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9943 (match_operand:DI 2 "gpc_reg_operand" "r")))
9944 (clobber (match_scratch:DI 3 "=&r"))]
9946 "sradi %3,%1,63\;andc %0,%2,%3"
9947 [(set_attr "length" "8")])
9950 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9954 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
9956 (match_operand:SI 2 "gpc_reg_operand" "r"))
9958 (clobber (match_scratch:SI 3 "=&r"))]
9960 "{srai|srawi} %3,%1,31\;andc. %3,%2,%3"
9961 [(set_attr "type" "compare")
9962 (set_attr "length" "8")])
9965 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9969 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9971 (match_operand:DI 2 "gpc_reg_operand" "r"))
9973 (clobber (match_scratch:DI 3 "=&r"))]
9975 "sradi %3,%1,63\;andc. %3,%2,%3"
9976 [(set_attr "type" "compare")
9977 (set_attr "length" "8")])
9980 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
9984 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
9986 (match_operand:SI 2 "gpc_reg_operand" "r"))
9988 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9989 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
9992 (clobber (match_scratch:SI 3 "=&r"))]
9994 "{srai|srawi} %3,%1,31\;andc. %0,%2,%3"
9995 [(set_attr "type" "compare")
9996 (set_attr "length" "8")])
9999 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
10003 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
10005 (match_operand:DI 2 "gpc_reg_operand" "r"))
10007 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
10008 (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1))
10011 (clobber (match_scratch:SI 3 "=&r"))]
10013 "sradi %3,%1,63\;andc. %0,%2,%3"
10014 [(set_attr "type" "compare")
10015 (set_attr "length" "8")])
10018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10019 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10020 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
10021 "! TARGET_POWERPC64"
10023 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
10024 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
10025 [(set_attr "length" "12")])
10028 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10029 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10030 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
10033 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
10034 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
10035 [(set_attr "length" "12")])
10038 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
10040 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10041 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
10043 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10044 (geu:SI (match_dup 1) (match_dup 2)))]
10045 "! TARGET_POWERPC64"
10047 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
10048 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
10049 [(set_attr "type" "compare")
10050 (set_attr "length" "12")])
10053 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
10055 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10056 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
10058 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10059 (geu:DI (match_dup 1) (match_dup 2)))]
10062 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
10063 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0"
10064 [(set_attr "type" "compare")
10065 (set_attr "length" "12")])
10068 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10069 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10070 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
10071 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
10072 (clobber (match_scratch:SI 4 "=&r,&r"))]
10073 "! TARGET_POWERPC64"
10075 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
10076 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
10077 [(set_attr "length" "8")])
10080 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
10082 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10083 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
10084 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10086 (clobber (match_scratch:SI 4 "=&r,&r"))]
10087 "! TARGET_POWERPC64"
10089 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
10090 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
10091 [(set_attr "type" "compare")
10092 (set_attr "length" "8")])
10095 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
10097 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10098 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
10099 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10101 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10102 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10103 (clobber (match_scratch:SI 4 "=&r,&r"))]
10104 "! TARGET_POWERPC64"
10106 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
10107 {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3"
10108 [(set_attr "type" "compare")
10109 (set_attr "length" "8")])
10112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10113 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10114 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
10115 "! TARGET_POWERPC64"
10117 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
10118 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
10119 [(set_attr "length" "12")])
10122 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10124 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10125 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
10126 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
10127 (clobber (match_scratch:SI 4 "=&r,&r"))]
10128 "! TARGET_POWERPC64"
10130 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
10131 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
10132 [(set_attr "length" "12")])
10135 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
10138 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10139 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
10140 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10142 (clobber (match_scratch:SI 4 "=&r,&r"))]
10143 "! TARGET_POWERPC64"
10145 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
10146 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
10147 [(set_attr "type" "compare")
10148 (set_attr "length" "12")])
10151 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
10154 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10155 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
10156 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10158 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10159 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
10160 (clobber (match_scratch:SI 4 "=&r,&r"))]
10161 "! TARGET_POWERPC64"
10163 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
10164 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
10165 [(set_attr "type" "compare")
10166 (set_attr "length" "12")])
10169 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10170 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10172 "! TARGET_POWERPC64"
10173 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
10174 [(set_attr "length" "12")])
10177 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10178 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10181 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
10182 [(set_attr "length" "12")])
10185 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
10187 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10190 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10191 (gt:SI (match_dup 1) (const_int 0)))]
10192 "! TARGET_POWERPC64"
10193 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"
10194 [(set_attr "type" "delayed_compare")
10195 (set_attr "length" "12")])
10198 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
10200 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10203 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
10204 (gt:DI (match_dup 1) (const_int 0)))]
10206 "subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63"
10207 [(set_attr "type" "delayed_compare")
10208 (set_attr "length" "12")])
10211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10212 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10213 (match_operand:SI 2 "reg_or_short_operand" "r")))]
10215 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
10216 [(set_attr "length" "12")])
10219 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
10221 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10222 (match_operand:SI 2 "reg_or_short_operand" "r"))
10224 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10225 (gt:SI (match_dup 1) (match_dup 2)))]
10227 "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
10228 [(set_attr "type" "delayed_compare")
10229 (set_attr "length" "12")])
10232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10233 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10235 (match_operand:SI 2 "gpc_reg_operand" "r")))
10236 (clobber (match_scratch:SI 3 "=&r"))]
10237 "! TARGET_POWERPC64"
10238 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
10239 [(set_attr "length" "12")])
10242 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10243 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10245 (match_operand:DI 2 "gpc_reg_operand" "r")))
10246 (clobber (match_scratch:DI 3 "=&r"))]
10248 "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2"
10249 [(set_attr "length" "12")])
10252 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
10254 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10256 (match_operand:SI 2 "gpc_reg_operand" "r"))
10258 (clobber (match_scratch:SI 3 "=&r"))]
10259 "! TARGET_POWERPC64"
10260 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
10261 [(set_attr "type" "compare")
10262 (set_attr "length" "12")])
10265 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
10267 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10269 (match_operand:DI 2 "gpc_reg_operand" "r"))
10271 (clobber (match_scratch:DI 3 "=&r"))]
10273 "addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2"
10274 [(set_attr "type" "compare")
10275 (set_attr "length" "12")])
10278 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
10280 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10282 (match_operand:SI 2 "gpc_reg_operand" "r"))
10284 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10285 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
10286 (clobber (match_scratch:SI 3 "=&r"))]
10287 "! TARGET_POWERPC64"
10288 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
10289 [(set_attr "type" "compare")
10290 (set_attr "length" "12")])
10293 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
10295 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10297 (match_operand:DI 2 "gpc_reg_operand" "r"))
10299 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
10300 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
10301 (clobber (match_scratch:DI 3 "=&r"))]
10303 "addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2"
10304 [(set_attr "type" "compare")
10305 (set_attr "length" "12")])
10308 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10309 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10310 (match_operand:SI 2 "reg_or_short_operand" "r"))
10311 (match_operand:SI 3 "gpc_reg_operand" "r")))
10312 (clobber (match_scratch:SI 4 "=&r"))]
10314 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
10315 [(set_attr "length" "12")])
10318 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
10320 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10321 (match_operand:SI 2 "reg_or_short_operand" "r"))
10322 (match_operand:SI 3 "gpc_reg_operand" "r"))
10324 (clobber (match_scratch:SI 4 "=&r"))]
10326 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
10327 [(set_attr "type" "compare")
10328 (set_attr "length" "12")])
10331 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
10333 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10334 (match_operand:SI 2 "reg_or_short_operand" "r"))
10335 (match_operand:SI 3 "gpc_reg_operand" "r"))
10337 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10338 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10339 (clobber (match_scratch:SI 4 "=&r"))]
10341 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
10342 [(set_attr "type" "compare")
10343 (set_attr "length" "12")])
10346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10347 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10349 "! TARGET_POWERPC64"
10350 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
10351 [(set_attr "length" "12")])
10354 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10355 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10358 "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63"
10359 [(set_attr "length" "12")])
10362 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10363 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10364 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
10366 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
10367 [(set_attr "length" "12")])
10370 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10371 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10372 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10373 "! TARGET_POWERPC64"
10374 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
10375 [(set_attr "length" "12")])
10378 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10379 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10380 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
10382 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
10383 [(set_attr "length" "12")])
10386 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
10388 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10389 (match_operand:SI 2 "reg_or_short_operand" "rI"))
10391 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10392 (gtu:SI (match_dup 1) (match_dup 2)))]
10393 "! TARGET_POWERPC64"
10394 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
10395 [(set_attr "type" "compare")
10396 (set_attr "length" "12")])
10399 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
10401 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10402 (match_operand:DI 2 "reg_or_short_operand" "rI"))
10404 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
10405 (gtu:DI (match_dup 1) (match_dup 2)))]
10407 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0"
10408 [(set_attr "type" "compare")
10409 (set_attr "length" "12")])
10412 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10413 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10414 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
10415 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))
10416 (clobber (match_scratch:SI 4 "=&r,&r"))]
10417 "! TARGET_POWERPC64"
10419 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
10420 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
10421 [(set_attr "length" "8,12")])
10424 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10425 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10426 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
10427 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))
10428 (clobber (match_scratch:DI 4 "=&r,&r"))]
10431 addic %4,%1,%k2\;addze %0,%3
10432 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3"
10433 [(set_attr "length" "8,12")])
10436 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
10438 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10439 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
10440 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10442 (clobber (match_scratch:SI 4 "=&r,&r"))]
10443 "! TARGET_POWERPC64"
10445 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
10446 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
10447 [(set_attr "type" "compare")
10448 (set_attr "length" "8,12")])
10451 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
10453 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10454 (match_operand:DI 2 "reg_or_short_operand" "I,r"))
10455 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10457 (clobber (match_scratch:DI 4 "=&r,&r"))]
10460 addic %4,%1,%k2\;addze. %4,%3
10461 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3"
10462 [(set_attr "type" "compare")
10463 (set_attr "length" "8,12")])
10466 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
10468 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10469 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
10470 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10472 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10473 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10474 (clobber (match_scratch:SI 4 "=&r,&r"))]
10475 "! TARGET_POWERPC64"
10477 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
10478 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
10479 [(set_attr "type" "compare")
10480 (set_attr "length" "8,12")])
10483 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
10485 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10486 (match_operand:DI 2 "reg_or_short_operand" "I,r"))
10487 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10489 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10490 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
10491 (clobber (match_scratch:DI 4 "=&r,&r"))]
10494 addic %4,%1,%k2\;addze. %0,%3
10495 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3"
10496 [(set_attr "type" "compare")
10497 (set_attr "length" "8,12")])
10500 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10501 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10502 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
10503 "! TARGET_POWERPC64"
10504 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
10505 [(set_attr "length" "8")])
10508 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10509 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10510 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
10512 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
10513 [(set_attr "length" "8")])
10515 ;; Define both directions of branch and return. If we need a reload
10516 ;; register, we'd rather use CR0 since it is much easier to copy a
10517 ;; register CC value to there.
10521 (if_then_else (match_operator 1 "branch_comparison_operator"
10523 "cc_reg_operand" "x,?y")
10525 (label_ref (match_operand 0 "" ""))
10530 if (get_attr_length (insn) == 8)
10531 return \"%C1bc %t1,%j1,%l0\";
10533 return \"%C1bc %T1,%j1,%$+8\;b %l0\";
10536 [(set_attr "type" "branch")])
10540 (if_then_else (match_operator 0 "branch_comparison_operator"
10542 "cc_reg_operand" "x,?y")
10547 "{%C0bcr|%C0bclr} %t0,%j0"
10548 [(set_attr "type" "branch")
10549 (set_attr "length" "8")])
10553 (if_then_else (match_operator 1 "branch_comparison_operator"
10555 "cc_reg_operand" "x,?y")
10558 (label_ref (match_operand 0 "" ""))))]
10562 if (get_attr_length (insn) == 8)
10563 return \"%C1bc %T1,%j1,%l0\";
10565 return \"%C1bc %t1,%j1,%$+8\;b %l0\";
10567 [(set_attr "type" "branch")])
10571 (if_then_else (match_operator 0 "branch_comparison_operator"
10573 "cc_reg_operand" "x,?y")
10578 "{%C0bcr|%C0bclr} %T0,%j0"
10579 [(set_attr "type" "branch")
10580 (set_attr "length" "8")])
10582 ;; Unconditional branch and return.
10584 (define_insn "jump"
10586 (label_ref (match_operand 0 "" "")))]
10589 [(set_attr "type" "branch")])
10591 (define_insn "return"
10595 [(set_attr "type" "jmpreg")])
10597 (define_expand "indirect_jump"
10598 [(set (pc) (match_operand 0 "register_operand" ""))]
10603 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
10605 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
10609 (define_insn "indirect_jumpsi"
10610 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
10615 [(set_attr "type" "jmpreg")])
10617 (define_insn "indirect_jumpdi"
10618 [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))]
10623 [(set_attr "type" "jmpreg")])
10625 ;; Table jump for switch statements:
10626 (define_expand "tablejump"
10627 [(use (match_operand 0 "" ""))
10628 (use (label_ref (match_operand 1 "" "")))]
10633 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
10635 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
10639 (define_expand "tablejumpsi"
10640 [(set (match_dup 3)
10641 (plus:SI (match_operand:SI 0 "" "")
10643 (parallel [(set (pc) (match_dup 3))
10644 (use (label_ref (match_operand 1 "" "")))])]
10647 { operands[0] = force_reg (SImode, operands[0]);
10648 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
10649 operands[3] = gen_reg_rtx (SImode);
10652 (define_expand "tablejumpdi"
10653 [(set (match_dup 3)
10654 (plus:DI (match_operand:DI 0 "" "")
10656 (parallel [(set (pc) (match_dup 3))
10657 (use (label_ref (match_operand 1 "" "")))])]
10660 { operands[0] = force_reg (DImode, operands[0]);
10661 operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
10662 operands[3] = gen_reg_rtx (DImode);
10667 (match_operand:SI 0 "register_operand" "c,l"))
10668 (use (label_ref (match_operand 1 "" "")))]
10673 [(set_attr "type" "jmpreg")])
10677 (match_operand:DI 0 "register_operand" "c,l"))
10678 (use (label_ref (match_operand 1 "" "")))]
10683 [(set_attr "type" "jmpreg")])
10688 "{cror 0,0,0|nop}")
10690 ;; Define the subtract-one-and-jump insns, starting with the template
10691 ;; so loop.c knows what to generate.
10693 (define_expand "decrement_and_branch_on_count"
10694 [(use (match_operand 0 "register_operand" ""))
10695 (use (label_ref (match_operand 1 "" "")))]
10699 if (TARGET_POWERPC64)
10700 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
10702 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
10706 (define_expand "ctrsi"
10707 [(parallel [(set (pc)
10708 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
10710 (label_ref (match_operand 1 "" ""))
10713 (plus:SI (match_dup 0)
10715 (clobber (match_scratch:CC 2 ""))
10716 (clobber (match_scratch:SI 3 ""))])]
10717 "! TARGET_POWERPC64"
10720 (define_expand "ctrdi"
10721 [(parallel [(set (pc)
10722 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
10724 (label_ref (match_operand 1 "" ""))
10727 (plus:DI (match_dup 0)
10729 (clobber (match_scratch:CC 2 ""))
10730 (clobber (match_scratch:DI 3 ""))])]
10734 ;; We need to be able to do this for any operand, including MEM, or we
10735 ;; will cause reload to blow up since we don't allow output reloads on
10737 ;; For the length attribute to be calculated correctly, the
10738 ;; label MUST be operand 0.
10740 (define_insn "*ctrsi_internal1"
10742 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
10744 (label_ref (match_operand 0 "" ""))
10746 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
10747 (plus:SI (match_dup 1)
10749 (clobber (match_scratch:CC 3 "=X,&x,&x"))
10750 (clobber (match_scratch:SI 4 "=X,X,r"))]
10751 "! TARGET_POWERPC64"
10754 if (which_alternative != 0)
10756 else if (get_attr_length (insn) == 8)
10757 return \"{bdn|bdnz} %l0\";
10759 return \"bdz %$+8\;b %l0\";
10761 [(set_attr "type" "branch")
10762 (set_attr "length" "*,12,16")])
10764 (define_insn "*ctrsi_internal2"
10766 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
10769 (label_ref (match_operand 0 "" ""))))
10770 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
10771 (plus:SI (match_dup 1)
10773 (clobber (match_scratch:CC 3 "=X,&x,&x"))
10774 (clobber (match_scratch:SI 4 "=X,X,r"))]
10775 "! TARGET_POWERPC64"
10778 if (which_alternative != 0)
10780 else if (get_attr_length (insn) == 8)
10781 return \"bdz %l0\";
10783 return \"{bdn|bdnz} %$+8\;b %l0\";
10785 [(set_attr "type" "branch")
10786 (set_attr "length" "*,12,16")])
10788 (define_insn "*ctrdi_internal1"
10790 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
10792 (label_ref (match_operand 0 "" ""))
10794 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
10795 (plus:DI (match_dup 1)
10797 (clobber (match_scratch:CC 3 "=X,&x,&x"))
10798 (clobber (match_scratch:DI 4 "=X,X,r"))]
10802 if (which_alternative != 0)
10804 else if (get_attr_length (insn) == 8)
10805 return \"{bdn|bdnz} %l0\";
10807 return \"bdz %$+8\;b %l0\";
10809 [(set_attr "type" "branch")
10810 (set_attr "length" "*,12,16")])
10812 (define_insn "*ctrdi_internal2"
10814 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
10817 (label_ref (match_operand 0 "" ""))))
10818 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
10819 (plus:DI (match_dup 1)
10821 (clobber (match_scratch:CC 3 "=X,&x,&x"))
10822 (clobber (match_scratch:DI 4 "=X,X,r"))]
10826 if (which_alternative != 0)
10828 else if (get_attr_length (insn) == 8)
10829 return \"bdz %l0\";
10831 return \"{bdn|bdnz} %$+8\;b %l0\";
10833 [(set_attr "type" "branch")
10834 (set_attr "length" "*,12,16")])
10836 ;; Similar, but we can use GE since we have a REG_NONNEG.
10838 (define_insn "*ctrsi_internal3"
10840 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
10842 (label_ref (match_operand 0 "" ""))
10844 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
10845 (plus:SI (match_dup 1)
10847 (clobber (match_scratch:CC 3 "=X,&x,&X"))
10848 (clobber (match_scratch:SI 4 "=X,X,r"))]
10849 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
10852 if (which_alternative != 0)
10854 else if (get_attr_length (insn) == 8)
10855 return \"{bdn|bdnz} %l0\";
10857 return \"bdz %$+8\;b %l0\";
10859 [(set_attr "type" "branch")
10860 (set_attr "length" "*,12,16")])
10862 (define_insn "*ctrsi_internal4"
10864 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
10867 (label_ref (match_operand 0 "" ""))))
10868 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
10869 (plus:SI (match_dup 1)
10871 (clobber (match_scratch:CC 3 "=X,&x,&X"))
10872 (clobber (match_scratch:SI 4 "=X,X,r"))]
10873 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
10876 if (which_alternative != 0)
10878 else if (get_attr_length (insn) == 8)
10879 return \"bdz %l0\";
10881 return \"{bdn|bdnz} %$+8\;b %l0\";
10883 [(set_attr "type" "branch")
10884 (set_attr "length" "*,12,16")])
10886 (define_insn "*ctrdi_internal3"
10888 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
10890 (label_ref (match_operand 0 "" ""))
10892 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
10893 (plus:DI (match_dup 1)
10895 (clobber (match_scratch:CC 3 "=X,&x,&X"))
10896 (clobber (match_scratch:DI 4 "=X,X,r"))]
10897 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
10900 if (which_alternative != 0)
10902 else if (get_attr_length (insn) == 8)
10903 return \"{bdn|bdnz} %l0\";
10905 return \"bdz %$+8\;b %l0\";
10907 [(set_attr "type" "branch")
10908 (set_attr "length" "*,12,16")])
10910 (define_insn "*ctrdi_internal4"
10912 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
10915 (label_ref (match_operand 0 "" ""))))
10916 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
10917 (plus:DI (match_dup 1)
10919 (clobber (match_scratch:CC 3 "=X,&x,&X"))
10920 (clobber (match_scratch:DI 4 "=X,X,r"))]
10921 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
10924 if (which_alternative != 0)
10926 else if (get_attr_length (insn) == 8)
10927 return \"bdz %l0\";
10929 return \"{bdn|bdnz} %$+8\;b %l0\";
10931 [(set_attr "type" "branch")
10932 (set_attr "length" "*,12,16")])
10934 ;; Similar but use EQ
10936 (define_insn "*ctrsi_internal5"
10938 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
10940 (label_ref (match_operand 0 "" ""))
10942 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
10943 (plus:SI (match_dup 1)
10945 (clobber (match_scratch:CC 3 "=X,&x,&x"))
10946 (clobber (match_scratch:SI 4 "=X,X,r"))]
10947 "! TARGET_POWERPC64"
10950 if (which_alternative != 0)
10952 else if (get_attr_length (insn) == 8)
10953 return \"bdz %l0\";
10955 return \"{bdn|bdnz} %$+8\;b %l0\";
10957 [(set_attr "type" "branch")
10958 (set_attr "length" "*,12,16")])
10960 (define_insn "*ctrsi_internal6"
10962 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
10965 (label_ref (match_operand 0 "" ""))))
10966 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
10967 (plus:SI (match_dup 1)
10969 (clobber (match_scratch:CC 3 "=X,&x,&x"))
10970 (clobber (match_scratch:SI 4 "=X,X,r"))]
10971 "! TARGET_POWERPC64"
10974 if (which_alternative != 0)
10976 else if (get_attr_length (insn) == 8)
10977 return \"{bdn|bdnz} %l0\";
10979 return \"bdz %$+8\;b %l0\";
10981 [(set_attr "type" "branch")
10982 (set_attr "length" "*,12,16")])
10984 (define_insn "*ctrdi_internal5"
10986 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
10988 (label_ref (match_operand 0 "" ""))
10990 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
10991 (plus:DI (match_dup 1)
10993 (clobber (match_scratch:CC 3 "=X,&x,&x"))
10994 (clobber (match_scratch:DI 4 "=X,X,r"))]
10998 if (which_alternative != 0)
11000 else if (get_attr_length (insn) == 8)
11001 return \"bdz %l0\";
11003 return \"{bdn|bdnz} %$+8\;b %l0\";
11005 [(set_attr "type" "branch")
11006 (set_attr "length" "*,12,16")])
11008 (define_insn "*ctrdi_internal6"
11010 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
11013 (label_ref (match_operand 0 "" ""))))
11014 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
11015 (plus:DI (match_dup 1)
11017 (clobber (match_scratch:CC 3 "=X,&x,&x"))
11018 (clobber (match_scratch:DI 4 "=X,X,r"))]
11022 if (which_alternative != 0)
11024 else if (get_attr_length (insn) == 8)
11025 return \"{bdn|bdnz} %l0\";
11027 return \"bdz %$+8\;b %l0\";
11029 [(set_attr "type" "branch")
11030 (set_attr "length" "*,12,16")])
11032 ;; Now the splitters if we could not allocate the CTR register
11036 (if_then_else (match_operator 2 "comparison_operator"
11037 [(match_operand:SI 1 "gpc_reg_operand" "")
11039 (match_operand 5 "" "")
11040 (match_operand 6 "" "")))
11041 (set (match_operand:SI 0 "gpc_reg_operand" "")
11042 (plus:SI (match_dup 1)
11044 (clobber (match_scratch:CC 3 ""))
11045 (clobber (match_scratch:SI 4 ""))]
11046 "! TARGET_POWERPC64 && reload_completed"
11047 [(parallel [(set (match_dup 3)
11048 (compare:CC (plus:SI (match_dup 1)
11052 (plus:SI (match_dup 1)
11054 (set (pc) (if_then_else (match_dup 7)
11058 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
11063 (if_then_else (match_operator 2 "comparison_operator"
11064 [(match_operand:SI 1 "gpc_reg_operand" "")
11066 (match_operand 5 "" "")
11067 (match_operand 6 "" "")))
11068 (set (match_operand:SI 0 "general_operand" "")
11069 (plus:SI (match_dup 1) (const_int -1)))
11070 (clobber (match_scratch:CC 3 ""))
11071 (clobber (match_scratch:SI 4 ""))]
11072 "! TARGET_POWERPC64 && reload_completed
11073 && ! gpc_reg_operand (operands[0], SImode)"
11074 [(parallel [(set (match_dup 3)
11075 (compare:CC (plus:SI (match_dup 1)
11079 (plus:SI (match_dup 1)
11083 (set (pc) (if_then_else (match_dup 7)
11087 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
11091 (if_then_else (match_operator 2 "comparison_operator"
11092 [(match_operand:DI 1 "gpc_reg_operand" "")
11094 (match_operand 5 "" "")
11095 (match_operand 6 "" "")))
11096 (set (match_operand:DI 0 "gpc_reg_operand" "")
11097 (plus:DI (match_dup 1)
11099 (clobber (match_scratch:CC 3 ""))
11100 (clobber (match_scratch:DI 4 ""))]
11101 "TARGET_POWERPC64 && reload_completed"
11102 [(parallel [(set (match_dup 3)
11103 (compare:CC (plus:DI (match_dup 1)
11107 (plus:DI (match_dup 1)
11109 (set (pc) (if_then_else (match_dup 7)
11113 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
11118 (if_then_else (match_operator 2 "comparison_operator"
11119 [(match_operand:DI 1 "gpc_reg_operand" "")
11121 (match_operand 5 "" "")
11122 (match_operand 6 "" "")))
11123 (set (match_operand:DI 0 "general_operand" "")
11124 (plus:DI (match_dup 1) (const_int -1)))
11125 (clobber (match_scratch:CC 3 ""))
11126 (clobber (match_scratch:DI 4 ""))]
11127 "TARGET_POWERPC64 && reload_completed
11128 && ! gpc_reg_operand (operands[0], DImode)"
11129 [(parallel [(set (match_dup 3)
11130 (compare:CC (plus:DI (match_dup 1)
11134 (plus:DI (match_dup 1)
11138 (set (pc) (if_then_else (match_dup 7)
11142 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
11145 (define_insn "trap"
11146 [(trap_if (const_int 1) (const_int 0))]
11150 (define_expand "conditional_trap"
11151 [(trap_if (match_operator 0 "trap_comparison_operator"
11152 [(match_dup 2) (match_dup 3)])
11153 (match_operand 1 "const_int_operand" ""))]
11155 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
11156 operands[2] = rs6000_compare_op0;
11157 operands[3] = rs6000_compare_op1;")
11160 [(trap_if (match_operator 0 "trap_comparison_operator"
11161 [(match_operand:SI 1 "register_operand" "r")
11162 (match_operand:SI 2 "reg_or_short_operand" "rI")])
11165 "{t|tw}%V0%I2 %1,%2")
11168 [(trap_if (match_operator 0 "trap_comparison_operator"
11169 [(match_operand:DI 1 "register_operand" "r")
11170 (match_operand:DI 2 "reg_or_short_operand" "rI")])