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* rtl.h (rtunion_def): Constify member `rtstr'.
[official-gcc.git] / gcc / config / arm / thumb.h
blob4837504a3cf9a5c62235e3ff64e9b5e912ed3162
1 /* Definitions of target machine for GNU compiler, for ARM/Thumb.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
3 The basis of this contribution was generated by
4 Richard Earnshaw, Advanced RISC Machines Ltd
5
6 This file is part of GNU CC.
7
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 /* ??? The files thumb.{c,h,md} are all seriously lacking comments. */
24
25 /* ??? The files thumb.{c,h,md} need to be reviewed by an experienced
26 gcc hacker in their entirety. */
27
28 /* ??? The files thumb.{c,h,md} and tcoff.h are all separate from the arm
29 files, which will lead to many maintenance problems. These files are
30 likely missing all bug fixes made to the arm port since they diverged. */
31
32 /* ??? Many patterns in the md file accept operands that will require a
33 reload. These should be eliminated if possible by tightening the
34 predicates and/or constraints. This will give faster/smaller code. */
35
36 /* ??? There is no pattern for the TST instuction. Check for other unsupported
37 instructions. */
38
39 /* Run Time Target Specifications */
40 #ifndef CPP_PREDEFINES
41 #define CPP_PREDEFINES "-Dthumb -D__thumb -Acpu(arm) -Amachine(arm)"
42 #endif
43
44 #ifndef CPP_SPEC
45 #define CPP_SPEC "\
46 %{mbig-endian:-D__ARMEB__ -D__THUMBEB__} \
47 %{mbe:-D__ARMEB__ -D__THUMBEB__} \
48 %{!mbe: %{!mbig-endian:-D__ARMEL__ -D__THUMBEL__}} \
49 "
50 #endif
51
52 #define ASM_SPEC "-marm7tdmi %{mthumb-interwork:-mthumb-interwork} %{mbig-endian:-EB}"
53 #ifndef LINK_SPEC
54 #define LINK_SPEC "%{mbig-endian:-EB} -X"
55 #endif
56
57 #define TARGET_VERSION fputs (" (ARM/THUMB:generic)", stderr);
58
59 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
60 #define THUMB_FLAG_BIG_END 0x0001
61 #define THUMB_FLAG_BACKTRACE 0x0002
62 #define THUMB_FLAG_LEAF_BACKTRACE 0x0004
63 #define ARM_FLAG_THUMB 0x1000 /* same as in arm.h */
64 #define THUMB_FLAG_SINGLE_PIC_BASE 0x4000 /* same as in arm.h */
65 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING 0x40000
66 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING 0x80000
67
68
69 /* Run-time compilation parameters selecting different hardware/software subsets. */
70 extern int target_flags;
71 #define TARGET_DEFAULT 0 /* ARM_FLAG_THUMB */
72 #define TARGET_BIG_END (target_flags & THUMB_FLAG_BIG_END)
73 #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
74 #define TARGET_BACKTRACE (leaf_function_p() \
75 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
76 : (target_flags & THUMB_FLAG_BACKTRACE))
77 #define TARGET_SINGLE_PIC_BASE (target_flags & THUMB_FLAG_SINGLE_PIC_BASE)
78
79 #ifndef GOT_PCREL
80 #define GOT_PCREL 0
81 #endif
82
83 #ifndef NEED_GOT_RELOC
84 #define NEED_GOT_RELOC 1
85 #endif
86
87 /* Set if externally visible functions should assume that they
88 might be called in ARM mode, from a non-thumb aware code. */
89 #define TARGET_CALLEE_INTERWORKING \
90 (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
91
92 /* Set if calls via function pointers should assume that their
93 destination is non-Thumb aware. */
94 #define TARGET_CALLER_INTERWORKING \
95 (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
96
97 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
98 #ifndef SUBTARGET_SWITCHES
99 #define SUBTARGET_SWITCHES
100 #endif
101
102 #define TARGET_SWITCHES \
103 { \
104 {"big-endian", THUMB_FLAG_BIG_END, ""}, \
105 {"little-endian", -THUMB_FLAG_BIG_END, ""}, \
106 {"thumb-interwork", ARM_FLAG_THUMB, ""}, \
107 {"no-thumb-interwork", -ARM_FLAG_THUMB, ""}, \
108 {"tpcs-frame", THUMB_FLAG_BACKTRACE, ""}, \
109 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, ""}, \
110 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, ""}, \
111 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, ""}, \
112 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, ""}, \
113 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, ""}, \
114 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, ""}, \
115 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, ""}, \
116 {"single-pic-base", THUMB_FLAG_SINGLE_PIC_BASE, \
117 "Do not load the PIC register in function prologues" }, \
118 {"no-single-pic-base", -THUMB_FLAG_SINGLE_PIC_BASE, ""}, \
119 SUBTARGET_SWITCHES \
120 {"", TARGET_DEFAULT, ""} \
121 }
122
123 #define TARGET_OPTIONS \
124 { \
125 { "structure-size-boundary=", & structure_size_string, \
126 "Specify the structure aligment: 8 or 32 bits" }, \
127 { "pic-register=", & thumb_pic_register_string, \
128 "Specify the register to be used for PIC addressing" } \
129 }
130
131 #define REGISTER_PREFIX ""
132
133 #define CAN_DEBUG_WITHOUT_FP 1
134 \f
135 #define ASM_APP_ON ""
136 #define ASM_APP_OFF "\t.code\t16\n"
137
138 /* Output a gap. In fact we fill it with nulls. */
139 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
140 fprintf ((STREAM), "\t.space\t%u\n", (NBYTES))
141
142 /* This is how to output an assembler line that says to advance the
143 location counter to a multiple of 2**LOG bytes. Advancing to the
144 nearest 1 byte boundary is redundant, and anyway the assembler would
145 treat it as meaning "advance to nearest 4 byte boundary", which we do
146 not want. */
147 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
148 do \
149 { \
150 if ((LOG) > 0) \
151 fprintf (STREAM, "\t.align\t%d\n", LOG); \
152 } \
153 while (0)
154
155 /* Output a common block */
156 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
157 (fprintf ((STREAM), "\t.comm\t"), \
158 assemble_name ((STREAM), (NAME)), \
159 fprintf((STREAM), ", %d\t%s %d\n", (ROUNDED), (ASM_COMMENT_START), (SIZE)))
160
161 #define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \
162 sprintf ((STRING), "*%s%s%d", (LOCAL_LABEL_PREFIX), (PREFIX), (NUM))
163
164 /* This is how to output an internal numbered label where
165 PREFIX is the class of label and NUM is the number within the class. */
166 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
167 fprintf ((STREAM), "%s%s%d:\n", (LOCAL_LABEL_PREFIX), (PREFIX), (NUM))
168
169 /* This is how to output a label which precedes a jumptable. Since
170 instructions are 2 bytes, we need explicit alignment here. */
171
172 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,JUMPTABLE) \
173 do { \
174 ASM_OUTPUT_ALIGN (FILE, 2); \
175 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
176 } while (0)
177
178 /* This says how to define a local common symbol (ie, not visible to
179 linker). */
180 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
181 (fprintf((STREAM),"\n\t.lcomm\t"), \
182 assemble_name((STREAM),(NAME)), \
183 fprintf((STREAM),",%u\n",(SIZE)))
184
185 /* Output a reference to a label. */
186 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
187 fprintf ((STREAM), "%s%s", user_label_prefix, (NAME))
188
189 /* This is how to output an assembler line for a numeric constant byte. */
190 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
191 fprintf ((STREAM), "\t.byte\t0x%x\n", (VALUE))
192
193 #define ASM_OUTPUT_INT(STREAM,VALUE) \
194 { \
195 fprintf (STREAM, "\t.word\t"); \
196 OUTPUT_INT_ADDR_CONST (STREAM, (VALUE)); \
197 fprintf (STREAM, "\n"); \
198 }
199
200 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
201 { \
202 fprintf (STREAM, "\t.short\t"); \
203 output_addr_const (STREAM, (VALUE)); \
204 fprintf (STREAM, "\n"); \
205 }
206
207 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
208 { \
209 fprintf (STREAM, "\t.byte\t"); \
210 output_addr_const (STREAM, (VALUE)); \
211 fprintf (STREAM, "\n"); \
212 }
213
214 #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
215 do { char dstr[30]; \
216 long l[3]; \
217 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
218 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
219 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%s long double %s\n", \
220 l[0], l[1], l[2], ASM_COMMENT_START, dstr); \
221 } while (0)
222
223 #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
224 do { char dstr[30]; \
225 long l[2]; \
226 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
227 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
228 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%s double %s\n", l[0], \
229 l[1], ASM_COMMENT_START, dstr); \
230 } while (0)
231
232 #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
233 do { char dstr[30]; \
234 long l; \
235 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
236 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
237 fprintf (STREAM, "\t.word 0x%lx\t%s float %s\n", l, \
238 ASM_COMMENT_START, dstr); \
239 } while (0);
240
241 /* Define results of standard character escape sequences. */
242 #define TARGET_BELL 007
243 #define TARGET_BS 010
244 #define TARGET_TAB 011
245 #define TARGET_NEWLINE 012
246 #define TARGET_VT 013
247 #define TARGET_FF 014
248 #define TARGET_CR 015
249
250 /* This is how to output a string. */
251 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
252 do { \
253 register int i, c, len = (LEN), cur_pos = 17; \
254 register const unsigned char *string = (const unsigned char *)(STRING); \
255 fprintf ((STREAM), "\t.ascii\t\""); \
256 for (i = 0; i < len; i++) \
257 { \
258 register int c = string[i]; \
259 \
260 switch (c) \
261 { \
262 case '\"': \
263 case '\\': \
264 putc ('\\', (STREAM)); \
265 putc (c, (STREAM)); \
266 cur_pos += 2; \
267 break; \
268 \
269 case TARGET_NEWLINE: \
270 fputs ("\\n", (STREAM)); \
271 if (i+1 < len \
272 && (((c = string[i+1]) >= '\040' && c <= '~') \
273 || c == TARGET_TAB)) \
274 cur_pos = 32767; /* break right here */ \
275 else \
276 cur_pos += 2; \
277 break; \
278 \
279 case TARGET_TAB: \
280 fputs ("\\t", (STREAM)); \
281 cur_pos += 2; \
282 break; \
283 \
284 case TARGET_FF: \
285 fputs ("\\f", (STREAM)); \
286 cur_pos += 2; \
287 break; \
288 \
289 case TARGET_BS: \
290 fputs ("\\b", (STREAM)); \
291 cur_pos += 2; \
292 break; \
293 \
294 case TARGET_CR: \
295 fputs ("\\r", (STREAM)); \
296 cur_pos += 2; \
297 break; \
298 \
299 default: \
300 if (c >= ' ' && c < 0177) \
301 { \
302 putc (c, (STREAM)); \
303 cur_pos++; \
304 } \
305 else \
306 { \
307 fprintf ((STREAM), "\\%03o", c); \
308 cur_pos += 4; \
309 } \
310 } \
311 \
312 if (cur_pos > 72 && i+1 < len) \
313 { \
314 cur_pos = 17; \
315 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
316 } \
317 } \
318 fprintf ((STREAM), "\"\n"); \
319 } while (0)
320
321 /* Output and Generation of Labels */
322 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
323 (assemble_name ((STREAM), (NAME)), \
324 fprintf ((STREAM), ":\n"))
325
326 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
327 (fprintf ((STREAM), "\t.globl\t"), \
328 assemble_name ((STREAM), (NAME)), \
329 fputc ('\n', (STREAM)))
330
331 /* Construct a private name. */
332 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
333 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
334 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
335
336 /* Switch to the text or data segment. */
337 #define TEXT_SECTION_ASM_OP ".text"
338 #define DATA_SECTION_ASM_OP ".data"
339 #define BSS_SECTION_ASM_OP ".bss"
340
341 /* The assembler's names for the registers. */
342 #ifndef REGISTER_NAMES
343 #define REGISTER_NAMES \
344 { \
345 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
346 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", "ap" \
347 }
348 #endif
349
350 #ifndef ADDITIONAL_REGISTER_NAMES
351 #define ADDITIONAL_REGISTER_NAMES \
352 { \
353 {"a1", 0}, \
354 {"a2", 1}, \
355 {"a3", 2}, \
356 {"a4", 3}, \
357 {"v1", 4}, \
358 {"v2", 5}, \
359 {"v3", 6}, \
360 {"v4", 7}, \
361 {"v5", 8}, \
362 {"v6", 9}, \
363 {"sb", 9}, \
364 {"v7", 10}, \
365 {"r10", 10}, /* sl */ \
366 {"r11", 11}, /* fp */ \
367 {"r12", 12}, /* ip */ \
368 {"r13", 13}, /* sp */ \
369 {"r14", 14}, /* lr */ \
370 {"r15", 15} /* pc */ \
371 }
372 #endif
373
374 /* The assembler's parentheses characters. */
375 #define ASM_OPEN_PAREN "("
376 #define ASM_CLOSE_PAREN ")"
377
378 #ifndef ASM_COMMENT_START
379 #define ASM_COMMENT_START "@"
380 #endif
381
382 /* Output an element of a dispatch table. */
383 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
384 fprintf (STREAM, "\t.word\t%sL%d\n", (LOCAL_LABEL_PREFIX), (VALUE))
385
386 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
387 fprintf (STREAM, "\tb\t%sL%d\n", (LOCAL_LABEL_PREFIX), (VALUE))
388 \f
389 /* Storage Layout */
390
391 /* Define this is most significant bit is lowest numbered in
392 instructions that operate on numbered bit-fields. */
393 #define BITS_BIG_ENDIAN 0
394
395 /* Define this if most significant byte of a word is the lowest
396 numbered. */
397 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
398
399 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
400
401 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
402 on processor pre-defineds when compiling libgcc2.c. */
403 #if defined(__THUMBEB__) && !defined(__THUMBEL__)
404 #define LIBGCC2_WORDS_BIG_ENDIAN 1
405 #else
406 #define LIBGCC2_WORDS_BIG_ENDIAN 0
407 #endif
408
409 #define FLOAT_WORDS_BIG_ENDIAN 1
410
411 #define BITS_PER_UNIT 8
412 #define BITS_PER_WORD 32
413
414 #define UNITS_PER_WORD 4
415
416 #define POINTER_SIZE 32
417
418 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
419 { \
420 if (GET_MODE_CLASS (MODE) == MODE_INT \
421 && GET_MODE_SIZE (MODE) < 4) \
422 { \
423 (UNSIGNEDP) = 1; \
424 (MODE) = SImode; \
425 } \
426 }
427
428 #define PARM_BOUNDARY 32
429 #define STACK_BOUNDARY 32
430
431 #define FUNCTION_BOUNDARY 32
432 #define BIGGEST_ALIGNMENT 32
433
434 /* Make strings word-aligned so strcpy from constants will be faster. */
435 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
436 (TREE_CODE (EXP) == STRING_CST \
437 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
438
439 #define EMPTY_FIELD_BOUNDARY 32
440
441 #define STRUCTURE_SIZE_BOUNDARY 32
442
443 /* Used when parsing command line option -mstructure_size_boundary. */
444 extern const char * structure_size_string;
445
446 #define STRICT_ALIGNMENT 1
447
448 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
449
450 \f
451 /* Layout of Source Language Data Types */
452
453 #define DEFAULT_SIGNED_CHAR 0
454
455 #define TARGET_BELL 007
456 #define TARGET_BS 010
457 #define TARGET_TAB 011
458 #define TARGET_NEWLINE 012
459 #define TARGET_VT 013
460 #define TARGET_FF 014
461 #define TARGET_CR 015
462
463 \f
464 /* Register Usage */
465
466 /* Note there are 16 hard registers on the Thumb. We invent a 17th register
467 which is assigned to ARG_POINTER_REGNUM, but this is later removed by
468 elimination passes in the compiler. */
469 #define FIRST_PSEUDO_REGISTER 17
470
471 /* ??? This is questionable. */
472 #define FIXED_REGISTERS \
473 { \
474 0,0,0,0, \
475 0,0,0,0, \
476 0,0,0,1, \
477 0,1,1,1,1 \
478 }
479
480 /* ??? This is questionable. */
481 #define CALL_USED_REGISTERS \
482 { \
483 1,1,1,1, \
484 0,0,0,0, \
485 0,0,0,1, \
486 1,1,1,1,1 \
487 }
488
489 #define HARD_REGNO_NREGS(REGNO,MODE) \
490 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
491 / UNITS_PER_WORD)
492
493 /* ??? Probably should only allow DImode/DFmode in even numbered registers. */
494 #define HARD_REGNO_MODE_OK(REGNO,MODE) ((GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (REGNO < 7) : 1)
495
496 #define MODES_TIEABLE_P(MODE1,MODE2) 1
497
498 /* The NOARG_LO_REGS class is the set of LO_REGS that are not used for passing
499 arguments to functions. These are the registers that are available for
500 spilling during reload. The code in reload1.c:init_reload() will detect this
501 class and place it into 'reload_address_base_reg_class'. */
502
503 enum reg_class
504 {
505 NO_REGS,
506 NONARG_LO_REGS,
507 LO_REGS,
508 STACK_REG,
509 BASE_REGS,
510 HI_REGS,
511 ALL_REGS,
512 LIM_REG_CLASSES
513 };
514
515 #define GENERAL_REGS ALL_REGS
516
517 #define N_REG_CLASSES (int) LIM_REG_CLASSES
518
519 #define REG_CLASS_NAMES \
520 { \
521 "NO_REGS", \
522 "NONARG_LO_REGS", \
523 "LO_REGS", \
524 "STACK_REG", \
525 "BASE_REGS", \
526 "HI_REGS", \
527 "ALL_REGS" \
528 }
529
530 #define REG_CLASS_CONTENTS \
531 { \
532 { 0x00000 }, \
533 { 0x000f0 }, \
534 { 0x000ff }, \
535 { 0x02000 }, \
536 { 0x020ff }, \
537 { 0x0ff00 }, \
538 { 0x1ffff }, \
539 }
540
541 #define REGNO_REG_CLASS(REGNO) \
542 ((REGNO) == STACK_POINTER_REGNUM ? STACK_REG \
543 : (REGNO) < 8 ? ((REGNO) < 4 ? LO_REGS \
544 : NONARG_LO_REGS) \
545 : HI_REGS)
546
547 #define BASE_REG_CLASS BASE_REGS
548
549 #define INDEX_REG_CLASS LO_REGS
550
551 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
552 registers explicitly used in the rtl to be used as spill registers
553 but prevents the compiler from extending the lifetime of these
554 registers. */
555
556 #define SMALL_REGISTER_CLASSES 1
557
558 #define REG_CLASS_FROM_LETTER(C) \
559 ((C) == 'l' ? LO_REGS \
560 : (C) == 'h' ? HI_REGS \
561 : (C) == 'b' ? BASE_REGS \
562 : (C) == 'k' ? STACK_REG \
563 : NO_REGS)
564
565 #define REGNO_OK_FOR_BASE_P(REGNO) \
566 ((REGNO) < 8 \
567 || (REGNO) == STACK_POINTER_REGNUM \
568 || (unsigned) reg_renumber[REGNO] < 8 \
569 || (unsigned) reg_renumber[REGNO] == STACK_POINTER_REGNUM)
570
571 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
572 ((REGNO) < 8 \
573 || (unsigned) reg_renumber[REGNO] < 8 \
574 || (GET_MODE_SIZE (MODE) >= 4 \
575 && ((REGNO) == STACK_POINTER_REGNUM \
576 || (unsigned) reg_renumber[REGNO] == STACK_POINTER_REGNUM)))
577
578 #define REGNO_OK_FOR_INDEX_P(REGNO) \
579 ((REGNO) < 8 \
580 || (unsigned) reg_renumber[REGNO] < 8)
581
582 #define INDEX_REGISTER_RTX_P(X) \
583 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
584
585 /* ??? This looks suspiciously wrong. */
586 /* We need to leave BASE_REGS reloads alone, in order to avoid caller_save
587 lossage. Caller_saves requests a BASE_REGS reload (caller_save_spill_class)
588 and then later we verify that one was allocated. If PREFERRED_RELOAD_CLASS
589 says to allocate a LO_REGS spill instead, then this mismatch gives an
590 abort. Alternatively, this could be fixed by modifying BASE_REG_CLASS
591 to be LO_REGS instead of BASE_REGS. It is not clear what affect this
592 change would have. */
593 /* ??? This looks even more suspiciously wrong. PREFERRED_RELOAD_CLASS
594 must always return a strict subset of the input class. Just blindly
595 returning LO_REGS is safe only if the input class is a superset of LO_REGS,
596 but there is no check for this. Added another exception for NONARG_LO_REGS
597 because it is not a superset of LO_REGS. */
598 /* ??? We now use NONARG_LO_REGS for caller_save_spill_class, so the
599 comments about BASE_REGS are now obsolete. */
600 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
601 ((CLASS) == BASE_REGS || (CLASS) == NONARG_LO_REGS ? (CLASS) \
602 : LO_REGS)
603 /*
604 ((CONSTANT_P ((X)) && GET_CODE ((X)) != CONST_INT \
605 && ! CONSTANT_POOL_ADDRESS_P((X))) ? NO_REGS \
606 : (GET_CODE ((X)) == CONST_INT \
607 && (unsigned HOST_WIDE_INT) INTVAL ((X)) > 255) ? NO_REGS \
608 : LO_REGS) */
609
610 /* Must leave BASE_REGS and NONARG_LO_REGS reloads alone, see comment
611 above. */
612 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \
613 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS && (CLASS) != NONARG_LO_REGS \
614 ? ((true_regnum (X) == -1 ? LO_REGS \
615 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
616 : NO_REGS)) \
617 : NO_REGS)
618
619 #define CLASS_MAX_NREGS(CLASS,MODE) HARD_REGNO_NREGS(0,(MODE))
620
621 int thumb_shiftable_const ();
622
623 #define CONST_OK_FOR_LETTER_P(VAL,C) \
624 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 \
625 : (C) == 'J' ? (VAL) > -256 && (VAL) <= 0 \
626 : (C) == 'K' ? thumb_shiftable_const (VAL) \
627 : (C) == 'L' ? (VAL) > -8 && (VAL) < 8 \
628 : (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
629 && ((VAL) & 3) == 0) \
630 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
631 : (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
632 : 0)
633
634 #define CONST_DOUBLE_OK_FOR_LETTER_P(VAL,C) 0
635
636 #define EXTRA_CONSTRAINT(X,C) \
637 ((C) == 'Q' ? (GET_CODE (X) == MEM \
638 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
639 \f
640 /* Stack Layout and Calling Conventions */
641
642 #define STACK_GROWS_DOWNWARD 1
643
644 /* #define FRAME_GROWS_DOWNWARD 1 */
645
646 /* #define ARGS_GROW_DOWNWARD 1 */
647
648 #define STARTING_FRAME_OFFSET 0
649
650 #define FIRST_PARM_OFFSET(FNDECL) 0
651
652 /* Registers that address the stack frame */
653
654 #define STACK_POINTER_REGNUM 13 /* Defined by the TPCS. */
655
656 #define FRAME_POINTER_REGNUM 7 /* TPCS defines this as 11 but it does not really mean it. */
657
658 #define ARG_POINTER_REGNUM 16 /* A fake hard register that is eliminated later on. */
659
660 #define STATIC_CHAIN_REGNUM 9
661
662 /* Define this if the program counter is overloaded on a register. */
663 #define PC_REGNUM 15
664
665 #define FRAME_POINTER_REQUIRED 0
666
667 #define ELIMINABLE_REGS \
668 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
669 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
670 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
671
672 /* On the Thumb we always want to perform the eliminations as we
673 actually only have one real register pointing to the stashed
674 variables: the stack pointer, and we never use the frame pointer. */
675 #define CAN_ELIMINATE(FROM,TO) 1
676
677 /* Note: This macro must match the code in thumb_function_prologue() in thumb.c. */
678 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \
679 { \
680 (OFFSET) = 0; \
681 if ((FROM) == ARG_POINTER_REGNUM) \
682 { \
683 int count_regs = 0; \
684 int regno; \
685 (OFFSET) += get_frame_size (); \
686 for (regno = 8; regno < 13; regno++) \
687 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
688 count_regs++; \
689 if (count_regs) \
690 (OFFSET) += 4 * count_regs; \
691 count_regs = 0; \
692 for (regno = 0; regno < 8; regno++) \
693 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
694 count_regs++; \
695 if (count_regs || ! leaf_function_p () || far_jump_used_p()) \
696 (OFFSET) += 4 * (count_regs + 1); \
697 if (TARGET_BACKTRACE) { \
698 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
699 (OFFSET) += 20; \
700 else \
701 (OFFSET) += 16; } \
702 } \
703 if ((TO) == STACK_POINTER_REGNUM) \
704 (OFFSET) += current_function_outgoing_args_size; \
705 }
706
707 /* A C expression whose value is RTL representing the value of the return
708 address for the frame COUNT steps up from the current frame. */
709
710 #define RETURN_ADDR_RTX(COUNT, FRAME) \
711 thumb_return_addr (COUNT)
712 /* Passing Arguments on the stack */
713
714 /* Initialize data used by insn expanders. This is called from insn_emit,
715 once for every function before code is generated. */
716 #define INIT_EXPANDERS thumb_init_expanders ()
717
718 #define PROMOTE_PROTOTYPES 1
719
720 #define ACCUMULATE_OUTGOING_ARGS 1
721
722 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
723
724 #define FUNCTION_ARG(CUM,MODE,TYPE,NAMED) \
725 ((NAMED) ? ((CUM) >= 16 ? 0 : gen_rtx (REG, (MODE), (CUM) / 4)) \
726 : 0)
727
728 #define FUNCTION_ARG_PARTIAL_NREGS(CUM,MODE,TYPE,NAMED) \
729 (((CUM) < 16 && (CUM) + (((MODE) == BLKmode) \
730 ? int_size_in_bytes (TYPE) \
731 : HARD_REGNO_NREGS (0, (MODE)) * 4) > 16) \
732 ? 4 - (CUM) / 4 : 0)
733
734 #define CUMULATIVE_ARGS int
735
736 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
737 ((CUM) = ((FNTYPE) && aggregate_value_p (TREE_TYPE (FNTYPE))) ? 4 : 0)
738
739 #define FUNCTION_ARG_ADVANCE(CUM,MODE,TYPE,NAMED) \
740 (CUM) += ((((MODE) == BLKmode) \
741 ? int_size_in_bytes (TYPE) \
742 : GET_MODE_SIZE (MODE)) + 3) & ~3
743
744 #define FUNCTION_ARG_REGNO_P(REGNO) \
745 ((REGNO) >=0 && (REGNO) <= 3)
746
747 #define FUNCTION_VALUE(VALTYPE,FUNC) gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
748
749 #define LIBCALL_VALUE(MODE) gen_rtx (REG, (MODE), 0)
750
751 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0)
752
753 /* How large values are returned */
754 /* A C expression which can inhibit the returning of certain function values
755 in registers, based on the type of value. */
756 #define RETURN_IN_MEMORY(TYPE) thumb_return_in_memory (TYPE)
757
758 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
759 values must be in memory. On the ARM, they need only do so if larger
760 than a word, or if they contain elements offset from zero in the struct. */
761 #define DEFAULT_PCC_STRUCT_RETURN 0
762
763
764 #define STRUCT_VALUE_REGNUM 0
765
766 #define FUNCTION_PROLOGUE(FILE,SIZE) thumb_function_prologue((FILE),(SIZE))
767
768 #define FUNCTION_EPILOGUE(FILE,SIZE) thumb_function_epilogue((FILE),(SIZE))
769
770 /* Generating code for profiling */
771 #define FUNCTION_PROFILER(STREAM,LABELNO) \
772 { \
773 fprintf ((STREAM), "\tmov\\tip, lr\n"); \
774 fprintf ((STREAM), "\tbl\tmcount\n"); \
775 fprintf ((STREAM), "\t.word\tLP%d\n", (LABELNO)); \
776 }
777
778 /* Implementing the Varargs Macros */
779
780 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
781 { \
782 extern int current_function_anonymous_args; \
783 current_function_anonymous_args = 1; \
784 if ((CUM) < 16) \
785 (PRETEND_SIZE) = 16 - (CUM); \
786 }
787
788 /* Trampolines for nested functions */
789
790 /* Output assembler code for a block containing the constant parts of
791 a trampoline, leaving space for the variable parts.
792
793 On the Thumb we always switch into ARM mode to execute the trampoline.
794 Why - because it is easier. This code will always be branched to via
795 a BX instruction and since the compiler magically generates the address
796 of the function the linker has no opportunity to ensure that the
797 bottom bit is set. Thus the processor will be in ARM mode when it
798 reaches this code. So we duplicate the ARM trampoline code and add
799 a switch into Thumb mode as well.
800
801 On the ARM, (if r8 is the static chain regnum, and remembering that
802 referencing pc adds an offset of 8) the trampoline looks like:
803 ldr r8, [pc, #0]
804 ldr pc, [pc]
805 .word static chain value
806 .word function's address
807 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
808 #define TRAMPOLINE_TEMPLATE(FILE) \
809 { \
810 fprintf ((FILE), "\t.code 32\n"); \
811 fprintf ((FILE), ".Ltrampoline_start:\n"); \
812 fprintf ((FILE), "\tldr\t%s, [%spc, #8]\n", \
813 reg_names[STATIC_CHAIN_REGNUM], REGISTER_PREFIX); \
814 fprintf ((FILE), "\tldr\t%sip, [%spc, #8]\n", \
815 REGISTER_PREFIX, REGISTER_PREFIX); \
816 fprintf ((FILE), "\torr\t%sip, %sip, #1\n", \
817 REGISTER_PREFIX, REGISTER_PREFIX); \
818 fprintf ((FILE), "\tbx\t%sip\n", REGISTER_PREFIX); \
819 fprintf ((FILE), "\t.word\t0\n"); \
820 fprintf ((FILE), "\t.word\t0\n"); \
821 fprintf ((FILE), "\t.code 16\n"); \
822 }
823
824 /* Length in units of the trampoline for entering a nested function. */
825 #define TRAMPOLINE_SIZE 24
826
827 /* Alignment required for a trampoline in units. */
828 #define TRAMPOLINE_ALIGN 4
829
830 #define INITIALIZE_TRAMPOLINE(ADDR,FNADDR,CHAIN) \
831 { \
832 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((ADDR), 16)), \
833 (CHAIN)); \
834 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((ADDR), 20)), \
835 (FNADDR)); \
836 }
837
838 \f
839 /* Position Independent Code. */
840 /* We decide which register to use based on the compilation options and
841 the assembler in use. @@@ Actually, we don't currently for Thumb. */
842 extern int thumb_pic_register;
843
844 /* The register number of the register used to address a table of static
845 data addresses in memory. */
846 #define PIC_OFFSET_TABLE_REGNUM thumb_pic_register
847
848 #define FINALIZE_PIC thumb_finalize_pic ()
849
850 /* We can't directly access anything that contains a symbol,
851 nor can we indirect via the constant pool. */
852 #define LEGITIMATE_PIC_OPERAND_P(X) \
853 (! thumb_symbol_mentioned_p (X) \
854 && (! CONSTANT_POOL_ADDRESS_P (X) \
855 || ! thumb_symbol_mentioned_p (get_pool_constant (X))))
856
857 /* We need to know when we are making a constant pool; this determines
858 whether data needs to be in the GOT or can be referenced via a GOT
859 offset. */
860 extern int making_const_table;
861
862 #define CONDITIONAL_REGISTER_USAGE \
863 { \
864 if (flag_pic) \
865 { \
866 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
867 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
868 } \
869 }
870
871 \f
872 /* Implicit Calls to Library Routines */
873
874 #define TARGET_MEM_FUNCTIONS 1
875
876 #define OVERRIDE_OPTIONS thumb_override_options ()
877
878 \f
879 /* Addressing Modes */
880
881 #define HAVE_POST_INCREMENT 1
882
883 #define CONSTANT_ADDRESS_P(X) \
884 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
885
886 #define MAX_REGS_PER_ADDRESS 2
887
888 #ifdef REG_OK_STRICT
889
890 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
891 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
892
893 #define REG_MODE_OK_FOR_BASE_P(X,MODE) \
894 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
895
896 #else /* REG_OK_STRICT */
897
898 #define REG_OK_FOR_BASE_P(X) \
899 (REGNO (X) < 8 || REGNO (X) == STACK_POINTER_REGNUM \
900 || (X) == arg_pointer_rtx \
901 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
902
903 #define REG_MODE_OK_FOR_BASE_P(X,MODE) \
904 (REGNO (X) < 8 \
905 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
906 || (GET_MODE_SIZE (MODE) >= 4 \
907 && (REGNO (X) == STACK_POINTER_REGNUM \
908 || (X) == arg_pointer_rtx)))
909
910 #define REG_OK_FOR_INDEX_P(X) \
911 (REGNO (X) < 8 \
912 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
913
914 #endif /* REG_OK_STRICT */
915
916 /* In a REG+REG address, both must be INDEX registers. */
917 #define REG_OK_FOR_INDEXED_BASE_P(X) REG_OK_FOR_INDEX_P(X)
918
919 #define LEGITIMATE_OFFSET(MODE,VAL) \
920 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
921 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
922 && ((VAL) & 1) == 0) \
923 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
924 && ((VAL) & 3) == 0))
925
926 /* The AP may be eliminated to either the SP or the FP, so we use the
927 least common denominator, e.g. SImode, and offsets from 0 to 64. */
928
929 /* ??? Verify whether the above is the right approach. */
930
931 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
932 needs special handling also. */
933
934 /* ??? Look at how the mips16 port solves this problem. It probably uses
935 better ways to solve some of these problems. */
936
937 /* Although it is not incorrect, we don't accept QImode and HImode
938 addresses based on the frame pointer or arg pointer until the reload pass starts.
939 This is so that eliminating such addresses into stack based ones
940 won't produce impossible code. */
941 #define GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
942 { \
943 /* ??? Not clear if this is right. Experiment. */ \
944 if (GET_MODE_SIZE (MODE) < 4 \
945 && ! (reload_in_progress || reload_completed) \
946 && (reg_mentioned_p (frame_pointer_rtx, X) \
947 || reg_mentioned_p (arg_pointer_rtx, X) \
948 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
949 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
950 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
951 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
952 ; \
953 /* Accept any base register. SP only in SImode or larger. */ \
954 else if (GET_CODE (X) == REG && REG_MODE_OK_FOR_BASE_P(X, MODE)) \
955 goto WIN; \
956 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
957 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
958 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
959 goto WIN; \
960 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
961 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
962 && (GET_CODE (X) == LABEL_REF \
963 || (GET_CODE (X) == CONST \
964 && GET_CODE (XEXP (X, 0)) == PLUS \
965 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
966 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
967 goto WIN; \
968 /* Post-inc indexing only supported for SImode and larger. */ \
969 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
970 && GET_CODE (XEXP (X, 0)) == REG \
971 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
972 goto WIN; \
973 else if (GET_CODE (X) == PLUS) \
974 { \
975 /* REG+REG address can be any two index registers. */ \
976 /* ??? REG+REG addresses have been completely disabled before \
977 reload completes, because we do not have enough available \
978 reload registers. We only have 3 guaranteed reload registers \
979 (NONARG_LO_REGS - the frame pointer), but we need at least 4 \
980 to support REG+REG addresses. We have left them enabled after \
981 reload completes, in the hope that reload_cse_regs and related \
982 routines will be able to create them after the fact. It is \
983 probably possible to support REG+REG addresses with additional \
984 reload work, but I do not not have enough time to attempt such \
985 a change at this time. */ \
986 /* ??? Normally checking the mode here is wrong, since it isn't \
987 impossible to use REG+REG with DFmode. However, the movdf \
988 pattern requires offsettable addresses, and REG+REG is not \
989 offsettable, so it must be rejected somehow. Trying to use \
990 'o' fails, because offsettable_address_p does a QImode check. \
991 QImode is not valid for stack addresses, and has a smaller \
992 range for non-stack bases, and this causes valid addresses \
993 to be rejected. So we just eliminate REG+REG here by checking \
994 the mode. */ \
995 /* We also disallow FRAME+REG addressing since we know that FRAME \
996 will be replaced with STACK, and SP relative addressing only \
997 permits SP+OFFSET. */ \
998 if (GET_MODE_SIZE (MODE) <= 4 \
999 /* ??? See comment above. */ \
1000 && reload_completed \
1001 && GET_CODE (XEXP (X, 0)) == REG \
1002 && GET_CODE (XEXP (X, 1)) == REG \
1003 && XEXP (X, 0) != frame_pointer_rtx \
1004 && XEXP (X, 1) != frame_pointer_rtx \
1005 && XEXP (X, 0) != virtual_stack_vars_rtx \
1006 && XEXP (X, 1) != virtual_stack_vars_rtx \
1007 && REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
1008 && REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
1009 goto WIN; \
1010 /* REG+const has 5-7 bit offset for non-SP registers. */ \
1011 else if (GET_CODE (XEXP (X, 0)) == REG \
1012 && (REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
1013 || XEXP (X, 0) == arg_pointer_rtx) \
1014 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1015 && LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1016 goto WIN; \
1017 /* REG+const has 10 bit offset for SP, but only SImode and \
1018 larger is supported. */ \
1019 /* ??? Should probably check for DI/DFmode overflow here \
1020 just like GO_IF_LEGITIMATE_OFFSET does. */ \
1021 else if (GET_CODE (XEXP (X, 0)) == REG \
1022 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
1023 && GET_MODE_SIZE (MODE) >= 4 \
1024 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1025 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
1026 + GET_MODE_SIZE (MODE)) <= 1024 \
1027 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
1028 goto WIN; \
1029 } \
1030 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1031 && GET_CODE (X) == SYMBOL_REF \
1032 && CONSTANT_POOL_ADDRESS_P (X) \
1033 && ! (flag_pic \
1034 && thumb_symbol_mentioned_p (get_pool_constant (X)))) \
1035 goto WIN; \
1036 }
1037
1038 /* ??? If an HImode FP+large_offset address is converted to an HImode
1039 SP+large_offset address, then reload won't know how to fix it. It sees
1040 only that SP isn't valid for HImode, and so reloads the SP into an index
1041 register, but the resulting address is still invalid because the offset
1042 is too big. We fix it here instead by reloading the entire address. */
1043 /* We could probably achieve better results by defining PROMOTE_MODE to help
1044 cope with the variances between the Thumb's signed and unsigned byte and
1045 halfword load instructions. */
1046 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1047 { \
1048 if (GET_CODE (X) == PLUS \
1049 && GET_MODE_SIZE (MODE) < 4 \
1050 && GET_CODE (XEXP (X, 0)) == REG \
1051 && XEXP (X, 0) == stack_pointer_rtx \
1052 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1053 && ! LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1054 { \
1055 rtx orig_X = X; \
1056 X = copy_rtx (X); \
1057 push_reload (orig_X, NULL_RTX, &X, NULL_PTR, \
1058 BASE_REG_CLASS, \
1059 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1060 goto WIN; \
1061 } \
1062 }
1063
1064 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1065
1066 extern struct rtx_def * legitimize_pic_address ();
1067 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1068 if (flag_pic) \
1069 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
1070
1071 #define LEGITIMATE_CONSTANT_P(X) \
1072 (GET_CODE (X) == CONST_INT \
1073 || GET_CODE (X) == CONST_DOUBLE \
1074 || CONSTANT_ADDRESS_P (X))
1075
1076 \f
1077 /* Condition Code Status */
1078
1079 #define NOTICE_UPDATE_CC(EXP,INSN) \
1080 { \
1081 if (get_attr_conds ((INSN)) != CONDS_UNCHANGED) \
1082 CC_STATUS_INIT; \
1083 }
1084
1085 \f
1086 /* Describing Relative Costs of Operations */
1087
1088 #define SLOW_BYTE_ACCESS 0
1089
1090 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
1091
1092 #define NO_FUNCTION_CSE 1
1093
1094 #define NO_RECURSIVE_FUNCTION_CSE 1
1095
1096 #define REGISTER_MOVE_COST(FROM,TO) \
1097 (((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1098
1099 #define MEMORY_MOVE_COST(M,CLASS,IN) \
1100 ((GET_MODE_SIZE(M) < 4 ? 8 : 2 * GET_MODE_SIZE(M)) * (CLASS == LO_REGS ? 1 : 2))
1101
1102 /* This will allow better space optimization when compiling with -O */
1103 #define BRANCH_COST (optimize > 1 ? 1 : 0)
1104
1105 #define RTX_COSTS(X,CODE,OUTER) \
1106 case MULT: \
1107 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1108 { \
1109 int cycles = 0; \
1110 unsigned HOST_WIDE_INT i = INTVAL (XEXP (X, 1)); \
1111 while (i) \
1112 { \
1113 i >>= 2; \
1114 cycles++; \
1115 } \
1116 return COSTS_N_INSNS (2) + cycles; \
1117 } \
1118 return COSTS_N_INSNS (1) + 16; \
1119 case ASHIFT: case ASHIFTRT: case LSHIFTRT: case ROTATERT: \
1120 case PLUS: case MINUS: case COMPARE: case NEG: case NOT: \
1121 return COSTS_N_INSNS (1); \
1122 case SET: \
1123 return (COSTS_N_INSNS (1) \
1124 + 4 * ((GET_CODE (SET_SRC (X)) == MEM) \
1125 + GET_CODE (SET_DEST (X)) == MEM))
1126
1127 #define CONST_COSTS(X,CODE,OUTER) \
1128 case CONST_INT: \
1129 if ((OUTER) == SET) \
1130 { \
1131 if ((unsigned HOST_WIDE_INT) INTVAL (X) < 256) \
1132 return 0; \
1133 if (thumb_shiftable_const (INTVAL (X))) \
1134 return COSTS_N_INSNS (2); \
1135 return COSTS_N_INSNS (3); \
1136 } \
1137 else if (OUTER == PLUS \
1138 && INTVAL (X) < 256 && INTVAL (X) > -256) \
1139 return 0; \
1140 else if (OUTER == COMPARE \
1141 && (unsigned HOST_WIDE_INT) INTVAL (X) < 256) \
1142 return 0; \
1143 else if (OUTER == ASHIFT || OUTER == ASHIFTRT \
1144 || OUTER == LSHIFTRT) \
1145 return 0; \
1146 return COSTS_N_INSNS (2); \
1147 case CONST: \
1148 case CONST_DOUBLE: \
1149 case LABEL_REF: \
1150 case SYMBOL_REF: \
1151 return COSTS_N_INSNS(3);
1152
1153 #define ADDRESS_COST(X) \
1154 ((GET_CODE (X) == REG \
1155 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1156 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
1157 ? 1 : 2)
1158
1159 \f
1160 /* Position Independent Code */
1161
1162 extern const char * thumb_pic_register_string;
1163 extern int thumb_pic_register;
1164
1165 /* The register number of the register used to address a table of static
1166 data addresses in memory. */
1167 #define PIC_OFFSET_TABLE_REGNUM thumb_pic_register
1168
1169 #define FINALIZE_PIC thumb_finalize_pic ()
1170
1171 /* We can't directly access anything that contains a symbol,
1172 nor can we indirect via the constant pool. */
1173 #define LEGITIMATE_PIC_OPERAND_P(X) \
1174 (! thumb_symbol_mentioned_p (X) \
1175 && (! CONSTANT_POOL_ADDRESS_P (X) \
1176 || ! thumb_symbol_mentioned_p (get_pool_constant (X))))
1177
1178 /* We need to know when we are making a constant pool; this determines
1179 whether data needs to be in the GOT or can be referenced via a GOT
1180 offset. */
1181 extern int making_const_table;
1182
1183 \f
1184 #define PRINT_OPERAND(STREAM,X,CODE) \
1185 thumb_print_operand((STREAM), (X), (CODE))
1186
1187 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1188 { \
1189 if (GET_CODE ((X)) == REG) \
1190 fprintf ((STREAM), "[%s]", reg_names[REGNO ((X))]); \
1191 else if (GET_CODE ((X)) == POST_INC) \
1192 fprintf ((STREAM), "%s!", reg_names[REGNO (XEXP (X, 0))]); \
1193 else if (GET_CODE ((X)) == PLUS) \
1194 { \
1195 if (GET_CODE (XEXP ((X), 1)) == CONST_INT) \
1196 fprintf ((STREAM), "[%s, #%d]", \
1197 reg_names[REGNO (XEXP ((X), 0))], \
1198 (int) INTVAL (XEXP ((X), 1))); \
1199 else \
1200 fprintf ((STREAM), "[%s, %s]", \
1201 reg_names[REGNO (XEXP ((X), 0))], \
1202 reg_names[REGNO (XEXP ((X), 1))]); \
1203 } \
1204 else \
1205 output_addr_const ((STREAM), (X)); \
1206 }
1207
1208 /* Handles PIC addr specially */
1209 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
1210 { \
1211 if (flag_pic && GET_CODE(X) == CONST && is_pic(X)) \
1212 { \
1213 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
1214 fputs(" - (", STREAM); \
1215 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
1216 fputs(")", STREAM); \
1217 } \
1218 else output_addr_const(STREAM, X); \
1219 \
1220 /* Mark symbols as position independent. We only do this in the \
1221 .text segment, not in the .data segment. */ \
1222 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
1223 (GET_CODE(X) == SYMBOL_REF || GET_CODE(X) == LABEL_REF)) \
1224 { \
1225 if (GET_CODE(X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(X)) \
1226 fprintf(STREAM, "(GOTOFF)"); \
1227 else if (GET_CODE (X) == LABEL_REF) \
1228 fprintf(STREAM, "(GOTOFF)"); \
1229 else \
1230 fprintf(STREAM, "(GOT)"); \
1231 } \
1232 }
1233
1234 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '@' || ((CODE) == '_') || ((CODE) == '|'))
1235
1236 /* Emit a special directive when defining a function name.
1237 This is used by the assembler to assit with interworking. */
1238 #define ASM_DECLARE_FUNCTION_NAME(file, name, decl) \
1239 if (! is_called_in_ARM_mode (decl)) \
1240 fprintf (file, "\t.thumb_func\n") ; \
1241 else \
1242 fprintf (file, "\t.code\t32\n") ; \
1243 ASM_OUTPUT_LABEL (file, name)
1244
1245 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1246 asm_fprintf ((STREAM), "\tpush {%R%s}\n", reg_names[(REGNO)])
1247
1248 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1249 asm_fprintf ((STREAM), "\tpop {%R%s}\n", reg_names[(REGNO)])
1250
1251 #define FINAL_PRESCAN_INSN(INSN,OPVEC,NOPERANDS) \
1252 thumb_final_prescan_insn (INSN)
1253 \f
1254 /* Controlling Debugging Information Format */
1255 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1256
1257 /* Specific options for DBX Output */
1258
1259 #define DEFAULT_GDB_EXTENSIONS 1
1260
1261 \f
1262 /* Cross Compilation and Floating Point */
1263
1264 #define REAL_ARITHMETIC
1265
1266 \f
1267 /* Miscellaneous Parameters */
1268
1269 #define PREDICATE_CODES \
1270 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}},
1271
1272 #define CASE_VECTOR_MODE Pmode
1273
1274 #define WORD_REGISTER_OPERATIONS
1275
1276 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1277
1278 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1279
1280 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1281
1282 #define MOVE_MAX 4
1283
1284 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1285
1286 #define STORE_FLAG_VALUE 1
1287
1288 #define Pmode SImode
1289
1290 #define FUNCTION_MODE SImode
1291
1292 #define DOLLARS_IN_IDENTIFIERS 0
1293
1294 #define NO_DOLLAR_IN_LABEL 1
1295
1296 /* The literal pool needs to reside in the text area due to the
1297 limited PC addressing range: */
1298 #define MACHINE_DEPENDENT_REORG(INSN) thumb_reorg (INSN)
1299
1300 \f
1301 /* Options specific to Thumb */
1302
1303 /* True if a return instruction can be used in this function. */
1304 #define USE_RETURN (reload_completed && thumb_trivial_epilogue ())
1305
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