1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2014 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
35 #include "stringpool.h"
36 #include "stor-layout.h"
38 #include "print-tree.h"
46 #include "basic-block.h"
47 #include "diagnostic-core.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
58 #include "sched-int.h"
59 #include "pointer-set.h"
60 #include "hash-table.h"
62 #include "basic-block.h"
63 #include "tree-ssa-alias.h"
64 #include "internal-fn.h"
65 #include "gimple-fold.h"
67 #include "gimple-expr.h"
71 #include "gimple-iterator.h"
72 #include "gimple-walk.h"
75 #include "tm-constrs.h"
78 #include "tree-vectorizer.h"
81 #include "target-globals.h"
83 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
86 #include "gstab.h" /* for N_SLINE */
89 #ifndef TARGET_NO_PROTOTYPE
90 #define TARGET_NO_PROTOTYPE 0
93 #define min(A,B) ((A) < (B) ? (A) : (B))
94 #define max(A,B) ((A) > (B) ? (A) : (B))
96 /* Structure used to define the rs6000 stack */
97 typedef struct rs6000_stack
{
98 int reload_completed
; /* stack info won't change from here on */
99 int first_gp_reg_save
; /* first callee saved GP register used */
100 int first_fp_reg_save
; /* first callee saved FP register used */
101 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
102 int lr_save_p
; /* true if the link reg needs to be saved */
103 int cr_save_p
; /* true if the CR reg needs to be saved */
104 unsigned int vrsave_mask
; /* mask of vec registers to save */
105 int push_p
; /* true if we need to allocate stack space */
106 int calls_p
; /* true if the function makes any calls */
107 int world_save_p
; /* true if we're saving *everything*:
108 r13-r31, cr, f14-f31, vrsave, v20-v31 */
109 enum rs6000_abi abi
; /* which ABI to use */
110 int gp_save_offset
; /* offset to save GP regs from initial SP */
111 int fp_save_offset
; /* offset to save FP regs from initial SP */
112 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
113 int lr_save_offset
; /* offset to save LR from initial SP */
114 int cr_save_offset
; /* offset to save CR from initial SP */
115 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
116 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
117 int varargs_save_offset
; /* offset to save the varargs registers */
118 int ehrd_offset
; /* offset to EH return data */
119 int ehcr_offset
; /* offset to EH CR field data */
120 int reg_size
; /* register size (4 or 8) */
121 HOST_WIDE_INT vars_size
; /* variable save area size */
122 int parm_size
; /* outgoing parameter size */
123 int save_size
; /* save area size */
124 int fixed_size
; /* fixed size of stack frame */
125 int gp_size
; /* size of saved GP registers */
126 int fp_size
; /* size of saved FP registers */
127 int altivec_size
; /* size of saved AltiVec registers */
128 int cr_size
; /* size to hold CR if not in save_size */
129 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
130 int altivec_padding_size
; /* size of altivec alignment padding if
132 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
133 int spe_padding_size
;
134 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
135 int spe_64bit_regs_used
;
139 /* A C structure for machine-specific, per-function data.
140 This is added to the cfun structure. */
141 typedef struct GTY(()) machine_function
143 /* Some local-dynamic symbol. */
144 const char *some_ld_name
;
145 /* Whether the instruction chain has been scanned already. */
146 int insn_chain_scanned_p
;
147 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
148 int ra_needs_full_frame
;
149 /* Flags if __builtin_return_address (0) was used. */
151 /* Cache lr_save_p after expansion of builtin_eh_return. */
153 /* Whether we need to save the TOC to the reserved stack location in the
154 function prologue. */
155 bool save_toc_in_prologue
;
156 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
157 varargs save area. */
158 HOST_WIDE_INT varargs_save_offset
;
159 /* Temporary stack slot to use for SDmode copies. This slot is
160 64-bits wide and is allocated early enough so that the offset
161 does not overflow the 16-bit load/store offset field. */
162 rtx sdmode_stack_slot
;
163 /* Flag if r2 setup is needed with ELFv2 ABI. */
164 bool r2_setup_needed
;
167 /* Support targetm.vectorize.builtin_mask_for_load. */
168 static GTY(()) tree altivec_builtin_mask_for_load
;
170 /* Set to nonzero once AIX common-mode calls have been defined. */
171 static GTY(()) int common_mode_defined
;
173 /* Label number of label created for -mrelocatable, to call to so we can
174 get the address of the GOT section */
175 static int rs6000_pic_labelno
;
178 /* Counter for labels which are to be placed in .fixup. */
179 int fixuplabelno
= 0;
182 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
185 /* Specify the machine mode that pointers have. After generation of rtl, the
186 compiler makes no further distinction between pointers and any other objects
187 of this machine mode. The type is unsigned since not all things that
188 include rs6000.h also include machmode.h. */
189 unsigned rs6000_pmode
;
191 /* Width in bits of a pointer. */
192 unsigned rs6000_pointer_size
;
194 #ifdef HAVE_AS_GNU_ATTRIBUTE
195 /* Flag whether floating point values have been passed/returned. */
196 static bool rs6000_passes_float
;
197 /* Flag whether vector values have been passed/returned. */
198 static bool rs6000_passes_vector
;
199 /* Flag whether small (<= 8 byte) structures have been returned. */
200 static bool rs6000_returns_struct
;
203 /* Value is TRUE if register/mode pair is acceptable. */
204 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
206 /* Maximum number of registers needed for a given register class and mode. */
207 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
209 /* How many registers are needed for a given register and mode. */
210 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
212 /* Map register number to register class. */
213 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
215 static int dbg_cost_ctrl
;
217 /* Built in types. */
218 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
219 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
221 /* Flag to say the TOC is initialized */
223 char toc_label_name
[10];
225 /* Cached value of rs6000_variable_issue. This is cached in
226 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
227 static short cached_can_issue_more
;
229 static GTY(()) section
*read_only_data_section
;
230 static GTY(()) section
*private_data_section
;
231 static GTY(()) section
*tls_data_section
;
232 static GTY(()) section
*tls_private_data_section
;
233 static GTY(()) section
*read_only_private_data_section
;
234 static GTY(()) section
*sdata2_section
;
235 static GTY(()) section
*toc_section
;
237 struct builtin_description
239 const HOST_WIDE_INT mask
;
240 const enum insn_code icode
;
241 const char *const name
;
242 const enum rs6000_builtins code
;
245 /* Describe the vector unit used for modes. */
246 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
247 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
249 /* Register classes for various constraints that are based on the target
251 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
253 /* Describe the alignment of a vector. */
254 int rs6000_vector_align
[NUM_MACHINE_MODES
];
256 /* Map selected modes to types for builtins. */
257 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
259 /* What modes to automatically generate reciprocal divide estimate (fre) and
260 reciprocal sqrt (frsqrte) for. */
261 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
263 /* Masks to determine which reciprocal esitmate instructions to generate
265 enum rs6000_recip_mask
{
266 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
267 RECIP_DF_DIV
= 0x002,
268 RECIP_V4SF_DIV
= 0x004,
269 RECIP_V2DF_DIV
= 0x008,
271 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
272 RECIP_DF_RSQRT
= 0x020,
273 RECIP_V4SF_RSQRT
= 0x040,
274 RECIP_V2DF_RSQRT
= 0x080,
276 /* Various combination of flags for -mrecip=xxx. */
278 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
279 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
280 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
282 RECIP_HIGH_PRECISION
= RECIP_ALL
,
284 /* On low precision machines like the power5, don't enable double precision
285 reciprocal square root estimate, since it isn't accurate enough. */
286 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
289 /* -mrecip options. */
292 const char *string
; /* option name */
293 unsigned int mask
; /* mask bits to set */
294 } recip_options
[] = {
295 { "all", RECIP_ALL
},
296 { "none", RECIP_NONE
},
297 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
299 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
300 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
301 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
302 | RECIP_V2DF_RSQRT
) },
303 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
304 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
307 /* Pointer to function (in rs6000-c.c) that can define or undefine target
308 macros that have changed. Languages that don't support the preprocessor
309 don't link in rs6000-c.c, so we can't call it directly. */
310 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
312 /* Simplfy register classes into simpler classifications. We assume
313 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
314 check for standard register classes (gpr/floating/altivec/vsx) and
315 floating/vector classes (float/altivec/vsx). */
317 enum rs6000_reg_type
{
330 /* Map register class to register type. */
331 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
333 /* First/last register type for the 'normal' register types (i.e. general
334 purpose, floating point, altivec, and VSX registers). */
335 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
337 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
340 /* Register classes we care about in secondary reload or go if legitimate
341 address. We only need to worry about GPR, FPR, and Altivec registers here,
342 along an ANY field that is the OR of the 3 register classes. */
344 enum rs6000_reload_reg_type
{
345 RELOAD_REG_GPR
, /* General purpose registers. */
346 RELOAD_REG_FPR
, /* Traditional floating point regs. */
347 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
348 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
352 /* For setting up register classes, loop through the 3 register classes mapping
353 into real registers, and skip the ANY class, which is just an OR of the
355 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
356 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
358 /* Map reload register type to a register in the register class. */
359 struct reload_reg_map_type
{
360 const char *name
; /* Register class name. */
361 int reg
; /* Register in the register class. */
364 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
365 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
366 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
367 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
368 { "Any", -1 }, /* RELOAD_REG_ANY. */
371 /* Mask bits for each register class, indexed per mode. Historically the
372 compiler has been more restrictive which types can do PRE_MODIFY instead of
373 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
374 typedef unsigned char addr_mask_type
;
376 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
377 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
378 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
379 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
380 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
381 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
383 /* Register type masks based on the type, of valid addressing modes. */
384 struct rs6000_reg_addr
{
385 enum insn_code reload_load
; /* INSN to reload for loading. */
386 enum insn_code reload_store
; /* INSN to reload for storing. */
387 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
388 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
389 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
390 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
393 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
395 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
397 mode_supports_pre_incdec_p (enum machine_mode mode
)
399 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
403 /* Helper function to say whether a mode supports PRE_MODIFY. */
405 mode_supports_pre_modify_p (enum machine_mode mode
)
407 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
412 /* Target cpu costs. */
414 struct processor_costs
{
415 const int mulsi
; /* cost of SImode multiplication. */
416 const int mulsi_const
; /* cost of SImode multiplication by constant. */
417 const int mulsi_const9
; /* cost of SImode mult by short constant. */
418 const int muldi
; /* cost of DImode multiplication. */
419 const int divsi
; /* cost of SImode division. */
420 const int divdi
; /* cost of DImode division. */
421 const int fp
; /* cost of simple SFmode and DFmode insns. */
422 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
423 const int sdiv
; /* cost of SFmode division (fdivs). */
424 const int ddiv
; /* cost of DFmode division (fdiv). */
425 const int cache_line_size
; /* cache line size in bytes. */
426 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
427 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
428 const int simultaneous_prefetches
; /* number of parallel prefetch
432 const struct processor_costs
*rs6000_cost
;
434 /* Processor costs (relative to an add) */
436 /* Instruction size costs on 32bit processors. */
438 struct processor_costs size32_cost
= {
439 COSTS_N_INSNS (1), /* mulsi */
440 COSTS_N_INSNS (1), /* mulsi_const */
441 COSTS_N_INSNS (1), /* mulsi_const9 */
442 COSTS_N_INSNS (1), /* muldi */
443 COSTS_N_INSNS (1), /* divsi */
444 COSTS_N_INSNS (1), /* divdi */
445 COSTS_N_INSNS (1), /* fp */
446 COSTS_N_INSNS (1), /* dmul */
447 COSTS_N_INSNS (1), /* sdiv */
448 COSTS_N_INSNS (1), /* ddiv */
455 /* Instruction size costs on 64bit processors. */
457 struct processor_costs size64_cost
= {
458 COSTS_N_INSNS (1), /* mulsi */
459 COSTS_N_INSNS (1), /* mulsi_const */
460 COSTS_N_INSNS (1), /* mulsi_const9 */
461 COSTS_N_INSNS (1), /* muldi */
462 COSTS_N_INSNS (1), /* divsi */
463 COSTS_N_INSNS (1), /* divdi */
464 COSTS_N_INSNS (1), /* fp */
465 COSTS_N_INSNS (1), /* dmul */
466 COSTS_N_INSNS (1), /* sdiv */
467 COSTS_N_INSNS (1), /* ddiv */
474 /* Instruction costs on RS64A processors. */
476 struct processor_costs rs64a_cost
= {
477 COSTS_N_INSNS (20), /* mulsi */
478 COSTS_N_INSNS (12), /* mulsi_const */
479 COSTS_N_INSNS (8), /* mulsi_const9 */
480 COSTS_N_INSNS (34), /* muldi */
481 COSTS_N_INSNS (65), /* divsi */
482 COSTS_N_INSNS (67), /* divdi */
483 COSTS_N_INSNS (4), /* fp */
484 COSTS_N_INSNS (4), /* dmul */
485 COSTS_N_INSNS (31), /* sdiv */
486 COSTS_N_INSNS (31), /* ddiv */
487 128, /* cache line size */
493 /* Instruction costs on MPCCORE processors. */
495 struct processor_costs mpccore_cost
= {
496 COSTS_N_INSNS (2), /* mulsi */
497 COSTS_N_INSNS (2), /* mulsi_const */
498 COSTS_N_INSNS (2), /* mulsi_const9 */
499 COSTS_N_INSNS (2), /* muldi */
500 COSTS_N_INSNS (6), /* divsi */
501 COSTS_N_INSNS (6), /* divdi */
502 COSTS_N_INSNS (4), /* fp */
503 COSTS_N_INSNS (5), /* dmul */
504 COSTS_N_INSNS (10), /* sdiv */
505 COSTS_N_INSNS (17), /* ddiv */
506 32, /* cache line size */
512 /* Instruction costs on PPC403 processors. */
514 struct processor_costs ppc403_cost
= {
515 COSTS_N_INSNS (4), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (4), /* mulsi_const9 */
518 COSTS_N_INSNS (4), /* muldi */
519 COSTS_N_INSNS (33), /* divsi */
520 COSTS_N_INSNS (33), /* divdi */
521 COSTS_N_INSNS (11), /* fp */
522 COSTS_N_INSNS (11), /* dmul */
523 COSTS_N_INSNS (11), /* sdiv */
524 COSTS_N_INSNS (11), /* ddiv */
525 32, /* cache line size */
531 /* Instruction costs on PPC405 processors. */
533 struct processor_costs ppc405_cost
= {
534 COSTS_N_INSNS (5), /* mulsi */
535 COSTS_N_INSNS (4), /* mulsi_const */
536 COSTS_N_INSNS (3), /* mulsi_const9 */
537 COSTS_N_INSNS (5), /* muldi */
538 COSTS_N_INSNS (35), /* divsi */
539 COSTS_N_INSNS (35), /* divdi */
540 COSTS_N_INSNS (11), /* fp */
541 COSTS_N_INSNS (11), /* dmul */
542 COSTS_N_INSNS (11), /* sdiv */
543 COSTS_N_INSNS (11), /* ddiv */
544 32, /* cache line size */
550 /* Instruction costs on PPC440 processors. */
552 struct processor_costs ppc440_cost
= {
553 COSTS_N_INSNS (3), /* mulsi */
554 COSTS_N_INSNS (2), /* mulsi_const */
555 COSTS_N_INSNS (2), /* mulsi_const9 */
556 COSTS_N_INSNS (3), /* muldi */
557 COSTS_N_INSNS (34), /* divsi */
558 COSTS_N_INSNS (34), /* divdi */
559 COSTS_N_INSNS (5), /* fp */
560 COSTS_N_INSNS (5), /* dmul */
561 COSTS_N_INSNS (19), /* sdiv */
562 COSTS_N_INSNS (33), /* ddiv */
563 32, /* cache line size */
569 /* Instruction costs on PPC476 processors. */
571 struct processor_costs ppc476_cost
= {
572 COSTS_N_INSNS (4), /* mulsi */
573 COSTS_N_INSNS (4), /* mulsi_const */
574 COSTS_N_INSNS (4), /* mulsi_const9 */
575 COSTS_N_INSNS (4), /* muldi */
576 COSTS_N_INSNS (11), /* divsi */
577 COSTS_N_INSNS (11), /* divdi */
578 COSTS_N_INSNS (6), /* fp */
579 COSTS_N_INSNS (6), /* dmul */
580 COSTS_N_INSNS (19), /* sdiv */
581 COSTS_N_INSNS (33), /* ddiv */
582 32, /* l1 cache line size */
588 /* Instruction costs on PPC601 processors. */
590 struct processor_costs ppc601_cost
= {
591 COSTS_N_INSNS (5), /* mulsi */
592 COSTS_N_INSNS (5), /* mulsi_const */
593 COSTS_N_INSNS (5), /* mulsi_const9 */
594 COSTS_N_INSNS (5), /* muldi */
595 COSTS_N_INSNS (36), /* divsi */
596 COSTS_N_INSNS (36), /* divdi */
597 COSTS_N_INSNS (4), /* fp */
598 COSTS_N_INSNS (5), /* dmul */
599 COSTS_N_INSNS (17), /* sdiv */
600 COSTS_N_INSNS (31), /* ddiv */
601 32, /* cache line size */
607 /* Instruction costs on PPC603 processors. */
609 struct processor_costs ppc603_cost
= {
610 COSTS_N_INSNS (5), /* mulsi */
611 COSTS_N_INSNS (3), /* mulsi_const */
612 COSTS_N_INSNS (2), /* mulsi_const9 */
613 COSTS_N_INSNS (5), /* muldi */
614 COSTS_N_INSNS (37), /* divsi */
615 COSTS_N_INSNS (37), /* divdi */
616 COSTS_N_INSNS (3), /* fp */
617 COSTS_N_INSNS (4), /* dmul */
618 COSTS_N_INSNS (18), /* sdiv */
619 COSTS_N_INSNS (33), /* ddiv */
620 32, /* cache line size */
626 /* Instruction costs on PPC604 processors. */
628 struct processor_costs ppc604_cost
= {
629 COSTS_N_INSNS (4), /* mulsi */
630 COSTS_N_INSNS (4), /* mulsi_const */
631 COSTS_N_INSNS (4), /* mulsi_const9 */
632 COSTS_N_INSNS (4), /* muldi */
633 COSTS_N_INSNS (20), /* divsi */
634 COSTS_N_INSNS (20), /* divdi */
635 COSTS_N_INSNS (3), /* fp */
636 COSTS_N_INSNS (3), /* dmul */
637 COSTS_N_INSNS (18), /* sdiv */
638 COSTS_N_INSNS (32), /* ddiv */
639 32, /* cache line size */
645 /* Instruction costs on PPC604e processors. */
647 struct processor_costs ppc604e_cost
= {
648 COSTS_N_INSNS (2), /* mulsi */
649 COSTS_N_INSNS (2), /* mulsi_const */
650 COSTS_N_INSNS (2), /* mulsi_const9 */
651 COSTS_N_INSNS (2), /* muldi */
652 COSTS_N_INSNS (20), /* divsi */
653 COSTS_N_INSNS (20), /* divdi */
654 COSTS_N_INSNS (3), /* fp */
655 COSTS_N_INSNS (3), /* dmul */
656 COSTS_N_INSNS (18), /* sdiv */
657 COSTS_N_INSNS (32), /* ddiv */
658 32, /* cache line size */
664 /* Instruction costs on PPC620 processors. */
666 struct processor_costs ppc620_cost
= {
667 COSTS_N_INSNS (5), /* mulsi */
668 COSTS_N_INSNS (4), /* mulsi_const */
669 COSTS_N_INSNS (3), /* mulsi_const9 */
670 COSTS_N_INSNS (7), /* muldi */
671 COSTS_N_INSNS (21), /* divsi */
672 COSTS_N_INSNS (37), /* divdi */
673 COSTS_N_INSNS (3), /* fp */
674 COSTS_N_INSNS (3), /* dmul */
675 COSTS_N_INSNS (18), /* sdiv */
676 COSTS_N_INSNS (32), /* ddiv */
677 128, /* cache line size */
683 /* Instruction costs on PPC630 processors. */
685 struct processor_costs ppc630_cost
= {
686 COSTS_N_INSNS (5), /* mulsi */
687 COSTS_N_INSNS (4), /* mulsi_const */
688 COSTS_N_INSNS (3), /* mulsi_const9 */
689 COSTS_N_INSNS (7), /* muldi */
690 COSTS_N_INSNS (21), /* divsi */
691 COSTS_N_INSNS (37), /* divdi */
692 COSTS_N_INSNS (3), /* fp */
693 COSTS_N_INSNS (3), /* dmul */
694 COSTS_N_INSNS (17), /* sdiv */
695 COSTS_N_INSNS (21), /* ddiv */
696 128, /* cache line size */
702 /* Instruction costs on Cell processor. */
703 /* COSTS_N_INSNS (1) ~ one add. */
705 struct processor_costs ppccell_cost
= {
706 COSTS_N_INSNS (9/2)+2, /* mulsi */
707 COSTS_N_INSNS (6/2), /* mulsi_const */
708 COSTS_N_INSNS (6/2), /* mulsi_const9 */
709 COSTS_N_INSNS (15/2)+2, /* muldi */
710 COSTS_N_INSNS (38/2), /* divsi */
711 COSTS_N_INSNS (70/2), /* divdi */
712 COSTS_N_INSNS (10/2), /* fp */
713 COSTS_N_INSNS (10/2), /* dmul */
714 COSTS_N_INSNS (74/2), /* sdiv */
715 COSTS_N_INSNS (74/2), /* ddiv */
716 128, /* cache line size */
722 /* Instruction costs on PPC750 and PPC7400 processors. */
724 struct processor_costs ppc750_cost
= {
725 COSTS_N_INSNS (5), /* mulsi */
726 COSTS_N_INSNS (3), /* mulsi_const */
727 COSTS_N_INSNS (2), /* mulsi_const9 */
728 COSTS_N_INSNS (5), /* muldi */
729 COSTS_N_INSNS (17), /* divsi */
730 COSTS_N_INSNS (17), /* divdi */
731 COSTS_N_INSNS (3), /* fp */
732 COSTS_N_INSNS (3), /* dmul */
733 COSTS_N_INSNS (17), /* sdiv */
734 COSTS_N_INSNS (31), /* ddiv */
735 32, /* cache line size */
741 /* Instruction costs on PPC7450 processors. */
743 struct processor_costs ppc7450_cost
= {
744 COSTS_N_INSNS (4), /* mulsi */
745 COSTS_N_INSNS (3), /* mulsi_const */
746 COSTS_N_INSNS (3), /* mulsi_const9 */
747 COSTS_N_INSNS (4), /* muldi */
748 COSTS_N_INSNS (23), /* divsi */
749 COSTS_N_INSNS (23), /* divdi */
750 COSTS_N_INSNS (5), /* fp */
751 COSTS_N_INSNS (5), /* dmul */
752 COSTS_N_INSNS (21), /* sdiv */
753 COSTS_N_INSNS (35), /* ddiv */
754 32, /* cache line size */
760 /* Instruction costs on PPC8540 processors. */
762 struct processor_costs ppc8540_cost
= {
763 COSTS_N_INSNS (4), /* mulsi */
764 COSTS_N_INSNS (4), /* mulsi_const */
765 COSTS_N_INSNS (4), /* mulsi_const9 */
766 COSTS_N_INSNS (4), /* muldi */
767 COSTS_N_INSNS (19), /* divsi */
768 COSTS_N_INSNS (19), /* divdi */
769 COSTS_N_INSNS (4), /* fp */
770 COSTS_N_INSNS (4), /* dmul */
771 COSTS_N_INSNS (29), /* sdiv */
772 COSTS_N_INSNS (29), /* ddiv */
773 32, /* cache line size */
776 1, /* prefetch streams /*/
779 /* Instruction costs on E300C2 and E300C3 cores. */
781 struct processor_costs ppce300c2c3_cost
= {
782 COSTS_N_INSNS (4), /* mulsi */
783 COSTS_N_INSNS (4), /* mulsi_const */
784 COSTS_N_INSNS (4), /* mulsi_const9 */
785 COSTS_N_INSNS (4), /* muldi */
786 COSTS_N_INSNS (19), /* divsi */
787 COSTS_N_INSNS (19), /* divdi */
788 COSTS_N_INSNS (3), /* fp */
789 COSTS_N_INSNS (4), /* dmul */
790 COSTS_N_INSNS (18), /* sdiv */
791 COSTS_N_INSNS (33), /* ddiv */
795 1, /* prefetch streams /*/
798 /* Instruction costs on PPCE500MC processors. */
800 struct processor_costs ppce500mc_cost
= {
801 COSTS_N_INSNS (4), /* mulsi */
802 COSTS_N_INSNS (4), /* mulsi_const */
803 COSTS_N_INSNS (4), /* mulsi_const9 */
804 COSTS_N_INSNS (4), /* muldi */
805 COSTS_N_INSNS (14), /* divsi */
806 COSTS_N_INSNS (14), /* divdi */
807 COSTS_N_INSNS (8), /* fp */
808 COSTS_N_INSNS (10), /* dmul */
809 COSTS_N_INSNS (36), /* sdiv */
810 COSTS_N_INSNS (66), /* ddiv */
811 64, /* cache line size */
814 1, /* prefetch streams /*/
817 /* Instruction costs on PPCE500MC64 processors. */
819 struct processor_costs ppce500mc64_cost
= {
820 COSTS_N_INSNS (4), /* mulsi */
821 COSTS_N_INSNS (4), /* mulsi_const */
822 COSTS_N_INSNS (4), /* mulsi_const9 */
823 COSTS_N_INSNS (4), /* muldi */
824 COSTS_N_INSNS (14), /* divsi */
825 COSTS_N_INSNS (14), /* divdi */
826 COSTS_N_INSNS (4), /* fp */
827 COSTS_N_INSNS (10), /* dmul */
828 COSTS_N_INSNS (36), /* sdiv */
829 COSTS_N_INSNS (66), /* ddiv */
830 64, /* cache line size */
833 1, /* prefetch streams /*/
836 /* Instruction costs on PPCE5500 processors. */
838 struct processor_costs ppce5500_cost
= {
839 COSTS_N_INSNS (5), /* mulsi */
840 COSTS_N_INSNS (5), /* mulsi_const */
841 COSTS_N_INSNS (4), /* mulsi_const9 */
842 COSTS_N_INSNS (5), /* muldi */
843 COSTS_N_INSNS (14), /* divsi */
844 COSTS_N_INSNS (14), /* divdi */
845 COSTS_N_INSNS (7), /* fp */
846 COSTS_N_INSNS (10), /* dmul */
847 COSTS_N_INSNS (36), /* sdiv */
848 COSTS_N_INSNS (66), /* ddiv */
849 64, /* cache line size */
852 1, /* prefetch streams /*/
855 /* Instruction costs on PPCE6500 processors. */
857 struct processor_costs ppce6500_cost
= {
858 COSTS_N_INSNS (5), /* mulsi */
859 COSTS_N_INSNS (5), /* mulsi_const */
860 COSTS_N_INSNS (4), /* mulsi_const9 */
861 COSTS_N_INSNS (5), /* muldi */
862 COSTS_N_INSNS (14), /* divsi */
863 COSTS_N_INSNS (14), /* divdi */
864 COSTS_N_INSNS (7), /* fp */
865 COSTS_N_INSNS (10), /* dmul */
866 COSTS_N_INSNS (36), /* sdiv */
867 COSTS_N_INSNS (66), /* ddiv */
868 64, /* cache line size */
871 1, /* prefetch streams /*/
874 /* Instruction costs on AppliedMicro Titan processors. */
876 struct processor_costs titan_cost
= {
877 COSTS_N_INSNS (5), /* mulsi */
878 COSTS_N_INSNS (5), /* mulsi_const */
879 COSTS_N_INSNS (5), /* mulsi_const9 */
880 COSTS_N_INSNS (5), /* muldi */
881 COSTS_N_INSNS (18), /* divsi */
882 COSTS_N_INSNS (18), /* divdi */
883 COSTS_N_INSNS (10), /* fp */
884 COSTS_N_INSNS (10), /* dmul */
885 COSTS_N_INSNS (46), /* sdiv */
886 COSTS_N_INSNS (72), /* ddiv */
887 32, /* cache line size */
890 1, /* prefetch streams /*/
893 /* Instruction costs on POWER4 and POWER5 processors. */
895 struct processor_costs power4_cost
= {
896 COSTS_N_INSNS (3), /* mulsi */
897 COSTS_N_INSNS (2), /* mulsi_const */
898 COSTS_N_INSNS (2), /* mulsi_const9 */
899 COSTS_N_INSNS (4), /* muldi */
900 COSTS_N_INSNS (18), /* divsi */
901 COSTS_N_INSNS (34), /* divdi */
902 COSTS_N_INSNS (3), /* fp */
903 COSTS_N_INSNS (3), /* dmul */
904 COSTS_N_INSNS (17), /* sdiv */
905 COSTS_N_INSNS (17), /* ddiv */
906 128, /* cache line size */
909 8, /* prefetch streams /*/
912 /* Instruction costs on POWER6 processors. */
914 struct processor_costs power6_cost
= {
915 COSTS_N_INSNS (8), /* mulsi */
916 COSTS_N_INSNS (8), /* mulsi_const */
917 COSTS_N_INSNS (8), /* mulsi_const9 */
918 COSTS_N_INSNS (8), /* muldi */
919 COSTS_N_INSNS (22), /* divsi */
920 COSTS_N_INSNS (28), /* divdi */
921 COSTS_N_INSNS (3), /* fp */
922 COSTS_N_INSNS (3), /* dmul */
923 COSTS_N_INSNS (13), /* sdiv */
924 COSTS_N_INSNS (16), /* ddiv */
925 128, /* cache line size */
928 16, /* prefetch streams */
931 /* Instruction costs on POWER7 processors. */
933 struct processor_costs power7_cost
= {
934 COSTS_N_INSNS (2), /* mulsi */
935 COSTS_N_INSNS (2), /* mulsi_const */
936 COSTS_N_INSNS (2), /* mulsi_const9 */
937 COSTS_N_INSNS (2), /* muldi */
938 COSTS_N_INSNS (18), /* divsi */
939 COSTS_N_INSNS (34), /* divdi */
940 COSTS_N_INSNS (3), /* fp */
941 COSTS_N_INSNS (3), /* dmul */
942 COSTS_N_INSNS (13), /* sdiv */
943 COSTS_N_INSNS (16), /* ddiv */
944 128, /* cache line size */
947 12, /* prefetch streams */
950 /* Instruction costs on POWER8 processors. */
952 struct processor_costs power8_cost
= {
953 COSTS_N_INSNS (3), /* mulsi */
954 COSTS_N_INSNS (3), /* mulsi_const */
955 COSTS_N_INSNS (3), /* mulsi_const9 */
956 COSTS_N_INSNS (3), /* muldi */
957 COSTS_N_INSNS (19), /* divsi */
958 COSTS_N_INSNS (35), /* divdi */
959 COSTS_N_INSNS (3), /* fp */
960 COSTS_N_INSNS (3), /* dmul */
961 COSTS_N_INSNS (14), /* sdiv */
962 COSTS_N_INSNS (17), /* ddiv */
963 128, /* cache line size */
966 12, /* prefetch streams */
969 /* Instruction costs on POWER A2 processors. */
971 struct processor_costs ppca2_cost
= {
972 COSTS_N_INSNS (16), /* mulsi */
973 COSTS_N_INSNS (16), /* mulsi_const */
974 COSTS_N_INSNS (16), /* mulsi_const9 */
975 COSTS_N_INSNS (16), /* muldi */
976 COSTS_N_INSNS (22), /* divsi */
977 COSTS_N_INSNS (28), /* divdi */
978 COSTS_N_INSNS (3), /* fp */
979 COSTS_N_INSNS (3), /* dmul */
980 COSTS_N_INSNS (59), /* sdiv */
981 COSTS_N_INSNS (72), /* ddiv */
985 16, /* prefetch streams */
989 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
990 #undef RS6000_BUILTIN_1
991 #undef RS6000_BUILTIN_2
992 #undef RS6000_BUILTIN_3
993 #undef RS6000_BUILTIN_A
994 #undef RS6000_BUILTIN_D
995 #undef RS6000_BUILTIN_E
996 #undef RS6000_BUILTIN_H
997 #undef RS6000_BUILTIN_P
998 #undef RS6000_BUILTIN_Q
999 #undef RS6000_BUILTIN_S
1000 #undef RS6000_BUILTIN_X
1002 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1003 { NAME, ICODE, MASK, ATTR },
1005 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1006 { NAME, ICODE, MASK, ATTR },
1008 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1009 { NAME, ICODE, MASK, ATTR },
1011 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1012 { NAME, ICODE, MASK, ATTR },
1014 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1015 { NAME, ICODE, MASK, ATTR },
1017 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1018 { NAME, ICODE, MASK, ATTR },
1020 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1021 { NAME, ICODE, MASK, ATTR },
1023 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1024 { NAME, ICODE, MASK, ATTR },
1026 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1027 { NAME, ICODE, MASK, ATTR },
1029 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1030 { NAME, ICODE, MASK, ATTR },
1032 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1033 { NAME, ICODE, MASK, ATTR },
1035 struct rs6000_builtin_info_type
{
1037 const enum insn_code icode
;
1038 const HOST_WIDE_INT mask
;
1039 const unsigned attr
;
1042 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1044 #include "rs6000-builtin.def"
1047 #undef RS6000_BUILTIN_1
1048 #undef RS6000_BUILTIN_2
1049 #undef RS6000_BUILTIN_3
1050 #undef RS6000_BUILTIN_A
1051 #undef RS6000_BUILTIN_D
1052 #undef RS6000_BUILTIN_E
1053 #undef RS6000_BUILTIN_H
1054 #undef RS6000_BUILTIN_P
1055 #undef RS6000_BUILTIN_Q
1056 #undef RS6000_BUILTIN_S
1057 #undef RS6000_BUILTIN_X
1059 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1060 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
1063 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
1064 static bool spe_func_has_64bit_regs_p (void);
1065 static struct machine_function
* rs6000_init_machine_status (void);
1066 static int rs6000_ra_ever_killed (void);
1067 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1068 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1069 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1070 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
1071 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
1072 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
1073 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
1074 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
1076 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
1077 static bool is_microcoded_insn (rtx
);
1078 static bool is_nonpipeline_insn (rtx
);
1079 static bool is_cracked_insn (rtx
);
1080 static bool is_load_insn (rtx
, rtx
*);
1081 static bool is_store_insn (rtx
, rtx
*);
1082 static bool set_to_load_agen (rtx
,rtx
);
1083 static bool insn_terminates_group_p (rtx
, enum group_termination
);
1084 static bool insn_must_be_first_in_group (rtx
);
1085 static bool insn_must_be_last_in_group (rtx
);
1086 static void altivec_init_builtins (void);
1087 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1088 enum machine_mode
, enum machine_mode
,
1089 enum rs6000_builtins
, const char *name
);
1090 static void rs6000_common_init_builtins (void);
1091 static void paired_init_builtins (void);
1092 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1093 static void spe_init_builtins (void);
1094 static void htm_init_builtins (void);
1095 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1096 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1097 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1098 static rs6000_stack_t
*rs6000_stack_info (void);
1099 static void is_altivec_return_reg (rtx
, void *);
1100 int easy_vector_constant (rtx
, enum machine_mode
);
1101 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1102 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1103 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
1104 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
1105 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1108 static void macho_branch_islands (void);
1110 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1112 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1114 static bool rs6000_mode_dependent_address (const_rtx
);
1115 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1116 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1117 enum machine_mode
, rtx
);
1118 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1121 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1122 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1124 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1126 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1129 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1132 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1135 static bool rs6000_save_toc_in_prologue_p (void);
1137 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1139 = rs6000_legitimize_reload_address
;
1141 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1142 = rs6000_mode_dependent_address
;
1144 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1145 enum machine_mode
, rtx
)
1146 = rs6000_secondary_reload_class
;
1148 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1149 = rs6000_preferred_reload_class
;
1151 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1153 = rs6000_secondary_memory_needed
;
1155 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1158 = rs6000_cannot_change_mode_class
;
1160 const int INSN_NOT_AVAILABLE
= -1;
1162 static void rs6000_print_isa_options (FILE *, int, const char *,
1164 static void rs6000_print_builtin_options (FILE *, int, const char *,
1167 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1168 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1169 enum rs6000_reg_type
,
1171 secondary_reload_info
*,
1174 /* Hash table stuff for keeping track of TOC entries. */
1176 struct GTY(()) toc_hash_struct
1178 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1179 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1181 enum machine_mode key_mode
;
1185 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1187 /* Hash table to keep track of the argument types for builtin functions. */
1189 struct GTY(()) builtin_hash_struct
1192 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1193 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1196 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1199 /* Default register names. */
1200 char rs6000_reg_names
[][8] =
1202 "0", "1", "2", "3", "4", "5", "6", "7",
1203 "8", "9", "10", "11", "12", "13", "14", "15",
1204 "16", "17", "18", "19", "20", "21", "22", "23",
1205 "24", "25", "26", "27", "28", "29", "30", "31",
1206 "0", "1", "2", "3", "4", "5", "6", "7",
1207 "8", "9", "10", "11", "12", "13", "14", "15",
1208 "16", "17", "18", "19", "20", "21", "22", "23",
1209 "24", "25", "26", "27", "28", "29", "30", "31",
1210 "mq", "lr", "ctr","ap",
1211 "0", "1", "2", "3", "4", "5", "6", "7",
1213 /* AltiVec registers. */
1214 "0", "1", "2", "3", "4", "5", "6", "7",
1215 "8", "9", "10", "11", "12", "13", "14", "15",
1216 "16", "17", "18", "19", "20", "21", "22", "23",
1217 "24", "25", "26", "27", "28", "29", "30", "31",
1219 /* SPE registers. */
1220 "spe_acc", "spefscr",
1221 /* Soft frame pointer. */
1223 /* HTM SPR registers. */
1224 "tfhar", "tfiar", "texasr"
1227 #ifdef TARGET_REGNAMES
1228 static const char alt_reg_names
[][8] =
1230 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1231 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1232 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1233 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1234 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1235 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1236 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1237 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1238 "mq", "lr", "ctr", "ap",
1239 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1241 /* AltiVec registers. */
1242 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1243 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1244 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1245 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1247 /* SPE registers. */
1248 "spe_acc", "spefscr",
1249 /* Soft frame pointer. */
1251 /* HTM SPR registers. */
1252 "tfhar", "tfiar", "texasr"
1256 /* Table of valid machine attributes. */
1258 static const struct attribute_spec rs6000_attribute_table
[] =
1260 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1261 affects_type_identity } */
1262 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1264 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1266 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1268 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1270 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1272 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1273 SUBTARGET_ATTRIBUTE_TABLE
,
1275 { NULL
, 0, 0, false, false, false, NULL
, false }
1278 #ifndef TARGET_PROFILE_KERNEL
1279 #define TARGET_PROFILE_KERNEL 0
1282 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1283 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1285 /* Initialize the GCC target structure. */
1286 #undef TARGET_ATTRIBUTE_TABLE
1287 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1288 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1289 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1290 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1291 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1293 #undef TARGET_ASM_ALIGNED_DI_OP
1294 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1296 /* Default unaligned ops are only provided for ELF. Find the ops needed
1297 for non-ELF systems. */
1298 #ifndef OBJECT_FORMAT_ELF
1300 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1302 #undef TARGET_ASM_UNALIGNED_HI_OP
1303 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1304 #undef TARGET_ASM_UNALIGNED_SI_OP
1305 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1306 #undef TARGET_ASM_UNALIGNED_DI_OP
1307 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1310 #undef TARGET_ASM_UNALIGNED_HI_OP
1311 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1312 #undef TARGET_ASM_UNALIGNED_SI_OP
1313 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1314 #undef TARGET_ASM_UNALIGNED_DI_OP
1315 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1316 #undef TARGET_ASM_ALIGNED_DI_OP
1317 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1321 /* This hook deals with fixups for relocatable code and DI-mode objects
1323 #undef TARGET_ASM_INTEGER
1324 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1326 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1327 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1328 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1331 #undef TARGET_SET_UP_BY_PROLOGUE
1332 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1334 #undef TARGET_HAVE_TLS
1335 #define TARGET_HAVE_TLS HAVE_AS_TLS
1337 #undef TARGET_CANNOT_FORCE_CONST_MEM
1338 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1340 #undef TARGET_DELEGITIMIZE_ADDRESS
1341 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1343 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1344 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1346 #undef TARGET_ASM_FUNCTION_PROLOGUE
1347 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1348 #undef TARGET_ASM_FUNCTION_EPILOGUE
1349 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1351 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1352 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1354 #undef TARGET_LEGITIMIZE_ADDRESS
1355 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1357 #undef TARGET_SCHED_VARIABLE_ISSUE
1358 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1360 #undef TARGET_SCHED_ISSUE_RATE
1361 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1362 #undef TARGET_SCHED_ADJUST_COST
1363 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1364 #undef TARGET_SCHED_ADJUST_PRIORITY
1365 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1366 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1367 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1368 #undef TARGET_SCHED_INIT
1369 #define TARGET_SCHED_INIT rs6000_sched_init
1370 #undef TARGET_SCHED_FINISH
1371 #define TARGET_SCHED_FINISH rs6000_sched_finish
1372 #undef TARGET_SCHED_REORDER
1373 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1374 #undef TARGET_SCHED_REORDER2
1375 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1377 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1378 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1380 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1381 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1383 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1384 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1385 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1386 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1387 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1388 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1389 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1390 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1392 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1393 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1394 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1395 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1396 rs6000_builtin_support_vector_misalignment
1397 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1398 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1399 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1400 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1401 rs6000_builtin_vectorization_cost
1402 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1403 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1404 rs6000_preferred_simd_mode
1405 #undef TARGET_VECTORIZE_INIT_COST
1406 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1407 #undef TARGET_VECTORIZE_ADD_STMT_COST
1408 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1409 #undef TARGET_VECTORIZE_FINISH_COST
1410 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1411 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1412 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1414 #undef TARGET_INIT_BUILTINS
1415 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1416 #undef TARGET_BUILTIN_DECL
1417 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1419 #undef TARGET_EXPAND_BUILTIN
1420 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1422 #undef TARGET_MANGLE_TYPE
1423 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1425 #undef TARGET_INIT_LIBFUNCS
1426 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1429 #undef TARGET_BINDS_LOCAL_P
1430 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1433 #undef TARGET_MS_BITFIELD_LAYOUT_P
1434 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1436 #undef TARGET_ASM_OUTPUT_MI_THUNK
1437 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1439 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1440 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1442 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1443 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1445 #undef TARGET_REGISTER_MOVE_COST
1446 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1447 #undef TARGET_MEMORY_MOVE_COST
1448 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1449 #undef TARGET_RTX_COSTS
1450 #define TARGET_RTX_COSTS rs6000_rtx_costs
1451 #undef TARGET_ADDRESS_COST
1452 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1454 #undef TARGET_DWARF_REGISTER_SPAN
1455 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1457 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1458 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1460 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1461 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1463 /* On rs6000, function arguments are promoted, as are function return
1465 #undef TARGET_PROMOTE_FUNCTION_MODE
1466 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1468 #undef TARGET_RETURN_IN_MEMORY
1469 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1471 #undef TARGET_RETURN_IN_MSB
1472 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1474 #undef TARGET_SETUP_INCOMING_VARARGS
1475 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1477 /* Always strict argument naming on rs6000. */
1478 #undef TARGET_STRICT_ARGUMENT_NAMING
1479 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1480 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1481 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1482 #undef TARGET_SPLIT_COMPLEX_ARG
1483 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1484 #undef TARGET_MUST_PASS_IN_STACK
1485 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1486 #undef TARGET_PASS_BY_REFERENCE
1487 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1488 #undef TARGET_ARG_PARTIAL_BYTES
1489 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1490 #undef TARGET_FUNCTION_ARG_ADVANCE
1491 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1492 #undef TARGET_FUNCTION_ARG
1493 #define TARGET_FUNCTION_ARG rs6000_function_arg
1494 #undef TARGET_FUNCTION_ARG_BOUNDARY
1495 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1497 #undef TARGET_BUILD_BUILTIN_VA_LIST
1498 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1500 #undef TARGET_EXPAND_BUILTIN_VA_START
1501 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1503 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1504 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1506 #undef TARGET_EH_RETURN_FILTER_MODE
1507 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1509 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1510 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1512 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1513 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1515 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1516 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1518 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1519 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1521 #undef TARGET_OPTION_OVERRIDE
1522 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1524 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1525 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1526 rs6000_builtin_vectorized_function
1529 #undef TARGET_STACK_PROTECT_FAIL
1530 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1533 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1534 The PowerPC architecture requires only weak consistency among
1535 processors--that is, memory accesses between processors need not be
1536 sequentially consistent and memory accesses among processors can occur
1537 in any order. The ability to order memory accesses weakly provides
1538 opportunities for more efficient use of the system bus. Unless a
1539 dependency exists, the 604e allows read operations to precede store
1541 #undef TARGET_RELAXED_ORDERING
1542 #define TARGET_RELAXED_ORDERING true
1545 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1546 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1549 /* Use a 32-bit anchor range. This leads to sequences like:
1551 addis tmp,anchor,high
1554 where tmp itself acts as an anchor, and can be shared between
1555 accesses to the same 64k page. */
1556 #undef TARGET_MIN_ANCHOR_OFFSET
1557 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1558 #undef TARGET_MAX_ANCHOR_OFFSET
1559 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1560 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1561 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1562 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1563 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1565 #undef TARGET_BUILTIN_RECIPROCAL
1566 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1568 #undef TARGET_EXPAND_TO_RTL_HOOK
1569 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1571 #undef TARGET_INSTANTIATE_DECLS
1572 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1574 #undef TARGET_SECONDARY_RELOAD
1575 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1577 #undef TARGET_LEGITIMATE_ADDRESS_P
1578 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1580 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1581 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1584 #define TARGET_LRA_P rs6000_lra_p
1586 #undef TARGET_CAN_ELIMINATE
1587 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1589 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1590 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1592 #undef TARGET_TRAMPOLINE_INIT
1593 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1595 #undef TARGET_FUNCTION_VALUE
1596 #define TARGET_FUNCTION_VALUE rs6000_function_value
1598 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1599 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1601 #undef TARGET_OPTION_SAVE
1602 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1604 #undef TARGET_OPTION_RESTORE
1605 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1607 #undef TARGET_OPTION_PRINT
1608 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1610 #undef TARGET_CAN_INLINE_P
1611 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1613 #undef TARGET_SET_CURRENT_FUNCTION
1614 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1616 #undef TARGET_LEGITIMATE_CONSTANT_P
1617 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1619 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1620 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1622 #undef TARGET_CAN_USE_DOLOOP_P
1623 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1626 /* Processor table. */
1629 const char *const name
; /* Canonical processor name. */
1630 const enum processor_type processor
; /* Processor type enum value. */
1631 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1634 static struct rs6000_ptt
const processor_target_table
[] =
1636 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1637 #include "rs6000-cpus.def"
1641 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1645 rs6000_cpu_name_lookup (const char *name
)
1651 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1652 if (! strcmp (name
, processor_target_table
[i
].name
))
1660 /* Return number of consecutive hard regs needed starting at reg REGNO
1661 to hold something of mode MODE.
1662 This is ordinarily the length in words of a value of mode MODE
1663 but can be less for certain modes in special long registers.
1665 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1666 scalar instructions. The upper 32 bits are only available to the
1669 POWER and PowerPC GPRs hold 32 bits worth;
1670 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1673 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1675 unsigned HOST_WIDE_INT reg_size
;
1677 /* TF/TD modes are special in that they always take 2 registers. */
1678 if (FP_REGNO_P (regno
))
1679 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1680 ? UNITS_PER_VSX_WORD
1681 : UNITS_PER_FP_WORD
);
1683 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1684 reg_size
= UNITS_PER_SPE_WORD
;
1686 else if (ALTIVEC_REGNO_P (regno
))
1687 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1689 /* The value returned for SCmode in the E500 double case is 2 for
1690 ABI compatibility; storing an SCmode value in a single register
1691 would require function_arg and rs6000_spe_function_arg to handle
1692 SCmode so as to pass the value correctly in a pair of
1694 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1695 && !DECIMAL_FLOAT_MODE_P (mode
))
1696 reg_size
= UNITS_PER_FP_WORD
;
1699 reg_size
= UNITS_PER_WORD
;
1701 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1704 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1707 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1709 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1711 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1712 register combinations, and use PTImode where we need to deal with quad
1713 word memory operations. Don't allow quad words in the argument or frame
1714 pointer registers, just registers 0..31. */
1715 if (mode
== PTImode
)
1716 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1717 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1718 && ((regno
& 1) == 0));
1720 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1721 implementations. Don't allow an item to be split between a FP register
1722 and an Altivec register. Allow TImode in all VSX registers if the user
1724 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1725 && (VECTOR_MEM_VSX_P (mode
)
1726 || (TARGET_VSX_SCALAR_FLOAT
&& mode
== SFmode
)
1727 || (TARGET_VSX_SCALAR_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
1728 || (TARGET_VSX_TIMODE
&& mode
== TImode
)
1729 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
1731 if (FP_REGNO_P (regno
))
1732 return FP_REGNO_P (last_regno
);
1734 if (ALTIVEC_REGNO_P (regno
))
1736 if (mode
== SFmode
&& !TARGET_UPPER_REGS_SF
)
1739 if ((mode
== DFmode
|| mode
== DImode
) && !TARGET_UPPER_REGS_DF
)
1742 return ALTIVEC_REGNO_P (last_regno
);
1746 /* The GPRs can hold any mode, but values bigger than one register
1747 cannot go past R31. */
1748 if (INT_REGNO_P (regno
))
1749 return INT_REGNO_P (last_regno
);
1751 /* The float registers (except for VSX vector modes) can only hold floating
1752 modes and DImode. */
1753 if (FP_REGNO_P (regno
))
1755 if (SCALAR_FLOAT_MODE_P (mode
)
1756 && (mode
!= TDmode
|| (regno
% 2) == 0)
1757 && FP_REGNO_P (last_regno
))
1760 if (GET_MODE_CLASS (mode
) == MODE_INT
1761 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1764 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1765 && PAIRED_VECTOR_MODE (mode
))
1771 /* The CR register can only hold CC modes. */
1772 if (CR_REGNO_P (regno
))
1773 return GET_MODE_CLASS (mode
) == MODE_CC
;
1775 if (CA_REGNO_P (regno
))
1776 return mode
== BImode
;
1778 /* AltiVec only in AldyVec registers. */
1779 if (ALTIVEC_REGNO_P (regno
))
1780 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
1781 || mode
== V1TImode
);
1783 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1784 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1787 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1788 and it must be able to fit within the register set. */
1790 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1793 /* Print interesting facts about registers. */
1795 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1799 for (r
= first_regno
; r
<= last_regno
; ++r
)
1801 const char *comma
= "";
1804 if (first_regno
== last_regno
)
1805 fprintf (stderr
, "%s:\t", reg_name
);
1807 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1810 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1811 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1815 fprintf (stderr
, ",\n\t");
1820 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1821 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1822 rs6000_hard_regno_nregs
[m
][r
]);
1824 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1829 if (call_used_regs
[r
])
1833 fprintf (stderr
, ",\n\t");
1838 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1846 fprintf (stderr
, ",\n\t");
1851 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1857 fprintf (stderr
, ",\n\t");
1861 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1862 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1867 fprintf (stderr
, ",\n\t");
1871 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1876 rs6000_debug_vector_unit (enum rs6000_vector v
)
1882 case VECTOR_NONE
: ret
= "none"; break;
1883 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1884 case VECTOR_VSX
: ret
= "vsx"; break;
1885 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1886 case VECTOR_PAIRED
: ret
= "paired"; break;
1887 case VECTOR_SPE
: ret
= "spe"; break;
1888 case VECTOR_OTHER
: ret
= "other"; break;
1889 default: ret
= "unknown"; break;
1895 /* Print the address masks in a human readble fashion. */
1897 rs6000_debug_print_mode (ssize_t m
)
1901 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
1902 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
1904 addr_mask_type mask
= reg_addr
[m
].addr_mask
[rc
];
1906 " %s: %c%c%c%c%c%c",
1907 reload_reg_map
[rc
].name
,
1908 (mask
& RELOAD_REG_VALID
) != 0 ? 'v' : ' ',
1909 (mask
& RELOAD_REG_MULTIPLE
) != 0 ? 'm' : ' ',
1910 (mask
& RELOAD_REG_INDEXED
) != 0 ? 'i' : ' ',
1911 (mask
& RELOAD_REG_OFFSET
) != 0 ? 'o' : ' ',
1912 (mask
& RELOAD_REG_PRE_INCDEC
) != 0 ? '+' : ' ',
1913 (mask
& RELOAD_REG_PRE_MODIFY
) != 0 ? '+' : ' ');
1916 if (rs6000_vector_unit
[m
] != VECTOR_NONE
1917 || rs6000_vector_mem
[m
] != VECTOR_NONE
1918 || (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
1919 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
1922 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",
1923 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
1924 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]),
1925 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
1926 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
1929 fputs ("\n", stderr
);
1932 #define DEBUG_FMT_ID "%-32s= "
1933 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1934 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1935 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1937 /* Print various interesting information with -mdebug=reg. */
1939 rs6000_debug_reg_global (void)
1941 static const char *const tf
[2] = { "false", "true" };
1942 const char *nl
= (const char *)0;
1945 char costly_num
[20];
1947 char flags_buffer
[40];
1948 const char *costly_str
;
1949 const char *nop_str
;
1950 const char *trace_str
;
1951 const char *abi_str
;
1952 const char *cmodel_str
;
1953 struct cl_target_option cl_opts
;
1955 /* Modes we want tieable information on. */
1956 static const enum machine_mode print_tieable_modes
[] = {
1992 /* Virtual regs we are interested in. */
1993 const static struct {
1994 int regno
; /* register number. */
1995 const char *name
; /* register name. */
1996 } virtual_regs
[] = {
1997 { STACK_POINTER_REGNUM
, "stack pointer:" },
1998 { TOC_REGNUM
, "toc: " },
1999 { STATIC_CHAIN_REGNUM
, "static chain: " },
2000 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2001 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2002 { ARG_POINTER_REGNUM
, "arg pointer: " },
2003 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2004 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2005 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2006 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2007 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2008 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2009 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2010 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2011 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2012 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2015 fputs ("\nHard register information:\n", stderr
);
2016 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2017 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2018 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2021 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2022 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2023 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2024 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2025 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2026 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2027 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2028 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2030 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2031 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2032 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2036 "d reg_class = %s\n"
2037 "f reg_class = %s\n"
2038 "v reg_class = %s\n"
2039 "wa reg_class = %s\n"
2040 "wd reg_class = %s\n"
2041 "wf reg_class = %s\n"
2042 "wg reg_class = %s\n"
2043 "wl reg_class = %s\n"
2044 "wm reg_class = %s\n"
2045 "wr reg_class = %s\n"
2046 "ws reg_class = %s\n"
2047 "wt reg_class = %s\n"
2048 "wu reg_class = %s\n"
2049 "wv reg_class = %s\n"
2050 "ww reg_class = %s\n"
2051 "wx reg_class = %s\n"
2052 "wy reg_class = %s\n"
2053 "wz reg_class = %s\n"
2055 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2056 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2057 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2058 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2059 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2060 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2061 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2062 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2063 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2064 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2065 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2066 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2067 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2068 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2069 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2070 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2071 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2072 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2075 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2076 rs6000_debug_print_mode (m
);
2078 fputs ("\n", stderr
);
2080 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2082 enum machine_mode mode1
= print_tieable_modes
[m1
];
2083 bool first_time
= true;
2085 nl
= (const char *)0;
2086 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2088 enum machine_mode mode2
= print_tieable_modes
[m2
];
2089 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2093 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2098 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2103 fputs ("\n", stderr
);
2109 if (rs6000_recip_control
)
2111 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2113 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2114 if (rs6000_recip_bits
[m
])
2117 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2119 (RS6000_RECIP_AUTO_RE_P (m
)
2121 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2122 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2124 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2127 fputs ("\n", stderr
);
2130 if (rs6000_cpu_index
>= 0)
2132 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2134 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2136 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2137 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2140 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2142 if (rs6000_tune_index
>= 0)
2144 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2146 = processor_target_table
[rs6000_tune_index
].target_enable
;
2148 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2149 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2152 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2154 cl_target_option_save (&cl_opts
, &global_options
);
2155 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2158 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2159 rs6000_isa_flags_explicit
);
2161 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2162 rs6000_builtin_mask
);
2164 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2166 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2167 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2169 switch (rs6000_sched_costly_dep
)
2171 case max_dep_latency
:
2172 costly_str
= "max_dep_latency";
2176 costly_str
= "no_dep_costly";
2179 case all_deps_costly
:
2180 costly_str
= "all_deps_costly";
2183 case true_store_to_load_dep_costly
:
2184 costly_str
= "true_store_to_load_dep_costly";
2187 case store_to_load_dep_costly
:
2188 costly_str
= "store_to_load_dep_costly";
2192 costly_str
= costly_num
;
2193 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2197 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2199 switch (rs6000_sched_insert_nops
)
2201 case sched_finish_regroup_exact
:
2202 nop_str
= "sched_finish_regroup_exact";
2205 case sched_finish_pad_groups
:
2206 nop_str
= "sched_finish_pad_groups";
2209 case sched_finish_none
:
2210 nop_str
= "sched_finish_none";
2215 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2219 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2221 switch (rs6000_sdata
)
2228 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2232 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2236 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2241 switch (rs6000_traceback
)
2243 case traceback_default
: trace_str
= "default"; break;
2244 case traceback_none
: trace_str
= "none"; break;
2245 case traceback_part
: trace_str
= "part"; break;
2246 case traceback_full
: trace_str
= "full"; break;
2247 default: trace_str
= "unknown"; break;
2250 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2252 switch (rs6000_current_cmodel
)
2254 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2255 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2256 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2257 default: cmodel_str
= "unknown"; break;
2260 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2262 switch (rs6000_current_abi
)
2264 case ABI_NONE
: abi_str
= "none"; break;
2265 case ABI_AIX
: abi_str
= "aix"; break;
2266 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2267 case ABI_V4
: abi_str
= "V4"; break;
2268 case ABI_DARWIN
: abi_str
= "darwin"; break;
2269 default: abi_str
= "unknown"; break;
2272 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2274 if (rs6000_altivec_abi
)
2275 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2278 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2280 if (rs6000_darwin64_abi
)
2281 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2283 if (rs6000_float_gprs
)
2284 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2286 if (TARGET_LINK_STACK
)
2287 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2289 if (targetm
.lra_p ())
2290 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2292 if (TARGET_P8_FUSION
)
2293 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2294 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2296 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2297 TARGET_SECURE_PLT
? "secure" : "bss");
2298 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2299 aix_struct_return
? "aix" : "sysv");
2300 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2301 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2302 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2303 tf
[!!rs6000_align_branch_targets
]);
2304 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2305 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2306 rs6000_long_double_type_size
);
2307 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2308 (int)rs6000_sched_restricted_insns_priority
);
2309 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2311 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2312 (int)RS6000_BUILTIN_COUNT
);
2315 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2316 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2320 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2321 legitimate address support to figure out the appropriate addressing to
2325 rs6000_setup_reg_addr_masks (void)
2327 ssize_t rc
, reg
, m
, nregs
;
2328 addr_mask_type any_addr_mask
, addr_mask
;
2330 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2332 /* SDmode is special in that we want to access it only via REG+REG
2333 addressing on power7 and above, since we want to use the LFIWZX and
2334 STFIWZX instructions to load it. */
2335 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2338 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2341 reg
= reload_reg_map
[rc
].reg
;
2343 /* Can mode values go in the GPR/FPR/Altivec registers? */
2344 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2346 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2347 addr_mask
|= RELOAD_REG_VALID
;
2349 /* Indicate if the mode takes more than 1 physical register. If
2350 it takes a single register, indicate it can do REG+REG
2352 if (nregs
> 1 || m
== BLKmode
)
2353 addr_mask
|= RELOAD_REG_MULTIPLE
;
2355 addr_mask
|= RELOAD_REG_INDEXED
;
2357 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2358 addressing. Restrict addressing on SPE for 64-bit types
2359 because of the SUBREG hackery used to address 64-bit floats in
2360 '32-bit' GPRs. To simplify secondary reload, don't allow
2361 update forms on scalar floating point types that can go in the
2365 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2366 && GET_MODE_SIZE (m
) <= 8
2367 && !VECTOR_MODE_P (m
)
2368 && !COMPLEX_MODE_P (m
)
2370 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (m
) == 8)
2371 && !(m
== DFmode
&& TARGET_UPPER_REGS_DF
)
2372 && !(m
== SFmode
&& TARGET_UPPER_REGS_SF
))
2374 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2376 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2377 we don't allow PRE_MODIFY for some multi-register
2382 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2386 if (TARGET_POWERPC64
)
2387 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2393 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2399 /* GPR and FPR registers can do REG+OFFSET addressing, except
2400 possibly for SDmode. */
2401 if ((addr_mask
!= 0) && !indexed_only_p
2402 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
))
2403 addr_mask
|= RELOAD_REG_OFFSET
;
2405 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2406 any_addr_mask
|= addr_mask
;
2409 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2414 /* Initialize the various global tables that are based on register size. */
2416 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2422 /* Precalculate REGNO_REG_CLASS. */
2423 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2424 for (r
= 1; r
< 32; ++r
)
2425 rs6000_regno_regclass
[r
] = BASE_REGS
;
2427 for (r
= 32; r
< 64; ++r
)
2428 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2430 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2431 rs6000_regno_regclass
[r
] = NO_REGS
;
2433 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2434 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2436 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2437 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2438 rs6000_regno_regclass
[r
] = CR_REGS
;
2440 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2441 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2442 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
2443 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2444 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2445 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2446 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2447 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2448 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2449 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2450 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2451 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2453 /* Precalculate register class to simpler reload register class. We don't
2454 need all of the register classes that are combinations of different
2455 classes, just the simple ones that have constraint letters. */
2456 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2457 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2459 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2460 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2461 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2462 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2463 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2464 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2465 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2466 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2467 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2468 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2469 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2470 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2474 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2475 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2479 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2480 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2483 /* Precalculate the valid memory formats as well as the vector information,
2484 this must be set up before the rs6000_hard_regno_nregs_internal calls
2486 gcc_assert ((int)VECTOR_NONE
== 0);
2487 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2488 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2490 gcc_assert ((int)CODE_FOR_nothing
== 0);
2491 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2493 gcc_assert ((int)NO_REGS
== 0);
2494 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2496 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2497 believes it can use native alignment or still uses 128-bit alignment. */
2498 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2509 /* V2DF mode, VSX only. */
2512 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2513 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2514 rs6000_vector_align
[V2DFmode
] = align64
;
2517 /* V4SF mode, either VSX or Altivec. */
2520 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2521 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2522 rs6000_vector_align
[V4SFmode
] = align32
;
2524 else if (TARGET_ALTIVEC
)
2526 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2527 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2528 rs6000_vector_align
[V4SFmode
] = align32
;
2531 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2535 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2536 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2537 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2538 rs6000_vector_align
[V4SImode
] = align32
;
2539 rs6000_vector_align
[V8HImode
] = align32
;
2540 rs6000_vector_align
[V16QImode
] = align32
;
2544 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2545 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2546 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2550 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2551 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2552 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2556 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2557 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2560 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2561 rs6000_vector_unit
[V2DImode
]
2562 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2563 rs6000_vector_align
[V2DImode
] = align64
;
2565 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
2566 rs6000_vector_unit
[V1TImode
]
2567 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2568 rs6000_vector_align
[V1TImode
] = 128;
2571 /* DFmode, see if we want to use the VSX unit. */
2572 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2574 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2575 rs6000_vector_mem
[DFmode
]
2576 = (TARGET_UPPER_REGS_DF
? VECTOR_VSX
: VECTOR_NONE
);
2577 rs6000_vector_align
[DFmode
] = align64
;
2580 /* Allow TImode in VSX register and set the VSX memory macros. */
2581 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2583 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2584 rs6000_vector_align
[TImode
] = align64
;
2587 /* TODO add SPE and paired floating point vector support. */
2589 /* Register class constraints for the constraints that depend on compile
2590 switches. When the VSX code was added, different constraints were added
2591 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2592 of the VSX registers are used. The register classes for scalar floating
2593 point types is set, based on whether we allow that type into the upper
2594 (Altivec) registers. GCC has register classes to target the Altivec
2595 registers for load/store operations, to select using a VSX memory
2596 operation instead of the traditional floating point operation. The
2599 d - Register class to use with traditional DFmode instructions.
2600 f - Register class to use with traditional SFmode instructions.
2601 v - Altivec register.
2602 wa - Any VSX register.
2603 wd - Preferred register class for V2DFmode.
2604 wf - Preferred register class for V4SFmode.
2605 wg - Float register for power6x move insns.
2606 wl - Float register if we can do 32-bit signed int loads.
2607 wm - VSX register for ISA 2.07 direct move operations.
2608 wr - GPR if 64-bit mode is permitted.
2609 ws - Register class to do ISA 2.06 DF operations.
2610 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2611 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2612 wt - VSX register for TImode in VSX registers.
2613 ww - Register class to do SF conversions in with VSX operations.
2614 wx - Float register if we can do 32-bit int stores.
2615 wy - Register class to do ISA 2.07 SF operations.
2616 wz - Float register if we can do 32-bit unsigned int loads. */
2618 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2619 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2621 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2622 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2626 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2627 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2628 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2630 if (TARGET_VSX_TIMODE
)
2631 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
;
2633 if (TARGET_UPPER_REGS_DF
)
2635 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2636 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2639 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2642 /* Add conditional constraints based on various options, to allow us to
2643 collapse multiple insn patterns. */
2645 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2648 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2651 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
;
2653 if (TARGET_DIRECT_MOVE
)
2654 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2656 if (TARGET_POWERPC64
)
2657 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2659 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
)
2661 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2662 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2663 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2665 else if (TARGET_P8_VECTOR
)
2667 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
2668 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2670 else if (TARGET_VSX
)
2671 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2674 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
;
2677 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
;
2679 /* Set up the reload helper and direct move functions. */
2680 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2684 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
2685 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
2686 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
2687 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
2688 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
2689 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
2690 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
2691 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
2692 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
2693 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
2694 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
2695 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
2696 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
2697 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
2698 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2700 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
2701 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
2702 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
2703 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
2705 if (TARGET_P8_VECTOR
)
2707 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
2708 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
2709 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
2710 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
2712 if (TARGET_VSX_TIMODE
)
2714 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
2715 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
2717 if (TARGET_DIRECT_MOVE
)
2719 if (TARGET_POWERPC64
)
2721 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
2722 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
2723 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
2724 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
2725 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
2726 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
2727 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
2728 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
2729 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
2731 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
2732 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
2733 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
2734 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
2735 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
2736 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
2737 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
2738 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
2739 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
2743 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
2744 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
2745 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
2751 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
2752 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
2753 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
2754 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
2755 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
2756 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
2757 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
2758 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
2759 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
2760 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
2761 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
2762 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
2763 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
2764 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
2765 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2767 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
2768 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
2769 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
2770 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
2772 if (TARGET_P8_VECTOR
)
2774 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
2775 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
2776 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
2777 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
2779 if (TARGET_VSX_TIMODE
)
2781 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
2782 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
2787 /* Precalculate HARD_REGNO_NREGS. */
2788 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2789 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2790 rs6000_hard_regno_nregs
[m
][r
]
2791 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2793 /* Precalculate HARD_REGNO_MODE_OK. */
2794 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2795 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2796 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2797 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2799 /* Precalculate CLASS_MAX_NREGS sizes. */
2800 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2804 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2805 reg_size
= UNITS_PER_VSX_WORD
;
2807 else if (c
== ALTIVEC_REGS
)
2808 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2810 else if (c
== FLOAT_REGS
)
2811 reg_size
= UNITS_PER_FP_WORD
;
2814 reg_size
= UNITS_PER_WORD
;
2816 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2818 int reg_size2
= reg_size
;
2820 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2821 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
)
2822 && (m
== TDmode
|| m
== TFmode
))
2823 reg_size2
= UNITS_PER_FP_WORD
;
2825 rs6000_class_max_nregs
[m
][c
]
2826 = (GET_MODE_SIZE (m
) + reg_size2
- 1) / reg_size2
;
2830 if (TARGET_E500_DOUBLE
)
2831 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2833 /* Calculate which modes to automatically generate code to use a the
2834 reciprocal divide and square root instructions. In the future, possibly
2835 automatically generate the instructions even if the user did not specify
2836 -mrecip. The older machines double precision reciprocal sqrt estimate is
2837 not accurate enough. */
2838 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2840 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2842 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2843 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2844 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2845 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2846 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2848 if (TARGET_FRSQRTES
)
2849 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2851 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2852 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2853 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2854 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2855 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2857 if (rs6000_recip_control
)
2859 if (!flag_finite_math_only
)
2860 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2861 if (flag_trapping_math
)
2862 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2863 if (!flag_reciprocal_math
)
2864 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2865 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2867 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2868 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2869 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2871 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2872 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2873 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2875 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2876 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2877 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2879 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2880 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2881 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2883 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2884 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2885 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2887 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2888 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2889 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2891 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2892 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2893 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2895 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2896 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2897 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2901 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2902 legitimate address support to figure out the appropriate addressing to
2904 rs6000_setup_reg_addr_masks ();
2906 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2908 if (TARGET_DEBUG_REG
)
2909 rs6000_debug_reg_global ();
2911 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2913 "SImode variable mult cost = %d\n"
2914 "SImode constant mult cost = %d\n"
2915 "SImode short constant mult cost = %d\n"
2916 "DImode multipliciation cost = %d\n"
2917 "SImode division cost = %d\n"
2918 "DImode division cost = %d\n"
2919 "Simple fp operation cost = %d\n"
2920 "DFmode multiplication cost = %d\n"
2921 "SFmode division cost = %d\n"
2922 "DFmode division cost = %d\n"
2923 "cache line size = %d\n"
2924 "l1 cache size = %d\n"
2925 "l2 cache size = %d\n"
2926 "simultaneous prefetches = %d\n"
2929 rs6000_cost
->mulsi_const
,
2930 rs6000_cost
->mulsi_const9
,
2938 rs6000_cost
->cache_line_size
,
2939 rs6000_cost
->l1_cache_size
,
2940 rs6000_cost
->l2_cache_size
,
2941 rs6000_cost
->simultaneous_prefetches
);
2946 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2949 darwin_rs6000_override_options (void)
2951 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2953 rs6000_altivec_abi
= 1;
2954 TARGET_ALTIVEC_VRSAVE
= 1;
2955 rs6000_current_abi
= ABI_DARWIN
;
2957 if (DEFAULT_ABI
== ABI_DARWIN
2959 darwin_one_byte_bool
= 1;
2961 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2963 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2964 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2968 rs6000_default_long_calls
= 1;
2969 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2972 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2974 if (!flag_mkernel
&& !flag_apple_kext
2976 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2977 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2979 /* Unless the user (not the configurer) has explicitly overridden
2980 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2981 G4 unless targeting the kernel. */
2984 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
2985 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
2986 && ! global_options_set
.x_rs6000_cpu_index
)
2988 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2993 /* If not otherwise specified by a target, make 'long double' equivalent to
2996 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2997 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3000 /* Return the builtin mask of the various options used that could affect which
3001 builtins were used. In the past we used target_flags, but we've run out of
3002 bits, and some options like SPE and PAIRED are no longer in
3006 rs6000_builtin_mask_calculate (void)
3008 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3009 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3010 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
3011 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
3012 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3013 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3014 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3015 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3016 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3017 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3018 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3019 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3020 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0));
3023 /* Override command line options. Mostly we process the processor type and
3024 sometimes adjust other TARGET_ options. */
3027 rs6000_option_override_internal (bool global_init_p
)
3030 bool have_cpu
= false;
3032 /* The default cpu requested at configure time, if any. */
3033 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3035 HOST_WIDE_INT set_masks
;
3038 struct cl_target_option
*main_target_opt
3039 = ((global_init_p
|| target_option_default_node
== NULL
)
3040 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3042 /* Remember the explicit arguments. */
3044 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3046 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3047 library functions, so warn about it. The flag may be useful for
3048 performance studies from time to time though, so don't disable it
3050 if (global_options_set
.x_rs6000_alignment_flags
3051 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3052 && DEFAULT_ABI
== ABI_DARWIN
3054 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3055 " it is incompatible with the installed C and C++ libraries");
3057 /* Numerous experiment shows that IRA based loop pressure
3058 calculation works better for RTL loop invariant motion on targets
3059 with enough (>= 32) registers. It is an expensive optimization.
3060 So it is on only for peak performance. */
3061 if (optimize
>= 3 && global_init_p
3062 && !global_options_set
.x_flag_ira_loop_pressure
)
3063 flag_ira_loop_pressure
= 1;
3065 /* Set the pointer size. */
3068 rs6000_pmode
= (int)DImode
;
3069 rs6000_pointer_size
= 64;
3073 rs6000_pmode
= (int)SImode
;
3074 rs6000_pointer_size
= 32;
3077 /* Some OSs don't support saving the high part of 64-bit registers on context
3078 switch. Other OSs don't support saving Altivec registers. On those OSs,
3079 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3080 if the user wants either, the user must explicitly specify them and we
3081 won't interfere with the user's specification. */
3083 set_masks
= POWERPC_MASKS
;
3084 #ifdef OS_MISSING_POWERPC64
3085 if (OS_MISSING_POWERPC64
)
3086 set_masks
&= ~OPTION_MASK_POWERPC64
;
3088 #ifdef OS_MISSING_ALTIVEC
3089 if (OS_MISSING_ALTIVEC
)
3090 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3093 /* Don't override by the processor default if given explicitly. */
3094 set_masks
&= ~rs6000_isa_flags_explicit
;
3096 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3097 the cpu in a target attribute or pragma, but did not specify a tuning
3098 option, use the cpu for the tuning option rather than the option specified
3099 with -mtune on the command line. Process a '--with-cpu' configuration
3100 request as an implicit --cpu. */
3101 if (rs6000_cpu_index
>= 0)
3103 cpu_index
= rs6000_cpu_index
;
3106 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3108 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3111 else if (implicit_cpu
)
3113 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3118 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
3119 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3123 gcc_assert (cpu_index
>= 0);
3125 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3126 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3127 with those from the cpu, except for options that were explicitly set. If
3128 we don't have a cpu, do not override the target bits set in
3132 rs6000_isa_flags
&= ~set_masks
;
3133 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3137 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3138 & ~rs6000_isa_flags_explicit
);
3140 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3141 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3142 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3143 to using rs6000_isa_flags, we need to do the initialization here. */
3145 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
3147 if (rs6000_tune_index
>= 0)
3148 tune_index
= rs6000_tune_index
;
3150 rs6000_tune_index
= tune_index
= cpu_index
;
3154 enum processor_type tune_proc
3155 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3158 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3159 if (processor_target_table
[i
].processor
== tune_proc
)
3161 rs6000_tune_index
= tune_index
= i
;
3166 gcc_assert (tune_index
>= 0);
3167 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3169 /* Pick defaults for SPE related control flags. Do this early to make sure
3170 that the TARGET_ macros are representative ASAP. */
3172 int spe_capable_cpu
=
3173 (rs6000_cpu
== PROCESSOR_PPC8540
3174 || rs6000_cpu
== PROCESSOR_PPC8548
);
3176 if (!global_options_set
.x_rs6000_spe_abi
)
3177 rs6000_spe_abi
= spe_capable_cpu
;
3179 if (!global_options_set
.x_rs6000_spe
)
3180 rs6000_spe
= spe_capable_cpu
;
3182 if (!global_options_set
.x_rs6000_float_gprs
)
3184 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3185 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3189 if (global_options_set
.x_rs6000_spe_abi
3192 error ("not configured for SPE ABI");
3194 if (global_options_set
.x_rs6000_spe
3197 error ("not configured for SPE instruction set");
3199 if (main_target_opt
!= NULL
3200 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3201 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3202 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3203 error ("target attribute or pragma changes SPE ABI");
3205 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3206 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3207 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3210 error ("AltiVec not supported in this target");
3212 error ("SPE not supported in this target");
3214 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3217 error ("SPE not supported in this target");
3220 /* Disable Cell microcode if we are optimizing for the Cell
3221 and not optimizing for size. */
3222 if (rs6000_gen_cell_microcode
== -1)
3223 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3226 /* If we are optimizing big endian systems for space and it's OK to
3227 use instructions that would be microcoded on the Cell, use the
3228 load/store multiple and string instructions. */
3229 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3230 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3231 | OPTION_MASK_STRING
);
3233 /* Don't allow -mmultiple or -mstring on little endian systems
3234 unless the cpu is a 750, because the hardware doesn't support the
3235 instructions used in little endian mode, and causes an alignment
3236 trap. The 750 does not cause an alignment trap (except when the
3237 target is unaligned). */
3239 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3241 if (TARGET_MULTIPLE
)
3243 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3244 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3245 warning (0, "-mmultiple is not supported on little endian systems");
3250 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3251 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3252 warning (0, "-mstring is not supported on little endian systems");
3256 /* If little-endian, default to -mstrict-align on older processors.
3257 Testing for htm matches power8 and later. */
3258 if (!BYTES_BIG_ENDIAN
3259 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3260 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3262 /* -maltivec={le,be} implies -maltivec. */
3263 if (rs6000_altivec_element_order
!= 0)
3264 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3266 /* Disallow -maltivec=le in big endian mode for now. This is not
3267 known to be useful for anyone. */
3268 if (BYTES_BIG_ENDIAN
&& rs6000_altivec_element_order
== 1)
3270 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
3271 rs6000_altivec_element_order
= 0;
3274 /* Add some warnings for VSX. */
3277 const char *msg
= NULL
;
3278 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3279 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3281 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3282 msg
= N_("-mvsx requires hardware floating point");
3285 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3286 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3289 else if (TARGET_PAIRED_FLOAT
)
3290 msg
= N_("-mvsx and -mpaired are incompatible");
3291 else if (TARGET_AVOID_XFORM
> 0)
3292 msg
= N_("-mvsx needs indexed addressing");
3293 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3294 & OPTION_MASK_ALTIVEC
))
3296 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3297 msg
= N_("-mvsx and -mno-altivec are incompatible");
3299 msg
= N_("-mno-altivec disables vsx");
3305 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3306 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3310 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3311 the -mcpu setting to enable options that conflict. */
3312 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3313 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3314 | OPTION_MASK_ALTIVEC
3315 | OPTION_MASK_VSX
)) != 0)
3316 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3317 | OPTION_MASK_DIRECT_MOVE
)
3318 & ~rs6000_isa_flags_explicit
);
3320 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3321 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3323 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3324 unless the user explicitly used the -mno-<option> to disable the code. */
3325 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3326 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3327 else if (TARGET_VSX
)
3328 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3329 else if (TARGET_POPCNTD
)
3330 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3331 else if (TARGET_DFP
)
3332 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3333 else if (TARGET_CMPB
)
3334 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3335 else if (TARGET_FPRND
)
3336 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3337 else if (TARGET_POPCNTB
)
3338 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3339 else if (TARGET_ALTIVEC
)
3340 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3342 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3344 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3345 error ("-mcrypto requires -maltivec");
3346 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3349 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3351 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3352 error ("-mdirect-move requires -mvsx");
3353 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3356 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3358 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3359 error ("-mpower8-vector requires -maltivec");
3360 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3363 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3365 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3366 error ("-mpower8-vector requires -mvsx");
3367 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3370 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3372 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3373 error ("-mvsx-timode requires -mvsx");
3374 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3377 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3378 silently turn off quad memory mode. */
3379 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
3381 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3382 warning (0, N_("-mquad-memory requires 64-bit mode"));
3384 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
3385 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
3387 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
3388 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
3391 /* Non-atomic quad memory load/store are disabled for little endian, since
3392 the words are reversed, but atomic operations can still be done by
3393 swapping the words. */
3394 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
3396 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3397 warning (0, N_("-mquad-memory is not available in little endian mode"));
3399 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3402 /* Assume if the user asked for normal quad memory instructions, they want
3403 the atomic versions as well, unless they explicity told us not to use quad
3404 word atomic instructions. */
3405 if (TARGET_QUAD_MEMORY
3406 && !TARGET_QUAD_MEMORY_ATOMIC
3407 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
3408 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
3410 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3411 generating power8 instructions. */
3412 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
3413 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
3414 & OPTION_MASK_P8_FUSION
);
3416 /* Power8 does not fuse sign extended loads with the addis. If we are
3417 optimizing at high levels for speed, convert a sign extended load into a
3418 zero extending load, and an explicit sign extension. */
3419 if (TARGET_P8_FUSION
3420 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
3421 && optimize_function_for_speed_p (cfun
)
3423 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
3425 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3426 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3428 /* E500mc does "better" if we inline more aggressively. Respect the
3429 user's opinion, though. */
3430 if (rs6000_block_move_inline_limit
== 0
3431 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3432 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3433 || rs6000_cpu
== PROCESSOR_PPCE5500
3434 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3435 rs6000_block_move_inline_limit
= 128;
3437 /* store_one_arg depends on expand_block_move to handle at least the
3438 size of reg_parm_stack_space. */
3439 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3440 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3444 /* If the appropriate debug option is enabled, replace the target hooks
3445 with debug versions that call the real version and then prints
3446 debugging information. */
3447 if (TARGET_DEBUG_COST
)
3449 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3450 targetm
.address_cost
= rs6000_debug_address_cost
;
3451 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3454 if (TARGET_DEBUG_ADDR
)
3456 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3457 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3458 rs6000_secondary_reload_class_ptr
3459 = rs6000_debug_secondary_reload_class
;
3460 rs6000_secondary_memory_needed_ptr
3461 = rs6000_debug_secondary_memory_needed
;
3462 rs6000_cannot_change_mode_class_ptr
3463 = rs6000_debug_cannot_change_mode_class
;
3464 rs6000_preferred_reload_class_ptr
3465 = rs6000_debug_preferred_reload_class
;
3466 rs6000_legitimize_reload_address_ptr
3467 = rs6000_debug_legitimize_reload_address
;
3468 rs6000_mode_dependent_address_ptr
3469 = rs6000_debug_mode_dependent_address
;
3472 if (rs6000_veclibabi_name
)
3474 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3475 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3478 error ("unknown vectorization library ABI type (%s) for "
3479 "-mveclibabi= switch", rs6000_veclibabi_name
);
3485 if (!global_options_set
.x_rs6000_long_double_type_size
)
3487 if (main_target_opt
!= NULL
3488 && (main_target_opt
->x_rs6000_long_double_type_size
3489 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3490 error ("target attribute or pragma changes long double size");
3492 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3495 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3496 if (!global_options_set
.x_rs6000_ieeequad
)
3497 rs6000_ieeequad
= 1;
3500 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3501 target attribute or pragma which automatically enables both options,
3502 unless the altivec ABI was set. This is set by default for 64-bit, but
3504 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3505 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3506 & ~rs6000_isa_flags_explicit
);
3508 /* Enable Altivec ABI for AIX -maltivec. */
3509 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3511 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3512 error ("target attribute or pragma changes AltiVec ABI");
3514 rs6000_altivec_abi
= 1;
3517 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3518 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3519 be explicitly overridden in either case. */
3522 if (!global_options_set
.x_rs6000_altivec_abi
3523 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3525 if (main_target_opt
!= NULL
&&
3526 !main_target_opt
->x_rs6000_altivec_abi
)
3527 error ("target attribute or pragma changes AltiVec ABI");
3529 rs6000_altivec_abi
= 1;
3533 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3534 So far, the only darwin64 targets are also MACH-O. */
3536 && DEFAULT_ABI
== ABI_DARWIN
3539 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3540 error ("target attribute or pragma changes darwin64 ABI");
3543 rs6000_darwin64_abi
= 1;
3544 /* Default to natural alignment, for better performance. */
3545 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3549 /* Place FP constants in the constant pool instead of TOC
3550 if section anchors enabled. */
3551 if (flag_section_anchors
3552 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3553 TARGET_NO_FP_IN_TOC
= 1;
3555 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3556 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3558 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3559 SUBTARGET_OVERRIDE_OPTIONS
;
3561 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3562 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3564 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3565 SUB3TARGET_OVERRIDE_OPTIONS
;
3568 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3569 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3571 /* For the E500 family of cores, reset the single/double FP flags to let us
3572 check that they remain constant across attributes or pragmas. Also,
3573 clear a possible request for string instructions, not supported and which
3574 we might have silently queried above for -Os.
3576 For other families, clear ISEL in case it was set implicitly.
3581 case PROCESSOR_PPC8540
:
3582 case PROCESSOR_PPC8548
:
3583 case PROCESSOR_PPCE500MC
:
3584 case PROCESSOR_PPCE500MC64
:
3585 case PROCESSOR_PPCE5500
:
3586 case PROCESSOR_PPCE6500
:
3588 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3589 rs6000_double_float
= TARGET_E500_DOUBLE
;
3591 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3597 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3598 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3603 if (main_target_opt
)
3605 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3606 error ("target attribute or pragma changes single precision floating "
3608 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3609 error ("target attribute or pragma changes double precision floating "
3613 /* Detect invalid option combinations with E500. */
3616 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3617 && rs6000_cpu
!= PROCESSOR_POWER5
3618 && rs6000_cpu
!= PROCESSOR_POWER6
3619 && rs6000_cpu
!= PROCESSOR_POWER7
3620 && rs6000_cpu
!= PROCESSOR_POWER8
3621 && rs6000_cpu
!= PROCESSOR_PPCA2
3622 && rs6000_cpu
!= PROCESSOR_CELL
3623 && rs6000_cpu
!= PROCESSOR_PPC476
);
3624 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3625 || rs6000_cpu
== PROCESSOR_POWER5
3626 || rs6000_cpu
== PROCESSOR_POWER7
3627 || rs6000_cpu
== PROCESSOR_POWER8
);
3628 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3629 || rs6000_cpu
== PROCESSOR_POWER5
3630 || rs6000_cpu
== PROCESSOR_POWER6
3631 || rs6000_cpu
== PROCESSOR_POWER7
3632 || rs6000_cpu
== PROCESSOR_POWER8
3633 || rs6000_cpu
== PROCESSOR_PPCE500MC
3634 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3635 || rs6000_cpu
== PROCESSOR_PPCE5500
3636 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3638 /* Allow debug switches to override the above settings. These are set to -1
3639 in rs6000.opt to indicate the user hasn't directly set the switch. */
3640 if (TARGET_ALWAYS_HINT
>= 0)
3641 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3643 if (TARGET_SCHED_GROUPS
>= 0)
3644 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3646 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3647 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3649 rs6000_sched_restricted_insns_priority
3650 = (rs6000_sched_groups
? 1 : 0);
3652 /* Handle -msched-costly-dep option. */
3653 rs6000_sched_costly_dep
3654 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3656 if (rs6000_sched_costly_dep_str
)
3658 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3659 rs6000_sched_costly_dep
= no_dep_costly
;
3660 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3661 rs6000_sched_costly_dep
= all_deps_costly
;
3662 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3663 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3664 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3665 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3667 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3668 atoi (rs6000_sched_costly_dep_str
));
3671 /* Handle -minsert-sched-nops option. */
3672 rs6000_sched_insert_nops
3673 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3675 if (rs6000_sched_insert_nops_str
)
3677 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3678 rs6000_sched_insert_nops
= sched_finish_none
;
3679 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3680 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3681 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3682 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3684 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3685 atoi (rs6000_sched_insert_nops_str
));
3690 #ifdef TARGET_REGNAMES
3691 /* If the user desires alternate register names, copy in the
3692 alternate names now. */
3693 if (TARGET_REGNAMES
)
3694 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3697 /* Set aix_struct_return last, after the ABI is determined.
3698 If -maix-struct-return or -msvr4-struct-return was explicitly
3699 used, don't override with the ABI default. */
3700 if (!global_options_set
.x_aix_struct_return
)
3701 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3704 /* IBM XL compiler defaults to unsigned bitfields. */
3705 if (TARGET_XL_COMPAT
)
3706 flag_signed_bitfields
= 0;
3709 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3710 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3713 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3715 /* We can only guarantee the availability of DI pseudo-ops when
3716 assembling for 64-bit targets. */
3719 targetm
.asm_out
.aligned_op
.di
= NULL
;
3720 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3724 /* Set branch target alignment, if not optimizing for size. */
3727 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3728 aligned 8byte to avoid misprediction by the branch predictor. */
3729 if (rs6000_cpu
== PROCESSOR_TITAN
3730 || rs6000_cpu
== PROCESSOR_CELL
)
3732 if (align_functions
<= 0)
3733 align_functions
= 8;
3734 if (align_jumps
<= 0)
3736 if (align_loops
<= 0)
3739 if (rs6000_align_branch_targets
)
3741 if (align_functions
<= 0)
3742 align_functions
= 16;
3743 if (align_jumps
<= 0)
3745 if (align_loops
<= 0)
3747 can_override_loop_align
= 1;
3751 if (align_jumps_max_skip
<= 0)
3752 align_jumps_max_skip
= 15;
3753 if (align_loops_max_skip
<= 0)
3754 align_loops_max_skip
= 15;
3757 /* Arrange to save and restore machine status around nested functions. */
3758 init_machine_status
= rs6000_init_machine_status
;
3760 /* We should always be splitting complex arguments, but we can't break
3761 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3762 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
3763 targetm
.calls
.split_complex_arg
= NULL
;
3766 /* Initialize rs6000_cost with the appropriate target costs. */
3768 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3772 case PROCESSOR_RS64A
:
3773 rs6000_cost
= &rs64a_cost
;
3776 case PROCESSOR_MPCCORE
:
3777 rs6000_cost
= &mpccore_cost
;
3780 case PROCESSOR_PPC403
:
3781 rs6000_cost
= &ppc403_cost
;
3784 case PROCESSOR_PPC405
:
3785 rs6000_cost
= &ppc405_cost
;
3788 case PROCESSOR_PPC440
:
3789 rs6000_cost
= &ppc440_cost
;
3792 case PROCESSOR_PPC476
:
3793 rs6000_cost
= &ppc476_cost
;
3796 case PROCESSOR_PPC601
:
3797 rs6000_cost
= &ppc601_cost
;
3800 case PROCESSOR_PPC603
:
3801 rs6000_cost
= &ppc603_cost
;
3804 case PROCESSOR_PPC604
:
3805 rs6000_cost
= &ppc604_cost
;
3808 case PROCESSOR_PPC604e
:
3809 rs6000_cost
= &ppc604e_cost
;
3812 case PROCESSOR_PPC620
:
3813 rs6000_cost
= &ppc620_cost
;
3816 case PROCESSOR_PPC630
:
3817 rs6000_cost
= &ppc630_cost
;
3820 case PROCESSOR_CELL
:
3821 rs6000_cost
= &ppccell_cost
;
3824 case PROCESSOR_PPC750
:
3825 case PROCESSOR_PPC7400
:
3826 rs6000_cost
= &ppc750_cost
;
3829 case PROCESSOR_PPC7450
:
3830 rs6000_cost
= &ppc7450_cost
;
3833 case PROCESSOR_PPC8540
:
3834 case PROCESSOR_PPC8548
:
3835 rs6000_cost
= &ppc8540_cost
;
3838 case PROCESSOR_PPCE300C2
:
3839 case PROCESSOR_PPCE300C3
:
3840 rs6000_cost
= &ppce300c2c3_cost
;
3843 case PROCESSOR_PPCE500MC
:
3844 rs6000_cost
= &ppce500mc_cost
;
3847 case PROCESSOR_PPCE500MC64
:
3848 rs6000_cost
= &ppce500mc64_cost
;
3851 case PROCESSOR_PPCE5500
:
3852 rs6000_cost
= &ppce5500_cost
;
3855 case PROCESSOR_PPCE6500
:
3856 rs6000_cost
= &ppce6500_cost
;
3859 case PROCESSOR_TITAN
:
3860 rs6000_cost
= &titan_cost
;
3863 case PROCESSOR_POWER4
:
3864 case PROCESSOR_POWER5
:
3865 rs6000_cost
= &power4_cost
;
3868 case PROCESSOR_POWER6
:
3869 rs6000_cost
= &power6_cost
;
3872 case PROCESSOR_POWER7
:
3873 rs6000_cost
= &power7_cost
;
3876 case PROCESSOR_POWER8
:
3877 rs6000_cost
= &power8_cost
;
3880 case PROCESSOR_PPCA2
:
3881 rs6000_cost
= &ppca2_cost
;
3890 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3891 rs6000_cost
->simultaneous_prefetches
,
3892 global_options
.x_param_values
,
3893 global_options_set
.x_param_values
);
3894 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3895 global_options
.x_param_values
,
3896 global_options_set
.x_param_values
);
3897 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3898 rs6000_cost
->cache_line_size
,
3899 global_options
.x_param_values
,
3900 global_options_set
.x_param_values
);
3901 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3902 global_options
.x_param_values
,
3903 global_options_set
.x_param_values
);
3905 /* Increase loop peeling limits based on performance analysis. */
3906 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3907 global_options
.x_param_values
,
3908 global_options_set
.x_param_values
);
3909 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3910 global_options
.x_param_values
,
3911 global_options_set
.x_param_values
);
3913 /* If using typedef char *va_list, signal that
3914 __builtin_va_start (&ap, 0) can be optimized to
3915 ap = __builtin_next_arg (0). */
3916 if (DEFAULT_ABI
!= ABI_V4
)
3917 targetm
.expand_builtin_va_start
= NULL
;
3920 /* Set up single/double float flags.
3921 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3922 then set both flags. */
3923 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3924 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3925 rs6000_single_float
= rs6000_double_float
= 1;
3927 /* If not explicitly specified via option, decide whether to generate indexed
3928 load/store instructions. */
3929 if (TARGET_AVOID_XFORM
== -1)
3930 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3931 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3932 need indexed accesses and the type used is the scalar type of the element
3933 being loaded or stored. */
3934 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3935 && !TARGET_ALTIVEC
);
3937 /* Set the -mrecip options. */
3938 if (rs6000_recip_name
)
3940 char *p
= ASTRDUP (rs6000_recip_name
);
3942 unsigned int mask
, i
;
3945 while ((q
= strtok (p
, ",")) != NULL
)
3956 if (!strcmp (q
, "default"))
3957 mask
= ((TARGET_RECIP_PRECISION
)
3958 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3961 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3962 if (!strcmp (q
, recip_options
[i
].string
))
3964 mask
= recip_options
[i
].mask
;
3968 if (i
== ARRAY_SIZE (recip_options
))
3970 error ("unknown option for -mrecip=%s", q
);
3978 rs6000_recip_control
&= ~mask
;
3980 rs6000_recip_control
|= mask
;
3984 /* Set the builtin mask of the various options used that could affect which
3985 builtins were used. In the past we used target_flags, but we've run out
3986 of bits, and some options like SPE and PAIRED are no longer in
3988 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
3989 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
3992 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
3993 rs6000_builtin_mask
);
3994 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
3997 /* Initialize all of the registers. */
3998 rs6000_init_hard_regno_mode_ok (global_init_p
);
4000 /* Save the initial options in case the user does function specific options */
4002 target_option_default_node
= target_option_current_node
4003 = build_target_option_node (&global_options
);
4005 /* If not explicitly specified via option, decide whether to generate the
4006 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4007 if (TARGET_LINK_STACK
== -1)
4008 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
4013 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4014 define the target cpu type. */
4017 rs6000_option_override (void)
4019 (void) rs6000_option_override_internal (true);
4023 /* Implement targetm.vectorize.builtin_mask_for_load. */
4025 rs6000_builtin_mask_for_load (void)
4027 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4028 return altivec_builtin_mask_for_load
;
4033 /* Implement LOOP_ALIGN. */
4035 rs6000_loop_align (rtx label
)
4040 /* Don't override loop alignment if -falign-loops was specified. */
4041 if (!can_override_loop_align
)
4042 return align_loops_log
;
4044 bb
= BLOCK_FOR_INSN (label
);
4045 ninsns
= num_loop_insns(bb
->loop_father
);
4047 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4048 if (ninsns
> 4 && ninsns
<= 8
4049 && (rs6000_cpu
== PROCESSOR_POWER4
4050 || rs6000_cpu
== PROCESSOR_POWER5
4051 || rs6000_cpu
== PROCESSOR_POWER6
4052 || rs6000_cpu
== PROCESSOR_POWER7
4053 || rs6000_cpu
== PROCESSOR_POWER8
))
4056 return align_loops_log
;
4059 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
4061 rs6000_loop_align_max_skip (rtx label
)
4063 return (1 << rs6000_loop_align (label
)) - 1;
4066 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4067 after applying N number of iterations. This routine does not determine
4068 how may iterations are required to reach desired alignment. */
4071 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
4078 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
4081 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4091 /* Assuming that all other types are naturally aligned. CHECKME! */
4096 /* Return true if the vector misalignment factor is supported by the
4099 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
4106 /* Return if movmisalign pattern is not supported for this mode. */
4107 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4110 if (misalignment
== -1)
4112 /* Misalignment factor is unknown at compile time but we know
4113 it's word aligned. */
4114 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4116 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
4118 if (element_size
== 64 || element_size
== 32)
4125 /* VSX supports word-aligned vector. */
4126 if (misalignment
% 4 == 0)
4132 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4134 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4135 tree vectype
, int misalign
)
4140 switch (type_of_cost
)
4150 case cond_branch_not_taken
:
4159 case vec_promote_demote
:
4165 case cond_branch_taken
:
4168 case unaligned_load
:
4169 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4171 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4173 /* Double word aligned. */
4181 /* Double word aligned. */
4185 /* Unknown misalignment. */
4198 /* Misaligned loads are not supported. */
4203 case unaligned_store
:
4204 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4206 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4208 /* Double word aligned. */
4216 /* Double word aligned. */
4220 /* Unknown misalignment. */
4233 /* Misaligned stores are not supported. */
4239 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4240 elem_type
= TREE_TYPE (vectype
);
4241 /* 32-bit vectors loaded into registers are stored as double
4242 precision, so we need n/2 converts in addition to the usual
4243 n/2 merges to construct a vector of short floats from them. */
4244 if (SCALAR_FLOAT_TYPE_P (elem_type
)
4245 && TYPE_PRECISION (elem_type
) == 32)
4246 return elements
+ 1;
4248 return elements
/ 2 + 1;
4255 /* Implement targetm.vectorize.preferred_simd_mode. */
4257 static enum machine_mode
4258 rs6000_preferred_simd_mode (enum machine_mode mode
)
4267 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4293 if (TARGET_PAIRED_FLOAT
4299 typedef struct _rs6000_cost_data
4301 struct loop
*loop_info
;
4305 /* Test for likely overcommitment of vector hardware resources. If a
4306 loop iteration is relatively large, and too large a percentage of
4307 instructions in the loop are vectorized, the cost model may not
4308 adequately reflect delays from unavailable vector resources.
4309 Penalize the loop body cost for this case. */
4312 rs6000_density_test (rs6000_cost_data
*data
)
4314 const int DENSITY_PCT_THRESHOLD
= 85;
4315 const int DENSITY_SIZE_THRESHOLD
= 70;
4316 const int DENSITY_PENALTY
= 10;
4317 struct loop
*loop
= data
->loop_info
;
4318 basic_block
*bbs
= get_loop_body (loop
);
4319 int nbbs
= loop
->num_nodes
;
4320 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
4323 for (i
= 0; i
< nbbs
; i
++)
4325 basic_block bb
= bbs
[i
];
4326 gimple_stmt_iterator gsi
;
4328 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
4330 gimple stmt
= gsi_stmt (gsi
);
4331 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
4333 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
4334 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
4340 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
4342 if (density_pct
> DENSITY_PCT_THRESHOLD
4343 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
4345 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
4346 if (dump_enabled_p ())
4347 dump_printf_loc (MSG_NOTE
, vect_location
,
4348 "density %d%%, cost %d exceeds threshold, penalizing "
4349 "loop body cost by %d%%", density_pct
,
4350 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4354 /* Implement targetm.vectorize.init_cost. */
4357 rs6000_init_cost (struct loop
*loop_info
)
4359 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4360 data
->loop_info
= loop_info
;
4361 data
->cost
[vect_prologue
] = 0;
4362 data
->cost
[vect_body
] = 0;
4363 data
->cost
[vect_epilogue
] = 0;
4367 /* Implement targetm.vectorize.add_stmt_cost. */
4370 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4371 struct _stmt_vec_info
*stmt_info
, int misalign
,
4372 enum vect_cost_model_location where
)
4374 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4375 unsigned retval
= 0;
4377 if (flag_vect_cost_model
)
4379 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4380 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4382 /* Statements in an inner loop relative to the loop being
4383 vectorized are weighted more heavily. The value here is
4384 arbitrary and could potentially be improved with analysis. */
4385 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4386 count
*= 50; /* FIXME. */
4388 retval
= (unsigned) (count
* stmt_cost
);
4389 cost_data
->cost
[where
] += retval
;
4395 /* Implement targetm.vectorize.finish_cost. */
4398 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4399 unsigned *body_cost
, unsigned *epilogue_cost
)
4401 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4403 if (cost_data
->loop_info
)
4404 rs6000_density_test (cost_data
);
4406 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4407 *body_cost
= cost_data
->cost
[vect_body
];
4408 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4411 /* Implement targetm.vectorize.destroy_cost_data. */
4414 rs6000_destroy_cost_data (void *data
)
4419 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4420 library with vectorized intrinsics. */
4423 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4426 const char *suffix
= NULL
;
4427 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4430 enum machine_mode el_mode
, in_mode
;
4433 /* Libmass is suitable for unsafe math only as it does not correctly support
4434 parts of IEEE with the required precision such as denormals. Only support
4435 it if we have VSX to use the simd d2 or f4 functions.
4436 XXX: Add variable length support. */
4437 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4440 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4441 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4442 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4443 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4444 if (el_mode
!= in_mode
4448 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4450 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4453 case BUILT_IN_ATAN2
:
4454 case BUILT_IN_HYPOT
:
4460 case BUILT_IN_ACOSH
:
4462 case BUILT_IN_ASINH
:
4464 case BUILT_IN_ATANH
:
4472 case BUILT_IN_EXPM1
:
4473 case BUILT_IN_LGAMMA
:
4474 case BUILT_IN_LOG10
:
4475 case BUILT_IN_LOG1P
:
4483 bdecl
= builtin_decl_implicit (fn
);
4484 suffix
= "d2"; /* pow -> powd2 */
4485 if (el_mode
!= DFmode
4491 case BUILT_IN_ATAN2F
:
4492 case BUILT_IN_HYPOTF
:
4497 case BUILT_IN_ACOSF
:
4498 case BUILT_IN_ACOSHF
:
4499 case BUILT_IN_ASINF
:
4500 case BUILT_IN_ASINHF
:
4501 case BUILT_IN_ATANF
:
4502 case BUILT_IN_ATANHF
:
4503 case BUILT_IN_CBRTF
:
4505 case BUILT_IN_COSHF
:
4507 case BUILT_IN_ERFCF
:
4508 case BUILT_IN_EXP2F
:
4510 case BUILT_IN_EXPM1F
:
4511 case BUILT_IN_LGAMMAF
:
4512 case BUILT_IN_LOG10F
:
4513 case BUILT_IN_LOG1PF
:
4514 case BUILT_IN_LOG2F
:
4517 case BUILT_IN_SINHF
:
4518 case BUILT_IN_SQRTF
:
4520 case BUILT_IN_TANHF
:
4521 bdecl
= builtin_decl_implicit (fn
);
4522 suffix
= "4"; /* powf -> powf4 */
4523 if (el_mode
!= SFmode
4536 gcc_assert (suffix
!= NULL
);
4537 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4541 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4542 strcat (name
, suffix
);
4545 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4546 else if (n_args
== 2)
4547 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4551 /* Build a function declaration for the vectorized function. */
4552 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4553 FUNCTION_DECL
, get_identifier (name
), fntype
);
4554 TREE_PUBLIC (new_fndecl
) = 1;
4555 DECL_EXTERNAL (new_fndecl
) = 1;
4556 DECL_IS_NOVOPS (new_fndecl
) = 1;
4557 TREE_READONLY (new_fndecl
) = 1;
4562 /* Returns a function decl for a vectorized version of the builtin function
4563 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4564 if it is not available. */
4567 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4570 enum machine_mode in_mode
, out_mode
;
4573 if (TARGET_DEBUG_BUILTIN
)
4574 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4575 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4576 GET_MODE_NAME (TYPE_MODE (type_out
)),
4577 GET_MODE_NAME (TYPE_MODE (type_in
)));
4579 if (TREE_CODE (type_out
) != VECTOR_TYPE
4580 || TREE_CODE (type_in
) != VECTOR_TYPE
4581 || !TARGET_VECTORIZE_BUILTINS
)
4584 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4585 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4586 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4587 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4589 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4591 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4594 case BUILT_IN_CLZIMAX
:
4595 case BUILT_IN_CLZLL
:
4598 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4600 if (out_mode
== QImode
&& out_n
== 16)
4601 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4602 else if (out_mode
== HImode
&& out_n
== 8)
4603 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4604 else if (out_mode
== SImode
&& out_n
== 4)
4605 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4606 else if (out_mode
== DImode
&& out_n
== 2)
4607 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4610 case BUILT_IN_COPYSIGN
:
4611 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4612 && out_mode
== DFmode
&& out_n
== 2
4613 && in_mode
== DFmode
&& in_n
== 2)
4614 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4616 case BUILT_IN_COPYSIGNF
:
4617 if (out_mode
!= SFmode
|| out_n
!= 4
4618 || in_mode
!= SFmode
|| in_n
!= 4)
4620 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4621 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4622 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4623 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4625 case BUILT_IN_POPCOUNTIMAX
:
4626 case BUILT_IN_POPCOUNTLL
:
4627 case BUILT_IN_POPCOUNTL
:
4628 case BUILT_IN_POPCOUNT
:
4629 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4631 if (out_mode
== QImode
&& out_n
== 16)
4632 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4633 else if (out_mode
== HImode
&& out_n
== 8)
4634 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4635 else if (out_mode
== SImode
&& out_n
== 4)
4636 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4637 else if (out_mode
== DImode
&& out_n
== 2)
4638 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4642 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4643 && out_mode
== DFmode
&& out_n
== 2
4644 && in_mode
== DFmode
&& in_n
== 2)
4645 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4647 case BUILT_IN_SQRTF
:
4648 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4649 && out_mode
== SFmode
&& out_n
== 4
4650 && in_mode
== SFmode
&& in_n
== 4)
4651 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4654 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4655 && out_mode
== DFmode
&& out_n
== 2
4656 && in_mode
== DFmode
&& in_n
== 2)
4657 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4659 case BUILT_IN_CEILF
:
4660 if (out_mode
!= SFmode
|| out_n
!= 4
4661 || in_mode
!= SFmode
|| in_n
!= 4)
4663 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4664 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4665 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4666 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4668 case BUILT_IN_FLOOR
:
4669 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4670 && out_mode
== DFmode
&& out_n
== 2
4671 && in_mode
== DFmode
&& in_n
== 2)
4672 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4674 case BUILT_IN_FLOORF
:
4675 if (out_mode
!= SFmode
|| out_n
!= 4
4676 || in_mode
!= SFmode
|| in_n
!= 4)
4678 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4679 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4680 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4681 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4684 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4685 && out_mode
== DFmode
&& out_n
== 2
4686 && in_mode
== DFmode
&& in_n
== 2)
4687 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4690 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4691 && out_mode
== SFmode
&& out_n
== 4
4692 && in_mode
== SFmode
&& in_n
== 4)
4693 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4694 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
4695 && out_mode
== SFmode
&& out_n
== 4
4696 && in_mode
== SFmode
&& in_n
== 4)
4697 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
4699 case BUILT_IN_TRUNC
:
4700 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4701 && out_mode
== DFmode
&& out_n
== 2
4702 && in_mode
== DFmode
&& in_n
== 2)
4703 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
4705 case BUILT_IN_TRUNCF
:
4706 if (out_mode
!= SFmode
|| out_n
!= 4
4707 || in_mode
!= SFmode
|| in_n
!= 4)
4709 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4710 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
4711 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4712 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
4714 case BUILT_IN_NEARBYINT
:
4715 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4716 && flag_unsafe_math_optimizations
4717 && out_mode
== DFmode
&& out_n
== 2
4718 && in_mode
== DFmode
&& in_n
== 2)
4719 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
4721 case BUILT_IN_NEARBYINTF
:
4722 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4723 && flag_unsafe_math_optimizations
4724 && out_mode
== SFmode
&& out_n
== 4
4725 && in_mode
== SFmode
&& in_n
== 4)
4726 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
4729 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4730 && !flag_trapping_math
4731 && out_mode
== DFmode
&& out_n
== 2
4732 && in_mode
== DFmode
&& in_n
== 2)
4733 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
4735 case BUILT_IN_RINTF
:
4736 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4737 && !flag_trapping_math
4738 && out_mode
== SFmode
&& out_n
== 4
4739 && in_mode
== SFmode
&& in_n
== 4)
4740 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
4747 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
4749 enum rs6000_builtins fn
4750 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
4753 case RS6000_BUILTIN_RSQRTF
:
4754 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4755 && out_mode
== SFmode
&& out_n
== 4
4756 && in_mode
== SFmode
&& in_n
== 4)
4757 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
4759 case RS6000_BUILTIN_RSQRT
:
4760 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4761 && out_mode
== DFmode
&& out_n
== 2
4762 && in_mode
== DFmode
&& in_n
== 2)
4763 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
4765 case RS6000_BUILTIN_RECIPF
:
4766 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4767 && out_mode
== SFmode
&& out_n
== 4
4768 && in_mode
== SFmode
&& in_n
== 4)
4769 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4771 case RS6000_BUILTIN_RECIP
:
4772 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4773 && out_mode
== DFmode
&& out_n
== 2
4774 && in_mode
== DFmode
&& in_n
== 2)
4775 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4782 /* Generate calls to libmass if appropriate. */
4783 if (rs6000_veclib_handler
)
4784 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4789 /* Default CPU string for rs6000*_file_start functions. */
4790 static const char *rs6000_default_cpu
;
4792 /* Do anything needed at the start of the asm file. */
4795 rs6000_file_start (void)
4798 const char *start
= buffer
;
4799 FILE *file
= asm_out_file
;
4801 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4803 default_file_start ();
4805 if (flag_verbose_asm
)
4807 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4809 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4811 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4815 if (global_options_set
.x_rs6000_cpu_index
)
4817 fprintf (file
, "%s -mcpu=%s", start
,
4818 processor_target_table
[rs6000_cpu_index
].name
);
4822 if (global_options_set
.x_rs6000_tune_index
)
4824 fprintf (file
, "%s -mtune=%s", start
,
4825 processor_target_table
[rs6000_tune_index
].name
);
4829 if (PPC405_ERRATUM77
)
4831 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4835 #ifdef USING_ELFOS_H
4836 switch (rs6000_sdata
)
4838 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4839 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4840 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4841 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4844 if (rs6000_sdata
&& g_switch_value
)
4846 fprintf (file
, "%s -G %d", start
,
4856 if (DEFAULT_ABI
== ABI_ELFv2
)
4857 fprintf (file
, "\t.abiversion 2\n");
4859 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
4860 || (TARGET_ELF
&& flag_pic
== 2))
4862 switch_to_section (toc_section
);
4863 switch_to_section (text_section
);
4868 /* Return nonzero if this function is known to have a null epilogue. */
4871 direct_return (void)
4873 if (reload_completed
)
4875 rs6000_stack_t
*info
= rs6000_stack_info ();
4877 if (info
->first_gp_reg_save
== 32
4878 && info
->first_fp_reg_save
== 64
4879 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4880 && ! info
->lr_save_p
4881 && ! info
->cr_save_p
4882 && info
->vrsave_mask
== 0
4890 /* Return the number of instructions it takes to form a constant in an
4891 integer register. */
4894 num_insns_constant_wide (HOST_WIDE_INT value
)
4896 /* signed constant loadable with addi */
4897 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4900 /* constant loadable with addis */
4901 else if ((value
& 0xffff) == 0
4902 && (value
>> 31 == -1 || value
>> 31 == 0))
4905 else if (TARGET_POWERPC64
)
4907 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4908 HOST_WIDE_INT high
= value
>> 31;
4910 if (high
== 0 || high
== -1)
4916 return num_insns_constant_wide (high
) + 1;
4918 return num_insns_constant_wide (low
) + 1;
4920 return (num_insns_constant_wide (high
)
4921 + num_insns_constant_wide (low
) + 1);
4929 num_insns_constant (rtx op
, enum machine_mode mode
)
4931 HOST_WIDE_INT low
, high
;
4933 switch (GET_CODE (op
))
4936 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4937 && mask64_operand (op
, mode
))
4940 return num_insns_constant_wide (INTVAL (op
));
4943 if (mode
== SFmode
|| mode
== SDmode
)
4948 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4949 if (DECIMAL_FLOAT_MODE_P (mode
))
4950 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4952 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4953 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4959 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4960 if (DECIMAL_FLOAT_MODE_P (mode
))
4961 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
4963 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
4964 high
= l
[WORDS_BIG_ENDIAN
== 0];
4965 low
= l
[WORDS_BIG_ENDIAN
!= 0];
4968 return (num_insns_constant_wide (low
)
4969 + num_insns_constant_wide (high
));
4972 if ((high
== 0 && low
>= 0)
4973 || (high
== -1 && low
< 0))
4974 return num_insns_constant_wide (low
);
4976 else if (mask64_operand (op
, mode
))
4980 return num_insns_constant_wide (high
) + 1;
4983 return (num_insns_constant_wide (high
)
4984 + num_insns_constant_wide (low
) + 1);
4992 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4993 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4994 corresponding element of the vector, but for V4SFmode and V2SFmode,
4995 the corresponding "float" is interpreted as an SImode integer. */
4998 const_vector_elt_as_int (rtx op
, unsigned int elt
)
5002 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5003 gcc_assert (GET_MODE (op
) != V2DImode
5004 && GET_MODE (op
) != V2DFmode
);
5006 tmp
= CONST_VECTOR_ELT (op
, elt
);
5007 if (GET_MODE (op
) == V4SFmode
5008 || GET_MODE (op
) == V2SFmode
)
5009 tmp
= gen_lowpart (SImode
, tmp
);
5010 return INTVAL (tmp
);
5013 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5014 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5015 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5016 all items are set to the same value and contain COPIES replicas of the
5017 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5018 operand and the others are set to the value of the operand's msb. */
5021 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
5023 enum machine_mode mode
= GET_MODE (op
);
5024 enum machine_mode inner
= GET_MODE_INNER (mode
);
5032 HOST_WIDE_INT splat_val
;
5033 HOST_WIDE_INT msb_val
;
5035 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
5038 nunits
= GET_MODE_NUNITS (mode
);
5039 bitsize
= GET_MODE_BITSIZE (inner
);
5040 mask
= GET_MODE_MASK (inner
);
5042 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5044 msb_val
= val
>= 0 ? 0 : -1;
5046 /* Construct the value to be splatted, if possible. If not, return 0. */
5047 for (i
= 2; i
<= copies
; i
*= 2)
5049 HOST_WIDE_INT small_val
;
5051 small_val
= splat_val
>> bitsize
;
5053 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
5055 splat_val
= small_val
;
5058 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5059 if (EASY_VECTOR_15 (splat_val
))
5062 /* Also check if we can splat, and then add the result to itself. Do so if
5063 the value is positive, of if the splat instruction is using OP's mode;
5064 for splat_val < 0, the splat and the add should use the same mode. */
5065 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
5066 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
5069 /* Also check if are loading up the most significant bit which can be done by
5070 loading up -1 and shifting the value left by -1. */
5071 else if (EASY_VECTOR_MSB (splat_val
, inner
))
5077 /* Check if VAL is present in every STEP-th element, and the
5078 other elements are filled with its most significant bit. */
5079 for (i
= 1; i
< nunits
; ++i
)
5081 HOST_WIDE_INT desired_val
;
5082 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
5083 if ((i
& (step
- 1)) == 0)
5086 desired_val
= msb_val
;
5088 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5096 /* Return true if OP is of the given MODE and can be synthesized
5097 with a vspltisb, vspltish or vspltisw. */
5100 easy_altivec_constant (rtx op
, enum machine_mode mode
)
5102 unsigned step
, copies
;
5104 if (mode
== VOIDmode
)
5105 mode
= GET_MODE (op
);
5106 else if (mode
!= GET_MODE (op
))
5109 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5111 if (mode
== V2DFmode
)
5112 return zero_constant (op
, mode
);
5114 else if (mode
== V2DImode
)
5116 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
5118 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5119 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5122 if (zero_constant (op
, mode
))
5125 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5126 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5132 /* V1TImode is a special container for TImode. Ignore for now. */
5133 else if (mode
== V1TImode
)
5136 /* Start with a vspltisw. */
5137 step
= GET_MODE_NUNITS (mode
) / 4;
5140 if (vspltis_constant (op
, step
, copies
))
5143 /* Then try with a vspltish. */
5149 if (vspltis_constant (op
, step
, copies
))
5152 /* And finally a vspltisb. */
5158 if (vspltis_constant (op
, step
, copies
))
5164 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5165 result is OP. Abort if it is not possible. */
5168 gen_easy_altivec_constant (rtx op
)
5170 enum machine_mode mode
= GET_MODE (op
);
5171 int nunits
= GET_MODE_NUNITS (mode
);
5172 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5173 unsigned step
= nunits
/ 4;
5174 unsigned copies
= 1;
5176 /* Start with a vspltisw. */
5177 if (vspltis_constant (op
, step
, copies
))
5178 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
5180 /* Then try with a vspltish. */
5186 if (vspltis_constant (op
, step
, copies
))
5187 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
5189 /* And finally a vspltisb. */
5195 if (vspltis_constant (op
, step
, copies
))
5196 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
5202 output_vec_const_move (rtx
*operands
)
5205 enum machine_mode mode
;
5210 mode
= GET_MODE (dest
);
5214 if (zero_constant (vec
, mode
))
5215 return "xxlxor %x0,%x0,%x0";
5217 if ((mode
== V2DImode
|| mode
== V1TImode
)
5218 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
5219 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
5220 return "vspltisw %0,-1";
5226 if (zero_constant (vec
, mode
))
5227 return "vxor %0,%0,%0";
5229 splat_vec
= gen_easy_altivec_constant (vec
);
5230 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
5231 operands
[1] = XEXP (splat_vec
, 0);
5232 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
5235 switch (GET_MODE (splat_vec
))
5238 return "vspltisw %0,%1";
5241 return "vspltish %0,%1";
5244 return "vspltisb %0,%1";
5251 gcc_assert (TARGET_SPE
);
5253 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5254 pattern of V1DI, V4HI, and V2SF.
5256 FIXME: We should probably return # and add post reload
5257 splitters for these, but this way is so easy ;-). */
5258 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
5259 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
5260 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
5261 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
5263 return "li %0,%1\n\tevmergelo %0,%0,%0";
5265 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5268 /* Initialize TARGET of vector PAIRED to VALS. */
5271 paired_expand_vector_init (rtx target
, rtx vals
)
5273 enum machine_mode mode
= GET_MODE (target
);
5274 int n_elts
= GET_MODE_NUNITS (mode
);
5276 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
5279 for (i
= 0; i
< n_elts
; ++i
)
5281 x
= XVECEXP (vals
, 0, i
);
5282 if (!(CONST_INT_P (x
)
5283 || GET_CODE (x
) == CONST_DOUBLE
5284 || GET_CODE (x
) == CONST_FIXED
))
5289 /* Load from constant pool. */
5290 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
5296 /* The vector is initialized only with non-constants. */
5297 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
5298 XVECEXP (vals
, 0, 1));
5300 emit_move_insn (target
, new_rtx
);
5304 /* One field is non-constant and the other one is a constant. Load the
5305 constant from the constant pool and use ps_merge instruction to
5306 construct the whole vector. */
5307 op1
= XVECEXP (vals
, 0, 0);
5308 op2
= XVECEXP (vals
, 0, 1);
5310 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
5312 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
5313 emit_move_insn (tmp
, constant_op
);
5315 if (CONSTANT_P (op1
))
5316 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
5318 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
5320 emit_move_insn (target
, new_rtx
);
5324 paired_expand_vector_move (rtx operands
[])
5326 rtx op0
= operands
[0], op1
= operands
[1];
5328 emit_move_insn (op0
, op1
);
5331 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5332 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5333 operands for the relation operation COND. This is a recursive
5337 paired_emit_vector_compare (enum rtx_code rcode
,
5338 rtx dest
, rtx op0
, rtx op1
,
5339 rtx cc_op0
, rtx cc_op1
)
5341 rtx tmp
= gen_reg_rtx (V2SFmode
);
5344 gcc_assert (TARGET_PAIRED_FLOAT
);
5345 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
5351 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5355 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5356 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5360 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5363 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5366 tmp1
= gen_reg_rtx (V2SFmode
);
5367 max
= gen_reg_rtx (V2SFmode
);
5368 min
= gen_reg_rtx (V2SFmode
);
5369 gen_reg_rtx (V2SFmode
);
5371 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5372 emit_insn (gen_selv2sf4
5373 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5374 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5375 emit_insn (gen_selv2sf4
5376 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5377 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5378 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5381 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5384 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5387 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5390 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5393 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5402 /* Emit vector conditional expression.
5403 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5404 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5407 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5408 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5410 enum rtx_code rcode
= GET_CODE (cond
);
5412 if (!TARGET_PAIRED_FLOAT
)
5415 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5420 /* Initialize vector TARGET to VALS. */
5423 rs6000_expand_vector_init (rtx target
, rtx vals
)
5425 enum machine_mode mode
= GET_MODE (target
);
5426 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5427 int n_elts
= GET_MODE_NUNITS (mode
);
5428 int n_var
= 0, one_var
= -1;
5429 bool all_same
= true, all_const_zero
= true;
5433 for (i
= 0; i
< n_elts
; ++i
)
5435 x
= XVECEXP (vals
, 0, i
);
5436 if (!(CONST_INT_P (x
)
5437 || GET_CODE (x
) == CONST_DOUBLE
5438 || GET_CODE (x
) == CONST_FIXED
))
5439 ++n_var
, one_var
= i
;
5440 else if (x
!= CONST0_RTX (inner_mode
))
5441 all_const_zero
= false;
5443 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5449 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5450 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5451 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5453 /* Zero register. */
5454 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5455 gen_rtx_XOR (mode
, target
, target
)));
5458 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5460 /* Splat immediate. */
5461 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
5466 /* Load from constant pool. */
5467 emit_move_insn (target
, const_vec
);
5472 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5473 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5475 rtx op0
= XVECEXP (vals
, 0, 0);
5476 rtx op1
= XVECEXP (vals
, 0, 1);
5479 if (!MEM_P (op0
) && !REG_P (op0
))
5480 op0
= force_reg (inner_mode
, op0
);
5481 if (mode
== V2DFmode
)
5482 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5484 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5488 op0
= force_reg (inner_mode
, op0
);
5489 op1
= force_reg (inner_mode
, op1
);
5490 if (mode
== V2DFmode
)
5491 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5493 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5498 /* With single precision floating point on VSX, know that internally single
5499 precision is actually represented as a double, and either make 2 V2DF
5500 vectors, and convert these vectors to single precision, or do one
5501 conversion, and splat the result to the other elements. */
5502 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5506 rtx freg
= gen_reg_rtx (V4SFmode
);
5507 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5508 rtx cvt
= ((TARGET_XSCVDPSPN
)
5509 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5510 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5513 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
, const0_rtx
));
5517 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5518 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5519 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5520 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5521 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5522 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5523 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5524 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5526 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5527 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5528 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5529 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5530 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5535 /* Store value to stack temp. Load vector element. Splat. However, splat
5536 of 64-bit items is not supported on Altivec. */
5537 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5539 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5540 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5541 XVECEXP (vals
, 0, 0));
5542 x
= gen_rtx_UNSPEC (VOIDmode
,
5543 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5544 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5546 gen_rtx_SET (VOIDmode
,
5549 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5550 gen_rtx_PARALLEL (VOIDmode
,
5551 gen_rtvec (1, const0_rtx
)));
5552 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5553 gen_rtx_VEC_DUPLICATE (mode
, x
)));
5557 /* One field is non-constant. Load constant then overwrite
5561 rtx copy
= copy_rtx (vals
);
5563 /* Load constant part of vector, substitute neighboring value for
5565 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5566 rs6000_expand_vector_init (target
, copy
);
5568 /* Insert variable. */
5569 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5573 /* Construct the vector in memory one field at a time
5574 and load the whole vector. */
5575 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5576 for (i
= 0; i
< n_elts
; i
++)
5577 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5578 i
* GET_MODE_SIZE (inner_mode
)),
5579 XVECEXP (vals
, 0, i
));
5580 emit_move_insn (target
, mem
);
5583 /* Set field ELT of TARGET to VAL. */
5586 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5588 enum machine_mode mode
= GET_MODE (target
);
5589 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5590 rtx reg
= gen_reg_rtx (mode
);
5592 int width
= GET_MODE_SIZE (inner_mode
);
5595 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5597 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5598 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5599 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5603 /* Simplify setting single element vectors like V1TImode. */
5604 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
5606 emit_move_insn (target
, gen_lowpart (mode
, val
));
5610 /* Load single variable value. */
5611 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5612 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5613 x
= gen_rtx_UNSPEC (VOIDmode
,
5614 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5615 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5617 gen_rtx_SET (VOIDmode
,
5621 /* Linear sequence. */
5622 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5623 for (i
= 0; i
< 16; ++i
)
5624 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5626 /* Set permute mask to insert element into target. */
5627 for (i
= 0; i
< width
; ++i
)
5628 XVECEXP (mask
, 0, elt
*width
+ i
)
5629 = GEN_INT (i
+ 0x10);
5630 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5632 if (BYTES_BIG_ENDIAN
)
5633 x
= gen_rtx_UNSPEC (mode
,
5634 gen_rtvec (3, target
, reg
,
5635 force_reg (V16QImode
, x
)),
5639 /* Invert selector. */
5640 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
5641 rtx andx
= gen_rtx_AND (V16QImode
, notx
, notx
);
5642 rtx tmp
= gen_reg_rtx (V16QImode
);
5643 emit_move_insn (tmp
, andx
);
5645 /* Permute with operands reversed and adjusted selector. */
5646 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
5650 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
5653 /* Extract field ELT from VEC into TARGET. */
5656 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5658 enum machine_mode mode
= GET_MODE (vec
);
5659 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5662 if (VECTOR_MEM_VSX_P (mode
))
5669 gcc_assert (elt
== 0 && inner_mode
== TImode
);
5670 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
5673 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
5676 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
5679 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
5684 /* Allocate mode-sized buffer. */
5685 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5687 emit_move_insn (mem
, vec
);
5689 /* Add offset to field within buffer matching vector element. */
5690 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
5692 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
5695 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5696 implement ANDing by the mask IN. */
5698 build_mask64_2_operands (rtx in
, rtx
*out
)
5700 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
5703 gcc_assert (GET_CODE (in
) == CONST_INT
);
5708 /* Assume c initially something like 0x00fff000000fffff. The idea
5709 is to rotate the word so that the middle ^^^^^^ group of zeros
5710 is at the MS end and can be cleared with an rldicl mask. We then
5711 rotate back and clear off the MS ^^ group of zeros with a
5713 c
= ~c
; /* c == 0xff000ffffff00000 */
5714 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
5715 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
5716 c
= ~c
; /* c == 0x00fff000000fffff */
5717 c
&= -lsb
; /* c == 0x00fff00000000000 */
5718 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5719 c
= ~c
; /* c == 0xff000fffffffffff */
5720 c
&= -lsb
; /* c == 0xff00000000000000 */
5722 while ((lsb
>>= 1) != 0)
5723 shift
++; /* shift == 44 on exit from loop */
5724 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
5725 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
5726 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
5730 /* Assume c initially something like 0xff000f0000000000. The idea
5731 is to rotate the word so that the ^^^ middle group of zeros
5732 is at the LS end and can be cleared with an rldicr mask. We then
5733 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5735 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
5736 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
5737 c
= ~c
; /* c == 0x00fff0ffffffffff */
5738 c
&= -lsb
; /* c == 0x00fff00000000000 */
5739 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5740 c
= ~c
; /* c == 0xff000fffffffffff */
5741 c
&= -lsb
; /* c == 0xff00000000000000 */
5743 while ((lsb
>>= 1) != 0)
5744 shift
++; /* shift == 44 on exit from loop */
5745 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
5746 m1
>>= shift
; /* m1 == 0x0000000000000fff */
5747 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
5750 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5751 masks will be all 1's. We are guaranteed more than one transition. */
5752 out
[0] = GEN_INT (64 - shift
);
5753 out
[1] = GEN_INT (m1
);
5754 out
[2] = GEN_INT (shift
);
5755 out
[3] = GEN_INT (m2
);
5758 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5761 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
5763 if (TARGET_E500_DOUBLE
)
5765 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5766 subreg:TI and reg:TF. Decimal float modes are like integer
5767 modes (only low part of each register used) for this
5769 if (GET_CODE (op
) == SUBREG
5770 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
5771 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
5772 && REG_P (SUBREG_REG (op
))
5773 && (GET_MODE (SUBREG_REG (op
)) == DFmode
5774 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
5777 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5779 if (GET_CODE (op
) == SUBREG
5780 && (mode
== DFmode
|| mode
== TFmode
)
5781 && REG_P (SUBREG_REG (op
))
5782 && (GET_MODE (SUBREG_REG (op
)) == DImode
5783 || GET_MODE (SUBREG_REG (op
)) == TImode
5784 || GET_MODE (SUBREG_REG (op
)) == PTImode
5785 || GET_MODE (SUBREG_REG (op
)) == DDmode
5786 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5791 && GET_CODE (op
) == SUBREG
5793 && REG_P (SUBREG_REG (op
))
5794 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5800 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
5801 selects whether the alignment is abi mandated, optional, or
5802 both abi and optional alignment. */
5805 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
5807 if (how
!= align_opt
)
5809 if (TREE_CODE (type
) == VECTOR_TYPE
)
5811 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
5812 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
5817 else if (align
< 128)
5820 else if (TARGET_E500_DOUBLE
5821 && TREE_CODE (type
) == REAL_TYPE
5822 && TYPE_MODE (type
) == DFmode
)
5829 if (how
!= align_abi
)
5831 if (TREE_CODE (type
) == ARRAY_TYPE
5832 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
5834 if (align
< BITS_PER_WORD
)
5835 align
= BITS_PER_WORD
;
5842 /* AIX increases natural record alignment to doubleword if the first
5843 field is an FP double while the FP fields remain word aligned. */
5846 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5847 unsigned int specified
)
5849 unsigned int align
= MAX (computed
, specified
);
5850 tree field
= TYPE_FIELDS (type
);
5852 /* Skip all non field decls */
5853 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5854 field
= DECL_CHAIN (field
);
5856 if (field
!= NULL
&& field
!= type
)
5858 type
= TREE_TYPE (field
);
5859 while (TREE_CODE (type
) == ARRAY_TYPE
)
5860 type
= TREE_TYPE (type
);
5862 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5863 align
= MAX (align
, 64);
5869 /* Darwin increases record alignment to the natural alignment of
5873 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5874 unsigned int specified
)
5876 unsigned int align
= MAX (computed
, specified
);
5878 if (TYPE_PACKED (type
))
5881 /* Find the first field, looking down into aggregates. */
5883 tree field
= TYPE_FIELDS (type
);
5884 /* Skip all non field decls */
5885 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5886 field
= DECL_CHAIN (field
);
5889 /* A packed field does not contribute any extra alignment. */
5890 if (DECL_PACKED (field
))
5892 type
= TREE_TYPE (field
);
5893 while (TREE_CODE (type
) == ARRAY_TYPE
)
5894 type
= TREE_TYPE (type
);
5895 } while (AGGREGATE_TYPE_P (type
));
5897 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5898 align
= MAX (align
, TYPE_ALIGN (type
));
5903 /* Return 1 for an operand in small memory on V.4/eabi. */
5906 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5907 enum machine_mode mode ATTRIBUTE_UNUSED
)
5912 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5915 if (DEFAULT_ABI
!= ABI_V4
)
5918 /* Vector and float memory instructions have a limited offset on the
5919 SPE, so using a vector or float variable directly as an operand is
5922 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5925 if (GET_CODE (op
) == SYMBOL_REF
)
5928 else if (GET_CODE (op
) != CONST
5929 || GET_CODE (XEXP (op
, 0)) != PLUS
5930 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5931 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5936 rtx sum
= XEXP (op
, 0);
5937 HOST_WIDE_INT summand
;
5939 /* We have to be careful here, because it is the referenced address
5940 that must be 32k from _SDA_BASE_, not just the symbol. */
5941 summand
= INTVAL (XEXP (sum
, 1));
5942 if (summand
< 0 || summand
> g_switch_value
)
5945 sym_ref
= XEXP (sum
, 0);
5948 return SYMBOL_REF_SMALL_P (sym_ref
);
5954 /* Return true if either operand is a general purpose register. */
5957 gpr_or_gpr_p (rtx op0
, rtx op1
)
5959 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5960 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
5963 /* Return true if this is a move direct operation between GPR registers and
5964 floating point/VSX registers. */
5967 direct_move_p (rtx op0
, rtx op1
)
5971 if (!REG_P (op0
) || !REG_P (op1
))
5974 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
5977 regno0
= REGNO (op0
);
5978 regno1
= REGNO (op1
);
5979 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
5982 if (INT_REGNO_P (regno0
))
5983 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
5985 else if (INT_REGNO_P (regno1
))
5987 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
5990 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
5997 /* Return true if this is a load or store quad operation. This function does
5998 not handle the atomic quad memory instructions. */
6001 quad_load_store_p (rtx op0
, rtx op1
)
6005 if (!TARGET_QUAD_MEMORY
)
6008 else if (REG_P (op0
) && MEM_P (op1
))
6009 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
6010 && quad_memory_operand (op1
, GET_MODE (op1
))
6011 && !reg_overlap_mentioned_p (op0
, op1
));
6013 else if (MEM_P (op0
) && REG_P (op1
))
6014 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
6015 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
6020 if (TARGET_DEBUG_ADDR
)
6022 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
6023 ret
? "true" : "false");
6024 debug_rtx (gen_rtx_SET (VOIDmode
, op0
, op1
));
6030 /* Given an address, return a constant offset term if one exists. */
6033 address_offset (rtx op
)
6035 if (GET_CODE (op
) == PRE_INC
6036 || GET_CODE (op
) == PRE_DEC
)
6038 else if (GET_CODE (op
) == PRE_MODIFY
6039 || GET_CODE (op
) == LO_SUM
)
6042 if (GET_CODE (op
) == CONST
)
6045 if (GET_CODE (op
) == PLUS
)
6048 if (CONST_INT_P (op
))
6054 /* Return true if the MEM operand is a memory operand suitable for use
6055 with a (full width, possibly multiple) gpr load/store. On
6056 powerpc64 this means the offset must be divisible by 4.
6057 Implements 'Y' constraint.
6059 Accept direct, indexed, offset, lo_sum and tocref. Since this is
6060 a constraint function we know the operand has satisfied a suitable
6061 memory predicate. Also accept some odd rtl generated by reload
6062 (see rs6000_legitimize_reload_address for various forms). It is
6063 important that reload rtl be accepted by appropriate constraints
6064 but not by the operand predicate.
6066 Offsetting a lo_sum should not be allowed, except where we know by
6067 alignment that a 32k boundary is not crossed, but see the ???
6068 comment in rs6000_legitimize_reload_address. Note that by
6069 "offsetting" here we mean a further offset to access parts of the
6070 MEM. It's fine to have a lo_sum where the inner address is offset
6071 from a sym, since the same sym+offset will appear in the high part
6072 of the address calculation. */
6075 mem_operand_gpr (rtx op
, enum machine_mode mode
)
6077 unsigned HOST_WIDE_INT offset
;
6079 rtx addr
= XEXP (op
, 0);
6081 op
= address_offset (addr
);
6085 offset
= INTVAL (op
);
6086 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
6089 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
6090 gcc_assert (extra
>= 0);
6092 if (GET_CODE (addr
) == LO_SUM
)
6093 /* For lo_sum addresses, we must allow any offset except one that
6094 causes a wrap, so test only the low 16 bits. */
6095 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
6097 return offset
+ 0x8000 < 0x10000u
- extra
;
6100 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6103 reg_offset_addressing_ok_p (enum machine_mode mode
)
6115 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6116 TImode is not a vector mode, if we want to use the VSX registers to
6117 move it around, we need to restrict ourselves to reg+reg
6119 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6127 /* Paired vector modes. Only reg+reg addressing is valid. */
6128 if (TARGET_PAIRED_FLOAT
)
6133 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6134 addressing for the LFIWZX and STFIWX instructions. */
6135 if (TARGET_NO_SDMODE_STACK
)
6147 virtual_stack_registers_memory_p (rtx op
)
6151 if (GET_CODE (op
) == REG
)
6152 regnum
= REGNO (op
);
6154 else if (GET_CODE (op
) == PLUS
6155 && GET_CODE (XEXP (op
, 0)) == REG
6156 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6157 regnum
= REGNO (XEXP (op
, 0));
6162 return (regnum
>= FIRST_VIRTUAL_REGISTER
6163 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6166 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6167 is known to not straddle a 32k boundary. */
6170 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6171 enum machine_mode mode
)
6174 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6176 if (GET_CODE (op
) != SYMBOL_REF
)
6179 dsize
= GET_MODE_SIZE (mode
);
6180 decl
= SYMBOL_REF_DECL (op
);
6186 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6187 replacing memory addresses with an anchor plus offset. We
6188 could find the decl by rummaging around in the block->objects
6189 VEC for the given offset but that seems like too much work. */
6190 dalign
= BITS_PER_UNIT
;
6191 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
6192 && SYMBOL_REF_ANCHOR_P (op
)
6193 && SYMBOL_REF_BLOCK (op
) != NULL
)
6195 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
6197 dalign
= block
->alignment
;
6198 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
6200 else if (CONSTANT_POOL_ADDRESS_P (op
))
6202 /* It would be nice to have get_pool_align().. */
6203 enum machine_mode cmode
= get_pool_mode (op
);
6205 dalign
= GET_MODE_ALIGNMENT (cmode
);
6208 else if (DECL_P (decl
))
6210 dalign
= DECL_ALIGN (decl
);
6214 /* Allow BLKmode when the entire object is known to not
6215 cross a 32k boundary. */
6216 if (!DECL_SIZE_UNIT (decl
))
6219 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
6222 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
6226 return dalign
/ BITS_PER_UNIT
>= dsize
;
6231 type
= TREE_TYPE (decl
);
6233 dalign
= TYPE_ALIGN (type
);
6234 if (CONSTANT_CLASS_P (decl
))
6235 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
6237 dalign
= DATA_ALIGNMENT (decl
, dalign
);
6241 /* BLKmode, check the entire object. */
6242 if (TREE_CODE (decl
) == STRING_CST
)
6243 dsize
= TREE_STRING_LENGTH (decl
);
6244 else if (TYPE_SIZE_UNIT (type
)
6245 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
6246 dsize
= tree_to_uhwi (TYPE_SIZE_UNIT (type
));
6252 return dalign
/ BITS_PER_UNIT
>= dsize
;
6256 /* Find how many bits of the alignment we know for this access. */
6257 mask
= dalign
/ BITS_PER_UNIT
- 1;
6258 lsb
= offset
& -offset
;
6262 return dalign
>= dsize
;
6266 constant_pool_expr_p (rtx op
)
6270 split_const (op
, &base
, &offset
);
6271 return (GET_CODE (base
) == SYMBOL_REF
6272 && CONSTANT_POOL_ADDRESS_P (base
)
6273 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
6276 static const_rtx tocrel_base
, tocrel_offset
;
6278 /* Return true if OP is a toc pointer relative address (the output
6279 of create_TOC_reference). If STRICT, do not match high part or
6280 non-split -mcmodel=large/medium toc pointer relative addresses. */
6283 toc_relative_expr_p (const_rtx op
, bool strict
)
6288 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6290 /* Only match the low part. */
6291 if (GET_CODE (op
) == LO_SUM
6292 && REG_P (XEXP (op
, 0))
6293 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
6300 tocrel_offset
= const0_rtx
;
6301 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
6303 tocrel_base
= XEXP (op
, 0);
6304 tocrel_offset
= XEXP (op
, 1);
6307 return (GET_CODE (tocrel_base
) == UNSPEC
6308 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
6311 /* Return true if X is a constant pool address, and also for cmodel=medium
6312 if X is a toc-relative address known to be offsettable within MODE. */
6315 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
6318 return (toc_relative_expr_p (x
, strict
)
6319 && (TARGET_CMODEL
!= CMODEL_MEDIUM
6320 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
6322 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
6323 INTVAL (tocrel_offset
), mode
)));
6327 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
6329 return (DEFAULT_ABI
== ABI_V4
6330 && !flag_pic
&& !TARGET_TOC
6331 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
6332 && small_data_operand (x
, mode
));
6335 /* SPE offset addressing is limited to 5-bits worth of double words. */
6336 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6339 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
6340 bool strict
, bool worst_case
)
6342 unsigned HOST_WIDE_INT offset
;
6345 if (GET_CODE (x
) != PLUS
)
6347 if (!REG_P (XEXP (x
, 0)))
6349 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6351 if (!reg_offset_addressing_ok_p (mode
))
6352 return virtual_stack_registers_memory_p (x
);
6353 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
6355 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6358 offset
= INTVAL (XEXP (x
, 1));
6366 /* SPE vector modes. */
6367 return SPE_CONST_OFFSET_OK (offset
);
6372 /* On e500v2, we may have:
6374 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6376 Which gets addressed with evldd instructions. */
6377 if (TARGET_E500_DOUBLE
)
6378 return SPE_CONST_OFFSET_OK (offset
);
6380 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6382 if (VECTOR_MEM_VSX_P (mode
))
6387 if (!TARGET_POWERPC64
)
6389 else if (offset
& 3)
6394 if (TARGET_E500_DOUBLE
)
6395 return (SPE_CONST_OFFSET_OK (offset
)
6396 && SPE_CONST_OFFSET_OK (offset
+ 8));
6405 if (!TARGET_POWERPC64
)
6407 else if (offset
& 3)
6416 return offset
< 0x10000 - extra
;
6420 legitimate_indexed_address_p (rtx x
, int strict
)
6424 if (GET_CODE (x
) != PLUS
)
6430 /* Recognize the rtl generated by reload which we know will later be
6431 replaced with proper base and index regs. */
6433 && reload_in_progress
6434 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6438 return (REG_P (op0
) && REG_P (op1
)
6439 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6440 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6441 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6442 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6446 avoiding_indexed_address_p (enum machine_mode mode
)
6448 /* Avoid indexed addressing for modes that have non-indexed
6449 load/store instruction forms. */
6450 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6454 legitimate_indirect_address_p (rtx x
, int strict
)
6456 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6460 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
6462 if (!TARGET_MACHO
|| !flag_pic
6463 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6467 if (GET_CODE (x
) != LO_SUM
)
6469 if (GET_CODE (XEXP (x
, 0)) != REG
)
6471 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6475 return CONSTANT_P (x
);
6479 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
6481 if (GET_CODE (x
) != LO_SUM
)
6483 if (GET_CODE (XEXP (x
, 0)) != REG
)
6485 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6487 /* Restrict addressing for DI because of our SUBREG hackery. */
6488 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6492 if (TARGET_ELF
|| TARGET_MACHO
)
6496 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
6498 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6499 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6500 recognizes some LO_SUM addresses as valid although this
6501 function says opposite. In most cases, LRA through different
6502 transformations can generate correct code for address reloads.
6503 It can not manage only some LO_SUM cases. So we need to add
6504 code analogous to one in rs6000_legitimize_reload_address for
6505 LOW_SUM here saying that some addresses are still valid. */
6506 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
6507 && small_toc_ref (x
, VOIDmode
));
6508 if (TARGET_TOC
&& ! large_toc_ok
)
6510 if (GET_MODE_NUNITS (mode
) != 1)
6512 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6513 && !(/* ??? Assume floating point reg based on mode? */
6514 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6515 && (mode
== DFmode
|| mode
== DDmode
)))
6518 return CONSTANT_P (x
) || large_toc_ok
;
6525 /* Try machine-dependent ways of modifying an illegitimate address
6526 to be legitimate. If we find one, return the new, valid address.
6527 This is used from only one place: `memory_address' in explow.c.
6529 OLDX is the address as it was before break_out_memory_refs was
6530 called. In some cases it is useful to look at this to decide what
6533 It is always safe for this function to do nothing. It exists to
6534 recognize opportunities to optimize the output.
6536 On RS/6000, first check for the sum of a register with a constant
6537 integer that is out of range. If so, generate code to add the
6538 constant with the low-order 16 bits masked to the register and force
6539 this result into another register (this can be done with `cau').
6540 Then generate an address of REG+(CONST&0xffff), allowing for the
6541 possibility of bit 16 being a one.
6543 Then check for the sum of a register and something not constant, try to
6544 load the other things into a register and return the sum. */
6547 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6548 enum machine_mode mode
)
6552 if (!reg_offset_addressing_ok_p (mode
))
6554 if (virtual_stack_registers_memory_p (x
))
6557 /* In theory we should not be seeing addresses of the form reg+0,
6558 but just in case it is generated, optimize it away. */
6559 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6560 return force_reg (Pmode
, XEXP (x
, 0));
6562 /* For TImode with load/store quad, restrict addresses to just a single
6563 pointer, so it works with both GPRs and VSX registers. */
6564 /* Make sure both operands are registers. */
6565 else if (GET_CODE (x
) == PLUS
6566 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6567 return gen_rtx_PLUS (Pmode
,
6568 force_reg (Pmode
, XEXP (x
, 0)),
6569 force_reg (Pmode
, XEXP (x
, 1)));
6571 return force_reg (Pmode
, x
);
6573 if (GET_CODE (x
) == SYMBOL_REF
)
6575 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6577 return rs6000_legitimize_tls_address (x
, model
);
6587 /* As in legitimate_offset_address_p we do not assume
6588 worst-case. The mode here is just a hint as to the registers
6589 used. A TImode is usually in gprs, but may actually be in
6590 fprs. Leave worst-case scenario for reload to handle via
6591 insn constraints. PTImode is only GPRs. */
6598 if (GET_CODE (x
) == PLUS
6599 && GET_CODE (XEXP (x
, 0)) == REG
6600 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6601 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6603 && !(SPE_VECTOR_MODE (mode
)
6604 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6606 HOST_WIDE_INT high_int
, low_int
;
6608 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6609 if (low_int
>= 0x8000 - extra
)
6611 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6612 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6613 GEN_INT (high_int
)), 0);
6614 return plus_constant (Pmode
, sum
, low_int
);
6616 else if (GET_CODE (x
) == PLUS
6617 && GET_CODE (XEXP (x
, 0)) == REG
6618 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6619 && GET_MODE_NUNITS (mode
) == 1
6620 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6621 || (/* ??? Assume floating point reg based on mode? */
6622 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6623 && (mode
== DFmode
|| mode
== DDmode
)))
6624 && !avoiding_indexed_address_p (mode
))
6626 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6627 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6629 else if (SPE_VECTOR_MODE (mode
)
6630 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6634 /* We accept [reg + reg] and [reg + OFFSET]. */
6636 if (GET_CODE (x
) == PLUS
)
6638 rtx op1
= XEXP (x
, 0);
6639 rtx op2
= XEXP (x
, 1);
6642 op1
= force_reg (Pmode
, op1
);
6644 if (GET_CODE (op2
) != REG
6645 && (GET_CODE (op2
) != CONST_INT
6646 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6647 || (GET_MODE_SIZE (mode
) > 8
6648 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6649 op2
= force_reg (Pmode
, op2
);
6651 /* We can't always do [reg + reg] for these, because [reg +
6652 reg + offset] is not a legitimate addressing mode. */
6653 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
6655 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
6656 return force_reg (Pmode
, y
);
6661 return force_reg (Pmode
, x
);
6663 else if ((TARGET_ELF
6665 || !MACHO_DYNAMIC_NO_PIC_P
6671 && GET_CODE (x
) != CONST_INT
6672 && GET_CODE (x
) != CONST_DOUBLE
6674 && GET_MODE_NUNITS (mode
) == 1
6675 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6676 || (/* ??? Assume floating point reg based on mode? */
6677 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6678 && (mode
== DFmode
|| mode
== DDmode
))))
6680 rtx reg
= gen_reg_rtx (Pmode
);
6682 emit_insn (gen_elf_high (reg
, x
));
6684 emit_insn (gen_macho_high (reg
, x
));
6685 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
6688 && GET_CODE (x
) == SYMBOL_REF
6689 && constant_pool_expr_p (x
)
6690 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
6691 return create_TOC_reference (x
, NULL_RTX
);
6696 /* Debug version of rs6000_legitimize_address. */
6698 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
6704 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
6705 insns
= get_insns ();
6711 "\nrs6000_legitimize_address: mode %s, old code %s, "
6712 "new code %s, modified\n",
6713 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
6714 GET_RTX_NAME (GET_CODE (ret
)));
6716 fprintf (stderr
, "Original address:\n");
6719 fprintf (stderr
, "oldx:\n");
6722 fprintf (stderr
, "New address:\n");
6727 fprintf (stderr
, "Insns added:\n");
6728 debug_rtx_list (insns
, 20);
6734 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6735 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
6746 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6747 We need to emit DTP-relative relocations. */
6749 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6751 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6756 fputs ("\t.long\t", file
);
6759 fputs (DOUBLE_INT_ASM_OP
, file
);
6764 output_addr_const (file
, x
);
6765 fputs ("@dtprel+0x8000", file
);
6768 /* In the name of slightly smaller debug output, and to cater to
6769 general assembler lossage, recognize various UNSPEC sequences
6770 and turn them back into a direct symbol reference. */
6773 rs6000_delegitimize_address (rtx orig_x
)
6777 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6783 if (TARGET_CMODEL
!= CMODEL_SMALL
6784 && GET_CODE (y
) == LO_SUM
)
6788 if (GET_CODE (y
) == PLUS
6789 && GET_MODE (y
) == Pmode
6790 && CONST_INT_P (XEXP (y
, 1)))
6792 offset
= XEXP (y
, 1);
6796 if (GET_CODE (y
) == UNSPEC
6797 && XINT (y
, 1) == UNSPEC_TOCREL
)
6799 #ifdef ENABLE_CHECKING
6800 if (REG_P (XVECEXP (y
, 0, 1))
6801 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
6805 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
6807 /* Weirdness alert. df_note_compute can replace r2 with a
6808 debug_expr when this unspec is in a debug_insn.
6809 Seen in gcc.dg/pr51957-1.c */
6817 y
= XVECEXP (y
, 0, 0);
6820 /* Do not associate thread-local symbols with the original
6821 constant pool symbol. */
6823 && GET_CODE (y
) == SYMBOL_REF
6824 && CONSTANT_POOL_ADDRESS_P (y
)
6825 && SYMBOL_REF_TLS_MODEL (get_pool_constant (y
)) >= TLS_MODEL_REAL
)
6829 if (offset
!= NULL_RTX
)
6830 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
6831 if (!MEM_P (orig_x
))
6834 return replace_equiv_address_nv (orig_x
, y
);
6838 && GET_CODE (orig_x
) == LO_SUM
6839 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
6841 y
= XEXP (XEXP (orig_x
, 1), 0);
6842 if (GET_CODE (y
) == UNSPEC
6843 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
6844 return XVECEXP (y
, 0, 0);
6850 /* Return true if X shouldn't be emitted into the debug info.
6851 The linker doesn't like .toc section references from
6852 .debug_* sections, so reject .toc section symbols. */
6855 rs6000_const_not_ok_for_debug_p (rtx x
)
6857 if (GET_CODE (x
) == SYMBOL_REF
6858 && CONSTANT_POOL_ADDRESS_P (x
))
6860 rtx c
= get_pool_constant (x
);
6861 enum machine_mode cmode
= get_pool_mode (x
);
6862 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
6869 /* Construct the SYMBOL_REF for the tls_get_addr function. */
6871 static GTY(()) rtx rs6000_tls_symbol
;
6873 rs6000_tls_get_addr (void)
6875 if (!rs6000_tls_symbol
)
6876 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
6878 return rs6000_tls_symbol
;
6881 /* Construct the SYMBOL_REF for TLS GOT references. */
6883 static GTY(()) rtx rs6000_got_symbol
;
6885 rs6000_got_sym (void)
6887 if (!rs6000_got_symbol
)
6889 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
6890 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
6891 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
6894 return rs6000_got_symbol
;
6897 /* AIX Thread-Local Address support. */
6900 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
6902 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
6906 name
= XSTR (addr
, 0);
6907 /* Append TLS CSECT qualifier, unless the symbol already is qualified
6908 or the symbol will be in TLS private data section. */
6909 if (name
[strlen (name
) - 1] != ']'
6910 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
6911 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
6913 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
6914 strcpy (tlsname
, name
);
6916 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
6917 tlsaddr
= copy_rtx (addr
);
6918 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
6923 /* Place addr into TOC constant pool. */
6924 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
6926 /* Output the TOC entry and create the MEM referencing the value. */
6927 if (constant_pool_expr_p (XEXP (sym
, 0))
6928 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
6930 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
6931 mem
= gen_const_mem (Pmode
, tocref
);
6932 set_mem_alias_set (mem
, get_TOC_alias_set ());
6937 /* Use global-dynamic for local-dynamic. */
6938 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
6939 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
6941 /* Create new TOC reference for @m symbol. */
6942 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
6943 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
6944 strcpy (tlsname
, "*LCM");
6945 strcat (tlsname
, name
+ 3);
6946 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
6947 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
6948 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
6949 rtx modmem
= gen_const_mem (Pmode
, tocref
);
6950 set_mem_alias_set (modmem
, get_TOC_alias_set ());
6952 rtx modreg
= gen_reg_rtx (Pmode
);
6953 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
6955 tmpreg
= gen_reg_rtx (Pmode
);
6956 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6958 dest
= gen_reg_rtx (Pmode
);
6960 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
6962 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
6965 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
6966 else if (TARGET_32BIT
)
6968 tlsreg
= gen_reg_rtx (SImode
);
6969 emit_insn (gen_tls_get_tpointer (tlsreg
));
6972 tlsreg
= gen_rtx_REG (DImode
, 13);
6974 /* Load the TOC value into temporary register. */
6975 tmpreg
= gen_reg_rtx (Pmode
);
6976 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6977 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
6978 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
6980 /* Add TOC symbol value to TLS pointer. */
6981 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
6986 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
6987 this (thread-local) address. */
6990 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
6995 return rs6000_legitimize_tls_address_aix (addr
, model
);
6997 dest
= gen_reg_rtx (Pmode
);
6998 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
7004 tlsreg
= gen_rtx_REG (Pmode
, 13);
7005 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
7009 tlsreg
= gen_rtx_REG (Pmode
, 2);
7010 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
7014 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
7018 tmp
= gen_reg_rtx (Pmode
);
7021 tlsreg
= gen_rtx_REG (Pmode
, 13);
7022 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
7026 tlsreg
= gen_rtx_REG (Pmode
, 2);
7027 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
7031 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
7033 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
7038 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
7040 /* We currently use relocations like @got@tlsgd for tls, which
7041 means the linker will handle allocation of tls entries, placing
7042 them in the .got section. So use a pointer to the .got section,
7043 not one to secondary TOC sections used by 64-bit -mminimal-toc,
7044 or to secondary GOT sections used by 32-bit -fPIC. */
7046 got
= gen_rtx_REG (Pmode
, 2);
7050 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
7053 rtx gsym
= rs6000_got_sym ();
7054 got
= gen_reg_rtx (Pmode
);
7056 rs6000_emit_move (got
, gsym
, Pmode
);
7061 tmp1
= gen_reg_rtx (Pmode
);
7062 tmp2
= gen_reg_rtx (Pmode
);
7063 mem
= gen_const_mem (Pmode
, tmp1
);
7064 lab
= gen_label_rtx ();
7065 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
7066 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
7067 if (TARGET_LINK_STACK
)
7068 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
7069 emit_move_insn (tmp2
, mem
);
7070 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
7071 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
7076 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
7078 tga
= rs6000_tls_get_addr ();
7079 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
7080 1, const0_rtx
, Pmode
);
7082 r3
= gen_rtx_REG (Pmode
, 3);
7083 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7086 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
7088 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
7090 else if (DEFAULT_ABI
== ABI_V4
)
7091 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
7094 call_insn
= last_call_insn ();
7095 PATTERN (call_insn
) = insn
;
7096 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7097 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7098 pic_offset_table_rtx
);
7100 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
7102 tga
= rs6000_tls_get_addr ();
7103 tmp1
= gen_reg_rtx (Pmode
);
7104 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7105 1, const0_rtx
, Pmode
);
7107 r3
= gen_rtx_REG (Pmode
, 3);
7108 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7111 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7113 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7115 else if (DEFAULT_ABI
== ABI_V4
)
7116 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7119 call_insn
= last_call_insn ();
7120 PATTERN (call_insn
) = insn
;
7121 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7122 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7123 pic_offset_table_rtx
);
7125 if (rs6000_tls_size
== 16)
7128 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7130 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7132 else if (rs6000_tls_size
== 32)
7134 tmp2
= gen_reg_rtx (Pmode
);
7136 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7138 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7141 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7143 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7147 tmp2
= gen_reg_rtx (Pmode
);
7149 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7151 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7153 insn
= gen_rtx_SET (Pmode
, dest
,
7154 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7160 /* IE, or 64-bit offset LE. */
7161 tmp2
= gen_reg_rtx (Pmode
);
7163 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7165 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7168 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7170 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
7178 /* Return 1 if X contains a thread-local symbol. */
7181 rs6000_tls_referenced_p (rtx x
)
7183 if (! TARGET_HAVE_TLS
)
7186 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
7189 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7192 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7194 if (GET_CODE (x
) == HIGH
7195 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
7198 /* A TLS symbol in the TOC cannot contain a sum. */
7199 if (GET_CODE (x
) == CONST
7200 && GET_CODE (XEXP (x
, 0)) == PLUS
7201 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
7202 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
7205 /* Do not place an ELF TLS symbol in the constant pool. */
7206 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
7209 /* Return 1 if *X is a thread-local symbol. This is the same as
7210 rs6000_tls_symbol_ref except for the type of the unused argument. */
7213 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7215 return RS6000_SYMBOL_REF_TLS_P (*x
);
7218 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7219 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7220 can be addressed relative to the toc pointer. */
7223 use_toc_relative_ref (rtx sym
)
7225 return ((constant_pool_expr_p (sym
)
7226 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
7227 get_pool_mode (sym
)))
7228 || (TARGET_CMODEL
== CMODEL_MEDIUM
7229 && SYMBOL_REF_LOCAL_P (sym
)));
7232 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7233 replace the input X, or the original X if no replacement is called for.
7234 The output parameter *WIN is 1 if the calling macro should goto WIN,
7237 For RS/6000, we wish to handle large displacements off a base
7238 register by splitting the addend across an addiu/addis and the mem insn.
7239 This cuts number of extra insns needed from 3 to 1.
7241 On Darwin, we use this to generate code for floating point constants.
7242 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7243 The Darwin code is inside #if TARGET_MACHO because only then are the
7244 machopic_* functions defined. */
7246 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7247 int opnum
, int type
,
7248 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
7250 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7252 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7253 DFmode/DImode MEM. */
7256 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
7257 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
7258 reg_offset_p
= false;
7260 /* We must recognize output that we have already generated ourselves. */
7261 if (GET_CODE (x
) == PLUS
7262 && GET_CODE (XEXP (x
, 0)) == PLUS
7263 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7264 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7265 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7267 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7268 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7269 opnum
, (enum reload_type
) type
);
7274 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7275 if (GET_CODE (x
) == LO_SUM
7276 && GET_CODE (XEXP (x
, 0)) == HIGH
)
7278 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7279 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7280 opnum
, (enum reload_type
) type
);
7286 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
7287 && GET_CODE (x
) == LO_SUM
7288 && GET_CODE (XEXP (x
, 0)) == PLUS
7289 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
7290 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
7291 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
7292 && machopic_operand_p (XEXP (x
, 1)))
7294 /* Result of previous invocation of this function on Darwin
7295 floating point constant. */
7296 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7297 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7298 opnum
, (enum reload_type
) type
);
7304 if (TARGET_CMODEL
!= CMODEL_SMALL
7306 && small_toc_ref (x
, VOIDmode
))
7308 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
7309 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
7310 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7311 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7312 opnum
, (enum reload_type
) type
);
7317 if (GET_CODE (x
) == PLUS
7318 && GET_CODE (XEXP (x
, 0)) == REG
7319 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
7320 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
7321 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7323 && !SPE_VECTOR_MODE (mode
)
7324 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7325 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
7327 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
7328 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
7330 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7332 /* Check for 32-bit overflow. */
7333 if (high
+ low
!= val
)
7339 /* Reload the high part into a base reg; leave the low part
7340 in the mem directly. */
7342 x
= gen_rtx_PLUS (GET_MODE (x
),
7343 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
7347 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7348 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7349 opnum
, (enum reload_type
) type
);
7354 if (GET_CODE (x
) == SYMBOL_REF
7356 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
7357 && !SPE_VECTOR_MODE (mode
)
7359 && DEFAULT_ABI
== ABI_DARWIN
7360 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
7361 && machopic_symbol_defined_p (x
)
7363 && DEFAULT_ABI
== ABI_V4
7366 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7367 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7369 ??? Assume floating point reg based on mode? This assumption is
7370 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7371 where reload ends up doing a DFmode load of a constant from
7372 mem using two gprs. Unfortunately, at this point reload
7373 hasn't yet selected regs so poking around in reload data
7374 won't help and even if we could figure out the regs reliably,
7375 we'd still want to allow this transformation when the mem is
7376 naturally aligned. Since we say the address is good here, we
7377 can't disable offsets from LO_SUMs in mem_operand_gpr.
7378 FIXME: Allow offset from lo_sum for other modes too, when
7379 mem is sufficiently aligned. */
7382 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
7384 && (mode
!= DImode
|| TARGET_POWERPC64
)
7385 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
7386 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
7391 rtx offset
= machopic_gen_offset (x
);
7392 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7393 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
7394 gen_rtx_HIGH (Pmode
, offset
)), offset
);
7398 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7399 gen_rtx_HIGH (Pmode
, x
), x
);
7401 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7402 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7403 opnum
, (enum reload_type
) type
);
7408 /* Reload an offset address wrapped by an AND that represents the
7409 masking of the lower bits. Strip the outer AND and let reload
7410 convert the offset address into an indirect address. For VSX,
7411 force reload to create the address with an AND in a separate
7412 register, because we can't guarantee an altivec register will
7414 if (VECTOR_MEM_ALTIVEC_P (mode
)
7415 && GET_CODE (x
) == AND
7416 && GET_CODE (XEXP (x
, 0)) == PLUS
7417 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7418 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7419 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7420 && INTVAL (XEXP (x
, 1)) == -16)
7429 && GET_CODE (x
) == SYMBOL_REF
7430 && use_toc_relative_ref (x
))
7432 x
= create_TOC_reference (x
, NULL_RTX
);
7433 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7434 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7435 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7436 opnum
, (enum reload_type
) type
);
7444 /* Debug version of rs6000_legitimize_reload_address. */
7446 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7447 int opnum
, int type
,
7448 int ind_levels
, int *win
)
7450 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7453 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7454 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7455 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7459 fprintf (stderr
, "Same address returned\n");
7461 fprintf (stderr
, "NULL returned\n");
7464 fprintf (stderr
, "New address:\n");
7471 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7472 that is a valid memory address for an instruction.
7473 The MODE argument is the machine mode for the MEM expression
7474 that wants to use this address.
7476 On the RS/6000, there are four valid address: a SYMBOL_REF that
7477 refers to a constant pool entry of an address (or the sum of it
7478 plus a constant), a short (16-bit signed) constant plus a register,
7479 the sum of two registers, or a register indirect, possibly with an
7480 auto-increment. For DFmode, DDmode and DImode with a constant plus
7481 register, we must ensure that both words are addressable or PowerPC64
7482 with offset word aligned.
7484 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7485 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7486 because adjacent memory cells are accessed by adding word-sized offsets
7487 during assembly output. */
7489 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
7491 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7493 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7494 if (VECTOR_MEM_ALTIVEC_P (mode
)
7495 && GET_CODE (x
) == AND
7496 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7497 && INTVAL (XEXP (x
, 1)) == -16)
7500 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7502 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7505 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7506 && mode_supports_pre_incdec_p (mode
)
7507 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7509 if (virtual_stack_registers_memory_p (x
))
7511 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7514 && legitimate_constant_pool_address_p (x
, mode
,
7515 reg_ok_strict
|| lra_in_progress
))
7517 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7518 allow register indirect addresses. This will allow the values to go in
7519 either GPRs or VSX registers without reloading. The vector types would
7520 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7521 somewhat split, in that some uses are GPR based, and some VSX based. */
7522 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
7524 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7527 && GET_CODE (x
) == PLUS
7528 && GET_CODE (XEXP (x
, 0)) == REG
7529 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7530 || XEXP (x
, 0) == arg_pointer_rtx
)
7531 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7533 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7537 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7539 || (mode
!= DFmode
&& mode
!= DDmode
)
7540 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7541 && (TARGET_POWERPC64
|| mode
!= DImode
)
7542 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7544 && !avoiding_indexed_address_p (mode
)
7545 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7547 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
7548 && mode_supports_pre_modify_p (mode
)
7549 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7550 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7551 reg_ok_strict
, false)
7552 || (!avoiding_indexed_address_p (mode
)
7553 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7554 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7556 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7561 /* Debug version of rs6000_legitimate_address_p. */
7563 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
7566 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7568 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7569 "strict = %d, reload = %s, code = %s\n",
7570 ret
? "true" : "false",
7571 GET_MODE_NAME (mode
),
7575 : (reload_in_progress
? "progress" : "before")),
7576 GET_RTX_NAME (GET_CODE (x
)));
7582 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7585 rs6000_mode_dependent_address_p (const_rtx addr
,
7586 addr_space_t as ATTRIBUTE_UNUSED
)
7588 return rs6000_mode_dependent_address_ptr (addr
);
7591 /* Go to LABEL if ADDR (a legitimate address expression)
7592 has an effect that depends on the machine mode it is used for.
7594 On the RS/6000 this is true of all integral offsets (since AltiVec
7595 and VSX modes don't allow them) or is a pre-increment or decrement.
7597 ??? Except that due to conceptual problems in offsettable_address_p
7598 we can't really report the problems of integral offsets. So leave
7599 this assuming that the adjustable offset must be valid for the
7600 sub-words of a TFmode operand, which is what we had before. */
7603 rs6000_mode_dependent_address (const_rtx addr
)
7605 switch (GET_CODE (addr
))
7608 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7609 is considered a legitimate address before reload, so there
7610 are no offset restrictions in that case. Note that this
7611 condition is safe in strict mode because any address involving
7612 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7613 been rejected as illegitimate. */
7614 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7615 && XEXP (addr
, 0) != arg_pointer_rtx
7616 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7618 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7619 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7624 /* Anything in the constant pool is sufficiently aligned that
7625 all bytes have the same high part address. */
7626 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7628 /* Auto-increment cases are now treated generically in recog.c. */
7630 return TARGET_UPDATE
;
7632 /* AND is only allowed in Altivec loads. */
7643 /* Debug version of rs6000_mode_dependent_address. */
7645 rs6000_debug_mode_dependent_address (const_rtx addr
)
7647 bool ret
= rs6000_mode_dependent_address (addr
);
7649 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7650 ret
? "true" : "false");
7656 /* Implement FIND_BASE_TERM. */
7659 rs6000_find_base_term (rtx op
)
7664 if (GET_CODE (base
) == CONST
)
7665 base
= XEXP (base
, 0);
7666 if (GET_CODE (base
) == PLUS
)
7667 base
= XEXP (base
, 0);
7668 if (GET_CODE (base
) == UNSPEC
)
7669 switch (XINT (base
, 1))
7672 case UNSPEC_MACHOPIC_OFFSET
:
7673 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7674 for aliasing purposes. */
7675 return XVECEXP (base
, 0, 0);
7681 /* More elaborate version of recog's offsettable_memref_p predicate
7682 that works around the ??? note of rs6000_mode_dependent_address.
7683 In particular it accepts
7685 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7687 in 32-bit mode, that the recog predicate rejects. */
7690 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
7697 /* First mimic offsettable_memref_p. */
7698 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
7701 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7702 the latter predicate knows nothing about the mode of the memory
7703 reference and, therefore, assumes that it is the largest supported
7704 mode (TFmode). As a consequence, legitimate offsettable memory
7705 references are rejected. rs6000_legitimate_offset_address_p contains
7706 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7707 at least with a little bit of help here given that we know the
7708 actual registers used. */
7709 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
7710 || GET_MODE_SIZE (reg_mode
) == 4);
7711 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
7715 /* Change register usage conditional on target flags. */
7717 rs6000_conditional_register_usage (void)
7721 if (TARGET_DEBUG_TARGET
)
7722 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
7724 /* Set MQ register fixed (already call_used) so that it will not be
7728 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7730 fixed_regs
[13] = call_used_regs
[13]
7731 = call_really_used_regs
[13] = 1;
7733 /* Conditionally disable FPRs. */
7734 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
7735 for (i
= 32; i
< 64; i
++)
7736 fixed_regs
[i
] = call_used_regs
[i
]
7737 = call_really_used_regs
[i
] = 1;
7739 /* The TOC register is not killed across calls in a way that is
7740 visible to the compiler. */
7741 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7742 call_really_used_regs
[2] = 0;
7744 if (DEFAULT_ABI
== ABI_V4
7745 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7747 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7749 if (DEFAULT_ABI
== ABI_V4
7750 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7752 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7753 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7754 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7756 if (DEFAULT_ABI
== ABI_DARWIN
7757 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
7758 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7759 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7760 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7762 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
7763 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7764 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7768 global_regs
[SPEFSCR_REGNO
] = 1;
7769 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7770 registers in prologues and epilogues. We no longer use r14
7771 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7772 pool for link-compatibility with older versions of GCC. Once
7773 "old" code has died out, we can return r14 to the allocation
7776 = call_used_regs
[14]
7777 = call_really_used_regs
[14] = 1;
7780 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
7782 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
7783 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7784 call_really_used_regs
[VRSAVE_REGNO
] = 1;
7787 if (TARGET_ALTIVEC
|| TARGET_VSX
)
7788 global_regs
[VSCR_REGNO
] = 1;
7790 if (TARGET_ALTIVEC_ABI
)
7792 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
7793 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7795 /* AIX reserves VR20:31 in non-extended ABI mode. */
7797 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
7798 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7803 /* Try to output insns to set TARGET equal to the constant C if it can
7804 be done in less than N insns. Do all computations in MODE.
7805 Returns the place where the output has been placed if it can be
7806 done and the insns have been emitted. If it would take more than N
7807 insns, zero is returned and no insns and emitted. */
7810 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
7811 rtx source
, int n ATTRIBUTE_UNUSED
)
7813 rtx result
, insn
, set
;
7814 HOST_WIDE_INT c0
, c1
;
7821 dest
= gen_reg_rtx (mode
);
7822 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
7826 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
7828 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
7829 GEN_INT (INTVAL (source
)
7830 & (~ (HOST_WIDE_INT
) 0xffff))));
7831 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
7832 gen_rtx_IOR (SImode
, copy_rtx (result
),
7833 GEN_INT (INTVAL (source
) & 0xffff))));
7838 switch (GET_CODE (source
))
7841 c0
= INTVAL (source
);
7849 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
7856 insn
= get_last_insn ();
7857 set
= single_set (insn
);
7858 if (! CONSTANT_P (SET_SRC (set
)))
7859 set_unique_reg_note (insn
, REG_EQUAL
, source
);
7864 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
7865 fall back to a straight forward decomposition. We do this to avoid
7866 exponential run times encountered when looking for longer sequences
7867 with rs6000_emit_set_const. */
7869 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
7871 if (!TARGET_POWERPC64
)
7873 rtx operand1
, operand2
;
7875 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
7877 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
7879 emit_move_insn (operand1
, GEN_INT (c1
));
7880 emit_move_insn (operand2
, GEN_INT (c2
));
7884 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
7887 ud2
= (c1
& 0xffff0000) >> 16;
7890 ud4
= (c2
& 0xffff0000) >> 16;
7892 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
7893 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
7894 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
7896 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
7897 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
7899 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7902 emit_move_insn (copy_rtx (dest
),
7903 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7906 else if (ud3
== 0 && ud4
== 0)
7908 gcc_assert (ud2
& 0x8000);
7909 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7912 emit_move_insn (copy_rtx (dest
),
7913 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7915 emit_move_insn (copy_rtx (dest
),
7916 gen_rtx_ZERO_EXTEND (DImode
,
7917 gen_lowpart (SImode
,
7920 else if ((ud4
== 0xffff && (ud3
& 0x8000))
7921 || (ud4
== 0 && ! (ud3
& 0x8000)))
7923 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
7926 emit_move_insn (copy_rtx (dest
),
7927 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7929 emit_move_insn (copy_rtx (dest
),
7930 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7933 emit_move_insn (copy_rtx (dest
),
7934 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7939 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
7942 emit_move_insn (copy_rtx (dest
),
7943 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7946 emit_move_insn (copy_rtx (dest
),
7947 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7950 emit_move_insn (copy_rtx (dest
),
7951 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7952 GEN_INT (ud2
<< 16)));
7954 emit_move_insn (copy_rtx (dest
),
7955 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7962 /* Helper for the following. Get rid of [r+r] memory refs
7963 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
7966 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
7968 if (reload_in_progress
)
7971 if (GET_CODE (operands
[0]) == MEM
7972 && GET_CODE (XEXP (operands
[0], 0)) != REG
7973 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
7974 GET_MODE (operands
[0]), false))
7976 = replace_equiv_address (operands
[0],
7977 copy_addr_to_reg (XEXP (operands
[0], 0)));
7979 if (GET_CODE (operands
[1]) == MEM
7980 && GET_CODE (XEXP (operands
[1], 0)) != REG
7981 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
7982 GET_MODE (operands
[1]), false))
7984 = replace_equiv_address (operands
[1],
7985 copy_addr_to_reg (XEXP (operands
[1], 0)));
7988 /* Generate a vector of constants to permute MODE for a little-endian
7989 storage operation by swapping the two halves of a vector. */
7991 rs6000_const_vec (enum machine_mode mode
)
8019 v
= rtvec_alloc (subparts
);
8021 for (i
= 0; i
< subparts
/ 2; ++i
)
8022 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
8023 for (i
= subparts
/ 2; i
< subparts
; ++i
)
8024 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
8029 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
8030 for a VSX load or store operation. */
8032 rs6000_gen_le_vsx_permute (rtx source
, enum machine_mode mode
)
8034 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
8035 return gen_rtx_VEC_SELECT (mode
, source
, par
);
8038 /* Emit a little-endian load from vector memory location SOURCE to VSX
8039 register DEST in mode MODE. The load is done with two permuting
8040 insn's that represent an lxvd2x and xxpermdi. */
8042 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, enum machine_mode mode
)
8044 rtx tmp
, permute_mem
, permute_reg
;
8046 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8048 if (mode
== TImode
|| mode
== V1TImode
)
8051 dest
= gen_lowpart (V2DImode
, dest
);
8052 source
= adjust_address (source
, V2DImode
, 0);
8055 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
8056 permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
8057 permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8058 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_mem
));
8059 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_reg
));
8062 /* Emit a little-endian store to vector memory location DEST from VSX
8063 register SOURCE in mode MODE. The store is done with two permuting
8064 insn's that represent an xxpermdi and an stxvd2x. */
8066 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, enum machine_mode mode
)
8068 rtx tmp
, permute_src
, permute_tmp
;
8070 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8072 if (mode
== TImode
|| mode
== V1TImode
)
8075 dest
= adjust_address (dest
, V2DImode
, 0);
8076 source
= gen_lowpart (V2DImode
, source
);
8079 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
8080 permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
8081 permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8082 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_src
));
8083 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_tmp
));
8086 /* Emit a sequence representing a little-endian VSX load or store,
8087 moving data from SOURCE to DEST in mode MODE. This is done
8088 separately from rs6000_emit_move to ensure it is called only
8089 during expand. LE VSX loads and stores introduced later are
8090 handled with a split. The expand-time RTL generation allows
8091 us to optimize away redundant pairs of register-permutes. */
8093 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, enum machine_mode mode
)
8095 gcc_assert (!BYTES_BIG_ENDIAN
8096 && VECTOR_MEM_VSX_P (mode
)
8097 && !gpr_or_gpr_p (dest
, source
)
8098 && (MEM_P (source
) ^ MEM_P (dest
)));
8102 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
8103 rs6000_emit_le_vsx_load (dest
, source
, mode
);
8107 if (!REG_P (source
))
8108 source
= force_reg (mode
, source
);
8109 rs6000_emit_le_vsx_store (dest
, source
, mode
);
8113 /* Emit a move from SOURCE to DEST in mode MODE. */
8115 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
8119 operands
[1] = source
;
8121 if (TARGET_DEBUG_ADDR
)
8124 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8125 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8126 GET_MODE_NAME (mode
),
8129 can_create_pseudo_p ());
8131 fprintf (stderr
, "source:\n");
8135 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8136 if (GET_CODE (operands
[1]) == CONST_DOUBLE
8137 && ! FLOAT_MODE_P (mode
)
8138 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8140 /* FIXME. This should never happen. */
8141 /* Since it seems that it does, do the safe thing and convert
8143 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
8145 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
8146 || FLOAT_MODE_P (mode
)
8147 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
8148 || CONST_DOUBLE_LOW (operands
[1]) < 0)
8149 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
8150 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
8152 /* Check if GCC is setting up a block move that will end up using FP
8153 registers as temporaries. We must make sure this is acceptable. */
8154 if (GET_CODE (operands
[0]) == MEM
8155 && GET_CODE (operands
[1]) == MEM
8157 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8158 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8159 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8160 ? 32 : MEM_ALIGN (operands
[0])))
8161 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8163 : MEM_ALIGN (operands
[1]))))
8164 && ! MEM_VOLATILE_P (operands
[0])
8165 && ! MEM_VOLATILE_P (operands
[1]))
8167 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8168 adjust_address (operands
[1], SImode
, 0));
8169 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8170 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8174 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8175 && !gpc_reg_operand (operands
[1], mode
))
8176 operands
[1] = force_reg (mode
, operands
[1]);
8178 /* Recognize the case where operand[1] is a reference to thread-local
8179 data and load its address to a register. */
8180 if (rs6000_tls_referenced_p (operands
[1]))
8182 enum tls_model model
;
8183 rtx tmp
= operands
[1];
8186 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8188 addend
= XEXP (XEXP (tmp
, 0), 1);
8189 tmp
= XEXP (XEXP (tmp
, 0), 0);
8192 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8193 model
= SYMBOL_REF_TLS_MODEL (tmp
);
8194 gcc_assert (model
!= 0);
8196 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
8199 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
8200 tmp
= force_operand (tmp
, operands
[0]);
8205 /* Handle the case where reload calls us with an invalid address. */
8206 if (reload_in_progress
&& mode
== Pmode
8207 && (! general_operand (operands
[1], mode
)
8208 || ! nonimmediate_operand (operands
[0], mode
)))
8211 /* 128-bit constant floating-point values on Darwin should really be
8212 loaded as two parts. */
8213 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
8214 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
8216 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
8217 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
8219 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
8220 GET_MODE_SIZE (DFmode
)),
8221 simplify_gen_subreg (DFmode
, operands
[1], mode
,
8222 GET_MODE_SIZE (DFmode
)),
8227 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
8228 cfun
->machine
->sdmode_stack_slot
=
8229 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
8234 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8235 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8236 && (REG_P (operands
[1])
8237 || (GET_CODE (operands
[1]) == SUBREG
8238 && REG_P (SUBREG_REG (operands
[1])))))
8240 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
8241 ? SUBREG_REG (operands
[1]) : operands
[1]);
8244 if (regno
>= FIRST_PSEUDO_REGISTER
)
8246 cl
= reg_preferred_class (regno
);
8247 gcc_assert (cl
!= NO_REGS
);
8248 regno
= ira_class_hard_regs
[cl
][0];
8250 if (FP_REGNO_P (regno
))
8252 if (GET_MODE (operands
[0]) != DDmode
)
8253 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
8254 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
8256 else if (INT_REGNO_P (regno
))
8257 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8264 && (REG_P (operands
[0])
8265 || (GET_CODE (operands
[0]) == SUBREG
8266 && REG_P (SUBREG_REG (operands
[0]))))
8267 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8268 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8270 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
8271 ? SUBREG_REG (operands
[0]) : operands
[0]);
8274 if (regno
>= FIRST_PSEUDO_REGISTER
)
8276 cl
= reg_preferred_class (regno
);
8277 gcc_assert (cl
!= NO_REGS
);
8278 regno
= ira_class_hard_regs
[cl
][0];
8280 if (FP_REGNO_P (regno
))
8282 if (GET_MODE (operands
[1]) != DDmode
)
8283 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
8284 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
8286 else if (INT_REGNO_P (regno
))
8287 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8293 if (reload_in_progress
8295 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8296 && MEM_P (operands
[0])
8297 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
8298 && REG_P (operands
[1]))
8300 if (FP_REGNO_P (REGNO (operands
[1])))
8302 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
8303 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8304 emit_insn (gen_movsd_store (mem
, operands
[1]));
8306 else if (INT_REGNO_P (REGNO (operands
[1])))
8308 rtx mem
= operands
[0];
8309 if (BYTES_BIG_ENDIAN
)
8310 mem
= adjust_address_nv (mem
, mode
, 4);
8311 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8312 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
8318 if (reload_in_progress
8320 && REG_P (operands
[0])
8321 && MEM_P (operands
[1])
8322 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8323 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
8325 if (FP_REGNO_P (REGNO (operands
[0])))
8327 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
8328 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8329 emit_insn (gen_movsd_load (operands
[0], mem
));
8331 else if (INT_REGNO_P (REGNO (operands
[0])))
8333 rtx mem
= operands
[1];
8334 if (BYTES_BIG_ENDIAN
)
8335 mem
= adjust_address_nv (mem
, mode
, 4);
8336 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8337 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
8344 /* FIXME: In the long term, this switch statement should go away
8345 and be replaced by a sequence of tests based on things like
8351 if (CONSTANT_P (operands
[1])
8352 && GET_CODE (operands
[1]) != CONST_INT
)
8353 operands
[1] = force_const_mem (mode
, operands
[1]);
8358 rs6000_eliminate_indexed_memrefs (operands
);
8365 if (CONSTANT_P (operands
[1])
8366 && ! easy_fp_constant (operands
[1], mode
))
8367 operands
[1] = force_const_mem (mode
, operands
[1]);
8381 if (CONSTANT_P (operands
[1])
8382 && !easy_vector_constant (operands
[1], mode
))
8383 operands
[1] = force_const_mem (mode
, operands
[1]);
8388 /* Use default pattern for address of ELF small data */
8391 && DEFAULT_ABI
== ABI_V4
8392 && (GET_CODE (operands
[1]) == SYMBOL_REF
8393 || GET_CODE (operands
[1]) == CONST
)
8394 && small_data_operand (operands
[1], mode
))
8396 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8400 if (DEFAULT_ABI
== ABI_V4
8401 && mode
== Pmode
&& mode
== SImode
8402 && flag_pic
== 1 && got_operand (operands
[1], mode
))
8404 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
8408 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
8412 && CONSTANT_P (operands
[1])
8413 && GET_CODE (operands
[1]) != HIGH
8414 && GET_CODE (operands
[1]) != CONST_INT
)
8416 rtx target
= (!can_create_pseudo_p ()
8418 : gen_reg_rtx (mode
));
8420 /* If this is a function address on -mcall-aixdesc,
8421 convert it to the address of the descriptor. */
8422 if (DEFAULT_ABI
== ABI_AIX
8423 && GET_CODE (operands
[1]) == SYMBOL_REF
8424 && XSTR (operands
[1], 0)[0] == '.')
8426 const char *name
= XSTR (operands
[1], 0);
8428 while (*name
== '.')
8430 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8431 CONSTANT_POOL_ADDRESS_P (new_ref
)
8432 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
8433 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
8434 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
8435 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
8436 operands
[1] = new_ref
;
8439 if (DEFAULT_ABI
== ABI_DARWIN
)
8442 if (MACHO_DYNAMIC_NO_PIC_P
)
8444 /* Take care of any required data indirection. */
8445 operands
[1] = rs6000_machopic_legitimize_pic_address (
8446 operands
[1], mode
, operands
[0]);
8447 if (operands
[0] != operands
[1])
8448 emit_insn (gen_rtx_SET (VOIDmode
,
8449 operands
[0], operands
[1]));
8453 emit_insn (gen_macho_high (target
, operands
[1]));
8454 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
8458 emit_insn (gen_elf_high (target
, operands
[1]));
8459 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
8463 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8464 and we have put it in the TOC, we just need to make a TOC-relative
8467 && GET_CODE (operands
[1]) == SYMBOL_REF
8468 && use_toc_relative_ref (operands
[1]))
8469 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
8470 else if (mode
== Pmode
8471 && CONSTANT_P (operands
[1])
8472 && GET_CODE (operands
[1]) != HIGH
8473 && ((GET_CODE (operands
[1]) != CONST_INT
8474 && ! easy_fp_constant (operands
[1], mode
))
8475 || (GET_CODE (operands
[1]) == CONST_INT
8476 && (num_insns_constant (operands
[1], mode
)
8477 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
8478 || (GET_CODE (operands
[0]) == REG
8479 && FP_REGNO_P (REGNO (operands
[0]))))
8480 && !toc_relative_expr_p (operands
[1], false)
8481 && (TARGET_CMODEL
== CMODEL_SMALL
8482 || can_create_pseudo_p ()
8483 || (REG_P (operands
[0])
8484 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
8488 /* Darwin uses a special PIC legitimizer. */
8489 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
8492 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
8494 if (operands
[0] != operands
[1])
8495 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8500 /* If we are to limit the number of things we put in the TOC and
8501 this is a symbol plus a constant we can add in one insn,
8502 just put the symbol in the TOC and add the constant. Don't do
8503 this if reload is in progress. */
8504 if (GET_CODE (operands
[1]) == CONST
8505 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
8506 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
8507 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
8508 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
8509 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
8510 && ! side_effects_p (operands
[0]))
8513 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
8514 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
8516 sym
= force_reg (mode
, sym
);
8517 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
8521 operands
[1] = force_const_mem (mode
, operands
[1]);
8524 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
8525 && constant_pool_expr_p (XEXP (operands
[1], 0))
8526 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
8527 get_pool_constant (XEXP (operands
[1], 0)),
8528 get_pool_mode (XEXP (operands
[1], 0))))
8530 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
8532 operands
[1] = gen_const_mem (mode
, tocref
);
8533 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
8539 if (!VECTOR_MEM_VSX_P (TImode
))
8540 rs6000_eliminate_indexed_memrefs (operands
);
8544 rs6000_eliminate_indexed_memrefs (operands
);
8548 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
8551 /* Above, we may have called force_const_mem which may have returned
8552 an invalid address. If we can, fix this up; otherwise, reload will
8553 have to deal with it. */
8554 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
8555 operands
[1] = validize_mem (operands
[1]);
8558 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8561 /* Return true if a structure, union or array containing FIELD should be
8562 accessed using `BLKMODE'.
8564 For the SPE, simd types are V2SI, and gcc can be tempted to put the
8565 entire thing in a DI and use subregs to access the internals.
8566 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
8567 back-end. Because a single GPR can hold a V2SI, but not a DI, the
8568 best thing to do is set structs to BLKmode and avoid Severe Tire
8571 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
8572 fit into 1, whereas DI still needs two. */
8575 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
8577 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
8578 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
8581 /* Nonzero if we can use a floating-point register to pass this arg. */
8582 #define USE_FP_FOR_ARG_P(CUM,MODE) \
8583 (SCALAR_FLOAT_MODE_P (MODE) \
8584 && (CUM)->fregno <= FP_ARG_MAX_REG \
8585 && TARGET_HARD_FLOAT && TARGET_FPRS)
8587 /* Nonzero if we can use an AltiVec register to pass this arg. */
8588 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
8589 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8590 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8591 && TARGET_ALTIVEC_ABI \
8594 /* Walk down the type tree of TYPE counting consecutive base elements.
8595 If *MODEP is VOIDmode, then set it to the first valid floating point
8596 or vector type. If a non-floating point or vector type is found, or
8597 if a floating point or vector type that doesn't match a non-VOIDmode
8598 *MODEP is found, then return -1, otherwise return the count in the
8602 rs6000_aggregate_candidate (const_tree type
, enum machine_mode
*modep
)
8604 enum machine_mode mode
;
8607 switch (TREE_CODE (type
))
8610 mode
= TYPE_MODE (type
);
8611 if (!SCALAR_FLOAT_MODE_P (mode
))
8614 if (*modep
== VOIDmode
)
8623 mode
= TYPE_MODE (TREE_TYPE (type
));
8624 if (!SCALAR_FLOAT_MODE_P (mode
))
8627 if (*modep
== VOIDmode
)
8636 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
8639 /* Use V4SImode as representative of all 128-bit vector types. */
8640 size
= int_size_in_bytes (type
);
8650 if (*modep
== VOIDmode
)
8653 /* Vector modes are considered to be opaque: two vectors are
8654 equivalent for the purposes of being homogeneous aggregates
8655 if they are the same size. */
8664 tree index
= TYPE_DOMAIN (type
);
8666 /* Can't handle incomplete types. */
8667 if (!COMPLETE_TYPE_P (type
))
8670 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
8673 || !TYPE_MAX_VALUE (index
)
8674 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
8675 || !TYPE_MIN_VALUE (index
)
8676 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
8680 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
8681 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
8683 /* There must be no padding. */
8684 if (!tree_fits_uhwi_p (TYPE_SIZE (type
))
8685 || ((HOST_WIDE_INT
) tree_to_uhwi (TYPE_SIZE (type
))
8686 != count
* GET_MODE_BITSIZE (*modep
)))
8698 /* Can't handle incomplete types. */
8699 if (!COMPLETE_TYPE_P (type
))
8702 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8704 if (TREE_CODE (field
) != FIELD_DECL
)
8707 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8713 /* There must be no padding. */
8714 if (!tree_fits_uhwi_p (TYPE_SIZE (type
))
8715 || ((HOST_WIDE_INT
) tree_to_uhwi (TYPE_SIZE (type
))
8716 != count
* GET_MODE_BITSIZE (*modep
)))
8723 case QUAL_UNION_TYPE
:
8725 /* These aren't very interesting except in a degenerate case. */
8730 /* Can't handle incomplete types. */
8731 if (!COMPLETE_TYPE_P (type
))
8734 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8736 if (TREE_CODE (field
) != FIELD_DECL
)
8739 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8742 count
= count
> sub_count
? count
: sub_count
;
8745 /* There must be no padding. */
8746 if (!tree_fits_uhwi_p (TYPE_SIZE (type
))
8747 || ((HOST_WIDE_INT
) tree_to_uhwi (TYPE_SIZE (type
))
8748 != count
* GET_MODE_BITSIZE (*modep
)))
8761 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
8762 float or vector aggregate that shall be passed in FP/vector registers
8763 according to the ELFv2 ABI, return the homogeneous element mode in
8764 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
8766 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
8769 rs6000_discover_homogeneous_aggregate (enum machine_mode mode
, const_tree type
,
8770 enum machine_mode
*elt_mode
,
8773 /* Note that we do not accept complex types at the top level as
8774 homogeneous aggregates; these types are handled via the
8775 targetm.calls.split_complex_arg mechanism. Complex types
8776 can be elements of homogeneous aggregates, however. */
8777 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
8779 enum machine_mode field_mode
= VOIDmode
;
8780 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
8782 if (field_count
> 0)
8784 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
)?
8785 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
8787 /* The ELFv2 ABI allows homogeneous aggregates to occupy
8788 up to AGGR_ARG_NUM_REG registers. */
8789 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
8792 *elt_mode
= field_mode
;
8794 *n_elts
= field_count
;
8807 /* Return a nonzero value to say to return the function value in
8808 memory, just as large structures are always returned. TYPE will be
8809 the data type of the value, and FNTYPE will be the type of the
8810 function doing the returning, or @code{NULL} for libcalls.
8812 The AIX ABI for the RS/6000 specifies that all structures are
8813 returned in memory. The Darwin ABI does the same.
8815 For the Darwin 64 Bit ABI, a function result can be returned in
8816 registers or in memory, depending on the size of the return data
8817 type. If it is returned in registers, the value occupies the same
8818 registers as it would if it were the first and only function
8819 argument. Otherwise, the function places its result in memory at
8820 the location pointed to by GPR3.
8822 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
8823 but a draft put them in memory, and GCC used to implement the draft
8824 instead of the final standard. Therefore, aix_struct_return
8825 controls this instead of DEFAULT_ABI; V.4 targets needing backward
8826 compatibility can change DRAFT_V4_STRUCT_RET to override the
8827 default, and -m switches get the final word. See
8828 rs6000_option_override_internal for more details.
8830 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
8831 long double support is enabled. These values are returned in memory.
8833 int_size_in_bytes returns -1 for variable size objects, which go in
8834 memory always. The cast to unsigned makes -1 > 8. */
8837 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
8839 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
8841 && rs6000_darwin64_abi
8842 && TREE_CODE (type
) == RECORD_TYPE
8843 && int_size_in_bytes (type
) > 0)
8845 CUMULATIVE_ARGS valcum
;
8849 valcum
.fregno
= FP_ARG_MIN_REG
;
8850 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
8851 /* Do a trial code generation as if this were going to be passed
8852 as an argument; if any part goes in memory, we return NULL. */
8853 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
8856 /* Otherwise fall through to more conventional ABI rules. */
8859 #if HAVE_UPC_PTS_STRUCT_REP
8860 if (POINTER_TYPE_P (type
) && upc_shared_type_p (TREE_TYPE (type
)))
8864 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
8865 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
8869 /* The ELFv2 ABI returns aggregates up to 16B in registers */
8870 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
8871 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
8874 if (AGGREGATE_TYPE_P (type
)
8875 && (aix_struct_return
8876 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
8879 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8880 modes only exist for GCC vector types if -maltivec. */
8881 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
8882 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
8885 /* Return synthetic vectors in memory. */
8886 if (TREE_CODE (type
) == VECTOR_TYPE
8887 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8889 static bool warned_for_return_big_vectors
= false;
8890 if (!warned_for_return_big_vectors
)
8892 warning (0, "GCC vector returned by reference: "
8893 "non-standard ABI extension with no compatibility guarantee");
8894 warned_for_return_big_vectors
= true;
8899 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
8905 /* Specify whether values returned in registers should be at the most
8906 significant end of a register. We want aggregates returned by
8907 value to match the way aggregates are passed to functions. */
8910 rs6000_return_in_msb (const_tree valtype
)
8912 return (DEFAULT_ABI
== ABI_ELFv2
8914 && AGGREGATE_TYPE_P (valtype
)
8915 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
8918 #ifdef HAVE_AS_GNU_ATTRIBUTE
8919 /* Return TRUE if a call to function FNDECL may be one that
8920 potentially affects the function calling ABI of the object file. */
8923 call_ABI_of_interest (tree fndecl
)
8925 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
8927 struct cgraph_node
*c_node
;
8929 /* Libcalls are always interesting. */
8930 if (fndecl
== NULL_TREE
)
8933 /* Any call to an external function is interesting. */
8934 if (DECL_EXTERNAL (fndecl
))
8937 /* Interesting functions that we are emitting in this object file. */
8938 c_node
= cgraph_get_node (fndecl
);
8939 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
8940 return !cgraph_only_called_directly_p (c_node
);
8946 /* Initialize a variable CUM of type CUMULATIVE_ARGS
8947 for a call to a function whose data type is FNTYPE.
8948 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
8950 For incoming args we set the number of arguments in the prototype large
8951 so we never return a PARALLEL. */
8954 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
8955 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
8956 int libcall
, int n_named_args
,
8957 tree fndecl ATTRIBUTE_UNUSED
,
8958 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
8960 static CUMULATIVE_ARGS zero_cumulative
;
8962 *cum
= zero_cumulative
;
8964 cum
->fregno
= FP_ARG_MIN_REG
;
8965 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
8966 cum
->prototype
= (fntype
&& prototype_p (fntype
));
8967 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
8968 ? CALL_LIBCALL
: CALL_NORMAL
);
8969 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
8970 cum
->stdarg
= stdarg_p (fntype
);
8972 cum
->nargs_prototype
= 0;
8973 if (incoming
|| cum
->prototype
)
8974 cum
->nargs_prototype
= n_named_args
;
8976 /* Check for a longcall attribute. */
8977 if ((!fntype
&& rs6000_default_long_calls
)
8979 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
8980 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
8981 cum
->call_cookie
|= CALL_LONG
;
8983 if (TARGET_DEBUG_ARG
)
8985 fprintf (stderr
, "\ninit_cumulative_args:");
8988 tree ret_type
= TREE_TYPE (fntype
);
8989 fprintf (stderr
, " ret code = %s,",
8990 get_tree_code_name (TREE_CODE (ret_type
)));
8993 if (cum
->call_cookie
& CALL_LONG
)
8994 fprintf (stderr
, " longcall,");
8996 fprintf (stderr
, " proto = %d, nargs = %d\n",
8997 cum
->prototype
, cum
->nargs_prototype
);
9000 #ifdef HAVE_AS_GNU_ATTRIBUTE
9001 if (DEFAULT_ABI
== ABI_V4
)
9003 cum
->escapes
= call_ABI_of_interest (fndecl
);
9010 return_type
= TREE_TYPE (fntype
);
9011 return_mode
= TYPE_MODE (return_type
);
9014 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
9016 if (return_type
!= NULL
)
9018 if (TREE_CODE (return_type
) == RECORD_TYPE
9019 && TYPE_TRANSPARENT_AGGR (return_type
))
9021 return_type
= TREE_TYPE (first_field (return_type
));
9022 return_mode
= TYPE_MODE (return_type
);
9024 if (AGGREGATE_TYPE_P (return_type
)
9025 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
9027 rs6000_returns_struct
= true;
9029 if (SCALAR_FLOAT_MODE_P (return_mode
))
9030 rs6000_passes_float
= true;
9031 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
9032 || SPE_VECTOR_MODE (return_mode
))
9033 rs6000_passes_vector
= true;
9040 && TARGET_ALTIVEC_ABI
9041 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
9043 error ("cannot return value in vector register because"
9044 " altivec instructions are disabled, use -maltivec"
9049 /* Return true if TYPE must be passed on the stack and not in registers. */
9052 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
9054 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
9055 return must_pass_in_stack_var_size (mode
, type
);
9057 return must_pass_in_stack_var_size_or_pad (mode
, type
);
9060 /* If defined, a C expression which determines whether, and in which
9061 direction, to pad out an argument with extra space. The value
9062 should be of type `enum direction': either `upward' to pad above
9063 the argument, `downward' to pad below, or `none' to inhibit
9066 For the AIX ABI structs are always stored left shifted in their
9070 function_arg_padding (enum machine_mode mode
, const_tree type
)
9072 #ifndef AGGREGATE_PADDING_FIXED
9073 #define AGGREGATE_PADDING_FIXED 0
9075 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
9076 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
9079 if (!AGGREGATE_PADDING_FIXED
)
9081 /* GCC used to pass structures of the same size as integer types as
9082 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
9083 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
9084 passed padded downward, except that -mstrict-align further
9085 muddied the water in that multi-component structures of 2 and 4
9086 bytes in size were passed padded upward.
9088 The following arranges for best compatibility with previous
9089 versions of gcc, but removes the -mstrict-align dependency. */
9090 if (BYTES_BIG_ENDIAN
)
9092 HOST_WIDE_INT size
= 0;
9094 if (mode
== BLKmode
)
9096 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
9097 size
= int_size_in_bytes (type
);
9100 size
= GET_MODE_SIZE (mode
);
9102 if (size
== 1 || size
== 2 || size
== 4)
9108 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
9110 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
9114 /* Fall back to the default. */
9115 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
9118 /* If defined, a C expression that gives the alignment boundary, in bits,
9119 of an argument with the specified mode and type. If it is not defined,
9120 PARM_BOUNDARY is used for all arguments.
9122 V.4 wants long longs and doubles to be double word aligned. Just
9123 testing the mode size is a boneheaded way to do this as it means
9124 that other types such as complex int are also double word aligned.
9125 However, we're stuck with this because changing the ABI might break
9126 existing library interfaces.
9128 Doubleword align SPE vectors.
9129 Quadword align Altivec/VSX vectors.
9130 Quadword align large synthetic vector types. */
9133 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
9135 enum machine_mode elt_mode
;
9138 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9140 if (DEFAULT_ABI
== ABI_V4
9141 && (GET_MODE_SIZE (mode
) == 8
9142 || (TARGET_HARD_FLOAT
9144 && (mode
== TFmode
|| mode
== TDmode
))))
9146 else if (SPE_VECTOR_MODE (mode
)
9147 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9148 && int_size_in_bytes (type
) >= 8
9149 && int_size_in_bytes (type
) < 16))
9151 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9152 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9153 && int_size_in_bytes (type
) >= 16))
9155 else if (((TARGET_MACHO
&& rs6000_darwin64_abi
)
9156 || DEFAULT_ABI
== ABI_ELFv2
9157 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
9159 && type
&& TYPE_ALIGN (type
) > 64)
9162 return PARM_BOUNDARY
;
9165 /* The offset in words to the start of the parameter save area. */
9168 rs6000_parm_offset (void)
9170 return (DEFAULT_ABI
== ABI_V4
? 2
9171 : DEFAULT_ABI
== ABI_ELFv2
? 4
9175 /* For a function parm of MODE and TYPE, return the starting word in
9176 the parameter area. NWORDS of the parameter area are already used. */
9179 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
9180 unsigned int nwords
)
9184 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
9185 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
9188 /* Compute the size (in words) of a function argument. */
9190 static unsigned long
9191 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
9195 if (mode
!= BLKmode
)
9196 size
= GET_MODE_SIZE (mode
);
9198 size
= int_size_in_bytes (type
);
9201 return (size
+ 3) >> 2;
9203 return (size
+ 7) >> 3;
9206 /* Use this to flush pending int fields. */
9209 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
9210 HOST_WIDE_INT bitpos
, int final
)
9212 unsigned int startbit
, endbit
;
9213 int intregs
, intoffset
;
9214 enum machine_mode mode
;
9216 /* Handle the situations where a float is taking up the first half
9217 of the GPR, and the other half is empty (typically due to
9218 alignment restrictions). We can detect this by a 8-byte-aligned
9219 int field, or by seeing that this is the final flush for this
9220 argument. Count the word and continue on. */
9221 if (cum
->floats_in_gpr
== 1
9222 && (cum
->intoffset
% 64 == 0
9223 || (cum
->intoffset
== -1 && final
)))
9226 cum
->floats_in_gpr
= 0;
9229 if (cum
->intoffset
== -1)
9232 intoffset
= cum
->intoffset
;
9233 cum
->intoffset
= -1;
9234 cum
->floats_in_gpr
= 0;
9236 if (intoffset
% BITS_PER_WORD
!= 0)
9238 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9240 if (mode
== BLKmode
)
9242 /* We couldn't find an appropriate mode, which happens,
9243 e.g., in packed structs when there are 3 bytes to load.
9244 Back intoffset back to the beginning of the word in this
9246 intoffset
= intoffset
& -BITS_PER_WORD
;
9250 startbit
= intoffset
& -BITS_PER_WORD
;
9251 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9252 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9253 cum
->words
+= intregs
;
9254 /* words should be unsigned. */
9255 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
9257 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
9262 /* The darwin64 ABI calls for us to recurse down through structs,
9263 looking for elements passed in registers. Unfortunately, we have
9264 to track int register count here also because of misalignments
9265 in powerpc alignment mode. */
9268 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
9270 HOST_WIDE_INT startbitpos
)
9274 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9275 if (TREE_CODE (f
) == FIELD_DECL
)
9277 HOST_WIDE_INT bitpos
= startbitpos
;
9278 tree ftype
= TREE_TYPE (f
);
9279 enum machine_mode mode
;
9280 if (ftype
== error_mark_node
)
9282 mode
= TYPE_MODE (ftype
);
9284 if (DECL_SIZE (f
) != 0
9285 && tree_fits_uhwi_p (bit_position (f
)))
9286 bitpos
+= int_bit_position (f
);
9288 /* ??? FIXME: else assume zero offset. */
9290 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9291 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
9292 else if (USE_FP_FOR_ARG_P (cum
, mode
))
9294 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9295 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9296 cum
->fregno
+= n_fpregs
;
9297 /* Single-precision floats present a special problem for
9298 us, because they are smaller than an 8-byte GPR, and so
9299 the structure-packing rules combined with the standard
9300 varargs behavior mean that we want to pack float/float
9301 and float/int combinations into a single register's
9302 space. This is complicated by the arg advance flushing,
9303 which works on arbitrarily large groups of int-type
9307 if (cum
->floats_in_gpr
== 1)
9309 /* Two floats in a word; count the word and reset
9312 cum
->floats_in_gpr
= 0;
9314 else if (bitpos
% 64 == 0)
9316 /* A float at the beginning of an 8-byte word;
9317 count it and put off adjusting cum->words until
9318 we see if a arg advance flush is going to do it
9320 cum
->floats_in_gpr
++;
9324 /* The float is at the end of a word, preceded
9325 by integer fields, so the arg advance flush
9326 just above has already set cum->words and
9327 everything is taken care of. */
9331 cum
->words
+= n_fpregs
;
9333 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9335 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9339 else if (cum
->intoffset
== -1)
9340 cum
->intoffset
= bitpos
;
9344 /* Check for an item that needs to be considered specially under the darwin 64
9345 bit ABI. These are record types where the mode is BLK or the structure is
9348 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
9350 return rs6000_darwin64_abi
9351 && ((mode
== BLKmode
9352 && TREE_CODE (type
) == RECORD_TYPE
9353 && int_size_in_bytes (type
) > 0)
9354 || (type
&& TREE_CODE (type
) == RECORD_TYPE
9355 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
9358 /* Update the data in CUM to advance over an argument
9359 of mode MODE and data type TYPE.
9360 (TYPE is null for libcalls where that information may not be available.)
9362 Note that for args passed by reference, function_arg will be called
9363 with MODE and TYPE set to that of the pointer to the arg, not the arg
9367 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9368 const_tree type
, bool named
, int depth
)
9370 enum machine_mode elt_mode
;
9373 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9375 /* Only tick off an argument if we're not recursing. */
9377 cum
->nargs_prototype
--;
9379 #ifdef HAVE_AS_GNU_ATTRIBUTE
9380 if (DEFAULT_ABI
== ABI_V4
9383 if (SCALAR_FLOAT_MODE_P (mode
))
9384 rs6000_passes_float
= true;
9385 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
9386 rs6000_passes_vector
= true;
9387 else if (SPE_VECTOR_MODE (mode
)
9389 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9390 rs6000_passes_vector
= true;
9394 if (TARGET_ALTIVEC_ABI
9395 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9396 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9397 && int_size_in_bytes (type
) == 16)))
9401 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9403 cum
->vregno
+= n_elts
;
9405 if (!TARGET_ALTIVEC
)
9406 error ("cannot pass argument in vector register because"
9407 " altivec instructions are disabled, use -maltivec"
9410 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9411 even if it is going to be passed in a vector register.
9412 Darwin does the same for variable-argument functions. */
9413 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9415 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
9425 /* Vector parameters must be 16-byte aligned. In 32-bit
9426 mode this means we need to take into account the offset
9427 to the parameter save area. In 64-bit mode, they just
9428 have to start on an even word, since the parameter save
9429 area is 16-byte aligned. */
9431 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9433 align
= cum
->words
& 1;
9434 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
9436 if (TARGET_DEBUG_ARG
)
9438 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
9440 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
9441 cum
->nargs_prototype
, cum
->prototype
,
9442 GET_MODE_NAME (mode
));
9446 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
9448 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9451 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9453 int size
= int_size_in_bytes (type
);
9454 /* Variable sized types have size == -1 and are
9455 treated as if consisting entirely of ints.
9456 Pad to 16 byte boundary if needed. */
9457 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9458 && (cum
->words
% 2) != 0)
9460 /* For varargs, we can just go up by the size of the struct. */
9462 cum
->words
+= (size
+ 7) / 8;
9465 /* It is tempting to say int register count just goes up by
9466 sizeof(type)/8, but this is wrong in a case such as
9467 { int; double; int; } [powerpc alignment]. We have to
9468 grovel through the fields for these too. */
9470 cum
->floats_in_gpr
= 0;
9471 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
9472 rs6000_darwin64_record_arg_advance_flush (cum
,
9473 size
* BITS_PER_UNIT
, 1);
9475 if (TARGET_DEBUG_ARG
)
9477 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
9478 cum
->words
, TYPE_ALIGN (type
), size
);
9480 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
9481 cum
->nargs_prototype
, cum
->prototype
,
9482 GET_MODE_NAME (mode
));
9485 else if (DEFAULT_ABI
== ABI_V4
)
9487 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9488 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9489 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9490 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9491 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9493 /* _Decimal128 must use an even/odd register pair. This assumes
9494 that the register number is odd when fregno is odd. */
9495 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9498 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9499 <= FP_ARG_V4_MAX_REG
)
9500 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
9503 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
9504 if (mode
== DFmode
|| mode
== TFmode
9505 || mode
== DDmode
|| mode
== TDmode
)
9506 cum
->words
+= cum
->words
& 1;
9507 cum
->words
+= rs6000_arg_size (mode
, type
);
9512 int n_words
= rs6000_arg_size (mode
, type
);
9513 int gregno
= cum
->sysv_gregno
;
9515 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9516 (r7,r8) or (r9,r10). As does any other 2 word item such
9517 as complex int due to a historical mistake. */
9519 gregno
+= (1 - gregno
) & 1;
9521 /* Multi-reg args are not split between registers and stack. */
9522 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9524 /* Long long and SPE vectors are aligned on the stack.
9525 So are other 2 word items such as complex int due to
9526 a historical mistake. */
9528 cum
->words
+= cum
->words
& 1;
9529 cum
->words
+= n_words
;
9532 /* Note: continuing to accumulate gregno past when we've started
9533 spilling to the stack indicates the fact that we've started
9534 spilling to the stack to expand_builtin_saveregs. */
9535 cum
->sysv_gregno
= gregno
+ n_words
;
9538 if (TARGET_DEBUG_ARG
)
9540 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9541 cum
->words
, cum
->fregno
);
9542 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
9543 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
9544 fprintf (stderr
, "mode = %4s, named = %d\n",
9545 GET_MODE_NAME (mode
), named
);
9550 int n_words
= rs6000_arg_size (mode
, type
);
9551 int start_words
= cum
->words
;
9552 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
9554 cum
->words
= align_words
+ n_words
;
9556 if (SCALAR_FLOAT_MODE_P (elt_mode
)
9557 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9559 /* _Decimal128 must be passed in an even/odd float register pair.
9560 This assumes that the register number is odd when fregno is
9562 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9564 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
9567 if (TARGET_DEBUG_ARG
)
9569 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9570 cum
->words
, cum
->fregno
);
9571 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
9572 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
9573 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
9574 named
, align_words
- start_words
, depth
);
9580 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
9581 const_tree type
, bool named
)
9583 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
9588 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
9595 r1
= gen_rtx_REG (DImode
, gregno
);
9596 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9597 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
9601 r1
= gen_rtx_REG (DImode
, gregno
);
9602 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9603 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9604 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9605 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
9608 r1
= gen_rtx_REG (DImode
, gregno
);
9609 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9610 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9611 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9612 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
9613 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
9614 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
9615 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
9616 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
9623 /* Determine where to put a SIMD argument on the SPE. */
9625 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9628 int gregno
= cum
->sysv_gregno
;
9630 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
9631 are passed and returned in a pair of GPRs for ABI compatibility. */
9632 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
9633 || mode
== DCmode
|| mode
== TCmode
))
9635 int n_words
= rs6000_arg_size (mode
, type
);
9637 /* Doubles go in an odd/even register pair (r5/r6, etc). */
9639 gregno
+= (1 - gregno
) & 1;
9641 /* Multi-reg args are not split between registers and stack. */
9642 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9645 return spe_build_register_parallel (mode
, gregno
);
9649 int n_words
= rs6000_arg_size (mode
, type
);
9651 /* SPE vectors are put in odd registers. */
9652 if (n_words
== 2 && (gregno
& 1) == 0)
9655 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
9658 enum machine_mode m
= SImode
;
9660 r1
= gen_rtx_REG (m
, gregno
);
9661 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
9662 r2
= gen_rtx_REG (m
, gregno
+ 1);
9663 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
9664 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
9671 if (gregno
<= GP_ARG_MAX_REG
)
9672 return gen_rtx_REG (mode
, gregno
);
9678 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
9679 structure between cum->intoffset and bitpos to integer registers. */
9682 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
9683 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
9685 enum machine_mode mode
;
9687 unsigned int startbit
, endbit
;
9688 int this_regno
, intregs
, intoffset
;
9691 if (cum
->intoffset
== -1)
9694 intoffset
= cum
->intoffset
;
9695 cum
->intoffset
= -1;
9697 /* If this is the trailing part of a word, try to only load that
9698 much into the register. Otherwise load the whole register. Note
9699 that in the latter case we may pick up unwanted bits. It's not a
9700 problem at the moment but may wish to revisit. */
9702 if (intoffset
% BITS_PER_WORD
!= 0)
9704 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9706 if (mode
== BLKmode
)
9708 /* We couldn't find an appropriate mode, which happens,
9709 e.g., in packed structs when there are 3 bytes to load.
9710 Back intoffset back to the beginning of the word in this
9712 intoffset
= intoffset
& -BITS_PER_WORD
;
9719 startbit
= intoffset
& -BITS_PER_WORD
;
9720 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9721 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9722 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
9724 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
9727 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
9731 intoffset
/= BITS_PER_UNIT
;
9734 regno
= GP_ARG_MIN_REG
+ this_regno
;
9735 reg
= gen_rtx_REG (mode
, regno
);
9737 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
9740 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
9744 while (intregs
> 0);
9747 /* Recursive workhorse for the following. */
9750 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
9751 HOST_WIDE_INT startbitpos
, rtx rvec
[],
9756 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9757 if (TREE_CODE (f
) == FIELD_DECL
)
9759 HOST_WIDE_INT bitpos
= startbitpos
;
9760 tree ftype
= TREE_TYPE (f
);
9761 enum machine_mode mode
;
9762 if (ftype
== error_mark_node
)
9764 mode
= TYPE_MODE (ftype
);
9766 if (DECL_SIZE (f
) != 0
9767 && tree_fits_uhwi_p (bit_position (f
)))
9768 bitpos
+= int_bit_position (f
);
9770 /* ??? FIXME: else assume zero offset. */
9772 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9773 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
9774 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
9776 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9780 case SCmode
: mode
= SFmode
; break;
9781 case DCmode
: mode
= DFmode
; break;
9782 case TCmode
: mode
= TFmode
; break;
9786 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9787 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9789 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9790 && (mode
== TFmode
|| mode
== TDmode
));
9791 /* Long double or _Decimal128 split over regs and memory. */
9792 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
9796 = gen_rtx_EXPR_LIST (VOIDmode
,
9797 gen_rtx_REG (mode
, cum
->fregno
++),
9798 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9799 if (mode
== TFmode
|| mode
== TDmode
)
9802 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9804 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9806 = gen_rtx_EXPR_LIST (VOIDmode
,
9807 gen_rtx_REG (mode
, cum
->vregno
++),
9808 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9810 else if (cum
->intoffset
== -1)
9811 cum
->intoffset
= bitpos
;
9815 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
9816 the register(s) to be used for each field and subfield of a struct
9817 being passed by value, along with the offset of where the
9818 register's value may be found in the block. FP fields go in FP
9819 register, vector fields go in vector registers, and everything
9820 else goes in int registers, packed as in memory.
9822 This code is also used for function return values. RETVAL indicates
9823 whether this is the case.
9825 Much of this is taken from the SPARC V9 port, which has a similar
9826 calling convention. */
9829 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
9830 bool named
, bool retval
)
9832 rtx rvec
[FIRST_PSEUDO_REGISTER
];
9833 int k
= 1, kbase
= 1;
9834 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
9835 /* This is a copy; modifications are not visible to our caller. */
9836 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
9837 CUMULATIVE_ARGS
*cum
= ©_cum
;
9839 /* Pad to 16 byte boundary if needed. */
9840 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9841 && (cum
->words
% 2) != 0)
9848 /* Put entries into rvec[] for individual FP and vector fields, and
9849 for the chunks of memory that go in int regs. Note we start at
9850 element 1; 0 is reserved for an indication of using memory, and
9851 may or may not be filled in below. */
9852 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
9853 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
9855 /* If any part of the struct went on the stack put all of it there.
9856 This hack is because the generic code for
9857 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
9858 parts of the struct are not at the beginning. */
9862 return NULL_RTX
; /* doesn't go in registers at all */
9864 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9866 if (k
> 1 || cum
->use_stack
)
9867 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
9872 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
9875 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
9880 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9882 if (align_words
>= GP_ARG_NUM_REG
)
9885 n_units
= rs6000_arg_size (mode
, type
);
9887 /* Optimize the simple case where the arg fits in one gpr, except in
9888 the case of BLKmode due to assign_parms assuming that registers are
9889 BITS_PER_WORD wide. */
9891 || (n_units
== 1 && mode
!= BLKmode
))
9892 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9895 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
9896 /* Not all of the arg fits in gprs. Say that it goes in memory too,
9897 using a magic NULL_RTX component.
9898 This is not strictly correct. Only some of the arg belongs in
9899 memory, not all of it. However, the normal scheme using
9900 function_arg_partial_nregs can result in unusual subregs, eg.
9901 (subreg:SI (reg:DF) 4), which are not handled well. The code to
9902 store the whole arg to memory is often more efficient than code
9903 to store pieces, and we know that space is available in the right
9904 place for the whole arg. */
9905 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9910 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
9911 rtx off
= GEN_INT (i
++ * 4);
9912 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9914 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
9916 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9919 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
9920 but must also be copied into the parameter save area starting at
9921 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
9922 to the GPRs and/or memory. Return the number of elements used. */
9925 rs6000_psave_function_arg (enum machine_mode mode
, const_tree type
,
9926 int align_words
, rtx
*rvec
)
9930 if (align_words
< GP_ARG_NUM_REG
)
9932 int n_words
= rs6000_arg_size (mode
, type
);
9934 if (align_words
+ n_words
> GP_ARG_NUM_REG
9936 || (TARGET_32BIT
&& TARGET_POWERPC64
))
9938 /* If this is partially on the stack, then we only
9939 include the portion actually in registers here. */
9940 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
9943 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9945 /* Not all of the arg fits in gprs. Say that it goes in memory
9946 too, using a magic NULL_RTX component. Also see comment in
9947 rs6000_mixed_function_arg for why the normal
9948 function_arg_partial_nregs scheme doesn't work in this case. */
9949 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9954 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
9955 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
9956 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9958 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
9962 /* The whole arg fits in gprs. */
9963 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9964 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9969 /* It's entirely in memory. */
9970 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9976 /* RVEC is a vector of K components of an argument of mode MODE.
9977 Construct the final function_arg return value from it. */
9980 rs6000_finish_function_arg (enum machine_mode mode
, rtx
*rvec
, int k
)
9982 gcc_assert (k
>= 1);
9984 /* Avoid returning a PARALLEL in the trivial cases. */
9987 if (XEXP (rvec
[0], 0) == NULL_RTX
)
9990 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
9991 return XEXP (rvec
[0], 0);
9994 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9997 /* Determine where to put an argument to a function.
9998 Value is zero to push the argument on the stack,
9999 or a hard register in which to store the argument.
10001 MODE is the argument's machine mode.
10002 TYPE is the data type of the argument (as a tree).
10003 This is null for libcalls where that information may
10005 CUM is a variable of type CUMULATIVE_ARGS which gives info about
10006 the preceding args and about the function being called. It is
10007 not modified in this routine.
10008 NAMED is nonzero if this argument is a named parameter
10009 (otherwise it is an extra parameter matching an ellipsis).
10011 On RS/6000 the first eight words of non-FP are normally in registers
10012 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
10013 Under V.4, the first 8 FP args are in registers.
10015 If this is floating-point and no prototype is specified, we use
10016 both an FP and integer register (or possibly FP reg and stack). Library
10017 functions (when CALL_LIBCALL is set) always have the proper types for args,
10018 so we can pass the FP value just in one register. emit_library_function
10019 doesn't support PARALLEL anyway.
10021 Note that for args passed by reference, function_arg will be called
10022 with MODE and TYPE set to that of the pointer to the arg, not the arg
10026 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
10027 const_tree type
, bool named
)
10029 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10030 enum rs6000_abi abi
= DEFAULT_ABI
;
10031 enum machine_mode elt_mode
;
10034 /* Return a marker to indicate whether CR1 needs to set or clear the
10035 bit that V.4 uses to say fp args were passed in registers.
10036 Assume that we don't need the marker for software floating point,
10037 or compiler generated library calls. */
10038 if (mode
== VOIDmode
)
10041 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
10043 || (cum
->nargs_prototype
< 0
10044 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
10046 /* For the SPE, we need to crxor CR6 always. */
10047 if (TARGET_SPE_ABI
)
10048 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
10049 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
10050 return GEN_INT (cum
->call_cookie
10051 | ((cum
->fregno
== FP_ARG_MIN_REG
)
10052 ? CALL_V4_SET_FP_ARGS
10053 : CALL_V4_CLEAR_FP_ARGS
));
10056 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
10059 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10061 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10063 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
10064 if (rslt
!= NULL_RTX
)
10066 /* Else fall through to usual handling. */
10069 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10071 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10075 /* Do we also need to pass this argument in the parameter
10077 if (TARGET_64BIT
&& ! cum
->prototype
)
10079 int align_words
= (cum
->words
+ 1) & ~1;
10080 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10083 /* Describe where this argument goes in the vector registers. */
10084 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
10086 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
10087 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10088 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10091 return rs6000_finish_function_arg (mode
, rvec
, k
);
10093 else if (TARGET_ALTIVEC_ABI
10094 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
10095 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10096 && int_size_in_bytes (type
) == 16)))
10098 if (named
|| abi
== ABI_V4
)
10102 /* Vector parameters to varargs functions under AIX or Darwin
10103 get passed in memory and possibly also in GPRs. */
10104 int align
, align_words
, n_words
;
10105 enum machine_mode part_mode
;
10107 /* Vector parameters must be 16-byte aligned. In 32-bit
10108 mode this means we need to take into account the offset
10109 to the parameter save area. In 64-bit mode, they just
10110 have to start on an even word, since the parameter save
10111 area is 16-byte aligned. */
10113 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
10115 align
= cum
->words
& 1;
10116 align_words
= cum
->words
+ align
;
10118 /* Out of registers? Memory, then. */
10119 if (align_words
>= GP_ARG_NUM_REG
)
10122 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10123 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10125 /* The vector value goes in GPRs. Only the part of the
10126 value in GPRs is reported here. */
10128 n_words
= rs6000_arg_size (mode
, type
);
10129 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10130 /* Fortunately, there are only two possibilities, the value
10131 is either wholly in GPRs or half in GPRs and half not. */
10132 part_mode
= DImode
;
10134 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
10137 else if (TARGET_SPE_ABI
&& TARGET_SPE
10138 && (SPE_VECTOR_MODE (mode
)
10139 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
10142 || mode
== TCmode
))))
10143 return rs6000_spe_function_arg (cum
, mode
, type
);
10145 else if (abi
== ABI_V4
)
10147 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10148 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10149 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10150 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
10151 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
10153 /* _Decimal128 must use an even/odd register pair. This assumes
10154 that the register number is odd when fregno is odd. */
10155 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10158 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
10159 <= FP_ARG_V4_MAX_REG
)
10160 return gen_rtx_REG (mode
, cum
->fregno
);
10166 int n_words
= rs6000_arg_size (mode
, type
);
10167 int gregno
= cum
->sysv_gregno
;
10169 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10170 (r7,r8) or (r9,r10). As does any other 2 word item such
10171 as complex int due to a historical mistake. */
10173 gregno
+= (1 - gregno
) & 1;
10175 /* Multi-reg args are not split between registers and stack. */
10176 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10179 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10180 return rs6000_mixed_function_arg (mode
, type
,
10181 gregno
- GP_ARG_MIN_REG
);
10182 return gen_rtx_REG (mode
, gregno
);
10187 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10189 /* _Decimal128 must be passed in an even/odd float register pair.
10190 This assumes that the register number is odd when fregno is odd. */
10191 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10194 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10196 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10199 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10201 /* Do we also need to pass this argument in the parameter
10203 if (type
&& (cum
->nargs_prototype
<= 0
10204 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10205 && TARGET_XL_COMPAT
10206 && align_words
>= GP_ARG_NUM_REG
)))
10207 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10209 /* Describe where this argument goes in the fprs. */
10210 for (i
= 0; i
< n_elts
10211 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
10213 /* Check if the argument is split over registers and memory.
10214 This can only ever happen for long double or _Decimal128;
10215 complex types are handled via split_complex_arg. */
10216 enum machine_mode fmode
= elt_mode
;
10217 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
10219 gcc_assert (fmode
== TFmode
|| fmode
== TDmode
);
10220 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
10223 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
10224 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10225 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10228 return rs6000_finish_function_arg (mode
, rvec
, k
);
10230 else if (align_words
< GP_ARG_NUM_REG
)
10232 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10233 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10235 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10242 /* For an arg passed partly in registers and partly in memory, this is
10243 the number of bytes passed in registers. For args passed entirely in
10244 registers or entirely in memory, zero. When an arg is described by a
10245 PARALLEL, perhaps using more than one register type, this function
10246 returns the number of bytes used by the first element of the PARALLEL. */
10249 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
10250 tree type
, bool named
)
10252 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10253 bool passed_in_gprs
= true;
10256 enum machine_mode elt_mode
;
10259 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10261 if (DEFAULT_ABI
== ABI_V4
)
10264 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10266 /* If we are passing this arg in the fixed parameter save area
10267 (gprs or memory) as well as VRs, we do not use the partial
10268 bytes mechanism; instead, rs6000_function_arg will return a
10269 PARALLEL including a memory element as necessary. */
10270 if (TARGET_64BIT
&& ! cum
->prototype
)
10273 /* Otherwise, we pass in VRs only. Check for partial copies. */
10274 passed_in_gprs
= false;
10275 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
10276 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
10279 /* In this complicated case we just disable the partial_nregs code. */
10280 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10283 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10285 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10287 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10289 /* If we are passing this arg in the fixed parameter save area
10290 (gprs or memory) as well as FPRs, we do not use the partial
10291 bytes mechanism; instead, rs6000_function_arg will return a
10292 PARALLEL including a memory element as necessary. */
10294 && (cum
->nargs_prototype
<= 0
10295 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10296 && TARGET_XL_COMPAT
10297 && align_words
>= GP_ARG_NUM_REG
)))
10300 /* Otherwise, we pass in FPRs only. Check for partial copies. */
10301 passed_in_gprs
= false;
10302 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
10303 ret
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
10304 * MIN (8, GET_MODE_SIZE (elt_mode
)));
10308 && align_words
< GP_ARG_NUM_REG
10309 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
10310 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
10312 if (ret
!= 0 && TARGET_DEBUG_ARG
)
10313 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
10318 /* A C expression that indicates when an argument must be passed by
10319 reference. If nonzero for an argument, a copy of that argument is
10320 made in memory and a pointer to the argument is passed instead of
10321 the argument itself. The pointer is passed in whatever way is
10322 appropriate for passing a pointer to that type.
10324 Under V.4, aggregates and long double are passed by reference.
10326 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
10327 reference unless the AltiVec vector extension ABI is in force.
10329 As an extension to all ABIs, variable sized types are passed by
10333 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
10334 enum machine_mode mode
, const_tree type
,
10335 bool named ATTRIBUTE_UNUSED
)
10337 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
10339 if (TARGET_DEBUG_ARG
)
10340 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
10347 #if HAVE_UPC_PTS_STRUCT_REP
10348 if (DEFAULT_ABI
== ABI_V4
&& POINTER_TYPE_P (type
)
10349 && upc_shared_type_p (TREE_TYPE (type
)))
10351 if (TARGET_DEBUG_ARG
)
10353 "function_arg_pass_by_reference: V4 UPC ptr to shared\n");
10358 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
10360 if (TARGET_DEBUG_ARG
)
10361 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
10365 if (int_size_in_bytes (type
) < 0)
10367 if (TARGET_DEBUG_ARG
)
10368 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
10372 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10373 modes only exist for GCC vector types if -maltivec. */
10374 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
10376 if (TARGET_DEBUG_ARG
)
10377 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
10381 /* Pass synthetic vectors in memory. */
10382 if (TREE_CODE (type
) == VECTOR_TYPE
10383 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10385 static bool warned_for_pass_big_vectors
= false;
10386 if (TARGET_DEBUG_ARG
)
10387 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
10388 if (!warned_for_pass_big_vectors
)
10390 warning (0, "GCC vector passed by reference: "
10391 "non-standard ABI extension with no compatibility guarantee");
10392 warned_for_pass_big_vectors
= true;
10400 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
10401 already processes. Return true if the parameter must be passed
10402 (fully or partially) on the stack. */
10405 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
10407 enum machine_mode mode
;
10411 /* Catch errors. */
10412 if (type
== NULL
|| type
== error_mark_node
)
10415 /* Handle types with no storage requirement. */
10416 if (TYPE_MODE (type
) == VOIDmode
)
10419 /* Handle complex types. */
10420 if (TREE_CODE (type
) == COMPLEX_TYPE
)
10421 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
10422 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
10424 /* Handle transparent aggregates. */
10425 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
10426 && TYPE_TRANSPARENT_AGGR (type
))
10427 type
= TREE_TYPE (first_field (type
));
10429 /* See if this arg was passed by invisible reference. */
10430 if (pass_by_reference (get_cumulative_args (args_so_far
),
10431 TYPE_MODE (type
), type
, true))
10432 type
= build_pointer_type (type
);
10434 /* Find mode as it is passed by the ABI. */
10435 unsignedp
= TYPE_UNSIGNED (type
);
10436 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
10438 /* If we must pass in stack, we need a stack. */
10439 if (rs6000_must_pass_in_stack (mode
, type
))
10442 /* If there is no incoming register, we need a stack. */
10443 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
10444 if (entry_parm
== NULL
)
10447 /* Likewise if we need to pass both in registers and on the stack. */
10448 if (GET_CODE (entry_parm
) == PARALLEL
10449 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
10452 /* Also true if we're partially in registers and partially not. */
10453 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
10456 /* Update info on where next arg arrives in registers. */
10457 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
10461 /* Return true if FUN has no prototype, has a variable argument
10462 list, or passes any parameter in memory. */
10465 rs6000_function_parms_need_stack (tree fun
)
10467 function_args_iterator args_iter
;
10469 CUMULATIVE_ARGS args_so_far_v
;
10470 cumulative_args_t args_so_far
;
10473 /* Must be a libcall, all of which only use reg parms. */
10476 fun
= TREE_TYPE (fun
);
10478 /* Varargs functions need the parameter save area. */
10479 if (!prototype_p (fun
) || stdarg_p (fun
))
10482 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fun
, NULL_RTX
);
10483 args_so_far
= pack_cumulative_args (&args_so_far_v
);
10485 if (aggregate_value_p (TREE_TYPE (fun
), fun
))
10487 tree type
= build_pointer_type (TREE_TYPE (fun
));
10488 rs6000_parm_needs_stack (args_so_far
, type
);
10491 FOREACH_FUNCTION_ARGS (fun
, arg_type
, args_iter
)
10492 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
10498 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
10499 usually a constant depending on the ABI. However, in the ELFv2 ABI
10500 the register parameter area is optional when calling a function that
10501 has a prototype is scope, has no variable argument list, and passes
10502 all parameters in registers. */
10505 rs6000_reg_parm_stack_space (tree fun
)
10507 int reg_parm_stack_space
;
10509 switch (DEFAULT_ABI
)
10512 reg_parm_stack_space
= 0;
10517 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10521 /* ??? Recomputing this every time is a bit expensive. Is there
10522 a place to cache this information? */
10523 if (rs6000_function_parms_need_stack (fun
))
10524 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10526 reg_parm_stack_space
= 0;
10530 return reg_parm_stack_space
;
10534 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
10537 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
10542 for (i
= 0; i
< nregs
; i
++)
10544 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
10545 if (reload_completed
)
10547 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
10550 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
10551 i
* GET_MODE_SIZE (reg_mode
));
10554 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
10558 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
10562 /* Perform any needed actions needed for a function that is receiving a
10563 variable number of arguments.
10567 MODE and TYPE are the mode and type of the current parameter.
10569 PRETEND_SIZE is a variable that should be set to the amount of stack
10570 that must be pushed by the prolog to pretend that our caller pushed
10573 Normally, this macro will push all remaining incoming registers on the
10574 stack and set PRETEND_SIZE to the length of the registers pushed. */
10577 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
10578 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
10581 CUMULATIVE_ARGS next_cum
;
10582 int reg_size
= TARGET_32BIT
? 4 : 8;
10583 rtx save_area
= NULL_RTX
, mem
;
10584 int first_reg_offset
;
10585 alias_set_type set
;
10587 /* Skip the last named argument. */
10588 next_cum
= *get_cumulative_args (cum
);
10589 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
10591 if (DEFAULT_ABI
== ABI_V4
)
10593 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
10597 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
10598 HOST_WIDE_INT offset
= 0;
10600 /* Try to optimize the size of the varargs save area.
10601 The ABI requires that ap.reg_save_area is doubleword
10602 aligned, but we don't need to allocate space for all
10603 the bytes, only those to which we actually will save
10605 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
10606 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
10607 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10608 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10609 && cfun
->va_list_fpr_size
)
10612 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
10613 * UNITS_PER_FP_WORD
;
10614 if (cfun
->va_list_fpr_size
10615 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10616 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
10618 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10619 * UNITS_PER_FP_WORD
;
10623 offset
= -((first_reg_offset
* reg_size
) & ~7);
10624 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
10626 gpr_reg_num
= cfun
->va_list_gpr_size
;
10627 if (reg_size
== 4 && (first_reg_offset
& 1))
10630 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
10633 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
10634 * UNITS_PER_FP_WORD
10635 - (int) (GP_ARG_NUM_REG
* reg_size
);
10637 if (gpr_size
+ fpr_size
)
10640 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
10641 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
10642 reg_save_area
= XEXP (reg_save_area
, 0);
10643 if (GET_CODE (reg_save_area
) == PLUS
)
10645 gcc_assert (XEXP (reg_save_area
, 0)
10646 == virtual_stack_vars_rtx
);
10647 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
10648 offset
+= INTVAL (XEXP (reg_save_area
, 1));
10651 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
10654 cfun
->machine
->varargs_save_offset
= offset
;
10655 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
10660 first_reg_offset
= next_cum
.words
;
10661 save_area
= virtual_incoming_args_rtx
;
10663 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
10664 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
10667 set
= get_varargs_alias_set ();
10668 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
10669 && cfun
->va_list_gpr_size
)
10671 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
10673 if (va_list_gpr_counter_field
)
10674 /* V4 va_list_gpr_size counts number of registers needed. */
10675 n_gpr
= cfun
->va_list_gpr_size
;
10677 /* char * va_list instead counts number of bytes needed. */
10678 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
10683 mem
= gen_rtx_MEM (BLKmode
,
10684 plus_constant (Pmode
, save_area
,
10685 first_reg_offset
* reg_size
));
10686 MEM_NOTRAP_P (mem
) = 1;
10687 set_mem_alias_set (mem
, set
);
10688 set_mem_align (mem
, BITS_PER_WORD
);
10690 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
10694 /* Save FP registers if needed. */
10695 if (DEFAULT_ABI
== ABI_V4
10696 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10698 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10699 && cfun
->va_list_fpr_size
)
10701 int fregno
= next_cum
.fregno
, nregs
;
10702 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
10703 rtx lab
= gen_label_rtx ();
10704 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
10705 * UNITS_PER_FP_WORD
);
10708 (gen_rtx_SET (VOIDmode
,
10710 gen_rtx_IF_THEN_ELSE (VOIDmode
,
10711 gen_rtx_NE (VOIDmode
, cr1
,
10713 gen_rtx_LABEL_REF (VOIDmode
, lab
),
10717 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
10718 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
10720 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10722 plus_constant (Pmode
, save_area
, off
));
10723 MEM_NOTRAP_P (mem
) = 1;
10724 set_mem_alias_set (mem
, set
);
10725 set_mem_align (mem
, GET_MODE_ALIGNMENT (
10726 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10727 ? DFmode
: SFmode
));
10728 emit_move_insn (mem
, gen_rtx_REG (
10729 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10730 ? DFmode
: SFmode
, fregno
));
10737 /* Create the va_list data type. */
10740 rs6000_build_builtin_va_list (void)
10742 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
10744 /* For AIX, prefer 'char *' because that's what the system
10745 header files like. */
10746 if (DEFAULT_ABI
!= ABI_V4
)
10747 return build_pointer_type (char_type_node
);
10749 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
10750 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
10751 get_identifier ("__va_list_tag"), record
);
10753 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
10754 unsigned_char_type_node
);
10755 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
10756 unsigned_char_type_node
);
10757 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
10758 every user file. */
10759 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10760 get_identifier ("reserved"), short_unsigned_type_node
);
10761 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10762 get_identifier ("overflow_arg_area"),
10764 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10765 get_identifier ("reg_save_area"),
10768 va_list_gpr_counter_field
= f_gpr
;
10769 va_list_fpr_counter_field
= f_fpr
;
10771 DECL_FIELD_CONTEXT (f_gpr
) = record
;
10772 DECL_FIELD_CONTEXT (f_fpr
) = record
;
10773 DECL_FIELD_CONTEXT (f_res
) = record
;
10774 DECL_FIELD_CONTEXT (f_ovf
) = record
;
10775 DECL_FIELD_CONTEXT (f_sav
) = record
;
10777 TYPE_STUB_DECL (record
) = type_decl
;
10778 TYPE_NAME (record
) = type_decl
;
10779 TYPE_FIELDS (record
) = f_gpr
;
10780 DECL_CHAIN (f_gpr
) = f_fpr
;
10781 DECL_CHAIN (f_fpr
) = f_res
;
10782 DECL_CHAIN (f_res
) = f_ovf
;
10783 DECL_CHAIN (f_ovf
) = f_sav
;
10785 layout_type (record
);
10787 /* The correct type is an array type of one element. */
10788 return build_array_type (record
, build_index_type (size_zero_node
));
10791 /* Implement va_start. */
10794 rs6000_va_start (tree valist
, rtx nextarg
)
10796 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
10797 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10798 tree gpr
, fpr
, ovf
, sav
, t
;
10800 /* Only SVR4 needs something special. */
10801 if (DEFAULT_ABI
!= ABI_V4
)
10803 std_expand_builtin_va_start (valist
, nextarg
);
10807 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10808 f_fpr
= DECL_CHAIN (f_gpr
);
10809 f_res
= DECL_CHAIN (f_fpr
);
10810 f_ovf
= DECL_CHAIN (f_res
);
10811 f_sav
= DECL_CHAIN (f_ovf
);
10813 valist
= build_simple_mem_ref (valist
);
10814 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10815 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10817 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10819 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10822 /* Count number of gp and fp argument registers used. */
10823 words
= crtl
->args
.info
.words
;
10824 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
10826 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
10829 if (TARGET_DEBUG_ARG
)
10830 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
10831 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
10832 words
, n_gpr
, n_fpr
);
10834 if (cfun
->va_list_gpr_size
)
10836 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
10837 build_int_cst (NULL_TREE
, n_gpr
));
10838 TREE_SIDE_EFFECTS (t
) = 1;
10839 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10842 if (cfun
->va_list_fpr_size
)
10844 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
10845 build_int_cst (NULL_TREE
, n_fpr
));
10846 TREE_SIDE_EFFECTS (t
) = 1;
10847 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10849 #ifdef HAVE_AS_GNU_ATTRIBUTE
10850 if (call_ABI_of_interest (cfun
->decl
))
10851 rs6000_passes_float
= true;
10855 /* Find the overflow area. */
10856 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
10858 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
10859 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
10860 TREE_SIDE_EFFECTS (t
) = 1;
10861 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10863 /* If there were no va_arg invocations, don't set up the register
10865 if (!cfun
->va_list_gpr_size
10866 && !cfun
->va_list_fpr_size
10867 && n_gpr
< GP_ARG_NUM_REG
10868 && n_fpr
< FP_ARG_V4_MAX_REG
)
10871 /* Find the register save area. */
10872 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
10873 if (cfun
->machine
->varargs_save_offset
)
10874 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
10875 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
10876 TREE_SIDE_EFFECTS (t
) = 1;
10877 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10880 /* Implement va_arg. */
10883 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
10884 gimple_seq
*post_p
)
10886 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10887 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
10888 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
10889 tree lab_false
, lab_over
, addr
;
10891 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
10895 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
10897 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
10898 return build_va_arg_indirect_ref (t
);
10901 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
10902 earlier version of gcc, with the property that it always applied alignment
10903 adjustments to the va-args (even for zero-sized types). The cheapest way
10904 to deal with this is to replicate the effect of the part of
10905 std_gimplify_va_arg_expr that carries out the align adjust, for the case
10907 We don't need to check for pass-by-reference because of the test above.
10908 We can return a simplifed answer, since we know there's no offset to add. */
10911 && rs6000_darwin64_abi
)
10912 || DEFAULT_ABI
== ABI_ELFv2
10913 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
10914 && integer_zerop (TYPE_SIZE (type
)))
10916 unsigned HOST_WIDE_INT align
, boundary
;
10917 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
10918 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
10919 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
10920 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
10921 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
10922 boundary
/= BITS_PER_UNIT
;
10923 if (boundary
> align
)
10926 /* This updates arg ptr by the amount that would be necessary
10927 to align the zero-sized (but not zero-alignment) item. */
10928 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10929 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
10930 gimplify_and_add (t
, pre_p
);
10932 t
= fold_convert (sizetype
, valist_tmp
);
10933 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10934 fold_convert (TREE_TYPE (valist
),
10935 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
10936 size_int (-boundary
))));
10937 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
10938 gimplify_and_add (t
, pre_p
);
10940 /* Since it is zero-sized there's no increment for the item itself. */
10941 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
10942 return build_va_arg_indirect_ref (valist_tmp
);
10945 if (DEFAULT_ABI
!= ABI_V4
)
10947 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
10949 tree elem_type
= TREE_TYPE (type
);
10950 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
10951 int elem_size
= GET_MODE_SIZE (elem_mode
);
10953 if (elem_size
< UNITS_PER_WORD
)
10955 tree real_part
, imag_part
;
10956 gimple_seq post
= NULL
;
10958 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10960 /* Copy the value into a temporary, lest the formal temporary
10961 be reused out from under us. */
10962 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
10963 gimple_seq_add_seq (pre_p
, post
);
10965 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10968 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
10972 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
10975 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10976 f_fpr
= DECL_CHAIN (f_gpr
);
10977 f_res
= DECL_CHAIN (f_fpr
);
10978 f_ovf
= DECL_CHAIN (f_res
);
10979 f_sav
= DECL_CHAIN (f_ovf
);
10981 valist
= build_va_arg_indirect_ref (valist
);
10982 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10983 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10985 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10987 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10990 size
= int_size_in_bytes (type
);
10991 rsize
= (size
+ 3) / 4;
10994 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10995 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
10996 || (TARGET_DOUBLE_FLOAT
10997 && (TYPE_MODE (type
) == DFmode
10998 || TYPE_MODE (type
) == TFmode
10999 || TYPE_MODE (type
) == SDmode
11000 || TYPE_MODE (type
) == DDmode
11001 || TYPE_MODE (type
) == TDmode
))))
11003 /* FP args go in FP registers, if present. */
11005 n_reg
= (size
+ 7) / 8;
11006 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
11007 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
11008 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
11013 /* Otherwise into GP registers. */
11022 /* Pull the value out of the saved registers.... */
11025 addr
= create_tmp_var (ptr_type_node
, "addr");
11027 /* AltiVec vectors never go in registers when -mabi=altivec. */
11028 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
11032 lab_false
= create_artificial_label (input_location
);
11033 lab_over
= create_artificial_label (input_location
);
11035 /* Long long and SPE vectors are aligned in the registers.
11036 As are any other 2 gpr item such as complex int due to a
11037 historical mistake. */
11039 if (n_reg
== 2 && reg
== gpr
)
11042 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11043 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
11044 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
11045 unshare_expr (reg
), u
);
11047 /* _Decimal128 is passed in even/odd fpr pairs; the stored
11048 reg number is 0 for f1, so we want to make it odd. */
11049 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
11051 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11052 build_int_cst (TREE_TYPE (reg
), 1));
11053 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
11056 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
11057 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
11058 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
11059 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
11060 gimplify_and_add (t
, pre_p
);
11064 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
11066 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11067 build_int_cst (TREE_TYPE (reg
), n_reg
));
11068 u
= fold_convert (sizetype
, u
);
11069 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
11070 t
= fold_build_pointer_plus (t
, u
);
11072 /* _Decimal32 varargs are located in the second word of the 64-bit
11073 FP register for 32-bit binaries. */
11074 if (!TARGET_POWERPC64
11075 && TARGET_HARD_FLOAT
&& TARGET_FPRS
11076 && TYPE_MODE (type
) == SDmode
)
11077 t
= fold_build_pointer_plus_hwi (t
, size
);
11079 gimplify_assign (addr
, t
, pre_p
);
11081 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
11083 stmt
= gimple_build_label (lab_false
);
11084 gimple_seq_add_stmt (pre_p
, stmt
);
11086 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
11088 /* Ensure that we don't find any more args in regs.
11089 Alignment has taken care of for special cases. */
11090 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
11094 /* ... otherwise out of the overflow area. */
11096 /* Care for on-stack alignment if needed. */
11100 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
11101 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
11102 build_int_cst (TREE_TYPE (t
), -align
));
11104 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
11106 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
11108 t
= fold_build_pointer_plus_hwi (t
, size
);
11109 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
11113 stmt
= gimple_build_label (lab_over
);
11114 gimple_seq_add_stmt (pre_p
, stmt
);
11117 if (STRICT_ALIGNMENT
11118 && (TYPE_ALIGN (type
)
11119 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
11121 /* The value (of type complex double, for example) may not be
11122 aligned in memory in the saved registers, so copy via a
11123 temporary. (This is the same code as used for SPARC.) */
11124 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
11125 tree dest_addr
= build_fold_addr_expr (tmp
);
11127 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
11128 3, dest_addr
, addr
, size_int (rsize
* 4));
11130 gimplify_and_add (copy
, pre_p
);
11134 addr
= fold_convert (ptrtype
, addr
);
11135 return build_va_arg_indirect_ref (addr
);
11141 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
11144 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
11145 const char *attr_string
= "";
11147 gcc_assert (name
!= NULL
);
11148 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
11150 if (rs6000_builtin_decls
[(int)code
])
11151 fatal_error ("internal error: builtin function %s already processed", name
);
11153 rs6000_builtin_decls
[(int)code
] = t
=
11154 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
11156 /* Set any special attributes. */
11157 if ((classify
& RS6000_BTC_CONST
) != 0)
11159 /* const function, function only depends on the inputs. */
11160 TREE_READONLY (t
) = 1;
11161 TREE_NOTHROW (t
) = 1;
11162 attr_string
= ", pure";
11164 else if ((classify
& RS6000_BTC_PURE
) != 0)
11166 /* pure function, function can read global memory, but does not set any
11168 DECL_PURE_P (t
) = 1;
11169 TREE_NOTHROW (t
) = 1;
11170 attr_string
= ", const";
11172 else if ((classify
& RS6000_BTC_FP
) != 0)
11174 /* Function is a math function. If rounding mode is on, then treat the
11175 function as not reading global memory, but it can have arbitrary side
11176 effects. If it is off, then assume the function is a const function.
11177 This mimics the ATTR_MATHFN_FPROUNDING attribute in
11178 builtin-attribute.def that is used for the math functions. */
11179 TREE_NOTHROW (t
) = 1;
11180 if (flag_rounding_math
)
11182 DECL_PURE_P (t
) = 1;
11183 DECL_IS_NOVOPS (t
) = 1;
11184 attr_string
= ", fp, pure";
11188 TREE_READONLY (t
) = 1;
11189 attr_string
= ", fp, const";
11192 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
11193 gcc_unreachable ();
11195 if (TARGET_DEBUG_BUILTIN
)
11196 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
11197 (int)code
, name
, attr_string
);
11200 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
11202 #undef RS6000_BUILTIN_1
11203 #undef RS6000_BUILTIN_2
11204 #undef RS6000_BUILTIN_3
11205 #undef RS6000_BUILTIN_A
11206 #undef RS6000_BUILTIN_D
11207 #undef RS6000_BUILTIN_E
11208 #undef RS6000_BUILTIN_H
11209 #undef RS6000_BUILTIN_P
11210 #undef RS6000_BUILTIN_Q
11211 #undef RS6000_BUILTIN_S
11212 #undef RS6000_BUILTIN_X
11214 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11215 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11216 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
11217 { MASK, ICODE, NAME, ENUM },
11219 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11220 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11221 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11222 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11223 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11224 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11225 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11226 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11228 static const struct builtin_description bdesc_3arg
[] =
11230 #include "rs6000-builtin.def"
11233 /* DST operations: void foo (void *, const int, const char). */
11235 #undef RS6000_BUILTIN_1
11236 #undef RS6000_BUILTIN_2
11237 #undef RS6000_BUILTIN_3
11238 #undef RS6000_BUILTIN_A
11239 #undef RS6000_BUILTIN_D
11240 #undef RS6000_BUILTIN_E
11241 #undef RS6000_BUILTIN_H
11242 #undef RS6000_BUILTIN_P
11243 #undef RS6000_BUILTIN_Q
11244 #undef RS6000_BUILTIN_S
11245 #undef RS6000_BUILTIN_X
11247 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11248 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11249 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11250 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11251 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
11252 { MASK, ICODE, NAME, ENUM },
11254 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11255 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11256 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11257 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11258 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11259 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11261 static const struct builtin_description bdesc_dst
[] =
11263 #include "rs6000-builtin.def"
11266 /* Simple binary operations: VECc = foo (VECa, VECb). */
11268 #undef RS6000_BUILTIN_1
11269 #undef RS6000_BUILTIN_2
11270 #undef RS6000_BUILTIN_3
11271 #undef RS6000_BUILTIN_A
11272 #undef RS6000_BUILTIN_D
11273 #undef RS6000_BUILTIN_E
11274 #undef RS6000_BUILTIN_H
11275 #undef RS6000_BUILTIN_P
11276 #undef RS6000_BUILTIN_Q
11277 #undef RS6000_BUILTIN_S
11278 #undef RS6000_BUILTIN_X
11280 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11281 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
11282 { MASK, ICODE, NAME, ENUM },
11284 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11285 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11286 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11287 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11288 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11289 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11290 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11291 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11292 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11294 static const struct builtin_description bdesc_2arg
[] =
11296 #include "rs6000-builtin.def"
11299 #undef RS6000_BUILTIN_1
11300 #undef RS6000_BUILTIN_2
11301 #undef RS6000_BUILTIN_3
11302 #undef RS6000_BUILTIN_A
11303 #undef RS6000_BUILTIN_D
11304 #undef RS6000_BUILTIN_E
11305 #undef RS6000_BUILTIN_H
11306 #undef RS6000_BUILTIN_P
11307 #undef RS6000_BUILTIN_Q
11308 #undef RS6000_BUILTIN_S
11309 #undef RS6000_BUILTIN_X
11311 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11312 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11313 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11314 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11315 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11316 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11317 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11318 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
11319 { MASK, ICODE, NAME, ENUM },
11321 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11322 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11323 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11325 /* AltiVec predicates. */
11327 static const struct builtin_description bdesc_altivec_preds
[] =
11329 #include "rs6000-builtin.def"
11332 /* SPE predicates. */
11333 #undef RS6000_BUILTIN_1
11334 #undef RS6000_BUILTIN_2
11335 #undef RS6000_BUILTIN_3
11336 #undef RS6000_BUILTIN_A
11337 #undef RS6000_BUILTIN_D
11338 #undef RS6000_BUILTIN_E
11339 #undef RS6000_BUILTIN_H
11340 #undef RS6000_BUILTIN_P
11341 #undef RS6000_BUILTIN_Q
11342 #undef RS6000_BUILTIN_S
11343 #undef RS6000_BUILTIN_X
11345 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11346 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11347 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11348 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11349 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11350 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11351 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11352 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11353 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11354 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
11355 { MASK, ICODE, NAME, ENUM },
11357 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11359 static const struct builtin_description bdesc_spe_predicates
[] =
11361 #include "rs6000-builtin.def"
11364 /* SPE evsel predicates. */
11365 #undef RS6000_BUILTIN_1
11366 #undef RS6000_BUILTIN_2
11367 #undef RS6000_BUILTIN_3
11368 #undef RS6000_BUILTIN_A
11369 #undef RS6000_BUILTIN_D
11370 #undef RS6000_BUILTIN_E
11371 #undef RS6000_BUILTIN_H
11372 #undef RS6000_BUILTIN_P
11373 #undef RS6000_BUILTIN_Q
11374 #undef RS6000_BUILTIN_S
11375 #undef RS6000_BUILTIN_X
11377 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11378 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11379 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11380 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11381 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11382 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
11383 { MASK, ICODE, NAME, ENUM },
11385 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11386 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11387 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11388 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11389 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11391 static const struct builtin_description bdesc_spe_evsel
[] =
11393 #include "rs6000-builtin.def"
11396 /* PAIRED predicates. */
11397 #undef RS6000_BUILTIN_1
11398 #undef RS6000_BUILTIN_2
11399 #undef RS6000_BUILTIN_3
11400 #undef RS6000_BUILTIN_A
11401 #undef RS6000_BUILTIN_D
11402 #undef RS6000_BUILTIN_E
11403 #undef RS6000_BUILTIN_H
11404 #undef RS6000_BUILTIN_P
11405 #undef RS6000_BUILTIN_Q
11406 #undef RS6000_BUILTIN_S
11407 #undef RS6000_BUILTIN_X
11409 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11410 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11411 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11412 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11413 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11414 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11415 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11416 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11417 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
11418 { MASK, ICODE, NAME, ENUM },
11420 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11421 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11423 static const struct builtin_description bdesc_paired_preds
[] =
11425 #include "rs6000-builtin.def"
11428 /* ABS* operations. */
11430 #undef RS6000_BUILTIN_1
11431 #undef RS6000_BUILTIN_2
11432 #undef RS6000_BUILTIN_3
11433 #undef RS6000_BUILTIN_A
11434 #undef RS6000_BUILTIN_D
11435 #undef RS6000_BUILTIN_E
11436 #undef RS6000_BUILTIN_H
11437 #undef RS6000_BUILTIN_P
11438 #undef RS6000_BUILTIN_Q
11439 #undef RS6000_BUILTIN_S
11440 #undef RS6000_BUILTIN_X
11442 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11443 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11444 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11445 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
11446 { MASK, ICODE, NAME, ENUM },
11448 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11449 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11450 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11451 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11452 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11453 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11454 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11456 static const struct builtin_description bdesc_abs
[] =
11458 #include "rs6000-builtin.def"
11461 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
11464 #undef RS6000_BUILTIN_1
11465 #undef RS6000_BUILTIN_2
11466 #undef RS6000_BUILTIN_3
11467 #undef RS6000_BUILTIN_A
11468 #undef RS6000_BUILTIN_D
11469 #undef RS6000_BUILTIN_E
11470 #undef RS6000_BUILTIN_H
11471 #undef RS6000_BUILTIN_P
11472 #undef RS6000_BUILTIN_Q
11473 #undef RS6000_BUILTIN_S
11474 #undef RS6000_BUILTIN_X
11476 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
11477 { MASK, ICODE, NAME, ENUM },
11479 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11480 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11481 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11482 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11483 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11484 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11485 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11486 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11487 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11488 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11490 static const struct builtin_description bdesc_1arg
[] =
11492 #include "rs6000-builtin.def"
11495 /* HTM builtins. */
11496 #undef RS6000_BUILTIN_1
11497 #undef RS6000_BUILTIN_2
11498 #undef RS6000_BUILTIN_3
11499 #undef RS6000_BUILTIN_A
11500 #undef RS6000_BUILTIN_D
11501 #undef RS6000_BUILTIN_E
11502 #undef RS6000_BUILTIN_H
11503 #undef RS6000_BUILTIN_P
11504 #undef RS6000_BUILTIN_Q
11505 #undef RS6000_BUILTIN_S
11506 #undef RS6000_BUILTIN_X
11508 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11509 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11510 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11511 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11512 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11513 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11514 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
11515 { MASK, ICODE, NAME, ENUM },
11517 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11518 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11519 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11520 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11522 static const struct builtin_description bdesc_htm
[] =
11524 #include "rs6000-builtin.def"
11527 #undef RS6000_BUILTIN_1
11528 #undef RS6000_BUILTIN_2
11529 #undef RS6000_BUILTIN_3
11530 #undef RS6000_BUILTIN_A
11531 #undef RS6000_BUILTIN_D
11532 #undef RS6000_BUILTIN_E
11533 #undef RS6000_BUILTIN_H
11534 #undef RS6000_BUILTIN_P
11535 #undef RS6000_BUILTIN_Q
11536 #undef RS6000_BUILTIN_S
11538 /* Return true if a builtin function is overloaded. */
11540 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
11542 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
11545 /* Expand an expression EXP that calls a builtin without arguments. */
11547 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
11550 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11552 if (icode
== CODE_FOR_nothing
)
11553 /* Builtin not supported on this processor. */
11557 || GET_MODE (target
) != tmode
11558 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11559 target
= gen_reg_rtx (tmode
);
11561 pat
= GEN_FCN (icode
) (target
);
11571 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
11574 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11575 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11576 rtx op0
= expand_normal (arg0
);
11577 rtx op1
= expand_normal (arg1
);
11578 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
11579 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
11581 if (icode
== CODE_FOR_nothing
)
11582 /* Builtin not supported on this processor. */
11585 /* If we got invalid arguments bail out before generating bad rtl. */
11586 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11589 if (GET_CODE (op0
) != CONST_INT
11590 || INTVAL (op0
) > 255
11591 || INTVAL (op0
) < 0)
11593 error ("argument 1 must be an 8-bit field value");
11597 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11598 op0
= copy_to_mode_reg (mode0
, op0
);
11600 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11601 op1
= copy_to_mode_reg (mode1
, op1
);
11603 pat
= GEN_FCN (icode
) (op0
, op1
);
11613 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11616 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11617 rtx op0
= expand_normal (arg0
);
11618 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11619 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11621 if (icode
== CODE_FOR_nothing
)
11622 /* Builtin not supported on this processor. */
11625 /* If we got invalid arguments bail out before generating bad rtl. */
11626 if (arg0
== error_mark_node
)
11629 if (icode
== CODE_FOR_altivec_vspltisb
11630 || icode
== CODE_FOR_altivec_vspltish
11631 || icode
== CODE_FOR_altivec_vspltisw
11632 || icode
== CODE_FOR_spe_evsplatfi
11633 || icode
== CODE_FOR_spe_evsplati
)
11635 /* Only allow 5-bit *signed* literals. */
11636 if (GET_CODE (op0
) != CONST_INT
11637 || INTVAL (op0
) > 15
11638 || INTVAL (op0
) < -16)
11640 error ("argument 1 must be a 5-bit signed literal");
11646 || GET_MODE (target
) != tmode
11647 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11648 target
= gen_reg_rtx (tmode
);
11650 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11651 op0
= copy_to_mode_reg (mode0
, op0
);
11653 pat
= GEN_FCN (icode
) (target
, op0
);
11662 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
11664 rtx pat
, scratch1
, scratch2
;
11665 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11666 rtx op0
= expand_normal (arg0
);
11667 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11668 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11670 /* If we have invalid arguments, bail out before generating bad rtl. */
11671 if (arg0
== error_mark_node
)
11675 || GET_MODE (target
) != tmode
11676 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11677 target
= gen_reg_rtx (tmode
);
11679 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11680 op0
= copy_to_mode_reg (mode0
, op0
);
11682 scratch1
= gen_reg_rtx (mode0
);
11683 scratch2
= gen_reg_rtx (mode0
);
11685 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
11694 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11697 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11698 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11699 rtx op0
= expand_normal (arg0
);
11700 rtx op1
= expand_normal (arg1
);
11701 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11702 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11703 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11705 if (icode
== CODE_FOR_nothing
)
11706 /* Builtin not supported on this processor. */
11709 /* If we got invalid arguments bail out before generating bad rtl. */
11710 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11713 if (icode
== CODE_FOR_altivec_vcfux
11714 || icode
== CODE_FOR_altivec_vcfsx
11715 || icode
== CODE_FOR_altivec_vctsxs
11716 || icode
== CODE_FOR_altivec_vctuxs
11717 || icode
== CODE_FOR_altivec_vspltb
11718 || icode
== CODE_FOR_altivec_vsplth
11719 || icode
== CODE_FOR_altivec_vspltw
11720 || icode
== CODE_FOR_spe_evaddiw
11721 || icode
== CODE_FOR_spe_evldd
11722 || icode
== CODE_FOR_spe_evldh
11723 || icode
== CODE_FOR_spe_evldw
11724 || icode
== CODE_FOR_spe_evlhhesplat
11725 || icode
== CODE_FOR_spe_evlhhossplat
11726 || icode
== CODE_FOR_spe_evlhhousplat
11727 || icode
== CODE_FOR_spe_evlwhe
11728 || icode
== CODE_FOR_spe_evlwhos
11729 || icode
== CODE_FOR_spe_evlwhou
11730 || icode
== CODE_FOR_spe_evlwhsplat
11731 || icode
== CODE_FOR_spe_evlwwsplat
11732 || icode
== CODE_FOR_spe_evrlwi
11733 || icode
== CODE_FOR_spe_evslwi
11734 || icode
== CODE_FOR_spe_evsrwis
11735 || icode
== CODE_FOR_spe_evsubifw
11736 || icode
== CODE_FOR_spe_evsrwiu
)
11738 /* Only allow 5-bit unsigned literals. */
11740 if (TREE_CODE (arg1
) != INTEGER_CST
11741 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11743 error ("argument 2 must be a 5-bit unsigned literal");
11749 || GET_MODE (target
) != tmode
11750 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11751 target
= gen_reg_rtx (tmode
);
11753 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11754 op0
= copy_to_mode_reg (mode0
, op0
);
11755 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11756 op1
= copy_to_mode_reg (mode1
, op1
);
11758 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11767 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11770 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
11771 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11772 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11773 rtx op0
= expand_normal (arg0
);
11774 rtx op1
= expand_normal (arg1
);
11775 enum machine_mode tmode
= SImode
;
11776 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11777 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11780 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
11782 error ("argument 1 of __builtin_altivec_predicate must be a constant");
11786 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
11788 gcc_assert (mode0
== mode1
);
11790 /* If we have invalid arguments, bail out before generating bad rtl. */
11791 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11795 || GET_MODE (target
) != tmode
11796 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11797 target
= gen_reg_rtx (tmode
);
11799 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11800 op0
= copy_to_mode_reg (mode0
, op0
);
11801 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11802 op1
= copy_to_mode_reg (mode1
, op1
);
11804 scratch
= gen_reg_rtx (mode0
);
11806 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11811 /* The vec_any* and vec_all* predicates use the same opcodes for two
11812 different operations, but the bits in CR6 will be different
11813 depending on what information we want. So we have to play tricks
11814 with CR6 to get the right bits out.
11816 If you think this is disgusting, look at the specs for the
11817 AltiVec predicates. */
11819 switch (cr6_form_int
)
11822 emit_insn (gen_cr6_test_for_zero (target
));
11825 emit_insn (gen_cr6_test_for_zero_reverse (target
));
11828 emit_insn (gen_cr6_test_for_lt (target
));
11831 emit_insn (gen_cr6_test_for_lt_reverse (target
));
11834 error ("argument 1 of __builtin_altivec_predicate is out of range");
11842 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
11845 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11846 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11847 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11848 enum machine_mode mode0
= Pmode
;
11849 enum machine_mode mode1
= Pmode
;
11850 rtx op0
= expand_normal (arg0
);
11851 rtx op1
= expand_normal (arg1
);
11853 if (icode
== CODE_FOR_nothing
)
11854 /* Builtin not supported on this processor. */
11857 /* If we got invalid arguments bail out before generating bad rtl. */
11858 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11862 || GET_MODE (target
) != tmode
11863 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11864 target
= gen_reg_rtx (tmode
);
11866 op1
= copy_to_mode_reg (mode1
, op1
);
11868 if (op0
== const0_rtx
)
11870 addr
= gen_rtx_MEM (tmode
, op1
);
11874 op0
= copy_to_mode_reg (mode0
, op0
);
11875 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11878 pat
= GEN_FCN (icode
) (target
, addr
);
11887 /* Return a constant vector for use as a little-endian permute control vector
11888 to reverse the order of elements of the given vector mode. */
11890 swap_selector_for_mode (enum machine_mode mode
)
11892 /* These are little endian vectors, so their elements are reversed
11893 from what you would normally expect for a permute control vector. */
11894 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
11895 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
11896 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
11897 unsigned int swap16
[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
11898 unsigned int *swaparray
, i
;
11915 swaparray
= swap16
;
11918 gcc_unreachable ();
11921 for (i
= 0; i
< 16; ++i
)
11922 perm
[i
] = GEN_INT (swaparray
[i
]);
11924 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
)));
11927 /* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target
11928 with -maltivec=be specified. Issue the load followed by an element-reversing
11931 altivec_expand_lvx_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
11933 rtx tmp
= gen_reg_rtx (mode
);
11934 rtx load
= gen_rtx_SET (VOIDmode
, tmp
, op1
);
11935 rtx lvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
11936 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, load
, lvx
));
11937 rtx sel
= swap_selector_for_mode (mode
);
11938 rtx vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, tmp
, tmp
, sel
), UNSPEC_VPERM
);
11940 gcc_assert (REG_P (op0
));
11942 emit_insn (gen_rtx_SET (VOIDmode
, op0
, vperm
));
11945 /* Generate code for a "stvx" or "stvxl" built-in for a little endian target
11946 with -maltivec=be specified. Issue the store preceded by an element-reversing
11949 altivec_expand_stvx_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
11951 rtx tmp
= gen_reg_rtx (mode
);
11952 rtx store
= gen_rtx_SET (VOIDmode
, op0
, tmp
);
11953 rtx stvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
11954 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, store
, stvx
));
11955 rtx sel
= swap_selector_for_mode (mode
);
11958 gcc_assert (REG_P (op1
));
11959 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
11960 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, vperm
));
11964 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
11965 specified. Issue the store preceded by an element-reversing permute. */
11967 altivec_expand_stvex_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
11969 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
11970 rtx tmp
= gen_reg_rtx (mode
);
11971 rtx stvx
= gen_rtx_UNSPEC (inner_mode
, gen_rtvec (1, tmp
), unspec
);
11972 rtx sel
= swap_selector_for_mode (mode
);
11975 gcc_assert (REG_P (op1
));
11976 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
11977 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, vperm
));
11978 emit_insn (gen_rtx_SET (VOIDmode
, op0
, stvx
));
11982 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
11985 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11986 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11987 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11988 enum machine_mode mode0
= Pmode
;
11989 enum machine_mode mode1
= Pmode
;
11990 rtx op0
= expand_normal (arg0
);
11991 rtx op1
= expand_normal (arg1
);
11993 if (icode
== CODE_FOR_nothing
)
11994 /* Builtin not supported on this processor. */
11997 /* If we got invalid arguments bail out before generating bad rtl. */
11998 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12002 || GET_MODE (target
) != tmode
12003 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12004 target
= gen_reg_rtx (tmode
);
12006 op1
= copy_to_mode_reg (mode1
, op1
);
12008 if (op0
== const0_rtx
)
12010 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
12014 op0
= copy_to_mode_reg (mode0
, op0
);
12015 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
12018 pat
= GEN_FCN (icode
) (target
, addr
);
12028 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
12030 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12031 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12032 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12033 rtx op0
= expand_normal (arg0
);
12034 rtx op1
= expand_normal (arg1
);
12035 rtx op2
= expand_normal (arg2
);
12037 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12038 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12039 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
12041 /* Invalid arguments. Bail before doing anything stoopid! */
12042 if (arg0
== error_mark_node
12043 || arg1
== error_mark_node
12044 || arg2
== error_mark_node
)
12047 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
12048 op0
= copy_to_mode_reg (mode2
, op0
);
12049 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
12050 op1
= copy_to_mode_reg (mode0
, op1
);
12051 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
12052 op2
= copy_to_mode_reg (mode1
, op2
);
12054 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
12061 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
12063 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12064 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12065 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12066 rtx op0
= expand_normal (arg0
);
12067 rtx op1
= expand_normal (arg1
);
12068 rtx op2
= expand_normal (arg2
);
12070 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12071 enum machine_mode mode1
= Pmode
;
12072 enum machine_mode mode2
= Pmode
;
12074 /* Invalid arguments. Bail before doing anything stoopid! */
12075 if (arg0
== error_mark_node
12076 || arg1
== error_mark_node
12077 || arg2
== error_mark_node
)
12080 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
12081 op0
= copy_to_mode_reg (tmode
, op0
);
12083 op2
= copy_to_mode_reg (mode2
, op2
);
12085 if (op1
== const0_rtx
)
12087 addr
= gen_rtx_MEM (tmode
, op2
);
12091 op1
= copy_to_mode_reg (mode1
, op1
);
12092 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12095 pat
= GEN_FCN (icode
) (addr
, op0
);
12102 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
12104 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12105 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12106 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12107 rtx op0
= expand_normal (arg0
);
12108 rtx op1
= expand_normal (arg1
);
12109 rtx op2
= expand_normal (arg2
);
12111 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12112 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
12113 enum machine_mode mode1
= Pmode
;
12114 enum machine_mode mode2
= Pmode
;
12116 /* Invalid arguments. Bail before doing anything stoopid! */
12117 if (arg0
== error_mark_node
12118 || arg1
== error_mark_node
12119 || arg2
== error_mark_node
)
12122 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
12123 op0
= copy_to_mode_reg (smode
, op0
);
12125 op2
= copy_to_mode_reg (mode2
, op2
);
12127 if (op1
== const0_rtx
)
12129 addr
= gen_rtx_MEM (tmode
, op2
);
12133 op1
= copy_to_mode_reg (mode1
, op1
);
12134 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12137 pat
= GEN_FCN (icode
) (addr
, op0
);
12143 /* Return the appropriate SPR number associated with the given builtin. */
12144 static inline HOST_WIDE_INT
12145 htm_spr_num (enum rs6000_builtins code
)
12147 if (code
== HTM_BUILTIN_GET_TFHAR
12148 || code
== HTM_BUILTIN_SET_TFHAR
)
12150 else if (code
== HTM_BUILTIN_GET_TFIAR
12151 || code
== HTM_BUILTIN_SET_TFIAR
)
12153 else if (code
== HTM_BUILTIN_GET_TEXASR
12154 || code
== HTM_BUILTIN_SET_TEXASR
)
12156 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
12157 || code
== HTM_BUILTIN_SET_TEXASRU
);
12158 return TEXASRU_SPR
;
12161 /* Return the appropriate SPR regno associated with the given builtin. */
12162 static inline HOST_WIDE_INT
12163 htm_spr_regno (enum rs6000_builtins code
)
12165 if (code
== HTM_BUILTIN_GET_TFHAR
12166 || code
== HTM_BUILTIN_SET_TFHAR
)
12167 return TFHAR_REGNO
;
12168 else if (code
== HTM_BUILTIN_GET_TFIAR
12169 || code
== HTM_BUILTIN_SET_TFIAR
)
12170 return TFIAR_REGNO
;
12171 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
12172 || code
== HTM_BUILTIN_SET_TEXASR
12173 || code
== HTM_BUILTIN_GET_TEXASRU
12174 || code
== HTM_BUILTIN_SET_TEXASRU
);
12175 return TEXASR_REGNO
;
12178 /* Return the correct ICODE value depending on whether we are
12179 setting or reading the HTM SPRs. */
12180 static inline enum insn_code
12181 rs6000_htm_spr_icode (bool nonvoid
)
12184 return (TARGET_64BIT
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
12186 return (TARGET_64BIT
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
12189 /* Expand the HTM builtin in EXP and store the result in TARGET.
12190 Store true in *EXPANDEDP if we found a builtin to expand. */
12192 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
12194 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12195 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
12196 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12197 const struct builtin_description
*d
;
12200 *expandedp
= false;
12202 /* Expand the HTM builtins. */
12204 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
12205 if (d
->code
== fcode
)
12207 rtx op
[MAX_HTM_OPERANDS
], pat
;
12210 call_expr_arg_iterator iter
;
12211 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
12212 enum insn_code icode
= d
->icode
;
12214 if (attr
& RS6000_BTC_SPR
)
12215 icode
= rs6000_htm_spr_icode (nonvoid
);
12219 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12221 || GET_MODE (target
) != tmode
12222 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12223 target
= gen_reg_rtx (tmode
);
12224 op
[nopnds
++] = target
;
12227 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
12229 const struct insn_operand_data
*insn_op
;
12231 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
12234 insn_op
= &insn_data
[icode
].operand
[nopnds
];
12236 op
[nopnds
] = expand_normal (arg
);
12238 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
12240 if (!strcmp (insn_op
->constraint
, "n"))
12242 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
12243 if (!CONST_INT_P (op
[nopnds
]))
12244 error ("argument %d must be an unsigned literal", arg_num
);
12246 error ("argument %d is an unsigned literal that is "
12247 "out of range", arg_num
);
12250 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
12256 /* Handle the builtins for extended mnemonics. These accept
12257 no arguments, but map to builtins that take arguments. */
12260 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
12261 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
12262 op
[nopnds
++] = GEN_INT (1);
12263 #ifdef ENABLE_CHECKING
12264 attr
|= RS6000_BTC_UNARY
;
12267 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
12268 op
[nopnds
++] = GEN_INT (0);
12269 #ifdef ENABLE_CHECKING
12270 attr
|= RS6000_BTC_UNARY
;
12277 /* If this builtin accesses SPRs, then pass in the appropriate
12278 SPR number and SPR regno as the last two operands. */
12279 if (attr
& RS6000_BTC_SPR
)
12281 op
[nopnds
++] = gen_rtx_CONST_INT (Pmode
, htm_spr_num (fcode
));
12282 op
[nopnds
++] = gen_rtx_REG (Pmode
, htm_spr_regno (fcode
));
12285 #ifdef ENABLE_CHECKING
12286 int expected_nopnds
= 0;
12287 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
12288 expected_nopnds
= 1;
12289 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
12290 expected_nopnds
= 2;
12291 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
12292 expected_nopnds
= 3;
12293 if (!(attr
& RS6000_BTC_VOID
))
12294 expected_nopnds
+= 1;
12295 if (attr
& RS6000_BTC_SPR
)
12296 expected_nopnds
+= 2;
12298 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
12304 pat
= GEN_FCN (icode
) (op
[0]);
12307 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
12310 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
12313 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
12316 gcc_unreachable ();
12332 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12335 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12336 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12337 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12338 rtx op0
= expand_normal (arg0
);
12339 rtx op1
= expand_normal (arg1
);
12340 rtx op2
= expand_normal (arg2
);
12341 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12342 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12343 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12344 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
12346 if (icode
== CODE_FOR_nothing
)
12347 /* Builtin not supported on this processor. */
12350 /* If we got invalid arguments bail out before generating bad rtl. */
12351 if (arg0
== error_mark_node
12352 || arg1
== error_mark_node
12353 || arg2
== error_mark_node
)
12356 /* Check and prepare argument depending on the instruction code.
12358 Note that a switch statement instead of the sequence of tests
12359 would be incorrect as many of the CODE_FOR values could be
12360 CODE_FOR_nothing and that would yield multiple alternatives
12361 with identical values. We'd never reach here at runtime in
12363 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
12364 || icode
== CODE_FOR_altivec_vsldoi_v4si
12365 || icode
== CODE_FOR_altivec_vsldoi_v8hi
12366 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
12368 /* Only allow 4-bit unsigned literals. */
12370 if (TREE_CODE (arg2
) != INTEGER_CST
12371 || TREE_INT_CST_LOW (arg2
) & ~0xf)
12373 error ("argument 3 must be a 4-bit unsigned literal");
12377 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
12378 || icode
== CODE_FOR_vsx_xxpermdi_v2di
12379 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
12380 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
12381 || icode
== CODE_FOR_vsx_xxsldwi_v4si
12382 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
12383 || icode
== CODE_FOR_vsx_xxsldwi_v2di
12384 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
12386 /* Only allow 2-bit unsigned literals. */
12388 if (TREE_CODE (arg2
) != INTEGER_CST
12389 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12391 error ("argument 3 must be a 2-bit unsigned literal");
12395 else if (icode
== CODE_FOR_vsx_set_v2df
12396 || icode
== CODE_FOR_vsx_set_v2di
)
12398 /* Only allow 1-bit unsigned literals. */
12400 if (TREE_CODE (arg2
) != INTEGER_CST
12401 || TREE_INT_CST_LOW (arg2
) & ~0x1)
12403 error ("argument 3 must be a 1-bit unsigned literal");
12407 else if (icode
== CODE_FOR_crypto_vshasigmaw
12408 || icode
== CODE_FOR_crypto_vshasigmad
)
12410 /* Check whether the 2nd and 3rd arguments are integer constants and in
12411 range and prepare arguments. */
12413 if (TREE_CODE (arg1
) != INTEGER_CST
12414 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 1))
12416 error ("argument 2 must be 0 or 1");
12421 if (TREE_CODE (arg2
) != INTEGER_CST
12422 || !IN_RANGE (TREE_INT_CST_LOW (arg2
), 0, 15))
12424 error ("argument 3 must be in the range 0..15");
12430 || GET_MODE (target
) != tmode
12431 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12432 target
= gen_reg_rtx (tmode
);
12434 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12435 op0
= copy_to_mode_reg (mode0
, op0
);
12436 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12437 op1
= copy_to_mode_reg (mode1
, op1
);
12438 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12439 op2
= copy_to_mode_reg (mode2
, op2
);
12441 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
12442 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
12444 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12452 /* Expand the lvx builtins. */
12454 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
12456 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12457 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12459 enum machine_mode tmode
, mode0
;
12461 enum insn_code icode
;
12465 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
12466 icode
= CODE_FOR_vector_altivec_load_v16qi
;
12468 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
12469 icode
= CODE_FOR_vector_altivec_load_v8hi
;
12471 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
12472 icode
= CODE_FOR_vector_altivec_load_v4si
;
12474 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
12475 icode
= CODE_FOR_vector_altivec_load_v4sf
;
12477 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
12478 icode
= CODE_FOR_vector_altivec_load_v2df
;
12480 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
12481 icode
= CODE_FOR_vector_altivec_load_v2di
;
12482 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti
:
12483 icode
= CODE_FOR_vector_altivec_load_v1ti
;
12486 *expandedp
= false;
12492 arg0
= CALL_EXPR_ARG (exp
, 0);
12493 op0
= expand_normal (arg0
);
12494 tmode
= insn_data
[icode
].operand
[0].mode
;
12495 mode0
= insn_data
[icode
].operand
[1].mode
;
12498 || GET_MODE (target
) != tmode
12499 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12500 target
= gen_reg_rtx (tmode
);
12502 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12503 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12505 pat
= GEN_FCN (icode
) (target
, op0
);
12512 /* Expand the stvx builtins. */
12514 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12517 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12518 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12520 enum machine_mode mode0
, mode1
;
12522 enum insn_code icode
;
12526 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
12527 icode
= CODE_FOR_vector_altivec_store_v16qi
;
12529 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
12530 icode
= CODE_FOR_vector_altivec_store_v8hi
;
12532 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
12533 icode
= CODE_FOR_vector_altivec_store_v4si
;
12535 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
12536 icode
= CODE_FOR_vector_altivec_store_v4sf
;
12538 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
12539 icode
= CODE_FOR_vector_altivec_store_v2df
;
12541 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
12542 icode
= CODE_FOR_vector_altivec_store_v2di
;
12543 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti
:
12544 icode
= CODE_FOR_vector_altivec_store_v1ti
;
12547 *expandedp
= false;
12551 arg0
= CALL_EXPR_ARG (exp
, 0);
12552 arg1
= CALL_EXPR_ARG (exp
, 1);
12553 op0
= expand_normal (arg0
);
12554 op1
= expand_normal (arg1
);
12555 mode0
= insn_data
[icode
].operand
[0].mode
;
12556 mode1
= insn_data
[icode
].operand
[1].mode
;
12558 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12559 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12560 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12561 op1
= copy_to_mode_reg (mode1
, op1
);
12563 pat
= GEN_FCN (icode
) (op0
, op1
);
12571 /* Expand the dst builtins. */
12573 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12576 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12577 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12578 tree arg0
, arg1
, arg2
;
12579 enum machine_mode mode0
, mode1
;
12580 rtx pat
, op0
, op1
, op2
;
12581 const struct builtin_description
*d
;
12584 *expandedp
= false;
12586 /* Handle DST variants. */
12588 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12589 if (d
->code
== fcode
)
12591 arg0
= CALL_EXPR_ARG (exp
, 0);
12592 arg1
= CALL_EXPR_ARG (exp
, 1);
12593 arg2
= CALL_EXPR_ARG (exp
, 2);
12594 op0
= expand_normal (arg0
);
12595 op1
= expand_normal (arg1
);
12596 op2
= expand_normal (arg2
);
12597 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12598 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12600 /* Invalid arguments, bail out before generating bad rtl. */
12601 if (arg0
== error_mark_node
12602 || arg1
== error_mark_node
12603 || arg2
== error_mark_node
)
12608 if (TREE_CODE (arg2
) != INTEGER_CST
12609 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12611 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
12615 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
12616 op0
= copy_to_mode_reg (Pmode
, op0
);
12617 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
12618 op1
= copy_to_mode_reg (mode1
, op1
);
12620 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
12630 /* Expand vec_init builtin. */
12632 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
12634 enum machine_mode tmode
= TYPE_MODE (type
);
12635 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
12636 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
12638 gcc_assert (VECTOR_MODE_P (tmode
));
12639 gcc_assert (n_elt
== call_expr_nargs (exp
));
12641 if (!target
|| !register_operand (target
, tmode
))
12642 target
= gen_reg_rtx (tmode
);
12644 /* If we have a vector compromised of a single element, such as V1TImode, do
12645 the initialization directly. */
12646 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
12648 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
12649 emit_move_insn (target
, gen_lowpart (tmode
, x
));
12653 rtvec v
= rtvec_alloc (n_elt
);
12655 for (i
= 0; i
< n_elt
; ++i
)
12657 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
12658 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
12661 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
12667 /* Return the integer constant in ARG. Constrain it to be in the range
12668 of the subparts of VEC_TYPE; issue an error if not. */
12671 get_element_number (tree vec_type
, tree arg
)
12673 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
12675 if (!tree_fits_uhwi_p (arg
)
12676 || (elt
= tree_to_uhwi (arg
), elt
> max
))
12678 error ("selector must be an integer constant in the range 0..%wi", max
);
12685 /* Expand vec_set builtin. */
12687 altivec_expand_vec_set_builtin (tree exp
)
12689 enum machine_mode tmode
, mode1
;
12690 tree arg0
, arg1
, arg2
;
12694 arg0
= CALL_EXPR_ARG (exp
, 0);
12695 arg1
= CALL_EXPR_ARG (exp
, 1);
12696 arg2
= CALL_EXPR_ARG (exp
, 2);
12698 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
12699 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12700 gcc_assert (VECTOR_MODE_P (tmode
));
12702 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
12703 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
12704 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
12706 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
12707 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
12709 op0
= force_reg (tmode
, op0
);
12710 op1
= force_reg (mode1
, op1
);
12712 rs6000_expand_vector_set (op0
, op1
, elt
);
12717 /* Expand vec_ext builtin. */
12719 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
12721 enum machine_mode tmode
, mode0
;
12726 arg0
= CALL_EXPR_ARG (exp
, 0);
12727 arg1
= CALL_EXPR_ARG (exp
, 1);
12729 op0
= expand_normal (arg0
);
12730 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
12732 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12733 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
12734 gcc_assert (VECTOR_MODE_P (mode0
));
12736 op0
= force_reg (mode0
, op0
);
12738 if (optimize
|| !target
|| !register_operand (target
, tmode
))
12739 target
= gen_reg_rtx (tmode
);
12741 rs6000_expand_vector_extract (target
, op0
, elt
);
12746 /* Expand the builtin in EXP and store the result in TARGET. Store
12747 true in *EXPANDEDP if we found a builtin to expand. */
12749 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12751 const struct builtin_description
*d
;
12753 enum insn_code icode
;
12754 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12757 enum machine_mode tmode
, mode0
;
12758 enum rs6000_builtins fcode
12759 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12761 if (rs6000_overloaded_builtin_p (fcode
))
12764 error ("unresolved overload for Altivec builtin %qF", fndecl
);
12766 /* Given it is invalid, just generate a normal call. */
12767 return expand_call (exp
, target
, false);
12770 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
12774 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
12778 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
12786 case ALTIVEC_BUILTIN_STVX_V2DF
:
12787 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df
, exp
);
12788 case ALTIVEC_BUILTIN_STVX_V2DI
:
12789 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di
, exp
);
12790 case ALTIVEC_BUILTIN_STVX_V4SF
:
12791 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf
, exp
);
12792 case ALTIVEC_BUILTIN_STVX
:
12793 case ALTIVEC_BUILTIN_STVX_V4SI
:
12794 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
12795 case ALTIVEC_BUILTIN_STVX_V8HI
:
12796 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi
, exp
);
12797 case ALTIVEC_BUILTIN_STVX_V16QI
:
12798 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi
, exp
);
12799 case ALTIVEC_BUILTIN_STVEBX
:
12800 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
12801 case ALTIVEC_BUILTIN_STVEHX
:
12802 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
12803 case ALTIVEC_BUILTIN_STVEWX
:
12804 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
12805 case ALTIVEC_BUILTIN_STVXL_V2DF
:
12806 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
12807 case ALTIVEC_BUILTIN_STVXL_V2DI
:
12808 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
12809 case ALTIVEC_BUILTIN_STVXL_V4SF
:
12810 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
12811 case ALTIVEC_BUILTIN_STVXL
:
12812 case ALTIVEC_BUILTIN_STVXL_V4SI
:
12813 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
12814 case ALTIVEC_BUILTIN_STVXL_V8HI
:
12815 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
12816 case ALTIVEC_BUILTIN_STVXL_V16QI
:
12817 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
12819 case ALTIVEC_BUILTIN_STVLX
:
12820 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
12821 case ALTIVEC_BUILTIN_STVLXL
:
12822 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
12823 case ALTIVEC_BUILTIN_STVRX
:
12824 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
12825 case ALTIVEC_BUILTIN_STVRXL
:
12826 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
12828 case VSX_BUILTIN_STXVD2X_V1TI
:
12829 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
12830 case VSX_BUILTIN_STXVD2X_V2DF
:
12831 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
12832 case VSX_BUILTIN_STXVD2X_V2DI
:
12833 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
12834 case VSX_BUILTIN_STXVW4X_V4SF
:
12835 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
12836 case VSX_BUILTIN_STXVW4X_V4SI
:
12837 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
12838 case VSX_BUILTIN_STXVW4X_V8HI
:
12839 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
12840 case VSX_BUILTIN_STXVW4X_V16QI
:
12841 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
12843 case ALTIVEC_BUILTIN_MFVSCR
:
12844 icode
= CODE_FOR_altivec_mfvscr
;
12845 tmode
= insn_data
[icode
].operand
[0].mode
;
12848 || GET_MODE (target
) != tmode
12849 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12850 target
= gen_reg_rtx (tmode
);
12852 pat
= GEN_FCN (icode
) (target
);
12858 case ALTIVEC_BUILTIN_MTVSCR
:
12859 icode
= CODE_FOR_altivec_mtvscr
;
12860 arg0
= CALL_EXPR_ARG (exp
, 0);
12861 op0
= expand_normal (arg0
);
12862 mode0
= insn_data
[icode
].operand
[0].mode
;
12864 /* If we got invalid arguments bail out before generating bad rtl. */
12865 if (arg0
== error_mark_node
)
12868 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12869 op0
= copy_to_mode_reg (mode0
, op0
);
12871 pat
= GEN_FCN (icode
) (op0
);
12876 case ALTIVEC_BUILTIN_DSSALL
:
12877 emit_insn (gen_altivec_dssall ());
12880 case ALTIVEC_BUILTIN_DSS
:
12881 icode
= CODE_FOR_altivec_dss
;
12882 arg0
= CALL_EXPR_ARG (exp
, 0);
12884 op0
= expand_normal (arg0
);
12885 mode0
= insn_data
[icode
].operand
[0].mode
;
12887 /* If we got invalid arguments bail out before generating bad rtl. */
12888 if (arg0
== error_mark_node
)
12891 if (TREE_CODE (arg0
) != INTEGER_CST
12892 || TREE_INT_CST_LOW (arg0
) & ~0x3)
12894 error ("argument to dss must be a 2-bit unsigned literal");
12898 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12899 op0
= copy_to_mode_reg (mode0
, op0
);
12901 emit_insn (gen_altivec_dss (op0
));
12904 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
12905 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
12906 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
12907 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
12908 case VSX_BUILTIN_VEC_INIT_V2DF
:
12909 case VSX_BUILTIN_VEC_INIT_V2DI
:
12910 case VSX_BUILTIN_VEC_INIT_V1TI
:
12911 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
12913 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
12914 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
12915 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
12916 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
12917 case VSX_BUILTIN_VEC_SET_V2DF
:
12918 case VSX_BUILTIN_VEC_SET_V2DI
:
12919 case VSX_BUILTIN_VEC_SET_V1TI
:
12920 return altivec_expand_vec_set_builtin (exp
);
12922 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
12923 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
12924 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
12925 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
12926 case VSX_BUILTIN_VEC_EXT_V2DF
:
12927 case VSX_BUILTIN_VEC_EXT_V2DI
:
12928 case VSX_BUILTIN_VEC_EXT_V1TI
:
12929 return altivec_expand_vec_ext_builtin (exp
, target
);
12933 /* Fall through. */
12936 /* Expand abs* operations. */
12938 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
12939 if (d
->code
== fcode
)
12940 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
12942 /* Expand the AltiVec predicates. */
12943 d
= bdesc_altivec_preds
;
12944 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
12945 if (d
->code
== fcode
)
12946 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
12948 /* LV* are funky. We initialized them differently. */
12951 case ALTIVEC_BUILTIN_LVSL
:
12952 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
12953 exp
, target
, false);
12954 case ALTIVEC_BUILTIN_LVSR
:
12955 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
12956 exp
, target
, false);
12957 case ALTIVEC_BUILTIN_LVEBX
:
12958 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
12959 exp
, target
, false);
12960 case ALTIVEC_BUILTIN_LVEHX
:
12961 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
12962 exp
, target
, false);
12963 case ALTIVEC_BUILTIN_LVEWX
:
12964 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
12965 exp
, target
, false);
12966 case ALTIVEC_BUILTIN_LVXL_V2DF
:
12967 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
12968 exp
, target
, false);
12969 case ALTIVEC_BUILTIN_LVXL_V2DI
:
12970 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
12971 exp
, target
, false);
12972 case ALTIVEC_BUILTIN_LVXL_V4SF
:
12973 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
12974 exp
, target
, false);
12975 case ALTIVEC_BUILTIN_LVXL
:
12976 case ALTIVEC_BUILTIN_LVXL_V4SI
:
12977 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
12978 exp
, target
, false);
12979 case ALTIVEC_BUILTIN_LVXL_V8HI
:
12980 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
12981 exp
, target
, false);
12982 case ALTIVEC_BUILTIN_LVXL_V16QI
:
12983 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
12984 exp
, target
, false);
12985 case ALTIVEC_BUILTIN_LVX_V2DF
:
12986 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df
,
12987 exp
, target
, false);
12988 case ALTIVEC_BUILTIN_LVX_V2DI
:
12989 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di
,
12990 exp
, target
, false);
12991 case ALTIVEC_BUILTIN_LVX_V4SF
:
12992 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf
,
12993 exp
, target
, false);
12994 case ALTIVEC_BUILTIN_LVX
:
12995 case ALTIVEC_BUILTIN_LVX_V4SI
:
12996 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
12997 exp
, target
, false);
12998 case ALTIVEC_BUILTIN_LVX_V8HI
:
12999 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi
,
13000 exp
, target
, false);
13001 case ALTIVEC_BUILTIN_LVX_V16QI
:
13002 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi
,
13003 exp
, target
, false);
13004 case ALTIVEC_BUILTIN_LVLX
:
13005 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
13006 exp
, target
, true);
13007 case ALTIVEC_BUILTIN_LVLXL
:
13008 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
13009 exp
, target
, true);
13010 case ALTIVEC_BUILTIN_LVRX
:
13011 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
13012 exp
, target
, true);
13013 case ALTIVEC_BUILTIN_LVRXL
:
13014 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
13015 exp
, target
, true);
13016 case VSX_BUILTIN_LXVD2X_V1TI
:
13017 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
13018 exp
, target
, false);
13019 case VSX_BUILTIN_LXVD2X_V2DF
:
13020 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
13021 exp
, target
, false);
13022 case VSX_BUILTIN_LXVD2X_V2DI
:
13023 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
13024 exp
, target
, false);
13025 case VSX_BUILTIN_LXVW4X_V4SF
:
13026 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
13027 exp
, target
, false);
13028 case VSX_BUILTIN_LXVW4X_V4SI
:
13029 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
13030 exp
, target
, false);
13031 case VSX_BUILTIN_LXVW4X_V8HI
:
13032 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
13033 exp
, target
, false);
13034 case VSX_BUILTIN_LXVW4X_V16QI
:
13035 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
13036 exp
, target
, false);
13040 /* Fall through. */
13043 *expandedp
= false;
13047 /* Expand the builtin in EXP and store the result in TARGET. Store
13048 true in *EXPANDEDP if we found a builtin to expand. */
13050 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
13052 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13053 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13054 const struct builtin_description
*d
;
13061 case PAIRED_BUILTIN_STX
:
13062 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
13063 case PAIRED_BUILTIN_LX
:
13064 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
13067 /* Fall through. */
13070 /* Expand the paired predicates. */
13071 d
= bdesc_paired_preds
;
13072 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
13073 if (d
->code
== fcode
)
13074 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
13076 *expandedp
= false;
13080 /* Binops that need to be initialized manually, but can be expanded
13081 automagically by rs6000_expand_binop_builtin. */
13082 static const struct builtin_description bdesc_2arg_spe
[] =
13084 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
13085 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
13086 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
13087 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
13088 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
13089 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
13090 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
13091 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
13092 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
13093 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
13094 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
13095 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
13096 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
13097 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
13098 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
13099 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
13100 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
13101 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
13102 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
13103 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
13104 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
13105 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
13108 /* Expand the builtin in EXP and store the result in TARGET. Store
13109 true in *EXPANDEDP if we found a builtin to expand.
13111 This expands the SPE builtins that are not simple unary and binary
13114 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
13116 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13118 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13119 enum insn_code icode
;
13120 enum machine_mode tmode
, mode0
;
13122 const struct builtin_description
*d
;
13127 /* Syntax check for a 5-bit unsigned immediate. */
13130 case SPE_BUILTIN_EVSTDD
:
13131 case SPE_BUILTIN_EVSTDH
:
13132 case SPE_BUILTIN_EVSTDW
:
13133 case SPE_BUILTIN_EVSTWHE
:
13134 case SPE_BUILTIN_EVSTWHO
:
13135 case SPE_BUILTIN_EVSTWWE
:
13136 case SPE_BUILTIN_EVSTWWO
:
13137 arg1
= CALL_EXPR_ARG (exp
, 2);
13138 if (TREE_CODE (arg1
) != INTEGER_CST
13139 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
13141 error ("argument 2 must be a 5-bit unsigned literal");
13149 /* The evsplat*i instructions are not quite generic. */
13152 case SPE_BUILTIN_EVSPLATFI
:
13153 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
13155 case SPE_BUILTIN_EVSPLATI
:
13156 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
13162 d
= bdesc_2arg_spe
;
13163 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
13164 if (d
->code
== fcode
)
13165 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13167 d
= bdesc_spe_predicates
;
13168 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
13169 if (d
->code
== fcode
)
13170 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
13172 d
= bdesc_spe_evsel
;
13173 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
13174 if (d
->code
== fcode
)
13175 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
13179 case SPE_BUILTIN_EVSTDDX
:
13180 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
13181 case SPE_BUILTIN_EVSTDHX
:
13182 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
13183 case SPE_BUILTIN_EVSTDWX
:
13184 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
13185 case SPE_BUILTIN_EVSTWHEX
:
13186 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
13187 case SPE_BUILTIN_EVSTWHOX
:
13188 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
13189 case SPE_BUILTIN_EVSTWWEX
:
13190 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
13191 case SPE_BUILTIN_EVSTWWOX
:
13192 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
13193 case SPE_BUILTIN_EVSTDD
:
13194 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
13195 case SPE_BUILTIN_EVSTDH
:
13196 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
13197 case SPE_BUILTIN_EVSTDW
:
13198 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
13199 case SPE_BUILTIN_EVSTWHE
:
13200 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
13201 case SPE_BUILTIN_EVSTWHO
:
13202 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
13203 case SPE_BUILTIN_EVSTWWE
:
13204 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
13205 case SPE_BUILTIN_EVSTWWO
:
13206 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
13207 case SPE_BUILTIN_MFSPEFSCR
:
13208 icode
= CODE_FOR_spe_mfspefscr
;
13209 tmode
= insn_data
[icode
].operand
[0].mode
;
13212 || GET_MODE (target
) != tmode
13213 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13214 target
= gen_reg_rtx (tmode
);
13216 pat
= GEN_FCN (icode
) (target
);
13221 case SPE_BUILTIN_MTSPEFSCR
:
13222 icode
= CODE_FOR_spe_mtspefscr
;
13223 arg0
= CALL_EXPR_ARG (exp
, 0);
13224 op0
= expand_normal (arg0
);
13225 mode0
= insn_data
[icode
].operand
[0].mode
;
13227 if (arg0
== error_mark_node
)
13230 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13231 op0
= copy_to_mode_reg (mode0
, op0
);
13233 pat
= GEN_FCN (icode
) (op0
);
13241 *expandedp
= false;
13246 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13248 rtx pat
, scratch
, tmp
;
13249 tree form
= CALL_EXPR_ARG (exp
, 0);
13250 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13251 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13252 rtx op0
= expand_normal (arg0
);
13253 rtx op1
= expand_normal (arg1
);
13254 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13255 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13257 enum rtx_code code
;
13259 if (TREE_CODE (form
) != INTEGER_CST
)
13261 error ("argument 1 of __builtin_paired_predicate must be a constant");
13265 form_int
= TREE_INT_CST_LOW (form
);
13267 gcc_assert (mode0
== mode1
);
13269 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13273 || GET_MODE (target
) != SImode
13274 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13275 target
= gen_reg_rtx (SImode
);
13276 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13277 op0
= copy_to_mode_reg (mode0
, op0
);
13278 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13279 op1
= copy_to_mode_reg (mode1
, op1
);
13281 scratch
= gen_reg_rtx (CCFPmode
);
13283 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13305 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13308 error ("argument 1 of __builtin_paired_predicate is out of range");
13312 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13313 emit_move_insn (target
, tmp
);
13318 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13320 rtx pat
, scratch
, tmp
;
13321 tree form
= CALL_EXPR_ARG (exp
, 0);
13322 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13323 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13324 rtx op0
= expand_normal (arg0
);
13325 rtx op1
= expand_normal (arg1
);
13326 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13327 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13329 enum rtx_code code
;
13331 if (TREE_CODE (form
) != INTEGER_CST
)
13333 error ("argument 1 of __builtin_spe_predicate must be a constant");
13337 form_int
= TREE_INT_CST_LOW (form
);
13339 gcc_assert (mode0
== mode1
);
13341 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13345 || GET_MODE (target
) != SImode
13346 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13347 target
= gen_reg_rtx (SImode
);
13349 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13350 op0
= copy_to_mode_reg (mode0
, op0
);
13351 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13352 op1
= copy_to_mode_reg (mode1
, op1
);
13354 scratch
= gen_reg_rtx (CCmode
);
13356 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13361 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
13362 _lower_. We use one compare, but look in different bits of the
13363 CR for each variant.
13365 There are 2 elements in each SPE simd type (upper/lower). The CR
13366 bits are set as follows:
13368 BIT0 | BIT 1 | BIT 2 | BIT 3
13369 U | L | (U | L) | (U & L)
13371 So, for an "all" relationship, BIT 3 would be set.
13372 For an "any" relationship, BIT 2 would be set. Etc.
13374 Following traditional nomenclature, these bits map to:
13376 BIT0 | BIT 1 | BIT 2 | BIT 3
13379 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
13384 /* All variant. OV bit. */
13386 /* We need to get to the OV bit, which is the ORDERED bit. We
13387 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
13388 that's ugly and will make validate_condition_mode die.
13389 So let's just use another pattern. */
13390 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13392 /* Any variant. EQ bit. */
13396 /* Upper variant. LT bit. */
13400 /* Lower variant. GT bit. */
13405 error ("argument 1 of __builtin_spe_predicate is out of range");
13409 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13410 emit_move_insn (target
, tmp
);
13415 /* The evsel builtins look like this:
13417 e = __builtin_spe_evsel_OP (a, b, c, d);
13419 and work like this:
13421 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
13422 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
13426 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
13429 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13430 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13431 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13432 tree arg3
= CALL_EXPR_ARG (exp
, 3);
13433 rtx op0
= expand_normal (arg0
);
13434 rtx op1
= expand_normal (arg1
);
13435 rtx op2
= expand_normal (arg2
);
13436 rtx op3
= expand_normal (arg3
);
13437 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13438 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13440 gcc_assert (mode0
== mode1
);
13442 if (arg0
== error_mark_node
|| arg1
== error_mark_node
13443 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
13447 || GET_MODE (target
) != mode0
13448 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
13449 target
= gen_reg_rtx (mode0
);
13451 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13452 op0
= copy_to_mode_reg (mode0
, op0
);
13453 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13454 op1
= copy_to_mode_reg (mode0
, op1
);
13455 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
13456 op2
= copy_to_mode_reg (mode0
, op2
);
13457 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
13458 op3
= copy_to_mode_reg (mode0
, op3
);
13460 /* Generate the compare. */
13461 scratch
= gen_reg_rtx (CCmode
);
13462 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13467 if (mode0
== V2SImode
)
13468 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
13470 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
13475 /* Raise an error message for a builtin function that is called without the
13476 appropriate target options being set. */
13479 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
13481 size_t uns_fncode
= (size_t)fncode
;
13482 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
13483 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
13485 gcc_assert (name
!= NULL
);
13486 if ((fnmask
& RS6000_BTM_CELL
) != 0)
13487 error ("Builtin function %s is only valid for the cell processor", name
);
13488 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
13489 error ("Builtin function %s requires the -mvsx option", name
);
13490 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
13491 error ("Builtin function %s requires the -mhtm option", name
);
13492 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
13493 error ("Builtin function %s requires the -maltivec option", name
);
13494 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
13495 error ("Builtin function %s requires the -mpaired option", name
);
13496 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
13497 error ("Builtin function %s requires the -mspe option", name
);
13499 error ("Builtin function %s is not supported with the current options",
13503 /* Expand an expression EXP that calls a built-in function,
13504 with result going to TARGET if that's convenient
13505 (and in mode MODE if that's convenient).
13506 SUBTARGET may be used as the target for computing one of EXP's operands.
13507 IGNORE is nonzero if the value is to be ignored. */
13510 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13511 enum machine_mode mode ATTRIBUTE_UNUSED
,
13512 int ignore ATTRIBUTE_UNUSED
)
13514 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13515 enum rs6000_builtins fcode
13516 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
13517 size_t uns_fcode
= (size_t)fcode
;
13518 const struct builtin_description
*d
;
13522 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
13523 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
13525 if (TARGET_DEBUG_BUILTIN
)
13527 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
13528 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
13529 const char *name2
= ((icode
!= CODE_FOR_nothing
)
13530 ? get_insn_name ((int)icode
)
13534 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
13536 default: name3
= "unknown"; break;
13537 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
13538 case RS6000_BTC_UNARY
: name3
= "unary"; break;
13539 case RS6000_BTC_BINARY
: name3
= "binary"; break;
13540 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
13541 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
13542 case RS6000_BTC_ABS
: name3
= "abs"; break;
13543 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
13544 case RS6000_BTC_DST
: name3
= "dst"; break;
13549 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
13550 (name1
) ? name1
: "---", fcode
,
13551 (name2
) ? name2
: "---", (int)icode
,
13553 func_valid_p
? "" : ", not valid");
13558 rs6000_invalid_builtin (fcode
);
13560 /* Given it is invalid, just generate a normal call. */
13561 return expand_call (exp
, target
, ignore
);
13566 case RS6000_BUILTIN_RECIP
:
13567 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
13569 case RS6000_BUILTIN_RECIPF
:
13570 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
13572 case RS6000_BUILTIN_RSQRTF
:
13573 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
13575 case RS6000_BUILTIN_RSQRT
:
13576 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
13578 case POWER7_BUILTIN_BPERMD
:
13579 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
13580 ? CODE_FOR_bpermd_di
13581 : CODE_FOR_bpermd_si
), exp
, target
);
13583 case RS6000_BUILTIN_GET_TB
:
13584 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
13587 case RS6000_BUILTIN_MFTB
:
13588 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
13589 ? CODE_FOR_rs6000_mftb_di
13590 : CODE_FOR_rs6000_mftb_si
),
13593 case RS6000_BUILTIN_MFFS
:
13594 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
13596 case RS6000_BUILTIN_MTFSF
:
13597 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
13599 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
13600 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
13602 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr
13603 : (int) CODE_FOR_altivec_lvsl
);
13604 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13605 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
13609 gcc_assert (TARGET_ALTIVEC
);
13611 arg
= CALL_EXPR_ARG (exp
, 0);
13612 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
13613 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
13614 addr
= memory_address (mode
, op
);
13615 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
13619 /* For the load case need to negate the address. */
13620 op
= gen_reg_rtx (GET_MODE (addr
));
13621 emit_insn (gen_rtx_SET (VOIDmode
, op
,
13622 gen_rtx_NEG (GET_MODE (addr
), addr
)));
13624 op
= gen_rtx_MEM (mode
, op
);
13627 || GET_MODE (target
) != tmode
13628 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13629 target
= gen_reg_rtx (tmode
);
13631 /*pat = gen_altivec_lvsr (target, op);*/
13632 pat
= GEN_FCN (icode
) (target
, op
);
13640 case ALTIVEC_BUILTIN_VCFUX
:
13641 case ALTIVEC_BUILTIN_VCFSX
:
13642 case ALTIVEC_BUILTIN_VCTUXS
:
13643 case ALTIVEC_BUILTIN_VCTSXS
:
13644 /* FIXME: There's got to be a nicer way to handle this case than
13645 constructing a new CALL_EXPR. */
13646 if (call_expr_nargs (exp
) == 1)
13648 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
13649 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
13657 if (TARGET_ALTIVEC
)
13659 ret
= altivec_expand_builtin (exp
, target
, &success
);
13666 ret
= spe_expand_builtin (exp
, target
, &success
);
13671 if (TARGET_PAIRED_FLOAT
)
13673 ret
= paired_expand_builtin (exp
, target
, &success
);
13680 ret
= htm_expand_builtin (exp
, target
, &success
);
13686 gcc_assert (TARGET_ALTIVEC
|| TARGET_VSX
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
13688 /* Handle simple unary operations. */
13690 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13691 if (d
->code
== fcode
)
13692 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
13694 /* Handle simple binary operations. */
13696 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13697 if (d
->code
== fcode
)
13698 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13700 /* Handle simple ternary operations. */
13702 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
13703 if (d
->code
== fcode
)
13704 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
13706 gcc_unreachable ();
13710 rs6000_init_builtins (void)
13714 enum machine_mode mode
;
13716 if (TARGET_DEBUG_BUILTIN
)
13717 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
13718 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
13719 (TARGET_SPE
) ? ", spe" : "",
13720 (TARGET_ALTIVEC
) ? ", altivec" : "",
13721 (TARGET_VSX
) ? ", vsx" : "");
13723 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
13724 V2SF_type_node
= build_vector_type (float_type_node
, 2);
13725 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
13726 V2DF_type_node
= build_vector_type (double_type_node
, 2);
13727 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
13728 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
13729 V4SF_type_node
= build_vector_type (float_type_node
, 4);
13730 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
13731 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
13733 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
13734 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
13735 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
13736 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
13738 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
13739 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
13740 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
13741 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
13743 /* We use V1TI mode as a special container to hold __int128_t items that
13744 must live in VSX registers. */
13745 if (intTI_type_node
)
13747 V1TI_type_node
= build_vector_type (intTI_type_node
, 1);
13748 unsigned_V1TI_type_node
= build_vector_type (unsigned_intTI_type_node
, 1);
13751 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
13752 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
13753 'vector unsigned short'. */
13755 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
13756 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13757 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
13758 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
13759 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13761 long_integer_type_internal_node
= long_integer_type_node
;
13762 long_unsigned_type_internal_node
= long_unsigned_type_node
;
13763 long_long_integer_type_internal_node
= long_long_integer_type_node
;
13764 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
13765 intQI_type_internal_node
= intQI_type_node
;
13766 uintQI_type_internal_node
= unsigned_intQI_type_node
;
13767 intHI_type_internal_node
= intHI_type_node
;
13768 uintHI_type_internal_node
= unsigned_intHI_type_node
;
13769 intSI_type_internal_node
= intSI_type_node
;
13770 uintSI_type_internal_node
= unsigned_intSI_type_node
;
13771 intDI_type_internal_node
= intDI_type_node
;
13772 uintDI_type_internal_node
= unsigned_intDI_type_node
;
13773 intTI_type_internal_node
= intTI_type_node
;
13774 uintTI_type_internal_node
= unsigned_intTI_type_node
;
13775 float_type_internal_node
= float_type_node
;
13776 double_type_internal_node
= double_type_node
;
13777 void_type_internal_node
= void_type_node
;
13779 /* Initialize the modes for builtin_function_type, mapping a machine mode to
13781 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
13782 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
13783 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
13784 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
13785 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
13786 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
13787 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
13788 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
13789 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
13790 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
13791 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
13792 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
13793 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
13794 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
13795 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
13796 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
13797 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
13798 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
13799 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
13800 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
13801 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
13802 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
13803 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
13804 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
13805 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
13807 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
13808 TYPE_NAME (bool_char_type_node
) = tdecl
;
13810 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
13811 TYPE_NAME (bool_short_type_node
) = tdecl
;
13813 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
13814 TYPE_NAME (bool_int_type_node
) = tdecl
;
13816 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
13817 TYPE_NAME (pixel_type_node
) = tdecl
;
13819 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
13820 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
13821 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
13822 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
13823 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
13825 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
13826 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
13828 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
13829 TYPE_NAME (V16QI_type_node
) = tdecl
;
13831 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
13832 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
13834 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
13835 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
13837 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
13838 TYPE_NAME (V8HI_type_node
) = tdecl
;
13840 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
13841 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
13843 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
13844 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
13846 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
13847 TYPE_NAME (V4SI_type_node
) = tdecl
;
13849 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
13850 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
13852 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
13853 TYPE_NAME (V4SF_type_node
) = tdecl
;
13855 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
13856 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
13858 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
13859 TYPE_NAME (V2DF_type_node
) = tdecl
;
13861 if (TARGET_POWERPC64
)
13863 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
13864 TYPE_NAME (V2DI_type_node
) = tdecl
;
13866 tdecl
= add_builtin_type ("__vector unsigned long",
13867 unsigned_V2DI_type_node
);
13868 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
13870 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
13871 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
13875 tdecl
= add_builtin_type ("__vector long long", V2DI_type_node
);
13876 TYPE_NAME (V2DI_type_node
) = tdecl
;
13878 tdecl
= add_builtin_type ("__vector unsigned long long",
13879 unsigned_V2DI_type_node
);
13880 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
13882 tdecl
= add_builtin_type ("__vector __bool long long",
13883 bool_V2DI_type_node
);
13884 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
13887 if (V1TI_type_node
)
13889 tdecl
= add_builtin_type ("__vector __int128", V1TI_type_node
);
13890 TYPE_NAME (V1TI_type_node
) = tdecl
;
13892 tdecl
= add_builtin_type ("__vector unsigned __int128",
13893 unsigned_V1TI_type_node
);
13894 TYPE_NAME (unsigned_V1TI_type_node
) = tdecl
;
13897 /* Paired and SPE builtins are only available if you build a compiler with
13898 the appropriate options, so only create those builtins with the
13899 appropriate compiler option. Create Altivec and VSX builtins on machines
13900 with at least the general purpose extensions (970 and newer) to allow the
13901 use of the target attribute. */
13902 if (TARGET_PAIRED_FLOAT
)
13903 paired_init_builtins ();
13905 spe_init_builtins ();
13906 if (TARGET_EXTRA_BUILTINS
)
13907 altivec_init_builtins ();
13909 htm_init_builtins ();
13911 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
13912 rs6000_common_init_builtins ();
13914 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
13915 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
13916 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
13918 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
13919 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
13920 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
13922 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
13923 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
13924 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
13926 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
13927 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
13928 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
13930 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
13931 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
13932 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
13933 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
13935 ftype
= build_function_type_list (unsigned_intDI_type_node
,
13937 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
13940 ftype
= build_function_type_list (unsigned_intDI_type_node
,
13943 ftype
= build_function_type_list (unsigned_intSI_type_node
,
13945 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
13947 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
13948 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
13950 ftype
= build_function_type_list (void_type_node
,
13951 intSI_type_node
, double_type_node
,
13953 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
13956 /* AIX libm provides clog as __clog. */
13957 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
13958 set_user_assembler_name (tdecl
, "__clog");
13961 #ifdef SUBTARGET_INIT_BUILTINS
13962 SUBTARGET_INIT_BUILTINS
;
13966 /* Returns the rs6000 builtin decl for CODE. */
13969 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
13971 HOST_WIDE_INT fnmask
;
13973 if (code
>= RS6000_BUILTIN_COUNT
)
13974 return error_mark_node
;
13976 fnmask
= rs6000_builtin_info
[code
].mask
;
13977 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
13979 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
13980 return error_mark_node
;
13983 return rs6000_builtin_decls
[code
];
13987 spe_init_builtins (void)
13989 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
13990 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
13991 const struct builtin_description
*d
;
13994 tree v2si_ftype_4_v2si
13995 = build_function_type_list (opaque_V2SI_type_node
,
13996 opaque_V2SI_type_node
,
13997 opaque_V2SI_type_node
,
13998 opaque_V2SI_type_node
,
13999 opaque_V2SI_type_node
,
14002 tree v2sf_ftype_4_v2sf
14003 = build_function_type_list (opaque_V2SF_type_node
,
14004 opaque_V2SF_type_node
,
14005 opaque_V2SF_type_node
,
14006 opaque_V2SF_type_node
,
14007 opaque_V2SF_type_node
,
14010 tree int_ftype_int_v2si_v2si
14011 = build_function_type_list (integer_type_node
,
14013 opaque_V2SI_type_node
,
14014 opaque_V2SI_type_node
,
14017 tree int_ftype_int_v2sf_v2sf
14018 = build_function_type_list (integer_type_node
,
14020 opaque_V2SF_type_node
,
14021 opaque_V2SF_type_node
,
14024 tree void_ftype_v2si_puint_int
14025 = build_function_type_list (void_type_node
,
14026 opaque_V2SI_type_node
,
14031 tree void_ftype_v2si_puint_char
14032 = build_function_type_list (void_type_node
,
14033 opaque_V2SI_type_node
,
14038 tree void_ftype_v2si_pv2si_int
14039 = build_function_type_list (void_type_node
,
14040 opaque_V2SI_type_node
,
14041 opaque_p_V2SI_type_node
,
14045 tree void_ftype_v2si_pv2si_char
14046 = build_function_type_list (void_type_node
,
14047 opaque_V2SI_type_node
,
14048 opaque_p_V2SI_type_node
,
14052 tree void_ftype_int
14053 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14055 tree int_ftype_void
14056 = build_function_type_list (integer_type_node
, NULL_TREE
);
14058 tree v2si_ftype_pv2si_int
14059 = build_function_type_list (opaque_V2SI_type_node
,
14060 opaque_p_V2SI_type_node
,
14064 tree v2si_ftype_puint_int
14065 = build_function_type_list (opaque_V2SI_type_node
,
14070 tree v2si_ftype_pushort_int
14071 = build_function_type_list (opaque_V2SI_type_node
,
14076 tree v2si_ftype_signed_char
14077 = build_function_type_list (opaque_V2SI_type_node
,
14078 signed_char_type_node
,
14081 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
14083 /* Initialize irregular SPE builtins. */
14085 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
14086 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
14087 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
14088 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
14089 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
14090 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
14091 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
14092 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
14093 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
14094 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
14095 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
14096 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
14097 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
14098 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
14099 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
14100 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
14101 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
14102 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
14105 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
14106 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
14107 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
14108 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
14109 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
14110 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
14111 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
14112 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
14113 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
14114 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
14115 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
14116 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
14117 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
14118 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
14119 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
14120 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
14121 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
14122 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
14123 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
14124 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
14125 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
14126 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
14129 d
= bdesc_spe_predicates
;
14130 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
14134 switch (insn_data
[d
->icode
].operand
[1].mode
)
14137 type
= int_ftype_int_v2si_v2si
;
14140 type
= int_ftype_int_v2sf_v2sf
;
14143 gcc_unreachable ();
14146 def_builtin (d
->name
, type
, d
->code
);
14149 /* Evsel predicates. */
14150 d
= bdesc_spe_evsel
;
14151 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
14155 switch (insn_data
[d
->icode
].operand
[1].mode
)
14158 type
= v2si_ftype_4_v2si
;
14161 type
= v2sf_ftype_4_v2sf
;
14164 gcc_unreachable ();
14167 def_builtin (d
->name
, type
, d
->code
);
14172 paired_init_builtins (void)
14174 const struct builtin_description
*d
;
14177 tree int_ftype_int_v2sf_v2sf
14178 = build_function_type_list (integer_type_node
,
14183 tree pcfloat_type_node
=
14184 build_pointer_type (build_qualified_type
14185 (float_type_node
, TYPE_QUAL_CONST
));
14187 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
14188 long_integer_type_node
,
14191 tree void_ftype_v2sf_long_pcfloat
=
14192 build_function_type_list (void_type_node
,
14194 long_integer_type_node
,
14199 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
14200 PAIRED_BUILTIN_LX
);
14203 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
14204 PAIRED_BUILTIN_STX
);
14207 d
= bdesc_paired_preds
;
14208 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
14212 if (TARGET_DEBUG_BUILTIN
)
14213 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
14214 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
14215 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
14217 switch (insn_data
[d
->icode
].operand
[1].mode
)
14220 type
= int_ftype_int_v2sf_v2sf
;
14223 gcc_unreachable ();
14226 def_builtin (d
->name
, type
, d
->code
);
14231 altivec_init_builtins (void)
14233 const struct builtin_description
*d
;
14238 tree pvoid_type_node
= build_pointer_type (void_type_node
);
14240 tree pcvoid_type_node
14241 = build_pointer_type (build_qualified_type (void_type_node
,
14244 tree int_ftype_opaque
14245 = build_function_type_list (integer_type_node
,
14246 opaque_V4SI_type_node
, NULL_TREE
);
14247 tree opaque_ftype_opaque
14248 = build_function_type_list (integer_type_node
, NULL_TREE
);
14249 tree opaque_ftype_opaque_int
14250 = build_function_type_list (opaque_V4SI_type_node
,
14251 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
14252 tree opaque_ftype_opaque_opaque_int
14253 = build_function_type_list (opaque_V4SI_type_node
,
14254 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
14255 integer_type_node
, NULL_TREE
);
14256 tree int_ftype_int_opaque_opaque
14257 = build_function_type_list (integer_type_node
,
14258 integer_type_node
, opaque_V4SI_type_node
,
14259 opaque_V4SI_type_node
, NULL_TREE
);
14260 tree int_ftype_int_v4si_v4si
14261 = build_function_type_list (integer_type_node
,
14262 integer_type_node
, V4SI_type_node
,
14263 V4SI_type_node
, NULL_TREE
);
14264 tree int_ftype_int_v2di_v2di
14265 = build_function_type_list (integer_type_node
,
14266 integer_type_node
, V2DI_type_node
,
14267 V2DI_type_node
, NULL_TREE
);
14268 tree void_ftype_v4si
14269 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
14270 tree v8hi_ftype_void
14271 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
14272 tree void_ftype_void
14273 = build_function_type_list (void_type_node
, NULL_TREE
);
14274 tree void_ftype_int
14275 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14277 tree opaque_ftype_long_pcvoid
14278 = build_function_type_list (opaque_V4SI_type_node
,
14279 long_integer_type_node
, pcvoid_type_node
,
14281 tree v16qi_ftype_long_pcvoid
14282 = build_function_type_list (V16QI_type_node
,
14283 long_integer_type_node
, pcvoid_type_node
,
14285 tree v8hi_ftype_long_pcvoid
14286 = build_function_type_list (V8HI_type_node
,
14287 long_integer_type_node
, pcvoid_type_node
,
14289 tree v4si_ftype_long_pcvoid
14290 = build_function_type_list (V4SI_type_node
,
14291 long_integer_type_node
, pcvoid_type_node
,
14293 tree v4sf_ftype_long_pcvoid
14294 = build_function_type_list (V4SF_type_node
,
14295 long_integer_type_node
, pcvoid_type_node
,
14297 tree v2df_ftype_long_pcvoid
14298 = build_function_type_list (V2DF_type_node
,
14299 long_integer_type_node
, pcvoid_type_node
,
14301 tree v2di_ftype_long_pcvoid
14302 = build_function_type_list (V2DI_type_node
,
14303 long_integer_type_node
, pcvoid_type_node
,
14306 tree void_ftype_opaque_long_pvoid
14307 = build_function_type_list (void_type_node
,
14308 opaque_V4SI_type_node
, long_integer_type_node
,
14309 pvoid_type_node
, NULL_TREE
);
14310 tree void_ftype_v4si_long_pvoid
14311 = build_function_type_list (void_type_node
,
14312 V4SI_type_node
, long_integer_type_node
,
14313 pvoid_type_node
, NULL_TREE
);
14314 tree void_ftype_v16qi_long_pvoid
14315 = build_function_type_list (void_type_node
,
14316 V16QI_type_node
, long_integer_type_node
,
14317 pvoid_type_node
, NULL_TREE
);
14318 tree void_ftype_v8hi_long_pvoid
14319 = build_function_type_list (void_type_node
,
14320 V8HI_type_node
, long_integer_type_node
,
14321 pvoid_type_node
, NULL_TREE
);
14322 tree void_ftype_v4sf_long_pvoid
14323 = build_function_type_list (void_type_node
,
14324 V4SF_type_node
, long_integer_type_node
,
14325 pvoid_type_node
, NULL_TREE
);
14326 tree void_ftype_v2df_long_pvoid
14327 = build_function_type_list (void_type_node
,
14328 V2DF_type_node
, long_integer_type_node
,
14329 pvoid_type_node
, NULL_TREE
);
14330 tree void_ftype_v2di_long_pvoid
14331 = build_function_type_list (void_type_node
,
14332 V2DI_type_node
, long_integer_type_node
,
14333 pvoid_type_node
, NULL_TREE
);
14334 tree int_ftype_int_v8hi_v8hi
14335 = build_function_type_list (integer_type_node
,
14336 integer_type_node
, V8HI_type_node
,
14337 V8HI_type_node
, NULL_TREE
);
14338 tree int_ftype_int_v16qi_v16qi
14339 = build_function_type_list (integer_type_node
,
14340 integer_type_node
, V16QI_type_node
,
14341 V16QI_type_node
, NULL_TREE
);
14342 tree int_ftype_int_v4sf_v4sf
14343 = build_function_type_list (integer_type_node
,
14344 integer_type_node
, V4SF_type_node
,
14345 V4SF_type_node
, NULL_TREE
);
14346 tree int_ftype_int_v2df_v2df
14347 = build_function_type_list (integer_type_node
,
14348 integer_type_node
, V2DF_type_node
,
14349 V2DF_type_node
, NULL_TREE
);
14350 tree v2di_ftype_v2di
14351 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
14352 tree v4si_ftype_v4si
14353 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
14354 tree v8hi_ftype_v8hi
14355 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
14356 tree v16qi_ftype_v16qi
14357 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
14358 tree v4sf_ftype_v4sf
14359 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
14360 tree v2df_ftype_v2df
14361 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
14362 tree void_ftype_pcvoid_int_int
14363 = build_function_type_list (void_type_node
,
14364 pcvoid_type_node
, integer_type_node
,
14365 integer_type_node
, NULL_TREE
);
14367 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
14368 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
14369 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
14370 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
14371 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
14372 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
14373 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
14374 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
14375 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
14376 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
14377 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
14378 ALTIVEC_BUILTIN_LVXL_V2DF
);
14379 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
14380 ALTIVEC_BUILTIN_LVXL_V2DI
);
14381 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
14382 ALTIVEC_BUILTIN_LVXL_V4SF
);
14383 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
14384 ALTIVEC_BUILTIN_LVXL_V4SI
);
14385 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
14386 ALTIVEC_BUILTIN_LVXL_V8HI
);
14387 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
14388 ALTIVEC_BUILTIN_LVXL_V16QI
);
14389 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
14390 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
14391 ALTIVEC_BUILTIN_LVX_V2DF
);
14392 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
14393 ALTIVEC_BUILTIN_LVX_V2DI
);
14394 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
14395 ALTIVEC_BUILTIN_LVX_V4SF
);
14396 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
14397 ALTIVEC_BUILTIN_LVX_V4SI
);
14398 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
14399 ALTIVEC_BUILTIN_LVX_V8HI
);
14400 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
14401 ALTIVEC_BUILTIN_LVX_V16QI
);
14402 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
14403 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
14404 ALTIVEC_BUILTIN_STVX_V2DF
);
14405 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
14406 ALTIVEC_BUILTIN_STVX_V2DI
);
14407 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
14408 ALTIVEC_BUILTIN_STVX_V4SF
);
14409 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
14410 ALTIVEC_BUILTIN_STVX_V4SI
);
14411 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
14412 ALTIVEC_BUILTIN_STVX_V8HI
);
14413 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
14414 ALTIVEC_BUILTIN_STVX_V16QI
);
14415 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
14416 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
14417 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
14418 ALTIVEC_BUILTIN_STVXL_V2DF
);
14419 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
14420 ALTIVEC_BUILTIN_STVXL_V2DI
);
14421 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
14422 ALTIVEC_BUILTIN_STVXL_V4SF
);
14423 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
14424 ALTIVEC_BUILTIN_STVXL_V4SI
);
14425 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
14426 ALTIVEC_BUILTIN_STVXL_V8HI
);
14427 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
14428 ALTIVEC_BUILTIN_STVXL_V16QI
);
14429 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
14430 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
14431 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
14432 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
14433 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
14434 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
14435 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
14436 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
14437 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
14438 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
14439 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
14440 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
14441 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
14442 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
14443 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
14444 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
14446 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
14447 VSX_BUILTIN_LXVD2X_V2DF
);
14448 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
14449 VSX_BUILTIN_LXVD2X_V2DI
);
14450 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
14451 VSX_BUILTIN_LXVW4X_V4SF
);
14452 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
14453 VSX_BUILTIN_LXVW4X_V4SI
);
14454 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
14455 VSX_BUILTIN_LXVW4X_V8HI
);
14456 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
14457 VSX_BUILTIN_LXVW4X_V16QI
);
14458 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
14459 VSX_BUILTIN_STXVD2X_V2DF
);
14460 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
14461 VSX_BUILTIN_STXVD2X_V2DI
);
14462 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
14463 VSX_BUILTIN_STXVW4X_V4SF
);
14464 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
14465 VSX_BUILTIN_STXVW4X_V4SI
);
14466 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
14467 VSX_BUILTIN_STXVW4X_V8HI
);
14468 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
14469 VSX_BUILTIN_STXVW4X_V16QI
);
14470 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
14471 VSX_BUILTIN_VEC_LD
);
14472 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
14473 VSX_BUILTIN_VEC_ST
);
14475 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
14476 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
14477 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
14479 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
14480 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
14481 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
14482 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
14483 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
14484 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
14485 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
14486 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
14487 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
14488 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
14489 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
14490 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
14492 /* Cell builtins. */
14493 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
14494 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
14495 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
14496 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
14498 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
14499 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
14500 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
14501 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
14503 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
14504 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
14505 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
14506 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
14508 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
14509 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
14510 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
14511 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
14513 /* Add the DST variants. */
14515 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
14516 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
14518 /* Initialize the predicates. */
14519 d
= bdesc_altivec_preds
;
14520 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
14522 enum machine_mode mode1
;
14525 if (rs6000_overloaded_builtin_p (d
->code
))
14528 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
14533 type
= int_ftype_int_opaque_opaque
;
14536 type
= int_ftype_int_v2di_v2di
;
14539 type
= int_ftype_int_v4si_v4si
;
14542 type
= int_ftype_int_v8hi_v8hi
;
14545 type
= int_ftype_int_v16qi_v16qi
;
14548 type
= int_ftype_int_v4sf_v4sf
;
14551 type
= int_ftype_int_v2df_v2df
;
14554 gcc_unreachable ();
14557 def_builtin (d
->name
, type
, d
->code
);
14560 /* Initialize the abs* operators. */
14562 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
14564 enum machine_mode mode0
;
14567 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
14572 type
= v2di_ftype_v2di
;
14575 type
= v4si_ftype_v4si
;
14578 type
= v8hi_ftype_v8hi
;
14581 type
= v16qi_ftype_v16qi
;
14584 type
= v4sf_ftype_v4sf
;
14587 type
= v2df_ftype_v2df
;
14590 gcc_unreachable ();
14593 def_builtin (d
->name
, type
, d
->code
);
14596 /* Initialize target builtin that implements
14597 targetm.vectorize.builtin_mask_for_load. */
14599 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
14600 v16qi_ftype_long_pcvoid
,
14601 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
14602 BUILT_IN_MD
, NULL
, NULL_TREE
);
14603 TREE_READONLY (decl
) = 1;
14604 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
14605 altivec_builtin_mask_for_load
= decl
;
14607 /* Access to the vec_init patterns. */
14608 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
14609 integer_type_node
, integer_type_node
,
14610 integer_type_node
, NULL_TREE
);
14611 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
14613 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
14614 short_integer_type_node
,
14615 short_integer_type_node
,
14616 short_integer_type_node
,
14617 short_integer_type_node
,
14618 short_integer_type_node
,
14619 short_integer_type_node
,
14620 short_integer_type_node
, NULL_TREE
);
14621 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
14623 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
14624 char_type_node
, char_type_node
,
14625 char_type_node
, char_type_node
,
14626 char_type_node
, char_type_node
,
14627 char_type_node
, char_type_node
,
14628 char_type_node
, char_type_node
,
14629 char_type_node
, char_type_node
,
14630 char_type_node
, char_type_node
,
14631 char_type_node
, NULL_TREE
);
14632 def_builtin ("__builtin_vec_init_v16qi", ftype
,
14633 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
14635 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
14636 float_type_node
, float_type_node
,
14637 float_type_node
, NULL_TREE
);
14638 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
14640 /* VSX builtins. */
14641 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
14642 double_type_node
, NULL_TREE
);
14643 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
14645 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
14646 intDI_type_node
, NULL_TREE
);
14647 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
14649 /* Access to the vec_set patterns. */
14650 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
14652 integer_type_node
, NULL_TREE
);
14653 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
14655 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
14657 integer_type_node
, NULL_TREE
);
14658 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
14660 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
14662 integer_type_node
, NULL_TREE
);
14663 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
14665 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
14667 integer_type_node
, NULL_TREE
);
14668 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
14670 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
14672 integer_type_node
, NULL_TREE
);
14673 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
14675 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
14677 integer_type_node
, NULL_TREE
);
14678 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
14680 /* Access to the vec_extract patterns. */
14681 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
14682 integer_type_node
, NULL_TREE
);
14683 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
14685 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
14686 integer_type_node
, NULL_TREE
);
14687 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
14689 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
14690 integer_type_node
, NULL_TREE
);
14691 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
14693 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
14694 integer_type_node
, NULL_TREE
);
14695 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
14697 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
14698 integer_type_node
, NULL_TREE
);
14699 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
14701 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
14702 integer_type_node
, NULL_TREE
);
14703 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
14706 if (V1TI_type_node
)
14708 tree v1ti_ftype_long_pcvoid
14709 = build_function_type_list (V1TI_type_node
,
14710 long_integer_type_node
, pcvoid_type_node
,
14712 tree void_ftype_v1ti_long_pvoid
14713 = build_function_type_list (void_type_node
,
14714 V1TI_type_node
, long_integer_type_node
,
14715 pvoid_type_node
, NULL_TREE
);
14716 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
14717 VSX_BUILTIN_LXVD2X_V1TI
);
14718 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
14719 VSX_BUILTIN_STXVD2X_V1TI
);
14720 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
14721 NULL_TREE
, NULL_TREE
);
14722 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
14723 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
14725 integer_type_node
, NULL_TREE
);
14726 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
14727 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
14728 integer_type_node
, NULL_TREE
);
14729 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
14735 htm_init_builtins (void)
14737 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
14738 const struct builtin_description
*d
;
14742 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14744 tree op
[MAX_HTM_OPERANDS
], type
;
14745 HOST_WIDE_INT mask
= d
->mask
;
14746 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
14747 bool void_func
= (attr
& RS6000_BTC_VOID
);
14748 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
14750 tree argtype
= (attr
& RS6000_BTC_SPR
) ? long_unsigned_type_node
14751 : unsigned_type_node
;
14753 if ((mask
& builtin_mask
) != mask
)
14755 if (TARGET_DEBUG_BUILTIN
)
14756 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
14762 if (TARGET_DEBUG_BUILTIN
)
14763 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
14764 (long unsigned) i
);
14768 op
[nopnds
++] = (void_func
) ? void_type_node
: argtype
;
14770 if (attr_args
== RS6000_BTC_UNARY
)
14771 op
[nopnds
++] = argtype
;
14772 else if (attr_args
== RS6000_BTC_BINARY
)
14774 op
[nopnds
++] = argtype
;
14775 op
[nopnds
++] = argtype
;
14777 else if (attr_args
== RS6000_BTC_TERNARY
)
14779 op
[nopnds
++] = argtype
;
14780 op
[nopnds
++] = argtype
;
14781 op
[nopnds
++] = argtype
;
14787 type
= build_function_type_list (op
[0], NULL_TREE
);
14790 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
14793 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
14796 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
14800 gcc_unreachable ();
14803 def_builtin (d
->name
, type
, d
->code
);
14807 /* Hash function for builtin functions with up to 3 arguments and a return
14810 builtin_hash_function (const void *hash_entry
)
14814 const struct builtin_hash_struct
*bh
=
14815 (const struct builtin_hash_struct
*) hash_entry
;
14817 for (i
= 0; i
< 4; i
++)
14819 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
14820 ret
= (ret
* 2) + bh
->uns_p
[i
];
14826 /* Compare builtin hash entries H1 and H2 for equivalence. */
14828 builtin_hash_eq (const void *h1
, const void *h2
)
14830 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
14831 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
14833 return ((p1
->mode
[0] == p2
->mode
[0])
14834 && (p1
->mode
[1] == p2
->mode
[1])
14835 && (p1
->mode
[2] == p2
->mode
[2])
14836 && (p1
->mode
[3] == p2
->mode
[3])
14837 && (p1
->uns_p
[0] == p2
->uns_p
[0])
14838 && (p1
->uns_p
[1] == p2
->uns_p
[1])
14839 && (p1
->uns_p
[2] == p2
->uns_p
[2])
14840 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
14843 /* Map types for builtin functions with an explicit return type and up to 3
14844 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
14845 of the argument. */
14847 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
14848 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
14849 enum rs6000_builtins builtin
, const char *name
)
14851 struct builtin_hash_struct h
;
14852 struct builtin_hash_struct
*h2
;
14856 tree ret_type
= NULL_TREE
;
14857 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
14859 /* Create builtin_hash_table. */
14860 if (builtin_hash_table
== NULL
)
14861 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
14862 builtin_hash_eq
, NULL
);
14864 h
.type
= NULL_TREE
;
14865 h
.mode
[0] = mode_ret
;
14866 h
.mode
[1] = mode_arg0
;
14867 h
.mode
[2] = mode_arg1
;
14868 h
.mode
[3] = mode_arg2
;
14874 /* If the builtin is a type that produces unsigned results or takes unsigned
14875 arguments, and it is returned as a decl for the vectorizer (such as
14876 widening multiplies, permute), make sure the arguments and return value
14877 are type correct. */
14880 /* unsigned 1 argument functions. */
14881 case CRYPTO_BUILTIN_VSBOX
:
14882 case P8V_BUILTIN_VGBBD
:
14887 /* unsigned 2 argument functions. */
14888 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
14889 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
14890 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
14891 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
14892 case CRYPTO_BUILTIN_VCIPHER
:
14893 case CRYPTO_BUILTIN_VCIPHERLAST
:
14894 case CRYPTO_BUILTIN_VNCIPHER
:
14895 case CRYPTO_BUILTIN_VNCIPHERLAST
:
14896 case CRYPTO_BUILTIN_VPMSUMB
:
14897 case CRYPTO_BUILTIN_VPMSUMH
:
14898 case CRYPTO_BUILTIN_VPMSUMW
:
14899 case CRYPTO_BUILTIN_VPMSUMD
:
14900 case CRYPTO_BUILTIN_VPMSUM
:
14906 /* unsigned 3 argument functions. */
14907 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
14908 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
14909 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
14910 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
14911 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
14912 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
14913 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
14914 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
14915 case VSX_BUILTIN_VPERM_16QI_UNS
:
14916 case VSX_BUILTIN_VPERM_8HI_UNS
:
14917 case VSX_BUILTIN_VPERM_4SI_UNS
:
14918 case VSX_BUILTIN_VPERM_2DI_UNS
:
14919 case VSX_BUILTIN_XXSEL_16QI_UNS
:
14920 case VSX_BUILTIN_XXSEL_8HI_UNS
:
14921 case VSX_BUILTIN_XXSEL_4SI_UNS
:
14922 case VSX_BUILTIN_XXSEL_2DI_UNS
:
14923 case CRYPTO_BUILTIN_VPERMXOR
:
14924 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
14925 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
14926 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
14927 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
14928 case CRYPTO_BUILTIN_VSHASIGMAW
:
14929 case CRYPTO_BUILTIN_VSHASIGMAD
:
14930 case CRYPTO_BUILTIN_VSHASIGMA
:
14937 /* signed permute functions with unsigned char mask. */
14938 case ALTIVEC_BUILTIN_VPERM_16QI
:
14939 case ALTIVEC_BUILTIN_VPERM_8HI
:
14940 case ALTIVEC_BUILTIN_VPERM_4SI
:
14941 case ALTIVEC_BUILTIN_VPERM_4SF
:
14942 case ALTIVEC_BUILTIN_VPERM_2DI
:
14943 case ALTIVEC_BUILTIN_VPERM_2DF
:
14944 case VSX_BUILTIN_VPERM_16QI
:
14945 case VSX_BUILTIN_VPERM_8HI
:
14946 case VSX_BUILTIN_VPERM_4SI
:
14947 case VSX_BUILTIN_VPERM_4SF
:
14948 case VSX_BUILTIN_VPERM_2DI
:
14949 case VSX_BUILTIN_VPERM_2DF
:
14953 /* unsigned args, signed return. */
14954 case VSX_BUILTIN_XVCVUXDDP_UNS
:
14955 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
14959 /* signed args, unsigned return. */
14960 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
14961 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
14969 /* Figure out how many args are present. */
14970 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
14974 fatal_error ("internal error: builtin function %s had no type", name
);
14976 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
14977 if (!ret_type
&& h
.uns_p
[0])
14978 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
14981 fatal_error ("internal error: builtin function %s had an unexpected "
14982 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
14984 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
14985 arg_type
[i
] = NULL_TREE
;
14987 for (i
= 0; i
< num_args
; i
++)
14989 int m
= (int) h
.mode
[i
+1];
14990 int uns_p
= h
.uns_p
[i
+1];
14992 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
14993 if (!arg_type
[i
] && uns_p
)
14994 arg_type
[i
] = builtin_mode_to_type
[m
][0];
14997 fatal_error ("internal error: builtin function %s, argument %d "
14998 "had unexpected argument type %s", name
, i
,
14999 GET_MODE_NAME (m
));
15002 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
15003 if (*found
== NULL
)
15005 h2
= ggc_alloc_builtin_hash_struct ();
15007 *found
= (void *)h2
;
15009 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
15010 arg_type
[2], NULL_TREE
);
15013 return ((struct builtin_hash_struct
*)(*found
))->type
;
15017 rs6000_common_init_builtins (void)
15019 const struct builtin_description
*d
;
15022 tree opaque_ftype_opaque
= NULL_TREE
;
15023 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
15024 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
15025 tree v2si_ftype_qi
= NULL_TREE
;
15026 tree v2si_ftype_v2si_qi
= NULL_TREE
;
15027 tree v2si_ftype_int_qi
= NULL_TREE
;
15028 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
15030 if (!TARGET_PAIRED_FLOAT
)
15032 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
15033 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
15036 /* Paired and SPE builtins are only available if you build a compiler with
15037 the appropriate options, so only create those builtins with the
15038 appropriate compiler option. Create Altivec and VSX builtins on machines
15039 with at least the general purpose extensions (970 and newer) to allow the
15040 use of the target attribute.. */
15042 if (TARGET_EXTRA_BUILTINS
)
15043 builtin_mask
|= RS6000_BTM_COMMON
;
15045 /* Add the ternary operators. */
15047 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
15050 HOST_WIDE_INT mask
= d
->mask
;
15052 if ((mask
& builtin_mask
) != mask
)
15054 if (TARGET_DEBUG_BUILTIN
)
15055 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
15059 if (rs6000_overloaded_builtin_p (d
->code
))
15061 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
15062 type
= opaque_ftype_opaque_opaque_opaque
15063 = build_function_type_list (opaque_V4SI_type_node
,
15064 opaque_V4SI_type_node
,
15065 opaque_V4SI_type_node
,
15066 opaque_V4SI_type_node
,
15071 enum insn_code icode
= d
->icode
;
15074 if (TARGET_DEBUG_BUILTIN
)
15075 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
15081 if (icode
== CODE_FOR_nothing
)
15083 if (TARGET_DEBUG_BUILTIN
)
15084 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
15090 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
15091 insn_data
[icode
].operand
[1].mode
,
15092 insn_data
[icode
].operand
[2].mode
,
15093 insn_data
[icode
].operand
[3].mode
,
15097 def_builtin (d
->name
, type
, d
->code
);
15100 /* Add the binary operators. */
15102 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
15104 enum machine_mode mode0
, mode1
, mode2
;
15106 HOST_WIDE_INT mask
= d
->mask
;
15108 if ((mask
& builtin_mask
) != mask
)
15110 if (TARGET_DEBUG_BUILTIN
)
15111 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
15115 if (rs6000_overloaded_builtin_p (d
->code
))
15117 if (! (type
= opaque_ftype_opaque_opaque
))
15118 type
= opaque_ftype_opaque_opaque
15119 = build_function_type_list (opaque_V4SI_type_node
,
15120 opaque_V4SI_type_node
,
15121 opaque_V4SI_type_node
,
15126 enum insn_code icode
= d
->icode
;
15129 if (TARGET_DEBUG_BUILTIN
)
15130 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
15136 if (icode
== CODE_FOR_nothing
)
15138 if (TARGET_DEBUG_BUILTIN
)
15139 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
15145 mode0
= insn_data
[icode
].operand
[0].mode
;
15146 mode1
= insn_data
[icode
].operand
[1].mode
;
15147 mode2
= insn_data
[icode
].operand
[2].mode
;
15149 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
15151 if (! (type
= v2si_ftype_v2si_qi
))
15152 type
= v2si_ftype_v2si_qi
15153 = build_function_type_list (opaque_V2SI_type_node
,
15154 opaque_V2SI_type_node
,
15159 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
15160 && mode2
== QImode
)
15162 if (! (type
= v2si_ftype_int_qi
))
15163 type
= v2si_ftype_int_qi
15164 = build_function_type_list (opaque_V2SI_type_node
,
15171 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
15175 def_builtin (d
->name
, type
, d
->code
);
15178 /* Add the simple unary operators. */
15180 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
15182 enum machine_mode mode0
, mode1
;
15184 HOST_WIDE_INT mask
= d
->mask
;
15186 if ((mask
& builtin_mask
) != mask
)
15188 if (TARGET_DEBUG_BUILTIN
)
15189 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
15193 if (rs6000_overloaded_builtin_p (d
->code
))
15195 if (! (type
= opaque_ftype_opaque
))
15196 type
= opaque_ftype_opaque
15197 = build_function_type_list (opaque_V4SI_type_node
,
15198 opaque_V4SI_type_node
,
15203 enum insn_code icode
= d
->icode
;
15206 if (TARGET_DEBUG_BUILTIN
)
15207 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
15213 if (icode
== CODE_FOR_nothing
)
15215 if (TARGET_DEBUG_BUILTIN
)
15216 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
15222 mode0
= insn_data
[icode
].operand
[0].mode
;
15223 mode1
= insn_data
[icode
].operand
[1].mode
;
15225 if (mode0
== V2SImode
&& mode1
== QImode
)
15227 if (! (type
= v2si_ftype_qi
))
15228 type
= v2si_ftype_qi
15229 = build_function_type_list (opaque_V2SI_type_node
,
15235 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
15239 def_builtin (d
->name
, type
, d
->code
);
15244 rs6000_init_libfuncs (void)
15246 if (!TARGET_IEEEQUAD
)
15247 /* AIX/Darwin/64-bit Linux quad floating point routines. */
15248 if (!TARGET_XL_COMPAT
)
15250 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
15251 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
15252 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
15253 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
15255 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
15257 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
15258 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
15259 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
15260 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
15261 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
15262 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
15263 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
15265 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
15266 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
15267 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
15268 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
15269 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
15270 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
15271 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
15272 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
15275 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
15276 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
15280 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
15281 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
15282 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
15283 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
15287 /* 32-bit SVR4 quad floating point routines. */
15289 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
15290 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
15291 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
15292 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
15293 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
15294 if (TARGET_PPC_GPOPT
)
15295 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
15297 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
15298 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
15299 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
15300 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
15301 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
15302 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
15304 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
15305 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
15306 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
15307 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
15308 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
15309 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
15310 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
15311 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
15316 /* Expand a block clear operation, and return 1 if successful. Return 0
15317 if we should let the compiler generate normal code.
15319 operands[0] is the destination
15320 operands[1] is the length
15321 operands[3] is the alignment */
15324 expand_block_clear (rtx operands
[])
15326 rtx orig_dest
= operands
[0];
15327 rtx bytes_rtx
= operands
[1];
15328 rtx align_rtx
= operands
[3];
15329 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
15330 HOST_WIDE_INT align
;
15331 HOST_WIDE_INT bytes
;
15336 /* If this is not a fixed size move, just call memcpy */
15340 /* This must be a fixed size alignment */
15341 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
15342 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
15344 /* Anything to clear? */
15345 bytes
= INTVAL (bytes_rtx
);
15349 /* Use the builtin memset after a point, to avoid huge code bloat.
15350 When optimize_size, avoid any significant code bloat; calling
15351 memset is about 4 instructions, so allow for one instruction to
15352 load zero and three to do clearing. */
15353 if (TARGET_ALTIVEC
&& align
>= 128)
15355 else if (TARGET_POWERPC64
&& align
>= 32)
15357 else if (TARGET_SPE
&& align
>= 64)
15362 if (optimize_size
&& bytes
> 3 * clear_step
)
15364 if (! optimize_size
&& bytes
> 8 * clear_step
)
15367 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
15369 enum machine_mode mode
= BLKmode
;
15372 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
15377 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
15382 else if (bytes
>= 8 && TARGET_POWERPC64
15383 /* 64-bit loads and stores require word-aligned
15385 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
15390 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15391 { /* move 4 bytes */
15395 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15396 { /* move 2 bytes */
15400 else /* move 1 byte at a time */
15406 dest
= adjust_address (orig_dest
, mode
, offset
);
15408 emit_move_insn (dest
, CONST0_RTX (mode
));
15415 /* Expand a block move operation, and return 1 if successful. Return 0
15416 if we should let the compiler generate normal code.
15418 operands[0] is the destination
15419 operands[1] is the source
15420 operands[2] is the length
15421 operands[3] is the alignment */
15423 #define MAX_MOVE_REG 4
15426 expand_block_move (rtx operands
[])
15428 rtx orig_dest
= operands
[0];
15429 rtx orig_src
= operands
[1];
15430 rtx bytes_rtx
= operands
[2];
15431 rtx align_rtx
= operands
[3];
15432 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
15437 rtx stores
[MAX_MOVE_REG
];
15440 /* If this is not a fixed size move, just call memcpy */
15444 /* This must be a fixed size alignment */
15445 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
15446 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
15448 /* Anything to move? */
15449 bytes
= INTVAL (bytes_rtx
);
15453 if (bytes
> rs6000_block_move_inline_limit
)
15456 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
15459 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
15460 rtx (*mov
) (rtx
, rtx
);
15462 enum machine_mode mode
= BLKmode
;
15465 /* Altivec first, since it will be faster than a string move
15466 when it applies, and usually not significantly larger. */
15467 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
15471 gen_func
.mov
= gen_movv4si
;
15473 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
15477 gen_func
.mov
= gen_movv2si
;
15479 else if (TARGET_STRING
15480 && bytes
> 24 /* move up to 32 bytes at a time */
15486 && ! fixed_regs
[10]
15487 && ! fixed_regs
[11]
15488 && ! fixed_regs
[12])
15490 move_bytes
= (bytes
> 32) ? 32 : bytes
;
15491 gen_func
.movmemsi
= gen_movmemsi_8reg
;
15493 else if (TARGET_STRING
15494 && bytes
> 16 /* move up to 24 bytes at a time */
15500 && ! fixed_regs
[10])
15502 move_bytes
= (bytes
> 24) ? 24 : bytes
;
15503 gen_func
.movmemsi
= gen_movmemsi_6reg
;
15505 else if (TARGET_STRING
15506 && bytes
> 8 /* move up to 16 bytes at a time */
15510 && ! fixed_regs
[8])
15512 move_bytes
= (bytes
> 16) ? 16 : bytes
;
15513 gen_func
.movmemsi
= gen_movmemsi_4reg
;
15515 else if (bytes
>= 8 && TARGET_POWERPC64
15516 /* 64-bit loads and stores require word-aligned
15518 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
15522 gen_func
.mov
= gen_movdi
;
15524 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
15525 { /* move up to 8 bytes at a time */
15526 move_bytes
= (bytes
> 8) ? 8 : bytes
;
15527 gen_func
.movmemsi
= gen_movmemsi_2reg
;
15529 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15530 { /* move 4 bytes */
15533 gen_func
.mov
= gen_movsi
;
15535 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15536 { /* move 2 bytes */
15539 gen_func
.mov
= gen_movhi
;
15541 else if (TARGET_STRING
&& bytes
> 1)
15542 { /* move up to 4 bytes at a time */
15543 move_bytes
= (bytes
> 4) ? 4 : bytes
;
15544 gen_func
.movmemsi
= gen_movmemsi_1reg
;
15546 else /* move 1 byte at a time */
15550 gen_func
.mov
= gen_movqi
;
15553 src
= adjust_address (orig_src
, mode
, offset
);
15554 dest
= adjust_address (orig_dest
, mode
, offset
);
15556 if (mode
!= BLKmode
)
15558 rtx tmp_reg
= gen_reg_rtx (mode
);
15560 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
15561 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
15564 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
15567 for (i
= 0; i
< num_reg
; i
++)
15568 emit_insn (stores
[i
]);
15572 if (mode
== BLKmode
)
15574 /* Move the address into scratch registers. The movmemsi
15575 patterns require zero offset. */
15576 if (!REG_P (XEXP (src
, 0)))
15578 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
15579 src
= replace_equiv_address (src
, src_reg
);
15581 set_mem_size (src
, move_bytes
);
15583 if (!REG_P (XEXP (dest
, 0)))
15585 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
15586 dest
= replace_equiv_address (dest
, dest_reg
);
15588 set_mem_size (dest
, move_bytes
);
15590 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
15591 GEN_INT (move_bytes
& 31),
15600 /* Return a string to perform a load_multiple operation.
15601 operands[0] is the vector.
15602 operands[1] is the source address.
15603 operands[2] is the first destination register. */
15606 rs6000_output_load_multiple (rtx operands
[3])
15608 /* We have to handle the case where the pseudo used to contain the address
15609 is assigned to one of the output registers. */
15611 int words
= XVECLEN (operands
[0], 0);
15614 if (XVECLEN (operands
[0], 0) == 1)
15615 return "lwz %2,0(%1)";
15617 for (i
= 0; i
< words
; i
++)
15618 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
15619 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
15623 xop
[0] = GEN_INT (4 * (words
-1));
15624 xop
[1] = operands
[1];
15625 xop
[2] = operands
[2];
15626 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
15631 xop
[0] = GEN_INT (4 * (words
-1));
15632 xop
[1] = operands
[1];
15633 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
15634 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
15639 for (j
= 0; j
< words
; j
++)
15642 xop
[0] = GEN_INT (j
* 4);
15643 xop
[1] = operands
[1];
15644 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
15645 output_asm_insn ("lwz %2,%0(%1)", xop
);
15647 xop
[0] = GEN_INT (i
* 4);
15648 xop
[1] = operands
[1];
15649 output_asm_insn ("lwz %1,%0(%1)", xop
);
15654 return "lswi %2,%1,%N0";
15658 /* A validation routine: say whether CODE, a condition code, and MODE
15659 match. The other alternatives either don't make sense or should
15660 never be generated. */
15663 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
15665 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
15666 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
15667 && GET_MODE_CLASS (mode
) == MODE_CC
);
15669 /* These don't make sense. */
15670 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
15671 || mode
!= CCUNSmode
);
15673 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
15674 || mode
== CCUNSmode
);
15676 gcc_assert (mode
== CCFPmode
15677 || (code
!= ORDERED
&& code
!= UNORDERED
15678 && code
!= UNEQ
&& code
!= LTGT
15679 && code
!= UNGT
&& code
!= UNLT
15680 && code
!= UNGE
&& code
!= UNLE
));
15682 /* These should never be generated except for
15683 flag_finite_math_only. */
15684 gcc_assert (mode
!= CCFPmode
15685 || flag_finite_math_only
15686 || (code
!= LE
&& code
!= GE
15687 && code
!= UNEQ
&& code
!= LTGT
15688 && code
!= UNGT
&& code
!= UNLT
));
15690 /* These are invalid; the information is not there. */
15691 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
15695 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
15696 mask required to convert the result of a rotate insn into a shift
15697 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
15700 includes_lshift_p (rtx shiftop
, rtx andop
)
15702 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15704 shift_mask
<<= INTVAL (shiftop
);
15706 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15709 /* Similar, but for right shift. */
15712 includes_rshift_p (rtx shiftop
, rtx andop
)
15714 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15716 shift_mask
>>= INTVAL (shiftop
);
15718 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15721 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
15722 to perform a left shift. It must have exactly SHIFTOP least
15723 significant 0's, then one or more 1's, then zero or more 0's. */
15726 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
15728 if (GET_CODE (andop
) == CONST_INT
)
15730 HOST_WIDE_INT c
, lsb
, shift_mask
;
15732 c
= INTVAL (andop
);
15733 if (c
== 0 || c
== ~0)
15737 shift_mask
<<= INTVAL (shiftop
);
15739 /* Find the least significant one bit. */
15742 /* It must coincide with the LSB of the shift mask. */
15743 if (-lsb
!= shift_mask
)
15746 /* Invert to look for the next transition (if any). */
15749 /* Remove the low group of ones (originally low group of zeros). */
15752 /* Again find the lsb, and check we have all 1's above. */
15760 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
15761 to perform a left shift. It must have SHIFTOP or more least
15762 significant 0's, with the remainder of the word 1's. */
15765 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
15767 if (GET_CODE (andop
) == CONST_INT
)
15769 HOST_WIDE_INT c
, lsb
, shift_mask
;
15772 shift_mask
<<= INTVAL (shiftop
);
15773 c
= INTVAL (andop
);
15775 /* Find the least significant one bit. */
15778 /* It must be covered by the shift mask.
15779 This test also rejects c == 0. */
15780 if ((lsb
& shift_mask
) == 0)
15783 /* Check we have all 1's above the transition, and reject all 1's. */
15784 return c
== -lsb
&& lsb
!= 1;
15790 /* Return 1 if operands will generate a valid arguments to rlwimi
15791 instruction for insert with right shift in 64-bit mode. The mask may
15792 not start on the first bit or stop on the last bit because wrap-around
15793 effects of instruction do not correspond to semantics of RTL insn. */
15796 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
15798 if (INTVAL (startop
) > 32
15799 && INTVAL (startop
) < 64
15800 && INTVAL (sizeop
) > 1
15801 && INTVAL (sizeop
) + INTVAL (startop
) < 64
15802 && INTVAL (shiftop
) > 0
15803 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
15804 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
15810 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
15811 for lfq and stfq insns iff the registers are hard registers. */
15814 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
15816 /* We might have been passed a SUBREG. */
15817 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
15820 /* We might have been passed non floating point registers. */
15821 if (!FP_REGNO_P (REGNO (reg1
))
15822 || !FP_REGNO_P (REGNO (reg2
)))
15825 return (REGNO (reg1
) == REGNO (reg2
) - 1);
15828 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
15829 addr1 and addr2 must be in consecutive memory locations
15830 (addr2 == addr1 + 8). */
15833 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
15836 unsigned int reg1
, reg2
;
15837 int offset1
, offset2
;
15839 /* The mems cannot be volatile. */
15840 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
15843 addr1
= XEXP (mem1
, 0);
15844 addr2
= XEXP (mem2
, 0);
15846 /* Extract an offset (if used) from the first addr. */
15847 if (GET_CODE (addr1
) == PLUS
)
15849 /* If not a REG, return zero. */
15850 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
15854 reg1
= REGNO (XEXP (addr1
, 0));
15855 /* The offset must be constant! */
15856 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
15858 offset1
= INTVAL (XEXP (addr1
, 1));
15861 else if (GET_CODE (addr1
) != REG
)
15865 reg1
= REGNO (addr1
);
15866 /* This was a simple (mem (reg)) expression. Offset is 0. */
15870 /* And now for the second addr. */
15871 if (GET_CODE (addr2
) == PLUS
)
15873 /* If not a REG, return zero. */
15874 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
15878 reg2
= REGNO (XEXP (addr2
, 0));
15879 /* The offset must be constant. */
15880 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
15882 offset2
= INTVAL (XEXP (addr2
, 1));
15885 else if (GET_CODE (addr2
) != REG
)
15889 reg2
= REGNO (addr2
);
15890 /* This was a simple (mem (reg)) expression. Offset is 0. */
15894 /* Both of these must have the same base register. */
15898 /* The offset for the second addr must be 8 more than the first addr. */
15899 if (offset2
!= offset1
+ 8)
15902 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
15909 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
15911 static bool eliminated
= false;
15914 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
15915 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
15918 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
15919 gcc_assert (mem
!= NULL_RTX
);
15923 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
15924 cfun
->machine
->sdmode_stack_slot
= mem
;
15930 if (TARGET_DEBUG_ADDR
)
15932 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
15933 GET_MODE_NAME (mode
));
15935 fprintf (stderr
, "\tNULL_RTX\n");
15943 /* Return the mode to be used for memory when a secondary memory
15944 location is needed. For SDmode values we need to use DDmode, in
15945 all other cases we can use the same mode. */
15947 rs6000_secondary_memory_needed_mode (enum machine_mode mode
)
15949 if (lra_in_progress
&& mode
== SDmode
)
15955 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
15957 /* Don't walk into types. */
15958 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
15960 *walk_subtrees
= 0;
15964 switch (TREE_CODE (*tp
))
15973 case VIEW_CONVERT_EXPR
:
15974 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
15984 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
15985 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
15986 only work on the traditional altivec registers, note if an altivec register
15989 static enum rs6000_reg_type
15990 register_to_reg_type (rtx reg
, bool *is_altivec
)
15992 HOST_WIDE_INT regno
;
15993 enum reg_class rclass
;
15995 if (GET_CODE (reg
) == SUBREG
)
15996 reg
= SUBREG_REG (reg
);
15999 return NO_REG_TYPE
;
16001 regno
= REGNO (reg
);
16002 if (regno
>= FIRST_PSEUDO_REGISTER
)
16004 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
16005 return PSEUDO_REG_TYPE
;
16007 regno
= true_regnum (reg
);
16008 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16009 return PSEUDO_REG_TYPE
;
16012 gcc_assert (regno
>= 0);
16014 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
16015 *is_altivec
= true;
16017 rclass
= rs6000_regno_regclass
[regno
];
16018 return reg_class_to_reg_type
[(int)rclass
];
16021 /* Helper function for rs6000_secondary_reload to return true if a move to a
16022 different register classe is really a simple move. */
16025 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
16026 enum rs6000_reg_type from_type
,
16027 enum machine_mode mode
)
16031 /* Add support for various direct moves available. In this function, we only
16032 look at cases where we don't need any extra registers, and one or more
16033 simple move insns are issued. At present, 32-bit integers are not allowed
16034 in FPR/VSX registers. Single precision binary floating is not a simple
16035 move because we need to convert to the single precision memory layout.
16036 The 4-byte SDmode can be moved. */
16037 size
= GET_MODE_SIZE (mode
);
16038 if (TARGET_DIRECT_MOVE
16039 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
16040 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16041 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16044 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
16045 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
16046 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16049 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
16050 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
16051 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16057 /* Power8 helper function for rs6000_secondary_reload, handle all of the
16058 special direct moves that involve allocating an extra register, return the
16059 insn code of the helper function if there is such a function or
16060 CODE_FOR_nothing if not. */
16063 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
16064 enum rs6000_reg_type from_type
,
16065 enum machine_mode mode
,
16066 secondary_reload_info
*sri
,
16070 enum insn_code icode
= CODE_FOR_nothing
;
16072 int size
= GET_MODE_SIZE (mode
);
16074 if (TARGET_POWERPC64
)
16078 /* Handle moving 128-bit values from GPRs to VSX point registers on
16079 power8 when running in 64-bit mode using XXPERMDI to glue the two
16080 64-bit values back together. */
16081 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16083 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
16084 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16087 /* Handle moving 128-bit values from VSX point registers to GPRs on
16088 power8 when running in 64-bit mode using XXPERMDI to get access to the
16089 bottom 64-bit value. */
16090 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16092 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
16093 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16097 else if (mode
== SFmode
)
16099 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16101 cost
= 3; /* xscvdpspn, mfvsrd, and. */
16102 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16105 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16107 cost
= 2; /* mtvsrz, xscvspdpn. */
16108 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16113 if (TARGET_POWERPC64
&& size
== 16)
16115 /* Handle moving 128-bit values from GPRs to VSX point registers on
16116 power8 when running in 64-bit mode using XXPERMDI to glue the two
16117 64-bit values back together. */
16118 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16120 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
16121 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16124 /* Handle moving 128-bit values from VSX point registers to GPRs on
16125 power8 when running in 64-bit mode using XXPERMDI to get access to the
16126 bottom 64-bit value. */
16127 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16129 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
16130 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16134 else if (!TARGET_POWERPC64
&& size
== 8)
16136 /* Handle moving 64-bit values from GPRs to floating point registers on
16137 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
16138 values back together. Altivec register classes must be handled
16139 specially since a different instruction is used, and the secondary
16140 reload support requires a single instruction class in the scratch
16141 register constraint. However, right now TFmode is not allowed in
16142 Altivec registers, so the pattern will never match. */
16143 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
16145 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
16146 icode
= reg_addr
[mode
].reload_fpr_gpr
;
16150 if (icode
!= CODE_FOR_nothing
)
16155 sri
->icode
= icode
;
16156 sri
->extra_cost
= cost
;
16163 /* Return whether a move between two register classes can be done either
16164 directly (simple move) or via a pattern that uses a single extra temporary
16165 (using power8's direct move in this case. */
16168 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
16169 enum rs6000_reg_type from_type
,
16170 enum machine_mode mode
,
16171 secondary_reload_info
*sri
,
16174 /* Fall back to load/store reloads if either type is not a register. */
16175 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
16178 /* If we haven't allocated registers yet, assume the move can be done for the
16179 standard register types. */
16180 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
16181 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
16182 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
16185 /* Moves to the same set of registers is a simple move for non-specialized
16187 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
16190 /* Check whether a simple move can be done directly. */
16191 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
16195 sri
->icode
= CODE_FOR_nothing
;
16196 sri
->extra_cost
= 0;
16201 /* Now check if we can do it in a few steps. */
16202 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
16206 /* Inform reload about cases where moving X with a mode MODE to a register in
16207 RCLASS requires an extra scratch or immediate register. Return the class
16208 needed for the immediate register.
16210 For VSX and Altivec, we may need a register to convert sp+offset into
16213 For misaligned 64-bit gpr loads and stores we need a register to
16214 convert an offset address to indirect. */
16217 rs6000_secondary_reload (bool in_p
,
16219 reg_class_t rclass_i
,
16220 enum machine_mode mode
,
16221 secondary_reload_info
*sri
)
16223 enum reg_class rclass
= (enum reg_class
) rclass_i
;
16224 reg_class_t ret
= ALL_REGS
;
16225 enum insn_code icode
;
16226 bool default_p
= false;
16228 sri
->icode
= CODE_FOR_nothing
;
16230 ? reg_addr
[mode
].reload_load
16231 : reg_addr
[mode
].reload_store
);
16233 if (REG_P (x
) || register_operand (x
, mode
))
16235 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
16236 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
16237 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
16241 enum rs6000_reg_type exchange
= to_type
;
16242 to_type
= from_type
;
16243 from_type
= exchange
;
16246 /* Can we do a direct move of some sort? */
16247 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
16250 icode
= (enum insn_code
)sri
->icode
;
16256 /* Handle vector moves with reload helper functions. */
16257 if (ret
== ALL_REGS
&& icode
!= CODE_FOR_nothing
)
16260 sri
->icode
= CODE_FOR_nothing
;
16261 sri
->extra_cost
= 0;
16263 if (GET_CODE (x
) == MEM
)
16265 rtx addr
= XEXP (x
, 0);
16267 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
16268 an extra register in that case, but it would need an extra
16269 register if the addressing is reg+reg or (reg+reg)&(-16). Special
16270 case load/store quad. */
16271 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
16273 if (TARGET_POWERPC64
&& TARGET_QUAD_MEMORY
16274 && GET_MODE_SIZE (mode
) == 16
16275 && quad_memory_operand (x
, mode
))
16277 sri
->icode
= icode
;
16278 sri
->extra_cost
= 2;
16281 else if (!legitimate_indirect_address_p (addr
, false)
16282 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16285 sri
->icode
= icode
;
16286 /* account for splitting the loads, and converting the
16287 address from reg+reg to reg. */
16288 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
16289 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
16292 /* Allow scalar loads to/from the traditional floating point
16293 registers, even if VSX memory is set. */
16294 else if ((rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
16295 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16296 && (legitimate_indirect_address_p (addr
, false)
16297 || legitimate_indirect_address_p (addr
, false)
16298 || rs6000_legitimate_offset_address_p (mode
, addr
,
16302 /* Loads to and stores from vector registers can only do reg+reg
16303 addressing. Altivec registers can also do (reg+reg)&(-16). Allow
16304 scalar modes loading up the traditional floating point registers
16305 to use offset addresses. */
16306 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
16307 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
16309 if (!VECTOR_MEM_ALTIVEC_P (mode
)
16310 && GET_CODE (addr
) == AND
16311 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16312 && INTVAL (XEXP (addr
, 1)) == -16
16313 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
16314 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
16316 sri
->icode
= icode
;
16317 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
16320 else if (!legitimate_indirect_address_p (addr
, false)
16321 && (rclass
== NO_REGS
16322 || !legitimate_indexed_address_p (addr
, false)))
16324 sri
->icode
= icode
;
16325 sri
->extra_cost
= 1;
16328 icode
= CODE_FOR_nothing
;
16330 /* Any other loads, including to pseudo registers which haven't been
16331 assigned to a register yet, default to require a scratch
16335 sri
->icode
= icode
;
16336 sri
->extra_cost
= 2;
16339 else if (REG_P (x
))
16341 int regno
= true_regnum (x
);
16343 icode
= CODE_FOR_nothing
;
16344 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16348 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
16349 enum rs6000_reg_type rtype1
= reg_class_to_reg_type
[(int)rclass
];
16350 enum rs6000_reg_type rtype2
= reg_class_to_reg_type
[(int)xclass
];
16352 /* If memory is needed, use default_secondary_reload to create the
16354 if (rtype1
!= rtype2
|| !IS_STD_REG_TYPE (rtype1
))
16363 else if (TARGET_POWERPC64
16364 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
16366 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
16368 rtx addr
= XEXP (x
, 0);
16369 rtx off
= address_offset (addr
);
16371 if (off
!= NULL_RTX
)
16373 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
16374 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
16376 /* We need a secondary reload when our legitimate_address_p
16377 says the address is good (as otherwise the entire address
16378 will be reloaded), and the offset is not a multiple of
16379 four or we have an address wrap. Address wrap will only
16380 occur for LO_SUMs since legitimate_offset_address_p
16381 rejects addresses for 16-byte mems that will wrap. */
16382 if (GET_CODE (addr
) == LO_SUM
16383 ? (1 /* legitimate_address_p allows any offset for lo_sum */
16384 && ((offset
& 3) != 0
16385 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
16386 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
16387 && (offset
& 3) != 0))
16390 sri
->icode
= CODE_FOR_reload_di_load
;
16392 sri
->icode
= CODE_FOR_reload_di_store
;
16393 sri
->extra_cost
= 2;
16402 else if (!TARGET_POWERPC64
16403 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
16405 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
16407 rtx addr
= XEXP (x
, 0);
16408 rtx off
= address_offset (addr
);
16410 if (off
!= NULL_RTX
)
16412 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
16413 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
16415 /* We need a secondary reload when our legitimate_address_p
16416 says the address is good (as otherwise the entire address
16417 will be reloaded), and we have a wrap.
16419 legitimate_lo_sum_address_p allows LO_SUM addresses to
16420 have any offset so test for wrap in the low 16 bits.
16422 legitimate_offset_address_p checks for the range
16423 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
16424 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
16425 [0x7ff4,0x7fff] respectively, so test for the
16426 intersection of these ranges, [0x7ffc,0x7fff] and
16427 [0x7ff4,0x7ff7] respectively.
16429 Note that the address we see here may have been
16430 manipulated by legitimize_reload_address. */
16431 if (GET_CODE (addr
) == LO_SUM
16432 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
16433 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
16436 sri
->icode
= CODE_FOR_reload_si_load
;
16438 sri
->icode
= CODE_FOR_reload_si_store
;
16439 sri
->extra_cost
= 2;
16452 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
16454 gcc_assert (ret
!= ALL_REGS
);
16456 if (TARGET_DEBUG_ADDR
)
16459 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
16461 reg_class_names
[ret
],
16462 in_p
? "true" : "false",
16463 reg_class_names
[rclass
],
16464 GET_MODE_NAME (mode
));
16467 fprintf (stderr
, ", default secondary reload");
16469 if (sri
->icode
!= CODE_FOR_nothing
)
16470 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
16471 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
16473 fprintf (stderr
, "\n");
16481 /* Better tracing for rs6000_secondary_reload_inner. */
16484 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
16489 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
16491 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
16492 store_p
? "store" : "load");
16495 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
16497 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
16499 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
16500 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
16504 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
16507 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
16508 gcc_unreachable ();
16511 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
16512 to SP+reg addressing. */
16515 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16517 int regno
= true_regnum (reg
);
16518 enum machine_mode mode
= GET_MODE (reg
);
16519 enum reg_class rclass
;
16521 rtx and_op2
= NULL_RTX
;
16524 rtx scratch_or_premodify
= scratch
;
16528 if (TARGET_DEBUG_ADDR
)
16529 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
16531 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16532 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16534 if (GET_CODE (mem
) != MEM
)
16535 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16537 rclass
= REGNO_REG_CLASS (regno
);
16538 addr
= find_replacement (&XEXP (mem
, 0));
16542 /* GPRs can handle reg + small constant, all other addresses need to use
16543 the scratch register. */
16546 if (GET_CODE (addr
) == AND
)
16548 and_op2
= XEXP (addr
, 1);
16549 addr
= find_replacement (&XEXP (addr
, 0));
16552 if (GET_CODE (addr
) == PRE_MODIFY
)
16554 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
16555 if (!REG_P (scratch_or_premodify
))
16556 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16558 addr
= find_replacement (&XEXP (addr
, 1));
16559 if (GET_CODE (addr
) != PLUS
)
16560 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16563 if (GET_CODE (addr
) == PLUS
16564 && (and_op2
!= NULL_RTX
16565 || !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16568 /* find_replacement already recurses into both operands of
16569 PLUS so we don't need to call it here. */
16570 addr_op1
= XEXP (addr
, 0);
16571 addr_op2
= XEXP (addr
, 1);
16572 if (!legitimate_indirect_address_p (addr_op1
, false))
16573 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16575 if (!REG_P (addr_op2
)
16576 && (GET_CODE (addr_op2
) != CONST_INT
16577 || !satisfies_constraint_I (addr_op2
)))
16579 if (TARGET_DEBUG_ADDR
)
16582 "\nMove plus addr to register %s, mode = %s: ",
16583 rs6000_reg_names
[REGNO (scratch
)],
16584 GET_MODE_NAME (mode
));
16585 debug_rtx (addr_op2
);
16587 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16588 addr_op2
= scratch
;
16591 emit_insn (gen_rtx_SET (VOIDmode
,
16592 scratch_or_premodify
,
16593 gen_rtx_PLUS (Pmode
,
16597 addr
= scratch_or_premodify
;
16598 scratch_or_premodify
= scratch
;
16600 else if (!legitimate_indirect_address_p (addr
, false)
16601 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16604 if (TARGET_DEBUG_ADDR
)
16606 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16607 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16608 GET_MODE_NAME (mode
));
16611 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16612 addr
= scratch_or_premodify
;
16613 scratch_or_premodify
= scratch
;
16617 /* Float registers can do offset+reg addressing for scalar types. */
16619 if (legitimate_indirect_address_p (addr
, false) /* reg */
16620 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16621 || ((GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16622 && and_op2
== NULL_RTX
16623 && scratch_or_premodify
== scratch
16624 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
16627 /* If this isn't a legacy floating point load/store, fall through to the
16630 /* VSX/Altivec registers can only handle reg+reg addressing. Move other
16631 addresses into a scratch register. */
16635 /* With float regs, we need to handle the AND ourselves, since we can't
16636 use the Altivec instruction with an implicit AND -16. Allow scalar
16637 loads to float registers to use reg+offset even if VSX. */
16638 if (GET_CODE (addr
) == AND
16639 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
16640 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
16641 || INTVAL (XEXP (addr
, 1)) != -16
16642 || !VECTOR_MEM_ALTIVEC_P (mode
)))
16644 and_op2
= XEXP (addr
, 1);
16645 addr
= find_replacement (&XEXP (addr
, 0));
16648 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
16649 as the address later. */
16650 if (GET_CODE (addr
) == PRE_MODIFY
16651 && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
16652 && (rclass
!= FLOAT_REGS
16653 || (GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)))
16654 || and_op2
!= NULL_RTX
16655 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
16657 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
16658 if (!legitimate_indirect_address_p (scratch_or_premodify
, false))
16659 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16661 addr
= find_replacement (&XEXP (addr
, 1));
16662 if (GET_CODE (addr
) != PLUS
)
16663 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16666 if (legitimate_indirect_address_p (addr
, false) /* reg */
16667 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16668 || (GET_CODE (addr
) == AND
/* Altivec memory */
16669 && rclass
== ALTIVEC_REGS
16670 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16671 && INTVAL (XEXP (addr
, 1)) == -16
16672 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
16673 || legitimate_indexed_address_p (XEXP (addr
, 0), false))))
16676 else if (GET_CODE (addr
) == PLUS
)
16678 addr_op1
= XEXP (addr
, 0);
16679 addr_op2
= XEXP (addr
, 1);
16680 if (!REG_P (addr_op1
))
16681 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16683 if (TARGET_DEBUG_ADDR
)
16685 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
16686 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16687 debug_rtx (addr_op2
);
16689 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16690 emit_insn (gen_rtx_SET (VOIDmode
,
16691 scratch_or_premodify
,
16692 gen_rtx_PLUS (Pmode
,
16695 addr
= scratch_or_premodify
;
16696 scratch_or_premodify
= scratch
;
16699 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
16700 || GET_CODE (addr
) == CONST_INT
|| GET_CODE (addr
) == LO_SUM
16703 if (TARGET_DEBUG_ADDR
)
16705 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16706 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16707 GET_MODE_NAME (mode
));
16711 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16712 addr
= scratch_or_premodify
;
16713 scratch_or_premodify
= scratch
;
16717 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16722 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16725 /* If the original address involved a pre-modify that we couldn't use the VSX
16726 memory instruction with update, and we haven't taken care of already,
16727 store the address in the pre-modify register and use that as the
16729 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
16731 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
16732 addr
= scratch_or_premodify
;
16735 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
16736 memory instruction, recreate the AND now, including the clobber which is
16737 generated by the general ANDSI3/ANDDI3 patterns for the
16738 andi. instruction. */
16739 if (and_op2
!= NULL_RTX
)
16741 if (! legitimate_indirect_address_p (addr
, false))
16743 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
16747 if (TARGET_DEBUG_ADDR
)
16749 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
16750 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16751 debug_rtx (and_op2
);
16754 and_rtx
= gen_rtx_SET (VOIDmode
,
16756 gen_rtx_AND (Pmode
,
16760 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
16761 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
16762 gen_rtvec (2, and_rtx
, cc_clobber
)));
16766 /* Adjust the address if it changed. */
16767 if (addr
!= XEXP (mem
, 0))
16769 mem
= replace_equiv_address_nv (mem
, addr
);
16770 if (TARGET_DEBUG_ADDR
)
16771 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
16774 /* Now create the move. */
16776 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16778 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16783 /* Convert reloads involving 64-bit gprs and misaligned offset
16784 addressing, or multiple 32-bit gprs and offsets that are too large,
16785 to use indirect addressing. */
16788 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16790 int regno
= true_regnum (reg
);
16791 enum reg_class rclass
;
16793 rtx scratch_or_premodify
= scratch
;
16795 if (TARGET_DEBUG_ADDR
)
16797 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
16798 store_p
? "store" : "load");
16799 fprintf (stderr
, "reg:\n");
16801 fprintf (stderr
, "mem:\n");
16803 fprintf (stderr
, "scratch:\n");
16804 debug_rtx (scratch
);
16807 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
16808 gcc_assert (GET_CODE (mem
) == MEM
);
16809 rclass
= REGNO_REG_CLASS (regno
);
16810 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
16811 addr
= XEXP (mem
, 0);
16813 if (GET_CODE (addr
) == PRE_MODIFY
)
16815 scratch_or_premodify
= XEXP (addr
, 0);
16816 gcc_assert (REG_P (scratch_or_premodify
));
16817 addr
= XEXP (addr
, 1);
16819 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
16821 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16823 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
16825 /* Now create the move. */
16827 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16829 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16834 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
16835 this function has any SDmode references. If we are on a power7 or later, we
16836 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
16837 can load/store the value. */
16840 rs6000_alloc_sdmode_stack_slot (void)
16844 gimple_stmt_iterator gsi
;
16846 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
16847 /* We use a different approach for dealing with the secondary
16852 if (TARGET_NO_SDMODE_STACK
)
16855 FOR_EACH_BB_FN (bb
, cfun
)
16856 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
16858 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
16861 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
16862 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
16868 /* Check for any SDmode parameters of the function. */
16869 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
16871 if (TREE_TYPE (t
) == error_mark_node
)
16874 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
16875 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
16877 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
16878 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
16886 rs6000_instantiate_decls (void)
16888 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
16889 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
16892 /* Given an rtx X being reloaded into a reg required to be
16893 in class CLASS, return the class of reg to actually use.
16894 In general this is just CLASS; but on some machines
16895 in some cases it is preferable to use a more restrictive class.
16897 On the RS/6000, we have to return NO_REGS when we want to reload a
16898 floating-point CONST_DOUBLE to force it to be copied to memory.
16900 We also don't want to reload integer values into floating-point
16901 registers if we can at all help it. In fact, this can
16902 cause reload to die, if it tries to generate a reload of CTR
16903 into a FP register and discovers it doesn't have the memory location
16906 ??? Would it be a good idea to have reload do the converse, that is
16907 try to reload floating modes into FP registers if possible?
16910 static enum reg_class
16911 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
16913 enum machine_mode mode
= GET_MODE (x
);
16915 if (TARGET_VSX
&& x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
16918 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
16919 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
16920 && easy_vector_constant (x
, mode
))
16921 return ALTIVEC_REGS
;
16923 if ((CONSTANT_P (x
) || GET_CODE (x
) == PLUS
))
16925 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
16926 return GENERAL_REGS
;
16927 if (reg_class_subset_p (BASE_REGS
, rclass
))
16932 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
16933 return GENERAL_REGS
;
16935 /* For VSX, prefer the traditional registers for 64-bit values because we can
16936 use the non-VSX loads. Prefer the Altivec registers if Altivec is
16937 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
16938 prefer Altivec loads.. */
16939 if (rclass
== VSX_REGS
)
16941 if (GET_MODE_SIZE (mode
) <= 8)
16944 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
16945 || mode
== V1TImode
)
16946 return ALTIVEC_REGS
;
16954 /* Debug version of rs6000_preferred_reload_class. */
16955 static enum reg_class
16956 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
16958 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
16961 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
16963 reg_class_names
[ret
], reg_class_names
[rclass
],
16964 GET_MODE_NAME (GET_MODE (x
)));
16970 /* If we are copying between FP or AltiVec registers and anything else, we need
16971 a memory location. The exception is when we are targeting ppc64 and the
16972 move to/from fpr to gpr instructions are available. Also, under VSX, you
16973 can copy vector registers from the FP register set to the Altivec register
16974 set and vice versa. */
16977 rs6000_secondary_memory_needed (enum reg_class from_class
,
16978 enum reg_class to_class
,
16979 enum machine_mode mode
)
16981 enum rs6000_reg_type from_type
, to_type
;
16982 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
16983 || (to_class
== ALTIVEC_REGS
));
16985 /* If a simple/direct move is available, we don't need secondary memory */
16986 from_type
= reg_class_to_reg_type
[(int)from_class
];
16987 to_type
= reg_class_to_reg_type
[(int)to_class
];
16989 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
16990 (secondary_reload_info
*)0, altivec_p
))
16993 /* If we have a floating point or vector register class, we need to use
16994 memory to transfer the data. */
16995 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
17001 /* Debug version of rs6000_secondary_memory_needed. */
17003 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
17004 enum reg_class to_class
,
17005 enum machine_mode mode
)
17007 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
17010 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
17011 "to_class = %s, mode = %s\n",
17012 ret
? "true" : "false",
17013 reg_class_names
[from_class
],
17014 reg_class_names
[to_class
],
17015 GET_MODE_NAME (mode
));
17020 /* Return the register class of a scratch register needed to copy IN into
17021 or out of a register in RCLASS in MODE. If it can be done directly,
17022 NO_REGS is returned. */
17024 static enum reg_class
17025 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
17030 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
17032 && MACHOPIC_INDIRECT
17036 /* We cannot copy a symbolic operand directly into anything
17037 other than BASE_REGS for TARGET_ELF. So indicate that a
17038 register from BASE_REGS is needed as an intermediate
17041 On Darwin, pic addresses require a load from memory, which
17042 needs a base register. */
17043 if (rclass
!= BASE_REGS
17044 && (GET_CODE (in
) == SYMBOL_REF
17045 || GET_CODE (in
) == HIGH
17046 || GET_CODE (in
) == LABEL_REF
17047 || GET_CODE (in
) == CONST
))
17051 if (GET_CODE (in
) == REG
)
17053 regno
= REGNO (in
);
17054 if (regno
>= FIRST_PSEUDO_REGISTER
)
17056 regno
= true_regnum (in
);
17057 if (regno
>= FIRST_PSEUDO_REGISTER
)
17061 else if (GET_CODE (in
) == SUBREG
)
17063 regno
= true_regnum (in
);
17064 if (regno
>= FIRST_PSEUDO_REGISTER
)
17070 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
17072 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
17073 || (regno
>= 0 && INT_REGNO_P (regno
)))
17076 /* Constants, memory, and FP registers can go into FP registers. */
17077 if ((regno
== -1 || FP_REGNO_P (regno
))
17078 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
17079 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
17081 /* Memory, and FP/altivec registers can go into fp/altivec registers under
17082 VSX. However, for scalar variables, use the traditional floating point
17083 registers so that we can use offset+register addressing. */
17085 && (regno
== -1 || VSX_REGNO_P (regno
))
17086 && VSX_REG_CLASS_P (rclass
))
17088 if (GET_MODE_SIZE (mode
) < 16)
17094 /* Memory, and AltiVec registers can go into AltiVec registers. */
17095 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
17096 && rclass
== ALTIVEC_REGS
)
17099 /* We can copy among the CR registers. */
17100 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
17101 && regno
>= 0 && CR_REGNO_P (regno
))
17104 /* Otherwise, we need GENERAL_REGS. */
17105 return GENERAL_REGS
;
17108 /* Debug version of rs6000_secondary_reload_class. */
17109 static enum reg_class
17110 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
17111 enum machine_mode mode
, rtx in
)
17113 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
17115 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
17116 "mode = %s, input rtx:\n",
17117 reg_class_names
[ret
], reg_class_names
[rclass
],
17118 GET_MODE_NAME (mode
));
17124 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
17127 rs6000_cannot_change_mode_class (enum machine_mode from
,
17128 enum machine_mode to
,
17129 enum reg_class rclass
)
17131 unsigned from_size
= GET_MODE_SIZE (from
);
17132 unsigned to_size
= GET_MODE_SIZE (to
);
17134 if (from_size
!= to_size
)
17136 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
17138 if (reg_classes_intersect_p (xclass
, rclass
))
17140 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
17141 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
17143 /* Don't allow 64-bit types to overlap with 128-bit types that take a
17144 single register under VSX because the scalar part of the register
17145 is in the upper 64-bits, and not the lower 64-bits. Types like
17146 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
17147 IEEE floating point can't overlap, and neither can small
17150 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
17153 /* TDmode in floating-mode registers must always go into a register
17154 pair with the most significant word in the even-numbered register
17155 to match ISA requirements. In little-endian mode, this does not
17156 match subreg numbering, so we cannot allow subregs. */
17157 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
17160 if (from_size
< 8 || to_size
< 8)
17163 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
17166 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
17175 if (TARGET_E500_DOUBLE
17176 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
17177 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
17178 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
17179 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
17180 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
17183 /* Since the VSX register set includes traditional floating point registers
17184 and altivec registers, just check for the size being different instead of
17185 trying to check whether the modes are vector modes. Otherwise it won't
17186 allow say DF and DI to change classes. For types like TFmode and TDmode
17187 that take 2 64-bit registers, rather than a single 128-bit register, don't
17188 allow subregs of those types to other 128 bit types. */
17189 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
17191 unsigned num_regs
= (from_size
+ 15) / 16;
17192 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
17193 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
17196 return (from_size
!= 8 && from_size
!= 16);
17199 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
17200 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
17203 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
17204 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
17210 /* Debug version of rs6000_cannot_change_mode_class. */
17212 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
17213 enum machine_mode to
,
17214 enum reg_class rclass
)
17216 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
17219 "rs6000_cannot_change_mode_class, return %s, from = %s, "
17220 "to = %s, rclass = %s\n",
17221 ret
? "true" : "false",
17222 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
17223 reg_class_names
[rclass
]);
17228 /* Return a string to do a move operation of 128 bits of data. */
17231 rs6000_output_move_128bit (rtx operands
[])
17233 rtx dest
= operands
[0];
17234 rtx src
= operands
[1];
17235 enum machine_mode mode
= GET_MODE (dest
);
17238 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
17239 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
17243 dest_regno
= REGNO (dest
);
17244 dest_gpr_p
= INT_REGNO_P (dest_regno
);
17245 dest_fp_p
= FP_REGNO_P (dest_regno
);
17246 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
17247 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
17252 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
17257 src_regno
= REGNO (src
);
17258 src_gpr_p
= INT_REGNO_P (src_regno
);
17259 src_fp_p
= FP_REGNO_P (src_regno
);
17260 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
17261 src_vsx_p
= src_fp_p
| src_vmx_p
;
17266 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
17269 /* Register moves. */
17270 if (dest_regno
>= 0 && src_regno
>= 0)
17277 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
17281 else if (TARGET_VSX
&& dest_vsx_p
)
17284 return "xxlor %x0,%x1,%x1";
17286 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
17290 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
17291 return "vor %0,%1,%1";
17293 else if (dest_fp_p
&& src_fp_p
)
17298 else if (dest_regno
>= 0 && MEM_P (src
))
17302 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
17308 else if (TARGET_ALTIVEC
&& dest_vmx_p
17309 && altivec_indexed_or_indirect_operand (src
, mode
))
17310 return "lvx %0,%y1";
17312 else if (TARGET_VSX
&& dest_vsx_p
)
17314 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
17315 return "lxvw4x %x0,%y1";
17317 return "lxvd2x %x0,%y1";
17320 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
17321 return "lvx %0,%y1";
17323 else if (dest_fp_p
)
17328 else if (src_regno
>= 0 && MEM_P (dest
))
17332 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
17333 return "stq %1,%0";
17338 else if (TARGET_ALTIVEC
&& src_vmx_p
17339 && altivec_indexed_or_indirect_operand (src
, mode
))
17340 return "stvx %1,%y0";
17342 else if (TARGET_VSX
&& src_vsx_p
)
17344 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
17345 return "stxvw4x %x1,%y0";
17347 return "stxvd2x %x1,%y0";
17350 else if (TARGET_ALTIVEC
&& src_vmx_p
)
17351 return "stvx %1,%y0";
17358 else if (dest_regno
>= 0
17359 && (GET_CODE (src
) == CONST_INT
17360 || GET_CODE (src
) == CONST_DOUBLE
17361 || GET_CODE (src
) == CONST_VECTOR
))
17366 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
17367 return "xxlxor %x0,%x0,%x0";
17369 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
17370 return output_vec_const_move (operands
);
17373 if (TARGET_DEBUG_ADDR
)
17375 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
17376 debug_rtx (gen_rtx_SET (VOIDmode
, dest
, src
));
17379 gcc_unreachable ();
17382 /* Validate a 128-bit move. */
17384 rs6000_move_128bit_ok_p (rtx operands
[])
17386 enum machine_mode mode
= GET_MODE (operands
[0]);
17387 return (gpc_reg_operand (operands
[0], mode
)
17388 || gpc_reg_operand (operands
[1], mode
));
17391 /* Return true if a 128-bit move needs to be split. */
17393 rs6000_split_128bit_ok_p (rtx operands
[])
17395 if (!reload_completed
)
17398 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
17401 if (quad_load_store_p (operands
[0], operands
[1]))
17408 /* Given a comparison operation, return the bit number in CCR to test. We
17409 know this is a valid comparison.
17411 SCC_P is 1 if this is for an scc. That means that %D will have been
17412 used instead of %C, so the bits will be in different places.
17414 Return -1 if OP isn't a valid comparison for some reason. */
17417 ccr_bit (rtx op
, int scc_p
)
17419 enum rtx_code code
= GET_CODE (op
);
17420 enum machine_mode cc_mode
;
17425 if (!COMPARISON_P (op
))
17428 reg
= XEXP (op
, 0);
17430 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
17432 cc_mode
= GET_MODE (reg
);
17433 cc_regnum
= REGNO (reg
);
17434 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
17436 validate_condition_mode (code
, cc_mode
);
17438 /* When generating a sCOND operation, only positive conditions are
17441 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
17442 || code
== GTU
|| code
== LTU
);
17447 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
17449 return base_bit
+ 2;
17450 case GT
: case GTU
: case UNLE
:
17451 return base_bit
+ 1;
17452 case LT
: case LTU
: case UNGE
:
17454 case ORDERED
: case UNORDERED
:
17455 return base_bit
+ 3;
17458 /* If scc, we will have done a cror to put the bit in the
17459 unordered position. So test that bit. For integer, this is ! LT
17460 unless this is an scc insn. */
17461 return scc_p
? base_bit
+ 3 : base_bit
;
17464 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
17467 gcc_unreachable ();
17471 /* Return the GOT register. */
17474 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
17476 /* The second flow pass currently (June 1999) can't update
17477 regs_ever_live without disturbing other parts of the compiler, so
17478 update it here to make the prolog/epilogue code happy. */
17479 if (!can_create_pseudo_p ()
17480 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
17481 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
17483 crtl
->uses_pic_offset_table
= 1;
17485 return pic_offset_table_rtx
;
17488 static rs6000_stack_t stack_info
;
17490 /* Function to init struct machine_function.
17491 This will be called, via a pointer variable,
17492 from push_function_context. */
17494 static struct machine_function
*
17495 rs6000_init_machine_status (void)
17497 stack_info
.reload_completed
= 0;
17498 return ggc_alloc_cleared_machine_function ();
17501 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
17504 extract_MB (rtx op
)
17507 unsigned long val
= INTVAL (op
);
17509 /* If the high bit is zero, the value is the first 1 bit we find
17511 if ((val
& 0x80000000) == 0)
17513 gcc_assert (val
& 0xffffffff);
17516 while (((val
<<= 1) & 0x80000000) == 0)
17521 /* If the high bit is set and the low bit is not, or the mask is all
17522 1's, the value is zero. */
17523 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
17526 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17529 while (((val
>>= 1) & 1) != 0)
17536 extract_ME (rtx op
)
17539 unsigned long val
= INTVAL (op
);
17541 /* If the low bit is zero, the value is the first 1 bit we find from
17543 if ((val
& 1) == 0)
17545 gcc_assert (val
& 0xffffffff);
17548 while (((val
>>= 1) & 1) == 0)
17554 /* If the low bit is set and the high bit is not, or the mask is all
17555 1's, the value is 31. */
17556 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
17559 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17562 while (((val
<<= 1) & 0x80000000) != 0)
17568 /* Locate some local-dynamic symbol still in use by this function
17569 so that we can print its name in some tls_ld pattern. */
17571 static const char *
17572 rs6000_get_some_local_dynamic_name (void)
17576 if (cfun
->machine
->some_ld_name
)
17577 return cfun
->machine
->some_ld_name
;
17579 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
17581 && for_each_rtx (&PATTERN (insn
),
17582 rs6000_get_some_local_dynamic_name_1
, 0))
17583 return cfun
->machine
->some_ld_name
;
17585 gcc_unreachable ();
17588 /* Helper function for rs6000_get_some_local_dynamic_name. */
17591 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
17595 if (GET_CODE (x
) == SYMBOL_REF
)
17597 const char *str
= XSTR (x
, 0);
17598 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
17600 cfun
->machine
->some_ld_name
= str
;
17608 /* Write out a function code label. */
17611 rs6000_output_function_entry (FILE *file
, const char *fname
)
17613 if (fname
[0] != '.')
17615 switch (DEFAULT_ABI
)
17618 gcc_unreachable ();
17624 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
17634 RS6000_OUTPUT_BASENAME (file
, fname
);
17637 /* Print an operand. Recognize special options, documented below. */
17640 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
17641 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
17643 #define SMALL_DATA_RELOC "sda21"
17644 #define SMALL_DATA_REG 0
17648 print_operand (FILE *file
, rtx x
, int code
)
17651 unsigned HOST_WIDE_INT uval
;
17655 /* %a is output_address. */
17658 /* If constant, low-order 16 bits of constant, unsigned.
17659 Otherwise, write normally. */
17661 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
17663 print_operand (file
, x
, 0);
17667 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
17668 for 64-bit mask direction. */
17669 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
17672 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
17676 /* Like 'J' but get to the GT bit only. */
17677 gcc_assert (REG_P (x
));
17679 /* Bit 1 is GT bit. */
17680 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
17682 /* Add one for shift count in rlinm for scc. */
17683 fprintf (file
, "%d", i
+ 1);
17687 /* X is a CR register. Print the number of the EQ bit of the CR */
17688 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17689 output_operand_lossage ("invalid %%E value");
17691 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
17695 /* X is a CR register. Print the shift count needed to move it
17696 to the high-order four bits. */
17697 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17698 output_operand_lossage ("invalid %%f value");
17700 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
17704 /* Similar, but print the count for the rotate in the opposite
17706 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17707 output_operand_lossage ("invalid %%F value");
17709 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
17713 /* X is a constant integer. If it is negative, print "m",
17714 otherwise print "z". This is to make an aze or ame insn. */
17715 if (GET_CODE (x
) != CONST_INT
)
17716 output_operand_lossage ("invalid %%G value");
17717 else if (INTVAL (x
) >= 0)
17724 /* If constant, output low-order five bits. Otherwise, write
17727 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
17729 print_operand (file
, x
, 0);
17733 /* If constant, output low-order six bits. Otherwise, write
17736 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
17738 print_operand (file
, x
, 0);
17742 /* Print `i' if this is a constant, else nothing. */
17748 /* Write the bit number in CCR for jump. */
17749 i
= ccr_bit (x
, 0);
17751 output_operand_lossage ("invalid %%j code");
17753 fprintf (file
, "%d", i
);
17757 /* Similar, but add one for shift count in rlinm for scc and pass
17758 scc flag to `ccr_bit'. */
17759 i
= ccr_bit (x
, 1);
17761 output_operand_lossage ("invalid %%J code");
17763 /* If we want bit 31, write a shift count of zero, not 32. */
17764 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
17768 /* X must be a constant. Write the 1's complement of the
17771 output_operand_lossage ("invalid %%k value");
17773 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
17777 /* X must be a symbolic constant on ELF. Write an
17778 expression suitable for an 'addi' that adds in the low 16
17779 bits of the MEM. */
17780 if (GET_CODE (x
) == CONST
)
17782 if (GET_CODE (XEXP (x
, 0)) != PLUS
17783 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
17784 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
17785 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
17786 output_operand_lossage ("invalid %%K value");
17788 print_operand_address (file
, x
);
17789 fputs ("@l", file
);
17792 /* %l is output_asm_label. */
17795 /* Write second word of DImode or DFmode reference. Works on register
17796 or non-indexed memory only. */
17798 fputs (reg_names
[REGNO (x
) + 1], file
);
17799 else if (MEM_P (x
))
17801 /* Handle possible auto-increment. Since it is pre-increment and
17802 we have already done it, we can just use an offset of word. */
17803 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17804 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17805 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17807 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17808 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17811 output_address (XEXP (adjust_address_nv (x
, SImode
,
17815 if (small_data_operand (x
, GET_MODE (x
)))
17816 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17817 reg_names
[SMALL_DATA_REG
]);
17822 /* MB value for a mask operand. */
17823 if (! mask_operand (x
, SImode
))
17824 output_operand_lossage ("invalid %%m value");
17826 fprintf (file
, "%d", extract_MB (x
));
17830 /* ME value for a mask operand. */
17831 if (! mask_operand (x
, SImode
))
17832 output_operand_lossage ("invalid %%M value");
17834 fprintf (file
, "%d", extract_ME (x
));
17837 /* %n outputs the negative of its operand. */
17840 /* Write the number of elements in the vector times 4. */
17841 if (GET_CODE (x
) != PARALLEL
)
17842 output_operand_lossage ("invalid %%N value");
17844 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
17848 /* Similar, but subtract 1 first. */
17849 if (GET_CODE (x
) != PARALLEL
)
17850 output_operand_lossage ("invalid %%O value");
17852 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
17856 /* X is a CONST_INT that is a power of two. Output the logarithm. */
17859 || (i
= exact_log2 (INTVAL (x
))) < 0)
17860 output_operand_lossage ("invalid %%p value");
17862 fprintf (file
, "%d", i
);
17866 /* The operand must be an indirect memory reference. The result
17867 is the register name. */
17868 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
17869 || REGNO (XEXP (x
, 0)) >= 32)
17870 output_operand_lossage ("invalid %%P value");
17872 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
17876 /* This outputs the logical code corresponding to a boolean
17877 expression. The expression may have one or both operands
17878 negated (if one, only the first one). For condition register
17879 logical operations, it will also treat the negated
17880 CR codes as NOTs, but not handle NOTs of them. */
17882 const char *const *t
= 0;
17884 enum rtx_code code
= GET_CODE (x
);
17885 static const char * const tbl
[3][3] = {
17886 { "and", "andc", "nor" },
17887 { "or", "orc", "nand" },
17888 { "xor", "eqv", "xor" } };
17892 else if (code
== IOR
)
17894 else if (code
== XOR
)
17897 output_operand_lossage ("invalid %%q value");
17899 if (GET_CODE (XEXP (x
, 0)) != NOT
)
17903 if (GET_CODE (XEXP (x
, 1)) == NOT
)
17914 if (! TARGET_MFCRF
)
17920 /* X is a CR register. Print the mask for `mtcrf'. */
17921 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17922 output_operand_lossage ("invalid %%R value");
17924 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
17928 /* Low 5 bits of 32 - value */
17930 output_operand_lossage ("invalid %%s value");
17932 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
17936 /* PowerPC64 mask position. All 0's is excluded.
17937 CONST_INT 32-bit mask is considered sign-extended so any
17938 transition must occur within the CONST_INT, not on the boundary. */
17939 if (! mask64_operand (x
, DImode
))
17940 output_operand_lossage ("invalid %%S value");
17944 if (uval
& 1) /* Clear Left */
17946 #if HOST_BITS_PER_WIDE_INT > 64
17947 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
17951 else /* Clear Right */
17954 #if HOST_BITS_PER_WIDE_INT > 64
17955 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
17961 gcc_assert (i
>= 0);
17962 fprintf (file
, "%d", i
);
17966 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
17967 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
17969 /* Bit 3 is OV bit. */
17970 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
17972 /* If we want bit 31, write a shift count of zero, not 32. */
17973 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
17977 /* Print the symbolic name of a branch target register. */
17978 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
17979 && REGNO (x
) != CTR_REGNO
))
17980 output_operand_lossage ("invalid %%T value");
17981 else if (REGNO (x
) == LR_REGNO
)
17982 fputs ("lr", file
);
17984 fputs ("ctr", file
);
17988 /* High-order 16 bits of constant for use in unsigned operand. */
17990 output_operand_lossage ("invalid %%u value");
17992 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
17993 (INTVAL (x
) >> 16) & 0xffff);
17997 /* High-order 16 bits of constant for use in signed operand. */
17999 output_operand_lossage ("invalid %%v value");
18001 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
18002 (INTVAL (x
) >> 16) & 0xffff);
18006 /* Print `u' if this has an auto-increment or auto-decrement. */
18008 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
18009 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
18010 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
18015 /* Print the trap code for this operand. */
18016 switch (GET_CODE (x
))
18019 fputs ("eq", file
); /* 4 */
18022 fputs ("ne", file
); /* 24 */
18025 fputs ("lt", file
); /* 16 */
18028 fputs ("le", file
); /* 20 */
18031 fputs ("gt", file
); /* 8 */
18034 fputs ("ge", file
); /* 12 */
18037 fputs ("llt", file
); /* 2 */
18040 fputs ("lle", file
); /* 6 */
18043 fputs ("lgt", file
); /* 1 */
18046 fputs ("lge", file
); /* 5 */
18049 gcc_unreachable ();
18054 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
18057 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
18058 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
18060 print_operand (file
, x
, 0);
18064 /* MB value for a PowerPC64 rldic operand. */
18065 i
= clz_hwi (INTVAL (x
));
18067 fprintf (file
, "%d", i
);
18071 /* X is a FPR or Altivec register used in a VSX context. */
18072 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
18073 output_operand_lossage ("invalid %%x value");
18076 int reg
= REGNO (x
);
18077 int vsx_reg
= (FP_REGNO_P (reg
)
18079 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
18081 #ifdef TARGET_REGNAMES
18082 if (TARGET_REGNAMES
)
18083 fprintf (file
, "%%vs%d", vsx_reg
);
18086 fprintf (file
, "%d", vsx_reg
);
18092 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
18093 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
18094 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
18099 /* Like 'L', for third word of TImode/PTImode */
18101 fputs (reg_names
[REGNO (x
) + 2], file
);
18102 else if (MEM_P (x
))
18104 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18105 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18106 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
18107 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18108 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
18110 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
18111 if (small_data_operand (x
, GET_MODE (x
)))
18112 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18113 reg_names
[SMALL_DATA_REG
]);
18118 /* X is a SYMBOL_REF. Write out the name preceded by a
18119 period and without any trailing data in brackets. Used for function
18120 names. If we are configured for System V (or the embedded ABI) on
18121 the PowerPC, do not emit the period, since those systems do not use
18122 TOCs and the like. */
18123 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
18125 /* For macho, check to see if we need a stub. */
18128 const char *name
= XSTR (x
, 0);
18130 if (darwin_emit_branch_islands
18131 && MACHOPIC_INDIRECT
18132 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
18133 name
= machopic_indirection_name (x
, /*stub_p=*/true);
18135 assemble_name (file
, name
);
18137 else if (!DOT_SYMBOLS
)
18138 assemble_name (file
, XSTR (x
, 0));
18140 rs6000_output_function_entry (file
, XSTR (x
, 0));
18144 /* Like 'L', for last word of TImode/PTImode. */
18146 fputs (reg_names
[REGNO (x
) + 3], file
);
18147 else if (MEM_P (x
))
18149 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18150 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18151 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
18152 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18153 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
18155 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
18156 if (small_data_operand (x
, GET_MODE (x
)))
18157 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18158 reg_names
[SMALL_DATA_REG
]);
18162 /* Print AltiVec or SPE memory operand. */
18167 gcc_assert (MEM_P (x
));
18171 /* Ugly hack because %y is overloaded. */
18172 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
18173 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
18174 || GET_MODE (x
) == TFmode
18175 || GET_MODE (x
) == TImode
18176 || GET_MODE (x
) == PTImode
))
18178 /* Handle [reg]. */
18181 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
18184 /* Handle [reg+UIMM]. */
18185 else if (GET_CODE (tmp
) == PLUS
&&
18186 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
18190 gcc_assert (REG_P (XEXP (tmp
, 0)));
18192 x
= INTVAL (XEXP (tmp
, 1));
18193 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
18197 /* Fall through. Must be [reg+reg]. */
18199 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
18200 && GET_CODE (tmp
) == AND
18201 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
18202 && INTVAL (XEXP (tmp
, 1)) == -16)
18203 tmp
= XEXP (tmp
, 0);
18204 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
18205 && GET_CODE (tmp
) == PRE_MODIFY
)
18206 tmp
= XEXP (tmp
, 1);
18208 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
18211 if (!GET_CODE (tmp
) == PLUS
18212 || !REG_P (XEXP (tmp
, 0))
18213 || !REG_P (XEXP (tmp
, 1)))
18215 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
18219 if (REGNO (XEXP (tmp
, 0)) == 0)
18220 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
18221 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
18223 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
18224 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
18231 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
18232 else if (MEM_P (x
))
18234 /* We need to handle PRE_INC and PRE_DEC here, since we need to
18235 know the width from the mode. */
18236 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
18237 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
18238 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
18239 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18240 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
18241 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
18242 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18243 output_address (XEXP (XEXP (x
, 0), 1));
18245 output_address (XEXP (x
, 0));
18249 if (toc_relative_expr_p (x
, false))
18250 /* This hack along with a corresponding hack in
18251 rs6000_output_addr_const_extra arranges to output addends
18252 where the assembler expects to find them. eg.
18253 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
18254 without this hack would be output as "x@toc+4". We
18256 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
18258 output_addr_const (file
, x
);
18263 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
18267 output_operand_lossage ("invalid %%xn code");
18271 /* Print the address of an operand. */
18274 print_operand_address (FILE *file
, rtx x
)
18277 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
18278 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
18279 || GET_CODE (x
) == LABEL_REF
)
18281 output_addr_const (file
, x
);
18282 if (small_data_operand (x
, GET_MODE (x
)))
18283 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18284 reg_names
[SMALL_DATA_REG
]);
18286 gcc_assert (!TARGET_TOC
);
18288 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
18289 && REG_P (XEXP (x
, 1)))
18291 if (REGNO (XEXP (x
, 0)) == 0)
18292 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
18293 reg_names
[ REGNO (XEXP (x
, 0)) ]);
18295 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
18296 reg_names
[ REGNO (XEXP (x
, 1)) ]);
18298 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
18299 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
18300 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
18301 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
18303 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
18304 && CONSTANT_P (XEXP (x
, 1)))
18306 fprintf (file
, "lo16(");
18307 output_addr_const (file
, XEXP (x
, 1));
18308 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
18312 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
18313 && CONSTANT_P (XEXP (x
, 1)))
18315 output_addr_const (file
, XEXP (x
, 1));
18316 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
18319 else if (toc_relative_expr_p (x
, false))
18321 /* This hack along with a corresponding hack in
18322 rs6000_output_addr_const_extra arranges to output addends
18323 where the assembler expects to find them. eg.
18325 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
18326 without this hack would be output as "x@toc+8@l(9)". We
18327 want "x+8@toc@l(9)". */
18328 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
18329 if (GET_CODE (x
) == LO_SUM
)
18330 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
18332 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
18335 gcc_unreachable ();
18338 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
18341 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
18343 if (GET_CODE (x
) == UNSPEC
)
18344 switch (XINT (x
, 1))
18346 case UNSPEC_TOCREL
:
18347 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
18348 && REG_P (XVECEXP (x
, 0, 1))
18349 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
18350 output_addr_const (file
, XVECEXP (x
, 0, 0));
18351 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
18353 if (INTVAL (tocrel_offset
) >= 0)
18354 fprintf (file
, "+");
18355 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
18357 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
18360 assemble_name (file
, toc_label_name
);
18362 else if (TARGET_ELF
)
18363 fputs ("@toc", file
);
18367 case UNSPEC_MACHOPIC_OFFSET
:
18368 output_addr_const (file
, XVECEXP (x
, 0, 0));
18370 machopic_output_function_base_name (file
);
18377 /* Target hook for assembling integer objects. The PowerPC version has
18378 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
18379 is defined. It also needs to handle DI-mode objects on 64-bit
18383 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
18385 #ifdef RELOCATABLE_NEEDS_FIXUP
18386 /* Special handling for SI values. */
18387 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
18389 static int recurse
= 0;
18391 /* For -mrelocatable, we mark all addresses that need to be fixed up in
18392 the .fixup section. Since the TOC section is already relocated, we
18393 don't need to mark it here. We used to skip the text section, but it
18394 should never be valid for relocated addresses to be placed in the text
18396 if (TARGET_RELOCATABLE
18397 && in_section
!= toc_section
18399 && GET_CODE (x
) != CONST_INT
18400 && GET_CODE (x
) != CONST_DOUBLE
18406 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
18408 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
18409 fprintf (asm_out_file
, "\t.long\t(");
18410 output_addr_const (asm_out_file
, x
);
18411 fprintf (asm_out_file
, ")@fixup\n");
18412 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
18413 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
18414 fprintf (asm_out_file
, "\t.long\t");
18415 assemble_name (asm_out_file
, buf
);
18416 fprintf (asm_out_file
, "\n\t.previous\n");
18420 /* Remove initial .'s to turn a -mcall-aixdesc function
18421 address into the address of the descriptor, not the function
18423 else if (GET_CODE (x
) == SYMBOL_REF
18424 && XSTR (x
, 0)[0] == '.'
18425 && DEFAULT_ABI
== ABI_AIX
)
18427 const char *name
= XSTR (x
, 0);
18428 while (*name
== '.')
18431 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
18435 #endif /* RELOCATABLE_NEEDS_FIXUP */
18436 return default_assemble_integer (x
, size
, aligned_p
);
18439 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
18440 /* Emit an assembler directive to set symbol visibility for DECL to
18441 VISIBILITY_TYPE. */
18444 rs6000_assemble_visibility (tree decl
, int vis
)
18449 /* Functions need to have their entry point symbol visibility set as
18450 well as their descriptor symbol visibility. */
18451 if (DEFAULT_ABI
== ABI_AIX
18453 && TREE_CODE (decl
) == FUNCTION_DECL
)
18455 static const char * const visibility_types
[] = {
18456 NULL
, "internal", "hidden", "protected"
18459 const char *name
, *type
;
18461 name
= ((* targetm
.strip_name_encoding
)
18462 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
18463 type
= visibility_types
[vis
];
18465 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
18466 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
18469 default_assemble_visibility (decl
, vis
);
18474 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
18476 /* Reversal of FP compares takes care -- an ordered compare
18477 becomes an unordered compare and vice versa. */
18478 if (mode
== CCFPmode
18479 && (!flag_finite_math_only
18480 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
18481 || code
== UNEQ
|| code
== LTGT
))
18482 return reverse_condition_maybe_unordered (code
);
18484 return reverse_condition (code
);
18487 /* Generate a compare for CODE. Return a brand-new rtx that
18488 represents the result of the compare. */
18491 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
18493 enum machine_mode comp_mode
;
18494 rtx compare_result
;
18495 enum rtx_code code
= GET_CODE (cmp
);
18496 rtx op0
= XEXP (cmp
, 0);
18497 rtx op1
= XEXP (cmp
, 1);
18499 if (FLOAT_MODE_P (mode
))
18500 comp_mode
= CCFPmode
;
18501 else if (code
== GTU
|| code
== LTU
18502 || code
== GEU
|| code
== LEU
)
18503 comp_mode
= CCUNSmode
;
18504 else if ((code
== EQ
|| code
== NE
)
18505 && unsigned_reg_p (op0
)
18506 && (unsigned_reg_p (op1
)
18507 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
18508 /* These are unsigned values, perhaps there will be a later
18509 ordering compare that can be shared with this one. */
18510 comp_mode
= CCUNSmode
;
18512 comp_mode
= CCmode
;
18514 /* If we have an unsigned compare, make sure we don't have a signed value as
18516 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
18517 && INTVAL (op1
) < 0)
18519 op0
= copy_rtx_if_shared (op0
);
18520 op1
= force_reg (GET_MODE (op0
), op1
);
18521 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
18524 /* First, the compare. */
18525 compare_result
= gen_reg_rtx (comp_mode
);
18527 /* E500 FP compare instructions on the GPRs. Yuck! */
18528 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18529 && FLOAT_MODE_P (mode
))
18531 rtx cmp
, or_result
, compare_result2
;
18532 enum machine_mode op_mode
= GET_MODE (op0
);
18535 if (op_mode
== VOIDmode
)
18536 op_mode
= GET_MODE (op1
);
18538 /* First reverse the condition codes that aren't directly supported. */
18546 code
= reverse_condition_maybe_unordered (code
);
18559 gcc_unreachable ();
18562 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
18563 This explains the following mess. */
18571 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18572 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
18573 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
18577 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18578 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
18579 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
18583 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18584 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
18585 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
18589 gcc_unreachable ();
18598 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18599 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
18600 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
18604 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18605 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
18606 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
18610 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18611 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
18612 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
18616 gcc_unreachable ();
18625 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18626 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
18627 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
18631 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18632 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
18633 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
18637 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18638 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
18639 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
18643 gcc_unreachable ();
18648 gcc_unreachable ();
18651 /* Synthesize LE and GE from LT/GT || EQ. */
18652 if (code
== LE
|| code
== GE
)
18656 compare_result2
= gen_reg_rtx (CCFPmode
);
18662 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18663 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
18664 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
18668 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18669 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
18670 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
18674 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18675 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
18676 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
18680 gcc_unreachable ();
18685 /* OR them together. */
18686 or_result
= gen_reg_rtx (CCFPmode
);
18687 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
18689 compare_result
= or_result
;
18692 code
= reverse_p
? NE
: EQ
;
18698 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
18699 CLOBBERs to match cmptf_internal2 pattern. */
18700 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
18701 && GET_MODE (op0
) == TFmode
18702 && !TARGET_IEEEQUAD
18703 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
18704 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
18706 gen_rtx_SET (VOIDmode
,
18708 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
18709 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18710 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18711 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18712 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18713 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18714 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18715 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18716 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18717 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
18718 else if (GET_CODE (op1
) == UNSPEC
18719 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
18721 rtx op1b
= XVECEXP (op1
, 0, 0);
18722 comp_mode
= CCEQmode
;
18723 compare_result
= gen_reg_rtx (CCEQmode
);
18725 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
18727 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
18730 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
18731 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
18734 /* Some kinds of FP comparisons need an OR operation;
18735 under flag_finite_math_only we don't bother. */
18736 if (FLOAT_MODE_P (mode
)
18737 && !flag_finite_math_only
18738 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
18739 && (code
== LE
|| code
== GE
18740 || code
== UNEQ
|| code
== LTGT
18741 || code
== UNGT
|| code
== UNLT
))
18743 enum rtx_code or1
, or2
;
18744 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
18745 rtx or_result
= gen_reg_rtx (CCEQmode
);
18749 case LE
: or1
= LT
; or2
= EQ
; break;
18750 case GE
: or1
= GT
; or2
= EQ
; break;
18751 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
18752 case LTGT
: or1
= LT
; or2
= GT
; break;
18753 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
18754 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
18755 default: gcc_unreachable ();
18757 validate_condition_mode (or1
, comp_mode
);
18758 validate_condition_mode (or2
, comp_mode
);
18759 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
18760 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
18761 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
18762 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
18764 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
18766 compare_result
= or_result
;
18770 validate_condition_mode (code
, GET_MODE (compare_result
));
18772 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
18776 /* Emit the RTL for an sISEL pattern. */
18779 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
18781 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
18785 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
18788 enum machine_mode op_mode
;
18789 enum rtx_code cond_code
;
18790 rtx result
= operands
[0];
18792 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
18794 rs6000_emit_sISEL (mode
, operands
);
18798 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
18799 cond_code
= GET_CODE (condition_rtx
);
18801 if (FLOAT_MODE_P (mode
)
18802 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18806 PUT_MODE (condition_rtx
, SImode
);
18807 t
= XEXP (condition_rtx
, 0);
18809 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
18811 if (cond_code
== NE
)
18812 emit_insn (gen_e500_flip_gt_bit (t
, t
));
18814 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
18818 if (cond_code
== NE
18819 || cond_code
== GE
|| cond_code
== LE
18820 || cond_code
== GEU
|| cond_code
== LEU
18821 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
18823 rtx not_result
= gen_reg_rtx (CCEQmode
);
18824 rtx not_op
, rev_cond_rtx
;
18825 enum machine_mode cc_mode
;
18827 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
18829 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
18830 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
18831 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
18832 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
18833 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
18836 op_mode
= GET_MODE (XEXP (operands
[1], 0));
18837 if (op_mode
== VOIDmode
)
18838 op_mode
= GET_MODE (XEXP (operands
[1], 1));
18840 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
18842 PUT_MODE (condition_rtx
, DImode
);
18843 convert_move (result
, condition_rtx
, 0);
18847 PUT_MODE (condition_rtx
, SImode
);
18848 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
18852 /* Emit a branch of kind CODE to location LOC. */
18855 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
18857 rtx condition_rtx
, loc_ref
;
18859 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
18860 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
18861 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
18862 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
18863 loc_ref
, pc_rtx
)));
18866 /* Return the string to output a conditional branch to LABEL, which is
18867 the operand template of the label, or NULL if the branch is really a
18868 conditional return.
18870 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
18871 condition code register and its mode specifies what kind of
18872 comparison we made.
18874 REVERSED is nonzero if we should reverse the sense of the comparison.
18876 INSN is the insn. */
18879 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
18881 static char string
[64];
18882 enum rtx_code code
= GET_CODE (op
);
18883 rtx cc_reg
= XEXP (op
, 0);
18884 enum machine_mode mode
= GET_MODE (cc_reg
);
18885 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
18886 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
18887 int really_reversed
= reversed
^ need_longbranch
;
18893 validate_condition_mode (code
, mode
);
18895 /* Work out which way this really branches. We could use
18896 reverse_condition_maybe_unordered here always but this
18897 makes the resulting assembler clearer. */
18898 if (really_reversed
)
18900 /* Reversal of FP compares takes care -- an ordered compare
18901 becomes an unordered compare and vice versa. */
18902 if (mode
== CCFPmode
)
18903 code
= reverse_condition_maybe_unordered (code
);
18905 code
= reverse_condition (code
);
18908 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
18910 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
18915 /* Opposite of GT. */
18924 gcc_unreachable ();
18930 /* Not all of these are actually distinct opcodes, but
18931 we distinguish them for clarity of the resulting assembler. */
18932 case NE
: case LTGT
:
18933 ccode
= "ne"; break;
18934 case EQ
: case UNEQ
:
18935 ccode
= "eq"; break;
18937 ccode
= "ge"; break;
18938 case GT
: case GTU
: case UNGT
:
18939 ccode
= "gt"; break;
18941 ccode
= "le"; break;
18942 case LT
: case LTU
: case UNLT
:
18943 ccode
= "lt"; break;
18944 case UNORDERED
: ccode
= "un"; break;
18945 case ORDERED
: ccode
= "nu"; break;
18946 case UNGE
: ccode
= "nl"; break;
18947 case UNLE
: ccode
= "ng"; break;
18949 gcc_unreachable ();
18952 /* Maybe we have a guess as to how likely the branch is. */
18954 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
18955 if (note
!= NULL_RTX
)
18957 /* PROB is the difference from 50%. */
18958 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
18960 /* Only hint for highly probable/improbable branches on newer
18961 cpus as static prediction overrides processor dynamic
18962 prediction. For older cpus we may as well always hint, but
18963 assume not taken for branches that are very close to 50% as a
18964 mispredicted taken branch is more expensive than a
18965 mispredicted not-taken branch. */
18966 if (rs6000_always_hint
18967 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
18968 && br_prob_note_reliable_p (note
)))
18970 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
18971 && ((prob
> 0) ^ need_longbranch
))
18979 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
18981 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
18983 /* We need to escape any '%' characters in the reg_names string.
18984 Assume they'd only be the first character.... */
18985 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
18987 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
18991 /* If the branch distance was too far, we may have to use an
18992 unconditional branch to go the distance. */
18993 if (need_longbranch
)
18994 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
18996 s
+= sprintf (s
, ",%s", label
);
19002 /* Return the string to flip the GT bit on a CR. */
19004 output_e500_flip_gt_bit (rtx dst
, rtx src
)
19006 static char string
[64];
19009 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
19010 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
19013 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
19014 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
19016 sprintf (string
, "crnot %d,%d", a
, b
);
19020 /* Return insn for VSX or Altivec comparisons. */
19023 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
19026 enum machine_mode mode
= GET_MODE (op0
);
19034 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
19044 mask
= gen_reg_rtx (mode
);
19045 emit_insn (gen_rtx_SET (VOIDmode
,
19047 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19054 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
19055 DMODE is expected destination mode. This is a recursive function. */
19058 rs6000_emit_vector_compare (enum rtx_code rcode
,
19060 enum machine_mode dmode
)
19063 bool swap_operands
= false;
19064 bool try_again
= false;
19066 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
19067 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
19069 /* See if the comparison works as is. */
19070 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
19078 swap_operands
= true;
19083 swap_operands
= true;
19091 /* Invert condition and try again.
19092 e.g., A != B becomes ~(A==B). */
19094 enum rtx_code rev_code
;
19095 enum insn_code nor_code
;
19098 rev_code
= reverse_condition_maybe_unordered (rcode
);
19099 if (rev_code
== UNKNOWN
)
19102 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
19103 if (nor_code
== CODE_FOR_nothing
)
19106 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
19110 mask
= gen_reg_rtx (dmode
);
19111 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
19119 /* Try GT/GTU/LT/LTU OR EQ */
19122 enum insn_code ior_code
;
19123 enum rtx_code new_code
;
19144 gcc_unreachable ();
19147 ior_code
= optab_handler (ior_optab
, dmode
);
19148 if (ior_code
== CODE_FOR_nothing
)
19151 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
19155 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
19159 mask
= gen_reg_rtx (dmode
);
19160 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
19178 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
19183 /* You only get two chances. */
19187 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
19188 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
19189 operands for the relation operation COND. */
19192 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
19193 rtx cond
, rtx cc_op0
, rtx cc_op1
)
19195 enum machine_mode dest_mode
= GET_MODE (dest
);
19196 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
19197 enum rtx_code rcode
= GET_CODE (cond
);
19198 enum machine_mode cc_mode
= CCmode
;
19202 bool invert_move
= false;
19204 if (VECTOR_UNIT_NONE_P (dest_mode
))
19207 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
19208 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
19212 /* Swap operands if we can, and fall back to doing the operation as
19213 specified, and doing a NOR to invert the test. */
19219 /* Invert condition and try again.
19220 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
19221 invert_move
= true;
19222 rcode
= reverse_condition_maybe_unordered (rcode
);
19223 if (rcode
== UNKNOWN
)
19227 /* Mark unsigned tests with CCUNSmode. */
19232 cc_mode
= CCUNSmode
;
19239 /* Get the vector mask for the given relational operations. */
19240 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
19248 op_true
= op_false
;
19252 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
19253 CONST0_RTX (dest_mode
));
19254 emit_insn (gen_rtx_SET (VOIDmode
,
19256 gen_rtx_IF_THEN_ELSE (dest_mode
,
19263 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
19264 operands of the last comparison is nonzero/true, FALSE_COND if it
19265 is zero/false. Return 0 if the hardware has no such operation. */
19268 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
19270 enum rtx_code code
= GET_CODE (op
);
19271 rtx op0
= XEXP (op
, 0);
19272 rtx op1
= XEXP (op
, 1);
19273 REAL_VALUE_TYPE c1
;
19274 enum machine_mode compare_mode
= GET_MODE (op0
);
19275 enum machine_mode result_mode
= GET_MODE (dest
);
19277 bool is_against_zero
;
19279 /* These modes should always match. */
19280 if (GET_MODE (op1
) != compare_mode
19281 /* In the isel case however, we can use a compare immediate, so
19282 op1 may be a small constant. */
19283 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
19285 if (GET_MODE (true_cond
) != result_mode
)
19287 if (GET_MODE (false_cond
) != result_mode
)
19290 /* Don't allow using floating point comparisons for integer results for
19292 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
19295 /* First, work out if the hardware can do this at all, or
19296 if it's too slow.... */
19297 if (!FLOAT_MODE_P (compare_mode
))
19300 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
19303 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
19304 && SCALAR_FLOAT_MODE_P (compare_mode
))
19307 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
19309 /* A floating-point subtract might overflow, underflow, or produce
19310 an inexact result, thus changing the floating-point flags, so it
19311 can't be generated if we care about that. It's safe if one side
19312 of the construct is zero, since then no subtract will be
19314 if (SCALAR_FLOAT_MODE_P (compare_mode
)
19315 && flag_trapping_math
&& ! is_against_zero
)
19318 /* Eliminate half of the comparisons by switching operands, this
19319 makes the remaining code simpler. */
19320 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
19321 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
19323 code
= reverse_condition_maybe_unordered (code
);
19325 true_cond
= false_cond
;
19329 /* UNEQ and LTGT take four instructions for a comparison with zero,
19330 it'll probably be faster to use a branch here too. */
19331 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
19334 if (GET_CODE (op1
) == CONST_DOUBLE
)
19335 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
19337 /* We're going to try to implement comparisons by performing
19338 a subtract, then comparing against zero. Unfortunately,
19339 Inf - Inf is NaN which is not zero, and so if we don't
19340 know that the operand is finite and the comparison
19341 would treat EQ different to UNORDERED, we can't do it. */
19342 if (HONOR_INFINITIES (compare_mode
)
19343 && code
!= GT
&& code
!= UNGE
19344 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
19345 /* Constructs of the form (a OP b ? a : b) are safe. */
19346 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
19347 || (! rtx_equal_p (op0
, true_cond
)
19348 && ! rtx_equal_p (op1
, true_cond
))))
19351 /* At this point we know we can use fsel. */
19353 /* Reduce the comparison to a comparison against zero. */
19354 if (! is_against_zero
)
19356 temp
= gen_reg_rtx (compare_mode
);
19357 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19358 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
19360 op1
= CONST0_RTX (compare_mode
);
19363 /* If we don't care about NaNs we can reduce some of the comparisons
19364 down to faster ones. */
19365 if (! HONOR_NANS (compare_mode
))
19371 true_cond
= false_cond
;
19384 /* Now, reduce everything down to a GE. */
19391 temp
= gen_reg_rtx (compare_mode
);
19392 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19397 temp
= gen_reg_rtx (compare_mode
);
19398 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
19403 temp
= gen_reg_rtx (compare_mode
);
19404 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19405 gen_rtx_NEG (compare_mode
,
19406 gen_rtx_ABS (compare_mode
, op0
))));
19411 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
19412 temp
= gen_reg_rtx (result_mode
);
19413 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19414 gen_rtx_IF_THEN_ELSE (result_mode
,
19415 gen_rtx_GE (VOIDmode
,
19417 true_cond
, false_cond
)));
19418 false_cond
= true_cond
;
19421 temp
= gen_reg_rtx (compare_mode
);
19422 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19427 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
19428 temp
= gen_reg_rtx (result_mode
);
19429 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19430 gen_rtx_IF_THEN_ELSE (result_mode
,
19431 gen_rtx_GE (VOIDmode
,
19433 true_cond
, false_cond
)));
19434 true_cond
= false_cond
;
19437 temp
= gen_reg_rtx (compare_mode
);
19438 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19443 gcc_unreachable ();
19446 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
19447 gen_rtx_IF_THEN_ELSE (result_mode
,
19448 gen_rtx_GE (VOIDmode
,
19450 true_cond
, false_cond
)));
19454 /* Same as above, but for ints (isel). */
19457 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
19459 rtx condition_rtx
, cr
;
19460 enum machine_mode mode
= GET_MODE (dest
);
19461 enum rtx_code cond_code
;
19462 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
19465 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
19468 /* We still have to do the compare, because isel doesn't do a
19469 compare, it just looks at the CRx bits set by a previous compare
19471 condition_rtx
= rs6000_generate_compare (op
, mode
);
19472 cond_code
= GET_CODE (condition_rtx
);
19473 cr
= XEXP (condition_rtx
, 0);
19474 signedp
= GET_MODE (cr
) == CCmode
;
19476 isel_func
= (mode
== SImode
19477 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
19478 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
19482 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
19483 /* isel handles these directly. */
19487 /* We need to swap the sense of the comparison. */
19490 true_cond
= false_cond
;
19492 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
19497 false_cond
= force_reg (mode
, false_cond
);
19498 if (true_cond
!= const0_rtx
)
19499 true_cond
= force_reg (mode
, true_cond
);
19501 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
19507 output_isel (rtx
*operands
)
19509 enum rtx_code code
;
19511 code
= GET_CODE (operands
[1]);
19513 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
19515 gcc_assert (GET_CODE (operands
[2]) == REG
19516 && GET_CODE (operands
[3]) == REG
);
19517 PUT_CODE (operands
[1], reverse_condition (code
));
19518 return "isel %0,%3,%2,%j1";
19521 return "isel %0,%2,%3,%j1";
19525 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
19527 enum machine_mode mode
= GET_MODE (op0
);
19531 /* VSX/altivec have direct min/max insns. */
19532 if ((code
== SMAX
|| code
== SMIN
)
19533 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
19534 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
19536 emit_insn (gen_rtx_SET (VOIDmode
,
19538 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19542 if (code
== SMAX
|| code
== SMIN
)
19547 if (code
== SMAX
|| code
== UMAX
)
19548 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19549 op0
, op1
, mode
, 0);
19551 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19552 op1
, op0
, mode
, 0);
19553 gcc_assert (target
);
19554 if (target
!= dest
)
19555 emit_move_insn (dest
, target
);
19558 /* A subroutine of the atomic operation splitters. Jump to LABEL if
19559 COND is true. Mark the jump as unlikely to be taken. */
19562 emit_unlikely_jump (rtx cond
, rtx label
)
19564 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
19567 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
19568 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
19569 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
19572 /* A subroutine of the atomic operation splitters. Emit a load-locked
19573 instruction in MODE. For QI/HImode, possibly use a pattern than includes
19574 the zero_extend operation. */
19577 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
19579 rtx (*fn
) (rtx
, rtx
) = NULL
;
19584 fn
= gen_load_lockedqi
;
19587 fn
= gen_load_lockedhi
;
19590 if (GET_MODE (mem
) == QImode
)
19591 fn
= gen_load_lockedqi_si
;
19592 else if (GET_MODE (mem
) == HImode
)
19593 fn
= gen_load_lockedhi_si
;
19595 fn
= gen_load_lockedsi
;
19598 fn
= gen_load_lockeddi
;
19601 fn
= gen_load_lockedti
;
19604 gcc_unreachable ();
19606 emit_insn (fn (reg
, mem
));
19609 /* A subroutine of the atomic operation splitters. Emit a store-conditional
19610 instruction in MODE. */
19613 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
19615 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
19620 fn
= gen_store_conditionalqi
;
19623 fn
= gen_store_conditionalhi
;
19626 fn
= gen_store_conditionalsi
;
19629 fn
= gen_store_conditionaldi
;
19632 fn
= gen_store_conditionalti
;
19635 gcc_unreachable ();
19638 /* Emit sync before stwcx. to address PPC405 Erratum. */
19639 if (PPC405_ERRATUM77
)
19640 emit_insn (gen_hwsync ());
19642 emit_insn (fn (res
, mem
, val
));
19645 /* Expand barriers before and after a load_locked/store_cond sequence. */
19648 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
19650 rtx addr
= XEXP (mem
, 0);
19651 int strict_p
= (reload_in_progress
|| reload_completed
);
19653 if (!legitimate_indirect_address_p (addr
, strict_p
)
19654 && !legitimate_indexed_address_p (addr
, strict_p
))
19656 addr
= force_reg (Pmode
, addr
);
19657 mem
= replace_equiv_address_nv (mem
, addr
);
19662 case MEMMODEL_RELAXED
:
19663 case MEMMODEL_CONSUME
:
19664 case MEMMODEL_ACQUIRE
:
19666 case MEMMODEL_RELEASE
:
19667 case MEMMODEL_ACQ_REL
:
19668 emit_insn (gen_lwsync ());
19670 case MEMMODEL_SEQ_CST
:
19671 emit_insn (gen_hwsync ());
19674 gcc_unreachable ();
19680 rs6000_post_atomic_barrier (enum memmodel model
)
19684 case MEMMODEL_RELAXED
:
19685 case MEMMODEL_CONSUME
:
19686 case MEMMODEL_RELEASE
:
19688 case MEMMODEL_ACQUIRE
:
19689 case MEMMODEL_ACQ_REL
:
19690 case MEMMODEL_SEQ_CST
:
19691 emit_insn (gen_isync ());
19694 gcc_unreachable ();
19698 /* A subroutine of the various atomic expanders. For sub-word operations,
19699 we must adjust things to operate on SImode. Given the original MEM,
19700 return a new aligned memory. Also build and return the quantities by
19701 which to shift and mask. */
19704 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
19706 rtx addr
, align
, shift
, mask
, mem
;
19707 HOST_WIDE_INT shift_mask
;
19708 enum machine_mode mode
= GET_MODE (orig_mem
);
19710 /* For smaller modes, we have to implement this via SImode. */
19711 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
19713 addr
= XEXP (orig_mem
, 0);
19714 addr
= force_reg (GET_MODE (addr
), addr
);
19716 /* Aligned memory containing subword. Generate a new memory. We
19717 do not want any of the existing MEM_ATTR data, as we're now
19718 accessing memory outside the original object. */
19719 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
19720 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19721 mem
= gen_rtx_MEM (SImode
, align
);
19722 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
19723 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
19724 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
19726 /* Shift amount for subword relative to aligned word. */
19727 shift
= gen_reg_rtx (SImode
);
19728 addr
= gen_lowpart (SImode
, addr
);
19729 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
19730 if (WORDS_BIG_ENDIAN
)
19731 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
19732 shift
, 1, OPTAB_LIB_WIDEN
);
19735 /* Mask for insertion. */
19736 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
19737 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19743 /* A subroutine of the various atomic expanders. For sub-word operands,
19744 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
19747 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
19751 x
= gen_reg_rtx (SImode
);
19752 emit_insn (gen_rtx_SET (VOIDmode
, x
,
19753 gen_rtx_AND (SImode
,
19754 gen_rtx_NOT (SImode
, mask
),
19757 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
19762 /* A subroutine of the various atomic expanders. For sub-word operands,
19763 extract WIDE to NARROW via SHIFT. */
19766 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
19768 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
19769 wide
, 1, OPTAB_LIB_WIDEN
);
19770 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
19773 /* Expand an atomic compare and swap operation. */
19776 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
19778 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
19779 rtx label1
, label2
, x
, mask
, shift
;
19780 enum machine_mode mode
, orig_mode
;
19781 enum memmodel mod_s
, mod_f
;
19784 boolval
= operands
[0];
19785 retval
= operands
[1];
19787 oldval
= operands
[3];
19788 newval
= operands
[4];
19789 is_weak
= (INTVAL (operands
[5]) != 0);
19790 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
19791 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
19792 orig_mode
= mode
= GET_MODE (mem
);
19794 mask
= shift
= NULL_RTX
;
19795 if (mode
== QImode
|| mode
== HImode
)
19797 /* Before power8, we didn't have access to lbarx/lharx, so generate a
19798 lwarx and shift/mask operations. With power8, we need to do the
19799 comparison in SImode, but the store is still done in QI/HImode. */
19800 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
19802 if (!TARGET_SYNC_HI_QI
)
19804 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19806 /* Shift and mask OLDVAL into position with the word. */
19807 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
19808 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19810 /* Shift and mask NEWVAL into position within the word. */
19811 newval
= convert_modes (SImode
, mode
, newval
, 1);
19812 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
19813 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19816 /* Prepare to adjust the return value. */
19817 retval
= gen_reg_rtx (SImode
);
19820 else if (reg_overlap_mentioned_p (retval
, oldval
))
19821 oldval
= copy_to_reg (oldval
);
19823 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
19828 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19829 emit_label (XEXP (label1
, 0));
19831 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19833 emit_load_locked (mode
, retval
, mem
);
19838 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
19839 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19842 cond
= gen_reg_rtx (CCmode
);
19843 /* If we have TImode, synthesize a comparison. */
19844 if (mode
!= TImode
)
19845 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
19848 rtx xor1_result
= gen_reg_rtx (DImode
);
19849 rtx xor2_result
= gen_reg_rtx (DImode
);
19850 rtx or_result
= gen_reg_rtx (DImode
);
19851 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
19852 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
19853 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
19854 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
19856 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
19857 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
19858 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
19859 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
19862 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
19864 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19865 emit_unlikely_jump (x
, label2
);
19869 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
19871 emit_store_conditional (orig_mode
, cond
, mem
, x
);
19875 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19876 emit_unlikely_jump (x
, label1
);
19879 if (mod_f
!= MEMMODEL_RELAXED
)
19880 emit_label (XEXP (label2
, 0));
19882 rs6000_post_atomic_barrier (mod_s
);
19884 if (mod_f
== MEMMODEL_RELAXED
)
19885 emit_label (XEXP (label2
, 0));
19888 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
19889 else if (mode
!= GET_MODE (operands
[1]))
19890 convert_move (operands
[1], retval
, 1);
19892 /* In all cases, CR0 contains EQ on success, and NE on failure. */
19893 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
19894 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
19897 /* Expand an atomic exchange operation. */
19900 rs6000_expand_atomic_exchange (rtx operands
[])
19902 rtx retval
, mem
, val
, cond
;
19903 enum machine_mode mode
;
19904 enum memmodel model
;
19905 rtx label
, x
, mask
, shift
;
19907 retval
= operands
[0];
19910 model
= (enum memmodel
) INTVAL (operands
[3]);
19911 mode
= GET_MODE (mem
);
19913 mask
= shift
= NULL_RTX
;
19914 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
19916 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19918 /* Shift and mask VAL into position with the word. */
19919 val
= convert_modes (SImode
, mode
, val
, 1);
19920 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
19921 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19923 /* Prepare to adjust the return value. */
19924 retval
= gen_reg_rtx (SImode
);
19928 mem
= rs6000_pre_atomic_barrier (mem
, model
);
19930 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19931 emit_label (XEXP (label
, 0));
19933 emit_load_locked (mode
, retval
, mem
);
19937 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
19939 cond
= gen_reg_rtx (CCmode
);
19940 emit_store_conditional (mode
, cond
, mem
, x
);
19942 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19943 emit_unlikely_jump (x
, label
);
19945 rs6000_post_atomic_barrier (model
);
19948 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
19951 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
19952 to perform. MEM is the memory on which to operate. VAL is the second
19953 operand of the binary operator. BEFORE and AFTER are optional locations to
19954 return the value of MEM either before of after the operation. MODEL_RTX
19955 is a CONST_INT containing the memory model to use. */
19958 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
19959 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
19961 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
19962 enum machine_mode mode
= GET_MODE (mem
);
19963 enum machine_mode store_mode
= mode
;
19964 rtx label
, x
, cond
, mask
, shift
;
19965 rtx before
= orig_before
, after
= orig_after
;
19967 mask
= shift
= NULL_RTX
;
19968 /* On power8, we want to use SImode for the operation. On previous systems,
19969 use the operation in a subword and shift/mask to get the proper byte or
19971 if (mode
== QImode
|| mode
== HImode
)
19973 if (TARGET_SYNC_HI_QI
)
19975 val
= convert_modes (SImode
, mode
, val
, 1);
19977 /* Prepare to adjust the return value. */
19978 before
= gen_reg_rtx (SImode
);
19980 after
= gen_reg_rtx (SImode
);
19985 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19987 /* Shift and mask VAL into position with the word. */
19988 val
= convert_modes (SImode
, mode
, val
, 1);
19989 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
19990 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19996 /* We've already zero-extended VAL. That is sufficient to
19997 make certain that it does not affect other bits. */
20002 /* If we make certain that all of the other bits in VAL are
20003 set, that will be sufficient to not affect other bits. */
20004 x
= gen_rtx_NOT (SImode
, mask
);
20005 x
= gen_rtx_IOR (SImode
, x
, val
);
20006 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
20013 /* These will all affect bits outside the field and need
20014 adjustment via MASK within the loop. */
20018 gcc_unreachable ();
20021 /* Prepare to adjust the return value. */
20022 before
= gen_reg_rtx (SImode
);
20024 after
= gen_reg_rtx (SImode
);
20025 store_mode
= mode
= SImode
;
20029 mem
= rs6000_pre_atomic_barrier (mem
, model
);
20031 label
= gen_label_rtx ();
20032 emit_label (label
);
20033 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
20035 if (before
== NULL_RTX
)
20036 before
= gen_reg_rtx (mode
);
20038 emit_load_locked (mode
, before
, mem
);
20042 x
= expand_simple_binop (mode
, AND
, before
, val
,
20043 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20044 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
20048 after
= expand_simple_binop (mode
, code
, before
, val
,
20049 after
, 1, OPTAB_LIB_WIDEN
);
20055 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
20056 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20057 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
20059 else if (store_mode
!= mode
)
20060 x
= convert_modes (store_mode
, mode
, x
, 1);
20062 cond
= gen_reg_rtx (CCmode
);
20063 emit_store_conditional (store_mode
, cond
, mem
, x
);
20065 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20066 emit_unlikely_jump (x
, label
);
20068 rs6000_post_atomic_barrier (model
);
20072 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
20073 then do the calcuations in a SImode register. */
20075 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
20077 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
20079 else if (store_mode
!= mode
)
20081 /* QImode/HImode on machines with lbarx/lharx where we do the native
20082 operation and then do the calcuations in a SImode register. */
20084 convert_move (orig_before
, before
, 1);
20086 convert_move (orig_after
, after
, 1);
20088 else if (orig_after
&& after
!= orig_after
)
20089 emit_move_insn (orig_after
, after
);
20092 /* Emit instructions to move SRC to DST. Called by splitters for
20093 multi-register moves. It will emit at most one instruction for
20094 each register that is accessed; that is, it won't emit li/lis pairs
20095 (or equivalent for 64-bit code). One of SRC or DST must be a hard
20099 rs6000_split_multireg_move (rtx dst
, rtx src
)
20101 /* The register number of the first register being moved. */
20103 /* The mode that is to be moved. */
20104 enum machine_mode mode
;
20105 /* The mode that the move is being done in, and its size. */
20106 enum machine_mode reg_mode
;
20108 /* The number of registers that will be moved. */
20111 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
20112 mode
= GET_MODE (dst
);
20113 nregs
= hard_regno_nregs
[reg
][mode
];
20114 if (FP_REGNO_P (reg
))
20115 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
20116 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
20117 else if (ALTIVEC_REGNO_P (reg
))
20118 reg_mode
= V16QImode
;
20119 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
20122 reg_mode
= word_mode
;
20123 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
20125 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
20127 /* TDmode residing in FP registers is special, since the ISA requires that
20128 the lower-numbered word of a register pair is always the most significant
20129 word, even in little-endian mode. This does not match the usual subreg
20130 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
20131 the appropriate constituent registers "by hand" in little-endian mode.
20133 Note we do not need to check for destructive overlap here since TDmode
20134 can only reside in even/odd register pairs. */
20135 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
20140 for (i
= 0; i
< nregs
; i
++)
20142 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
20143 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
20145 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
20146 i
* reg_mode_size
);
20148 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
20149 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
20151 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
20152 i
* reg_mode_size
);
20154 emit_insn (gen_rtx_SET (VOIDmode
, p_dst
, p_src
));
20160 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
20162 /* Move register range backwards, if we might have destructive
20165 for (i
= nregs
- 1; i
>= 0; i
--)
20166 emit_insn (gen_rtx_SET (VOIDmode
,
20167 simplify_gen_subreg (reg_mode
, dst
, mode
,
20168 i
* reg_mode_size
),
20169 simplify_gen_subreg (reg_mode
, src
, mode
,
20170 i
* reg_mode_size
)));
20176 bool used_update
= false;
20177 rtx restore_basereg
= NULL_RTX
;
20179 if (MEM_P (src
) && INT_REGNO_P (reg
))
20183 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
20184 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
20187 breg
= XEXP (XEXP (src
, 0), 0);
20188 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
20189 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
20190 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
20191 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
20192 src
= replace_equiv_address (src
, breg
);
20194 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
20196 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
20198 rtx basereg
= XEXP (XEXP (src
, 0), 0);
20201 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
20202 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
20203 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
20204 used_update
= true;
20207 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
20208 XEXP (XEXP (src
, 0), 1)));
20209 src
= replace_equiv_address (src
, basereg
);
20213 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
20214 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
20215 src
= replace_equiv_address (src
, basereg
);
20219 breg
= XEXP (src
, 0);
20220 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
20221 breg
= XEXP (breg
, 0);
20223 /* If the base register we are using to address memory is
20224 also a destination reg, then change that register last. */
20226 && REGNO (breg
) >= REGNO (dst
)
20227 && REGNO (breg
) < REGNO (dst
) + nregs
)
20228 j
= REGNO (breg
) - REGNO (dst
);
20230 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
20234 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
20235 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
20238 breg
= XEXP (XEXP (dst
, 0), 0);
20239 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
20240 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
20241 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
20243 /* We have to update the breg before doing the store.
20244 Use store with update, if available. */
20248 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
20249 emit_insn (TARGET_32BIT
20250 ? (TARGET_POWERPC64
20251 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
20252 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
20253 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
20254 used_update
= true;
20257 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
20258 dst
= replace_equiv_address (dst
, breg
);
20260 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
20261 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
20263 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
20265 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
20268 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
20269 emit_insn (gen_rtx_SET (VOIDmode
,
20270 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
20271 used_update
= true;
20274 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
20275 XEXP (XEXP (dst
, 0), 1)));
20276 dst
= replace_equiv_address (dst
, basereg
);
20280 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
20281 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
20282 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
20284 && REG_P (offsetreg
)
20285 && REGNO (basereg
) != REGNO (offsetreg
));
20286 if (REGNO (basereg
) == 0)
20288 rtx tmp
= offsetreg
;
20289 offsetreg
= basereg
;
20292 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
20293 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
20294 dst
= replace_equiv_address (dst
, basereg
);
20297 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
20298 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
20301 for (i
= 0; i
< nregs
; i
++)
20303 /* Calculate index to next subword. */
20308 /* If compiler already emitted move of first word by
20309 store with update, no need to do anything. */
20310 if (j
== 0 && used_update
)
20313 emit_insn (gen_rtx_SET (VOIDmode
,
20314 simplify_gen_subreg (reg_mode
, dst
, mode
,
20315 j
* reg_mode_size
),
20316 simplify_gen_subreg (reg_mode
, src
, mode
,
20317 j
* reg_mode_size
)));
20319 if (restore_basereg
!= NULL_RTX
)
20320 emit_insn (restore_basereg
);
20325 /* This page contains routines that are used to determine what the
20326 function prologue and epilogue code will do and write them out. */
20331 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
20334 /* Return the first fixed-point register that is required to be
20335 saved. 32 if none. */
20338 first_reg_to_save (void)
20342 /* Find lowest numbered live register. */
20343 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
20344 if (save_reg_p (first_reg
))
20347 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
20348 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
20349 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
20350 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
20351 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
20352 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
20356 && crtl
->uses_pic_offset_table
20357 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
20358 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
20364 /* Similar, for FP regs. */
20367 first_fp_reg_to_save (void)
20371 /* Find lowest numbered live register. */
20372 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
20373 if (save_reg_p (first_reg
))
20379 /* Similar, for AltiVec regs. */
20382 first_altivec_reg_to_save (void)
20386 /* Stack frame remains as is unless we are in AltiVec ABI. */
20387 if (! TARGET_ALTIVEC_ABI
)
20388 return LAST_ALTIVEC_REGNO
+ 1;
20390 /* On Darwin, the unwind routines are compiled without
20391 TARGET_ALTIVEC, and use save_world to save/restore the
20392 altivec registers when necessary. */
20393 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
20394 && ! TARGET_ALTIVEC
)
20395 return FIRST_ALTIVEC_REGNO
+ 20;
20397 /* Find lowest numbered live register. */
20398 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20399 if (save_reg_p (i
))
20405 /* Return a 32-bit mask of the AltiVec registers we need to set in
20406 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
20407 the 32-bit word is 0. */
20409 static unsigned int
20410 compute_vrsave_mask (void)
20412 unsigned int i
, mask
= 0;
20414 /* On Darwin, the unwind routines are compiled without
20415 TARGET_ALTIVEC, and use save_world to save/restore the
20416 call-saved altivec registers when necessary. */
20417 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
20418 && ! TARGET_ALTIVEC
)
20421 /* First, find out if we use _any_ altivec registers. */
20422 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20423 if (df_regs_ever_live_p (i
))
20424 mask
|= ALTIVEC_REG_BIT (i
);
20429 /* Next, remove the argument registers from the set. These must
20430 be in the VRSAVE mask set by the caller, so we don't need to add
20431 them in again. More importantly, the mask we compute here is
20432 used to generate CLOBBERs in the set_vrsave insn, and we do not
20433 wish the argument registers to die. */
20434 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
20435 mask
&= ~ALTIVEC_REG_BIT (i
);
20437 /* Similarly, remove the return value from the set. */
20440 diddle_return_value (is_altivec_return_reg
, &yes
);
20442 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
20448 /* For a very restricted set of circumstances, we can cut down the
20449 size of prologues/epilogues by calling our own save/restore-the-world
20453 compute_save_world_info (rs6000_stack_t
*info_ptr
)
20455 info_ptr
->world_save_p
= 1;
20456 info_ptr
->world_save_p
20457 = (WORLD_SAVE_P (info_ptr
)
20458 && DEFAULT_ABI
== ABI_DARWIN
20459 && !cfun
->has_nonlocal_label
20460 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
20461 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
20462 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
20463 && info_ptr
->cr_save_p
);
20465 /* This will not work in conjunction with sibcalls. Make sure there
20466 are none. (This check is expensive, but seldom executed.) */
20467 if (WORLD_SAVE_P (info_ptr
))
20470 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
20471 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
20473 info_ptr
->world_save_p
= 0;
20478 if (WORLD_SAVE_P (info_ptr
))
20480 /* Even if we're not touching VRsave, make sure there's room on the
20481 stack for it, if it looks like we're calling SAVE_WORLD, which
20482 will attempt to save it. */
20483 info_ptr
->vrsave_size
= 4;
20485 /* If we are going to save the world, we need to save the link register too. */
20486 info_ptr
->lr_save_p
= 1;
20488 /* "Save" the VRsave register too if we're saving the world. */
20489 if (info_ptr
->vrsave_mask
== 0)
20490 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
20492 /* Because the Darwin register save/restore routines only handle
20493 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
20495 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
20496 && (info_ptr
->first_altivec_reg_save
20497 >= FIRST_SAVED_ALTIVEC_REGNO
));
20504 is_altivec_return_reg (rtx reg
, void *xyes
)
20506 bool *yes
= (bool *) xyes
;
20507 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
20512 /* Look for user-defined global regs in the range FIRST to LAST-1.
20513 We should not restore these, and so cannot use lmw or out-of-line
20514 restore functions if there are any. We also can't save them
20515 (well, emit frame notes for them), because frame unwinding during
20516 exception handling will restore saved registers. */
20519 global_regs_p (unsigned first
, unsigned last
)
20521 while (first
< last
)
20522 if (global_regs
[first
++])
20527 /* Determine the strategy for savings/restoring registers. */
20530 SAVRES_MULTIPLE
= 0x1,
20531 SAVE_INLINE_FPRS
= 0x2,
20532 SAVE_INLINE_GPRS
= 0x4,
20533 REST_INLINE_FPRS
= 0x8,
20534 REST_INLINE_GPRS
= 0x10,
20535 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
20536 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
20537 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
20538 SAVE_INLINE_VRS
= 0x100,
20539 REST_INLINE_VRS
= 0x200
20543 rs6000_savres_strategy (rs6000_stack_t
*info
,
20544 bool using_static_chain_p
)
20549 if (TARGET_MULTIPLE
20550 && !TARGET_POWERPC64
20551 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
20552 && info
->first_gp_reg_save
< 31
20553 && !global_regs_p (info
->first_gp_reg_save
, 32))
20554 strategy
|= SAVRES_MULTIPLE
;
20556 if (crtl
->calls_eh_return
20557 || cfun
->machine
->ra_need_lr
)
20558 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
20559 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
20560 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20562 if (info
->first_fp_reg_save
== 64
20563 /* The out-of-line FP routines use double-precision stores;
20564 we can't use those routines if we don't have such stores. */
20565 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
20566 || global_regs_p (info
->first_fp_reg_save
, 64))
20567 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20569 if (info
->first_gp_reg_save
== 32
20570 || (!(strategy
& SAVRES_MULTIPLE
)
20571 && global_regs_p (info
->first_gp_reg_save
, 32)))
20572 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20574 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
20575 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
20576 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20578 /* Define cutoff for using out-of-line functions to save registers. */
20579 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
20581 if (!optimize_size
)
20583 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20584 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20585 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20589 /* Prefer out-of-line restore if it will exit. */
20590 if (info
->first_fp_reg_save
> 61)
20591 strategy
|= SAVE_INLINE_FPRS
;
20592 if (info
->first_gp_reg_save
> 29)
20594 if (info
->first_fp_reg_save
== 64)
20595 strategy
|= SAVE_INLINE_GPRS
;
20597 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20599 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
20600 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20603 else if (DEFAULT_ABI
== ABI_DARWIN
)
20605 if (info
->first_fp_reg_save
> 60)
20606 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20607 if (info
->first_gp_reg_save
> 29)
20608 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20609 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20613 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
20614 if (info
->first_fp_reg_save
> 61)
20615 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20616 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20617 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20620 /* Don't bother to try to save things out-of-line if r11 is occupied
20621 by the static chain. It would require too much fiddling and the
20622 static chain is rarely used anyway. FPRs are saved w.r.t the stack
20623 pointer on Darwin, and AIX uses r1 or r12. */
20624 if (using_static_chain_p
20625 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
20626 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
20628 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20630 /* We can only use the out-of-line routines to restore if we've
20631 saved all the registers from first_fp_reg_save in the prologue.
20632 Otherwise, we risk loading garbage. */
20633 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
20637 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
20638 if (!save_reg_p (i
))
20640 strategy
|= REST_INLINE_FPRS
;
20645 /* If we are going to use store multiple, then don't even bother
20646 with the out-of-line routines, since the store-multiple
20647 instruction will always be smaller. */
20648 if ((strategy
& SAVRES_MULTIPLE
))
20649 strategy
|= SAVE_INLINE_GPRS
;
20651 /* info->lr_save_p isn't yet set if the only reason lr needs to be
20652 saved is an out-of-line save or restore. Set up the value for
20653 the next test (excluding out-of-line gpr restore). */
20654 lr_save_p
= (info
->lr_save_p
20655 || !(strategy
& SAVE_INLINE_GPRS
)
20656 || !(strategy
& SAVE_INLINE_FPRS
)
20657 || !(strategy
& SAVE_INLINE_VRS
)
20658 || !(strategy
& REST_INLINE_FPRS
)
20659 || !(strategy
& REST_INLINE_VRS
));
20661 /* The situation is more complicated with load multiple. We'd
20662 prefer to use the out-of-line routines for restores, since the
20663 "exit" out-of-line routines can handle the restore of LR and the
20664 frame teardown. However if doesn't make sense to use the
20665 out-of-line routine if that is the only reason we'd need to save
20666 LR, and we can't use the "exit" out-of-line gpr restore if we
20667 have saved some fprs; In those cases it is advantageous to use
20668 load multiple when available. */
20669 if ((strategy
& SAVRES_MULTIPLE
)
20671 || info
->first_fp_reg_save
!= 64))
20672 strategy
|= REST_INLINE_GPRS
;
20674 /* Saving CR interferes with the exit routines used on the SPE, so
20677 && info
->spe_64bit_regs_used
20678 && info
->cr_save_p
)
20679 strategy
|= REST_INLINE_GPRS
;
20681 /* We can only use load multiple or the out-of-line routines to
20682 restore if we've used store multiple or out-of-line routines
20683 in the prologue, i.e. if we've saved all the registers from
20684 first_gp_reg_save. Otherwise, we risk loading garbage. */
20685 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
20686 == SAVE_INLINE_GPRS
)
20690 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
20691 if (!save_reg_p (i
))
20693 strategy
|= REST_INLINE_GPRS
;
20698 if (TARGET_ELF
&& TARGET_64BIT
)
20700 if (!(strategy
& SAVE_INLINE_FPRS
))
20701 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20702 else if (!(strategy
& SAVE_INLINE_GPRS
)
20703 && info
->first_fp_reg_save
== 64)
20704 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
20706 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
20707 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
20709 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
20710 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20715 /* Calculate the stack information for the current function. This is
20716 complicated by having two separate calling sequences, the AIX calling
20717 sequence and the V.4 calling sequence.
20719 AIX (and Darwin/Mac OS X) stack frames look like:
20721 SP----> +---------------------------------------+
20722 | back chain to caller | 0 0
20723 +---------------------------------------+
20724 | saved CR | 4 8 (8-11)
20725 +---------------------------------------+
20727 +---------------------------------------+
20728 | reserved for compilers | 12 24
20729 +---------------------------------------+
20730 | reserved for binders | 16 32
20731 +---------------------------------------+
20732 | saved TOC pointer | 20 40
20733 +---------------------------------------+
20734 | Parameter save area (P) | 24 48
20735 +---------------------------------------+
20736 | Alloca space (A) | 24+P etc.
20737 +---------------------------------------+
20738 | Local variable space (L) | 24+P+A
20739 +---------------------------------------+
20740 | Float/int conversion temporary (X) | 24+P+A+L
20741 +---------------------------------------+
20742 | Save area for AltiVec registers (W) | 24+P+A+L+X
20743 +---------------------------------------+
20744 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
20745 +---------------------------------------+
20746 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
20747 +---------------------------------------+
20748 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
20749 +---------------------------------------+
20750 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
20751 +---------------------------------------+
20752 old SP->| back chain to caller's caller |
20753 +---------------------------------------+
20755 The required alignment for AIX configurations is two words (i.e., 8
20758 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
20760 SP----> +---------------------------------------+
20761 | Back chain to caller | 0
20762 +---------------------------------------+
20763 | Save area for CR | 8
20764 +---------------------------------------+
20766 +---------------------------------------+
20767 | Saved TOC pointer | 24
20768 +---------------------------------------+
20769 | Parameter save area (P) | 32
20770 +---------------------------------------+
20771 | Alloca space (A) | 32+P
20772 +---------------------------------------+
20773 | Local variable space (L) | 32+P+A
20774 +---------------------------------------+
20775 | Save area for AltiVec registers (W) | 32+P+A+L
20776 +---------------------------------------+
20777 | AltiVec alignment padding (Y) | 32+P+A+L+W
20778 +---------------------------------------+
20779 | Save area for GP registers (G) | 32+P+A+L+W+Y
20780 +---------------------------------------+
20781 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
20782 +---------------------------------------+
20783 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
20784 +---------------------------------------+
20787 V.4 stack frames look like:
20789 SP----> +---------------------------------------+
20790 | back chain to caller | 0
20791 +---------------------------------------+
20792 | caller's saved LR | 4
20793 +---------------------------------------+
20794 | Parameter save area (P) | 8
20795 +---------------------------------------+
20796 | Alloca space (A) | 8+P
20797 +---------------------------------------+
20798 | Varargs save area (V) | 8+P+A
20799 +---------------------------------------+
20800 | Local variable space (L) | 8+P+A+V
20801 +---------------------------------------+
20802 | Float/int conversion temporary (X) | 8+P+A+V+L
20803 +---------------------------------------+
20804 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
20805 +---------------------------------------+
20806 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
20807 +---------------------------------------+
20808 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
20809 +---------------------------------------+
20810 | SPE: area for 64-bit GP registers |
20811 +---------------------------------------+
20812 | SPE alignment padding |
20813 +---------------------------------------+
20814 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
20815 +---------------------------------------+
20816 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
20817 +---------------------------------------+
20818 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
20819 +---------------------------------------+
20820 old SP->| back chain to caller's caller |
20821 +---------------------------------------+
20823 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
20824 given. (But note below and in sysv4.h that we require only 8 and
20825 may round up the size of our stack frame anyways. The historical
20826 reason is early versions of powerpc-linux which didn't properly
20827 align the stack at program startup. A happy side-effect is that
20828 -mno-eabi libraries can be used with -meabi programs.)
20830 The EABI configuration defaults to the V.4 layout. However,
20831 the stack alignment requirements may differ. If -mno-eabi is not
20832 given, the required stack alignment is 8 bytes; if -mno-eabi is
20833 given, the required alignment is 16 bytes. (But see V.4 comment
20836 #ifndef ABI_STACK_BOUNDARY
20837 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
20840 static rs6000_stack_t
*
20841 rs6000_stack_info (void)
20843 rs6000_stack_t
*info_ptr
= &stack_info
;
20844 int reg_size
= TARGET_32BIT
? 4 : 8;
20849 HOST_WIDE_INT non_fixed_size
;
20850 bool using_static_chain_p
;
20852 if (reload_completed
&& info_ptr
->reload_completed
)
20855 memset (info_ptr
, 0, sizeof (*info_ptr
));
20856 info_ptr
->reload_completed
= reload_completed
;
20860 /* Cache value so we don't rescan instruction chain over and over. */
20861 if (cfun
->machine
->insn_chain_scanned_p
== 0)
20862 cfun
->machine
->insn_chain_scanned_p
20863 = spe_func_has_64bit_regs_p () + 1;
20864 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
20867 /* Select which calling sequence. */
20868 info_ptr
->abi
= DEFAULT_ABI
;
20870 /* Calculate which registers need to be saved & save area size. */
20871 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
20872 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
20873 even if it currently looks like we won't. Reload may need it to
20874 get at a constant; if so, it will have already created a constant
20875 pool entry for it. */
20876 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
20877 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
20878 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
20879 && crtl
->uses_const_pool
20880 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
20881 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
20883 first_gp
= info_ptr
->first_gp_reg_save
;
20885 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
20887 /* For the SPE, we have an additional upper 32-bits on each GPR.
20888 Ideally we should save the entire 64-bits only when the upper
20889 half is used in SIMD instructions. Since we only record
20890 registers live (not the size they are used in), this proves
20891 difficult because we'd have to traverse the instruction chain at
20892 the right time, taking reload into account. This is a real pain,
20893 so we opt to save the GPRs in 64-bits always if but one register
20894 gets used in 64-bits. Otherwise, all the registers in the frame
20895 get saved in 32-bits.
20897 So... since when we save all GPRs (except the SP) in 64-bits, the
20898 traditional GP save area will be empty. */
20899 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20900 info_ptr
->gp_size
= 0;
20902 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
20903 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
20905 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
20906 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
20907 - info_ptr
->first_altivec_reg_save
);
20909 /* Does this function call anything? */
20910 info_ptr
->calls_p
= (! crtl
->is_leaf
20911 || cfun
->machine
->ra_needs_full_frame
);
20913 /* Determine if we need to save the condition code registers. */
20914 if (df_regs_ever_live_p (CR2_REGNO
)
20915 || df_regs_ever_live_p (CR3_REGNO
)
20916 || df_regs_ever_live_p (CR4_REGNO
))
20918 info_ptr
->cr_save_p
= 1;
20919 if (DEFAULT_ABI
== ABI_V4
)
20920 info_ptr
->cr_size
= reg_size
;
20923 /* If the current function calls __builtin_eh_return, then we need
20924 to allocate stack space for registers that will hold data for
20925 the exception handler. */
20926 if (crtl
->calls_eh_return
)
20929 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
20932 /* SPE saves EH registers in 64-bits. */
20933 ehrd_size
= i
* (TARGET_SPE_ABI
20934 && info_ptr
->spe_64bit_regs_used
!= 0
20935 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
20940 /* In the ELFv2 ABI, we also need to allocate space for separate
20941 CR field save areas if the function calls __builtin_eh_return. */
20942 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
20944 /* This hard-codes that we have three call-saved CR fields. */
20945 ehcr_size
= 3 * reg_size
;
20946 /* We do *not* use the regular CR save mechanism. */
20947 info_ptr
->cr_save_p
= 0;
20952 /* Determine various sizes. */
20953 info_ptr
->reg_size
= reg_size
;
20954 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
20955 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
20956 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
20957 TARGET_ALTIVEC
? 16 : 8);
20958 if (FRAME_GROWS_DOWNWARD
)
20959 info_ptr
->vars_size
20960 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
20961 + info_ptr
->parm_size
,
20962 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
20963 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
20964 + info_ptr
->parm_size
);
20966 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20967 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
20969 info_ptr
->spe_gp_size
= 0;
20971 if (TARGET_ALTIVEC_ABI
)
20972 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
20974 info_ptr
->vrsave_mask
= 0;
20976 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
20977 info_ptr
->vrsave_size
= 4;
20979 info_ptr
->vrsave_size
= 0;
20981 compute_save_world_info (info_ptr
);
20983 /* Calculate the offsets. */
20984 switch (DEFAULT_ABI
)
20988 gcc_unreachable ();
20993 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
20994 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
20996 if (TARGET_ALTIVEC_ABI
)
20998 info_ptr
->vrsave_save_offset
20999 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
21001 /* Align stack so vector save area is on a quadword boundary.
21002 The padding goes above the vectors. */
21003 if (info_ptr
->altivec_size
!= 0)
21004 info_ptr
->altivec_padding_size
21005 = info_ptr
->vrsave_save_offset
& 0xF;
21007 info_ptr
->altivec_padding_size
= 0;
21009 info_ptr
->altivec_save_offset
21010 = info_ptr
->vrsave_save_offset
21011 - info_ptr
->altivec_padding_size
21012 - info_ptr
->altivec_size
;
21013 gcc_assert (info_ptr
->altivec_size
== 0
21014 || info_ptr
->altivec_save_offset
% 16 == 0);
21016 /* Adjust for AltiVec case. */
21017 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
21020 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
21022 info_ptr
->ehcr_offset
= info_ptr
->ehrd_offset
- ehcr_size
;
21023 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
21024 info_ptr
->lr_save_offset
= 2*reg_size
;
21028 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
21029 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
21030 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
21032 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21034 /* Align stack so SPE GPR save area is aligned on a
21035 double-word boundary. */
21036 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
21037 info_ptr
->spe_padding_size
21038 = 8 - (-info_ptr
->cr_save_offset
% 8);
21040 info_ptr
->spe_padding_size
= 0;
21042 info_ptr
->spe_gp_save_offset
21043 = info_ptr
->cr_save_offset
21044 - info_ptr
->spe_padding_size
21045 - info_ptr
->spe_gp_size
;
21047 /* Adjust for SPE case. */
21048 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
21050 else if (TARGET_ALTIVEC_ABI
)
21052 info_ptr
->vrsave_save_offset
21053 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
21055 /* Align stack so vector save area is on a quadword boundary. */
21056 if (info_ptr
->altivec_size
!= 0)
21057 info_ptr
->altivec_padding_size
21058 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
21060 info_ptr
->altivec_padding_size
= 0;
21062 info_ptr
->altivec_save_offset
21063 = info_ptr
->vrsave_save_offset
21064 - info_ptr
->altivec_padding_size
21065 - info_ptr
->altivec_size
;
21067 /* Adjust for AltiVec case. */
21068 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
21071 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
21072 info_ptr
->ehrd_offset
-= ehrd_size
;
21073 info_ptr
->lr_save_offset
= reg_size
;
21077 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
21078 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
21079 + info_ptr
->gp_size
21080 + info_ptr
->altivec_size
21081 + info_ptr
->altivec_padding_size
21082 + info_ptr
->spe_gp_size
21083 + info_ptr
->spe_padding_size
21086 + info_ptr
->cr_size
21087 + info_ptr
->vrsave_size
,
21090 non_fixed_size
= (info_ptr
->vars_size
21091 + info_ptr
->parm_size
21092 + info_ptr
->save_size
);
21094 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
21095 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
21097 /* Determine if we need to save the link register. */
21098 if (info_ptr
->calls_p
21099 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21101 && !TARGET_PROFILE_KERNEL
)
21102 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
21103 #ifdef TARGET_RELOCATABLE
21104 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
21106 || rs6000_ra_ever_killed ())
21107 info_ptr
->lr_save_p
= 1;
21109 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
21110 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
21111 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
21112 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
21113 using_static_chain_p
);
21115 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
21116 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
21117 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
21118 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
21119 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
21120 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
21121 info_ptr
->lr_save_p
= 1;
21123 if (info_ptr
->lr_save_p
)
21124 df_set_regs_ever_live (LR_REGNO
, true);
21126 /* Determine if we need to allocate any stack frame:
21128 For AIX we need to push the stack if a frame pointer is needed
21129 (because the stack might be dynamically adjusted), if we are
21130 debugging, if we make calls, or if the sum of fp_save, gp_save,
21131 and local variables are more than the space needed to save all
21132 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
21133 + 18*8 = 288 (GPR13 reserved).
21135 For V.4 we don't have the stack cushion that AIX uses, but assume
21136 that the debugger can handle stackless frames. */
21138 if (info_ptr
->calls_p
)
21139 info_ptr
->push_p
= 1;
21141 else if (DEFAULT_ABI
== ABI_V4
)
21142 info_ptr
->push_p
= non_fixed_size
!= 0;
21144 else if (frame_pointer_needed
)
21145 info_ptr
->push_p
= 1;
21147 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
21148 info_ptr
->push_p
= 1;
21151 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
21153 /* Zero offsets if we're not saving those registers. */
21154 if (info_ptr
->fp_size
== 0)
21155 info_ptr
->fp_save_offset
= 0;
21157 if (info_ptr
->gp_size
== 0)
21158 info_ptr
->gp_save_offset
= 0;
21160 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
21161 info_ptr
->altivec_save_offset
= 0;
21163 /* Zero VRSAVE offset if not saved and restored. */
21164 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
21165 info_ptr
->vrsave_save_offset
= 0;
21167 if (! TARGET_SPE_ABI
21168 || info_ptr
->spe_64bit_regs_used
== 0
21169 || info_ptr
->spe_gp_size
== 0)
21170 info_ptr
->spe_gp_save_offset
= 0;
21172 if (! info_ptr
->lr_save_p
)
21173 info_ptr
->lr_save_offset
= 0;
21175 if (! info_ptr
->cr_save_p
)
21176 info_ptr
->cr_save_offset
= 0;
21181 /* Return true if the current function uses any GPRs in 64-bit SIMD
21185 spe_func_has_64bit_regs_p (void)
21189 /* Functions that save and restore all the call-saved registers will
21190 need to save/restore the registers in 64-bits. */
21191 if (crtl
->calls_eh_return
21192 || cfun
->calls_setjmp
21193 || crtl
->has_nonlocal_goto
)
21196 insns
= get_insns ();
21198 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
21204 /* FIXME: This should be implemented with attributes...
21206 (set_attr "spe64" "true")....then,
21207 if (get_spe64(insn)) return true;
21209 It's the only reliable way to do the stuff below. */
21211 i
= PATTERN (insn
);
21212 if (GET_CODE (i
) == SET
)
21214 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
21216 if (SPE_VECTOR_MODE (mode
))
21218 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
21228 debug_stack_info (rs6000_stack_t
*info
)
21230 const char *abi_string
;
21233 info
= rs6000_stack_info ();
21235 fprintf (stderr
, "\nStack information for function %s:\n",
21236 ((current_function_decl
&& DECL_NAME (current_function_decl
))
21237 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
21242 default: abi_string
= "Unknown"; break;
21243 case ABI_NONE
: abi_string
= "NONE"; break;
21244 case ABI_AIX
: abi_string
= "AIX"; break;
21245 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
21246 case ABI_DARWIN
: abi_string
= "Darwin"; break;
21247 case ABI_V4
: abi_string
= "V.4"; break;
21250 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
21252 if (TARGET_ALTIVEC_ABI
)
21253 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
21255 if (TARGET_SPE_ABI
)
21256 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
21258 if (info
->first_gp_reg_save
!= 32)
21259 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
21261 if (info
->first_fp_reg_save
!= 64)
21262 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
21264 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
21265 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
21266 info
->first_altivec_reg_save
);
21268 if (info
->lr_save_p
)
21269 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
21271 if (info
->cr_save_p
)
21272 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
21274 if (info
->vrsave_mask
)
21275 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
21278 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
21281 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
21283 if (info
->gp_save_offset
)
21284 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
21286 if (info
->fp_save_offset
)
21287 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
21289 if (info
->altivec_save_offset
)
21290 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
21291 info
->altivec_save_offset
);
21293 if (info
->spe_gp_save_offset
)
21294 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
21295 info
->spe_gp_save_offset
);
21297 if (info
->vrsave_save_offset
)
21298 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
21299 info
->vrsave_save_offset
);
21301 if (info
->lr_save_offset
)
21302 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
21304 if (info
->cr_save_offset
)
21305 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
21307 if (info
->varargs_save_offset
)
21308 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
21310 if (info
->total_size
)
21311 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
21314 if (info
->vars_size
)
21315 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
21318 if (info
->parm_size
)
21319 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
21321 if (info
->fixed_size
)
21322 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
21325 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
21327 if (info
->spe_gp_size
)
21328 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
21331 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
21333 if (info
->altivec_size
)
21334 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
21336 if (info
->vrsave_size
)
21337 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
21339 if (info
->altivec_padding_size
)
21340 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
21341 info
->altivec_padding_size
);
21343 if (info
->spe_padding_size
)
21344 fprintf (stderr
, "\tspe_padding_size = %5d\n",
21345 info
->spe_padding_size
);
21348 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
21350 if (info
->save_size
)
21351 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
21353 if (info
->reg_size
!= 4)
21354 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
21356 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
21358 fprintf (stderr
, "\n");
21362 rs6000_return_addr (int count
, rtx frame
)
21364 /* Currently we don't optimize very well between prolog and body
21365 code and for PIC code the code can be actually quite bad, so
21366 don't try to be too clever here. */
21368 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
21370 cfun
->machine
->ra_needs_full_frame
= 1;
21377 plus_constant (Pmode
,
21379 (gen_rtx_MEM (Pmode
,
21380 memory_address (Pmode
, frame
))),
21381 RETURN_ADDRESS_OFFSET
)));
21384 cfun
->machine
->ra_need_lr
= 1;
21385 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
21388 /* Say whether a function is a candidate for sibcall handling or not. */
21391 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
21396 fntype
= TREE_TYPE (decl
);
21398 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
21400 /* We can't do it if the called function has more vector parameters
21401 than the current function; there's nowhere to put the VRsave code. */
21402 if (TARGET_ALTIVEC_ABI
21403 && TARGET_ALTIVEC_VRSAVE
21404 && !(decl
&& decl
== current_function_decl
))
21406 function_args_iterator args_iter
;
21410 /* Functions with vector parameters are required to have a
21411 prototype, so the argument type info must be available
21413 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
21414 if (TREE_CODE (type
) == VECTOR_TYPE
21415 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
21418 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
21419 if (TREE_CODE (type
) == VECTOR_TYPE
21420 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
21427 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
21428 functions, because the callee may have a different TOC pointer to
21429 the caller and there's no way to ensure we restore the TOC when
21430 we return. With the secure-plt SYSV ABI we can't make non-local
21431 calls when -fpic/PIC because the plt call stubs use r30. */
21432 if (DEFAULT_ABI
== ABI_DARWIN
21433 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21435 && !DECL_EXTERNAL (decl
)
21436 && (*targetm
.binds_local_p
) (decl
))
21437 || (DEFAULT_ABI
== ABI_V4
21438 && (!TARGET_SECURE_PLT
21441 && (*targetm
.binds_local_p
) (decl
)))))
21443 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
21445 if (!lookup_attribute ("longcall", attr_list
)
21446 || lookup_attribute ("shortcall", attr_list
))
21454 rs6000_ra_ever_killed (void)
21460 if (cfun
->is_thunk
)
21463 if (cfun
->machine
->lr_save_state
)
21464 return cfun
->machine
->lr_save_state
- 1;
21466 /* regs_ever_live has LR marked as used if any sibcalls are present,
21467 but this should not force saving and restoring in the
21468 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
21469 clobbers LR, so that is inappropriate. */
21471 /* Also, the prologue can generate a store into LR that
21472 doesn't really count, like this:
21475 bcl to set PIC register
21479 When we're called from the epilogue, we need to avoid counting
21480 this as a store. */
21482 push_topmost_sequence ();
21483 top
= get_insns ();
21484 pop_topmost_sequence ();
21485 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
21487 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
21493 if (!SIBLING_CALL_P (insn
))
21496 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
21498 else if (set_of (reg
, insn
) != NULL_RTX
21499 && !prologue_epilogue_contains (insn
))
21506 /* Emit instructions needed to load the TOC register.
21507 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
21508 a constant pool; or for SVR4 -fpic. */
21511 rs6000_emit_load_toc_table (int fromprolog
)
21514 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
21516 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
21519 rtx lab
, tmp1
, tmp2
, got
;
21521 lab
= gen_label_rtx ();
21522 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
21523 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21525 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21527 got
= rs6000_got_sym ();
21528 tmp1
= tmp2
= dest
;
21531 tmp1
= gen_reg_rtx (Pmode
);
21532 tmp2
= gen_reg_rtx (Pmode
);
21534 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
21535 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
21536 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
21537 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
21539 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
21541 emit_insn (gen_load_toc_v4_pic_si ());
21542 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21544 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
21547 rtx temp0
= (fromprolog
21548 ? gen_rtx_REG (Pmode
, 0)
21549 : gen_reg_rtx (Pmode
));
21555 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
21556 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21558 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
21559 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21561 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
21562 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21563 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
21569 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21570 lab
= gen_label_rtx ();
21571 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
21572 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21573 if (TARGET_LINK_STACK
)
21574 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
21575 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
21577 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
21579 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
21581 /* This is for AIX code running in non-PIC ELF32. */
21584 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
21585 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21587 emit_insn (gen_elf_high (dest
, realsym
));
21588 emit_insn (gen_elf_low (dest
, dest
, realsym
));
21592 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
21595 emit_insn (gen_load_toc_aix_si (dest
));
21597 emit_insn (gen_load_toc_aix_di (dest
));
21601 /* Emit instructions to restore the link register after determining where
21602 its value has been stored. */
21605 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
21607 rs6000_stack_t
*info
= rs6000_stack_info ();
21610 operands
[0] = source
;
21611 operands
[1] = scratch
;
21613 if (info
->lr_save_p
)
21615 rtx frame_rtx
= stack_pointer_rtx
;
21616 HOST_WIDE_INT sp_offset
= 0;
21619 if (frame_pointer_needed
21620 || cfun
->calls_alloca
21621 || info
->total_size
> 32767)
21623 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
21624 emit_move_insn (operands
[1], tmp
);
21625 frame_rtx
= operands
[1];
21627 else if (info
->push_p
)
21628 sp_offset
= info
->total_size
;
21630 tmp
= plus_constant (Pmode
, frame_rtx
,
21631 info
->lr_save_offset
+ sp_offset
);
21632 tmp
= gen_frame_mem (Pmode
, tmp
);
21633 emit_move_insn (tmp
, operands
[0]);
21636 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
21638 /* Freeze lr_save_p. We've just emitted rtl that depends on the
21639 state of lr_save_p so any change from here on would be a bug. In
21640 particular, stop rs6000_ra_ever_killed from considering the SET
21641 of lr we may have added just above. */
21642 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
21645 static GTY(()) alias_set_type set
= -1;
21648 get_TOC_alias_set (void)
21651 set
= new_alias_set ();
21655 /* This returns nonzero if the current function uses the TOC. This is
21656 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
21657 is generated by the ABI_V4 load_toc_* patterns. */
21664 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
21667 rtx pat
= PATTERN (insn
);
21670 if (GET_CODE (pat
) == PARALLEL
)
21671 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
21673 rtx sub
= XVECEXP (pat
, 0, i
);
21674 if (GET_CODE (sub
) == USE
)
21676 sub
= XEXP (sub
, 0);
21677 if (GET_CODE (sub
) == UNSPEC
21678 && XINT (sub
, 1) == UNSPEC_TOC
)
21688 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
21690 rtx tocrel
, tocreg
, hi
;
21692 if (TARGET_DEBUG_ADDR
)
21694 if (GET_CODE (symbol
) == SYMBOL_REF
)
21695 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
21699 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
21700 GET_RTX_NAME (GET_CODE (symbol
)));
21701 debug_rtx (symbol
);
21705 if (!can_create_pseudo_p ())
21706 df_set_regs_ever_live (TOC_REGISTER
, true);
21708 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
21709 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
21710 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
21713 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
21714 if (largetoc_reg
!= NULL
)
21716 emit_move_insn (largetoc_reg
, hi
);
21719 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
21722 /* Issue assembly directives that create a reference to the given DWARF
21723 FRAME_TABLE_LABEL from the current function section. */
21725 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
21727 fprintf (asm_out_file
, "\t.ref %s\n",
21728 (* targetm
.strip_name_encoding
) (frame_table_label
));
21731 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
21732 and the change to the stack pointer. */
21735 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
21742 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21743 if (hard_frame_needed
)
21744 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
21745 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
21746 || (hard_frame_needed
21747 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
21750 p
= rtvec_alloc (i
);
21753 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
21754 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
21757 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
21760 /* Emit the correct code for allocating stack space, as insns.
21761 If COPY_REG, make sure a copy of the old frame is left there.
21762 The generated code may use hard register 0 as a temporary. */
21765 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
21768 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21769 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
21770 rtx todec
= gen_int_mode (-size
, Pmode
);
21773 if (INTVAL (todec
) != -size
)
21775 warning (0, "stack frame too large");
21776 emit_insn (gen_trap ());
21780 if (crtl
->limit_stack
)
21782 if (REG_P (stack_limit_rtx
)
21783 && REGNO (stack_limit_rtx
) > 1
21784 && REGNO (stack_limit_rtx
) <= 31)
21786 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
21787 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21790 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
21792 && DEFAULT_ABI
== ABI_V4
)
21794 rtx toload
= gen_rtx_CONST (VOIDmode
,
21795 gen_rtx_PLUS (Pmode
,
21799 emit_insn (gen_elf_high (tmp_reg
, toload
));
21800 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
21801 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21805 warning (0, "stack limit expression is not supported");
21811 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
21813 emit_move_insn (copy_reg
, stack_reg
);
21818 /* Need a note here so that try_split doesn't get confused. */
21819 if (get_last_insn () == NULL_RTX
)
21820 emit_note (NOTE_INSN_DELETED
);
21821 insn
= emit_move_insn (tmp_reg
, todec
);
21822 try_split (PATTERN (insn
), insn
, 0);
21826 insn
= emit_insn (TARGET_32BIT
21827 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
21829 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
21830 todec
, stack_reg
));
21831 /* Since we didn't use gen_frame_mem to generate the MEM, grab
21832 it now and set the alias set/attributes. The above gen_*_update
21833 calls will generate a PARALLEL with the MEM set being the first
21835 par
= PATTERN (insn
);
21836 gcc_assert (GET_CODE (par
) == PARALLEL
);
21837 set
= XVECEXP (par
, 0, 0);
21838 gcc_assert (GET_CODE (set
) == SET
);
21839 mem
= SET_DEST (set
);
21840 gcc_assert (MEM_P (mem
));
21841 MEM_NOTRAP_P (mem
) = 1;
21842 set_mem_alias_set (mem
, get_frame_alias_set ());
21844 RTX_FRAME_RELATED_P (insn
) = 1;
21845 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
21846 gen_rtx_SET (VOIDmode
, stack_reg
,
21847 gen_rtx_PLUS (Pmode
, stack_reg
,
21848 GEN_INT (-size
))));
21851 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
21853 #if PROBE_INTERVAL > 32768
21854 #error Cannot use indexed addressing mode for stack probing
21857 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
21858 inclusive. These are offsets from the current stack pointer. */
21861 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
21863 /* See if we have a constant small number of probes to generate. If so,
21864 that's the easy case. */
21865 if (first
+ size
<= 32768)
21869 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
21870 it exceeds SIZE. If only one probe is needed, this will not
21871 generate any code. Then probe at FIRST + SIZE. */
21872 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
21873 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
21876 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
21880 /* Otherwise, do the same as above, but in a loop. Note that we must be
21881 extra careful with variables wrapping around because we might be at
21882 the very top (or the very bottom) of the address space and we have
21883 to be able to handle this case properly; in particular, we use an
21884 equality test for the loop condition. */
21887 HOST_WIDE_INT rounded_size
;
21888 rtx r12
= gen_rtx_REG (Pmode
, 12);
21889 rtx r0
= gen_rtx_REG (Pmode
, 0);
21891 /* Sanity check for the addressing mode we're going to use. */
21892 gcc_assert (first
<= 32768);
21894 /* Step 1: round SIZE to the previous multiple of the interval. */
21896 rounded_size
= size
& -PROBE_INTERVAL
;
21899 /* Step 2: compute initial and final value of the loop counter. */
21901 /* TEST_ADDR = SP + FIRST. */
21902 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
21903 plus_constant (Pmode
, stack_pointer_rtx
,
21906 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
21907 if (rounded_size
> 32768)
21909 emit_move_insn (r0
, GEN_INT (-rounded_size
));
21910 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
21911 gen_rtx_PLUS (Pmode
, r12
, r0
)));
21914 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
21915 plus_constant (Pmode
, r12
, -rounded_size
)));
21918 /* Step 3: the loop
21920 while (TEST_ADDR != LAST_ADDR)
21922 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
21926 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
21927 until it is equal to ROUNDED_SIZE. */
21930 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
21932 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
21935 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
21936 that SIZE is equal to ROUNDED_SIZE. */
21938 if (size
!= rounded_size
)
21939 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
21943 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
21944 absolute addresses. */
21947 output_probe_stack_range (rtx reg1
, rtx reg2
)
21949 static int labelno
= 0;
21950 char loop_lab
[32], end_lab
[32];
21953 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
21954 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
21956 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
21958 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
21962 output_asm_insn ("cmpd 0,%0,%1", xops
);
21964 output_asm_insn ("cmpw 0,%0,%1", xops
);
21966 fputs ("\tbeq 0,", asm_out_file
);
21967 assemble_name_raw (asm_out_file
, end_lab
);
21968 fputc ('\n', asm_out_file
);
21970 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
21971 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
21972 output_asm_insn ("addi %0,%0,%1", xops
);
21974 /* Probe at TEST_ADDR and branch. */
21975 xops
[1] = gen_rtx_REG (Pmode
, 0);
21976 output_asm_insn ("stw %1,0(%0)", xops
);
21977 fprintf (asm_out_file
, "\tb ");
21978 assemble_name_raw (asm_out_file
, loop_lab
);
21979 fputc ('\n', asm_out_file
);
21981 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
21986 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
21987 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
21988 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
21989 deduce these equivalences by itself so it wasn't necessary to hold
21990 its hand so much. Don't be tempted to always supply d2_f_d_e with
21991 the actual cfa register, ie. r31 when we are using a hard frame
21992 pointer. That fails when saving regs off r1, and sched moves the
21993 r31 setup past the reg saves. */
21996 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
21997 rtx reg2
, rtx rreg
, rtx split_reg
)
22001 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
22003 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
22006 gcc_checking_assert (val
== 0);
22007 real
= PATTERN (insn
);
22008 if (GET_CODE (real
) == PARALLEL
)
22009 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
22010 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
22012 rtx set
= XVECEXP (real
, 0, i
);
22014 RTX_FRAME_RELATED_P (set
) = 1;
22016 RTX_FRAME_RELATED_P (insn
) = 1;
22020 /* copy_rtx will not make unique copies of registers, so we need to
22021 ensure we don't have unwanted sharing here. */
22023 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
22026 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
22028 real
= copy_rtx (PATTERN (insn
));
22030 if (reg2
!= NULL_RTX
)
22031 real
= replace_rtx (real
, reg2
, rreg
);
22033 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
22034 gcc_checking_assert (val
== 0);
22036 real
= replace_rtx (real
, reg
,
22037 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
22038 STACK_POINTER_REGNUM
),
22041 /* We expect that 'real' is either a SET or a PARALLEL containing
22042 SETs (and possibly other stuff). In a PARALLEL, all the SETs
22043 are important so they all have to be marked RTX_FRAME_RELATED_P. */
22045 if (GET_CODE (real
) == SET
)
22049 temp
= simplify_rtx (SET_SRC (set
));
22051 SET_SRC (set
) = temp
;
22052 temp
= simplify_rtx (SET_DEST (set
));
22054 SET_DEST (set
) = temp
;
22055 if (GET_CODE (SET_DEST (set
)) == MEM
)
22057 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
22059 XEXP (SET_DEST (set
), 0) = temp
;
22066 gcc_assert (GET_CODE (real
) == PARALLEL
);
22067 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
22068 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
22070 rtx set
= XVECEXP (real
, 0, i
);
22072 temp
= simplify_rtx (SET_SRC (set
));
22074 SET_SRC (set
) = temp
;
22075 temp
= simplify_rtx (SET_DEST (set
));
22077 SET_DEST (set
) = temp
;
22078 if (GET_CODE (SET_DEST (set
)) == MEM
)
22080 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
22082 XEXP (SET_DEST (set
), 0) = temp
;
22084 RTX_FRAME_RELATED_P (set
) = 1;
22088 /* If a store insn has been split into multiple insns, the
22089 true source register is given by split_reg. */
22090 if (split_reg
!= NULL_RTX
)
22091 real
= gen_rtx_SET (VOIDmode
, SET_DEST (real
), split_reg
);
22093 RTX_FRAME_RELATED_P (insn
) = 1;
22094 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
22099 /* Returns an insn that has a vrsave set operation with the
22100 appropriate CLOBBERs. */
22103 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
22106 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
22107 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
22110 = gen_rtx_SET (VOIDmode
,
22112 gen_rtx_UNSPEC_VOLATILE (SImode
,
22113 gen_rtvec (2, reg
, vrsave
),
22114 UNSPECV_SET_VRSAVE
));
22118 /* We need to clobber the registers in the mask so the scheduler
22119 does not move sets to VRSAVE before sets of AltiVec registers.
22121 However, if the function receives nonlocal gotos, reload will set
22122 all call saved registers live. We will end up with:
22124 (set (reg 999) (mem))
22125 (parallel [ (set (reg vrsave) (unspec blah))
22126 (clobber (reg 999))])
22128 The clobber will cause the store into reg 999 to be dead, and
22129 flow will attempt to delete an epilogue insn. In this case, we
22130 need an unspec use/set of the register. */
22132 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22133 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22135 if (!epiloguep
|| call_used_regs
[i
])
22136 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
22137 gen_rtx_REG (V4SImode
, i
));
22140 rtx reg
= gen_rtx_REG (V4SImode
, i
);
22143 = gen_rtx_SET (VOIDmode
,
22145 gen_rtx_UNSPEC (V4SImode
,
22146 gen_rtvec (1, reg
), 27));
22150 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
22152 for (i
= 0; i
< nclobs
; ++i
)
22153 XVECEXP (insn
, 0, i
) = clobs
[i
];
22159 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
22163 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
22164 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
22165 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
22169 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
22171 return gen_frame_set (reg
, frame_reg
, offset
, false);
22175 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
22177 return gen_frame_set (reg
, frame_reg
, offset
, true);
22180 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
22181 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
22184 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
22185 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
22189 /* Some cases that need register indexed addressing. */
22190 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
22191 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
22192 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
22194 && SPE_VECTOR_MODE (mode
)
22195 && !SPE_CONST_OFFSET_OK (offset
))));
22197 reg
= gen_rtx_REG (mode
, regno
);
22198 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
22199 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
22200 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22203 /* Emit an offset memory reference suitable for a frame store, while
22204 converting to a valid addressing mode. */
22207 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
22209 rtx int_rtx
, offset_rtx
;
22211 int_rtx
= GEN_INT (offset
);
22213 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
22214 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
22216 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
22217 emit_move_insn (offset_rtx
, int_rtx
);
22220 offset_rtx
= int_rtx
;
22222 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
22225 #ifndef TARGET_FIX_AND_CONTINUE
22226 #define TARGET_FIX_AND_CONTINUE 0
22229 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
22230 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
22231 #define LAST_SAVRES_REGISTER 31
22232 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
22243 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
22245 /* Temporary holding space for an out-of-line register save/restore
22247 static char savres_routine_name
[30];
22249 /* Return the name for an out-of-line register save/restore routine.
22250 We are saving/restoring GPRs if GPR is true. */
22253 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
22255 const char *prefix
= "";
22256 const char *suffix
= "";
22258 /* Different targets are supposed to define
22259 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
22260 routine name could be defined with:
22262 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
22264 This is a nice idea in practice, but in reality, things are
22265 complicated in several ways:
22267 - ELF targets have save/restore routines for GPRs.
22269 - SPE targets use different prefixes for 32/64-bit registers, and
22270 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
22272 - PPC64 ELF targets have routines for save/restore of GPRs that
22273 differ in what they do with the link register, so having a set
22274 prefix doesn't work. (We only use one of the save routines at
22275 the moment, though.)
22277 - PPC32 elf targets have "exit" versions of the restore routines
22278 that restore the link register and can save some extra space.
22279 These require an extra suffix. (There are also "tail" versions
22280 of the restore routines and "GOT" versions of the save routines,
22281 but we don't generate those at present. Same problems apply,
22284 We deal with all this by synthesizing our own prefix/suffix and
22285 using that for the simple sprintf call shown above. */
22288 /* No floating point saves on the SPE. */
22289 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
22291 if ((sel
& SAVRES_SAVE
))
22292 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
22294 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
22296 if ((sel
& SAVRES_LR
))
22299 else if (DEFAULT_ABI
== ABI_V4
)
22304 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22305 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
22306 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22307 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
22308 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22309 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
22313 if ((sel
& SAVRES_LR
))
22316 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22318 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
22319 /* No out-of-line save/restore routines for GPRs on AIX. */
22320 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
22324 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22325 prefix
= ((sel
& SAVRES_SAVE
)
22326 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
22327 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
22328 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22330 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
22331 if ((sel
& SAVRES_LR
))
22332 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
22336 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
22337 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
22340 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22341 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
22346 if (DEFAULT_ABI
== ABI_DARWIN
)
22348 /* The Darwin approach is (slightly) different, in order to be
22349 compatible with code generated by the system toolchain. There is a
22350 single symbol for the start of save sequence, and the code here
22351 embeds an offset into that code on the basis of the first register
22353 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
22354 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22355 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
22356 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
22357 (regno
- 13) * 4, prefix
, regno
);
22358 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22359 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
22360 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
22361 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22362 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
22363 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
22368 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
22370 return savres_routine_name
;
22373 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
22374 We are saving/restoring GPRs if GPR is true. */
22377 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
22379 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22380 ? info
->first_gp_reg_save
22381 : (sel
& SAVRES_REG
) == SAVRES_FPR
22382 ? info
->first_fp_reg_save
- 32
22383 : (sel
& SAVRES_REG
) == SAVRES_VR
22384 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
22389 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
22390 versions of the gpr routines. */
22391 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
22392 && info
->spe_64bit_regs_used
)
22393 select
^= SAVRES_FPR
^ SAVRES_GPR
;
22395 /* Don't generate bogus routine names. */
22396 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
22397 && regno
<= LAST_SAVRES_REGISTER
22398 && select
>= 0 && select
<= 12);
22400 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
22406 name
= rs6000_savres_routine_name (info
, regno
, sel
);
22408 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
22409 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
22410 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
22416 /* Emit a sequence of insns, including a stack tie if needed, for
22417 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
22418 reset the stack pointer, but move the base of the frame into
22419 reg UPDT_REGNO for use by out-of-line register restore routines. */
22422 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
22423 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
22424 unsigned updt_regno
)
22428 /* This blockage is needed so that sched doesn't decide to move
22429 the sp change before the register restores. */
22430 if (DEFAULT_ABI
== ABI_V4
22432 && info
->spe_64bit_regs_used
!= 0
22433 && info
->first_gp_reg_save
!= 32))
22434 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
22436 /* If we are restoring registers out-of-line, we will be using the
22437 "exit" variants of the restore routines, which will reset the
22438 stack for us. But we do need to point updt_reg into the
22439 right place for those routines. */
22440 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
22442 if (frame_off
!= 0)
22443 return emit_insn (gen_add3_insn (updt_reg_rtx
,
22444 frame_reg_rtx
, GEN_INT (frame_off
)));
22445 else if (REGNO (frame_reg_rtx
) != updt_regno
)
22446 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
22451 /* Return the register number used as a pointer by out-of-line
22452 save/restore functions. */
22454 static inline unsigned
22455 ptr_regno_for_savres (int sel
)
22457 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22458 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
22459 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
22462 /* Construct a parallel rtx describing the effect of a call to an
22463 out-of-line register save/restore routine, and emit the insn
22464 or jump_insn as appropriate. */
22467 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
22468 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
22469 enum machine_mode reg_mode
, int sel
)
22472 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
22473 int reg_size
= GET_MODE_SIZE (reg_mode
);
22479 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22480 ? info
->first_gp_reg_save
22481 : (sel
& SAVRES_REG
) == SAVRES_FPR
22482 ? info
->first_fp_reg_save
22483 : (sel
& SAVRES_REG
) == SAVRES_VR
22484 ? info
->first_altivec_reg_save
22486 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22488 : (sel
& SAVRES_REG
) == SAVRES_FPR
22490 : (sel
& SAVRES_REG
) == SAVRES_VR
22491 ? LAST_ALTIVEC_REGNO
+ 1
22493 n_regs
= end_reg
- start_reg
;
22494 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
22495 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
22498 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22499 RTVEC_ELT (p
, offset
++) = ret_rtx
;
22501 RTVEC_ELT (p
, offset
++)
22502 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
22504 sym
= rs6000_savres_routine_sym (info
, sel
);
22505 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
22507 use_reg
= ptr_regno_for_savres (sel
);
22508 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22510 /* Vector regs are saved/restored using [reg+reg] addressing. */
22511 RTVEC_ELT (p
, offset
++)
22512 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
22513 RTVEC_ELT (p
, offset
++)
22514 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
22517 RTVEC_ELT (p
, offset
++)
22518 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
22520 for (i
= 0; i
< end_reg
- start_reg
; i
++)
22521 RTVEC_ELT (p
, i
+ offset
)
22522 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
22523 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
22524 (sel
& SAVRES_SAVE
) != 0);
22526 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22527 RTVEC_ELT (p
, i
+ offset
)
22528 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
22530 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
22532 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22534 insn
= emit_jump_insn (par
);
22535 JUMP_LABEL (insn
) = ret_rtx
;
22538 insn
= emit_insn (par
);
22542 /* Emit code to store CR fields that need to be saved into REG. */
22545 rs6000_emit_move_from_cr (rtx reg
)
22547 /* Only the ELFv2 ABI allows storing only selected fields. */
22548 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
22550 int i
, cr_reg
[8], count
= 0;
22552 /* Collect CR fields that must be saved. */
22553 for (i
= 0; i
< 8; i
++)
22554 if (save_reg_p (CR0_REGNO
+ i
))
22555 cr_reg
[count
++] = i
;
22557 /* If it's just a single one, use mfcrf. */
22560 rtvec p
= rtvec_alloc (1);
22561 rtvec r
= rtvec_alloc (2);
22562 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
22563 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
22565 = gen_rtx_SET (VOIDmode
, reg
,
22566 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
22568 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22572 /* ??? It might be better to handle count == 2 / 3 cases here
22573 as well, using logical operations to combine the values. */
22576 emit_insn (gen_movesi_from_cr (reg
));
22579 /* Determine whether the gp REG is really used. */
22582 rs6000_reg_live_or_pic_offset_p (int reg
)
22584 /* If the function calls eh_return, claim used all the registers that would
22585 be checked for liveness otherwise. This is required for the PIC offset
22586 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
22587 register allocation purposes in this case. */
22589 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
22590 && (!call_used_regs
[reg
]
22591 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22592 && !TARGET_SINGLE_PIC_BASE
22593 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
22594 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22595 && !TARGET_SINGLE_PIC_BASE
22596 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
22597 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
22600 /* Emit function prologue as insns. */
22603 rs6000_emit_prologue (void)
22605 rs6000_stack_t
*info
= rs6000_stack_info ();
22606 enum machine_mode reg_mode
= Pmode
;
22607 int reg_size
= TARGET_32BIT
? 4 : 8;
22608 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22609 rtx frame_reg_rtx
= sp_reg_rtx
;
22610 unsigned int cr_save_regno
;
22611 rtx cr_save_rtx
= NULL_RTX
;
22614 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
22615 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
22616 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
22617 /* Offset to top of frame for frame_reg and sp respectively. */
22618 HOST_WIDE_INT frame_off
= 0;
22619 HOST_WIDE_INT sp_off
= 0;
22621 #ifdef ENABLE_CHECKING
22622 /* Track and check usage of r0, r11, r12. */
22623 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
22624 #define START_USE(R) do \
22626 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22627 reg_inuse |= 1 << (R); \
22629 #define END_USE(R) do \
22631 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
22632 reg_inuse &= ~(1 << (R)); \
22634 #define NOT_INUSE(R) do \
22636 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22639 #define START_USE(R) do {} while (0)
22640 #define END_USE(R) do {} while (0)
22641 #define NOT_INUSE(R) do {} while (0)
22644 if (DEFAULT_ABI
== ABI_ELFv2
)
22646 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
22648 /* With -mminimal-toc we may generate an extra use of r2 below. */
22649 if (!TARGET_SINGLE_PIC_BASE
22650 && TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
22651 cfun
->machine
->r2_setup_needed
= true;
22655 if (flag_stack_usage_info
)
22656 current_function_static_stack_size
= info
->total_size
;
22658 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
22660 HOST_WIDE_INT size
= info
->total_size
;
22662 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
22664 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
22665 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
22666 size
- STACK_CHECK_PROTECT
);
22669 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
22672 if (TARGET_FIX_AND_CONTINUE
)
22674 /* gdb on darwin arranges to forward a function from the old
22675 address by modifying the first 5 instructions of the function
22676 to branch to the overriding function. This is necessary to
22677 permit function pointers that point to the old function to
22678 actually forward to the new function. */
22679 emit_insn (gen_nop ());
22680 emit_insn (gen_nop ());
22681 emit_insn (gen_nop ());
22682 emit_insn (gen_nop ());
22683 emit_insn (gen_nop ());
22686 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
22688 reg_mode
= V2SImode
;
22692 /* Handle world saves specially here. */
22693 if (WORLD_SAVE_P (info
))
22700 /* save_world expects lr in r0. */
22701 reg0
= gen_rtx_REG (Pmode
, 0);
22702 if (info
->lr_save_p
)
22704 insn
= emit_move_insn (reg0
,
22705 gen_rtx_REG (Pmode
, LR_REGNO
));
22706 RTX_FRAME_RELATED_P (insn
) = 1;
22709 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
22710 assumptions about the offsets of various bits of the stack
22712 gcc_assert (info
->gp_save_offset
== -220
22713 && info
->fp_save_offset
== -144
22714 && info
->lr_save_offset
== 8
22715 && info
->cr_save_offset
== 4
22718 && (!crtl
->calls_eh_return
22719 || info
->ehrd_offset
== -432)
22720 && info
->vrsave_save_offset
== -224
22721 && info
->altivec_save_offset
== -416);
22723 treg
= gen_rtx_REG (SImode
, 11);
22724 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
22726 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
22727 in R11. It also clobbers R12, so beware! */
22729 /* Preserve CR2 for save_world prologues */
22731 sz
+= 32 - info
->first_gp_reg_save
;
22732 sz
+= 64 - info
->first_fp_reg_save
;
22733 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
22734 p
= rtvec_alloc (sz
);
22736 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
22737 gen_rtx_REG (SImode
,
22739 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
22740 gen_rtx_SYMBOL_REF (Pmode
,
22742 /* We do floats first so that the instruction pattern matches
22744 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22746 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22748 info
->first_fp_reg_save
+ i
),
22750 info
->fp_save_offset
+ frame_off
+ 8 * i
);
22751 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
22753 = gen_frame_store (gen_rtx_REG (V4SImode
,
22754 info
->first_altivec_reg_save
+ i
),
22756 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
22757 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22759 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22761 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22763 /* CR register traditionally saved as CR2. */
22765 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
22766 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
22767 /* Explain about use of R0. */
22768 if (info
->lr_save_p
)
22770 = gen_frame_store (reg0
,
22771 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
22772 /* Explain what happens to the stack pointer. */
22774 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
22775 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
22778 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22779 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22780 treg
, GEN_INT (-info
->total_size
), NULL_RTX
);
22781 sp_off
= frame_off
= info
->total_size
;
22784 strategy
= info
->savres_strategy
;
22786 /* For V.4, update stack before we do any saving and set back pointer. */
22787 if (! WORLD_SAVE_P (info
)
22789 && (DEFAULT_ABI
== ABI_V4
22790 || crtl
->calls_eh_return
))
22792 bool need_r11
= (TARGET_SPE
22793 ? (!(strategy
& SAVE_INLINE_GPRS
)
22794 && info
->spe_64bit_regs_used
== 0)
22795 : (!(strategy
& SAVE_INLINE_FPRS
)
22796 || !(strategy
& SAVE_INLINE_GPRS
)
22797 || !(strategy
& SAVE_INLINE_VRS
)));
22798 int ptr_regno
= -1;
22799 rtx ptr_reg
= NULL_RTX
;
22802 if (info
->total_size
< 32767)
22803 frame_off
= info
->total_size
;
22806 else if (info
->cr_save_p
22808 || info
->first_fp_reg_save
< 64
22809 || info
->first_gp_reg_save
< 32
22810 || info
->altivec_size
!= 0
22811 || info
->vrsave_mask
!= 0
22812 || crtl
->calls_eh_return
)
22816 /* The prologue won't be saving any regs so there is no need
22817 to set up a frame register to access any frame save area.
22818 We also won't be using frame_off anywhere below, but set
22819 the correct value anyway to protect against future
22820 changes to this function. */
22821 frame_off
= info
->total_size
;
22823 if (ptr_regno
!= -1)
22825 /* Set up the frame offset to that needed by the first
22826 out-of-line save function. */
22827 START_USE (ptr_regno
);
22828 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22829 frame_reg_rtx
= ptr_reg
;
22830 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
22831 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
22832 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
22833 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
22834 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
22835 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
22836 frame_off
= -ptr_off
;
22838 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
22839 sp_off
= info
->total_size
;
22840 if (frame_reg_rtx
!= sp_reg_rtx
)
22841 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22844 /* If we use the link register, get it into r0. */
22845 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
22847 rtx addr
, reg
, mem
;
22849 reg
= gen_rtx_REG (Pmode
, 0);
22851 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
22852 RTX_FRAME_RELATED_P (insn
) = 1;
22854 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
22855 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
22857 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
22858 GEN_INT (info
->lr_save_offset
+ frame_off
));
22859 mem
= gen_rtx_MEM (Pmode
, addr
);
22860 /* This should not be of rs6000_sr_alias_set, because of
22861 __builtin_return_address. */
22863 insn
= emit_move_insn (mem
, reg
);
22864 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22865 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22870 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
22871 r12 will be needed by out-of-line gpr restore. */
22872 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22873 && !(strategy
& (SAVE_INLINE_GPRS
22874 | SAVE_NOINLINE_GPRS_SAVES_LR
))
22876 if (!WORLD_SAVE_P (info
)
22878 && REGNO (frame_reg_rtx
) != cr_save_regno
22879 && !(using_static_chain_p
&& cr_save_regno
== 11))
22881 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
22882 START_USE (cr_save_regno
);
22883 rs6000_emit_move_from_cr (cr_save_rtx
);
22886 /* Do any required saving of fpr's. If only one or two to save, do
22887 it ourselves. Otherwise, call function. */
22888 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
22891 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22892 if (save_reg_p (info
->first_fp_reg_save
+ i
))
22893 emit_frame_save (frame_reg_rtx
,
22894 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22895 ? DFmode
: SFmode
),
22896 info
->first_fp_reg_save
+ i
,
22897 info
->fp_save_offset
+ frame_off
+ 8 * i
,
22898 sp_off
- frame_off
);
22900 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
22902 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
22903 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22904 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22905 rtx ptr_reg
= frame_reg_rtx
;
22907 if (REGNO (frame_reg_rtx
) == ptr_regno
)
22908 gcc_checking_assert (frame_off
== 0);
22911 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22912 NOT_INUSE (ptr_regno
);
22913 emit_insn (gen_add3_insn (ptr_reg
,
22914 frame_reg_rtx
, GEN_INT (frame_off
)));
22916 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
22917 info
->fp_save_offset
,
22918 info
->lr_save_offset
,
22920 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
22921 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22926 /* Save GPRs. This is done as a PARALLEL if we are using
22927 the store-multiple instructions. */
22928 if (!WORLD_SAVE_P (info
)
22930 && info
->spe_64bit_regs_used
!= 0
22931 && info
->first_gp_reg_save
!= 32)
22934 rtx spe_save_area_ptr
;
22935 HOST_WIDE_INT save_off
;
22936 int ool_adjust
= 0;
22938 /* Determine whether we can address all of the registers that need
22939 to be saved with an offset from frame_reg_rtx that fits in
22940 the small const field for SPE memory instructions. */
22941 int spe_regs_addressable
22942 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
22943 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
22944 && (strategy
& SAVE_INLINE_GPRS
));
22946 if (spe_regs_addressable
)
22948 spe_save_area_ptr
= frame_reg_rtx
;
22949 save_off
= frame_off
;
22953 /* Make r11 point to the start of the SPE save area. We need
22954 to be careful here if r11 is holding the static chain. If
22955 it is, then temporarily save it in r0. */
22956 HOST_WIDE_INT offset
;
22958 if (!(strategy
& SAVE_INLINE_GPRS
))
22959 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
22960 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
22961 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
22962 save_off
= frame_off
- offset
;
22964 if (using_static_chain_p
)
22966 rtx r0
= gen_rtx_REG (Pmode
, 0);
22969 gcc_assert (info
->first_gp_reg_save
> 11);
22971 emit_move_insn (r0
, spe_save_area_ptr
);
22973 else if (REGNO (frame_reg_rtx
) != 11)
22976 emit_insn (gen_addsi3 (spe_save_area_ptr
,
22977 frame_reg_rtx
, GEN_INT (offset
)));
22978 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
22979 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
22982 if ((strategy
& SAVE_INLINE_GPRS
))
22984 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22985 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22986 emit_frame_save (spe_save_area_ptr
, reg_mode
,
22987 info
->first_gp_reg_save
+ i
,
22988 (info
->spe_gp_save_offset
+ save_off
22990 sp_off
- save_off
);
22994 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
22995 info
->spe_gp_save_offset
+ save_off
,
22997 SAVRES_SAVE
| SAVRES_GPR
);
22999 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
23000 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23003 /* Move the static chain pointer back. */
23004 if (!spe_regs_addressable
)
23006 if (using_static_chain_p
)
23008 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
23011 else if (REGNO (frame_reg_rtx
) != 11)
23015 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
23017 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
23018 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23019 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23020 rtx ptr_reg
= frame_reg_rtx
;
23021 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
23022 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
23026 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23028 /* Need to adjust r11 (r12) if we saved any FPRs. */
23029 if (end_save
+ frame_off
!= 0)
23031 rtx offset
= GEN_INT (end_save
+ frame_off
);
23034 frame_off
= -end_save
;
23036 NOT_INUSE (ptr_regno
);
23037 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23039 else if (!ptr_set_up
)
23041 NOT_INUSE (ptr_regno
);
23042 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23044 ptr_off
= -end_save
;
23045 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
23046 info
->gp_save_offset
+ ptr_off
,
23047 info
->lr_save_offset
+ ptr_off
,
23049 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
23050 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23054 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
23058 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
23059 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23061 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23063 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
23064 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23065 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23066 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23068 else if (!WORLD_SAVE_P (info
))
23071 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23072 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23073 emit_frame_save (frame_reg_rtx
, reg_mode
,
23074 info
->first_gp_reg_save
+ i
,
23075 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
23076 sp_off
- frame_off
);
23079 if (crtl
->calls_eh_return
)
23086 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
23087 if (regno
== INVALID_REGNUM
)
23091 p
= rtvec_alloc (i
);
23095 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
23096 if (regno
== INVALID_REGNUM
)
23100 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
23102 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
23103 RTVEC_ELT (p
, i
) = insn
;
23104 RTX_FRAME_RELATED_P (insn
) = 1;
23107 insn
= emit_insn (gen_blockage ());
23108 RTX_FRAME_RELATED_P (insn
) = 1;
23109 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
23112 /* In AIX ABI we need to make sure r2 is really saved. */
23113 if (TARGET_AIX
&& crtl
->calls_eh_return
)
23115 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
23116 rtx save_insn
, join_insn
, note
;
23117 long toc_restore_insn
;
23119 tmp_reg
= gen_rtx_REG (Pmode
, 11);
23120 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
23121 if (using_static_chain_p
)
23124 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
23128 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
23129 /* Peek at instruction to which this function returns. If it's
23130 restoring r2, then we know we've already saved r2. We can't
23131 unconditionally save r2 because the value we have will already
23132 be updated if we arrived at this function via a plt call or
23133 toc adjusting stub. */
23134 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
23135 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
23136 + RS6000_TOC_SAVE_SLOT
);
23137 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
23138 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
23139 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
23140 validate_condition_mode (EQ
, CCUNSmode
);
23141 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
23142 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
23143 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
23144 toc_save_done
= gen_label_rtx ();
23145 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
23146 gen_rtx_EQ (VOIDmode
, compare_result
,
23148 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
23150 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
23151 JUMP_LABEL (jump
) = toc_save_done
;
23152 LABEL_NUSES (toc_save_done
) += 1;
23154 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
23155 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
23156 sp_off
- frame_off
);
23158 emit_label (toc_save_done
);
23160 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
23161 have a CFG that has different saves along different paths.
23162 Move the note to a dummy blockage insn, which describes that
23163 R2 is unconditionally saved after the label. */
23164 /* ??? An alternate representation might be a special insn pattern
23165 containing both the branch and the store. That might let the
23166 code that minimizes the number of DW_CFA_advance opcodes better
23167 freedom in placing the annotations. */
23168 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
23170 remove_note (save_insn
, note
);
23172 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
23173 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
23174 RTX_FRAME_RELATED_P (save_insn
) = 0;
23176 join_insn
= emit_insn (gen_blockage ());
23177 REG_NOTES (join_insn
) = note
;
23178 RTX_FRAME_RELATED_P (join_insn
) = 1;
23180 if (using_static_chain_p
)
23182 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
23189 /* Save CR if we use any that must be preserved. */
23190 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
23192 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
23193 GEN_INT (info
->cr_save_offset
+ frame_off
));
23194 rtx mem
= gen_frame_mem (SImode
, addr
);
23196 /* If we didn't copy cr before, do so now using r0. */
23197 if (cr_save_rtx
== NULL_RTX
)
23200 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
23201 rs6000_emit_move_from_cr (cr_save_rtx
);
23204 /* Saving CR requires a two-instruction sequence: one instruction
23205 to move the CR to a general-purpose register, and a second
23206 instruction that stores the GPR to memory.
23208 We do not emit any DWARF CFI records for the first of these,
23209 because we cannot properly represent the fact that CR is saved in
23210 a register. One reason is that we cannot express that multiple
23211 CR fields are saved; another reason is that on 64-bit, the size
23212 of the CR register in DWARF (4 bytes) differs from the size of
23213 a general-purpose register.
23215 This means if any intervening instruction were to clobber one of
23216 the call-saved CR fields, we'd have incorrect CFI. To prevent
23217 this from happening, we mark the store to memory as a use of
23218 those CR fields, which prevents any such instruction from being
23219 scheduled in between the two instructions. */
23224 crsave_v
[n_crsave
++] = gen_rtx_SET (VOIDmode
, mem
, cr_save_rtx
);
23225 for (i
= 0; i
< 8; i
++)
23226 if (save_reg_p (CR0_REGNO
+ i
))
23227 crsave_v
[n_crsave
++]
23228 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
23230 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
23231 gen_rtvec_v (n_crsave
, crsave_v
)));
23232 END_USE (REGNO (cr_save_rtx
));
23234 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
23235 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
23236 so we need to construct a frame expression manually. */
23237 RTX_FRAME_RELATED_P (insn
) = 1;
23239 /* Update address to be stack-pointer relative, like
23240 rs6000_frame_related would do. */
23241 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
23242 GEN_INT (info
->cr_save_offset
+ sp_off
));
23243 mem
= gen_frame_mem (SImode
, addr
);
23245 if (DEFAULT_ABI
== ABI_ELFv2
)
23247 /* In the ELFv2 ABI we generate separate CFI records for each
23248 CR field that was actually saved. They all point to the
23249 same 32-bit stack slot. */
23253 for (i
= 0; i
< 8; i
++)
23254 if (save_reg_p (CR0_REGNO
+ i
))
23257 = gen_rtx_SET (VOIDmode
, mem
,
23258 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23260 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
23264 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
23265 gen_rtx_PARALLEL (VOIDmode
,
23266 gen_rtvec_v (n_crframe
, crframe
)));
23270 /* In other ABIs, by convention, we use a single CR regnum to
23271 represent the fact that all call-saved CR fields are saved.
23272 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
23273 rtx set
= gen_rtx_SET (VOIDmode
, mem
,
23274 gen_rtx_REG (SImode
, CR2_REGNO
));
23275 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
23279 /* In the ELFv2 ABI we need to save all call-saved CR fields into
23280 *separate* slots if the routine calls __builtin_eh_return, so
23281 that they can be independently restored by the unwinder. */
23282 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
23284 int i
, cr_off
= info
->ehcr_offset
;
23287 /* ??? We might get better performance by using multiple mfocrf
23289 crsave
= gen_rtx_REG (SImode
, 0);
23290 emit_insn (gen_movesi_from_cr (crsave
));
23292 for (i
= 0; i
< 8; i
++)
23293 if (!call_used_regs
[CR0_REGNO
+ i
])
23295 rtvec p
= rtvec_alloc (2);
23297 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
23299 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
23301 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23303 RTX_FRAME_RELATED_P (insn
) = 1;
23304 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
23305 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
23306 sp_reg_rtx
, cr_off
+ sp_off
));
23308 cr_off
+= reg_size
;
23312 /* Update stack and set back pointer unless this is V.4,
23313 for which it was done previously. */
23314 if (!WORLD_SAVE_P (info
) && info
->push_p
23315 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
23317 rtx ptr_reg
= NULL
;
23320 /* If saving altivec regs we need to be able to address all save
23321 locations using a 16-bit offset. */
23322 if ((strategy
& SAVE_INLINE_VRS
) == 0
23323 || (info
->altivec_size
!= 0
23324 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
23325 + info
->total_size
- frame_off
) > 32767)
23326 || (info
->vrsave_size
!= 0
23327 && (info
->vrsave_save_offset
23328 + info
->total_size
- frame_off
) > 32767))
23330 int sel
= SAVRES_SAVE
| SAVRES_VR
;
23331 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23333 if (using_static_chain_p
23334 && ptr_regno
== STATIC_CHAIN_REGNUM
)
23336 if (REGNO (frame_reg_rtx
) != ptr_regno
)
23337 START_USE (ptr_regno
);
23338 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23339 frame_reg_rtx
= ptr_reg
;
23340 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
23341 frame_off
= -ptr_off
;
23343 else if (REGNO (frame_reg_rtx
) == 1)
23344 frame_off
= info
->total_size
;
23345 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
23346 sp_off
= info
->total_size
;
23347 if (frame_reg_rtx
!= sp_reg_rtx
)
23348 rs6000_emit_stack_tie (frame_reg_rtx
, false);
23351 /* Set frame pointer, if needed. */
23352 if (frame_pointer_needed
)
23354 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
23356 RTX_FRAME_RELATED_P (insn
) = 1;
23359 /* Save AltiVec registers if needed. Save here because the red zone does
23360 not always include AltiVec registers. */
23361 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
23362 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
23364 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
23366 /* Oddly, the vector save/restore functions point r0 at the end
23367 of the save area, then use r11 or r12 to load offsets for
23368 [reg+reg] addressing. */
23369 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
23370 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
23371 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
23373 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
23375 if (end_save
+ frame_off
!= 0)
23377 rtx offset
= GEN_INT (end_save
+ frame_off
);
23379 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23382 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23384 ptr_off
= -end_save
;
23385 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
23386 info
->altivec_save_offset
+ ptr_off
,
23387 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
23388 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
23389 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23390 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
23392 /* The oddity mentioned above clobbered our frame reg. */
23393 emit_move_insn (frame_reg_rtx
, ptr_reg
);
23394 frame_off
= ptr_off
;
23397 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
23398 && info
->altivec_size
!= 0)
23402 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23403 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23405 rtx areg
, savereg
, mem
, split_reg
;
23408 offset
= (info
->altivec_save_offset
+ frame_off
23409 + 16 * (i
- info
->first_altivec_reg_save
));
23411 savereg
= gen_rtx_REG (V4SImode
, i
);
23414 areg
= gen_rtx_REG (Pmode
, 0);
23415 emit_move_insn (areg
, GEN_INT (offset
));
23417 /* AltiVec addressing mode is [reg+reg]. */
23418 mem
= gen_frame_mem (V4SImode
,
23419 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
23421 insn
= emit_move_insn (mem
, savereg
);
23423 /* When we split a VSX store into two insns, we need to make
23424 sure the DWARF info knows which register we are storing.
23425 Pass it in to be used on the appropriate note. */
23426 if (!BYTES_BIG_ENDIAN
23427 && GET_CODE (PATTERN (insn
)) == SET
23428 && GET_CODE (SET_SRC (PATTERN (insn
))) == VEC_SELECT
)
23429 split_reg
= savereg
;
23431 split_reg
= NULL_RTX
;
23433 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23434 areg
, GEN_INT (offset
), split_reg
);
23438 /* VRSAVE is a bit vector representing which AltiVec registers
23439 are used. The OS uses this to determine which vector
23440 registers to save on a context switch. We need to save
23441 VRSAVE on the stack frame, add whatever AltiVec registers we
23442 used in this function, and do the corresponding magic in the
23445 if (!WORLD_SAVE_P (info
)
23447 && TARGET_ALTIVEC_VRSAVE
23448 && info
->vrsave_mask
!= 0)
23454 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
23455 be using r12 as frame_reg_rtx and r11 as the static chain
23456 pointer for nested functions. */
23458 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23459 && !using_static_chain_p
)
23461 else if (REGNO (frame_reg_rtx
) == 12)
23464 if (using_static_chain_p
)
23468 NOT_INUSE (save_regno
);
23469 reg
= gen_rtx_REG (SImode
, save_regno
);
23470 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
23472 emit_insn (gen_get_vrsave_internal (reg
));
23474 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
23477 offset
= info
->vrsave_save_offset
+ frame_off
;
23478 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
23480 /* Include the registers in the mask. */
23481 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
23483 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
23486 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
23487 if (!TARGET_SINGLE_PIC_BASE
23488 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
23489 || (DEFAULT_ABI
== ABI_V4
23490 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
23491 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
23493 /* If emit_load_toc_table will use the link register, we need to save
23494 it. We use R12 for this purpose because emit_load_toc_table
23495 can use register 0. This allows us to use a plain 'blr' to return
23496 from the procedure more often. */
23497 int save_LR_around_toc_setup
= (TARGET_ELF
23498 && DEFAULT_ABI
== ABI_V4
23500 && ! info
->lr_save_p
23501 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
23502 if (save_LR_around_toc_setup
)
23504 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23505 rtx tmp
= gen_rtx_REG (Pmode
, 12);
23507 insn
= emit_move_insn (tmp
, lr
);
23508 RTX_FRAME_RELATED_P (insn
) = 1;
23510 rs6000_emit_load_toc_table (TRUE
);
23512 insn
= emit_move_insn (lr
, tmp
);
23513 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23514 RTX_FRAME_RELATED_P (insn
) = 1;
23517 rs6000_emit_load_toc_table (TRUE
);
23521 if (!TARGET_SINGLE_PIC_BASE
23522 && DEFAULT_ABI
== ABI_DARWIN
23523 && flag_pic
&& crtl
->uses_pic_offset_table
)
23525 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23526 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
23528 /* Save and restore LR locally around this call (in R0). */
23529 if (!info
->lr_save_p
)
23530 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
23532 emit_insn (gen_load_macho_picbase (src
));
23534 emit_move_insn (gen_rtx_REG (Pmode
,
23535 RS6000_PIC_OFFSET_TABLE_REGNUM
),
23538 if (!info
->lr_save_p
)
23539 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
23543 /* If we need to, save the TOC register after doing the stack setup.
23544 Do not emit eh frame info for this save. The unwinder wants info,
23545 conceptually attached to instructions in this function, about
23546 register values in the caller of this function. This R2 may have
23547 already been changed from the value in the caller.
23548 We don't attempt to write accurate DWARF EH frame info for R2
23549 because code emitted by gcc for a (non-pointer) function call
23550 doesn't save and restore R2. Instead, R2 is managed out-of-line
23551 by a linker generated plt call stub when the function resides in
23552 a shared library. This behaviour is costly to describe in DWARF,
23553 both in terms of the size of DWARF info and the time taken in the
23554 unwinder to interpret it. R2 changes, apart from the
23555 calls_eh_return case earlier in this function, are handled by
23556 linux-unwind.h frob_update_context. */
23557 if (rs6000_save_toc_in_prologue_p ())
23559 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
23560 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
23564 /* Write function prologue. */
23567 rs6000_output_function_prologue (FILE *file
,
23568 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
23570 rs6000_stack_t
*info
= rs6000_stack_info ();
23572 if (TARGET_DEBUG_STACK
)
23573 debug_stack_info (info
);
23575 /* Write .extern for any function we will call to save and restore
23577 if (info
->first_fp_reg_save
< 64
23582 int regno
= info
->first_fp_reg_save
- 32;
23584 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
23586 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23587 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23588 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23589 fprintf (file
, "\t.extern %s\n", name
);
23591 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
23593 bool lr
= (info
->savres_strategy
23594 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
23595 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23596 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23597 fprintf (file
, "\t.extern %s\n", name
);
23601 /* ELFv2 ABI r2 setup code and local entry point. This must follow
23602 immediately after the global entry point label. */
23603 if (DEFAULT_ABI
== ABI_ELFv2
&& cfun
->machine
->r2_setup_needed
)
23605 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
23607 fprintf (file
, "0:\taddis 2,12,.TOC.-0b@ha\n");
23608 fprintf (file
, "\taddi 2,2,.TOC.-0b@l\n");
23610 fputs ("\t.localentry\t", file
);
23611 assemble_name (file
, name
);
23612 fputs (",.-", file
);
23613 assemble_name (file
, name
);
23614 fputs ("\n", file
);
23617 /* Output -mprofile-kernel code. This needs to be done here instead of
23618 in output_function_profile since it must go after the ELFv2 ABI
23619 local entry point. */
23620 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
23622 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
23623 gcc_assert (!TARGET_32BIT
);
23625 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
23626 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
23628 /* In the ELFv2 ABI we have no compiler stack word. It must be
23629 the resposibility of _mcount to preserve the static chain
23630 register if required. */
23631 if (DEFAULT_ABI
!= ABI_ELFv2
23632 && cfun
->static_chain_decl
!= NULL
)
23634 asm_fprintf (file
, "\tstd %s,24(%s)\n",
23635 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23636 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23637 asm_fprintf (file
, "\tld %s,24(%s)\n",
23638 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23641 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23644 rs6000_pic_labelno
++;
23647 /* Non-zero if vmx regs are restored before the frame pop, zero if
23648 we restore after the pop when possible. */
23649 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
23651 /* Restoring cr is a two step process: loading a reg from the frame
23652 save, then moving the reg to cr. For ABI_V4 we must let the
23653 unwinder know that the stack location is no longer valid at or
23654 before the stack deallocation, but we can't emit a cfa_restore for
23655 cr at the stack deallocation like we do for other registers.
23656 The trouble is that it is possible for the move to cr to be
23657 scheduled after the stack deallocation. So say exactly where cr
23658 is located on each of the two insns. */
23661 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
23663 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
23664 rtx reg
= gen_rtx_REG (SImode
, regno
);
23665 rtx insn
= emit_move_insn (reg
, mem
);
23667 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
23669 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23670 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
23672 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
23673 RTX_FRAME_RELATED_P (insn
) = 1;
23678 /* Reload CR from REG. */
23681 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
23686 if (using_mfcr_multiple
)
23688 for (i
= 0; i
< 8; i
++)
23689 if (save_reg_p (CR0_REGNO
+ i
))
23691 gcc_assert (count
);
23694 if (using_mfcr_multiple
&& count
> 1)
23700 p
= rtvec_alloc (count
);
23703 for (i
= 0; i
< 8; i
++)
23704 if (save_reg_p (CR0_REGNO
+ i
))
23706 rtvec r
= rtvec_alloc (2);
23707 RTVEC_ELT (r
, 0) = reg
;
23708 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
23709 RTVEC_ELT (p
, ndx
) =
23710 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
23711 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
23714 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23715 gcc_assert (ndx
== count
);
23717 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23718 CR field separately. */
23719 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23721 for (i
= 0; i
< 8; i
++)
23722 if (save_reg_p (CR0_REGNO
+ i
))
23723 add_reg_note (insn
, REG_CFA_RESTORE
,
23724 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23726 RTX_FRAME_RELATED_P (insn
) = 1;
23730 for (i
= 0; i
< 8; i
++)
23731 if (save_reg_p (CR0_REGNO
+ i
))
23733 rtx insn
= emit_insn (gen_movsi_to_cr_one
23734 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
23736 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23737 CR field separately, attached to the insn that in fact
23738 restores this particular CR field. */
23739 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23741 add_reg_note (insn
, REG_CFA_RESTORE
,
23742 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23744 RTX_FRAME_RELATED_P (insn
) = 1;
23748 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
23749 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
23750 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
23752 rtx insn
= get_last_insn ();
23753 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23755 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
23756 RTX_FRAME_RELATED_P (insn
) = 1;
23760 /* Like cr, the move to lr instruction can be scheduled after the
23761 stack deallocation, but unlike cr, its stack frame save is still
23762 valid. So we only need to emit the cfa_restore on the correct
23766 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
23768 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
23769 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23771 emit_move_insn (reg
, mem
);
23775 restore_saved_lr (int regno
, bool exit_func
)
23777 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23778 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23779 rtx insn
= emit_move_insn (lr
, reg
);
23781 if (!exit_func
&& flag_shrink_wrap
)
23783 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23784 RTX_FRAME_RELATED_P (insn
) = 1;
23789 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
23791 if (DEFAULT_ABI
== ABI_ELFv2
)
23794 for (i
= 0; i
< 8; i
++)
23795 if (save_reg_p (CR0_REGNO
+ i
))
23797 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
23798 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
23802 else if (info
->cr_save_p
)
23803 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23804 gen_rtx_REG (SImode
, CR2_REGNO
),
23807 if (info
->lr_save_p
)
23808 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23809 gen_rtx_REG (Pmode
, LR_REGNO
),
23811 return cfa_restores
;
23814 /* Return true if OFFSET from stack pointer can be clobbered by signals.
23815 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
23816 below stack pointer not cloberred by signals. */
23819 offset_below_red_zone_p (HOST_WIDE_INT offset
)
23821 return offset
< (DEFAULT_ABI
== ABI_V4
23823 : TARGET_32BIT
? -220 : -288);
23826 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
23829 emit_cfa_restores (rtx cfa_restores
)
23831 rtx insn
= get_last_insn ();
23832 rtx
*loc
= ®_NOTES (insn
);
23835 loc
= &XEXP (*loc
, 1);
23836 *loc
= cfa_restores
;
23837 RTX_FRAME_RELATED_P (insn
) = 1;
23840 /* Emit function epilogue as insns. */
23843 rs6000_emit_epilogue (int sibcall
)
23845 rs6000_stack_t
*info
;
23846 int restoring_GPRs_inline
;
23847 int restoring_FPRs_inline
;
23848 int using_load_multiple
;
23849 int using_mtcr_multiple
;
23850 int use_backchain_to_restore_sp
;
23853 HOST_WIDE_INT frame_off
= 0;
23854 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
23855 rtx frame_reg_rtx
= sp_reg_rtx
;
23856 rtx cfa_restores
= NULL_RTX
;
23858 rtx cr_save_reg
= NULL_RTX
;
23859 enum machine_mode reg_mode
= Pmode
;
23860 int reg_size
= TARGET_32BIT
? 4 : 8;
23863 unsigned ptr_regno
;
23865 info
= rs6000_stack_info ();
23867 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
23869 reg_mode
= V2SImode
;
23873 strategy
= info
->savres_strategy
;
23874 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
23875 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
23876 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
23877 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
23878 || rs6000_cpu
== PROCESSOR_PPC603
23879 || rs6000_cpu
== PROCESSOR_PPC750
23881 /* Restore via the backchain when we have a large frame, since this
23882 is more efficient than an addis, addi pair. The second condition
23883 here will not trigger at the moment; We don't actually need a
23884 frame pointer for alloca, but the generic parts of the compiler
23885 give us one anyway. */
23886 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
23887 || (cfun
->calls_alloca
23888 && !frame_pointer_needed
));
23889 restore_lr
= (info
->lr_save_p
23890 && (restoring_FPRs_inline
23891 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
23892 && (restoring_GPRs_inline
23893 || info
->first_fp_reg_save
< 64));
23895 if (WORLD_SAVE_P (info
))
23899 const char *alloc_rname
;
23902 /* eh_rest_world_r10 will return to the location saved in the LR
23903 stack slot (which is not likely to be our caller.)
23904 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
23905 rest_world is similar, except any R10 parameter is ignored.
23906 The exception-handling stuff that was here in 2.95 is no
23907 longer necessary. */
23911 + 32 - info
->first_gp_reg_save
23912 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
23913 + 63 + 1 - info
->first_fp_reg_save
);
23915 strcpy (rname
, ((crtl
->calls_eh_return
) ?
23916 "*eh_rest_world_r10" : "*rest_world"));
23917 alloc_rname
= ggc_strdup (rname
);
23920 RTVEC_ELT (p
, j
++) = ret_rtx
;
23921 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
23922 gen_rtx_REG (Pmode
,
23925 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
23926 /* The instruction pattern requires a clobber here;
23927 it is shared with the restVEC helper. */
23929 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
23932 /* CR register traditionally saved as CR2. */
23933 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
23935 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
23936 if (flag_shrink_wrap
)
23938 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23939 gen_rtx_REG (Pmode
, LR_REGNO
),
23941 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23945 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23947 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
23949 = gen_frame_load (reg
,
23950 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
23951 if (flag_shrink_wrap
)
23952 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23954 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
23956 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
23958 = gen_frame_load (reg
,
23959 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
23960 if (flag_shrink_wrap
)
23961 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23963 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
23965 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23966 ? DFmode
: SFmode
),
23967 info
->first_fp_reg_save
+ i
);
23969 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
23970 if (flag_shrink_wrap
)
23971 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23974 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
23976 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
23978 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
23980 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
23982 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
23983 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23985 if (flag_shrink_wrap
)
23987 REG_NOTES (insn
) = cfa_restores
;
23988 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
23989 RTX_FRAME_RELATED_P (insn
) = 1;
23994 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
23996 frame_off
= info
->total_size
;
23998 /* Restore AltiVec registers if we must do so before adjusting the
24000 if (TARGET_ALTIVEC_ABI
24001 && info
->altivec_size
!= 0
24002 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24003 || (DEFAULT_ABI
!= ABI_V4
24004 && offset_below_red_zone_p (info
->altivec_save_offset
))))
24007 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
24009 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
24010 if (use_backchain_to_restore_sp
)
24012 int frame_regno
= 11;
24014 if ((strategy
& REST_INLINE_VRS
) == 0)
24016 /* Of r11 and r12, select the one not clobbered by an
24017 out-of-line restore function for the frame register. */
24018 frame_regno
= 11 + 12 - scratch_regno
;
24020 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
24021 emit_move_insn (frame_reg_rtx
,
24022 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24025 else if (frame_pointer_needed
)
24026 frame_reg_rtx
= hard_frame_pointer_rtx
;
24028 if ((strategy
& REST_INLINE_VRS
) == 0)
24030 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24032 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24033 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24035 if (end_save
+ frame_off
!= 0)
24037 rtx offset
= GEN_INT (end_save
+ frame_off
);
24039 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24042 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24044 ptr_off
= -end_save
;
24045 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24046 info
->altivec_save_offset
+ ptr_off
,
24047 0, V4SImode
, SAVRES_VR
);
24051 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24052 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24054 rtx addr
, areg
, mem
, reg
;
24056 areg
= gen_rtx_REG (Pmode
, 0);
24058 (areg
, GEN_INT (info
->altivec_save_offset
24060 + 16 * (i
- info
->first_altivec_reg_save
)));
24062 /* AltiVec addressing mode is [reg+reg]. */
24063 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
24064 mem
= gen_frame_mem (V4SImode
, addr
);
24066 reg
= gen_rtx_REG (V4SImode
, i
);
24067 emit_move_insn (reg
, mem
);
24071 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24072 if (((strategy
& REST_INLINE_VRS
) == 0
24073 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
24074 && (flag_shrink_wrap
24075 || (offset_below_red_zone_p
24076 (info
->altivec_save_offset
24077 + 16 * (i
- info
->first_altivec_reg_save
)))))
24079 rtx reg
= gen_rtx_REG (V4SImode
, i
);
24080 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24084 /* Restore VRSAVE if we must do so before adjusting the stack. */
24086 && TARGET_ALTIVEC_VRSAVE
24087 && info
->vrsave_mask
!= 0
24088 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24089 || (DEFAULT_ABI
!= ABI_V4
24090 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
24094 if (frame_reg_rtx
== sp_reg_rtx
)
24096 if (use_backchain_to_restore_sp
)
24098 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24099 emit_move_insn (frame_reg_rtx
,
24100 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24103 else if (frame_pointer_needed
)
24104 frame_reg_rtx
= hard_frame_pointer_rtx
;
24107 reg
= gen_rtx_REG (SImode
, 12);
24108 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24109 info
->vrsave_save_offset
+ frame_off
));
24111 emit_insn (generate_set_vrsave (reg
, info
, 1));
24115 /* If we have a large stack frame, restore the old stack pointer
24116 using the backchain. */
24117 if (use_backchain_to_restore_sp
)
24119 if (frame_reg_rtx
== sp_reg_rtx
)
24121 /* Under V.4, don't reset the stack pointer until after we're done
24122 loading the saved registers. */
24123 if (DEFAULT_ABI
== ABI_V4
)
24124 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24126 insn
= emit_move_insn (frame_reg_rtx
,
24127 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24130 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24131 && DEFAULT_ABI
== ABI_V4
)
24132 /* frame_reg_rtx has been set up by the altivec restore. */
24136 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
24137 frame_reg_rtx
= sp_reg_rtx
;
24140 /* If we have a frame pointer, we can restore the old stack pointer
24142 else if (frame_pointer_needed
)
24144 frame_reg_rtx
= sp_reg_rtx
;
24145 if (DEFAULT_ABI
== ABI_V4
)
24146 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24147 /* Prevent reordering memory accesses against stack pointer restore. */
24148 else if (cfun
->calls_alloca
24149 || offset_below_red_zone_p (-info
->total_size
))
24150 rs6000_emit_stack_tie (frame_reg_rtx
, true);
24152 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
24153 GEN_INT (info
->total_size
)));
24156 else if (info
->push_p
24157 && DEFAULT_ABI
!= ABI_V4
24158 && !crtl
->calls_eh_return
)
24160 /* Prevent reordering memory accesses against stack pointer restore. */
24161 if (cfun
->calls_alloca
24162 || offset_below_red_zone_p (-info
->total_size
))
24163 rs6000_emit_stack_tie (frame_reg_rtx
, false);
24164 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
24165 GEN_INT (info
->total_size
)));
24168 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
24172 REG_NOTES (insn
) = cfa_restores
;
24173 cfa_restores
= NULL_RTX
;
24175 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24176 RTX_FRAME_RELATED_P (insn
) = 1;
24179 /* Restore AltiVec registers if we have not done so already. */
24180 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24181 && TARGET_ALTIVEC_ABI
24182 && info
->altivec_size
!= 0
24183 && (DEFAULT_ABI
== ABI_V4
24184 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
24188 if ((strategy
& REST_INLINE_VRS
) == 0)
24190 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24192 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24193 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
24194 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24196 if (end_save
+ frame_off
!= 0)
24198 rtx offset
= GEN_INT (end_save
+ frame_off
);
24200 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24203 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24205 ptr_off
= -end_save
;
24206 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24207 info
->altivec_save_offset
+ ptr_off
,
24208 0, V4SImode
, SAVRES_VR
);
24209 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
24211 /* Frame reg was clobbered by out-of-line save. Restore it
24212 from ptr_reg, and if we are calling out-of-line gpr or
24213 fpr restore set up the correct pointer and offset. */
24214 unsigned newptr_regno
= 1;
24215 if (!restoring_GPRs_inline
)
24217 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
24218 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
24219 newptr_regno
= ptr_regno_for_savres (sel
);
24220 end_save
= info
->gp_save_offset
+ info
->gp_size
;
24222 else if (!restoring_FPRs_inline
)
24224 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
24225 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24226 newptr_regno
= ptr_regno_for_savres (sel
);
24227 end_save
= info
->gp_save_offset
+ info
->gp_size
;
24230 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
24231 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
24233 if (end_save
+ ptr_off
!= 0)
24235 rtx offset
= GEN_INT (end_save
+ ptr_off
);
24237 frame_off
= -end_save
;
24238 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
24242 frame_off
= ptr_off
;
24243 emit_move_insn (frame_reg_rtx
, ptr_reg
);
24249 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24250 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24252 rtx addr
, areg
, mem
, reg
;
24254 areg
= gen_rtx_REG (Pmode
, 0);
24256 (areg
, GEN_INT (info
->altivec_save_offset
24258 + 16 * (i
- info
->first_altivec_reg_save
)));
24260 /* AltiVec addressing mode is [reg+reg]. */
24261 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
24262 mem
= gen_frame_mem (V4SImode
, addr
);
24264 reg
= gen_rtx_REG (V4SImode
, i
);
24265 emit_move_insn (reg
, mem
);
24269 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24270 if (((strategy
& REST_INLINE_VRS
) == 0
24271 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
24272 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
24274 rtx reg
= gen_rtx_REG (V4SImode
, i
);
24275 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24279 /* Restore VRSAVE if we have not done so already. */
24280 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24282 && TARGET_ALTIVEC_VRSAVE
24283 && info
->vrsave_mask
!= 0
24284 && (DEFAULT_ABI
== ABI_V4
24285 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
24289 reg
= gen_rtx_REG (SImode
, 12);
24290 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24291 info
->vrsave_save_offset
+ frame_off
));
24293 emit_insn (generate_set_vrsave (reg
, info
, 1));
24296 /* If we exit by an out-of-line restore function on ABI_V4 then that
24297 function will deallocate the stack, so we don't need to worry
24298 about the unwinder restoring cr from an invalid stack frame
24300 exit_func
= (!restoring_FPRs_inline
24301 || (!restoring_GPRs_inline
24302 && info
->first_fp_reg_save
== 64));
24304 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
24305 *separate* slots if the routine calls __builtin_eh_return, so
24306 that they can be independently restored by the unwinder. */
24307 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
24309 int i
, cr_off
= info
->ehcr_offset
;
24311 for (i
= 0; i
< 8; i
++)
24312 if (!call_used_regs
[CR0_REGNO
+ i
])
24314 rtx reg
= gen_rtx_REG (SImode
, 0);
24315 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24316 cr_off
+ frame_off
));
24318 insn
= emit_insn (gen_movsi_to_cr_one
24319 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
24321 if (!exit_func
&& flag_shrink_wrap
)
24323 add_reg_note (insn
, REG_CFA_RESTORE
,
24324 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
24326 RTX_FRAME_RELATED_P (insn
) = 1;
24329 cr_off
+= reg_size
;
24333 /* Get the old lr if we saved it. If we are restoring registers
24334 out-of-line, then the out-of-line routines can do this for us. */
24335 if (restore_lr
&& restoring_GPRs_inline
)
24336 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24338 /* Get the old cr if we saved it. */
24339 if (info
->cr_save_p
)
24341 unsigned cr_save_regno
= 12;
24343 if (!restoring_GPRs_inline
)
24345 /* Ensure we don't use the register used by the out-of-line
24346 gpr register restore below. */
24347 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
24348 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
24349 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
24351 if (gpr_ptr_regno
== 12)
24352 cr_save_regno
= 11;
24353 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
24355 else if (REGNO (frame_reg_rtx
) == 12)
24356 cr_save_regno
= 11;
24358 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
24359 info
->cr_save_offset
+ frame_off
,
24363 /* Set LR here to try to overlap restores below. */
24364 if (restore_lr
&& restoring_GPRs_inline
)
24365 restore_saved_lr (0, exit_func
);
24367 /* Load exception handler data registers, if needed. */
24368 if (crtl
->calls_eh_return
)
24370 unsigned int i
, regno
;
24374 rtx reg
= gen_rtx_REG (reg_mode
, 2);
24375 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24376 frame_off
+ RS6000_TOC_SAVE_SLOT
));
24383 regno
= EH_RETURN_DATA_REGNO (i
);
24384 if (regno
== INVALID_REGNUM
)
24387 /* Note: possible use of r0 here to address SPE regs. */
24388 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
24389 info
->ehrd_offset
+ frame_off
24390 + reg_size
* (int) i
);
24392 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
24396 /* Restore GPRs. This is done as a PARALLEL if we are using
24397 the load-multiple instructions. */
24399 && info
->spe_64bit_regs_used
24400 && info
->first_gp_reg_save
!= 32)
24402 /* Determine whether we can address all of the registers that need
24403 to be saved with an offset from frame_reg_rtx that fits in
24404 the small const field for SPE memory instructions. */
24405 int spe_regs_addressable
24406 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
24407 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
24408 && restoring_GPRs_inline
);
24410 if (!spe_regs_addressable
)
24412 int ool_adjust
= 0;
24413 rtx old_frame_reg_rtx
= frame_reg_rtx
;
24414 /* Make r11 point to the start of the SPE save area. We worried about
24415 not clobbering it when we were saving registers in the prologue.
24416 There's no need to worry here because the static chain is passed
24417 anew to every function. */
24419 if (!restoring_GPRs_inline
)
24420 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
24421 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24422 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
24423 GEN_INT (info
->spe_gp_save_offset
24426 /* Keep the invariant that frame_reg_rtx + frame_off points
24427 at the top of the stack frame. */
24428 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
24431 if (restoring_GPRs_inline
)
24433 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
24435 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24436 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24438 rtx offset
, addr
, mem
, reg
;
24440 /* We're doing all this to ensure that the immediate offset
24441 fits into the immediate field of 'evldd'. */
24442 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
24444 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
24445 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
24446 mem
= gen_rtx_MEM (V2SImode
, addr
);
24447 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
24449 emit_move_insn (reg
, mem
);
24453 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
24454 info
->spe_gp_save_offset
+ frame_off
,
24455 info
->lr_save_offset
+ frame_off
,
24457 SAVRES_GPR
| SAVRES_LR
);
24459 else if (!restoring_GPRs_inline
)
24461 /* We are jumping to an out-of-line function. */
24463 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
24464 bool can_use_exit
= end_save
== 0;
24465 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
24468 /* Emit stack reset code if we need it. */
24469 ptr_regno
= ptr_regno_for_savres (sel
);
24470 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
24472 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24473 else if (end_save
+ frame_off
!= 0)
24474 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
24475 GEN_INT (end_save
+ frame_off
)));
24476 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
24477 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24478 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24479 frame_off
= -end_save
;
24481 if (can_use_exit
&& info
->cr_save_p
)
24482 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
24484 ptr_off
= -end_save
;
24485 rs6000_emit_savres_rtx (info
, ptr_reg
,
24486 info
->gp_save_offset
+ ptr_off
,
24487 info
->lr_save_offset
+ ptr_off
,
24490 else if (using_load_multiple
)
24493 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
24494 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24496 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24498 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
24499 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24503 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24504 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24505 emit_insn (gen_frame_load
24506 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24508 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
24511 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24513 /* If the frame pointer was used then we can't delay emitting
24514 a REG_CFA_DEF_CFA note. This must happen on the insn that
24515 restores the frame pointer, r31. We may have already emitted
24516 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
24517 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
24518 be harmless if emitted. */
24519 if (frame_pointer_needed
)
24521 insn
= get_last_insn ();
24522 add_reg_note (insn
, REG_CFA_DEF_CFA
,
24523 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
24524 RTX_FRAME_RELATED_P (insn
) = 1;
24527 /* Set up cfa_restores. We always need these when
24528 shrink-wrapping. If not shrink-wrapping then we only need
24529 the cfa_restore when the stack location is no longer valid.
24530 The cfa_restores must be emitted on or before the insn that
24531 invalidates the stack, and of course must not be emitted
24532 before the insn that actually does the restore. The latter
24533 is why it is a bad idea to emit the cfa_restores as a group
24534 on the last instruction here that actually does a restore:
24535 That insn may be reordered with respect to others doing
24537 if (flag_shrink_wrap
24538 && !restoring_GPRs_inline
24539 && info
->first_fp_reg_save
== 64)
24540 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24542 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
24543 if (!restoring_GPRs_inline
24544 || using_load_multiple
24545 || rs6000_reg_live_or_pic_offset_p (i
))
24547 rtx reg
= gen_rtx_REG (reg_mode
, i
);
24549 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24553 if (!restoring_GPRs_inline
24554 && info
->first_fp_reg_save
== 64)
24556 /* We are jumping to an out-of-line function. */
24558 emit_cfa_restores (cfa_restores
);
24562 if (restore_lr
&& !restoring_GPRs_inline
)
24564 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24565 restore_saved_lr (0, exit_func
);
24568 /* Restore fpr's if we need to do it without calling a function. */
24569 if (restoring_FPRs_inline
)
24570 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24571 if (save_reg_p (info
->first_fp_reg_save
+ i
))
24573 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24574 ? DFmode
: SFmode
),
24575 info
->first_fp_reg_save
+ i
);
24576 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24577 info
->fp_save_offset
+ frame_off
+ 8 * i
));
24578 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24579 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24582 /* If we saved cr, restore it here. Just those that were used. */
24583 if (info
->cr_save_p
)
24584 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
24586 /* If this is V.4, unwind the stack pointer after all of the loads
24587 have been done, or set up r11 if we are restoring fp out of line. */
24589 if (!restoring_FPRs_inline
)
24591 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24592 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24593 ptr_regno
= ptr_regno_for_savres (sel
);
24596 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24597 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24600 if (insn
&& restoring_FPRs_inline
)
24604 REG_NOTES (insn
) = cfa_restores
;
24605 cfa_restores
= NULL_RTX
;
24607 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24608 RTX_FRAME_RELATED_P (insn
) = 1;
24611 if (crtl
->calls_eh_return
)
24613 rtx sa
= EH_RETURN_STACKADJ_RTX
;
24614 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
24620 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24621 if (! restoring_FPRs_inline
)
24623 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
24624 RTVEC_ELT (p
, 0) = ret_rtx
;
24630 /* We can't hang the cfa_restores off a simple return,
24631 since the shrink-wrap code sometimes uses an existing
24632 return. This means there might be a path from
24633 pre-prologue code to this return, and dwarf2cfi code
24634 wants the eh_frame unwinder state to be the same on
24635 all paths to any point. So we need to emit the
24636 cfa_restores before the return. For -m64 we really
24637 don't need epilogue cfa_restores at all, except for
24638 this irritating dwarf2cfi with shrink-wrap
24639 requirement; The stack red-zone means eh_frame info
24640 from the prologue telling the unwinder to restore
24641 from the stack is perfectly good right to the end of
24643 emit_insn (gen_blockage ());
24644 emit_cfa_restores (cfa_restores
);
24645 cfa_restores
= NULL_RTX
;
24647 p
= rtvec_alloc (2);
24648 RTVEC_ELT (p
, 0) = simple_return_rtx
;
24651 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
24652 ? gen_rtx_USE (VOIDmode
,
24653 gen_rtx_REG (Pmode
, LR_REGNO
))
24654 : gen_rtx_CLOBBER (VOIDmode
,
24655 gen_rtx_REG (Pmode
, LR_REGNO
)));
24657 /* If we have to restore more than two FP registers, branch to the
24658 restore function. It will return to our caller. */
24659 if (! restoring_FPRs_inline
)
24665 if (flag_shrink_wrap
)
24666 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24668 sym
= rs6000_savres_routine_sym (info
,
24669 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
24670 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
24671 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
24672 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
24674 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24676 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
24678 RTVEC_ELT (p
, i
+ 4)
24679 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
24680 if (flag_shrink_wrap
)
24681 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
24686 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24692 /* Ensure the cfa_restores are hung off an insn that won't
24693 be reordered above other restores. */
24694 emit_insn (gen_blockage ());
24696 emit_cfa_restores (cfa_restores
);
24700 /* Write function epilogue. */
24703 rs6000_output_function_epilogue (FILE *file
,
24704 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
24707 macho_branch_islands ();
24708 /* Mach-O doesn't support labels at the end of objects, so if
24709 it looks like we might want one, insert a NOP. */
24711 rtx insn
= get_last_insn ();
24712 rtx deleted_debug_label
= NULL_RTX
;
24715 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
24717 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
24718 notes only, instead set their CODE_LABEL_NUMBER to -1,
24719 otherwise there would be code generation differences
24720 in between -g and -g0. */
24721 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24722 deleted_debug_label
= insn
;
24723 insn
= PREV_INSN (insn
);
24728 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
24729 fputs ("\tnop\n", file
);
24730 else if (deleted_debug_label
)
24731 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
24732 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24733 CODE_LABEL_NUMBER (insn
) = -1;
24737 /* Output a traceback table here. See /usr/include/sys/debug.h for info
24740 We don't output a traceback table if -finhibit-size-directive was
24741 used. The documentation for -finhibit-size-directive reads
24742 ``don't output a @code{.size} assembler directive, or anything
24743 else that would cause trouble if the function is split in the
24744 middle, and the two halves are placed at locations far apart in
24745 memory.'' The traceback table has this property, since it
24746 includes the offset from the start of the function to the
24747 traceback table itself.
24749 System V.4 Powerpc's (and the embedded ABI derived from it) use a
24750 different traceback table. */
24751 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24752 && ! flag_inhibit_size_directive
24753 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
24755 const char *fname
= NULL
;
24756 const char *language_string
= lang_hooks
.name
;
24757 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
24759 int optional_tbtab
;
24760 rs6000_stack_t
*info
= rs6000_stack_info ();
24762 if (rs6000_traceback
== traceback_full
)
24763 optional_tbtab
= 1;
24764 else if (rs6000_traceback
== traceback_part
)
24765 optional_tbtab
= 0;
24767 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
24769 if (optional_tbtab
)
24771 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
24772 while (*fname
== '.') /* V.4 encodes . in the name */
24775 /* Need label immediately before tbtab, so we can compute
24776 its offset from the function start. */
24777 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
24778 ASM_OUTPUT_LABEL (file
, fname
);
24781 /* The .tbtab pseudo-op can only be used for the first eight
24782 expressions, since it can't handle the possibly variable
24783 length fields that follow. However, if you omit the optional
24784 fields, the assembler outputs zeros for all optional fields
24785 anyways, giving each variable length field is minimum length
24786 (as defined in sys/debug.h). Thus we can not use the .tbtab
24787 pseudo-op at all. */
24789 /* An all-zero word flags the start of the tbtab, for debuggers
24790 that have to find it by searching forward from the entry
24791 point or from the current pc. */
24792 fputs ("\t.long 0\n", file
);
24794 /* Tbtab format type. Use format type 0. */
24795 fputs ("\t.byte 0,", file
);
24797 /* Language type. Unfortunately, there does not seem to be any
24798 official way to discover the language being compiled, so we
24799 use language_string.
24800 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
24801 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
24802 a number, so for now use 9. LTO, Go, and UPC aren't assigned numbers
24803 either, so for now use 0. */
24804 if (! strcmp (language_string
, "GNU C")
24805 || ! strcmp (language_string
, "GNU GIMPLE")
24806 || ! strcmp (language_string
, "GNU Go")
24807 || ! strcmp (language_string
, "GNU UPC"))
24809 else if (! strcmp (language_string
, "GNU F77")
24810 || ! strcmp (language_string
, "GNU Fortran"))
24812 else if (! strcmp (language_string
, "GNU Pascal"))
24814 else if (! strcmp (language_string
, "GNU Ada"))
24816 else if (! strcmp (language_string
, "GNU C++")
24817 || ! strcmp (language_string
, "GNU Objective-C++"))
24819 else if (! strcmp (language_string
, "GNU Java"))
24821 else if (! strcmp (language_string
, "GNU Objective-C"))
24824 gcc_unreachable ();
24825 fprintf (file
, "%d,", i
);
24827 /* 8 single bit fields: global linkage (not set for C extern linkage,
24828 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
24829 from start of procedure stored in tbtab, internal function, function
24830 has controlled storage, function has no toc, function uses fp,
24831 function logs/aborts fp operations. */
24832 /* Assume that fp operations are used if any fp reg must be saved. */
24833 fprintf (file
, "%d,",
24834 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
24836 /* 6 bitfields: function is interrupt handler, name present in
24837 proc table, function calls alloca, on condition directives
24838 (controls stack walks, 3 bits), saves condition reg, saves
24840 /* The `function calls alloca' bit seems to be set whenever reg 31 is
24841 set up as a frame pointer, even when there is no alloca call. */
24842 fprintf (file
, "%d,",
24843 ((optional_tbtab
<< 6)
24844 | ((optional_tbtab
& frame_pointer_needed
) << 5)
24845 | (info
->cr_save_p
<< 1)
24846 | (info
->lr_save_p
)));
24848 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
24850 fprintf (file
, "%d,",
24851 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
24853 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
24854 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
24856 if (optional_tbtab
)
24858 /* Compute the parameter info from the function decl argument
24861 int next_parm_info_bit
= 31;
24863 for (decl
= DECL_ARGUMENTS (current_function_decl
);
24864 decl
; decl
= DECL_CHAIN (decl
))
24866 rtx parameter
= DECL_INCOMING_RTL (decl
);
24867 enum machine_mode mode
= GET_MODE (parameter
);
24869 if (GET_CODE (parameter
) == REG
)
24871 if (SCALAR_FLOAT_MODE_P (mode
))
24892 gcc_unreachable ();
24895 /* If only one bit will fit, don't or in this entry. */
24896 if (next_parm_info_bit
> 0)
24897 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
24898 next_parm_info_bit
-= 2;
24902 fixed_parms
+= ((GET_MODE_SIZE (mode
)
24903 + (UNITS_PER_WORD
- 1))
24905 next_parm_info_bit
-= 1;
24911 /* Number of fixed point parameters. */
24912 /* This is actually the number of words of fixed point parameters; thus
24913 an 8 byte struct counts as 2; and thus the maximum value is 8. */
24914 fprintf (file
, "%d,", fixed_parms
);
24916 /* 2 bitfields: number of floating point parameters (7 bits), parameters
24918 /* This is actually the number of fp registers that hold parameters;
24919 and thus the maximum value is 13. */
24920 /* Set parameters on stack bit if parameters are not in their original
24921 registers, regardless of whether they are on the stack? Xlc
24922 seems to set the bit when not optimizing. */
24923 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
24925 if (! optional_tbtab
)
24928 /* Optional fields follow. Some are variable length. */
24930 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
24931 11 double float. */
24932 /* There is an entry for each parameter in a register, in the order that
24933 they occur in the parameter list. Any intervening arguments on the
24934 stack are ignored. If the list overflows a long (max possible length
24935 34 bits) then completely leave off all elements that don't fit. */
24936 /* Only emit this long if there was at least one parameter. */
24937 if (fixed_parms
|| float_parms
)
24938 fprintf (file
, "\t.long %d\n", parm_info
);
24940 /* Offset from start of code to tb table. */
24941 fputs ("\t.long ", file
);
24942 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
24943 RS6000_OUTPUT_BASENAME (file
, fname
);
24945 rs6000_output_function_entry (file
, fname
);
24948 /* Interrupt handler mask. */
24949 /* Omit this long, since we never set the interrupt handler bit
24952 /* Number of CTL (controlled storage) anchors. */
24953 /* Omit this long, since the has_ctl bit is never set above. */
24955 /* Displacement into stack of each CTL anchor. */
24956 /* Omit this list of longs, because there are no CTL anchors. */
24958 /* Length of function name. */
24961 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
24963 /* Function name. */
24964 assemble_string (fname
, strlen (fname
));
24966 /* Register for alloca automatic storage; this is always reg 31.
24967 Only emit this if the alloca bit was set above. */
24968 if (frame_pointer_needed
)
24969 fputs ("\t.byte 31\n", file
);
24971 fputs ("\t.align 2\n", file
);
24975 /* A C compound statement that outputs the assembler code for a thunk
24976 function, used to implement C++ virtual function calls with
24977 multiple inheritance. The thunk acts as a wrapper around a virtual
24978 function, adjusting the implicit object parameter before handing
24979 control off to the real function.
24981 First, emit code to add the integer DELTA to the location that
24982 contains the incoming first argument. Assume that this argument
24983 contains a pointer, and is the one used to pass the `this' pointer
24984 in C++. This is the incoming argument *before* the function
24985 prologue, e.g. `%o0' on a sparc. The addition must preserve the
24986 values of all other incoming arguments.
24988 After the addition, emit code to jump to FUNCTION, which is a
24989 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
24990 not touch the return address. Hence returning from FUNCTION will
24991 return to whoever called the current `thunk'.
24993 The effect must be as if FUNCTION had been called directly with the
24994 adjusted first argument. This macro is responsible for emitting
24995 all of the code for a thunk function; output_function_prologue()
24996 and output_function_epilogue() are not invoked.
24998 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
24999 been extracted from it.) It might possibly be useful on some
25000 targets, but probably not.
25002 If you do not define this macro, the target-independent code in the
25003 C++ frontend will generate a less efficient heavyweight thunk that
25004 calls FUNCTION instead of jumping to it. The generic approach does
25005 not support varargs. */
25008 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
25009 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
25012 rtx this_rtx
, insn
, funexp
;
25014 reload_completed
= 1;
25015 epilogue_completed
= 1;
25017 /* Mark the end of the (empty) prologue. */
25018 emit_note (NOTE_INSN_PROLOGUE_END
);
25020 /* Find the "this" pointer. If the function returns a structure,
25021 the structure return pointer is in r3. */
25022 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
25023 this_rtx
= gen_rtx_REG (Pmode
, 4);
25025 this_rtx
= gen_rtx_REG (Pmode
, 3);
25027 /* Apply the constant offset, if required. */
25029 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
25031 /* Apply the offset from the vtable, if required. */
25034 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
25035 rtx tmp
= gen_rtx_REG (Pmode
, 12);
25037 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
25038 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
25040 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
25041 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
25045 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
25047 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
25049 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
25052 /* Generate a tail call to the target function. */
25053 if (!TREE_USED (function
))
25055 assemble_external (function
);
25056 TREE_USED (function
) = 1;
25058 funexp
= XEXP (DECL_RTL (function
), 0);
25059 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
25062 if (MACHOPIC_INDIRECT
)
25063 funexp
= machopic_indirect_call_target (funexp
);
25066 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
25067 generate sibcall RTL explicitly. */
25068 insn
= emit_call_insn (
25069 gen_rtx_PARALLEL (VOIDmode
,
25071 gen_rtx_CALL (VOIDmode
,
25072 funexp
, const0_rtx
),
25073 gen_rtx_USE (VOIDmode
, const0_rtx
),
25074 gen_rtx_USE (VOIDmode
,
25075 gen_rtx_REG (SImode
,
25077 simple_return_rtx
)));
25078 SIBLING_CALL_P (insn
) = 1;
25081 /* Ensure we have a global entry point for the thunk. ??? We could
25082 avoid that if the target routine doesn't need a global entry point,
25083 but we do not know whether this is the case at this point. */
25084 if (DEFAULT_ABI
== ABI_ELFv2
)
25085 cfun
->machine
->r2_setup_needed
= true;
25087 /* Run just enough of rest_of_compilation to get the insns emitted.
25088 There's not really enough bulk here to make other passes such as
25089 instruction scheduling worth while. Note that use_thunk calls
25090 assemble_start_function and assemble_end_function. */
25091 insn
= get_insns ();
25092 shorten_branches (insn
);
25093 final_start_function (insn
, file
, 1);
25094 final (insn
, file
, 1);
25095 final_end_function ();
25097 reload_completed
= 0;
25098 epilogue_completed
= 0;
25101 /* A quick summary of the various types of 'constant-pool tables'
25104 Target Flags Name One table per
25105 AIX (none) AIX TOC object file
25106 AIX -mfull-toc AIX TOC object file
25107 AIX -mminimal-toc AIX minimal TOC translation unit
25108 SVR4/EABI (none) SVR4 SDATA object file
25109 SVR4/EABI -fpic SVR4 pic object file
25110 SVR4/EABI -fPIC SVR4 PIC translation unit
25111 SVR4/EABI -mrelocatable EABI TOC function
25112 SVR4/EABI -maix AIX TOC object file
25113 SVR4/EABI -maix -mminimal-toc
25114 AIX minimal TOC translation unit
25116 Name Reg. Set by entries contains:
25117 made by addrs? fp? sum?
25119 AIX TOC 2 crt0 as Y option option
25120 AIX minimal TOC 30 prolog gcc Y Y option
25121 SVR4 SDATA 13 crt0 gcc N Y N
25122 SVR4 pic 30 prolog ld Y not yet N
25123 SVR4 PIC 30 prolog gcc Y option option
25124 EABI TOC 30 prolog gcc Y option option
25128 /* Hash functions for the hash table. */
25131 rs6000_hash_constant (rtx k
)
25133 enum rtx_code code
= GET_CODE (k
);
25134 enum machine_mode mode
= GET_MODE (k
);
25135 unsigned result
= (code
<< 3) ^ mode
;
25136 const char *format
;
25139 format
= GET_RTX_FORMAT (code
);
25140 flen
= strlen (format
);
25146 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
25149 if (mode
!= VOIDmode
)
25150 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
25162 for (; fidx
< flen
; fidx
++)
25163 switch (format
[fidx
])
25168 const char *str
= XSTR (k
, fidx
);
25169 len
= strlen (str
);
25170 result
= result
* 613 + len
;
25171 for (i
= 0; i
< len
; i
++)
25172 result
= result
* 613 + (unsigned) str
[i
];
25177 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
25181 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
25184 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
25185 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
25189 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
25190 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
25197 gcc_unreachable ();
25204 toc_hash_function (const void *hash_entry
)
25206 const struct toc_hash_struct
*thc
=
25207 (const struct toc_hash_struct
*) hash_entry
;
25208 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
25211 /* Compare H1 and H2 for equivalence. */
25214 toc_hash_eq (const void *h1
, const void *h2
)
25216 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
25217 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
25219 if (((const struct toc_hash_struct
*) h1
)->key_mode
25220 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
25223 return rtx_equal_p (r1
, r2
);
25226 /* These are the names given by the C++ front-end to vtables, and
25227 vtable-like objects. Ideally, this logic should not be here;
25228 instead, there should be some programmatic way of inquiring as
25229 to whether or not an object is a vtable. */
25231 #define VTABLE_NAME_P(NAME) \
25232 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
25233 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
25234 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
25235 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
25236 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
25238 #ifdef NO_DOLLAR_IN_LABEL
25239 /* Return a GGC-allocated character string translating dollar signs in
25240 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
25243 rs6000_xcoff_strip_dollar (const char *name
)
25249 q
= (const char *) strchr (name
, '$');
25251 if (q
== 0 || q
== name
)
25254 len
= strlen (name
);
25255 strip
= XALLOCAVEC (char, len
+ 1);
25256 strcpy (strip
, name
);
25257 p
= strip
+ (q
- name
);
25261 p
= strchr (p
+ 1, '$');
25264 return ggc_alloc_string (strip
, len
);
25269 rs6000_output_symbol_ref (FILE *file
, rtx x
)
25271 /* Currently C++ toc references to vtables can be emitted before it
25272 is decided whether the vtable is public or private. If this is
25273 the case, then the linker will eventually complain that there is
25274 a reference to an unknown section. Thus, for vtables only,
25275 we emit the TOC reference to reference the symbol and not the
25277 const char *name
= XSTR (x
, 0);
25279 if (VTABLE_NAME_P (name
))
25281 RS6000_OUTPUT_BASENAME (file
, name
);
25284 assemble_name (file
, name
);
25287 /* Output a TOC entry. We derive the entry name from what is being
25291 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
25294 const char *name
= buf
;
25296 HOST_WIDE_INT offset
= 0;
25298 gcc_assert (!TARGET_NO_TOC
);
25300 /* When the linker won't eliminate them, don't output duplicate
25301 TOC entries (this happens on AIX if there is any kind of TOC,
25302 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
25304 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
25306 struct toc_hash_struct
*h
;
25309 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
25310 time because GGC is not initialized at that point. */
25311 if (toc_hash_table
== NULL
)
25312 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
25313 toc_hash_eq
, NULL
);
25315 h
= ggc_alloc_toc_hash_struct ();
25317 h
->key_mode
= mode
;
25318 h
->labelno
= labelno
;
25320 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
25321 if (*found
== NULL
)
25323 else /* This is indeed a duplicate.
25324 Set this label equal to that label. */
25326 fputs ("\t.set ", file
);
25327 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
25328 fprintf (file
, "%d,", labelno
);
25329 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
25330 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
25334 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
25335 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
25336 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
25338 fputs ("\t.set ", file
);
25339 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
25340 fprintf (file
, "%d,", labelno
);
25341 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
25342 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
25350 /* If we're going to put a double constant in the TOC, make sure it's
25351 aligned properly when strict alignment is on. */
25352 if (GET_CODE (x
) == CONST_DOUBLE
25353 && STRICT_ALIGNMENT
25354 && GET_MODE_BITSIZE (mode
) >= 64
25355 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
25356 ASM_OUTPUT_ALIGN (file
, 3);
25359 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
25361 /* Handle FP constants specially. Note that if we have a minimal
25362 TOC, things we put here aren't actually in the TOC, so we can allow
25364 if (GET_CODE (x
) == CONST_DOUBLE
&&
25365 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
25367 REAL_VALUE_TYPE rv
;
25370 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25371 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25372 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
25374 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
25378 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25379 fputs (DOUBLE_INT_ASM_OP
, file
);
25381 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
25382 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25383 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25384 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
25385 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
25386 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
25387 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
25388 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
25393 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25394 fputs ("\t.long ", file
);
25396 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
25397 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25398 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25399 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
25400 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25401 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25405 else if (GET_CODE (x
) == CONST_DOUBLE
&&
25406 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
25408 REAL_VALUE_TYPE rv
;
25411 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25413 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25414 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
25416 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
25420 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25421 fputs (DOUBLE_INT_ASM_OP
, file
);
25423 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
25424 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25425 fprintf (file
, "0x%lx%08lx\n",
25426 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
25427 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
25432 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25433 fputs ("\t.long ", file
);
25435 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
25436 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25437 fprintf (file
, "0x%lx,0x%lx\n",
25438 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25442 else if (GET_CODE (x
) == CONST_DOUBLE
&&
25443 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
25445 REAL_VALUE_TYPE rv
;
25448 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25449 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25450 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
25452 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
25456 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25457 fputs (DOUBLE_INT_ASM_OP
, file
);
25459 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
25460 if (WORDS_BIG_ENDIAN
)
25461 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
25463 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
25468 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25469 fputs ("\t.long ", file
);
25471 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
25472 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
25476 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
25478 unsigned HOST_WIDE_INT low
;
25479 HOST_WIDE_INT high
;
25481 low
= INTVAL (x
) & 0xffffffff;
25482 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
25484 /* TOC entries are always Pmode-sized, so when big-endian
25485 smaller integer constants in the TOC need to be padded.
25486 (This is still a win over putting the constants in
25487 a separate constant pool, because then we'd have
25488 to have both a TOC entry _and_ the actual constant.)
25490 For a 32-bit target, CONST_INT values are loaded and shifted
25491 entirely within `low' and can be stored in one TOC entry. */
25493 /* It would be easy to make this work, but it doesn't now. */
25494 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
25496 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
25499 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
25500 high
= (HOST_WIDE_INT
) low
>> 32;
25506 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25507 fputs (DOUBLE_INT_ASM_OP
, file
);
25509 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
25510 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25511 fprintf (file
, "0x%lx%08lx\n",
25512 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25517 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
25519 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25520 fputs ("\t.long ", file
);
25522 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
25523 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25524 fprintf (file
, "0x%lx,0x%lx\n",
25525 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25529 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25530 fputs ("\t.long ", file
);
25532 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
25533 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
25539 if (GET_CODE (x
) == CONST
)
25541 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
25542 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
25544 base
= XEXP (XEXP (x
, 0), 0);
25545 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
25548 switch (GET_CODE (base
))
25551 name
= XSTR (base
, 0);
25555 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
25556 CODE_LABEL_NUMBER (XEXP (base
, 0)));
25560 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
25564 gcc_unreachable ();
25567 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25568 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
25571 fputs ("\t.tc ", file
);
25572 RS6000_OUTPUT_BASENAME (file
, name
);
25575 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
25577 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
25579 /* Mark large TOC symbols on AIX with [TE] so they are mapped
25580 after other TOC symbols, reducing overflow of small TOC access
25581 to [TC] symbols. */
25582 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
25583 ? "[TE]," : "[TC],", file
);
25586 /* Currently C++ toc references to vtables can be emitted before it
25587 is decided whether the vtable is public or private. If this is
25588 the case, then the linker will eventually complain that there is
25589 a TOC reference to an unknown section. Thus, for vtables only,
25590 we emit the TOC reference to reference the symbol and not the
25592 if (VTABLE_NAME_P (name
))
25594 RS6000_OUTPUT_BASENAME (file
, name
);
25596 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
25597 else if (offset
> 0)
25598 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
25601 output_addr_const (file
, x
);
25604 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
25605 && SYMBOL_REF_TLS_MODEL (base
) != 0)
25607 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
25608 fputs ("@le", file
);
25609 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
25610 fputs ("@ie", file
);
25611 /* Use global-dynamic for local-dynamic. */
25612 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
25613 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
25616 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
25617 fputs ("\t.tc .", file
);
25618 RS6000_OUTPUT_BASENAME (file
, name
);
25619 fputs ("[TC],", file
);
25620 output_addr_const (file
, x
);
25621 fputs ("@m", file
);
25629 /* Output an assembler pseudo-op to write an ASCII string of N characters
25630 starting at P to FILE.
25632 On the RS/6000, we have to do this using the .byte operation and
25633 write out special characters outside the quoted string.
25634 Also, the assembler is broken; very long strings are truncated,
25635 so we must artificially break them up early. */
25638 output_ascii (FILE *file
, const char *p
, int n
)
25641 int i
, count_string
;
25642 const char *for_string
= "\t.byte \"";
25643 const char *for_decimal
= "\t.byte ";
25644 const char *to_close
= NULL
;
25647 for (i
= 0; i
< n
; i
++)
25650 if (c
>= ' ' && c
< 0177)
25653 fputs (for_string
, file
);
25656 /* Write two quotes to get one. */
25664 for_decimal
= "\"\n\t.byte ";
25668 if (count_string
>= 512)
25670 fputs (to_close
, file
);
25672 for_string
= "\t.byte \"";
25673 for_decimal
= "\t.byte ";
25681 fputs (for_decimal
, file
);
25682 fprintf (file
, "%d", c
);
25684 for_string
= "\n\t.byte \"";
25685 for_decimal
= ", ";
25691 /* Now close the string if we have written one. Then end the line. */
25693 fputs (to_close
, file
);
25696 /* Generate a unique section name for FILENAME for a section type
25697 represented by SECTION_DESC. Output goes into BUF.
25699 SECTION_DESC can be any string, as long as it is different for each
25700 possible section type.
25702 We name the section in the same manner as xlc. The name begins with an
25703 underscore followed by the filename (after stripping any leading directory
25704 names) with the last period replaced by the string SECTION_DESC. If
25705 FILENAME does not contain a period, SECTION_DESC is appended to the end of
25709 rs6000_gen_section_name (char **buf
, const char *filename
,
25710 const char *section_desc
)
25712 const char *q
, *after_last_slash
, *last_period
= 0;
25716 after_last_slash
= filename
;
25717 for (q
= filename
; *q
; q
++)
25720 after_last_slash
= q
+ 1;
25721 else if (*q
== '.')
25725 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
25726 *buf
= (char *) xmalloc (len
);
25731 for (q
= after_last_slash
; *q
; q
++)
25733 if (q
== last_period
)
25735 strcpy (p
, section_desc
);
25736 p
+= strlen (section_desc
);
25740 else if (ISALNUM (*q
))
25744 if (last_period
== 0)
25745 strcpy (p
, section_desc
);
25750 /* Emit profile function. */
25753 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
25755 /* Non-standard profiling for kernels, which just saves LR then calls
25756 _mcount without worrying about arg saves. The idea is to change
25757 the function prologue as little as possible as it isn't easy to
25758 account for arg save/restore code added just for _mcount. */
25759 if (TARGET_PROFILE_KERNEL
)
25762 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25764 #ifndef NO_PROFILE_COUNTERS
25765 # define NO_PROFILE_COUNTERS 0
25767 if (NO_PROFILE_COUNTERS
)
25768 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25769 LCT_NORMAL
, VOIDmode
, 0);
25773 const char *label_name
;
25776 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25777 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
25778 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
25780 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25781 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
25784 else if (DEFAULT_ABI
== ABI_DARWIN
)
25786 const char *mcount_name
= RS6000_MCOUNT
;
25787 int caller_addr_regno
= LR_REGNO
;
25789 /* Be conservative and always set this, at least for now. */
25790 crtl
->uses_pic_offset_table
= 1;
25793 /* For PIC code, set up a stub and collect the caller's address
25794 from r0, which is where the prologue puts it. */
25795 if (MACHOPIC_INDIRECT
25796 && crtl
->uses_pic_offset_table
)
25797 caller_addr_regno
= 0;
25799 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
25800 LCT_NORMAL
, VOIDmode
, 1,
25801 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
25805 /* Write function profiler code. */
25808 output_function_profiler (FILE *file
, int labelno
)
25812 switch (DEFAULT_ABI
)
25815 gcc_unreachable ();
25820 warning (0, "no profiling of 64-bit code for this ABI");
25823 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25824 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
25825 if (NO_PROFILE_COUNTERS
)
25827 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25828 reg_names
[0], reg_names
[1]);
25830 else if (TARGET_SECURE_PLT
&& flag_pic
)
25832 if (TARGET_LINK_STACK
)
25835 get_ppc476_thunk_name (name
);
25836 asm_fprintf (file
, "\tbl %s\n", name
);
25839 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
25840 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25841 reg_names
[0], reg_names
[1]);
25842 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
25843 asm_fprintf (file
, "\taddis %s,%s,",
25844 reg_names
[12], reg_names
[12]);
25845 assemble_name (file
, buf
);
25846 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
25847 assemble_name (file
, buf
);
25848 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
25850 else if (flag_pic
== 1)
25852 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
25853 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25854 reg_names
[0], reg_names
[1]);
25855 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
25856 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
25857 assemble_name (file
, buf
);
25858 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
25860 else if (flag_pic
> 1)
25862 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25863 reg_names
[0], reg_names
[1]);
25864 /* Now, we need to get the address of the label. */
25865 if (TARGET_LINK_STACK
)
25868 get_ppc476_thunk_name (name
);
25869 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
25870 assemble_name (file
, buf
);
25871 fputs ("-.\n1:", file
);
25872 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
25873 asm_fprintf (file
, "\taddi %s,%s,4\n",
25874 reg_names
[11], reg_names
[11]);
25878 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
25879 assemble_name (file
, buf
);
25880 fputs ("-.\n1:", file
);
25881 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
25883 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
25884 reg_names
[0], reg_names
[11]);
25885 asm_fprintf (file
, "\tadd %s,%s,%s\n",
25886 reg_names
[0], reg_names
[0], reg_names
[11]);
25890 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
25891 assemble_name (file
, buf
);
25892 fputs ("@ha\n", file
);
25893 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25894 reg_names
[0], reg_names
[1]);
25895 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
25896 assemble_name (file
, buf
);
25897 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
25900 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
25901 fprintf (file
, "\tbl %s%s\n",
25902 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
25908 /* Don't do anything, done in output_profile_hook (). */
25915 /* The following variable value is the last issued insn. */
25917 static rtx last_scheduled_insn
;
25919 /* The following variable helps to balance issuing of load and
25920 store instructions */
25922 static int load_store_pendulum
;
25924 /* Power4 load update and store update instructions are cracked into a
25925 load or store and an integer insn which are executed in the same cycle.
25926 Branches have their own dispatch slot which does not count against the
25927 GCC issue rate, but it changes the program flow so there are no other
25928 instructions to issue in this cycle. */
25931 rs6000_variable_issue_1 (rtx insn
, int more
)
25933 last_scheduled_insn
= insn
;
25934 if (GET_CODE (PATTERN (insn
)) == USE
25935 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25937 cached_can_issue_more
= more
;
25938 return cached_can_issue_more
;
25941 if (insn_terminates_group_p (insn
, current_group
))
25943 cached_can_issue_more
= 0;
25944 return cached_can_issue_more
;
25947 /* If no reservation, but reach here */
25948 if (recog_memoized (insn
) < 0)
25951 if (rs6000_sched_groups
)
25953 if (is_microcoded_insn (insn
))
25954 cached_can_issue_more
= 0;
25955 else if (is_cracked_insn (insn
))
25956 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
25958 cached_can_issue_more
= more
- 1;
25960 return cached_can_issue_more
;
25963 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
25966 cached_can_issue_more
= more
- 1;
25967 return cached_can_issue_more
;
25971 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
25973 int r
= rs6000_variable_issue_1 (insn
, more
);
25975 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
25979 /* Adjust the cost of a scheduling dependency. Return the new cost of
25980 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
25983 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
25985 enum attr_type attr_type
;
25987 if (! recog_memoized (insn
))
25990 switch (REG_NOTE_KIND (link
))
25994 /* Data dependency; DEP_INSN writes a register that INSN reads
25995 some cycles later. */
25997 /* Separate a load from a narrower, dependent store. */
25998 if (rs6000_sched_groups
25999 && GET_CODE (PATTERN (insn
)) == SET
26000 && GET_CODE (PATTERN (dep_insn
)) == SET
26001 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
26002 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
26003 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
26004 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
26007 attr_type
= get_attr_type (insn
);
26012 /* Tell the first scheduling pass about the latency between
26013 a mtctr and bctr (and mtlr and br/blr). The first
26014 scheduling pass will not know about this latency since
26015 the mtctr instruction, which has the latency associated
26016 to it, will be generated by reload. */
26019 /* Leave some extra cycles between a compare and its
26020 dependent branch, to inhibit expensive mispredicts. */
26021 if ((rs6000_cpu_attr
== CPU_PPC603
26022 || rs6000_cpu_attr
== CPU_PPC604
26023 || rs6000_cpu_attr
== CPU_PPC604E
26024 || rs6000_cpu_attr
== CPU_PPC620
26025 || rs6000_cpu_attr
== CPU_PPC630
26026 || rs6000_cpu_attr
== CPU_PPC750
26027 || rs6000_cpu_attr
== CPU_PPC7400
26028 || rs6000_cpu_attr
== CPU_PPC7450
26029 || rs6000_cpu_attr
== CPU_PPCE5500
26030 || rs6000_cpu_attr
== CPU_PPCE6500
26031 || rs6000_cpu_attr
== CPU_POWER4
26032 || rs6000_cpu_attr
== CPU_POWER5
26033 || rs6000_cpu_attr
== CPU_POWER7
26034 || rs6000_cpu_attr
== CPU_POWER8
26035 || rs6000_cpu_attr
== CPU_CELL
)
26036 && recog_memoized (dep_insn
)
26037 && (INSN_CODE (dep_insn
) >= 0))
26039 switch (get_attr_type (dep_insn
))
26043 case TYPE_DELAYED_COMPARE
:
26044 case TYPE_IMUL_COMPARE
:
26045 case TYPE_LMUL_COMPARE
:
26046 case TYPE_FPCOMPARE
:
26047 case TYPE_CR_LOGICAL
:
26048 case TYPE_DELAYED_CR
:
26057 case TYPE_STORE_UX
:
26059 case TYPE_FPSTORE_U
:
26060 case TYPE_FPSTORE_UX
:
26061 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26062 && recog_memoized (dep_insn
)
26063 && (INSN_CODE (dep_insn
) >= 0))
26066 if (GET_CODE (PATTERN (insn
)) != SET
)
26067 /* If this happens, we have to extend this to schedule
26068 optimally. Return default for now. */
26071 /* Adjust the cost for the case where the value written
26072 by a fixed point operation is used as the address
26073 gen value on a store. */
26074 switch (get_attr_type (dep_insn
))
26081 if (! store_data_bypass_p (dep_insn
, insn
))
26085 case TYPE_LOAD_EXT
:
26086 case TYPE_LOAD_EXT_U
:
26087 case TYPE_LOAD_EXT_UX
:
26088 case TYPE_VAR_SHIFT_ROTATE
:
26089 case TYPE_VAR_DELAYED_COMPARE
:
26091 if (! store_data_bypass_p (dep_insn
, insn
))
26097 case TYPE_FAST_COMPARE
:
26100 case TYPE_INSERT_WORD
:
26101 case TYPE_INSERT_DWORD
:
26102 case TYPE_FPLOAD_U
:
26103 case TYPE_FPLOAD_UX
:
26105 case TYPE_STORE_UX
:
26106 case TYPE_FPSTORE_U
:
26107 case TYPE_FPSTORE_UX
:
26109 if (! store_data_bypass_p (dep_insn
, insn
))
26117 case TYPE_IMUL_COMPARE
:
26118 case TYPE_LMUL_COMPARE
:
26120 if (! store_data_bypass_p (dep_insn
, insn
))
26126 if (! store_data_bypass_p (dep_insn
, insn
))
26132 if (! store_data_bypass_p (dep_insn
, insn
))
26145 case TYPE_LOAD_EXT
:
26146 case TYPE_LOAD_EXT_U
:
26147 case TYPE_LOAD_EXT_UX
:
26148 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26149 && recog_memoized (dep_insn
)
26150 && (INSN_CODE (dep_insn
) >= 0))
26153 /* Adjust the cost for the case where the value written
26154 by a fixed point instruction is used within the address
26155 gen portion of a subsequent load(u)(x) */
26156 switch (get_attr_type (dep_insn
))
26163 if (set_to_load_agen (dep_insn
, insn
))
26167 case TYPE_LOAD_EXT
:
26168 case TYPE_LOAD_EXT_U
:
26169 case TYPE_LOAD_EXT_UX
:
26170 case TYPE_VAR_SHIFT_ROTATE
:
26171 case TYPE_VAR_DELAYED_COMPARE
:
26173 if (set_to_load_agen (dep_insn
, insn
))
26179 case TYPE_FAST_COMPARE
:
26182 case TYPE_INSERT_WORD
:
26183 case TYPE_INSERT_DWORD
:
26184 case TYPE_FPLOAD_U
:
26185 case TYPE_FPLOAD_UX
:
26187 case TYPE_STORE_UX
:
26188 case TYPE_FPSTORE_U
:
26189 case TYPE_FPSTORE_UX
:
26191 if (set_to_load_agen (dep_insn
, insn
))
26199 case TYPE_IMUL_COMPARE
:
26200 case TYPE_LMUL_COMPARE
:
26202 if (set_to_load_agen (dep_insn
, insn
))
26208 if (set_to_load_agen (dep_insn
, insn
))
26214 if (set_to_load_agen (dep_insn
, insn
))
26225 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26226 && recog_memoized (dep_insn
)
26227 && (INSN_CODE (dep_insn
) >= 0)
26228 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
26235 /* Fall out to return default cost. */
26239 case REG_DEP_OUTPUT
:
26240 /* Output dependency; DEP_INSN writes a register that INSN writes some
26242 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26243 && recog_memoized (dep_insn
)
26244 && (INSN_CODE (dep_insn
) >= 0))
26246 attr_type
= get_attr_type (insn
);
26251 if (get_attr_type (dep_insn
) == TYPE_FP
)
26255 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
26263 /* Anti dependency; DEP_INSN reads a register that INSN writes some
26268 gcc_unreachable ();
26274 /* Debug version of rs6000_adjust_cost. */
26277 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
26279 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
26285 switch (REG_NOTE_KIND (link
))
26287 default: dep
= "unknown depencency"; break;
26288 case REG_DEP_TRUE
: dep
= "data dependency"; break;
26289 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
26290 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
26294 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
26295 "%s, insn:\n", ret
, cost
, dep
);
26303 /* The function returns a true if INSN is microcoded.
26304 Return false otherwise. */
26307 is_microcoded_insn (rtx insn
)
26309 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26310 || GET_CODE (PATTERN (insn
)) == USE
26311 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26314 if (rs6000_cpu_attr
== CPU_CELL
)
26315 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
26317 if (rs6000_sched_groups
26318 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
26320 enum attr_type type
= get_attr_type (insn
);
26321 if (type
== TYPE_LOAD_EXT_U
26322 || type
== TYPE_LOAD_EXT_UX
26323 || type
== TYPE_LOAD_UX
26324 || type
== TYPE_STORE_UX
26325 || type
== TYPE_MFCR
)
26332 /* The function returns true if INSN is cracked into 2 instructions
26333 by the processor (and therefore occupies 2 issue slots). */
26336 is_cracked_insn (rtx insn
)
26338 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26339 || GET_CODE (PATTERN (insn
)) == USE
26340 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26343 if (rs6000_sched_groups
26344 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
26346 enum attr_type type
= get_attr_type (insn
);
26347 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
26348 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
26349 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
26350 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
26351 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
26352 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
26353 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
26354 || type
== TYPE_INSERT_WORD
)
26361 /* The function returns true if INSN can be issued only from
26362 the branch slot. */
26365 is_branch_slot_insn (rtx insn
)
26367 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26368 || GET_CODE (PATTERN (insn
)) == USE
26369 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26372 if (rs6000_sched_groups
)
26374 enum attr_type type
= get_attr_type (insn
);
26375 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
26383 /* The function returns true if out_inst sets a value that is
26384 used in the address generation computation of in_insn */
26386 set_to_load_agen (rtx out_insn
, rtx in_insn
)
26388 rtx out_set
, in_set
;
26390 /* For performance reasons, only handle the simple case where
26391 both loads are a single_set. */
26392 out_set
= single_set (out_insn
);
26395 in_set
= single_set (in_insn
);
26397 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
26403 /* Try to determine base/offset/size parts of the given MEM.
26404 Return true if successful, false if all the values couldn't
26407 This function only looks for REG or REG+CONST address forms.
26408 REG+REG address form will return false. */
26411 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
26412 HOST_WIDE_INT
*size
)
26415 if MEM_SIZE_KNOWN_P (mem
)
26416 *size
= MEM_SIZE (mem
);
26420 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
26421 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
26423 addr_rtx
= (XEXP (mem
, 0));
26425 if (GET_CODE (addr_rtx
) == REG
)
26430 else if (GET_CODE (addr_rtx
) == PLUS
26431 && CONST_INT_P (XEXP (addr_rtx
, 1)))
26433 *base
= XEXP (addr_rtx
, 0);
26434 *offset
= INTVAL (XEXP (addr_rtx
, 1));
26442 /* The function returns true if the target storage location of
26443 mem1 is adjacent to the target storage location of mem2 */
26444 /* Return 1 if memory locations are adjacent. */
26447 adjacent_mem_locations (rtx mem1
, rtx mem2
)
26450 HOST_WIDE_INT off1
, size1
, off2
, size2
;
26452 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
26453 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
26454 return ((REGNO (reg1
) == REGNO (reg2
))
26455 && ((off1
+ size1
== off2
)
26456 || (off2
+ size2
== off1
)));
26461 /* This function returns true if it can be determined that the two MEM
26462 locations overlap by at least 1 byte based on base reg/offset/size. */
26465 mem_locations_overlap (rtx mem1
, rtx mem2
)
26468 HOST_WIDE_INT off1
, size1
, off2
, size2
;
26470 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
26471 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
26472 return ((REGNO (reg1
) == REGNO (reg2
))
26473 && (((off1
<= off2
) && (off1
+ size1
> off2
))
26474 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
26479 /* A C statement (sans semicolon) to update the integer scheduling
26480 priority INSN_PRIORITY (INSN). Increase the priority to execute the
26481 INSN earlier, reduce the priority to execute INSN later. Do not
26482 define this macro if you do not need to adjust the scheduling
26483 priorities of insns. */
26486 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
26488 rtx load_mem
, str_mem
;
26489 /* On machines (like the 750) which have asymmetric integer units,
26490 where one integer unit can do multiply and divides and the other
26491 can't, reduce the priority of multiply/divide so it is scheduled
26492 before other integer operations. */
26495 if (! INSN_P (insn
))
26498 if (GET_CODE (PATTERN (insn
)) == USE
)
26501 switch (rs6000_cpu_attr
) {
26503 switch (get_attr_type (insn
))
26510 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
26511 priority
, priority
);
26512 if (priority
>= 0 && priority
< 0x01000000)
26519 if (insn_must_be_first_in_group (insn
)
26520 && reload_completed
26521 && current_sched_info
->sched_max_insns_priority
26522 && rs6000_sched_restricted_insns_priority
)
26525 /* Prioritize insns that can be dispatched only in the first
26527 if (rs6000_sched_restricted_insns_priority
== 1)
26528 /* Attach highest priority to insn. This means that in
26529 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
26530 precede 'priority' (critical path) considerations. */
26531 return current_sched_info
->sched_max_insns_priority
;
26532 else if (rs6000_sched_restricted_insns_priority
== 2)
26533 /* Increase priority of insn by a minimal amount. This means that in
26534 haifa-sched.c:ready_sort(), only 'priority' (critical path)
26535 considerations precede dispatch-slot restriction considerations. */
26536 return (priority
+ 1);
26539 if (rs6000_cpu
== PROCESSOR_POWER6
26540 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
26541 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
26542 /* Attach highest priority to insn if the scheduler has just issued two
26543 stores and this instruction is a load, or two loads and this instruction
26544 is a store. Power6 wants loads and stores scheduled alternately
26546 return current_sched_info
->sched_max_insns_priority
;
26551 /* Return true if the instruction is nonpipelined on the Cell. */
26553 is_nonpipeline_insn (rtx insn
)
26555 enum attr_type type
;
26556 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26557 || GET_CODE (PATTERN (insn
)) == USE
26558 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26561 type
= get_attr_type (insn
);
26562 if (type
== TYPE_IMUL
26563 || type
== TYPE_IMUL2
26564 || type
== TYPE_IMUL3
26565 || type
== TYPE_LMUL
26566 || type
== TYPE_IDIV
26567 || type
== TYPE_LDIV
26568 || type
== TYPE_SDIV
26569 || type
== TYPE_DDIV
26570 || type
== TYPE_SSQRT
26571 || type
== TYPE_DSQRT
26572 || type
== TYPE_MFCR
26573 || type
== TYPE_MFCRF
26574 || type
== TYPE_MFJMPR
)
26582 /* Return how many instructions the machine can issue per cycle. */
26585 rs6000_issue_rate (void)
26587 /* Unless scheduling for register pressure, use issue rate of 1 for
26588 first scheduling pass to decrease degradation. */
26589 if (!reload_completed
&& !flag_sched_pressure
)
26592 switch (rs6000_cpu_attr
) {
26594 case CPU_PPC601
: /* ? */
26604 case CPU_PPCE300C2
:
26605 case CPU_PPCE300C3
:
26606 case CPU_PPCE500MC
:
26607 case CPU_PPCE500MC64
:
26630 /* Return how many instructions to look ahead for better insn
26634 rs6000_use_sched_lookahead (void)
26636 switch (rs6000_cpu_attr
)
26643 return (reload_completed
? 8 : 0);
26650 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
26652 rs6000_use_sched_lookahead_guard (rtx insn
)
26654 if (rs6000_cpu_attr
!= CPU_CELL
)
26657 if (insn
== NULL_RTX
|| !INSN_P (insn
))
26660 if (!reload_completed
26661 || is_nonpipeline_insn (insn
)
26662 || is_microcoded_insn (insn
))
26668 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
26669 and return true. */
26672 find_mem_ref (rtx pat
, rtx
*mem_ref
)
26677 /* stack_tie does not produce any real memory traffic. */
26678 if (tie_operand (pat
, VOIDmode
))
26681 if (GET_CODE (pat
) == MEM
)
26687 /* Recursively process the pattern. */
26688 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
26690 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
26694 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
26697 else if (fmt
[i
] == 'E')
26698 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
26700 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
26708 /* Determine if PAT is a PATTERN of a load insn. */
26711 is_load_insn1 (rtx pat
, rtx
*load_mem
)
26713 if (!pat
|| pat
== NULL_RTX
)
26716 if (GET_CODE (pat
) == SET
)
26717 return find_mem_ref (SET_SRC (pat
), load_mem
);
26719 if (GET_CODE (pat
) == PARALLEL
)
26723 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26724 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
26731 /* Determine if INSN loads from memory. */
26734 is_load_insn (rtx insn
, rtx
*load_mem
)
26736 if (!insn
|| !INSN_P (insn
))
26742 return is_load_insn1 (PATTERN (insn
), load_mem
);
26745 /* Determine if PAT is a PATTERN of a store insn. */
26748 is_store_insn1 (rtx pat
, rtx
*str_mem
)
26750 if (!pat
|| pat
== NULL_RTX
)
26753 if (GET_CODE (pat
) == SET
)
26754 return find_mem_ref (SET_DEST (pat
), str_mem
);
26756 if (GET_CODE (pat
) == PARALLEL
)
26760 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26761 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
26768 /* Determine if INSN stores to memory. */
26771 is_store_insn (rtx insn
, rtx
*str_mem
)
26773 if (!insn
|| !INSN_P (insn
))
26776 return is_store_insn1 (PATTERN (insn
), str_mem
);
26779 /* Returns whether the dependence between INSN and NEXT is considered
26780 costly by the given target. */
26783 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
26787 rtx load_mem
, str_mem
;
26789 /* If the flag is not enabled - no dependence is considered costly;
26790 allow all dependent insns in the same group.
26791 This is the most aggressive option. */
26792 if (rs6000_sched_costly_dep
== no_dep_costly
)
26795 /* If the flag is set to 1 - a dependence is always considered costly;
26796 do not allow dependent instructions in the same group.
26797 This is the most conservative option. */
26798 if (rs6000_sched_costly_dep
== all_deps_costly
)
26801 insn
= DEP_PRO (dep
);
26802 next
= DEP_CON (dep
);
26804 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
26805 && is_load_insn (next
, &load_mem
)
26806 && is_store_insn (insn
, &str_mem
))
26807 /* Prevent load after store in the same group. */
26810 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
26811 && is_load_insn (next
, &load_mem
)
26812 && is_store_insn (insn
, &str_mem
)
26813 && DEP_TYPE (dep
) == REG_DEP_TRUE
26814 && mem_locations_overlap(str_mem
, load_mem
))
26815 /* Prevent load after store in the same group if it is a true
26819 /* The flag is set to X; dependences with latency >= X are considered costly,
26820 and will not be scheduled in the same group. */
26821 if (rs6000_sched_costly_dep
<= max_dep_latency
26822 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
26828 /* Return the next insn after INSN that is found before TAIL is reached,
26829 skipping any "non-active" insns - insns that will not actually occupy
26830 an issue slot. Return NULL_RTX if such an insn is not found. */
26833 get_next_active_insn (rtx insn
, rtx tail
)
26835 if (insn
== NULL_RTX
|| insn
== tail
)
26840 insn
= NEXT_INSN (insn
);
26841 if (insn
== NULL_RTX
|| insn
== tail
)
26845 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
26846 || (NONJUMP_INSN_P (insn
)
26847 && GET_CODE (PATTERN (insn
)) != USE
26848 && GET_CODE (PATTERN (insn
)) != CLOBBER
26849 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
26855 /* We are about to begin issuing insns for this clock cycle. */
26858 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
26859 rtx
*ready ATTRIBUTE_UNUSED
,
26860 int *pn_ready ATTRIBUTE_UNUSED
,
26861 int clock_var ATTRIBUTE_UNUSED
)
26863 int n_ready
= *pn_ready
;
26866 fprintf (dump
, "// rs6000_sched_reorder :\n");
26868 /* Reorder the ready list, if the second to last ready insn
26869 is a nonepipeline insn. */
26870 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
26872 if (is_nonpipeline_insn (ready
[n_ready
- 1])
26873 && (recog_memoized (ready
[n_ready
- 2]) > 0))
26874 /* Simply swap first two insns. */
26876 rtx tmp
= ready
[n_ready
- 1];
26877 ready
[n_ready
- 1] = ready
[n_ready
- 2];
26878 ready
[n_ready
- 2] = tmp
;
26882 if (rs6000_cpu
== PROCESSOR_POWER6
)
26883 load_store_pendulum
= 0;
26885 return rs6000_issue_rate ();
26888 /* Like rs6000_sched_reorder, but called after issuing each insn. */
26891 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
26892 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
26895 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
26897 /* For Power6, we need to handle some special cases to try and keep the
26898 store queue from overflowing and triggering expensive flushes.
26900 This code monitors how load and store instructions are being issued
26901 and skews the ready list one way or the other to increase the likelihood
26902 that a desired instruction is issued at the proper time.
26904 A couple of things are done. First, we maintain a "load_store_pendulum"
26905 to track the current state of load/store issue.
26907 - If the pendulum is at zero, then no loads or stores have been
26908 issued in the current cycle so we do nothing.
26910 - If the pendulum is 1, then a single load has been issued in this
26911 cycle and we attempt to locate another load in the ready list to
26914 - If the pendulum is -2, then two stores have already been
26915 issued in this cycle, so we increase the priority of the first load
26916 in the ready list to increase it's likelihood of being chosen first
26919 - If the pendulum is -1, then a single store has been issued in this
26920 cycle and we attempt to locate another store in the ready list to
26921 issue with it, preferring a store to an adjacent memory location to
26922 facilitate store pairing in the store queue.
26924 - If the pendulum is 2, then two loads have already been
26925 issued in this cycle, so we increase the priority of the first store
26926 in the ready list to increase it's likelihood of being chosen first
26929 - If the pendulum < -2 or > 2, then do nothing.
26931 Note: This code covers the most common scenarios. There exist non
26932 load/store instructions which make use of the LSU and which
26933 would need to be accounted for to strictly model the behavior
26934 of the machine. Those instructions are currently unaccounted
26935 for to help minimize compile time overhead of this code.
26937 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
26941 rtx tmp
, load_mem
, str_mem
;
26943 if (is_store_insn (last_scheduled_insn
, &str_mem
))
26944 /* Issuing a store, swing the load_store_pendulum to the left */
26945 load_store_pendulum
--;
26946 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
26947 /* Issuing a load, swing the load_store_pendulum to the right */
26948 load_store_pendulum
++;
26950 return cached_can_issue_more
;
26952 /* If the pendulum is balanced, or there is only one instruction on
26953 the ready list, then all is well, so return. */
26954 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
26955 return cached_can_issue_more
;
26957 if (load_store_pendulum
== 1)
26959 /* A load has been issued in this cycle. Scan the ready list
26960 for another load to issue with it */
26965 if (is_load_insn (ready
[pos
], &load_mem
))
26967 /* Found a load. Move it to the head of the ready list,
26968 and adjust it's priority so that it is more likely to
26971 for (i
=pos
; i
<*pn_ready
-1; i
++)
26972 ready
[i
] = ready
[i
+ 1];
26973 ready
[*pn_ready
-1] = tmp
;
26975 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
26976 INSN_PRIORITY (tmp
)++;
26982 else if (load_store_pendulum
== -2)
26984 /* Two stores have been issued in this cycle. Increase the
26985 priority of the first load in the ready list to favor it for
26986 issuing in the next cycle. */
26991 if (is_load_insn (ready
[pos
], &load_mem
)
26993 && INSN_PRIORITY_KNOWN (ready
[pos
]))
26995 INSN_PRIORITY (ready
[pos
])++;
26997 /* Adjust the pendulum to account for the fact that a load
26998 was found and increased in priority. This is to prevent
26999 increasing the priority of multiple loads */
27000 load_store_pendulum
--;
27007 else if (load_store_pendulum
== -1)
27009 /* A store has been issued in this cycle. Scan the ready list for
27010 another store to issue with it, preferring a store to an adjacent
27012 int first_store_pos
= -1;
27018 if (is_store_insn (ready
[pos
], &str_mem
))
27021 /* Maintain the index of the first store found on the
27023 if (first_store_pos
== -1)
27024 first_store_pos
= pos
;
27026 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
27027 && adjacent_mem_locations (str_mem
, str_mem2
))
27029 /* Found an adjacent store. Move it to the head of the
27030 ready list, and adjust it's priority so that it is
27031 more likely to stay there */
27033 for (i
=pos
; i
<*pn_ready
-1; i
++)
27034 ready
[i
] = ready
[i
+ 1];
27035 ready
[*pn_ready
-1] = tmp
;
27037 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27038 INSN_PRIORITY (tmp
)++;
27040 first_store_pos
= -1;
27048 if (first_store_pos
>= 0)
27050 /* An adjacent store wasn't found, but a non-adjacent store was,
27051 so move the non-adjacent store to the front of the ready
27052 list, and adjust its priority so that it is more likely to
27054 tmp
= ready
[first_store_pos
];
27055 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
27056 ready
[i
] = ready
[i
+ 1];
27057 ready
[*pn_ready
-1] = tmp
;
27058 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27059 INSN_PRIORITY (tmp
)++;
27062 else if (load_store_pendulum
== 2)
27064 /* Two loads have been issued in this cycle. Increase the priority
27065 of the first store in the ready list to favor it for issuing in
27071 if (is_store_insn (ready
[pos
], &str_mem
)
27073 && INSN_PRIORITY_KNOWN (ready
[pos
]))
27075 INSN_PRIORITY (ready
[pos
])++;
27077 /* Adjust the pendulum to account for the fact that a store
27078 was found and increased in priority. This is to prevent
27079 increasing the priority of multiple stores */
27080 load_store_pendulum
++;
27089 return cached_can_issue_more
;
27092 /* Return whether the presence of INSN causes a dispatch group termination
27093 of group WHICH_GROUP.
27095 If WHICH_GROUP == current_group, this function will return true if INSN
27096 causes the termination of the current group (i.e, the dispatch group to
27097 which INSN belongs). This means that INSN will be the last insn in the
27098 group it belongs to.
27100 If WHICH_GROUP == previous_group, this function will return true if INSN
27101 causes the termination of the previous group (i.e, the dispatch group that
27102 precedes the group to which INSN belongs). This means that INSN will be
27103 the first insn in the group it belongs to). */
27106 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
27113 first
= insn_must_be_first_in_group (insn
);
27114 last
= insn_must_be_last_in_group (insn
);
27119 if (which_group
== current_group
)
27121 else if (which_group
== previous_group
)
27129 insn_must_be_first_in_group (rtx insn
)
27131 enum attr_type type
;
27135 || DEBUG_INSN_P (insn
)
27136 || GET_CODE (PATTERN (insn
)) == USE
27137 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27140 switch (rs6000_cpu
)
27142 case PROCESSOR_POWER5
:
27143 if (is_cracked_insn (insn
))
27145 case PROCESSOR_POWER4
:
27146 if (is_microcoded_insn (insn
))
27149 if (!rs6000_sched_groups
)
27152 type
= get_attr_type (insn
);
27159 case TYPE_DELAYED_CR
:
27160 case TYPE_CR_LOGICAL
:
27174 case PROCESSOR_POWER6
:
27175 type
= get_attr_type (insn
);
27179 case TYPE_INSERT_DWORD
:
27183 case TYPE_VAR_SHIFT_ROTATE
:
27190 case TYPE_INSERT_WORD
:
27191 case TYPE_DELAYED_COMPARE
:
27192 case TYPE_IMUL_COMPARE
:
27193 case TYPE_LMUL_COMPARE
:
27194 case TYPE_FPCOMPARE
:
27205 case TYPE_LOAD_EXT_UX
:
27207 case TYPE_STORE_UX
:
27208 case TYPE_FPLOAD_U
:
27209 case TYPE_FPLOAD_UX
:
27210 case TYPE_FPSTORE_U
:
27211 case TYPE_FPSTORE_UX
:
27217 case PROCESSOR_POWER7
:
27218 type
= get_attr_type (insn
);
27222 case TYPE_CR_LOGICAL
:
27229 case TYPE_DELAYED_COMPARE
:
27230 case TYPE_VAR_DELAYED_COMPARE
:
27236 case TYPE_LOAD_EXT
:
27237 case TYPE_LOAD_EXT_U
:
27238 case TYPE_LOAD_EXT_UX
:
27240 case TYPE_STORE_UX
:
27241 case TYPE_FPLOAD_U
:
27242 case TYPE_FPLOAD_UX
:
27243 case TYPE_FPSTORE_U
:
27244 case TYPE_FPSTORE_UX
:
27252 case PROCESSOR_POWER8
:
27253 type
= get_attr_type (insn
);
27257 case TYPE_CR_LOGICAL
:
27258 case TYPE_DELAYED_CR
:
27263 case TYPE_DELAYED_COMPARE
:
27264 case TYPE_VAR_DELAYED_COMPARE
:
27265 case TYPE_IMUL_COMPARE
:
27266 case TYPE_LMUL_COMPARE
:
27273 case TYPE_LOAD_EXT
:
27274 case TYPE_LOAD_EXT_U
:
27275 case TYPE_LOAD_EXT_UX
:
27276 case TYPE_STORE_UX
:
27277 case TYPE_VECSTORE
:
27293 insn_must_be_last_in_group (rtx insn
)
27295 enum attr_type type
;
27299 || DEBUG_INSN_P (insn
)
27300 || GET_CODE (PATTERN (insn
)) == USE
27301 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27304 switch (rs6000_cpu
) {
27305 case PROCESSOR_POWER4
:
27306 case PROCESSOR_POWER5
:
27307 if (is_microcoded_insn (insn
))
27310 if (is_branch_slot_insn (insn
))
27314 case PROCESSOR_POWER6
:
27315 type
= get_attr_type (insn
);
27322 case TYPE_VAR_SHIFT_ROTATE
:
27329 case TYPE_DELAYED_COMPARE
:
27330 case TYPE_IMUL_COMPARE
:
27331 case TYPE_LMUL_COMPARE
:
27332 case TYPE_FPCOMPARE
:
27346 case PROCESSOR_POWER7
:
27347 type
= get_attr_type (insn
);
27355 case TYPE_LOAD_EXT_U
:
27356 case TYPE_LOAD_EXT_UX
:
27357 case TYPE_STORE_UX
:
27363 case PROCESSOR_POWER8
:
27364 type
= get_attr_type (insn
);
27374 case TYPE_LOAD_EXT_U
:
27375 case TYPE_LOAD_EXT_UX
:
27376 case TYPE_STORE_UX
:
27389 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
27390 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
27393 is_costly_group (rtx
*group_insns
, rtx next_insn
)
27396 int issue_rate
= rs6000_issue_rate ();
27398 for (i
= 0; i
< issue_rate
; i
++)
27400 sd_iterator_def sd_it
;
27402 rtx insn
= group_insns
[i
];
27407 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
27409 rtx next
= DEP_CON (dep
);
27411 if (next
== next_insn
27412 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
27420 /* Utility of the function redefine_groups.
27421 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
27422 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
27423 to keep it "far" (in a separate group) from GROUP_INSNS, following
27424 one of the following schemes, depending on the value of the flag
27425 -minsert_sched_nops = X:
27426 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
27427 in order to force NEXT_INSN into a separate group.
27428 (2) X < sched_finish_regroup_exact: insert exactly X nops.
27429 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
27430 insertion (has a group just ended, how many vacant issue slots remain in the
27431 last group, and how many dispatch groups were encountered so far). */
27434 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
27435 rtx next_insn
, bool *group_end
, int can_issue_more
,
27440 int issue_rate
= rs6000_issue_rate ();
27441 bool end
= *group_end
;
27444 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
27445 return can_issue_more
;
27447 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
27448 return can_issue_more
;
27450 force
= is_costly_group (group_insns
, next_insn
);
27452 return can_issue_more
;
27454 if (sched_verbose
> 6)
27455 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
27456 *group_count
,can_issue_more
);
27458 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
27461 can_issue_more
= 0;
27463 /* Since only a branch can be issued in the last issue_slot, it is
27464 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
27465 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
27466 in this case the last nop will start a new group and the branch
27467 will be forced to the new group. */
27468 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
27471 /* Do we have a special group ending nop? */
27472 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
27473 || rs6000_cpu_attr
== CPU_POWER8
)
27475 nop
= gen_group_ending_nop ();
27476 emit_insn_before (nop
, next_insn
);
27477 can_issue_more
= 0;
27480 while (can_issue_more
> 0)
27483 emit_insn_before (nop
, next_insn
);
27491 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
27493 int n_nops
= rs6000_sched_insert_nops
;
27495 /* Nops can't be issued from the branch slot, so the effective
27496 issue_rate for nops is 'issue_rate - 1'. */
27497 if (can_issue_more
== 0)
27498 can_issue_more
= issue_rate
;
27500 if (can_issue_more
== 0)
27502 can_issue_more
= issue_rate
- 1;
27505 for (i
= 0; i
< issue_rate
; i
++)
27507 group_insns
[i
] = 0;
27514 emit_insn_before (nop
, next_insn
);
27515 if (can_issue_more
== issue_rate
- 1) /* new group begins */
27518 if (can_issue_more
== 0)
27520 can_issue_more
= issue_rate
- 1;
27523 for (i
= 0; i
< issue_rate
; i
++)
27525 group_insns
[i
] = 0;
27531 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
27534 /* Is next_insn going to start a new group? */
27537 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27538 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27539 || (can_issue_more
< issue_rate
&&
27540 insn_terminates_group_p (next_insn
, previous_group
)));
27541 if (*group_end
&& end
)
27544 if (sched_verbose
> 6)
27545 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
27546 *group_count
, can_issue_more
);
27547 return can_issue_more
;
27550 return can_issue_more
;
27553 /* This function tries to synch the dispatch groups that the compiler "sees"
27554 with the dispatch groups that the processor dispatcher is expected to
27555 form in practice. It tries to achieve this synchronization by forcing the
27556 estimated processor grouping on the compiler (as opposed to the function
27557 'pad_goups' which tries to force the scheduler's grouping on the processor).
27559 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
27560 examines the (estimated) dispatch groups that will be formed by the processor
27561 dispatcher. It marks these group boundaries to reflect the estimated
27562 processor grouping, overriding the grouping that the scheduler had marked.
27563 Depending on the value of the flag '-minsert-sched-nops' this function can
27564 force certain insns into separate groups or force a certain distance between
27565 them by inserting nops, for example, if there exists a "costly dependence"
27568 The function estimates the group boundaries that the processor will form as
27569 follows: It keeps track of how many vacant issue slots are available after
27570 each insn. A subsequent insn will start a new group if one of the following
27572 - no more vacant issue slots remain in the current dispatch group.
27573 - only the last issue slot, which is the branch slot, is vacant, but the next
27574 insn is not a branch.
27575 - only the last 2 or less issue slots, including the branch slot, are vacant,
27576 which means that a cracked insn (which occupies two issue slots) can't be
27577 issued in this group.
27578 - less than 'issue_rate' slots are vacant, and the next insn always needs to
27579 start a new group. */
27582 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27584 rtx insn
, next_insn
;
27586 int can_issue_more
;
27589 int group_count
= 0;
27593 issue_rate
= rs6000_issue_rate ();
27594 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
27595 for (i
= 0; i
< issue_rate
; i
++)
27597 group_insns
[i
] = 0;
27599 can_issue_more
= issue_rate
;
27601 insn
= get_next_active_insn (prev_head_insn
, tail
);
27604 while (insn
!= NULL_RTX
)
27606 slot
= (issue_rate
- can_issue_more
);
27607 group_insns
[slot
] = insn
;
27609 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27610 if (insn_terminates_group_p (insn
, current_group
))
27611 can_issue_more
= 0;
27613 next_insn
= get_next_active_insn (insn
, tail
);
27614 if (next_insn
== NULL_RTX
)
27615 return group_count
+ 1;
27617 /* Is next_insn going to start a new group? */
27619 = (can_issue_more
== 0
27620 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27621 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27622 || (can_issue_more
< issue_rate
&&
27623 insn_terminates_group_p (next_insn
, previous_group
)));
27625 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
27626 next_insn
, &group_end
, can_issue_more
,
27632 can_issue_more
= 0;
27633 for (i
= 0; i
< issue_rate
; i
++)
27635 group_insns
[i
] = 0;
27639 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
27640 PUT_MODE (next_insn
, VOIDmode
);
27641 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
27642 PUT_MODE (next_insn
, TImode
);
27645 if (can_issue_more
== 0)
27646 can_issue_more
= issue_rate
;
27649 return group_count
;
27652 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
27653 dispatch group boundaries that the scheduler had marked. Pad with nops
27654 any dispatch groups which have vacant issue slots, in order to force the
27655 scheduler's grouping on the processor dispatcher. The function
27656 returns the number of dispatch groups found. */
27659 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27661 rtx insn
, next_insn
;
27664 int can_issue_more
;
27666 int group_count
= 0;
27668 /* Initialize issue_rate. */
27669 issue_rate
= rs6000_issue_rate ();
27670 can_issue_more
= issue_rate
;
27672 insn
= get_next_active_insn (prev_head_insn
, tail
);
27673 next_insn
= get_next_active_insn (insn
, tail
);
27675 while (insn
!= NULL_RTX
)
27678 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27680 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
27682 if (next_insn
== NULL_RTX
)
27687 /* If the scheduler had marked group termination at this location
27688 (between insn and next_insn), and neither insn nor next_insn will
27689 force group termination, pad the group with nops to force group
27692 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27693 && !insn_terminates_group_p (insn
, current_group
)
27694 && !insn_terminates_group_p (next_insn
, previous_group
))
27696 if (!is_branch_slot_insn (next_insn
))
27699 while (can_issue_more
)
27702 emit_insn_before (nop
, next_insn
);
27707 can_issue_more
= issue_rate
;
27712 next_insn
= get_next_active_insn (insn
, tail
);
27715 return group_count
;
27718 /* We're beginning a new block. Initialize data structures as necessary. */
27721 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
27722 int sched_verbose ATTRIBUTE_UNUSED
,
27723 int max_ready ATTRIBUTE_UNUSED
)
27725 last_scheduled_insn
= NULL_RTX
;
27726 load_store_pendulum
= 0;
27729 /* The following function is called at the end of scheduling BB.
27730 After reload, it inserts nops at insn group bundling. */
27733 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
27738 fprintf (dump
, "=== Finishing schedule.\n");
27740 if (reload_completed
&& rs6000_sched_groups
)
27742 /* Do not run sched_finish hook when selective scheduling enabled. */
27743 if (sel_sched_p ())
27746 if (rs6000_sched_insert_nops
== sched_finish_none
)
27749 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27750 n_groups
= pad_groups (dump
, sched_verbose
,
27751 current_sched_info
->prev_head
,
27752 current_sched_info
->next_tail
);
27754 n_groups
= redefine_groups (dump
, sched_verbose
,
27755 current_sched_info
->prev_head
,
27756 current_sched_info
->next_tail
);
27758 if (sched_verbose
>= 6)
27760 fprintf (dump
, "ngroups = %d\n", n_groups
);
27761 print_rtl (dump
, current_sched_info
->prev_head
);
27762 fprintf (dump
, "Done finish_sched\n");
27767 struct _rs6000_sched_context
27769 short cached_can_issue_more
;
27770 rtx last_scheduled_insn
;
27771 int load_store_pendulum
;
27774 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
27775 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
27777 /* Allocate store for new scheduling context. */
27779 rs6000_alloc_sched_context (void)
27781 return xmalloc (sizeof (rs6000_sched_context_def
));
27784 /* If CLEAN_P is true then initializes _SC with clean data,
27785 and from the global context otherwise. */
27787 rs6000_init_sched_context (void *_sc
, bool clean_p
)
27789 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27793 sc
->cached_can_issue_more
= 0;
27794 sc
->last_scheduled_insn
= NULL_RTX
;
27795 sc
->load_store_pendulum
= 0;
27799 sc
->cached_can_issue_more
= cached_can_issue_more
;
27800 sc
->last_scheduled_insn
= last_scheduled_insn
;
27801 sc
->load_store_pendulum
= load_store_pendulum
;
27805 /* Sets the global scheduling context to the one pointed to by _SC. */
27807 rs6000_set_sched_context (void *_sc
)
27809 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27811 gcc_assert (sc
!= NULL
);
27813 cached_can_issue_more
= sc
->cached_can_issue_more
;
27814 last_scheduled_insn
= sc
->last_scheduled_insn
;
27815 load_store_pendulum
= sc
->load_store_pendulum
;
27820 rs6000_free_sched_context (void *_sc
)
27822 gcc_assert (_sc
!= NULL
);
27828 /* Length in units of the trampoline for entering a nested function. */
27831 rs6000_trampoline_size (void)
27835 switch (DEFAULT_ABI
)
27838 gcc_unreachable ();
27841 ret
= (TARGET_32BIT
) ? 12 : 24;
27845 gcc_assert (!TARGET_32BIT
);
27851 ret
= (TARGET_32BIT
) ? 40 : 48;
27858 /* Emit RTL insns to initialize the variable parts of a trampoline.
27859 FNADDR is an RTX for the address of the function's pure code.
27860 CXT is an RTX for the static chain value for the function. */
27863 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
27865 int regsize
= (TARGET_32BIT
) ? 4 : 8;
27866 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
27867 rtx ctx_reg
= force_reg (Pmode
, cxt
);
27868 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
27870 switch (DEFAULT_ABI
)
27873 gcc_unreachable ();
27875 /* Under AIX, just build the 3 word function descriptor */
27878 rtx fnmem
, fn_reg
, toc_reg
;
27880 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
27881 error ("You cannot take the address of a nested function if you use "
27882 "the -mno-pointers-to-nested-functions option.");
27884 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
27885 fn_reg
= gen_reg_rtx (Pmode
);
27886 toc_reg
= gen_reg_rtx (Pmode
);
27888 /* Macro to shorten the code expansions below. */
27889 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
27891 m_tramp
= replace_equiv_address (m_tramp
, addr
);
27893 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
27894 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
27895 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
27896 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
27897 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
27903 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
27907 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
27908 LCT_NORMAL
, VOIDmode
, 4,
27910 GEN_INT (rs6000_trampoline_size ()), SImode
,
27918 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
27919 identifier as an argument, so the front end shouldn't look it up. */
27922 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
27924 return is_attribute_p ("altivec", attr_id
);
27927 /* Handle the "altivec" attribute. The attribute may have
27928 arguments as follows:
27930 __attribute__((altivec(vector__)))
27931 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
27932 __attribute__((altivec(bool__))) (always followed by 'unsigned')
27934 and may appear more than once (e.g., 'vector bool char') in a
27935 given declaration. */
27938 rs6000_handle_altivec_attribute (tree
*node
,
27939 tree name ATTRIBUTE_UNUSED
,
27941 int flags ATTRIBUTE_UNUSED
,
27942 bool *no_add_attrs
)
27944 tree type
= *node
, result
= NULL_TREE
;
27945 enum machine_mode mode
;
27948 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
27949 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
27950 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
27953 while (POINTER_TYPE_P (type
)
27954 || TREE_CODE (type
) == FUNCTION_TYPE
27955 || TREE_CODE (type
) == METHOD_TYPE
27956 || TREE_CODE (type
) == ARRAY_TYPE
)
27957 type
= TREE_TYPE (type
);
27959 mode
= TYPE_MODE (type
);
27961 /* Check for invalid AltiVec type qualifiers. */
27962 if (type
== long_double_type_node
)
27963 error ("use of %<long double%> in AltiVec types is invalid");
27964 else if (type
== boolean_type_node
)
27965 error ("use of boolean types in AltiVec types is invalid");
27966 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
27967 error ("use of %<complex%> in AltiVec types is invalid");
27968 else if (DECIMAL_FLOAT_MODE_P (mode
))
27969 error ("use of decimal floating point types in AltiVec types is invalid");
27970 else if (!TARGET_VSX
)
27972 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
27975 error ("use of %<long%> in AltiVec types is invalid for "
27976 "64-bit code without -mvsx");
27977 else if (rs6000_warn_altivec_long
)
27978 warning (0, "use of %<long%> in AltiVec types is deprecated; "
27981 else if (type
== long_long_unsigned_type_node
27982 || type
== long_long_integer_type_node
)
27983 error ("use of %<long long%> in AltiVec types is invalid without "
27985 else if (type
== double_type_node
)
27986 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
27989 switch (altivec_type
)
27992 unsigned_p
= TYPE_UNSIGNED (type
);
27996 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
27999 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
28002 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
28005 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
28008 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
28010 case SFmode
: result
= V4SF_type_node
; break;
28011 case DFmode
: result
= V2DF_type_node
; break;
28012 /* If the user says 'vector int bool', we may be handed the 'bool'
28013 attribute _before_ the 'vector' attribute, and so select the
28014 proper type in the 'b' case below. */
28015 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
28016 case V2DImode
: case V2DFmode
:
28024 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
28025 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
28026 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
28027 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
28034 case V8HImode
: result
= pixel_V8HI_type_node
;
28040 /* Propagate qualifiers attached to the element type
28041 onto the vector type. */
28042 if (result
&& result
!= type
&& TYPE_QUALS (type
))
28043 result
= build_qualified_type (result
, TYPE_QUALS (type
));
28045 *no_add_attrs
= true; /* No need to hang on to the attribute. */
28048 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
28053 /* AltiVec defines four built-in scalar types that serve as vector
28054 elements; we must teach the compiler how to mangle them. */
28056 static const char *
28057 rs6000_mangle_type (const_tree type
)
28059 type
= TYPE_MAIN_VARIANT (type
);
28061 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
28062 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
28065 if (type
== bool_char_type_node
) return "U6__boolc";
28066 if (type
== bool_short_type_node
) return "U6__bools";
28067 if (type
== pixel_type_node
) return "u7__pixel";
28068 if (type
== bool_int_type_node
) return "U6__booli";
28069 if (type
== bool_long_type_node
) return "U6__booll";
28071 /* Mangle IBM extended float long double as `g' (__float128) on
28072 powerpc*-linux where long-double-64 previously was the default. */
28073 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
28075 && TARGET_LONG_DOUBLE_128
28076 && !TARGET_IEEEQUAD
)
28079 /* For all other types, use normal C++ mangling. */
28083 /* Handle a "longcall" or "shortcall" attribute; arguments as in
28084 struct attribute_spec.handler. */
28087 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
28088 tree args ATTRIBUTE_UNUSED
,
28089 int flags ATTRIBUTE_UNUSED
,
28090 bool *no_add_attrs
)
28092 if (TREE_CODE (*node
) != FUNCTION_TYPE
28093 && TREE_CODE (*node
) != FIELD_DECL
28094 && TREE_CODE (*node
) != TYPE_DECL
)
28096 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
28098 *no_add_attrs
= true;
28104 /* Set longcall attributes on all functions declared when
28105 rs6000_default_long_calls is true. */
28107 rs6000_set_default_type_attributes (tree type
)
28109 if (rs6000_default_long_calls
28110 && (TREE_CODE (type
) == FUNCTION_TYPE
28111 || TREE_CODE (type
) == METHOD_TYPE
))
28112 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
28114 TYPE_ATTRIBUTES (type
));
28117 darwin_set_default_type_attributes (type
);
28121 /* Return a reference suitable for calling a function with the
28122 longcall attribute. */
28125 rs6000_longcall_ref (rtx call_ref
)
28127 const char *call_name
;
28130 if (GET_CODE (call_ref
) != SYMBOL_REF
)
28133 /* System V adds '.' to the internal name, so skip them. */
28134 call_name
= XSTR (call_ref
, 0);
28135 if (*call_name
== '.')
28137 while (*call_name
== '.')
28140 node
= get_identifier (call_name
);
28141 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
28144 return force_reg (Pmode
, call_ref
);
28147 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
28148 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
28151 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
28152 struct attribute_spec.handler. */
28154 rs6000_handle_struct_attribute (tree
*node
, tree name
,
28155 tree args ATTRIBUTE_UNUSED
,
28156 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
28159 if (DECL_P (*node
))
28161 if (TREE_CODE (*node
) == TYPE_DECL
)
28162 type
= &TREE_TYPE (*node
);
28167 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
28168 || TREE_CODE (*type
) == UNION_TYPE
)))
28170 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
28171 *no_add_attrs
= true;
28174 else if ((is_attribute_p ("ms_struct", name
)
28175 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
28176 || ((is_attribute_p ("gcc_struct", name
)
28177 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
28179 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
28181 *no_add_attrs
= true;
28188 rs6000_ms_bitfield_layout_p (const_tree record_type
)
28190 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
28191 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
28192 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
28195 #ifdef USING_ELFOS_H
28197 /* A get_unnamed_section callback, used for switching to toc_section. */
28200 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
28202 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28203 && TARGET_MINIMAL_TOC
28204 && !TARGET_RELOCATABLE
)
28206 if (!toc_initialized
)
28208 toc_initialized
= 1;
28209 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
28210 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
28211 fprintf (asm_out_file
, "\t.tc ");
28212 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
28213 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28214 fprintf (asm_out_file
, "\n");
28216 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28217 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28218 fprintf (asm_out_file
, " = .+32768\n");
28221 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28223 else if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28224 && !TARGET_RELOCATABLE
)
28225 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
28228 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28229 if (!toc_initialized
)
28231 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28232 fprintf (asm_out_file
, " = .+32768\n");
28233 toc_initialized
= 1;
28238 /* Implement TARGET_ASM_INIT_SECTIONS. */
28241 rs6000_elf_asm_init_sections (void)
28244 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
28247 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
28248 SDATA2_SECTION_ASM_OP
);
28251 /* Implement TARGET_SELECT_RTX_SECTION. */
28254 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
28255 unsigned HOST_WIDE_INT align
)
28257 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
28258 return toc_section
;
28260 return default_elf_select_rtx_section (mode
, x
, align
);
28263 /* For a SYMBOL_REF, set generic flags and then perform some
28264 target-specific processing.
28266 When the AIX ABI is requested on a non-AIX system, replace the
28267 function name with the real name (with a leading .) rather than the
28268 function descriptor name. This saves a lot of overriding code to
28269 read the prefixes. */
28271 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
28273 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
28275 default_encode_section_info (decl
, rtl
, first
);
28278 && TREE_CODE (decl
) == FUNCTION_DECL
28280 && DEFAULT_ABI
== ABI_AIX
)
28282 rtx sym_ref
= XEXP (rtl
, 0);
28283 size_t len
= strlen (XSTR (sym_ref
, 0));
28284 char *str
= XALLOCAVEC (char, len
+ 2);
28286 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
28287 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
28292 compare_section_name (const char *section
, const char *templ
)
28296 len
= strlen (templ
);
28297 return (strncmp (section
, templ
, len
) == 0
28298 && (section
[len
] == 0 || section
[len
] == '.'));
28302 rs6000_elf_in_small_data_p (const_tree decl
)
28304 if (rs6000_sdata
== SDATA_NONE
)
28307 /* We want to merge strings, so we never consider them small data. */
28308 if (TREE_CODE (decl
) == STRING_CST
)
28311 /* Functions are never in the small data area. */
28312 if (TREE_CODE (decl
) == FUNCTION_DECL
)
28315 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
28317 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
28318 if (compare_section_name (section
, ".sdata")
28319 || compare_section_name (section
, ".sdata2")
28320 || compare_section_name (section
, ".gnu.linkonce.s")
28321 || compare_section_name (section
, ".sbss")
28322 || compare_section_name (section
, ".sbss2")
28323 || compare_section_name (section
, ".gnu.linkonce.sb")
28324 || strcmp (section
, ".PPC.EMB.sdata0") == 0
28325 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
28330 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
28333 && size
<= g_switch_value
28334 /* If it's not public, and we're not going to reference it there,
28335 there's no need to put it in the small data section. */
28336 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
28343 #endif /* USING_ELFOS_H */
28345 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
28348 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
28350 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
28353 /* Do not place thread-local symbols refs in the object blocks. */
28356 rs6000_use_blocks_for_decl_p (const_tree decl
)
28358 return !DECL_THREAD_LOCAL_P (decl
);
28361 /* Return a REG that occurs in ADDR with coefficient 1.
28362 ADDR can be effectively incremented by incrementing REG.
28364 r0 is special and we must not select it as an address
28365 register by this routine since our caller will try to
28366 increment the returned register via an "la" instruction. */
28369 find_addr_reg (rtx addr
)
28371 while (GET_CODE (addr
) == PLUS
)
28373 if (GET_CODE (XEXP (addr
, 0)) == REG
28374 && REGNO (XEXP (addr
, 0)) != 0)
28375 addr
= XEXP (addr
, 0);
28376 else if (GET_CODE (XEXP (addr
, 1)) == REG
28377 && REGNO (XEXP (addr
, 1)) != 0)
28378 addr
= XEXP (addr
, 1);
28379 else if (CONSTANT_P (XEXP (addr
, 0)))
28380 addr
= XEXP (addr
, 1);
28381 else if (CONSTANT_P (XEXP (addr
, 1)))
28382 addr
= XEXP (addr
, 0);
28384 gcc_unreachable ();
28386 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
28391 rs6000_fatal_bad_address (rtx op
)
28393 fatal_insn ("bad address", op
);
28398 typedef struct branch_island_d
{
28399 tree function_name
;
28405 static vec
<branch_island
, va_gc
> *branch_islands
;
28407 /* Remember to generate a branch island for far calls to the given
28411 add_compiler_branch_island (tree label_name
, tree function_name
,
28414 branch_island bi
= {function_name
, label_name
, line_number
};
28415 vec_safe_push (branch_islands
, bi
);
28418 /* Generate far-jump branch islands for everything recorded in
28419 branch_islands. Invoked immediately after the last instruction of
28420 the epilogue has been emitted; the branch islands must be appended
28421 to, and contiguous with, the function body. Mach-O stubs are
28422 generated in machopic_output_stub(). */
28425 macho_branch_islands (void)
28429 while (!vec_safe_is_empty (branch_islands
))
28431 branch_island
*bi
= &branch_islands
->last ();
28432 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
28433 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
28434 char name_buf
[512];
28435 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
28436 if (name
[0] == '*' || name
[0] == '&')
28437 strcpy (name_buf
, name
+1);
28441 strcpy (name_buf
+1, name
);
28443 strcpy (tmp_buf
, "\n");
28444 strcat (tmp_buf
, label
);
28445 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
28446 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
28447 dbxout_stabd (N_SLINE
, bi
->line_number
);
28448 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
28451 if (TARGET_LINK_STACK
)
28454 get_ppc476_thunk_name (name
);
28455 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
28456 strcat (tmp_buf
, name
);
28457 strcat (tmp_buf
, "\n");
28458 strcat (tmp_buf
, label
);
28459 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
28463 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
28464 strcat (tmp_buf
, label
);
28465 strcat (tmp_buf
, "_pic\n");
28466 strcat (tmp_buf
, label
);
28467 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
28470 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
28471 strcat (tmp_buf
, name_buf
);
28472 strcat (tmp_buf
, " - ");
28473 strcat (tmp_buf
, label
);
28474 strcat (tmp_buf
, "_pic)\n");
28476 strcat (tmp_buf
, "\tmtlr r0\n");
28478 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
28479 strcat (tmp_buf
, name_buf
);
28480 strcat (tmp_buf
, " - ");
28481 strcat (tmp_buf
, label
);
28482 strcat (tmp_buf
, "_pic)\n");
28484 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
28488 strcat (tmp_buf
, ":\nlis r12,hi16(");
28489 strcat (tmp_buf
, name_buf
);
28490 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
28491 strcat (tmp_buf
, name_buf
);
28492 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
28494 output_asm_insn (tmp_buf
, 0);
28495 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
28496 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
28497 dbxout_stabd (N_SLINE
, bi
->line_number
);
28498 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
28499 branch_islands
->pop ();
28503 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
28504 already there or not. */
28507 no_previous_def (tree function_name
)
28512 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
28513 if (function_name
== bi
->function_name
)
28518 /* GET_PREV_LABEL gets the label name from the previous definition of
28522 get_prev_label (tree function_name
)
28527 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
28528 if (function_name
== bi
->function_name
)
28529 return bi
->label_name
;
28533 /* INSN is either a function call or a millicode call. It may have an
28534 unconditional jump in its delay slot.
28536 CALL_DEST is the routine we are calling. */
28539 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
28540 int cookie_operand_number
)
28542 static char buf
[256];
28543 if (darwin_emit_branch_islands
28544 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
28545 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
28548 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
28550 if (no_previous_def (funname
))
28552 rtx label_rtx
= gen_label_rtx ();
28553 char *label_buf
, temp_buf
[256];
28554 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
28555 CODE_LABEL_NUMBER (label_rtx
));
28556 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
28557 labelname
= get_identifier (label_buf
);
28558 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
28561 labelname
= get_prev_label (funname
);
28563 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
28564 instruction will reach 'foo', otherwise link as 'bl L42'".
28565 "L42" should be a 'branch island', that will do a far jump to
28566 'foo'. Branch islands are generated in
28567 macho_branch_islands(). */
28568 sprintf (buf
, "jbsr %%z%d,%.246s",
28569 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
28572 sprintf (buf
, "bl %%z%d", dest_operand_number
);
28576 /* Generate PIC and indirect symbol stubs. */
28579 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
28581 unsigned int length
;
28582 char *symbol_name
, *lazy_ptr_name
;
28583 char *local_label_0
;
28584 static int label
= 0;
28586 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
28587 symb
= (*targetm
.strip_name_encoding
) (symb
);
28590 length
= strlen (symb
);
28591 symbol_name
= XALLOCAVEC (char, length
+ 32);
28592 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
28594 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
28595 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
28598 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
28600 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
28604 fprintf (file
, "\t.align 5\n");
28606 fprintf (file
, "%s:\n", stub
);
28607 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28610 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
28611 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
28613 fprintf (file
, "\tmflr r0\n");
28614 if (TARGET_LINK_STACK
)
28617 get_ppc476_thunk_name (name
);
28618 fprintf (file
, "\tbl %s\n", name
);
28619 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28623 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
28624 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28626 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
28627 lazy_ptr_name
, local_label_0
);
28628 fprintf (file
, "\tmtlr r0\n");
28629 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
28630 (TARGET_64BIT
? "ldu" : "lwzu"),
28631 lazy_ptr_name
, local_label_0
);
28632 fprintf (file
, "\tmtctr r12\n");
28633 fprintf (file
, "\tbctr\n");
28637 fprintf (file
, "\t.align 4\n");
28639 fprintf (file
, "%s:\n", stub
);
28640 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28642 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
28643 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
28644 (TARGET_64BIT
? "ldu" : "lwzu"),
28646 fprintf (file
, "\tmtctr r12\n");
28647 fprintf (file
, "\tbctr\n");
28650 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
28651 fprintf (file
, "%s:\n", lazy_ptr_name
);
28652 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28653 fprintf (file
, "%sdyld_stub_binding_helper\n",
28654 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
28657 /* Legitimize PIC addresses. If the address is already
28658 position-independent, we return ORIG. Newly generated
28659 position-independent addresses go into a reg. This is REG if non
28660 zero, otherwise we allocate register(s) as necessary. */
28662 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
28665 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
28670 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
28671 reg
= gen_reg_rtx (Pmode
);
28673 if (GET_CODE (orig
) == CONST
)
28677 if (GET_CODE (XEXP (orig
, 0)) == PLUS
28678 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
28681 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
28683 /* Use a different reg for the intermediate value, as
28684 it will be marked UNCHANGING. */
28685 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
28686 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
28689 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
28692 if (GET_CODE (offset
) == CONST_INT
)
28694 if (SMALL_INT (offset
))
28695 return plus_constant (Pmode
, base
, INTVAL (offset
));
28696 else if (! reload_in_progress
&& ! reload_completed
)
28697 offset
= force_reg (Pmode
, offset
);
28700 rtx mem
= force_const_mem (Pmode
, orig
);
28701 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
28704 return gen_rtx_PLUS (Pmode
, base
, offset
);
28707 /* Fall back on generic machopic code. */
28708 return machopic_legitimize_pic_address (orig
, mode
, reg
);
28711 /* Output a .machine directive for the Darwin assembler, and call
28712 the generic start_file routine. */
28715 rs6000_darwin_file_start (void)
28717 static const struct
28721 HOST_WIDE_INT if_set
;
28723 { "ppc64", "ppc64", MASK_64BIT
},
28724 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
28725 { "power4", "ppc970", 0 },
28726 { "G5", "ppc970", 0 },
28727 { "7450", "ppc7450", 0 },
28728 { "7400", "ppc7400", MASK_ALTIVEC
},
28729 { "G4", "ppc7400", 0 },
28730 { "750", "ppc750", 0 },
28731 { "740", "ppc750", 0 },
28732 { "G3", "ppc750", 0 },
28733 { "604e", "ppc604e", 0 },
28734 { "604", "ppc604", 0 },
28735 { "603e", "ppc603", 0 },
28736 { "603", "ppc603", 0 },
28737 { "601", "ppc601", 0 },
28738 { NULL
, "ppc", 0 } };
28739 const char *cpu_id
= "";
28742 rs6000_file_start ();
28743 darwin_file_start ();
28745 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
28747 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
28748 cpu_id
= rs6000_default_cpu
;
28750 if (global_options_set
.x_rs6000_cpu_index
)
28751 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
28753 /* Look through the mapping array. Pick the first name that either
28754 matches the argument, has a bit set in IF_SET that is also set
28755 in the target flags, or has a NULL name. */
28758 while (mapping
[i
].arg
!= NULL
28759 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
28760 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
28763 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
28766 #endif /* TARGET_MACHO */
28770 rs6000_elf_reloc_rw_mask (void)
28774 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28780 /* Record an element in the table of global constructors. SYMBOL is
28781 a SYMBOL_REF of the function to be called; PRIORITY is a number
28782 between 0 and MAX_INIT_PRIORITY.
28784 This differs from default_named_section_asm_out_constructor in
28785 that we have special handling for -mrelocatable. */
28787 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
28789 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
28791 const char *section
= ".ctors";
28794 if (priority
!= DEFAULT_INIT_PRIORITY
)
28796 sprintf (buf
, ".ctors.%.5u",
28797 /* Invert the numbering so the linker puts us in the proper
28798 order; constructors are run from right to left, and the
28799 linker sorts in increasing order. */
28800 MAX_INIT_PRIORITY
- priority
);
28804 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
28805 assemble_align (POINTER_SIZE
);
28807 if (TARGET_RELOCATABLE
)
28809 fputs ("\t.long (", asm_out_file
);
28810 output_addr_const (asm_out_file
, symbol
);
28811 fputs (")@fixup\n", asm_out_file
);
28814 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
28817 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
28819 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
28821 const char *section
= ".dtors";
28824 if (priority
!= DEFAULT_INIT_PRIORITY
)
28826 sprintf (buf
, ".dtors.%.5u",
28827 /* Invert the numbering so the linker puts us in the proper
28828 order; constructors are run from right to left, and the
28829 linker sorts in increasing order. */
28830 MAX_INIT_PRIORITY
- priority
);
28834 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
28835 assemble_align (POINTER_SIZE
);
28837 if (TARGET_RELOCATABLE
)
28839 fputs ("\t.long (", asm_out_file
);
28840 output_addr_const (asm_out_file
, symbol
);
28841 fputs (")@fixup\n", asm_out_file
);
28844 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
28848 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
28850 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
28852 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
28853 ASM_OUTPUT_LABEL (file
, name
);
28854 fputs (DOUBLE_INT_ASM_OP
, file
);
28855 rs6000_output_function_entry (file
, name
);
28856 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
28859 fputs ("\t.size\t", file
);
28860 assemble_name (file
, name
);
28861 fputs (",24\n\t.type\t.", file
);
28862 assemble_name (file
, name
);
28863 fputs (",@function\n", file
);
28864 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
28866 fputs ("\t.globl\t.", file
);
28867 assemble_name (file
, name
);
28872 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
28873 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
28874 rs6000_output_function_entry (file
, name
);
28875 fputs (":\n", file
);
28879 if (TARGET_RELOCATABLE
28880 && !TARGET_SECURE_PLT
28881 && (get_pool_size () != 0 || crtl
->profile
)
28886 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
28888 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
28889 fprintf (file
, "\t.long ");
28890 assemble_name (file
, buf
);
28892 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
28893 assemble_name (file
, buf
);
28897 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
28898 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
28900 if (DEFAULT_ABI
== ABI_AIX
)
28902 const char *desc_name
, *orig_name
;
28904 orig_name
= (*targetm
.strip_name_encoding
) (name
);
28905 desc_name
= orig_name
;
28906 while (*desc_name
== '.')
28909 if (TREE_PUBLIC (decl
))
28910 fprintf (file
, "\t.globl %s\n", desc_name
);
28912 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28913 fprintf (file
, "%s:\n", desc_name
);
28914 fprintf (file
, "\t.long %s\n", orig_name
);
28915 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
28916 fputs ("\t.long 0\n", file
);
28917 fprintf (file
, "\t.previous\n");
28919 ASM_OUTPUT_LABEL (file
, name
);
28922 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
28924 rs6000_elf_file_end (void)
28926 #ifdef HAVE_AS_GNU_ATTRIBUTE
28927 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
28929 if (rs6000_passes_float
)
28930 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
28931 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
28932 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
28934 if (rs6000_passes_vector
)
28935 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
28936 (TARGET_ALTIVEC_ABI
? 2
28937 : TARGET_SPE_ABI
? 3
28939 if (rs6000_returns_struct
)
28940 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
28941 aix_struct_return
? 2 : 1);
28944 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
28945 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
28946 file_end_indicate_exec_stack ();
28953 rs6000_xcoff_asm_output_anchor (rtx symbol
)
28957 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
28958 SYMBOL_REF_BLOCK_OFFSET (symbol
));
28959 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
28963 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
28965 fputs (GLOBAL_ASM_OP
, stream
);
28966 RS6000_OUTPUT_BASENAME (stream
, name
);
28967 putc ('\n', stream
);
28970 /* A get_unnamed_decl callback, used for read-only sections. PTR
28971 points to the section string variable. */
28974 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
28976 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
28977 *(const char *const *) directive
,
28978 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28981 /* Likewise for read-write sections. */
28984 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
28986 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
28987 *(const char *const *) directive
,
28988 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28992 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
28994 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
28995 *(const char *const *) directive
,
28996 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28999 /* A get_unnamed_section callback, used for switching to toc_section. */
29002 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
29004 if (TARGET_MINIMAL_TOC
)
29006 /* toc_section is always selected at least once from
29007 rs6000_xcoff_file_start, so this is guaranteed to
29008 always be defined once and only once in each file. */
29009 if (!toc_initialized
)
29011 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
29012 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
29013 toc_initialized
= 1;
29015 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
29016 (TARGET_32BIT
? "" : ",3"));
29019 fputs ("\t.toc\n", asm_out_file
);
29022 /* Implement TARGET_ASM_INIT_SECTIONS. */
29025 rs6000_xcoff_asm_init_sections (void)
29027 read_only_data_section
29028 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
29029 &xcoff_read_only_section_name
);
29031 private_data_section
29032 = get_unnamed_section (SECTION_WRITE
,
29033 rs6000_xcoff_output_readwrite_section_asm_op
,
29034 &xcoff_private_data_section_name
);
29037 = get_unnamed_section (SECTION_TLS
,
29038 rs6000_xcoff_output_tls_section_asm_op
,
29039 &xcoff_tls_data_section_name
);
29041 tls_private_data_section
29042 = get_unnamed_section (SECTION_TLS
,
29043 rs6000_xcoff_output_tls_section_asm_op
,
29044 &xcoff_private_data_section_name
);
29046 read_only_private_data_section
29047 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
29048 &xcoff_private_data_section_name
);
29051 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
29053 readonly_data_section
= read_only_data_section
;
29054 exception_section
= data_section
;
29058 rs6000_xcoff_reloc_rw_mask (void)
29064 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
29065 tree decl ATTRIBUTE_UNUSED
)
29068 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
29070 if (flags
& SECTION_CODE
)
29072 else if (flags
& SECTION_TLS
)
29074 else if (flags
& SECTION_WRITE
)
29079 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
29080 (flags
& SECTION_CODE
) ? "." : "",
29081 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
29084 #define IN_NAMED_SECTION(DECL) \
29085 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
29086 && DECL_SECTION_NAME (DECL) != NULL_TREE)
29089 rs6000_xcoff_select_section (tree decl
, int reloc
,
29090 unsigned HOST_WIDE_INT align
)
29092 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
29094 if (align
> BIGGEST_ALIGNMENT
)
29096 resolve_unique_section (decl
, reloc
, true);
29097 if (IN_NAMED_SECTION (decl
))
29098 return get_named_section (decl
, NULL
, reloc
);
29101 if (decl_readonly_section (decl
, reloc
))
29103 if (TREE_PUBLIC (decl
))
29104 return read_only_data_section
;
29106 return read_only_private_data_section
;
29111 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
29113 if (TREE_PUBLIC (decl
))
29114 return tls_data_section
;
29115 else if (bss_initializer_p (decl
))
29117 /* Convert to COMMON to emit in BSS. */
29118 DECL_COMMON (decl
) = 1;
29119 return tls_comm_section
;
29122 return tls_private_data_section
;
29126 if (TREE_PUBLIC (decl
))
29127 return data_section
;
29129 return private_data_section
;
29134 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
29138 /* Use select_section for private data and uninitialized data with
29139 alignment <= BIGGEST_ALIGNMENT. */
29140 if (!TREE_PUBLIC (decl
)
29141 || DECL_COMMON (decl
)
29142 || (DECL_INITIAL (decl
) == NULL_TREE
29143 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
29144 || DECL_INITIAL (decl
) == error_mark_node
29145 || (flag_zero_initialized_in_bss
29146 && initializer_zerop (DECL_INITIAL (decl
))))
29149 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
29150 name
= (*targetm
.strip_name_encoding
) (name
);
29151 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
29154 /* Select section for constant in constant pool.
29156 On RS/6000, all constants are in the private read-only data area.
29157 However, if this is being placed in the TOC it must be output as a
29161 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
29162 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
29164 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
29165 return toc_section
;
29167 return read_only_private_data_section
;
29170 /* Remove any trailing [DS] or the like from the symbol name. */
29172 static const char *
29173 rs6000_xcoff_strip_name_encoding (const char *name
)
29178 len
= strlen (name
);
29179 if (name
[len
- 1] == ']')
29180 return ggc_alloc_string (name
, len
- 4);
29185 /* Section attributes. AIX is always PIC. */
29187 static unsigned int
29188 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
29190 unsigned int align
;
29191 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
29193 /* Align to at least UNIT size. */
29194 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
29195 align
= MIN_UNITS_PER_WORD
;
29197 /* Increase alignment of large objects if not already stricter. */
29198 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
29199 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
29200 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
29202 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
29205 /* Output at beginning of assembler file.
29207 Initialize the section names for the RS/6000 at this point.
29209 Specify filename, including full path, to assembler.
29211 We want to go into the TOC section so at least one .toc will be emitted.
29212 Also, in order to output proper .bs/.es pairs, we need at least one static
29213 [RW] section emitted.
29215 Finally, declare mcount when profiling to make the assembler happy. */
29218 rs6000_xcoff_file_start (void)
29220 rs6000_gen_section_name (&xcoff_bss_section_name
,
29221 main_input_filename
, ".bss_");
29222 rs6000_gen_section_name (&xcoff_private_data_section_name
,
29223 main_input_filename
, ".rw_");
29224 rs6000_gen_section_name (&xcoff_read_only_section_name
,
29225 main_input_filename
, ".ro_");
29226 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
29227 main_input_filename
, ".tls_");
29228 rs6000_gen_section_name (&xcoff_tbss_section_name
,
29229 main_input_filename
, ".tbss_[UL]");
29231 fputs ("\t.file\t", asm_out_file
);
29232 output_quoted_string (asm_out_file
, main_input_filename
);
29233 fputc ('\n', asm_out_file
);
29234 if (write_symbols
!= NO_DEBUG
)
29235 switch_to_section (private_data_section
);
29236 switch_to_section (text_section
);
29238 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
29239 rs6000_file_start ();
29242 /* Output at end of assembler file.
29243 On the RS/6000, referencing data should automatically pull in text. */
29246 rs6000_xcoff_file_end (void)
29248 switch_to_section (text_section
);
29249 fputs ("_section_.text:\n", asm_out_file
);
29250 switch_to_section (data_section
);
29251 fputs (TARGET_32BIT
29252 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
29258 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
29263 default_encode_section_info (decl
, rtl
, first
);
29265 /* Careful not to prod global register variables. */
29268 symbol
= XEXP (rtl
, 0);
29269 if (GET_CODE (symbol
) != SYMBOL_REF
)
29272 flags
= SYMBOL_REF_FLAGS (symbol
);
29274 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
29275 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
29277 SYMBOL_REF_FLAGS (symbol
) = flags
;
29279 #endif /* HAVE_AS_TLS */
29280 #endif /* TARGET_XCOFF */
29282 /* Compute a (partial) cost for rtx X. Return true if the complete
29283 cost has been computed, and false if subexpressions should be
29284 scanned. In either case, *TOTAL contains the cost result. */
29287 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
29288 int *total
, bool speed
)
29290 enum machine_mode mode
= GET_MODE (x
);
29294 /* On the RS/6000, if it is valid in the insn, it is free. */
29296 if (((outer_code
== SET
29297 || outer_code
== PLUS
29298 || outer_code
== MINUS
)
29299 && (satisfies_constraint_I (x
)
29300 || satisfies_constraint_L (x
)))
29301 || (outer_code
== AND
29302 && (satisfies_constraint_K (x
)
29304 ? satisfies_constraint_L (x
)
29305 : satisfies_constraint_J (x
))
29306 || mask_operand (x
, mode
)
29308 && mask64_operand (x
, DImode
))))
29309 || ((outer_code
== IOR
|| outer_code
== XOR
)
29310 && (satisfies_constraint_K (x
)
29312 ? satisfies_constraint_L (x
)
29313 : satisfies_constraint_J (x
))))
29314 || outer_code
== ASHIFT
29315 || outer_code
== ASHIFTRT
29316 || outer_code
== LSHIFTRT
29317 || outer_code
== ROTATE
29318 || outer_code
== ROTATERT
29319 || outer_code
== ZERO_EXTRACT
29320 || (outer_code
== MULT
29321 && satisfies_constraint_I (x
))
29322 || ((outer_code
== DIV
|| outer_code
== UDIV
29323 || outer_code
== MOD
|| outer_code
== UMOD
)
29324 && exact_log2 (INTVAL (x
)) >= 0)
29325 || (outer_code
== COMPARE
29326 && (satisfies_constraint_I (x
)
29327 || satisfies_constraint_K (x
)))
29328 || ((outer_code
== EQ
|| outer_code
== NE
)
29329 && (satisfies_constraint_I (x
)
29330 || satisfies_constraint_K (x
)
29332 ? satisfies_constraint_L (x
)
29333 : satisfies_constraint_J (x
))))
29334 || (outer_code
== GTU
29335 && satisfies_constraint_I (x
))
29336 || (outer_code
== LTU
29337 && satisfies_constraint_P (x
)))
29342 else if ((outer_code
== PLUS
29343 && reg_or_add_cint_operand (x
, VOIDmode
))
29344 || (outer_code
== MINUS
29345 && reg_or_sub_cint_operand (x
, VOIDmode
))
29346 || ((outer_code
== SET
29347 || outer_code
== IOR
29348 || outer_code
== XOR
)
29350 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
29352 *total
= COSTS_N_INSNS (1);
29362 /* When optimizing for size, MEM should be slightly more expensive
29363 than generating address, e.g., (plus (reg) (const)).
29364 L1 cache latency is about two instructions. */
29365 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
29374 if (FLOAT_MODE_P (mode
))
29375 *total
= rs6000_cost
->fp
;
29377 *total
= COSTS_N_INSNS (1);
29381 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
29382 && satisfies_constraint_I (XEXP (x
, 1)))
29384 if (INTVAL (XEXP (x
, 1)) >= -256
29385 && INTVAL (XEXP (x
, 1)) <= 255)
29386 *total
= rs6000_cost
->mulsi_const9
;
29388 *total
= rs6000_cost
->mulsi_const
;
29390 else if (mode
== SFmode
)
29391 *total
= rs6000_cost
->fp
;
29392 else if (FLOAT_MODE_P (mode
))
29393 *total
= rs6000_cost
->dmul
;
29394 else if (mode
== DImode
)
29395 *total
= rs6000_cost
->muldi
;
29397 *total
= rs6000_cost
->mulsi
;
29401 if (mode
== SFmode
)
29402 *total
= rs6000_cost
->fp
;
29404 *total
= rs6000_cost
->dmul
;
29409 if (FLOAT_MODE_P (mode
))
29411 *total
= mode
== DFmode
? rs6000_cost
->ddiv
29412 : rs6000_cost
->sdiv
;
29419 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
29420 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
29422 if (code
== DIV
|| code
== MOD
)
29424 *total
= COSTS_N_INSNS (2);
29427 *total
= COSTS_N_INSNS (1);
29431 if (GET_MODE (XEXP (x
, 1)) == DImode
)
29432 *total
= rs6000_cost
->divdi
;
29434 *total
= rs6000_cost
->divsi
;
29436 /* Add in shift and subtract for MOD. */
29437 if (code
== MOD
|| code
== UMOD
)
29438 *total
+= COSTS_N_INSNS (2);
29443 *total
= COSTS_N_INSNS (4);
29447 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
29451 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
29455 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
29467 *total
= COSTS_N_INSNS (1);
29475 /* Handle mul_highpart. */
29476 if (outer_code
== TRUNCATE
29477 && GET_CODE (XEXP (x
, 0)) == MULT
)
29479 if (mode
== DImode
)
29480 *total
= rs6000_cost
->muldi
;
29482 *total
= rs6000_cost
->mulsi
;
29485 else if (outer_code
== AND
)
29488 *total
= COSTS_N_INSNS (1);
29493 if (GET_CODE (XEXP (x
, 0)) == MEM
)
29496 *total
= COSTS_N_INSNS (1);
29502 if (!FLOAT_MODE_P (mode
))
29504 *total
= COSTS_N_INSNS (1);
29510 case UNSIGNED_FLOAT
:
29513 case FLOAT_TRUNCATE
:
29514 *total
= rs6000_cost
->fp
;
29518 if (mode
== DFmode
)
29521 *total
= rs6000_cost
->fp
;
29525 switch (XINT (x
, 1))
29528 *total
= rs6000_cost
->fp
;
29540 *total
= COSTS_N_INSNS (1);
29543 else if (FLOAT_MODE_P (mode
)
29544 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
29546 *total
= rs6000_cost
->fp
;
29554 /* Carry bit requires mode == Pmode.
29555 NEG or PLUS already counted so only add one. */
29557 && (outer_code
== NEG
|| outer_code
== PLUS
))
29559 *total
= COSTS_N_INSNS (1);
29562 if (outer_code
== SET
)
29564 if (XEXP (x
, 1) == const0_rtx
)
29566 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29567 *total
= COSTS_N_INSNS (8);
29569 *total
= COSTS_N_INSNS (2);
29572 else if (mode
== Pmode
)
29574 *total
= COSTS_N_INSNS (3);
29583 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
29585 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29586 *total
= COSTS_N_INSNS (8);
29588 *total
= COSTS_N_INSNS (2);
29592 if (outer_code
== COMPARE
)
29606 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
29609 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
29612 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
29615 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
29616 "opno = %d, total = %d, speed = %s, x:\n",
29617 ret
? "complete" : "scan inner",
29618 GET_RTX_NAME (code
),
29619 GET_RTX_NAME (outer_code
),
29622 speed
? "true" : "false");
29629 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
29632 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
29633 addr_space_t as
, bool speed
)
29635 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
29637 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
29638 ret
, speed
? "true" : "false");
29645 /* A C expression returning the cost of moving data from a register of class
29646 CLASS1 to one of CLASS2. */
29649 rs6000_register_move_cost (enum machine_mode mode
,
29650 reg_class_t from
, reg_class_t to
)
29654 if (TARGET_DEBUG_COST
)
29657 /* Moves from/to GENERAL_REGS. */
29658 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
29659 || reg_classes_intersect_p (from
, GENERAL_REGS
))
29661 reg_class_t rclass
= from
;
29663 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
29666 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
29667 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
29668 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
29670 /* It's more expensive to move CR_REGS than CR0_REGS because of the
29672 else if (rclass
== CR_REGS
)
29675 /* For those processors that have slow LR/CTR moves, make them more
29676 expensive than memory in order to bias spills to memory .*/
29677 else if ((rs6000_cpu
== PROCESSOR_POWER6
29678 || rs6000_cpu
== PROCESSOR_POWER7
29679 || rs6000_cpu
== PROCESSOR_POWER8
)
29680 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
29681 ret
= 6 * hard_regno_nregs
[0][mode
];
29684 /* A move will cost one instruction per GPR moved. */
29685 ret
= 2 * hard_regno_nregs
[0][mode
];
29688 /* If we have VSX, we can easily move between FPR or Altivec registers. */
29689 else if (VECTOR_MEM_VSX_P (mode
)
29690 && reg_classes_intersect_p (to
, VSX_REGS
)
29691 && reg_classes_intersect_p (from
, VSX_REGS
))
29692 ret
= 2 * hard_regno_nregs
[32][mode
];
29694 /* Moving between two similar registers is just one instruction. */
29695 else if (reg_classes_intersect_p (to
, from
))
29696 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
29698 /* Everything else has to go through GENERAL_REGS. */
29700 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
29701 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
29703 if (TARGET_DEBUG_COST
)
29705 if (dbg_cost_ctrl
== 1)
29707 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
29708 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
29709 reg_class_names
[to
]);
29716 /* A C expressions returning the cost of moving data of MODE from a register to
29720 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
29721 bool in ATTRIBUTE_UNUSED
)
29725 if (TARGET_DEBUG_COST
)
29728 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
29729 ret
= 4 * hard_regno_nregs
[0][mode
];
29730 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
29731 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
29732 ret
= 4 * hard_regno_nregs
[32][mode
];
29733 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
29734 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
29736 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
29738 if (TARGET_DEBUG_COST
)
29740 if (dbg_cost_ctrl
== 1)
29742 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
29743 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
29750 /* Returns a code for a target-specific builtin that implements
29751 reciprocal of the function, or NULL_TREE if not available. */
29754 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
29755 bool sqrt ATTRIBUTE_UNUSED
)
29757 if (optimize_insn_for_size_p ())
29763 case VSX_BUILTIN_XVSQRTDP
:
29764 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
29767 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
29769 case VSX_BUILTIN_XVSQRTSP
:
29770 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
29773 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
29782 case BUILT_IN_SQRT
:
29783 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
29786 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
29788 case BUILT_IN_SQRTF
:
29789 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
29792 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
29799 /* Load up a constant. If the mode is a vector mode, splat the value across
29800 all of the vector elements. */
29803 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
29807 if (mode
== SFmode
|| mode
== DFmode
)
29809 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
29810 reg
= force_reg (mode
, d
);
29812 else if (mode
== V4SFmode
)
29814 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
29815 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
29816 reg
= gen_reg_rtx (mode
);
29817 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
29819 else if (mode
== V2DFmode
)
29821 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
29822 rtvec v
= gen_rtvec (2, d
, d
);
29823 reg
= gen_reg_rtx (mode
);
29824 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
29827 gcc_unreachable ();
29832 /* Generate an FMA instruction. */
29835 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
29837 enum machine_mode mode
= GET_MODE (target
);
29840 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
29841 gcc_assert (dst
!= NULL
);
29844 emit_move_insn (target
, dst
);
29847 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
29850 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
29852 enum machine_mode mode
= GET_MODE (target
);
29855 /* Altivec does not support fms directly;
29856 generate in terms of fma in that case. */
29857 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
29858 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
29861 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
29862 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
29864 gcc_assert (dst
!= NULL
);
29867 emit_move_insn (target
, dst
);
29870 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
29873 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
29875 enum machine_mode mode
= GET_MODE (dst
);
29878 /* This is a tad more complicated, since the fnma_optab is for
29879 a different expression: fma(-m1, m2, a), which is the same
29880 thing except in the case of signed zeros.
29882 Fortunately we know that if FMA is supported that FNMSUB is
29883 also supported in the ISA. Just expand it directly. */
29885 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
29887 r
= gen_rtx_NEG (mode
, a
);
29888 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
29889 r
= gen_rtx_NEG (mode
, r
);
29890 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
29893 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
29894 add a reg_note saying that this was a division. Support both scalar and
29895 vector divide. Assumes no trapping math and finite arguments. */
29898 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
29900 enum machine_mode mode
= GET_MODE (dst
);
29901 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
29904 /* Low precision estimates guarantee 5 bits of accuracy. High
29905 precision estimates guarantee 14 bits of accuracy. SFmode
29906 requires 23 bits of accuracy. DFmode requires 52 bits of
29907 accuracy. Each pass at least doubles the accuracy, leading
29908 to the following. */
29909 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
29910 if (mode
== DFmode
|| mode
== V2DFmode
)
29913 enum insn_code code
= optab_handler (smul_optab
, mode
);
29914 insn_gen_fn gen_mul
= GEN_FCN (code
);
29916 gcc_assert (code
!= CODE_FOR_nothing
);
29918 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
29920 /* x0 = 1./d estimate */
29921 x0
= gen_reg_rtx (mode
);
29922 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
29923 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
29926 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
29929 /* e0 = 1. - d * x0 */
29930 e0
= gen_reg_rtx (mode
);
29931 rs6000_emit_nmsub (e0
, d
, x0
, one
);
29933 /* x1 = x0 + e0 * x0 */
29934 x1
= gen_reg_rtx (mode
);
29935 rs6000_emit_madd (x1
, e0
, x0
, x0
);
29937 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
29938 ++i
, xprev
= xnext
, eprev
= enext
) {
29940 /* enext = eprev * eprev */
29941 enext
= gen_reg_rtx (mode
);
29942 emit_insn (gen_mul (enext
, eprev
, eprev
));
29944 /* xnext = xprev + enext * xprev */
29945 xnext
= gen_reg_rtx (mode
);
29946 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
29952 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
29954 /* u = n * xprev */
29955 u
= gen_reg_rtx (mode
);
29956 emit_insn (gen_mul (u
, n
, xprev
));
29958 /* v = n - (d * u) */
29959 v
= gen_reg_rtx (mode
);
29960 rs6000_emit_nmsub (v
, d
, u
, n
);
29962 /* dst = (v * xprev) + u */
29963 rs6000_emit_madd (dst
, v
, xprev
, u
);
29966 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
29969 /* Newton-Raphson approximation of single/double-precision floating point
29970 rsqrt. Assumes no trapping math and finite arguments. */
29973 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
29975 enum machine_mode mode
= GET_MODE (src
);
29976 rtx x0
= gen_reg_rtx (mode
);
29977 rtx y
= gen_reg_rtx (mode
);
29979 /* Low precision estimates guarantee 5 bits of accuracy. High
29980 precision estimates guarantee 14 bits of accuracy. SFmode
29981 requires 23 bits of accuracy. DFmode requires 52 bits of
29982 accuracy. Each pass at least doubles the accuracy, leading
29983 to the following. */
29984 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
29985 if (mode
== DFmode
|| mode
== V2DFmode
)
29988 REAL_VALUE_TYPE dconst3_2
;
29991 enum insn_code code
= optab_handler (smul_optab
, mode
);
29992 insn_gen_fn gen_mul
= GEN_FCN (code
);
29994 gcc_assert (code
!= CODE_FOR_nothing
);
29996 /* Load up the constant 1.5 either as a scalar, or as a vector. */
29997 real_from_integer (&dconst3_2
, VOIDmode
, 3, 0, 0);
29998 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
30000 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
30002 /* x0 = rsqrt estimate */
30003 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
30004 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
30007 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
30008 rs6000_emit_msub (y
, src
, halfthree
, src
);
30010 for (i
= 0; i
< passes
; i
++)
30012 rtx x1
= gen_reg_rtx (mode
);
30013 rtx u
= gen_reg_rtx (mode
);
30014 rtx v
= gen_reg_rtx (mode
);
30016 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
30017 emit_insn (gen_mul (u
, x0
, x0
));
30018 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
30019 emit_insn (gen_mul (x1
, x0
, v
));
30023 emit_move_insn (dst
, x0
);
30027 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
30028 (Power7) targets. DST is the target, and SRC is the argument operand. */
30031 rs6000_emit_popcount (rtx dst
, rtx src
)
30033 enum machine_mode mode
= GET_MODE (dst
);
30036 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
30037 if (TARGET_POPCNTD
)
30039 if (mode
== SImode
)
30040 emit_insn (gen_popcntdsi2 (dst
, src
));
30042 emit_insn (gen_popcntddi2 (dst
, src
));
30046 tmp1
= gen_reg_rtx (mode
);
30048 if (mode
== SImode
)
30050 emit_insn (gen_popcntbsi2 (tmp1
, src
));
30051 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
30053 tmp2
= force_reg (SImode
, tmp2
);
30054 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
30058 emit_insn (gen_popcntbdi2 (tmp1
, src
));
30059 tmp2
= expand_mult (DImode
, tmp1
,
30060 GEN_INT ((HOST_WIDE_INT
)
30061 0x01010101 << 32 | 0x01010101),
30063 tmp2
= force_reg (DImode
, tmp2
);
30064 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
30069 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
30070 target, and SRC is the argument operand. */
30073 rs6000_emit_parity (rtx dst
, rtx src
)
30075 enum machine_mode mode
= GET_MODE (dst
);
30078 tmp
= gen_reg_rtx (mode
);
30080 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
30083 if (mode
== SImode
)
30085 emit_insn (gen_popcntbsi2 (tmp
, src
));
30086 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
30090 emit_insn (gen_popcntbdi2 (tmp
, src
));
30091 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
30096 if (mode
== SImode
)
30098 /* Is mult+shift >= shift+xor+shift+xor? */
30099 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
30101 rtx tmp1
, tmp2
, tmp3
, tmp4
;
30103 tmp1
= gen_reg_rtx (SImode
);
30104 emit_insn (gen_popcntbsi2 (tmp1
, src
));
30106 tmp2
= gen_reg_rtx (SImode
);
30107 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
30108 tmp3
= gen_reg_rtx (SImode
);
30109 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
30111 tmp4
= gen_reg_rtx (SImode
);
30112 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
30113 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
30116 rs6000_emit_popcount (tmp
, src
);
30117 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
30121 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
30122 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
30124 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
30126 tmp1
= gen_reg_rtx (DImode
);
30127 emit_insn (gen_popcntbdi2 (tmp1
, src
));
30129 tmp2
= gen_reg_rtx (DImode
);
30130 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
30131 tmp3
= gen_reg_rtx (DImode
);
30132 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
30134 tmp4
= gen_reg_rtx (DImode
);
30135 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
30136 tmp5
= gen_reg_rtx (DImode
);
30137 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
30139 tmp6
= gen_reg_rtx (DImode
);
30140 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
30141 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
30144 rs6000_emit_popcount (tmp
, src
);
30145 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
30149 /* Expand an Altivec constant permutation for little endian mode.
30150 There are two issues: First, the two input operands must be
30151 swapped so that together they form a double-wide array in LE
30152 order. Second, the vperm instruction has surprising behavior
30153 in LE mode: it interprets the elements of the source vectors
30154 in BE mode ("left to right") and interprets the elements of
30155 the destination vector in LE mode ("right to left"). To
30156 correct for this, we must subtract each element of the permute
30157 control vector from 31.
30159 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
30160 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
30161 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
30162 serve as the permute control vector. Then, in BE mode,
30166 places the desired result in vr9. However, in LE mode the
30167 vector contents will be
30169 vr10 = 00000003 00000002 00000001 00000000
30170 vr11 = 00000007 00000006 00000005 00000004
30172 The result of the vperm using the same permute control vector is
30174 vr9 = 05000000 07000000 01000000 03000000
30176 That is, the leftmost 4 bytes of vr10 are interpreted as the
30177 source for the rightmost 4 bytes of vr9, and so on.
30179 If we change the permute control vector to
30181 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
30189 vr9 = 00000006 00000004 00000002 00000000. */
30192 altivec_expand_vec_perm_const_le (rtx operands
[4])
30196 rtx constv
, unspec
;
30197 rtx target
= operands
[0];
30198 rtx op0
= operands
[1];
30199 rtx op1
= operands
[2];
30200 rtx sel
= operands
[3];
30202 /* Unpack and adjust the constant selector. */
30203 for (i
= 0; i
< 16; ++i
)
30205 rtx e
= XVECEXP (sel
, 0, i
);
30206 unsigned int elt
= 31 - (INTVAL (e
) & 31);
30207 perm
[i
] = GEN_INT (elt
);
30210 /* Expand to a permute, swapping the inputs and using the
30211 adjusted selector. */
30213 op0
= force_reg (V16QImode
, op0
);
30215 op1
= force_reg (V16QImode
, op1
);
30217 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
30218 constv
= force_reg (V16QImode
, constv
);
30219 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
30221 if (!REG_P (target
))
30223 rtx tmp
= gen_reg_rtx (V16QImode
);
30224 emit_move_insn (tmp
, unspec
);
30228 emit_move_insn (target
, unspec
);
30231 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
30232 permute control vector. But here it's not a constant, so we must
30233 generate a vector NOR to do the adjustment. */
30236 altivec_expand_vec_perm_le (rtx operands
[4])
30238 rtx notx
, andx
, unspec
;
30239 rtx target
= operands
[0];
30240 rtx op0
= operands
[1];
30241 rtx op1
= operands
[2];
30242 rtx sel
= operands
[3];
30244 rtx norreg
= gen_reg_rtx (V16QImode
);
30245 enum machine_mode mode
= GET_MODE (target
);
30247 /* Get everything in regs so the pattern matches. */
30249 op0
= force_reg (mode
, op0
);
30251 op1
= force_reg (mode
, op1
);
30253 sel
= force_reg (V16QImode
, sel
);
30254 if (!REG_P (target
))
30255 tmp
= gen_reg_rtx (mode
);
30257 /* Invert the selector with a VNOR. */
30258 notx
= gen_rtx_NOT (V16QImode
, sel
);
30259 andx
= gen_rtx_AND (V16QImode
, notx
, notx
);
30260 emit_move_insn (norreg
, andx
);
30262 /* Permute with operands reversed and adjusted selector. */
30263 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
30266 /* Copy into target, possibly by way of a register. */
30267 if (!REG_P (target
))
30269 emit_move_insn (tmp
, unspec
);
30273 emit_move_insn (target
, unspec
);
30276 /* Expand an Altivec constant permutation. Return true if we match
30277 an efficient implementation; false to fall back to VPERM. */
30280 altivec_expand_vec_perm_const (rtx operands
[4])
30282 struct altivec_perm_insn
{
30283 HOST_WIDE_INT mask
;
30284 enum insn_code impl
;
30285 unsigned char perm
[16];
30287 static const struct altivec_perm_insn patterns
[] = {
30288 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
30289 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
30290 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
30291 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
30292 { OPTION_MASK_ALTIVEC
,
30293 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
30294 : CODE_FOR_altivec_vmrglb_direct
),
30295 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
30296 { OPTION_MASK_ALTIVEC
,
30297 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
30298 : CODE_FOR_altivec_vmrglh_direct
),
30299 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
30300 { OPTION_MASK_ALTIVEC
,
30301 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
30302 : CODE_FOR_altivec_vmrglw_direct
),
30303 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
30304 { OPTION_MASK_ALTIVEC
,
30305 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
30306 : CODE_FOR_altivec_vmrghb_direct
),
30307 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
30308 { OPTION_MASK_ALTIVEC
,
30309 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
30310 : CODE_FOR_altivec_vmrghh_direct
),
30311 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
30312 { OPTION_MASK_ALTIVEC
,
30313 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
30314 : CODE_FOR_altivec_vmrghw_direct
),
30315 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
30316 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
30317 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
30318 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
30319 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
30322 unsigned int i
, j
, elt
, which
;
30323 unsigned char perm
[16];
30324 rtx target
, op0
, op1
, sel
, x
;
30327 target
= operands
[0];
30332 /* Unpack the constant selector. */
30333 for (i
= which
= 0; i
< 16; ++i
)
30335 rtx e
= XVECEXP (sel
, 0, i
);
30336 elt
= INTVAL (e
) & 31;
30337 which
|= (elt
< 16 ? 1 : 2);
30341 /* Simplify the constant selector based on operands. */
30345 gcc_unreachable ();
30349 if (!rtx_equal_p (op0
, op1
))
30354 for (i
= 0; i
< 16; ++i
)
30366 /* Look for splat patterns. */
30371 for (i
= 0; i
< 16; ++i
)
30372 if (perm
[i
] != elt
)
30376 if (!BYTES_BIG_ENDIAN
)
30378 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
30384 for (i
= 0; i
< 16; i
+= 2)
30385 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
30389 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
30390 x
= gen_reg_rtx (V8HImode
);
30391 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
30393 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30400 for (i
= 0; i
< 16; i
+= 4)
30402 || perm
[i
+ 1] != elt
+ 1
30403 || perm
[i
+ 2] != elt
+ 2
30404 || perm
[i
+ 3] != elt
+ 3)
30408 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
30409 x
= gen_reg_rtx (V4SImode
);
30410 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
30412 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30418 /* Look for merge and pack patterns. */
30419 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
30423 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
30426 elt
= patterns
[j
].perm
[0];
30427 if (perm
[0] == elt
)
30429 else if (perm
[0] == elt
+ 16)
30433 for (i
= 1; i
< 16; ++i
)
30435 elt
= patterns
[j
].perm
[i
];
30437 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
30438 else if (one_vec
&& elt
>= 16)
30440 if (perm
[i
] != elt
)
30445 enum insn_code icode
= patterns
[j
].impl
;
30446 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
30447 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
30449 /* For little-endian, don't use vpkuwum and vpkuhum if the
30450 underlying vector type is not V4SI and V8HI, respectively.
30451 For example, using vpkuwum with a V8HI picks up the even
30452 halfwords (BE numbering) when the even halfwords (LE
30453 numbering) are what we need. */
30454 if (!BYTES_BIG_ENDIAN
30455 && icode
== CODE_FOR_altivec_vpkuwum_direct
30456 && ((GET_CODE (op0
) == REG
30457 && GET_MODE (op0
) != V4SImode
)
30458 || (GET_CODE (op0
) == SUBREG
30459 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
30461 if (!BYTES_BIG_ENDIAN
30462 && icode
== CODE_FOR_altivec_vpkuhum_direct
30463 && ((GET_CODE (op0
) == REG
30464 && GET_MODE (op0
) != V8HImode
)
30465 || (GET_CODE (op0
) == SUBREG
30466 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
30469 /* For little-endian, the two input operands must be swapped
30470 (or swapped back) to ensure proper right-to-left numbering
30472 if (swapped
^ !BYTES_BIG_ENDIAN
)
30473 x
= op0
, op0
= op1
, op1
= x
;
30474 if (imode
!= V16QImode
)
30476 op0
= gen_lowpart (imode
, op0
);
30477 op1
= gen_lowpart (imode
, op1
);
30479 if (omode
== V16QImode
)
30482 x
= gen_reg_rtx (omode
);
30483 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
30484 if (omode
!= V16QImode
)
30485 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30490 if (!BYTES_BIG_ENDIAN
)
30492 altivec_expand_vec_perm_const_le (operands
);
30499 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
30500 Return true if we match an efficient implementation. */
30503 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
30504 unsigned char perm0
, unsigned char perm1
)
30508 /* If both selectors come from the same operand, fold to single op. */
30509 if ((perm0
& 2) == (perm1
& 2))
30516 /* If both operands are equal, fold to simpler permutation. */
30517 if (rtx_equal_p (op0
, op1
))
30520 perm1
= (perm1
& 1) + 2;
30522 /* If the first selector comes from the second operand, swap. */
30523 else if (perm0
& 2)
30529 x
= op0
, op0
= op1
, op1
= x
;
30531 /* If the second selector does not come from the second operand, fail. */
30532 else if ((perm1
& 2) == 0)
30536 if (target
!= NULL
)
30538 enum machine_mode vmode
, dmode
;
30541 vmode
= GET_MODE (target
);
30542 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
30543 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
30544 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
30545 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
30546 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
30547 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
30553 rs6000_expand_vec_perm_const (rtx operands
[4])
30555 rtx target
, op0
, op1
, sel
;
30556 unsigned char perm0
, perm1
;
30558 target
= operands
[0];
30563 /* Unpack the constant selector. */
30564 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
30565 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
30567 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
30570 /* Test whether a constant permutation is supported. */
30573 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
30574 const unsigned char *sel
)
30576 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
30577 if (TARGET_ALTIVEC
)
30580 /* Check for ps_merge* or evmerge* insns. */
30581 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
30582 || (TARGET_SPE
&& vmode
== V2SImode
))
30584 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
30585 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
30586 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
30592 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
30595 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
30596 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
30598 enum machine_mode imode
;
30602 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
30604 imode
= GET_MODE_INNER (vmode
);
30605 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
30606 imode
= mode_for_vector (imode
, nelt
);
30609 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
30610 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
30612 emit_move_insn (target
, x
);
30615 /* Expand an extract even operation. */
30618 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
30620 enum machine_mode vmode
= GET_MODE (target
);
30621 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
30624 for (i
= 0; i
< nelt
; i
++)
30625 perm
[i
] = GEN_INT (i
* 2);
30627 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30630 /* Expand a vector interleave operation. */
30633 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
30635 enum machine_mode vmode
= GET_MODE (target
);
30636 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
30639 high
= (highp
? 0 : nelt
/ 2);
30640 for (i
= 0; i
< nelt
/ 2; i
++)
30642 perm
[i
* 2] = GEN_INT (i
+ high
);
30643 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
30646 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30649 /* Return an RTX representing where to find the function value of a
30650 function returning MODE. */
30652 rs6000_complex_function_value (enum machine_mode mode
)
30654 unsigned int regno
;
30656 enum machine_mode inner
= GET_MODE_INNER (mode
);
30657 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
30659 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30660 regno
= FP_ARG_RETURN
;
30663 regno
= GP_ARG_RETURN
;
30665 /* 32-bit is OK since it'll go in r3/r4. */
30666 if (TARGET_32BIT
&& inner_bytes
>= 4)
30667 return gen_rtx_REG (mode
, regno
);
30670 if (inner_bytes
>= 8)
30671 return gen_rtx_REG (mode
, regno
);
30673 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
30675 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
30676 GEN_INT (inner_bytes
));
30677 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
30680 /* Target hook for TARGET_FUNCTION_VALUE.
30682 On the SPE, both FPs and vectors are returned in r3.
30684 On RS/6000 an integer value is in r3 and a floating-point value is in
30685 fp1, unless -msoft-float. */
30688 rs6000_function_value (const_tree valtype
,
30689 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
30690 bool outgoing ATTRIBUTE_UNUSED
)
30692 enum machine_mode mode
;
30693 unsigned int regno
;
30694 enum machine_mode elt_mode
;
30697 /* Special handling for structs in darwin64. */
30699 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
30701 CUMULATIVE_ARGS valcum
;
30705 valcum
.fregno
= FP_ARG_MIN_REG
;
30706 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
30707 /* Do a trial code generation as if this were going to be passed as
30708 an argument; if any part goes in memory, we return NULL. */
30709 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
30712 /* Otherwise fall through to standard ABI rules. */
30715 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
30716 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype
), valtype
,
30717 &elt_mode
, &n_elts
))
30719 int first_reg
, n_regs
, i
;
30722 if (SCALAR_FLOAT_MODE_P (elt_mode
))
30724 /* _Decimal128 must use even/odd register pairs. */
30725 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30726 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
30730 first_reg
= ALTIVEC_ARG_RETURN
;
30734 par
= gen_rtx_PARALLEL (TYPE_MODE (valtype
), rtvec_alloc (n_elts
));
30735 for (i
= 0; i
< n_elts
; i
++)
30737 rtx r
= gen_rtx_REG (elt_mode
, first_reg
+ i
* n_regs
);
30738 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
30739 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
30745 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
30747 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
30748 return gen_rtx_PARALLEL (DImode
,
30750 gen_rtx_EXPR_LIST (VOIDmode
,
30751 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30753 gen_rtx_EXPR_LIST (VOIDmode
,
30754 gen_rtx_REG (SImode
,
30755 GP_ARG_RETURN
+ 1),
30758 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
30760 return gen_rtx_PARALLEL (DCmode
,
30762 gen_rtx_EXPR_LIST (VOIDmode
,
30763 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30765 gen_rtx_EXPR_LIST (VOIDmode
,
30766 gen_rtx_REG (SImode
,
30767 GP_ARG_RETURN
+ 1),
30769 gen_rtx_EXPR_LIST (VOIDmode
,
30770 gen_rtx_REG (SImode
,
30771 GP_ARG_RETURN
+ 2),
30773 gen_rtx_EXPR_LIST (VOIDmode
,
30774 gen_rtx_REG (SImode
,
30775 GP_ARG_RETURN
+ 3),
30779 mode
= TYPE_MODE (valtype
);
30780 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
30781 || (POINTER_TYPE_P (valtype
) && !upc_shared_type_p (TREE_TYPE (valtype
))))
30782 mode
= TARGET_32BIT
? SImode
: DImode
;
30784 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30785 /* _Decimal128 must use an even/odd register pair. */
30786 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30787 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
30788 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
30789 regno
= FP_ARG_RETURN
;
30790 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
30791 && targetm
.calls
.split_complex_arg
)
30792 return rs6000_complex_function_value (mode
);
30793 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
30794 return register is used in both cases, and we won't see V2DImode/V2DFmode
30795 for pure altivec, combine the two cases. */
30796 else if (TREE_CODE (valtype
) == VECTOR_TYPE
30797 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
30798 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
30799 regno
= ALTIVEC_ARG_RETURN
;
30800 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
30801 && (mode
== DFmode
|| mode
== DCmode
30802 || mode
== TFmode
|| mode
== TCmode
))
30803 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
30805 regno
= GP_ARG_RETURN
;
30807 return gen_rtx_REG (mode
, regno
);
30810 /* Define how to find the value returned by a library function
30811 assuming the value has mode MODE. */
30813 rs6000_libcall_value (enum machine_mode mode
)
30815 unsigned int regno
;
30817 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
30819 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
30820 return gen_rtx_PARALLEL (DImode
,
30822 gen_rtx_EXPR_LIST (VOIDmode
,
30823 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30825 gen_rtx_EXPR_LIST (VOIDmode
,
30826 gen_rtx_REG (SImode
,
30827 GP_ARG_RETURN
+ 1),
30831 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30832 /* _Decimal128 must use an even/odd register pair. */
30833 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30834 else if (SCALAR_FLOAT_MODE_P (mode
)
30835 && TARGET_HARD_FLOAT
&& TARGET_FPRS
30836 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
30837 regno
= FP_ARG_RETURN
;
30838 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
30839 return register is used in both cases, and we won't see V2DImode/V2DFmode
30840 for pure altivec, combine the two cases. */
30841 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
30842 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
30843 regno
= ALTIVEC_ARG_RETURN
;
30844 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
30845 return rs6000_complex_function_value (mode
);
30846 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
30847 && (mode
== DFmode
|| mode
== DCmode
30848 || mode
== TFmode
|| mode
== TCmode
))
30849 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
30851 regno
= GP_ARG_RETURN
;
30853 return gen_rtx_REG (mode
, regno
);
30857 /* Return true if we use LRA instead of reload pass. */
30859 rs6000_lra_p (void)
30861 return rs6000_lra_flag
;
30864 /* Given FROM and TO register numbers, say whether this elimination is allowed.
30865 Frame pointer elimination is automatically handled.
30867 For the RS/6000, if frame pointer elimination is being done, we would like
30868 to convert ap into fp, not sp.
30870 We need r30 if -mminimal-toc was specified, and there are constant pool
30874 rs6000_can_eliminate (const int from
, const int to
)
30876 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
30877 ? ! frame_pointer_needed
30878 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
30879 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
30883 /* Define the offset between two registers, FROM to be eliminated and its
30884 replacement TO, at the start of a routine. */
30886 rs6000_initial_elimination_offset (int from
, int to
)
30888 rs6000_stack_t
*info
= rs6000_stack_info ();
30889 HOST_WIDE_INT offset
;
30891 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30892 offset
= info
->push_p
? 0 : -info
->total_size
;
30893 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30895 offset
= info
->push_p
? 0 : -info
->total_size
;
30896 if (FRAME_GROWS_DOWNWARD
)
30897 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
30899 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
30900 offset
= FRAME_GROWS_DOWNWARD
30901 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
30903 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
30904 offset
= info
->total_size
;
30905 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30906 offset
= info
->push_p
? info
->total_size
: 0;
30907 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
30910 gcc_unreachable ();
30916 rs6000_dwarf_register_span (rtx reg
)
30920 unsigned regno
= REGNO (reg
);
30921 enum machine_mode mode
= GET_MODE (reg
);
30925 && (SPE_VECTOR_MODE (GET_MODE (reg
))
30926 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
30927 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
30932 regno
= REGNO (reg
);
30934 /* The duality of the SPE register size wreaks all kinds of havoc.
30935 This is a way of distinguishing r0 in 32-bits from r0 in
30937 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
30938 gcc_assert (words
<= 4);
30939 for (i
= 0; i
< words
; i
++, regno
++)
30941 if (BYTES_BIG_ENDIAN
)
30943 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
30944 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
30948 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
30949 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
30953 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
30956 /* Fill in sizes for SPE register high parts in table used by unwinder. */
30959 rs6000_init_dwarf_reg_sizes_extra (tree address
)
30964 enum machine_mode mode
= TYPE_MODE (char_type_node
);
30965 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
30966 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
30967 rtx value
= gen_int_mode (4, mode
);
30969 for (i
= 1201; i
< 1232; i
++)
30971 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
30972 HOST_WIDE_INT offset
30973 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
30975 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
30979 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
30982 enum machine_mode mode
= TYPE_MODE (char_type_node
);
30983 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
30984 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
30985 rtx value
= gen_int_mode (16, mode
);
30987 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
30988 The unwinder still needs to know the size of Altivec registers. */
30990 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
30992 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
30993 HOST_WIDE_INT offset
30994 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
30996 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
31001 /* Map internal gcc register numbers to DWARF2 register numbers. */
31004 rs6000_dbx_register_number (unsigned int regno
)
31006 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
31008 if (regno
== LR_REGNO
)
31010 if (regno
== CTR_REGNO
)
31012 if (CR_REGNO_P (regno
))
31013 return regno
- CR0_REGNO
+ 86;
31014 if (regno
== CA_REGNO
)
31015 return 101; /* XER */
31016 if (ALTIVEC_REGNO_P (regno
))
31017 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
31018 if (regno
== VRSAVE_REGNO
)
31020 if (regno
== VSCR_REGNO
)
31022 if (regno
== SPE_ACC_REGNO
)
31024 if (regno
== SPEFSCR_REGNO
)
31026 /* SPE high reg number. We get these values of regno from
31027 rs6000_dwarf_register_span. */
31028 gcc_assert (regno
>= 1200 && regno
< 1232);
31032 /* target hook eh_return_filter_mode */
31033 static enum machine_mode
31034 rs6000_eh_return_filter_mode (void)
31036 return TARGET_32BIT
? SImode
: word_mode
;
31039 /* Target hook for scalar_mode_supported_p. */
31041 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
31043 if (DECIMAL_FLOAT_MODE_P (mode
))
31044 return default_decimal_float_supported_p ();
31046 return default_scalar_mode_supported_p (mode
);
31049 /* Target hook for vector_mode_supported_p. */
31051 rs6000_vector_mode_supported_p (enum machine_mode mode
)
31054 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
31057 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
31060 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
31067 /* Target hook for invalid_arg_for_unprototyped_fn. */
31068 static const char *
31069 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
31071 return (!rs6000_darwin64_abi
31073 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
31074 && (funcdecl
== NULL_TREE
31075 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
31076 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
31077 ? N_("AltiVec argument passed to unprototyped function")
31081 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
31082 setup by using __stack_chk_fail_local hidden function instead of
31083 calling __stack_chk_fail directly. Otherwise it is better to call
31084 __stack_chk_fail directly. */
31086 static tree ATTRIBUTE_UNUSED
31087 rs6000_stack_protect_fail (void)
31089 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
31090 ? default_hidden_stack_protect_fail ()
31091 : default_external_stack_protect_fail ();
31095 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
31096 int num_operands ATTRIBUTE_UNUSED
)
31098 if (rs6000_warn_cell_microcode
)
31101 int insn_code_number
= recog_memoized (insn
);
31102 location_t location
= INSN_LOCATION (insn
);
31104 /* Punt on insns we cannot recognize. */
31105 if (insn_code_number
< 0)
31108 temp
= get_insn_template (insn_code_number
, insn
);
31110 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
31111 warning_at (location
, OPT_mwarn_cell_microcode
,
31112 "emitting microcode insn %s\t[%s] #%d",
31113 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
31114 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
31115 warning_at (location
, OPT_mwarn_cell_microcode
,
31116 "emitting conditional microcode insn %s\t[%s] #%d",
31117 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
31121 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
31124 static unsigned HOST_WIDE_INT
31125 rs6000_asan_shadow_offset (void)
31127 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
31131 /* Mask options that we want to support inside of attribute((target)) and
31132 #pragma GCC target operations. Note, we do not include things like
31133 64/32-bit, endianess, hard/soft floating point, etc. that would have
31134 different calling sequences. */
31136 struct rs6000_opt_mask
{
31137 const char *name
; /* option name */
31138 HOST_WIDE_INT mask
; /* mask to set */
31139 bool invert
; /* invert sense of mask */
31140 bool valid_target
; /* option is a target option */
31143 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
31145 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
31146 { "cmpb", OPTION_MASK_CMPB
, false, true },
31147 { "crypto", OPTION_MASK_CRYPTO
, false, true },
31148 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
31149 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
31150 { "fprnd", OPTION_MASK_FPRND
, false, true },
31151 { "hard-dfp", OPTION_MASK_DFP
, false, true },
31152 { "htm", OPTION_MASK_HTM
, false, true },
31153 { "isel", OPTION_MASK_ISEL
, false, true },
31154 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
31155 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
31156 { "mulhw", OPTION_MASK_MULHW
, false, true },
31157 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
31158 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
31159 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
31160 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
31161 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
31162 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
31163 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
31164 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
31165 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
31166 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
31167 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
31168 { "string", OPTION_MASK_STRING
, false, true },
31169 { "update", OPTION_MASK_NO_UPDATE
, true , true },
31170 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, false },
31171 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, false },
31172 { "vsx", OPTION_MASK_VSX
, false, true },
31173 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
31174 #ifdef OPTION_MASK_64BIT
31176 { "aix64", OPTION_MASK_64BIT
, false, false },
31177 { "aix32", OPTION_MASK_64BIT
, true, false },
31179 { "64", OPTION_MASK_64BIT
, false, false },
31180 { "32", OPTION_MASK_64BIT
, true, false },
31183 #ifdef OPTION_MASK_EABI
31184 { "eabi", OPTION_MASK_EABI
, false, false },
31186 #ifdef OPTION_MASK_LITTLE_ENDIAN
31187 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
31188 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
31190 #ifdef OPTION_MASK_RELOCATABLE
31191 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
31193 #ifdef OPTION_MASK_STRICT_ALIGN
31194 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
31196 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
31197 { "string", OPTION_MASK_STRING
, false, false },
31200 /* Builtin mask mapping for printing the flags. */
31201 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
31203 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
31204 { "vsx", RS6000_BTM_VSX
, false, false },
31205 { "spe", RS6000_BTM_SPE
, false, false },
31206 { "paired", RS6000_BTM_PAIRED
, false, false },
31207 { "fre", RS6000_BTM_FRE
, false, false },
31208 { "fres", RS6000_BTM_FRES
, false, false },
31209 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
31210 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
31211 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
31212 { "cell", RS6000_BTM_CELL
, false, false },
31213 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
31214 { "crypto", RS6000_BTM_CRYPTO
, false, false },
31215 { "htm", RS6000_BTM_HTM
, false, false },
31218 /* Option variables that we want to support inside attribute((target)) and
31219 #pragma GCC target operations. */
31221 struct rs6000_opt_var
{
31222 const char *name
; /* option name */
31223 size_t global_offset
; /* offset of the option in global_options. */
31224 size_t target_offset
; /* offset of the option in target optiosn. */
31227 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
31230 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
31231 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
31232 { "avoid-indexed-addresses",
31233 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
31234 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
31236 offsetof (struct gcc_options
, x_rs6000_paired_float
),
31237 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
31239 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
31240 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
31243 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
31244 parsing. Return true if there were no errors. */
31247 rs6000_inner_target_options (tree args
, bool attr_p
)
31251 if (args
== NULL_TREE
)
31254 else if (TREE_CODE (args
) == STRING_CST
)
31256 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
31259 while ((q
= strtok (p
, ",")) != NULL
)
31261 bool error_p
= false;
31262 bool not_valid_p
= false;
31263 const char *cpu_opt
= NULL
;
31266 if (strncmp (q
, "cpu=", 4) == 0)
31268 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
31269 if (cpu_index
>= 0)
31270 rs6000_cpu_index
= cpu_index
;
31277 else if (strncmp (q
, "tune=", 5) == 0)
31279 int tune_index
= rs6000_cpu_name_lookup (q
+5);
31280 if (tune_index
>= 0)
31281 rs6000_tune_index
= tune_index
;
31291 bool invert
= false;
31295 if (strncmp (r
, "no-", 3) == 0)
31301 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
31302 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
31304 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
31306 if (!rs6000_opt_masks
[i
].valid_target
)
31307 not_valid_p
= true;
31311 rs6000_isa_flags_explicit
|= mask
;
31313 /* VSX needs altivec, so -mvsx automagically sets
31315 if (mask
== OPTION_MASK_VSX
&& !invert
)
31316 mask
|= OPTION_MASK_ALTIVEC
;
31318 if (rs6000_opt_masks
[i
].invert
)
31322 rs6000_isa_flags
&= ~mask
;
31324 rs6000_isa_flags
|= mask
;
31329 if (error_p
&& !not_valid_p
)
31331 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
31332 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
31334 size_t j
= rs6000_opt_vars
[i
].global_offset
;
31335 *((int *) ((char *)&global_options
+ j
)) = !invert
;
31344 const char *eprefix
, *esuffix
;
31349 eprefix
= "__attribute__((__target__(";
31354 eprefix
= "#pragma GCC target ";
31359 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
31361 else if (not_valid_p
)
31362 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
31364 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
31369 else if (TREE_CODE (args
) == TREE_LIST
)
31373 tree value
= TREE_VALUE (args
);
31376 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
31380 args
= TREE_CHAIN (args
);
31382 while (args
!= NULL_TREE
);
31386 gcc_unreachable ();
31391 /* Print out the target options as a list for -mdebug=target. */
31394 rs6000_debug_target_options (tree args
, const char *prefix
)
31396 if (args
== NULL_TREE
)
31397 fprintf (stderr
, "%s<NULL>", prefix
);
31399 else if (TREE_CODE (args
) == STRING_CST
)
31401 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
31404 while ((q
= strtok (p
, ",")) != NULL
)
31407 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
31412 else if (TREE_CODE (args
) == TREE_LIST
)
31416 tree value
= TREE_VALUE (args
);
31419 rs6000_debug_target_options (value
, prefix
);
31422 args
= TREE_CHAIN (args
);
31424 while (args
!= NULL_TREE
);
31428 gcc_unreachable ();
31434 /* Hook to validate attribute((target("..."))). */
31437 rs6000_valid_attribute_p (tree fndecl
,
31438 tree
ARG_UNUSED (name
),
31442 struct cl_target_option cur_target
;
31444 tree old_optimize
= build_optimization_node (&global_options
);
31445 tree new_target
, new_optimize
;
31446 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
31448 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
31450 if (TARGET_DEBUG_TARGET
)
31452 tree tname
= DECL_NAME (fndecl
);
31453 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
31455 fprintf (stderr
, "function: %.*s\n",
31456 (int) IDENTIFIER_LENGTH (tname
),
31457 IDENTIFIER_POINTER (tname
));
31459 fprintf (stderr
, "function: unknown\n");
31461 fprintf (stderr
, "args:");
31462 rs6000_debug_target_options (args
, " ");
31463 fprintf (stderr
, "\n");
31466 fprintf (stderr
, "flags: 0x%x\n", flags
);
31468 fprintf (stderr
, "--------------------\n");
31471 old_optimize
= build_optimization_node (&global_options
);
31472 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
31474 /* If the function changed the optimization levels as well as setting target
31475 options, start with the optimizations specified. */
31476 if (func_optimize
&& func_optimize
!= old_optimize
)
31477 cl_optimization_restore (&global_options
,
31478 TREE_OPTIMIZATION (func_optimize
));
31480 /* The target attributes may also change some optimization flags, so update
31481 the optimization options if necessary. */
31482 cl_target_option_save (&cur_target
, &global_options
);
31483 rs6000_cpu_index
= rs6000_tune_index
= -1;
31484 ret
= rs6000_inner_target_options (args
, true);
31486 /* Set up any additional state. */
31489 ret
= rs6000_option_override_internal (false);
31490 new_target
= build_target_option_node (&global_options
);
31495 new_optimize
= build_optimization_node (&global_options
);
31502 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
31504 if (old_optimize
!= new_optimize
)
31505 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
31508 cl_target_option_restore (&global_options
, &cur_target
);
31510 if (old_optimize
!= new_optimize
)
31511 cl_optimization_restore (&global_options
,
31512 TREE_OPTIMIZATION (old_optimize
));
31518 /* Hook to validate the current #pragma GCC target and set the state, and
31519 update the macros based on what was changed. If ARGS is NULL, then
31520 POP_TARGET is used to reset the options. */
31523 rs6000_pragma_target_parse (tree args
, tree pop_target
)
31525 tree prev_tree
= build_target_option_node (&global_options
);
31527 struct cl_target_option
*prev_opt
, *cur_opt
;
31528 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
31529 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
31531 if (TARGET_DEBUG_TARGET
)
31533 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
31534 fprintf (stderr
, "args:");
31535 rs6000_debug_target_options (args
, " ");
31536 fprintf (stderr
, "\n");
31540 fprintf (stderr
, "pop_target:\n");
31541 debug_tree (pop_target
);
31544 fprintf (stderr
, "pop_target: <NULL>\n");
31546 fprintf (stderr
, "--------------------\n");
31551 cur_tree
= ((pop_target
)
31553 : target_option_default_node
);
31554 cl_target_option_restore (&global_options
,
31555 TREE_TARGET_OPTION (cur_tree
));
31559 rs6000_cpu_index
= rs6000_tune_index
= -1;
31560 if (!rs6000_inner_target_options (args
, false)
31561 || !rs6000_option_override_internal (false)
31562 || (cur_tree
= build_target_option_node (&global_options
))
31565 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
31566 fprintf (stderr
, "invalid pragma\n");
31572 target_option_current_node
= cur_tree
;
31574 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
31575 change the macros that are defined. */
31576 if (rs6000_target_modify_macros_ptr
)
31578 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
31579 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
31580 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
31582 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
31583 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
31584 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
31586 diff_bumask
= (prev_bumask
^ cur_bumask
);
31587 diff_flags
= (prev_flags
^ cur_flags
);
31589 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
31591 /* Delete old macros. */
31592 rs6000_target_modify_macros_ptr (false,
31593 prev_flags
& diff_flags
,
31594 prev_bumask
& diff_bumask
);
31596 /* Define new macros. */
31597 rs6000_target_modify_macros_ptr (true,
31598 cur_flags
& diff_flags
,
31599 cur_bumask
& diff_bumask
);
31607 /* Remember the last target of rs6000_set_current_function. */
31608 static GTY(()) tree rs6000_previous_fndecl
;
31610 /* Establish appropriate back-end context for processing the function
31611 FNDECL. The argument might be NULL to indicate processing at top
31612 level, outside of any function scope. */
31614 rs6000_set_current_function (tree fndecl
)
31616 tree old_tree
= (rs6000_previous_fndecl
31617 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
31620 tree new_tree
= (fndecl
31621 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
31624 if (TARGET_DEBUG_TARGET
)
31626 bool print_final
= false;
31627 fprintf (stderr
, "\n==================== rs6000_set_current_function");
31630 fprintf (stderr
, ", fndecl %s (%p)",
31631 (DECL_NAME (fndecl
)
31632 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
31633 : "<unknown>"), (void *)fndecl
);
31635 if (rs6000_previous_fndecl
)
31636 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
31638 fprintf (stderr
, "\n");
31641 fprintf (stderr
, "\nnew fndecl target specific options:\n");
31642 debug_tree (new_tree
);
31643 print_final
= true;
31648 fprintf (stderr
, "\nold fndecl target specific options:\n");
31649 debug_tree (old_tree
);
31650 print_final
= true;
31654 fprintf (stderr
, "--------------------\n");
31657 /* Only change the context if the function changes. This hook is called
31658 several times in the course of compiling a function, and we don't want to
31659 slow things down too much or call target_reinit when it isn't safe. */
31660 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
31662 rs6000_previous_fndecl
= fndecl
;
31663 if (old_tree
== new_tree
)
31668 cl_target_option_restore (&global_options
,
31669 TREE_TARGET_OPTION (new_tree
));
31670 if (TREE_TARGET_GLOBALS (new_tree
))
31671 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
31673 TREE_TARGET_GLOBALS (new_tree
)
31674 = save_target_globals_default_opts ();
31679 new_tree
= target_option_current_node
;
31680 cl_target_option_restore (&global_options
,
31681 TREE_TARGET_OPTION (new_tree
));
31682 if (TREE_TARGET_GLOBALS (new_tree
))
31683 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
31684 else if (new_tree
== target_option_default_node
)
31685 restore_target_globals (&default_target_globals
);
31687 TREE_TARGET_GLOBALS (new_tree
)
31688 = save_target_globals_default_opts ();
31694 /* Save the current options */
31697 rs6000_function_specific_save (struct cl_target_option
*ptr
,
31698 struct gcc_options
*opts
)
31700 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
31701 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
31704 /* Restore the current options */
31707 rs6000_function_specific_restore (struct gcc_options
*opts
,
31708 struct cl_target_option
*ptr
)
31711 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
31712 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
31713 (void) rs6000_option_override_internal (false);
31716 /* Print the current options */
31719 rs6000_function_specific_print (FILE *file
, int indent
,
31720 struct cl_target_option
*ptr
)
31722 rs6000_print_isa_options (file
, indent
, "Isa options set",
31723 ptr
->x_rs6000_isa_flags
);
31725 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
31726 ptr
->x_rs6000_isa_flags_explicit
);
31729 /* Helper function to print the current isa or misc options on a line. */
31732 rs6000_print_options_internal (FILE *file
,
31734 const char *string
,
31735 HOST_WIDE_INT flags
,
31736 const char *prefix
,
31737 const struct rs6000_opt_mask
*opts
,
31738 size_t num_elements
)
31741 size_t start_column
= 0;
31743 size_t max_column
= 76;
31744 const char *comma
= "";
31747 start_column
+= fprintf (file
, "%*s", indent
, "");
31751 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
31755 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
31757 /* Print the various mask options. */
31758 cur_column
= start_column
;
31759 for (i
= 0; i
< num_elements
; i
++)
31761 if ((flags
& opts
[i
].mask
) != 0)
31763 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
31764 size_t len
= (strlen (comma
)
31767 + strlen (rs6000_opt_masks
[i
].name
));
31770 if (cur_column
> max_column
)
31772 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
31773 cur_column
= start_column
+ len
;
31777 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
31778 rs6000_opt_masks
[i
].name
);
31779 flags
&= ~ opts
[i
].mask
;
31784 fputs ("\n", file
);
31787 /* Helper function to print the current isa options on a line. */
31790 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
31791 HOST_WIDE_INT flags
)
31793 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
31794 &rs6000_opt_masks
[0],
31795 ARRAY_SIZE (rs6000_opt_masks
));
31799 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
31800 HOST_WIDE_INT flags
)
31802 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
31803 &rs6000_builtin_mask_names
[0],
31804 ARRAY_SIZE (rs6000_builtin_mask_names
));
31808 /* Hook to determine if one function can safely inline another. */
31811 rs6000_can_inline_p (tree caller
, tree callee
)
31814 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
31815 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
31817 /* If callee has no option attributes, then it is ok to inline. */
31821 /* If caller has no option attributes, but callee does then it is not ok to
31823 else if (!caller_tree
)
31828 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
31829 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
31831 /* Callee's options should a subset of the caller's, i.e. a vsx function
31832 can inline an altivec function but a non-vsx function can't inline a
31834 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
31835 == callee_opts
->x_rs6000_isa_flags
)
31839 if (TARGET_DEBUG_TARGET
)
31840 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
31841 (DECL_NAME (caller
)
31842 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
31844 (DECL_NAME (callee
)
31845 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
31847 (ret
? "can" : "cannot"));
31852 /* Allocate a stack temp and fixup the address so it meets the particular
31853 memory requirements (either offetable or REG+REG addressing). */
31856 rs6000_allocate_stack_temp (enum machine_mode mode
,
31857 bool offsettable_p
,
31860 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
31861 rtx addr
= XEXP (stack
, 0);
31862 int strict_p
= (reload_in_progress
|| reload_completed
);
31864 if (!legitimate_indirect_address_p (addr
, strict_p
))
31867 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
31868 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
31870 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
31871 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
31877 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
31878 to such a form to deal with memory reference instructions like STFIWX that
31879 only take reg+reg addressing. */
31882 rs6000_address_for_fpconvert (rtx x
)
31884 int strict_p
= (reload_in_progress
|| reload_completed
);
31887 gcc_assert (MEM_P (x
));
31888 addr
= XEXP (x
, 0);
31889 if (! legitimate_indirect_address_p (addr
, strict_p
)
31890 && ! legitimate_indexed_address_p (addr
, strict_p
))
31892 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
31894 rtx reg
= XEXP (addr
, 0);
31895 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
31896 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
31897 gcc_assert (REG_P (reg
));
31898 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
31901 else if (GET_CODE (addr
) == PRE_MODIFY
)
31903 rtx reg
= XEXP (addr
, 0);
31904 rtx expr
= XEXP (addr
, 1);
31905 gcc_assert (REG_P (reg
));
31906 gcc_assert (GET_CODE (expr
) == PLUS
);
31907 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
31911 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
31917 /* Given a memory reference, if it is not in the form for altivec memory
31918 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
31919 convert to the altivec format. */
31922 rs6000_address_for_altivec (rtx x
)
31924 gcc_assert (MEM_P (x
));
31925 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
31927 rtx addr
= XEXP (x
, 0);
31928 int strict_p
= (reload_in_progress
|| reload_completed
);
31930 if (!legitimate_indexed_address_p (addr
, strict_p
)
31931 && !legitimate_indirect_address_p (addr
, strict_p
))
31932 addr
= copy_to_mode_reg (Pmode
, addr
);
31934 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
31935 x
= change_address (x
, GET_MODE (x
), addr
);
31941 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
31943 On the RS/6000, all integer constants are acceptable, most won't be valid
31944 for particular insns, though. Only easy FP constants are acceptable. */
31947 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
31949 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
31952 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
31953 || GET_MODE (x
) == VOIDmode
31954 || (TARGET_POWERPC64
&& mode
== DImode
)
31955 || easy_fp_constant (x
, mode
)
31956 || easy_vector_constant (x
, mode
));
31961 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
31964 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
31966 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
31967 rtx toc_load
= NULL_RTX
;
31968 rtx toc_restore
= NULL_RTX
;
31970 rtx abi_reg
= NULL_RTX
;
31975 /* Handle longcall attributes. */
31976 if (INTVAL (cookie
) & CALL_LONG
)
31977 func_desc
= rs6000_longcall_ref (func_desc
);
31979 /* Handle indirect calls. */
31980 if (GET_CODE (func_desc
) != SYMBOL_REF
31981 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
31983 /* Save the TOC into its reserved slot before the call,
31984 and prepare to restore it after the call. */
31985 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
31986 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
31987 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
31988 gen_rtx_PLUS (Pmode
, stack_ptr
,
31989 stack_toc_offset
));
31990 toc_restore
= gen_rtx_SET (VOIDmode
, toc_reg
, stack_toc_mem
);
31992 /* Can we optimize saving the TOC in the prologue or
31993 do we need to do it at every call? */
31994 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
31995 cfun
->machine
->save_toc_in_prologue
= true;
31998 MEM_VOLATILE_P (stack_toc_mem
) = 1;
31999 emit_move_insn (stack_toc_mem
, toc_reg
);
32002 if (DEFAULT_ABI
== ABI_ELFv2
)
32004 /* A function pointer in the ELFv2 ABI is just a plain address, but
32005 the ABI requires it to be loaded into r12 before the call. */
32006 func_addr
= gen_rtx_REG (Pmode
, 12);
32007 emit_move_insn (func_addr
, func_desc
);
32008 abi_reg
= func_addr
;
32012 /* A function pointer under AIX is a pointer to a data area whose
32013 first word contains the actual address of the function, whose
32014 second word contains a pointer to its TOC, and whose third word
32015 contains a value to place in the static chain register (r11).
32016 Note that if we load the static chain, our "trampoline" need
32017 not have any executable code. */
32019 /* Load up address of the actual function. */
32020 func_desc
= force_reg (Pmode
, func_desc
);
32021 func_addr
= gen_reg_rtx (Pmode
);
32022 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
32024 /* Prepare to load the TOC of the called function. Note that the
32025 TOC load must happen immediately before the actual call so
32026 that unwinding the TOC registers works correctly. See the
32027 comment in frob_update_context. */
32028 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
32029 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
32030 gen_rtx_PLUS (Pmode
, func_desc
,
32032 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
32034 /* If we have a static chain, load it up. */
32035 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
32037 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
32038 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
32039 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
32040 gen_rtx_PLUS (Pmode
, func_desc
,
32042 emit_move_insn (sc_reg
, func_sc_mem
);
32049 /* Direct calls use the TOC: for local calls, the callee will
32050 assume the TOC register is set; for non-local calls, the
32051 PLT stub needs the TOC register. */
32053 func_addr
= func_desc
;
32056 /* Create the call. */
32057 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
32058 if (value
!= NULL_RTX
)
32059 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
32063 call
[n_call
++] = toc_load
;
32065 call
[n_call
++] = toc_restore
;
32067 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
32069 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
32070 insn
= emit_call_insn (insn
);
32072 /* Mention all registers defined by the ABI to hold information
32073 as uses in CALL_INSN_FUNCTION_USAGE. */
32075 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
32078 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
32081 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
32086 gcc_assert (INTVAL (cookie
) == 0);
32088 /* Create the call. */
32089 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
32090 if (value
!= NULL_RTX
)
32091 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
32093 call
[1] = simple_return_rtx
;
32095 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
32096 insn
= emit_call_insn (insn
);
32098 /* Note use of the TOC register. */
32099 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
32100 /* We need to also mark a use of the link register since the function we
32101 sibling-call to will use it to return to our caller. */
32102 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, LR_REGNO
));
32105 /* Return whether we need to always update the saved TOC pointer when we update
32106 the stack pointer. */
32109 rs6000_save_toc_in_prologue_p (void)
32111 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
32114 #ifdef HAVE_GAS_HIDDEN
32115 # define USE_HIDDEN_LINKONCE 1
32117 # define USE_HIDDEN_LINKONCE 0
32120 /* Fills in the label name that should be used for a 476 link stack thunk. */
32123 get_ppc476_thunk_name (char name
[32])
32125 gcc_assert (TARGET_LINK_STACK
);
32127 if (USE_HIDDEN_LINKONCE
)
32128 sprintf (name
, "__ppc476.get_thunk");
32130 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
32133 /* This function emits the simple thunk routine that is used to preserve
32134 the link stack on the 476 cpu. */
32136 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
32138 rs6000_code_end (void)
32143 if (!TARGET_LINK_STACK
)
32146 get_ppc476_thunk_name (name
);
32148 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
32149 build_function_type_list (void_type_node
, NULL_TREE
));
32150 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
32151 NULL_TREE
, void_type_node
);
32152 TREE_PUBLIC (decl
) = 1;
32153 TREE_STATIC (decl
) = 1;
32156 if (USE_HIDDEN_LINKONCE
)
32158 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
32159 targetm
.asm_out
.unique_section (decl
, 0);
32160 switch_to_section (get_named_section (decl
, NULL
, 0));
32161 DECL_WEAK (decl
) = 1;
32162 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
32163 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
32164 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
32165 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
32170 switch_to_section (text_section
);
32171 ASM_OUTPUT_LABEL (asm_out_file
, name
);
32174 DECL_INITIAL (decl
) = make_node (BLOCK
);
32175 current_function_decl
= decl
;
32176 init_function_start (decl
);
32177 first_function_block_is_cold
= false;
32178 /* Make sure unwind info is emitted for the thunk if needed. */
32179 final_start_function (emit_barrier (), asm_out_file
, 1);
32181 fputs ("\tblr\n", asm_out_file
);
32183 final_end_function ();
32184 init_insn_lengths ();
32185 free_after_compilation (cfun
);
32187 current_function_decl
= NULL
;
32190 /* Add r30 to hard reg set if the prologue sets it up and it is not
32191 pic_offset_table_rtx. */
32194 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
32196 if (!TARGET_SINGLE_PIC_BASE
32198 && TARGET_MINIMAL_TOC
32199 && get_pool_size () != 0)
32200 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
32204 /* Helper function for rs6000_split_logical to emit a logical instruction after
32205 spliting the operation to single GPR registers.
32207 DEST is the destination register.
32208 OP1 and OP2 are the input source registers.
32209 CODE is the base operation (AND, IOR, XOR, NOT).
32210 MODE is the machine mode.
32211 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32212 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32213 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
32214 CLOBBER_REG is either NULL or a scratch register of type CC to allow
32215 formation of the AND instructions. */
32218 rs6000_split_logical_inner (rtx dest
,
32221 enum rtx_code code
,
32222 enum machine_mode mode
,
32223 bool complement_final_p
,
32224 bool complement_op1_p
,
32225 bool complement_op2_p
,
32231 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
32232 if (op2
&& GET_CODE (op2
) == CONST_INT
32233 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
32234 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
32236 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
32237 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
32239 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
32244 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
32248 else if (value
== mask
)
32250 if (!rtx_equal_p (dest
, op1
))
32251 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
32256 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
32257 into separate ORI/ORIS or XORI/XORIS instrucitons. */
32258 else if (code
== IOR
|| code
== XOR
)
32262 if (!rtx_equal_p (dest
, op1
))
32263 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
32269 if (complement_op1_p
)
32270 op1
= gen_rtx_NOT (mode
, op1
);
32272 if (complement_op2_p
)
32273 op2
= gen_rtx_NOT (mode
, op2
);
32275 bool_rtx
= ((code
== NOT
)
32276 ? gen_rtx_NOT (mode
, op1
)
32277 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
32279 if (complement_final_p
)
32280 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
32282 set_rtx
= gen_rtx_SET (VOIDmode
, dest
, bool_rtx
);
32284 /* Is this AND with an explicit clobber? */
32287 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, clobber_reg
);
32288 set_rtx
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set_rtx
, clobber
));
32291 emit_insn (set_rtx
);
32295 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
32296 operations are split immediately during RTL generation to allow for more
32297 optimizations of the AND/IOR/XOR.
32299 OPERANDS is an array containing the destination and two input operands.
32300 CODE is the base operation (AND, IOR, XOR, NOT).
32301 MODE is the machine mode.
32302 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32303 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32304 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
32305 CLOBBER_REG is either NULL or a scratch register of type CC to allow
32306 formation of the AND instructions. */
32309 rs6000_split_logical_di (rtx operands
[3],
32310 enum rtx_code code
,
32311 bool complement_final_p
,
32312 bool complement_op1_p
,
32313 bool complement_op2_p
,
32316 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
32317 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
32318 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
32319 enum hi_lo
{ hi
= 0, lo
= 1 };
32320 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
32323 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
32324 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
32325 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
32326 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
32329 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
32332 if (GET_CODE (operands
[2]) != CONST_INT
)
32334 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
32335 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
32339 HOST_WIDE_INT value
= INTVAL (operands
[2]);
32340 HOST_WIDE_INT value_hi_lo
[2];
32342 gcc_assert (!complement_final_p
);
32343 gcc_assert (!complement_op1_p
);
32344 gcc_assert (!complement_op2_p
);
32346 value_hi_lo
[hi
] = value
>> 32;
32347 value_hi_lo
[lo
] = value
& lower_32bits
;
32349 for (i
= 0; i
< 2; i
++)
32351 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
32353 if (sub_value
& sign_bit
)
32354 sub_value
|= upper_32bits
;
32356 op2_hi_lo
[i
] = GEN_INT (sub_value
);
32358 /* If this is an AND instruction, check to see if we need to load
32359 the value in a register. */
32360 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
32361 && !and_operand (op2_hi_lo
[i
], SImode
))
32362 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
32367 for (i
= 0; i
< 2; i
++)
32369 /* Split large IOR/XOR operations. */
32370 if ((code
== IOR
|| code
== XOR
)
32371 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
32372 && !complement_final_p
32373 && !complement_op1_p
32374 && !complement_op2_p
32375 && clobber_reg
== NULL_RTX
32376 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
32378 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
32379 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
32380 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
32381 rtx tmp
= gen_reg_rtx (SImode
);
32383 /* Make sure the constant is sign extended. */
32384 if ((hi_16bits
& sign_bit
) != 0)
32385 hi_16bits
|= upper_32bits
;
32387 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
32388 code
, SImode
, false, false, false,
32391 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
32392 code
, SImode
, false, false, false,
32396 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
32397 code
, SImode
, complement_final_p
,
32398 complement_op1_p
, complement_op2_p
,
32405 /* Split the insns that make up boolean operations operating on multiple GPR
32406 registers. The boolean MD patterns ensure that the inputs either are
32407 exactly the same as the output registers, or there is no overlap.
32409 OPERANDS is an array containing the destination and two input operands.
32410 CODE is the base operation (AND, IOR, XOR, NOT).
32411 MODE is the machine mode.
32412 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32413 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32414 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
32415 CLOBBER_REG is either NULL or a scratch register of type CC to allow
32416 formation of the AND instructions. */
32419 rs6000_split_logical (rtx operands
[3],
32420 enum rtx_code code
,
32421 bool complement_final_p
,
32422 bool complement_op1_p
,
32423 bool complement_op2_p
,
32426 enum machine_mode mode
= GET_MODE (operands
[0]);
32427 enum machine_mode sub_mode
;
32429 int sub_size
, regno0
, regno1
, nregs
, i
;
32431 /* If this is DImode, use the specialized version that can run before
32432 register allocation. */
32433 if (mode
== DImode
&& !TARGET_POWERPC64
)
32435 rs6000_split_logical_di (operands
, code
, complement_final_p
,
32436 complement_op1_p
, complement_op2_p
,
32443 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
32444 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
32445 sub_size
= GET_MODE_SIZE (sub_mode
);
32446 regno0
= REGNO (op0
);
32447 regno1
= REGNO (op1
);
32449 gcc_assert (reload_completed
);
32450 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
32451 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
32453 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
32454 gcc_assert (nregs
> 1);
32456 if (op2
&& REG_P (op2
))
32457 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
32459 for (i
= 0; i
< nregs
; i
++)
32461 int offset
= i
* sub_size
;
32462 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
32463 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
32464 rtx sub_op2
= ((code
== NOT
)
32466 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
32468 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
32469 complement_final_p
, complement_op1_p
,
32470 complement_op2_p
, clobber_reg
);
32477 /* Return true if the peephole2 can combine a load involving a combination of
32478 an addis instruction and a load with an offset that can be fused together on
32482 operands[0] register set with addis
32483 operands[1] value set via addis
32484 operands[2] target register being loaded
32485 operands[3] D-form memory reference using operands[0].
32487 In addition, we are passed a boolean that is true if this is a peephole2,
32488 and we can use see if the addis_reg is dead after the insn and can be
32489 replaced by the target register. */
32492 fusion_gpr_load_p (rtx
*operands
, bool peep2_p
)
32494 rtx addis_reg
= operands
[0];
32495 rtx addis_value
= operands
[1];
32496 rtx target
= operands
[2];
32497 rtx mem
= operands
[3];
32501 /* Validate arguments. */
32502 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
32505 if (!base_reg_operand (target
, GET_MODE (target
)))
32508 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
32511 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
32514 /* Allow sign/zero extension. */
32515 if (GET_CODE (mem
) == ZERO_EXTEND
32516 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
32517 mem
= XEXP (mem
, 0);
32522 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
32523 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
32526 /* Validate that the register used to load the high value is either the
32527 register being loaded, or we can safely replace its use in a peephole2.
32529 If this is a peephole2, we assume that there are 2 instructions in the
32530 peephole (addis and load), so we want to check if the target register was
32531 not used in the memory address and the register to hold the addis result
32532 is dead after the peephole. */
32533 if (REGNO (addis_reg
) != REGNO (target
))
32538 if (reg_mentioned_p (target
, mem
))
32541 if (!peep2_reg_dead_p (2, addis_reg
))
32544 /* If the target register being loaded is the stack pointer, we must
32545 avoid loading any other value into it, even temporarily. */
32546 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
32550 base_reg
= XEXP (addr
, 0);
32551 return REGNO (addis_reg
) == REGNO (base_reg
);
32554 /* During the peephole2 pass, adjust and expand the insns for a load fusion
32555 sequence. We adjust the addis register to use the target register. If the
32556 load sign extends, we adjust the code to do the zero extending load, and an
32557 explicit sign extension later since the fusion only covers zero extending
32561 operands[0] register set with addis (to be replaced with target)
32562 operands[1] value set via addis
32563 operands[2] target register being loaded
32564 operands[3] D-form memory reference using operands[0]. */
32567 expand_fusion_gpr_load (rtx
*operands
)
32569 rtx addis_value
= operands
[1];
32570 rtx target
= operands
[2];
32571 rtx orig_mem
= operands
[3];
32572 rtx new_addr
, new_mem
, orig_addr
, offset
;
32573 enum rtx_code plus_or_lo_sum
;
32574 enum machine_mode target_mode
= GET_MODE (target
);
32575 enum machine_mode extend_mode
= target_mode
;
32576 enum machine_mode ptr_mode
= Pmode
;
32577 enum rtx_code extend
= UNKNOWN
;
32578 rtx addis_reg
= ((ptr_mode
== target_mode
)
32580 : simplify_subreg (ptr_mode
, target
, target_mode
, 0));
32582 if (GET_CODE (orig_mem
) == ZERO_EXTEND
32583 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
32585 extend
= GET_CODE (orig_mem
);
32586 orig_mem
= XEXP (orig_mem
, 0);
32587 target_mode
= GET_MODE (orig_mem
);
32590 gcc_assert (MEM_P (orig_mem
));
32592 orig_addr
= XEXP (orig_mem
, 0);
32593 plus_or_lo_sum
= GET_CODE (orig_addr
);
32594 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
32596 offset
= XEXP (orig_addr
, 1);
32597 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_reg
, offset
);
32598 new_mem
= change_address (orig_mem
, target_mode
, new_addr
);
32600 if (extend
!= UNKNOWN
)
32601 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
32603 emit_insn (gen_rtx_SET (VOIDmode
, addis_reg
, addis_value
));
32604 emit_insn (gen_rtx_SET (VOIDmode
, target
, new_mem
));
32606 if (extend
== SIGN_EXTEND
)
32608 int sub_off
= ((BYTES_BIG_ENDIAN
)
32609 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
32612 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
32614 emit_insn (gen_rtx_SET (VOIDmode
, target
,
32615 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
32621 /* Return a string to fuse an addis instruction with a gpr load to the same
32622 register that we loaded up the addis instruction. The code is complicated,
32623 so we call output_asm_insn directly, and just return "".
32626 operands[0] register set with addis (must be same reg as target).
32627 operands[1] value set via addis
32628 operands[2] target register being loaded
32629 operands[3] D-form memory reference using operands[0]. */
32632 emit_fusion_gpr_load (rtx
*operands
)
32634 rtx addis_reg
= operands
[0];
32635 rtx addis_value
= operands
[1];
32636 rtx target
= operands
[2];
32637 rtx mem
= operands
[3];
32641 const char *addis_str
= NULL
;
32642 const char *load_str
= NULL
;
32643 const char *extend_insn
= NULL
;
32644 const char *mode_name
= NULL
;
32645 char insn_template
[80];
32646 enum machine_mode mode
;
32647 const char *comment_str
= ASM_COMMENT_START
;
32648 bool sign_p
= false;
32650 gcc_assert (REG_P (addis_reg
) && REG_P (target
));
32651 gcc_assert (REGNO (addis_reg
) == REGNO (target
));
32653 if (*comment_str
== ' ')
32656 /* Allow sign/zero extension. */
32657 if (GET_CODE (mem
) == ZERO_EXTEND
)
32658 mem
= XEXP (mem
, 0);
32660 else if (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
)
32663 mem
= XEXP (mem
, 0);
32666 gcc_assert (MEM_P (mem
));
32667 addr
= XEXP (mem
, 0);
32668 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
32669 gcc_unreachable ();
32671 load_offset
= XEXP (addr
, 1);
32673 /* Now emit the load instruction to the same register. */
32674 mode
= GET_MODE (mem
);
32678 mode_name
= "char";
32680 extend_insn
= "extsb %0,%0";
32684 mode_name
= "short";
32686 extend_insn
= "extsh %0,%0";
32692 extend_insn
= "extsw %0,%0";
32696 if (TARGET_POWERPC64
)
32698 mode_name
= "long";
32702 gcc_unreachable ();
32706 gcc_unreachable ();
32709 /* Emit the addis instruction. */
32710 fuse_ops
[0] = target
;
32711 if (satisfies_constraint_L (addis_value
))
32713 fuse_ops
[1] = addis_value
;
32714 addis_str
= "lis %0,%v1";
32717 else if (GET_CODE (addis_value
) == PLUS
)
32719 rtx op0
= XEXP (addis_value
, 0);
32720 rtx op1
= XEXP (addis_value
, 1);
32722 if (REG_P (op0
) && CONST_INT_P (op1
)
32723 && satisfies_constraint_L (op1
))
32727 addis_str
= "addis %0,%1,%v2";
32731 else if (GET_CODE (addis_value
) == HIGH
)
32733 rtx value
= XEXP (addis_value
, 0);
32734 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
32736 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
32737 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
32739 addis_str
= "addis %0,%2,%1@toc@ha";
32741 else if (TARGET_XCOFF
)
32742 addis_str
= "addis %0,%1@u(%2)";
32745 gcc_unreachable ();
32748 else if (GET_CODE (value
) == PLUS
)
32750 rtx op0
= XEXP (value
, 0);
32751 rtx op1
= XEXP (value
, 1);
32753 if (GET_CODE (op0
) == UNSPEC
32754 && XINT (op0
, 1) == UNSPEC_TOCREL
32755 && CONST_INT_P (op1
))
32757 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
32758 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
32761 addis_str
= "addis %0,%2,%1+%3@toc@ha";
32763 else if (TARGET_XCOFF
)
32764 addis_str
= "addis %0,%1+%3@u(%2)";
32767 gcc_unreachable ();
32771 else if (satisfies_constraint_L (value
))
32773 fuse_ops
[1] = value
;
32774 addis_str
= "lis %0,%v1";
32777 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
32779 fuse_ops
[1] = value
;
32780 addis_str
= "lis %0,%1@ha";
32785 fatal_insn ("Could not generate addis value for fusion", addis_value
);
32787 sprintf (insn_template
, "%s\t\t%s gpr load fusion, type %s", addis_str
,
32788 comment_str
, mode_name
);
32789 output_asm_insn (insn_template
, fuse_ops
);
32791 /* Emit the D-form load instruction. */
32792 if (CONST_INT_P (load_offset
) && satisfies_constraint_I (load_offset
))
32794 sprintf (insn_template
, "%s %%0,%%1(%%0)", load_str
);
32795 fuse_ops
[1] = load_offset
;
32796 output_asm_insn (insn_template
, fuse_ops
);
32799 else if (GET_CODE (load_offset
) == UNSPEC
32800 && XINT (load_offset
, 1) == UNSPEC_TOCREL
)
32803 sprintf (insn_template
, "%s %%0,%%1@toc@l(%%0)", load_str
);
32805 else if (TARGET_XCOFF
)
32806 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
32809 gcc_unreachable ();
32811 fuse_ops
[1] = XVECEXP (load_offset
, 0, 0);
32812 output_asm_insn (insn_template
, fuse_ops
);
32815 else if (GET_CODE (load_offset
) == PLUS
32816 && GET_CODE (XEXP (load_offset
, 0)) == UNSPEC
32817 && XINT (XEXP (load_offset
, 0), 1) == UNSPEC_TOCREL
32818 && CONST_INT_P (XEXP (load_offset
, 1)))
32820 rtx tocrel_unspec
= XEXP (load_offset
, 0);
32822 sprintf (insn_template
, "%s %%0,%%1+%%2@toc@l(%%0)", load_str
);
32824 else if (TARGET_XCOFF
)
32825 sprintf (insn_template
, "%s %%0,%%1+%%2@l(%%0)", load_str
);
32828 gcc_unreachable ();
32830 fuse_ops
[1] = XVECEXP (tocrel_unspec
, 0, 0);
32831 fuse_ops
[2] = XEXP (load_offset
, 1);
32832 output_asm_insn (insn_template
, fuse_ops
);
32835 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (load_offset
))
32837 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
32839 fuse_ops
[1] = load_offset
;
32840 output_asm_insn (insn_template
, fuse_ops
);
32844 fatal_insn ("Unable to generate load offset for fusion", load_offset
);
32846 /* Handle sign extension. The peephole2 pass generates this as a separate
32847 insn, but we handle it just in case it got reattached. */
32850 gcc_assert (extend_insn
!= NULL
);
32851 output_asm_insn (extend_insn
, fuse_ops
);
32858 struct gcc_target targetm
= TARGET_INITIALIZER
;
32860 #include "gt-rs6000.h"