1 ;; Machine Description for Renesas RL78 processors
2 ;; Copyright (C) 2011-2015 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
50 (UNS_TRAMPOLINE_INIT 20)
51 (UNS_TRAMPOLINE_UNINIT 21)
52 (UNS_NONLOCAL_GOTO 22)
62 (define_mode_iterator QHI [QI HI])
64 (include "predicates.md")
65 (include "constraints.md")
66 (include "rl78-expand.md")
67 (include "rl78-virt.md")
68 (include "rl78-real.md")
71 ;; Function Prologue/Epilogue Instructions
73 (define_expand "prologue"
76 "rl78_expand_prologue (); DONE;"
79 (define_expand "epilogue"
82 "rl78_expand_epilogue (); DONE;"
85 (define_expand "sibcall_epilogue"
91 (define_insn "rl78_return"
97 (define_insn "interrupt_return"
98 [(unspec_volatile [(return)] UNS_RETI) ]
103 (define_insn "brk_interrupt_return"
104 [(unspec_volatile [(return)] UNS_RETB) ]
109 (define_expand "eh_return"
110 [(match_operand:HI 0 "")]
112 "rl78_expand_eh_epilogue (operands[0]);
117 ;; These are used only by prologue/epilogue so it's "safe" to pass
118 ;; virtual registers.
120 [(set (reg:HI SP_REG)
121 (plus:HI (reg:HI SP_REG)
123 (set (mem:HI (reg:HI SP_REG))
124 (match_operand:HI 0 "register_operand" "ABDT,vZint"))]
132 [(set (match_operand:HI 0 "register_operand" "=ABDT,vZint")
133 (mem:HI (reg:HI SP_REG)))
135 (plus:HI (reg:HI SP_REG)
143 (define_insn "sel_rb"
144 [(unspec_volatile [(match_operand 0 "immediate_operand" "")] UNS_SET_RB)]
149 (define_insn "trampoline_init"
150 [(set (match_operand 0 "register_operand" "=Z08W")
151 (unspec_volatile [(match_operand 1 "register_operand" "Z08W")
152 (match_operand 2 "register_operand" "Z10W")
153 ] UNS_TRAMPOLINE_INIT))
156 "call !!___trampoline_init ; %0 <= %1 %2"
159 (define_insn "trampoline_uninit"
160 [(unspec_volatile [(const_int 0)] UNS_TRAMPOLINE_UNINIT)
163 "call !!___trampoline_uninit"
166 ;; GCC restores $fp *before* using it to access values on the *old*
167 ;; frame. So, we do it ourselves, to ensure this is not the case.
168 ;; Note that while %1 is usually a label_ref, we allow for a
169 ;; non-immediate as well.
170 (define_expand "nonlocal_goto"
172 (unspec_volatile [(match_operand 0 "") ;; fp (ignore)
173 (match_operand 1 "") ;; target
174 (match_operand 2 "") ;; sp
175 (match_operand 3 "") ;; ?
176 ] UNS_NONLOCAL_GOTO))
179 "emit_jump_insn (gen_nonlocal_goto_insn (operands[0], operands[1], operands[2], operands[3]));
184 (define_insn "nonlocal_goto_insn"
186 (unspec_volatile [(match_operand 0 "" "") ;; fp (ignore)
187 (match_operand 1 "" "vi") ;; target
188 (match_operand 2 "" "vi") ;; sp
189 (match_operand 3 "" "vi") ;; ?
190 ] UNS_NONLOCAL_GOTO))
203 (define_expand "es_addr"
204 [(unspec:SI [(reg:QI ES_REG)
205 (match_operand:HI 0 "")
211 ;;======================================================================
213 ;; "macro" insns - cases where inline chunks of code are more
214 ;; efficient than anything else.
216 (define_expand "addsi3"
217 [(set (match_operand:SI 0 "nonimmediate_operand" "=&vm")
218 (plus:SI (match_operand:SI 1 "general_operand" "vim")
219 (match_operand 2 "general_operand" "vim")))
222 "emit_insn (gen_addsi3_internal_virt (operands[0], operands[1], operands[2]));
226 (define_insn "addsi3_internal_virt"
227 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vm, vm")
228 (plus:SI (match_operand:SI 1 "general_operand" "0, vim, vim")
229 (match_operand 2 "general_operand" "vim,vim,vim")))
230 (clobber (reg:HI AX_REG))
231 (clobber (reg:HI BC_REG))
233 "rl78_virt_insns_ok ()"
235 [(set_attr "valloc" "macax")]
238 (define_insn "addsi3_internal_real"
239 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vU, vU")
240 (plus:SI (match_operand:SI 1 "general_operand" "+0, viU, viU")
241 (match_operand 2 "general_operand" "viWabWhlWh1,viWabWhlWh1,viWabWhlWh1")))
242 (clobber (reg:HI AX_REG))
243 (clobber (reg:HI BC_REG))
245 "rl78_real_insns_ok ()"
246 { return rl78_addsi3_internal (operands, which_alternative); }
247 [(set_attr "valloc" "macax")]
250 (define_expand "subsi3"
251 [(set (match_operand:SI 0 "nonimmediate_operand")
252 (minus:SI (match_operand:SI 1 "general_operand")
253 (match_operand 2 "general_operand")))
256 "emit_insn (gen_subsi3_internal_virt (operands[0], operands[1], operands[2]));
260 (define_insn "subsi3_internal_virt"
261 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vm, vm")
262 (minus:SI (match_operand:SI 1 "general_operand" "0, vim, vim")
263 (match_operand 2 "general_operand" "vim,vim,vim")))
264 (clobber (reg:HI AX_REG))
265 (clobber (reg:HI BC_REG))
267 "rl78_virt_insns_ok ()"
269 [(set_attr "valloc" "macax")]
272 (define_insn "subsi3_internal_real"
273 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vU, vU")
274 (minus:SI (match_operand:SI 1 "general_operand" "+0, viU, viU")
275 (match_operand 2 "general_operand" "viWabWhlWh1,viWabWhlWh1,viWabWhlWh1")))
276 (clobber (reg:HI AX_REG))
277 (clobber (reg:HI BC_REG))
279 "rl78_real_insns_ok ()"
281 movw ax,%h1 \;subw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax
282 movw ax,%h1 \;subw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax
283 movw ax,%h1 \;subw ax,%h2 \;movw bc, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax \;movw ax,bc \;movw %h0, ax"
284 [(set_attr "valloc" "macax")]
287 (define_expand "mulqi3"
289 [(set (match_operand:QI 0 "register_operand")
290 (mult:QI (match_operand:QI 1 "general_operand")
291 (match_operand:QI 2 "nonmemory_operand")))
292 (clobber (reg:HI AX_REG))
295 "" ; mulu supported by all targets
299 (define_expand "mulhi3"
300 [(set (match_operand:HI 0 "register_operand")
301 (mult:HI (match_operand:HI 1 "general_operand")
302 (match_operand:HI 2 "nonmemory_operand")))
307 emit_insn (gen_mulhi3_g14 (operands[0], operands[1], operands[2]));
308 else /* RL78_MUL_G13 */
309 emit_insn (gen_mulhi3_g13 (operands[0], operands[1], operands[2]));
314 (define_expand "mulsi3"
315 [(set (match_operand:SI 0 "register_operand")
316 (mult:SI (match_operand:SI 1 "general_operand")
317 (match_operand:SI 2 "nonmemory_operand")))
322 emit_insn (gen_mulsi3_g14 (operands[0], operands[1], operands[2]));
323 else /* RL78_MUL_G13 */
324 emit_insn (gen_mulsi3_g13 (operands[0], operands[1], operands[2]));
329 (define_insn "*mulqi3_rl78"
330 [(set (match_operand:QI 0 "register_operand" "=&v")
331 (mult:QI (match_operand:QI 1 "general_operand" "viU")
332 (match_operand:QI 2 "general_operand" "vi")))
333 (clobber (reg:HI AX_REG))
335 "" ; mulu supported by all targets
336 "; mulqi macro %0 = %1 * %2
343 ; end of mulqi macro"
344 [(set_attr "valloc" "macax")]
347 (define_insn "mulhi3_g14"
348 [(set (match_operand:HI 0 "register_operand" "=&v")
349 (mult:HI (match_operand:HI 1 "general_operand" "viU")
350 (match_operand:HI 2 "general_operand" "vi")))
351 (clobber (reg:HI AX_REG))
352 (clobber (reg:HI BC_REG))
355 "; G14 mulhi macro %0 = %1 * %2
358 mulhu ; bcax = bc * ax
360 ; end of mulhi macro"
361 [(set_attr "valloc" "macax")]
364 (define_insn "mulhi3_g13"
365 [(set (match_operand:HI 0 "register_operand" "=&v")
366 (mult:HI (match_operand:HI 1 "general_operand" "viU")
367 (match_operand:HI 2 "general_operand" "vi")))
368 (clobber (reg:HI AX_REG))
371 "; G13 mulhi macro %0 = %1 * %2
373 mov !0xf00e8, a ; MDUC
375 movw 0xffff0, ax ; MDAL
377 movw 0xffff2, ax ; MDAH
378 nop ; mdb = mdal * mdah
379 movw ax, 0xffff6 ; MDBL
381 ; end of mulhi macro"
382 [(set_attr "valloc" "macax")]
385 ;; 0xFFFF0 is MACR(L). 0xFFFF2 is MACR(H) but we don't care about it
386 ;; because we're only using the lower 16 bits (which is the upper 16
387 ;; bits of the result).
388 (define_insn "mulsi3_g14"
389 [(set (match_operand:SI 0 "register_operand" "=&v")
390 (mult:SI (match_operand:SI 1 "general_operand" "viU")
391 (match_operand:SI 2 "general_operand" "vi")))
392 (clobber (reg:HI AX_REG))
393 (clobber (reg:HI BC_REG))
396 "; G14 mulsi macro %0 = %1 * %2
399 MULHU ; bcax = bc * ax
405 MACHU ; MACR += bc * ax
408 MACHU ; MACR += bc * ax
411 ; end of mulsi macro"
412 [(set_attr "valloc" "macax")]
415 ;; 0xFFFF0 is MDAL. 0xFFFF2 is MDAH.
416 ;; 0xFFFF6 is MDBL. 0xFFFF4 is MDBH.
417 ;; 0xF00E0 is MDCL. 0xF00E2 is MDCH.
419 ;; Warning: this matches the silicon not the documentation.
420 (define_insn "mulsi3_g13"
421 [(set (match_operand:SI 0 "register_operand" "=&v")
422 (mult:SI (match_operand:SI 1 "general_operand" "viU")
423 (match_operand:SI 2 "general_operand" "viU")))
424 (clobber (reg:HI AX_REG))
425 (clobber (reg:HI BC_REG))
428 "; G13 mulsi macro %0 = %1 * %2
430 mov !0xf00e8, a ; MDUC
432 movw 0xffff0, ax ; MDAL
434 movw 0xffff2, ax ; MDAH
435 nop ; mdb = mdal * mdah
436 movw ax, 0xffff6 ; MDBL
440 mov !0xf00e8, a ; MDUC
441 movw ax, 0xffff4 ; MDBH
442 movw !0xf00e0, ax ; MDCL
444 movw !0xf00e2, ax ; MDCL
446 movw 0xffff0, ax ; MDAL
448 movw 0xffff2, ax ; MDAH
449 nop ; mdc += mdal * mdah
452 mov !0xf00e8, a ; MDUC
454 movw 0xffff0, ax ; MDAL
456 movw 0xffff2, ax ; MDAH
457 nop ; mdc += mdal * mdah
458 nop ; Additional nop for MAC
459 movw ax, !0xf00e0 ; MDCL
461 ; end of mulsi macro"
462 [(set_attr "valloc" "macax")]
465 (define_expand "udivmodhi4"
467 [(set (match_operand:HI 0 "register_operand")
468 (udiv:HI (match_operand:HI 1 "register_operand")
469 (match_operand:HI 2 "register_operand")))
470 (set (match_operand:HI 3 "register_operand")
471 (umod:HI (match_dup 1) (match_dup 2)))
472 (clobber (reg:HI AX_REG))
473 (clobber (reg:HI DE_REG))
480 (define_insn "*udivmodhi4_g14"
481 [(set (match_operand:HI 0 "register_operand" "=v")
482 (udiv:HI (match_operand:HI 1 "register_operand" "v")
483 (match_operand:HI 2 "register_operand" "v")))
484 (set (match_operand:HI 3 "register_operand" "=v")
485 (umod:HI (match_dup 1) (match_dup 2)))
486 (clobber (reg:HI AX_REG))
487 (clobber (reg:HI DE_REG))
491 if (find_reg_note (insn, REG_UNUSED, operands[3]))
492 return "; G14 udivhi macro %0 = %1 / %2 \n\
495 push psw ; Save the current interrupt status \n\
496 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
497 divhu ; ax = ax / de \n\
498 pop psw ; Restore saved interrupt status \n\
500 ; end of udivhi macro";
501 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
502 return "; G14 umodhi macro %3 = %1 %% %2 \n\
505 push psw ; Save the current interrupt status \n\
506 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
507 divhu ; de = ax %% de \n\
508 pop psw ; Restore saved interrupt status \n\
511 ; end of umodhi macro";
513 return "; G14 udivmodhi macro %0 = %1 / %2 and %3 = %1 %% %2 \n\
516 push psw ; Save the current interrupt status \n\
517 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
518 divhu ; ax = ax / de, de = ax %% de \n\
519 pop psw ; Restore saved interrupt status \n\
523 ; end of udivmodhi macro";
525 [(set_attr "valloc" "divhi")]
528 (define_expand "udivmodsi4"
530 [(set (match_operand:SI 0 "register_operand")
531 (udiv:SI (match_operand:SI 1 "register_operand")
532 (match_operand:SI 2 "register_operand")))
533 (set (match_operand:SI 3 "register_operand")
534 (umod:SI (match_dup 1) (match_dup 2)))
537 "! RL78_MUL_NONE && ! optimize_size"
540 emit_insn (gen_udivmodsi4_g14 (operands[0], operands[1], operands[2], operands[3]));
541 else /* RL78_MUL_G13 */
542 emit_insn (gen_udivmodsi4_g13 (operands[0], operands[1], operands[2], operands[3]));
547 (define_insn "udivmodsi4_g14"
548 [(set (match_operand:SI 0 "register_operand" "=v")
549 (udiv:SI (match_operand:SI 1 "register_operand" "v")
550 (match_operand:SI 2 "register_operand" "v")))
551 (set (match_operand:SI 3 "register_operand" "=v")
552 (umod:SI (match_dup 1) (match_dup 2)))
553 (clobber (reg:HI AX_REG))
554 (clobber (reg:HI BC_REG))
555 (clobber (reg:HI DE_REG))
556 (clobber (reg:HI HL_REG))
560 if (find_reg_note (insn, REG_UNUSED, operands[3]))
561 return "; G14 udivsi macro %0 = %1 / %2 \n\
566 push psw ; Save the current interrupt status \n\
567 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
568 divwu ; bcax = bcax / hlde \n\
569 pop psw ; Restore saved interrupt status \n\
573 ; end of udivsi macro";
574 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
575 return "; G14 umodsi macro %3 = %1 %% %2 \n\
580 push psw ; Save the current interrupt status \n\
581 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
582 divwu ; hlde = bcax %% hlde \n\
583 pop psw ; Restore saved interrupt status \n\
588 ; end of umodsi macro";
590 return "; G14 udivmodsi macro %0 = %1 / %2 and %3 = %1 %% %2 \n\
595 push psw ; Save the current interrupt status \n\
596 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
597 divwu ; bcax = bcax / hlde, hlde = bcax %% hlde \n\
598 pop psw ; Restore saved interrupt status \n\
606 ; end of udivmodsi macro";
608 [(set_attr "valloc" "divsi")]
611 ;; Warning: these values match the silicon not the documentation.
612 ;; 0xFFFF0 is MDAL. 0xFFFF2 is MDAH.
613 ;; 0xFFFF6 is MDBL. 0xFFFF4 is MDBH.
614 ;; 0xF00E0 is MDCL. 0xF00E2 is MDCH.
617 (define_insn "udivmodsi4_g13"
618 [(set (match_operand:SI 0 "register_operand" "=v")
619 (udiv:SI (match_operand:SI 1 "register_operand" "v")
620 (match_operand:SI 2 "register_operand" "v")))
621 (set (match_operand:SI 3 "register_operand" "=v")
622 (umod:SI (match_dup 1) (match_dup 2)))
623 (clobber (reg:HI AX_REG))
627 if (find_reg_note (insn, REG_UNUSED, operands[3]))
628 return "; G13 udivsi macro %0 = %1 / %2 \n\
629 mov a, #0xC0 ; Set DIVMODE=1 and MACMODE=1 \n\
630 mov !0xf00e8, a ; This preps the peripheral for division without interrupt generation \n\
632 movw 0xffff2, ax ; MDAH \n\
634 movw 0xffff0, ax ; MDAL \n\
636 movw 0xffff4, ax ; MDBH \n\
638 movw 0xffff6, ax ; MDBL \n\
639 mov a, #0xC1 ; Set the DIVST bit in MDUC \n\
640 mov !0xf00e8, a ; This starts the division op \n\
641 1: mov a, !0xf00e8 ; Wait 16 clocks or until DIVST is clear \n\
643 movw ax, 0xffff0 ; Read the quotient \n\
647 ; end of udivsi macro";
648 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
649 return "; G13 umodsi macro %3 = %1 %% %2 \n\
650 mov a, #0xC0 ; Set DIVMODE=1 and MACMODE=1 \n\
651 mov !0xf00e8, a ; This preps the peripheral for division without interrupt generation \n\
653 movw 0xffff2, ax ; MDAH \n\
655 movw 0xffff0, ax ; MDAL \n\
657 movw 0xffff4, ax ; MDBH \n\
659 movw 0xffff6, ax ; MDBL \n\
660 mov a, #0xC1 ; Set the DIVST bit in MDUC \n\
661 mov !0xf00e8, a ; This starts the division op \n\
662 1: mov a, !0xf00e8 ; Wait 16 clocks or until DIVST is clear \n\
664 movw ax, !0xf00e0 ; Read the remainder \n\
666 movw ax, !0xf00e2 \n\
668 ; end of umodsi macro";
670 return "; G13 udivmodsi macro %0 = %1 / %2 and %3 = %1 %% %2 \n\
671 mov a, #0xC0 ; Set DIVMODE=1 and MACMODE=1 \n\
672 mov !0xf00e8, a ; This preps the peripheral for division without interrupt generation \n\
674 movw 0xffff2, ax ; MDAH \n\
676 movw 0xffff0, ax ; MDAL \n\
678 movw 0xffff4, ax ; MDBH \n\
680 movw 0xffff6, ax ; MDBL \n\
681 mov a, #0xC1 ; Set the DIVST bit in MDUC \n\
682 mov !0xf00e8, a ; This starts the division op \n\
683 1: mov a, !0xf00e8 ; Wait 16 clocks or until DIVST is clear \n\
685 movw ax, 0xffff0 ; Read the quotient \n\
689 movw ax, !0xf00e0 ; Read the remainder \n\
691 movw ax, !0xf00e2 \n\
693 ; end of udivmodsi macro";
695 [(set_attr "valloc" "macax")]