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gcc/ChangeLog:
[official-gcc.git] / gcc / config / sh / sh.h
blob71546facf9d95a17344165822589edb9cc8dde14
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
29
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
34
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
43 builtin_define ("__sh1__"); \
44 break; \
45 case PROCESSOR_SH2: \
46 builtin_define ("__sh2__"); \
47 break; \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
50 break; \
51 case PROCESSOR_SH3: \
52 builtin_define ("__sh3__"); \
53 builtin_define ("__SH3__"); \
54 if (TARGET_HARD_SH4) \
55 builtin_define ("__SH4_NOFPU__"); \
56 break; \
57 case PROCESSOR_SH3E: \
58 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
59 break; \
60 case PROCESSOR_SH4: \
61 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
62 break; \
63 case PROCESSOR_SH4A: \
64 builtin_define ("__SH4A__"); \
65 builtin_define (TARGET_SH4 \
66 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
67 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
68 : "__SH4_NOFPU__"); \
69 break; \
70 case PROCESSOR_SH5: \
71 { \
72 builtin_define_with_value ("__SH5__", \
73 TARGET_SHMEDIA64 ? "64" : "32", 0); \
74 builtin_define_with_value ("__SHMEDIA__", \
75 TARGET_SHMEDIA ? "1" : "0", 0); \
76 if (! TARGET_FPU_DOUBLE) \
77 builtin_define ("__SH4_NOFPU__"); \
78 } \
79 } \
80 if (TARGET_HITACHI) \
81 builtin_define ("__HITACHI__"); \
82 builtin_define (TARGET_LITTLE_ENDIAN \
83 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
84 if (flag_pic) \
85 { \
86 builtin_define ("__pic__"); \
87 builtin_define ("__PIC__"); \
88 } \
89 } while (0)
90
91 /* We can not debug without a frame pointer. */
92 /* #define CAN_DEBUG_WITHOUT_FP */
93
94 #define CONDITIONAL_REGISTER_USAGE do \
95 { \
96 int regno; \
97 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
98 if (! VALID_REGISTER_P (regno)) \
99 fixed_regs[regno] = call_used_regs[regno] = 1; \
100 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
101 if (TARGET_SH5) \
102 call_used_regs[FIRST_GENERAL_REG + 8] \
103 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
104 if (TARGET_SHMEDIA) \
105 { \
106 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
107 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
108 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
109 } \
110 if (flag_pic) \
111 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
112 /* Renesas saves and restores mac registers on call. */ \
113 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
114 { \
115 call_used_regs[MACH_REG] = 0; \
116 call_used_regs[MACL_REG] = 0; \
117 } \
118 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
119 regno <= LAST_FP_REG; regno += 2) \
120 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
121 if (TARGET_SHMEDIA) \
122 { \
123 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
124 if (! fixed_regs[regno] && call_used_regs[regno]) \
125 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
126 } \
127 else \
128 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
129 if (! fixed_regs[regno] && call_used_regs[regno]) \
130 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
131 } while (0)
132 \f
133 /* ??? Need to write documentation for all SH options and add it to the
134 invoke.texi file. */
135
136 /* Run-time compilation parameters selecting different hardware subsets. */
137
138 extern int target_flags;
139 #define ISIZE_BIT (1<<1)
140 #define DALIGN_BIT (1<<6)
141 #define SH1_BIT (1<<8)
142 #define SH2_BIT (1<<9)
143 #define SH3_BIT (1<<10)
144 #define SH_E_BIT (1<<11)
145 #define HARD_SH4_BIT (1<<5)
146 #define FPU_SINGLE_BIT (1<<7)
147 #define SH4_BIT (1<<12)
148 #define SH4A_BIT (1<<3)
149 #define FMOVD_BIT (1<<4)
150 #define SH5_BIT (1<<0)
151 #define SPACE_BIT (1<<13)
152 #define BIGTABLE_BIT (1<<14)
153 #define RELAX_BIT (1<<15)
154 #define USERMODE_BIT (1<<16)
155 #define HITACHI_BIT (1<<22)
156 #define NOMACSAVE_BIT (1<<23)
157 #define PREFERGOT_BIT (1<<24)
158 #define PADSTRUCT_BIT (1<<28)
159 #define LITTLE_ENDIAN_BIT (1<<29)
160 #define IEEE_BIT (1<<30)
161 #define SAVE_ALL_TR_BIT (1<<2)
162
163 /* Nonzero if this is an ELF target - compile time only */
164 #define TARGET_ELF 0
165
166 /* Nonzero if we should dump out instruction size info. */
167 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
168
169 /* Nonzero to align doubles on 64 bit boundaries. */
170 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
171
172 /* Nonzero if we should generate code using type 1 insns. */
173 #define TARGET_SH1 (target_flags & SH1_BIT)
174
175 /* Nonzero if we should generate code using type 2 insns. */
176 #define TARGET_SH2 (target_flags & SH2_BIT)
177
178 /* Nonzero if we should generate code using type 2E insns. */
179 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
180
181 /* Nonzero if we should generate code using type 3 insns. */
182 #define TARGET_SH3 (target_flags & SH3_BIT)
183
184 /* Nonzero if we should generate code using type 3E insns. */
185 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
186
187 /* Nonzero if the cache line size is 32. */
188 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
189
190 /* Nonzero if we schedule for a superscalar implementation. */
191 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
192
193 /* Nonzero if the target has separate instruction and data caches. */
194 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
195
196 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
197 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
198
199 /* Nonzero if the default precision of th FPU is single */
200 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
201
202 /* Nonzero if a double-precision FPU is available. */
203 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
204
205 /* Nonzero if an FPU is available. */
206 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
207
208 /* Nonzero if we should generate code using type 4 insns. */
209 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
210
211 /* Nonzero if we're generating code for the common subset of
212 instructions present on both SH4a and SH4al-dsp. */
213 #define TARGET_SH4A_ARCH (target_flags & SH4A_BIT)
214
215 /* Nonzero if we're generating code for SH4a, unless the use of the
216 FPU is disabled (which makes it compatible with SH4al-dsp). */
217 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
218
219 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
220 #define TARGET_SH5 (target_flags & SH5_BIT)
221
222 /* Nonzero if we should generate code using the SHcompact instruction
223 set and 32-bit ABI. */
224 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
225
226 /* Nonzero if we should generate code using the SHmedia instruction
227 set and ABI. */
228 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
229
230 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
231 ABI. */
232 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
233 && (target_flags & SH_E_BIT))
234
235 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
236 ABI. */
237 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
238 && ! (target_flags & SH_E_BIT))
239
240 /* Nonzero if we should generate code using SHmedia FPU instructions. */
241 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
242 /* Nonzero if we should generate fmovd. */
243 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
244
245 /* Nonzero if we respect NANs. */
246 #define TARGET_IEEE (target_flags & IEEE_BIT)
247
248 /* Nonzero if we should generate smaller code rather than faster code. */
249 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
250
251 /* Nonzero to use long jump tables. */
252 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
253
254 /* Nonzero to generate pseudo-ops needed by the assembler and linker
255 to do function call relaxing. */
256 #define TARGET_RELAX (target_flags & RELAX_BIT)
257
258 /* Nonzero if using Renesas's calling convention. */
259 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
260
261 /* Nonzero if not saving macl/mach when using -mhitachi */
262 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
263
264 /* Nonzero if padding structures to a multiple of 4 bytes. This is
265 incompatible with Renesas's compiler, and gives unusual structure layouts
266 which confuse programmers.
267 ??? This option is not useful, but is retained in case there are people
268 who are still relying on it. It may be deleted in the future. */
269 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
270
271 /* Nonzero if generating code for a little endian SH. */
272 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
273
274 /* Nonzero if we should do everything in userland. */
275 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
276
277 /* Nonzero if we should prefer @GOT calls when generating PIC. */
278 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
279
280 #define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
281
282 /* This is not used by the SH2E calling convention */
283 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
284 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
285 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
286
287 #ifndef TARGET_CPU_DEFAULT
288 #define TARGET_CPU_DEFAULT SELECT_SH1
289 #define SUPPORT_SH1
290 #define SUPPORT_SH2E
291 #define SUPPORT_SH4
292 #define SUPPORT_SH4_SINGLE
293 #endif
294
295 #define SELECT_SH1 (SH1_BIT)
296 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
297 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
298 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
299 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
300 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
301 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
302 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
303 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
304 #define SELECT_SH4A_NOFPU (SH4A_BIT | SELECT_SH4_NOFPU)
305 #define SELECT_SH4A_SINGLE_ONLY (SH4A_BIT | SELECT_SH4_SINGLE_ONLY)
306 #define SELECT_SH4A (SH4A_BIT | SELECT_SH4)
307 #define SELECT_SH4A_SINGLE (SH4A_BIT | SELECT_SH4_SINGLE)
308 #define SELECT_SH5_64MEDIA (SH5_BIT | SH4_BIT)
309 #define SELECT_SH5_64MEDIA_NOFPU (SH5_BIT)
310 #define SELECT_SH5_32MEDIA (SH5_BIT | SH4_BIT | SH_E_BIT)
311 #define SELECT_SH5_32MEDIA_NOFPU (SH5_BIT | SH_E_BIT)
312 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
313 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
314
315 /* Disable processor switches for which we have no suitable multilibs. */
316 #ifndef SUPPORT_SH1
317 #define TARGET_SWITCH_SH1
318 #ifndef SUPPORT_SH2
319 #define TARGET_SWITCH_SH2
320 #ifndef SUPPORT_SH3
321 #define TARGET_SWITCH_SH3
322 #ifndef SUPPORT_SH4_NOFPU
323 #define TARGET_SWITCH_SH4_NOFPU
324 #endif
325 #ifndef SUPPORT_SH4A_NOFPU
326 #define TARGET_SWITCH_SH4A_NOFPU
327 #endif
328 #ifndef SUPPORT_SH4AL
329 #define TARGET_SWITCH_SH4AL
330 #endif
331 #endif
332 #endif
333 #endif
334
335 #ifndef SUPPORT_SH2E
336 #define TARGET_SWITCH_SH2E
337 #ifndef SUPPORT_SH3E
338 #define TARGET_SWITCH_SH3E
339 #ifndef SUPPORT_SH4_SINGLE_ONLY
340 #define TARGET_SWITCH_SH4_SINGLE_ONLY
341 #endif
342 #ifndef SUPPORT_SH4A_SINGLE_ONLY
343 #define TARGET_SWITCH_SH4A_SINGLE_ONLY
344 #endif
345 #endif
346 #endif
347
348 #ifndef SUPPORT_SH4
349 #define TARGET_SWITCH_SH4
350 #ifndef SUPPORT_SH4A
351 #define TARGET_SWITCH_SH4A
352 #endif
353 #endif
354
355 #ifndef SUPPORT_SH4_SINGLE
356 #define TARGET_SWITCH_SH4_SINGLE
357 #ifndef SUPPORT_SH4A_SINGLE
358 #define TARGET_SWITCH_SH4A_SINGLE
359 #endif
360 #endif
361
362 #ifndef SUPPORT_SH5_64MEDIA
363 #define TARGET_SWITCH_SH5_64MEDIA
364 #endif
365
366 #ifndef SUPPORT_SH5_64MEDIA_NOFPU
367 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU
368 #endif
369
370 #if !defined(SUPPORT_SH5_32MEDIA) && !defined (SUPPORT_SH5_COMPACT)
371 #define TARGET_SWITCHES_SH5_32MEDIA
372 #endif
373
374 #if !defined(SUPPORT_SH5_32MEDIA_NOFPU) && !defined (SUPPORT_SH5_COMPACT_NOFPU)
375 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU
376 #endif
377
378 /* Reset all target-selection flags. */
379 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
380 | SH4A_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
381
382 #ifndef TARGET_SWITCH_SH1
383 #define TARGET_SWITCH_SH1 \
384 {"1", TARGET_NONE, "" }, \
385 {"1", SELECT_SH1, "Generate SH1 code" },
386 #endif
387 #ifndef TARGET_SWITCH_SH2
388 #define TARGET_SWITCH_SH2 \
389 {"2", TARGET_NONE, "" }, \
390 {"2", SELECT_SH2, "Generate SH2 code" },
391 #endif
392 #ifndef TARGET_SWITCH_SH2E
393 #define TARGET_SWITCH_SH2E \
394 {"2e", TARGET_NONE, "" }, \
395 {"2e", SELECT_SH2E, "Generate SH2e code" },
396 #endif
397 #ifndef TARGET_SWITCH_SH3
398 #define TARGET_SWITCH_SH3 \
399 {"3", TARGET_NONE, "" }, \
400 {"3", SELECT_SH3, "Generate SH3 code" },
401 #endif
402 #ifndef TARGET_SWITCH_SH3E
403 #define TARGET_SWITCH_SH3E \
404 {"3e", TARGET_NONE, "" }, \
405 {"3e", SELECT_SH3E, "Generate SH3e code" },
406 #endif
407 #ifndef TARGET_SWITCH_SH4_SINGLE_ONLY
408 #define TARGET_SWITCH_SH4_SINGLE_ONLY \
409 {"4-single-only", TARGET_NONE, "" }, \
410 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },
411 #endif
412 #ifndef TARGET_SWITCH_SH4_SINGLE
413 #define TARGET_SWITCH_SH4_SINGLE \
414 {"4-single", TARGET_NONE, "" }, \
415 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },
416 #endif
417 #ifndef TARGET_SWITCH_SH4_NOFPU
418 #define TARGET_SWITCH_SH4_NOFPU \
419 {"4-nofpu", TARGET_NONE, "" }, \
420 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },
421 #endif
422 #ifndef TARGET_SWITCH_SH4
423 #define TARGET_SWITCH_SH4 \
424 {"4", TARGET_NONE, "" }, \
425 {"4", SELECT_SH4, "Generate SH4 code" },
426 #endif
427 #ifndef TARGET_SWITCH_SH4A
428 #define TARGET_SWITCH_SH4A \
429 {"4a", TARGET_NONE, "" }, \
430 {"4a", SELECT_SH4A, "Generate SH4a code" },
431 #endif
432 #ifndef TARGET_SWITCH_SH4A_SINGLE_ONLY
433 #define TARGET_SWITCH_SH4A_SINGLE_ONLY \
434 {"4a-single-only", TARGET_NONE, "" }, \
435 {"4a-single-only", SELECT_SH4A_SINGLE_ONLY, "Generate only single-precision SH4a code" },
436 #endif
437 #ifndef TARGET_SWITCH_SH4A_SINGLE
438 #define TARGET_SWITCH_SH4A_SINGLE \
439 {"4a-single", TARGET_NONE, "" },\
440 {"4a-single", SELECT_SH4A_SINGLE, "Generate default single-precision SH4a code" },
441 #endif
442 #ifndef TARGET_SWITCH_SH4A_NOFPU
443 #define TARGET_SWITCH_SH4A_NOFPU \
444 {"4a-nofpu", TARGET_NONE, "" },\
445 {"4a-nofpu", SELECT_SH4A_NOFPU, "Generate SH4a FPU-less code" },
446 #endif
447 #ifndef TARGET_SWITCH_SH4AL
448 #define TARGET_SWITCH_SH4AL \
449 {"4al", TARGET_NONE, "" },\
450 {"4al", SELECT_SH4A_NOFPU, "Generate SH4al-dsp code" },
451 #endif
452 #ifndef TARGET_SWITCH_SH5_64MEDIA
453 #define TARGET_SWITCH_SH5_64MEDIA \
454 {"5-64media", TARGET_NONE, "" }, \
455 {"5-64media", SELECT_SH5_64MEDIA, "Generate 64-bit SHmedia code" },
456 #endif
457 #ifndef TARGET_SWITCH_SH5_64MEDIA_NOFPU
458 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU \
459 {"5-64media-nofpu", TARGET_NONE, "" }, \
460 {"5-64media-nofpu", SELECT_SH5_64MEDIA_NOFPU, "Generate 64-bit FPU-less SHmedia code" },
461 #endif
462 #ifndef TARGET_SWITCHES_SH5_32MEDIA
463 #define TARGET_SWITCHES_SH5_32MEDIA \
464 {"5-32media", TARGET_NONE, "" }, \
465 {"5-32media", SELECT_SH5_32MEDIA, "Generate 32-bit SHmedia code" }, \
466 {"5-compact", TARGET_NONE, "" }, \
467 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" },
468 #endif
469 #ifndef TARGET_SWITCHES_SH5_32MEDIA_NOFPU
470 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
471 {"5-32media-nofpu", TARGET_NONE, "" }, \
472 {"5-32media-nofpu", SELECT_SH5_32MEDIA_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
473 {"5-compact-nofpu", TARGET_NONE, "" }, \
474 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" },
475 #endif
476
477 #define TARGET_SWITCHES \
478 { TARGET_SWITCH_SH1 \
479 TARGET_SWITCH_SH2 \
480 TARGET_SWITCH_SH2E \
481 TARGET_SWITCH_SH3 \
482 TARGET_SWITCH_SH3E \
483 TARGET_SWITCH_SH4_SINGLE_ONLY \
484 TARGET_SWITCH_SH4_SINGLE \
485 TARGET_SWITCH_SH4_NOFPU \
486 TARGET_SWITCH_SH4 \
487 TARGET_SWITCH_SH4A_SINGLE_ONLY \
488 TARGET_SWITCH_SH4A_SINGLE \
489 TARGET_SWITCH_SH4A_NOFPU \
490 TARGET_SWITCH_SH4A \
491 TARGET_SWITCH_SH4AL \
492 TARGET_SWITCH_SH5_64MEDIA \
493 TARGET_SWITCH_SH5_64MEDIA_NOFPU \
494 TARGET_SWITCHES_SH5_32MEDIA \
495 TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
496 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
497 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
498 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
499 {"fmovd", FMOVD_BIT, "" }, \
500 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
501 {"renesas", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
502 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
503 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
504 {"isize", ISIZE_BIT, "" }, \
505 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
506 {"no-ieee", -IEEE_BIT, "" }, \
507 {"padstruct", PADSTRUCT_BIT, "" }, \
508 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
509 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
510 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
511 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
512 SUBTARGET_SWITCHES \
513 {"", TARGET_DEFAULT, "" } \
514 }
515
516 /* This are meant to be redefined in the host dependent files */
517 #define SUBTARGET_SWITCHES
518
519 /* This defaults us to big-endian. */
520 #ifndef TARGET_ENDIAN_DEFAULT
521 #define TARGET_ENDIAN_DEFAULT 0
522 #endif
523
524 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
525
526 #ifndef SH_MULTILIB_CPU_DEFAULT
527 #define SH_MULTILIB_CPU_DEFAULT "m1"
528 #endif
529
530 #if TARGET_ENDIAN_DEFAULT
531 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
532 #else
533 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
534 #endif
535
536 #define CPP_SPEC " %(subtarget_cpp_spec) "
537
538 #ifndef SUBTARGET_CPP_SPEC
539 #define SUBTARGET_CPP_SPEC ""
540 #endif
541
542 #ifndef SUBTARGET_EXTRA_SPECS
543 #define SUBTARGET_EXTRA_SPECS
544 #endif
545
546 #define EXTRA_SPECS \
547 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
548 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
549 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
550 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
551 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
552 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
553 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
554 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
555 SUBTARGET_EXTRA_SPECS
556
557 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
558 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
559 #else
560 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
561 #endif
562
563 #define SH_ASM_SPEC \
564 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
565 %(subtarget_asm_isa_spec) %{m4al:-dsp}"
566
567 #define ASM_SPEC SH_ASM_SPEC
568
569 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
570 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
571 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
572 #else
573 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
574 #endif
575 #endif
576
577 #define SUBTARGET_ASM_ISA_SPEC ""
578
579 #define LINK_EMUL_PREFIX "sh%{ml:l}"
580
581 #if TARGET_CPU_DEFAULT & SH5_BIT
582 #if TARGET_CPU_DEFAULT & SH_E_BIT
583 #define LINK_DEFAULT_CPU_EMUL "32"
584 #if TARGET_CPU_DEFAULT & SH1_BIT
585 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
586 #else
587 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
588 #endif /* SH1_BIT */
589 #else /* !SH_E_BIT */
590 #define LINK_DEFAULT_CPU_EMUL "64"
591 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
592 #endif /* SH_E_BIT */
593 #define ASM_ISA_DEFAULT_SPEC \
594 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
595 #else /* !SH5_BIT */
596 #define LINK_DEFAULT_CPU_EMUL ""
597 #define ASM_ISA_DEFAULT_SPEC ""
598 #endif /* SH5_BIT */
599
600 #define SUBTARGET_LINK_EMUL_SUFFIX ""
601 #define SUBTARGET_LINK_SPEC ""
602
603 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
604 so that we can undo the damage without code replication. */
605 #define LINK_SPEC SH_LINK_SPEC
606
607 #define SH_LINK_SPEC "\
608 -m %(link_emul_prefix)\
609 %{m5-compact*|m5-32media*:32}\
610 %{m5-64media*:64}\
611 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
612 %(subtarget_link_emul_suffix) \
613 %{mrelax:-relax} %(subtarget_link_spec)"
614
615 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
616 do { \
617 if (LEVEL) \
618 flag_omit_frame_pointer = -1; \
619 if (SIZE) \
620 target_flags |= SPACE_BIT; \
621 if (TARGET_SHMEDIA && LEVEL > 1) \
622 { \
623 flag_branch_target_load_optimize = 1; \
624 if (! (SIZE)) \
625 target_flags |= SAVE_ALL_TR_BIT; \
626 } \
627 } while (0)
628
629 #define ASSEMBLER_DIALECT assembler_dialect
630
631 extern int assembler_dialect;
632
633 #define OVERRIDE_OPTIONS \
634 do { \
635 int regno; \
636 \
637 sh_cpu = CPU_SH1; \
638 assembler_dialect = 0; \
639 if (TARGET_SH2) \
640 sh_cpu = CPU_SH2; \
641 if (TARGET_SH2E) \
642 sh_cpu = CPU_SH2E; \
643 if (TARGET_SH3) \
644 sh_cpu = CPU_SH3; \
645 if (TARGET_SH3E) \
646 sh_cpu = CPU_SH3E; \
647 if (TARGET_SH4) \
648 { \
649 assembler_dialect = 1; \
650 sh_cpu = CPU_SH4; \
651 } \
652 if (TARGET_SH4A_ARCH) \
653 { \
654 assembler_dialect = 1; \
655 sh_cpu = CPU_SH4A; \
656 } \
657 if (TARGET_SH5) \
658 { \
659 sh_cpu = CPU_SH5; \
660 target_flags |= DALIGN_BIT; \
661 if (TARGET_FPU_ANY \
662 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
663 target_flags |= FMOVD_BIT; \
664 if (TARGET_SHMEDIA) \
665 { \
666 /* There are no delay slots on SHmedia. */ \
667 flag_delayed_branch = 0; \
668 /* Relaxation isn't yet supported for SHmedia */ \
669 target_flags &= ~RELAX_BIT; \
670 } \
671 /* -fprofile-arcs needs a working libgcov . In unified tree \
672 configurations with newlib, this requires to configure with \
673 --with-newlib --with-headers. But there is no way to check \
674 here we have a working libgcov, so just assume that we have. */\
675 if (profile_flag) \
676 { \
677 warning ("Profiling is not supported on this target."); \
678 profile_flag = profile_arc_flag = 0; \
679 } \
680 } \
681 else \
682 { \
683 /* Only the sh64-elf assembler fully supports .quad properly. */\
684 targetm.asm_out.aligned_op.di = NULL; \
685 targetm.asm_out.unaligned_op.di = NULL; \
686 } \
687 if (TARGET_FMOVD) \
688 reg_class_from_letter['e' - 'a'] = NO_REGS; \
689 \
690 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
691 if (! VALID_REGISTER_P (regno)) \
692 sh_register_names[regno][0] = '\0'; \
693 \
694 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
695 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
696 sh_additional_register_names[regno][0] = '\0'; \
697 \
698 if (flag_omit_frame_pointer < 0) \
699 { \
700 /* The debugging information is sufficient, \
701 but gdb doesn't implement this yet */ \
702 if (0) \
703 flag_omit_frame_pointer \
704 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
705 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
706 else \
707 flag_omit_frame_pointer = 0; \
708 } \
709 \
710 if (flag_pic && ! TARGET_PREFERGOT) \
711 flag_no_function_cse = 1; \
712 \
713 if (SMALL_REGISTER_CLASSES) \
714 { \
715 /* Never run scheduling before reload, since that can \
716 break global alloc, and generates slower code anyway due \
717 to the pressure on R0. */ \
718 /* Enable sched1 for SH4; ready queue will be reordered by \
719 the target hooks when pressure is high. We can not do this for \
720 SH3 and lower as they give spill failures for R0. */ \
721 if (!TARGET_HARD_SH4) \
722 flag_schedule_insns = 0; \
723 } \
724 \
725 if (align_loops == 0) \
726 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
727 if (align_jumps == 0) \
728 align_jumps = 1 << CACHE_LOG; \
729 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
730 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
731 \
732 /* Allocation boundary (in *bytes*) for the code of a function. \
733 SH1: 32 bit alignment is faster, because instructions are always \
734 fetched as a pair from a longword boundary. \
735 SH2 .. SH5 : align to cache line start. */ \
736 if (align_functions == 0) \
737 align_functions \
738 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
739 /* The linker relaxation code breaks when a function contains \
740 alignments that are larger than that at the start of a \
741 compilation unit. */ \
742 if (TARGET_RELAX) \
743 { \
744 int min_align \
745 = align_loops > align_jumps ? align_loops : align_jumps; \
746 \
747 /* Also take possible .long constants / mova tables int account. */\
748 if (min_align < 4) \
749 min_align = 4; \
750 if (align_functions < min_align) \
751 align_functions = min_align; \
752 } \
753 } while (0)
754 \f
755 /* Target machine storage layout. */
756
757 /* Define this if most significant bit is lowest numbered
758 in instructions that operate on numbered bit-fields. */
759
760 #define BITS_BIG_ENDIAN 0
761
762 /* Define this if most significant byte of a word is the lowest numbered. */
763 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
764
765 /* Define this if most significant word of a multiword number is the lowest
766 numbered. */
767 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
768
769 /* Define this to set the endianness to use in libgcc2.c, which can
770 not depend on target_flags. */
771 #if defined(__LITTLE_ENDIAN__)
772 #define LIBGCC2_WORDS_BIG_ENDIAN 0
773 #else
774 #define LIBGCC2_WORDS_BIG_ENDIAN 1
775 #endif
776
777 #define MAX_BITS_PER_WORD 64
778
779 /* Width in bits of an `int'. We want just 32-bits, even if words are
780 longer. */
781 #define INT_TYPE_SIZE 32
782
783 /* Width in bits of a `long'. */
784 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
785
786 /* Width in bits of a `long long'. */
787 #define LONG_LONG_TYPE_SIZE 64
788
789 /* Width in bits of a `long double'. */
790 #define LONG_DOUBLE_TYPE_SIZE 64
791
792 /* Width of a word, in units (bytes). */
793 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
794 #define MIN_UNITS_PER_WORD 4
795
796 /* Scaling factor for Dwarf data offsets for CFI information.
797 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
798 SHmedia; however, since we do partial register saves for the registers
799 visible to SHcompact, and for target registers for SHMEDIA32, we have
800 to allow saves that are only 4-byte aligned. */
801 #define DWARF_CIE_DATA_ALIGNMENT -4
802
803 /* Width in bits of a pointer.
804 See also the macro `Pmode' defined below. */
805 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
806
807 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
808 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
809
810 /* Boundary (in *bits*) on which stack pointer should be aligned. */
811 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
812
813 /* The log (base 2) of the cache line size, in bytes. Processors prior to
814 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
815 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
816 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
817
818 /* ABI given & required minimum allocation boundary (in *bits*) for the
819 code of a function. */
820 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
821
822 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
823 the vbit must go into the delta field of
824 pointers-to-member-functions. */
825 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
826 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
827
828 /* Alignment of field after `int : 0' in a structure. */
829 #define EMPTY_FIELD_BOUNDARY 32
830
831 /* No data type wants to be aligned rounder than this. */
832 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
833
834 /* The best alignment to use in cases where we have a choice. */
835 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
836
837 /* Make strings word-aligned so strcpy from constants will be faster. */
838 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
839 ((TREE_CODE (EXP) == STRING_CST \
840 && (ALIGN) < FASTEST_ALIGNMENT) \
841 ? FASTEST_ALIGNMENT : (ALIGN))
842
843 /* get_mode_alignment assumes complex values are always held in multiple
844 registers, but that is not the case on the SH; CQImode and CHImode are
845 held in a single integer register. SH5 also holds CSImode and SCmode
846 values in integer registers. This is relevant for argument passing on
847 SHcompact as we use a stack temp in order to pass CSImode by reference. */
848 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
849 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
850 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
851 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
852 : (unsigned) ALIGN)
853
854 /* Make arrays of chars word-aligned for the same reasons. */
855 #define DATA_ALIGNMENT(TYPE, ALIGN) \
856 (TREE_CODE (TYPE) == ARRAY_TYPE \
857 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
858 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
859
860 /* Number of bits which any structure or union's size must be a
861 multiple of. Each structure or union's size is rounded up to a
862 multiple of this. */
863 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
864
865 /* Set this nonzero if move instructions will actually fail to work
866 when given unaligned data. */
867 #define STRICT_ALIGNMENT 1
868
869 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
870 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
871 barrier_align (LABEL_AFTER_BARRIER)
872
873 #define LOOP_ALIGN(A_LABEL) \
874 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
875 ? 0 : sh_loop_align (A_LABEL))
876
877 #define LABEL_ALIGN(A_LABEL) \
878 ( \
879 (PREV_INSN (A_LABEL) \
880 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
881 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
882 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
883 /* explicit alignment insn in constant tables. */ \
884 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
885 : 0)
886
887 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
888 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
889
890 /* The base two logarithm of the known minimum alignment of an insn length. */
891 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
892 (GET_CODE (A_INSN) == INSN \
893 ? 1 << TARGET_SHMEDIA \
894 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
895 ? 1 << TARGET_SHMEDIA \
896 : CACHE_LOG)
897 \f
898 /* Standard register usage. */
899
900 /* Register allocation for the Renesas calling convention:
901
902 r0 arg return
903 r1..r3 scratch
904 r4..r7 args in
905 r8..r13 call saved
906 r14 frame pointer/call saved
907 r15 stack pointer
908 ap arg pointer (doesn't really exist, always eliminated)
909 pr subroutine return address
910 t t bit
911 mach multiply/accumulate result, high part
912 macl multiply/accumulate result, low part.
913 fpul fp/int communication register
914 rap return address pointer register
915 fr0 fp arg return
916 fr1..fr3 scratch floating point registers
917 fr4..fr11 fp args in
918 fr12..fr15 call saved floating point registers */
919
920 #define MAX_REGISTER_NAME_LENGTH 5
921 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
922
923 #define SH_REGISTER_NAMES_INITIALIZER \
924 { \
925 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
926 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
927 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
928 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
929 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
930 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
931 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
932 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
933 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
934 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
935 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
936 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
937 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
938 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
939 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
940 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
941 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
942 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
943 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
944 "rap" \
945 }
946
947 #define REGNAMES_ARR_INDEX_1(index) \
948 (sh_register_names[index])
949 #define REGNAMES_ARR_INDEX_2(index) \
950 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
951 #define REGNAMES_ARR_INDEX_4(index) \
952 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
953 #define REGNAMES_ARR_INDEX_8(index) \
954 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
955 #define REGNAMES_ARR_INDEX_16(index) \
956 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
957 #define REGNAMES_ARR_INDEX_32(index) \
958 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
959 #define REGNAMES_ARR_INDEX_64(index) \
960 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
961
962 #define REGISTER_NAMES \
963 { \
964 REGNAMES_ARR_INDEX_64 (0), \
965 REGNAMES_ARR_INDEX_64 (64), \
966 REGNAMES_ARR_INDEX_8 (128), \
967 REGNAMES_ARR_INDEX_8 (136), \
968 REGNAMES_ARR_INDEX_8 (144), \
969 REGNAMES_ARR_INDEX_1 (152) \
970 }
971
972 #define ADDREGNAMES_SIZE 32
973 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
974 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
975 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
976
977 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
978 { \
979 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
980 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
981 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
982 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
983 }
984
985 #define ADDREGNAMES_REGNO(index) \
986 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
987 : (-1))
988
989 #define ADDREGNAMES_ARR_INDEX_1(index) \
990 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
991 #define ADDREGNAMES_ARR_INDEX_2(index) \
992 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
993 #define ADDREGNAMES_ARR_INDEX_4(index) \
994 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
995 #define ADDREGNAMES_ARR_INDEX_8(index) \
996 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
997 #define ADDREGNAMES_ARR_INDEX_16(index) \
998 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
999 #define ADDREGNAMES_ARR_INDEX_32(index) \
1000 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1001
1002 #define ADDITIONAL_REGISTER_NAMES \
1003 { \
1004 ADDREGNAMES_ARR_INDEX_32 (0) \
1005 }
1006
1007 /* Number of actual hardware registers.
1008 The hardware registers are assigned numbers for the compiler
1009 from 0 to just below FIRST_PSEUDO_REGISTER.
1010 All registers that the compiler knows about must be given numbers,
1011 even those that are not normally considered general registers. */
1012
1013 /* There are many other relevant definitions in sh.md's md_constants. */
1014
1015 #define FIRST_GENERAL_REG R0_REG
1016 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1017 #define FIRST_FP_REG DR0_REG
1018 #define LAST_FP_REG (FIRST_FP_REG + \
1019 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1020 #define FIRST_XD_REG XD0_REG
1021 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1022 #define FIRST_TARGET_REG TR0_REG
1023 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1024
1025 #define GENERAL_REGISTER_P(REGNO) \
1026 IN_RANGE ((REGNO), \
1027 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1028 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1029
1030 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1031 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
1032
1033 #define FP_REGISTER_P(REGNO) \
1034 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1035
1036 #define XD_REGISTER_P(REGNO) \
1037 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1038
1039 #define FP_OR_XD_REGISTER_P(REGNO) \
1040 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1041
1042 #define FP_ANY_REGISTER_P(REGNO) \
1043 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1044
1045 #define SPECIAL_REGISTER_P(REGNO) \
1046 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1047 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1048
1049 #define TARGET_REGISTER_P(REGNO) \
1050 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1051
1052 #define SHMEDIA_REGISTER_P(REGNO) \
1053 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1054 || TARGET_REGISTER_P (REGNO))
1055
1056 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1057 that should be fixed. */
1058 #define VALID_REGISTER_P(REGNO) \
1059 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1060 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1061 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1062 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1063
1064 /* The mode that should be generally used to store a register by
1065 itself in the stack, or to load it back. */
1066 #define REGISTER_NATURAL_MODE(REGNO) \
1067 (FP_REGISTER_P (REGNO) ? SFmode \
1068 : XD_REGISTER_P (REGNO) ? DFmode \
1069 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1070 ? DImode \
1071 : SImode)
1072
1073 #define FIRST_PSEUDO_REGISTER 153
1074
1075 /* 1 for registers that have pervasive standard uses
1076 and are not available for the register allocator.
1077
1078 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1079 It is 32 bits wide for SH2. */
1080
1081 #define FIXED_REGISTERS \
1082 { \
1083 /* Regular registers. */ \
1084 0, 0, 0, 0, 0, 0, 0, 0, \
1085 0, 0, 0, 0, 0, 0, 0, 1, \
1086 /* r16 is reserved, r18 is the former pr. */ \
1087 1, 0, 0, 0, 0, 0, 0, 0, \
1088 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1089 /* r26 is a global variable data pointer; r27 is for constants. */ \
1090 1, 1, 1, 1, 0, 0, 0, 0, \
1091 0, 0, 0, 0, 0, 0, 0, 0, \
1092 0, 0, 0, 0, 0, 0, 0, 0, \
1093 0, 0, 0, 0, 0, 0, 0, 0, \
1094 0, 0, 0, 0, 0, 0, 0, 1, \
1095 /* FP registers. */ \
1096 0, 0, 0, 0, 0, 0, 0, 0, \
1097 0, 0, 0, 0, 0, 0, 0, 0, \
1098 0, 0, 0, 0, 0, 0, 0, 0, \
1099 0, 0, 0, 0, 0, 0, 0, 0, \
1100 0, 0, 0, 0, 0, 0, 0, 0, \
1101 0, 0, 0, 0, 0, 0, 0, 0, \
1102 0, 0, 0, 0, 0, 0, 0, 0, \
1103 0, 0, 0, 0, 0, 0, 0, 0, \
1104 /* Branch target registers. */ \
1105 0, 0, 0, 0, 0, 0, 0, 0, \
1106 /* XD registers. */ \
1107 0, 0, 0, 0, 0, 0, 0, 0, \
1108 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1109 1, 1, 1, 1, 1, 1, 0, 1, \
1110 /*"rap" */ \
1111 1, \
1112 }
1113
1114 /* 1 for registers not available across function calls.
1115 These must include the FIXED_REGISTERS and also any
1116 registers that can be used without being saved.
1117 The latter must include the registers where values are returned
1118 and the register where structure-value addresses are passed.
1119 Aside from that, you can include as many other registers as you like. */
1120
1121 #define CALL_USED_REGISTERS \
1122 { \
1123 /* Regular registers. */ \
1124 1, 1, 1, 1, 1, 1, 1, 1, \
1125 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1126 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1127 across SH5 function calls. */ \
1128 0, 0, 0, 0, 0, 0, 0, 1, \
1129 1, 1, 1, 1, 1, 1, 1, 1, \
1130 1, 1, 1, 1, 0, 0, 0, 0, \
1131 0, 0, 0, 0, 1, 1, 1, 1, \
1132 1, 1, 1, 1, 0, 0, 0, 0, \
1133 0, 0, 0, 0, 0, 0, 0, 0, \
1134 0, 0, 0, 0, 1, 1, 1, 1, \
1135 /* FP registers. */ \
1136 1, 1, 1, 1, 1, 1, 1, 1, \
1137 1, 1, 1, 1, 0, 0, 0, 0, \
1138 1, 1, 1, 1, 1, 1, 1, 1, \
1139 1, 1, 1, 1, 1, 1, 1, 1, \
1140 1, 1, 1, 1, 0, 0, 0, 0, \
1141 0, 0, 0, 0, 0, 0, 0, 0, \
1142 0, 0, 0, 0, 0, 0, 0, 0, \
1143 0, 0, 0, 0, 0, 0, 0, 0, \
1144 /* Branch target registers. */ \
1145 1, 1, 1, 1, 1, 0, 0, 0, \
1146 /* XD registers. */ \
1147 1, 1, 1, 1, 1, 1, 0, 0, \
1148 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1149 1, 1, 1, 1, 1, 1, 1, 1, \
1150 /*"rap" */ \
1151 1, \
1152 }
1153
1154 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1155 across SHcompact function calls. We can't tell whether a called
1156 function is SHmedia or SHcompact, so we assume it may be when
1157 compiling SHmedia code with the 32-bit ABI, since that's the only
1158 ABI that can be linked with SHcompact code. */
1159 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1160 (TARGET_SHMEDIA32 \
1161 && GET_MODE_SIZE (MODE) > 4 \
1162 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1163 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1164 || TARGET_REGISTER_P (REGNO) \
1165 || (REGNO) == PR_MEDIA_REG))
1166
1167 /* Return number of consecutive hard regs needed starting at reg REGNO
1168 to hold something of mode MODE.
1169 This is ordinarily the length in words of a value of mode MODE
1170 but can be less for certain modes in special long registers.
1171
1172 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1173
1174 #define HARD_REGNO_NREGS(REGNO, MODE) \
1175 (XD_REGISTER_P (REGNO) \
1176 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1177 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1178 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1179 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1180
1181 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1182 We can allow any mode in any general register. The special registers
1183 only allow SImode. Don't allow any mode in the PR. */
1184
1185 /* We cannot hold DCmode values in the XD registers because alter_reg
1186 handles subregs of them incorrectly. We could work around this by
1187 spacing the XD registers like the DR registers, but this would require
1188 additional memory in every compilation to hold larger register vectors.
1189 We could hold SFmode / SCmode values in XD registers, but that
1190 would require a tertiary reload when reloading from / to memory,
1191 and a secondary reload to reload from / to general regs; that
1192 seems to be a loosing proposition. */
1193 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1194 it won't be ferried through GP registers first. */
1195 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1196 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1197 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1198 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1199 ? 1 \
1200 : (MODE) == V2SFmode \
1201 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1202 || GENERAL_REGISTER_P (REGNO)) \
1203 : (MODE) == V4SFmode \
1204 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1205 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
1206 : (MODE) == V16SFmode \
1207 ? (TARGET_SHMEDIA \
1208 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1209 : (REGNO) == FIRST_XD_REG) \
1210 : FP_REGISTER_P (REGNO) \
1211 ? ((MODE) == SFmode || (MODE) == SImode \
1212 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1213 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
1214 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1215 || (MODE) == V2SFmode || (MODE) == TImode))) \
1216 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
1217 : XD_REGISTER_P (REGNO) \
1218 ? (MODE) == DFmode \
1219 : TARGET_REGISTER_P (REGNO) \
1220 ? ((MODE) == DImode || (MODE) == SImode) \
1221 : (REGNO) == PR_REG ? (MODE) == SImode \
1222 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1223 : 1)
1224
1225 /* Value is 1 if MODE is a supported vector mode. */
1226 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1227 ((TARGET_FPU_ANY \
1228 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
1229 || (TARGET_SHMEDIA \
1230 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
1231 || (MODE) == V2SImode)))
1232
1233 /* Value is 1 if it is a good idea to tie two pseudo registers
1234 when one has mode MODE1 and one has mode MODE2.
1235 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1236 for any hard reg, then this must be 0 for correct output.
1237 That's the case for xd registers: we don't hold SFmode values in
1238 them, so we can't tie an SFmode pseudos with one in another
1239 floating-point mode. */
1240
1241 #define MODES_TIEABLE_P(MODE1, MODE2) \
1242 ((MODE1) == (MODE2) \
1243 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1244 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1245 && (GET_MODE_SIZE (MODE2) <= 4)) \
1246 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1247
1248 /* A C expression that is nonzero if hard register NEW_REG can be
1249 considered for use as a rename register for OLD_REG register */
1250
1251 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1252 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1253
1254 /* Specify the registers used for certain standard purposes.
1255 The values of these macros are register numbers. */
1256
1257 /* Define this if the program counter is overloaded on a register. */
1258 /* #define PC_REGNUM 15*/
1259
1260 /* Register to use for pushing function arguments. */
1261 #define STACK_POINTER_REGNUM SP_REG
1262
1263 /* Base register for access to local variables of the function. */
1264 #define FRAME_POINTER_REGNUM FP_REG
1265
1266 /* Fake register that holds the address on the stack of the
1267 current function's return address. */
1268 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1269
1270 /* Register to hold the addressing base for position independent
1271 code access to data items. */
1272 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1273
1274 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1275
1276 /* Value should be nonzero if functions must have frame pointers.
1277 Zero means the frame pointer need not be set up (and parms may be accessed
1278 via the stack pointer) in functions that seem suitable. */
1279
1280 #define FRAME_POINTER_REQUIRED 0
1281
1282 /* Definitions for register eliminations.
1283
1284 We have three registers that can be eliminated on the SH. First, the
1285 frame pointer register can often be eliminated in favor of the stack
1286 pointer register. Secondly, the argument pointer register can always be
1287 eliminated; it is replaced with either the stack or frame pointer.
1288 Third, there is the return address pointer, which can also be replaced
1289 with either the stack or the frame pointer. */
1290
1291 /* This is an array of structures. Each structure initializes one pair
1292 of eliminable registers. The "from" register number is given first,
1293 followed by "to". Eliminations of the same "from" register are listed
1294 in order of preference. */
1295
1296 /* If you add any registers here that are not actually hard registers,
1297 and that have any alternative of elimination that doesn't always
1298 apply, you need to amend calc_live_regs to exclude it, because
1299 reload spills all eliminable registers where it sees an
1300 can_eliminate == 0 entry, thus making them 'live' .
1301 If you add any hard registers that can be eliminated in different
1302 ways, you have to patch reload to spill them only when all alternatives
1303 of elimination fail. */
1304
1305 #define ELIMINABLE_REGS \
1306 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1307 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1308 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1309 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1310 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1311
1312 /* Given FROM and TO register numbers, say whether this elimination
1313 is allowed. */
1314 #define CAN_ELIMINATE(FROM, TO) \
1315 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1316
1317 /* Define the offset between two registers, one to be eliminated, and the other
1318 its replacement, at the start of a routine. */
1319
1320 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1321 OFFSET = initial_elimination_offset ((FROM), (TO))
1322
1323 /* Base register for access to arguments of the function. */
1324 #define ARG_POINTER_REGNUM AP_REG
1325
1326 /* Register in which the static-chain is passed to a function. */
1327 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1328
1329 /* Don't default to pcc-struct-return, because we have already specified
1330 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1331 target hook. */
1332
1333 #define DEFAULT_PCC_STRUCT_RETURN 0
1334
1335 #define SHMEDIA_REGS_STACK_ADJUST() \
1336 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1337 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1338 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1339 : 0)
1340
1341 \f
1342 /* Define the classes of registers for register constraints in the
1343 machine description. Also define ranges of constants.
1344
1345 One of the classes must always be named ALL_REGS and include all hard regs.
1346 If there is more than one class, another class must be named NO_REGS
1347 and contain no registers.
1348
1349 The name GENERAL_REGS must be the name of a class (or an alias for
1350 another name such as ALL_REGS). This is the class of registers
1351 that is allowed by "g" or "r" in a register constraint.
1352 Also, registers outside this class are allocated only when
1353 instructions express preferences for them.
1354
1355 The classes must be numbered in nondecreasing order; that is,
1356 a larger-numbered class must never be contained completely
1357 in a smaller-numbered class.
1358
1359 For any two classes, it is very desirable that there be another
1360 class that represents their union. */
1361
1362 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1363 be used as the destination of some of the arithmetic ops. There are
1364 also some special purpose registers; the T bit register, the
1365 Procedure Return Register and the Multiply Accumulate Registers. */
1366 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1367 reg_class_subunion. We don't want to have an actual union class
1368 of these, because it would only be used when both classes are calculated
1369 to give the same cost, but there is only one FPUL register.
1370 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1371 applying to the actual instruction alternative considered. E.g., the
1372 y/r alternative of movsi_ie is considered to have no more cost that
1373 the r/r alternative, which is patently untrue. */
1374
1375 enum reg_class
1376 {
1377 NO_REGS,
1378 R0_REGS,
1379 PR_REGS,
1380 T_REGS,
1381 MAC_REGS,
1382 FPUL_REGS,
1383 SIBCALL_REGS,
1384 GENERAL_REGS,
1385 FP0_REGS,
1386 FP_REGS,
1387 DF_HI_REGS,
1388 DF_REGS,
1389 FPSCR_REGS,
1390 GENERAL_FP_REGS,
1391 TARGET_REGS,
1392 ALL_REGS,
1393 LIM_REG_CLASSES
1394 };
1395
1396 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1397
1398 /* Give names of register classes as strings for dump file. */
1399 #define REG_CLASS_NAMES \
1400 { \
1401 "NO_REGS", \
1402 "R0_REGS", \
1403 "PR_REGS", \
1404 "T_REGS", \
1405 "MAC_REGS", \
1406 "FPUL_REGS", \
1407 "SIBCALL_REGS", \
1408 "GENERAL_REGS", \
1409 "FP0_REGS", \
1410 "FP_REGS", \
1411 "DF_HI_REGS", \
1412 "DF_REGS", \
1413 "FPSCR_REGS", \
1414 "GENERAL_FP_REGS", \
1415 "TARGET_REGS", \
1416 "ALL_REGS", \
1417 }
1418
1419 /* Define which registers fit in which classes.
1420 This is an initializer for a vector of HARD_REG_SET
1421 of length N_REG_CLASSES. */
1422
1423 #define REG_CLASS_CONTENTS \
1424 { \
1425 /* NO_REGS: */ \
1426 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1427 /* R0_REGS: */ \
1428 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1429 /* PR_REGS: */ \
1430 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1431 /* T_REGS: */ \
1432 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1433 /* MAC_REGS: */ \
1434 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1435 /* FPUL_REGS: */ \
1436 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1437 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1438 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1439 /* GENERAL_REGS: */ \
1440 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1441 /* FP0_REGS: */ \
1442 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1443 /* FP_REGS: */ \
1444 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1445 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1446 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1447 /* DF_REGS: */ \
1448 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1449 /* FPSCR_REGS: */ \
1450 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1451 /* GENERAL_FP_REGS: */ \
1452 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1453 /* TARGET_REGS: */ \
1454 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1455 /* ALL_REGS: */ \
1456 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1457 }
1458
1459 /* The same information, inverted:
1460 Return the class number of the smallest class containing
1461 reg number REGNO. This could be a conditional expression
1462 or could index an array. */
1463
1464 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1465 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1466
1467 /* When defined, the compiler allows registers explicitly used in the
1468 rtl to be used as spill registers but prevents the compiler from
1469 extending the lifetime of these registers. */
1470
1471 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1472
1473 /* The order in which register should be allocated. */
1474 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1475 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1476 spilled or used otherwise, we better have the FP_REGS allocated first. */
1477 #define REG_ALLOC_ORDER \
1478 {/* Caller-saved FPRs */ \
1479 65, 66, 67, 68, 69, 70, 71, 64, \
1480 72, 73, 74, 75, 80, 81, 82, 83, \
1481 84, 85, 86, 87, 88, 89, 90, 91, \
1482 92, 93, 94, 95, 96, 97, 98, 99, \
1483 /* Callee-saved FPRs */ \
1484 76, 77, 78, 79,100,101,102,103, \
1485 104,105,106,107,108,109,110,111, \
1486 112,113,114,115,116,117,118,119, \
1487 120,121,122,123,124,125,126,127, \
1488 136,137,138,139,140,141,142,143, \
1489 /* FPSCR */ 151, \
1490 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1491 1, 2, 3, 7, 6, 5, 4, 0, \
1492 8, 9, 17, 19, 20, 21, 22, 23, \
1493 36, 37, 38, 39, 40, 41, 42, 43, \
1494 60, 61, 62, \
1495 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1496 10, 11, 12, 13, 14, 18, \
1497 /* SH5 callee-saved GPRs */ \
1498 28, 29, 30, 31, 32, 33, 34, 35, \
1499 44, 45, 46, 47, 48, 49, 50, 51, \
1500 52, 53, 54, 55, 56, 57, 58, 59, \
1501 /* FPUL */ 150, \
1502 /* SH5 branch target registers */ \
1503 128,129,130,131,132,133,134,135, \
1504 /* Fixed registers */ \
1505 15, 16, 24, 25, 26, 27, 63,144, \
1506 145,146,147,148,149,152 }
1507
1508 /* The class value for index registers, and the one for base regs. */
1509 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1510 #define BASE_REG_CLASS GENERAL_REGS
1511
1512 /* Get reg_class from a letter such as appears in the machine
1513 description. */
1514 extern enum reg_class reg_class_from_letter[];
1515
1516 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1517 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1518 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1519 \f
1520 /* Overview of uppercase letter constraints:
1521 A: Addresses (constraint len == 3)
1522 Ac4: sh4 cache operations
1523 Ac5: sh5 cache operations
1524 Bxx: miscellaneous constraints
1525 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1526 fldi0 / fldi0 cases
1527 C: Constants other than only CONST_INT (constraint len == 3)
1528 C16: 16 bit constant, literal or symbolic
1529 Csy: label or symbol
1530 Cpg: non-explicit constants that can be directly loaded into a general
1531 purpose register in PIC code. like 's' except we don't allow
1532 PIC_DIRECT_ADDR_P
1533 IJKLMNOP: CONT_INT constants
1534 Ixx: signed xx bit
1535 J16: 0xffffffff00000000 | 0x00000000ffffffff
1536 Kxx: unsigned xx bit
1537 M: 1
1538 N: 0
1539 P27: 1 | 2 | 8 | 16
1540 Q: pc relative load operand
1541 Rxx: reserved for exotic register classes.
1542 S: extra memory (storage) constraints (constraint len == 3)
1543 Sua: unaligned memory operations
1544 W: vector
1545 Z: zero in any mode
1546
1547 unused CONST_INT constraint letters: LO
1548 unused EXTRA_CONSTRAINT letters: D T U Y */
1549
1550 #if 1 /* check that the transition went well. */
1551 #define CONSTRAINT_LEN(C,STR) \
1552 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1553 || (C) == 'Y' \
1554 || ((C) == 'I' \
1555 && (((STR)[1] != '0' && (STR)[1] != '1') \
1556 || (STR)[2] < '0' || (STR)[2] > '9')) \
1557 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1558 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1559 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1560 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1561 ? -1 \
1562 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1563 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1564 || (C) == 'R' || (C) == 'S') \
1565 ? 3 \
1566 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1567 #else
1568 #define CONSTRAINT_LEN(C,STR) \
1569 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1570 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1571 || (C) == 'R' || (C) == 'S') \
1572 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1573 #endif
1574
1575 /* The letters I, J, K, L and M in a register constraint string
1576 can be used to stand for particular ranges of immediate operands.
1577 This macro defines what the ranges are.
1578 C is the letter, and VALUE is a constant value.
1579 Return 1 if VALUE is in the range specified by C.
1580 I08: arithmetic operand -127..128, as used in add, sub, etc
1581 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1582 P27: shift operand 1,2,8 or 16
1583 K08: logical operand 0..255, as used in and, or, etc.
1584 M: constant 1
1585 N: constant 0
1586 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1587 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1588 */
1589
1590 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1591 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1592 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1593 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1594 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1595 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1596 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1597 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1598 #define CONST_OK_FOR_I(VALUE, STR) \
1599 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1600 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1601 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1602 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1603 : 0)
1604
1605 #define CONST_OK_FOR_J16(VALUE) \
1606 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1607 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1608 #define CONST_OK_FOR_J(VALUE, STR) \
1609 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1610 : 0)
1611
1612 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1613 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1614 #define CONST_OK_FOR_K(VALUE, STR) \
1615 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1616 : 0)
1617 #define CONST_OK_FOR_P27(VALUE) \
1618 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1619 #define CONST_OK_FOR_P(VALUE, STR) \
1620 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1621 : 0)
1622 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1623 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1624 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1625 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1626 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1627 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1628 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1629 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1630 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1631 : 0)
1632
1633 /* Similar, but for floating constants, and defining letters G and H.
1634 Here VALUE is the CONST_DOUBLE rtx itself. */
1635
1636 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1637 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1638 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1639 : (C) == 'F')
1640
1641 /* Given an rtx X being reloaded into a reg required to be
1642 in class CLASS, return the class of reg to actually use.
1643 In general this is just CLASS; but on some machines
1644 in some cases it is preferable to use a more restrictive class. */
1645
1646 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1647 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1648 && (GET_CODE (X) == CONST_DOUBLE \
1649 || GET_CODE (X) == SYMBOL_REF) \
1650 ? GENERAL_REGS \
1651 : (CLASS)) \
1652
1653 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1654 ((((REGCLASS_HAS_FP_REG (CLASS) \
1655 && (GET_CODE (X) == REG \
1656 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1657 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1658 && TARGET_FMOVD)))) \
1659 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1660 && GET_CODE (X) == REG \
1661 && FP_REGISTER_P (REGNO (X)))) \
1662 && ! TARGET_SHMEDIA \
1663 && ((MODE) == SFmode || (MODE) == SImode)) \
1664 ? FPUL_REGS \
1665 : (((CLASS) == FPUL_REGS \
1666 || (REGCLASS_HAS_FP_REG (CLASS) \
1667 && ! TARGET_SHMEDIA && MODE == SImode)) \
1668 && (GET_CODE (X) == MEM \
1669 || (GET_CODE (X) == REG \
1670 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1671 || REGNO (X) == T_REG \
1672 || system_reg_operand (X, VOIDmode))))) \
1673 ? GENERAL_REGS \
1674 : ((CLASS) == TARGET_REGS \
1675 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1676 ? ((target_operand ((X), (MODE)) \
1677 && ! target_reg_operand ((X), (MODE))) \
1678 ? NO_REGS : GENERAL_REGS) \
1679 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1680 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1681 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1682 ? GENERAL_REGS \
1683 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1684 && TARGET_REGISTER_P (REGNO (X))) \
1685 ? GENERAL_REGS : NO_REGS)
1686
1687 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1688 ((REGCLASS_HAS_FP_REG (CLASS) \
1689 && ! TARGET_SHMEDIA \
1690 && immediate_operand ((X), (MODE)) \
1691 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1692 && (MODE) == SFmode && fldi_ok ())) \
1693 ? R0_REGS \
1694 : (CLASS == FPUL_REGS \
1695 && ((GET_CODE (X) == REG \
1696 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1697 || REGNO (X) == T_REG)) \
1698 || GET_CODE (X) == PLUS)) \
1699 ? GENERAL_REGS \
1700 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1701 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1702 ? GENERAL_REGS \
1703 : R0_REGS) \
1704 : (CLASS == FPSCR_REGS \
1705 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1706 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1707 ? GENERAL_REGS \
1708 : (REGCLASS_HAS_FP_REG (CLASS) \
1709 && TARGET_SHMEDIA \
1710 && immediate_operand ((X), (MODE)) \
1711 && (X) != CONST0_RTX (GET_MODE (X)) \
1712 && GET_MODE (X) != V4SFmode) \
1713 ? GENERAL_REGS \
1714 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1715
1716 /* Return the maximum number of consecutive registers
1717 needed to represent mode MODE in a register of class CLASS.
1718
1719 If TARGET_SHMEDIA, we need two FP registers per word.
1720 Otherwise we will need at most one register per word. */
1721 #define CLASS_MAX_NREGS(CLASS, MODE) \
1722 (TARGET_SHMEDIA \
1723 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1724 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1725 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1726
1727 /* If defined, gives a class of registers that cannot be used as the
1728 operand of a SUBREG that changes the mode of the object illegally. */
1729 /* ??? We need to renumber the internal numbers for the frnn registers
1730 when in little endian in order to allow mode size changes. */
1731
1732 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1733 sh_cannot_change_mode_class (FROM, TO, CLASS)
1734 \f
1735 /* Stack layout; function entry, exit and calling. */
1736
1737 /* Define the number of registers that can hold parameters.
1738 These macros are used only in other macro definitions below. */
1739
1740 #define NPARM_REGS(MODE) \
1741 (TARGET_FPU_ANY && (MODE) == SFmode \
1742 ? (TARGET_SH5 ? 12 : 8) \
1743 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1744 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1745 ? (TARGET_SH5 ? 12 : 8) \
1746 : (TARGET_SH5 ? 8 : 4))
1747
1748 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1749 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1750
1751 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1752 #define FIRST_FP_RET_REG FIRST_FP_REG
1753
1754 /* Define this if pushing a word on the stack
1755 makes the stack pointer a smaller address. */
1756 #define STACK_GROWS_DOWNWARD
1757
1758 /* Define this macro if the addresses of local variable slots are at
1759 negative offsets from the frame pointer.
1760
1761 The SH only has positive indexes, so grow the frame up. */
1762 /* #define FRAME_GROWS_DOWNWARD */
1763
1764 /* Offset from the frame pointer to the first local variable slot to
1765 be allocated. */
1766 #define STARTING_FRAME_OFFSET 0
1767
1768 /* If we generate an insn to push BYTES bytes,
1769 this says how many the stack pointer really advances by. */
1770 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1771 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1772 do correct alignment. */
1773 #if 0
1774 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1775 #endif
1776
1777 /* Offset of first parameter from the argument pointer register value. */
1778 #define FIRST_PARM_OFFSET(FNDECL) 0
1779
1780 /* Value is the number of byte of arguments automatically
1781 popped when returning from a subroutine call.
1782 FUNDECL is the declaration node of the function (as a tree),
1783 FUNTYPE is the data type of the function (as a tree),
1784 or for a library call it is an identifier node for the subroutine name.
1785 SIZE is the number of bytes of arguments passed on the stack.
1786
1787 On the SH, the caller does not pop any of its arguments that were passed
1788 on the stack. */
1789 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1790
1791 /* Value is the number of bytes of arguments automatically popped when
1792 calling a subroutine.
1793 CUM is the accumulated argument list.
1794
1795 On SHcompact, the call trampoline pops arguments off the stack. */
1796 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1797
1798 /* Some subroutine macros specific to this machine. */
1799
1800 #define BASE_RETURN_VALUE_REG(MODE) \
1801 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1802 ? FIRST_FP_RET_REG \
1803 : TARGET_FPU_ANY && (MODE) == SCmode \
1804 ? FIRST_FP_RET_REG \
1805 : (TARGET_FPU_DOUBLE \
1806 && ((MODE) == DFmode || (MODE) == SFmode \
1807 || (MODE) == DCmode || (MODE) == SCmode )) \
1808 ? FIRST_FP_RET_REG \
1809 : FIRST_RET_REG)
1810
1811 #define BASE_ARG_REG(MODE) \
1812 ((TARGET_SH2E && ((MODE) == SFmode)) \
1813 ? FIRST_FP_PARM_REG \
1814 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1815 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1816 ? FIRST_FP_PARM_REG \
1817 : FIRST_PARM_REG)
1818
1819 /* Define how to find the value returned by a function.
1820 VALTYPE is the data type of the value (as a tree).
1821 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1822 otherwise, FUNC is 0.
1823 For the SH, this is like LIBCALL_VALUE, except that we must change the
1824 mode like PROMOTE_MODE does.
1825 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1826 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1827
1828 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1829 gen_rtx_REG ( \
1830 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1831 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1832 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1833 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1834 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1835 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1836 || TREE_CODE (VALTYPE) == REAL_TYPE \
1837 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1838 && sh_promote_prototypes (VALTYPE) \
1839 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1840 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1841
1842 /* Define how to find the value returned by a library function
1843 assuming the value has mode MODE. */
1844 #define LIBCALL_VALUE(MODE) \
1845 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1846
1847 /* 1 if N is a possible register number for a function value. */
1848 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1849 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1850 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1851
1852 /* 1 if N is a possible register number for function argument passing. */
1853 /* ??? There are some callers that pass REGNO as int, and others that pass
1854 it as unsigned. We get warnings unless we do casts everywhere. */
1855 #define FUNCTION_ARG_REGNO_P(REGNO) \
1856 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1857 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1858 || (TARGET_FPU_ANY \
1859 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1860 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1861 + NPARM_REGS (SFmode))))
1862 \f
1863 /* Define a data type for recording info about an argument list
1864 during the scan of that argument list. This data type should
1865 hold all necessary information about the function itself
1866 and about the args processed so far, enough to enable macros
1867 such as FUNCTION_ARG to determine where the next arg should go.
1868
1869 On SH, this is a single integer, which is a number of words
1870 of arguments scanned so far (including the invisible argument,
1871 if any, which holds the structure-value-address).
1872 Thus NARGREGS or more means all following args should go on the stack. */
1873
1874 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1875 struct sh_args {
1876 int arg_count[2];
1877 int force_mem;
1878 /* Nonzero if a prototype is available for the function. */
1879 int prototype_p;
1880 /* The number of an odd floating-point register, that should be used
1881 for the next argument of type float. */
1882 int free_single_fp_reg;
1883 /* Whether we're processing an outgoing function call. */
1884 int outgoing;
1885 /* The number of general-purpose registers that should have been
1886 used to pass partial arguments, that are passed totally on the
1887 stack. On SHcompact, a call trampoline will pop them off the
1888 stack before calling the actual function, and, if the called
1889 function is implemented in SHcompact mode, the incoming arguments
1890 decoder will push such arguments back onto the stack. For
1891 incoming arguments, STACK_REGS also takes into account other
1892 arguments passed by reference, that the decoder will also push
1893 onto the stack. */
1894 int stack_regs;
1895 /* The number of general-purpose registers that should have been
1896 used to pass arguments, if the arguments didn't have to be passed
1897 by reference. */
1898 int byref_regs;
1899 /* Set as by shcompact_byref if the current argument is to be passed
1900 by reference. */
1901 int byref;
1902
1903 /* call_cookie is a bitmask used by call expanders, as well as
1904 function prologue and epilogues, to allow SHcompact to comply
1905 with the SH5 32-bit ABI, that requires 64-bit registers to be
1906 used even though only the lower 32-bit half is visible in
1907 SHcompact mode. The strategy is to call SHmedia trampolines.
1908
1909 The alternatives for each of the argument-passing registers are
1910 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1911 contents from the address in it; (d) add 8 to it, storing the
1912 result in the next register, then (c); (e) copy it from some
1913 floating-point register,
1914
1915 Regarding copies from floating-point registers, r2 may only be
1916 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1917 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1918 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1919 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1920 dr10.
1921
1922 The bit mask is structured as follows:
1923
1924 - 1 bit to tell whether to set up a return trampoline.
1925
1926 - 3 bits to count the number consecutive registers to pop off the
1927 stack.
1928
1929 - 4 bits for each of r9, r8, r7 and r6.
1930
1931 - 3 bits for each of r5, r4, r3 and r2.
1932
1933 - 3 bits set to 0 (the most significant ones)
1934
1935 3 2 1 0
1936 1098 7654 3210 9876 5432 1098 7654 3210
1937 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1938 2223 3344 4555 6666 7777 8888 9999 SSS-
1939
1940 - If F is set, the register must be copied from an FP register,
1941 whose number is encoded in the remaining bits.
1942
1943 - Else, if L is set, the register must be loaded from the address
1944 contained in it. If the P bit is *not* set, the address of the
1945 following dword should be computed first, and stored in the
1946 following register.
1947
1948 - Else, if P is set, the register alone should be popped off the
1949 stack.
1950
1951 - After all this processing, the number of registers represented
1952 in SSS will be popped off the stack. This is an optimization
1953 for pushing/popping consecutive registers, typically used for
1954 varargs and large arguments partially passed in registers.
1955
1956 - If T is set, a return trampoline will be set up for 64-bit
1957 return values to be split into 2 32-bit registers. */
1958 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1959 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1960 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1961 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1962 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1963 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1964 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1965 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1966 #define CALL_COOKIE_INT_REG(REG, VAL) \
1967 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1968 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1969 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1970 long call_cookie;
1971
1972 /* This is set to nonzero when the call in question must use the Renesas ABI,
1973 even without the -mrenesas option. */
1974 int renesas_abi;
1975 };
1976
1977 #define CUMULATIVE_ARGS struct sh_args
1978
1979 #define GET_SH_ARG_CLASS(MODE) \
1980 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1981 ? SH_ARG_FLOAT \
1982 /* There's no mention of complex float types in the SH5 ABI, so we
1983 should presumably handle them as aggregate types. */ \
1984 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1985 ? SH_ARG_INT \
1986 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1987 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1988 ? SH_ARG_FLOAT : SH_ARG_INT)
1989
1990 #define ROUND_ADVANCE(SIZE) \
1991 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1992
1993 /* Round a register number up to a proper boundary for an arg of mode
1994 MODE.
1995
1996 The SH doesn't care about double alignment, so we only
1997 round doubles to even regs when asked to explicitly. */
1998
1999 #define ROUND_REG(CUM, MODE) \
2000 (((TARGET_ALIGN_DOUBLE \
2001 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
2002 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
2003 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
2004 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
2005 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
2006 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
2007
2008 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2009 for a call to a function whose data type is FNTYPE.
2010 For a library call, FNTYPE is 0.
2011
2012 On SH, the offset always starts at 0: the first parm reg is always
2013 the same reg for a given argument class.
2014
2015 For TARGET_HITACHI, the structure value pointer is passed in memory. */
2016
2017 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
2018 do { \
2019 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
2020 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
2021 (CUM).renesas_abi = sh_attr_renesas_p (FNTYPE) ? 1 : 0; \
2022 (CUM).force_mem \
2023 = ((TARGET_HITACHI || (CUM).renesas_abi) && (FNTYPE) \
2024 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
2025 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
2026 (CUM).arg_count[(int) SH_ARG_INT] \
2027 = (TARGET_SH5 && (FNTYPE) \
2028 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
2029 (CUM).free_single_fp_reg = 0; \
2030 (CUM).outgoing = 1; \
2031 (CUM).stack_regs = 0; \
2032 (CUM).byref_regs = 0; \
2033 (CUM).byref = 0; \
2034 (CUM).call_cookie \
2035 = (CALL_COOKIE_RET_TRAMP \
2036 (TARGET_SHCOMPACT && (FNTYPE) \
2037 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
2038 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
2039 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
2040 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
2041 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
2042 (FNTYPE))) \
2043 == FIRST_RET_REG))); \
2044 } while (0)
2045
2046 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
2047 do { \
2048 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0, 0); \
2049 (CUM).call_cookie \
2050 = (CALL_COOKIE_RET_TRAMP \
2051 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
2052 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
2053 } while (0)
2054
2055 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
2056 do { \
2057 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0, 0); \
2058 (CUM).outgoing = 0; \
2059 } while (0)
2060
2061 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2062 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
2063 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2064 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
2065
2066 /* Return boolean indicating arg of mode MODE will be passed in a reg.
2067 This macro is only used in this file. */
2068
2069 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2070 (((TYPE) == 0 \
2071 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2072 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2073 || ! (AGGREGATE_TYPE_P (TYPE) \
2074 || (!TARGET_FPU_ANY \
2075 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2076 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2077 && ! (CUM).force_mem \
2078 && (TARGET_SH2E \
2079 ? ((MODE) == BLKmode \
2080 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2081 + int_size_in_bytes (TYPE)) \
2082 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2083 : ((ROUND_REG((CUM), (MODE)) \
2084 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2085 <= NPARM_REGS (MODE))) \
2086 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2087
2088 /* By accident we got stuck with passing SCmode on SH4 little endian
2089 in two registers that are nominally successive - which is different from
2090 two single SFmode values, where we take endianness translation into
2091 account. That does not work at all if an odd number of registers is
2092 already in use, so that got fixed, but library functions are still more
2093 likely to use complex numbers without mixing them with SFmode arguments
2094 (which in C would have to be structures), so for the sake of ABI
2095 compatibility the way SCmode values are passed when an even number of
2096 FP registers is in use remains different from a pair of SFmode values for
2097 now.
2098 I.e.:
2099 foo (double); a: fr5,fr4
2100 foo (float a, float b); a: fr5 b: fr4
2101 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2102 this should be the other way round...
2103 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2104 #define FUNCTION_ARG_SCmode_WART 1
2105
2106 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2107 register in SHcompact mode, it must be padded in the most
2108 significant end. This means that passing it by reference wouldn't
2109 pad properly on a big-endian machine. In this particular case, we
2110 pass this argument on the stack, in a way that the call trampoline
2111 will load its value into the appropriate register. */
2112 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2113 ((MODE) == BLKmode \
2114 && TARGET_SHCOMPACT \
2115 && ! TARGET_LITTLE_ENDIAN \
2116 && int_size_in_bytes (TYPE) > 4 \
2117 && int_size_in_bytes (TYPE) < 8)
2118
2119 /* Minimum alignment for an argument to be passed by callee-copy
2120 reference. We need such arguments to be aligned to 8 byte
2121 boundaries, because they'll be loaded using quad loads. */
2122 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2123
2124 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
2125 ((CUM).outgoing \
2126 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
2127 : GET_MODE_ALIGNMENT (MODE)) \
2128 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
2129
2130 /* The SH5 ABI requires floating-point arguments to be passed to
2131 functions without a prototype in both an FP register and a regular
2132 register or the stack. When passing the argument in both FP and
2133 general-purpose registers, list the FP register first. */
2134 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2135 (gen_rtx_PARALLEL \
2136 ((MODE), \
2137 gen_rtvec (2, \
2138 gen_rtx_EXPR_LIST \
2139 (VOIDmode, \
2140 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2141 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2142 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2143 : NULL_RTX), \
2144 const0_rtx), \
2145 gen_rtx_EXPR_LIST \
2146 (VOIDmode, \
2147 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2148 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2149 + (CUM).arg_count[(int) SH_ARG_INT]) \
2150 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2151 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2152 const0_rtx))))
2153
2154 /* The SH5 ABI requires regular registers or stack slots to be
2155 reserved for floating-point arguments. Registers are taken care of
2156 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2157 Unfortunately, there's no way to just reserve a stack slot, so
2158 we'll end up needlessly storing a copy of the argument in the
2159 stack. For incoming arguments, however, the PARALLEL will be
2160 optimized to the register-only form, and the value in the stack
2161 slot won't be used at all. */
2162 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2163 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2164 ? gen_rtx_REG ((MODE), (REG)) \
2165 : gen_rtx_PARALLEL ((MODE), \
2166 gen_rtvec (2, \
2167 gen_rtx_EXPR_LIST \
2168 (VOIDmode, NULL_RTX, \
2169 const0_rtx), \
2170 gen_rtx_EXPR_LIST \
2171 (VOIDmode, gen_rtx_REG ((MODE), \
2172 (REG)), \
2173 const0_rtx))))
2174
2175 /* For an arg passed partly in registers and partly in memory,
2176 this is the number of registers used.
2177 For args passed entirely in registers or entirely in memory, zero.
2178
2179 We sometimes split args. */
2180
2181 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2182 ((! TARGET_SH5 \
2183 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2184 && ! TARGET_SH4 \
2185 && (ROUND_REG ((CUM), (MODE)) \
2186 + ((MODE) != BLKmode \
2187 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2188 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2189 > NPARM_REGS (MODE))) \
2190 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2191 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2192 && ! TARGET_SHCOMPACT) \
2193 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2194 : 0)
2195
2196 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2197 (TARGET_SH5 \
2198 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2199 || (MODE) == DCmode) \
2200 && ((CUM).arg_count[(int) SH_ARG_INT] \
2201 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2202
2203 /* Perform any needed actions needed for a function that is receiving a
2204 variable number of arguments. */
2205
2206 /* Implement `va_start' for varargs and stdarg. */
2207 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2208 sh_va_start (valist, nextarg)
2209
2210 /* Call the function profiler with a given profile label.
2211 We use two .aligns, so as to make sure that both the .long is aligned
2212 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2213 from the trapa instruction. */
2214
2215 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2216 { \
2217 fprintf((STREAM), "\t.align\t2\n"); \
2218 fprintf((STREAM), "\ttrapa\t#33\n"); \
2219 fprintf((STREAM), "\t.align\t2\n"); \
2220 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2221 }
2222
2223 /* Define this macro if the code for function profiling should come
2224 before the function prologue. Normally, the profiling code comes
2225 after. */
2226
2227 #define PROFILE_BEFORE_PROLOGUE
2228
2229 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2230 the stack pointer does not matter. The value is tested only in
2231 functions that have frame pointers.
2232 No definition is equivalent to always zero. */
2233
2234 #define EXIT_IGNORE_STACK 1
2235
2236 /*
2237 On the SH, the trampoline looks like
2238 2 0002 D202 mov.l l2,r2
2239 1 0000 D301 mov.l l1,r3
2240 3 0004 422B jmp @r2
2241 4 0006 0009 nop
2242 5 0008 00000000 l1: .long area
2243 6 000c 00000000 l2: .long function */
2244
2245 /* Length in units of the trampoline for entering a nested function. */
2246 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2247
2248 /* Alignment required for a trampoline in bits . */
2249 #define TRAMPOLINE_ALIGNMENT \
2250 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2251 : TARGET_SHMEDIA ? 256 : 64)
2252
2253 /* Emit RTL insns to initialize the variable parts of a trampoline.
2254 FNADDR is an RTX for the address of the function's pure code.
2255 CXT is an RTX for the static chain value for the function. */
2256
2257 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2258 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2259
2260 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2261
2262 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2263 { \
2264 if (TARGET_SHMEDIA) \
2265 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2266 gen_reg_rtx (Pmode), 0, \
2267 OPTAB_LIB_WIDEN); \
2268 } while (0)
2269
2270 /* A C expression whose value is RTL representing the value of the return
2271 address for the frame COUNT steps up from the current frame.
2272 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2273 can ignore COUNT. */
2274
2275 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2276 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2277
2278 /* A C expression whose value is RTL representing the location of the
2279 incoming return address at the beginning of any function, before the
2280 prologue. This RTL is either a REG, indicating that the return
2281 value is saved in REG, or a MEM representing a location in
2282 the stack. */
2283 #define INCOMING_RETURN_ADDR_RTX \
2284 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2285 \f
2286 /* Addressing modes, and classification of registers for them. */
2287 #define HAVE_POST_INCREMENT TARGET_SH1
2288 #define HAVE_PRE_DECREMENT TARGET_SH1
2289
2290 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2291 ? 0 : TARGET_SH1)
2292 #define USE_LOAD_PRE_DECREMENT(mode) 0
2293 #define USE_STORE_POST_INCREMENT(mode) 0
2294 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2295 ? 0 : TARGET_SH1)
2296
2297 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2298 < (TARGET_SMALLCODE ? 2 : \
2299 ((ALIGN >= 32) ? 16 : 2)))
2300
2301 /* Macros to check register numbers against specific register classes. */
2302
2303 /* These assume that REGNO is a hard or pseudo reg number.
2304 They give nonzero only if REGNO is a hard reg of the suitable class
2305 or a pseudo reg currently allocated to a suitable hard reg.
2306 Since they use reg_renumber, they are safe only once reg_renumber
2307 has been allocated, which happens in local-alloc.c. */
2308
2309 #define REGNO_OK_FOR_BASE_P(REGNO) \
2310 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2311 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2312 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2313 (TARGET_SHMEDIA \
2314 ? (GENERAL_REGISTER_P (REGNO) \
2315 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2316 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2317
2318 /* Maximum number of registers that can appear in a valid memory
2319 address. */
2320
2321 #define MAX_REGS_PER_ADDRESS 2
2322
2323 /* Recognize any constant value that is a valid address. */
2324
2325 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2326
2327 /* Nonzero if the constant value X is a legitimate general operand. */
2328
2329 #define LEGITIMATE_CONSTANT_P(X) \
2330 (TARGET_SHMEDIA \
2331 ? ((GET_MODE (X) != DFmode \
2332 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2333 || (X) == CONST0_RTX (GET_MODE (X)) \
2334 || ! TARGET_SHMEDIA_FPU \
2335 || TARGET_SHMEDIA64) \
2336 : (GET_CODE (X) != CONST_DOUBLE \
2337 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2338 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2339
2340 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2341 and check its validity for a certain class.
2342 We have two alternate definitions for each of them.
2343 The usual definition accepts all pseudo regs; the other rejects
2344 them unless they have been allocated suitable hard regs.
2345 The symbol REG_OK_STRICT causes the latter definition to be used. */
2346
2347 #ifndef REG_OK_STRICT
2348
2349 /* Nonzero if X is a hard reg that can be used as a base reg
2350 or if it is a pseudo reg. */
2351 #define REG_OK_FOR_BASE_P(X) \
2352 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2353
2354 /* Nonzero if X is a hard reg that can be used as an index
2355 or if it is a pseudo reg. */
2356 #define REG_OK_FOR_INDEX_P(X) \
2357 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2358 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2359
2360 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2361 or if X is a pseudo reg. */
2362 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2363 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2364 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2365
2366 #else
2367
2368 /* Nonzero if X is a hard reg that can be used as a base reg. */
2369 #define REG_OK_FOR_BASE_P(X) \
2370 REGNO_OK_FOR_BASE_P (REGNO (X))
2371
2372 /* Nonzero if X is a hard reg that can be used as an index. */
2373 #define REG_OK_FOR_INDEX_P(X) \
2374 REGNO_OK_FOR_INDEX_P (REGNO (X))
2375
2376 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2377 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2378 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2379
2380 #endif
2381
2382 /* The 'Q' constraint is a pc relative load operand. */
2383 #define EXTRA_CONSTRAINT_Q(OP) \
2384 (GET_CODE (OP) == MEM \
2385 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2386 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2387 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2388 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2389 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2390
2391 /* Extra address constraints. */
2392 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2393
2394 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2395 operand is not SCRATCH (i.e. REG) then R0 is probably being
2396 used, hence mova is being used, hence do not select this pattern */
2397 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2398 #define EXTRA_CONSTRAINT_B(OP, STR) \
2399 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2400 : 0)
2401
2402 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2403 #define EXTRA_CONSTRAINT_C16(OP) \
2404 (GET_CODE (OP) == CONST \
2405 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2406 && GET_MODE (XEXP ((OP), 0)) == DImode \
2407 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2408 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2409 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2410 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2411 && (MOVI_SHORI_BASE_OPERAND_P \
2412 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2413 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2414 1)) == CONST_INT)))
2415
2416 /* Check whether OP is a datalabel unspec. */
2417 #define DATALABEL_REF_NO_CONST_P(OP) \
2418 (GET_CODE (OP) == UNSPEC \
2419 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2420 && XVECLEN ((OP), 0) == 1 \
2421 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2422 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2423
2424 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2425 CONST. */
2426 #define DATALABEL_REF_P(OP) \
2427 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2428 || DATALABEL_REF_NO_CONST_P (OP))
2429
2430 #define GOT_ENTRY_P(OP) \
2431 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2432 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2433
2434 #define GOTPLT_ENTRY_P(OP) \
2435 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2436 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2437
2438 #define UNSPEC_GOTOFF_P(OP) \
2439 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2440
2441 #define GOTOFF_P(OP) \
2442 (GET_CODE (OP) == CONST \
2443 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2444 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2445 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2446 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2447
2448 #define PIC_ADDR_P(OP) \
2449 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2450 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2451
2452 #define PIC_OFFSET_P(OP) \
2453 (PIC_ADDR_P (OP) \
2454 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2455 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2456
2457 #define PIC_DIRECT_ADDR_P(OP) \
2458 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2459
2460 #define NON_PIC_REFERENCE_P(OP) \
2461 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2462 || DATALABEL_REF_P (OP) \
2463 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2464 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2465 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2466 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2467
2468 #define PIC_REFERENCE_P(OP) \
2469 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2470 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2471
2472 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2473 (flag_pic \
2474 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2475 || PIC_OFFSET_P (OP)) \
2476 : NON_PIC_REFERENCE_P (OP))
2477
2478 /* The `Csy' constraint is a label or a symbol. */
2479 #define EXTRA_CONSTRAINT_Csy(OP) \
2480 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2481
2482 /* A zero in any shape or form. */
2483 #define EXTRA_CONSTRAINT_Z(OP) \
2484 ((OP) == CONST0_RTX (GET_MODE (OP)))
2485
2486 /* Any vector constant we can handle. */
2487 #define EXTRA_CONSTRAINT_W(OP) \
2488 (GET_CODE (OP) == CONST_VECTOR \
2489 && (sh_rep_vec ((OP), VOIDmode) \
2490 || (HOST_BITS_PER_WIDE_INT >= 64 \
2491 ? sh_const_vec ((OP), VOIDmode) \
2492 : sh_1el_vec ((OP), VOIDmode))))
2493
2494 /* A non-explicit constant that can be loaded directly into a general purpose
2495 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2496 #define EXTRA_CONSTRAINT_Cpg(OP) \
2497 (CONSTANT_P (OP) \
2498 && GET_CODE (OP) != CONST_INT \
2499 && GET_CODE (OP) != CONST_DOUBLE \
2500 && (!flag_pic \
2501 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2502 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2503 && GET_CODE (OP) != LABEL_REF)))
2504 #define EXTRA_CONSTRAINT_C(OP, STR) \
2505 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2506 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2507 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2508 : 0)
2509
2510 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2511 #define EXTRA_CONSTRAINT_Sr0(OP) \
2512 (memory_operand((OP), GET_MODE (OP)) \
2513 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2514 #define EXTRA_CONSTRAINT_Sua(OP) \
2515 (memory_operand((OP), GET_MODE (OP)) \
2516 && GET_CODE (XEXP (OP, 0)) != PLUS)
2517 #define EXTRA_CONSTRAINT_S(OP, STR) \
2518 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2519 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2520 : 0)
2521
2522 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2523 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2524 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2525 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2526 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2527 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2528 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2529 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2530 : 0)
2531 \f
2532 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2533 that is a valid memory address for an instruction.
2534 The MODE argument is the machine mode for the MEM expression
2535 that wants to use this address. */
2536
2537 #define MODE_DISP_OK_4(X,MODE) \
2538 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2539 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2540
2541 #define MODE_DISP_OK_8(X,MODE) \
2542 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2543 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2544
2545 #define BASE_REGISTER_RTX_P(X) \
2546 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2547 || (GET_CODE (X) == SUBREG \
2548 && GET_CODE (SUBREG_REG (X)) == REG \
2549 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2550
2551 /* Since this must be r0, which is a single register class, we must check
2552 SUBREGs more carefully, to be sure that we don't accept one that extends
2553 outside the class. */
2554 #define INDEX_REGISTER_RTX_P(X) \
2555 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2556 || (GET_CODE (X) == SUBREG \
2557 && GET_CODE (SUBREG_REG (X)) == REG \
2558 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2559
2560 /* Jump to LABEL if X is a valid address RTX. This must also take
2561 REG_OK_STRICT into account when deciding about valid registers, but it uses
2562 the above macros so we are in luck.
2563
2564 Allow REG
2565 REG+disp
2566 REG+r0
2567 REG++
2568 --REG */
2569
2570 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2571 into the FRx registers. We implement this by setting the maximum offset
2572 to zero when the value is SFmode. This also restricts loading of SFmode
2573 values into the integer registers, but that can't be helped. */
2574
2575 /* The SH allows a displacement in a QI or HI amode, but only when the
2576 other operand is R0. GCC doesn't handle this very well, so we forgo
2577 all of that.
2578
2579 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2580 DI can be any number 0..60. */
2581
2582 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2583 do { \
2584 if (GET_CODE (OP) == CONST_INT) \
2585 { \
2586 if (TARGET_SHMEDIA) \
2587 { \
2588 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2589 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2590 && INTVAL (OP) >= -512 * MODE_SIZE \
2591 && INTVAL (OP) < 512 * MODE_SIZE) \
2592 goto LABEL; \
2593 else \
2594 break; \
2595 } \
2596 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2597 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2598 } \
2599 } while(0)
2600
2601 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2602 { \
2603 if (BASE_REGISTER_RTX_P (X)) \
2604 goto LABEL; \
2605 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2606 && ! TARGET_SHMEDIA \
2607 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2608 goto LABEL; \
2609 else if (GET_CODE (X) == PLUS \
2610 && ((MODE) != PSImode || reload_completed)) \
2611 { \
2612 rtx xop0 = XEXP ((X), 0); \
2613 rtx xop1 = XEXP ((X), 1); \
2614 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2615 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2616 if (GET_MODE_SIZE (MODE) <= 4 \
2617 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2618 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2619 { \
2620 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2621 goto LABEL; \
2622 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2623 goto LABEL; \
2624 } \
2625 } \
2626 }
2627 \f
2628 /* Try machine-dependent ways of modifying an illegitimate address
2629 to be legitimate. If we find one, return the new, valid address.
2630 This macro is used in only one place: `memory_address' in explow.c.
2631
2632 OLDX is the address as it was before break_out_memory_refs was called.
2633 In some cases it is useful to look at this to decide what needs to be done.
2634
2635 MODE and WIN are passed so that this macro can use
2636 GO_IF_LEGITIMATE_ADDRESS.
2637
2638 It is always safe for this macro to do nothing. It exists to recognize
2639 opportunities to optimize the output.
2640
2641 For the SH, if X is almost suitable for indexing, but the offset is
2642 out of range, convert it into a normal form so that cse has a chance
2643 of reducing the number of address registers used. */
2644
2645 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2646 { \
2647 if (flag_pic) \
2648 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2649 if (GET_CODE (X) == PLUS \
2650 && (GET_MODE_SIZE (MODE) == 4 \
2651 || GET_MODE_SIZE (MODE) == 8) \
2652 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2653 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2654 && ! TARGET_SHMEDIA \
2655 && ! (TARGET_SH4 && (MODE) == DFmode) \
2656 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2657 { \
2658 rtx index_rtx = XEXP ((X), 1); \
2659 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2660 rtx sum; \
2661 \
2662 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2663 /* On rare occasions, we might get an unaligned pointer \
2664 that is indexed in a way to give an aligned address. \
2665 Therefore, keep the lower two bits in offset_base. */ \
2666 /* Instead of offset_base 128..131 use 124..127, so that \
2667 simple add suffices. */ \
2668 if (offset > 127) \
2669 { \
2670 offset_base = ((offset + 4) & ~60) - 4; \
2671 } \
2672 else \
2673 offset_base = offset & ~60; \
2674 /* Sometimes the normal form does not suit DImode. We \
2675 could avoid that by using smaller ranges, but that \
2676 would give less optimized code when SImode is \
2677 prevalent. */ \
2678 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2679 { \
2680 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2681 GEN_INT (offset_base), NULL_RTX, 0, \
2682 OPTAB_LIB_WIDEN); \
2683 \
2684 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2685 goto WIN; \
2686 } \
2687 } \
2688 }
2689
2690 /* A C compound statement that attempts to replace X, which is an address
2691 that needs reloading, with a valid memory address for an operand of
2692 mode MODE. WIN is a C statement label elsewhere in the code.
2693
2694 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2695 of the address. That will allow inheritance of the address reloads. */
2696
2697 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2698 { \
2699 if (GET_CODE (X) == PLUS \
2700 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2701 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2702 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2703 && ! TARGET_SHMEDIA \
2704 && ! (TARGET_SH4 && (MODE) == DFmode) \
2705 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2706 { \
2707 rtx index_rtx = XEXP (X, 1); \
2708 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2709 rtx sum; \
2710 \
2711 if (TARGET_SH2E && MODE == SFmode) \
2712 { \
2713 X = copy_rtx (X); \
2714 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2715 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2716 (TYPE)); \
2717 goto WIN; \
2718 } \
2719 /* Instead of offset_base 128..131 use 124..127, so that \
2720 simple add suffices. */ \
2721 if (offset > 127) \
2722 { \
2723 offset_base = ((offset + 4) & ~60) - 4; \
2724 } \
2725 else \
2726 offset_base = offset & ~60; \
2727 /* Sometimes the normal form does not suit DImode. We \
2728 could avoid that by using smaller ranges, but that \
2729 would give less optimized code when SImode is \
2730 prevalent. */ \
2731 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2732 { \
2733 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2734 GEN_INT (offset_base)); \
2735 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2736 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2737 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2738 (TYPE)); \
2739 goto WIN; \
2740 } \
2741 } \
2742 /* We must re-recognize what we created before. */ \
2743 else if (GET_CODE (X) == PLUS \
2744 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2745 && GET_CODE (XEXP (X, 0)) == PLUS \
2746 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2747 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2748 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2749 && ! TARGET_SHMEDIA \
2750 && ! (TARGET_SH2E && MODE == SFmode)) \
2751 { \
2752 /* Because this address is so complex, we know it must have \
2753 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2754 it is already unshared, and needs no further unsharing. */ \
2755 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2756 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2757 goto WIN; \
2758 } \
2759 }
2760
2761 /* Go to LABEL if ADDR (a legitimate address expression)
2762 has an effect that depends on the machine mode it is used for.
2763
2764 ??? Strictly speaking, we should also include all indexed addressing,
2765 because the index scale factor is the length of the operand.
2766 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2767 high if we did that. So we rely on reload to fix things up. */
2768
2769 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2770 { \
2771 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2772 goto LABEL; \
2773 }
2774 \f
2775 /* Specify the machine mode that this machine uses
2776 for the index in the tablejump instruction. */
2777 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2778
2779 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2780 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2781 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2782 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2783 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2784 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2785 : SImode)
2786
2787 /* Define as C expression which evaluates to nonzero if the tablejump
2788 instruction expects the table to contain offsets from the address of the
2789 table.
2790 Do not define this if the table should contain absolute addresses. */
2791 #define CASE_VECTOR_PC_RELATIVE 1
2792
2793 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2794 #define FLOAT_TYPE_SIZE 32
2795
2796 /* Since the SH2e has only `float' support, it is desirable to make all
2797 floating point types equivalent to `float'. */
2798 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4) ? 32 : 64)
2799
2800 /* 'char' is signed by default. */
2801 #define DEFAULT_SIGNED_CHAR 1
2802
2803 /* The type of size_t unsigned int. */
2804 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2805
2806 #undef PTRDIFF_TYPE
2807 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2808
2809 #define WCHAR_TYPE "short unsigned int"
2810 #define WCHAR_TYPE_SIZE 16
2811
2812 #define SH_ELF_WCHAR_TYPE "long int"
2813
2814 /* Max number of bytes we can move from memory to memory
2815 in one reasonably fast instruction. */
2816 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2817
2818 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2819 MOVE_MAX is not a compile-time constant. */
2820 #define MAX_MOVE_MAX 8
2821
2822 /* Max number of bytes we want move_by_pieces to be able to copy
2823 efficiently. */
2824 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2825
2826 /* Define if operations between registers always perform the operation
2827 on the full register even if a narrower mode is specified. */
2828 #define WORD_REGISTER_OPERATIONS
2829
2830 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2831 will either zero-extend or sign-extend. The value of this macro should
2832 be the code that says which one of the two operations is implicitly
2833 done, NIL if none. */
2834 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2835 /* FP registers can load SImode values, but don't implicitly sign-extend
2836 them to DImode. */
2837 #define LOAD_EXTEND_OP(MODE) \
2838 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2839 : (MODE) != SImode ? SIGN_EXTEND : NIL)
2840
2841 /* Define if loading short immediate values into registers sign extends. */
2842 #define SHORT_IMMEDIATES_SIGN_EXTEND
2843
2844 /* Nonzero if access to memory by bytes is no faster than for words. */
2845 #define SLOW_BYTE_ACCESS 1
2846
2847 /* Immediate shift counts are truncated by the output routines (or was it
2848 the assembler?). Shift counts in a register are truncated by SH. Note
2849 that the native compiler puts too large (> 32) immediate shift counts
2850 into a register and shifts by the register, letting the SH decide what
2851 to do instead of doing that itself. */
2852 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2853 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2854 expects - the sign bit is significant - so it appears that we need to
2855 leave this zero for correct SH3 code. */
2856 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2857
2858 /* All integers have the same format so truncation is easy. */
2859 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2860
2861 /* Define this if addresses of constant functions
2862 shouldn't be put through pseudo regs where they can be cse'd.
2863 Desirable on machines where ordinary constants are expensive
2864 but a CALL with constant address is cheap. */
2865 /*#define NO_FUNCTION_CSE 1*/
2866
2867 /* The machine modes of pointers and functions. */
2868 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2869 #define FUNCTION_MODE Pmode
2870
2871 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2872 are actually function calls with some special constraints on arguments
2873 and register usage.
2874
2875 These macros tell reorg that the references to arguments and
2876 register clobbers for insns of type sfunc do not appear to happen
2877 until after the millicode call. This allows reorg to put insns
2878 which set the argument registers into the delay slot of the millicode
2879 call -- thus they act more like traditional CALL_INSNs.
2880
2881 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2882 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2883 in particular. */
2884
2885 #define INSN_SETS_ARE_DELAYED(X) \
2886 ((GET_CODE (X) == INSN \
2887 && GET_CODE (PATTERN (X)) != SEQUENCE \
2888 && GET_CODE (PATTERN (X)) != USE \
2889 && GET_CODE (PATTERN (X)) != CLOBBER \
2890 && get_attr_is_sfunc (X)))
2891
2892 #define INSN_REFERENCES_ARE_DELAYED(X) \
2893 ((GET_CODE (X) == INSN \
2894 && GET_CODE (PATTERN (X)) != SEQUENCE \
2895 && GET_CODE (PATTERN (X)) != USE \
2896 && GET_CODE (PATTERN (X)) != CLOBBER \
2897 && get_attr_is_sfunc (X)))
2898
2899 \f
2900 /* Position Independent Code. */
2901
2902 /* We can't directly access anything that contains a symbol,
2903 nor can we indirect via the constant pool. */
2904 #define LEGITIMATE_PIC_OPERAND_P(X) \
2905 ((! nonpic_symbol_mentioned_p (X) \
2906 && (GET_CODE (X) != SYMBOL_REF \
2907 || ! CONSTANT_POOL_ADDRESS_P (X) \
2908 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2909 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2910
2911 #define SYMBOLIC_CONST_P(X) \
2912 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2913 && nonpic_symbol_mentioned_p (X))
2914 \f
2915 /* Compute extra cost of moving data between one register class
2916 and another. */
2917
2918 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2919 uses this information. Hence, the general register <-> floating point
2920 register information here is not used for SFmode. */
2921
2922 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2923 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2924 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2925
2926 #define REGCLASS_HAS_FP_REG(CLASS) \
2927 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2928 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2929
2930 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2931 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2932
2933 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2934 would be so that people with slow memory systems could generate
2935 different code that does fewer memory accesses. */
2936
2937 /* A C expression for the cost of a branch instruction. A value of 1
2938 is the default; other values are interpreted relative to that.
2939 The SH1 does not have delay slots, hence we get a pipeline stall
2940 at every branch. The SH4 is superscalar, so the single delay slot
2941 is not sufficient to keep both pipelines filled. */
2942 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2943 \f
2944 /* Assembler output control. */
2945
2946 /* A C string constant describing how to begin a comment in the target
2947 assembler language. The compiler assumes that the comment will end at
2948 the end of the line. */
2949 #define ASM_COMMENT_START "!"
2950
2951 #define ASM_APP_ON ""
2952 #define ASM_APP_OFF ""
2953 #define FILE_ASM_OP "\t.file\n"
2954 #define SET_ASM_OP "\t.set\t"
2955
2956 /* How to change between sections. */
2957
2958 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2959 #define DATA_SECTION_ASM_OP "\t.data"
2960
2961 #if defined CRT_BEGIN || defined CRT_END
2962 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2963 # undef TEXT_SECTION_ASM_OP
2964 # if __SHMEDIA__ == 1 && __SH5__ == 32
2965 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2966 # else
2967 # define TEXT_SECTION_ASM_OP "\t.text"
2968 # endif
2969 #endif
2970
2971
2972 /* If defined, a C expression whose value is a string containing the
2973 assembler operation to identify the following data as
2974 uninitialized global data. If not defined, and neither
2975 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2976 uninitialized global data will be output in the data section if
2977 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2978 used. */
2979 #ifndef BSS_SECTION_ASM_OP
2980 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2981 #endif
2982
2983 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2984 separate, explicit argument. If you define this macro, it is used
2985 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2986 handling the required alignment of the variable. The alignment is
2987 specified as the number of bits.
2988
2989 Try to use function `asm_output_aligned_bss' defined in file
2990 `varasm.c' when defining this macro. */
2991 #ifndef ASM_OUTPUT_ALIGNED_BSS
2992 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2993 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2994 #endif
2995
2996 /* Define this so that jump tables go in same section as the current function,
2997 which could be text or it could be a user defined section. */
2998 #define JUMP_TABLES_IN_TEXT_SECTION 1
2999
3000 #undef DO_GLOBAL_CTORS_BODY
3001 #define DO_GLOBAL_CTORS_BODY \
3002 { \
3003 typedef (*pfunc)(); \
3004 extern pfunc __ctors[]; \
3005 extern pfunc __ctors_end[]; \
3006 pfunc *p; \
3007 for (p = __ctors_end; p > __ctors; ) \
3008 { \
3009 (*--p)(); \
3010 } \
3011 }
3012
3013 #undef DO_GLOBAL_DTORS_BODY
3014 #define DO_GLOBAL_DTORS_BODY \
3015 { \
3016 typedef (*pfunc)(); \
3017 extern pfunc __dtors[]; \
3018 extern pfunc __dtors_end[]; \
3019 pfunc *p; \
3020 for (p = __dtors; p < __dtors_end; p++) \
3021 { \
3022 (*p)(); \
3023 } \
3024 }
3025
3026 #define ASM_OUTPUT_REG_PUSH(file, v) \
3027 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
3028
3029 #define ASM_OUTPUT_REG_POP(file, v) \
3030 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
3031
3032 /* DBX register number for a given compiler register number. */
3033 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3034 to match gdb. */
3035 /* svr4.h undefines this macro, yet we really want to use the same numbers
3036 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3037 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3038 register exists, so we should return -1 for invalid register numbers. */
3039 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3040
3041 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3042 used to use the encodings 245..260, but that doesn't make sense:
3043 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3044 the FP registers stay the same when switching between compact and media
3045 mode. Hence, we also need to use the same dwarf frame columns.
3046 Likewise, we need to support unwind information for SHmedia registers
3047 even in compact code. */
3048 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3049 (IN_RANGE ((REGNO), \
3050 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3051 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3052 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3053 : ((int) (REGNO) >= FIRST_FP_REG \
3054 && ((int) (REGNO) \
3055 <= (FIRST_FP_REG + \
3056 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3057 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3058 + (TARGET_SH5 ? 77 : 25)) \
3059 : XD_REGISTER_P (REGNO) \
3060 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3061 : TARGET_REGISTER_P (REGNO) \
3062 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3063 : (REGNO) == PR_REG \
3064 ? (TARGET_SH5 ? 18 : 17) \
3065 : (REGNO) == PR_MEDIA_REG \
3066 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3067 : (REGNO) == T_REG \
3068 ? (TARGET_SH5 ? 242 : 18) \
3069 : (REGNO) == GBR_REG \
3070 ? (TARGET_SH5 ? 238 : 19) \
3071 : (REGNO) == MACH_REG \
3072 ? (TARGET_SH5 ? 239 : 20) \
3073 : (REGNO) == MACL_REG \
3074 ? (TARGET_SH5 ? 240 : 21) \
3075 : (REGNO) == FPUL_REG \
3076 ? (TARGET_SH5 ? 244 : 23) \
3077 : (unsigned) -1)
3078
3079 /* This is how to output a reference to a symbol_ref. On SH5,
3080 references to non-code symbols must be preceded by `datalabel'. */
3081 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3082 do \
3083 { \
3084 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3085 fputs ("datalabel ", (FILE)); \
3086 assemble_name ((FILE), XSTR ((SYM), 0)); \
3087 } \
3088 while (0)
3089
3090 /* This is how to output an assembler line
3091 that says to advance the location counter
3092 to a multiple of 2**LOG bytes. */
3093
3094 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3095 if ((LOG) != 0) \
3096 fprintf ((FILE), "\t.align %d\n", (LOG))
3097
3098 /* Globalizing directive for a label. */
3099 #define GLOBAL_ASM_OP "\t.global\t"
3100
3101 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3102
3103 /* Output a relative address table. */
3104
3105 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3106 switch (GET_MODE (BODY)) \
3107 { \
3108 case SImode: \
3109 if (TARGET_SH5) \
3110 { \
3111 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3112 (VALUE), (REL)); \
3113 break; \
3114 } \
3115 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3116 break; \
3117 case HImode: \
3118 if (TARGET_SH5) \
3119 { \
3120 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3121 (VALUE), (REL)); \
3122 break; \
3123 } \
3124 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3125 break; \
3126 case QImode: \
3127 if (TARGET_SH5) \
3128 { \
3129 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3130 (VALUE), (REL)); \
3131 break; \
3132 } \
3133 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3134 break; \
3135 default: \
3136 break; \
3137 }
3138
3139 /* Output an absolute table element. */
3140
3141 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3142 if (! optimize || TARGET_BIGTABLE) \
3143 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3144 else \
3145 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3146
3147 \f
3148 /* A C statement to be executed just prior to the output of
3149 assembler code for INSN, to modify the extracted operands so
3150 they will be output differently.
3151
3152 Here the argument OPVEC is the vector containing the operands
3153 extracted from INSN, and NOPERANDS is the number of elements of
3154 the vector which contain meaningful data for this insn.
3155 The contents of this vector are what will be used to convert the insn
3156 template into assembler code, so you can change the assembler output
3157 by changing the contents of the vector. */
3158
3159 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3160 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3161
3162 /* Print operand X (an rtx) in assembler syntax to file FILE.
3163 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3164 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3165
3166 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3167
3168 /* Print a memory address as an operand to reference that memory location. */
3169
3170 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3171
3172 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3173 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3174 || (CHAR) == '$'|| (CHAR) == '\'')
3175
3176 /* Recognize machine-specific patterns that may appear within
3177 constants. Used for PIC-specific UNSPECs. */
3178 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3179 do \
3180 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3181 { \
3182 switch (XINT ((X), 1)) \
3183 { \
3184 case UNSPEC_DATALABEL: \
3185 fputs ("datalabel ", (STREAM)); \
3186 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3187 break; \
3188 case UNSPEC_PIC: \
3189 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3190 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3191 break; \
3192 case UNSPEC_GOT: \
3193 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3194 fputs ("@GOT", (STREAM)); \
3195 break; \
3196 case UNSPEC_GOTOFF: \
3197 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3198 fputs ("@GOTOFF", (STREAM)); \
3199 break; \
3200 case UNSPEC_PLT: \
3201 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3202 fputs ("@PLT", (STREAM)); \
3203 break; \
3204 case UNSPEC_GOTPLT: \
3205 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3206 fputs ("@GOTPLT", (STREAM)); \
3207 break; \
3208 case UNSPEC_DTPOFF: \
3209 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3210 fputs ("@DTPOFF", (STREAM)); \
3211 break; \
3212 case UNSPEC_GOTTPOFF: \
3213 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3214 fputs ("@GOTTPOFF", (STREAM)); \
3215 break; \
3216 case UNSPEC_TPOFF: \
3217 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3218 fputs ("@TPOFF", (STREAM)); \
3219 break; \
3220 case UNSPEC_CALLER: \
3221 { \
3222 char name[32]; \
3223 /* LPCS stands for Label for PIC Call Site. */ \
3224 ASM_GENERATE_INTERNAL_LABEL \
3225 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3226 assemble_name ((STREAM), name); \
3227 } \
3228 break; \
3229 default: \
3230 goto FAIL; \
3231 } \
3232 break; \
3233 } \
3234 else \
3235 goto FAIL; \
3236 while (0)
3237
3238 \f
3239 extern struct rtx_def *sh_compare_op0;
3240 extern struct rtx_def *sh_compare_op1;
3241
3242 /* Which processor to schedule for. The elements of the enumeration must
3243 match exactly the cpu attribute in the sh.md file. */
3244
3245 enum processor_type {
3246 PROCESSOR_SH1,
3247 PROCESSOR_SH2,
3248 PROCESSOR_SH2E,
3249 PROCESSOR_SH3,
3250 PROCESSOR_SH3E,
3251 PROCESSOR_SH4,
3252 PROCESSOR_SH4A,
3253 PROCESSOR_SH5
3254 };
3255
3256 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3257 extern enum processor_type sh_cpu;
3258
3259 extern int optimize; /* needed for gen_casesi. */
3260
3261 enum mdep_reorg_phase_e
3262 {
3263 SH_BEFORE_MDEP_REORG,
3264 SH_INSERT_USES_LABELS,
3265 SH_SHORTEN_BRANCHES0,
3266 SH_FIXUP_PCLOAD,
3267 SH_SHORTEN_BRANCHES1,
3268 SH_AFTER_MDEP_REORG
3269 };
3270
3271 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3272
3273 /* Handle Renesas compiler's pragmas. */
3274 #define REGISTER_TARGET_PRAGMAS() do { \
3275 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3276 c_register_pragma (0, "trapa", sh_pr_trapa); \
3277 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3278 } while (0)
3279
3280 /* Set when processing a function with pragma interrupt turned on. */
3281
3282 extern int pragma_interrupt;
3283
3284 /* Set when processing a function with interrupt attribute. */
3285
3286 extern int current_function_interrupt;
3287
3288 /* Set to an RTX containing the address of the stack to switch to
3289 for interrupt functions. */
3290 extern struct rtx_def *sp_switch;
3291
3292 extern int rtx_equal_function_value_matters;
3293
3294 \f
3295 /* Instructions with unfilled delay slots take up an
3296 extra two bytes for the nop in the delay slot.
3297 sh-dsp parallel processing insns are four bytes long. */
3298
3299 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3300 (LENGTH) += sh_insn_length_adjustment (X);
3301 \f
3302 /* Define the codes that are matched by predicates in sh.c. */
3303 #define PREDICATE_CODES \
3304 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3305 {"any_register_operand", {SUBREG, REG}}, \
3306 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3307 {"arith_reg_dest", {SUBREG, REG}}, \
3308 {"arith_reg_operand", {SUBREG, REG}}, \
3309 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3310 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3311 {"binary_logical_operator", {AND, IOR, XOR}}, \
3312 {"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \
3313 {"commutative_float_operator", {PLUS, MULT}}, \
3314 {"equality_comparison_operator", {EQ,NE}}, \
3315 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3316 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3317 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3318 {"fpscr_operand", {REG}}, \
3319 {"fpul_operand", {REG}}, \
3320 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3321 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3322 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3323 {"unaligned_load_operand", {MEM}}, \
3324 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3325 {"int_gpr_dest", {SUBREG, REG}}, \
3326 {"inqhi_operand", {TRUNCATE}}, \
3327 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3328 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3329 {"mextr_bit_offset", {CONST_INT}}, \
3330 {"noncommutative_float_operator", {MINUS, DIV}}, \
3331 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3332 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
3333 {"target_reg_operand", {SUBREG, REG}}, \
3334 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3335 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3336 {"register_operand", {SUBREG, REG}}, \
3337 {"sh_const_vec", {CONST_VECTOR}}, \
3338 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3339 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3340 {"symbol_ref_operand", {SYMBOL_REF}}, \
3341 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3342
3343 #define SPECIAL_MODE_PREDICATES \
3344 "any_register_operand", \
3345 "int_gpr_dest", \
3346 "trunc_hi_operand", \
3347 /* This line intentionally left blank. */
3348
3349 #define any_register_operand register_operand
3350
3351 /* Define this macro if it is advisable to hold scalars in registers
3352 in a wider mode than that declared by the program. In such cases,
3353 the value is constrained to be within the bounds of the declared
3354 type, but kept valid in the wider mode. The signedness of the
3355 extension may differ from that of the type.
3356
3357 Leaving the unsignedp unchanged gives better code than always setting it
3358 to 0. This is despite the fact that we have only signed char and short
3359 load instructions. */
3360 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3361 if (GET_MODE_CLASS (MODE) == MODE_INT \
3362 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3363 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3364 (MODE) = (TARGET_SH1 ? SImode : DImode);
3365
3366 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3367
3368 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3369 and popping arguments. However, we do have push/pop instructions, and
3370 rather limited offsets (4 bits) in load/store instructions, so it isn't
3371 clear if this would give better code. If implemented, should check for
3372 compatibility problems. */
3373
3374 #define SH_DYNAMIC_SHIFT_COST \
3375 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3376
3377
3378 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3379
3380 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3381
3382 #define ACTUAL_NORMAL_MODE(ENTITY) \
3383 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3384
3385 #define NORMAL_MODE(ENTITY) \
3386 (sh_cfun_interrupt_handler_p () \
3387 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3388 : ACTUAL_NORMAL_MODE (ENTITY))
3389
3390 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3391
3392 #define MODE_EXIT(ENTITY) \
3393 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3394
3395 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3396 && (REGNO) == FPSCR_REG)
3397
3398 #define MODE_NEEDED(ENTITY, INSN) \
3399 (recog_memoized (INSN) >= 0 \
3400 ? get_attr_fp_mode (INSN) \
3401 : FP_MODE_NONE)
3402
3403 #define MODE_AFTER(MODE, INSN) \
3404 (TARGET_HITACHI \
3405 && recog_memoized (INSN) >= 0 \
3406 && get_attr_fp_set (INSN) != FP_SET_NONE \
3407 ? (int) get_attr_fp_set (INSN) \
3408 : (MODE))
3409
3410 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3411 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3412
3413 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3414 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3415
3416 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3417 sh_can_redirect_branch ((INSN), (SEQ))
3418
3419 #define DWARF_FRAME_RETURN_COLUMN \
3420 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3421
3422 #define EH_RETURN_DATA_REGNO(N) \
3423 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3424
3425 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3426 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3427
3428 /* We have to distinguish between code and data, so that we apply
3429 datalabel where and only where appropriate. Use textrel for code. */
3430 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3431 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3432 | ((CODE) ? DW_EH_PE_textrel : flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))
3433
3434 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3435 indirect are handled automatically. */
3436 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3437 do { \
3438 if (((ENCODING) & 0x70) == DW_EH_PE_textrel) \
3439 { \
3440 encoding &= ~DW_EH_PE_textrel; \
3441 encoding |= flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr; \
3442 if (GET_CODE (ADDR) != SYMBOL_REF) \
3443 abort (); \
3444 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3445 if (0) goto DONE; \
3446 } \
3447 } while (0)
3448
3449 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3450 /* SH constant pool breaks the devices in crtstuff.c to control section
3451 in where code resides. We have to write it as asm code. */
3452 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3453 asm (SECTION_OP "\n\
3454 mov.l 1f,r1\n\
3455 mova 2f,r0\n\
3456 braf r1\n\
3457 lds r0,pr\n\
3458 0: .p2align 2\n\
3459 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3460 2:\n" TEXT_SECTION_ASM_OP);
3461 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3462
3463 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3464 (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
3465 ? (current_function_is_leaf \
3466 && ! sh_pr_n_sets () \
3467 && ! (TARGET_SHCOMPACT \
3468 && ((current_function_args_info.call_cookie \
3469 & ~ CALL_COOKIE_RET_TRAMP (1)) \
3470 || current_function_has_nonlocal_label)) \
3471 ? (hard_reg) \
3472 : gen_rtx_MEM (Pmode, return_address_pointer_rtx)) \
3473 : NULL_RTX)
3474
3475 #endif /* ! GCC_SH_H */
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