1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
43 #include "target-def.h"
45 /* Save the operands last given to a compare for use when we
46 generate a scc or bcc insn. */
47 rtx m32r_compare_op0
, m32r_compare_op1
;
49 /* Array of valid operand punctuation characters. */
50 char m32r_punct_chars
[256];
52 /* Selected code model. */
53 const char * m32r_model_string
= M32R_MODEL_DEFAULT
;
54 enum m32r_model m32r_model
;
56 /* Selected SDA support. */
57 const char * m32r_sdata_string
= M32R_SDATA_DEFAULT
;
58 enum m32r_sdata m32r_sdata
;
60 /* Scheduler support */
61 static int m32r_sched_odd_word_p
;
63 /* Machine-specific symbol_ref flags. */
64 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
65 #define SYMBOL_REF_MODEL(X) \
66 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
68 /* For string literals, etc. */
69 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
71 /* Forward declaration. */
72 static void init_reg_tables
PARAMS ((void));
73 static void block_move_call
PARAMS ((rtx
, rtx
, rtx
));
74 static int m32r_is_insn
PARAMS ((rtx
));
75 const struct attribute_spec m32r_attribute_table
[];
76 static tree m32r_handle_model_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
77 static void m32r_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
78 static void m32r_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
80 static void m32r_file_start
PARAMS ((void));
82 static int m32r_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
83 static int m32r_adjust_priority
PARAMS ((rtx
, int));
84 static void m32r_sched_init
PARAMS ((FILE *, int, int));
85 static int m32r_sched_reorder
PARAMS ((FILE *, int, rtx
*, int *, int));
86 static int m32r_variable_issue
PARAMS ((FILE *, int, rtx
, int));
87 static int m32r_issue_rate
PARAMS ((void));
89 static void m32r_encode_section_info
PARAMS ((tree
, rtx
, int));
90 static bool m32r_in_small_data_p
PARAMS ((tree
));
91 static void init_idents
PARAMS ((void));
92 static bool m32r_rtx_costs
PARAMS ((rtx
, int, int, int *));
94 /* Initialize the GCC target structure. */
95 #undef TARGET_ATTRIBUTE_TABLE
96 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
98 #undef TARGET_ASM_ALIGNED_HI_OP
99 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
100 #undef TARGET_ASM_ALIGNED_SI_OP
101 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
103 #undef TARGET_ASM_FUNCTION_PROLOGUE
104 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
105 #undef TARGET_ASM_FUNCTION_EPILOGUE
106 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
108 #undef TARGET_ASM_FILE_START
109 #define TARGET_ASM_FILE_START m32r_file_start
111 #undef TARGET_SCHED_ADJUST_COST
112 #define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
113 #undef TARGET_SCHED_ADJUST_PRIORITY
114 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
115 #undef TARGET_SCHED_ISSUE_RATE
116 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
117 #undef TARGET_SCHED_VARIABLE_ISSUE
118 #define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
119 #undef TARGET_SCHED_INIT
120 #define TARGET_SCHED_INIT m32r_sched_init
121 #undef TARGET_SCHED_REORDER
122 #define TARGET_SCHED_REORDER m32r_sched_reorder
124 #undef TARGET_ENCODE_SECTION_INFO
125 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
126 #undef TARGET_IN_SMALL_DATA_P
127 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
129 #undef TARGET_RTX_COSTS
130 #define TARGET_RTX_COSTS m32r_rtx_costs
131 #undef TARGET_ADDRESS_COST
132 #define TARGET_ADDRESS_COST hook_int_rtx_0
134 struct gcc_target targetm
= TARGET_INITIALIZER
;
136 /* Called by OVERRIDE_OPTIONS to initialize various things. */
143 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
144 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
145 m32r_punct_chars
['#'] = 1;
146 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
148 /* Provide default value if not specified. */
150 g_switch_value
= SDATA_DEFAULT_SIZE
;
152 if (strcmp (m32r_model_string
, "small") == 0)
153 m32r_model
= M32R_MODEL_SMALL
;
154 else if (strcmp (m32r_model_string
, "medium") == 0)
155 m32r_model
= M32R_MODEL_MEDIUM
;
156 else if (strcmp (m32r_model_string
, "large") == 0)
157 m32r_model
= M32R_MODEL_LARGE
;
159 error ("bad value (%s) for -mmodel switch", m32r_model_string
);
161 if (strcmp (m32r_sdata_string
, "none") == 0)
162 m32r_sdata
= M32R_SDATA_NONE
;
163 else if (strcmp (m32r_sdata_string
, "sdata") == 0)
164 m32r_sdata
= M32R_SDATA_SDATA
;
165 else if (strcmp (m32r_sdata_string
, "use") == 0)
166 m32r_sdata
= M32R_SDATA_USE
;
168 error ("bad value (%s) for -msdata switch", m32r_sdata_string
);
171 /* Vectors to keep interesting information about registers where it can easily
172 be got. We use to use the actual mode value as the bit number, but there
173 is (or may be) more than 32 modes now. Instead we use two tables: one
174 indexed by hard register number, and one indexed by mode. */
176 /* The purpose of m32r_mode_class is to shrink the range of modes so that
177 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
178 mapped into one m32r_mode_class mode. */
183 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
184 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
187 /* Modes for condition codes. */
188 #define C_MODES (1 << (int) C_MODE)
190 /* Modes for single-word and smaller quantities. */
191 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
193 /* Modes for double-word and smaller quantities. */
194 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
196 /* Modes for quad-word and smaller quantities. */
197 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
199 /* Modes for accumulators. */
200 #define A_MODES (1 << (int) A_MODE)
202 /* Value is 1 if register/mode pair is acceptable on arc. */
204 const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
206 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
207 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
208 S_MODES
, C_MODES
, A_MODES
, A_MODES
211 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
213 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
220 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
222 switch (GET_MODE_CLASS (i
))
225 case MODE_PARTIAL_INT
:
226 case MODE_COMPLEX_INT
:
227 if (GET_MODE_SIZE (i
) <= 4)
228 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
229 else if (GET_MODE_SIZE (i
) == 8)
230 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
231 else if (GET_MODE_SIZE (i
) == 16)
232 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
233 else if (GET_MODE_SIZE (i
) == 32)
234 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
236 m32r_mode_class
[i
] = 0;
239 case MODE_COMPLEX_FLOAT
:
240 if (GET_MODE_SIZE (i
) <= 4)
241 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
242 else if (GET_MODE_SIZE (i
) == 8)
243 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
244 else if (GET_MODE_SIZE (i
) == 16)
245 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
246 else if (GET_MODE_SIZE (i
) == 32)
247 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
249 m32r_mode_class
[i
] = 0;
253 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
254 we must explicitly check for them here. */
255 if (i
== (int) CCmode
)
256 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
258 m32r_mode_class
[i
] = 0;
263 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
266 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
267 else if (i
== ARG_POINTER_REGNUM
)
268 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
270 m32r_regno_reg_class
[i
] = NO_REGS
;
274 /* M32R specific attribute support.
276 interrupt - for interrupt functions
278 model - select code model used to access object
280 small: addresses use 24 bits, use bl to make calls
281 medium: addresses use 32 bits, use bl to make calls
282 large: addresses use 32 bits, use seth/add3/jl to make calls
284 Grep for MODEL in m32r.h for more info.
287 static tree small_ident1
;
288 static tree small_ident2
;
289 static tree medium_ident1
;
290 static tree medium_ident2
;
291 static tree large_ident1
;
292 static tree large_ident2
;
297 if (small_ident1
== 0)
299 small_ident1
= get_identifier ("small");
300 small_ident2
= get_identifier ("__small__");
301 medium_ident1
= get_identifier ("medium");
302 medium_ident2
= get_identifier ("__medium__");
303 large_ident1
= get_identifier ("large");
304 large_ident2
= get_identifier ("__large__");
308 const struct attribute_spec m32r_attribute_table
[] =
310 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
311 { "interrupt", 0, 0, true, false, false, NULL
},
312 { "model", 1, 1, true, false, false, m32r_handle_model_attribute
},
313 { NULL
, 0, 0, false, false, false, NULL
}
317 /* Handle an "model" attribute; arguments as in
318 struct attribute_spec.handler. */
320 m32r_handle_model_attribute (node
, name
, args
, flags
, no_add_attrs
)
321 tree
*node ATTRIBUTE_UNUSED
;
324 int flags ATTRIBUTE_UNUSED
;
330 arg
= TREE_VALUE (args
);
332 if (arg
!= small_ident1
333 && arg
!= small_ident2
334 && arg
!= medium_ident1
335 && arg
!= medium_ident2
336 && arg
!= large_ident1
337 && arg
!= large_ident2
)
339 warning ("invalid argument of `%s' attribute",
340 IDENTIFIER_POINTER (name
));
341 *no_add_attrs
= true;
347 /* Encode section information of DECL, which is either a VAR_DECL,
348 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
350 For the M32R we want to record:
352 - whether the object lives in .sdata/.sbss.
353 - what code model should be used to access the object
357 m32r_encode_section_info (decl
, rtl
, first
)
364 enum m32r_model model
;
366 default_encode_section_info (decl
, rtl
, first
);
371 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
378 id
= TREE_VALUE (TREE_VALUE (model_attr
));
380 if (id
== small_ident1
|| id
== small_ident2
)
381 model
= M32R_MODEL_SMALL
;
382 else if (id
== medium_ident1
|| id
== medium_ident2
)
383 model
= M32R_MODEL_MEDIUM
;
384 else if (id
== large_ident1
|| id
== large_ident2
)
385 model
= M32R_MODEL_LARGE
;
387 abort (); /* shouldn't happen */
391 if (TARGET_MODEL_SMALL
)
392 model
= M32R_MODEL_SMALL
;
393 else if (TARGET_MODEL_MEDIUM
)
394 model
= M32R_MODEL_MEDIUM
;
395 else if (TARGET_MODEL_LARGE
)
396 model
= M32R_MODEL_LARGE
;
398 abort (); /* shouldn't happen */
400 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
403 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
406 /* Only mark the object as being small data area addressable if
407 it hasn't been explicitly marked with a code model.
409 The user can explicitly put an object in the small data area with the
410 section attribute. If the object is in sdata/sbss and marked with a
411 code model do both [put the object in .sdata and mark it as being
412 addressed with a specific code model - don't mark it as being addressed
413 with an SDA reloc though]. This is ok and might be useful at times. If
414 the object doesn't fit the linker will give an error. */
417 m32r_in_small_data_p (decl
)
422 if (TREE_CODE (decl
) != VAR_DECL
)
425 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl
)))
428 section
= DECL_SECTION_NAME (decl
);
431 char *name
= (char *) TREE_STRING_POINTER (section
);
432 if (strcmp (name
, ".sdata") == 0 || strcmp (name
, ".sbss") == 0)
437 if (! TREE_READONLY (decl
) && ! TARGET_SDATA_NONE
)
439 int size
= int_size_in_bytes (TREE_TYPE (decl
));
441 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
449 /* Do anything needed before RTL is emitted for each function. */
452 m32r_init_expanders ()
454 /* ??? At one point there was code here. The function is left in
455 to make it easy to experiment. */
458 /* Acceptable arguments to the call insn. */
461 call_address_operand (op
, mode
)
463 enum machine_mode mode
;
465 return symbolic_operand (op
, mode
);
467 /* Constants and values in registers are not OK, because
468 the m32r BL instruction can only support PC relative branching. */
472 call_operand (op
, mode
)
474 enum machine_mode mode
;
476 if (GET_CODE (op
) != MEM
)
479 return call_address_operand (op
, mode
);
482 /* Returns 1 if OP is a symbol reference. */
485 symbolic_operand (op
, mode
)
487 enum machine_mode mode ATTRIBUTE_UNUSED
;
489 switch (GET_CODE (op
))
501 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
504 small_data_operand (op
, mode
)
506 enum machine_mode mode ATTRIBUTE_UNUSED
;
508 if (! TARGET_SDATA_USE
)
511 if (GET_CODE (op
) == SYMBOL_REF
)
512 return SYMBOL_REF_SMALL_P (op
);
514 if (GET_CODE (op
) == CONST
515 && GET_CODE (XEXP (op
, 0)) == PLUS
516 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
517 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
518 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
519 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op
, 0), 0));
524 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
527 addr24_operand (op
, mode
)
529 enum machine_mode mode ATTRIBUTE_UNUSED
;
533 if (GET_CODE (op
) == LABEL_REF
)
534 return TARGET_ADDR24
;
536 if (GET_CODE (op
) == SYMBOL_REF
)
538 else if (GET_CODE (op
) == CONST
539 && GET_CODE (XEXP (op
, 0)) == PLUS
540 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
541 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
542 && UINT24_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
543 sym
= XEXP (XEXP (op
, 0), 0);
547 if (SYMBOL_REF_MODEL (sym
) == M32R_MODEL_SMALL
)
551 && (CONSTANT_POOL_ADDRESS_P (sym
)
552 || LIT_NAME_P (XSTR (sym
, 0))))
558 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
561 addr32_operand (op
, mode
)
563 enum machine_mode mode
;
567 if (GET_CODE (op
) == LABEL_REF
)
568 return TARGET_ADDR32
;
570 if (GET_CODE (op
) == SYMBOL_REF
)
572 else if (GET_CODE (op
) == CONST
573 && GET_CODE (XEXP (op
, 0)) == PLUS
574 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
575 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
576 sym
= XEXP (XEXP (op
, 0), 0);
580 return (! addr24_operand (sym
, mode
)
581 && ! small_data_operand (sym
, mode
));
584 /* Return 1 if OP is a function that can be called with the `bl' insn. */
587 call26_operand (op
, mode
)
589 enum machine_mode mode ATTRIBUTE_UNUSED
;
591 if (GET_CODE (op
) == SYMBOL_REF
)
592 return SYMBOL_REF_MODEL (op
) != M32R_MODEL_LARGE
;
594 return TARGET_CALL26
;
597 /* Returns 1 if OP is an acceptable operand for seth/add3. */
600 seth_add3_operand (op
, mode
)
602 enum machine_mode mode ATTRIBUTE_UNUSED
;
604 if (GET_CODE (op
) == SYMBOL_REF
605 || GET_CODE (op
) == LABEL_REF
)
608 if (GET_CODE (op
) == CONST
609 && GET_CODE (XEXP (op
, 0)) == PLUS
610 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
611 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
612 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
618 /* Return true if OP is a signed 8 bit immediate value. */
621 int8_operand (op
, mode
)
623 enum machine_mode mode ATTRIBUTE_UNUSED
;
625 if (GET_CODE (op
) != CONST_INT
)
627 return INT8_P (INTVAL (op
));
630 /* Return true if OP is a signed 16 bit immediate value
631 useful in comparisons. */
634 cmp_int16_operand (op
, mode
)
636 enum machine_mode mode ATTRIBUTE_UNUSED
;
638 if (GET_CODE (op
) != CONST_INT
)
640 return CMP_INT16_P (INTVAL (op
));
643 /* Return true if OP is an unsigned 16 bit immediate value. */
646 uint16_operand (op
, mode
)
648 enum machine_mode mode ATTRIBUTE_UNUSED
;
650 if (GET_CODE (op
) != CONST_INT
)
652 return UINT16_P (INTVAL (op
));
655 /* Return true if OP is a register or signed 16 bit value. */
658 reg_or_int16_operand (op
, mode
)
660 enum machine_mode mode
;
662 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
663 return register_operand (op
, mode
);
664 if (GET_CODE (op
) != CONST_INT
)
666 return INT16_P (INTVAL (op
));
669 /* Return true if OP is a register or an unsigned 16 bit value. */
672 reg_or_uint16_operand (op
, mode
)
674 enum machine_mode mode
;
676 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
677 return register_operand (op
, mode
);
678 if (GET_CODE (op
) != CONST_INT
)
680 return UINT16_P (INTVAL (op
));
683 /* Return true if OP is a register or an integer value that can be
684 used is SEQ/SNE. We can use either XOR of the value or ADD of
685 the negative of the value for the constant. Don't allow 0,
686 because that is special cased. */
689 reg_or_eq_int16_operand (op
, mode
)
691 enum machine_mode mode
;
695 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
696 return register_operand (op
, mode
);
698 if (GET_CODE (op
) != CONST_INT
)
702 return (value
!= 0) && (UINT16_P (value
) || CMP_INT16_P (-value
));
705 /* Return true if OP is a register or signed 16 bit value for compares. */
708 reg_or_cmp_int16_operand (op
, mode
)
710 enum machine_mode mode
;
712 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
713 return register_operand (op
, mode
);
714 if (GET_CODE (op
) != CONST_INT
)
716 return CMP_INT16_P (INTVAL (op
));
719 /* Return true if OP is a register or the constant 0. */
722 reg_or_zero_operand (op
, mode
)
724 enum machine_mode mode
;
726 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
727 return register_operand (op
, mode
);
729 if (GET_CODE (op
) != CONST_INT
)
732 return INTVAL (op
) == 0;
735 /* Return true if OP is a const_int requiring two instructions to load. */
738 two_insn_const_operand (op
, mode
)
740 enum machine_mode mode ATTRIBUTE_UNUSED
;
742 if (GET_CODE (op
) != CONST_INT
)
744 if (INT16_P (INTVAL (op
))
745 || UINT24_P (INTVAL (op
))
746 || UPPER16_P (INTVAL (op
)))
751 /* Return true if OP is an acceptable argument for a single word
755 move_src_operand (op
, mode
)
757 enum machine_mode mode
;
759 switch (GET_CODE (op
))
763 return addr24_operand (op
, mode
);
765 /* ??? We allow more cse opportunities if we only allow constants
766 loadable with one insn, and split the rest into two. The instances
767 where this would help should be rare and the current way is
769 if (HOST_BITS_PER_WIDE_INT
> 32)
771 HOST_WIDE_INT rest
= INTVAL (op
) >> 31;
772 return (rest
== 0 || rest
== -1);
777 return TARGET_ADDR24
;
781 else if (mode
== SImode
)
783 /* Large unsigned constants are represented as const_double's. */
784 unsigned HOST_WIDE_INT low
, high
;
786 low
= CONST_DOUBLE_LOW (op
);
787 high
= CONST_DOUBLE_HIGH (op
);
788 return high
== 0 && low
<= (unsigned) 0xffffffff;
793 return register_operand (op
, mode
);
795 /* (subreg (mem ...) ...) can occur here if the inner part was once a
796 pseudo-reg and is now a stack slot. */
797 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
798 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
800 return register_operand (op
, mode
);
802 if (GET_CODE (XEXP (op
, 0)) == PRE_INC
803 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
)
804 return 0; /* loads can't do pre-{inc,dec} */
805 return address_operand (XEXP (op
, 0), mode
);
811 /* Return true if OP is an acceptable argument for a double word
815 move_double_src_operand (op
, mode
)
817 enum machine_mode mode
;
819 switch (GET_CODE (op
))
825 return register_operand (op
, mode
);
827 /* (subreg (mem ...) ...) can occur here if the inner part was once a
828 pseudo-reg and is now a stack slot. */
829 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
830 return move_double_src_operand (SUBREG_REG (op
), mode
);
832 return register_operand (op
, mode
);
834 /* Disallow auto inc/dec for now. */
835 if (GET_CODE (XEXP (op
, 0)) == PRE_DEC
836 || GET_CODE (XEXP (op
, 0)) == PRE_INC
)
838 return address_operand (XEXP (op
, 0), mode
);
844 /* Return true if OP is an acceptable argument for a move destination. */
847 move_dest_operand (op
, mode
)
849 enum machine_mode mode
;
851 switch (GET_CODE (op
))
854 return register_operand (op
, mode
);
856 /* (subreg (mem ...) ...) can occur here if the inner part was once a
857 pseudo-reg and is now a stack slot. */
858 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
859 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
861 return register_operand (op
, mode
);
863 if (GET_CODE (XEXP (op
, 0)) == POST_INC
)
864 return 0; /* stores can't do post inc */
865 return address_operand (XEXP (op
, 0), mode
);
871 /* Return 1 if OP is a DImode const we want to handle inline.
872 This must match the code in the movdi pattern.
873 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
879 rtx high_rtx
, low_rtx
;
880 HOST_WIDE_INT high
, low
;
882 split_double (op
, &high_rtx
, &low_rtx
);
883 high
= INTVAL (high_rtx
);
884 low
= INTVAL (low_rtx
);
885 /* Pick constants loadable with 2 16 bit `ldi' insns. */
886 if (high
>= -128 && high
<= 127
887 && low
>= -128 && low
<= 127)
892 /* Return 1 if OP is a DFmode const we want to handle inline.
893 This must match the code in the movdf pattern.
894 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
903 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
904 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
905 if (l
[0] == 0 && l
[1] == 0)
907 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
912 /* Return 1 if OP is an EQ or NE comparison operator. */
915 eqne_comparison_operator (op
, mode
)
917 enum machine_mode mode ATTRIBUTE_UNUSED
;
919 enum rtx_code code
= GET_CODE (op
);
921 if (GET_RTX_CLASS (code
) != '<')
923 return (code
== EQ
|| code
== NE
);
926 /* Return 1 if OP is a signed comparison operator. */
929 signed_comparison_operator (op
, mode
)
931 enum machine_mode mode ATTRIBUTE_UNUSED
;
933 enum rtx_code code
= GET_CODE (op
);
935 if (GET_RTX_CLASS (code
) != '<')
937 return (code
== EQ
|| code
== NE
938 || code
== LT
|| code
== LE
|| code
== GT
|| code
== GE
);
941 /* Return 1 if OP is (mem (reg ...)).
942 This is used in insn length calcs. */
945 memreg_operand (op
, mode
)
947 enum machine_mode mode ATTRIBUTE_UNUSED
;
949 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == REG
;
952 /* Return true if OP is an acceptable input argument for a zero/sign extend
956 extend_operand (op
, mode
)
958 enum machine_mode mode
;
962 switch (GET_CODE (op
))
966 return register_operand (op
, mode
);
970 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
971 return 0; /* loads can't do pre inc/pre dec */
973 return address_operand (addr
, mode
);
980 /* Return nonzero if the operand is an insn that is a small insn.
981 Allow const_int 0 as well, which is a placeholder for NOP slots. */
984 small_insn_p (op
, mode
)
986 enum machine_mode mode ATTRIBUTE_UNUSED
;
988 if (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
994 return get_attr_length (op
) == 2;
997 /* Return nonzero if the operand is an insn that is a large insn. */
1000 large_insn_p (op
, mode
)
1002 enum machine_mode mode ATTRIBUTE_UNUSED
;
1007 return get_attr_length (op
) != 2;
1010 /* Return nonzero if TYPE must be passed or returned in memory.
1011 The m32r treats both directions the same so we handle both directions
1012 in this function. */
1015 m32r_pass_by_reference (type
)
1018 int size
= int_size_in_bytes (type
);
1020 if (size
< 0 || size
> 8)
1028 /* X and Y are two things to compare using CODE. Emit the compare insn and
1029 return the rtx for compare [arg0 of the if_then_else].
1030 If need_compare is true then the comparison insn must be generated, rather
1031 than being susummed into the following branch instruction. */
1034 gen_compare (code
, x
, y
, need_compare
)
1039 enum rtx_code compare_code
, branch_code
;
1040 rtx cc_reg
= gen_rtx_REG (CCmode
, CARRY_REGNUM
);
1045 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
1046 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
1047 case LT
: compare_code
= LT
; branch_code
= NE
; break;
1048 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
1049 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
1050 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
1051 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
1052 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
1053 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
1054 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
1062 switch (compare_code
)
1065 if (GET_CODE (y
) == CONST_INT
1066 && CMP_INT16_P (INTVAL (y
)) /* reg equal to small const. */
1069 rtx tmp
= gen_reg_rtx (SImode
);
1071 emit_insn (gen_cmp_ne_small_const_insn (tmp
, x
, y
));
1075 else if (CONSTANT_P (y
)) /* reg equal to const. */
1077 rtx tmp
= force_reg (GET_MODE (x
), y
);
1081 if (register_operand (y
, SImode
) /* reg equal to reg. */
1082 || y
== const0_rtx
) /* req equal to zero. */
1084 emit_insn (gen_cmp_eqsi_insn (x
, y
));
1086 return gen_rtx (code
, CCmode
, cc_reg
, const0_rtx
);
1091 if (register_operand (y
, SImode
)
1092 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
1094 rtx tmp
= gen_reg_rtx (SImode
); /* reg compared to reg. */
1099 emit_insn (gen_cmp_ltsi_insn (x
, y
));
1103 if (y
== const0_rtx
)
1106 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1107 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
1111 if (GET_CODE (y
) == CONST_INT
)
1112 tmp
= gen_rtx (PLUS
, SImode
, y
, const1_rtx
);
1114 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1115 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
1119 emit_insn (gen_cmp_ltsi_insn (x
, y
));
1126 return gen_rtx (code
, CCmode
, cc_reg
, const0_rtx
);
1131 if (register_operand (y
, SImode
)
1132 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
1134 rtx tmp
= gen_reg_rtx (SImode
); /* reg (unsigned) compared to reg. */
1139 emit_insn (gen_cmp_ltusi_insn (x
, y
));
1143 if (y
== const0_rtx
)
1146 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1147 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
1151 if (GET_CODE (y
) == CONST_INT
)
1152 tmp
= gen_rtx (PLUS
, SImode
, y
, const1_rtx
);
1154 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1155 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
1159 emit_insn (gen_cmp_ltusi_insn (x
, y
));
1166 return gen_rtx (code
, CCmode
, cc_reg
, const0_rtx
);
1176 /* reg/reg equal comparison */
1177 if (compare_code
== EQ
1178 && register_operand (y
, SImode
))
1179 return gen_rtx (code
, CCmode
, x
, y
);
1181 /* reg/zero signed comparison */
1182 if ((compare_code
== EQ
|| compare_code
== LT
)
1184 return gen_rtx (code
, CCmode
, x
, y
);
1186 /* reg/smallconst equal comparison */
1187 if (compare_code
== EQ
1188 && GET_CODE (y
) == CONST_INT
1189 && CMP_INT16_P (INTVAL (y
)))
1191 rtx tmp
= gen_reg_rtx (SImode
);
1192 emit_insn (gen_cmp_ne_small_const_insn (tmp
, x
, y
));
1193 return gen_rtx (code
, CCmode
, tmp
, const0_rtx
);
1196 /* reg/const equal comparison */
1197 if (compare_code
== EQ
1200 rtx tmp
= force_reg (GET_MODE (x
), y
);
1201 return gen_rtx (code
, CCmode
, x
, tmp
);
1208 y
= force_reg (GET_MODE (x
), y
);
1212 (code
== LTU
|| code
== LEU
|| code
== GTU
|| code
== GEU
)
1213 ? uint16_operand (y
, GET_MODE (y
))
1214 : reg_or_cmp_int16_operand (y
, GET_MODE (y
));
1217 y
= force_reg (GET_MODE (x
), y
);
1221 switch (compare_code
)
1224 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1227 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1230 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1237 return gen_rtx (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (CCmode
));
1240 /* Split a 2 word move (DI or DF) into component parts. */
1243 gen_split_move_double (operands
)
1246 enum machine_mode mode
= GET_MODE (operands
[0]);
1247 rtx dest
= operands
[0];
1248 rtx src
= operands
[1];
1251 /* We might have (SUBREG (MEM)) here, so just get rid of the
1252 subregs to make this code simpler. It is safe to call
1253 alter_subreg any time after reload. */
1254 if (GET_CODE (dest
) == SUBREG
)
1255 alter_subreg (&dest
);
1256 if (GET_CODE (src
) == SUBREG
)
1257 alter_subreg (&src
);
1260 if (GET_CODE (dest
) == REG
)
1262 int dregno
= REGNO (dest
);
1265 if (GET_CODE (src
) == REG
)
1267 int sregno
= REGNO (src
);
1269 int reverse
= (dregno
== sregno
+ 1);
1271 /* We normally copy the low-numbered register first. However, if
1272 the first register operand 0 is the same as the second register of
1273 operand 1, we must copy in the opposite order. */
1274 emit_insn (gen_rtx_SET (VOIDmode
,
1275 operand_subword (dest
, reverse
, TRUE
, mode
),
1276 operand_subword (src
, reverse
, TRUE
, mode
)));
1278 emit_insn (gen_rtx_SET (VOIDmode
,
1279 operand_subword (dest
, !reverse
, TRUE
, mode
),
1280 operand_subword (src
, !reverse
, TRUE
, mode
)));
1283 /* reg = constant */
1284 else if (GET_CODE (src
) == CONST_INT
|| GET_CODE (src
) == CONST_DOUBLE
)
1287 split_double (src
, &words
[0], &words
[1]);
1288 emit_insn (gen_rtx_SET (VOIDmode
,
1289 operand_subword (dest
, 0, TRUE
, mode
),
1292 emit_insn (gen_rtx_SET (VOIDmode
,
1293 operand_subword (dest
, 1, TRUE
, mode
),
1298 else if (GET_CODE (src
) == MEM
)
1300 /* If the high-address word is used in the address, we must load it
1301 last. Otherwise, load it first. */
1303 = (refers_to_regno_p (dregno
, dregno
+ 1, XEXP (src
, 0), 0) != 0);
1305 /* We used to optimize loads from single registers as
1309 if r3 were not used subsequently. However, the REG_NOTES aren't
1310 propigated correctly by the reload phase, and it can cause bad
1311 code to be generated. We could still try:
1313 ld r1,r3+; ld r2,r3; addi r3,-4
1315 which saves 2 bytes and doesn't force longword alignment. */
1316 emit_insn (gen_rtx_SET (VOIDmode
,
1317 operand_subword (dest
, reverse
, TRUE
, mode
),
1318 adjust_address (src
, SImode
,
1319 reverse
* UNITS_PER_WORD
)));
1321 emit_insn (gen_rtx_SET (VOIDmode
,
1322 operand_subword (dest
, !reverse
, TRUE
, mode
),
1323 adjust_address (src
, SImode
,
1324 !reverse
* UNITS_PER_WORD
)));
1332 /* We used to optimize loads from single registers as
1336 if r3 were not used subsequently. However, the REG_NOTES aren't
1337 propigated correctly by the reload phase, and it can cause bad
1338 code to be generated. We could still try:
1340 st r1,r3; st r2,+r3; addi r3,-4
1342 which saves 2 bytes and doesn't force longword alignment. */
1343 else if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
1345 emit_insn (gen_rtx_SET (VOIDmode
,
1346 adjust_address (dest
, SImode
, 0),
1347 operand_subword (src
, 0, TRUE
, mode
)));
1349 emit_insn (gen_rtx_SET (VOIDmode
,
1350 adjust_address (dest
, SImode
, UNITS_PER_WORD
),
1351 operand_subword (src
, 1, TRUE
, mode
)));
1363 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1366 function_arg_partial_nregs (cum
, mode
, type
, named
)
1367 CUMULATIVE_ARGS
*cum
;
1368 enum machine_mode mode
;
1370 int named ATTRIBUTE_UNUSED
;
1374 (((mode
== BLKmode
&& type
)
1375 ? (unsigned int) int_size_in_bytes (type
)
1376 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
1379 if (*cum
>= M32R_MAX_PARM_REGS
)
1381 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1382 ret
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1389 /* Do any needed setup for a variadic function. For the M32R, we must
1390 create a register parameter block, and then copy any anonymous arguments
1391 in registers to memory.
1393 CUM has not been updated for the last named argument which has type TYPE
1394 and mode MODE, and we rely on this fact. */
1397 m32r_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
1398 CUMULATIVE_ARGS
*cum
;
1399 enum machine_mode mode
;
1409 /* All BLKmode values are passed by reference. */
1410 if (mode
== BLKmode
)
1413 first_anon_arg
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1414 + ROUND_ADVANCE_ARG (mode
, type
));
1416 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1418 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1419 int first_reg_offset
= first_anon_arg
;
1420 /* Size in words to "pretend" allocate. */
1421 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1424 regblock
= gen_rtx_MEM (BLKmode
,
1425 plus_constant (arg_pointer_rtx
,
1426 FIRST_PARM_OFFSET (0)));
1427 set_mem_alias_set (regblock
, get_varargs_alias_set ());
1428 move_block_from_reg (first_reg_offset
, regblock
, size
);
1430 *pretend_size
= (size
* UNITS_PER_WORD
);
1435 /* Implement `va_arg'. */
1438 m32r_va_arg (valist
, type
)
1441 HOST_WIDE_INT size
, rsize
;
1445 size
= int_size_in_bytes (type
);
1446 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
1448 if (m32r_pass_by_reference (type
))
1450 tree type_ptr
, type_ptr_ptr
;
1452 /* Pass by reference. */
1454 type_ptr
= build_pointer_type (type
);
1455 type_ptr_ptr
= build_pointer_type (type_ptr
);
1457 t
= build (POSTINCREMENT_EXPR
, va_list_type_node
, valist
,
1458 build_int_2 (UNITS_PER_WORD
, 0));
1459 TREE_SIDE_EFFECTS (t
) = 1;
1460 t
= build1 (NOP_EXPR
, type_ptr_ptr
, t
);
1461 TREE_SIDE_EFFECTS (t
) = 1;
1462 t
= build1 (INDIRECT_REF
, type_ptr
, t
);
1464 addr_rtx
= expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1468 /* Pass by value. */
1470 if (size
< UNITS_PER_WORD
)
1472 /* Care for bigendian correction on the aligned address. */
1473 t
= build (PLUS_EXPR
, ptr_type_node
, valist
,
1474 build_int_2 (rsize
- size
, 0));
1475 addr_rtx
= expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1476 addr_rtx
= copy_to_reg (addr_rtx
);
1479 t
= build (PLUS_EXPR
, va_list_type_node
, valist
,
1480 build_int_2 (rsize
, 0));
1481 t
= build (MODIFY_EXPR
, va_list_type_node
, valist
, t
);
1482 TREE_SIDE_EFFECTS (t
) = 1;
1483 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
1487 t
= build (POSTINCREMENT_EXPR
, va_list_type_node
, valist
,
1488 build_int_2 (rsize
, 0));
1489 TREE_SIDE_EFFECTS (t
) = 1;
1490 addr_rtx
= expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1498 m32r_adjust_cost (insn
, link
, dep_insn
, cost
)
1499 rtx insn ATTRIBUTE_UNUSED
;
1500 rtx link ATTRIBUTE_UNUSED
;
1501 rtx dep_insn ATTRIBUTE_UNUSED
;
1508 /* Return true if INSN is real instruction bearing insn. */
1514 return (INSN_P (insn
)
1515 && GET_CODE (PATTERN (insn
)) != USE
1516 && GET_CODE (PATTERN (insn
)) != CLOBBER
1517 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
);
1520 /* Increase the priority of long instructions so that the
1521 short instructions are scheduled ahead of the long ones. */
1524 m32r_adjust_priority (insn
, priority
)
1528 if (m32r_is_insn (insn
)
1529 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1536 /* Initialize for scheduling a group of instructions. */
1539 m32r_sched_init (stream
, verbose
, max_ready
)
1540 FILE * stream ATTRIBUTE_UNUSED
;
1541 int verbose ATTRIBUTE_UNUSED
;
1542 int max_ready ATTRIBUTE_UNUSED
;
1544 m32r_sched_odd_word_p
= FALSE
;
1548 /* Reorder the schedulers priority list if needed */
1551 m32r_sched_reorder (stream
, verbose
, ready
, n_readyp
, clock
)
1556 int clock ATTRIBUTE_UNUSED
;
1558 int n_ready
= *n_readyp
;
1561 return m32r_issue_rate ();
1568 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1570 (m32r_sched_odd_word_p
) ? "odd" : "even");
1574 rtx
* long_head
= (rtx
*) alloca (sizeof (rtx
) * n_ready
);
1575 rtx
* long_tail
= long_head
;
1576 rtx
* short_head
= (rtx
*) alloca (sizeof (rtx
) * n_ready
);
1577 rtx
* short_tail
= short_head
;
1578 rtx
* new_head
= (rtx
*) alloca (sizeof (rtx
) * n_ready
);
1579 rtx
* new_tail
= new_head
+ (n_ready
- 1);
1582 /* Loop through the instructions, classifing them as short/long. Try
1583 to keep 2 short together and/or 1 long. Note, the ready list is
1584 actually ordered backwards, so keep it in that manner. */
1585 for (i
= n_ready
-1; i
>= 0; i
--)
1587 rtx insn
= ready
[i
];
1589 if (! m32r_is_insn (insn
))
1591 /* Dump all current short/long insns just in case. */
1592 while (long_head
!= long_tail
)
1593 *new_tail
-- = *long_head
++;
1595 while (short_head
!= short_tail
)
1596 *new_tail
-- = *short_head
++;
1601 ";;\t\t::: Skipping non instruction %d\n",
1608 if (get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1609 *long_tail
++ = insn
;
1612 *short_tail
++ = insn
;
1616 /* If we are on an odd word, emit a single short instruction if
1618 if (m32r_sched_odd_word_p
&& short_head
!= short_tail
)
1619 *new_tail
-- = *short_head
++;
1621 /* Now dump out all of the long instructions */
1622 while (long_head
!= long_tail
)
1623 *new_tail
-- = *long_head
++;
1625 /* Now dump out all of the short instructions */
1626 while (short_head
!= short_tail
)
1627 *new_tail
-- = *short_head
++;
1629 if (new_tail
+1 != new_head
)
1632 memcpy (ready
, new_head
, sizeof (rtx
) * n_ready
);
1636 fprintf (stream
, ";;\t\t::: New ready list: ");
1637 for (i
= 0; i
< n_ready
; i
++)
1639 rtx insn
= ready
[i
];
1641 fprintf (stream
, " %d", INSN_UID (ready
[i
]));
1643 if (! m32r_is_insn (insn
))
1644 fputs ("(?)", stream
);
1646 else if (get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1647 fputs ("(l)", stream
);
1650 fputs ("(s)", stream
);
1653 fprintf (stream
, "\n");
1656 return m32r_issue_rate ();
1659 /* Indicate how many instructions can be issued at the same time.
1660 This is sort of a lie. The m32r can issue only 1 long insn at
1661 once, but it can issue 2 short insns. The default therefore is
1662 set at 2, but this can be overridden by the command line option
1667 return ((TARGET_LOW_ISSUE_RATE
) ? 1 : 2);
1670 /* If we have a machine that can issue a variable # of instructions
1671 per cycle, indicate how many more instructions can be issued
1672 after the current one. */
1674 m32r_variable_issue (stream
, verbose
, insn
, how_many
)
1680 int orig_odd_word_p
= m32r_sched_odd_word_p
;
1681 int short_p
= FALSE
;
1684 if (how_many
> 0 && !TARGET_DEBUG
)
1686 if (! m32r_is_insn (insn
))
1689 else if (get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1692 m32r_sched_odd_word_p
= 0;
1696 m32r_sched_odd_word_p
= !m32r_sched_odd_word_p
;
1701 if (verbose
> 7 && stream
)
1703 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1704 short_p
? "short" : "long",
1706 orig_odd_word_p
? "odd" : "even",
1712 /* Cost functions. */
1715 m32r_rtx_costs (x
, code
, outer_code
, total
)
1717 int code
, outer_code ATTRIBUTE_UNUSED
;
1722 /* Small integers are as cheap as registers. 4 byte values can be
1723 fetched as immediate constants - let's give that the cost of an
1726 if (INT16_P (INTVAL (x
)))
1736 *total
= COSTS_N_INSNS (1);
1742 split_double (x
, &high
, &low
);
1743 *total
= COSTS_N_INSNS (!INT16_P (INTVAL (high
))
1744 + !INT16_P (INTVAL (low
)));
1749 *total
= COSTS_N_INSNS (3);
1756 *total
= COSTS_N_INSNS (10);
1764 /* Type of function DECL.
1766 The result is cached. To reset the cache at the end of a function,
1767 call with DECL = NULL_TREE. */
1769 enum m32r_function_type
1770 m32r_compute_function_type (decl
)
1774 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1775 /* Last function we were called for. */
1776 static tree last_fn
= NULL_TREE
;
1778 /* Resetting the cached value? */
1779 if (decl
== NULL_TREE
)
1781 fn_type
= M32R_FUNCTION_UNKNOWN
;
1782 last_fn
= NULL_TREE
;
1786 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1789 /* Compute function type. */
1790 fn_type
= (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1791 ? M32R_FUNCTION_INTERRUPT
1792 : M32R_FUNCTION_NORMAL
);
1797 \f/* Function prologue/epilogue handlers. */
1799 /* M32R stack frames look like:
1801 Before call After call
1802 +-----------------------+ +-----------------------+
1804 high | local variables, | | local variables, |
1805 mem | reg save area, etc. | | reg save area, etc. |
1807 +-----------------------+ +-----------------------+
1809 | arguments on stack. | | arguments on stack. |
1811 SP+0->+-----------------------+ +-----------------------+
1812 | reg parm save area, |
1813 | only created for |
1814 | variable argument |
1816 +-----------------------+
1817 | previous frame ptr |
1818 +-----------------------+
1820 | register save area |
1822 +-----------------------+
1824 +-----------------------+
1828 +-----------------------+
1830 | alloca allocations |
1832 +-----------------------+
1834 low | arguments on stack |
1836 SP+0->+-----------------------+
1839 1) The "reg parm save area" does not exist for non variable argument fns.
1840 2) The "reg parm save area" can be eliminated completely if we saved regs
1841 containing anonymous args separately but that complicates things too
1842 much (so it's not done).
1843 3) The return address is saved after the register save area so as to have as
1844 many insns as possible between the restoration of `lr' and the `jmp lr'.
1847 /* Structure to be filled in by m32r_compute_frame_size with register
1848 save masks, and offsets for the current function. */
1849 struct m32r_frame_info
1851 unsigned int total_size
; /* # bytes that the entire frame takes up */
1852 unsigned int extra_size
; /* # bytes of extra stuff */
1853 unsigned int pretend_size
; /* # bytes we push and pretend caller did */
1854 unsigned int args_size
; /* # bytes that outgoing arguments take up */
1855 unsigned int reg_size
; /* # bytes needed to store regs */
1856 unsigned int var_size
; /* # bytes that variables take up */
1857 unsigned int gmask
; /* mask of saved gp registers */
1858 unsigned int save_fp
; /* nonzero if fp must be saved */
1859 unsigned int save_lr
; /* nonzero if lr (return addr) must be saved */
1860 int initialized
; /* nonzero if frame size already calculated */
1863 /* Current frame information calculated by m32r_compute_frame_size. */
1864 static struct m32r_frame_info current_frame_info
;
1866 /* Zero structure to initialize current_frame_info. */
1867 static struct m32r_frame_info zero_frame_info
;
1869 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1870 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1872 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1873 The return address and frame pointer are treated separately.
1874 Don't consider them here. */
1875 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1876 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1877 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1879 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1880 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1882 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1883 #define LONG_INSN_SIZE 4 /* size of long instructions */
1885 /* Return the bytes needed to compute the frame pointer from the current
1888 SIZE is the size needed for local variables. */
1891 m32r_compute_frame_size (size
)
1892 int size
; /* # of var. bytes allocated. */
1895 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1896 unsigned int reg_size
, frame_size
;
1898 enum m32r_function_type fn_type
;
1901 var_size
= M32R_STACK_ALIGN (size
);
1902 args_size
= M32R_STACK_ALIGN (current_function_outgoing_args_size
);
1903 pretend_size
= current_function_pretend_args_size
;
1904 extra_size
= FIRST_PARM_OFFSET (0);
1905 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1909 /* See if this is an interrupt handler. Call used registers must be saved
1911 fn_type
= m32r_compute_function_type (current_function_decl
);
1912 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1914 /* Calculate space needed for registers. */
1916 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1918 if (MUST_SAVE_REGISTER (regno
, interrupt_p
))
1920 reg_size
+= UNITS_PER_WORD
;
1921 gmask
|= 1 << regno
;
1925 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1926 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
;
1928 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1930 total_size
+= reg_size
;
1932 /* ??? Not sure this is necessary, and I don't think the epilogue
1933 handler will do the right thing if this changes total_size. */
1934 total_size
= M32R_STACK_ALIGN (total_size
);
1936 frame_size
= total_size
- (pretend_size
+ reg_size
);
1938 /* Save computed information. */
1939 current_frame_info
.total_size
= total_size
;
1940 current_frame_info
.extra_size
= extra_size
;
1941 current_frame_info
.pretend_size
= pretend_size
;
1942 current_frame_info
.var_size
= var_size
;
1943 current_frame_info
.args_size
= args_size
;
1944 current_frame_info
.reg_size
= reg_size
;
1945 current_frame_info
.gmask
= gmask
;
1946 current_frame_info
.initialized
= reload_completed
;
1948 /* Ok, we're done. */
1952 /* When the `length' insn attribute is used, this macro specifies the
1953 value to be assigned to the address of the first insn in a
1954 function. If not specified, 0 is used. */
1957 m32r_first_insn_address ()
1959 if (! current_frame_info
.initialized
)
1960 m32r_compute_frame_size (get_frame_size ());
1965 /* Expand the m32r prologue as a series of insns. */
1968 m32r_expand_prologue ()
1974 if (! current_frame_info
.initialized
)
1975 m32r_compute_frame_size (get_frame_size ());
1977 gmask
= current_frame_info
.gmask
;
1979 /* These cases shouldn't happen. Catch them now. */
1980 if (current_frame_info
.total_size
== 0 && gmask
)
1983 /* Allocate space for register arguments if this is a variadic function. */
1984 if (current_frame_info
.pretend_size
!= 0)
1986 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1987 the wrong result on a 64-bit host. */
1988 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1989 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1991 GEN_INT (-pretend_size
)));
1994 /* Save any registers we need to and set up fp. */
1996 if (current_frame_info
.save_fp
)
1997 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
1999 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
2001 /* Save any needed call-saved regs (and call-used if this is an
2002 interrupt handler). */
2003 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
2005 if ((gmask
& (1 << regno
)) != 0)
2006 emit_insn (gen_movsi_push (stack_pointer_rtx
,
2007 gen_rtx_REG (Pmode
, regno
)));
2010 if (current_frame_info
.save_lr
)
2011 emit_insn (gen_movsi_push (stack_pointer_rtx
,
2012 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
2014 /* Allocate the stack frame. */
2015 frame_size
= (current_frame_info
.total_size
2016 - (current_frame_info
.pretend_size
2017 + current_frame_info
.reg_size
));
2019 if (frame_size
== 0)
2020 ; /* nothing to do */
2021 else if (frame_size
<= 32768)
2022 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2023 GEN_INT (-frame_size
)));
2026 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
2027 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
2028 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
2031 if (frame_pointer_needed
)
2032 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2034 if (current_function_profile
)
2035 emit_insn (gen_blockage ());
2039 /* Set up the stack and frame pointer (if desired) for the function.
2040 Note, if this is changed, you need to mirror the changes in
2041 m32r_compute_frame_size which calculates the prolog size. */
2044 m32r_output_function_prologue (file
, size
)
2048 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
2050 /* If this is an interrupt handler, mark it as such. */
2051 if (M32R_INTERRUPT_P (fn_type
))
2053 fprintf (file
, "\t%s interrupt handler\n",
2057 if (! current_frame_info
.initialized
)
2058 m32r_compute_frame_size (size
);
2060 /* This is only for the human reader. */
2062 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2064 current_frame_info
.var_size
,
2065 current_frame_info
.reg_size
/ 4,
2066 current_frame_info
.args_size
,
2067 current_frame_info
.extra_size
);
2070 /* Do any necessary cleanup after a function to restore stack, frame,
2074 m32r_output_function_epilogue (file
, size
)
2076 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
2079 int noepilogue
= FALSE
;
2081 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
2083 /* This is only for the human reader. */
2084 fprintf (file
, "\t%s EPILOGUE\n", ASM_COMMENT_START
);
2086 if (!current_frame_info
.initialized
)
2088 total_size
= current_frame_info
.total_size
;
2090 if (total_size
== 0)
2092 rtx insn
= get_last_insn ();
2094 /* If the last insn was a BARRIER, we don't have to write any code
2095 because a jump (aka return) was put there. */
2096 if (GET_CODE (insn
) == NOTE
)
2097 insn
= prev_nonnote_insn (insn
);
2098 if (insn
&& GET_CODE (insn
) == BARRIER
)
2104 unsigned int var_size
= current_frame_info
.var_size
;
2105 unsigned int args_size
= current_frame_info
.args_size
;
2106 unsigned int gmask
= current_frame_info
.gmask
;
2107 int can_trust_sp_p
= !current_function_calls_alloca
;
2108 const char * sp_str
= reg_names
[STACK_POINTER_REGNUM
];
2109 const char * fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
2111 /* The first thing to do is point the sp at the bottom of the register
2115 unsigned int reg_offset
= var_size
+ args_size
;
2116 if (reg_offset
== 0)
2117 ; /* nothing to do */
2118 else if (reg_offset
< 128)
2119 fprintf (file
, "\taddi %s,%s%d\n",
2120 sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
2121 else if (reg_offset
< 32768)
2122 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
2123 sp_str
, sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
2125 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2126 reg_names
[PROLOGUE_TMP_REGNUM
],
2127 IMMEDIATE_PREFIX
, reg_offset
,
2128 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
2130 else if (frame_pointer_needed
)
2132 unsigned int reg_offset
= var_size
+ args_size
;
2133 if (reg_offset
== 0)
2134 fprintf (file
, "\tmv %s,%s\n", sp_str
, fp_str
);
2135 else if (reg_offset
< 32768)
2136 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
2137 sp_str
, fp_str
, IMMEDIATE_PREFIX
, reg_offset
);
2139 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2140 reg_names
[PROLOGUE_TMP_REGNUM
],
2141 IMMEDIATE_PREFIX
, reg_offset
,
2142 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
2147 if (current_frame_info
.save_lr
)
2148 fprintf (file
, "\tpop %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
2150 /* Restore any saved registers, in reverse order of course. */
2151 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
2152 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
2154 if ((gmask
& (1L << regno
)) != 0)
2155 fprintf (file
, "\tpop %s\n", reg_names
[regno
]);
2158 if (current_frame_info
.save_fp
)
2159 fprintf (file
, "\tpop %s\n", fp_str
);
2161 /* Remove varargs area if present. */
2162 if (current_frame_info
.pretend_size
!= 0)
2163 fprintf (file
, "\taddi %s,%s%d\n",
2164 sp_str
, IMMEDIATE_PREFIX
, current_frame_info
.pretend_size
);
2166 /* Emit the return instruction. */
2167 if (M32R_INTERRUPT_P (fn_type
))
2168 fprintf (file
, "\trte\n");
2170 fprintf (file
, "\tjmp %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
2173 #if 0 /* no longer needed */
2174 /* Ensure the function cleanly ends on a 32 bit boundary. */
2175 fprintf (file
, "\t.fillinsn\n");
2178 /* Reset state info for each function. */
2179 current_frame_info
= zero_frame_info
;
2180 m32r_compute_function_type (NULL_TREE
);
2183 /* Return nonzero if this function is known to have a null or 1 instruction
2189 if (!reload_completed
)
2192 if (! current_frame_info
.initialized
)
2193 m32r_compute_frame_size (get_frame_size ());
2195 return current_frame_info
.total_size
== 0;
2201 /* Emit special PIC prologues and epilogues. */
2204 m32r_finalize_pic ()
2209 /* Nested function support. */
2211 /* Emit RTL insns to initialize the variable parts of a trampoline.
2212 FNADDR is an RTX for the address of the function's pure code.
2213 CXT is an RTX for the static chain value for the function. */
2216 m32r_initialize_trampoline (tramp
, fnaddr
, cxt
)
2217 rtx tramp ATTRIBUTE_UNUSED
;
2218 rtx fnaddr ATTRIBUTE_UNUSED
;
2219 rtx cxt ATTRIBUTE_UNUSED
;
2226 default_file_start ();
2228 if (flag_verbose_asm
)
2229 fprintf (asm_out_file
,
2230 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
2231 ASM_COMMENT_START
, g_switch_value
);
2234 /* Print operand X (an rtx) in assembler syntax to file FILE.
2235 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2236 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2239 m32r_print_operand (file
, x
, code
)
2248 /* The 's' and 'p' codes are used by output_block_move() to
2249 indicate post-increment 's'tores and 'p're-increment loads. */
2251 if (GET_CODE (x
) == REG
)
2252 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
2254 output_operand_lossage ("invalid operand to %%s code");
2258 if (GET_CODE (x
) == REG
)
2259 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
2261 output_operand_lossage ("invalid operand to %%p code");
2265 /* Write second word of DImode or DFmode reference,
2266 register or memory. */
2267 if (GET_CODE (x
) == REG
)
2268 fputs (reg_names
[REGNO (x
)+1], file
);
2269 else if (GET_CODE (x
) == MEM
)
2271 fprintf (file
, "@(");
2272 /* Handle possible auto-increment. Since it is pre-increment and
2273 we have already done it, we can just use an offset of four. */
2274 /* ??? This is taken from rs6000.c I think. I don't think it is
2275 currently necessary, but keep it around. */
2276 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2277 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2278 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 4));
2280 output_address (plus_constant (XEXP (x
, 0), 4));
2284 output_operand_lossage ("invalid operand to %%R code");
2287 case 'H' : /* High word */
2288 case 'L' : /* Low word */
2289 if (GET_CODE (x
) == REG
)
2291 /* L = least significant word, H = most significant word */
2292 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
2293 fputs (reg_names
[REGNO (x
)], file
);
2295 fputs (reg_names
[REGNO (x
)+1], file
);
2297 else if (GET_CODE (x
) == CONST_INT
2298 || GET_CODE (x
) == CONST_DOUBLE
)
2302 split_double (x
, &first
, &second
);
2303 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2304 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
2307 output_operand_lossage ("invalid operand to %%H/%%L code");
2314 if (GET_CODE (x
) != CONST_DOUBLE
2315 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
2316 fatal_insn ("bad insn for 'A'", x
);
2318 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
2319 fprintf (file
, "%s", str
);
2323 case 'B' : /* Bottom half */
2324 case 'T' : /* Top half */
2325 /* Output the argument to a `seth' insn (sets the Top half-word).
2326 For constants output arguments to a seth/or3 pair to set Top and
2327 Bottom halves. For symbols output arguments to a seth/add3 pair to
2328 set Top and Bottom halves. The difference exists because for
2329 constants seth/or3 is more readable but for symbols we need to use
2330 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2331 switch (GET_CODE (x
))
2338 split_double (x
, &first
, &second
);
2339 x
= WORDS_BIG_ENDIAN
? second
: first
;
2340 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2342 ? INTVAL (x
) & 0xffff
2343 : (INTVAL (x
) >> 16) & 0xffff));
2349 && small_data_operand (x
, VOIDmode
))
2351 fputs ("sda(", file
);
2352 output_addr_const (file
, x
);
2358 fputs (code
== 'T' ? "shigh(" : "low(", file
);
2359 output_addr_const (file
, x
);
2363 output_operand_lossage ("invalid operand to %%T/%%B code");
2370 /* Output a load/store with update indicator if appropriate. */
2371 if (GET_CODE (x
) == MEM
)
2373 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2374 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2378 output_operand_lossage ("invalid operand to %%U code");
2382 /* Print a constant value negated. */
2383 if (GET_CODE (x
) == CONST_INT
)
2384 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
2386 output_operand_lossage ("invalid operand to %%N code");
2390 /* Print a const_int in hex. Used in comments. */
2391 if (GET_CODE (x
) == CONST_INT
)
2392 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
2396 fputs (IMMEDIATE_PREFIX
, file
);
2399 #if 0 /* ??? no longer used */
2401 fputs (reg_names
[SDA_REGNUM
], file
);
2406 /* Do nothing special. */
2411 output_operand_lossage ("invalid operand output code");
2414 switch (GET_CODE (x
))
2417 fputs (reg_names
[REGNO (x
)], file
);
2422 if (GET_CODE (addr
) == PRE_INC
)
2424 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2425 fatal_insn ("pre-increment address is not a register", x
);
2427 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2429 else if (GET_CODE (addr
) == PRE_DEC
)
2431 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2432 fatal_insn ("pre-decrement address is not a register", x
);
2434 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2436 else if (GET_CODE (addr
) == POST_INC
)
2438 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2439 fatal_insn ("post-increment address is not a register", x
);
2441 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2446 output_address (XEXP (x
, 0));
2452 /* We handle SFmode constants here as output_addr_const doesn't. */
2453 if (GET_MODE (x
) == SFmode
)
2458 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2459 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
2460 fprintf (file
, "0x%08lx", l
);
2464 /* Fall through. Let output_addr_const deal with it. */
2467 output_addr_const (file
, x
);
2472 /* Print a memory address as an operand to reference that memory location. */
2475 m32r_print_operand_address (file
, addr
)
2480 register rtx index
= 0;
2483 switch (GET_CODE (addr
))
2486 fputs (reg_names
[REGNO (addr
)], file
);
2490 if (GET_CODE (XEXP (addr
, 0)) == CONST_INT
)
2491 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
2492 else if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
2493 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
2495 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
2496 if (GET_CODE (base
) == REG
)
2498 /* Print the offset first (if present) to conform to the manual. */
2502 fprintf (file
, "%d,", offset
);
2503 fputs (reg_names
[REGNO (base
)], file
);
2505 /* The chip doesn't support this, but left in for generality. */
2506 else if (GET_CODE (index
) == REG
)
2507 fprintf (file
, "%s,%s",
2508 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2509 /* Not sure this can happen, but leave in for now. */
2510 else if (GET_CODE (index
) == SYMBOL_REF
)
2512 output_addr_const (file
, index
);
2514 fputs (reg_names
[REGNO (base
)], file
);
2517 fatal_insn ("bad address", addr
);
2519 else if (GET_CODE (base
) == LO_SUM
)
2522 || GET_CODE (XEXP (base
, 0)) != REG
)
2524 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2525 fputs ("sda(", file
);
2527 fputs ("low(", file
);
2528 output_addr_const (file
, plus_constant (XEXP (base
, 1), offset
));
2530 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2533 fatal_insn ("bad address", addr
);
2537 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2538 fatal_insn ("lo_sum not of register", addr
);
2539 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2540 fputs ("sda(", file
);
2542 fputs ("low(", file
);
2543 output_addr_const (file
, XEXP (addr
, 1));
2545 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2548 case PRE_INC
: /* Assume SImode */
2549 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2552 case PRE_DEC
: /* Assume SImode */
2553 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2556 case POST_INC
: /* Assume SImode */
2557 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2561 output_addr_const (file
, addr
);
2566 /* Return true if the operands are the constants 0 and 1. */
2568 zero_and_one (operand1
, operand2
)
2573 GET_CODE (operand1
) == CONST_INT
2574 && GET_CODE (operand2
) == CONST_INT
2575 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2576 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2579 /* Return nonzero if the operand is suitable for use in a conditional move sequence. */
2581 conditional_move_operand (operand
, mode
)
2583 enum machine_mode mode
;
2585 /* Only defined for simple integers so far... */
2586 if (mode
!= SImode
&& mode
!= HImode
&& mode
!= QImode
)
2589 /* At the moment we can hanndle moving registers and loading constants. */
2590 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2592 switch (GET_CODE (operand
))
2598 return INT8_P (INTVAL (operand
));
2602 fprintf (stderr
, "Test for cond move op of type: %s\n",
2603 GET_RTX_NAME (GET_CODE (operand
)));
2609 /* Return true if the code is a test of the carry bit */
2611 carry_compare_operand (op
, mode
)
2613 enum machine_mode mode ATTRIBUTE_UNUSED
;
2617 if (GET_MODE (op
) != CCmode
&& GET_MODE (op
) != VOIDmode
)
2620 if (GET_CODE (op
) != NE
&& GET_CODE (op
) != EQ
)
2624 if (GET_CODE (x
) != REG
|| REGNO (x
) != CARRY_REGNUM
)
2628 if (GET_CODE (x
) != CONST_INT
|| INTVAL (x
) != 0)
2634 /* Generate the correct assembler code to handle the conditional loading of a
2635 value into a register. It is known that the operands satisfy the
2636 conditional_move_operand() function above. The destination is operand[0].
2637 The condition is operand [1]. The 'true' value is operand [2] and the
2638 'false' value is operand [3]. */
2640 emit_cond_move (operands
, insn
)
2642 rtx insn ATTRIBUTE_UNUSED
;
2644 static char buffer
[100];
2645 const char * dest
= reg_names
[REGNO (operands
[0])];
2649 /* Destination must be a register. */
2650 if (GET_CODE (operands
[0]) != REG
)
2652 if (! conditional_move_operand (operands
[2], SImode
))
2654 if (! conditional_move_operand (operands
[3], SImode
))
2657 /* Check to see if the test is reversed. */
2658 if (GET_CODE (operands
[1]) == NE
)
2660 rtx tmp
= operands
[2];
2661 operands
[2] = operands
[3];
2665 sprintf (buffer
, "mvfc %s, cbr", dest
);
2667 /* If the true value was '0' then we need to invert the results of the move. */
2668 if (INTVAL (operands
[2]) == 0)
2669 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2675 /* Returns true if the registers contained in the two
2676 rtl expressions are different. */
2678 m32r_not_same_reg (a
, b
)
2685 while (GET_CODE (a
) == SUBREG
)
2688 if (GET_CODE (a
) == REG
)
2691 while (GET_CODE (b
) == SUBREG
)
2694 if (GET_CODE (b
) == REG
)
2697 return reg_a
!= reg_b
;
2701 /* Use a library function to move some bytes. */
2703 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2708 /* We want to pass the size as Pmode, which will normally be SImode
2709 but will be DImode if we are using 64 bit longs and pointers. */
2710 if (GET_MODE (bytes_rtx
) != VOIDmode
2711 && GET_MODE (bytes_rtx
) != Pmode
)
2712 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2714 #ifdef TARGET_MEM_FUNCTIONS
2715 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2716 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2717 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2718 TREE_UNSIGNED (sizetype
)),
2719 TYPE_MODE (sizetype
));
2721 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2722 VOIDmode
, 3, src_reg
, Pmode
, dest_reg
, Pmode
,
2723 convert_to_mode (TYPE_MODE (integer_type_node
), bytes_rtx
,
2724 TREE_UNSIGNED (integer_type_node
)),
2725 TYPE_MODE (integer_type_node
));
2729 /* The maximum number of bytes to copy using pairs of load/store instructions.
2730 If a block is larger than this then a loop will be generated to copy
2731 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitary choice.
2732 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2733 string copy in it. */
2734 #define MAX_MOVE_BYTES 32
2736 /* Expand string/block move operations.
2738 operands[0] is the pointer to the destination.
2739 operands[1] is the pointer to the source.
2740 operands[2] is the number of bytes to move.
2741 operands[3] is the alignment. */
2744 m32r_expand_block_move (operands
)
2747 rtx orig_dst
= operands
[0];
2748 rtx orig_src
= operands
[1];
2749 rtx bytes_rtx
= operands
[2];
2750 rtx align_rtx
= operands
[3];
2751 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
2752 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2753 int align
= INTVAL (align_rtx
);
2758 if (constp
&& bytes
<= 0)
2761 /* Move the address into scratch registers. */
2762 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2763 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2765 if (align
> UNITS_PER_WORD
)
2766 align
= UNITS_PER_WORD
;
2768 /* If we prefer size over speed, always use a function call.
2769 If we do not know the size, use a function call.
2770 If the blocks are not word aligned, use a function call. */
2771 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2773 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2777 leftover
= bytes
% MAX_MOVE_BYTES
;
2780 /* If necessary, generate a loop to handle the bulk of the copy. */
2783 rtx label
= NULL_RTX
;
2784 rtx final_src
= NULL_RTX
;
2785 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2786 rtx rounded_total
= GEN_INT (bytes
);
2788 /* If we are going to have to perform this loop more than
2789 once, then generate a label and compute the address the
2790 source register will contain upon completion of the final
2792 if (bytes
> MAX_MOVE_BYTES
)
2794 final_src
= gen_reg_rtx (Pmode
);
2797 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2800 emit_insn (gen_movsi (final_src
, rounded_total
));
2801 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2804 label
= gen_label_rtx ();
2808 /* It is known that output_block_move() will update src_reg to point
2809 to the word after the end of the source block, and dst_reg to point
2810 to the last word of the destination block, provided that the block
2811 is MAX_MOVE_BYTES long. */
2812 emit_insn (gen_movstrsi_internal (dst_reg
, src_reg
, at_a_time
));
2813 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2815 if (bytes
> MAX_MOVE_BYTES
)
2817 emit_insn (gen_cmpsi (src_reg
, final_src
));
2818 emit_jump_insn (gen_bne (label
));
2823 emit_insn (gen_movstrsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
)));
2827 /* Emit load/stores for a small constant word aligned block_move.
2829 operands[0] is the memory address of the destination.
2830 operands[1] is the memory address of the source.
2831 operands[2] is the number of bytes to move.
2832 operands[3] is a temp register.
2833 operands[4] is a temp register. */
2836 m32r_output_block_move (insn
, operands
)
2837 rtx insn ATTRIBUTE_UNUSED
;
2840 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2844 if (bytes
< 1 || bytes
> MAX_MOVE_BYTES
)
2847 /* We do not have a post-increment store available, so the first set of
2848 stores are done without any increment, then the remaining ones can use
2849 the pre-increment addressing mode.
2851 Note: expand_block_move() also relies upon this behavior when building
2852 loops to copy large blocks. */
2861 output_asm_insn ("ld\t%3, %p1", operands
);
2862 output_asm_insn ("ld\t%4, %p1", operands
);
2863 output_asm_insn ("st\t%3, @%0", operands
);
2864 output_asm_insn ("st\t%4, %s0", operands
);
2868 output_asm_insn ("ld\t%3, %p1", operands
);
2869 output_asm_insn ("ld\t%4, %p1", operands
);
2870 output_asm_insn ("st\t%3, %s0", operands
);
2871 output_asm_insn ("st\t%4, %s0", operands
);
2876 else if (bytes
>= 4)
2881 output_asm_insn ("ld\t%3, %p1", operands
);
2884 output_asm_insn ("ld\t%4, %p1", operands
);
2887 output_asm_insn ("st\t%3, @%0", operands
);
2889 output_asm_insn ("st\t%3, %s0", operands
);
2895 /* Get the entire next word, even though we do not want all of it.
2896 The saves us from doing several smaller loads, and we assume that
2897 we cannot cause a page fault when at least part of the word is in
2898 valid memory [since we don't get called if things aren't properly
2900 int dst_offset
= first_time
? 0 : 4;
2904 /* If got_extra is true then we have already loaded
2905 the next word as part of loading and storing the previous word. */
2907 output_asm_insn ("ld\t%4, @%1", operands
);
2913 output_asm_insn ("sra3\t%3, %4, #16", operands
);
2914 my_operands
[0] = operands
[3];
2915 my_operands
[1] = GEN_INT (dst_offset
);
2916 my_operands
[2] = operands
[0];
2917 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2919 /* If there is a byte left to store then increment the
2920 destination address and shift the contents of the source
2921 register down by 8 bits. We could not do the address
2922 increment in the store half word instruction, because it does
2923 not have an auto increment mode. */
2924 if (bytes
> 0) /* assert (bytes == 1) */
2935 my_operands
[0] = operands
[4];
2936 my_operands
[1] = GEN_INT (last_shift
);
2937 output_asm_insn ("srai\t%0, #%1", my_operands
);
2938 my_operands
[0] = operands
[4];
2939 my_operands
[1] = GEN_INT (dst_offset
);
2940 my_operands
[2] = operands
[0];
2941 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2951 /* Return true if op is an integer constant, less than or equal to
2954 m32r_block_immediate_operand (op
, mode
)
2956 enum machine_mode mode ATTRIBUTE_UNUSED
;
2958 if (GET_CODE (op
) != CONST_INT
2959 || INTVAL (op
) > MAX_MOVE_BYTES
2960 || INTVAL (op
) <= 0)
2966 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2969 m32r_hard_regno_rename_ok (old_reg
, new_reg
)
2970 unsigned int old_reg ATTRIBUTE_UNUSED
;
2971 unsigned int new_reg
;
2973 /* Interrupt routines can't clobber any register that isn't already used. */
2974 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
))
2975 && !regs_ever_live
[new_reg
])
2978 /* We currently emit epilogues as text, not rtl, so the liveness
2979 of the return address register isn't visible. */
2980 if (current_function_is_leaf
&& new_reg
== RETURN_ADDR_REGNUM
)