1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Forward declarations. */
49 static const char *byte_reg (rtx
, int);
50 static int h8300_interrupt_function_p (tree
);
51 static int h8300_monitor_function_p (tree
);
52 static int h8300_os_task_function_p (tree
);
53 static void dosize (int, unsigned int);
54 static int round_frame_size (int);
55 static unsigned int compute_saved_regs (void);
56 static void push (int);
57 static void pop (int);
58 static const char *cond_string (enum rtx_code
);
59 static unsigned int h8300_asm_insn_count (const char *);
60 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
61 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
62 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
63 #ifndef OBJECT_FORMAT_ELF
64 static void h8300_asm_named_section (const char *, unsigned int);
66 static int h8300_and_costs (rtx
);
67 static int h8300_shift_costs (rtx
);
69 /* CPU_TYPE, says what cpu we're compiling for. */
72 /* True if a #pragma interrupt has been seen for the current function. */
73 static int pragma_interrupt
;
75 /* True if a #pragma saveall has been seen for the current function. */
76 static int pragma_saveall
;
78 static const char *const names_big
[] =
79 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
81 static const char *const names_extended
[] =
82 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
84 static const char *const names_upper_extended
[] =
85 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
87 /* Points to one of the above. */
88 /* ??? The above could be put in an array indexed by CPU_TYPE. */
89 const char * const *h8_reg_names
;
91 /* Various operations needed by the following, indexed by CPU_TYPE. */
93 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
95 /* Machine-specific symbol_ref flags. */
96 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
97 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
98 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
100 /* See below where shifts are handled for explanation of this enum. */
110 /* Symbols of the various shifts which can be used as indices. */
114 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
117 /* Macros to keep the shift algorithm tables small. */
118 #define INL SHIFT_INLINE
119 #define ROT SHIFT_ROT_AND
120 #define LOP SHIFT_LOOP
121 #define SPC SHIFT_SPECIAL
123 /* The shift algorithms for each machine, mode, shift type, and shift
124 count are defined below. The three tables below correspond to
125 QImode, HImode, and SImode, respectively. Each table is organized
126 by, in the order of indices, machine, shift type, and shift count. */
128 static enum shift_alg shift_alg_qi
[3][3][8] = {
131 /* 0 1 2 3 4 5 6 7 */
132 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
133 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
134 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
138 /* 0 1 2 3 4 5 6 7 */
139 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
140 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
141 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
145 /* 0 1 2 3 4 5 6 7 */
146 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
147 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
148 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
152 static enum shift_alg shift_alg_hi
[3][3][16] = {
155 /* 0 1 2 3 4 5 6 7 */
156 /* 8 9 10 11 12 13 14 15 */
157 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
158 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
159 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
160 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
161 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
162 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
166 /* 0 1 2 3 4 5 6 7 */
167 /* 8 9 10 11 12 13 14 15 */
168 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
169 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
170 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
171 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
172 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
173 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
177 /* 0 1 2 3 4 5 6 7 */
178 /* 8 9 10 11 12 13 14 15 */
179 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
180 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
181 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
182 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
183 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
184 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
188 static enum shift_alg shift_alg_si
[3][3][32] = {
191 /* 0 1 2 3 4 5 6 7 */
192 /* 8 9 10 11 12 13 14 15 */
193 /* 16 17 18 19 20 21 22 23 */
194 /* 24 25 26 27 28 29 30 31 */
195 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
196 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
197 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
198 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
199 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
200 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
201 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
202 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
203 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
204 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
205 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
206 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
210 /* 0 1 2 3 4 5 6 7 */
211 /* 8 9 10 11 12 13 14 15 */
212 /* 16 17 18 19 20 21 22 23 */
213 /* 24 25 26 27 28 29 30 31 */
214 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
215 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
216 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
217 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
218 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
219 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
220 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
221 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
222 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
223 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
224 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
225 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
229 /* 0 1 2 3 4 5 6 7 */
230 /* 8 9 10 11 12 13 14 15 */
231 /* 16 17 18 19 20 21 22 23 */
232 /* 24 25 26 27 28 29 30 31 */
233 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
234 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
235 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
236 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
237 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
238 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
239 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
240 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
241 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
242 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
243 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
244 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
260 /* Initialize various cpu specific globals at start up. */
263 h8300_init_once (void)
265 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
266 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
267 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
271 cpu_type
= (int) CPU_H8300
;
272 h8_reg_names
= names_big
;
276 /* For this we treat the H8/300H and H8S the same. */
277 cpu_type
= (int) CPU_H8300H
;
278 h8_reg_names
= names_extended
;
280 h8_push_op
= h8_push_ops
[cpu_type
];
281 h8_pop_op
= h8_pop_ops
[cpu_type
];
282 h8_mov_op
= h8_mov_ops
[cpu_type
];
284 if (!TARGET_H8300S
&& TARGET_MAC
)
286 error ("-ms2600 is used without -ms");
287 target_flags
|= MASK_H8300S
;
290 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
292 error ("-mn is used without -mh or -ms");
293 target_flags
^= MASK_NORMAL_MODE
;
296 /* Some of the shifts are optimized for speed by default.
297 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
298 If optimizing for size, change shift_alg for those shift to
303 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
304 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
305 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
306 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
308 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
309 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
311 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
312 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
315 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
316 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
318 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
319 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
321 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
322 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
323 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
324 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
327 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
332 byte_reg (rtx x
, int b
)
334 static const char *const names_small
[] = {
335 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
336 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
339 return names_small
[REGNO (x
) * 2 + b
];
342 /* REGNO must be saved/restored across calls if this macro is true. */
344 #define WORD_REG_USED(regno) \
346 /* No need to save registers if this function will not return. */ \
347 && ! TREE_THIS_VOLATILE (current_function_decl) \
349 /* Save any call saved register that was used. */ \
350 || (regs_ever_live[regno] && !call_used_regs[regno]) \
351 /* Save the frame pointer if it was used. */ \
352 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
353 /* Save any register used in an interrupt handler. */ \
354 || (h8300_current_function_interrupt_function_p () \
355 && regs_ever_live[regno]) \
356 /* Save call clobbered registers in non-leaf interrupt \
358 || (h8300_current_function_interrupt_function_p () \
359 && call_used_regs[regno] \
360 && !current_function_is_leaf)))
362 /* Output assembly language to FILE for the operation OP with operand size
363 SIZE to adjust the stack pointer. */
370 /* H8/300 cannot add/subtract a large constant with a single
371 instruction. If a temporary register is available, load the
372 constant to it and then do the addition. */
375 && !h8300_current_function_interrupt_function_p ()
376 && !(current_function_needs_context
&& sign
< 0))
379 rtx r3
= gen_rtx_REG (Pmode
, 3);
380 emit_insn (gen_rtx_SET (Pmode
, r3
, GEN_INT (sign
* size
)));
381 new_sp
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r3
);
382 emit_insn (gen_rtx_SET (Pmode
, stack_pointer_rtx
, new_sp
));
386 /* The stack adjustment made here is further optimized by the
387 splitter. In case of H8/300, the splitter always splits the
388 addition emitted here to make the adjustment
390 rtx new_sp
= plus_constant (stack_pointer_rtx
, sign
* size
);
391 emit_insn (gen_rtx_SET (Pmode
, stack_pointer_rtx
, new_sp
));
395 /* Round up frame size SIZE. */
398 round_frame_size (int size
)
400 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
401 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
404 /* Compute which registers to push/pop.
405 Return a bit vector of registers. */
408 compute_saved_regs (void)
410 unsigned int saved_regs
= 0;
413 /* Construct a bit vector of registers to be pushed/popped. */
414 for (regno
= 0; regno
<= FRAME_POINTER_REGNUM
; regno
++)
416 if (WORD_REG_USED (regno
))
417 saved_regs
|= 1 << regno
;
420 /* Don't push/pop the frame pointer as it is treated separately. */
421 if (frame_pointer_needed
)
422 saved_regs
&= ~(1 << FRAME_POINTER_REGNUM
);
427 /* Emit an insn to push register RN. */
432 rtx reg
= gen_rtx_REG (word_mode
, rn
);
436 x
= gen_push_h8300 (reg
);
438 x
= gen_push_h8300hs (reg
);
440 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
443 /* Emit an insn to pop register RN. */
448 rtx reg
= gen_rtx_REG (word_mode
, rn
);
452 x
= gen_pop_h8300 (reg
);
454 x
= gen_pop_h8300hs (reg
);
456 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
459 /* This is what the stack looks like after the prolog of
460 a function with a frame has been set up:
466 <saved registers> <- sp
468 This is what the stack looks like after the prolog of
469 a function which doesn't have a frame:
474 <saved registers> <- sp
477 /* Generate RTL code for the function prologue. */
480 h8300_expand_prologue (void)
486 /* If the current function has the OS_Task attribute set, then
487 we have a naked prologue. */
488 if (h8300_os_task_function_p (current_function_decl
))
491 if (h8300_monitor_function_p (current_function_decl
))
492 /* My understanding of monitor functions is they act just like
493 interrupt functions, except the prologue must mask
495 emit_insn (gen_monitor_prologue ());
497 if (frame_pointer_needed
)
500 push (FRAME_POINTER_REGNUM
);
501 emit_insn (gen_rtx_SET (Pmode
, frame_pointer_rtx
, stack_pointer_rtx
));
504 /* Leave room for locals. */
505 dosize (-1, round_frame_size (get_frame_size ()));
507 /* Push the rest of the registers in ascending order. */
508 saved_regs
= compute_saved_regs ();
509 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
512 if (saved_regs
& (1 << regno
))
516 /* See how many registers we can push at the same time. */
517 if ((regno
== 0 || regno
== 4)
518 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
521 else if ((regno
== 0 || regno
== 4)
522 && ((saved_regs
>> regno
) & 0x07) == 0x07)
525 else if ((regno
== 0 || regno
== 2 || regno
== 4 || regno
== 6)
526 && ((saved_regs
>> regno
) & 0x03) == 0x03)
536 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode
, regno
),
537 gen_rtx_REG (SImode
, regno
+ 1)));
540 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode
, regno
),
541 gen_rtx_REG (SImode
, regno
+ 1),
542 gen_rtx_REG (SImode
, regno
+ 2)));
545 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode
, regno
),
546 gen_rtx_REG (SImode
, regno
+ 1),
547 gen_rtx_REG (SImode
, regno
+ 2),
548 gen_rtx_REG (SImode
, regno
+ 3)));
558 h8300_can_use_return_insn_p (void)
560 return (reload_completed
561 && !frame_pointer_needed
562 && get_frame_size () == 0
563 && compute_saved_regs () == 0);
566 /* Generate RTL code for the function epilogue. */
569 h8300_expand_epilogue (void)
575 if (h8300_os_task_function_p (current_function_decl
))
576 /* OS_Task epilogues are nearly naked -- they just have an
580 /* Pop the saved registers in descending order. */
581 saved_regs
= compute_saved_regs ();
582 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
585 if (saved_regs
& (1 << regno
))
589 /* See how many registers we can pop at the same time. */
590 if ((regno
== 7 || regno
== 3)
591 && ((saved_regs
>> (regno
- 3)) & 0x0f) == 0x0f)
594 else if ((regno
== 6 || regno
== 2)
595 && ((saved_regs
>> (regno
- 2)) & 0x07) == 0x07)
598 else if ((regno
== 7 || regno
== 5 || regno
== 3 || regno
== 1)
599 && ((saved_regs
>> (regno
- 1)) & 0x03) == 0x03)
609 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode
, regno
- 1),
610 gen_rtx_REG (SImode
, regno
)));
613 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode
, regno
- 2),
614 gen_rtx_REG (SImode
, regno
- 1),
615 gen_rtx_REG (SImode
, regno
)));
618 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode
, regno
- 3),
619 gen_rtx_REG (SImode
, regno
- 2),
620 gen_rtx_REG (SImode
, regno
- 1),
621 gen_rtx_REG (SImode
, regno
)));
629 /* Deallocate locals. */
630 dosize (1, round_frame_size (get_frame_size ()));
632 /* Pop frame pointer if we had one. */
633 if (frame_pointer_needed
)
634 pop (FRAME_POINTER_REGNUM
);
637 /* Output assembly language code for the function epilogue. */
640 h8300_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
641 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
646 /* Return nonzero if the current function is an interrupt
650 h8300_current_function_interrupt_function_p (void)
652 return (h8300_interrupt_function_p (current_function_decl
)
653 || h8300_monitor_function_p (current_function_decl
));
656 /* Output assembly code for the start of the file. */
659 h8300_file_start (void)
661 default_file_start ();
664 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
665 else if (TARGET_H8300S
)
666 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
669 /* Output assembly language code for the end of file. */
672 h8300_file_end (void)
674 fputs ("\t.end\n", asm_out_file
);
677 /* Return true if OP is a valid source operand for an integer move
681 general_operand_src (rtx op
, enum machine_mode mode
)
683 if (GET_MODE (op
) == mode
684 && GET_CODE (op
) == MEM
685 && GET_CODE (XEXP (op
, 0)) == POST_INC
)
687 return general_operand (op
, mode
);
690 /* Return true if OP is a valid destination operand for an integer move
694 general_operand_dst (rtx op
, enum machine_mode mode
)
696 if (GET_MODE (op
) == mode
697 && GET_CODE (op
) == MEM
698 && GET_CODE (XEXP (op
, 0)) == PRE_DEC
)
700 return general_operand (op
, mode
);
703 /* Return true if OP is a constant that contains only one 1 in its
704 binary representation. */
707 single_one_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
709 if (GET_CODE (operand
) == CONST_INT
)
711 /* We really need to do this masking because 0x80 in QImode is
712 represented as -128 for example. */
713 if (exact_log2 (INTVAL (operand
) & GET_MODE_MASK (mode
)) >= 0)
720 /* Return true if OP is a constant that contains only one 0 in its
721 binary representation. */
724 single_zero_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
726 if (GET_CODE (operand
) == CONST_INT
)
728 /* We really need to do this masking because 0x80 in QImode is
729 represented as -128 for example. */
730 if (exact_log2 (~INTVAL (operand
) & GET_MODE_MASK (mode
)) >= 0)
737 /* Return true if OP is a valid call operand. */
740 call_insn_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
742 if (GET_CODE (op
) == MEM
)
744 rtx inside
= XEXP (op
, 0);
745 if (register_operand (inside
, Pmode
))
747 if (CONSTANT_ADDRESS_P (inside
))
753 /* Return 1 if an addition/subtraction of a constant integer can be
754 transformed into two consecutive adds/subs that are faster than the
755 straightforward way. Otherwise, return 0. */
758 two_insn_adds_subs_operand (rtx op
, enum machine_mode mode
)
760 if (GET_CODE (op
) == CONST_INT
)
762 HOST_WIDE_INT value
= INTVAL (op
);
764 /* Force VALUE to be positive so that we do not have to consider
765 the negative case. */
768 if (TARGET_H8300H
|| TARGET_H8300S
)
770 /* A constant addition/subtraction takes 2 states in QImode,
771 4 states in HImode, and 6 states in SImode. Thus, the
772 only case we can win is when SImode is used, in which
773 case, two adds/subs are used, taking 4 states. */
783 /* We do not profit directly by splitting addition or
784 subtraction of 3 and 4. However, since these are
785 implemented as a sequence of adds or subs, they do not
786 clobber (cc0) unlike a sequence of add.b and add.x. */
797 /* Split an add of a small constant into two adds/subs insns.
799 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
800 instead of adds/subs. */
803 split_adds_subs (enum machine_mode mode
, rtx
*operands
)
805 HOST_WIDE_INT val
= INTVAL (operands
[1]);
806 rtx reg
= operands
[0];
807 HOST_WIDE_INT sign
= 1;
808 HOST_WIDE_INT amount
;
809 rtx (*gen_add
) (rtx
, rtx
, rtx
);
811 /* Force VAL to be positive so that we do not have to consider the
822 gen_add
= gen_addhi3
;
826 gen_add
= gen_addsi3
;
833 /* Try different amounts in descending order. */
834 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
838 for (; val
>= amount
; val
-= amount
)
839 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
845 /* Return true if OP is a valid call operand, and OP represents
846 an operand for a small call (4 bytes instead of 6 bytes). */
849 small_call_insn_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
851 if (GET_CODE (op
) == MEM
)
853 rtx inside
= XEXP (op
, 0);
855 /* Register indirect is a small call. */
856 if (register_operand (inside
, Pmode
))
859 /* A call through the function vector is a small call too. */
860 if (GET_CODE (inside
) == SYMBOL_REF
861 && (SYMBOL_REF_FLAGS (inside
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
864 /* Otherwise it's a large call. */
868 /* Return true if OP is a valid jump operand. */
871 jump_address_operand (rtx op
, enum machine_mode mode
)
873 if (GET_CODE (op
) == REG
)
874 return mode
== Pmode
;
876 if (GET_CODE (op
) == MEM
)
878 rtx inside
= XEXP (op
, 0);
879 if (register_operand (inside
, Pmode
))
881 if (CONSTANT_ADDRESS_P (inside
))
887 /* Recognize valid operands for bit-field instructions. */
889 extern int rtx_equal_function_value_matters
;
892 bit_operand (rtx op
, enum machine_mode mode
)
894 /* We can accept any general operand, except that MEM operands must
895 be limited to those that use addresses valid for the 'U' constraint. */
896 if (!general_operand (op
, mode
))
899 /* Accept any mem during RTL generation. Otherwise, the code that does
900 insv and extzv will think that we can not handle memory. However,
901 to avoid reload problems, we only accept 'U' MEM operands after RTL
902 generation. This means that any named pattern which uses this predicate
903 must force its operands to match 'U' before emitting RTL. */
905 if (GET_CODE (op
) == REG
)
907 if (GET_CODE (op
) == SUBREG
)
909 return (GET_CODE (op
) == MEM
910 && EXTRA_CONSTRAINT (op
, 'U'));
914 bit_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
916 return (GET_CODE (op
) == MEM
917 && EXTRA_CONSTRAINT (op
, 'U'));
920 /* Handle machine specific pragmas for compatibility with existing
921 compilers for the H8/300.
923 pragma saveall generates prologue/epilogue code which saves and
924 restores all the registers on function entry.
926 pragma interrupt saves and restores all registers, and exits with
927 an rte instruction rather than an rts. A pointer to a function
928 with this attribute may be safely used in an interrupt vector. */
931 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
933 pragma_interrupt
= 1;
937 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
942 /* If the next function argument with MODE and TYPE is to be passed in
943 a register, return a reg RTX for the hard register in which to pass
944 the argument. CUM represents the state after the last argument.
945 If the argument is to be pushed, NULL_RTX is returned. */
948 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
949 tree type
, int named
)
951 static const char *const hand_list
[] = {
970 rtx result
= NULL_RTX
;
974 /* Never pass unnamed arguments in registers. */
978 /* Pass 3 regs worth of data in regs when user asked on the command line. */
979 if (TARGET_QUICKCALL
)
982 /* If calling hand written assembler, use 4 regs of args. */
985 const char * const *p
;
987 fname
= XSTR (cum
->libcall
, 0);
989 /* See if this libcall is one of the hand coded ones. */
990 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1001 if (mode
== BLKmode
)
1002 size
= int_size_in_bytes (type
);
1004 size
= GET_MODE_SIZE (mode
);
1006 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1007 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1008 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1015 h8300_and_costs (rtx x
)
1019 if (GET_MODE (x
) == QImode
)
1022 if (GET_MODE (x
) != HImode
1023 && GET_MODE (x
) != SImode
)
1028 operands
[2] = XEXP (x
, 1);
1030 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1034 h8300_shift_costs (rtx x
)
1038 if (GET_MODE (x
) != QImode
1039 && GET_MODE (x
) != HImode
1040 && GET_MODE (x
) != SImode
)
1045 operands
[2] = XEXP (x
, 1);
1047 return compute_a_shift_length (NULL
, operands
) / 2;
1051 h8300_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1057 HOST_WIDE_INT n
= INTVAL (x
);
1059 if (-4 <= n
|| n
<= 4)
1070 *total
= 0 + (outer_code
== SET
);
1074 if (TARGET_H8300H
|| TARGET_H8300S
)
1075 *total
= 0 + (outer_code
== SET
);
1096 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1099 /* We say that MOD and DIV are so expensive because otherwise we'll
1100 generate some really horrible code for division of a power of two. */
1113 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1118 if (GET_MODE (x
) == HImode
)
1130 /* Documentation for the machine specific operand escapes:
1132 'E' like s but negative.
1133 'F' like t but negative.
1134 'G' constant just the negative
1135 'R' print operand as a byte:8 address if appropriate, else fall back to
1137 'S' print operand as a long word
1138 'T' print operand as a word
1139 'V' find the set bit, and print its number.
1140 'W' find the clear bit, and print its number.
1141 'X' print operand as a byte
1142 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1143 If this operand isn't a register, fall back to 'R' handling.
1145 'c' print the opcode corresponding to rtl
1146 'e' first word of 32 bit value - if reg, then least reg. if mem
1147 then least. if const then most sig word
1148 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1149 then +2. if const then least sig word
1150 'j' print operand as condition code.
1151 'k' print operand as reverse condition code.
1152 's' print as low byte of 16 bit value
1153 't' print as high byte of 16 bit value
1154 'w' print as low byte of 32 bit value
1155 'x' print as 2nd byte of 32 bit value
1156 'y' print as 3rd byte of 32 bit value
1157 'z' print as msb of 32 bit value
1160 /* Return assembly language string which identifies a comparison type. */
1163 cond_string (enum rtx_code code
)
1192 /* Print operand X using operand code CODE to assembly language output file
1196 print_operand (FILE *file
, rtx x
, int code
)
1198 /* This is used for communication between codes V,W,Z and Y. */
1204 switch (GET_CODE (x
))
1207 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1210 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1217 switch (GET_CODE (x
))
1220 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1223 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1230 if (GET_CODE (x
) != CONST_INT
)
1232 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1235 if (GET_CODE (x
) == REG
)
1236 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1241 if (GET_CODE (x
) == REG
)
1242 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1247 bitint
= exact_log2 (INTVAL (x
) & 0xff);
1250 fprintf (file
, "#%d", bitint
);
1253 bitint
= exact_log2 ((~INTVAL (x
)) & 0xff);
1256 fprintf (file
, "#%d", bitint
);
1260 if (GET_CODE (x
) == REG
)
1261 fprintf (file
, "%s", byte_reg (x
, 0));
1268 if (GET_CODE (x
) == REG
)
1269 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1271 print_operand (file
, x
, 'R');
1275 bitint
= INTVAL (x
);
1276 fprintf (file
, "#%d", bitint
& 7);
1279 switch (GET_CODE (x
))
1282 fprintf (file
, "or");
1285 fprintf (file
, "xor");
1288 fprintf (file
, "and");
1295 switch (GET_CODE (x
))
1299 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1301 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1304 print_operand (file
, x
, 0);
1307 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1313 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1314 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1315 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1324 switch (GET_CODE (x
))
1328 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1330 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1333 x
= adjust_address (x
, HImode
, 2);
1334 print_operand (file
, x
, 0);
1337 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1343 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1344 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1345 fprintf (file
, "#%ld", (val
& 0xffff));
1353 fputs (cond_string (GET_CODE (x
)), file
);
1356 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1359 if (GET_CODE (x
) == CONST_INT
)
1360 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1362 fprintf (file
, "%s", byte_reg (x
, 0));
1365 if (GET_CODE (x
) == CONST_INT
)
1366 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1368 fprintf (file
, "%s", byte_reg (x
, 1));
1371 if (GET_CODE (x
) == CONST_INT
)
1372 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1374 fprintf (file
, "%s",
1375 byte_reg (x
, TARGET_H8300
? 2 : 0));
1378 if (GET_CODE (x
) == CONST_INT
)
1379 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1381 fprintf (file
, "%s",
1382 byte_reg (x
, TARGET_H8300
? 3 : 1));
1385 if (GET_CODE (x
) == CONST_INT
)
1386 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1388 fprintf (file
, "%s", byte_reg (x
, 0));
1391 if (GET_CODE (x
) == CONST_INT
)
1392 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1394 fprintf (file
, "%s", byte_reg (x
, 1));
1399 switch (GET_CODE (x
))
1402 switch (GET_MODE (x
))
1405 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1406 fprintf (file
, "%s", byte_reg (x
, 0));
1407 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1408 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1412 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1416 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1425 rtx addr
= XEXP (x
, 0);
1427 fprintf (file
, "@");
1428 output_address (addr
);
1430 /* We fall back from smaller addressing to larger
1431 addressing in various ways depending on CODE. */
1435 /* Used for mov.b and bit operations. */
1436 if (h8300_eightbit_constant_address_p (addr
))
1438 fprintf (file
, ":8");
1442 /* Fall through. We should not get here if we are
1443 processing bit operations on H8/300 or H8/300H
1444 because 'U' constraint does not allow bit
1445 operations on the tiny area on these machines. */
1449 /* Used for mov.w and mov.l. */
1450 if (h8300_tiny_constant_address_p (addr
))
1451 fprintf (file
, ":16");
1463 fprintf (file
, "#");
1464 print_operand_address (file
, x
);
1470 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1471 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1472 fprintf (file
, "#%ld", val
);
1481 /* Output assembly language output for the address ADDR to FILE. */
1484 print_operand_address (FILE *file
, rtx addr
)
1486 switch (GET_CODE (addr
))
1489 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1493 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1497 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1501 fprintf (file
, "(");
1502 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1505 print_operand_address (file
, XEXP (addr
, 1));
1506 fprintf (file
, ",");
1507 print_operand_address (file
, XEXP (addr
, 0));
1512 print_operand_address (file
, XEXP (addr
, 0));
1513 fprintf (file
, "+");
1514 print_operand_address (file
, XEXP (addr
, 1));
1516 fprintf (file
, ")");
1521 /* Since the H8/300 only has 16 bit pointers, negative values are also
1522 those >= 32768. This happens for example with pointer minus a
1523 constant. We don't want to turn (char *p - 2) into
1524 (char *p + 65534) because loop unrolling can build upon this
1525 (IE: char *p + 131068). */
1526 int n
= INTVAL (addr
);
1528 n
= (int) (short) n
;
1529 fprintf (file
, "%d", n
);
1534 output_addr_const (file
, addr
);
1539 /* Output all insn addresses and their sizes into the assembly language
1540 output file. This is helpful for debugging whether the length attributes
1541 in the md file are correct. This is not meant to be a user selectable
1545 final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1546 int num_operands ATTRIBUTE_UNUSED
)
1548 /* This holds the last insn address. */
1549 static int last_insn_address
= 0;
1551 const int uid
= INSN_UID (insn
);
1553 if (TARGET_ADDRESSES
)
1555 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1556 INSN_ADDRESSES (uid
) - last_insn_address
);
1557 last_insn_address
= INSN_ADDRESSES (uid
);
1561 /* Prepare for an SI sized move. */
1564 do_movsi (rtx operands
[])
1566 rtx src
= operands
[1];
1567 rtx dst
= operands
[0];
1568 if (!reload_in_progress
&& !reload_completed
)
1570 if (!register_operand (dst
, GET_MODE (dst
)))
1572 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1573 emit_move_insn (tmp
, src
);
1580 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1581 Define the offset between two registers, one to be eliminated, and
1582 the other its replacement, at the start of a routine. */
1585 h8300_initial_elimination_offset (int from
, int to
)
1588 /* The number of bytes that the return address takes on the stack. */
1589 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1591 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1592 offset
= pc_size
+ frame_pointer_needed
* UNITS_PER_WORD
;
1593 else if (from
== RETURN_ADDRESS_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1594 offset
= frame_pointer_needed
* UNITS_PER_WORD
;
1599 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1600 if (WORD_REG_USED (regno
))
1601 offset
+= UNITS_PER_WORD
;
1603 /* See the comments for get_frame_size. We need to round it up to
1606 offset
+= round_frame_size (get_frame_size ());
1608 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1609 /* Skip saved PC. */
1617 h8300_return_addr_rtx (int count
, rtx frame
)
1622 ret
= gen_rtx_MEM (Pmode
,
1623 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
1624 else if (flag_omit_frame_pointer
)
1627 ret
= gen_rtx_MEM (Pmode
,
1628 memory_address (Pmode
,
1629 plus_constant (frame
, UNITS_PER_WORD
)));
1630 set_mem_alias_set (ret
, get_frame_alias_set ());
1634 /* Update the condition code from the insn. */
1637 notice_update_cc (rtx body
, rtx insn
)
1641 switch (get_attr_cc (insn
))
1644 /* Insn does not affect CC at all. */
1648 /* Insn does not change CC, but the 0'th operand has been changed. */
1649 if (cc_status
.value1
!= 0
1650 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
1651 cc_status
.value1
= 0;
1652 if (cc_status
.value2
!= 0
1653 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
1654 cc_status
.value2
= 0;
1658 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1659 The V flag is unusable. The C flag may or may not be known but
1660 that's ok because alter_cond will change tests to use EQ/NE. */
1662 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
1663 set
= single_set (insn
);
1664 cc_status
.value1
= SET_SRC (set
);
1665 if (SET_DEST (set
) != cc0_rtx
)
1666 cc_status
.value2
= SET_DEST (set
);
1670 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1671 The C flag may or may not be known but that's ok because
1672 alter_cond will change tests to use EQ/NE. */
1674 cc_status
.flags
|= CC_NO_CARRY
;
1675 set
= single_set (insn
);
1676 cc_status
.value1
= SET_SRC (set
);
1677 if (SET_DEST (set
) != cc0_rtx
)
1679 /* If the destination is STRICT_LOW_PART, strip off
1681 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1682 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
1684 cc_status
.value2
= SET_DEST (set
);
1689 /* The insn is a compare instruction. */
1691 cc_status
.value1
= SET_SRC (body
);
1695 /* Insn doesn't leave CC in a usable state. */
1701 /* Return nonzero if X is a stack pointer. */
1704 stack_pointer_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1706 return x
== stack_pointer_rtx
;
1709 /* Return nonzero if X is a constant whose absolute value is greater
1713 const_int_gt_2_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1715 return (GET_CODE (x
) == CONST_INT
1716 && abs (INTVAL (x
)) > 2);
1719 /* Return nonzero if X is a constant whose absolute value is no
1723 const_int_ge_8_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1725 return (GET_CODE (x
) == CONST_INT
1726 && abs (INTVAL (x
)) >= 8);
1729 /* Return nonzero if X is a constant expressible in QImode. */
1732 const_int_qi_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1734 return (GET_CODE (x
) == CONST_INT
1735 && (INTVAL (x
) & 0xff) == INTVAL (x
));
1738 /* Return nonzero if X is a constant expressible in HImode. */
1741 const_int_hi_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1743 return (GET_CODE (x
) == CONST_INT
1744 && (INTVAL (x
) & 0xffff) == INTVAL (x
));
1747 /* Return nonzero if X is a constant suitable for inc/dec. */
1750 incdec_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1752 return (GET_CODE (x
) == CONST_INT
1753 && (CONST_OK_FOR_M (INTVAL (x
))
1754 || CONST_OK_FOR_O (INTVAL (x
))));
1757 /* Return nonzero if X is either EQ or NE. */
1760 eqne_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1762 enum rtx_code code
= GET_CODE (x
);
1764 return (code
== EQ
|| code
== NE
);
1767 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1770 gtle_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1772 enum rtx_code code
= GET_CODE (x
);
1774 return (code
== GT
|| code
== LE
|| code
== GTU
|| code
== LEU
);
1777 /* Return nonzero if X is either GTU or LEU. */
1780 gtuleu_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1782 enum rtx_code code
= GET_CODE (x
);
1784 return (code
== GTU
|| code
== LEU
);
1787 /* Return nonzero if X is either IOR or XOR. */
1790 iorxor_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1792 enum rtx_code code
= GET_CODE (x
);
1794 return (code
== IOR
|| code
== XOR
);
1797 /* Recognize valid operators for bit instructions. */
1800 bit_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1802 enum rtx_code code
= GET_CODE (x
);
1810 output_plussi (rtx
*operands
)
1812 enum machine_mode mode
= GET_MODE (operands
[0]);
1819 if (GET_CODE (operands
[2]) == REG
)
1820 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1822 if (GET_CODE (operands
[2]) == CONST_INT
)
1824 HOST_WIDE_INT n
= INTVAL (operands
[2]);
1826 if ((n
& 0xffffff) == 0)
1827 return "add\t%z2,%z0";
1828 if ((n
& 0xffff) == 0)
1829 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
1830 if ((n
& 0xff) == 0)
1831 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1834 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1838 if (GET_CODE (operands
[2]) == REG
)
1839 return "add.l\t%S2,%S0";
1841 if (GET_CODE (operands
[2]) == CONST_INT
)
1843 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
1845 /* See if we can finish with 2 bytes. */
1847 switch ((unsigned int) intval
& 0xffffffff)
1852 return "adds\t%2,%S0";
1857 return "subs\t%G2,%S0";
1861 operands
[2] = GEN_INT (intval
>> 16);
1862 return "inc.w\t%2,%e0";
1866 operands
[2] = GEN_INT (intval
>> 16);
1867 return "dec.w\t%G2,%e0";
1870 /* See if we can finish with 4 bytes. */
1871 if ((intval
& 0xffff) == 0)
1873 operands
[2] = GEN_INT (intval
>> 16);
1874 return "add.w\t%2,%e0";
1878 return "add.l\t%S2,%S0";
1883 compute_plussi_length (rtx
*operands
)
1885 enum machine_mode mode
= GET_MODE (operands
[0]);
1892 if (GET_CODE (operands
[2]) == REG
)
1895 if (GET_CODE (operands
[2]) == CONST_INT
)
1897 HOST_WIDE_INT n
= INTVAL (operands
[2]);
1899 if ((n
& 0xffffff) == 0)
1901 if ((n
& 0xffff) == 0)
1903 if ((n
& 0xff) == 0)
1911 if (GET_CODE (operands
[2]) == REG
)
1914 if (GET_CODE (operands
[2]) == CONST_INT
)
1916 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
1918 /* See if we can finish with 2 bytes. */
1920 switch ((unsigned int) intval
& 0xffffffff)
1941 /* See if we can finish with 4 bytes. */
1942 if ((intval
& 0xffff) == 0)
1951 compute_plussi_cc (rtx
*operands
)
1953 enum machine_mode mode
= GET_MODE (operands
[0]);
1964 if (GET_CODE (operands
[2]) == REG
)
1967 if (GET_CODE (operands
[2]) == CONST_INT
)
1969 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
1971 /* See if we can finish with 2 bytes. */
1973 switch ((unsigned int) intval
& 0xffffffff)
1978 return CC_NONE_0HIT
;
1983 return CC_NONE_0HIT
;
1994 /* See if we can finish with 4 bytes. */
1995 if ((intval
& 0xffff) == 0)
2004 output_logical_op (enum machine_mode mode
, rtx
*operands
)
2006 /* Figure out the logical op that we need to perform. */
2007 enum rtx_code code
= GET_CODE (operands
[3]);
2008 /* Pretend that every byte is affected if both operands are registers. */
2009 const unsigned HOST_WIDE_INT intval
=
2010 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
2011 ? INTVAL (operands
[2]) : 0x55555555);
2012 /* The determinant of the algorithm. If we perform an AND, 0
2013 affects a bit. Otherwise, 1 affects a bit. */
2014 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
2015 /* Break up DET into pieces. */
2016 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
2017 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
2018 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
2019 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
2020 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
2021 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
2022 int lower_half_easy_p
= 0;
2023 int upper_half_easy_p
= 0;
2024 /* The name of an insn. */
2046 /* First, see if we can finish with one insn. */
2047 if ((TARGET_H8300H
|| TARGET_H8300S
)
2051 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
2052 output_asm_insn (insn_buf
, operands
);
2056 /* Take care of the lower byte. */
2059 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
2060 output_asm_insn (insn_buf
, operands
);
2062 /* Take care of the upper byte. */
2065 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
2066 output_asm_insn (insn_buf
, operands
);
2071 if (TARGET_H8300H
|| TARGET_H8300S
)
2073 /* Determine if the lower half can be taken care of in no more
2075 lower_half_easy_p
= (b0
== 0
2077 || (code
!= IOR
&& w0
== 0xffff));
2079 /* Determine if the upper half can be taken care of in no more
2081 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
2082 || (code
== AND
&& w1
== 0xff00));
2085 /* Check if doing everything with one insn is no worse than
2086 using multiple insns. */
2087 if ((TARGET_H8300H
|| TARGET_H8300S
)
2088 && w0
!= 0 && w1
!= 0
2089 && !(lower_half_easy_p
&& upper_half_easy_p
)
2090 && !(code
== IOR
&& w1
== 0xffff
2091 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
2093 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
2094 output_asm_insn (insn_buf
, operands
);
2098 /* Take care of the lower and upper words individually. For
2099 each word, we try different methods in the order of
2101 1) the special insn (in case of AND or XOR),
2102 2) the word-wise insn, and
2103 3) The byte-wise insn. */
2105 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
2106 output_asm_insn ((code
== AND
)
2107 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2109 else if ((TARGET_H8300H
|| TARGET_H8300S
)
2113 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
2114 output_asm_insn (insn_buf
, operands
);
2120 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
2121 output_asm_insn (insn_buf
, operands
);
2125 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
2126 output_asm_insn (insn_buf
, operands
);
2131 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
2132 output_asm_insn ((code
== AND
)
2133 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2135 else if ((TARGET_H8300H
|| TARGET_H8300S
)
2138 && (w0
& 0x8000) != 0)
2140 output_asm_insn ("exts.l\t%S0", operands
);
2142 else if ((TARGET_H8300H
|| TARGET_H8300S
)
2146 output_asm_insn ("extu.w\t%e0", operands
);
2148 else if (TARGET_H8300H
|| TARGET_H8300S
)
2152 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
2153 output_asm_insn (insn_buf
, operands
);
2160 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
2161 output_asm_insn (insn_buf
, operands
);
2165 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
2166 output_asm_insn (insn_buf
, operands
);
2178 compute_logical_op_length (enum machine_mode mode
, rtx
*operands
)
2180 /* Figure out the logical op that we need to perform. */
2181 enum rtx_code code
= GET_CODE (operands
[3]);
2182 /* Pretend that every byte is affected if both operands are registers. */
2183 const unsigned HOST_WIDE_INT intval
=
2184 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
2185 ? INTVAL (operands
[2]) : 0x55555555);
2186 /* The determinant of the algorithm. If we perform an AND, 0
2187 affects a bit. Otherwise, 1 affects a bit. */
2188 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
2189 /* Break up DET into pieces. */
2190 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
2191 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
2192 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
2193 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
2194 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
2195 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
2196 int lower_half_easy_p
= 0;
2197 int upper_half_easy_p
= 0;
2199 unsigned int length
= 0;
2204 /* First, see if we can finish with one insn. */
2205 if ((TARGET_H8300H
|| TARGET_H8300S
)
2209 if (REG_P (operands
[2]))
2216 /* Take care of the lower byte. */
2220 /* Take care of the upper byte. */
2226 if (TARGET_H8300H
|| TARGET_H8300S
)
2228 /* Determine if the lower half can be taken care of in no more
2230 lower_half_easy_p
= (b0
== 0
2232 || (code
!= IOR
&& w0
== 0xffff));
2234 /* Determine if the upper half can be taken care of in no more
2236 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
2237 || (code
== AND
&& w1
== 0xff00));
2240 /* Check if doing everything with one insn is no worse than
2241 using multiple insns. */
2242 if ((TARGET_H8300H
|| TARGET_H8300S
)
2243 && w0
!= 0 && w1
!= 0
2244 && !(lower_half_easy_p
&& upper_half_easy_p
)
2245 && !(code
== IOR
&& w1
== 0xffff
2246 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
2248 if (REG_P (operands
[2]))
2255 /* Take care of the lower and upper words individually. For
2256 each word, we try different methods in the order of
2258 1) the special insn (in case of AND or XOR),
2259 2) the word-wise insn, and
2260 3) The byte-wise insn. */
2262 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
2266 else if ((TARGET_H8300H
|| TARGET_H8300S
)
2282 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
2286 else if ((TARGET_H8300H
|| TARGET_H8300S
)
2289 && (w0
& 0x8000) != 0)
2293 else if ((TARGET_H8300H
|| TARGET_H8300S
)
2299 else if (TARGET_H8300H
|| TARGET_H8300S
)
2321 compute_logical_op_cc (enum machine_mode mode
, rtx
*operands
)
2323 /* Figure out the logical op that we need to perform. */
2324 enum rtx_code code
= GET_CODE (operands
[3]);
2325 /* Pretend that every byte is affected if both operands are registers. */
2326 const unsigned HOST_WIDE_INT intval
=
2327 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
2328 ? INTVAL (operands
[2]) : 0x55555555);
2329 /* The determinant of the algorithm. If we perform an AND, 0
2330 affects a bit. Otherwise, 1 affects a bit. */
2331 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
2332 /* Break up DET into pieces. */
2333 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
2334 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
2335 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
2336 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
2337 int lower_half_easy_p
= 0;
2338 int upper_half_easy_p
= 0;
2339 /* Condition code. */
2340 enum attr_cc cc
= CC_CLOBBER
;
2345 /* First, see if we can finish with one insn. */
2346 if ((TARGET_H8300H
|| TARGET_H8300S
)
2354 if (TARGET_H8300H
|| TARGET_H8300S
)
2356 /* Determine if the lower half can be taken care of in no more
2358 lower_half_easy_p
= (b0
== 0
2360 || (code
!= IOR
&& w0
== 0xffff));
2362 /* Determine if the upper half can be taken care of in no more
2364 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
2365 || (code
== AND
&& w1
== 0xff00));
2368 /* Check if doing everything with one insn is no worse than
2369 using multiple insns. */
2370 if ((TARGET_H8300H
|| TARGET_H8300S
)
2371 && w0
!= 0 && w1
!= 0
2372 && !(lower_half_easy_p
&& upper_half_easy_p
)
2373 && !(code
== IOR
&& w1
== 0xffff
2374 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
2380 if ((TARGET_H8300H
|| TARGET_H8300S
)
2383 && (w0
& 0x8000) != 0)
2397 We devote a fair bit of code to getting efficient shifts since we
2398 can only shift one bit at a time on the H8/300 and H8/300H and only
2399 one or two bits at a time on the H8S.
2401 All shift code falls into one of the following ways of
2404 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2405 when a straight line shift is about the same size or smaller than
2408 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2409 off the bits we don't need. This is used when only a few of the
2410 bits in the original value will survive in the shifted value.
2412 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2413 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2414 shifts can be added if the shift count is slightly more than 8 or
2415 16. This case also includes other oddballs that are not worth
2418 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2420 For each shift count, we try to use code that has no trade-off
2421 between code size and speed whenever possible.
2423 If the trade-off is unavoidable, we try to be reasonable.
2424 Specifically, the fastest version is one instruction longer than
2425 the shortest version, we take the fastest version. We also provide
2426 the use a way to switch back to the shortest version with -Os.
2428 For the details of the shift algorithms for various shift counts,
2429 refer to shift_alg_[qhs]i. */
2432 nshift_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2434 switch (GET_CODE (x
))
2446 /* Emit code to do shifts. */
2449 expand_a_shift (enum machine_mode mode
, int code
, rtx operands
[])
2451 emit_move_insn (operands
[0], operands
[1]);
2453 /* Need a loop to get all the bits we want - we generate the
2454 code at emit time, but need to allocate a scratch reg now. */
2456 emit_insn (gen_rtx_PARALLEL
2459 gen_rtx_SET (VOIDmode
, operands
[0],
2460 gen_rtx (code
, mode
, operands
[0],
2462 gen_rtx_CLOBBER (VOIDmode
,
2463 gen_rtx_SCRATCH (QImode
)))));
2466 /* Symbols of the various modes which can be used as indices. */
2470 QIshift
, HIshift
, SIshift
2473 /* For single bit shift insns, record assembler and what bits of the
2474 condition code are valid afterwards (represented as various CC_FOO
2475 bits, 0 means CC isn't left in a usable state). */
2479 const char *const assembler
;
2483 /* Assembler instruction shift table.
2485 These tables are used to look up the basic shifts.
2486 They are indexed by cpu, shift_type, and mode. */
2488 static const struct shift_insn shift_one
[2][3][3] =
2494 { "shll\t%X0", CC_SET_ZNV
},
2495 { "add.w\t%T0,%T0", CC_SET_ZN
},
2496 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
2498 /* SHIFT_LSHIFTRT */
2500 { "shlr\t%X0", CC_SET_ZNV
},
2501 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
2502 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
2504 /* SHIFT_ASHIFTRT */
2506 { "shar\t%X0", CC_SET_ZNV
},
2507 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
2508 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
2515 { "shll.b\t%X0", CC_SET_ZNV
},
2516 { "shll.w\t%T0", CC_SET_ZNV
},
2517 { "shll.l\t%S0", CC_SET_ZNV
}
2519 /* SHIFT_LSHIFTRT */
2521 { "shlr.b\t%X0", CC_SET_ZNV
},
2522 { "shlr.w\t%T0", CC_SET_ZNV
},
2523 { "shlr.l\t%S0", CC_SET_ZNV
}
2525 /* SHIFT_ASHIFTRT */
2527 { "shar.b\t%X0", CC_SET_ZNV
},
2528 { "shar.w\t%T0", CC_SET_ZNV
},
2529 { "shar.l\t%S0", CC_SET_ZNV
}
2534 static const struct shift_insn shift_two
[3][3] =
2538 { "shll.b\t#2,%X0", CC_SET_ZNV
},
2539 { "shll.w\t#2,%T0", CC_SET_ZNV
},
2540 { "shll.l\t#2,%S0", CC_SET_ZNV
}
2542 /* SHIFT_LSHIFTRT */
2544 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
2545 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
2546 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
2548 /* SHIFT_ASHIFTRT */
2550 { "shar.b\t#2,%X0", CC_SET_ZNV
},
2551 { "shar.w\t#2,%T0", CC_SET_ZNV
},
2552 { "shar.l\t#2,%S0", CC_SET_ZNV
}
2556 /* Rotates are organized by which shift they'll be used in implementing.
2557 There's no need to record whether the cc is valid afterwards because
2558 it is the AND insn that will decide this. */
2560 static const char *const rotate_one
[2][3][3] =
2567 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2570 /* SHIFT_LSHIFTRT */
2573 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2576 /* SHIFT_ASHIFTRT */
2579 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2591 /* SHIFT_LSHIFTRT */
2597 /* SHIFT_ASHIFTRT */
2606 static const char *const rotate_two
[3][3] =
2614 /* SHIFT_LSHIFTRT */
2620 /* SHIFT_ASHIFTRT */
2629 /* Shift algorithm. */
2632 /* The number of bits to be shifted by shift1 and shift2. Valid
2633 when ALG is SHIFT_SPECIAL. */
2634 unsigned int remainder
;
2636 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2637 const char *special
;
2639 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2640 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2643 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2644 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2647 /* CC status for SHIFT_INLINE. */
2650 /* CC status for SHIFT_SPECIAL. */
2654 static void get_shift_alg (enum shift_type
,
2655 enum shift_mode
, unsigned int,
2656 struct shift_info
*);
2658 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2659 best algorithm for doing the shift. The assembler code is stored
2660 in the pointers in INFO. We achieve the maximum efficiency in most
2661 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2662 SImode in particular have a lot of room to optimize.
2664 We first determine the strategy of the shift algorithm by a table
2665 lookup. If that tells us to use a hand crafted assembly code, we
2666 go into the big switch statement to find what that is. Otherwise,
2667 we resort to a generic way, such as inlining. In either case, the
2668 result is returned through INFO. */
2671 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
2672 unsigned int count
, struct shift_info
*info
)
2676 /* Find the target CPU. */
2679 else if (TARGET_H8300H
)
2684 /* Find the shift algorithm. */
2685 info
->alg
= SHIFT_LOOP
;
2689 if (count
< GET_MODE_BITSIZE (QImode
))
2690 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
2694 if (count
< GET_MODE_BITSIZE (HImode
))
2695 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
2699 if (count
< GET_MODE_BITSIZE (SImode
))
2700 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
2707 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2711 info
->remainder
= count
;
2715 /* It is up to the caller to know that looping clobbers cc. */
2716 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
2717 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
2718 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
2722 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
2723 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
2724 info
->cc_inline
= CC_CLOBBER
;
2728 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2729 info
->remainder
= 0;
2730 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
2731 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
2732 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
2733 info
->cc_special
= CC_CLOBBER
;
2737 /* Here we only deal with SHIFT_SPECIAL. */
2741 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2742 through the entire value. */
2743 if (shift_type
== SHIFT_ASHIFTRT
&& count
== 7)
2745 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
2757 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2759 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2761 case SHIFT_LSHIFTRT
:
2763 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2765 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2767 case SHIFT_ASHIFTRT
:
2768 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2772 else if ((8 <= count
&& count
<= 13)
2773 || (TARGET_H8300S
&& count
== 14))
2775 info
->remainder
= count
- 8;
2780 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2782 case SHIFT_LSHIFTRT
:
2785 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2786 info
->shift1
= "shlr.b\t%s0";
2787 info
->cc_inline
= CC_SET_ZNV
;
2791 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
2792 info
->cc_special
= CC_SET_ZNV
;
2795 case SHIFT_ASHIFTRT
:
2798 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2799 info
->shift1
= "shar.b\t%s0";
2803 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
2804 info
->cc_special
= CC_SET_ZNV
;
2809 else if (count
== 14)
2815 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
2817 case SHIFT_LSHIFTRT
:
2819 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
2821 case SHIFT_ASHIFTRT
:
2823 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
2824 else if (TARGET_H8300H
)
2826 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
2827 info
->cc_special
= CC_SET_ZNV
;
2829 else /* TARGET_H8300S */
2834 else if (count
== 15)
2839 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
2841 case SHIFT_LSHIFTRT
:
2842 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
2844 case SHIFT_ASHIFTRT
:
2845 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2852 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
2854 info
->remainder
= count
- 8;
2859 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2861 case SHIFT_LSHIFTRT
:
2862 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2863 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
2865 case SHIFT_ASHIFTRT
:
2866 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2870 else if (count
== 8 && !TARGET_H8300
)
2875 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2877 case SHIFT_LSHIFTRT
:
2878 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2880 case SHIFT_ASHIFTRT
:
2881 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2885 else if (count
== 15 && TARGET_H8300
)
2891 case SHIFT_LSHIFTRT
:
2892 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
2894 case SHIFT_ASHIFTRT
:
2895 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
2899 else if (count
== 15 && !TARGET_H8300
)
2904 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
2905 info
->cc_special
= CC_SET_ZNV
;
2907 case SHIFT_LSHIFTRT
:
2908 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
2909 info
->cc_special
= CC_SET_ZNV
;
2911 case SHIFT_ASHIFTRT
:
2915 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
2916 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
2917 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
2919 info
->remainder
= count
- 16;
2924 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2926 info
->shift1
= "add.w\t%e0,%e0";
2928 case SHIFT_LSHIFTRT
:
2931 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2932 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
2936 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
2937 info
->cc_special
= CC_SET_ZNV
;
2940 case SHIFT_ASHIFTRT
:
2943 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2944 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
2948 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
2949 info
->cc_special
= CC_SET_ZNV
;
2954 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
2956 info
->remainder
= count
- 24;
2961 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
2962 info
->shift1
= "shll.b\t%z0";
2963 info
->cc_inline
= CC_SET_ZNV
;
2965 case SHIFT_LSHIFTRT
:
2966 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
2967 info
->shift1
= "shlr.b\t%w0";
2968 info
->cc_inline
= CC_SET_ZNV
;
2970 case SHIFT_ASHIFTRT
:
2971 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
2972 info
->shift1
= "shar.b\t%w0";
2973 info
->cc_inline
= CC_SET_ZNV
;
2977 else if ((TARGET_H8300H
&& count
== 24)
2978 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
2980 info
->remainder
= count
- 24;
2985 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2987 case SHIFT_LSHIFTRT
:
2988 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2989 info
->cc_special
= CC_SET_ZNV
;
2991 case SHIFT_ASHIFTRT
:
2992 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2993 info
->cc_special
= CC_SET_ZNV
;
2997 else if (!TARGET_H8300
&& count
== 28)
3003 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3005 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3007 case SHIFT_LSHIFTRT
:
3010 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3011 info
->cc_special
= CC_SET_ZNV
;
3014 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3016 case SHIFT_ASHIFTRT
:
3020 else if (!TARGET_H8300
&& count
== 29)
3026 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3028 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3030 case SHIFT_LSHIFTRT
:
3033 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3034 info
->cc_special
= CC_SET_ZNV
;
3038 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3039 info
->cc_special
= CC_SET_ZNV
;
3042 case SHIFT_ASHIFTRT
:
3046 else if (!TARGET_H8300
&& count
== 30)
3052 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3054 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3056 case SHIFT_LSHIFTRT
:
3058 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3060 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3062 case SHIFT_ASHIFTRT
:
3066 else if (count
== 31)
3073 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3075 case SHIFT_LSHIFTRT
:
3076 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3078 case SHIFT_ASHIFTRT
:
3079 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3088 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3089 info
->cc_special
= CC_SET_ZNV
;
3091 case SHIFT_LSHIFTRT
:
3092 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3093 info
->cc_special
= CC_SET_ZNV
;
3095 case SHIFT_ASHIFTRT
:
3096 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3097 info
->cc_special
= CC_SET_ZNV
;
3110 info
->shift2
= NULL
;
3113 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3114 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3117 h8300_shift_needs_scratch_p (int count
, enum machine_mode mode
)
3122 if (GET_MODE_BITSIZE (mode
) <= count
)
3125 /* Find out the target CPU. */
3128 else if (TARGET_H8300H
)
3133 /* Find the shift algorithm. */
3137 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
3138 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
3139 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
3143 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
3144 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
3145 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
3149 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
3150 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
3151 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
3158 /* On H8/300H, count == 8 uses a scratch register. */
3159 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
3160 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
3163 /* Emit the assembler code for doing shifts. */
3166 output_a_shift (rtx
*operands
)
3168 static int loopend_lab
;
3169 rtx shift
= operands
[3];
3170 enum machine_mode mode
= GET_MODE (shift
);
3171 enum rtx_code code
= GET_CODE (shift
);
3172 enum shift_type shift_type
;
3173 enum shift_mode shift_mode
;
3174 struct shift_info info
;
3181 shift_mode
= QIshift
;
3184 shift_mode
= HIshift
;
3187 shift_mode
= SIshift
;
3196 shift_type
= SHIFT_ASHIFTRT
;
3199 shift_type
= SHIFT_LSHIFTRT
;
3202 shift_type
= SHIFT_ASHIFT
;
3208 if (GET_CODE (operands
[2]) != CONST_INT
)
3210 /* This case must be taken care of by one of the two splitters
3211 that convert a variable shift into a loop. */
3216 int n
= INTVAL (operands
[2]);
3218 /* If the count is negative, make it 0. */
3221 /* If the count is too big, truncate it.
3222 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3223 do the intuitive thing. */
3224 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
3225 n
= GET_MODE_BITSIZE (mode
);
3227 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
3232 output_asm_insn (info
.special
, operands
);
3238 /* Emit two bit shifts first. */
3239 if (info
.shift2
!= NULL
)
3241 for (; n
> 1; n
-= 2)
3242 output_asm_insn (info
.shift2
, operands
);
3245 /* Now emit one bit shifts for any residual. */
3247 output_asm_insn (info
.shift1
, operands
);
3252 int m
= GET_MODE_BITSIZE (mode
) - n
;
3253 const int mask
= (shift_type
== SHIFT_ASHIFT
3254 ? ((1 << m
) - 1) << n
3258 /* Not all possibilities of rotate are supported. They shouldn't
3259 be generated, but let's watch for 'em. */
3260 if (info
.shift1
== 0)
3263 /* Emit two bit rotates first. */
3264 if (info
.shift2
!= NULL
)
3266 for (; m
> 1; m
-= 2)
3267 output_asm_insn (info
.shift2
, operands
);
3270 /* Now single bit rotates for any residual. */
3272 output_asm_insn (info
.shift1
, operands
);
3274 /* Now mask off the high bits. */
3276 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
3277 else if (mode
== HImode
&& (TARGET_H8300H
|| TARGET_H8300S
))
3278 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
3282 output_asm_insn (insn_buf
, operands
);
3287 /* A loop to shift by a "large" constant value.
3288 If we have shift-by-2 insns, use them. */
3289 if (info
.shift2
!= NULL
)
3291 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
3292 names_big
[REGNO (operands
[4])]);
3293 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
3294 output_asm_insn (info
.shift2
, operands
);
3295 output_asm_insn ("add #0xff,%X4", operands
);
3296 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
3298 output_asm_insn (info
.shift1
, operands
);
3302 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
3303 names_big
[REGNO (operands
[4])]);
3304 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
3305 output_asm_insn (info
.shift1
, operands
);
3306 output_asm_insn ("add #0xff,%X4", operands
);
3307 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
3318 h8300_asm_insn_count (const char *template)
3320 unsigned int count
= 1;
3322 for (; *template; template++)
3323 if (*template == '\n')
3330 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
3332 rtx shift
= operands
[3];
3333 enum machine_mode mode
= GET_MODE (shift
);
3334 enum rtx_code code
= GET_CODE (shift
);
3335 enum shift_type shift_type
;
3336 enum shift_mode shift_mode
;
3337 struct shift_info info
;
3338 unsigned int wlength
= 0;
3343 shift_mode
= QIshift
;
3346 shift_mode
= HIshift
;
3349 shift_mode
= SIshift
;
3358 shift_type
= SHIFT_ASHIFTRT
;
3361 shift_type
= SHIFT_LSHIFTRT
;
3364 shift_type
= SHIFT_ASHIFT
;
3370 if (GET_CODE (operands
[2]) != CONST_INT
)
3372 /* Get the assembler code to do one shift. */
3373 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
3375 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
3379 int n
= INTVAL (operands
[2]);
3381 /* If the count is negative, make it 0. */
3384 /* If the count is too big, truncate it.
3385 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3386 do the intuitive thing. */
3387 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
3388 n
= GET_MODE_BITSIZE (mode
);
3390 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
3395 wlength
+= h8300_asm_insn_count (info
.special
);
3397 /* Every assembly instruction used in SHIFT_SPECIAL case
3398 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3399 see xor.l, we just pretend that xor.l counts as two insns
3400 so that the insn length will be computed correctly. */
3401 if (strstr (info
.special
, "xor.l") != NULL
)
3409 if (info
.shift2
!= NULL
)
3411 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
3415 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
3421 int m
= GET_MODE_BITSIZE (mode
) - n
;
3423 /* Not all possibilities of rotate are supported. They shouldn't
3424 be generated, but let's watch for 'em. */
3425 if (info
.shift1
== 0)
3428 if (info
.shift2
!= NULL
)
3430 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
3434 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
3436 /* Now mask off the high bits. */
3457 /* A loop to shift by a "large" constant value.
3458 If we have shift-by-2 insns, use them. */
3459 if (info
.shift2
!= NULL
)
3461 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
3463 wlength
+= h8300_asm_insn_count (info
.shift1
);
3467 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
3478 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
3480 rtx shift
= operands
[3];
3481 enum machine_mode mode
= GET_MODE (shift
);
3482 enum rtx_code code
= GET_CODE (shift
);
3483 enum shift_type shift_type
;
3484 enum shift_mode shift_mode
;
3485 struct shift_info info
;
3490 shift_mode
= QIshift
;
3493 shift_mode
= HIshift
;
3496 shift_mode
= SIshift
;
3505 shift_type
= SHIFT_ASHIFTRT
;
3508 shift_type
= SHIFT_LSHIFTRT
;
3511 shift_type
= SHIFT_ASHIFT
;
3517 if (GET_CODE (operands
[2]) != CONST_INT
)
3519 /* This case must be taken care of by one of the two splitters
3520 that convert a variable shift into a loop. */
3525 int n
= INTVAL (operands
[2]);
3527 /* If the count is negative, make it 0. */
3530 /* If the count is too big, truncate it.
3531 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3532 do the intuitive thing. */
3533 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
3534 n
= GET_MODE_BITSIZE (mode
);
3536 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
3541 if (info
.remainder
== 0)
3542 return info
.cc_special
;
3547 return info
.cc_inline
;
3550 /* This case always ends with an and instruction. */
3554 /* A loop to shift by a "large" constant value.
3555 If we have shift-by-2 insns, use them. */
3556 if (info
.shift2
!= NULL
)
3559 return info
.cc_inline
;
3569 /* A rotation by a non-constant will cause a loop to be generated, in
3570 which a rotation by one bit is used. A rotation by a constant,
3571 including the one in the loop, will be taken care of by
3572 emit_a_rotate () at the insn emit time. */
3575 expand_a_rotate (enum rtx_code code
, rtx operands
[])
3577 rtx dst
= operands
[0];
3578 rtx src
= operands
[1];
3579 rtx rotate_amount
= operands
[2];
3580 enum machine_mode mode
= GET_MODE (dst
);
3583 /* We rotate in place. */
3584 emit_move_insn (dst
, src
);
3586 if (GET_CODE (rotate_amount
) != CONST_INT
)
3588 rtx counter
= gen_reg_rtx (QImode
);
3589 rtx start_label
= gen_label_rtx ();
3590 rtx end_label
= gen_label_rtx ();
3592 /* If the rotate amount is less than or equal to 0,
3593 we go out of the loop. */
3594 emit_cmp_and_jump_insns (rotate_amount
, GEN_INT (0), LE
, NULL_RTX
,
3595 QImode
, 0, end_label
);
3597 /* Initialize the loop counter. */
3598 emit_move_insn (counter
, rotate_amount
);
3600 emit_label (start_label
);
3602 /* Rotate by one bit. */
3603 tmp
= gen_rtx (code
, mode
, dst
, GEN_INT (1));
3604 emit_insn (gen_rtx_SET (mode
, dst
, tmp
));
3606 /* Decrement the counter by 1. */
3607 tmp
= gen_rtx_PLUS (QImode
, counter
, GEN_INT (-1));
3608 emit_insn (gen_rtx_SET (VOIDmode
, counter
, tmp
));
3610 /* If the loop counter is nonzero, we go back to the beginning
3612 emit_cmp_and_jump_insns (counter
, GEN_INT (0), NE
, NULL_RTX
, QImode
, 1,
3615 emit_label (end_label
);
3619 /* Rotate by AMOUNT bits. */
3620 tmp
= gen_rtx (code
, mode
, dst
, rotate_amount
);
3621 emit_insn (gen_rtx_SET (mode
, dst
, tmp
));
3627 /* Emit rotate insns. */
3630 emit_a_rotate (enum rtx_code code
, rtx
*operands
)
3632 rtx dst
= operands
[0];
3633 rtx rotate_amount
= operands
[2];
3634 enum shift_mode rotate_mode
;
3635 enum shift_type rotate_type
;
3636 const char *insn_buf
;
3639 enum machine_mode mode
= GET_MODE (dst
);
3641 if (GET_CODE (rotate_amount
) != CONST_INT
)
3647 rotate_mode
= QIshift
;
3650 rotate_mode
= HIshift
;
3653 rotate_mode
= SIshift
;
3662 rotate_type
= SHIFT_ASHIFT
;
3665 rotate_type
= SHIFT_LSHIFTRT
;
3671 amount
= INTVAL (rotate_amount
);
3673 /* Clean up AMOUNT. */
3676 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
3677 amount
= GET_MODE_BITSIZE (mode
);
3679 /* Determine the faster direction. After this phase, amount will be
3680 at most a half of GET_MODE_BITSIZE (mode). */
3681 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
3683 /* Flip the direction. */
3684 amount
= GET_MODE_BITSIZE (mode
) - amount
;
3686 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
3689 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3690 boost up the rotation. */
3691 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
3692 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
3693 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
3694 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
3695 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
3700 /* This code works on any family. */
3701 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3702 output_asm_insn (insn_buf
, operands
);
3706 /* This code works on the H8/300H and H8S. */
3707 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3708 output_asm_insn (insn_buf
, operands
);
3715 /* Adjust AMOUNT and flip the direction. */
3716 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
3718 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
3721 /* Emit rotate insns. */
3722 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
3725 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
3727 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
3729 for (; amount
>= bits
; amount
-= bits
)
3730 output_asm_insn (insn_buf
, operands
);
3736 /* Fix the operands of a gen_xxx so that it could become a bit
3740 fix_bit_operand (rtx
*operands
, int what
, enum rtx_code type
)
3742 /* The bit_operand predicate accepts any memory during RTL generation, but
3743 only 'U' memory afterwards, so if this is a MEM operand, we must force
3744 it to be valid for 'U' by reloading the address. */
3746 if ((what
== 0 && single_zero_operand (operands
[2], QImode
))
3747 || (what
== 1 && single_one_operand (operands
[2], QImode
)))
3749 /* OK to have a memory dest. */
3750 if (GET_CODE (operands
[0]) == MEM
3751 && !EXTRA_CONSTRAINT (operands
[0], 'U'))
3753 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
3754 copy_to_mode_reg (Pmode
,
3755 XEXP (operands
[0], 0)));
3756 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
3760 if (GET_CODE (operands
[1]) == MEM
3761 && !EXTRA_CONSTRAINT (operands
[1], 'U'))
3763 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
3764 copy_to_mode_reg (Pmode
,
3765 XEXP (operands
[1], 0)));
3766 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
3772 /* Dest and src op must be register. */
3774 operands
[1] = force_reg (QImode
, operands
[1]);
3776 rtx res
= gen_reg_rtx (QImode
);
3777 emit_insn (gen_rtx_SET (VOIDmode
, res
,
3778 gen_rtx (type
, QImode
, operands
[1], operands
[2])));
3779 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], res
));
3784 /* Return nonzero if FUNC is an interrupt function as specified
3785 by the "interrupt" attribute. */
3788 h8300_interrupt_function_p (tree func
)
3792 if (TREE_CODE (func
) != FUNCTION_DECL
)
3795 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
3796 return a
!= NULL_TREE
;
3799 /* Return nonzero if FUNC is an OS_Task function as specified
3800 by the "OS_Task" attribute. */
3803 h8300_os_task_function_p (tree func
)
3807 if (TREE_CODE (func
) != FUNCTION_DECL
)
3810 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
3811 return a
!= NULL_TREE
;
3814 /* Return nonzero if FUNC is a monitor function as specified
3815 by the "monitor" attribute. */
3818 h8300_monitor_function_p (tree func
)
3822 if (TREE_CODE (func
) != FUNCTION_DECL
)
3825 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
3826 return a
!= NULL_TREE
;
3829 /* Return nonzero if FUNC is a function that should be called
3830 through the function vector. */
3833 h8300_funcvec_function_p (tree func
)
3837 if (TREE_CODE (func
) != FUNCTION_DECL
)
3840 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
3841 return a
!= NULL_TREE
;
3844 /* Return nonzero if DECL is a variable that's in the eight bit
3848 h8300_eightbit_data_p (tree decl
)
3852 if (TREE_CODE (decl
) != VAR_DECL
)
3855 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
3856 return a
!= NULL_TREE
;
3859 /* Return nonzero if DECL is a variable that's in the tiny
3863 h8300_tiny_data_p (tree decl
)
3867 if (TREE_CODE (decl
) != VAR_DECL
)
3870 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
3871 return a
!= NULL_TREE
;
3874 /* Generate an 'interrupt_handler' attribute for decls. */
3877 h8300_insert_attributes (tree node
, tree
*attributes
)
3879 if (!pragma_interrupt
3880 || TREE_CODE (node
) != FUNCTION_DECL
)
3883 pragma_interrupt
= 0;
3885 /* Add an 'interrupt_handler' attribute. */
3886 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
3890 /* Supported attributes:
3892 interrupt_handler: output a prologue and epilogue suitable for an
3895 function_vector: This function should be called through the
3898 eightbit_data: This variable lives in the 8-bit data area and can
3899 be referenced with 8-bit absolute memory addresses.
3901 tiny_data: This variable lives in the tiny data area and can be
3902 referenced with 16-bit absolute memory references. */
3904 const struct attribute_spec h8300_attribute_table
[] =
3906 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3907 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
3908 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
3909 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
3910 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
3911 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute
},
3912 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute
},
3913 { NULL
, 0, 0, false, false, false, NULL
}
3917 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
3918 struct attribute_spec.handler. */
3920 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
3921 tree args ATTRIBUTE_UNUSED
,
3922 int flags ATTRIBUTE_UNUSED
,
3925 if (TREE_CODE (*node
) != FUNCTION_DECL
)
3927 warning ("`%s' attribute only applies to functions",
3928 IDENTIFIER_POINTER (name
));
3929 *no_add_attrs
= true;
3935 /* Handle an "eightbit_data" attribute; arguments as in
3936 struct attribute_spec.handler. */
3938 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
3939 tree args ATTRIBUTE_UNUSED
,
3940 int flags ATTRIBUTE_UNUSED
,
3945 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
3947 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
3951 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
3952 *no_add_attrs
= true;
3958 /* Handle an "tiny_data" attribute; arguments as in
3959 struct attribute_spec.handler. */
3961 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
3962 tree args ATTRIBUTE_UNUSED
,
3963 int flags ATTRIBUTE_UNUSED
,
3968 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
3970 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
3974 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
3975 *no_add_attrs
= true;
3981 /* Mark function vectors, and various small data objects. */
3984 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
3986 int extra_flags
= 0;
3988 default_encode_section_info (decl
, rtl
, first
);
3990 if (TREE_CODE (decl
) == FUNCTION_DECL
3991 && h8300_funcvec_function_p (decl
))
3992 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
3993 else if (TREE_CODE (decl
) == VAR_DECL
3994 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
3996 if (h8300_eightbit_data_p (decl
))
3997 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
3998 else if (first
&& h8300_tiny_data_p (decl
))
3999 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
4003 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
4007 output_simode_bld (int bild
, rtx operands
[])
4011 /* Clear the destination register. */
4012 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
4014 /* Now output the bit load or bit inverse load, and store it in
4017 output_asm_insn ("bild\t%Z2,%Y1", operands
);
4019 output_asm_insn ("bld\t%Z2,%Y1", operands
);
4021 output_asm_insn ("bst\t#0,%w0", operands
);
4025 /* Determine if we can clear the destination first. */
4026 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
4027 && REGNO (operands
[0]) != REGNO (operands
[1]));
4030 output_asm_insn ("sub.l\t%S0,%S0", operands
);
4032 /* Output the bit load or bit inverse load. */
4034 output_asm_insn ("bild\t%Z2,%Y1", operands
);
4036 output_asm_insn ("bld\t%Z2,%Y1", operands
);
4039 output_asm_insn ("xor.l\t%S0,%S0", operands
);
4041 /* Perform the bit store. */
4042 output_asm_insn ("bst\t#0,%w0", operands
);
4049 /* Given INSN and its current length LENGTH, return the adjustment
4050 (in bytes) to correctly compute INSN's length.
4052 We use this to get the lengths of various memory references correct. */
4055 h8300_adjust_insn_length (rtx insn
, int length ATTRIBUTE_UNUSED
)
4057 rtx pat
= PATTERN (insn
);
4059 /* We must filter these out before calling get_attr_adjust_length. */
4060 if (GET_CODE (pat
) == USE
4061 || GET_CODE (pat
) == CLOBBER
4062 || GET_CODE (pat
) == SEQUENCE
4063 || GET_CODE (pat
) == ADDR_VEC
4064 || GET_CODE (pat
) == ADDR_DIFF_VEC
)
4067 if (get_attr_adjust_length (insn
) == ADJUST_LENGTH_NO
)
4070 /* Adjust length for reg->mem and mem->reg copies. */
4071 if (GET_CODE (pat
) == SET
4072 && (GET_CODE (SET_SRC (pat
)) == MEM
4073 || GET_CODE (SET_DEST (pat
)) == MEM
))
4075 /* This insn might need a length adjustment. */
4078 if (GET_CODE (SET_SRC (pat
)) == MEM
)
4079 addr
= XEXP (SET_SRC (pat
), 0);
4081 addr
= XEXP (SET_DEST (pat
), 0);
4085 /* On the H8/300, we subtract the difference between the
4086 actual length and the longest one, which is @(d:16,ERs). */
4088 /* @Rs is 2 bytes shorter than the longest. */
4089 if (GET_CODE (addr
) == REG
)
4092 /* @aa:8 is 2 bytes shorter than the longest. */
4093 if (GET_MODE (SET_SRC (pat
)) == QImode
4094 && h8300_eightbit_constant_address_p (addr
))
4099 /* On the H8/300H and H8S, we subtract the difference
4100 between the actual length and the longest one, which is
4103 /* @ERs is 6 bytes shorter than the longest. */
4104 if (GET_CODE (addr
) == REG
)
4107 /* @(d:16,ERs) is 6 bytes shorter than the longest. */
4108 if (GET_CODE (addr
) == PLUS
4109 && GET_CODE (XEXP (addr
, 0)) == REG
4110 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
4111 && INTVAL (XEXP (addr
, 1)) > -32768
4112 && INTVAL (XEXP (addr
, 1)) < 32767)
4115 /* @aa:8 is 6 bytes shorter than the longest. */
4116 if (GET_MODE (SET_SRC (pat
)) == QImode
4117 && h8300_eightbit_constant_address_p (addr
))
4120 /* @aa:16 is 4 bytes shorter than the longest. */
4121 if (h8300_tiny_constant_address_p (addr
))
4124 /* @aa:24 is 2 bytes shorter than the longest. */
4125 if (GET_CODE (addr
) == CONST_INT
)
4130 /* Loading some constants needs adjustment. */
4131 if (GET_CODE (pat
) == SET
4132 && GET_CODE (SET_SRC (pat
)) == CONST_INT
4133 && GET_MODE (SET_DEST (pat
)) == SImode
4134 && INTVAL (SET_SRC (pat
)) != 0)
4136 int val
= INTVAL (SET_SRC (pat
));
4139 && ((val
& 0xffff) == 0
4140 || ((val
>> 16) & 0xffff) == 0))
4143 if (TARGET_H8300H
|| TARGET_H8300S
)
4145 if (val
== (val
& 0xff)
4146 || val
== (val
& 0xff00))
4149 switch (val
& 0xffffffff)
4165 /* Rotations need various adjustments. */
4166 if (GET_CODE (pat
) == SET
4167 && (GET_CODE (SET_SRC (pat
)) == ROTATE
4168 || GET_CODE (SET_SRC (pat
)) == ROTATERT
))
4170 rtx src
= SET_SRC (pat
);
4171 enum machine_mode mode
= GET_MODE (src
);
4175 if (GET_CODE (XEXP (src
, 1)) != CONST_INT
)
4178 amount
= INTVAL (XEXP (src
, 1));
4180 /* Clean up AMOUNT. */
4183 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
4184 amount
= GET_MODE_BITSIZE (mode
);
4186 /* Determine the faster direction. After this phase, amount
4187 will be at most a half of GET_MODE_BITSIZE (mode). */
4188 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
4189 /* Flip the direction. */
4190 amount
= GET_MODE_BITSIZE (mode
) - amount
;
4192 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4193 boost up the rotation. */
4194 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
4195 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
4196 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
4197 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
4198 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
4200 /* Adjust AMOUNT and flip the direction. */
4201 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
4205 /* We use 2-bit rotations on the H8S. */
4207 amount
= amount
/ 2 + amount
% 2;
4209 /* The H8/300 uses three insns to rotate one bit, taking 6
4211 states
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
4213 return -(20 - states
);
4219 #ifndef OBJECT_FORMAT_ELF
4221 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
)
4223 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4224 fprintf (asm_out_file
, "\t.section %s\n", name
);
4226 #endif /* ! OBJECT_FORMAT_ELF */
4228 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4229 which is a special case of the 'R' operand. */
4232 h8300_eightbit_constant_address_p (rtx x
)
4234 /* The ranges of the 8-bit area. */
4235 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
4236 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
4237 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
4238 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
4239 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
4240 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
4242 unsigned HOST_WIDE_INT addr
;
4244 /* We accept symbols declared with eightbit_data. */
4245 if (GET_CODE (x
) == SYMBOL_REF
)
4246 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
4248 if (GET_CODE (x
) != CONST_INT
)
4254 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
4255 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
4256 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
4259 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4260 on H8/300H and H8S. */
4263 h8300_tiny_constant_address_p (rtx x
)
4265 /* The ranges of the 16-bit area. */
4266 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
4267 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
4268 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
4269 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
4270 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
4271 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
4272 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
4273 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
4275 unsigned HOST_WIDE_INT addr
;
4277 /* We accept symbols declared with tiny_data. */
4278 if (GET_CODE (x
) == SYMBOL_REF
)
4279 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0;
4281 if (GET_CODE (x
) != CONST_INT
)
4287 || TARGET_NORMAL_MODE
4289 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
4291 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
4295 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
4297 HOST_WIDE_INT offset1
, offset2
;
4305 else if (GET_CODE (addr1
) == PLUS
4306 && REG_P (XEXP (addr1
, 0))
4307 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
4309 reg1
= XEXP (addr1
, 0);
4310 offset1
= INTVAL (XEXP (addr1
, 1));
4320 else if (GET_CODE (addr2
) == PLUS
4321 && REG_P (XEXP (addr2
, 0))
4322 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
4324 reg2
= XEXP (addr2
, 0);
4325 offset2
= INTVAL (XEXP (addr2
, 1));
4330 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
4331 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
4333 && offset1
+ 1 == offset2
)
4339 /* Initialize the GCC target structure. */
4340 #undef TARGET_ATTRIBUTE_TABLE
4341 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4343 #undef TARGET_ASM_ALIGNED_HI_OP
4344 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4346 #undef TARGET_ASM_FUNCTION_EPILOGUE
4347 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
4349 #undef TARGET_ASM_FILE_START
4350 #define TARGET_ASM_FILE_START h8300_file_start
4351 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4352 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4354 #undef TARGET_ASM_FILE_END
4355 #define TARGET_ASM_FILE_END h8300_file_end
4357 #undef TARGET_ENCODE_SECTION_INFO
4358 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4360 #undef TARGET_INSERT_ATTRIBUTES
4361 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4363 #undef TARGET_RTX_COSTS
4364 #define TARGET_RTX_COSTS h8300_rtx_costs
4366 struct gcc_target targetm
= TARGET_INITIALIZER
;