| blob | 31f03fc98786b468855b7d386fee66c257b3a5cc |
1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
53 #include <splay-tree.h>
56 /* Specify which cpu to schedule for. */
60 {
62 };
64 /* Specify how accurate floating-point traps need to be. */
68 /* Specify the floating-point rounding mode. */
72 /* Specify which things cause traps. */
76 /* Specify bit size of immediate TLS offsets. */
80 /* Strings decoded into the above options. */
90 /* Save information from a "cmpxx" operation until the branch or scc is
91 emitted. */
95 /* Nonzero if inside of a function, because the Alpha asm can't
96 handle .files inside of functions. */
100 /* The number of cycles of latency we should assume on memory reads. */
104 /* Whether the function needs the GP. */
108 /* The alias set for prologue/epilogue register save/restore. */
112 /* The assembler name of the current function. */
116 /* The next explicit relocation sequence number. */
120 /* The literal and gpdisp sequence numbers for this insn, as printed
121 by %# and %* respectively. */
127 /* Costs of various operations on the different architectures. */
129 struct alpha_rtx_cost_data
130 {
139 };
142 {
152 },
162 },
172 },
173 };
175 /* Get the number of args of a function in one of two ways. */
176 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
177 #define NUM_ARGS current_function_args_info.num_args
178 #else
179 #define NUM_ARGS current_function_args_info
180 #endif
182 #define REG_PV 27
183 #define REG_RA 26
185 /* Declarations of static functions. */
189 #if TARGET_ABI_OPEN_VMS
191 #endif
197 \f
198 /* Parse target option strings. */
200 void
202 {
209 #define EV5_MASK (MASK_CPU_EV5)
210 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
226 };
228 /* Unicos/Mk doesn't have shared libraries. */
230 {
234 }
236 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
237 floating-point instructions. Make that the default for this target. */
240 else
246 /* We cannot use su and sui qualifiers for conversion instructions on
247 Unicos/Mk. I'm not sure if this is due to assembler or hardware
248 limitations. Right now, we issue a warning if -mieee is specified
249 and then ignore it; eventually, we should either get it right or
250 disable the option altogether. */
253 {
256 else
257 {
260 }
261 }
264 {
267 else
268 {
271 }
272 }
275 {
282 else
284 }
287 {
296 else
298 alpha_fprm_string);
299 }
302 {
311 else
313 }
316 {
323 else
325 }
327 alpha_cpu
332 {
335 {
341 }
344 }
347 {
350 {
353 }
356 }
358 /* Do some sanity checks on the above options. */
361 {
364 }
368 {
371 }
374 {
375 /* Except for EV6 pass 1 (not released), we always have precise
376 arithmetic traps. Which means we can do software completion
377 without minding trap shadows. */
379 }
382 {
384 {
387 }
389 {
392 }
393 }
395 {
404 ;
408 {
410 {
414 };
418 {
422 }
423 else
425 }
427 {
428 /* Most current memories have about 370ns latency. This is
429 a reasonable guess for a fast cpu. */
431 }
432 else
433 {
436 }
439 }
441 /* Default the definition of "small data" to 8 bytes. */
445 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
451 /* Align labels and loops for optimal branching. */
452 /* ??? Kludge these by not doing anything if we don't optimize and also if
453 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
455 {
460 }
464 /* Acquire a unique set number for our register saves and restores. */
467 /* Register variables and functions with the garbage collector. */
469 /* Set up function hooks. */
472 /* Tell the compiler when we're using VAX floating point. */
474 {
478 }
479 }
480 \f
481 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
483 int
485 {
494 }
496 /* Returns 1 if OP is either the constant zero or a register. If a
497 register, it must be in the proper mode unless MODE is VOIDmode. */
499 int
501 {
503 }
505 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
506 any register. */
508 int
510 {
514 }
517 /* Return 1 if OP is an 8-bit constant or any register. */
519 int
521 {
525 }
527 /* Return 1 if OP is a constant or any register. */
529 int
531 {
533 }
535 /* Return 1 if OP is an 8-bit constant. */
537 int
539 {
542 }
544 /* Return 1 if the operand is a valid second operand to an add insn. */
546 int
548 {
550 /* Constraints I, J, O and P are covered by K. */
555 }
557 /* Return 1 if the operand is a valid second operand to a sign-extending
558 add insn. */
560 int
562 {
568 }
570 /* Return 1 if OP is the constant 4 or 8. */
572 int
574 {
577 }
579 /* Return 1 if OP is a valid first operand to an AND insn. */
581 int
583 {
594 }
596 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
598 int
600 {
606 }
608 /* Return 1 if OP is a constant that is the width, in bits, of an integral
609 mode smaller than DImode. */
611 int
613 {
617 }
619 /* Return 1 if OP is a constant that is the width of an integral machine mode
620 smaller than an integer. */
622 int
624 {
626 {
637 }
639 {
642 }
645 }
647 /* Return 1 if OP is a multiple of 8 less than 64. */
649 int
651 {
655 }
657 /* Return 1 if OP is the zero constant for MODE. */
659 int
661 {
663 }
665 /* Return 1 if OP is a hard floating-point register. */
667 int
669 {
676 }
678 /* Return 1 if OP is a hard general register. */
680 int
682 {
689 }
691 /* Return 1 if OP is a register or a constant integer. */
694 int
696 {
699 }
701 /* Return 1 if OP is something that can be reloaded into a register;
702 if it is a MEM, it need not be valid. */
704 int
706 {
711 {
728 }
731 }
733 /* Likewise, but don't accept constants. */
735 int
737 {
745 }
747 /* Return 1 if OP is a valid operand for the source of a move insn. */
749 int
751 {
759 {
764 {
765 /* We don't split symbolic operands into something unintelligable
766 until after reload, but we do not wish non-small, non-global
767 symbolic operands to be reconstructed from their high/lo_sum
768 form. */
773 }
775 /* This handles both the Windows/NT and OSF cases. */
789 /* ... fall through ... */
806 }
809 }
811 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
812 file, and in the same section as the current function. */
814 int
816 {
820 /* Easy test for recursion. */
824 /* Functions that are not local can be overridden, and thus may
825 not share the same gp. */
829 /* If -msmall-data is in effect, assume that there is only one GP
830 for the module, and so any local symbol has this property. We
831 need explicit relocations to be able to enforce this for symbols
832 not defined in this unit of translation, however. */
836 /* Functions that are not external are defined in this UoT,
837 and thus must share the same gp. */
839 }
841 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
843 int
845 {
848 /* Must share the same GP. */
852 /* If profiling is implemented via linker tricks, we can't jump
853 to the nogp alternate entry point. Note that current_function_profile
854 would not be correct, since that doesn't indicate if the target
855 function uses profiling. */
856 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
857 but is approximately correct for the OSF ABIs. Don't know
858 what to do for VMS, NT, or UMK. */
862 /* Must be a function. In some cases folks create thunks in static
863 data structures and then make calls to them. If we allow the
864 direct call, we'll get an error from the linker about !samegp reloc
865 against a symbol without a .prologue directive. */
869 /* Must be "near" so that the branch is assumed to reach. With
870 -msmall-text, this is assumed true of all local symbols. Since
871 we've already checked samegp, locality is already assured. */
875 /* Otherwise, a decl is "near" if it is defined in the same section. */
890 }
892 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
893 a (non-tls) variable known to be defined in this file. */
895 int
897 {
913 }
915 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
916 known to be defined in this file in the small data area. */
918 int
920 {
935 /* ??? There's no encode_section_info equivalent for the rtl
936 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
943 }
945 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
946 not known (or known not) to be defined in this file. */
948 int
950 {
963 }
965 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
967 int
969 {
974 {
976 {
977 /* Disallow virtual registers to cope with pathalogical test cases
978 such as compile/930117-1.c in which the virtual reg decomposes
979 to the frame pointer. Which is a hard reg that is not $27. */
981 }
982 else
984 }
991 }
993 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
994 possibly with an offset. */
996 int
998 {
1009 }
1011 /* Return true if OP is valid for a particular TLS relocation. */
1013 static int
1015 {
1031 {
1034 }
1035 else
1036 {
1039 }
1042 {
1051 }
1052 }
1054 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1056 int
1058 {
1060 }
1062 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1064 int
1066 {
1068 }
1070 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1072 int
1074 {
1076 }
1078 /* Return true if OP is valid for 16-bit TP relative relocations. */
1080 int
1082 {
1084 }
1086 /* Return true if OP is valid for 32-bit TP relative relocations. */
1088 int
1090 {
1092 }
1094 /* Return true if OP is valid for 64-bit TP relative relocations. */
1096 int
1098 {
1100 }
1102 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1103 comparisons are valid in which insn. */
1105 int
1107 {
1115 }
1117 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1118 Here we know which comparisons are valid in which insn. */
1120 int
1122 {
1130 }
1132 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1134 int
1136 {
1146 }
1148 /* Return 1 if OP is a signed comparison operation. */
1150 int
1152 {
1161 }
1163 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1164 Here we know which comparisons are valid in which insn. */
1166 int
1168 {
1175 }
1177 /* Return 1 if this is a divide or modulus operator. */
1179 int
1181 {
1183 {
1189 }
1192 }
1194 /* Return 1 if this memory address is a known aligned register plus
1195 a constant. It must be a valid address. This means that we can do
1196 this as an aligned reference plus some offset.
1198 Take into account what reload will do. */
1200 int
1202 {
1203 rtx base;
1206 {
1212 {
1216 }
1217 }
1224 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1225 sorts of constructs. Dig for the real base register. */
1230 else
1231 {
1235 }
1238 }
1240 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1242 int
1244 {
1245 rtx base;
1248 {
1254 {
1258 }
1259 }
1266 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1267 sorts of constructs. Dig for the real base register. */
1272 else
1273 {
1277 }
1280 }
1282 /* Return 1 if OP is either a register or an unaligned memory location. */
1284 int
1286 {
1288 }
1290 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1292 int
1294 {
1302 }
1304 /* Returns 1 if OP is not an eliminable register.
1306 This exists to cure a pathological abort in the s8addq (et al) patterns,
1308 long foo () { long t; bar(); return (long) &t * 26107; }
1310 which run afoul of a hack in reload to cure a (presumably) similar
1311 problem with lea-type instructions on other targets. But there is
1312 one of us and many of them, so work around the problem by selectively
1313 preventing combine from making the optimization. */
1315 int
1317 {
1325 }
1327 /* Return 1 is OP is a memory location that is not a reference (using
1328 an AND) to an unaligned location. Take into account what reload
1329 will do. */
1331 int
1333 {
1335 {
1341 {
1344 /* This may not have been assigned an equivalent address if it will
1345 be eliminated. In that case, it doesn't matter what we do. */
1348 }
1349 }
1352 }
1354 /* Accept a register, but not a subreg of any kind. This allows us to
1355 avoid pathological cases in reload wrt data movement common in
1356 int->fp conversion. */
1358 int
1360 {
1364 }
1366 /* Recognize an addition operation that includes a constant. Used to
1367 convince reload to canonize (plus (plus reg c1) c2) during register
1368 elimination. */
1370 int
1372 {
1381 }
1383 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1384 the range defined for C in [I-P]. */
1386 bool
1388 {
1390 {
1392 /* An unsigned 8 bit constant. */
1395 /* The constant zero. */
1398 /* A signed 16 bit constant. */
1401 /* A shifted signed 16 bit constant appropriate for LDAH. */
1405 /* A constant that can be AND'ed with using a ZAP insn. */
1408 /* A complemented unsigned 8 bit constant. */
1411 /* A negated unsigned 8 bit constant. */
1414 /* The constant 1, 2 or 3. */
1419 }
1420 }
1422 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1423 matches for C in [GH]. */
1425 bool
1427 {
1429 {
1431 /* The floating point zero constant. */
1436 /* A valid operand of a ZAP insn. */
1443 }
1444 }
1446 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1447 matches for C. */
1449 bool
1451 {
1453 {
1470 }
1471 }
1473 /* Return 1 if this function can directly return via $26. */
1475 int
1477 {
1479 && reload_completed
1484 }
1486 /* Return the ADDR_VEC associated with a tablejump insn. */
1488 rtx
1490 {
1491 rtx tmp;
1503 }
1505 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1507 rtx
1509 {
1513 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1514 there for edge frequency counts from profile data. */
1517 {
1523 {
1529 count++;
1533 }
1534 }
1537 }
1539 /* Return the TLS model to use for SYMBOL. */
1541 static enum tls_model
1543 {
1550 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1555 }
1556 \f
1557 /* Return true if the function DECL will share the same GP as any
1558 function in the current unit of translation. */
1560 static bool
1562 {
1563 /* Functions that are not local can be overridden, and thus may
1564 not share the same gp. */
1568 /* If -msmall-data is in effect, assume that there is only one GP
1569 for the module, and so any local symbol has this property. We
1570 need explicit relocations to be able to enforce this for symbols
1571 not defined in this unit of translation, however. */
1575 /* Functions that are not external are defined in this UoT. */
1576 /* ??? Irritatingly, static functions not yet emitted are still
1577 marked "external". Apply this to non-static functions only. */
1579 }
1581 /* Return true if EXP should be placed in the small data section. */
1583 static bool
1585 {
1586 /* We want to merge strings, so we never consider them small data. */
1591 {
1596 }
1597 else
1598 {
1601 /* If this is an incomplete type with size 0, then we can't put it
1602 in sdata because it might be too big when completed. */
1605 }
1608 }
1610 #if TARGET_ABI_OPEN_VMS
1611 static bool
1613 {
1620 }
1622 #define LINKAGE_SYMBOL_REF_P(X) \
1623 ((GET_CODE (X) == SYMBOL_REF \
1624 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1625 || (GET_CODE (X) == CONST \
1626 && GET_CODE (XEXP (X, 0)) == PLUS \
1627 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1628 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1629 #endif
1631 /* legitimate_address_p recognizes an RTL expression that is a valid
1632 memory address for an instruction. The MODE argument is the
1633 machine mode for the MEM expression that wants to use this address.
1635 For Alpha, we have either a constant address or the sum of a
1636 register and a constant address, or just a register. For DImode,
1637 any of those forms can be surrounded with an AND that clear the
1638 low-order three bits; this is an "unaligned" access. */
1640 bool
1642 {
1643 /* If this is an ldq_u type address, discard the outer AND. */
1650 /* Discard non-paradoxical subregs. */
1656 /* Unadorned general registers are valid. */
1658 && (strict
1663 /* Constant addresses (i.e. +/- 32k) are valid. */
1667 #if TARGET_ABI_OPEN_VMS
1670 #endif
1672 /* Register plus a small constant offset is valid. */
1674 {
1678 /* Discard non-paradoxical subregs. */
1685 {
1695 }
1699 }
1701 /* If we're managing explicit relocations, LO_SUM is valid, as
1702 are small data symbols. */
1704 {
1709 {
1713 /* Discard non-paradoxical subregs. */
1719 /* Must have a valid base register. */
1721 && (strict
1726 /* The symbol must be local. */
1731 }
1732 }
1735 }
1737 /* Build the SYMBOL_REF for __tls_get_addr. */
1741 static rtx
1743 {
1747 }
1749 /* Try machine-dependent ways of modifying an illegitimate address
1750 to be legitimate. If we find one, return the new, valid address. */
1752 rtx
1755 {
1756 HOST_WIDE_INT addend;
1758 /* If the address is (plus reg const_int) and the CONST_INT is not a
1759 valid offset, compute the high part of the constant and add it to
1760 the register. Then our address is (plus temp low-part-const). */
1765 {
1769 }
1771 /* If the address is (const (plus FOO const_int)), find the low-order
1772 part of the CONST_INT. Then load FOO plus any high-order part of the
1773 CONST_INT into a register. Our address is (plus reg low-part-const).
1774 This is done to reduce the number of GOT entries. */
1779 {
1783 }
1785 /* If we have a (plus reg const), emit the load as in (2), then add
1786 the two registers, and finally generate (plus reg low-part-const) as
1787 our address. */
1794 {
1800 }
1802 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1804 {
1808 {
1849 UNSPEC_TLSLDM_CALL);
1856 {
1861 }
1863 {
1868 }
1890 {
1895 }
1897 }
1900 {
1903 else
1904 {
1910 }
1911 }
1912 }
1916 split_addend:
1917 {
1935 }
1936 }
1938 /* We do not allow indirect calls to be optimized into sibling calls, nor
1939 can we allow a call to a function with a different GP to be optimized
1940 into a sibcall. */
1942 static bool
1944 {
1945 /* Can't do indirect tail calls, since we don't know if the target
1946 uses the same GP. */
1950 /* Otherwise, we can make a tail call if the target function shares
1951 the same GP. */
1953 }
1955 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1956 small symbolic operand until after reload. At which point we need
1957 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1958 so that sched2 has the proper dependency information. */
1960 static int
1962 {
1965 /* Don't re-split. */
1970 }
1972 int
1974 {
1976 }
1978 static int
1980 {
1983 /* Don't re-split. */
1988 {
1992 }
1995 }
1997 rtx
1999 {
2003 }
2005 /* Indicate that INSN cannot be duplicated. This is true for any insn
2006 that we've marked with gpdisp relocs, since those have to stay in
2007 1-1 correspondence with one another.
2009 Techinically we could copy them if we could set up a mapping from one
2010 sequence number to another, across the set of insns to be duplicated.
2011 This seems overly complicated and error-prone since interblock motion
2012 from sched-ebb could move one of the pair of insns to a different block. */
2014 static bool
2016 {
2017 rtx pat;
2032 {
2036 }
2038 {
2041 }
2044 }
2047 /* Try a machine-dependent way of reloading an illegitimate address
2048 operand. If we find one, push the reload and return the new rtx. */
2050 rtx
2055 {
2056 /* We must recognize output that we have already generated ourselves. */
2062 {
2067 }
2069 /* We wish to handle large displacements off a base register by
2070 splitting the addend across an ldah and the mem insn. This
2071 cuts number of extra insns needed from 3 to 1. */
2077 {
2080 HOST_WIDE_INT high
2083 /* Check for 32-bit overflow. */
2087 /* Reload the high part into a base reg; leave the low part
2088 in the mem directly. */
2098 }
2101 }
2102 \f
2103 /* Compute a (partial) cost for rtx X. Return true if the complete
2104 cost has been computed, and false if subexpressions should be
2105 scanned. In either case, *TOTAL contains the cost result. */
2107 static bool
2109 {
2114 {
2115 /* If this is an 8-bit constant, return zero since it can be used
2116 nearly anywhere with no cost. If it is a valid operand for an
2117 ADD or AND, likewise return 0 if we know it will be used in that
2118 context. Otherwise, return 2 since it might be used there later.
2119 All other constants take at least two insns. */
2122 {
2125 }
2126 /* FALLTHRU */
2136 else
2148 /* Estimate of cost for call_pal rduniq. */
2150 else
2151 /* Otherwise we do a load from the GOT. */
2161 {
2165 }
2173 else
2180 {
2183 }
2184 /* FALLTHRU */
2194 else
2206 else
2216 {
2219 }
2220 /* FALLTHRU */
2224 {
2227 }
2228 /* FALLTHRU */
2241 }
2242 }
2243 \f
2244 /* REF is an alignable memory location. Place an aligned SImode
2245 reference into *PALIGNED_MEM and the number of bits to shift into
2246 *PBITNUM. SCRATCH is a free register for use in reloading out
2247 of range stack slots. */
2249 void
2251 {
2252 rtx base;
2260 {
2265 }
2266 else
2267 {
2269 }
2274 *paligned_mem
2280 else
2282 }
2284 /* Similar, but just get the address. Handle the two reload cases.
2285 Add EXTRA_OFFSET to the address we return. */
2287 rtx
2289 {
2290 rtx base;
2298 {
2303 }
2304 else
2305 {
2307 }
2313 }
2315 /* On the Alpha, all (non-symbolic) constants except zero go into
2316 a floating-point register via memory. Note that we cannot
2317 return anything that is not a subset of CLASS, and that some
2318 symbolic constants cannot be dropped to memory. */
2320 enum reg_class
2322 {
2323 /* Zero is present in any register class. */
2327 /* These sorts of constants we can easily drop to memory. */
2329 {
2335 }
2337 /* All other kinds of constants should not (and in the case of HIGH
2338 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2339 secondary reload. */
2344 }
2346 /* Loading and storing HImode or QImode values to and from memory
2347 usually requires a scratch register. The exceptions are loading
2348 QImode and HImode from an aligned address to a general register
2349 unless byte instructions are permitted.
2351 We also cannot load an unaligned address or a paradoxical SUBREG
2352 into an FP register.
2354 We also cannot do integral arithmetic into FP regs, as might result
2355 from register elimination into a DImode fp register. */
2357 enum reg_class
2360 {
2362 {
2369 {
2372 }
2373 }
2376 {
2388 }
2391 }
2392 \f
2393 /* Subfunction of the following function. Update the flags of any MEM
2394 found in part of X. */
2396 static void
2398 {
2402 {
2409 unchanging_p);
2414 unchanging_p);
2419 unchanging_p);
2421 unchanging_p);
2428 /* Sadly, we cannot use alias sets because the extra aliasing
2429 produced by the AND interferes. Given that two-byte quantities
2430 are the only thing we would be able to differentiate anyway,
2431 there does not seem to be any point in convoluting the early
2432 out of the alias check. */
2437 }
2438 }
2440 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2441 generated to perform a memory operation, look for any MEMs in either
2442 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2443 volatile flags from REF into each of the MEMs found. If REF is not
2444 a MEM, don't do anything. */
2446 void
2448 {
2458 /* This is only called from alpha.md, after having had something
2459 generated from one of the insn patterns. So if everything is
2460 zero, the pattern is already up-to-date. */
2465 }
2466 \f
2467 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2469 static rtx
2472 {
2475 /* Use a pseudo if highly optimizing and still generating RTL. */
2476 rtx subtarget
2480 /* If this is a sign-extended 32-bit constant, we can do this in at most
2481 three insns, so do it if we have enough insns left. We always have
2482 a sign-extended 32-bit constant when compiling on a narrow machine. */
2486 {
2492 /* If HIGH will be interpreted as negative but the constant is
2493 positive, we must adjust it to do two ldha insns. */
2496 {
2500 }
2503 {
2504 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2505 but that meant that we can't handle INT_MIN on 32-bit machines
2506 (like NT/Alpha), because we recurse indefinitely through
2507 emit_move_insn to gen_movdi. So instead, since we know exactly
2508 what we want, create it explicitly. */
2514 }
2516 {
2519 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2520 This means that if we go through expand_binop, we'll try to
2521 generate extensions, etc, which will require new pseudos, which
2522 will fail during some split phases. The SImode add patterns
2523 still exist, but are not named. So build the insns by hand. */
2526 {
2533 }
2541 }
2542 }
2544 /* If we couldn't do it that way, try some other methods. But if we have
2545 no instructions left, don't bother. Likewise, if this is SImode and
2546 we can't make pseudos, we can't do anything since the expand_binop
2547 and expand_unop calls will widen and try to make pseudos. */
2552 /* Next, see if we can load a related constant and then shift and possibly
2553 negate it to get the constant we want. Try this once each increasing
2554 numbers of insns. */
2557 {
2558 /* First, see if minus some low bits, we've an easy load of
2559 high bits. */
2567 /* Next try complementing. */
2571 /* Next try to form a constant and do a left shift. We can do this
2572 if some low-order bits are zero; the exact_log2 call below tells
2573 us that information. The bits we are shifting out could be any
2574 value, but here we'll just try the 0- and sign-extended forms of
2575 the constant. To try to increase the chance of having the same
2576 constant in more than one insn, start at the highest number of
2577 bits to shift, but try all possibilities in case a ZAPNOT will
2578 be useful. */
2591 /* Now try high-order zero bits. Here we try the shifted-in bits as
2592 all zero and all ones. Be careful to avoid shifting outside the
2593 mode and to avoid shifting outside the host wide int size. */
2594 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2595 confuse the recursive call and set all of the high 32 bits. */
2605 i)))
2610 /* Now try high-order 1 bits. We get that with a sign-extension.
2611 But one bit isn't enough here. Be careful to avoid shifting outside
2612 the mode and to avoid shifting outside the host wide int size. */
2622 i)))
2626 }
2628 #if HOST_BITS_PER_WIDE_INT == 64
2629 /* Finally, see if can load a value into the target that is the same as the
2630 constant except that all bytes that are 0 are changed to be 0xff. If we
2631 can, then we can do a ZAPNOT to obtain the desired constant. */
2638 /* We are only called for SImode and DImode. If this is SImode, ensure that
2639 we are sign extended to a full word. */
2648 #endif
2651 }
2653 /* Try to output insns to set TARGET equal to the constant C if it can be
2654 done in less than N insns. Do all computations in MODE. Returns the place
2655 where the output has been placed if it can be done and the insns have been
2656 emitted. If it would take more than N insns, zero is returned and no
2657 insns and emitted. */
2659 rtx
2662 {
2667 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2668 can't load this constant in one insn, do this in DImode. */
2672 {
2675 }
2677 /* Try 1 insn, then 2, then up to N. */
2679 {
2682 {
2688 }
2689 }
2691 /* Allow for the case where we changed the mode of TARGET. */
2696 }
2698 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2699 fall back to a straight forward decomposition. We do this to avoid
2700 exponential run times encountered when looking for longer sequences
2701 with alpha_emit_set_const. */
2703 rtx
2705 {
2708 /* Decompose the entire word */
2709 #if HOST_BITS_PER_WIDE_INT >= 64
2721 #else
2733 #endif
2735 /* Construct the high word */
2737 {
2741 }
2742 else
2745 /* Shift it into place */
2748 /* Add in the low bits. */
2755 }
2757 /* Expand a move instruction; return true if all work is done.
2758 We don't handle non-bwx subword loads here. */
2760 bool
2762 {
2763 /* If the output is not a register, the input must be. */
2768 /* Allow legitimize_address to perform some simplifications. */
2770 {
2771 rtx tmp;
2773 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2774 compiled at the end of compilation. In the meantime, someone can
2775 re-encode-section-info on some symbol changing it e.g. from global
2776 to local-not-small. If this happens, we'd have emitted a plain
2777 load rather than a high+losum load and not recognize the insn.
2779 So if rtl inlining is in effect, we delay the global/not-global
2780 decision until rest_of_compilation by wrapping it in an
2781 UNSPEC_SYMBOL. */
2783 && rtx_equal_function_value_matters
2785 {
2788 }
2792 {
2797 }
2798 }
2800 /* Early out for non-constants and valid constants. */
2804 /* Split large integers. */
2807 {
2812 {
2815 }
2817 {
2820 }
2821 else
2822 {
2825 }
2834 {
2839 }
2840 }
2842 /* Otherwise we've nothing left but to drop the thing to memory. */
2845 {
2849 }
2850 else
2853 }
2855 /* Expand a non-bwx QImode or HImode move instruction;
2856 return true if all work is done. */
2858 bool
2860 {
2861 /* If the output is not a register, the input must be. */
2865 /* Handle four memory cases, unaligned and aligned for either the input
2866 or the output. The only case where we can be called during reload is
2867 for aligned loads; all other cases require temporaries. */
2877 {
2879 {
2881 {
2883 ? gen_reload_inqi_help
2887 }
2888 else
2889 {
2896 ? gen_aligned_loadqi
2899 }
2900 }
2901 else
2902 {
2903 /* Don't pass these as parameters since that makes the generated
2904 code depend on parameter evaluation order which will cause
2905 bootstrap failures. */
2910 ? gen_unaligned_loadqi
2917 }
2919 }
2929 {
2931 {
2940 }
2941 else
2942 {
2947 ? gen_unaligned_storeqi
2954 }
2956 }
2959 }
2961 /* Generate an unsigned DImode to FP conversion. This is the same code
2962 optabs would emit if we didn't have TFmode patterns.
2964 For SFmode, this is the only construction I've found that can pass
2965 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2966 intermediates will work, because you'll get intermediate rounding
2967 that ruins the end result. Some of this could be fixed by turning
2968 on round-to-positive-infinity, but that requires diddling the fpsr,
2969 which kills performance. I tried turning this around and converting
2970 to a negative number, so that I could turn on /m, but either I did
2971 it wrong or there's something else cause I wound up with the exact
2972 same single-bit error. There is a branch-less form of this same code:
2974 srl $16,1,$1
2975 and $16,1,$2
2976 cmplt $16,0,$3
2977 or $1,$2,$2
2978 cmovge $16,$16,$2
2979 itoft $3,$f10
2980 itoft $2,$f11
2981 cvtqs $f11,$f11
2982 adds $f11,$f11,$f0
2983 fcmoveq $f10,$f11,$f0
2985 I'm not using it because it's the same number of instructions as
2986 this branch-full form, and it has more serialized long latency
2987 instructions on the critical path.
2989 For DFmode, we can avoid rounding errors by breaking up the word
2990 into two pieces, converting them separately, and adding them back:
2992 LC0: .long 0,0x5f800000
2994 itoft $16,$f11
2995 lda $2,LC0
2996 cmplt $16,0,$1
2997 cpyse $f11,$f31,$f10
2998 cpyse $f31,$f11,$f11
2999 s4addq $1,$2,$1
3000 lds $f12,0($1)
3001 cvtqt $f10,$f10
3002 cvtqt $f11,$f11
3003 addt $f12,$f10,$f0
3004 addt $f0,$f11,$f0
3006 This doesn't seem to be a clear-cut win over the optabs form.
3007 It probably all depends on the distribution of numbers being
3008 converted -- in the optabs form, all but high-bit-set has a
3009 much lower minimum execution time. */
3011 void
3013 {
3041 }
3043 /* Generate the comparison for a conditional branch. */
3045 rtx
3047 {
3051 rtx tem;
3054 {
3058 /* X_floating library comparison functions return
3059 -1 unordered
3060 0 false
3061 1 true
3062 Convert the compare against the raw return value. */
3065 {
3082 }
3087 }
3089 /* The general case: fold the comparison code to the types of compares
3090 that we have, choosing the branch as necessary. */
3092 {
3095 /* We have these compares: */
3101 /* These must be reversed. */
3106 /* For FP, we swap them, for INT, we reverse them. */
3108 {
3112 }
3113 else
3114 {
3117 }
3122 }
3125 {
3128 {
3129 /* When we are not as concerned about non-finite values, and we
3130 are comparing against zero, we can branch directly. */
3134 {
3135 /* Undo the swap we probably did just above. */
3139 }
3140 }
3141 else
3142 {
3143 /* ??? We mark the branch mode to be CCmode to prevent the
3144 compare and branch from being combined, since the compare
3145 insn follows IEEE rules that the branch does not. */
3147 }
3148 }
3149 else
3150 {
3153 /* The following optimizations are only for signed compares. */
3155 {
3156 /* Whee. Compare and branch against 0 directly. */
3160 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3161 bypass between logicals and br/cmov on EV5. But we don't want to
3162 force valid immediate constants into registers needlessly. */
3164 {
3170 {
3173 }
3174 }
3175 }
3181 }
3183 /* Emit an initial compare instruction, if necessary. */
3186 {
3189 }
3191 /* Zero the operands. */
3194 /* Return the branch comparison. */
3196 }
3198 /* Certain simplifications can be done to make invalid setcc operations
3199 valid. Return the final comparison, or NULL if we can't work. */
3201 rtx
3203 {
3207 rtx tmp;
3209 /* Zero the operands. */
3213 {
3217 /* X_floating library comparison functions return
3218 -1 unordered
3219 0 false
3220 1 true
3221 Convert the compare against the raw return value. */
3225 else
3236 else
3238 }
3243 /* The general case: fold the comparison code to the types of compares
3244 that we have, choosing the branch as necessary. */
3248 {
3251 /* We have these compares. */
3259 /* FALLTHRU */
3267 /* These normally need swapping, but for integer zero we have
3268 special patterns that recognize swapped operands. */
3279 }
3282 {
3287 }
3289 /* Emit an initial compare instruction, if necessary. */
3291 {
3300 }
3302 /* Return the setcc comparison. */
3304 }
3307 /* Rewrite a comparison against zero CMP of the form
3308 (CODE (cc0) (const_int 0)) so it can be written validly in
3309 a conditional move (if_then_else CMP ...).
3310 If both of the operands that set cc0 are nonzero we must emit
3311 an insn to perform the compare (it can't be done within
3312 the conditional move). */
3314 rtx
3316 {
3322 enum machine_mode cmp_mode
3327 rtx tem;
3329 /* Zero the operands. */
3333 {
3339 /* If we have fp<->int register move instructions, do a cmov by
3340 performing the comparison in fp registers, and move the
3341 zero/nonzero value to integer registers, where we can then
3342 use a normal cmov, or vice-versa. */
3345 {
3347 /* We have these compares. */
3352 /* This must be reversed. */
3357 /* These normally need swapping, but for integer zero we have
3358 special patterns that recognize swapped operands. */
3361 else
3362 {
3366 }
3371 }
3383 }
3385 /* We may be able to use a conditional move directly.
3386 This avoids emitting spurious compares. */
3392 /* We can't put the comparison inside the conditional move;
3393 emit a compare instruction and put that inside the
3394 conditional move. Make sure we emit only comparisons we have;
3395 swap or reverse as necessary. */
3401 {
3403 /* We have these compares: */
3407 /* This must be reversed. */
3413 /* These must be swapped. */
3415 {
3418 }
3423 }
3426 {
3431 }
3433 /* ??? We mark the branch mode to be CCmode to prevent the compare
3434 and cmov from being combined, since the compare insn follows IEEE
3435 rules that the cmov does not. */
3442 }
3444 /* Simplify a conditional move of two constants into a setcc with
3445 arithmetic. This is done with a splitter since combine would
3446 just undo the work if done during code generation. It also catches
3447 cases we wouldn't have before cse. */
3449 int
3452 {
3464 {
3468 }
3472 {
3476 else
3478 }
3479 /* Below, we must be careful to use copy_rtx on target and subtarget
3480 in intermediate insns, as they may be a subreg rtx, which may not
3481 be shared. */
3484 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3485 viable over a longer latency cmove. On EV5, the E0 slot is a
3486 scarce resource, and on EV4 shift has the same latency as a cmove. */
3488 {
3495 }
3497 {
3502 }
3504 {
3505 rtx add_op;
3512 else
3513 {
3516 {
3521 }
3522 else
3524 }
3525 }
3526 else
3530 }
3531 \f
3532 /* Look up the function X_floating library function name for the
3533 given operation. */
3537 {
3538 struct xfloating_op
3539 {
3542 };
3545 {
3561 };
3564 {
3580 };
3586 /* How irritating. Nothing to key off for the table. Hardcode
3587 knowledge of the G_floating routines. */
3589 {
3591 {
3596 }
3597 else
3598 {
3603 }
3604 }
3608 else
3616 }
3618 /* Most X_floating operations take the rounding mode as an argument.
3619 Compute that here. */
3621 static int
3624 {
3628 {
3644 /* XXX For reference, round to +inf is mode = 3. */
3645 }
3651 }
3653 /* Emit an X_floating library function call.
3655 Note that these functions do not follow normal calling conventions:
3656 TFmode arguments are passed in two integer registers (as opposed to
3657 indirect); TFmode return values appear in R16+R17.
3659 FUNC is the function name to call.
3660 TARGET is where the output belongs.
3661 OPERANDS are the inputs.
3662 NOPERANDS is the count of inputs.
3663 EQUIV is the expression equivalent for the function.
3664 */
3666 static void
3669 {
3676 {
3678 {
3692 /* FALLTHRU */
3700 }
3704 }
3707 {
3719 }
3730 }
3732 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3734 void
3736 {
3750 }
3752 /* Emit an X_floating library function call for a comparison. */
3754 static rtx
3756 {
3766 /* ??? Strange mode for equiv because what's actually returned
3767 is -1,0,1, not a proper boolean value. */
3772 }
3774 /* Emit an X_floating library function call for a conversion. */
3776 void
3778 {
3788 {
3801 }
3806 }
3808 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3809 OP[0] into OP[0,1]. Naturally, output operand ordering is
3810 little-endian. */
3812 void
3814 {
3816 {
3819 }
3821 {
3824 }
3827 else
3831 {
3834 }
3836 {
3839 }
3840 else
3842 }
3844 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3845 op2 is a register containing the sign bit, operation is the
3846 logical operation to be performed. */
3848 void
3850 {
3852 rtx scratch;
3857 /* Detect three flavors of operand overlap. */
3862 {
3865 else
3867 }
3872 /* ??? If the destination overlaps both source tf and high_bit, then
3873 assume source tf is dead in its entirety and use the other half
3874 for a scratch register. Otherwise "scratch" is just the proper
3875 destination register. */
3881 {
3885 }
3886 }
3887 \f
3888 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3889 unaligned data:
3891 unsigned: signed:
3892 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3893 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3894 lda r3,X(r11) lda r3,X+2(r11)
3895 extwl r1,r3,r1 extql r1,r3,r1
3896 extwh r2,r3,r2 extqh r2,r3,r2
3897 or r1.r2.r1 or r1,r2,r1
3898 sra r1,48,r1
3900 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3901 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3902 lda r3,X(r11) lda r3,X(r11)
3903 extll r1,r3,r1 extll r1,r3,r1
3904 extlh r2,r3,r2 extlh r2,r3,r2
3905 or r1.r2.r1 addl r1,r2,r1
3907 quad: ldq_u r1,X(r11)
3908 ldq_u r2,X+7(r11)
3909 lda r3,X(r11)
3910 extql r1,r3,r1
3911 extqh r2,r3,r2
3912 or r1.r2.r1
3913 */
3915 void
3918 {
3932 /* AND addresses cannot be in any alias set, since they may implicitly
3933 alias surrounding code. Ideally we'd have some alias set that
3934 covered all types except those with alignment 8 or higher. */
3951 {
3960 }
3962 {
3968 /* We must use tgt here for the target. Alpha-vms port fails if we use
3969 addr for the target, because addr is marked as a pointer and combine
3970 knows that pointers are always sign-extended 32 bit values. */
3974 }
3975 else
3976 {
3978 {
3981 {
3999 }
4001 }
4002 else
4003 {
4007 {
4025 }
4026 }
4031 }
4035 }
4037 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4039 void
4042 {
4054 /* AND addresses cannot be in any alias set, since they may implicitly
4055 alias surrounding code. Ideally we'd have some alias set that
4056 covered all types except those with alignment 8 or higher. */
4073 {
4077 {
4079 {
4089 }
4092 }
4095 {
4100 {
4104 }
4108 }
4111 }
4112 else
4113 {
4117 {
4122 {
4132 }
4133 }
4138 {
4143 {
4147 }
4151 }
4152 }
4155 {
4158 }
4161 {
4164 }
4165 else
4166 {
4167 /* Must store high before low for degenerate case of aligned. */
4170 }
4171 }
4173 /* The block move code tries to maximize speed by separating loads and
4174 stores at the expense of register pressure: we load all of the data
4175 before we store it back out. There are two secondary effects worth
4176 mentioning, that this speeds copying to/from aligned and unaligned
4177 buffers, and that it makes the code significantly easier to write. */
4179 #define MAX_MOVE_WORDS 8
4181 /* Load an integral number of consecutive unaligned quadwords. */
4183 static void
4186 {
4191 HOST_WIDE_INT i;
4197 /* Generate all the tmp registers we need. */
4199 {
4202 }
4208 /* Load up all of the source data. */
4210 {
4214 im8));
4217 }
4222 im8));
4226 /* Extract the half-word fragments. Unfortunately DEC decided to make
4227 extxh with offset zero a noop instead of zeroing the register, so
4228 we must take care of that edge condition ourselves with cmov. */
4236 {
4238 {
4241 }
4242 else
4243 {
4246 }
4250 const0_rtx),
4252 }
4254 /* Merge the half-words into whole words. */
4256 {
4259 }
4260 }
4262 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4263 may be NULL to store zeros. */
4265 static void
4268 {
4274 HOST_WIDE_INT i;
4280 /* Generate all the tmp registers we need. */
4293 im8));
4300 /* Load up the destination end bits. */
4304 /* Shift the input data into place. */
4309 {
4311 {
4313 {
4316 }
4317 else
4318 {
4321 }
4322 }
4324 {
4327 OPTAB_WIDEN);
4328 }
4329 }
4331 /* Split and merge the ends with the destination data. */
4333 {
4336 }
4337 else
4338 {
4341 }
4344 {
4349 }
4351 /* Store it all. */
4354 else
4357 {
4362 im8));
4365 }
4368 else
4370 }
4373 /* Expand string/block move operations.
4375 operands[0] is the pointer to the destination.
4376 operands[1] is the pointer to the source.
4377 operands[2] is the number of bytes to move.
4378 operands[3] is the alignment. */
4380 int
4382 {
4392 rtx tmp;
4400 /* Look for additional alignment information from recorded register info. */
4408 {
4413 {
4420 }
4421 }
4429 {
4434 {
4441 }
4442 }
4444 /* Load the entire block into registers. */
4446 {
4451 /* Don't use the existing register if we're reading more than
4452 is held in the register. Nor if there is not a mode that
4453 handles the exact size. */
4457 {
4459 {
4463 }
4464 else
4468 }
4470 /* No appropriate mode; fall back on memory. */
4474 }
4478 {
4491 }
4494 {
4507 }
4510 {
4522 }
4525 {
4530 }
4533 {
4535 {
4542 }
4544 {
4549 }
4550 }
4553 {
4558 }
4560 src_done:
4565 /* Now save it back out again. */
4570 {
4576 {
4578 {
4582 }
4585 {
4586 /* Undo the subregging done above when copying between
4587 two TImode registers. */
4591 else
4592 {
4593 rtx seq;
4603 }
4607 }
4608 }
4610 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4611 /* ??? Optimize mode < dst_mode with strict_low_part. */
4613 /* No appropriate mode; fall back on memory. We can speed things
4614 up by recognizing extra alignment information. */
4618 }
4620 /* Write out the data in whatever chunks reading the source allowed. */
4622 {
4624 {
4628 i++;
4629 }
4630 }
4633 {
4634 /* If the source has remaining DImode regs, write them out in
4635 two pieces. */
4637 {
4646 i++;
4647 }
4650 {
4654 i++;
4655 }
4656 }
4659 {
4660 /* Write out a remaining block of words using unaligned methods. */
4668 else
4674 }
4676 /* Due to the above, this won't be aligned. */
4677 /* ??? If we have more than one of these, consider constructing full
4678 words in registers and using alpha_expand_unaligned_store_words. */
4680 {
4683 i++;
4684 }
4688 {
4690 i++;
4692 }
4693 else
4695 {
4697 i++;
4699 }
4702 {
4704 i++;
4706 }
4708 dst_done:
4714 }
4716 int
4718 {
4726 rtx tmp;
4734 /* Look for stricter alignment. */
4741 {
4746 {
4753 }
4754 }
4756 {
4761 {
4764 }
4766 /* No appropriate mode; fall back on memory. */
4769 }
4771 /* Handle an unaligned prefix first. */
4774 {
4775 #if HOST_BITS_PER_WIDE_INT >= 64
4776 /* Given that alignofs is bounded by align, the only time BWX could
4777 generate three stores is for a 7 byte fill. Prefer two individual
4778 stores over a load/mask/store sequence. */
4782 {
4786 HOST_WIDE_INT mask;
4793 {
4797 }
4798 else
4799 {
4802 }
4809 }
4810 #endif
4813 {
4818 }
4820 {
4825 }
4827 {
4832 }
4834 /* If we've not used the extra lead alignment information by now,
4835 we won't be able to. Downgrade align to match what's left over. */
4837 {
4840 }
4841 }
4843 /* Handle a block of contiguous long-words. */
4846 {
4851 const0_rtx);
4855 }
4857 /* If the block is large and appropriately aligned, emit a single
4858 store followed by a sequence of stq_u insns. */
4861 {
4862 rtx orig_dsta;
4874 {
4875 rtx mem
4882 }
4884 /* Depending on the alignment, the first stq_u may have overlapped
4885 with the initial stl, which means that the last stq_u didn't
4886 write as much as it would appear. Leave those questionable bytes
4887 unaccounted for. */
4890 }
4892 /* Handle a smaller block of aligned words. */
4896 {
4901 const0_rtx);
4905 }
4907 /* An unaligned block uses stq_u stores for as many as possible. */
4910 {
4917 }
4919 /* Next clean up any trailing pieces. */
4921 #if HOST_BITS_PER_WIDE_INT >= 64
4922 /* Count the number of bits in BYTES for which aligned stores could
4923 be emitted. */
4929 /* If we have appropriate alignment (and it wouldn't take too many
4930 instructions otherwise), mask out the bytes we need. */
4932 {
4934 {
4936 HOST_WIDE_INT mask;
4948 }
4950 {
4952 HOST_WIDE_INT mask;
4964 }
4965 }
4966 #endif
4969 {
4973 }
4976 {
4978 {
4981 const0_rtx);
4985 }
4987 {
4991 }
4992 }
4995 {
4999 }
5002 }
5004 /* Returns a mask so that zap(x, value) == x & mask. */
5006 rtx
5008 {
5009 rtx result;
5013 {
5017 {
5021 }
5024 }
5026 {
5030 {
5034 }
5037 {
5041 }
5044 }
5045 else
5049 }
5051 void
5055 {
5060 else
5065 else
5069 }
5070 \f
5071 /* Adjust the cost of a scheduling dependency. Return the new cost of
5072 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5074 static int
5076 {
5079 /* If the dependence is an anti-dependence, there is no cost. For an
5080 output dependence, there is sometimes a cost, but it doesn't seem
5081 worth handling those few cases. */
5085 /* If we can't recognize the insns, we can't really do anything. */
5092 /* Bring in the user-defined memory latency. */
5098 /* Everything else handled in DFA bypasses now. */
5101 }
5103 /* The number of instructions that can be issued per cycle. */
5105 static int
5107 {
5109 }
5111 static int
5113 {
5115 }
5117 /* How many alternative schedules to try. This should be as wide as the
5118 scheduling freedom in the DFA, but no wider. Making this value too
5119 large results extra work for the scheduler.
5121 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5122 alternative schedules. For EV5, we can choose between E0/E1 and
5123 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5125 static int
5127 {
5129 }
5130 \f
5131 /* Machine-specific function data. */
5134 {
5135 /* For unicosmk. */
5136 /* List of call information words for calls from this function. */
5141 /* List of deferred case vectors. */
5144 /* For OSF. */
5146 };
5148 /* How to allocate a 'struct machine_function'. */
5152 {
5155 }
5157 /* Functions to save and restore alpha_return_addr_rtx. */
5159 /* Start the ball rolling with RETURN_ADDR_RTX. */
5161 rtx
5163 {
5168 }
5170 /* Return or create a pseudo containing the gp value for the current
5171 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5173 rtx
5175 {
5180 }
5182 static int
5184 {
5185 rtx top;
5195 }
5197 \f
5198 /* Return the trap mode suffix applicable to the current
5199 instruction, or NULL. */
5203 {
5207 {
5223 {
5231 }
5236 {
5245 }
5250 {
5259 }
5261 }
5263 }
5265 /* Return the rounding mode suffix applicable to the current
5266 instruction, or NULL. */
5270 {
5274 {
5279 {
5288 }
5293 }
5295 }
5297 /* Locate some local-dynamic symbol still in use by this function
5298 so that we can print its name in some movdi_er_tlsldm pattern. */
5300 static int
5302 {
5307 {
5310 }
5313 }
5317 {
5318 rtx insn;
5329 }
5331 /* Print an operand. Recognize special options, documented below. */
5333 void
5335 {
5339 {
5341 /* Print the assembler name of the current function. */
5350 {
5358 }
5361 /* Generates single precision instruction suffix. */
5366 /* Generates double precision instruction suffix. */
5371 /* Generates a nop after a noreturn call at the very end of the
5372 function. */
5392 else
5397 {
5401 {
5404 }
5406 {
5409 }
5412 else
5413 {
5416 }
5420 }
5424 /* If this operand is the constant zero, write it as "$31". */
5429 else
5434 /* Similar, but for floating-point. */
5439 else
5444 /* Write the 1's complement of a constant. */
5452 /* Write 1 << C, for a constant C. */
5460 /* Write the high-order 16 bits of a constant, sign-extended. */
5468 /* Write the low-order 16 bits of a constant, sign-extended. */
5477 /* Write mask for ZAP insn. */
5479 {
5481 HOST_WIDE_INT value;
5496 }
5499 {
5507 }
5508 else
5513 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5527 /* Similar, except do it from the mask. */
5529 {
5533 {
5536 }
5538 {
5541 }
5543 {
5546 }
5548 {
5551 }
5552 }
5557 {
5560 }
5565 /* Write the constant value divided by 8 for little-endian mode or
5566 (56 - value) / 8 for big-endian mode. */
5576 WORDS_BIG_ENDIAN
5582 /* Same, except compute (64 - c) / 8 */
5593 {
5594 /* On Unicos/Mk systems: use a DEX expression if the symbol
5595 clashes with a register name. */
5599 else
5601 }
5605 /* Write out comparison name. */
5606 {
5625 else
5627 }
5631 /* Write the divide or modulus operator. */
5633 {
5649 }
5653 /* Write "_u" for unaligned access. */
5664 {
5666 {
5674 }
5675 }
5676 else
5682 }
5683 }
5685 void
5687 {
5696 {
5699 }
5702 {
5707 {
5710 {
5722 }
5725 }
5726 else
5727 {
5731 }
5742 else
5748 }
5758 #if TARGET_ABI_OPEN_VMS
5760 {
5763 }
5767 {
5772 }
5773 #endif
5775 else
5779 }
5780 \f
5781 /* Emit RTL insns to initialize the variable parts of a trampoline at
5782 TRAMP. FNADDR is an RTX for the address of the function's pure
5783 code. CXT is an RTX for the static chain value for the function.
5785 The three offset parameters are for the individual template's
5786 layout. A JMPOFS < 0 indicates that the trampoline does not
5787 contain instructions at all.
5789 We assume here that a function will be called many more times than
5790 its address is taken (e.g., it might be passed to qsort), so we
5791 take the trouble to initialize the "hint" field in the JMP insn.
5792 Note that the hint field is PC (new) + 4 * bits 13:0. */
5794 void
5797 {
5799 /* VMS really uses DImode pointers in memory at this point. */
5802 #ifdef POINTERS_EXTEND_UNSIGNED
5805 #endif
5807 /* Store function address and CXT. */
5813 /* This has been disabled since the hint only has a 32k range, and in
5814 no existing OS is the stack within 32k of the text segment. */
5816 {
5817 /* Compute hint value. */
5820 OPTAB_WIDEN);
5826 /* Merge in the hint. */
5831 OPTAB_WIDEN);
5833 }
5835 #ifdef TRANSFER_FROM_TRAMPOLINE
5838 #endif
5842 }
5843 \f
5844 /* Determine where to put an argument to a function.
5845 Value is zero to push the argument on the stack,
5846 or a hard register in which to store the argument.
5848 MODE is the argument's machine mode.
5849 TYPE is the data type of the argument (as a tree).
5850 This is null for libcalls where that information may
5851 not be available.
5852 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5853 the preceding args and about the function being called.
5854 NAMED is nonzero if this argument is a named parameter
5855 (otherwise it is an extra parameter matching an ellipsis).
5857 On Alpha the first 6 words of args are normally in registers
5858 and the rest are pushed. */
5860 rtx
5863 {
5867 /* Set up defaults for FP operands passed in FP registers, and
5868 integral operands passed in integer registers. */
5873 else
5876 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5877 the three platforms, so we can't avoid conditional compilation. */
5878 #if TARGET_ABI_OPEN_VMS
5879 {
5886 }
5887 #else
5888 #if TARGET_ABI_UNICOSMK
5889 {
5892 /* If this is the last argument, generate the call info word (CIW). */
5893 /* ??? We don't include the caller's line number in the CIW because
5894 I don't know how to determine it if debug infos are turned off. */
5896 {
5898 HOST_WIDE_INT lo;
5899 HOST_WIDE_INT hi;
5900 rtx ciw;
5910 else
5913 #if HOST_BITS_PER_WIDE_INT == 32
5915 #else
5919 #endif
5923 UNSPEC_UMK_LOAD_CIW);
5924 }
5932 {
5938 /* The argument fits in two registers. Note that we still need to
5939 reserve a register for empty structures. */
5944 else
5945 {
5949 }
5950 }
5951 }
5952 #else
5953 {
5958 /* VOID is passed as a special flag for "last argument". */
5965 }
5970 }
5972 tree
5974 {
5985 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5988 integer_type_node);
5992 ptr_type_node);
6000 }
6002 /* Perform any needed actions needed for a function that is receiving a
6003 variable number of arguments.
6005 On the Alpha, we allocate space for all 12 arg registers, but only
6006 push those that are remaining. However, if NO registers need to be
6007 saved, don't allocate any space. This is not only because we won't
6008 need the space, but because AP includes the current_pretend_args_size
6009 and we don't want to mess up any ap-relative addresses already made.
6011 If we are not to use the floating-point registers, save the integer
6012 registers where we would put the floating-point registers. This is
6013 not the most efficient way to implement varargs with just one register
6014 class, but it isn't worth doing anything more efficient in this rare
6015 case. */
6017 #if TARGET_ABI_OSF
6018 void
6021 tree type ATTRIBUTE_UNUSED,
6023 {
6028 {
6030 rtx tmp;
6044 }
6046 }
6047 #endif
6049 void
6051 {
6052 HOST_WIDE_INT offset;
6061 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6062 up by 48, storing fp arg registers in the first 48 bytes, and the
6063 integer arg registers in the next 48 bytes. This is only done,
6064 however, if any integer registers need to be stored.
6066 If no integer registers need be stored, then we must subtract 48
6067 in order to account for the integer arg registers which are counted
6068 in argsize above, but which are not actually stored on the stack.
6069 Must further be careful here about structures straddling the last
6070 integer argument register; that futzes with pretend_args_size,
6071 which changes the meaning of AP. */
6075 else
6079 {
6087 }
6088 else
6089 {
6108 }
6109 }
6111 rtx
6113 {
6114 rtx addr;
6127 else
6131 type_size,
6144 /* If the type could not be passed in registers, skip the block
6145 reserved for the registers. */
6147 {
6153 }
6161 {
6164 }
6166 {
6177 }
6192 {
6195 }
6198 }
6199 \f
6200 /* Builtins. */
6202 enum alpha_builtin
6203 {
6204 ALPHA_BUILTIN_CMPBGE,
6205 ALPHA_BUILTIN_EXTBL,
6206 ALPHA_BUILTIN_EXTWL,
6207 ALPHA_BUILTIN_EXTLL,
6208 ALPHA_BUILTIN_EXTQL,
6209 ALPHA_BUILTIN_EXTWH,
6210 ALPHA_BUILTIN_EXTLH,
6211 ALPHA_BUILTIN_EXTQH,
6212 ALPHA_BUILTIN_INSBL,
6213 ALPHA_BUILTIN_INSWL,
6214 ALPHA_BUILTIN_INSLL,
6215 ALPHA_BUILTIN_INSQL,
6216 ALPHA_BUILTIN_INSWH,
6217 ALPHA_BUILTIN_INSLH,
6218 ALPHA_BUILTIN_INSQH,
6219 ALPHA_BUILTIN_MSKBL,
6220 ALPHA_BUILTIN_MSKWL,
6221 ALPHA_BUILTIN_MSKLL,
6222 ALPHA_BUILTIN_MSKQL,
6223 ALPHA_BUILTIN_MSKWH,
6224 ALPHA_BUILTIN_MSKLH,
6225 ALPHA_BUILTIN_MSKQH,
6226 ALPHA_BUILTIN_UMULH,
6227 ALPHA_BUILTIN_ZAP,
6228 ALPHA_BUILTIN_ZAPNOT,
6229 ALPHA_BUILTIN_AMASK,
6230 ALPHA_BUILTIN_IMPLVER,
6231 ALPHA_BUILTIN_RPCC,
6232 ALPHA_BUILTIN_THREAD_POINTER,
6233 ALPHA_BUILTIN_SET_THREAD_POINTER,
6235 /* TARGET_MAX */
6236 ALPHA_BUILTIN_MINUB8,
6237 ALPHA_BUILTIN_MINSB8,
6238 ALPHA_BUILTIN_MINUW4,
6239 ALPHA_BUILTIN_MINSW4,
6240 ALPHA_BUILTIN_MAXUB8,
6241 ALPHA_BUILTIN_MAXSB8,
6242 ALPHA_BUILTIN_MAXUW4,
6243 ALPHA_BUILTIN_MAXSW4,
6244 ALPHA_BUILTIN_PERR,
6245 ALPHA_BUILTIN_PKLB,
6246 ALPHA_BUILTIN_PKWB,
6247 ALPHA_BUILTIN_UNPKBL,
6248 ALPHA_BUILTIN_UNPKBW,
6250 /* TARGET_CIX */
6251 ALPHA_BUILTIN_CTTZ,
6252 ALPHA_BUILTIN_CTLZ,
6253 ALPHA_BUILTIN_CTPOP,
6255 ALPHA_BUILTIN_max
6256 };
6259 CODE_FOR_builtin_cmpbge,
6260 CODE_FOR_builtin_extbl,
6261 CODE_FOR_builtin_extwl,
6262 CODE_FOR_builtin_extll,
6263 CODE_FOR_builtin_extql,
6264 CODE_FOR_builtin_extwh,
6265 CODE_FOR_builtin_extlh,
6266 CODE_FOR_builtin_extqh,
6267 CODE_FOR_builtin_insbl,
6268 CODE_FOR_builtin_inswl,
6269 CODE_FOR_builtin_insll,
6270 CODE_FOR_builtin_insql,
6271 CODE_FOR_builtin_inswh,
6272 CODE_FOR_builtin_inslh,
6273 CODE_FOR_builtin_insqh,
6274 CODE_FOR_builtin_mskbl,
6275 CODE_FOR_builtin_mskwl,
6276 CODE_FOR_builtin_mskll,
6277 CODE_FOR_builtin_mskql,
6278 CODE_FOR_builtin_mskwh,
6279 CODE_FOR_builtin_msklh,
6280 CODE_FOR_builtin_mskqh,
6281 CODE_FOR_umuldi3_highpart,
6282 CODE_FOR_builtin_zap,
6283 CODE_FOR_builtin_zapnot,
6284 CODE_FOR_builtin_amask,
6285 CODE_FOR_builtin_implver,
6286 CODE_FOR_builtin_rpcc,
6287 CODE_FOR_load_tp,
6288 CODE_FOR_set_tp,
6290 /* TARGET_MAX */
6291 CODE_FOR_builtin_minub8,
6292 CODE_FOR_builtin_minsb8,
6293 CODE_FOR_builtin_minuw4,
6294 CODE_FOR_builtin_minsw4,
6295 CODE_FOR_builtin_maxub8,
6296 CODE_FOR_builtin_maxsb8,
6297 CODE_FOR_builtin_maxuw4,
6298 CODE_FOR_builtin_maxsw4,
6299 CODE_FOR_builtin_perr,
6300 CODE_FOR_builtin_pklb,
6301 CODE_FOR_builtin_pkwb,
6302 CODE_FOR_builtin_unpkbl,
6303 CODE_FOR_builtin_unpkbw,
6305 /* TARGET_CIX */
6306 CODE_FOR_builtin_cttz,
6307 CODE_FOR_builtin_ctlz,
6308 CODE_FOR_builtin_ctpop
6309 };
6311 struct alpha_builtin_def
6312 {
6316 };
6321 };
6332 };
6369 };
6371 static void
6373 {
6375 tree ftype;
6396 long_integer_type_node,
6414 }
6416 /* Expand an expression EXP that calls a built-in function,
6417 with result going to TARGET if that's convenient
6418 (and in mode MODE if that's convenient).
6419 SUBTARGET may be used as the target for computing one of EXP's operands.
6420 IGNORE is nonzero if the value is to be ignored. */
6422 static rtx
6424 rtx subtarget ATTRIBUTE_UNUSED,
6427 {
6428 #define MAX_ARGS 2
6447 arglist;
6449 {
6464 }
6467 {
6473 }
6476 {
6483 else
6491 }
6498 else
6500 }
6501 \f
6502 /* This page contains routines that are used to determine what the function
6503 prologue and epilogue code will do and write them out. */
6505 /* Compute the size of the save area in the stack. */
6507 /* These variables are used for communication between the following functions.
6508 They indicate various things about the current function being compiled
6509 that are used to tell what kind of prologue, epilogue and procedure
6510 descriptior to generate. */
6512 /* Nonzero if we need a stack procedure. */
6516 /* Register number (either FP or SP) that is used to unwind the frame. */
6519 /* Register number used to save FP. We need not have one for RA since
6520 we don't modify it for register procedures. This is only defined
6521 for register frame procedures. */
6524 /* Register number used to reference objects off our PV. */
6527 /* Compute register masks for saved registers. */
6529 static void
6531 {
6536 /* Irritatingly, there are two kinds of thunks -- those created with
6537 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
6538 through the regular part of the compiler. In the
6539 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
6540 info, but assemble_start_function wants to output .frame and
6541 .mask directives. */
6543 {
6547 }
6552 /* One for every register we have to save. */
6557 {
6560 else
6562 }
6564 /* We need to restore these for the handler. */
6567 {
6572 }
6574 /* If any register spilled, then spill the return address also. */
6575 /* ??? This is required by the Digital stack unwind specification
6576 and isn't needed if we're doing Dwarf2 unwinding. */
6582 }
6584 int
6586 {
6594 {
6597 }
6598 else
6599 {
6603 sa_size++;
6604 }
6607 {
6608 /* We might not need to generate a frame if we don't make any calls
6609 (including calls to __T3E_MISMATCH if this is a vararg function),
6610 don't have any local variables which require stack slots, don't
6611 use alloca and have not determined that we need a frame for other
6612 reasons. */
6614 alpha_procedure_type
6616 || current_function_outgoing_args_size
6621 /* Always reserve space for saving callee-saved registers if we
6622 need a frame as required by the calling convention. */
6625 }
6627 {
6628 /* Start by assuming we can use a register procedure if we don't
6629 make any calls (REG_RA not used) or need to save any
6630 registers and a stack procedure if we do. */
6635 else
6638 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6639 made the final decision on stack procedure vs register procedure. */
6643 /* Decide whether to refer to objects off our PV via FP or PV.
6644 If we need FP for something else or if we receive a nonlocal
6645 goto (which expects PV to contain the value), we must use PV.
6646 Otherwise, start by assuming we can use FP. */
6648 vms_base_regno
6649 = (frame_pointer_needed
6650 || current_function_has_nonlocal_label
6655 /* If we want to copy PV into FP, we need to find some register
6656 in which to save FP. */
6669 /* Stack unwinding should be done via FP unless we use it for PV. */
6673 /* If this is a stack procedure, allow space for saving FP and RA. */
6676 }
6677 else
6678 {
6679 /* Our size must be even (multiple of 16 bytes). */
6681 sa_size++;
6682 }
6685 }
6687 /* Define the offset between two registers, one to be eliminated,
6688 and the other its replacement, at the start of a routine. */
6690 HOST_WIDE_INT
6693 {
6694 HOST_WIDE_INT ret;
6700 ;
6705 else
6709 }
6711 int
6713 {
6716 }
6718 int
6720 {
6723 }
6725 #if TARGET_ABI_OPEN_VMS
6728 {
6729 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6734 };
6736 #endif
6738 static int
6740 {
6742 }
6744 int
6746 {
6748 }
6750 static int
6752 {
6753 rtx insn;
6755 /* The GP being variable is an OSF abi thing. */
6765 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6766 Even if we are a static function, we still need to do this in case
6767 our address is taken and passed to something like qsort. */
6781 }
6783 \f
6784 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6785 sequences. */
6787 static rtx
6789 {
6791 rtx insn;
6799 {
6802 {
6805 }
6807 }
6808 else
6809 {
6812 }
6814 }
6816 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6818 /* Write function prologue. */
6820 /* On vms we have two kinds of functions:
6822 - stack frame (PROC_STACK)
6823 these are 'normal' functions with local vars and which are
6824 calling other functions
6825 - register frame (PROC_REGISTER)
6826 keeps all data in registers, needs no stack
6828 We must pass this to the assembler so it can generate the
6829 proper pdsc (procedure descriptor)
6830 This is done with the '.pdesc' command.
6832 On not-vms, we don't really differentiate between the two, as we can
6833 simply allocate stack without saving registers. */
6835 void
6837 {
6838 /* Registers to save. */
6841 /* Stack space needed for pushing registers clobbered by us. */
6842 HOST_WIDE_INT sa_size;
6843 /* Complete stack size needed. */
6844 HOST_WIDE_INT frame_size;
6845 /* Offset from base reg to register save area. */
6846 HOST_WIDE_INT reg_offset;
6856 + frame_size
6859 /* We have to allocate space for the DSIB if we generate a frame. */
6864 else
6866 + sa_size
6872 else
6877 /* Emit an insn to reload GP, if needed. */
6879 {
6883 }
6885 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
6886 the call to mcount ourselves, rather than having the linker do it
6887 magically in response to -pg. Since _mcount has special linkage,
6888 don't represent the call as a call. */
6895 /* Adjust the stack by the frame size. If the frame size is > 4096
6896 bytes, we need to be sure we probe somewhere in the first and last
6897 4096 bytes (we can probably get away without the latter test) and
6898 every 8192 bytes in between. If the frame size is > 32768, we
6899 do this in a loop. Otherwise, we generate the explicit probe
6900 instructions.
6902 Note that we are only allowed to adjust sp once in the prologue. */
6905 {
6907 {
6910 do
6916 /* We only have to do this probe if we aren't saving registers. */
6919 }
6926 }
6927 else
6928 {
6929 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
6930 number of 8192 byte blocks to probe. We then probe each block
6931 in the loop and then set SP to the proper location. If the
6932 amount remaining is > 4096, we have to do one more probe if we
6933 are not saving any registers. */
6939 rtx seq;
6945 /* Because of the difficulty in emitting a new basic block this
6946 late in the compilation, generate the loop as a single insn. */
6950 {
6954 }
6957 {
6958 /* For NT stack unwind (done by 'reverse execution'), it's
6959 not OK to take the result of a loop, even though the value
6960 is already in ptr, so we reload it via a single operation
6961 and subtract it to sp.
6963 Yes, that's correct -- we have to reload the whole constant
6964 into a temporary via ldah+lda then subtract from sp. To
6965 ensure we get ldah+lda, we use a special pattern. */
6974 ptr));
6975 }
6976 else
6977 {
6980 }
6982 /* This alternative is special, because the DWARF code cannot
6983 possibly intuit through the loop above. So we invent this
6984 note it looks at instead. */
6994 }
6997 {
6998 /* Cope with very large offsets to the register save area. */
7001 {
7003 HOST_WIDE_INT bias;
7007 else
7013 }
7015 /* Save regs in stack order. Beginning with VMS PV. */
7017 {
7021 }
7023 /* Save register RA next. */
7025 {
7031 }
7033 /* Now save any other registers required to be saved. */
7036 {
7041 }
7045 {
7050 }
7051 }
7053 {
7054 /* The standard frame on the T3E includes space for saving registers.
7055 We just have to use it. We don't have to save the return address and
7056 the old frame pointer here - they are saved in the DSIB. */
7061 {
7063 reg_offset));
7067 }
7070 {
7072 reg_offset));
7076 }
7077 }
7080 {
7082 /* Register frame procedures save the fp.
7083 ?? Ought to have a dwarf2 save for this. */
7085 hard_frame_pointer_rtx);
7095 /* If we have to allocate space for outgoing args, do it now. */
7097 {
7098 rtx seq
7100 plus_constant
7102 - (ALPHA_ROUND
7105 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7106 if ! frame_pointer_needed. Setting the bit will change the CFA
7107 computation rule to use sp again, which would be wrong if we had
7108 frame_pointer_needed, as this means sp might move unpredictably
7109 later on.
7111 Also, note that
7112 frame_pointer_needed
7113 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7114 and
7115 current_function_outgoing_args_size != 0
7116 => alpha_procedure_type != PT_NULL,
7118 so when we are not setting the bit here, we are guaranteed to
7119 have emited an FRP frame pointer update just before. */
7121 }
7122 }
7124 {
7125 /* If we need a frame pointer, set it from the stack pointer. */
7127 {
7130 else
7131 /* This must always be the last instruction in the
7132 prologue, thus we emit a special move + clobber. */
7135 }
7136 }
7138 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7139 the prologue, for exception handling reasons, we cannot do this for
7140 any insn that might fault. We could prevent this for mems with a
7141 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7142 have to prevent all such scheduling with a blockage.
7144 Linux, on the other hand, never bothered to implement OSF/1's
7145 exception handling, and so doesn't care about such things. Anyone
7146 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7150 }
7152 /* Output the textual info surrounding the prologue. */
7154 void
7156 tree decl ATTRIBUTE_UNUSED)
7157 {
7160 /* Stack space needed for pushing registers clobbered by us. */
7161 HOST_WIDE_INT sa_size;
7162 /* Complete stack size needed. */
7164 /* Offset from base reg to register save area. */
7165 HOST_WIDE_INT reg_offset;
7169 /* Don't emit an extern directive for functions defined in the same file. */
7171 {
7172 tree name_tree;
7175 }
7184 + frame_size
7191 else
7193 + sa_size
7199 else
7204 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7205 We have to do that before the .ent directive as we cannot switch
7206 files within procedures with native ecoff because line numbers are
7207 linked to procedure descriptors.
7208 Outputting the lineno helps debugging of one line functions as they
7209 would otherwise get no line number at all. Please note that we would
7210 like to put out last_linenum from final.c, but it is not accessible. */
7213 {
7214 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7217 #endif
7218 #ifdef ASM_OUTPUT_SOURCE_LINE
7222 #endif
7223 }
7225 /* Issue function start and label. */
7228 {
7233 /* If the function needs GP, we'll write the "..ng" label there.
7234 Otherwise, do it here. */
7236 && ! alpha_function_needs_gp
7238 {
7242 }
7243 }
7249 /* For public functions, the label must be globalized by appending an
7250 additional colon. */
7262 {
7263 /* Set flags in procedure descriptor to request IEEE-conformant
7264 math-library routines. The value we set it to is PDSC_EXC_IEEE
7265 (/usr/include/pdsc.h). */
7267 }
7269 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7273 /* Describe our frame. If the frame size is larger than an integer,
7274 print it as zero to avoid an assembler error. We won't be
7275 properly describing such a frame, but that's the best we can do. */
7277 ;
7281 vms_unwind_regno,
7283 reg_offset);
7286 (frame_pointer_needed
7289 current_function_pretend_args_size);
7291 /* Describe which registers were spilled. */
7293 ;
7295 {
7297 /* ??? Does VMS care if mask contains ra? The old code didn't
7298 set it, so I don't here. */
7304 }
7306 {
7308 {
7315 }
7320 }
7322 #if TARGET_ABI_OPEN_VMS
7323 /* Ifdef'ed cause link_section are only available then. */
7332 #endif
7333 }
7335 /* Emit the .prologue note at the scheduled end of the prologue. */
7337 static void
7339 {
7341 ;
7349 }
7351 /* Write function epilogue. */
7353 /* ??? At some point we will want to support full unwind, and so will
7354 need to mark the epilogue as well. At the moment, we just confuse
7355 dwarf2out. */
7356 #undef FRP
7357 #define FRP(exp) exp
7359 void
7361 {
7362 /* Registers to save. */
7365 /* Stack space needed for pushing registers clobbered by us. */
7366 HOST_WIDE_INT sa_size;
7367 /* Complete stack size needed. */
7368 HOST_WIDE_INT frame_size;
7369 /* Offset from base reg to register save area. */
7370 HOST_WIDE_INT reg_offset;
7374 rtx eh_ofs;
7383 + frame_size
7390 else
7392 + sa_size
7397 {
7400 else
7402 }
7403 else
7408 fp_is_frame_pointer
7416 else
7420 {
7421 /* If we have a frame pointer, restore SP from it. */
7427 /* Cope with very large offsets to the register save area. */
7429 {
7431 HOST_WIDE_INT bias;
7435 else
7442 }
7444 /* Restore registers in order, excepting a true frame pointer. */
7456 {
7459 else
7460 {
7464 }
7466 }
7470 {
7475 }
7476 }
7478 {
7479 /* Restore callee-saved general-purpose registers. */
7485 {
7487 reg_offset));
7491 }
7495 {
7497 reg_offset));
7501 }
7503 /* Restore the return address from the DSIB. */
7508 }
7511 {
7515 {
7519 }
7521 /* If the stack size is large, begin computation into a temporary
7522 register so as not to interfere with a potential fp restore,
7523 which must be consecutive with an SP restore. */
7528 {
7532 }
7534 {
7540 else
7541 {
7544 }
7546 }
7547 else
7548 {
7552 {
7553 /* We can't drop new things to memory this late, afaik,
7554 so build it up by pieces. */
7559 }
7560 }
7562 /* From now on, things must be in order. So emit blockages. */
7564 /* Restore the frame pointer. */
7566 {
7572 }
7574 {
7579 }
7581 {
7585 }
7587 /* Restore the stack pointer. */
7591 else
7594 }
7595 else
7596 {
7598 {
7602 }
7604 {
7605 /* Decrement the frame pointer if the function does not have a
7606 frame. */
7611 }
7612 }
7613 }
7614 \f
7615 /* Output the rest of the textual info surrounding the epilogue. */
7617 void
7619 {
7620 /* End the function. */
7622 {
7626 }
7629 #if TARGET_ABI_OPEN_VMS
7631 #endif
7633 /* Output jump tables and the static subroutine information block. */
7635 {
7638 }
7639 }
7641 #if TARGET_ABI_OSF
7642 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7644 In order to avoid the hordes of differences between generated code
7645 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7646 lots of code loading up large constants, generate rtl and emit it
7647 instead of going straight to text.
7649 Not sure why this idea hasn't been explored before... */
7651 static void
7654 tree function)
7655 {
7659 /* We always require a valid GP. */
7663 /* Find the "this" pointer. If the function returns a structure,
7664 the structure return pointer is in $16. */
7667 else
7670 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7671 entire constant for the add. */
7675 {
7680 }
7681 else
7682 {
7686 }
7688 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7690 {
7699 {
7702 }
7703 else
7704 {
7709 }
7712 else
7717 }
7719 /* Generate a tail call to the target function. */
7721 {
7724 }
7730 /* Run just enough of rest_of_compilation to get the insns emitted.
7731 There's not really enough bulk here to make other passes such as
7732 instruction scheduling worth while. Note that use_thunk calls
7733 assemble_start_function and assemble_end_function. */
7740 }
7742 \f
7743 /* Debugging support. */
7747 /* Count the number of sdb related labels are generated (to find block
7748 start and end boundaries). */
7752 /* Next label # for each statement. */
7756 /* Count the number of .file directives, so that .loc is up to date. */
7760 /* Name of the file containing the current function. */
7764 /* Offsets to alpha virtual arg/local debugging pointers. */
7768 \f
7769 /* Emit a new filename to a stream. */
7771 void
7773 {
7778 {
7787 }
7790 {
7795 }
7799 {
7802 else
7803 {
7807 }
7811 }
7812 }
7814 /* Emit a linenumber to a stream. */
7816 void
7818 {
7820 {
7821 /* mips-tfile doesn't understand .stabd directives. */
7825 }
7826 else
7828 }
7829 \f
7830 /* Structure to show the current status of registers and memory. */
7832 struct shadow_summary
7833 {
7839 };
7841 /* Summary the effects of expression X on the machine. Update SUM, a pointer
7842 to the summary structure. SET is nonzero if the insn is setting the
7843 object, otherwise zero. */
7845 static void
7847 {
7855 {
7856 /* ??? Note that this case would be incorrect if the Alpha had a
7857 ZERO_EXTRACT in SET_DEST. */
7886 {
7894 {
7897 else
7899 }
7900 else
7901 {
7904 else
7906 }
7907 }
7913 else
7916 /* Find the regs used in memory address computation: */
7925 /* Handle common unary and binary ops for efficiency. */
7947 {
7962 }
7963 }
7964 }
7966 /* Ensure a sufficient number of `trapb' insns are in the code when
7967 the user requests code with a trap precision of functions or
7968 instructions.
7970 In naive mode, when the user requests a trap-precision of
7971 "instruction", a trapb is needed after every instruction that may
7972 generate a trap. This ensures that the code is resumption safe but
7973 it is also slow.
7975 When optimizations are turned on, we delay issuing a trapb as long
7976 as possible. In this context, a trap shadow is the sequence of
7977 instructions that starts with a (potentially) trap generating
7978 instruction and extends to the next trapb or call_pal instruction
7979 (but GCC never generates call_pal by itself). We can delay (and
7980 therefore sometimes omit) a trapb subject to the following
7981 conditions:
7983 (a) On entry to the trap shadow, if any Alpha register or memory
7984 location contains a value that is used as an operand value by some
7985 instruction in the trap shadow (live on entry), then no instruction
7986 in the trap shadow may modify the register or memory location.
7988 (b) Within the trap shadow, the computation of the base register
7989 for a memory load or store instruction may not involve using the
7990 result of an instruction that might generate an UNPREDICTABLE
7991 result.
7993 (c) Within the trap shadow, no register may be used more than once
7994 as a destination register. (This is to make life easier for the
7995 trap-handler.)
7997 (d) The trap shadow may not include any branch instructions. */
7999 static void
8001 {
8014 {
8016 {
8018 {
8020 exception_nesting++;
8026 exception_nesting--;
8035 }
8036 }
8038 {
8040 {
8044 }
8046 {
8048 {
8057 {
8059 /* Annoyingly, get_attr_trap will abort on these. */
8068 {
8069 /* (c) would be violated */
8071 }
8073 /* Combine shadow with summary of current insn: */
8084 {
8085 /* (a) would be violated (also takes care of (b)) */
8092 }
8102 }
8103 }
8104 else
8105 {
8106 close_shadow:
8115 }
8116 }
8117 }
8124 {
8128 }
8129 }
8130 }
8131 \f
8132 /* Alpha can only issue instruction groups simultaneously if they are
8133 suitibly aligned. This is very processor-specific. */
8140 };
8151 };
8153 static enum alphaev4_pipe
8155 {
8162 {
8192 }
8193 }
8195 static enum alphaev5_pipe
8197 {
8204 {
8241 }
8242 }
8244 /* IN_USE is a mask of the slots currently filled within the insn group.
8245 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8246 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8248 LEN is, of course, the length of the group in bytes. */
8250 static rtx
8252 {
8263 {
8268 {
8270 /* Force complex instructions to start new groups. */
8274 /* If this is a completely unrecognized insn, its an asm.
8275 We don't know how long it is, so record length as -1 to
8276 signal a needed realignment. */
8279 else
8285 {
8289 }
8290 else
8296 {
8300 }
8312 }
8315 /* Haifa doesn't do well scheduling branches. */
8319 next:
8325 /* Let Haifa tell us where it thinks insn group boundaries are. */
8331 }
8333 next_and_done:
8336 done:
8340 }
8342 /* IN_USE is a mask of the slots currently filled within the insn group.
8343 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8344 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8346 LEN is, of course, the length of the group in bytes. */
8348 static rtx
8350 {
8361 {
8366 {
8368 /* Force complex instructions to start new groups. */
8372 /* If this is a completely unrecognized insn, its an asm.
8373 We don't know how long it is, so record length as -1 to
8374 signal a needed realignment. */
8377 else
8381 /* ??? Most of the places below, we would like to abort, as
8382 it would indicate an error either in Haifa, or in the
8383 scheduling description. Unfortunately, Haifa never
8384 schedules the last instruction of the BB, so we don't
8385 have an accurate TI bit to go off. */
8388 {
8392 }
8393 else
8399 {
8403 }
8415 {
8419 }
8420 else
8441 }
8444 /* Haifa doesn't do well scheduling branches. */
8445 /* ??? If this is predicted not-taken, slotting continues, except
8446 that no more IBR, FBR, or JSR insns may be slotted. */
8450 next:
8456 /* Let Haifa tell us where it thinks insn group boundaries are. */
8462 }
8464 next_and_done:
8467 done:
8471 }
8473 static rtx
8475 {
8477 rtx nop;
8480 {
8483 }
8485 {
8488 }
8490 {
8493 }
8494 else
8499 }
8501 static rtx
8503 {
8505 rtx nop;
8508 {
8511 }
8513 {
8516 }
8518 {
8521 }
8522 else
8527 }
8529 /* The instruction group alignment main loop. */
8531 static void
8535 {
8536 /* ALIGN is the known alignment for the insn group. */
8538 /* OFS is the offset of the current insn in the insn group. */
8543 /* Let shorten branches care for assigning alignments to code labels. */
8550 else
8559 {
8562 /* When we see a label, resync alignment etc. */
8564 {
8568 {
8571 }
8577 }
8579 /* Handle complex instructions special. */
8581 {
8582 /* Asms will have length < 0. This is a signal that we have
8583 lost alignment knowledge. Assume, however, that the asm
8584 will not mis-align instructions. */
8586 {
8590 }
8591 }
8593 /* If the known alignment is smaller than the recognized insn group,
8594 realign the output. */
8596 {
8604 /* Can't realign between a call and its gp reload. */
8607 {
8611 }
8612 }
8614 /* If the group won't fit in the same INT16 as the previous,
8615 we need to add padding to keep the group together. Rather
8616 than simply leaving the insn filling to the assembler, we
8617 can make use of the knowledge of what sorts of instructions
8618 were issued in the previous group to make sure that all of
8619 the added nops are really free. */
8621 {
8623 rtx where;
8625 /* Insert nops before labels, branches, and calls to truely merge
8626 the execution of the nops with the previous instruction group. */
8629 {
8631 {
8635 }
8638 }
8639 else
8642 do
8646 }
8651 }
8652 }
8653 \f
8654 /* Machine dependent reorg pass. */
8656 static void
8658 {
8662 /* Due to the number of extra trapb insns, don't bother fixing up
8663 alignment when trap precision is instruction. Moreover, we can
8664 only do our job when sched2 is run. */
8668 {
8673 }
8674 }
8675 \f
8676 #if !TARGET_ABI_UNICOSMK
8678 #ifdef HAVE_STAMP_H
8679 #include <stamp.h>
8680 #endif
8682 static void
8684 {
8686 #ifdef MS_STAMP
8688 #endif
8700 : (TARGET_CPU_EV5
8703 }
8704 #endif
8706 #ifdef OBJECT_FORMAT_ELF
8708 /* Switch to the section to which we should output X. The only thing
8709 special we do here is to honor small data. */
8711 static void
8714 {
8716 /* ??? Consider using mergable sdata sections. */
8718 else
8720 }
8723 \f
8724 /* Structure to collect function names for final output in link section. */
8725 /* Note that items marked with GTY can't be ifdef'ed out. */
8731 {
8733 rtx linkage;
8736 };
8739 {
8742 links;
8743 };
8746 splay_tree alpha_links_tree;
8748 splay_tree alpha_funcs_tree;
8752 #if TARGET_ABI_OPEN_VMS
8754 /* Return the VMS argument type corresponding to MODE. */
8756 enum avms_arg_type
8758 {
8760 {
8767 }
8768 }
8770 /* Return an rtx for an integer representing the VMS Argument Information
8771 register value. */
8773 rtx
8775 {
8783 }
8784 \f
8785 /* Make (or fake) .linkage entry for function call.
8787 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8789 Return an SYMBOL_REF rtx for the linkage. */
8791 rtx
8793 {
8794 splay_tree_node node;
8798 name++;
8801 {
8806 splay_tree_compare_pointers);
8816 }
8819 {
8820 /* Is this name already defined? */
8824 {
8827 {
8828 /* Defined here but external assumed. */
8831 }
8832 else
8833 {
8834 /* Used here but unused assumed. */
8837 }
8839 }
8840 }
8841 else
8847 /* Assume external if no definition. */
8850 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
8853 /* Construct a SYMBOL_REF for us to call. */
8854 {
8862 }
8868 }
8870 rtx
8872 {
8873 splay_tree_node cfunnode;
8885 {
8886 splay_tree_node lnode;
8888 /* Is this name already defined? */
8893 }
8894 else
8898 {
8907 name++;
8916 {
8919 }
8931 }
8935 else
8940 else
8942 }
8944 static int
8946 {
8953 {
8955 {
8956 /* Local and used */
8958 }
8959 else
8960 {
8961 /* External and used, request code address. */
8963 }
8964 }
8965 else
8966 {
8968 {
8969 /* Local and used, build linkage pair. */
8972 }
8973 else
8974 {
8975 /* External and used, request linkage pair. */
8977 }
8978 }
8981 }
8983 static void
8985 {
8986 splay_tree_node node;
9005 {
9007 /* splay_tree_delete (func->links); */
9008 }
9009 }
9011 /* Given a decl, a section name, and whether the decl initializer
9012 has relocs, choose attributes for the section. */
9014 #define SECTION_VMS_OVERLAY SECTION_FORGET
9015 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9016 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9018 static unsigned int
9020 {
9034 }
9036 /* Switch to an arbitrary section NAME with attributes as specified
9037 by FLAGS. ALIGN specifies any known alignment requirements for
9038 the section; 0 if the default should be used. */
9040 static void
9042 {
9056 }
9058 /* Record an element in the table of global constructors. SYMBOL is
9059 a SYMBOL_REF of the function to be called; PRIORITY is a number
9060 between 0 and MAX_INIT_PRIORITY.
9062 Differs from default_ctors_section_asm_out_constructor in that the
9063 width of the .ctors entry is always 64 bits, rather than the 32 bits
9064 used by a normal pointer. */
9066 static void
9068 {
9072 }
9074 static void
9076 {
9080 }
9081 #else
9083 rtx
9086 {
9088 }
9090 rtx
9092 tree cfundecl ATTRIBUTE_UNUSED,
9095 {
9097 }
9100 \f
9101 #if TARGET_ABI_UNICOSMK
9103 /* Define the offset between two registers, one to be eliminated, and the
9104 other its replacement, at the start of a routine. */
9106 int
9108 {
9126 else
9128 }
9130 /* Output the module name for .ident and .end directives. We have to strip
9131 directories and add make sure that the module name starts with a letter
9132 or '$'. */
9134 static void
9136 {
9139 /* Strip directories. */
9144 else
9147 /* CAM only accepts module names that start with a letter or '$'. We
9148 prefix the module name with a '$' if necessary. */
9153 }
9155 /* Output the definition of a common variable. */
9157 void
9159 {
9160 tree name_tree;
9169 /* Mark the symbol as defined in this module. */
9172 }
9174 #define SECTION_PUBLIC SECTION_MACH_DEP
9175 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9178 static unsigned int
9181 {
9188 {
9195 }
9196 else
9203 }
9205 /* Generate a section name for decl and associate it with the
9206 declaration. */
9208 static void
9210 {
9222 {
9225 /* It is essential that we prefix the section name here because
9226 otherwise the section names generated for constructors and
9227 destructors confuse collect2. */
9232 }
9235 else
9236 {
9242 }
9243 }
9245 /* Switch to an arbitrary section NAME with attributes as specified
9246 by FLAGS. ALIGN specifies any known alignment requirements for
9247 the section; 0 if the default should be used. */
9249 static void
9251 {
9254 /* Close the previous section. */
9258 /* Find out what kind of section we are opening. */
9267 else
9273 else
9275 }
9277 static void
9279 {
9283 }
9285 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9286 in code sections because .align fill unused space with zeroes. */
9288 void
9290 {
9293 else
9295 }
9297 /* Add a case vector to the current function's list of deferred case
9298 vectors. Case vectors have to be put into a separate section because CAM
9299 does not allow data definitions in code sections. */
9301 void
9303 {
9309 }
9311 /* Output a case vector. */
9313 static void
9315 {
9324 {
9325 ASM_OUTPUT_ADDR_VEC_ELT
9327 }
9328 }
9330 /* Output current function's deferred case vectors. */
9332 static void
9334 {
9336 rtx t;
9344 }
9346 /* Generate the name of the SSIB section for the current function. */
9349 #define SSIB_PREFIX_LEN 7
9353 {
9354 /* This is ok since CAM won't be able to deal with names longer than that
9355 anyway. */
9359 rtx x;
9380 }
9382 /* Set up the dynamic subprogram information block (DSIB) and update the
9383 frame pointer register ($15) for subroutines which have a frame. If the
9384 subroutine doesn't have a frame, simply increment $15. */
9386 static void
9388 {
9390 {
9392 rtx mem;
9394 /* Allocate 64 bytes for the DSIB. */
9400 /* Save the return address. */
9407 /* Save the old frame pointer. */
9416 /* Store the SSIB pointer. */
9426 /* Save the CIW index. */
9434 /* Set the new frame pointer. */
9439 }
9440 else
9441 {
9442 /* Increment the frame pointer register to indicate that we do not
9443 have a frame. */
9447 }
9448 }
9450 /* Output the static subroutine information block for the current
9451 function. */
9453 static void
9455 {
9458 rtx x;
9459 rtx ciw;
9466 /* Some required stuff and the function name length. */
9471 /* Saved registers
9472 ??? We don't do that yet. */
9476 /* Function address. */
9485 /* Function name.
9486 ??? We do it the same way Cray CC does it but this could be
9487 simplified. */
9493 else
9496 /* All call information words used in the function. */
9499 {
9501 #if HOST_BITS_PER_WIDE_INT == 32
9504 #else
9506 #endif
9507 }
9508 }
9510 /* Add a call information word (CIW) to the list of the current function's
9511 CIWs and return its index.
9513 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9515 rtx
9517 {
9518 rtx node;
9524 else
9532 }
9538 {
9541 count++);
9543 }
9547 {
9550 count++);
9552 }
9554 /* The Cray assembler doesn't accept extern declarations for symbols which
9555 are defined in the same file. We have to keep track of all global
9556 symbols which are referenced and/or defined in a source file and output
9557 extern declarations for those which are referenced but not defined at
9558 the end of file. */
9560 /* List of identifiers for which an extern declaration might have to be
9561 emitted. */
9562 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9564 struct unicosmk_extern_list
9565 {
9568 };
9572 /* Output extern declarations which are required for every asm file. */
9574 static void
9576 {
9587 }
9589 /* Output extern declarations for global symbols which are have been
9590 referenced but not defined. */
9592 static void
9594 {
9598 tree name_tree;
9602 {
9603 /* We have to strip the encoding and possibly remove user_label_prefix
9604 from the identifier in order to handle -fleading-underscore and
9605 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9613 {
9618 }
9619 }
9620 }
9622 /* Record an extern. */
9624 void
9626 {
9634 }
9636 /* The Cray assembler generates incorrect code if identifiers which
9637 conflict with register names are used as instruction operands. We have
9638 to replace such identifiers with DEX expressions. */
9640 /* Structure to collect identifiers which have been replaced by DEX
9641 expressions. */
9642 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9647 };
9649 /* List of identifiers which have been replaced by DEX expressions. The DEX
9650 number is determined by the position in the list. */
9654 /* The number of elements in the DEX list. */
9658 /* Check if NAME must be replaced by a DEX expression. */
9660 static int
9662 {
9673 {
9683 }
9684 }
9686 /* Return the DEX number if X must be replaced by a DEX expression and 0
9687 otherwise. */
9689 static int
9691 {
9705 {
9709 }
9718 }
9720 /* Output the DEX definitions for this file. */
9722 static void
9724 {
9735 {
9740 }
9743 }
9745 /* Output text that to appear at the beginning of an assembler file. */
9747 static void
9749 {
9756 /* The Unicos/Mk assembler uses different register names. Instead of trying
9757 to support them, we simply use micro definitions. */
9759 /* CAM has different register names: rN for the integer register N and fN
9760 for the floating-point register N. Instead of trying to use these in
9761 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9762 register. */
9772 /* The .align directive fill unused space with zeroes which does not work
9773 in code sections. We define the macro 'gcc@code@align' which uses nops
9774 instead. Note that it assumes that code sections always have the
9775 biggest possible alignment since . refers to the current offset from
9776 the beginning of the section. */
9788 /* Output extern declarations which should always be visible. */
9791 /* Open a dummy section. We always need to be inside a section for the
9792 section-switching code to work correctly.
9793 ??? This should be a module id or something like that. I still have to
9794 figure out what the rules for those are. */
9796 }
9798 /* Output text to appear at the end of an assembler file. This includes all
9799 pending extern declarations and DEX expressions. */
9801 static void
9803 {
9806 /* Output all pending externs. */
9810 /* Output dex definitions used for functions whose names conflict with
9811 register names. */
9818 }
9820 #else
9822 static void
9824 {}
9826 static void
9828 {}
9830 static void
9833 {}
9835 rtx
9837 {
9839 }
9841 static int
9843 {
9845 }
9849 \f
9850 /* Initialize the GCC target structure. */
9851 #if TARGET_ABI_OPEN_VMS
9852 # undef TARGET_ATTRIBUTE_TABLE
9853 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
9854 # undef TARGET_SECTION_TYPE_FLAGS
9855 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
9856 #endif
9858 #undef TARGET_IN_SMALL_DATA_P
9859 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
9861 #if TARGET_ABI_UNICOSMK
9862 # undef TARGET_INSERT_ATTRIBUTES
9863 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
9864 # undef TARGET_SECTION_TYPE_FLAGS
9865 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
9866 # undef TARGET_ASM_UNIQUE_SECTION
9867 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
9868 # undef TARGET_ASM_GLOBALIZE_LABEL
9869 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
9870 #endif
9872 #undef TARGET_ASM_ALIGNED_HI_OP
9874 #undef TARGET_ASM_ALIGNED_DI_OP
9877 /* Default unaligned ops are provided for ELF systems. To get unaligned
9878 data for non-ELF systems, we have to turn off auto alignment. */
9879 #ifndef OBJECT_FORMAT_ELF
9880 #undef TARGET_ASM_UNALIGNED_HI_OP
9882 #undef TARGET_ASM_UNALIGNED_SI_OP
9884 #undef TARGET_ASM_UNALIGNED_DI_OP
9886 #endif
9888 #ifdef OBJECT_FORMAT_ELF
9889 #undef TARGET_ASM_SELECT_RTX_SECTION
9890 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
9891 #endif
9893 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
9894 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
9896 #if TARGET_ABI_UNICOSMK
9897 #undef TARGET_ASM_FILE_START
9898 #define TARGET_ASM_FILE_START unicosmk_file_start
9899 #undef TARGET_ASM_FILE_END
9900 #define TARGET_ASM_FILE_END unicosmk_file_end
9901 #else
9902 #undef TARGET_ASM_FILE_START
9903 #define TARGET_ASM_FILE_START alpha_file_start
9904 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
9905 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
9906 #endif
9908 #undef TARGET_SCHED_ADJUST_COST
9909 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
9910 #undef TARGET_SCHED_ISSUE_RATE
9911 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
9912 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
9913 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
9914 alpha_use_dfa_pipeline_interface
9915 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9916 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
9917 alpha_multipass_dfa_lookahead
9919 #undef TARGET_HAVE_TLS
9920 #define TARGET_HAVE_TLS HAVE_AS_TLS
9922 #undef TARGET_INIT_BUILTINS
9923 #define TARGET_INIT_BUILTINS alpha_init_builtins
9924 #undef TARGET_EXPAND_BUILTIN
9925 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
9927 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9928 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
9929 #undef TARGET_CANNOT_COPY_INSN_P
9930 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
9932 #if TARGET_ABI_OSF
9933 #undef TARGET_ASM_OUTPUT_MI_THUNK
9934 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
9935 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9936 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9937 #endif
9939 #undef TARGET_RTX_COSTS
9940 #define TARGET_RTX_COSTS alpha_rtx_costs
9941 #undef TARGET_ADDRESS_COST
9942 #define TARGET_ADDRESS_COST hook_int_rtx_0
9944 #undef TARGET_MACHINE_DEPENDENT_REORG
9945 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
9949 \f