1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "diagnostic-core.h"
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
38 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
39 #include "addresses.h"
41 /* Forward declarations */
42 static void set_of_1 (rtx
, const_rtx
, void *);
43 static bool covers_regno_p (const_rtx
, unsigned int);
44 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
45 static int rtx_referenced_p_1 (rtx
*, void *);
46 static int computed_jump_p_1 (const_rtx
);
47 static void parms_set (rtx
, const_rtx
, void *);
49 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, enum machine_mode
,
50 const_rtx
, enum machine_mode
,
51 unsigned HOST_WIDE_INT
);
52 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, enum machine_mode
,
53 const_rtx
, enum machine_mode
,
54 unsigned HOST_WIDE_INT
);
55 static unsigned int cached_num_sign_bit_copies (const_rtx
, enum machine_mode
, const_rtx
,
58 static unsigned int num_sign_bit_copies1 (const_rtx
, enum machine_mode
, const_rtx
,
59 enum machine_mode
, unsigned int);
61 /* Offset of the first 'e', 'E' or 'V' operand for each rtx code, or
62 -1 if a code has no such operand. */
63 static int non_rtx_starting_operands
[NUM_RTX_CODE
];
65 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
66 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
67 SIGN_EXTEND then while narrowing we also have to enforce the
68 representation and sign-extend the value to mode DESTINATION_REP.
70 If the value is already sign-extended to DESTINATION_REP mode we
71 can just switch to DESTINATION mode on it. For each pair of
72 integral modes SOURCE and DESTINATION, when truncating from SOURCE
73 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
74 contains the number of high-order bits in SOURCE that have to be
75 copies of the sign-bit so that we can do this mode-switch to
79 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
81 /* Return 1 if the value of X is unstable
82 (would be different at a different point in the program).
83 The frame pointer, arg pointer, etc. are considered stable
84 (within one function) and so is anything marked `unchanging'. */
87 rtx_unstable_p (const_rtx x
)
89 const RTX_CODE code
= GET_CODE (x
);
96 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
105 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
106 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
107 /* The arg pointer varies if it is not a fixed register. */
108 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
110 /* ??? When call-clobbered, the value is stable modulo the restore
111 that must happen after a call. This currently screws up local-alloc
112 into believing that the restore is not needed. */
113 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
118 if (MEM_VOLATILE_P (x
))
127 fmt
= GET_RTX_FORMAT (code
);
128 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
131 if (rtx_unstable_p (XEXP (x
, i
)))
134 else if (fmt
[i
] == 'E')
137 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
138 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
145 /* Return 1 if X has a value that can vary even between two
146 executions of the program. 0 means X can be compared reliably
147 against certain constants or near-constants.
148 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
149 zero, we are slightly more conservative.
150 The frame pointer and the arg pointer are considered constant. */
153 rtx_varies_p (const_rtx x
, bool for_alias
)
166 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
175 /* Note that we have to test for the actual rtx used for the frame
176 and arg pointers and not just the register number in case we have
177 eliminated the frame and/or arg pointer and are using it
179 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
180 /* The arg pointer varies if it is not a fixed register. */
181 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
183 if (x
== pic_offset_table_rtx
184 /* ??? When call-clobbered, the value is stable modulo the restore
185 that must happen after a call. This currently screws up
186 local-alloc into believing that the restore is not needed, so we
187 must return 0 only if we are called from alias analysis. */
188 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
193 /* The operand 0 of a LO_SUM is considered constant
194 (in fact it is related specifically to operand 1)
195 during alias analysis. */
196 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
197 || rtx_varies_p (XEXP (x
, 1), for_alias
);
200 if (MEM_VOLATILE_P (x
))
209 fmt
= GET_RTX_FORMAT (code
);
210 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
213 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
216 else if (fmt
[i
] == 'E')
219 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
220 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
227 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
228 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
229 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
230 references on strict alignment machines. */
233 rtx_addr_can_trap_p_1 (const_rtx x
, HOST_WIDE_INT offset
, HOST_WIDE_INT size
,
234 enum machine_mode mode
, bool unaligned_mems
)
236 enum rtx_code code
= GET_CODE (x
);
238 /* The offset must be a multiple of the mode size if we are considering
239 unaligned memory references on strict alignment machines. */
240 if (STRICT_ALIGNMENT
&& unaligned_mems
&& GET_MODE_SIZE (mode
) != 0)
242 HOST_WIDE_INT actual_offset
= offset
;
244 #ifdef SPARC_STACK_BOUNDARY_HACK
245 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
246 the real alignment of %sp. However, when it does this, the
247 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
248 if (SPARC_STACK_BOUNDARY_HACK
249 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
250 actual_offset
-= STACK_POINTER_OFFSET
;
253 if (actual_offset
% GET_MODE_SIZE (mode
) != 0)
260 if (SYMBOL_REF_WEAK (x
))
262 if (!CONSTANT_POOL_ADDRESS_P (x
))
265 HOST_WIDE_INT decl_size
;
270 size
= GET_MODE_SIZE (mode
);
274 /* If the size of the access or of the symbol is unknown,
276 decl
= SYMBOL_REF_DECL (x
);
278 /* Else check that the access is in bounds. TODO: restructure
279 expr_size/tree_expr_size/int_expr_size and just use the latter. */
282 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
283 decl_size
= (host_integerp (DECL_SIZE_UNIT (decl
), 0)
284 ? tree_low_cst (DECL_SIZE_UNIT (decl
), 0)
286 else if (TREE_CODE (decl
) == STRING_CST
)
287 decl_size
= TREE_STRING_LENGTH (decl
);
288 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
289 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
293 return (decl_size
<= 0 ? offset
!= 0 : offset
+ size
> decl_size
);
302 /* Stack references are assumed not to trap, but we need to deal with
303 nonsensical offsets. */
304 if (x
== frame_pointer_rtx
)
306 HOST_WIDE_INT adj_offset
= offset
- STARTING_FRAME_OFFSET
;
308 size
= GET_MODE_SIZE (mode
);
309 if (FRAME_GROWS_DOWNWARD
)
311 if (adj_offset
< frame_offset
|| adj_offset
+ size
- 1 >= 0)
316 if (adj_offset
< 0 || adj_offset
+ size
- 1 >= frame_offset
)
321 /* ??? Need to add a similar guard for nonsensical offsets. */
322 if (x
== hard_frame_pointer_rtx
323 || x
== stack_pointer_rtx
324 /* The arg pointer varies if it is not a fixed register. */
325 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
327 /* All of the virtual frame registers are stack references. */
328 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
329 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
334 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
335 mode
, unaligned_mems
);
338 /* An address is assumed not to trap if:
339 - it is the pic register plus a constant. */
340 if (XEXP (x
, 0) == pic_offset_table_rtx
&& CONSTANT_P (XEXP (x
, 1)))
343 /* - or it is an address that can't trap plus a constant integer. */
344 if (CONST_INT_P (XEXP (x
, 1))
345 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ INTVAL (XEXP (x
, 1)),
346 size
, mode
, unaligned_mems
))
353 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
354 mode
, unaligned_mems
);
361 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
362 mode
, unaligned_mems
);
368 /* If it isn't one of the case above, it can cause a trap. */
372 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
375 rtx_addr_can_trap_p (const_rtx x
)
377 return rtx_addr_can_trap_p_1 (x
, 0, 0, VOIDmode
, false);
380 /* Return true if X is an address that is known to not be zero. */
383 nonzero_address_p (const_rtx x
)
385 const enum rtx_code code
= GET_CODE (x
);
390 return !SYMBOL_REF_WEAK (x
);
396 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
397 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
398 || x
== stack_pointer_rtx
399 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
401 /* All of the virtual frame registers are stack references. */
402 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
403 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
408 return nonzero_address_p (XEXP (x
, 0));
411 /* Handle PIC references. */
412 if (XEXP (x
, 0) == pic_offset_table_rtx
413 && CONSTANT_P (XEXP (x
, 1)))
418 /* Similar to the above; allow positive offsets. Further, since
419 auto-inc is only allowed in memories, the register must be a
421 if (CONST_INT_P (XEXP (x
, 1))
422 && INTVAL (XEXP (x
, 1)) > 0)
424 return nonzero_address_p (XEXP (x
, 0));
427 /* Similarly. Further, the offset is always positive. */
434 return nonzero_address_p (XEXP (x
, 0));
437 return nonzero_address_p (XEXP (x
, 1));
443 /* If it isn't one of the case above, might be zero. */
447 /* Return 1 if X refers to a memory location whose address
448 cannot be compared reliably with constant addresses,
449 or if X refers to a BLKmode memory object.
450 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
451 zero, we are slightly more conservative. */
454 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
465 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
467 fmt
= GET_RTX_FORMAT (code
);
468 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
471 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
474 else if (fmt
[i
] == 'E')
477 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
478 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
484 /* Return the CALL in X if there is one. */
487 get_call_rtx_from (rtx x
)
491 if (GET_CODE (x
) == PARALLEL
)
492 x
= XVECEXP (x
, 0, 0);
493 if (GET_CODE (x
) == SET
)
495 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
500 /* Return the value of the integer term in X, if one is apparent;
502 Only obvious integer terms are detected.
503 This is used in cse.c with the `related_value' field. */
506 get_integer_term (const_rtx x
)
508 if (GET_CODE (x
) == CONST
)
511 if (GET_CODE (x
) == MINUS
512 && CONST_INT_P (XEXP (x
, 1)))
513 return - INTVAL (XEXP (x
, 1));
514 if (GET_CODE (x
) == PLUS
515 && CONST_INT_P (XEXP (x
, 1)))
516 return INTVAL (XEXP (x
, 1));
520 /* If X is a constant, return the value sans apparent integer term;
522 Only obvious integer terms are detected. */
525 get_related_value (const_rtx x
)
527 if (GET_CODE (x
) != CONST
)
530 if (GET_CODE (x
) == PLUS
531 && CONST_INT_P (XEXP (x
, 1)))
533 else if (GET_CODE (x
) == MINUS
534 && CONST_INT_P (XEXP (x
, 1)))
539 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
540 to somewhere in the same object or object_block as SYMBOL. */
543 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
547 if (GET_CODE (symbol
) != SYMBOL_REF
)
555 if (CONSTANT_POOL_ADDRESS_P (symbol
)
556 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
559 decl
= SYMBOL_REF_DECL (symbol
);
560 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
564 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
565 && SYMBOL_REF_BLOCK (symbol
)
566 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
567 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
568 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
574 /* Split X into a base and a constant offset, storing them in *BASE_OUT
575 and *OFFSET_OUT respectively. */
578 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
580 if (GET_CODE (x
) == CONST
)
583 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
585 *base_out
= XEXP (x
, 0);
586 *offset_out
= XEXP (x
, 1);
591 *offset_out
= const0_rtx
;
594 /* Return the number of places FIND appears within X. If COUNT_DEST is
595 zero, we do not count occurrences inside the destination of a SET. */
598 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
602 const char *format_ptr
;
621 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
623 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
627 if (MEM_P (find
) && rtx_equal_p (x
, find
))
632 if (SET_DEST (x
) == find
&& ! count_dest
)
633 return count_occurrences (SET_SRC (x
), find
, count_dest
);
640 format_ptr
= GET_RTX_FORMAT (code
);
643 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
645 switch (*format_ptr
++)
648 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
652 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
653 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
661 /* Return TRUE if OP is a register or subreg of a register that
662 holds an unsigned quantity. Otherwise, return FALSE. */
665 unsigned_reg_p (rtx op
)
669 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
672 if (GET_CODE (op
) == SUBREG
673 && SUBREG_PROMOTED_UNSIGNED_P (op
))
680 /* Nonzero if register REG appears somewhere within IN.
681 Also works if REG is not a register; in this case it checks
682 for a subexpression of IN that is Lisp "equal" to REG. */
685 reg_mentioned_p (const_rtx reg
, const_rtx in
)
697 if (GET_CODE (in
) == LABEL_REF
)
698 return reg
== XEXP (in
, 0);
700 code
= GET_CODE (in
);
704 /* Compare registers by number. */
706 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
708 /* These codes have no constituent expressions
716 /* These are kept unique for a given value. */
723 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
726 fmt
= GET_RTX_FORMAT (code
);
728 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
733 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
734 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
737 else if (fmt
[i
] == 'e'
738 && reg_mentioned_p (reg
, XEXP (in
, i
)))
744 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
745 no CODE_LABEL insn. */
748 no_labels_between_p (const_rtx beg
, const_rtx end
)
753 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
759 /* Nonzero if register REG is used in an insn between
760 FROM_INSN and TO_INSN (exclusive of those two). */
763 reg_used_between_p (const_rtx reg
, const_rtx from_insn
, const_rtx to_insn
)
767 if (from_insn
== to_insn
)
770 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
771 if (NONDEBUG_INSN_P (insn
)
772 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
773 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
778 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
779 is entirely replaced by a new value and the only use is as a SET_DEST,
780 we do not consider it a reference. */
783 reg_referenced_p (const_rtx x
, const_rtx body
)
787 switch (GET_CODE (body
))
790 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
793 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
794 of a REG that occupies all of the REG, the insn references X if
795 it is mentioned in the destination. */
796 if (GET_CODE (SET_DEST (body
)) != CC0
797 && GET_CODE (SET_DEST (body
)) != PC
798 && !REG_P (SET_DEST (body
))
799 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
800 && REG_P (SUBREG_REG (SET_DEST (body
)))
801 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body
))))
802 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
803 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body
)))
804 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
805 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
810 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
811 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
818 return reg_overlap_mentioned_p (x
, body
);
821 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
824 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
827 case UNSPEC_VOLATILE
:
828 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
829 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
834 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
835 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
840 if (MEM_P (XEXP (body
, 0)))
841 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
846 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
848 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
855 /* Nonzero if register REG is set or clobbered in an insn between
856 FROM_INSN and TO_INSN (exclusive of those two). */
859 reg_set_between_p (const_rtx reg
, const_rtx from_insn
, const_rtx to_insn
)
863 if (from_insn
== to_insn
)
866 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
867 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
872 /* Internals of reg_set_between_p. */
874 reg_set_p (const_rtx reg
, const_rtx insn
)
876 /* We can be passed an insn or part of one. If we are passed an insn,
877 check if a side-effect of the insn clobbers REG. */
879 && (FIND_REG_INC_NOTE (insn
, reg
)
882 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
883 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
884 GET_MODE (reg
), REGNO (reg
)))
886 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
889 return set_of (reg
, insn
) != NULL_RTX
;
892 /* Similar to reg_set_between_p, but check all registers in X. Return 0
893 only if none of them are modified between START and END. Return 1 if
894 X contains a MEM; this routine does use memory aliasing. */
897 modified_between_p (const_rtx x
, const_rtx start
, const_rtx end
)
899 const enum rtx_code code
= GET_CODE (x
);
920 if (modified_between_p (XEXP (x
, 0), start
, end
))
922 if (MEM_READONLY_P (x
))
924 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
925 if (memory_modified_in_insn_p (x
, insn
))
931 return reg_set_between_p (x
, start
, end
);
937 fmt
= GET_RTX_FORMAT (code
);
938 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
940 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
943 else if (fmt
[i
] == 'E')
944 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
945 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
952 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
953 of them are modified in INSN. Return 1 if X contains a MEM; this routine
954 does use memory aliasing. */
957 modified_in_p (const_rtx x
, const_rtx insn
)
959 const enum rtx_code code
= GET_CODE (x
);
976 if (modified_in_p (XEXP (x
, 0), insn
))
978 if (MEM_READONLY_P (x
))
980 if (memory_modified_in_insn_p (x
, insn
))
986 return reg_set_p (x
, insn
);
992 fmt
= GET_RTX_FORMAT (code
);
993 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
995 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
998 else if (fmt
[i
] == 'E')
999 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1000 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1007 /* Helper function for set_of. */
1015 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1017 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1018 if (rtx_equal_p (x
, data
->pat
)
1019 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1023 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1024 (either directly or via STRICT_LOW_PART and similar modifiers). */
1026 set_of (const_rtx pat
, const_rtx insn
)
1028 struct set_of_data data
;
1029 data
.found
= NULL_RTX
;
1031 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1035 /* This function, called through note_stores, collects sets and
1036 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1039 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1041 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1042 if (REG_P (x
) && HARD_REGISTER_P (x
))
1043 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1046 /* Examine INSN, and compute the set of hard registers written by it.
1047 Store it in *PSET. Should only be called after reload. */
1049 find_all_hard_reg_sets (const_rtx insn
, HARD_REG_SET
*pset
)
1053 CLEAR_HARD_REG_SET (*pset
);
1054 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1056 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1057 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1058 if (REG_NOTE_KIND (link
) == REG_INC
)
1059 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1062 /* A for_each_rtx subroutine of record_hard_reg_uses. */
1064 record_hard_reg_uses_1 (rtx
*px
, void *data
)
1067 HARD_REG_SET
*pused
= (HARD_REG_SET
*)data
;
1069 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1071 int nregs
= hard_regno_nregs
[REGNO (x
)][GET_MODE (x
)];
1073 SET_HARD_REG_BIT (*pused
, REGNO (x
) + nregs
);
1078 /* Like record_hard_reg_sets, but called through note_uses. */
1080 record_hard_reg_uses (rtx
*px
, void *data
)
1082 for_each_rtx (px
, record_hard_reg_uses_1
, data
);
1085 /* Given an INSN, return a SET expression if this insn has only a single SET.
1086 It may also have CLOBBERs, USEs, or SET whose output
1087 will not be used, which we ignore. */
1090 single_set_2 (const_rtx insn
, const_rtx pat
)
1093 int set_verified
= 1;
1096 if (GET_CODE (pat
) == PARALLEL
)
1098 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1100 rtx sub
= XVECEXP (pat
, 0, i
);
1101 switch (GET_CODE (sub
))
1108 /* We can consider insns having multiple sets, where all
1109 but one are dead as single set insns. In common case
1110 only single set is present in the pattern so we want
1111 to avoid checking for REG_UNUSED notes unless necessary.
1113 When we reach set first time, we just expect this is
1114 the single set we are looking for and only when more
1115 sets are found in the insn, we check them. */
1118 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1119 && !side_effects_p (set
))
1125 set
= sub
, set_verified
= 0;
1126 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1127 || side_effects_p (sub
))
1139 /* Given an INSN, return nonzero if it has more than one SET, else return
1143 multiple_sets (const_rtx insn
)
1148 /* INSN must be an insn. */
1149 if (! INSN_P (insn
))
1152 /* Only a PARALLEL can have multiple SETs. */
1153 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1155 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1156 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1158 /* If we have already found a SET, then return now. */
1166 /* Either zero or one SET. */
1170 /* Return nonzero if the destination of SET equals the source
1171 and there are no side effects. */
1174 set_noop_p (const_rtx set
)
1176 rtx src
= SET_SRC (set
);
1177 rtx dst
= SET_DEST (set
);
1179 if (dst
== pc_rtx
&& src
== pc_rtx
)
1182 if (MEM_P (dst
) && MEM_P (src
))
1183 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1185 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1186 return rtx_equal_p (XEXP (dst
, 0), src
)
1187 && ! BYTES_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1188 && !side_effects_p (src
);
1190 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1191 dst
= XEXP (dst
, 0);
1193 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1195 if (SUBREG_BYTE (src
) != SUBREG_BYTE (dst
))
1197 src
= SUBREG_REG (src
);
1198 dst
= SUBREG_REG (dst
);
1201 return (REG_P (src
) && REG_P (dst
)
1202 && REGNO (src
) == REGNO (dst
));
1205 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1209 noop_move_p (const_rtx insn
)
1211 rtx pat
= PATTERN (insn
);
1213 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1216 /* Insns carrying these notes are useful later on. */
1217 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1220 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1223 if (GET_CODE (pat
) == PARALLEL
)
1226 /* If nothing but SETs of registers to themselves,
1227 this insn can also be deleted. */
1228 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1230 rtx tem
= XVECEXP (pat
, 0, i
);
1232 if (GET_CODE (tem
) == USE
1233 || GET_CODE (tem
) == CLOBBER
)
1236 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1246 /* Return the last thing that X was assigned from before *PINSN. If VALID_TO
1247 is not NULL_RTX then verify that the object is not modified up to VALID_TO.
1248 If the object was modified, if we hit a partial assignment to X, or hit a
1249 CODE_LABEL first, return X. If we found an assignment, update *PINSN to
1250 point to it. ALLOW_HWREG is set to 1 if hardware registers are allowed to
1254 find_last_value (rtx x
, rtx
*pinsn
, rtx valid_to
, int allow_hwreg
)
1258 for (p
= PREV_INSN (*pinsn
); p
&& !LABEL_P (p
);
1262 rtx set
= single_set (p
);
1263 rtx note
= find_reg_note (p
, REG_EQUAL
, NULL_RTX
);
1265 if (set
&& rtx_equal_p (x
, SET_DEST (set
)))
1267 rtx src
= SET_SRC (set
);
1269 if (note
&& GET_CODE (XEXP (note
, 0)) != EXPR_LIST
)
1270 src
= XEXP (note
, 0);
1272 if ((valid_to
== NULL_RTX
1273 || ! modified_between_p (src
, PREV_INSN (p
), valid_to
))
1274 /* Reject hard registers because we don't usually want
1275 to use them; we'd rather use a pseudo. */
1277 && REGNO (src
) < FIRST_PSEUDO_REGISTER
) || allow_hwreg
))
1284 /* If set in non-simple way, we don't have a value. */
1285 if (reg_set_p (x
, p
))
1292 /* Return nonzero if register in range [REGNO, ENDREGNO)
1293 appears either explicitly or implicitly in X
1294 other than being stored into.
1296 References contained within the substructure at LOC do not count.
1297 LOC may be zero, meaning don't ignore anything. */
1300 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1304 unsigned int x_regno
;
1309 /* The contents of a REG_NONNEG note is always zero, so we must come here
1310 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1314 code
= GET_CODE (x
);
1319 x_regno
= REGNO (x
);
1321 /* If we modifying the stack, frame, or argument pointer, it will
1322 clobber a virtual register. In fact, we could be more precise,
1323 but it isn't worth it. */
1324 if ((x_regno
== STACK_POINTER_REGNUM
1325 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1326 || x_regno
== ARG_POINTER_REGNUM
1328 || x_regno
== FRAME_POINTER_REGNUM
)
1329 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1332 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1335 /* If this is a SUBREG of a hard reg, we can see exactly which
1336 registers are being modified. Otherwise, handle normally. */
1337 if (REG_P (SUBREG_REG (x
))
1338 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1340 unsigned int inner_regno
= subreg_regno (x
);
1341 unsigned int inner_endregno
1342 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1343 ? subreg_nregs (x
) : 1);
1345 return endregno
> inner_regno
&& regno
< inner_endregno
;
1351 if (&SET_DEST (x
) != loc
1352 /* Note setting a SUBREG counts as referring to the REG it is in for
1353 a pseudo but not for hard registers since we can
1354 treat each word individually. */
1355 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1356 && loc
!= &SUBREG_REG (SET_DEST (x
))
1357 && REG_P (SUBREG_REG (SET_DEST (x
)))
1358 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1359 && refers_to_regno_p (regno
, endregno
,
1360 SUBREG_REG (SET_DEST (x
)), loc
))
1361 || (!REG_P (SET_DEST (x
))
1362 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1365 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1374 /* X does not match, so try its subexpressions. */
1376 fmt
= GET_RTX_FORMAT (code
);
1377 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1379 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1387 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1390 else if (fmt
[i
] == 'E')
1393 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1394 if (loc
!= &XVECEXP (x
, i
, j
)
1395 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1402 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1403 we check if any register number in X conflicts with the relevant register
1404 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1405 contains a MEM (we don't bother checking for memory addresses that can't
1406 conflict because we expect this to be a rare case. */
1409 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1411 unsigned int regno
, endregno
;
1413 /* If either argument is a constant, then modifying X can not
1414 affect IN. Here we look at IN, we can profitably combine
1415 CONSTANT_P (x) with the switch statement below. */
1416 if (CONSTANT_P (in
))
1420 switch (GET_CODE (x
))
1422 case STRICT_LOW_PART
:
1425 /* Overly conservative. */
1430 regno
= REGNO (SUBREG_REG (x
));
1431 if (regno
< FIRST_PSEUDO_REGISTER
)
1432 regno
= subreg_regno (x
);
1433 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1434 ? subreg_nregs (x
) : 1);
1439 endregno
= END_REGNO (x
);
1441 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1451 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1452 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1455 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1458 else if (fmt
[i
] == 'E')
1461 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1462 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1472 return reg_mentioned_p (x
, in
);
1478 /* If any register in here refers to it we return true. */
1479 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1480 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1481 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1487 gcc_assert (CONSTANT_P (x
));
1492 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1493 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1494 ignored by note_stores, but passed to FUN.
1496 FUN receives three arguments:
1497 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1498 2. the SET or CLOBBER rtx that does the store,
1499 3. the pointer DATA provided to note_stores.
1501 If the item being stored in or clobbered is a SUBREG of a hard register,
1502 the SUBREG will be passed. */
1505 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1509 if (GET_CODE (x
) == COND_EXEC
)
1510 x
= COND_EXEC_CODE (x
);
1512 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1514 rtx dest
= SET_DEST (x
);
1516 while ((GET_CODE (dest
) == SUBREG
1517 && (!REG_P (SUBREG_REG (dest
))
1518 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1519 || GET_CODE (dest
) == ZERO_EXTRACT
1520 || GET_CODE (dest
) == STRICT_LOW_PART
)
1521 dest
= XEXP (dest
, 0);
1523 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1524 each of whose first operand is a register. */
1525 if (GET_CODE (dest
) == PARALLEL
)
1527 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1528 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1529 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1532 (*fun
) (dest
, x
, data
);
1535 else if (GET_CODE (x
) == PARALLEL
)
1536 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1537 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1540 /* Like notes_stores, but call FUN for each expression that is being
1541 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1542 FUN for each expression, not any interior subexpressions. FUN receives a
1543 pointer to the expression and the DATA passed to this function.
1545 Note that this is not quite the same test as that done in reg_referenced_p
1546 since that considers something as being referenced if it is being
1547 partially set, while we do not. */
1550 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1555 switch (GET_CODE (body
))
1558 (*fun
) (&COND_EXEC_TEST (body
), data
);
1559 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1563 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1564 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1568 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1569 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1573 (*fun
) (&XEXP (body
, 0), data
);
1577 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1578 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1582 (*fun
) (&TRAP_CONDITION (body
), data
);
1586 (*fun
) (&XEXP (body
, 0), data
);
1590 case UNSPEC_VOLATILE
:
1591 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1592 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1596 if (MEM_P (XEXP (body
, 0)))
1597 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
1602 rtx dest
= SET_DEST (body
);
1604 /* For sets we replace everything in source plus registers in memory
1605 expression in store and operands of a ZERO_EXTRACT. */
1606 (*fun
) (&SET_SRC (body
), data
);
1608 if (GET_CODE (dest
) == ZERO_EXTRACT
)
1610 (*fun
) (&XEXP (dest
, 1), data
);
1611 (*fun
) (&XEXP (dest
, 2), data
);
1614 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
1615 dest
= XEXP (dest
, 0);
1618 (*fun
) (&XEXP (dest
, 0), data
);
1623 /* All the other possibilities never store. */
1624 (*fun
) (pbody
, data
);
1629 /* Return nonzero if X's old contents don't survive after INSN.
1630 This will be true if X is (cc0) or if X is a register and
1631 X dies in INSN or because INSN entirely sets X.
1633 "Entirely set" means set directly and not through a SUBREG, or
1634 ZERO_EXTRACT, so no trace of the old contents remains.
1635 Likewise, REG_INC does not count.
1637 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1638 but for this use that makes no difference, since regs don't overlap
1639 during their lifetimes. Therefore, this function may be used
1640 at any time after deaths have been computed.
1642 If REG is a hard reg that occupies multiple machine registers, this
1643 function will only return 1 if each of those registers will be replaced
1647 dead_or_set_p (const_rtx insn
, const_rtx x
)
1649 unsigned int regno
, end_regno
;
1652 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1653 if (GET_CODE (x
) == CC0
)
1656 gcc_assert (REG_P (x
));
1659 end_regno
= END_REGNO (x
);
1660 for (i
= regno
; i
< end_regno
; i
++)
1661 if (! dead_or_set_regno_p (insn
, i
))
1667 /* Return TRUE iff DEST is a register or subreg of a register and
1668 doesn't change the number of words of the inner register, and any
1669 part of the register is TEST_REGNO. */
1672 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
1674 unsigned int regno
, endregno
;
1676 if (GET_CODE (dest
) == SUBREG
1677 && (((GET_MODE_SIZE (GET_MODE (dest
))
1678 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
1679 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
1680 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)))
1681 dest
= SUBREG_REG (dest
);
1686 regno
= REGNO (dest
);
1687 endregno
= END_REGNO (dest
);
1688 return (test_regno
>= regno
&& test_regno
< endregno
);
1691 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
1692 any member matches the covers_regno_no_parallel_p criteria. */
1695 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
1697 if (GET_CODE (dest
) == PARALLEL
)
1699 /* Some targets place small structures in registers for return
1700 values of functions, and those registers are wrapped in
1701 PARALLELs that we may see as the destination of a SET. */
1704 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1706 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
1707 if (inner
!= NULL_RTX
1708 && covers_regno_no_parallel_p (inner
, test_regno
))
1715 return covers_regno_no_parallel_p (dest
, test_regno
);
1718 /* Utility function for dead_or_set_p to check an individual register. */
1721 dead_or_set_regno_p (const_rtx insn
, unsigned int test_regno
)
1725 /* See if there is a death note for something that includes TEST_REGNO. */
1726 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
1730 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
1733 pattern
= PATTERN (insn
);
1735 /* If a COND_EXEC is not executed, the value survives. */
1736 if (GET_CODE (pattern
) == COND_EXEC
)
1739 if (GET_CODE (pattern
) == SET
)
1740 return covers_regno_p (SET_DEST (pattern
), test_regno
);
1741 else if (GET_CODE (pattern
) == PARALLEL
)
1745 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
1747 rtx body
= XVECEXP (pattern
, 0, i
);
1749 if (GET_CODE (body
) == COND_EXEC
)
1750 body
= COND_EXEC_CODE (body
);
1752 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
1753 && covers_regno_p (SET_DEST (body
), test_regno
))
1761 /* Return the reg-note of kind KIND in insn INSN, if there is one.
1762 If DATUM is nonzero, look for one whose datum is DATUM. */
1765 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
1769 gcc_checking_assert (insn
);
1771 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
1772 if (! INSN_P (insn
))
1776 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1777 if (REG_NOTE_KIND (link
) == kind
)
1782 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1783 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
1788 /* Return the reg-note of kind KIND in insn INSN which applies to register
1789 number REGNO, if any. Return 0 if there is no such reg-note. Note that
1790 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
1791 it might be the case that the note overlaps REGNO. */
1794 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
1798 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
1799 if (! INSN_P (insn
))
1802 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1803 if (REG_NOTE_KIND (link
) == kind
1804 /* Verify that it is a register, so that scratch and MEM won't cause a
1806 && REG_P (XEXP (link
, 0))
1807 && REGNO (XEXP (link
, 0)) <= regno
1808 && END_REGNO (XEXP (link
, 0)) > regno
)
1813 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
1817 find_reg_equal_equiv_note (const_rtx insn
)
1824 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1825 if (REG_NOTE_KIND (link
) == REG_EQUAL
1826 || REG_NOTE_KIND (link
) == REG_EQUIV
)
1828 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
1829 insns that have multiple sets. Checking single_set to
1830 make sure of this is not the proper check, as explained
1831 in the comment in set_unique_reg_note.
1833 This should be changed into an assert. */
1834 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
1841 /* Check whether INSN is a single_set whose source is known to be
1842 equivalent to a constant. Return that constant if so, otherwise
1846 find_constant_src (const_rtx insn
)
1850 set
= single_set (insn
);
1853 x
= avoid_constant_pool_reference (SET_SRC (set
));
1858 note
= find_reg_equal_equiv_note (insn
);
1859 if (note
&& CONSTANT_P (XEXP (note
, 0)))
1860 return XEXP (note
, 0);
1865 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
1866 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
1869 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
1871 /* If it's not a CALL_INSN, it can't possibly have a
1872 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
1882 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1884 link
= XEXP (link
, 1))
1885 if (GET_CODE (XEXP (link
, 0)) == code
1886 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
1891 unsigned int regno
= REGNO (datum
);
1893 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
1894 to pseudo registers, so don't bother checking. */
1896 if (regno
< FIRST_PSEUDO_REGISTER
)
1898 unsigned int end_regno
= END_HARD_REGNO (datum
);
1901 for (i
= regno
; i
< end_regno
; i
++)
1902 if (find_regno_fusage (insn
, code
, i
))
1910 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
1911 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
1914 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
1918 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
1919 to pseudo registers, so don't bother checking. */
1921 if (regno
>= FIRST_PSEUDO_REGISTER
1925 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1929 if (GET_CODE (op
= XEXP (link
, 0)) == code
1930 && REG_P (reg
= XEXP (op
, 0))
1931 && REGNO (reg
) <= regno
1932 && END_HARD_REGNO (reg
) > regno
)
1940 /* Allocate a register note with kind KIND and datum DATUM. LIST is
1941 stored as the pointer to the next register note. */
1944 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
1952 case REG_LABEL_TARGET
:
1953 case REG_LABEL_OPERAND
:
1955 /* These types of register notes use an INSN_LIST rather than an
1956 EXPR_LIST, so that copying is done right and dumps look
1958 note
= alloc_INSN_LIST (datum
, list
);
1959 PUT_REG_NOTE_KIND (note
, kind
);
1963 note
= alloc_EXPR_LIST (kind
, datum
, list
);
1970 /* Add register note with kind KIND and datum DATUM to INSN. */
1973 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
1975 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
1978 /* Remove register note NOTE from the REG_NOTES of INSN. */
1981 remove_note (rtx insn
, const_rtx note
)
1985 if (note
== NULL_RTX
)
1988 if (REG_NOTES (insn
) == note
)
1989 REG_NOTES (insn
) = XEXP (note
, 1);
1991 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1992 if (XEXP (link
, 1) == note
)
1994 XEXP (link
, 1) = XEXP (note
, 1);
1998 switch (REG_NOTE_KIND (note
))
2002 df_notes_rescan (insn
);
2009 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes. */
2012 remove_reg_equal_equiv_notes (rtx insn
)
2016 loc
= ®_NOTES (insn
);
2019 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2020 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2021 *loc
= XEXP (*loc
, 1);
2023 loc
= &XEXP (*loc
, 1);
2027 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2030 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2037 /* This loop is a little tricky. We cannot just go down the chain because
2038 it is being modified by some actions in the loop. So we just iterate
2039 over the head. We plan to drain the list anyway. */
2040 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2042 rtx insn
= DF_REF_INSN (eq_use
);
2043 rtx note
= find_reg_equal_equiv_note (insn
);
2045 /* This assert is generally triggered when someone deletes a REG_EQUAL
2046 or REG_EQUIV note by hacking the list manually rather than calling
2050 remove_note (insn
, note
);
2054 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2055 return 1 if it is found. A simple equality test is used to determine if
2059 in_expr_list_p (const_rtx listp
, const_rtx node
)
2063 for (x
= listp
; x
; x
= XEXP (x
, 1))
2064 if (node
== XEXP (x
, 0))
2070 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2071 remove that entry from the list if it is found.
2073 A simple equality test is used to determine if NODE matches. */
2076 remove_node_from_expr_list (const_rtx node
, rtx
*listp
)
2079 rtx prev
= NULL_RTX
;
2083 if (node
== XEXP (temp
, 0))
2085 /* Splice the node out of the list. */
2087 XEXP (prev
, 1) = XEXP (temp
, 1);
2089 *listp
= XEXP (temp
, 1);
2095 temp
= XEXP (temp
, 1);
2099 /* Nonzero if X contains any volatile instructions. These are instructions
2100 which may cause unpredictable machine state instructions, and thus no
2101 instructions or register uses should be moved or combined across them.
2102 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2105 volatile_insn_p (const_rtx x
)
2107 const RTX_CODE code
= GET_CODE (x
);
2125 case UNSPEC_VOLATILE
:
2130 if (MEM_VOLATILE_P (x
))
2137 /* Recursively scan the operands of this expression. */
2140 const char *const fmt
= GET_RTX_FORMAT (code
);
2143 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2147 if (volatile_insn_p (XEXP (x
, i
)))
2150 else if (fmt
[i
] == 'E')
2153 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2154 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2162 /* Nonzero if X contains any volatile memory references
2163 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2166 volatile_refs_p (const_rtx x
)
2168 const RTX_CODE code
= GET_CODE (x
);
2184 case UNSPEC_VOLATILE
:
2190 if (MEM_VOLATILE_P (x
))
2197 /* Recursively scan the operands of this expression. */
2200 const char *const fmt
= GET_RTX_FORMAT (code
);
2203 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2207 if (volatile_refs_p (XEXP (x
, i
)))
2210 else if (fmt
[i
] == 'E')
2213 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2214 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2222 /* Similar to above, except that it also rejects register pre- and post-
2226 side_effects_p (const_rtx x
)
2228 const RTX_CODE code
= GET_CODE (x
);
2245 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2246 when some combination can't be done. If we see one, don't think
2247 that we can simplify the expression. */
2248 return (GET_MODE (x
) != VOIDmode
);
2257 case UNSPEC_VOLATILE
:
2263 if (MEM_VOLATILE_P (x
))
2270 /* Recursively scan the operands of this expression. */
2273 const char *fmt
= GET_RTX_FORMAT (code
);
2276 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2280 if (side_effects_p (XEXP (x
, i
)))
2283 else if (fmt
[i
] == 'E')
2286 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2287 if (side_effects_p (XVECEXP (x
, i
, j
)))
2295 /* Return nonzero if evaluating rtx X might cause a trap.
2296 FLAGS controls how to consider MEMs. A nonzero means the context
2297 of the access may have changed from the original, such that the
2298 address may have become invalid. */
2301 may_trap_p_1 (const_rtx x
, unsigned flags
)
2307 /* We make no distinction currently, but this function is part of
2308 the internal target-hooks ABI so we keep the parameter as
2309 "unsigned flags". */
2310 bool code_changed
= flags
!= 0;
2314 code
= GET_CODE (x
);
2317 /* Handle these cases quickly. */
2329 return targetm
.unspec_may_trap_p (x
, flags
);
2331 case UNSPEC_VOLATILE
:
2337 return MEM_VOLATILE_P (x
);
2339 /* Memory ref can trap unless it's a static var or a stack slot. */
2341 /* Recognize specific pattern of stack checking probes. */
2342 if (flag_stack_check
2343 && MEM_VOLATILE_P (x
)
2344 && XEXP (x
, 0) == stack_pointer_rtx
)
2346 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2347 reference; moving it out of context such as when moving code
2348 when optimizing, might cause its address to become invalid. */
2350 || !MEM_NOTRAP_P (x
))
2352 HOST_WIDE_INT size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : 0;
2353 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2354 GET_MODE (x
), code_changed
);
2359 /* Division by a non-constant might trap. */
2364 if (HONOR_SNANS (GET_MODE (x
)))
2366 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)))
2367 return flag_trapping_math
;
2368 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2373 /* An EXPR_LIST is used to represent a function call. This
2374 certainly may trap. */
2383 /* Some floating point comparisons may trap. */
2384 if (!flag_trapping_math
)
2386 /* ??? There is no machine independent way to check for tests that trap
2387 when COMPARE is used, though many targets do make this distinction.
2388 For instance, sparc uses CCFPE for compares which generate exceptions
2389 and CCFP for compares which do not generate exceptions. */
2390 if (HONOR_NANS (GET_MODE (x
)))
2392 /* But often the compare has some CC mode, so check operand
2394 if (HONOR_NANS (GET_MODE (XEXP (x
, 0)))
2395 || HONOR_NANS (GET_MODE (XEXP (x
, 1))))
2401 if (HONOR_SNANS (GET_MODE (x
)))
2403 /* Often comparison is CC mode, so check operand modes. */
2404 if (HONOR_SNANS (GET_MODE (XEXP (x
, 0)))
2405 || HONOR_SNANS (GET_MODE (XEXP (x
, 1))))
2410 /* Conversion of floating point might trap. */
2411 if (flag_trapping_math
&& HONOR_NANS (GET_MODE (XEXP (x
, 0))))
2418 /* These operations don't trap even with floating point. */
2422 /* Any floating arithmetic may trap. */
2423 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2427 fmt
= GET_RTX_FORMAT (code
);
2428 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2432 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2435 else if (fmt
[i
] == 'E')
2438 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2439 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2446 /* Return nonzero if evaluating rtx X might cause a trap. */
2449 may_trap_p (const_rtx x
)
2451 return may_trap_p_1 (x
, 0);
2454 /* Same as above, but additionally return nonzero if evaluating rtx X might
2455 cause a fault. We define a fault for the purpose of this function as a
2456 erroneous execution condition that cannot be encountered during the normal
2457 execution of a valid program; the typical example is an unaligned memory
2458 access on a strict alignment machine. The compiler guarantees that it
2459 doesn't generate code that will fault from a valid program, but this
2460 guarantee doesn't mean anything for individual instructions. Consider
2461 the following example:
2463 struct S { int d; union { char *cp; int *ip; }; };
2465 int foo(struct S *s)
2473 on a strict alignment machine. In a valid program, foo will never be
2474 invoked on a structure for which d is equal to 1 and the underlying
2475 unique field of the union not aligned on a 4-byte boundary, but the
2476 expression *s->ip might cause a fault if considered individually.
2478 At the RTL level, potentially problematic expressions will almost always
2479 verify may_trap_p; for example, the above dereference can be emitted as
2480 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2481 However, suppose that foo is inlined in a caller that causes s->cp to
2482 point to a local character variable and guarantees that s->d is not set
2483 to 1; foo may have been effectively translated into pseudo-RTL as:
2486 (set (reg:SI) (mem:SI (%fp - 7)))
2488 (set (reg:QI) (mem:QI (%fp - 7)))
2490 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2491 memory reference to a stack slot, but it will certainly cause a fault
2492 on a strict alignment machine. */
2495 may_trap_or_fault_p (const_rtx x
)
2497 return may_trap_p_1 (x
, 1);
2500 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2501 i.e., an inequality. */
2504 inequality_comparisons_p (const_rtx x
)
2508 const enum rtx_code code
= GET_CODE (x
);
2536 len
= GET_RTX_LENGTH (code
);
2537 fmt
= GET_RTX_FORMAT (code
);
2539 for (i
= 0; i
< len
; i
++)
2543 if (inequality_comparisons_p (XEXP (x
, i
)))
2546 else if (fmt
[i
] == 'E')
2549 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2550 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
2558 /* Replace any occurrence of FROM in X with TO. The function does
2559 not enter into CONST_DOUBLE for the replace.
2561 Note that copying is not done so X must not be shared unless all copies
2562 are to be modified. */
2565 replace_rtx (rtx x
, rtx from
, rtx to
)
2573 /* Allow this function to make replacements in EXPR_LISTs. */
2577 if (GET_CODE (x
) == SUBREG
)
2579 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
);
2581 if (CONST_INT_P (new_rtx
))
2583 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
2584 GET_MODE (SUBREG_REG (x
)),
2589 SUBREG_REG (x
) = new_rtx
;
2593 else if (GET_CODE (x
) == ZERO_EXTEND
)
2595 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
);
2597 if (CONST_INT_P (new_rtx
))
2599 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
2600 new_rtx
, GET_MODE (XEXP (x
, 0)));
2604 XEXP (x
, 0) = new_rtx
;
2609 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
2610 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
2613 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
);
2614 else if (fmt
[i
] == 'E')
2615 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2616 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
), from
, to
);
2622 /* Replace occurrences of the old label in *X with the new one.
2623 DATA is a REPLACE_LABEL_DATA containing the old and new labels. */
2626 replace_label (rtx
*x
, void *data
)
2629 rtx old_label
= ((replace_label_data
*) data
)->r1
;
2630 rtx new_label
= ((replace_label_data
*) data
)->r2
;
2631 bool update_label_nuses
= ((replace_label_data
*) data
)->update_label_nuses
;
2636 if (GET_CODE (l
) == SYMBOL_REF
2637 && CONSTANT_POOL_ADDRESS_P (l
))
2639 rtx c
= get_pool_constant (l
);
2640 if (rtx_referenced_p (old_label
, c
))
2643 replace_label_data
*d
= (replace_label_data
*) data
;
2645 /* Create a copy of constant C; replace the label inside
2646 but do not update LABEL_NUSES because uses in constant pool
2648 new_c
= copy_rtx (c
);
2649 d
->update_label_nuses
= false;
2650 for_each_rtx (&new_c
, replace_label
, data
);
2651 d
->update_label_nuses
= update_label_nuses
;
2653 /* Add the new constant NEW_C to constant pool and replace
2654 the old reference to constant by new reference. */
2655 new_l
= XEXP (force_const_mem (get_pool_mode (l
), new_c
), 0);
2656 *x
= replace_rtx (l
, l
, new_l
);
2661 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
2662 field. This is not handled by for_each_rtx because it doesn't
2663 handle unprinted ('0') fields. */
2664 if (JUMP_P (l
) && JUMP_LABEL (l
) == old_label
)
2665 JUMP_LABEL (l
) = new_label
;
2667 if ((GET_CODE (l
) == LABEL_REF
2668 || GET_CODE (l
) == INSN_LIST
)
2669 && XEXP (l
, 0) == old_label
)
2671 XEXP (l
, 0) = new_label
;
2672 if (update_label_nuses
)
2674 ++LABEL_NUSES (new_label
);
2675 --LABEL_NUSES (old_label
);
2683 /* When *BODY is equal to X or X is directly referenced by *BODY
2684 return nonzero, thus FOR_EACH_RTX stops traversing and returns nonzero
2685 too, otherwise FOR_EACH_RTX continues traversing *BODY. */
2688 rtx_referenced_p_1 (rtx
*body
, void *x
)
2692 if (*body
== NULL_RTX
)
2693 return y
== NULL_RTX
;
2695 /* Return true if a label_ref *BODY refers to label Y. */
2696 if (GET_CODE (*body
) == LABEL_REF
&& LABEL_P (y
))
2697 return XEXP (*body
, 0) == y
;
2699 /* If *BODY is a reference to pool constant traverse the constant. */
2700 if (GET_CODE (*body
) == SYMBOL_REF
2701 && CONSTANT_POOL_ADDRESS_P (*body
))
2702 return rtx_referenced_p (y
, get_pool_constant (*body
));
2704 /* By default, compare the RTL expressions. */
2705 return rtx_equal_p (*body
, y
);
2708 /* Return true if X is referenced in BODY. */
2711 rtx_referenced_p (rtx x
, rtx body
)
2713 return for_each_rtx (&body
, rtx_referenced_p_1
, x
);
2716 /* If INSN is a tablejump return true and store the label (before jump table) to
2717 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
2720 tablejump_p (const_rtx insn
, rtx
*labelp
, rtx
*tablep
)
2727 label
= JUMP_LABEL (insn
);
2728 if (label
!= NULL_RTX
&& !ANY_RETURN_P (label
)
2729 && (table
= next_active_insn (label
)) != NULL_RTX
2730 && JUMP_TABLE_DATA_P (table
))
2741 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
2742 constant that is not in the constant pool and not in the condition
2743 of an IF_THEN_ELSE. */
2746 computed_jump_p_1 (const_rtx x
)
2748 const enum rtx_code code
= GET_CODE (x
);
2765 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
2766 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
2769 return (computed_jump_p_1 (XEXP (x
, 1))
2770 || computed_jump_p_1 (XEXP (x
, 2)));
2776 fmt
= GET_RTX_FORMAT (code
);
2777 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2780 && computed_jump_p_1 (XEXP (x
, i
)))
2783 else if (fmt
[i
] == 'E')
2784 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2785 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
2792 /* Return nonzero if INSN is an indirect jump (aka computed jump).
2794 Tablejumps and casesi insns are not considered indirect jumps;
2795 we can recognize them by a (use (label_ref)). */
2798 computed_jump_p (const_rtx insn
)
2803 rtx pat
= PATTERN (insn
);
2805 /* If we have a JUMP_LABEL set, we're not a computed jump. */
2806 if (JUMP_LABEL (insn
) != NULL
)
2809 if (GET_CODE (pat
) == PARALLEL
)
2811 int len
= XVECLEN (pat
, 0);
2812 int has_use_labelref
= 0;
2814 for (i
= len
- 1; i
>= 0; i
--)
2815 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
2816 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
2818 has_use_labelref
= 1;
2820 if (! has_use_labelref
)
2821 for (i
= len
- 1; i
>= 0; i
--)
2822 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
2823 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
2824 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
2827 else if (GET_CODE (pat
) == SET
2828 && SET_DEST (pat
) == pc_rtx
2829 && computed_jump_p_1 (SET_SRC (pat
)))
2835 /* Optimized loop of for_each_rtx, trying to avoid useless recursive
2836 calls. Processes the subexpressions of EXP and passes them to F. */
2838 for_each_rtx_1 (rtx exp
, int n
, rtx_function f
, void *data
)
2841 const char *format
= GET_RTX_FORMAT (GET_CODE (exp
));
2844 for (; format
[n
] != '\0'; n
++)
2851 result
= (*f
) (x
, data
);
2853 /* Do not traverse sub-expressions. */
2855 else if (result
!= 0)
2856 /* Stop the traversal. */
2860 /* There are no sub-expressions. */
2863 i
= non_rtx_starting_operands
[GET_CODE (*x
)];
2866 result
= for_each_rtx_1 (*x
, i
, f
, data
);
2874 if (XVEC (exp
, n
) == 0)
2876 for (j
= 0; j
< XVECLEN (exp
, n
); ++j
)
2879 x
= &XVECEXP (exp
, n
, j
);
2880 result
= (*f
) (x
, data
);
2882 /* Do not traverse sub-expressions. */
2884 else if (result
!= 0)
2885 /* Stop the traversal. */
2889 /* There are no sub-expressions. */
2892 i
= non_rtx_starting_operands
[GET_CODE (*x
)];
2895 result
= for_each_rtx_1 (*x
, i
, f
, data
);
2903 /* Nothing to do. */
2911 /* Traverse X via depth-first search, calling F for each
2912 sub-expression (including X itself). F is also passed the DATA.
2913 If F returns -1, do not traverse sub-expressions, but continue
2914 traversing the rest of the tree. If F ever returns any other
2915 nonzero value, stop the traversal, and return the value returned
2916 by F. Otherwise, return 0. This function does not traverse inside
2917 tree structure that contains RTX_EXPRs, or into sub-expressions
2918 whose format code is `0' since it is not known whether or not those
2919 codes are actually RTL.
2921 This routine is very general, and could (should?) be used to
2922 implement many of the other routines in this file. */
2925 for_each_rtx (rtx
*x
, rtx_function f
, void *data
)
2931 result
= (*f
) (x
, data
);
2933 /* Do not traverse sub-expressions. */
2935 else if (result
!= 0)
2936 /* Stop the traversal. */
2940 /* There are no sub-expressions. */
2943 i
= non_rtx_starting_operands
[GET_CODE (*x
)];
2947 return for_each_rtx_1 (*x
, i
, f
, data
);
2952 /* Data structure that holds the internal state communicated between
2953 for_each_inc_dec, for_each_inc_dec_find_mem and
2954 for_each_inc_dec_find_inc_dec. */
2956 struct for_each_inc_dec_ops
{
2957 /* The function to be called for each autoinc operation found. */
2958 for_each_inc_dec_fn fn
;
2959 /* The opaque argument to be passed to it. */
2961 /* The MEM we're visiting, if any. */
2965 static int for_each_inc_dec_find_mem (rtx
*r
, void *d
);
2967 /* Find PRE/POST-INC/DEC/MODIFY operations within *R, extract the
2968 operands of the equivalent add insn and pass the result to the
2969 operator specified by *D. */
2972 for_each_inc_dec_find_inc_dec (rtx
*r
, void *d
)
2975 struct for_each_inc_dec_ops
*data
= (struct for_each_inc_dec_ops
*)d
;
2977 switch (GET_CODE (x
))
2982 int size
= GET_MODE_SIZE (GET_MODE (data
->mem
));
2983 rtx r1
= XEXP (x
, 0);
2984 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
2985 return data
->fn (data
->mem
, x
, r1
, r1
, c
, data
->arg
);
2991 int size
= GET_MODE_SIZE (GET_MODE (data
->mem
));
2992 rtx r1
= XEXP (x
, 0);
2993 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
2994 return data
->fn (data
->mem
, x
, r1
, r1
, c
, data
->arg
);
3000 rtx r1
= XEXP (x
, 0);
3001 rtx add
= XEXP (x
, 1);
3002 return data
->fn (data
->mem
, x
, r1
, add
, NULL
, data
->arg
);
3007 rtx save
= data
->mem
;
3008 int ret
= for_each_inc_dec_find_mem (r
, d
);
3018 /* If *R is a MEM, find PRE/POST-INC/DEC/MODIFY operations within its
3019 address, extract the operands of the equivalent add insn and pass
3020 the result to the operator specified by *D. */
3023 for_each_inc_dec_find_mem (rtx
*r
, void *d
)
3026 if (x
!= NULL_RTX
&& MEM_P (x
))
3028 struct for_each_inc_dec_ops
*data
= (struct for_each_inc_dec_ops
*) d
;
3033 result
= for_each_rtx (&XEXP (x
, 0), for_each_inc_dec_find_inc_dec
,
3043 /* Traverse *X looking for MEMs, and for autoinc operations within
3044 them. For each such autoinc operation found, call FN, passing it
3045 the innermost enclosing MEM, the operation itself, the RTX modified
3046 by the operation, two RTXs (the second may be NULL) that, once
3047 added, represent the value to be held by the modified RTX
3048 afterwards, and ARG. FN is to return -1 to skip looking for other
3049 autoinc operations within the visited operation, 0 to continue the
3050 traversal, or any other value to have it returned to the caller of
3051 for_each_inc_dec. */
3054 for_each_inc_dec (rtx
*x
,
3055 for_each_inc_dec_fn fn
,
3058 struct for_each_inc_dec_ops data
;
3064 return for_each_rtx (x
, for_each_inc_dec_find_mem
, &data
);
3068 /* Searches X for any reference to REGNO, returning the rtx of the
3069 reference found if any. Otherwise, returns NULL_RTX. */
3072 regno_use_in (unsigned int regno
, rtx x
)
3078 if (REG_P (x
) && REGNO (x
) == regno
)
3081 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3082 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3086 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3089 else if (fmt
[i
] == 'E')
3090 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3091 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3098 /* Return a value indicating whether OP, an operand of a commutative
3099 operation, is preferred as the first or second operand. The higher
3100 the value, the stronger the preference for being the first operand.
3101 We use negative values to indicate a preference for the first operand
3102 and positive values for the second operand. */
3105 commutative_operand_precedence (rtx op
)
3107 enum rtx_code code
= GET_CODE (op
);
3109 /* Constants always come the second operand. Prefer "nice" constants. */
3110 if (code
== CONST_INT
)
3112 if (code
== CONST_DOUBLE
)
3114 if (code
== CONST_FIXED
)
3116 op
= avoid_constant_pool_reference (op
);
3117 code
= GET_CODE (op
);
3119 switch (GET_RTX_CLASS (code
))
3122 if (code
== CONST_INT
)
3124 if (code
== CONST_DOUBLE
)
3126 if (code
== CONST_FIXED
)
3131 /* SUBREGs of objects should come second. */
3132 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3137 /* Complex expressions should be the first, so decrease priority
3138 of objects. Prefer pointer objects over non pointer objects. */
3139 if ((REG_P (op
) && REG_POINTER (op
))
3140 || (MEM_P (op
) && MEM_POINTER (op
)))
3144 case RTX_COMM_ARITH
:
3145 /* Prefer operands that are themselves commutative to be first.
3146 This helps to make things linear. In particular,
3147 (and (and (reg) (reg)) (not (reg))) is canonical. */
3151 /* If only one operand is a binary expression, it will be the first
3152 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3153 is canonical, although it will usually be further simplified. */
3157 /* Then prefer NEG and NOT. */
3158 if (code
== NEG
|| code
== NOT
)
3166 /* Return 1 iff it is necessary to swap operands of commutative operation
3167 in order to canonicalize expression. */
3170 swap_commutative_operands_p (rtx x
, rtx y
)
3172 return (commutative_operand_precedence (x
)
3173 < commutative_operand_precedence (y
));
3176 /* Return 1 if X is an autoincrement side effect and the register is
3177 not the stack pointer. */
3179 auto_inc_p (const_rtx x
)
3181 switch (GET_CODE (x
))
3189 /* There are no REG_INC notes for SP. */
3190 if (XEXP (x
, 0) != stack_pointer_rtx
)
3198 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3200 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3209 code
= GET_CODE (in
);
3210 fmt
= GET_RTX_FORMAT (code
);
3211 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3215 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3218 else if (fmt
[i
] == 'E')
3219 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3220 if (loc
== &XVECEXP (in
, i
, j
)
3221 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3227 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3228 and SUBREG_BYTE, return the bit offset where the subreg begins
3229 (counting from the least significant bit of the operand). */
3232 subreg_lsb_1 (enum machine_mode outer_mode
,
3233 enum machine_mode inner_mode
,
3234 unsigned int subreg_byte
)
3236 unsigned int bitpos
;
3240 /* A paradoxical subreg begins at bit position 0. */
3241 if (GET_MODE_PRECISION (outer_mode
) > GET_MODE_PRECISION (inner_mode
))
3244 if (WORDS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
3245 /* If the subreg crosses a word boundary ensure that
3246 it also begins and ends on a word boundary. */
3247 gcc_assert (!((subreg_byte
% UNITS_PER_WORD
3248 + GET_MODE_SIZE (outer_mode
)) > UNITS_PER_WORD
3249 && (subreg_byte
% UNITS_PER_WORD
3250 || GET_MODE_SIZE (outer_mode
) % UNITS_PER_WORD
)));
3252 if (WORDS_BIG_ENDIAN
)
3253 word
= (GET_MODE_SIZE (inner_mode
)
3254 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) / UNITS_PER_WORD
;
3256 word
= subreg_byte
/ UNITS_PER_WORD
;
3257 bitpos
= word
* BITS_PER_WORD
;
3259 if (BYTES_BIG_ENDIAN
)
3260 byte
= (GET_MODE_SIZE (inner_mode
)
3261 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) % UNITS_PER_WORD
;
3263 byte
= subreg_byte
% UNITS_PER_WORD
;
3264 bitpos
+= byte
* BITS_PER_UNIT
;
3269 /* Given a subreg X, return the bit offset where the subreg begins
3270 (counting from the least significant bit of the reg). */
3273 subreg_lsb (const_rtx x
)
3275 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3279 /* Fill in information about a subreg of a hard register.
3280 xregno - A regno of an inner hard subreg_reg (or what will become one).
3281 xmode - The mode of xregno.
3282 offset - The byte offset.
3283 ymode - The mode of a top level SUBREG (or what may become one).
3284 info - Pointer to structure to fill in. */
3286 subreg_get_info (unsigned int xregno
, enum machine_mode xmode
,
3287 unsigned int offset
, enum machine_mode ymode
,
3288 struct subreg_info
*info
)
3290 int nregs_xmode
, nregs_ymode
;
3291 int mode_multiple
, nregs_multiple
;
3292 int offset_adj
, y_offset
, y_offset_adj
;
3293 int regsize_xmode
, regsize_ymode
;
3296 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3300 /* If there are holes in a non-scalar mode in registers, we expect
3301 that it is made up of its units concatenated together. */
3302 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3304 enum machine_mode xmode_unit
;
3306 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3307 if (GET_MODE_INNER (xmode
) == VOIDmode
)
3310 xmode_unit
= GET_MODE_INNER (xmode
);
3311 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3312 gcc_assert (nregs_xmode
3313 == (GET_MODE_NUNITS (xmode
)
3314 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3315 gcc_assert (hard_regno_nregs
[xregno
][xmode
]
3316 == (hard_regno_nregs
[xregno
][xmode_unit
]
3317 * GET_MODE_NUNITS (xmode
)));
3319 /* You can only ask for a SUBREG of a value with holes in the middle
3320 if you don't cross the holes. (Such a SUBREG should be done by
3321 picking a different register class, or doing it in memory if
3322 necessary.) An example of a value with holes is XCmode on 32-bit
3323 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3324 3 for each part, but in memory it's two 128-bit parts.
3325 Padding is assumed to be at the end (not necessarily the 'high part')
3327 if ((offset
/ GET_MODE_SIZE (xmode_unit
) + 1
3328 < GET_MODE_NUNITS (xmode
))
3329 && (offset
/ GET_MODE_SIZE (xmode_unit
)
3330 != ((offset
+ GET_MODE_SIZE (ymode
) - 1)
3331 / GET_MODE_SIZE (xmode_unit
))))
3333 info
->representable_p
= false;
3338 nregs_xmode
= hard_regno_nregs
[xregno
][xmode
];
3340 nregs_ymode
= hard_regno_nregs
[xregno
][ymode
];
3342 /* Paradoxical subregs are otherwise valid. */
3345 && GET_MODE_PRECISION (ymode
) > GET_MODE_PRECISION (xmode
))
3347 info
->representable_p
= true;
3348 /* If this is a big endian paradoxical subreg, which uses more
3349 actual hard registers than the original register, we must
3350 return a negative offset so that we find the proper highpart
3352 if (GET_MODE_SIZE (ymode
) > UNITS_PER_WORD
3353 ? REG_WORDS_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
3354 info
->offset
= nregs_xmode
- nregs_ymode
;
3357 info
->nregs
= nregs_ymode
;
3361 /* If registers store different numbers of bits in the different
3362 modes, we cannot generally form this subreg. */
3363 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3364 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3365 && (GET_MODE_SIZE (xmode
) % nregs_xmode
) == 0
3366 && (GET_MODE_SIZE (ymode
) % nregs_ymode
) == 0)
3368 regsize_xmode
= GET_MODE_SIZE (xmode
) / nregs_xmode
;
3369 regsize_ymode
= GET_MODE_SIZE (ymode
) / nregs_ymode
;
3370 if (!rknown
&& regsize_xmode
> regsize_ymode
&& nregs_ymode
> 1)
3372 info
->representable_p
= false;
3374 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3375 info
->offset
= offset
/ regsize_xmode
;
3378 if (!rknown
&& regsize_ymode
> regsize_xmode
&& nregs_xmode
> 1)
3380 info
->representable_p
= false;
3382 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3383 info
->offset
= offset
/ regsize_xmode
;
3388 /* Lowpart subregs are otherwise valid. */
3389 if (!rknown
&& offset
== subreg_lowpart_offset (ymode
, xmode
))
3391 info
->representable_p
= true;
3394 if (offset
== 0 || nregs_xmode
== nregs_ymode
)
3397 info
->nregs
= nregs_ymode
;
3402 /* This should always pass, otherwise we don't know how to verify
3403 the constraint. These conditions may be relaxed but
3404 subreg_regno_offset would need to be redesigned. */
3405 gcc_assert ((GET_MODE_SIZE (xmode
) % GET_MODE_SIZE (ymode
)) == 0);
3406 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3408 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
3409 && GET_MODE_SIZE (xmode
) > UNITS_PER_WORD
)
3411 HOST_WIDE_INT xsize
= GET_MODE_SIZE (xmode
);
3412 HOST_WIDE_INT ysize
= GET_MODE_SIZE (ymode
);
3413 HOST_WIDE_INT off_low
= offset
& (ysize
- 1);
3414 HOST_WIDE_INT off_high
= offset
& ~(ysize
- 1);
3415 offset
= (xsize
- ysize
- off_high
) | off_low
;
3417 /* The XMODE value can be seen as a vector of NREGS_XMODE
3418 values. The subreg must represent a lowpart of given field.
3419 Compute what field it is. */
3420 offset_adj
= offset
;
3421 offset_adj
-= subreg_lowpart_offset (ymode
,
3422 mode_for_size (GET_MODE_BITSIZE (xmode
)
3426 /* Size of ymode must not be greater than the size of xmode. */
3427 mode_multiple
= GET_MODE_SIZE (xmode
) / GET_MODE_SIZE (ymode
);
3428 gcc_assert (mode_multiple
!= 0);
3430 y_offset
= offset
/ GET_MODE_SIZE (ymode
);
3431 y_offset_adj
= offset_adj
/ GET_MODE_SIZE (ymode
);
3432 nregs_multiple
= nregs_xmode
/ nregs_ymode
;
3434 gcc_assert ((offset_adj
% GET_MODE_SIZE (ymode
)) == 0);
3435 gcc_assert ((mode_multiple
% nregs_multiple
) == 0);
3439 info
->representable_p
= (!(y_offset_adj
% (mode_multiple
/ nregs_multiple
)));
3442 info
->offset
= (y_offset
/ (mode_multiple
/ nregs_multiple
)) * nregs_ymode
;
3443 info
->nregs
= nregs_ymode
;
3446 /* This function returns the regno offset of a subreg expression.
3447 xregno - A regno of an inner hard subreg_reg (or what will become one).
3448 xmode - The mode of xregno.
3449 offset - The byte offset.
3450 ymode - The mode of a top level SUBREG (or what may become one).
3451 RETURN - The regno offset which would be used. */
3453 subreg_regno_offset (unsigned int xregno
, enum machine_mode xmode
,
3454 unsigned int offset
, enum machine_mode ymode
)
3456 struct subreg_info info
;
3457 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3461 /* This function returns true when the offset is representable via
3462 subreg_offset in the given regno.
3463 xregno - A regno of an inner hard subreg_reg (or what will become one).
3464 xmode - The mode of xregno.
3465 offset - The byte offset.
3466 ymode - The mode of a top level SUBREG (or what may become one).
3467 RETURN - Whether the offset is representable. */
3469 subreg_offset_representable_p (unsigned int xregno
, enum machine_mode xmode
,
3470 unsigned int offset
, enum machine_mode ymode
)
3472 struct subreg_info info
;
3473 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3474 return info
.representable_p
;
3477 /* Return the number of a YMODE register to which
3479 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3481 can be simplified. Return -1 if the subreg can't be simplified.
3483 XREGNO is a hard register number. */
3486 simplify_subreg_regno (unsigned int xregno
, enum machine_mode xmode
,
3487 unsigned int offset
, enum machine_mode ymode
)
3489 struct subreg_info info
;
3490 unsigned int yregno
;
3492 #ifdef CANNOT_CHANGE_MODE_CLASS
3493 /* Give the backend a chance to disallow the mode change. */
3494 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3495 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3496 && REG_CANNOT_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3497 /* We can use mode change in LRA for some transformations. */
3498 && ! lra_in_progress
)
3502 /* We shouldn't simplify stack-related registers. */
3503 if ((!reload_completed
|| frame_pointer_needed
)
3504 && xregno
== FRAME_POINTER_REGNUM
)
3507 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3508 && xregno
== ARG_POINTER_REGNUM
)
3511 if (xregno
== STACK_POINTER_REGNUM
3512 /* We should convert hard stack register in LRA if it is
3514 && ! lra_in_progress
)
3517 /* Try to get the register offset. */
3518 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3519 if (!info
.representable_p
)
3522 /* Make sure that the offsetted register value is in range. */
3523 yregno
= xregno
+ info
.offset
;
3524 if (!HARD_REGISTER_NUM_P (yregno
))
3527 /* See whether (reg:YMODE YREGNO) is valid.
3529 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3530 This is a kludge to work around how complex FP arguments are passed
3531 on IA-64 and should be fixed. See PR target/49226. */
3532 if (!HARD_REGNO_MODE_OK (yregno
, ymode
)
3533 && HARD_REGNO_MODE_OK (xregno
, xmode
))
3536 return (int) yregno
;
3539 /* Return the final regno that a subreg expression refers to. */
3541 subreg_regno (const_rtx x
)
3544 rtx subreg
= SUBREG_REG (x
);
3545 int regno
= REGNO (subreg
);
3547 ret
= regno
+ subreg_regno_offset (regno
,
3555 /* Return the number of registers that a subreg expression refers
3558 subreg_nregs (const_rtx x
)
3560 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
3563 /* Return the number of registers that a subreg REG with REGNO
3564 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3565 changed so that the regno can be passed in. */
3568 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
3570 struct subreg_info info
;
3571 rtx subreg
= SUBREG_REG (x
);
3573 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
3579 struct parms_set_data
3585 /* Helper function for noticing stores to parameter registers. */
3587 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
3589 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
3590 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
3591 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
3593 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
3598 /* Look backward for first parameter to be loaded.
3599 Note that loads of all parameters will not necessarily be
3600 found if CSE has eliminated some of them (e.g., an argument
3601 to the outer function is passed down as a parameter).
3602 Do not skip BOUNDARY. */
3604 find_first_parameter_load (rtx call_insn
, rtx boundary
)
3606 struct parms_set_data parm
;
3607 rtx p
, before
, first_set
;
3609 /* Since different machines initialize their parameter registers
3610 in different orders, assume nothing. Collect the set of all
3611 parameter registers. */
3612 CLEAR_HARD_REG_SET (parm
.regs
);
3614 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
3615 if (GET_CODE (XEXP (p
, 0)) == USE
3616 && REG_P (XEXP (XEXP (p
, 0), 0)))
3618 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
3620 /* We only care about registers which can hold function
3622 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
3625 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
3629 first_set
= call_insn
;
3631 /* Search backward for the first set of a register in this set. */
3632 while (parm
.nregs
&& before
!= boundary
)
3634 before
= PREV_INSN (before
);
3636 /* It is possible that some loads got CSEed from one call to
3637 another. Stop in that case. */
3638 if (CALL_P (before
))
3641 /* Our caller needs either ensure that we will find all sets
3642 (in case code has not been optimized yet), or take care
3643 for possible labels in a way by setting boundary to preceding
3645 if (LABEL_P (before
))
3647 gcc_assert (before
== boundary
);
3651 if (INSN_P (before
))
3653 int nregs_old
= parm
.nregs
;
3654 note_stores (PATTERN (before
), parms_set
, &parm
);
3655 /* If we found something that did not set a parameter reg,
3656 we're done. Do not keep going, as that might result
3657 in hoisting an insn before the setting of a pseudo
3658 that is used by the hoisted insn. */
3659 if (nregs_old
!= parm
.nregs
)
3668 /* Return true if we should avoid inserting code between INSN and preceding
3669 call instruction. */
3672 keep_with_call_p (const_rtx insn
)
3676 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
3678 if (REG_P (SET_DEST (set
))
3679 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
3680 && fixed_regs
[REGNO (SET_DEST (set
))]
3681 && general_operand (SET_SRC (set
), VOIDmode
))
3683 if (REG_P (SET_SRC (set
))
3684 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
3685 && REG_P (SET_DEST (set
))
3686 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3688 /* There may be a stack pop just after the call and before the store
3689 of the return register. Search for the actual store when deciding
3690 if we can break or not. */
3691 if (SET_DEST (set
) == stack_pointer_rtx
)
3693 /* This CONST_CAST is okay because next_nonnote_insn just
3694 returns its argument and we assign it to a const_rtx
3696 const_rtx i2
= next_nonnote_insn (CONST_CAST_RTX(insn
));
3697 if (i2
&& keep_with_call_p (i2
))
3704 /* Return true if LABEL is a target of JUMP_INSN. This applies only
3705 to non-complex jumps. That is, direct unconditional, conditional,
3706 and tablejumps, but not computed jumps or returns. It also does
3707 not apply to the fallthru case of a conditional jump. */
3710 label_is_jump_target_p (const_rtx label
, const_rtx jump_insn
)
3712 rtx tmp
= JUMP_LABEL (jump_insn
);
3717 if (tablejump_p (jump_insn
, NULL
, &tmp
))
3719 rtvec vec
= XVEC (PATTERN (tmp
),
3720 GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
);
3721 int i
, veclen
= GET_NUM_ELEM (vec
);
3723 for (i
= 0; i
< veclen
; ++i
)
3724 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
3728 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
3735 /* Return an estimate of the cost of computing rtx X.
3736 One use is in cse, to decide which expression to keep in the hash table.
3737 Another is in rtl generation, to pick the cheapest way to multiply.
3738 Other uses like the latter are expected in the future.
3740 X appears as operand OPNO in an expression with code OUTER_CODE.
3741 SPEED specifies whether costs optimized for speed or size should
3745 rtx_cost (rtx x
, enum rtx_code outer_code
, int opno
, bool speed
)
3756 /* A size N times larger than UNITS_PER_WORD likely needs N times as
3757 many insns, taking N times as long. */
3758 factor
= GET_MODE_SIZE (GET_MODE (x
)) / UNITS_PER_WORD
;
3762 /* Compute the default costs of certain things.
3763 Note that targetm.rtx_costs can override the defaults. */
3765 code
= GET_CODE (x
);
3769 /* Multiplication has time-complexity O(N*N), where N is the
3770 number of units (translated from digits) when using
3771 schoolbook long multiplication. */
3772 total
= factor
* factor
* COSTS_N_INSNS (5);
3778 /* Similarly, complexity for schoolbook long division. */
3779 total
= factor
* factor
* COSTS_N_INSNS (7);
3782 /* Used in combine.c as a marker. */
3786 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
3787 the mode for the factor. */
3788 factor
= GET_MODE_SIZE (GET_MODE (SET_DEST (x
))) / UNITS_PER_WORD
;
3793 total
= factor
* COSTS_N_INSNS (1);
3803 /* If we can't tie these modes, make this expensive. The larger
3804 the mode, the more expensive it is. */
3805 if (! MODES_TIEABLE_P (GET_MODE (x
), GET_MODE (SUBREG_REG (x
))))
3806 return COSTS_N_INSNS (2 + factor
);
3810 if (targetm
.rtx_costs (x
, code
, outer_code
, opno
, &total
, speed
))
3815 /* Sum the costs of the sub-rtx's, plus cost of this operation,
3816 which is already in total. */
3818 fmt
= GET_RTX_FORMAT (code
);
3819 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3821 total
+= rtx_cost (XEXP (x
, i
), code
, i
, speed
);
3822 else if (fmt
[i
] == 'E')
3823 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3824 total
+= rtx_cost (XVECEXP (x
, i
, j
), code
, i
, speed
);
3829 /* Fill in the structure C with information about both speed and size rtx
3830 costs for X, which is operand OPNO in an expression with code OUTER. */
3833 get_full_rtx_cost (rtx x
, enum rtx_code outer
, int opno
,
3834 struct full_rtx_costs
*c
)
3836 c
->speed
= rtx_cost (x
, outer
, opno
, true);
3837 c
->size
= rtx_cost (x
, outer
, opno
, false);
3841 /* Return cost of address expression X.
3842 Expect that X is properly formed address reference.
3844 SPEED parameter specify whether costs optimized for speed or size should
3848 address_cost (rtx x
, enum machine_mode mode
, addr_space_t as
, bool speed
)
3850 /* We may be asked for cost of various unusual addresses, such as operands
3851 of push instruction. It is not worthwhile to complicate writing
3852 of the target hook by such cases. */
3854 if (!memory_address_addr_space_p (mode
, x
, as
))
3857 return targetm
.address_cost (x
, mode
, as
, speed
);
3860 /* If the target doesn't override, compute the cost as with arithmetic. */
3863 default_address_cost (rtx x
, enum machine_mode
, addr_space_t
, bool speed
)
3865 return rtx_cost (x
, MEM
, 0, speed
);
3869 unsigned HOST_WIDE_INT
3870 nonzero_bits (const_rtx x
, enum machine_mode mode
)
3872 return cached_nonzero_bits (x
, mode
, NULL_RTX
, VOIDmode
, 0);
3876 num_sign_bit_copies (const_rtx x
, enum machine_mode mode
)
3878 return cached_num_sign_bit_copies (x
, mode
, NULL_RTX
, VOIDmode
, 0);
3881 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
3882 It avoids exponential behavior in nonzero_bits1 when X has
3883 identical subexpressions on the first or the second level. */
3885 static unsigned HOST_WIDE_INT
3886 cached_nonzero_bits (const_rtx x
, enum machine_mode mode
, const_rtx known_x
,
3887 enum machine_mode known_mode
,
3888 unsigned HOST_WIDE_INT known_ret
)
3890 if (x
== known_x
&& mode
== known_mode
)
3893 /* Try to find identical subexpressions. If found call
3894 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
3895 precomputed value for the subexpression as KNOWN_RET. */
3897 if (ARITHMETIC_P (x
))
3899 rtx x0
= XEXP (x
, 0);
3900 rtx x1
= XEXP (x
, 1);
3902 /* Check the first level. */
3904 return nonzero_bits1 (x
, mode
, x0
, mode
,
3905 cached_nonzero_bits (x0
, mode
, known_x
,
3906 known_mode
, known_ret
));
3908 /* Check the second level. */
3909 if (ARITHMETIC_P (x0
)
3910 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
3911 return nonzero_bits1 (x
, mode
, x1
, mode
,
3912 cached_nonzero_bits (x1
, mode
, known_x
,
3913 known_mode
, known_ret
));
3915 if (ARITHMETIC_P (x1
)
3916 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
3917 return nonzero_bits1 (x
, mode
, x0
, mode
,
3918 cached_nonzero_bits (x0
, mode
, known_x
,
3919 known_mode
, known_ret
));
3922 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
3925 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
3926 We don't let nonzero_bits recur into num_sign_bit_copies, because that
3927 is less useful. We can't allow both, because that results in exponential
3928 run time recursion. There is a nullstone testcase that triggered
3929 this. This macro avoids accidental uses of num_sign_bit_copies. */
3930 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
3932 /* Given an expression, X, compute which bits in X can be nonzero.
3933 We don't care about bits outside of those defined in MODE.
3935 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
3936 an arithmetic operation, we can do better. */
3938 static unsigned HOST_WIDE_INT
3939 nonzero_bits1 (const_rtx x
, enum machine_mode mode
, const_rtx known_x
,
3940 enum machine_mode known_mode
,
3941 unsigned HOST_WIDE_INT known_ret
)
3943 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
3944 unsigned HOST_WIDE_INT inner_nz
;
3946 enum machine_mode inner_mode
;
3947 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
3949 /* For floating-point and vector values, assume all bits are needed. */
3950 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
)
3951 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
3954 /* If X is wider than MODE, use its mode instead. */
3955 if (GET_MODE_PRECISION (GET_MODE (x
)) > mode_width
)
3957 mode
= GET_MODE (x
);
3958 nonzero
= GET_MODE_MASK (mode
);
3959 mode_width
= GET_MODE_PRECISION (mode
);
3962 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
3963 /* Our only callers in this case look for single bit values. So
3964 just return the mode mask. Those tests will then be false. */
3967 #ifndef WORD_REGISTER_OPERATIONS
3968 /* If MODE is wider than X, but both are a single word for both the host
3969 and target machines, we can compute this from which bits of the
3970 object might be nonzero in its own mode, taking into account the fact
3971 that on many CISC machines, accessing an object in a wider mode
3972 causes the high-order bits to become undefined. So they are
3973 not known to be zero. */
3975 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
3976 && GET_MODE_PRECISION (GET_MODE (x
)) <= BITS_PER_WORD
3977 && GET_MODE_PRECISION (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
3978 && GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (GET_MODE (x
)))
3980 nonzero
&= cached_nonzero_bits (x
, GET_MODE (x
),
3981 known_x
, known_mode
, known_ret
);
3982 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
3987 code
= GET_CODE (x
);
3991 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
3992 /* If pointers extend unsigned and this is a pointer in Pmode, say that
3993 all the bits above ptr_mode are known to be zero. */
3994 /* As we do not know which address space the pointer is referring to,
3995 we can do this only if the target does not support different pointer
3996 or address modes depending on the address space. */
3997 if (target_default_pointer_address_modes_p ()
3998 && POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4000 nonzero
&= GET_MODE_MASK (ptr_mode
);
4003 /* Include declared information about alignment of pointers. */
4004 /* ??? We don't properly preserve REG_POINTER changes across
4005 pointer-to-integer casts, so we can't trust it except for
4006 things that we know must be pointers. See execute/960116-1.c. */
4007 if ((x
== stack_pointer_rtx
4008 || x
== frame_pointer_rtx
4009 || x
== arg_pointer_rtx
)
4010 && REGNO_POINTER_ALIGN (REGNO (x
)))
4012 unsigned HOST_WIDE_INT alignment
4013 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4015 #ifdef PUSH_ROUNDING
4016 /* If PUSH_ROUNDING is defined, it is possible for the
4017 stack to be momentarily aligned only to that amount,
4018 so we pick the least alignment. */
4019 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4020 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
4024 nonzero
&= ~(alignment
- 1);
4028 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4029 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, mode
, known_x
,
4030 known_mode
, known_ret
,
4034 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4035 known_mode
, known_ret
);
4037 return nonzero_for_hook
;
4041 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
4042 /* If X is negative in MODE, sign-extend the value. */
4044 && mode_width
< BITS_PER_WORD
4045 && (UINTVAL (x
) & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
4047 return UINTVAL (x
) | ((unsigned HOST_WIDE_INT
) (-1) << mode_width
);
4053 #ifdef LOAD_EXTEND_OP
4054 /* In many, if not most, RISC machines, reading a byte from memory
4055 zeros the rest of the register. Noticing that fact saves a lot
4056 of extra zero-extends. */
4057 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
4058 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
4063 case UNEQ
: case LTGT
:
4064 case GT
: case GTU
: case UNGT
:
4065 case LT
: case LTU
: case UNLT
:
4066 case GE
: case GEU
: case UNGE
:
4067 case LE
: case LEU
: case UNLE
:
4068 case UNORDERED
: case ORDERED
:
4069 /* If this produces an integer result, we know which bits are set.
4070 Code here used to clear bits outside the mode of X, but that is
4072 /* Mind that MODE is the mode the caller wants to look at this
4073 operation in, and not the actual operation mode. We can wind
4074 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4075 that describes the results of a vector compare. */
4076 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
4077 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4078 nonzero
= STORE_FLAG_VALUE
;
4083 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4084 and num_sign_bit_copies. */
4085 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4086 == GET_MODE_PRECISION (GET_MODE (x
)))
4090 if (GET_MODE_PRECISION (GET_MODE (x
)) < mode_width
)
4091 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
4096 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4097 and num_sign_bit_copies. */
4098 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4099 == GET_MODE_PRECISION (GET_MODE (x
)))
4105 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4106 known_x
, known_mode
, known_ret
)
4107 & GET_MODE_MASK (mode
));
4111 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4112 known_x
, known_mode
, known_ret
);
4113 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4114 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4118 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4119 Otherwise, show all the bits in the outer mode but not the inner
4121 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4122 known_x
, known_mode
, known_ret
);
4123 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4125 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4126 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4127 inner_nz
|= (GET_MODE_MASK (mode
)
4128 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4131 nonzero
&= inner_nz
;
4135 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4136 known_x
, known_mode
, known_ret
)
4137 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4138 known_x
, known_mode
, known_ret
);
4142 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4144 unsigned HOST_WIDE_INT nonzero0
4145 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4146 known_x
, known_mode
, known_ret
);
4148 /* Don't call nonzero_bits for the second time if it cannot change
4150 if ((nonzero
& nonzero0
) != nonzero
)
4152 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4153 known_x
, known_mode
, known_ret
);
4157 case PLUS
: case MINUS
:
4159 case DIV
: case UDIV
:
4160 case MOD
: case UMOD
:
4161 /* We can apply the rules of arithmetic to compute the number of
4162 high- and low-order zero bits of these operations. We start by
4163 computing the width (position of the highest-order nonzero bit)
4164 and the number of low-order zero bits for each value. */
4166 unsigned HOST_WIDE_INT nz0
4167 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4168 known_x
, known_mode
, known_ret
);
4169 unsigned HOST_WIDE_INT nz1
4170 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4171 known_x
, known_mode
, known_ret
);
4172 int sign_index
= GET_MODE_PRECISION (GET_MODE (x
)) - 1;
4173 int width0
= floor_log2 (nz0
) + 1;
4174 int width1
= floor_log2 (nz1
) + 1;
4175 int low0
= floor_log2 (nz0
& -nz0
);
4176 int low1
= floor_log2 (nz1
& -nz1
);
4177 unsigned HOST_WIDE_INT op0_maybe_minusp
4178 = nz0
& ((unsigned HOST_WIDE_INT
) 1 << sign_index
);
4179 unsigned HOST_WIDE_INT op1_maybe_minusp
4180 = nz1
& ((unsigned HOST_WIDE_INT
) 1 << sign_index
);
4181 unsigned int result_width
= mode_width
;
4187 result_width
= MAX (width0
, width1
) + 1;
4188 result_low
= MIN (low0
, low1
);
4191 result_low
= MIN (low0
, low1
);
4194 result_width
= width0
+ width1
;
4195 result_low
= low0
+ low1
;
4200 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4201 result_width
= width0
;
4206 result_width
= width0
;
4211 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4212 result_width
= MIN (width0
, width1
);
4213 result_low
= MIN (low0
, low1
);
4218 result_width
= MIN (width0
, width1
);
4219 result_low
= MIN (low0
, low1
);
4225 if (result_width
< mode_width
)
4226 nonzero
&= ((unsigned HOST_WIDE_INT
) 1 << result_width
) - 1;
4229 nonzero
&= ~(((unsigned HOST_WIDE_INT
) 1 << result_low
) - 1);
4234 if (CONST_INT_P (XEXP (x
, 1))
4235 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4236 nonzero
&= ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
4240 /* If this is a SUBREG formed for a promoted variable that has
4241 been zero-extended, we know that at least the high-order bits
4242 are zero, though others might be too. */
4244 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
4245 nonzero
= GET_MODE_MASK (GET_MODE (x
))
4246 & cached_nonzero_bits (SUBREG_REG (x
), GET_MODE (x
),
4247 known_x
, known_mode
, known_ret
);
4249 inner_mode
= GET_MODE (SUBREG_REG (x
));
4250 /* If the inner mode is a single word for both the host and target
4251 machines, we can compute this from which bits of the inner
4252 object might be nonzero. */
4253 if (GET_MODE_PRECISION (inner_mode
) <= BITS_PER_WORD
4254 && (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
))
4256 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4257 known_x
, known_mode
, known_ret
);
4259 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
4260 /* If this is a typical RISC machine, we only have to worry
4261 about the way loads are extended. */
4262 if ((LOAD_EXTEND_OP (inner_mode
) == SIGN_EXTEND
4263 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4264 : LOAD_EXTEND_OP (inner_mode
) != ZERO_EXTEND
)
4265 || !MEM_P (SUBREG_REG (x
)))
4268 /* On many CISC machines, accessing an object in a wider mode
4269 causes the high-order bits to become undefined. So they are
4270 not known to be zero. */
4271 if (GET_MODE_PRECISION (GET_MODE (x
))
4272 > GET_MODE_PRECISION (inner_mode
))
4273 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
4274 & ~GET_MODE_MASK (inner_mode
));
4283 /* The nonzero bits are in two classes: any bits within MODE
4284 that aren't in GET_MODE (x) are always significant. The rest of the
4285 nonzero bits are those that are significant in the operand of
4286 the shift when shifted the appropriate number of bits. This
4287 shows that high-order bits are cleared by the right shift and
4288 low-order bits by left shifts. */
4289 if (CONST_INT_P (XEXP (x
, 1))
4290 && INTVAL (XEXP (x
, 1)) >= 0
4291 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4292 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4294 enum machine_mode inner_mode
= GET_MODE (x
);
4295 unsigned int width
= GET_MODE_PRECISION (inner_mode
);
4296 int count
= INTVAL (XEXP (x
, 1));
4297 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
4298 unsigned HOST_WIDE_INT op_nonzero
4299 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4300 known_x
, known_mode
, known_ret
);
4301 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4302 unsigned HOST_WIDE_INT outer
= 0;
4304 if (mode_width
> width
)
4305 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4307 if (code
== LSHIFTRT
)
4309 else if (code
== ASHIFTRT
)
4313 /* If the sign bit may have been nonzero before the shift, we
4314 need to mark all the places it could have been copied to
4315 by the shift as possibly nonzero. */
4316 if (inner
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
4317 inner
|= (((unsigned HOST_WIDE_INT
) 1 << count
) - 1)
4320 else if (code
== ASHIFT
)
4323 inner
= ((inner
<< (count
% width
)
4324 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
4326 nonzero
&= (outer
| inner
);
4332 /* This is at most the number of bits in the mode. */
4333 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4337 /* If CLZ has a known value at zero, then the nonzero bits are
4338 that value, plus the number of bits in the mode minus one. */
4339 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4341 |= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4347 /* If CTZ has a known value at zero, then the nonzero bits are
4348 that value, plus the number of bits in the mode minus one. */
4349 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4351 |= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4357 /* This is at most the number of bits in the mode minus 1. */
4358 nonzero
= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4367 unsigned HOST_WIDE_INT nonzero_true
4368 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4369 known_x
, known_mode
, known_ret
);
4371 /* Don't call nonzero_bits for the second time if it cannot change
4373 if ((nonzero
& nonzero_true
) != nonzero
)
4374 nonzero
&= nonzero_true
4375 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4376 known_x
, known_mode
, known_ret
);
4387 /* See the macro definition above. */
4388 #undef cached_num_sign_bit_copies
4391 /* The function cached_num_sign_bit_copies is a wrapper around
4392 num_sign_bit_copies1. It avoids exponential behavior in
4393 num_sign_bit_copies1 when X has identical subexpressions on the
4394 first or the second level. */
4397 cached_num_sign_bit_copies (const_rtx x
, enum machine_mode mode
, const_rtx known_x
,
4398 enum machine_mode known_mode
,
4399 unsigned int known_ret
)
4401 if (x
== known_x
&& mode
== known_mode
)
4404 /* Try to find identical subexpressions. If found call
4405 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4406 the precomputed value for the subexpression as KNOWN_RET. */
4408 if (ARITHMETIC_P (x
))
4410 rtx x0
= XEXP (x
, 0);
4411 rtx x1
= XEXP (x
, 1);
4413 /* Check the first level. */
4416 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4417 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4421 /* Check the second level. */
4422 if (ARITHMETIC_P (x0
)
4423 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4425 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4426 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4430 if (ARITHMETIC_P (x1
)
4431 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4433 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4434 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4439 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4442 /* Return the number of bits at the high-order end of X that are known to
4443 be equal to the sign bit. X will be used in mode MODE; if MODE is
4444 VOIDmode, X will be used in its own mode. The returned value will always
4445 be between 1 and the number of bits in MODE. */
4448 num_sign_bit_copies1 (const_rtx x
, enum machine_mode mode
, const_rtx known_x
,
4449 enum machine_mode known_mode
,
4450 unsigned int known_ret
)
4452 enum rtx_code code
= GET_CODE (x
);
4453 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
4454 int num0
, num1
, result
;
4455 unsigned HOST_WIDE_INT nonzero
;
4457 /* If we weren't given a mode, use the mode of X. If the mode is still
4458 VOIDmode, we don't know anything. Likewise if one of the modes is
4461 if (mode
== VOIDmode
)
4462 mode
= GET_MODE (x
);
4464 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
))
4465 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4468 /* For a smaller object, just ignore the high bits. */
4469 if (bitwidth
< GET_MODE_PRECISION (GET_MODE (x
)))
4471 num0
= cached_num_sign_bit_copies (x
, GET_MODE (x
),
4472 known_x
, known_mode
, known_ret
);
4474 num0
- (int) (GET_MODE_PRECISION (GET_MODE (x
)) - bitwidth
));
4477 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_PRECISION (GET_MODE (x
)))
4479 #ifndef WORD_REGISTER_OPERATIONS
4480 /* If this machine does not do all register operations on the entire
4481 register and MODE is wider than the mode of X, we can say nothing
4482 at all about the high-order bits. */
4485 /* Likewise on machines that do, if the mode of the object is smaller
4486 than a word and loads of that size don't sign extend, we can say
4487 nothing about the high order bits. */
4488 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
4489 #ifdef LOAD_EXTEND_OP
4490 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
4501 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
4502 /* If pointers extend signed and this is a pointer in Pmode, say that
4503 all the bits above ptr_mode are known to be sign bit copies. */
4504 /* As we do not know which address space the pointer is referring to,
4505 we can do this only if the target does not support different pointer
4506 or address modes depending on the address space. */
4507 if (target_default_pointer_address_modes_p ()
4508 && ! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4509 && mode
== Pmode
&& REG_POINTER (x
))
4510 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
4514 unsigned int copies_for_hook
= 1, copies
= 1;
4515 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, mode
, known_x
,
4516 known_mode
, known_ret
,
4520 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
4521 known_mode
, known_ret
);
4523 if (copies
> 1 || copies_for_hook
> 1)
4524 return MAX (copies
, copies_for_hook
);
4526 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4531 #ifdef LOAD_EXTEND_OP
4532 /* Some RISC machines sign-extend all loads of smaller than a word. */
4533 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
4534 return MAX (1, ((int) bitwidth
4535 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1));
4540 /* If the constant is negative, take its 1's complement and remask.
4541 Then see how many zero bits we have. */
4542 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
4543 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4544 && (nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4545 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4547 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4550 /* If this is a SUBREG for a promoted object that is sign-extended
4551 and we are looking at it in a wider mode, we know that at least the
4552 high-order bits are known to be sign bit copies. */
4554 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
4556 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4557 known_x
, known_mode
, known_ret
);
4558 return MAX ((int) bitwidth
4559 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1,
4563 /* For a smaller object, just ignore the high bits. */
4564 if (bitwidth
<= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
))))
4566 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
,
4567 known_x
, known_mode
, known_ret
);
4568 return MAX (1, (num0
4569 - (int) (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
)))
4573 #ifdef WORD_REGISTER_OPERATIONS
4574 #ifdef LOAD_EXTEND_OP
4575 /* For paradoxical SUBREGs on machines where all register operations
4576 affect the entire register, just look inside. Note that we are
4577 passing MODE to the recursive call, so the number of sign bit copies
4578 will remain relative to that mode, not the inner mode. */
4580 /* This works only if loads sign extend. Otherwise, if we get a
4581 reload for the inner part, it may be loaded from the stack, and
4582 then we lose all sign bit copies that existed before the store
4585 if (paradoxical_subreg_p (x
)
4586 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
4587 && MEM_P (SUBREG_REG (x
)))
4588 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4589 known_x
, known_mode
, known_ret
);
4595 if (CONST_INT_P (XEXP (x
, 1)))
4596 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
4600 return (bitwidth
- GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4601 + cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4602 known_x
, known_mode
, known_ret
));
4605 /* For a smaller object, just ignore the high bits. */
4606 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4607 known_x
, known_mode
, known_ret
);
4608 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4612 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4613 known_x
, known_mode
, known_ret
);
4615 case ROTATE
: case ROTATERT
:
4616 /* If we are rotating left by a number of bits less than the number
4617 of sign bit copies, we can just subtract that amount from the
4619 if (CONST_INT_P (XEXP (x
, 1))
4620 && INTVAL (XEXP (x
, 1)) >= 0
4621 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
4623 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4624 known_x
, known_mode
, known_ret
);
4625 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
4626 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
4631 /* In general, this subtracts one sign bit copy. But if the value
4632 is known to be positive, the number of sign bit copies is the
4633 same as that of the input. Finally, if the input has just one bit
4634 that might be nonzero, all the bits are copies of the sign bit. */
4635 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4636 known_x
, known_mode
, known_ret
);
4637 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4638 return num0
> 1 ? num0
- 1 : 1;
4640 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
4645 && (((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
4650 case IOR
: case AND
: case XOR
:
4651 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
4652 /* Logical operations will preserve the number of sign-bit copies.
4653 MIN and MAX operations always return one of the operands. */
4654 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4655 known_x
, known_mode
, known_ret
);
4656 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4657 known_x
, known_mode
, known_ret
);
4659 /* If num1 is clearing some of the top bits then regardless of
4660 the other term, we are guaranteed to have at least that many
4661 high-order zero bits. */
4664 && bitwidth
<= HOST_BITS_PER_WIDE_INT
4665 && CONST_INT_P (XEXP (x
, 1))
4666 && (UINTVAL (XEXP (x
, 1))
4667 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) == 0)
4670 /* Similarly for IOR when setting high-order bits. */
4673 && bitwidth
<= HOST_BITS_PER_WIDE_INT
4674 && CONST_INT_P (XEXP (x
, 1))
4675 && (UINTVAL (XEXP (x
, 1))
4676 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4679 return MIN (num0
, num1
);
4681 case PLUS
: case MINUS
:
4682 /* For addition and subtraction, we can have a 1-bit carry. However,
4683 if we are subtracting 1 from a positive number, there will not
4684 be such a carry. Furthermore, if the positive number is known to
4685 be 0 or 1, we know the result is either -1 or 0. */
4687 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
4688 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
4690 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
4691 if ((((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
4692 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
4693 : bitwidth
- floor_log2 (nonzero
) - 1);
4696 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4697 known_x
, known_mode
, known_ret
);
4698 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4699 known_x
, known_mode
, known_ret
);
4700 result
= MAX (1, MIN (num0
, num1
) - 1);
4705 /* The number of bits of the product is the sum of the number of
4706 bits of both terms. However, unless one of the terms if known
4707 to be positive, we must allow for an additional bit since negating
4708 a negative number can remove one sign bit copy. */
4710 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4711 known_x
, known_mode
, known_ret
);
4712 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4713 known_x
, known_mode
, known_ret
);
4715 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
4717 && (bitwidth
> HOST_BITS_PER_WIDE_INT
4718 || (((nonzero_bits (XEXP (x
, 0), mode
)
4719 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4720 && ((nonzero_bits (XEXP (x
, 1), mode
)
4721 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)))
4725 return MAX (1, result
);
4728 /* The result must be <= the first operand. If the first operand
4729 has the high bit set, we know nothing about the number of sign
4731 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4733 else if ((nonzero_bits (XEXP (x
, 0), mode
)
4734 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4737 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4738 known_x
, known_mode
, known_ret
);
4741 /* The result must be <= the second operand. If the second operand
4742 has (or just might have) the high bit set, we know nothing about
4743 the number of sign bit copies. */
4744 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4746 else if ((nonzero_bits (XEXP (x
, 1), mode
)
4747 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4750 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4751 known_x
, known_mode
, known_ret
);
4754 /* Similar to unsigned division, except that we have to worry about
4755 the case where the divisor is negative, in which case we have
4757 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4758 known_x
, known_mode
, known_ret
);
4760 && (bitwidth
> HOST_BITS_PER_WIDE_INT
4761 || (nonzero_bits (XEXP (x
, 1), mode
)
4762 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
4768 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4769 known_x
, known_mode
, known_ret
);
4771 && (bitwidth
> HOST_BITS_PER_WIDE_INT
4772 || (nonzero_bits (XEXP (x
, 1), mode
)
4773 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
4779 /* Shifts by a constant add to the number of bits equal to the
4781 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4782 known_x
, known_mode
, known_ret
);
4783 if (CONST_INT_P (XEXP (x
, 1))
4784 && INTVAL (XEXP (x
, 1)) > 0
4785 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4786 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
4791 /* Left shifts destroy copies. */
4792 if (!CONST_INT_P (XEXP (x
, 1))
4793 || INTVAL (XEXP (x
, 1)) < 0
4794 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
4795 || INTVAL (XEXP (x
, 1)) >= GET_MODE_PRECISION (GET_MODE (x
)))
4798 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4799 known_x
, known_mode
, known_ret
);
4800 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
4803 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4804 known_x
, known_mode
, known_ret
);
4805 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
4806 known_x
, known_mode
, known_ret
);
4807 return MIN (num0
, num1
);
4809 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
4810 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
4811 case GEU
: case GTU
: case LEU
: case LTU
:
4812 case UNORDERED
: case ORDERED
:
4813 /* If the constant is negative, take its 1's complement and remask.
4814 Then see how many zero bits we have. */
4815 nonzero
= STORE_FLAG_VALUE
;
4816 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4817 && (nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4818 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4820 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4826 /* If we haven't been able to figure it out by one of the above rules,
4827 see if some of the high-order bits are known to be zero. If so,
4828 count those bits and return one less than that amount. If we can't
4829 safely compute the mask for this mode, always return BITWIDTH. */
4831 bitwidth
= GET_MODE_PRECISION (mode
);
4832 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4835 nonzero
= nonzero_bits (x
, mode
);
4836 return nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))
4837 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
4840 /* Calculate the rtx_cost of a single instruction. A return value of
4841 zero indicates an instruction pattern without a known cost. */
4844 insn_rtx_cost (rtx pat
, bool speed
)
4849 /* Extract the single set rtx from the instruction pattern.
4850 We can't use single_set since we only have the pattern. */
4851 if (GET_CODE (pat
) == SET
)
4853 else if (GET_CODE (pat
) == PARALLEL
)
4856 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
4858 rtx x
= XVECEXP (pat
, 0, i
);
4859 if (GET_CODE (x
) == SET
)
4872 cost
= set_src_cost (SET_SRC (set
), speed
);
4873 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
4876 /* Given an insn INSN and condition COND, return the condition in a
4877 canonical form to simplify testing by callers. Specifically:
4879 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
4880 (2) Both operands will be machine operands; (cc0) will have been replaced.
4881 (3) If an operand is a constant, it will be the second operand.
4882 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
4883 for GE, GEU, and LEU.
4885 If the condition cannot be understood, or is an inequality floating-point
4886 comparison which needs to be reversed, 0 will be returned.
4888 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
4890 If EARLIEST is nonzero, it is a pointer to a place where the earliest
4891 insn used in locating the condition was found. If a replacement test
4892 of the condition is desired, it should be placed in front of that
4893 insn and we will be sure that the inputs are still valid.
4895 If WANT_REG is nonzero, we wish the condition to be relative to that
4896 register, if possible. Therefore, do not canonicalize the condition
4897 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
4898 to be a compare to a CC mode register.
4900 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
4904 canonicalize_condition (rtx insn
, rtx cond
, int reverse
, rtx
*earliest
,
4905 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
4912 int reverse_code
= 0;
4913 enum machine_mode mode
;
4914 basic_block bb
= BLOCK_FOR_INSN (insn
);
4916 code
= GET_CODE (cond
);
4917 mode
= GET_MODE (cond
);
4918 op0
= XEXP (cond
, 0);
4919 op1
= XEXP (cond
, 1);
4922 code
= reversed_comparison_code (cond
, insn
);
4923 if (code
== UNKNOWN
)
4929 /* If we are comparing a register with zero, see if the register is set
4930 in the previous insn to a COMPARE or a comparison operation. Perform
4931 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
4934 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
4935 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
4936 && op1
== CONST0_RTX (GET_MODE (op0
))
4939 /* Set nonzero when we find something of interest. */
4943 /* If comparison with cc0, import actual comparison from compare
4947 if ((prev
= prev_nonnote_insn (prev
)) == 0
4948 || !NONJUMP_INSN_P (prev
)
4949 || (set
= single_set (prev
)) == 0
4950 || SET_DEST (set
) != cc0_rtx
)
4953 op0
= SET_SRC (set
);
4954 op1
= CONST0_RTX (GET_MODE (op0
));
4960 /* If this is a COMPARE, pick up the two things being compared. */
4961 if (GET_CODE (op0
) == COMPARE
)
4963 op1
= XEXP (op0
, 1);
4964 op0
= XEXP (op0
, 0);
4967 else if (!REG_P (op0
))
4970 /* Go back to the previous insn. Stop if it is not an INSN. We also
4971 stop if it isn't a single set or if it has a REG_INC note because
4972 we don't want to bother dealing with it. */
4974 prev
= prev_nonnote_nondebug_insn (prev
);
4977 || !NONJUMP_INSN_P (prev
)
4978 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
4979 /* In cfglayout mode, there do not have to be labels at the
4980 beginning of a block, or jumps at the end, so the previous
4981 conditions would not stop us when we reach bb boundary. */
4982 || BLOCK_FOR_INSN (prev
) != bb
)
4985 set
= set_of (op0
, prev
);
4988 && (GET_CODE (set
) != SET
4989 || !rtx_equal_p (SET_DEST (set
), op0
)))
4992 /* If this is setting OP0, get what it sets it to if it looks
4996 enum machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
4997 #ifdef FLOAT_STORE_FLAG_VALUE
4998 REAL_VALUE_TYPE fsfv
;
5001 /* ??? We may not combine comparisons done in a CCmode with
5002 comparisons not done in a CCmode. This is to aid targets
5003 like Alpha that have an IEEE compliant EQ instruction, and
5004 a non-IEEE compliant BEQ instruction. The use of CCmode is
5005 actually artificial, simply to prevent the combination, but
5006 should not affect other platforms.
5008 However, we must allow VOIDmode comparisons to match either
5009 CCmode or non-CCmode comparison, because some ports have
5010 modeless comparisons inside branch patterns.
5012 ??? This mode check should perhaps look more like the mode check
5013 in simplify_comparison in combine. */
5015 if ((GET_CODE (SET_SRC (set
)) == COMPARE
5018 && val_signbit_known_set_p (inner_mode
,
5020 #ifdef FLOAT_STORE_FLAG_VALUE
5022 && SCALAR_FLOAT_MODE_P (inner_mode
)
5023 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5024 REAL_VALUE_NEGATIVE (fsfv
)))
5027 && COMPARISON_P (SET_SRC (set
))))
5028 && (((GET_MODE_CLASS (mode
) == MODE_CC
)
5029 == (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5030 || mode
== VOIDmode
|| inner_mode
== VOIDmode
))
5032 else if (((code
== EQ
5034 && val_signbit_known_set_p (inner_mode
,
5036 #ifdef FLOAT_STORE_FLAG_VALUE
5038 && SCALAR_FLOAT_MODE_P (inner_mode
)
5039 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5040 REAL_VALUE_NEGATIVE (fsfv
)))
5043 && COMPARISON_P (SET_SRC (set
))
5044 && (((GET_MODE_CLASS (mode
) == MODE_CC
)
5045 == (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5046 || mode
== VOIDmode
|| inner_mode
== VOIDmode
))
5056 else if (reg_set_p (op0
, prev
))
5057 /* If this sets OP0, but not directly, we have to give up. */
5062 /* If the caller is expecting the condition to be valid at INSN,
5063 make sure X doesn't change before INSN. */
5064 if (valid_at_insn_p
)
5065 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5067 if (COMPARISON_P (x
))
5068 code
= GET_CODE (x
);
5071 code
= reversed_comparison_code (x
, prev
);
5072 if (code
== UNKNOWN
)
5077 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5083 /* If constant is first, put it last. */
5084 if (CONSTANT_P (op0
))
5085 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5087 /* If OP0 is the result of a comparison, we weren't able to find what
5088 was really being compared, so fail. */
5090 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5093 /* Canonicalize any ordered comparison with integers involving equality
5094 if we can do computations in the relevant mode and we do not
5097 if (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_CC
5098 && CONST_INT_P (op1
)
5099 && GET_MODE (op0
) != VOIDmode
5100 && GET_MODE_PRECISION (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
)
5102 HOST_WIDE_INT const_val
= INTVAL (op1
);
5103 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5104 unsigned HOST_WIDE_INT max_val
5105 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (GET_MODE (op0
));
5110 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5111 code
= LT
, op1
= gen_int_mode (const_val
+ 1, GET_MODE (op0
));
5114 /* When cross-compiling, const_val might be sign-extended from
5115 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5117 if ((const_val
& max_val
)
5118 != ((unsigned HOST_WIDE_INT
) 1
5119 << (GET_MODE_PRECISION (GET_MODE (op0
)) - 1)))
5120 code
= GT
, op1
= gen_int_mode (const_val
- 1, GET_MODE (op0
));
5124 if (uconst_val
< max_val
)
5125 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, GET_MODE (op0
));
5129 if (uconst_val
!= 0)
5130 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, GET_MODE (op0
));
5138 /* Never return CC0; return zero instead. */
5142 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5145 /* Given a jump insn JUMP, return the condition that will cause it to branch
5146 to its JUMP_LABEL. If the condition cannot be understood, or is an
5147 inequality floating-point comparison which needs to be reversed, 0 will
5150 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5151 insn used in locating the condition was found. If a replacement test
5152 of the condition is desired, it should be placed in front of that
5153 insn and we will be sure that the inputs are still valid. If EARLIEST
5154 is null, the returned condition will be valid at INSN.
5156 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5157 compare CC mode register.
5159 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5162 get_condition (rtx jump
, rtx
*earliest
, int allow_cc_mode
, int valid_at_insn_p
)
5168 /* If this is not a standard conditional jump, we can't parse it. */
5170 || ! any_condjump_p (jump
))
5172 set
= pc_set (jump
);
5174 cond
= XEXP (SET_SRC (set
), 0);
5176 /* If this branches to JUMP_LABEL when the condition is false, reverse
5179 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5180 && XEXP (XEXP (SET_SRC (set
), 2), 0) == JUMP_LABEL (jump
);
5182 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5183 allow_cc_mode
, valid_at_insn_p
);
5186 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5187 TARGET_MODE_REP_EXTENDED.
5189 Note that we assume that the property of
5190 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5191 narrower than mode B. I.e., if A is a mode narrower than B then in
5192 order to be able to operate on it in mode B, mode A needs to
5193 satisfy the requirements set by the representation of mode B. */
5196 init_num_sign_bit_copies_in_rep (void)
5198 enum machine_mode mode
, in_mode
;
5200 for (in_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); in_mode
!= VOIDmode
;
5201 in_mode
= GET_MODE_WIDER_MODE (mode
))
5202 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= in_mode
;
5203 mode
= GET_MODE_WIDER_MODE (mode
))
5205 enum machine_mode i
;
5207 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5208 extends to the next widest mode. */
5209 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5210 || GET_MODE_WIDER_MODE (mode
) == in_mode
);
5212 /* We are in in_mode. Count how many bits outside of mode
5213 have to be copies of the sign-bit. */
5214 for (i
= mode
; i
!= in_mode
; i
= GET_MODE_WIDER_MODE (i
))
5216 enum machine_mode wider
= GET_MODE_WIDER_MODE (i
);
5218 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5219 /* We can only check sign-bit copies starting from the
5220 top-bit. In order to be able to check the bits we
5221 have already seen we pretend that subsequent bits
5222 have to be sign-bit copies too. */
5223 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5224 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5225 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5230 /* Suppose that truncation from the machine mode of X to MODE is not a
5231 no-op. See if there is anything special about X so that we can
5232 assume it already contains a truncated value of MODE. */
5235 truncated_to_mode (enum machine_mode mode
, const_rtx x
)
5237 /* This register has already been used in MODE without explicit
5239 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5242 /* See if we already satisfy the requirements of MODE. If yes we
5243 can just switch to MODE. */
5244 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5245 && (num_sign_bit_copies (x
, GET_MODE (x
))
5246 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5252 /* Initialize non_rtx_starting_operands, which is used to speed up
5258 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5260 const char *format
= GET_RTX_FORMAT (i
);
5261 const char *first
= strpbrk (format
, "eEV");
5262 non_rtx_starting_operands
[i
] = first
? first
- format
: -1;
5265 init_num_sign_bit_copies_in_rep ();
5268 /* Check whether this is a constant pool constant. */
5270 constant_pool_constant_p (rtx x
)
5272 x
= avoid_constant_pool_reference (x
);
5273 return CONST_DOUBLE_P (x
);
5276 /* If M is a bitmask that selects a field of low-order bits within an item but
5277 not the entire word, return the length of the field. Return -1 otherwise.
5278 M is used in machine mode MODE. */
5281 low_bitmask_len (enum machine_mode mode
, unsigned HOST_WIDE_INT m
)
5283 if (mode
!= VOIDmode
)
5285 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
5287 m
&= GET_MODE_MASK (mode
);
5290 return exact_log2 (m
+ 1);
5293 /* Return the mode of MEM's address. */
5296 get_address_mode (rtx mem
)
5298 enum machine_mode mode
;
5300 gcc_assert (MEM_P (mem
));
5301 mode
= GET_MODE (XEXP (mem
, 0));
5302 if (mode
!= VOIDmode
)
5304 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5307 /* Split up a CONST_DOUBLE or integer constant rtx
5308 into two rtx's for single words,
5309 storing in *FIRST the word that comes first in memory in the target
5310 and in *SECOND the other. */
5313 split_double (rtx value
, rtx
*first
, rtx
*second
)
5315 if (CONST_INT_P (value
))
5317 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5319 /* In this case the CONST_INT holds both target words.
5320 Extract the bits from it into two word-sized pieces.
5321 Sign extend each half to HOST_WIDE_INT. */
5322 unsigned HOST_WIDE_INT low
, high
;
5323 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5324 unsigned bits_per_word
= BITS_PER_WORD
;
5326 /* Set sign_bit to the most significant bit of a word. */
5328 sign_bit
<<= bits_per_word
- 1;
5330 /* Set mask so that all bits of the word are set. We could
5331 have used 1 << BITS_PER_WORD instead of basing the
5332 calculation on sign_bit. However, on machines where
5333 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5334 compiler warning, even though the code would never be
5336 mask
= sign_bit
<< 1;
5339 /* Set sign_extend as any remaining bits. */
5340 sign_extend
= ~mask
;
5342 /* Pick the lower word and sign-extend it. */
5343 low
= INTVAL (value
);
5348 /* Pick the higher word, shifted to the least significant
5349 bits, and sign-extend it. */
5350 high
= INTVAL (value
);
5351 high
>>= bits_per_word
- 1;
5354 if (high
& sign_bit
)
5355 high
|= sign_extend
;
5357 /* Store the words in the target machine order. */
5358 if (WORDS_BIG_ENDIAN
)
5360 *first
= GEN_INT (high
);
5361 *second
= GEN_INT (low
);
5365 *first
= GEN_INT (low
);
5366 *second
= GEN_INT (high
);
5371 /* The rule for using CONST_INT for a wider mode
5372 is that we regard the value as signed.
5373 So sign-extend it. */
5374 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
5375 if (WORDS_BIG_ENDIAN
)
5387 else if (!CONST_DOUBLE_P (value
))
5389 if (WORDS_BIG_ENDIAN
)
5391 *first
= const0_rtx
;
5397 *second
= const0_rtx
;
5400 else if (GET_MODE (value
) == VOIDmode
5401 /* This is the old way we did CONST_DOUBLE integers. */
5402 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
5404 /* In an integer, the words are defined as most and least significant.
5405 So order them by the target's convention. */
5406 if (WORDS_BIG_ENDIAN
)
5408 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5409 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
5413 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
5414 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5421 REAL_VALUE_FROM_CONST_DOUBLE (r
, value
);
5423 /* Note, this converts the REAL_VALUE_TYPE to the target's
5424 format, splits up the floating point double and outputs
5425 exactly 32 bits of it into each of l[0] and l[1] --
5426 not necessarily BITS_PER_WORD bits. */
5427 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
5429 /* If 32 bits is an entire word for the target, but not for the host,
5430 then sign-extend on the host so that the number will look the same
5431 way on the host that it would on the target. See for instance
5432 simplify_unary_operation. The #if is needed to avoid compiler
5435 #if HOST_BITS_PER_LONG > 32
5436 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
5438 if (l
[0] & ((long) 1 << 31))
5439 l
[0] |= ((long) (-1) << 32);
5440 if (l
[1] & ((long) 1 << 31))
5441 l
[1] |= ((long) (-1) << 32);
5445 *first
= GEN_INT (l
[0]);
5446 *second
= GEN_INT (l
[1]);
5450 /* Strip outer address "mutations" from LOC and return a pointer to the
5451 inner value. If OUTER_CODE is nonnull, store the code of the innermost
5452 stripped expression there.
5454 "Mutations" either convert between modes or apply some kind of
5458 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
5462 enum rtx_code code
= GET_CODE (*loc
);
5463 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
5464 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
5465 used to convert between pointer sizes. */
5466 loc
= &XEXP (*loc
, 0);
5467 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
5468 /* (and ... (const_int -X)) is used to align to X bytes. */
5469 loc
= &XEXP (*loc
, 0);
5470 else if (code
== SUBREG
5471 && !OBJECT_P (SUBREG_REG (*loc
))
5472 && subreg_lowpart_p (*loc
))
5473 /* (subreg (operator ...) ...) inside and is used for mode
5475 loc
= &SUBREG_REG (*loc
);
5483 /* Return true if X must be a base rather than an index. */
5486 must_be_base_p (rtx x
)
5488 return GET_CODE (x
) == LO_SUM
;
5491 /* Return true if X must be an index rather than a base. */
5494 must_be_index_p (rtx x
)
5496 return GET_CODE (x
) == MULT
|| GET_CODE (x
) == ASHIFT
;
5499 /* Set the segment part of address INFO to LOC, given that INNER is the
5503 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5505 gcc_checking_assert (GET_CODE (*inner
) == UNSPEC
);
5507 gcc_assert (!info
->segment
);
5508 info
->segment
= loc
;
5509 info
->segment_term
= inner
;
5512 /* Set the base part of address INFO to LOC, given that INNER is the
5516 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5518 if (GET_CODE (*inner
) == LO_SUM
)
5519 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5520 gcc_checking_assert (REG_P (*inner
)
5522 || GET_CODE (*inner
) == SUBREG
);
5524 gcc_assert (!info
->base
);
5526 info
->base_term
= inner
;
5529 /* Set the index part of address INFO to LOC, given that INNER is the
5533 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5535 if ((GET_CODE (*inner
) == MULT
|| GET_CODE (*inner
) == ASHIFT
)
5536 && CONSTANT_P (XEXP (*inner
, 1)))
5537 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5538 gcc_checking_assert (REG_P (*inner
)
5540 || GET_CODE (*inner
) == SUBREG
);
5542 gcc_assert (!info
->index
);
5544 info
->index_term
= inner
;
5547 /* Set the displacement part of address INFO to LOC, given that INNER
5548 is the constant term. */
5551 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5553 gcc_checking_assert (CONSTANT_P (*inner
));
5555 gcc_assert (!info
->disp
);
5557 info
->disp_term
= inner
;
5560 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
5561 rest of INFO accordingly. */
5564 decompose_incdec_address (struct address_info
*info
)
5566 info
->autoinc_p
= true;
5568 rtx
*base
= &XEXP (*info
->inner
, 0);
5569 set_address_base (info
, base
, base
);
5570 gcc_checking_assert (info
->base
== info
->base_term
);
5572 /* These addresses are only valid when the size of the addressed
5574 gcc_checking_assert (info
->mode
!= VOIDmode
);
5577 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
5578 of INFO accordingly. */
5581 decompose_automod_address (struct address_info
*info
)
5583 info
->autoinc_p
= true;
5585 rtx
*base
= &XEXP (*info
->inner
, 0);
5586 set_address_base (info
, base
, base
);
5587 gcc_checking_assert (info
->base
== info
->base_term
);
5589 rtx plus
= XEXP (*info
->inner
, 1);
5590 gcc_assert (GET_CODE (plus
) == PLUS
);
5592 info
->base_term2
= &XEXP (plus
, 0);
5593 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
5595 rtx
*step
= &XEXP (plus
, 1);
5596 rtx
*inner_step
= strip_address_mutations (step
);
5597 if (CONSTANT_P (*inner_step
))
5598 set_address_disp (info
, step
, inner_step
);
5600 set_address_index (info
, step
, inner_step
);
5603 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
5604 values in [PTR, END). Return a pointer to the end of the used array. */
5607 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
5610 if (GET_CODE (x
) == PLUS
)
5612 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
5613 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
5617 gcc_assert (ptr
!= end
);
5623 /* Evaluate the likelihood of X being a base or index value, returning
5624 positive if it is likely to be a base, negative if it is likely to be
5625 an index, and 0 if we can't tell. Make the magnitude of the return
5626 value reflect the amount of confidence we have in the answer.
5628 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
5631 baseness (rtx x
, enum machine_mode mode
, addr_space_t as
,
5632 enum rtx_code outer_code
, enum rtx_code index_code
)
5634 /* See whether we can be certain. */
5635 if (must_be_base_p (x
))
5637 if (must_be_index_p (x
))
5640 /* Believe *_POINTER unless the address shape requires otherwise. */
5641 if (REG_P (x
) && REG_POINTER (x
))
5643 if (MEM_P (x
) && MEM_POINTER (x
))
5646 if (REG_P (x
) && HARD_REGISTER_P (x
))
5648 /* X is a hard register. If it only fits one of the base
5649 or index classes, choose that interpretation. */
5650 int regno
= REGNO (x
);
5651 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
5652 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
5653 if (base_p
!= index_p
)
5654 return base_p
? 1 : -1;
5659 /* INFO->INNER describes a normal, non-automodified address.
5660 Fill in the rest of INFO accordingly. */
5663 decompose_normal_address (struct address_info
*info
)
5665 /* Treat the address as the sum of up to four values. */
5667 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
5668 ops
+ ARRAY_SIZE (ops
)) - ops
;
5670 /* If there is more than one component, any base component is in a PLUS. */
5672 info
->base_outer_code
= PLUS
;
5674 /* Separate the parts that contain a REG or MEM from those that don't.
5675 Record the latter in INFO and leave the former in OPS. */
5678 for (size_t in
= 0; in
< n_ops
; ++in
)
5681 rtx
*inner
= strip_address_mutations (loc
);
5682 if (CONSTANT_P (*inner
))
5683 set_address_disp (info
, loc
, inner
);
5684 else if (GET_CODE (*inner
) == UNSPEC
)
5685 set_address_segment (info
, loc
, inner
);
5689 inner_ops
[out
] = inner
;
5694 /* Classify the remaining OPS members as bases and indexes. */
5697 /* Assume that the remaining value is a base unless the shape
5698 requires otherwise. */
5699 if (!must_be_index_p (*inner_ops
[0]))
5700 set_address_base (info
, ops
[0], inner_ops
[0]);
5702 set_address_index (info
, ops
[0], inner_ops
[0]);
5706 /* In the event of a tie, assume the base comes first. */
5707 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
5709 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
5710 GET_CODE (*ops
[0])))
5712 set_address_base (info
, ops
[0], inner_ops
[0]);
5713 set_address_index (info
, ops
[1], inner_ops
[1]);
5717 set_address_base (info
, ops
[1], inner_ops
[1]);
5718 set_address_index (info
, ops
[0], inner_ops
[0]);
5722 gcc_assert (out
== 0);
5725 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
5726 or VOIDmode if not known. AS is the address space associated with LOC.
5727 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
5730 decompose_address (struct address_info
*info
, rtx
*loc
, enum machine_mode mode
,
5731 addr_space_t as
, enum rtx_code outer_code
)
5733 memset (info
, 0, sizeof (*info
));
5736 info
->addr_outer_code
= outer_code
;
5738 info
->inner
= strip_address_mutations (loc
, &outer_code
);
5739 info
->base_outer_code
= outer_code
;
5740 switch (GET_CODE (*info
->inner
))
5746 decompose_incdec_address (info
);
5751 decompose_automod_address (info
);
5755 decompose_normal_address (info
);
5760 /* Describe address operand LOC in INFO. */
5763 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
5765 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
5768 /* Describe the address of MEM X in INFO. */
5771 decompose_mem_address (struct address_info
*info
, rtx x
)
5773 gcc_assert (MEM_P (x
));
5774 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
5775 MEM_ADDR_SPACE (x
), MEM
);
5778 /* Update INFO after a change to the address it describes. */
5781 update_address (struct address_info
*info
)
5783 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
5784 info
->addr_outer_code
);
5787 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
5788 more complicated than that. */
5791 get_index_scale (const struct address_info
*info
)
5793 rtx index
= *info
->index
;
5794 if (GET_CODE (index
) == MULT
5795 && CONST_INT_P (XEXP (index
, 1))
5796 && info
->index_term
== &XEXP (index
, 0))
5797 return INTVAL (XEXP (index
, 1));
5799 if (GET_CODE (index
) == ASHIFT
5800 && CONST_INT_P (XEXP (index
, 1))
5801 && info
->index_term
== &XEXP (index
, 0))
5802 return (HOST_WIDE_INT
) 1 << INTVAL (XEXP (index
, 1));
5804 if (info
->index
== info
->index_term
)
5810 /* Return the "index code" of INFO, in the form required by
5814 get_index_code (const struct address_info
*info
)
5817 return GET_CODE (*info
->index
);
5820 return GET_CODE (*info
->disp
);