| blob | f821e499f2aba893d2147c11205b2d55ad4e437f |
1 ; GCC machine description for Matsushita MN10300
2 ;; Copyright (C) 1996, 1997 Free Software Foundation, Inc.
4 ;; Contributed by Jeff Law (law@cygnus.com).
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;; The original PO technology requires these to be ordered by speed,
24 ;; so that assigner will pick the fastest.
26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;; Condition code settings.
29 ;; none - insn does not affect cc
30 ;; none_0hit - insn does not affect cc but it does modify operand 0
31 ;; This attribute is used to keep track of when operand 0 changes.
32 ;; See the description of NOTICE_UPDATE_CC for more info.
33 ;; set_znv - insn sets z,n,v to useable values; c is unusable.
34 ;; set_zn - insn sets z,n to useable values; v,c are unuseable.
35 ;; compare - compare instruction
36 ;; invert -- like compare, but flags are inverted.
37 ;; clobber - value of cc is unknown
38 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber,invert"
39 (const_string "clobber"))
40 \f
41 ;; ----------------------------------------------------------------------
42 ;; MOVE INSTRUCTIONS
43 ;; ----------------------------------------------------------------------
45 ;; movqi
47 (define_expand "movqi"
48 [(set (match_operand:QI 0 "general_operand" "")
49 (match_operand:QI 1 "general_operand" ""))]
50 ""
51 "
52 {
53 /* One of the ops has to be in a register */
54 if (!register_operand (operand0, QImode)
55 && !register_operand (operand1, QImode))
56 operands[1] = copy_to_mode_reg (QImode, operand1);
57 }")
59 (define_insn ""
60 [(set (match_operand:QI 0 "general_operand" "=d,a,d,a,d,a,d,a,d,m")
61 (match_operand:QI 1 "general_operand" "0,0,I,I,a,d,di,ia,m,d"))]
62 "register_operand (operands[0], QImode)
63 || register_operand (operands[1], QImode)"
64 "*
65 {
66 switch (which_alternative)
67 {
68 case 0:
69 case 1:
70 return \"nop\";
71 case 2:
72 return \"clr %0\";
73 case 3:
74 if (zero_areg)
75 {
76 rtx xoperands[2];
78 xoperands[0] = operands[0];
79 xoperands[1] = zero_areg;
80 if (rtx_equal_p (xoperands[0], xoperands[1]))
81 output_asm_insn (\"sub %1,%0\", xoperands);
82 else
83 output_asm_insn (\"mov %1,%0\", xoperands);
84 return \"\";
85 }
87 /* FALLTHROUGH */
88 case 4:
89 case 5:
90 case 6:
91 case 7:
92 return \"mov %1,%0\";
93 case 8:
94 case 9:
95 return \"movbu %1,%0\";
96 }
97 }"
98 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
100 ;; movhi
102 (define_expand "movhi"
103 [(set (match_operand:HI 0 "general_operand" "")
104 (match_operand:HI 1 "general_operand" ""))]
105 ""
106 "
107 {
108 /* One of the ops has to be in a register */
109 if (!register_operand (operand1, HImode)
110 && !register_operand (operand0, HImode))
111 operands[1] = copy_to_mode_reg (HImode, operand1);
112 }")
114 (define_insn ""
115 [(set (match_operand:HI 0 "general_operand" "=d,a,d,a,d,a,d,a,d,m")
116 (match_operand:HI 1 "general_operand" "0,0,I,I,a,d,di,ia,m,d"))]
117 "register_operand (operands[0], HImode)
118 || register_operand (operands[1], HImode)"
119 "*
120 {
121 switch (which_alternative)
122 {
123 case 0:
124 case 1:
125 return \"nop\";
126 case 2:
127 return \"clr %0\";
128 case 3:
129 if (zero_areg)
130 {
131 rtx xoperands[2];
133 xoperands[0] = operands[0];
134 xoperands[1] = zero_areg;
135 if (rtx_equal_p (xoperands[0], xoperands[1]))
136 output_asm_insn (\"sub %1,%0\", xoperands);
137 else
138 output_asm_insn (\"mov %1,%0\", xoperands);
139 return \"\";
140 }
142 /* FALLTHROUGH */
143 case 4:
144 case 5:
145 case 6:
146 case 7:
147 return \"mov %1,%0\";
148 case 8:
149 case 9:
150 return \"movhu %1,%0\";
151 }
152 }"
153 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
155 ;; movsi and helpers
157 ;; We use this to handle addition of two values when one operand is the
158 ;; stack pointer and the other is a memory reference of some kind. Reload
159 ;; does not handle them correctly without this expander.
160 (define_expand "reload_insi"
161 [(set (match_operand:SI 0 "register_operand" "=a")
162 (match_operand:SI 1 "impossible_plus_operand" ""))
163 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
164 ""
165 "
166 {
167 if (XEXP (operands[1], 0) == stack_pointer_rtx)
168 {
169 emit_move_insn (operands[0], XEXP (operands[1], 0));
170 if (GET_CODE (XEXP (operands[1], 1)) == SUBREG
171 && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 1)))
172 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 1))))))
173 emit_move_insn (operands[2],
174 gen_rtx (ZERO_EXTEND, GET_MODE (XEXP (operands[1], 1)),
175 SUBREG_REG (XEXP (operands[1], 1))));
176 else
177 emit_move_insn (operands[2], XEXP (operands[1], 1));
178 }
179 else
180 {
181 emit_move_insn (operands[0], XEXP (operands[1], 1));
182 if (GET_CODE (XEXP (operands[1], 0)) == SUBREG
183 && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 0)))
184 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 0))))))
185 emit_move_insn (operands[2],
186 gen_rtx (ZERO_EXTEND, GET_MODE (XEXP (operands[1], 0)),
187 SUBREG_REG (XEXP (operands[1], 0))));
188 else
189 emit_move_insn (operands[2], XEXP (operands[1], 0));
190 }
191 emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
192 DONE;
193 }")
195 (define_expand "movsi"
196 [(set (match_operand:SI 0 "general_operand" "")
197 (match_operand:SI 1 "general_operand" ""))]
198 ""
199 "
200 {
201 /* One of the ops has to be in a register */
202 if (!register_operand (operand1, SImode)
203 && !register_operand (operand0, SImode))
204 operands[1] = copy_to_mode_reg (SImode, operand1);
205 }")
207 (define_insn ""
208 [(set (match_operand:SI 0 "general_operand"
209 "=d,a,d,a,dm,dm,am,am,d,d,a,a,aR,x")
210 (match_operand:SI 1 "general_operand"
211 "0,0,I,I,d,a,d,a,dim,aim,dim,aim,x,aR"))]
212 "register_operand (operands[0], SImode)
213 || register_operand (operands[1], SImode)"
214 "*
215 {
216 switch (which_alternative)
217 {
218 case 0:
219 case 1:
220 return \"nop\";
221 case 2:
222 return \"clr %0\";
223 case 3:
224 if (zero_areg)
225 {
226 rtx xoperands[2];
228 xoperands[0] = operands[0];
229 xoperands[1] = zero_areg;
230 if (rtx_equal_p (xoperands[0], xoperands[1]))
231 output_asm_insn (\"sub %1,%0\", xoperands);
232 else
233 output_asm_insn (\"mov %1,%0\", xoperands);
234 return \"\";
235 }
237 /* FALLTHROUGH */
238 case 4:
239 case 5:
240 case 6:
241 case 7:
242 case 8:
243 case 9:
244 case 10:
245 case 11:
246 case 12:
247 case 13:
248 return \"mov %1,%0\";
249 }
250 }"
251 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
253 (define_expand "movsf"
254 [(set (match_operand:SF 0 "general_operand" "")
255 (match_operand:SF 1 "general_operand" ""))]
256 ""
257 "
258 {
259 /* One of the ops has to be in a register */
260 if (!register_operand (operand1, SFmode)
261 && !register_operand (operand0, SFmode))
262 operands[1] = copy_to_mode_reg (SFmode, operand1);
263 }")
265 (define_insn ""
266 [(set (match_operand:SF 0 "general_operand" "=d,a,d,a,dam,da")
267 (match_operand:SF 1 "general_operand" "0,0,G,G,da,daim"))]
268 "register_operand (operands[0], SFmode)
269 || register_operand (operands[1], SFmode)"
270 "*
271 {
272 switch (which_alternative)
273 {
274 case 0:
275 case 1:
276 return \"nop\";
277 case 2:
278 return \"clr %0\";
279 case 3:
280 if (zero_areg)
281 {
282 rtx xoperands[2];
284 xoperands[0] = operands[0];
285 xoperands[1] = zero_areg;
286 if (rtx_equal_p (xoperands[0], xoperands[1]))
287 output_asm_insn (\"sub %1,%0\", xoperands);
288 else
289 output_asm_insn (\"mov %1,%0\", xoperands);
290 return \"\";
291 }
293 /* FALLTHROUGH */
294 case 4:
295 case 5:
296 return \"mov %1,%0\";
297 }
298 }"
299 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit")])
301 (define_expand "movdi"
302 [(set (match_operand:DI 0 "general_operand" "")
303 (match_operand:DI 1 "general_operand" ""))]
304 ""
305 "
306 {
307 /* One of the ops has to be in a register */
308 if (!register_operand (operand1, DImode)
309 && !register_operand (operand0, DImode))
310 operands[1] = copy_to_mode_reg (DImode, operand1);
311 }")
313 (define_insn ""
314 [(set (match_operand:DI 0 "general_operand"
315 "=d,a,d,a,dm,dm,am,am,d,d,a,a")
316 (match_operand:DI 1 "general_operand"
317 "0,0,I,I,d,a,d,a,dim,aim,dim,aim"))]
318 "register_operand (operands[0], DImode)
319 || register_operand (operands[1], DImode)"
320 "*
321 {
322 long val[2];
323 REAL_VALUE_TYPE rv;
325 switch (which_alternative)
326 {
327 case 0:
328 case 1:
329 return \"nop\";
331 case 2:
332 return \"clr %L0\;clr %H0\";
334 case 3:
335 {
336 rtx xoperands[2];
338 xoperands[0] = operands[0];
339 xoperands[1] = zero_areg ? zero_areg : operands[1];
340 if (rtx_equal_p (xoperands[0], xoperands[1]))
341 output_asm_insn (\"sub %L1,%L0\;mov %L0,%H0\", xoperands);
342 else
343 output_asm_insn (\"mov %1,%L0\;mov %L0,%H0\", xoperands);
344 return \"\";
345 }
346 case 4:
347 case 5:
348 case 6:
349 case 7:
350 case 8:
351 case 9:
352 case 10:
353 case 11:
354 if (GET_CODE (operands[1]) == CONST_INT)
355 {
356 val[0] = INTVAL (operands[1]);
357 val[1] = val[0] < 0 ? -1 : 0;
358 }
359 if (GET_CODE (operands[1]) == CONST_DOUBLE)
360 {
361 if (GET_MODE (operands[1]) == DFmode)
362 {
363 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
364 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
365 }
366 else if (GET_MODE (operands[1]) == VOIDmode
367 || GET_MODE (operands[1]) == DImode)
368 {
369 val[0] = CONST_DOUBLE_LOW (operands[1]);
370 val[1] = CONST_DOUBLE_HIGH (operands[1]);
371 }
372 }
374 if (GET_CODE (operands[1]) == MEM
375 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
376 {
377 rtx temp = operands[0];
379 while (GET_CODE (temp) == SUBREG)
380 temp = SUBREG_REG (temp);
382 if (GET_CODE (temp) != REG)
383 abort ();
385 if (reg_overlap_mentioned_p (gen_rtx (REG, SImode, REGNO (temp)),
386 XEXP (operands[1], 0)))
387 return \"mov %H1,%H0\;mov %L1,%L0\";
388 else
389 return \"mov %L1,%L0\;mov %H1,%H0\";
391 }
392 else if (GET_CODE (operands[1]) == MEM
393 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
394 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
395 {
396 rtx xoperands[2];
398 xoperands[0] = operands[0];
399 xoperands[1] = XEXP (operands[1], 0);
401 output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
402 xoperands);
403 return \"\";
404 }
405 else
406 {
407 if ((GET_CODE (operands[1]) == CONST_INT
408 || GET_CODE (operands[1]) == CONST_DOUBLE)
409 && val[0] == 0)
410 {
411 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
412 output_asm_insn (\"clr %L0\", operands);
413 else if (zero_areg)
414 {
415 rtx xoperands[2];
417 xoperands[0] = operands[0];
418 xoperands[1] = zero_areg;
419 if (rtx_equal_p (xoperands[0], xoperands[1]))
420 output_asm_insn (\"sub %L0,%L0\", xoperands);
421 else
422 output_asm_insn (\"mov %1,%L0\", xoperands);
423 }
424 else
425 output_asm_insn (\"mov %L1,%L0\", operands);
426 }
427 else
428 output_asm_insn (\"mov %L1,%L0\", operands);
430 if ((GET_CODE (operands[1]) == CONST_INT
431 || GET_CODE (operands[1]) == CONST_DOUBLE)
432 && val[1] == 0)
433 {
434 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
435 output_asm_insn (\"clr %H0\", operands);
436 else if (zero_areg)
437 {
438 rtx xoperands[2];
440 xoperands[0] = operands[0];
441 xoperands[1] = zero_areg;
442 if (rtx_equal_p (xoperands[0], xoperands[1]))
443 output_asm_insn (\"sub %H0,%H0\", xoperands);
444 else
445 output_asm_insn (\"mov %1,%H0\", xoperands);
446 }
447 else
448 output_asm_insn (\"mov %H1,%H0\", operands);
449 }
450 else if ((GET_CODE (operands[1]) == CONST_INT
451 || GET_CODE (operands[1]) == CONST_DOUBLE)
452 && val[0] == val[1])
453 output_asm_insn (\"mov %L0,%H0\", operands);
454 else
455 output_asm_insn (\"mov %H1,%H0\", operands);
456 return \"\";
457 }
458 }
459 }"
460 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
462 (define_expand "movdf"
463 [(set (match_operand:DF 0 "general_operand" "")
464 (match_operand:DF 1 "general_operand" ""))]
465 ""
466 "
467 {
468 /* One of the ops has to be in a register */
469 if (!register_operand (operand1, DFmode)
470 && !register_operand (operand0, DFmode))
471 operands[1] = copy_to_mode_reg (DFmode, operand1);
472 }")
474 (define_insn ""
475 [(set (match_operand:DF 0 "general_operand"
476 "=d,a,d,a,dm,dm,am,am,d,d,a,a")
477 (match_operand:DF 1 "general_operand"
478 "0,0,G,G,d,a,d,a,dim,aim,dim,aim"))]
479 "register_operand (operands[0], DFmode)
480 || register_operand (operands[1], DFmode)"
481 "*
482 {
483 long val[2];
484 REAL_VALUE_TYPE rv;
486 switch (which_alternative)
487 {
488 case 0:
489 case 1:
490 return \"nop\";
492 case 2:
493 return \"clr %L0\;clr %H0\";
495 case 3:
496 {
497 rtx xoperands[2];
499 xoperands[0] = operands[0];
500 xoperands[1] = zero_areg ? zero_areg : operands[1];
501 if (rtx_equal_p (xoperands[0], xoperands[1]))
502 output_asm_insn (\"sub %L1,%L0\;mov %L0,%H0\", xoperands);
503 else
504 output_asm_insn (\"mov %1,%L0\;mov %L0,%H0\", xoperands);
505 return \"\";
506 }
507 case 4:
508 case 5:
509 case 6:
510 case 7:
511 case 8:
512 case 9:
513 case 10:
514 case 11:
515 if (GET_CODE (operands[1]) == CONST_INT)
516 {
517 val[0] = INTVAL (operands[1]);
518 val[1] = val[0] < 0 ? -1 : 0;
519 }
520 if (GET_CODE (operands[1]) == CONST_DOUBLE)
521 {
522 if (GET_MODE (operands[1]) == DFmode)
523 {
524 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
525 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
526 }
527 else if (GET_MODE (operands[1]) == VOIDmode
528 || GET_MODE (operands[1]) == DImode)
529 {
530 val[0] = CONST_DOUBLE_LOW (operands[1]);
531 val[1] = CONST_DOUBLE_HIGH (operands[1]);
532 }
533 }
535 if (GET_CODE (operands[1]) == MEM
536 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
537 {
538 rtx temp = operands[0];
540 while (GET_CODE (temp) == SUBREG)
541 temp = SUBREG_REG (temp);
543 if (GET_CODE (temp) != REG)
544 abort ();
546 if (reg_overlap_mentioned_p (gen_rtx (REG, SImode, REGNO (temp)),
547 XEXP (operands[1], 0)))
548 return \"mov %H1,%H0\;mov %L1,%L0\";
549 else
550 return \"mov %L1,%L0\;mov %H1,%H0\";
552 }
553 else if (GET_CODE (operands[1]) == MEM
554 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
555 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
556 {
557 rtx xoperands[2];
559 xoperands[0] = operands[0];
560 xoperands[1] = XEXP (operands[1], 0);
562 output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
563 xoperands);
564 return \"\";
565 }
566 else
567 {
568 if ((GET_CODE (operands[1]) == CONST_INT
569 || GET_CODE (operands[1]) == CONST_DOUBLE)
570 && val[0] == 0)
571 {
572 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
573 output_asm_insn (\"clr %L0\", operands);
574 else if (zero_areg)
575 {
576 rtx xoperands[2];
578 xoperands[0] = operands[0];
579 xoperands[1] = zero_areg;
580 if (rtx_equal_p (xoperands[0], xoperands[1]))
581 output_asm_insn (\"sub %L0,%L0\", xoperands);
582 else
583 output_asm_insn (\"mov %1,%L0\", xoperands);
584 }
585 else
586 output_asm_insn (\"mov %L1,%L0\", operands);
587 }
588 else
589 output_asm_insn (\"mov %L1,%L0\", operands);
591 if ((GET_CODE (operands[1]) == CONST_INT
592 || GET_CODE (operands[1]) == CONST_DOUBLE)
593 && val[1] == 0)
594 {
595 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
596 output_asm_insn (\"clr %H0\", operands);
597 else if (zero_areg)
598 {
599 rtx xoperands[2];
601 xoperands[0] = operands[0];
602 xoperands[1] = zero_areg;
603 if (rtx_equal_p (xoperands[0], xoperands[1]))
604 output_asm_insn (\"sub %H0,%H0\", xoperands);
605 else
606 output_asm_insn (\"mov %1,%H0\", xoperands);
607 }
608 else
609 output_asm_insn (\"mov %H1,%H0\", operands);
610 }
611 else if ((GET_CODE (operands[1]) == CONST_INT
612 || GET_CODE (operands[1]) == CONST_DOUBLE)
613 && val[0] == val[1])
614 output_asm_insn (\"mov %L0,%H0\", operands);
615 else
616 output_asm_insn (\"mov %H1,%H0\", operands);
617 return \"\";
618 }
619 }
620 }"
621 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
624 \f
625 ;; ----------------------------------------------------------------------
626 ;; TEST INSTRUCTIONS
627 ;; ----------------------------------------------------------------------
629 ;; Go ahead and define tstsi so we can eliminate redundant tst insns
630 ;; when we start trying to optimize this port.
631 (define_insn "tstsi"
632 [(set (cc0) (match_operand:SI 0 "register_operand" "da"))]
633 ""
634 "* return output_tst (operands[0], insn);"
635 [(set_attr "cc" "set_znv")])
637 (define_insn ""
638 [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "d")))]
639 ""
640 "* return output_tst (operands[0], insn);"
641 [(set_attr "cc" "set_znv")])
643 (define_insn ""
644 [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "d")))]
645 ""
646 "* return output_tst (operands[0], insn);"
647 [(set_attr "cc" "set_znv")])
650 (define_insn "cmpsi"
651 [(set (cc0)
652 (compare (match_operand:SI 0 "register_operand" "!*d*a,da")
653 (match_operand:SI 1 "nonmemory_operand" "!*0,dai")))]
654 ""
655 "@
656 add 0,%0
657 cmp %1,%0"
658 [(set_attr "cc" "invert,compare")])
659 \f
660 ;; ----------------------------------------------------------------------
661 ;; ADD INSTRUCTIONS
662 ;; ----------------------------------------------------------------------
664 (define_expand "addsi3"
665 [(set (match_operand:SI 0 "register_operand" "")
666 (plus:SI (match_operand:SI 1 "register_operand" "")
667 (match_operand:SI 2 "nonmemory_operand" "")))]
668 ""
669 "
670 {
671 /* We can't add a variable amount directly to the stack pointer;
672 so do so via a temporary register. */
673 if (operands[0] == stack_pointer_rtx
674 && GET_CODE (operands[1]) != CONST_INT
675 && GET_CODE (operands[2]) != CONST_INT)
676 {
677 rtx temp = gen_reg_rtx (SImode);
678 emit_move_insn (temp, gen_rtx (PLUS, SImode, operands[1], operands[2]));
679 emit_move_insn (operands[0], temp);
680 DONE;
681 }
682 }")
684 (define_insn ""
685 [(set (match_operand:SI 0 "register_operand" "=d,a,a,da,x,&!da")
686 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,da")
687 (match_operand:SI 2 "nonmemory_operand" "J,J,L,dai,i,da")))]
688 ""
689 "@
690 inc %0
691 inc %0
692 inc4 %0
693 add %2,%0
694 add %2,%0
695 mov %2,%0\;add %1,%0"
696 [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
698 ;; ----------------------------------------------------------------------
699 ;; SUBTRACT INSTRUCTIONS
700 ;; ----------------------------------------------------------------------
702 (define_insn "subsi3"
703 [(set (match_operand:SI 0 "register_operand" "=da")
704 (minus:SI (match_operand:SI 1 "register_operand" "0")
705 (match_operand:SI 2 "nonmemory_operand" "dai")))]
706 ""
707 "sub %2,%0"
708 [(set_attr "cc" "set_zn")])
710 (define_expand "negsi2"
711 [(set (match_operand:SI 0 "register_operand" "")
712 (neg:SI (match_operand:SI 1 "register_operand" "")))]
713 ""
714 "
715 {
716 rtx target = gen_reg_rtx (SImode);
718 emit_move_insn (target, GEN_INT (0));
719 emit_insn (gen_subsi3 (target, target, operands[1]));
720 emit_move_insn (operands[0], target);
721 DONE;
722 }")
724 ;; ----------------------------------------------------------------------
725 ;; MULTIPLY INSTRUCTIONS
726 ;; ----------------------------------------------------------------------
728 (define_insn "mulsi3"
729 [(set (match_operand:SI 0 "register_operand" "=d")
730 (mult:SI (match_operand:SI 1 "register_operand" "%0")
731 (match_operand:SI 2 "register_operand" "d")))]
732 ""
733 "mul %2,%0"
734 [(set_attr "cc" "set_zn")])
736 (define_insn "udivmodsi4"
737 [(set (match_operand:SI 0 "general_operand" "=d")
738 (udiv:SI (match_operand:SI 1 "general_operand" "0")
739 (match_operand:SI 2 "general_operand" "d")))
740 (set (match_operand:SI 3 "general_operand" "=&d")
741 (umod:SI (match_dup 1) (match_dup 2)))]
742 ""
743 "*
744 {
745 if (zero_dreg)
746 output_asm_insn (\"mov %0,mdr\", &zero_dreg);
747 else
748 output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
750 if (find_reg_note (insn, REG_UNUSED, operands[3]))
751 return \"divu %2,%0\";
752 else
753 return \"divu %2,%0\;mov mdr,%3\";
754 }"
755 [(set_attr "cc" "set_zn")])
757 (define_insn "divmodsi4"
758 [(set (match_operand:SI 0 "general_operand" "=d")
759 (div:SI (match_operand:SI 1 "general_operand" "0")
760 (match_operand:SI 2 "general_operand" "d")))
761 (set (match_operand:SI 3 "general_operand" "=d")
762 (mod:SI (match_dup 1) (match_dup 2)))]
763 ""
764 "*
765 {
766 if (find_reg_note (insn, REG_UNUSED, operands[3]))
767 return \"ext %0\;div %2,%0\";
768 else
769 return \"ext %0\;div %2,%0\;mov mdr,%3\";
770 }"
771 [(set_attr "cc" "set_zn")])
773 \f
774 ;; ----------------------------------------------------------------------
775 ;; AND INSTRUCTIONS
776 ;; ----------------------------------------------------------------------
778 (define_insn "andsi3"
779 [(set (match_operand:SI 0 "register_operand" "=d,d")
780 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
781 (match_operand:SI 2 "nonmemory_operand" "N,di")))]
782 ""
783 "*
784 {
785 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
786 return \"extbu %0\";
787 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
788 return \"exthu %0\";
789 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
790 return \"add %0,%0\;lsr 1,%0\";
791 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
792 return \"asl2 %0\;lsr 2,%0\";
793 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
794 return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
795 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
796 return \"asl2 %0,%0\;asl2 %0\;lsr 4,%0\";
797 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
798 return \"lsr 1,%0\;add %0,%0\";
799 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
800 return \"lsr 2,%0\;asl2 %0\";
801 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
802 return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
803 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
804 return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
805 return \"and %2,%0\";
806 }"
807 [(set_attr "cc" "none_0hit,set_znv")])
809 ;; ----------------------------------------------------------------------
810 ;; OR INSTRUCTIONS
811 ;; ----------------------------------------------------------------------
813 (define_insn "iorsi3"
814 [(set (match_operand:SI 0 "register_operand" "=d")
815 (ior:SI (match_operand:SI 1 "register_operand" "%0")
816 (match_operand:SI 2 "nonmemory_operand" "di")))]
817 ""
818 "or %2,%0"
819 [(set_attr "cc" "set_znv")])
821 ;; ----------------------------------------------------------------------
822 ;; XOR INSTRUCTIONS
823 ;; ----------------------------------------------------------------------
825 (define_insn "xorsi3"
826 [(set (match_operand:SI 0 "register_operand" "=d")
827 (xor:SI (match_operand:SI 1 "register_operand" "%0")
828 (match_operand:SI 2 "nonmemory_operand" "di")))]
829 ""
830 "xor %2,%0"
831 [(set_attr "cc" "set_znv")])
833 ;; ----------------------------------------------------------------------
834 ;; NOT INSTRUCTIONS
835 ;; ----------------------------------------------------------------------
837 (define_insn "one_cmplsi2"
838 [(set (match_operand:SI 0 "register_operand" "=d")
839 (not:SI (match_operand:SI 1 "register_operand" "0")))]
840 ""
841 "not %0"
842 [(set_attr "cc" "set_znv")])
843 \f
844 ;; -----------------------------------------------------------------
845 ;; BIT FIELDS
846 ;; -----------------------------------------------------------------
849 ;; These set/clear memory in byte sized chunks.
850 ;;
851 ;; They are no smaller/faster than loading the value into a register
852 ;; and storing the register, but they don't need a scratch register
853 ;; which may allow for better code generation.
854 (define_insn ""
855 [(set (match_operand:QI 0 "general_operand" "=R,d") (const_int 0))]
856 ""
857 "@
858 bclr 255,%A0
859 clr %0"
860 [(set_attr "cc" "clobber")])
862 (define_insn ""
863 [(set (match_operand:QI 0 "general_operand" "=R,d") (const_int -1))]
864 ""
865 "@
866 bset 255,%A0
867 mov -1,%0"
868 [(set_attr "cc" "clobber,none_0hit")])
870 (define_insn ""
871 [(set (match_operand:QI 0 "general_operand" "=R,d")
872 (subreg:QI
873 (and:SI (subreg:SI (match_dup 0) 0)
874 (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
875 ""
876 "@
877 bclr %N1,%A0
878 and %1,%0"
879 [(set_attr "cc" "clobber,set_znv")])
881 (define_insn ""
882 [(set (match_operand:QI 0 "general_operand" "=R,d")
883 (subreg:QI
884 (ior:SI (subreg:SI (match_dup 0) 0)
885 (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
886 ""
887 "@
888 bset %1,%A0
889 or %1,%0"
890 [(set_attr "cc" "clobber,set_znv")])
892 (define_insn ""
893 [(set (cc0)
894 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
895 (match_operand 1 "const_int_operand" "")
896 (match_operand 2 "const_int_operand" "")))]
897 ""
898 "*
899 {
900 int len = INTVAL (operands[1]);
901 int bit = INTVAL (operands[2]);
902 int mask = 0;
903 rtx xoperands[2];
905 while (len > 0)
906 {
907 mask |= (1 << bit);
908 bit++;
909 len--;
910 }
912 xoperands[0] = operands[0];
913 xoperands[1] = GEN_INT (mask);
914 output_asm_insn (\"btst %1,%0\", xoperands);
915 return \"\";
916 }"
917 [(set_attr "cc" "set_znv")])
919 (define_insn ""
920 [(set (cc0)
921 (zero_extract:SI (match_operand:QI 0 "general_operand" "R,d")
922 (match_operand 1 "const_int_operand" "")
923 (match_operand 2 "const_int_operand" "")))]
924 "INTVAL (operands[1]) <= 8 && INTVAL (operands[2]) <= 7"
925 "*
926 {
927 int len = INTVAL (operands[1]);
928 int bit = INTVAL (operands[2]);
929 int mask = 0;
930 rtx xoperands[2];
932 while (len > 0)
933 {
934 mask |= (1 << bit);
935 bit++;
936 len--;
937 }
939 xoperands[0] = operands[0];
940 xoperands[1] = GEN_INT (mask);
941 if (GET_CODE (operands[0]) == REG)
942 output_asm_insn (\"btst %1,%0\", xoperands);
943 else
944 output_asm_insn (\"btst %1,%A0\", xoperands);
945 return \"\";
946 }"
947 [(set_attr "cc" "set_znv")])
949 (define_insn ""
950 [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "d")
951 (match_operand:SI 1 "const_int_operand" "")))]
952 ""
953 "btst %1,%0"
954 [(set_attr "cc" "set_znv")])
956 (define_insn ""
957 [(set (cc0)
958 (and:SI
959 (subreg:SI (match_operand:QI 0 "general_operand" "R,d") 0)
960 (match_operand:SI 1 "const_int_operand" "")))]
961 ""
962 "@
963 btst %1,%A0
964 btst %1,%0"
965 [(set_attr "cc" "set_znv")])
967 \f
968 ;; ----------------------------------------------------------------------
969 ;; JUMP INSTRUCTIONS
970 ;; ----------------------------------------------------------------------
972 ;; Conditional jump instructions
974 (define_expand "ble"
975 [(set (pc)
976 (if_then_else (le (cc0)
977 (const_int 0))
978 (label_ref (match_operand 0 "" ""))
979 (pc)))]
980 ""
981 "")
983 (define_expand "bleu"
984 [(set (pc)
985 (if_then_else (leu (cc0)
986 (const_int 0))
987 (label_ref (match_operand 0 "" ""))
988 (pc)))]
989 ""
990 "")
992 (define_expand "bge"
993 [(set (pc)
994 (if_then_else (ge (cc0)
995 (const_int 0))
996 (label_ref (match_operand 0 "" ""))
997 (pc)))]
998 ""
999 "")
1001 (define_expand "bgeu"
1002 [(set (pc)
1003 (if_then_else (geu (cc0)
1004 (const_int 0))
1005 (label_ref (match_operand 0 "" ""))
1006 (pc)))]
1007 ""
1008 "")
1010 (define_expand "blt"
1011 [(set (pc)
1012 (if_then_else (lt (cc0)
1013 (const_int 0))
1014 (label_ref (match_operand 0 "" ""))
1015 (pc)))]
1016 ""
1017 "")
1019 (define_expand "bltu"
1020 [(set (pc)
1021 (if_then_else (ltu (cc0)
1022 (const_int 0))
1023 (label_ref (match_operand 0 "" ""))
1024 (pc)))]
1025 ""
1026 "")
1028 (define_expand "bgt"
1029 [(set (pc)
1030 (if_then_else (gt (cc0)
1031 (const_int 0))
1032 (label_ref (match_operand 0 "" ""))
1033 (pc)))]
1034 ""
1035 "")
1037 (define_expand "bgtu"
1038 [(set (pc)
1039 (if_then_else (gtu (cc0)
1040 (const_int 0))
1041 (label_ref (match_operand 0 "" ""))
1042 (pc)))]
1043 ""
1044 "")
1046 (define_expand "beq"
1047 [(set (pc)
1048 (if_then_else (eq (cc0)
1049 (const_int 0))
1050 (label_ref (match_operand 0 "" ""))
1051 (pc)))]
1052 ""
1053 "")
1055 (define_expand "bne"
1056 [(set (pc)
1057 (if_then_else (ne (cc0)
1058 (const_int 0))
1059 (label_ref (match_operand 0 "" ""))
1060 (pc)))]
1061 ""
1062 "")
1064 (define_insn ""
1065 [(set (pc)
1066 (if_then_else (match_operator 1 "comparison_operator"
1067 [(cc0) (const_int 0)])
1068 (label_ref (match_operand 0 "" ""))
1069 (pc)))]
1070 ""
1071 "*
1072 {
1073 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1074 && (GET_CODE (operands[1]) == GT
1075 || GET_CODE (operands[1]) == GE
1076 || GET_CODE (operands[1]) == LE
1077 || GET_CODE (operands[1]) == LT))
1078 return 0;
1079 return \"b%b1 %0\";
1080 }"
1081 [(set_attr "cc" "none")])
1083 (define_insn ""
1084 [(set (pc)
1085 (if_then_else (match_operator 1 "comparison_operator"
1086 [(cc0) (const_int 0)])
1087 (pc)
1088 (label_ref (match_operand 0 "" ""))))]
1089 ""
1090 "*
1091 {
1092 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1093 && (GET_CODE (operands[1]) == GT
1094 || GET_CODE (operands[1]) == GE
1095 || GET_CODE (operands[1]) == LE
1096 || GET_CODE (operands[1]) == LT))
1097 return 0;
1098 return \"b%B1 %0\";
1099 }"
1100 [(set_attr "cc" "none")])
1102 ;; Unconditional and other jump instructions.
1104 (define_insn "jump"
1105 [(set (pc)
1106 (label_ref (match_operand 0 "" "")))]
1107 ""
1108 "jmp %l0"
1109 [(set_attr "cc" "none")])
1111 (define_insn "indirect_jump"
1112 [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
1113 ""
1114 "jmp (%0)"
1115 [(set_attr "cc" "none")])
1117 (define_insn "tablejump"
1118 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1119 (use (label_ref (match_operand 1 "" "")))]
1120 ""
1121 "jmp (%0)"
1122 [(set_attr "cc" "none")])
1124 ;; Call subroutine with no return value.
1126 (define_expand "call"
1127 [(call (match_operand:QI 0 "general_operand" "")
1128 (match_operand:SI 1 "general_operand" ""))]
1129 ""
1130 "
1131 {
1132 if (! call_address_operand (XEXP (operands[0], 0)))
1133 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
1134 emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
1135 DONE;
1136 }")
1138 (define_insn "call_internal"
1139 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "aS"))
1140 (match_operand:SI 1 "general_operand" "g"))]
1141 ""
1142 "*
1143 {
1144 if (REG_P (operands[0]))
1145 return \"calls %C0\";
1146 else
1147 return \"call %C0,[],0\";
1148 }"
1149 [(set_attr "cc" "clobber")])
1151 ;; Call subroutine, returning value in operand 0
1152 ;; (which must be a hard register).
1154 (define_expand "call_value"
1155 [(set (match_operand 0 "" "")
1156 (call (match_operand:QI 1 "general_operand" "")
1157 (match_operand:SI 2 "general_operand" "")))]
1158 ""
1159 "
1160 {
1161 if (! call_address_operand (XEXP (operands[1], 0)))
1162 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1163 emit_call_insn (gen_call_value_internal (operands[0],
1164 XEXP (operands[1], 0),
1165 operands[2]));
1166 DONE;
1167 }")
1169 (define_insn "call_value_internal"
1170 [(set (match_operand 0 "" "=da")
1171 (call (mem:QI (match_operand:SI 1 "call_address_operand" "aS"))
1172 (match_operand:SI 2 "general_operand" "g")))]
1173 ""
1174 "*
1175 {
1176 if (REG_P (operands[1]))
1177 return \"calls %C1\";
1178 else
1179 return \"call %C1,[],0\";
1180 }"
1181 [(set_attr "cc" "clobber")])
1183 (define_expand "untyped_call"
1184 [(parallel [(call (match_operand 0 "" "")
1185 (const_int 0))
1186 (match_operand 1 "" "")
1187 (match_operand 2 "" "")])]
1188 ""
1189 "
1190 {
1191 int i;
1193 emit_call_insn (gen_call (operands[0], const0_rtx));
1195 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1196 {
1197 rtx set = XVECEXP (operands[2], 0, i);
1198 emit_move_insn (SET_DEST (set), SET_SRC (set));
1199 }
1200 DONE;
1201 }")
1203 (define_insn "nop"
1204 [(const_int 0)]
1205 ""
1206 "nop"
1207 [(set_attr "cc" "none")])
1208 \f
1209 ;; ----------------------------------------------------------------------
1210 ;; EXTEND INSTRUCTIONS
1211 ;; ----------------------------------------------------------------------
1213 (define_insn "zero_extendqisi2"
1214 [(set (match_operand:SI 0 "general_operand" "=d,d,d")
1215 (zero_extend:SI
1216 (match_operand:QI 1 "general_operand" "0,d,m")))]
1217 ""
1218 "@
1219 extbu %0
1220 mov %1,%0\;extbu %0
1221 movbu %1,%0"
1222 [(set_attr "cc" "none_0hit")])
1224 (define_insn "zero_extendhisi2"
1225 [(set (match_operand:SI 0 "general_operand" "=d,d,d")
1226 (zero_extend:SI
1227 (match_operand:HI 1 "general_operand" "0,d,m")))]
1228 ""
1229 "@
1230 exthu %0
1231 mov %1,%0\;exthu %0
1232 movhu %1,%0"
1233 [(set_attr "cc" "none_0hit")])
1235 ;;- sign extension instructions
1237 (define_insn "extendqisi2"
1238 [(set (match_operand:SI 0 "general_operand" "=d,d")
1239 (sign_extend:SI
1240 (match_operand:QI 1 "general_operand" "0,d")))]
1241 ""
1242 "@
1243 extb %0
1244 mov %1,%0\;extb %0"
1245 [(set_attr "cc" "none_0hit")])
1247 (define_insn "extendhisi2"
1248 [(set (match_operand:SI 0 "general_operand" "=d,d")
1249 (sign_extend:SI
1250 (match_operand:HI 1 "general_operand" "0,d")))]
1251 ""
1252 "@
1253 exth %0
1254 mov %1,%0\;exth %0"
1255 [(set_attr "cc" "none_0hit")])
1256 \f
1257 ;; ----------------------------------------------------------------------
1258 ;; SHIFTS
1259 ;; ----------------------------------------------------------------------
1261 (define_insn "ashlsi3"
1262 [(set (match_operand:SI 0 "register_operand" "=da,d,d,d,d")
1263 (ashift:SI
1264 (match_operand:SI 1 "register_operand" "0,0,0,0,0")
1265 (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,di")))]
1266 ""
1267 "@
1268 add %0,%0
1269 asl2 %0
1270 asl2 %0\;add %0,%0
1271 asl2 %0\;asl2 %0
1272 asl %2,%0"
1273 [(set_attr "cc" "set_zn")])
1275 (define_insn "lshrsi3"
1276 [(set (match_operand:SI 0 "register_operand" "=d")
1277 (lshiftrt:SI
1278 (match_operand:SI 1 "register_operand" "0")
1279 (match_operand:QI 2 "nonmemory_operand" "di")))]
1280 ""
1281 "lsr %2,%0"
1282 [(set_attr "cc" "set_zn")])
1284 (define_insn "ashrsi3"
1285 [(set (match_operand:SI 0 "register_operand" "=d")
1286 (ashiftrt:SI
1287 (match_operand:SI 1 "register_operand" "0")
1288 (match_operand:QI 2 "nonmemory_operand" "di")))]
1289 ""
1290 "asr %2,%0"
1291 [(set_attr "cc" "set_zn")])
1293 ;; ----------------------------------------------------------------------
1294 ;; PROLOGUE/EPILOGUE
1295 ;; ----------------------------------------------------------------------
1296 (define_expand "prologue"
1297 [(const_int 0)]
1298 ""
1299 "expand_prologue (); DONE;")
1301 (define_expand "epilogue"
1302 [(return)]
1303 ""
1304 "
1305 {
1306 expand_epilogue ();
1307 DONE;
1308 }")
1310 (define_insn "return_internal"
1311 [(const_int 2)]
1312 ""
1313 "rets"
1314 [(set_attr "cc" "clobber")])
1316 ;; This insn restores the callee saved registers and does a return, it
1317 ;; can also deallocate stack space.
1318 (define_insn "return_internal_regs"
1319 [(const_int 0)
1320 (match_operand:SI 0 "const_int_operand" "i")
1321 (return)]
1322 ""
1323 "ret [d2,d3,a2,a3],%0"
1324 [(set_attr "cc" "clobber")])
1326 (define_insn "store_movm"
1327 [(const_int 1)]
1328 ""
1329 "movm [d2,d3,a2,a3],(sp)"
1330 [(set_attr "cc" "clobber")])
1332 (define_insn "return"
1333 [(return)]
1334 "can_use_return_insn ()"
1335 "*
1336 {
1337 rtx next = next_active_insn (insn);
1339 if (next
1340 && GET_CODE (next) == JUMP_INSN
1341 && GET_CODE (PATTERN (next)) == RETURN)
1342 return \"\";
1343 else
1344 return \"rets\";
1345 }"
1346 [(set_attr "cc" "clobber")])
1348 ;; Try to combine consecutive updates of the stack pointer (or any
1349 ;; other register for that matter).
1350 (define_peephole
1351 [(set (match_operand:SI 0 "register_operand" "=dax")
1352 (plus:SI (match_dup 0)
1353 (match_operand 1 "const_int_operand" "")))
1354 (set (match_dup 0)
1355 (plus:SI (match_dup 0)
1356 (match_operand 2 "const_int_operand" "")))]
1357 ""
1358 "*
1359 {
1360 operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
1361 return \"add %1,%0\";
1362 }"
1363 [(set_attr "cc" "clobber")])
1365 ;;
1366 ;; We had patterns to check eq/ne, but the they don't work because
1367 ;; 0x80000000 + 0x80000000 = 0x0 with a carry out.
1368 ;;
1369 ;; The Z flag and C flag would be set, and we have no way to
1370 ;; check for the Z flag set and C flag clear.
1371 ;;
1372 ;; This will work on the mn10200 because we can check the ZX flag
1373 ;; if the comparison is in HImode.
1374 (define_peephole
1375 [(set (cc0) (match_operand:SI 0 "register_operand" "d"))
1376 (set (pc) (if_then_else (ge (cc0) (const_int 0))
1377 (match_operand 1 "" "")
1378 (pc)))]
1379 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
1380 "add %0,%0\;bcc %1"
1381 [(set_attr "cc" "clobber")])
1383 (define_peephole
1384 [(set (cc0) (match_operand:SI 0 "register_operand" "d"))
1385 (set (pc) (if_then_else (lt (cc0) (const_int 0))
1386 (match_operand 1 "" "")
1387 (pc)))]
1388 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
1389 "add %0,%0\;bcs %1"
1390 [(set_attr "cc" "clobber")])
1392 (define_peephole
1393 [(set (cc0) (match_operand:SI 0 "register_operand" "d"))
1394 (set (pc) (if_then_else (ge (cc0) (const_int 0))
1395 (pc)
1396 (match_operand 1 "" "")))]
1397 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
1398 "add %0,%0\;bcs %1"
1399 [(set_attr "cc" "clobber")])
1401 (define_peephole
1402 [(set (cc0) (match_operand:SI 0 "register_operand" "d"))
1403 (set (pc) (if_then_else (lt (cc0) (const_int 0))
1404 (pc)
1405 (match_operand 1 "" "")))]
1406 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
1407 "add %0,%0\;bcc %1"
1408 [(set_attr "cc" "clobber")])