| blob | 21959a53f0fe118b456a9ba1dcfbdaf3f5efa1df |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 2, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the
21 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 ;; MA 02110-1301, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;;
27 ;; UNSPEC usage
28 ;;
30 (define_constants
31 [(UNSPEC_FRSP 0) ; frsp for POWER machines
32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MOVSI_GOT 8)
36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_FCTIWZ 10)
38 (UNSPEC_FRIM 11)
39 (UNSPEC_FRIN 12)
40 (UNSPEC_FRIP 13)
41 (UNSPEC_FRIZ 14)
42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
44 (UNSPEC_TLSGD 17)
45 (UNSPEC_TLSLD 18)
46 (UNSPEC_MOVESI_FROM_CR 19)
47 (UNSPEC_MOVESI_TO_CR 20)
48 (UNSPEC_TLSDTPREL 21)
49 (UNSPEC_TLSDTPRELHA 22)
50 (UNSPEC_TLSDTPRELLO 23)
51 (UNSPEC_TLSGOTDTPREL 24)
52 (UNSPEC_TLSTPREL 25)
53 (UNSPEC_TLSTPRELHA 26)
54 (UNSPEC_TLSTPRELLO 27)
55 (UNSPEC_TLSGOTTPREL 28)
56 (UNSPEC_TLSTLS 29)
57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
59 (UNSPEC_STFIWX 32)
60 (UNSPEC_POPCNTB 33)
61 (UNSPEC_FRES 34)
62 (UNSPEC_SP_SET 35)
63 (UNSPEC_SP_TEST 36)
64 (UNSPEC_SYNC 37)
65 (UNSPEC_LWSYNC 38)
66 (UNSPEC_ISYNC 39)
67 (UNSPEC_SYNC_OP 40)
68 (UNSPEC_ATOMIC 41)
69 (UNSPEC_CMPXCHG 42)
70 (UNSPEC_XCHG 43)
71 (UNSPEC_AND 44)
72 (UNSPEC_DLMZB 45)
73 (UNSPEC_DLMZB_CR 46)
74 (UNSPEC_DLMZB_STRLEN 47)
75 ])
77 ;;
78 ;; UNSPEC_VOLATILE usage
79 ;;
81 (define_constants
82 [(UNSPECV_BLOCK 0)
83 (UNSPECV_LL 1) ; load-locked
84 (UNSPECV_SC 2) ; store-conditional
85 (UNSPECV_EH_RR 9) ; eh_reg_restore
86 ])
87 \f
88 ;; Define an insn type attribute. This is used in function unit delay
89 ;; computations.
90 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
91 (const_string "integer"))
93 ;; Length (in bytes).
94 ; '(pc)' in the following doesn't include the instruction itself; it is
95 ; calculated as if the instruction had zero size.
96 (define_attr "length" ""
97 (if_then_else (eq_attr "type" "branch")
98 (if_then_else (and (ge (minus (match_dup 0) (pc))
99 (const_int -32768))
100 (lt (minus (match_dup 0) (pc))
101 (const_int 32764)))
102 (const_int 4)
103 (const_int 8))
104 (const_int 4)))
106 ;; Processor type -- this attribute must exactly match the processor_type
107 ;; enumeration in rs6000.h.
109 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
110 (const (symbol_ref "rs6000_cpu_attr")))
113 ;; If this instruction is microcoded on the CELL processor
114 ; The default for load and stores is conditional
115 ; The default for load extended and the recorded instructions is always microcoded
116 (define_attr "cell_micro" "not,conditional,always"
117 (if_then_else (ior (ior (eq_attr "type" "load")
118 (eq_attr "type" "store"))
119 (ior (eq_attr "type" "fpload")
120 (eq_attr "type" "fpstore")))
121 (const_string "conditional")
122 (if_then_else (ior (eq_attr "type" "load_ext")
123 (ior (eq_attr "type" "compare")
124 (eq_attr "type" "delayed_compare")))
125 (const_string "always")
126 (const_string "not"))))
129 (automata_option "ndfa")
131 (include "rios1.md")
132 (include "rios2.md")
133 (include "rs64.md")
134 (include "mpc.md")
135 (include "40x.md")
136 (include "440.md")
137 (include "603.md")
138 (include "6xx.md")
139 (include "7xx.md")
140 (include "7450.md")
141 (include "8540.md")
142 (include "power4.md")
143 (include "power5.md")
144 (include "power6.md")
145 (include "cell.md")
147 (include "predicates.md")
148 (include "constraints.md")
150 (include "darwin.md")
152 \f
153 ;; Mode macros
155 ; This mode macro allows :GPR to be used to indicate the allowable size
156 ; of whole values in GPRs.
157 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
159 ; Any supported integer mode.
160 (define_mode_macro INT [QI HI SI DI TI])
162 ; Any supported integer mode that fits in one register.
163 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
165 ; extend modes for DImode
166 (define_mode_macro QHSI [QI HI SI])
168 ; SImode or DImode, even if DImode doesn't fit in GPRs.
169 (define_mode_macro SDI [SI DI])
171 ; The size of a pointer. Also, the size of the value that a record-condition
172 ; (one with a '.') will compare.
173 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
175 ; Any hardware-supported floating-point mode
176 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
177 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
178 (TF "!TARGET_IEEEQUAD
179 && TARGET_HARD_FLOAT
180 && (TARGET_FPRS || TARGET_E500_DOUBLE)
181 && TARGET_LONG_DOUBLE_128")])
183 ; Various instructions that come in SI and DI forms.
184 ; A generic w/d attribute, for things like cmpw/cmpd.
185 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
187 ; DImode bits
188 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
190 \f
191 ;; Start with fixed-point load and store insns. Here we put only the more
192 ;; complex forms. Basic data transfer is done later.
194 (define_expand "zero_extend<mode>di2"
195 [(set (match_operand:DI 0 "gpc_reg_operand" "")
196 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
197 "TARGET_POWERPC64"
198 "")
200 (define_insn "*zero_extend<mode>di2_internal1"
201 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
202 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
203 "TARGET_POWERPC64"
204 "@
205 l<wd>z%U1%X1 %0,%1
206 rldicl %0,%1,0,<dbits>"
207 [(set_attr "type" "load,*")])
209 (define_insn "*zero_extend<mode>di2_internal2"
210 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
211 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
212 (const_int 0)))
213 (clobber (match_scratch:DI 2 "=r,r"))]
214 "TARGET_64BIT"
215 "@
216 rldicl. %2,%1,0,<dbits>
217 #"
218 [(set_attr "type" "compare")
219 (set_attr "length" "4,8")])
221 (define_split
222 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
223 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
224 (const_int 0)))
225 (clobber (match_scratch:DI 2 ""))]
226 "TARGET_POWERPC64 && reload_completed"
227 [(set (match_dup 2)
228 (zero_extend:DI (match_dup 1)))
229 (set (match_dup 0)
230 (compare:CC (match_dup 2)
231 (const_int 0)))]
232 "")
234 (define_insn "*zero_extend<mode>di2_internal3"
235 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
236 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
237 (const_int 0)))
238 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
239 (zero_extend:DI (match_dup 1)))]
240 "TARGET_64BIT"
241 "@
242 rldicl. %0,%1,0,<dbits>
243 #"
244 [(set_attr "type" "compare")
245 (set_attr "length" "4,8")])
247 (define_split
248 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
249 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
250 (const_int 0)))
251 (set (match_operand:DI 0 "gpc_reg_operand" "")
252 (zero_extend:DI (match_dup 1)))]
253 "TARGET_POWERPC64 && reload_completed"
254 [(set (match_dup 0)
255 (zero_extend:DI (match_dup 1)))
256 (set (match_dup 2)
257 (compare:CC (match_dup 0)
258 (const_int 0)))]
259 "")
261 (define_insn "extendqidi2"
262 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
263 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
264 "TARGET_POWERPC64"
265 "extsb %0,%1"
266 [(set_attr "type" "exts")])
268 (define_insn ""
269 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
270 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
271 (const_int 0)))
272 (clobber (match_scratch:DI 2 "=r,r"))]
273 "TARGET_64BIT"
274 "@
275 extsb. %2,%1
276 #"
277 [(set_attr "type" "compare")
278 (set_attr "length" "4,8")])
280 (define_split
281 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
282 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
283 (const_int 0)))
284 (clobber (match_scratch:DI 2 ""))]
285 "TARGET_POWERPC64 && reload_completed"
286 [(set (match_dup 2)
287 (sign_extend:DI (match_dup 1)))
288 (set (match_dup 0)
289 (compare:CC (match_dup 2)
290 (const_int 0)))]
291 "")
293 (define_insn ""
294 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
295 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
296 (const_int 0)))
297 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
298 (sign_extend:DI (match_dup 1)))]
299 "TARGET_64BIT"
300 "@
301 extsb. %0,%1
302 #"
303 [(set_attr "type" "compare")
304 (set_attr "length" "4,8")])
306 (define_split
307 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
308 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
309 (const_int 0)))
310 (set (match_operand:DI 0 "gpc_reg_operand" "")
311 (sign_extend:DI (match_dup 1)))]
312 "TARGET_POWERPC64 && reload_completed"
313 [(set (match_dup 0)
314 (sign_extend:DI (match_dup 1)))
315 (set (match_dup 2)
316 (compare:CC (match_dup 0)
317 (const_int 0)))]
318 "")
320 (define_expand "extendhidi2"
321 [(set (match_operand:DI 0 "gpc_reg_operand" "")
322 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
323 "TARGET_POWERPC64"
324 "")
326 (define_insn ""
327 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
328 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
329 "TARGET_POWERPC64"
330 "@
331 lha%U1%X1 %0,%1
332 extsh %0,%1"
333 [(set_attr "type" "load_ext,exts")])
335 (define_insn ""
336 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
337 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
338 (const_int 0)))
339 (clobber (match_scratch:DI 2 "=r,r"))]
340 "TARGET_64BIT"
341 "@
342 extsh. %2,%1
343 #"
344 [(set_attr "type" "compare")
345 (set_attr "length" "4,8")])
347 (define_split
348 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
349 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
350 (const_int 0)))
351 (clobber (match_scratch:DI 2 ""))]
352 "TARGET_POWERPC64 && reload_completed"
353 [(set (match_dup 2)
354 (sign_extend:DI (match_dup 1)))
355 (set (match_dup 0)
356 (compare:CC (match_dup 2)
357 (const_int 0)))]
358 "")
360 (define_insn ""
361 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
362 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
363 (const_int 0)))
364 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
365 (sign_extend:DI (match_dup 1)))]
366 "TARGET_64BIT"
367 "@
368 extsh. %0,%1
369 #"
370 [(set_attr "type" "compare")
371 (set_attr "length" "4,8")])
373 (define_split
374 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
375 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
376 (const_int 0)))
377 (set (match_operand:DI 0 "gpc_reg_operand" "")
378 (sign_extend:DI (match_dup 1)))]
379 "TARGET_POWERPC64 && reload_completed"
380 [(set (match_dup 0)
381 (sign_extend:DI (match_dup 1)))
382 (set (match_dup 2)
383 (compare:CC (match_dup 0)
384 (const_int 0)))]
385 "")
387 (define_expand "extendsidi2"
388 [(set (match_operand:DI 0 "gpc_reg_operand" "")
389 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
390 "TARGET_POWERPC64"
391 "")
393 (define_insn ""
394 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
395 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
396 "TARGET_POWERPC64"
397 "@
398 lwa%U1%X1 %0,%1
399 extsw %0,%1"
400 [(set_attr "type" "load_ext,exts")])
402 (define_insn ""
403 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
404 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
405 (const_int 0)))
406 (clobber (match_scratch:DI 2 "=r,r"))]
407 "TARGET_64BIT"
408 "@
409 extsw. %2,%1
410 #"
411 [(set_attr "type" "compare")
412 (set_attr "length" "4,8")])
414 (define_split
415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
416 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
417 (const_int 0)))
418 (clobber (match_scratch:DI 2 ""))]
419 "TARGET_POWERPC64 && reload_completed"
420 [(set (match_dup 2)
421 (sign_extend:DI (match_dup 1)))
422 (set (match_dup 0)
423 (compare:CC (match_dup 2)
424 (const_int 0)))]
425 "")
427 (define_insn ""
428 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
429 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
430 (const_int 0)))
431 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
432 (sign_extend:DI (match_dup 1)))]
433 "TARGET_64BIT"
434 "@
435 extsw. %0,%1
436 #"
437 [(set_attr "type" "compare")
438 (set_attr "length" "4,8")])
440 (define_split
441 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
442 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
443 (const_int 0)))
444 (set (match_operand:DI 0 "gpc_reg_operand" "")
445 (sign_extend:DI (match_dup 1)))]
446 "TARGET_POWERPC64 && reload_completed"
447 [(set (match_dup 0)
448 (sign_extend:DI (match_dup 1)))
449 (set (match_dup 2)
450 (compare:CC (match_dup 0)
451 (const_int 0)))]
452 "")
454 (define_expand "zero_extendqisi2"
455 [(set (match_operand:SI 0 "gpc_reg_operand" "")
456 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
457 ""
458 "")
460 (define_insn ""
461 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
462 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
463 ""
464 "@
465 lbz%U1%X1 %0,%1
466 {rlinm|rlwinm} %0,%1,0,0xff"
467 [(set_attr "type" "load,*")])
469 (define_insn ""
470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
471 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
472 (const_int 0)))
473 (clobber (match_scratch:SI 2 "=r,r"))]
474 ""
475 "@
476 {andil.|andi.} %2,%1,0xff
477 #"
478 [(set_attr "type" "compare")
479 (set_attr "length" "4,8")])
481 (define_split
482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
483 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
484 (const_int 0)))
485 (clobber (match_scratch:SI 2 ""))]
486 "reload_completed"
487 [(set (match_dup 2)
488 (zero_extend:SI (match_dup 1)))
489 (set (match_dup 0)
490 (compare:CC (match_dup 2)
491 (const_int 0)))]
492 "")
494 (define_insn ""
495 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
496 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
497 (const_int 0)))
498 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
499 (zero_extend:SI (match_dup 1)))]
500 ""
501 "@
502 {andil.|andi.} %0,%1,0xff
503 #"
504 [(set_attr "type" "compare")
505 (set_attr "length" "4,8")])
507 (define_split
508 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
509 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
510 (const_int 0)))
511 (set (match_operand:SI 0 "gpc_reg_operand" "")
512 (zero_extend:SI (match_dup 1)))]
513 "reload_completed"
514 [(set (match_dup 0)
515 (zero_extend:SI (match_dup 1)))
516 (set (match_dup 2)
517 (compare:CC (match_dup 0)
518 (const_int 0)))]
519 "")
521 (define_expand "extendqisi2"
522 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
523 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
524 ""
525 "
526 {
527 if (TARGET_POWERPC)
528 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
529 else if (TARGET_POWER)
530 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
531 else
532 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
533 DONE;
534 }")
536 (define_insn "extendqisi2_ppc"
537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
538 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
539 "TARGET_POWERPC"
540 "extsb %0,%1"
541 [(set_attr "type" "exts")])
543 (define_insn ""
544 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
545 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
546 (const_int 0)))
547 (clobber (match_scratch:SI 2 "=r,r"))]
548 "TARGET_POWERPC"
549 "@
550 extsb. %2,%1
551 #"
552 [(set_attr "type" "compare")
553 (set_attr "length" "4,8")])
555 (define_split
556 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
557 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
558 (const_int 0)))
559 (clobber (match_scratch:SI 2 ""))]
560 "TARGET_POWERPC && reload_completed"
561 [(set (match_dup 2)
562 (sign_extend:SI (match_dup 1)))
563 (set (match_dup 0)
564 (compare:CC (match_dup 2)
565 (const_int 0)))]
566 "")
568 (define_insn ""
569 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
570 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
571 (const_int 0)))
572 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
573 (sign_extend:SI (match_dup 1)))]
574 "TARGET_POWERPC"
575 "@
576 extsb. %0,%1
577 #"
578 [(set_attr "type" "compare")
579 (set_attr "length" "4,8")])
581 (define_split
582 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
583 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
584 (const_int 0)))
585 (set (match_operand:SI 0 "gpc_reg_operand" "")
586 (sign_extend:SI (match_dup 1)))]
587 "TARGET_POWERPC && reload_completed"
588 [(set (match_dup 0)
589 (sign_extend:SI (match_dup 1)))
590 (set (match_dup 2)
591 (compare:CC (match_dup 0)
592 (const_int 0)))]
593 "")
595 (define_expand "extendqisi2_power"
596 [(parallel [(set (match_dup 2)
597 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
598 (const_int 24)))
599 (clobber (scratch:SI))])
600 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
601 (ashiftrt:SI (match_dup 2)
602 (const_int 24)))
603 (clobber (scratch:SI))])]
604 "TARGET_POWER"
605 "
606 { operands[1] = gen_lowpart (SImode, operands[1]);
607 operands[2] = gen_reg_rtx (SImode); }")
609 (define_expand "extendqisi2_no_power"
610 [(set (match_dup 2)
611 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
612 (const_int 24)))
613 (set (match_operand:SI 0 "gpc_reg_operand" "")
614 (ashiftrt:SI (match_dup 2)
615 (const_int 24)))]
616 "! TARGET_POWER && ! TARGET_POWERPC"
617 "
618 { operands[1] = gen_lowpart (SImode, operands[1]);
619 operands[2] = gen_reg_rtx (SImode); }")
621 (define_expand "zero_extendqihi2"
622 [(set (match_operand:HI 0 "gpc_reg_operand" "")
623 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
624 ""
625 "")
627 (define_insn ""
628 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
629 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
630 ""
631 "@
632 lbz%U1%X1 %0,%1
633 {rlinm|rlwinm} %0,%1,0,0xff"
634 [(set_attr "type" "load,*")])
636 (define_insn ""
637 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
638 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
639 (const_int 0)))
640 (clobber (match_scratch:HI 2 "=r,r"))]
641 ""
642 "@
643 {andil.|andi.} %2,%1,0xff
644 #"
645 [(set_attr "type" "compare")
646 (set_attr "length" "4,8")])
648 (define_split
649 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
650 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
651 (const_int 0)))
652 (clobber (match_scratch:HI 2 ""))]
653 "reload_completed"
654 [(set (match_dup 2)
655 (zero_extend:HI (match_dup 1)))
656 (set (match_dup 0)
657 (compare:CC (match_dup 2)
658 (const_int 0)))]
659 "")
661 (define_insn ""
662 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
663 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
664 (const_int 0)))
665 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
666 (zero_extend:HI (match_dup 1)))]
667 ""
668 "@
669 {andil.|andi.} %0,%1,0xff
670 #"
671 [(set_attr "type" "compare")
672 (set_attr "length" "4,8")])
674 (define_split
675 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
676 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
677 (const_int 0)))
678 (set (match_operand:HI 0 "gpc_reg_operand" "")
679 (zero_extend:HI (match_dup 1)))]
680 "reload_completed"
681 [(set (match_dup 0)
682 (zero_extend:HI (match_dup 1)))
683 (set (match_dup 2)
684 (compare:CC (match_dup 0)
685 (const_int 0)))]
686 "")
688 (define_expand "extendqihi2"
689 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
690 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
691 ""
692 "
693 {
694 if (TARGET_POWERPC)
695 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
696 else if (TARGET_POWER)
697 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
698 else
699 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
700 DONE;
701 }")
703 (define_insn "extendqihi2_ppc"
704 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
705 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
706 "TARGET_POWERPC"
707 "extsb %0,%1"
708 [(set_attr "type" "exts")])
710 (define_insn ""
711 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
712 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
713 (const_int 0)))
714 (clobber (match_scratch:HI 2 "=r,r"))]
715 "TARGET_POWERPC"
716 "@
717 extsb. %2,%1
718 #"
719 [(set_attr "type" "compare")
720 (set_attr "length" "4,8")])
722 (define_split
723 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
724 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
725 (const_int 0)))
726 (clobber (match_scratch:HI 2 ""))]
727 "TARGET_POWERPC && reload_completed"
728 [(set (match_dup 2)
729 (sign_extend:HI (match_dup 1)))
730 (set (match_dup 0)
731 (compare:CC (match_dup 2)
732 (const_int 0)))]
733 "")
735 (define_insn ""
736 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
737 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
738 (const_int 0)))
739 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
740 (sign_extend:HI (match_dup 1)))]
741 "TARGET_POWERPC"
742 "@
743 extsb. %0,%1
744 #"
745 [(set_attr "type" "compare")
746 (set_attr "length" "4,8")])
748 (define_split
749 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
750 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
751 (const_int 0)))
752 (set (match_operand:HI 0 "gpc_reg_operand" "")
753 (sign_extend:HI (match_dup 1)))]
754 "TARGET_POWERPC && reload_completed"
755 [(set (match_dup 0)
756 (sign_extend:HI (match_dup 1)))
757 (set (match_dup 2)
758 (compare:CC (match_dup 0)
759 (const_int 0)))]
760 "")
762 (define_expand "extendqihi2_power"
763 [(parallel [(set (match_dup 2)
764 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
765 (const_int 24)))
766 (clobber (scratch:SI))])
767 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
768 (ashiftrt:SI (match_dup 2)
769 (const_int 24)))
770 (clobber (scratch:SI))])]
771 "TARGET_POWER"
772 "
773 { operands[0] = gen_lowpart (SImode, operands[0]);
774 operands[1] = gen_lowpart (SImode, operands[1]);
775 operands[2] = gen_reg_rtx (SImode); }")
777 (define_expand "extendqihi2_no_power"
778 [(set (match_dup 2)
779 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
780 (const_int 24)))
781 (set (match_operand:HI 0 "gpc_reg_operand" "")
782 (ashiftrt:SI (match_dup 2)
783 (const_int 24)))]
784 "! TARGET_POWER && ! TARGET_POWERPC"
785 "
786 { operands[0] = gen_lowpart (SImode, operands[0]);
787 operands[1] = gen_lowpart (SImode, operands[1]);
788 operands[2] = gen_reg_rtx (SImode); }")
790 (define_expand "zero_extendhisi2"
791 [(set (match_operand:SI 0 "gpc_reg_operand" "")
792 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
793 ""
794 "")
796 (define_insn ""
797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
798 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
799 ""
800 "@
801 lhz%U1%X1 %0,%1
802 {rlinm|rlwinm} %0,%1,0,0xffff"
803 [(set_attr "type" "load,*")])
805 (define_insn ""
806 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
807 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
808 (const_int 0)))
809 (clobber (match_scratch:SI 2 "=r,r"))]
810 ""
811 "@
812 {andil.|andi.} %2,%1,0xffff
813 #"
814 [(set_attr "type" "compare")
815 (set_attr "length" "4,8")])
817 (define_split
818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
819 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
820 (const_int 0)))
821 (clobber (match_scratch:SI 2 ""))]
822 "reload_completed"
823 [(set (match_dup 2)
824 (zero_extend:SI (match_dup 1)))
825 (set (match_dup 0)
826 (compare:CC (match_dup 2)
827 (const_int 0)))]
828 "")
830 (define_insn ""
831 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
832 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
833 (const_int 0)))
834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
835 (zero_extend:SI (match_dup 1)))]
836 ""
837 "@
838 {andil.|andi.} %0,%1,0xffff
839 #"
840 [(set_attr "type" "compare")
841 (set_attr "length" "4,8")])
843 (define_split
844 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
845 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
846 (const_int 0)))
847 (set (match_operand:SI 0 "gpc_reg_operand" "")
848 (zero_extend:SI (match_dup 1)))]
849 "reload_completed"
850 [(set (match_dup 0)
851 (zero_extend:SI (match_dup 1)))
852 (set (match_dup 2)
853 (compare:CC (match_dup 0)
854 (const_int 0)))]
855 "")
857 (define_expand "extendhisi2"
858 [(set (match_operand:SI 0 "gpc_reg_operand" "")
859 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
860 ""
861 "")
863 (define_insn ""
864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
865 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
866 ""
867 "@
868 lha%U1%X1 %0,%1
869 {exts|extsh} %0,%1"
870 [(set_attr "type" "load_ext,exts")])
872 (define_insn ""
873 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
874 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
875 (const_int 0)))
876 (clobber (match_scratch:SI 2 "=r,r"))]
877 ""
878 "@
879 {exts.|extsh.} %2,%1
880 #"
881 [(set_attr "type" "compare")
882 (set_attr "length" "4,8")])
884 (define_split
885 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
886 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
887 (const_int 0)))
888 (clobber (match_scratch:SI 2 ""))]
889 "reload_completed"
890 [(set (match_dup 2)
891 (sign_extend:SI (match_dup 1)))
892 (set (match_dup 0)
893 (compare:CC (match_dup 2)
894 (const_int 0)))]
895 "")
897 (define_insn ""
898 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
899 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
900 (const_int 0)))
901 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
902 (sign_extend:SI (match_dup 1)))]
903 ""
904 "@
905 {exts.|extsh.} %0,%1
906 #"
907 [(set_attr "type" "compare")
908 (set_attr "length" "4,8")])
909 \f
910 ;; IBM 405 and 440 half-word multiplication operations.
912 (define_insn "*macchwc"
913 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
914 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
915 (match_operand:SI 2 "gpc_reg_operand" "r")
916 (const_int 16))
917 (sign_extend:SI
918 (match_operand:HI 1 "gpc_reg_operand" "r")))
919 (match_operand:SI 4 "gpc_reg_operand" "0"))
920 (const_int 0)))
921 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
922 (plus:SI (mult:SI (ashiftrt:SI
923 (match_dup 2)
924 (const_int 16))
925 (sign_extend:SI
926 (match_dup 1)))
927 (match_dup 4)))]
928 "TARGET_MULHW"
929 "macchw. %0, %1, %2"
930 [(set_attr "type" "imul3")])
932 (define_insn "*macchw"
933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
934 (plus:SI (mult:SI (ashiftrt:SI
935 (match_operand:SI 2 "gpc_reg_operand" "r")
936 (const_int 16))
937 (sign_extend:SI
938 (match_operand:HI 1 "gpc_reg_operand" "r")))
939 (match_operand:SI 3 "gpc_reg_operand" "0")))]
940 "TARGET_MULHW"
941 "macchw %0, %1, %2"
942 [(set_attr "type" "imul3")])
944 (define_insn "*macchwuc"
945 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
946 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
947 (match_operand:SI 2 "gpc_reg_operand" "r")
948 (const_int 16))
949 (zero_extend:SI
950 (match_operand:HI 1 "gpc_reg_operand" "r")))
951 (match_operand:SI 4 "gpc_reg_operand" "0"))
952 (const_int 0)))
953 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
954 (plus:SI (mult:SI (lshiftrt:SI
955 (match_dup 2)
956 (const_int 16))
957 (zero_extend:SI
958 (match_dup 1)))
959 (match_dup 4)))]
960 "TARGET_MULHW"
961 "macchwu. %0, %1, %2"
962 [(set_attr "type" "imul3")])
964 (define_insn "*macchwu"
965 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
966 (plus:SI (mult:SI (lshiftrt:SI
967 (match_operand:SI 2 "gpc_reg_operand" "r")
968 (const_int 16))
969 (zero_extend:SI
970 (match_operand:HI 1 "gpc_reg_operand" "r")))
971 (match_operand:SI 3 "gpc_reg_operand" "0")))]
972 "TARGET_MULHW"
973 "macchwu %0, %1, %2"
974 [(set_attr "type" "imul3")])
976 (define_insn "*machhwc"
977 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
978 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
979 (match_operand:SI 1 "gpc_reg_operand" "%r")
980 (const_int 16))
981 (ashiftrt:SI
982 (match_operand:SI 2 "gpc_reg_operand" "r")
983 (const_int 16)))
984 (match_operand:SI 4 "gpc_reg_operand" "0"))
985 (const_int 0)))
986 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
987 (plus:SI (mult:SI (ashiftrt:SI
988 (match_dup 1)
989 (const_int 16))
990 (ashiftrt:SI
991 (match_dup 2)
992 (const_int 16)))
993 (match_dup 4)))]
994 "TARGET_MULHW"
995 "machhw. %0, %1, %2"
996 [(set_attr "type" "imul3")])
998 (define_insn "*machhw"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1000 (plus:SI (mult:SI (ashiftrt:SI
1001 (match_operand:SI 1 "gpc_reg_operand" "%r")
1002 (const_int 16))
1003 (ashiftrt:SI
1004 (match_operand:SI 2 "gpc_reg_operand" "r")
1005 (const_int 16)))
1006 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1007 "TARGET_MULHW"
1008 "machhw %0, %1, %2"
1009 [(set_attr "type" "imul3")])
1011 (define_insn "*machhwuc"
1012 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1013 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1014 (match_operand:SI 1 "gpc_reg_operand" "%r")
1015 (const_int 16))
1016 (lshiftrt:SI
1017 (match_operand:SI 2 "gpc_reg_operand" "r")
1018 (const_int 16)))
1019 (match_operand:SI 4 "gpc_reg_operand" "0"))
1020 (const_int 0)))
1021 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1022 (plus:SI (mult:SI (lshiftrt:SI
1023 (match_dup 1)
1024 (const_int 16))
1025 (lshiftrt:SI
1026 (match_dup 2)
1027 (const_int 16)))
1028 (match_dup 4)))]
1029 "TARGET_MULHW"
1030 "machhwu. %0, %1, %2"
1031 [(set_attr "type" "imul3")])
1033 (define_insn "*machhwu"
1034 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1035 (plus:SI (mult:SI (lshiftrt:SI
1036 (match_operand:SI 1 "gpc_reg_operand" "%r")
1037 (const_int 16))
1038 (lshiftrt:SI
1039 (match_operand:SI 2 "gpc_reg_operand" "r")
1040 (const_int 16)))
1041 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1042 "TARGET_MULHW"
1043 "machhwu %0, %1, %2"
1044 [(set_attr "type" "imul3")])
1046 (define_insn "*maclhwc"
1047 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1048 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1049 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1050 (sign_extend:SI
1051 (match_operand:HI 2 "gpc_reg_operand" "r")))
1052 (match_operand:SI 4 "gpc_reg_operand" "0"))
1053 (const_int 0)))
1054 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1055 (plus:SI (mult:SI (sign_extend:SI
1056 (match_dup 1))
1057 (sign_extend:SI
1058 (match_dup 2)))
1059 (match_dup 4)))]
1060 "TARGET_MULHW"
1061 "maclhw. %0, %1, %2"
1062 [(set_attr "type" "imul3")])
1064 (define_insn "*maclhw"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1066 (plus:SI (mult:SI (sign_extend:SI
1067 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1068 (sign_extend:SI
1069 (match_operand:HI 2 "gpc_reg_operand" "r")))
1070 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1071 "TARGET_MULHW"
1072 "maclhw %0, %1, %2"
1073 [(set_attr "type" "imul3")])
1075 (define_insn "*maclhwuc"
1076 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1077 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1078 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1079 (zero_extend:SI
1080 (match_operand:HI 2 "gpc_reg_operand" "r")))
1081 (match_operand:SI 4 "gpc_reg_operand" "0"))
1082 (const_int 0)))
1083 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1084 (plus:SI (mult:SI (zero_extend:SI
1085 (match_dup 1))
1086 (zero_extend:SI
1087 (match_dup 2)))
1088 (match_dup 4)))]
1089 "TARGET_MULHW"
1090 "maclhwu. %0, %1, %2"
1091 [(set_attr "type" "imul3")])
1093 (define_insn "*maclhwu"
1094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1095 (plus:SI (mult:SI (zero_extend:SI
1096 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1097 (zero_extend:SI
1098 (match_operand:HI 2 "gpc_reg_operand" "r")))
1099 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1100 "TARGET_MULHW"
1101 "maclhwu %0, %1, %2"
1102 [(set_attr "type" "imul3")])
1104 (define_insn "*nmacchwc"
1105 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1106 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1107 (mult:SI (ashiftrt:SI
1108 (match_operand:SI 2 "gpc_reg_operand" "r")
1109 (const_int 16))
1110 (sign_extend:SI
1111 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1112 (const_int 0)))
1113 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1114 (minus:SI (match_dup 4)
1115 (mult:SI (ashiftrt:SI
1116 (match_dup 2)
1117 (const_int 16))
1118 (sign_extend:SI
1119 (match_dup 1)))))]
1120 "TARGET_MULHW"
1121 "nmacchw. %0, %1, %2"
1122 [(set_attr "type" "imul3")])
1124 (define_insn "*nmacchw"
1125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1126 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1127 (mult:SI (ashiftrt:SI
1128 (match_operand:SI 2 "gpc_reg_operand" "r")
1129 (const_int 16))
1130 (sign_extend:SI
1131 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1132 "TARGET_MULHW"
1133 "nmacchw %0, %1, %2"
1134 [(set_attr "type" "imul3")])
1136 (define_insn "*nmachhwc"
1137 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1138 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1139 (mult:SI (ashiftrt:SI
1140 (match_operand:SI 1 "gpc_reg_operand" "%r")
1141 (const_int 16))
1142 (ashiftrt:SI
1143 (match_operand:SI 2 "gpc_reg_operand" "r")
1144 (const_int 16))))
1145 (const_int 0)))
1146 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1147 (minus:SI (match_dup 4)
1148 (mult:SI (ashiftrt:SI
1149 (match_dup 1)
1150 (const_int 16))
1151 (ashiftrt:SI
1152 (match_dup 2)
1153 (const_int 16)))))]
1154 "TARGET_MULHW"
1155 "nmachhw. %0, %1, %2"
1156 [(set_attr "type" "imul3")])
1158 (define_insn "*nmachhw"
1159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1160 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1161 (mult:SI (ashiftrt:SI
1162 (match_operand:SI 1 "gpc_reg_operand" "%r")
1163 (const_int 16))
1164 (ashiftrt:SI
1165 (match_operand:SI 2 "gpc_reg_operand" "r")
1166 (const_int 16)))))]
1167 "TARGET_MULHW"
1168 "nmachhw %0, %1, %2"
1169 [(set_attr "type" "imul3")])
1171 (define_insn "*nmaclhwc"
1172 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1173 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1174 (mult:SI (sign_extend:SI
1175 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1176 (sign_extend:SI
1177 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1178 (const_int 0)))
1179 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1180 (minus:SI (match_dup 4)
1181 (mult:SI (sign_extend:SI
1182 (match_dup 1))
1183 (sign_extend:SI
1184 (match_dup 2)))))]
1185 "TARGET_MULHW"
1186 "nmaclhw. %0, %1, %2"
1187 [(set_attr "type" "imul3")])
1189 (define_insn "*nmaclhw"
1190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1192 (mult:SI (sign_extend:SI
1193 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1194 (sign_extend:SI
1195 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1196 "TARGET_MULHW"
1197 "nmaclhw %0, %1, %2"
1198 [(set_attr "type" "imul3")])
1200 (define_insn "*mulchwc"
1201 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1202 (compare:CC (mult:SI (ashiftrt:SI
1203 (match_operand:SI 2 "gpc_reg_operand" "r")
1204 (const_int 16))
1205 (sign_extend:SI
1206 (match_operand:HI 1 "gpc_reg_operand" "r")))
1207 (const_int 0)))
1208 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1209 (mult:SI (ashiftrt:SI
1210 (match_dup 2)
1211 (const_int 16))
1212 (sign_extend:SI
1213 (match_dup 1))))]
1214 "TARGET_MULHW"
1215 "mulchw. %0, %1, %2"
1216 [(set_attr "type" "imul3")])
1218 (define_insn "*mulchw"
1219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1220 (mult:SI (ashiftrt:SI
1221 (match_operand:SI 2 "gpc_reg_operand" "r")
1222 (const_int 16))
1223 (sign_extend:SI
1224 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1225 "TARGET_MULHW"
1226 "mulchw %0, %1, %2"
1227 [(set_attr "type" "imul3")])
1229 (define_insn "*mulchwuc"
1230 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1231 (compare:CC (mult:SI (lshiftrt:SI
1232 (match_operand:SI 2 "gpc_reg_operand" "r")
1233 (const_int 16))
1234 (zero_extend:SI
1235 (match_operand:HI 1 "gpc_reg_operand" "r")))
1236 (const_int 0)))
1237 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1238 (mult:SI (lshiftrt:SI
1239 (match_dup 2)
1240 (const_int 16))
1241 (zero_extend:SI
1242 (match_dup 1))))]
1243 "TARGET_MULHW"
1244 "mulchwu. %0, %1, %2"
1245 [(set_attr "type" "imul3")])
1247 (define_insn "*mulchwu"
1248 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1249 (mult:SI (lshiftrt:SI
1250 (match_operand:SI 2 "gpc_reg_operand" "r")
1251 (const_int 16))
1252 (zero_extend:SI
1253 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1254 "TARGET_MULHW"
1255 "mulchwu %0, %1, %2"
1256 [(set_attr "type" "imul3")])
1258 (define_insn "*mulhhwc"
1259 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1260 (compare:CC (mult:SI (ashiftrt:SI
1261 (match_operand:SI 1 "gpc_reg_operand" "%r")
1262 (const_int 16))
1263 (ashiftrt:SI
1264 (match_operand:SI 2 "gpc_reg_operand" "r")
1265 (const_int 16)))
1266 (const_int 0)))
1267 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1268 (mult:SI (ashiftrt:SI
1269 (match_dup 1)
1270 (const_int 16))
1271 (ashiftrt:SI
1272 (match_dup 2)
1273 (const_int 16))))]
1274 "TARGET_MULHW"
1275 "mulhhw. %0, %1, %2"
1276 [(set_attr "type" "imul3")])
1278 (define_insn "*mulhhw"
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1280 (mult:SI (ashiftrt:SI
1281 (match_operand:SI 1 "gpc_reg_operand" "%r")
1282 (const_int 16))
1283 (ashiftrt:SI
1284 (match_operand:SI 2 "gpc_reg_operand" "r")
1285 (const_int 16))))]
1286 "TARGET_MULHW"
1287 "mulhhw %0, %1, %2"
1288 [(set_attr "type" "imul3")])
1290 (define_insn "*mulhhwuc"
1291 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1292 (compare:CC (mult:SI (lshiftrt:SI
1293 (match_operand:SI 1 "gpc_reg_operand" "%r")
1294 (const_int 16))
1295 (lshiftrt:SI
1296 (match_operand:SI 2 "gpc_reg_operand" "r")
1297 (const_int 16)))
1298 (const_int 0)))
1299 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1300 (mult:SI (lshiftrt:SI
1301 (match_dup 1)
1302 (const_int 16))
1303 (lshiftrt:SI
1304 (match_dup 2)
1305 (const_int 16))))]
1306 "TARGET_MULHW"
1307 "mulhhwu. %0, %1, %2"
1308 [(set_attr "type" "imul3")])
1310 (define_insn "*mulhhwu"
1311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1312 (mult:SI (lshiftrt:SI
1313 (match_operand:SI 1 "gpc_reg_operand" "%r")
1314 (const_int 16))
1315 (lshiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16))))]
1318 "TARGET_MULHW"
1319 "mulhhwu %0, %1, %2"
1320 [(set_attr "type" "imul3")])
1322 (define_insn "*mullhwc"
1323 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1324 (compare:CC (mult:SI (sign_extend:SI
1325 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1326 (sign_extend:SI
1327 (match_operand:HI 2 "gpc_reg_operand" "r")))
1328 (const_int 0)))
1329 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1330 (mult:SI (sign_extend:SI
1331 (match_dup 1))
1332 (sign_extend:SI
1333 (match_dup 2))))]
1334 "TARGET_MULHW"
1335 "mullhw. %0, %1, %2"
1336 [(set_attr "type" "imul3")])
1338 (define_insn "*mullhw"
1339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1340 (mult:SI (sign_extend:SI
1341 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1342 (sign_extend:SI
1343 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1344 "TARGET_MULHW"
1345 "mullhw %0, %1, %2"
1346 [(set_attr "type" "imul3")])
1348 (define_insn "*mullhwuc"
1349 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1350 (compare:CC (mult:SI (zero_extend:SI
1351 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1352 (zero_extend:SI
1353 (match_operand:HI 2 "gpc_reg_operand" "r")))
1354 (const_int 0)))
1355 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 (mult:SI (zero_extend:SI
1357 (match_dup 1))
1358 (zero_extend:SI
1359 (match_dup 2))))]
1360 "TARGET_MULHW"
1361 "mullhwu. %0, %1, %2"
1362 [(set_attr "type" "imul3")])
1364 (define_insn "*mullhwu"
1365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1366 (mult:SI (zero_extend:SI
1367 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1368 (zero_extend:SI
1369 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1370 "TARGET_MULHW"
1371 "mullhwu %0, %1, %2"
1372 [(set_attr "type" "imul3")])
1373 \f
1374 ;; IBM 405 and 440 string-search dlmzb instruction support.
1375 (define_insn "dlmzb"
1376 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1377 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1378 (match_operand:SI 2 "gpc_reg_operand" "r")]
1379 UNSPEC_DLMZB_CR))
1380 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1381 (unspec:SI [(match_dup 1)
1382 (match_dup 2)]
1383 UNSPEC_DLMZB))]
1384 "TARGET_DLMZB"
1385 "dlmzb. %0, %1, %2")
1387 (define_expand "strlensi"
1388 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1389 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1390 (match_operand:QI 2 "const_int_operand" "")
1391 (match_operand 3 "const_int_operand" "")]
1392 UNSPEC_DLMZB_STRLEN))
1393 (clobber (match_scratch:CC 4 "=x"))]
1394 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1395 {
1396 rtx result = operands[0];
1397 rtx src = operands[1];
1398 rtx search_char = operands[2];
1399 rtx align = operands[3];
1400 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1401 rtx loop_label, end_label, mem, cr0, cond;
1402 if (search_char != const0_rtx
1403 || GET_CODE (align) != CONST_INT
1404 || INTVAL (align) < 8)
1405 FAIL;
1406 word1 = gen_reg_rtx (SImode);
1407 word2 = gen_reg_rtx (SImode);
1408 scratch_dlmzb = gen_reg_rtx (SImode);
1409 scratch_string = gen_reg_rtx (Pmode);
1410 loop_label = gen_label_rtx ();
1411 end_label = gen_label_rtx ();
1412 addr = force_reg (Pmode, XEXP (src, 0));
1413 emit_move_insn (scratch_string, addr);
1414 emit_label (loop_label);
1415 mem = change_address (src, SImode, scratch_string);
1416 emit_move_insn (word1, mem);
1417 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1418 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1419 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1420 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1421 emit_jump_insn (gen_rtx_SET (VOIDmode,
1422 pc_rtx,
1423 gen_rtx_IF_THEN_ELSE (VOIDmode,
1424 cond,
1425 gen_rtx_LABEL_REF
1426 (VOIDmode,
1427 end_label),
1428 pc_rtx)));
1429 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1430 emit_jump_insn (gen_rtx_SET (VOIDmode,
1431 pc_rtx,
1432 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1433 emit_barrier ();
1434 emit_label (end_label);
1435 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1436 emit_insn (gen_subsi3 (result, scratch_string, addr));
1437 emit_insn (gen_subsi3 (result, result, const1_rtx));
1438 DONE;
1439 })
1440 \f
1441 (define_split
1442 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1443 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1444 (const_int 0)))
1445 (set (match_operand:SI 0 "gpc_reg_operand" "")
1446 (sign_extend:SI (match_dup 1)))]
1447 "reload_completed"
1448 [(set (match_dup 0)
1449 (sign_extend:SI (match_dup 1)))
1450 (set (match_dup 2)
1451 (compare:CC (match_dup 0)
1452 (const_int 0)))]
1453 "")
1455 ;; Fixed-point arithmetic insns.
1457 (define_expand "add<mode>3"
1458 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1459 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1460 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1461 ""
1462 {
1463 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1464 {
1465 if (non_short_cint_operand (operands[2], DImode))
1466 FAIL;
1467 }
1468 else if (GET_CODE (operands[2]) == CONST_INT
1469 && ! add_operand (operands[2], <MODE>mode))
1470 {
1471 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1472 ? operands[0] : gen_reg_rtx (<MODE>mode));
1474 HOST_WIDE_INT val = INTVAL (operands[2]);
1475 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1476 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1478 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1479 FAIL;
1481 /* The ordering here is important for the prolog expander.
1482 When space is allocated from the stack, adding 'low' first may
1483 produce a temporary deallocation (which would be bad). */
1484 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1485 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1486 DONE;
1487 }
1488 })
1490 ;; Discourage ai/addic because of carry but provide it in an alternative
1491 ;; allowing register zero as source.
1492 (define_insn "*add<mode>3_internal1"
1493 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1494 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1495 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1496 ""
1497 "@
1498 {cax|add} %0,%1,%2
1499 {cal %0,%2(%1)|addi %0,%1,%2}
1500 {ai|addic} %0,%1,%2
1501 {cau|addis} %0,%1,%v2"
1502 [(set_attr "length" "4,4,4,4")])
1504 (define_insn "addsi3_high"
1505 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1506 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1507 (high:SI (match_operand 2 "" ""))))]
1508 "TARGET_MACHO && !TARGET_64BIT"
1509 "{cau|addis} %0,%1,ha16(%2)"
1510 [(set_attr "length" "4")])
1512 (define_insn "*add<mode>3_internal2"
1513 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1514 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1515 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1516 (const_int 0)))
1517 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1518 ""
1519 "@
1520 {cax.|add.} %3,%1,%2
1521 {ai.|addic.} %3,%1,%2
1522 #
1523 #"
1524 [(set_attr "type" "fast_compare,compare,compare,compare")
1525 (set_attr "length" "4,4,8,8")])
1527 (define_split
1528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1529 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1530 (match_operand:GPR 2 "reg_or_short_operand" ""))
1531 (const_int 0)))
1532 (clobber (match_scratch:GPR 3 ""))]
1533 "reload_completed"
1534 [(set (match_dup 3)
1535 (plus:GPR (match_dup 1)
1536 (match_dup 2)))
1537 (set (match_dup 0)
1538 (compare:CC (match_dup 3)
1539 (const_int 0)))]
1540 "")
1542 (define_insn "*add<mode>3_internal3"
1543 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1544 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1545 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1546 (const_int 0)))
1547 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1548 (plus:P (match_dup 1)
1549 (match_dup 2)))]
1550 ""
1551 "@
1552 {cax.|add.} %0,%1,%2
1553 {ai.|addic.} %0,%1,%2
1554 #
1555 #"
1556 [(set_attr "type" "fast_compare,compare,compare,compare")
1557 (set_attr "length" "4,4,8,8")])
1559 (define_split
1560 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1561 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1562 (match_operand:P 2 "reg_or_short_operand" ""))
1563 (const_int 0)))
1564 (set (match_operand:P 0 "gpc_reg_operand" "")
1565 (plus:P (match_dup 1) (match_dup 2)))]
1566 "reload_completed"
1567 [(set (match_dup 0)
1568 (plus:P (match_dup 1)
1569 (match_dup 2)))
1570 (set (match_dup 3)
1571 (compare:CC (match_dup 0)
1572 (const_int 0)))]
1573 "")
1575 ;; Split an add that we can't do in one insn into two insns, each of which
1576 ;; does one 16-bit part. This is used by combine. Note that the low-order
1577 ;; add should be last in case the result gets used in an address.
1579 (define_split
1580 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1581 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1582 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1583 ""
1584 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1585 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1586 {
1587 HOST_WIDE_INT val = INTVAL (operands[2]);
1588 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1589 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1591 operands[4] = GEN_INT (low);
1592 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1593 operands[3] = GEN_INT (rest);
1594 else if (! no_new_pseudos)
1595 {
1596 operands[3] = gen_reg_rtx (DImode);
1597 emit_move_insn (operands[3], operands[2]);
1598 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1599 DONE;
1600 }
1601 else
1602 FAIL;
1603 })
1605 (define_insn "one_cmpl<mode>2"
1606 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1607 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1608 ""
1609 "nor %0,%1,%1")
1611 (define_insn ""
1612 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1613 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1614 (const_int 0)))
1615 (clobber (match_scratch:P 2 "=r,r"))]
1616 ""
1617 "@
1618 nor. %2,%1,%1
1619 #"
1620 [(set_attr "type" "compare")
1621 (set_attr "length" "4,8")])
1623 (define_split
1624 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1625 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1626 (const_int 0)))
1627 (clobber (match_scratch:P 2 ""))]
1628 "reload_completed"
1629 [(set (match_dup 2)
1630 (not:P (match_dup 1)))
1631 (set (match_dup 0)
1632 (compare:CC (match_dup 2)
1633 (const_int 0)))]
1634 "")
1636 (define_insn ""
1637 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1638 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1639 (const_int 0)))
1640 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1641 (not:P (match_dup 1)))]
1642 ""
1643 "@
1644 nor. %0,%1,%1
1645 #"
1646 [(set_attr "type" "compare")
1647 (set_attr "length" "4,8")])
1649 (define_split
1650 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1651 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1652 (const_int 0)))
1653 (set (match_operand:P 0 "gpc_reg_operand" "")
1654 (not:P (match_dup 1)))]
1655 "reload_completed"
1656 [(set (match_dup 0)
1657 (not:P (match_dup 1)))
1658 (set (match_dup 2)
1659 (compare:CC (match_dup 0)
1660 (const_int 0)))]
1661 "")
1663 (define_insn ""
1664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1665 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1666 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1667 "! TARGET_POWERPC"
1668 "{sf%I1|subf%I1c} %0,%2,%1")
1670 (define_insn ""
1671 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1672 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1673 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1674 "TARGET_POWERPC"
1675 "@
1676 subf %0,%2,%1
1677 subfic %0,%2,%1")
1679 (define_insn ""
1680 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1681 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1682 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1683 (const_int 0)))
1684 (clobber (match_scratch:SI 3 "=r,r"))]
1685 "! TARGET_POWERPC"
1686 "@
1687 {sf.|subfc.} %3,%2,%1
1688 #"
1689 [(set_attr "type" "compare")
1690 (set_attr "length" "4,8")])
1692 (define_insn ""
1693 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1694 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1695 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1696 (const_int 0)))
1697 (clobber (match_scratch:P 3 "=r,r"))]
1698 "TARGET_POWERPC"
1699 "@
1700 subf. %3,%2,%1
1701 #"
1702 [(set_attr "type" "fast_compare")
1703 (set_attr "length" "4,8")])
1705 (define_split
1706 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1707 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1708 (match_operand:P 2 "gpc_reg_operand" ""))
1709 (const_int 0)))
1710 (clobber (match_scratch:P 3 ""))]
1711 "reload_completed"
1712 [(set (match_dup 3)
1713 (minus:P (match_dup 1)
1714 (match_dup 2)))
1715 (set (match_dup 0)
1716 (compare:CC (match_dup 3)
1717 (const_int 0)))]
1718 "")
1720 (define_insn ""
1721 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1722 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1723 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1724 (const_int 0)))
1725 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1726 (minus:SI (match_dup 1) (match_dup 2)))]
1727 "! TARGET_POWERPC"
1728 "@
1729 {sf.|subfc.} %0,%2,%1
1730 #"
1731 [(set_attr "type" "compare")
1732 (set_attr "length" "4,8")])
1734 (define_insn ""
1735 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1736 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1737 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1738 (const_int 0)))
1739 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1740 (minus:P (match_dup 1)
1741 (match_dup 2)))]
1742 "TARGET_POWERPC"
1743 "@
1744 subf. %0,%2,%1
1745 #"
1746 [(set_attr "type" "fast_compare")
1747 (set_attr "length" "4,8")])
1749 (define_split
1750 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1751 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1752 (match_operand:P 2 "gpc_reg_operand" ""))
1753 (const_int 0)))
1754 (set (match_operand:P 0 "gpc_reg_operand" "")
1755 (minus:P (match_dup 1)
1756 (match_dup 2)))]
1757 "reload_completed"
1758 [(set (match_dup 0)
1759 (minus:P (match_dup 1)
1760 (match_dup 2)))
1761 (set (match_dup 3)
1762 (compare:CC (match_dup 0)
1763 (const_int 0)))]
1764 "")
1766 (define_expand "sub<mode>3"
1767 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1768 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1769 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1770 ""
1771 "
1772 {
1773 if (GET_CODE (operands[2]) == CONST_INT)
1774 {
1775 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1776 negate_rtx (<MODE>mode, operands[2])));
1777 DONE;
1778 }
1779 }")
1781 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1782 ;; instruction and some auxiliary computations. Then we just have a single
1783 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1784 ;; combine.
1786 (define_expand "sminsi3"
1787 [(set (match_dup 3)
1788 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1789 (match_operand:SI 2 "reg_or_short_operand" ""))
1790 (const_int 0)
1791 (minus:SI (match_dup 2) (match_dup 1))))
1792 (set (match_operand:SI 0 "gpc_reg_operand" "")
1793 (minus:SI (match_dup 2) (match_dup 3)))]
1794 "TARGET_POWER || TARGET_ISEL"
1795 "
1796 {
1797 if (TARGET_ISEL)
1798 {
1799 operands[2] = force_reg (SImode, operands[2]);
1800 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1801 DONE;
1802 }
1804 operands[3] = gen_reg_rtx (SImode);
1805 }")
1807 (define_split
1808 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1809 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1810 (match_operand:SI 2 "reg_or_short_operand" "")))
1811 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1812 "TARGET_POWER"
1813 [(set (match_dup 3)
1814 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1815 (const_int 0)
1816 (minus:SI (match_dup 2) (match_dup 1))))
1817 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1818 "")
1820 (define_expand "smaxsi3"
1821 [(set (match_dup 3)
1822 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1823 (match_operand:SI 2 "reg_or_short_operand" ""))
1824 (const_int 0)
1825 (minus:SI (match_dup 2) (match_dup 1))))
1826 (set (match_operand:SI 0 "gpc_reg_operand" "")
1827 (plus:SI (match_dup 3) (match_dup 1)))]
1828 "TARGET_POWER || TARGET_ISEL"
1829 "
1830 {
1831 if (TARGET_ISEL)
1832 {
1833 operands[2] = force_reg (SImode, operands[2]);
1834 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1835 DONE;
1836 }
1837 operands[3] = gen_reg_rtx (SImode);
1838 }")
1840 (define_split
1841 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1842 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1843 (match_operand:SI 2 "reg_or_short_operand" "")))
1844 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1845 "TARGET_POWER"
1846 [(set (match_dup 3)
1847 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1848 (const_int 0)
1849 (minus:SI (match_dup 2) (match_dup 1))))
1850 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1851 "")
1853 (define_expand "uminsi3"
1854 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1855 (match_dup 5)))
1856 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1857 (match_dup 5)))
1858 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1859 (const_int 0)
1860 (minus:SI (match_dup 4) (match_dup 3))))
1861 (set (match_operand:SI 0 "gpc_reg_operand" "")
1862 (minus:SI (match_dup 2) (match_dup 3)))]
1863 "TARGET_POWER || TARGET_ISEL"
1864 "
1865 {
1866 if (TARGET_ISEL)
1867 {
1868 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1869 DONE;
1870 }
1871 operands[3] = gen_reg_rtx (SImode);
1872 operands[4] = gen_reg_rtx (SImode);
1873 operands[5] = GEN_INT (-2147483647 - 1);
1874 }")
1876 (define_expand "umaxsi3"
1877 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1878 (match_dup 5)))
1879 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1880 (match_dup 5)))
1881 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1882 (const_int 0)
1883 (minus:SI (match_dup 4) (match_dup 3))))
1884 (set (match_operand:SI 0 "gpc_reg_operand" "")
1885 (plus:SI (match_dup 3) (match_dup 1)))]
1886 "TARGET_POWER || TARGET_ISEL"
1887 "
1888 {
1889 if (TARGET_ISEL)
1890 {
1891 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1892 DONE;
1893 }
1894 operands[3] = gen_reg_rtx (SImode);
1895 operands[4] = gen_reg_rtx (SImode);
1896 operands[5] = GEN_INT (-2147483647 - 1);
1897 }")
1899 (define_insn ""
1900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1901 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1902 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1903 (const_int 0)
1904 (minus:SI (match_dup 2) (match_dup 1))))]
1905 "TARGET_POWER"
1906 "doz%I2 %0,%1,%2")
1908 (define_insn ""
1909 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1910 (compare:CC
1911 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1912 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1913 (const_int 0)
1914 (minus:SI (match_dup 2) (match_dup 1)))
1915 (const_int 0)))
1916 (clobber (match_scratch:SI 3 "=r,r"))]
1917 "TARGET_POWER"
1918 "@
1919 doz%I2. %3,%1,%2
1920 #"
1921 [(set_attr "type" "delayed_compare")
1922 (set_attr "length" "4,8")])
1924 (define_split
1925 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1926 (compare:CC
1927 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1928 (match_operand:SI 2 "reg_or_short_operand" ""))
1929 (const_int 0)
1930 (minus:SI (match_dup 2) (match_dup 1)))
1931 (const_int 0)))
1932 (clobber (match_scratch:SI 3 ""))]
1933 "TARGET_POWER && reload_completed"
1934 [(set (match_dup 3)
1935 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1936 (const_int 0)
1937 (minus:SI (match_dup 2) (match_dup 1))))
1938 (set (match_dup 0)
1939 (compare:CC (match_dup 3)
1940 (const_int 0)))]
1941 "")
1943 (define_insn ""
1944 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1945 (compare:CC
1946 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1947 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1948 (const_int 0)
1949 (minus:SI (match_dup 2) (match_dup 1)))
1950 (const_int 0)))
1951 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1952 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1953 (const_int 0)
1954 (minus:SI (match_dup 2) (match_dup 1))))]
1955 "TARGET_POWER"
1956 "@
1957 doz%I2. %0,%1,%2
1958 #"
1959 [(set_attr "type" "delayed_compare")
1960 (set_attr "length" "4,8")])
1962 (define_split
1963 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1964 (compare:CC
1965 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1966 (match_operand:SI 2 "reg_or_short_operand" ""))
1967 (const_int 0)
1968 (minus:SI (match_dup 2) (match_dup 1)))
1969 (const_int 0)))
1970 (set (match_operand:SI 0 "gpc_reg_operand" "")
1971 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1972 (const_int 0)
1973 (minus:SI (match_dup 2) (match_dup 1))))]
1974 "TARGET_POWER && reload_completed"
1975 [(set (match_dup 0)
1976 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1977 (const_int 0)
1978 (minus:SI (match_dup 2) (match_dup 1))))
1979 (set (match_dup 3)
1980 (compare:CC (match_dup 0)
1981 (const_int 0)))]
1982 "")
1984 ;; We don't need abs with condition code because such comparisons should
1985 ;; never be done.
1986 (define_expand "abssi2"
1987 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1988 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1989 ""
1990 "
1991 {
1992 if (TARGET_ISEL)
1993 {
1994 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1995 DONE;
1996 }
1997 else if (! TARGET_POWER)
1998 {
1999 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2000 DONE;
2001 }
2002 }")
2004 (define_insn "*abssi2_power"
2005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2006 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2007 "TARGET_POWER"
2008 "abs %0,%1")
2010 (define_insn_and_split "abssi2_isel"
2011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2012 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2013 (clobber (match_scratch:SI 2 "=&b"))
2014 (clobber (match_scratch:CC 3 "=y"))]
2015 "TARGET_ISEL"
2016 "#"
2017 "&& reload_completed"
2018 [(set (match_dup 2) (neg:SI (match_dup 1)))
2019 (set (match_dup 3)
2020 (compare:CC (match_dup 1)
2021 (const_int 0)))
2022 (set (match_dup 0)
2023 (if_then_else:SI (ge (match_dup 3)
2024 (const_int 0))
2025 (match_dup 1)
2026 (match_dup 2)))]
2027 "")
2029 (define_insn_and_split "abssi2_nopower"
2030 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2031 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2032 (clobber (match_scratch:SI 2 "=&r,&r"))]
2033 "! TARGET_POWER && ! TARGET_ISEL"
2034 "#"
2035 "&& reload_completed"
2036 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2037 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2038 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2039 "")
2041 (define_insn "*nabs_power"
2042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2043 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2044 "TARGET_POWER"
2045 "nabs %0,%1")
2047 (define_insn_and_split "*nabs_nopower"
2048 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2049 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2050 (clobber (match_scratch:SI 2 "=&r,&r"))]
2051 "! TARGET_POWER"
2052 "#"
2053 "&& reload_completed"
2054 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2055 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2056 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2057 "")
2059 (define_expand "neg<mode>2"
2060 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2061 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2062 ""
2063 "")
2065 (define_insn "*neg<mode>2_internal"
2066 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2067 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2068 ""
2069 "neg %0,%1")
2071 (define_insn ""
2072 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2073 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2074 (const_int 0)))
2075 (clobber (match_scratch:P 2 "=r,r"))]
2076 ""
2077 "@
2078 neg. %2,%1
2079 #"
2080 [(set_attr "type" "fast_compare")
2081 (set_attr "length" "4,8")])
2083 (define_split
2084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2085 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2086 (const_int 0)))
2087 (clobber (match_scratch:P 2 ""))]
2088 "reload_completed"
2089 [(set (match_dup 2)
2090 (neg:P (match_dup 1)))
2091 (set (match_dup 0)
2092 (compare:CC (match_dup 2)
2093 (const_int 0)))]
2094 "")
2096 (define_insn ""
2097 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2098 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2099 (const_int 0)))
2100 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2101 (neg:P (match_dup 1)))]
2102 ""
2103 "@
2104 neg. %0,%1
2105 #"
2106 [(set_attr "type" "fast_compare")
2107 (set_attr "length" "4,8")])
2109 (define_split
2110 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2111 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2112 (const_int 0)))
2113 (set (match_operand:P 0 "gpc_reg_operand" "")
2114 (neg:P (match_dup 1)))]
2115 "reload_completed"
2116 [(set (match_dup 0)
2117 (neg:P (match_dup 1)))
2118 (set (match_dup 2)
2119 (compare:CC (match_dup 0)
2120 (const_int 0)))]
2121 "")
2123 (define_insn "clz<mode>2"
2124 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2125 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2126 ""
2127 "{cntlz|cntlz<wd>} %0,%1"
2128 [(set_attr "type" "cntlz")])
2130 (define_expand "ctz<mode>2"
2131 [(set (match_dup 2)
2132 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2133 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2134 (match_dup 2)))
2135 (clobber (scratch:CC))])
2136 (set (match_dup 4) (clz:GPR (match_dup 3)))
2137 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2138 (minus:GPR (match_dup 5) (match_dup 4)))]
2139 ""
2140 {
2141 operands[2] = gen_reg_rtx (<MODE>mode);
2142 operands[3] = gen_reg_rtx (<MODE>mode);
2143 operands[4] = gen_reg_rtx (<MODE>mode);
2144 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2145 })
2147 (define_expand "ffs<mode>2"
2148 [(set (match_dup 2)
2149 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2150 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2151 (match_dup 2)))
2152 (clobber (scratch:CC))])
2153 (set (match_dup 4) (clz:GPR (match_dup 3)))
2154 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2155 (minus:GPR (match_dup 5) (match_dup 4)))]
2156 ""
2157 {
2158 operands[2] = gen_reg_rtx (<MODE>mode);
2159 operands[3] = gen_reg_rtx (<MODE>mode);
2160 operands[4] = gen_reg_rtx (<MODE>mode);
2161 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2162 })
2164 (define_insn "popcntb<mode>2"
2165 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2166 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2167 UNSPEC_POPCNTB))]
2168 "TARGET_POPCNTB"
2169 "popcntb %0,%1")
2171 (define_expand "popcount<mode>2"
2172 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2173 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2174 "TARGET_POPCNTB"
2175 {
2176 rs6000_emit_popcount (operands[0], operands[1]);
2177 DONE;
2178 })
2180 (define_expand "parity<mode>2"
2181 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2182 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2183 "TARGET_POPCNTB"
2184 {
2185 rs6000_emit_parity (operands[0], operands[1]);
2186 DONE;
2187 })
2189 (define_expand "mulsi3"
2190 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2191 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2192 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2193 ""
2194 "
2195 {
2196 if (TARGET_POWER)
2197 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2198 else
2199 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2200 DONE;
2201 }")
2203 (define_insn "mulsi3_mq"
2204 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2205 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2206 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2207 (clobber (match_scratch:SI 3 "=q,q"))]
2208 "TARGET_POWER"
2209 "@
2210 {muls|mullw} %0,%1,%2
2211 {muli|mulli} %0,%1,%2"
2212 [(set (attr "type")
2213 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2214 (const_string "imul3")
2215 (match_operand:SI 2 "short_cint_operand" "")
2216 (const_string "imul2")]
2217 (const_string "imul")))])
2219 (define_insn "mulsi3_no_mq"
2220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2221 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2222 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2223 "! TARGET_POWER"
2224 "@
2225 {muls|mullw} %0,%1,%2
2226 {muli|mulli} %0,%1,%2"
2227 [(set (attr "type")
2228 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2229 (const_string "imul3")
2230 (match_operand:SI 2 "short_cint_operand" "")
2231 (const_string "imul2")]
2232 (const_string "imul")))])
2234 (define_insn "*mulsi3_mq_internal1"
2235 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2236 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2237 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2238 (const_int 0)))
2239 (clobber (match_scratch:SI 3 "=r,r"))
2240 (clobber (match_scratch:SI 4 "=q,q"))]
2241 "TARGET_POWER"
2242 "@
2243 {muls.|mullw.} %3,%1,%2
2244 #"
2245 [(set_attr "type" "imul_compare")
2246 (set_attr "length" "4,8")])
2248 (define_split
2249 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2250 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2251 (match_operand:SI 2 "gpc_reg_operand" ""))
2252 (const_int 0)))
2253 (clobber (match_scratch:SI 3 ""))
2254 (clobber (match_scratch:SI 4 ""))]
2255 "TARGET_POWER && reload_completed"
2256 [(parallel [(set (match_dup 3)
2257 (mult:SI (match_dup 1) (match_dup 2)))
2258 (clobber (match_dup 4))])
2259 (set (match_dup 0)
2260 (compare:CC (match_dup 3)
2261 (const_int 0)))]
2262 "")
2264 (define_insn "*mulsi3_no_mq_internal1"
2265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2266 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2267 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2268 (const_int 0)))
2269 (clobber (match_scratch:SI 3 "=r,r"))]
2270 "! TARGET_POWER"
2271 "@
2272 {muls.|mullw.} %3,%1,%2
2273 #"
2274 [(set_attr "type" "imul_compare")
2275 (set_attr "length" "4,8")])
2277 (define_split
2278 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2279 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2280 (match_operand:SI 2 "gpc_reg_operand" ""))
2281 (const_int 0)))
2282 (clobber (match_scratch:SI 3 ""))]
2283 "! TARGET_POWER && reload_completed"
2284 [(set (match_dup 3)
2285 (mult:SI (match_dup 1) (match_dup 2)))
2286 (set (match_dup 0)
2287 (compare:CC (match_dup 3)
2288 (const_int 0)))]
2289 "")
2291 (define_insn "*mulsi3_mq_internal2"
2292 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2293 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2294 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2295 (const_int 0)))
2296 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2297 (mult:SI (match_dup 1) (match_dup 2)))
2298 (clobber (match_scratch:SI 4 "=q,q"))]
2299 "TARGET_POWER"
2300 "@
2301 {muls.|mullw.} %0,%1,%2
2302 #"
2303 [(set_attr "type" "imul_compare")
2304 (set_attr "length" "4,8")])
2306 (define_split
2307 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2308 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2309 (match_operand:SI 2 "gpc_reg_operand" ""))
2310 (const_int 0)))
2311 (set (match_operand:SI 0 "gpc_reg_operand" "")
2312 (mult:SI (match_dup 1) (match_dup 2)))
2313 (clobber (match_scratch:SI 4 ""))]
2314 "TARGET_POWER && reload_completed"
2315 [(parallel [(set (match_dup 0)
2316 (mult:SI (match_dup 1) (match_dup 2)))
2317 (clobber (match_dup 4))])
2318 (set (match_dup 3)
2319 (compare:CC (match_dup 0)
2320 (const_int 0)))]
2321 "")
2323 (define_insn "*mulsi3_no_mq_internal2"
2324 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2325 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2326 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2327 (const_int 0)))
2328 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2329 (mult:SI (match_dup 1) (match_dup 2)))]
2330 "! TARGET_POWER"
2331 "@
2332 {muls.|mullw.} %0,%1,%2
2333 #"
2334 [(set_attr "type" "imul_compare")
2335 (set_attr "length" "4,8")])
2337 (define_split
2338 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2339 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2340 (match_operand:SI 2 "gpc_reg_operand" ""))
2341 (const_int 0)))
2342 (set (match_operand:SI 0 "gpc_reg_operand" "")
2343 (mult:SI (match_dup 1) (match_dup 2)))]
2344 "! TARGET_POWER && reload_completed"
2345 [(set (match_dup 0)
2346 (mult:SI (match_dup 1) (match_dup 2)))
2347 (set (match_dup 3)
2348 (compare:CC (match_dup 0)
2349 (const_int 0)))]
2350 "")
2352 ;; Operand 1 is divided by operand 2; quotient goes to operand
2353 ;; 0 and remainder to operand 3.
2354 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2356 (define_expand "divmodsi4"
2357 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2358 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2359 (match_operand:SI 2 "gpc_reg_operand" "")))
2360 (set (match_operand:SI 3 "register_operand" "")
2361 (mod:SI (match_dup 1) (match_dup 2)))])]
2362 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2363 "
2364 {
2365 if (! TARGET_POWER && ! TARGET_POWERPC)
2366 {
2367 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2368 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2369 emit_insn (gen_divss_call ());
2370 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2371 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2372 DONE;
2373 }
2374 }")
2376 (define_insn "*divmodsi4_internal"
2377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2378 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2379 (match_operand:SI 2 "gpc_reg_operand" "r")))
2380 (set (match_operand:SI 3 "register_operand" "=q")
2381 (mod:SI (match_dup 1) (match_dup 2)))]
2382 "TARGET_POWER"
2383 "divs %0,%1,%2"
2384 [(set_attr "type" "idiv")])
2386 (define_expand "udiv<mode>3"
2387 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2388 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2389 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2390 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2391 "
2392 {
2393 if (! TARGET_POWER && ! TARGET_POWERPC)
2394 {
2395 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2396 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2397 emit_insn (gen_quous_call ());
2398 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2399 DONE;
2400 }
2401 else if (TARGET_POWER)
2402 {
2403 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2404 DONE;
2405 }
2406 }")
2408 (define_insn "udivsi3_mq"
2409 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2410 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2411 (match_operand:SI 2 "gpc_reg_operand" "r")))
2412 (clobber (match_scratch:SI 3 "=q"))]
2413 "TARGET_POWERPC && TARGET_POWER"
2414 "divwu %0,%1,%2"
2415 [(set_attr "type" "idiv")])
2417 (define_insn "*udivsi3_no_mq"
2418 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2419 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2420 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2421 "TARGET_POWERPC && ! TARGET_POWER"
2422 "div<wd>u %0,%1,%2"
2423 [(set (attr "type")
2424 (cond [(match_operand:SI 0 "" "")
2425 (const_string "idiv")]
2426 (const_string "ldiv")))])
2429 ;; For powers of two we can do srai/aze for divide and then adjust for
2430 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2431 ;; used; for PowerPC, force operands into register and do a normal divide;
2432 ;; for AIX common-mode, use quoss call on register operands.
2433 (define_expand "div<mode>3"
2434 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2435 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2436 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2437 ""
2438 "
2439 {
2440 if (GET_CODE (operands[2]) == CONST_INT
2441 && INTVAL (operands[2]) > 0
2442 && exact_log2 (INTVAL (operands[2])) >= 0)
2443 ;
2444 else if (TARGET_POWERPC)
2445 {
2446 operands[2] = force_reg (<MODE>mode, operands[2]);
2447 if (TARGET_POWER)
2448 {
2449 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2450 DONE;
2451 }
2452 }
2453 else if (TARGET_POWER)
2454 FAIL;
2455 else
2456 {
2457 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2458 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2459 emit_insn (gen_quoss_call ());
2460 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2461 DONE;
2462 }
2463 }")
2465 (define_insn "divsi3_mq"
2466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2467 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2468 (match_operand:SI 2 "gpc_reg_operand" "r")))
2469 (clobber (match_scratch:SI 3 "=q"))]
2470 "TARGET_POWERPC && TARGET_POWER"
2471 "divw %0,%1,%2"
2472 [(set_attr "type" "idiv")])
2474 (define_insn "*div<mode>3_no_mq"
2475 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2476 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2477 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2478 "TARGET_POWERPC && ! TARGET_POWER"
2479 "div<wd> %0,%1,%2"
2480 [(set (attr "type")
2481 (cond [(match_operand:SI 0 "" "")
2482 (const_string "idiv")]
2483 (const_string "ldiv")))])
2485 (define_expand "mod<mode>3"
2486 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2487 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2488 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2489 ""
2490 "
2491 {
2492 int i;
2493 rtx temp1;
2494 rtx temp2;
2496 if (GET_CODE (operands[2]) != CONST_INT
2497 || INTVAL (operands[2]) <= 0
2498 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2499 FAIL;
2501 temp1 = gen_reg_rtx (<MODE>mode);
2502 temp2 = gen_reg_rtx (<MODE>mode);
2504 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2505 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2506 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2507 DONE;
2508 }")
2510 (define_insn ""
2511 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2512 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2513 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2514 ""
2515 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2516 [(set_attr "type" "two")
2517 (set_attr "length" "8")])
2519 (define_insn ""
2520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2521 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2522 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2523 (const_int 0)))
2524 (clobber (match_scratch:P 3 "=r,r"))]
2525 ""
2526 "@
2527 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2528 #"
2529 [(set_attr "type" "compare")
2530 (set_attr "length" "8,12")])
2532 (define_split
2533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2534 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2535 (match_operand:GPR 2 "exact_log2_cint_operand"
2536 ""))
2537 (const_int 0)))
2538 (clobber (match_scratch:GPR 3 ""))]
2539 "reload_completed"
2540 [(set (match_dup 3)
2541 (div:<MODE> (match_dup 1) (match_dup 2)))
2542 (set (match_dup 0)
2543 (compare:CC (match_dup 3)
2544 (const_int 0)))]
2545 "")
2547 (define_insn ""
2548 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2549 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2550 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2551 (const_int 0)))
2552 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2553 (div:P (match_dup 1) (match_dup 2)))]
2554 ""
2555 "@
2556 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2557 #"
2558 [(set_attr "type" "compare")
2559 (set_attr "length" "8,12")])
2561 (define_split
2562 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2563 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2564 (match_operand:GPR 2 "exact_log2_cint_operand"
2565 ""))
2566 (const_int 0)))
2567 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2568 (div:GPR (match_dup 1) (match_dup 2)))]
2569 "reload_completed"
2570 [(set (match_dup 0)
2571 (div:<MODE> (match_dup 1) (match_dup 2)))
2572 (set (match_dup 3)
2573 (compare:CC (match_dup 0)
2574 (const_int 0)))]
2575 "")
2577 (define_insn ""
2578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2579 (udiv:SI
2580 (plus:DI (ashift:DI
2581 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2582 (const_int 32))
2583 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2584 (match_operand:SI 3 "gpc_reg_operand" "r")))
2585 (set (match_operand:SI 2 "register_operand" "=*q")
2586 (umod:SI
2587 (plus:DI (ashift:DI
2588 (zero_extend:DI (match_dup 1)) (const_int 32))
2589 (zero_extend:DI (match_dup 4)))
2590 (match_dup 3)))]
2591 "TARGET_POWER"
2592 "div %0,%1,%3"
2593 [(set_attr "type" "idiv")])
2595 ;; To do unsigned divide we handle the cases of the divisor looking like a
2596 ;; negative number. If it is a constant that is less than 2**31, we don't
2597 ;; have to worry about the branches. So make a few subroutines here.
2598 ;;
2599 ;; First comes the normal case.
2600 (define_expand "udivmodsi4_normal"
2601 [(set (match_dup 4) (const_int 0))
2602 (parallel [(set (match_operand:SI 0 "" "")
2603 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2604 (const_int 32))
2605 (zero_extend:DI (match_operand:SI 1 "" "")))
2606 (match_operand:SI 2 "" "")))
2607 (set (match_operand:SI 3 "" "")
2608 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2609 (const_int 32))
2610 (zero_extend:DI (match_dup 1)))
2611 (match_dup 2)))])]
2612 "TARGET_POWER"
2613 "
2614 { operands[4] = gen_reg_rtx (SImode); }")
2616 ;; This handles the branches.
2617 (define_expand "udivmodsi4_tests"
2618 [(set (match_operand:SI 0 "" "") (const_int 0))
2619 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2620 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2621 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2622 (label_ref (match_operand:SI 4 "" "")) (pc)))
2623 (set (match_dup 0) (const_int 1))
2624 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2625 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2626 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2627 (label_ref (match_dup 4)) (pc)))]
2628 "TARGET_POWER"
2629 "
2630 { operands[5] = gen_reg_rtx (CCUNSmode);
2631 operands[6] = gen_reg_rtx (CCmode);
2632 }")
2634 (define_expand "udivmodsi4"
2635 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2636 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2637 (match_operand:SI 2 "reg_or_cint_operand" "")))
2638 (set (match_operand:SI 3 "gpc_reg_operand" "")
2639 (umod:SI (match_dup 1) (match_dup 2)))])]
2640 ""
2641 "
2642 {
2643 rtx label = 0;
2645 if (! TARGET_POWER)
2646 {
2647 if (! TARGET_POWERPC)
2648 {
2649 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2650 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2651 emit_insn (gen_divus_call ());
2652 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2653 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2654 DONE;
2655 }
2656 else
2657 FAIL;
2658 }
2660 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2661 {
2662 operands[2] = force_reg (SImode, operands[2]);
2663 label = gen_label_rtx ();
2664 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2665 operands[3], label));
2666 }
2667 else
2668 operands[2] = force_reg (SImode, operands[2]);
2670 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2671 operands[3]));
2672 if (label)
2673 emit_label (label);
2675 DONE;
2676 }")
2678 ;; AIX architecture-independent common-mode multiply (DImode),
2679 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2680 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2681 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2682 ;; assumed unused if generating common-mode, so ignore.
2683 (define_insn "mulh_call"
2684 [(set (reg:SI 3)
2685 (truncate:SI
2686 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2687 (sign_extend:DI (reg:SI 4)))
2688 (const_int 32))))
2689 (clobber (match_scratch:SI 0 "=l"))]
2690 "! TARGET_POWER && ! TARGET_POWERPC"
2691 "bla __mulh"
2692 [(set_attr "type" "imul")])
2694 (define_insn "mull_call"
2695 [(set (reg:DI 3)
2696 (mult:DI (sign_extend:DI (reg:SI 3))
2697 (sign_extend:DI (reg:SI 4))))
2698 (clobber (match_scratch:SI 0 "=l"))
2699 (clobber (reg:SI 0))]
2700 "! TARGET_POWER && ! TARGET_POWERPC"
2701 "bla __mull"
2702 [(set_attr "type" "imul")])
2704 (define_insn "divss_call"
2705 [(set (reg:SI 3)
2706 (div:SI (reg:SI 3) (reg:SI 4)))
2707 (set (reg:SI 4)
2708 (mod:SI (reg:SI 3) (reg:SI 4)))
2709 (clobber (match_scratch:SI 0 "=l"))
2710 (clobber (reg:SI 0))]
2711 "! TARGET_POWER && ! TARGET_POWERPC"
2712 "bla __divss"
2713 [(set_attr "type" "idiv")])
2715 (define_insn "divus_call"
2716 [(set (reg:SI 3)
2717 (udiv:SI (reg:SI 3) (reg:SI 4)))
2718 (set (reg:SI 4)
2719 (umod:SI (reg:SI 3) (reg:SI 4)))
2720 (clobber (match_scratch:SI 0 "=l"))
2721 (clobber (reg:SI 0))
2722 (clobber (match_scratch:CC 1 "=x"))
2723 (clobber (reg:CC 69))]
2724 "! TARGET_POWER && ! TARGET_POWERPC"
2725 "bla __divus"
2726 [(set_attr "type" "idiv")])
2728 (define_insn "quoss_call"
2729 [(set (reg:SI 3)
2730 (div:SI (reg:SI 3) (reg:SI 4)))
2731 (clobber (match_scratch:SI 0 "=l"))]
2732 "! TARGET_POWER && ! TARGET_POWERPC"
2733 "bla __quoss"
2734 [(set_attr "type" "idiv")])
2736 (define_insn "quous_call"
2737 [(set (reg:SI 3)
2738 (udiv:SI (reg:SI 3) (reg:SI 4)))
2739 (clobber (match_scratch:SI 0 "=l"))
2740 (clobber (reg:SI 0))
2741 (clobber (match_scratch:CC 1 "=x"))
2742 (clobber (reg:CC 69))]
2743 "! TARGET_POWER && ! TARGET_POWERPC"
2744 "bla __quous"
2745 [(set_attr "type" "idiv")])
2746 \f
2747 ;; Logical instructions
2748 ;; The logical instructions are mostly combined by using match_operator,
2749 ;; but the plain AND insns are somewhat different because there is no
2750 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2751 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2753 (define_insn "andsi3"
2754 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2755 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2756 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2757 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2758 ""
2759 "@
2760 and %0,%1,%2
2761 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2762 {andil.|andi.} %0,%1,%b2
2763 {andiu.|andis.} %0,%1,%u2"
2764 [(set_attr "type" "*,*,compare,compare")])
2766 ;; Note to set cr's other than cr0 we do the and immediate and then
2767 ;; the test again -- this avoids a mfcr which on the higher end
2768 ;; machines causes an execution serialization
2770 (define_insn "*andsi3_internal2"
2771 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2772 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2773 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2774 (const_int 0)))
2775 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2776 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2777 "TARGET_32BIT"
2778 "@
2779 and. %3,%1,%2
2780 {andil.|andi.} %3,%1,%b2
2781 {andiu.|andis.} %3,%1,%u2
2782 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2783 #
2784 #
2785 #
2786 #"
2787 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2788 (set_attr "length" "4,4,4,4,8,8,8,8")])
2790 (define_insn "*andsi3_internal3"
2791 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2792 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2793 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2794 (const_int 0)))
2795 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2796 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2797 "TARGET_64BIT"
2798 "@
2799 #
2800 {andil.|andi.} %3,%1,%b2
2801 {andiu.|andis.} %3,%1,%u2
2802 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2803 #
2804 #
2805 #
2806 #"
2807 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2808 (set_attr "length" "8,4,4,4,8,8,8,8")])
2810 (define_split
2811 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2812 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2813 (match_operand:GPR 2 "and_operand" ""))
2814 (const_int 0)))
2815 (clobber (match_scratch:GPR 3 ""))
2816 (clobber (match_scratch:CC 4 ""))]
2817 "reload_completed"
2818 [(parallel [(set (match_dup 3)
2819 (and:<MODE> (match_dup 1)
2820 (match_dup 2)))
2821 (clobber (match_dup 4))])
2822 (set (match_dup 0)
2823 (compare:CC (match_dup 3)
2824 (const_int 0)))]
2825 "")
2827 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2828 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2830 (define_split
2831 [(set (match_operand:CC 0 "cc_reg_operand" "")
2832 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2833 (match_operand:SI 2 "gpc_reg_operand" ""))
2834 (const_int 0)))
2835 (clobber (match_scratch:SI 3 ""))
2836 (clobber (match_scratch:CC 4 ""))]
2837 "TARGET_POWERPC64 && reload_completed"
2838 [(parallel [(set (match_dup 3)
2839 (and:SI (match_dup 1)
2840 (match_dup 2)))
2841 (clobber (match_dup 4))])
2842 (set (match_dup 0)
2843 (compare:CC (match_dup 3)
2844 (const_int 0)))]
2845 "")
2847 (define_insn "*andsi3_internal4"
2848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2849 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2850 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2851 (const_int 0)))
2852 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2853 (and:SI (match_dup 1)
2854 (match_dup 2)))
2855 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2856 "TARGET_32BIT"
2857 "@
2858 and. %0,%1,%2
2859 {andil.|andi.} %0,%1,%b2
2860 {andiu.|andis.} %0,%1,%u2
2861 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2862 #
2863 #
2864 #
2865 #"
2866 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2867 (set_attr "length" "4,4,4,4,8,8,8,8")])
2869 (define_insn "*andsi3_internal5"
2870 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2871 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2872 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2873 (const_int 0)))
2874 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2875 (and:SI (match_dup 1)
2876 (match_dup 2)))
2877 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2878 "TARGET_64BIT"
2879 "@
2880 #
2881 {andil.|andi.} %0,%1,%b2
2882 {andiu.|andis.} %0,%1,%u2
2883 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2884 #
2885 #
2886 #
2887 #"
2888 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2889 (set_attr "length" "8,4,4,4,8,8,8,8")])
2891 (define_split
2892 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2893 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2894 (match_operand:SI 2 "and_operand" ""))
2895 (const_int 0)))
2896 (set (match_operand:SI 0 "gpc_reg_operand" "")
2897 (and:SI (match_dup 1)
2898 (match_dup 2)))
2899 (clobber (match_scratch:CC 4 ""))]
2900 "reload_completed"
2901 [(parallel [(set (match_dup 0)
2902 (and:SI (match_dup 1)
2903 (match_dup 2)))
2904 (clobber (match_dup 4))])
2905 (set (match_dup 3)
2906 (compare:CC (match_dup 0)
2907 (const_int 0)))]
2908 "")
2910 (define_split
2911 [(set (match_operand:CC 3 "cc_reg_operand" "")
2912 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2913 (match_operand:SI 2 "gpc_reg_operand" ""))
2914 (const_int 0)))
2915 (set (match_operand:SI 0 "gpc_reg_operand" "")
2916 (and:SI (match_dup 1)
2917 (match_dup 2)))
2918 (clobber (match_scratch:CC 4 ""))]
2919 "TARGET_POWERPC64 && reload_completed"
2920 [(parallel [(set (match_dup 0)
2921 (and:SI (match_dup 1)
2922 (match_dup 2)))
2923 (clobber (match_dup 4))])
2924 (set (match_dup 3)
2925 (compare:CC (match_dup 0)
2926 (const_int 0)))]
2927 "")
2929 ;; Handle the PowerPC64 rlwinm corner case
2931 (define_insn_and_split "*andsi3_internal6"
2932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2933 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2934 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2935 "TARGET_POWERPC64"
2936 "#"
2937 "TARGET_POWERPC64"
2938 [(set (match_dup 0)
2939 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2940 (match_dup 4)))
2941 (set (match_dup 0)
2942 (rotate:SI (match_dup 0) (match_dup 5)))]
2943 "
2944 {
2945 int mb = extract_MB (operands[2]);
2946 int me = extract_ME (operands[2]);
2947 operands[3] = GEN_INT (me + 1);
2948 operands[5] = GEN_INT (32 - (me + 1));
2949 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2950 }"
2951 [(set_attr "length" "8")])
2953 (define_expand "iorsi3"
2954 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2955 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2956 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2957 ""
2958 "
2959 {
2960 if (GET_CODE (operands[2]) == CONST_INT
2961 && ! logical_operand (operands[2], SImode))
2962 {
2963 HOST_WIDE_INT value = INTVAL (operands[2]);
2964 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2965 ? operands[0] : gen_reg_rtx (SImode));
2967 emit_insn (gen_iorsi3 (tmp, operands[1],
2968 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2969 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2970 DONE;
2971 }
2972 }")
2974 (define_expand "xorsi3"
2975 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2976 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2977 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2978 ""
2979 "
2980 {
2981 if (GET_CODE (operands[2]) == CONST_INT
2982 && ! logical_operand (operands[2], SImode))
2983 {
2984 HOST_WIDE_INT value = INTVAL (operands[2]);
2985 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2986 ? operands[0] : gen_reg_rtx (SImode));
2988 emit_insn (gen_xorsi3 (tmp, operands[1],
2989 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2990 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2991 DONE;
2992 }
2993 }")
2995 (define_insn "*boolsi3_internal1"
2996 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2997 (match_operator:SI 3 "boolean_or_operator"
2998 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2999 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3000 ""
3001 "@
3002 %q3 %0,%1,%2
3003 {%q3il|%q3i} %0,%1,%b2
3004 {%q3iu|%q3is} %0,%1,%u2")
3006 (define_insn "*boolsi3_internal2"
3007 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3008 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3009 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3010 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3011 (const_int 0)))
3012 (clobber (match_scratch:SI 3 "=r,r"))]
3013 "TARGET_32BIT"
3014 "@
3015 %q4. %3,%1,%2
3016 #"
3017 [(set_attr "type" "compare")
3018 (set_attr "length" "4,8")])
3020 (define_split
3021 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3022 (compare:CC (match_operator:SI 4 "boolean_operator"
3023 [(match_operand:SI 1 "gpc_reg_operand" "")
3024 (match_operand:SI 2 "gpc_reg_operand" "")])
3025 (const_int 0)))
3026 (clobber (match_scratch:SI 3 ""))]
3027 "TARGET_32BIT && reload_completed"
3028 [(set (match_dup 3) (match_dup 4))
3029 (set (match_dup 0)
3030 (compare:CC (match_dup 3)
3031 (const_int 0)))]
3032 "")
3034 (define_insn "*boolsi3_internal3"
3035 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3036 (compare:CC (match_operator:SI 4 "boolean_operator"
3037 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3038 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3039 (const_int 0)))
3040 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3041 (match_dup 4))]
3042 "TARGET_32BIT"
3043 "@
3044 %q4. %0,%1,%2
3045 #"
3046 [(set_attr "type" "compare")
3047 (set_attr "length" "4,8")])
3049 (define_split
3050 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3051 (compare:CC (match_operator:SI 4 "boolean_operator"
3052 [(match_operand:SI 1 "gpc_reg_operand" "")
3053 (match_operand:SI 2 "gpc_reg_operand" "")])
3054 (const_int 0)))
3055 (set (match_operand:SI 0 "gpc_reg_operand" "")
3056 (match_dup 4))]
3057 "TARGET_32BIT && reload_completed"
3058 [(set (match_dup 0) (match_dup 4))
3059 (set (match_dup 3)
3060 (compare:CC (match_dup 0)
3061 (const_int 0)))]
3062 "")
3064 ;; Split a logical operation that we can't do in one insn into two insns,
3065 ;; each of which does one 16-bit part. This is used by combine.
3067 (define_split
3068 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3069 (match_operator:SI 3 "boolean_or_operator"
3070 [(match_operand:SI 1 "gpc_reg_operand" "")
3071 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3072 ""
3073 [(set (match_dup 0) (match_dup 4))
3074 (set (match_dup 0) (match_dup 5))]
3075 "
3076 {
3077 rtx i;
3078 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3079 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3080 operands[1], i);
3081 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3082 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3083 operands[0], i);
3084 }")
3086 (define_insn "*boolcsi3_internal1"
3087 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3088 (match_operator:SI 3 "boolean_operator"
3089 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3090 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3091 ""
3092 "%q3 %0,%2,%1")
3094 (define_insn "*boolcsi3_internal2"
3095 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3096 (compare:CC (match_operator:SI 4 "boolean_operator"
3097 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3098 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3099 (const_int 0)))
3100 (clobber (match_scratch:SI 3 "=r,r"))]
3101 "TARGET_32BIT"
3102 "@
3103 %q4. %3,%2,%1
3104 #"
3105 [(set_attr "type" "compare")
3106 (set_attr "length" "4,8")])
3108 (define_split
3109 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3110 (compare:CC (match_operator:SI 4 "boolean_operator"
3111 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3112 (match_operand:SI 2 "gpc_reg_operand" "")])
3113 (const_int 0)))
3114 (clobber (match_scratch:SI 3 ""))]
3115 "TARGET_32BIT && reload_completed"
3116 [(set (match_dup 3) (match_dup 4))
3117 (set (match_dup 0)
3118 (compare:CC (match_dup 3)
3119 (const_int 0)))]
3120 "")
3122 (define_insn "*boolcsi3_internal3"
3123 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3124 (compare:CC (match_operator:SI 4 "boolean_operator"
3125 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3126 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3127 (const_int 0)))
3128 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3129 (match_dup 4))]
3130 "TARGET_32BIT"
3131 "@
3132 %q4. %0,%2,%1
3133 #"
3134 [(set_attr "type" "compare")
3135 (set_attr "length" "4,8")])
3137 (define_split
3138 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3139 (compare:CC (match_operator:SI 4 "boolean_operator"
3140 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3141 (match_operand:SI 2 "gpc_reg_operand" "")])
3142 (const_int 0)))
3143 (set (match_operand:SI 0 "gpc_reg_operand" "")
3144 (match_dup 4))]
3145 "TARGET_32BIT && reload_completed"
3146 [(set (match_dup 0) (match_dup 4))
3147 (set (match_dup 3)
3148 (compare:CC (match_dup 0)
3149 (const_int 0)))]
3150 "")
3152 (define_insn "*boolccsi3_internal1"
3153 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3154 (match_operator:SI 3 "boolean_operator"
3155 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3156 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3157 ""
3158 "%q3 %0,%1,%2")
3160 (define_insn "*boolccsi3_internal2"
3161 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3162 (compare:CC (match_operator:SI 4 "boolean_operator"
3163 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3164 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3165 (const_int 0)))
3166 (clobber (match_scratch:SI 3 "=r,r"))]
3167 "TARGET_32BIT"
3168 "@
3169 %q4. %3,%1,%2
3170 #"
3171 [(set_attr "type" "compare")
3172 (set_attr "length" "4,8")])
3174 (define_split
3175 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3176 (compare:CC (match_operator:SI 4 "boolean_operator"
3177 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3178 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3179 (const_int 0)))
3180 (clobber (match_scratch:SI 3 ""))]
3181 "TARGET_32BIT && reload_completed"
3182 [(set (match_dup 3) (match_dup 4))
3183 (set (match_dup 0)
3184 (compare:CC (match_dup 3)
3185 (const_int 0)))]
3186 "")
3188 (define_insn "*boolccsi3_internal3"
3189 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3190 (compare:CC (match_operator:SI 4 "boolean_operator"
3191 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3192 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3193 (const_int 0)))
3194 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3195 (match_dup 4))]
3196 "TARGET_32BIT"
3197 "@
3198 %q4. %0,%1,%2
3199 #"
3200 [(set_attr "type" "compare")
3201 (set_attr "length" "4,8")])
3203 (define_split
3204 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3205 (compare:CC (match_operator:SI 4 "boolean_operator"
3206 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3207 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3208 (const_int 0)))
3209 (set (match_operand:SI 0 "gpc_reg_operand" "")
3210 (match_dup 4))]
3211 "TARGET_32BIT && reload_completed"
3212 [(set (match_dup 0) (match_dup 4))
3213 (set (match_dup 3)
3214 (compare:CC (match_dup 0)
3215 (const_int 0)))]
3216 "")
3218 ;; maskir insn. We need four forms because things might be in arbitrary
3219 ;; orders. Don't define forms that only set CR fields because these
3220 ;; would modify an input register.
3222 (define_insn "*maskir_internal1"
3223 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3224 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3225 (match_operand:SI 1 "gpc_reg_operand" "0"))
3226 (and:SI (match_dup 2)
3227 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3228 "TARGET_POWER"
3229 "maskir %0,%3,%2")
3231 (define_insn "*maskir_internal2"
3232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3233 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3234 (match_operand:SI 1 "gpc_reg_operand" "0"))
3235 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3236 (match_dup 2))))]
3237 "TARGET_POWER"
3238 "maskir %0,%3,%2")
3240 (define_insn "*maskir_internal3"
3241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3242 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3243 (match_operand:SI 3 "gpc_reg_operand" "r"))
3244 (and:SI (not:SI (match_dup 2))
3245 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3246 "TARGET_POWER"
3247 "maskir %0,%3,%2")
3249 (define_insn "*maskir_internal4"
3250 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3251 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3252 (match_operand:SI 2 "gpc_reg_operand" "r"))
3253 (and:SI (not:SI (match_dup 2))
3254 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3255 "TARGET_POWER"
3256 "maskir %0,%3,%2")
3258 (define_insn "*maskir_internal5"
3259 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3260 (compare:CC
3261 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3262 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3263 (and:SI (match_dup 2)
3264 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3265 (const_int 0)))
3266 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3267 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3268 (and:SI (match_dup 2) (match_dup 3))))]
3269 "TARGET_POWER"
3270 "@
3271 maskir. %0,%3,%2
3272 #"
3273 [(set_attr "type" "compare")
3274 (set_attr "length" "4,8")])
3276 (define_split
3277 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3278 (compare:CC
3279 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3280 (match_operand:SI 1 "gpc_reg_operand" ""))
3281 (and:SI (match_dup 2)
3282 (match_operand:SI 3 "gpc_reg_operand" "")))
3283 (const_int 0)))
3284 (set (match_operand:SI 0 "gpc_reg_operand" "")
3285 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3286 (and:SI (match_dup 2) (match_dup 3))))]
3287 "TARGET_POWER && reload_completed"
3288 [(set (match_dup 0)
3289 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3290 (and:SI (match_dup 2) (match_dup 3))))
3291 (set (match_dup 4)
3292 (compare:CC (match_dup 0)
3293 (const_int 0)))]
3294 "")
3296 (define_insn "*maskir_internal6"
3297 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3298 (compare:CC
3299 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3300 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3301 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3302 (match_dup 2)))
3303 (const_int 0)))
3304 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3305 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3306 (and:SI (match_dup 3) (match_dup 2))))]
3307 "TARGET_POWER"
3308 "@
3309 maskir. %0,%3,%2
3310 #"
3311 [(set_attr "type" "compare")
3312 (set_attr "length" "4,8")])
3314 (define_split
3315 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3316 (compare:CC
3317 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3318 (match_operand:SI 1 "gpc_reg_operand" ""))
3319 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3320 (match_dup 2)))
3321 (const_int 0)))
3322 (set (match_operand:SI 0 "gpc_reg_operand" "")
3323 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3324 (and:SI (match_dup 3) (match_dup 2))))]
3325 "TARGET_POWER && reload_completed"
3326 [(set (match_dup 0)
3327 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3328 (and:SI (match_dup 3) (match_dup 2))))
3329 (set (match_dup 4)
3330 (compare:CC (match_dup 0)
3331 (const_int 0)))]
3332 "")
3334 (define_insn "*maskir_internal7"
3335 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3336 (compare:CC
3337 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3338 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3339 (and:SI (not:SI (match_dup 2))
3340 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3341 (const_int 0)))
3342 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3343 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3344 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3345 "TARGET_POWER"
3346 "@
3347 maskir. %0,%3,%2
3348 #"
3349 [(set_attr "type" "compare")
3350 (set_attr "length" "4,8")])
3352 (define_split
3353 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3354 (compare:CC
3355 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3356 (match_operand:SI 3 "gpc_reg_operand" ""))
3357 (and:SI (not:SI (match_dup 2))
3358 (match_operand:SI 1 "gpc_reg_operand" "")))
3359 (const_int 0)))
3360 (set (match_operand:SI 0 "gpc_reg_operand" "")
3361 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3362 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3363 "TARGET_POWER && reload_completed"
3364 [(set (match_dup 0)
3365 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3366 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3367 (set (match_dup 4)
3368 (compare:CC (match_dup 0)
3369 (const_int 0)))]
3370 "")
3372 (define_insn "*maskir_internal8"
3373 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3374 (compare:CC
3375 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3376 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3377 (and:SI (not:SI (match_dup 2))
3378 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3379 (const_int 0)))
3380 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3381 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3382 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3383 "TARGET_POWER"
3384 "@
3385 maskir. %0,%3,%2
3386 #"
3387 [(set_attr "type" "compare")
3388 (set_attr "length" "4,8")])
3390 (define_split
3391 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3392 (compare:CC
3393 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3394 (match_operand:SI 2 "gpc_reg_operand" ""))
3395 (and:SI (not:SI (match_dup 2))
3396 (match_operand:SI 1 "gpc_reg_operand" "")))
3397 (const_int 0)))
3398 (set (match_operand:SI 0 "gpc_reg_operand" "")
3399 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3400 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3401 "TARGET_POWER && reload_completed"
3402 [(set (match_dup 0)
3403 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3404 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3405 (set (match_dup 4)
3406 (compare:CC (match_dup 0)
3407 (const_int 0)))]
3408 "")
3409 \f
3410 ;; Rotate and shift insns, in all their variants. These support shifts,
3411 ;; field inserts and extracts, and various combinations thereof.
3412 (define_expand "insv"
3413 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3414 (match_operand:SI 1 "const_int_operand" "")
3415 (match_operand:SI 2 "const_int_operand" ""))
3416 (match_operand 3 "gpc_reg_operand" ""))]
3417 ""
3418 "
3419 {
3420 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3421 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3422 compiler if the address of the structure is taken later. Likewise, do
3423 not handle invalid E500 subregs. */
3424 if (GET_CODE (operands[0]) == SUBREG
3425 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3426 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3427 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3428 FAIL;
3430 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3431 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3432 else
3433 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3434 DONE;
3435 }")
3437 (define_insn "insvsi"
3438 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3439 (match_operand:SI 1 "const_int_operand" "i")
3440 (match_operand:SI 2 "const_int_operand" "i"))
3441 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3442 ""
3443 "*
3444 {
3445 int start = INTVAL (operands[2]) & 31;
3446 int size = INTVAL (operands[1]) & 31;
3448 operands[4] = GEN_INT (32 - start - size);
3449 operands[1] = GEN_INT (start + size - 1);
3450 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3451 }"
3452 [(set_attr "type" "insert_word")])
3454 (define_insn "*insvsi_internal1"
3455 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3456 (match_operand:SI 1 "const_int_operand" "i")
3457 (match_operand:SI 2 "const_int_operand" "i"))
3458 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3459 (match_operand:SI 4 "const_int_operand" "i")))]
3460 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3461 "*
3462 {
3463 int shift = INTVAL (operands[4]) & 31;
3464 int start = INTVAL (operands[2]) & 31;
3465 int size = INTVAL (operands[1]) & 31;
3467 operands[4] = GEN_INT (shift - start - size);
3468 operands[1] = GEN_INT (start + size - 1);
3469 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3470 }"
3471 [(set_attr "type" "insert_word")])
3473 (define_insn "*insvsi_internal2"
3474 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3475 (match_operand:SI 1 "const_int_operand" "i")
3476 (match_operand:SI 2 "const_int_operand" "i"))
3477 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3478 (match_operand:SI 4 "const_int_operand" "i")))]
3479 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3480 "*
3481 {
3482 int shift = INTVAL (operands[4]) & 31;
3483 int start = INTVAL (operands[2]) & 31;
3484 int size = INTVAL (operands[1]) & 31;
3486 operands[4] = GEN_INT (32 - shift - start - size);
3487 operands[1] = GEN_INT (start + size - 1);
3488 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3489 }"
3490 [(set_attr "type" "insert_word")])
3492 (define_insn "*insvsi_internal3"
3493 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3494 (match_operand:SI 1 "const_int_operand" "i")
3495 (match_operand:SI 2 "const_int_operand" "i"))
3496 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3497 (match_operand:SI 4 "const_int_operand" "i")))]
3498 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3499 "*
3500 {
3501 int shift = INTVAL (operands[4]) & 31;
3502 int start = INTVAL (operands[2]) & 31;
3503 int size = INTVAL (operands[1]) & 31;
3505 operands[4] = GEN_INT (32 - shift - start - size);
3506 operands[1] = GEN_INT (start + size - 1);
3507 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3508 }"
3509 [(set_attr "type" "insert_word")])
3511 (define_insn "*insvsi_internal4"
3512 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3513 (match_operand:SI 1 "const_int_operand" "i")
3514 (match_operand:SI 2 "const_int_operand" "i"))
3515 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3516 (match_operand:SI 4 "const_int_operand" "i")
3517 (match_operand:SI 5 "const_int_operand" "i")))]
3518 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3519 "*
3520 {
3521 int extract_start = INTVAL (operands[5]) & 31;
3522 int extract_size = INTVAL (operands[4]) & 31;
3523 int insert_start = INTVAL (operands[2]) & 31;
3524 int insert_size = INTVAL (operands[1]) & 31;
3526 /* Align extract field with insert field */
3527 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3528 operands[1] = GEN_INT (insert_start + insert_size - 1);
3529 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3530 }"
3531 [(set_attr "type" "insert_word")])
3533 ;; combine patterns for rlwimi
3534 (define_insn "*insvsi_internal5"
3535 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3536 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3537 (match_operand:SI 1 "mask_operand" "i"))
3538 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3539 (match_operand:SI 2 "const_int_operand" "i"))
3540 (match_operand:SI 5 "mask_operand" "i"))))]
3541 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3542 "*
3543 {
3544 int me = extract_ME(operands[5]);
3545 int mb = extract_MB(operands[5]);
3546 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3547 operands[2] = GEN_INT(mb);
3548 operands[1] = GEN_INT(me);
3549 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3550 }"
3551 [(set_attr "type" "insert_word")])
3553 (define_insn "*insvsi_internal6"
3554 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3555 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3556 (match_operand:SI 2 "const_int_operand" "i"))
3557 (match_operand:SI 5 "mask_operand" "i"))
3558 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3559 (match_operand:SI 1 "mask_operand" "i"))))]
3560 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3561 "*
3562 {
3563 int me = extract_ME(operands[5]);
3564 int mb = extract_MB(operands[5]);
3565 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3566 operands[2] = GEN_INT(mb);
3567 operands[1] = GEN_INT(me);
3568 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3569 }"
3570 [(set_attr "type" "insert_word")])
3572 (define_insn "insvdi"
3573 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3574 (match_operand:SI 1 "const_int_operand" "i")
3575 (match_operand:SI 2 "const_int_operand" "i"))
3576 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3577 "TARGET_POWERPC64"
3578 "*
3579 {
3580 int start = INTVAL (operands[2]) & 63;
3581 int size = INTVAL (operands[1]) & 63;
3583 operands[1] = GEN_INT (64 - start - size);
3584 return \"rldimi %0,%3,%H1,%H2\";
3585 }"
3586 [(set_attr "type" "insert_dword")])
3588 (define_insn "*insvdi_internal2"
3589 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3590 (match_operand:SI 1 "const_int_operand" "i")
3591 (match_operand:SI 2 "const_int_operand" "i"))
3592 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3593 (match_operand:SI 4 "const_int_operand" "i")))]
3594 "TARGET_POWERPC64
3595 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3596 "*
3597 {
3598 int shift = INTVAL (operands[4]) & 63;
3599 int start = (INTVAL (operands[2]) & 63) - 32;
3600 int size = INTVAL (operands[1]) & 63;
3602 operands[4] = GEN_INT (64 - shift - start - size);
3603 operands[2] = GEN_INT (start);
3604 operands[1] = GEN_INT (start + size - 1);
3605 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3606 }")
3608 (define_insn "*insvdi_internal3"
3609 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3610 (match_operand:SI 1 "const_int_operand" "i")
3611 (match_operand:SI 2 "const_int_operand" "i"))
3612 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3613 (match_operand:SI 4 "const_int_operand" "i")))]
3614 "TARGET_POWERPC64
3615 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3616 "*
3617 {
3618 int shift = INTVAL (operands[4]) & 63;
3619 int start = (INTVAL (operands[2]) & 63) - 32;
3620 int size = INTVAL (operands[1]) & 63;
3622 operands[4] = GEN_INT (64 - shift - start - size);
3623 operands[2] = GEN_INT (start);
3624 operands[1] = GEN_INT (start + size - 1);
3625 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3626 }")
3628 (define_expand "extzv"
3629 [(set (match_operand 0 "gpc_reg_operand" "")
3630 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3631 (match_operand:SI 2 "const_int_operand" "")
3632 (match_operand:SI 3 "const_int_operand" "")))]
3633 ""
3634 "
3635 {
3636 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3637 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3638 compiler if the address of the structure is taken later. */
3639 if (GET_CODE (operands[0]) == SUBREG
3640 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3641 FAIL;
3643 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3644 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3645 else
3646 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3647 DONE;
3648 }")
3650 (define_insn "extzvsi"
3651 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3652 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3653 (match_operand:SI 2 "const_int_operand" "i")
3654 (match_operand:SI 3 "const_int_operand" "i")))]
3655 ""
3656 "*
3657 {
3658 int start = INTVAL (operands[3]) & 31;
3659 int size = INTVAL (operands[2]) & 31;
3661 if (start + size >= 32)
3662 operands[3] = const0_rtx;
3663 else
3664 operands[3] = GEN_INT (start + size);
3665 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3666 }")
3668 (define_insn "*extzvsi_internal1"
3669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3670 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3671 (match_operand:SI 2 "const_int_operand" "i,i")
3672 (match_operand:SI 3 "const_int_operand" "i,i"))
3673 (const_int 0)))
3674 (clobber (match_scratch:SI 4 "=r,r"))]
3675 ""
3676 "*
3677 {
3678 int start = INTVAL (operands[3]) & 31;
3679 int size = INTVAL (operands[2]) & 31;
3681 /* Force split for non-cc0 compare. */
3682 if (which_alternative == 1)
3683 return \"#\";
3685 /* If the bit-field being tested fits in the upper or lower half of a
3686 word, it is possible to use andiu. or andil. to test it. This is
3687 useful because the condition register set-use delay is smaller for
3688 andi[ul]. than for rlinm. This doesn't work when the starting bit
3689 position is 0 because the LT and GT bits may be set wrong. */
3691 if ((start > 0 && start + size <= 16) || start >= 16)
3692 {
3693 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3694 - (1 << (16 - (start & 15) - size))));
3695 if (start < 16)
3696 return \"{andiu.|andis.} %4,%1,%3\";
3697 else
3698 return \"{andil.|andi.} %4,%1,%3\";
3699 }
3701 if (start + size >= 32)
3702 operands[3] = const0_rtx;
3703 else
3704 operands[3] = GEN_INT (start + size);
3705 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3706 }"
3707 [(set_attr "type" "delayed_compare")
3708 (set_attr "length" "4,8")])
3710 (define_split
3711 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3712 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3713 (match_operand:SI 2 "const_int_operand" "")
3714 (match_operand:SI 3 "const_int_operand" ""))
3715 (const_int 0)))
3716 (clobber (match_scratch:SI 4 ""))]
3717 "reload_completed"
3718 [(set (match_dup 4)
3719 (zero_extract:SI (match_dup 1) (match_dup 2)
3720 (match_dup 3)))
3721 (set (match_dup 0)
3722 (compare:CC (match_dup 4)
3723 (const_int 0)))]
3724 "")
3726 (define_insn "*extzvsi_internal2"
3727 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3728 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3729 (match_operand:SI 2 "const_int_operand" "i,i")
3730 (match_operand:SI 3 "const_int_operand" "i,i"))
3731 (const_int 0)))
3732 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3733 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3734 ""
3735 "*
3736 {
3737 int start = INTVAL (operands[3]) & 31;
3738 int size = INTVAL (operands[2]) & 31;
3740 /* Force split for non-cc0 compare. */
3741 if (which_alternative == 1)
3742 return \"#\";
3744 /* Since we are using the output value, we can't ignore any need for
3745 a shift. The bit-field must end at the LSB. */
3746 if (start >= 16 && start + size == 32)
3747 {
3748 operands[3] = GEN_INT ((1 << size) - 1);
3749 return \"{andil.|andi.} %0,%1,%3\";
3750 }
3752 if (start + size >= 32)
3753 operands[3] = const0_rtx;
3754 else
3755 operands[3] = GEN_INT (start + size);
3756 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3757 }"
3758 [(set_attr "type" "delayed_compare")
3759 (set_attr "length" "4,8")])
3761 (define_split
3762 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3763 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3764 (match_operand:SI 2 "const_int_operand" "")
3765 (match_operand:SI 3 "const_int_operand" ""))
3766 (const_int 0)))
3767 (set (match_operand:SI 0 "gpc_reg_operand" "")
3768 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3769 "reload_completed"
3770 [(set (match_dup 0)
3771 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3772 (set (match_dup 4)
3773 (compare:CC (match_dup 0)
3774 (const_int 0)))]
3775 "")
3777 (define_insn "extzvdi"
3778 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3779 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3780 (match_operand:SI 2 "const_int_operand" "i")
3781 (match_operand:SI 3 "const_int_operand" "i")))]
3782 "TARGET_POWERPC64"
3783 "*
3784 {
3785 int start = INTVAL (operands[3]) & 63;
3786 int size = INTVAL (operands[2]) & 63;
3788 if (start + size >= 64)
3789 operands[3] = const0_rtx;
3790 else
3791 operands[3] = GEN_INT (start + size);
3792 operands[2] = GEN_INT (64 - size);
3793 return \"rldicl %0,%1,%3,%2\";
3794 }")
3796 (define_insn "*extzvdi_internal1"
3797 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3798 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3799 (match_operand:SI 2 "const_int_operand" "i")
3800 (match_operand:SI 3 "const_int_operand" "i"))
3801 (const_int 0)))
3802 (clobber (match_scratch:DI 4 "=r"))]
3803 "TARGET_64BIT"
3804 "*
3805 {
3806 int start = INTVAL (operands[3]) & 63;
3807 int size = INTVAL (operands[2]) & 63;
3809 if (start + size >= 64)
3810 operands[3] = const0_rtx;
3811 else
3812 operands[3] = GEN_INT (start + size);
3813 operands[2] = GEN_INT (64 - size);
3814 return \"rldicl. %4,%1,%3,%2\";
3815 }"
3816 [(set_attr "type" "compare")])
3818 (define_insn "*extzvdi_internal2"
3819 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3820 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3821 (match_operand:SI 2 "const_int_operand" "i")
3822 (match_operand:SI 3 "const_int_operand" "i"))
3823 (const_int 0)))
3824 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3825 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3826 "TARGET_64BIT"
3827 "*
3828 {
3829 int start = INTVAL (operands[3]) & 63;
3830 int size = INTVAL (operands[2]) & 63;
3832 if (start + size >= 64)
3833 operands[3] = const0_rtx;
3834 else
3835 operands[3] = GEN_INT (start + size);
3836 operands[2] = GEN_INT (64 - size);
3837 return \"rldicl. %0,%1,%3,%2\";
3838 }"
3839 [(set_attr "type" "compare")])
3841 (define_insn "rotlsi3"
3842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3843 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3844 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3845 ""
3846 "@
3847 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3848 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3849 [(set_attr "type" "var_shift_rotate,integer")])
3851 (define_insn "*rotlsi3_internal2"
3852 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3853 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3854 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3855 (const_int 0)))
3856 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3857 ""
3858 "@
3859 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3860 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3861 #
3862 #"
3863 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3864 (set_attr "length" "4,4,8,8")])
3866 (define_split
3867 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3868 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3869 (match_operand:SI 2 "reg_or_cint_operand" ""))
3870 (const_int 0)))
3871 (clobber (match_scratch:SI 3 ""))]
3872 "reload_completed"
3873 [(set (match_dup 3)
3874 (rotate:SI (match_dup 1) (match_dup 2)))
3875 (set (match_dup 0)
3876 (compare:CC (match_dup 3)
3877 (const_int 0)))]
3878 "")
3880 (define_insn "*rotlsi3_internal3"
3881 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3882 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3883 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3884 (const_int 0)))
3885 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3886 (rotate:SI (match_dup 1) (match_dup 2)))]
3887 ""
3888 "@
3889 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3890 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3891 #
3892 #"
3893 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3894 (set_attr "length" "4,4,8,8")])
3896 (define_split
3897 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3898 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3899 (match_operand:SI 2 "reg_or_cint_operand" ""))
3900 (const_int 0)))
3901 (set (match_operand:SI 0 "gpc_reg_operand" "")
3902 (rotate:SI (match_dup 1) (match_dup 2)))]
3903 "reload_completed"
3904 [(set (match_dup 0)
3905 (rotate:SI (match_dup 1) (match_dup 2)))
3906 (set (match_dup 3)
3907 (compare:CC (match_dup 0)
3908 (const_int 0)))]
3909 "")
3911 (define_insn "*rotlsi3_internal4"
3912 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3913 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3914 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3915 (match_operand:SI 3 "mask_operand" "n,n")))]
3916 ""
3917 "@
3918 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3919 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3920 [(set_attr "type" "var_shift_rotate,integer")])
3922 (define_insn "*rotlsi3_internal5"
3923 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3924 (compare:CC (and:SI
3925 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3926 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3927 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3928 (const_int 0)))
3929 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3930 ""
3931 "@
3932 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3933 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3934 #
3935 #"
3936 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3937 (set_attr "length" "4,4,8,8")])
3939 (define_split
3940 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3941 (compare:CC (and:SI
3942 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3943 (match_operand:SI 2 "reg_or_cint_operand" ""))
3944 (match_operand:SI 3 "mask_operand" ""))
3945 (const_int 0)))
3946 (clobber (match_scratch:SI 4 ""))]
3947 "reload_completed"
3948 [(set (match_dup 4)
3949 (and:SI (rotate:SI (match_dup 1)
3950 (match_dup 2))
3951 (match_dup 3)))
3952 (set (match_dup 0)
3953 (compare:CC (match_dup 4)
3954 (const_int 0)))]
3955 "")
3957 (define_insn "*rotlsi3_internal6"
3958 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3959 (compare:CC (and:SI
3960 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3961 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3962 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3963 (const_int 0)))
3964 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3965 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3966 ""
3967 "@
3968 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
3969 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3970 #
3971 #"
3972 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3973 (set_attr "length" "4,4,8,8")])
3975 (define_split
3976 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3977 (compare:CC (and:SI
3978 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3979 (match_operand:SI 2 "reg_or_cint_operand" ""))
3980 (match_operand:SI 3 "mask_operand" ""))
3981 (const_int 0)))
3982 (set (match_operand:SI 0 "gpc_reg_operand" "")
3983 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3984 "reload_completed"
3985 [(set (match_dup 0)
3986 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3987 (set (match_dup 4)
3988 (compare:CC (match_dup 0)
3989 (const_int 0)))]
3990 "")
3992 (define_insn "*rotlsi3_internal7"
3993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3994 (zero_extend:SI
3995 (subreg:QI
3996 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3997 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3998 ""
3999 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4001 (define_insn "*rotlsi3_internal8"
4002 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4003 (compare:CC (zero_extend:SI
4004 (subreg:QI
4005 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4006 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4007 (const_int 0)))
4008 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4009 ""
4010 "@
4011 {rlnm.|rlwnm.} %3,%1,%2,0xff
4012 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4013 #
4014 #"
4015 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4016 (set_attr "length" "4,4,8,8")])
4018 (define_split
4019 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4020 (compare:CC (zero_extend:SI
4021 (subreg:QI
4022 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4023 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4024 (const_int 0)))
4025 (clobber (match_scratch:SI 3 ""))]
4026 "reload_completed"
4027 [(set (match_dup 3)
4028 (zero_extend:SI (subreg:QI
4029 (rotate:SI (match_dup 1)
4030 (match_dup 2)) 0)))
4031 (set (match_dup 0)
4032 (compare:CC (match_dup 3)
4033 (const_int 0)))]
4034 "")
4036 (define_insn "*rotlsi3_internal9"
4037 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4038 (compare:CC (zero_extend:SI
4039 (subreg:QI
4040 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4041 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4042 (const_int 0)))
4043 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4044 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4045 ""
4046 "@
4047 {rlnm.|rlwnm.} %0,%1,%2,0xff
4048 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4049 #
4050 #"
4051 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4052 (set_attr "length" "4,4,8,8")])
4054 (define_split
4055 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4056 (compare:CC (zero_extend:SI
4057 (subreg:QI
4058 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4059 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4060 (const_int 0)))
4061 (set (match_operand:SI 0 "gpc_reg_operand" "")
4062 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4063 "reload_completed"
4064 [(set (match_dup 0)
4065 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4066 (set (match_dup 3)
4067 (compare:CC (match_dup 0)
4068 (const_int 0)))]
4069 "")
4071 (define_insn "*rotlsi3_internal10"
4072 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4073 (zero_extend:SI
4074 (subreg:HI
4075 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4076 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4077 ""
4078 "@
4079 {rlnm|rlwnm} %0,%1,%2,0xffff
4080 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4081 [(set_attr "type" "var_shift_rotate,integer")])
4084 (define_insn "*rotlsi3_internal11"
4085 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4086 (compare:CC (zero_extend:SI
4087 (subreg:HI
4088 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4089 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4090 (const_int 0)))
4091 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4092 ""
4093 "@
4094 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4095 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4096 #
4097 #"
4098 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4099 (set_attr "length" "4,4,8,8")])
4101 (define_split
4102 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4103 (compare:CC (zero_extend:SI
4104 (subreg:HI
4105 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4106 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4107 (const_int 0)))
4108 (clobber (match_scratch:SI 3 ""))]
4109 "reload_completed"
4110 [(set (match_dup 3)
4111 (zero_extend:SI (subreg:HI
4112 (rotate:SI (match_dup 1)
4113 (match_dup 2)) 0)))
4114 (set (match_dup 0)
4115 (compare:CC (match_dup 3)
4116 (const_int 0)))]
4117 "")
4119 (define_insn "*rotlsi3_internal12"
4120 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4121 (compare:CC (zero_extend:SI
4122 (subreg:HI
4123 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4124 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4125 (const_int 0)))
4126 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4127 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4128 ""
4129 "@
4130 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4131 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4132 #
4133 #"
4134 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4135 (set_attr "length" "4,4,8,8")])
4137 (define_split
4138 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4139 (compare:CC (zero_extend:SI
4140 (subreg:HI
4141 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4142 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4143 (const_int 0)))
4144 (set (match_operand:SI 0 "gpc_reg_operand" "")
4145 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4146 "reload_completed"
4147 [(set (match_dup 0)
4148 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4149 (set (match_dup 3)
4150 (compare:CC (match_dup 0)
4151 (const_int 0)))]
4152 "")
4154 ;; Note that we use "sle." instead of "sl." so that we can set
4155 ;; SHIFT_COUNT_TRUNCATED.
4157 (define_expand "ashlsi3"
4158 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4159 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4160 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4161 ""
4162 "
4163 {
4164 if (TARGET_POWER)
4165 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4166 else
4167 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4168 DONE;
4169 }")
4171 (define_insn "ashlsi3_power"
4172 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4173 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4174 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4175 (clobber (match_scratch:SI 3 "=q,X"))]
4176 "TARGET_POWER"
4177 "@
4178 sle %0,%1,%2
4179 {sli|slwi} %0,%1,%h2")
4181 (define_insn "ashlsi3_no_power"
4182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4183 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4184 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4185 "! TARGET_POWER"
4186 "@
4187 {sl|slw} %0,%1,%2
4188 {sli|slwi} %0,%1,%h2"
4189 [(set_attr "type" "var_shift_rotate,shift")])
4191 (define_insn ""
4192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4193 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4194 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4195 (const_int 0)))
4196 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4197 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4198 "TARGET_POWER"
4199 "@
4200 sle. %3,%1,%2
4201 {sli.|slwi.} %3,%1,%h2
4202 #
4203 #"
4204 [(set_attr "type" "delayed_compare")
4205 (set_attr "length" "4,4,8,8")])
4207 (define_split
4208 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4209 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4210 (match_operand:SI 2 "reg_or_cint_operand" ""))
4211 (const_int 0)))
4212 (clobber (match_scratch:SI 3 ""))
4213 (clobber (match_scratch:SI 4 ""))]
4214 "TARGET_POWER && reload_completed"
4215 [(parallel [(set (match_dup 3)
4216 (ashift:SI (match_dup 1) (match_dup 2)))
4217 (clobber (match_dup 4))])
4218 (set (match_dup 0)
4219 (compare:CC (match_dup 3)
4220 (const_int 0)))]
4221 "")
4223 (define_insn ""
4224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4225 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4226 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4227 (const_int 0)))
4228 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4229 "! TARGET_POWER && TARGET_32BIT"
4230 "@
4231 {sl.|slw.} %3,%1,%2
4232 {sli.|slwi.} %3,%1,%h2
4233 #
4234 #"
4235 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4236 (set_attr "length" "4,4,8,8")])
4238 (define_split
4239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4240 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4241 (match_operand:SI 2 "reg_or_cint_operand" ""))
4242 (const_int 0)))
4243 (clobber (match_scratch:SI 3 ""))]
4244 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4245 [(set (match_dup 3)
4246 (ashift:SI (match_dup 1) (match_dup 2)))
4247 (set (match_dup 0)
4248 (compare:CC (match_dup 3)
4249 (const_int 0)))]
4250 "")
4252 (define_insn ""
4253 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4254 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4255 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4256 (const_int 0)))
4257 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4258 (ashift:SI (match_dup 1) (match_dup 2)))
4259 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4260 "TARGET_POWER"
4261 "@
4262 sle. %0,%1,%2
4263 {sli.|slwi.} %0,%1,%h2
4264 #
4265 #"
4266 [(set_attr "type" "delayed_compare")
4267 (set_attr "length" "4,4,8,8")])
4269 (define_split
4270 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4271 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4272 (match_operand:SI 2 "reg_or_cint_operand" ""))
4273 (const_int 0)))
4274 (set (match_operand:SI 0 "gpc_reg_operand" "")
4275 (ashift:SI (match_dup 1) (match_dup 2)))
4276 (clobber (match_scratch:SI 4 ""))]
4277 "TARGET_POWER && reload_completed"
4278 [(parallel [(set (match_dup 0)
4279 (ashift:SI (match_dup 1) (match_dup 2)))
4280 (clobber (match_dup 4))])
4281 (set (match_dup 3)
4282 (compare:CC (match_dup 0)
4283 (const_int 0)))]
4284 "")
4286 (define_insn ""
4287 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4288 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4289 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4290 (const_int 0)))
4291 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4292 (ashift:SI (match_dup 1) (match_dup 2)))]
4293 "! TARGET_POWER && TARGET_32BIT"
4294 "@
4295 {sl.|slw.} %0,%1,%2
4296 {sli.|slwi.} %0,%1,%h2
4297 #
4298 #"
4299 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4300 (set_attr "length" "4,4,8,8")])
4302 (define_split
4303 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4304 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4305 (match_operand:SI 2 "reg_or_cint_operand" ""))
4306 (const_int 0)))
4307 (set (match_operand:SI 0 "gpc_reg_operand" "")
4308 (ashift:SI (match_dup 1) (match_dup 2)))]
4309 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4310 [(set (match_dup 0)
4311 (ashift:SI (match_dup 1) (match_dup 2)))
4312 (set (match_dup 3)
4313 (compare:CC (match_dup 0)
4314 (const_int 0)))]
4315 "")
4317 (define_insn "rlwinm"
4318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4319 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4320 (match_operand:SI 2 "const_int_operand" "i"))
4321 (match_operand:SI 3 "mask_operand" "n")))]
4322 "includes_lshift_p (operands[2], operands[3])"
4323 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4325 (define_insn ""
4326 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4327 (compare:CC
4328 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4329 (match_operand:SI 2 "const_int_operand" "i,i"))
4330 (match_operand:SI 3 "mask_operand" "n,n"))
4331 (const_int 0)))
4332 (clobber (match_scratch:SI 4 "=r,r"))]
4333 "includes_lshift_p (operands[2], operands[3])"
4334 "@
4335 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4336 #"
4337 [(set_attr "type" "delayed_compare")
4338 (set_attr "length" "4,8")])
4340 (define_split
4341 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4342 (compare:CC
4343 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4344 (match_operand:SI 2 "const_int_operand" ""))
4345 (match_operand:SI 3 "mask_operand" ""))
4346 (const_int 0)))
4347 (clobber (match_scratch:SI 4 ""))]
4348 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4349 [(set (match_dup 4)
4350 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4351 (match_dup 3)))
4352 (set (match_dup 0)
4353 (compare:CC (match_dup 4)
4354 (const_int 0)))]
4355 "")
4357 (define_insn ""
4358 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4359 (compare:CC
4360 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4361 (match_operand:SI 2 "const_int_operand" "i,i"))
4362 (match_operand:SI 3 "mask_operand" "n,n"))
4363 (const_int 0)))
4364 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4365 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4366 "includes_lshift_p (operands[2], operands[3])"
4367 "@
4368 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4369 #"
4370 [(set_attr "type" "delayed_compare")
4371 (set_attr "length" "4,8")])
4373 (define_split
4374 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4375 (compare:CC
4376 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4377 (match_operand:SI 2 "const_int_operand" ""))
4378 (match_operand:SI 3 "mask_operand" ""))
4379 (const_int 0)))
4380 (set (match_operand:SI 0 "gpc_reg_operand" "")
4381 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4382 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4383 [(set (match_dup 0)
4384 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4385 (set (match_dup 4)
4386 (compare:CC (match_dup 0)
4387 (const_int 0)))]
4388 "")
4390 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4391 ;; "sli x,x,0".
4392 (define_expand "lshrsi3"
4393 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4394 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4395 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4396 ""
4397 "
4398 {
4399 if (TARGET_POWER)
4400 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4401 else
4402 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4403 DONE;
4404 }")
4406 (define_insn "lshrsi3_power"
4407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4408 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4409 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4410 (clobber (match_scratch:SI 3 "=q,X,X"))]
4411 "TARGET_POWER"
4412 "@
4413 sre %0,%1,%2
4414 mr %0,%1
4415 {s%A2i|s%A2wi} %0,%1,%h2")
4417 (define_insn "lshrsi3_no_power"
4418 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4419 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4420 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4421 "! TARGET_POWER"
4422 "@
4423 mr %0,%1
4424 {sr|srw} %0,%1,%2
4425 {sri|srwi} %0,%1,%h2"
4426 [(set_attr "type" "integer,var_shift_rotate,shift")])
4428 (define_insn ""
4429 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4430 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4431 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4432 (const_int 0)))
4433 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4434 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4435 "TARGET_POWER"
4436 "@
4437 sre. %3,%1,%2
4438 mr. %1,%1
4439 {s%A2i.|s%A2wi.} %3,%1,%h2
4440 #
4441 #
4442 #"
4443 [(set_attr "type" "delayed_compare")
4444 (set_attr "length" "4,4,4,8,8,8")])
4446 (define_split
4447 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4448 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4449 (match_operand:SI 2 "reg_or_cint_operand" ""))
4450 (const_int 0)))
4451 (clobber (match_scratch:SI 3 ""))
4452 (clobber (match_scratch:SI 4 ""))]
4453 "TARGET_POWER && reload_completed"
4454 [(parallel [(set (match_dup 3)
4455 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4456 (clobber (match_dup 4))])
4457 (set (match_dup 0)
4458 (compare:CC (match_dup 3)
4459 (const_int 0)))]
4460 "")
4462 (define_insn ""
4463 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4464 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4465 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4466 (const_int 0)))
4467 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4468 "! TARGET_POWER && TARGET_32BIT"
4469 "@
4470 mr. %1,%1
4471 {sr.|srw.} %3,%1,%2
4472 {sri.|srwi.} %3,%1,%h2
4473 #
4474 #
4475 #"
4476 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4477 (set_attr "length" "4,4,4,8,8,8")])
4479 (define_split
4480 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4481 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4482 (match_operand:SI 2 "reg_or_cint_operand" ""))
4483 (const_int 0)))
4484 (clobber (match_scratch:SI 3 ""))]
4485 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4486 [(set (match_dup 3)
4487 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4488 (set (match_dup 0)
4489 (compare:CC (match_dup 3)
4490 (const_int 0)))]
4491 "")
4493 (define_insn ""
4494 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4495 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4496 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4497 (const_int 0)))
4498 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4499 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4500 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4501 "TARGET_POWER"
4502 "@
4503 sre. %0,%1,%2
4504 mr. %0,%1
4505 {s%A2i.|s%A2wi.} %0,%1,%h2
4506 #
4507 #
4508 #"
4509 [(set_attr "type" "delayed_compare")
4510 (set_attr "length" "4,4,4,8,8,8")])
4512 (define_split
4513 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4514 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4515 (match_operand:SI 2 "reg_or_cint_operand" ""))
4516 (const_int 0)))
4517 (set (match_operand:SI 0 "gpc_reg_operand" "")
4518 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4519 (clobber (match_scratch:SI 4 ""))]
4520 "TARGET_POWER && reload_completed"
4521 [(parallel [(set (match_dup 0)
4522 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4523 (clobber (match_dup 4))])
4524 (set (match_dup 3)
4525 (compare:CC (match_dup 0)
4526 (const_int 0)))]
4527 "")
4529 (define_insn ""
4530 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4531 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4532 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4533 (const_int 0)))
4534 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4535 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4536 "! TARGET_POWER && TARGET_32BIT"
4537 "@
4538 mr. %0,%1
4539 {sr.|srw.} %0,%1,%2
4540 {sri.|srwi.} %0,%1,%h2
4541 #
4542 #
4543 #"
4544 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4545 (set_attr "length" "4,4,4,8,8,8")])
4547 (define_split
4548 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4549 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4550 (match_operand:SI 2 "reg_or_cint_operand" ""))
4551 (const_int 0)))
4552 (set (match_operand:SI 0 "gpc_reg_operand" "")
4553 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4554 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4555 [(set (match_dup 0)
4556 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4557 (set (match_dup 3)
4558 (compare:CC (match_dup 0)
4559 (const_int 0)))]
4560 "")
4562 (define_insn ""
4563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4564 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4565 (match_operand:SI 2 "const_int_operand" "i"))
4566 (match_operand:SI 3 "mask_operand" "n")))]
4567 "includes_rshift_p (operands[2], operands[3])"
4568 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4570 (define_insn ""
4571 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4572 (compare:CC
4573 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4574 (match_operand:SI 2 "const_int_operand" "i,i"))
4575 (match_operand:SI 3 "mask_operand" "n,n"))
4576 (const_int 0)))
4577 (clobber (match_scratch:SI 4 "=r,r"))]
4578 "includes_rshift_p (operands[2], operands[3])"
4579 "@
4580 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4581 #"
4582 [(set_attr "type" "delayed_compare")
4583 (set_attr "length" "4,8")])
4585 (define_split
4586 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4587 (compare:CC
4588 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4589 (match_operand:SI 2 "const_int_operand" ""))
4590 (match_operand:SI 3 "mask_operand" ""))
4591 (const_int 0)))
4592 (clobber (match_scratch:SI 4 ""))]
4593 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4594 [(set (match_dup 4)
4595 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4596 (match_dup 3)))
4597 (set (match_dup 0)
4598 (compare:CC (match_dup 4)
4599 (const_int 0)))]
4600 "")
4602 (define_insn ""
4603 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4604 (compare:CC
4605 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4606 (match_operand:SI 2 "const_int_operand" "i,i"))
4607 (match_operand:SI 3 "mask_operand" "n,n"))
4608 (const_int 0)))
4609 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4610 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4611 "includes_rshift_p (operands[2], operands[3])"
4612 "@
4613 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4614 #"
4615 [(set_attr "type" "delayed_compare")
4616 (set_attr "length" "4,8")])
4618 (define_split
4619 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4620 (compare:CC
4621 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4622 (match_operand:SI 2 "const_int_operand" ""))
4623 (match_operand:SI 3 "mask_operand" ""))
4624 (const_int 0)))
4625 (set (match_operand:SI 0 "gpc_reg_operand" "")
4626 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4627 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4628 [(set (match_dup 0)
4629 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4630 (set (match_dup 4)
4631 (compare:CC (match_dup 0)
4632 (const_int 0)))]
4633 "")
4635 (define_insn ""
4636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4637 (zero_extend:SI
4638 (subreg:QI
4639 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4640 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4641 "includes_rshift_p (operands[2], GEN_INT (255))"
4642 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4644 (define_insn ""
4645 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4646 (compare:CC
4647 (zero_extend:SI
4648 (subreg:QI
4649 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4650 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4651 (const_int 0)))
4652 (clobber (match_scratch:SI 3 "=r,r"))]
4653 "includes_rshift_p (operands[2], GEN_INT (255))"
4654 "@
4655 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4656 #"
4657 [(set_attr "type" "delayed_compare")
4658 (set_attr "length" "4,8")])
4660 (define_split
4661 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4662 (compare:CC
4663 (zero_extend:SI
4664 (subreg:QI
4665 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4666 (match_operand:SI 2 "const_int_operand" "")) 0))
4667 (const_int 0)))
4668 (clobber (match_scratch:SI 3 ""))]
4669 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4670 [(set (match_dup 3)
4671 (zero_extend:SI (subreg:QI
4672 (lshiftrt:SI (match_dup 1)
4673 (match_dup 2)) 0)))
4674 (set (match_dup 0)
4675 (compare:CC (match_dup 3)
4676 (const_int 0)))]
4677 "")
4679 (define_insn ""
4680 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4681 (compare:CC
4682 (zero_extend:SI
4683 (subreg:QI
4684 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4685 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4686 (const_int 0)))
4687 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4688 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4689 "includes_rshift_p (operands[2], GEN_INT (255))"
4690 "@
4691 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4692 #"
4693 [(set_attr "type" "delayed_compare")
4694 (set_attr "length" "4,8")])
4696 (define_split
4697 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4698 (compare:CC
4699 (zero_extend:SI
4700 (subreg:QI
4701 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4702 (match_operand:SI 2 "const_int_operand" "")) 0))
4703 (const_int 0)))
4704 (set (match_operand:SI 0 "gpc_reg_operand" "")
4705 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4706 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4707 [(set (match_dup 0)
4708 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4709 (set (match_dup 3)
4710 (compare:CC (match_dup 0)
4711 (const_int 0)))]
4712 "")
4714 (define_insn ""
4715 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4716 (zero_extend:SI
4717 (subreg:HI
4718 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4719 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4720 "includes_rshift_p (operands[2], GEN_INT (65535))"
4721 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4723 (define_insn ""
4724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4725 (compare:CC
4726 (zero_extend:SI
4727 (subreg:HI
4728 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4729 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4730 (const_int 0)))
4731 (clobber (match_scratch:SI 3 "=r,r"))]
4732 "includes_rshift_p (operands[2], GEN_INT (65535))"
4733 "@
4734 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4735 #"
4736 [(set_attr "type" "delayed_compare")
4737 (set_attr "length" "4,8")])
4739 (define_split
4740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4741 (compare:CC
4742 (zero_extend:SI
4743 (subreg:HI
4744 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4745 (match_operand:SI 2 "const_int_operand" "")) 0))
4746 (const_int 0)))
4747 (clobber (match_scratch:SI 3 ""))]
4748 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4749 [(set (match_dup 3)
4750 (zero_extend:SI (subreg:HI
4751 (lshiftrt:SI (match_dup 1)
4752 (match_dup 2)) 0)))
4753 (set (match_dup 0)
4754 (compare:CC (match_dup 3)
4755 (const_int 0)))]
4756 "")
4758 (define_insn ""
4759 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4760 (compare:CC
4761 (zero_extend:SI
4762 (subreg:HI
4763 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4764 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4765 (const_int 0)))
4766 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4767 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4768 "includes_rshift_p (operands[2], GEN_INT (65535))"
4769 "@
4770 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4771 #"
4772 [(set_attr "type" "delayed_compare")
4773 (set_attr "length" "4,8")])
4775 (define_split
4776 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4777 (compare:CC
4778 (zero_extend:SI
4779 (subreg:HI
4780 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4781 (match_operand:SI 2 "const_int_operand" "")) 0))
4782 (const_int 0)))
4783 (set (match_operand:SI 0 "gpc_reg_operand" "")
4784 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4785 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4786 [(set (match_dup 0)
4787 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4788 (set (match_dup 3)
4789 (compare:CC (match_dup 0)
4790 (const_int 0)))]
4791 "")
4793 (define_insn ""
4794 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4795 (const_int 1)
4796 (match_operand:SI 1 "gpc_reg_operand" "r"))
4797 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4798 (const_int 31)))]
4799 "TARGET_POWER"
4800 "rrib %0,%1,%2")
4802 (define_insn ""
4803 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4804 (const_int 1)
4805 (match_operand:SI 1 "gpc_reg_operand" "r"))
4806 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4807 (const_int 31)))]
4808 "TARGET_POWER"
4809 "rrib %0,%1,%2")
4811 (define_insn ""
4812 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4813 (const_int 1)
4814 (match_operand:SI 1 "gpc_reg_operand" "r"))
4815 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4816 (const_int 1)
4817 (const_int 0)))]
4818 "TARGET_POWER"
4819 "rrib %0,%1,%2")
4821 (define_expand "ashrsi3"
4822 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4823 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4824 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4825 ""
4826 "
4827 {
4828 if (TARGET_POWER)
4829 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4830 else
4831 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4832 DONE;
4833 }")
4835 (define_insn "ashrsi3_power"
4836 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4837 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4838 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4839 (clobber (match_scratch:SI 3 "=q,X"))]
4840 "TARGET_POWER"
4841 "@
4842 srea %0,%1,%2
4843 {srai|srawi} %0,%1,%h2"
4844 [(set_attr "type" "shift")])
4846 (define_insn "ashrsi3_no_power"
4847 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4848 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4849 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4850 "! TARGET_POWER"
4851 "@
4852 {sra|sraw} %0,%1,%2
4853 {srai|srawi} %0,%1,%h2"
4854 [(set_attr "type" "var_shift_rotate,shift")])
4856 (define_insn ""
4857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4858 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4859 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4860 (const_int 0)))
4861 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4862 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4863 "TARGET_POWER"
4864 "@
4865 srea. %3,%1,%2
4866 {srai.|srawi.} %3,%1,%h2
4867 #
4868 #"
4869 [(set_attr "type" "delayed_compare")
4870 (set_attr "length" "4,4,8,8")])
4872 (define_split
4873 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4874 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4875 (match_operand:SI 2 "reg_or_cint_operand" ""))
4876 (const_int 0)))
4877 (clobber (match_scratch:SI 3 ""))
4878 (clobber (match_scratch:SI 4 ""))]
4879 "TARGET_POWER && reload_completed"
4880 [(parallel [(set (match_dup 3)
4881 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4882 (clobber (match_dup 4))])
4883 (set (match_dup 0)
4884 (compare:CC (match_dup 3)
4885 (const_int 0)))]
4886 "")
4888 (define_insn ""
4889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4890 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4891 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4892 (const_int 0)))
4893 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4894 "! TARGET_POWER"
4895 "@
4896 {sra.|sraw.} %3,%1,%2
4897 {srai.|srawi.} %3,%1,%h2
4898 #
4899 #"
4900 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4901 (set_attr "length" "4,4,8,8")])
4903 (define_split
4904 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4905 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4906 (match_operand:SI 2 "reg_or_cint_operand" ""))
4907 (const_int 0)))
4908 (clobber (match_scratch:SI 3 ""))]
4909 "! TARGET_POWER && reload_completed"
4910 [(set (match_dup 3)
4911 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4912 (set (match_dup 0)
4913 (compare:CC (match_dup 3)
4914 (const_int 0)))]
4915 "")
4917 (define_insn ""
4918 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4919 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4920 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4921 (const_int 0)))
4922 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4923 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4924 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4925 "TARGET_POWER"
4926 "@
4927 srea. %0,%1,%2
4928 {srai.|srawi.} %0,%1,%h2
4929 #
4930 #"
4931 [(set_attr "type" "delayed_compare")
4932 (set_attr "length" "4,4,8,8")])
4934 (define_split
4935 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4936 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4937 (match_operand:SI 2 "reg_or_cint_operand" ""))
4938 (const_int 0)))
4939 (set (match_operand:SI 0 "gpc_reg_operand" "")
4940 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4941 (clobber (match_scratch:SI 4 ""))]
4942 "TARGET_POWER && reload_completed"
4943 [(parallel [(set (match_dup 0)
4944 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4945 (clobber (match_dup 4))])
4946 (set (match_dup 3)
4947 (compare:CC (match_dup 0)
4948 (const_int 0)))]
4949 "")
4951 (define_insn ""
4952 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4953 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4954 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4955 (const_int 0)))
4956 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4957 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4958 "! TARGET_POWER"
4959 "@
4960 {sra.|sraw.} %0,%1,%2
4961 {srai.|srawi.} %0,%1,%h2
4962 #
4963 #"
4964 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4965 (set_attr "length" "4,4,8,8")])
4966 \f
4967 (define_split
4968 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4969 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4970 (match_operand:SI 2 "reg_or_cint_operand" ""))
4971 (const_int 0)))
4972 (set (match_operand:SI 0 "gpc_reg_operand" "")
4973 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4974 "! TARGET_POWER && reload_completed"
4975 [(set (match_dup 0)
4976 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4977 (set (match_dup 3)
4978 (compare:CC (match_dup 0)
4979 (const_int 0)))]
4980 "")
4982 ;; Floating-point insns, excluding normal data motion.
4983 ;;
4984 ;; PowerPC has a full set of single-precision floating point instructions.
4985 ;;
4986 ;; For the POWER architecture, we pretend that we have both SFmode and
4987 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4988 ;; The only conversions we will do will be when storing to memory. In that
4989 ;; case, we will use the "frsp" instruction before storing.
4990 ;;
4991 ;; Note that when we store into a single-precision memory location, we need to
4992 ;; use the frsp insn first. If the register being stored isn't dead, we
4993 ;; need a scratch register for the frsp. But this is difficult when the store
4994 ;; is done by reload. It is not incorrect to do the frsp on the register in
4995 ;; this case, we just lose precision that we would have otherwise gotten but
4996 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4998 (define_expand "extendsfdf2"
4999 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5000 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5001 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5002 "")
5004 (define_insn_and_split "*extendsfdf2_fpr"
5005 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5006 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5007 "TARGET_HARD_FLOAT && TARGET_FPRS"
5008 "@
5009 #
5010 fmr %0,%1
5011 lfs%U1%X1 %0,%1"
5012 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5013 [(const_int 0)]
5014 {
5015 emit_note (NOTE_INSN_DELETED);
5016 DONE;
5017 }
5018 [(set_attr "type" "fp,fp,fpload")])
5020 (define_expand "truncdfsf2"
5021 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5022 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5023 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5024 "")
5026 (define_insn "*truncdfsf2_fpr"
5027 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5028 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5029 "TARGET_HARD_FLOAT && TARGET_FPRS"
5030 "frsp %0,%1"
5031 [(set_attr "type" "fp")])
5033 (define_insn "aux_truncdfsf2"
5034 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5035 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5036 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5037 "frsp %0,%1"
5038 [(set_attr "type" "fp")])
5040 (define_expand "negsf2"
5041 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5042 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5043 "TARGET_HARD_FLOAT"
5044 "")
5046 (define_insn "*negsf2"
5047 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5048 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5049 "TARGET_HARD_FLOAT && TARGET_FPRS"
5050 "fneg %0,%1"
5051 [(set_attr "type" "fp")])
5053 (define_expand "abssf2"
5054 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5055 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5056 "TARGET_HARD_FLOAT"
5057 "")
5059 (define_insn "*abssf2"
5060 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5061 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5062 "TARGET_HARD_FLOAT && TARGET_FPRS"
5063 "fabs %0,%1"
5064 [(set_attr "type" "fp")])
5066 (define_insn ""
5067 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5068 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5069 "TARGET_HARD_FLOAT && TARGET_FPRS"
5070 "fnabs %0,%1"
5071 [(set_attr "type" "fp")])
5073 (define_expand "addsf3"
5074 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5075 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5076 (match_operand:SF 2 "gpc_reg_operand" "")))]
5077 "TARGET_HARD_FLOAT"
5078 "")
5080 (define_insn ""
5081 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5082 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5083 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5084 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5085 "fadds %0,%1,%2"
5086 [(set_attr "type" "fp")])
5088 (define_insn ""
5089 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5090 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5091 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5092 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5093 "{fa|fadd} %0,%1,%2"
5094 [(set_attr "type" "fp")])
5096 (define_expand "subsf3"
5097 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5098 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5099 (match_operand:SF 2 "gpc_reg_operand" "")))]
5100 "TARGET_HARD_FLOAT"
5101 "")
5103 (define_insn ""
5104 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5105 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5106 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5107 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5108 "fsubs %0,%1,%2"
5109 [(set_attr "type" "fp")])
5111 (define_insn ""
5112 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5113 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5114 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5115 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5116 "{fs|fsub} %0,%1,%2"
5117 [(set_attr "type" "fp")])
5119 (define_expand "mulsf3"
5120 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5121 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5122 (match_operand:SF 2 "gpc_reg_operand" "")))]
5123 "TARGET_HARD_FLOAT"
5124 "")
5126 (define_insn ""
5127 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5128 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5129 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5130 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5131 "fmuls %0,%1,%2"
5132 [(set_attr "type" "fp")])
5134 (define_insn ""
5135 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5136 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5137 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5138 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5139 "{fm|fmul} %0,%1,%2"
5140 [(set_attr "type" "dmul")])
5142 (define_insn "fres"
5143 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5144 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5145 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5146 "fres %0,%1"
5147 [(set_attr "type" "fp")])
5149 (define_expand "divsf3"
5150 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5151 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5152 (match_operand:SF 2 "gpc_reg_operand" "")))]
5153 "TARGET_HARD_FLOAT"
5154 {
5155 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5156 && flag_finite_math_only && !flag_trapping_math)
5157 {
5158 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5159 DONE;
5160 }
5161 })
5163 (define_insn ""
5164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5165 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5166 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5167 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5168 "fdivs %0,%1,%2"
5169 [(set_attr "type" "sdiv")])
5171 (define_insn ""
5172 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5173 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5174 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5175 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5176 "{fd|fdiv} %0,%1,%2"
5177 [(set_attr "type" "ddiv")])
5179 (define_insn ""
5180 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5181 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5182 (match_operand:SF 2 "gpc_reg_operand" "f"))
5183 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5184 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5185 "fmadds %0,%1,%2,%3"
5186 [(set_attr "type" "fp")])
5188 (define_insn ""
5189 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5190 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5191 (match_operand:SF 2 "gpc_reg_operand" "f"))
5192 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5193 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5194 "{fma|fmadd} %0,%1,%2,%3"
5195 [(set_attr "type" "dmul")])
5197 (define_insn ""
5198 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5199 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5200 (match_operand:SF 2 "gpc_reg_operand" "f"))
5201 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5202 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5203 "fmsubs %0,%1,%2,%3"
5204 [(set_attr "type" "fp")])
5206 (define_insn ""
5207 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5208 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5209 (match_operand:SF 2 "gpc_reg_operand" "f"))
5210 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5211 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5212 "{fms|fmsub} %0,%1,%2,%3"
5213 [(set_attr "type" "dmul")])
5215 (define_insn ""
5216 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5217 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5218 (match_operand:SF 2 "gpc_reg_operand" "f"))
5219 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5220 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5221 && HONOR_SIGNED_ZEROS (SFmode)"
5222 "fnmadds %0,%1,%2,%3"
5223 [(set_attr "type" "fp")])
5225 (define_insn ""
5226 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5227 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5228 (match_operand:SF 2 "gpc_reg_operand" "f"))
5229 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5230 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5231 && ! HONOR_SIGNED_ZEROS (SFmode)"
5232 "fnmadds %0,%1,%2,%3"
5233 [(set_attr "type" "fp")])
5235 (define_insn ""
5236 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5237 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5238 (match_operand:SF 2 "gpc_reg_operand" "f"))
5239 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5240 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5241 "{fnma|fnmadd} %0,%1,%2,%3"
5242 [(set_attr "type" "dmul")])
5244 (define_insn ""
5245 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5246 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5247 (match_operand:SF 2 "gpc_reg_operand" "f"))
5248 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5249 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5250 && ! HONOR_SIGNED_ZEROS (SFmode)"
5251 "{fnma|fnmadd} %0,%1,%2,%3"
5252 [(set_attr "type" "dmul")])
5254 (define_insn ""
5255 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5256 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5257 (match_operand:SF 2 "gpc_reg_operand" "f"))
5258 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5259 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5260 && HONOR_SIGNED_ZEROS (SFmode)"
5261 "fnmsubs %0,%1,%2,%3"
5262 [(set_attr "type" "fp")])
5264 (define_insn ""
5265 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5266 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5267 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5268 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5269 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5270 && ! HONOR_SIGNED_ZEROS (SFmode)"
5271 "fnmsubs %0,%1,%2,%3"
5272 [(set_attr "type" "fp")])
5274 (define_insn ""
5275 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5276 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5277 (match_operand:SF 2 "gpc_reg_operand" "f"))
5278 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5279 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5280 "{fnms|fnmsub} %0,%1,%2,%3"
5281 [(set_attr "type" "dmul")])
5283 (define_insn ""
5284 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5285 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5286 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5287 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5288 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5289 && ! HONOR_SIGNED_ZEROS (SFmode)"
5290 "{fnms|fnmsub} %0,%1,%2,%3"
5291 [(set_attr "type" "dmul")])
5293 (define_expand "sqrtsf2"
5294 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5295 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5296 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5297 "")
5299 (define_insn ""
5300 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5301 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5302 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5303 "fsqrts %0,%1"
5304 [(set_attr "type" "ssqrt")])
5306 (define_insn ""
5307 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5308 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5309 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5310 "fsqrt %0,%1"
5311 [(set_attr "type" "dsqrt")])
5313 (define_expand "copysignsf3"
5314 [(set (match_dup 3)
5315 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5316 (set (match_dup 4)
5317 (neg:SF (abs:SF (match_dup 1))))
5318 (set (match_operand:SF 0 "gpc_reg_operand" "")
5319 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5320 (match_dup 5))
5321 (match_dup 3)
5322 (match_dup 4)))]
5323 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5324 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5325 {
5326 operands[3] = gen_reg_rtx (SFmode);
5327 operands[4] = gen_reg_rtx (SFmode);
5328 operands[5] = CONST0_RTX (SFmode);
5329 })
5331 (define_expand "copysigndf3"
5332 [(set (match_dup 3)
5333 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5334 (set (match_dup 4)
5335 (neg:DF (abs:DF (match_dup 1))))
5336 (set (match_operand:DF 0 "gpc_reg_operand" "")
5337 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5338 (match_dup 5))
5339 (match_dup 3)
5340 (match_dup 4)))]
5341 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5342 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5343 {
5344 operands[3] = gen_reg_rtx (DFmode);
5345 operands[4] = gen_reg_rtx (DFmode);
5346 operands[5] = CONST0_RTX (DFmode);
5347 })
5349 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5350 ;; fsel instruction and some auxiliary computations. Then we just have a
5351 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5352 ;; combine.
5353 (define_expand "smaxsf3"
5354 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5355 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5356 (match_operand:SF 2 "gpc_reg_operand" ""))
5357 (match_dup 1)
5358 (match_dup 2)))]
5359 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5360 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5362 (define_expand "sminsf3"
5363 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5364 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5365 (match_operand:SF 2 "gpc_reg_operand" ""))
5366 (match_dup 2)
5367 (match_dup 1)))]
5368 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5369 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5371 (define_split
5372 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5373 (match_operator:SF 3 "min_max_operator"
5374 [(match_operand:SF 1 "gpc_reg_operand" "")
5375 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5376 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5377 [(const_int 0)]
5378 "
5379 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5380 operands[1], operands[2]);
5381 DONE;
5382 }")
5384 (define_expand "movsicc"
5385 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5386 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5387 (match_operand:SI 2 "gpc_reg_operand" "")
5388 (match_operand:SI 3 "gpc_reg_operand" "")))]
5389 "TARGET_ISEL"
5390 "
5391 {
5392 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5393 DONE;
5394 else
5395 FAIL;
5396 }")
5398 ;; We use the BASE_REGS for the isel input operands because, if rA is
5399 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5400 ;; because we may switch the operands and rB may end up being rA.
5401 ;;
5402 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5403 ;; leave out the mode in operand 4 and use one pattern, but reload can
5404 ;; change the mode underneath our feet and then gets confused trying
5405 ;; to reload the value.
5406 (define_insn "isel_signed"
5407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5408 (if_then_else:SI
5409 (match_operator 1 "comparison_operator"
5410 [(match_operand:CC 4 "cc_reg_operand" "y")
5411 (const_int 0)])
5412 (match_operand:SI 2 "gpc_reg_operand" "b")
5413 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5414 "TARGET_ISEL"
5415 "*
5416 { return output_isel (operands); }"
5417 [(set_attr "length" "4")])
5419 (define_insn "isel_unsigned"
5420 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5421 (if_then_else:SI
5422 (match_operator 1 "comparison_operator"
5423 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5424 (const_int 0)])
5425 (match_operand:SI 2 "gpc_reg_operand" "b")
5426 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5427 "TARGET_ISEL"
5428 "*
5429 { return output_isel (operands); }"
5430 [(set_attr "length" "4")])
5432 (define_expand "movsfcc"
5433 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5434 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5435 (match_operand:SF 2 "gpc_reg_operand" "")
5436 (match_operand:SF 3 "gpc_reg_operand" "")))]
5437 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5438 "
5439 {
5440 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5441 DONE;
5442 else
5443 FAIL;
5444 }")
5446 (define_insn "*fselsfsf4"
5447 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5448 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5449 (match_operand:SF 4 "zero_fp_constant" "F"))
5450 (match_operand:SF 2 "gpc_reg_operand" "f")
5451 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5452 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5453 "fsel %0,%1,%2,%3"
5454 [(set_attr "type" "fp")])
5456 (define_insn "*fseldfsf4"
5457 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5458 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5459 (match_operand:DF 4 "zero_fp_constant" "F"))
5460 (match_operand:SF 2 "gpc_reg_operand" "f")
5461 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5462 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5463 "fsel %0,%1,%2,%3"
5464 [(set_attr "type" "fp")])
5466 (define_expand "negdf2"
5467 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5468 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5469 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5470 "")
5472 (define_insn "*negdf2_fpr"
5473 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5474 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5475 "TARGET_HARD_FLOAT && TARGET_FPRS"
5476 "fneg %0,%1"
5477 [(set_attr "type" "fp")])
5479 (define_expand "absdf2"
5480 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5481 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5482 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5483 "")
5485 (define_insn "*absdf2_fpr"
5486 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5487 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5488 "TARGET_HARD_FLOAT && TARGET_FPRS"
5489 "fabs %0,%1"
5490 [(set_attr "type" "fp")])
5492 (define_insn "*nabsdf2_fpr"
5493 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5494 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5495 "TARGET_HARD_FLOAT && TARGET_FPRS"
5496 "fnabs %0,%1"
5497 [(set_attr "type" "fp")])
5499 (define_expand "adddf3"
5500 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5501 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5502 (match_operand:DF 2 "gpc_reg_operand" "")))]
5503 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5504 "")
5506 (define_insn "*adddf3_fpr"
5507 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5508 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5509 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5510 "TARGET_HARD_FLOAT && TARGET_FPRS"
5511 "{fa|fadd} %0,%1,%2"
5512 [(set_attr "type" "fp")])
5514 (define_expand "subdf3"
5515 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5516 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5517 (match_operand:DF 2 "gpc_reg_operand" "")))]
5518 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5519 "")
5521 (define_insn "*subdf3_fpr"
5522 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5523 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5524 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5525 "TARGET_HARD_FLOAT && TARGET_FPRS"
5526 "{fs|fsub} %0,%1,%2"
5527 [(set_attr "type" "fp")])
5529 (define_expand "muldf3"
5530 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5531 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5532 (match_operand:DF 2 "gpc_reg_operand" "")))]
5533 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5534 "")
5536 (define_insn "*muldf3_fpr"
5537 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5538 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5539 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5540 "TARGET_HARD_FLOAT && TARGET_FPRS"
5541 "{fm|fmul} %0,%1,%2"
5542 [(set_attr "type" "dmul")])
5544 (define_insn "fred"
5545 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5546 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5547 "TARGET_POPCNTB && flag_finite_math_only"
5548 "fre %0,%1"
5549 [(set_attr "type" "fp")])
5551 (define_expand "divdf3"
5552 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5553 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5554 (match_operand:DF 2 "gpc_reg_operand" "")))]
5555 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5556 {
5557 if (swdiv && !optimize_size && TARGET_POPCNTB
5558 && flag_finite_math_only && !flag_trapping_math)
5559 {
5560 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5561 DONE;
5562 }
5563 })
5565 (define_insn "*divdf3_fpr"
5566 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5567 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5568 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5569 "TARGET_HARD_FLOAT && TARGET_FPRS"
5570 "{fd|fdiv} %0,%1,%2"
5571 [(set_attr "type" "ddiv")])
5573 (define_insn ""
5574 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5575 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5576 (match_operand:DF 2 "gpc_reg_operand" "f"))
5577 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5578 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5579 "{fma|fmadd} %0,%1,%2,%3"
5580 [(set_attr "type" "dmul")])
5582 (define_insn ""
5583 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5584 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5585 (match_operand:DF 2 "gpc_reg_operand" "f"))
5586 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5587 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5588 "{fms|fmsub} %0,%1,%2,%3"
5589 [(set_attr "type" "dmul")])
5591 (define_insn ""
5592 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5593 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5594 (match_operand:DF 2 "gpc_reg_operand" "f"))
5595 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5596 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5597 && HONOR_SIGNED_ZEROS (DFmode)"
5598 "{fnma|fnmadd} %0,%1,%2,%3"
5599 [(set_attr "type" "dmul")])
5601 (define_insn ""
5602 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5603 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5604 (match_operand:DF 2 "gpc_reg_operand" "f"))
5605 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5606 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5607 && ! HONOR_SIGNED_ZEROS (DFmode)"
5608 "{fnma|fnmadd} %0,%1,%2,%3"
5609 [(set_attr "type" "dmul")])
5611 (define_insn ""
5612 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5613 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5614 (match_operand:DF 2 "gpc_reg_operand" "f"))
5615 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5616 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5617 && HONOR_SIGNED_ZEROS (DFmode)"
5618 "{fnms|fnmsub} %0,%1,%2,%3"
5619 [(set_attr "type" "dmul")])
5621 (define_insn ""
5622 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5623 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5624 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5625 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5626 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5627 && ! HONOR_SIGNED_ZEROS (DFmode)"
5628 "{fnms|fnmsub} %0,%1,%2,%3"
5629 [(set_attr "type" "dmul")])
5631 (define_insn "sqrtdf2"
5632 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5633 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5634 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5635 "fsqrt %0,%1"
5636 [(set_attr "type" "dsqrt")])
5638 ;; The conditional move instructions allow us to perform max and min
5639 ;; operations even when
5641 (define_expand "smaxdf3"
5642 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5643 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5644 (match_operand:DF 2 "gpc_reg_operand" ""))
5645 (match_dup 1)
5646 (match_dup 2)))]
5647 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5648 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5650 (define_expand "smindf3"
5651 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5652 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5653 (match_operand:DF 2 "gpc_reg_operand" ""))
5654 (match_dup 2)
5655 (match_dup 1)))]
5656 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5657 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5659 (define_split
5660 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5661 (match_operator:DF 3 "min_max_operator"
5662 [(match_operand:DF 1 "gpc_reg_operand" "")
5663 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5664 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5665 [(const_int 0)]
5666 "
5667 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5668 operands[1], operands[2]);
5669 DONE;
5670 }")
5672 (define_expand "movdfcc"
5673 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5674 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5675 (match_operand:DF 2 "gpc_reg_operand" "")
5676 (match_operand:DF 3 "gpc_reg_operand" "")))]
5677 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5678 "
5679 {
5680 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5681 DONE;
5682 else
5683 FAIL;
5684 }")
5686 (define_insn "*fseldfdf4"
5687 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5688 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5689 (match_operand:DF 4 "zero_fp_constant" "F"))
5690 (match_operand:DF 2 "gpc_reg_operand" "f")
5691 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5692 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5693 "fsel %0,%1,%2,%3"
5694 [(set_attr "type" "fp")])
5696 (define_insn "*fselsfdf4"
5697 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5698 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5699 (match_operand:SF 4 "zero_fp_constant" "F"))
5700 (match_operand:DF 2 "gpc_reg_operand" "f")
5701 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5702 "TARGET_PPC_GFXOPT"
5703 "fsel %0,%1,%2,%3"
5704 [(set_attr "type" "fp")])
5705 \f
5706 ;; Conversions to and from floating-point.
5708 (define_expand "fixuns_truncsfsi2"
5709 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5710 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5711 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5712 "")
5714 (define_expand "fix_truncsfsi2"
5715 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5716 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5717 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5718 "")
5720 ; For each of these conversions, there is a define_expand, a define_insn
5721 ; with a '#' template, and a define_split (with C code). The idea is
5722 ; to allow constant folding with the template of the define_insn,
5723 ; then to have the insns split later (between sched1 and final).
5725 (define_expand "floatsidf2"
5726 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5727 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5728 (use (match_dup 2))
5729 (use (match_dup 3))
5730 (clobber (match_dup 4))
5731 (clobber (match_dup 5))
5732 (clobber (match_dup 6))])]
5733 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5734 "
5735 {
5736 if (TARGET_E500_DOUBLE)
5737 {
5738 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5739 DONE;
5740 }
5741 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5742 {
5743 rtx t1 = gen_reg_rtx (DImode);
5744 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5745 DONE;
5746 }
5747 if (TARGET_POWERPC64)
5748 {
5749 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5750 rtx t1 = gen_reg_rtx (DImode);
5751 rtx t2 = gen_reg_rtx (DImode);
5752 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5753 DONE;
5754 }
5756 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5757 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5758 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5759 operands[5] = gen_reg_rtx (DFmode);
5760 operands[6] = gen_reg_rtx (SImode);
5761 }")
5763 (define_insn_and_split "*floatsidf2_internal"
5764 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5765 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5766 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5767 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5768 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5769 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5770 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5771 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5772 "#"
5773 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5774 [(pc)]
5775 "
5776 {
5777 rtx lowword, highword;
5778 gcc_assert (MEM_P (operands[4]));
5779 highword = adjust_address (operands[4], SImode, 0);
5780 lowword = adjust_address (operands[4], SImode, 4);
5781 if (! WORDS_BIG_ENDIAN)
5782 {
5783 rtx tmp;
5784 tmp = highword; highword = lowword; lowword = tmp;
5785 }
5787 emit_insn (gen_xorsi3 (operands[6], operands[1],
5788 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5789 emit_move_insn (lowword, operands[6]);
5790 emit_move_insn (highword, operands[2]);
5791 emit_move_insn (operands[5], operands[4]);
5792 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5793 DONE;
5794 }"
5795 [(set_attr "length" "24")])
5797 (define_expand "floatunssisf2"
5798 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5799 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5800 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5801 "")
5803 (define_expand "floatunssidf2"
5804 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5805 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5806 (use (match_dup 2))
5807 (use (match_dup 3))
5808 (clobber (match_dup 4))
5809 (clobber (match_dup 5))])]
5810 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5811 "
5812 {
5813 if (TARGET_E500_DOUBLE)
5814 {
5815 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5816 DONE;
5817 }
5818 if (TARGET_POWERPC64)
5819 {
5820 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5821 rtx t1 = gen_reg_rtx (DImode);
5822 rtx t2 = gen_reg_rtx (DImode);
5823 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5824 t1, t2));
5825 DONE;
5826 }
5828 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5829 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5830 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5831 operands[5] = gen_reg_rtx (DFmode);
5832 }")
5834 (define_insn_and_split "*floatunssidf2_internal"
5835 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5836 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5837 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5838 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5839 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5840 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5841 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5842 "#"
5843 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5844 [(pc)]
5845 "
5846 {
5847 rtx lowword, highword;
5848 gcc_assert (MEM_P (operands[4]));
5849 highword = adjust_address (operands[4], SImode, 0);
5850 lowword = adjust_address (operands[4], SImode, 4);
5851 if (! WORDS_BIG_ENDIAN)
5852 {
5853 rtx tmp;
5854 tmp = highword; highword = lowword; lowword = tmp;
5855 }
5857 emit_move_insn (lowword, operands[1]);
5858 emit_move_insn (highword, operands[2]);
5859 emit_move_insn (operands[5], operands[4]);
5860 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5861 DONE;
5862 }"
5863 [(set_attr "length" "20")])
5865 (define_expand "fix_truncdfsi2"
5866 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5867 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5868 (clobber (match_dup 2))
5869 (clobber (match_dup 3))])]
5870 "(TARGET_POWER2 || TARGET_POWERPC)
5871 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5872 "
5873 {
5874 if (TARGET_E500_DOUBLE)
5875 {
5876 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5877 DONE;
5878 }
5879 operands[2] = gen_reg_rtx (DImode);
5880 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5881 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5882 {
5883 operands[3] = gen_reg_rtx (DImode);
5884 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5885 operands[2], operands[3]));
5886 DONE;
5887 }
5888 if (TARGET_PPC_GFXOPT)
5889 {
5890 rtx orig_dest = operands[0];
5891 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5892 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5893 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5894 operands[2]));
5895 if (operands[0] != orig_dest)
5896 emit_move_insn (orig_dest, operands[0]);
5897 DONE;
5898 }
5899 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5900 }")
5902 (define_insn_and_split "*fix_truncdfsi2_internal"
5903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5904 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5905 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5906 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5907 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5908 "#"
5909 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5910 [(pc)]
5911 "
5912 {
5913 rtx lowword;
5914 gcc_assert (MEM_P (operands[3]));
5915 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5917 emit_insn (gen_fctiwz (operands[2], operands[1]));
5918 emit_move_insn (operands[3], operands[2]);
5919 emit_move_insn (operands[0], lowword);
5920 DONE;
5921 }"
5922 [(set_attr "length" "16")])
5924 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5925 [(set (match_operand:SI 0 "memory_operand" "=Z")
5926 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5927 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5928 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5929 && TARGET_PPC_GFXOPT"
5930 "#"
5931 "&& 1"
5932 [(pc)]
5933 "
5934 {
5935 emit_insn (gen_fctiwz (operands[2], operands[1]));
5936 emit_insn (gen_stfiwx (operands[0], operands[2]));
5937 DONE;
5938 }"
5939 [(set_attr "length" "16")])
5941 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
5942 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5943 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5944 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5945 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
5946 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
5947 "#"
5948 "&& 1"
5949 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
5950 (set (match_dup 3) (match_dup 2))
5951 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
5952 ""
5953 [(set_attr "length" "12")])
5955 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5956 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5957 ; because the first makes it clear that operand 0 is not live
5958 ; before the instruction.
5959 (define_insn "fctiwz"
5960 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5961 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5962 UNSPEC_FCTIWZ))]
5963 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5964 "{fcirz|fctiwz} %0,%1"
5965 [(set_attr "type" "fp")])
5967 (define_insn "btruncdf2"
5968 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5969 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5970 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5971 "friz %0,%1"
5972 [(set_attr "type" "fp")])
5974 (define_insn "btruncsf2"
5975 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5976 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5977 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5978 "friz %0,%1"
5979 [(set_attr "type" "fp")])
5981 (define_insn "ceildf2"
5982 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5983 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5984 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5985 "frip %0,%1"
5986 [(set_attr "type" "fp")])
5988 (define_insn "ceilsf2"
5989 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5990 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5991 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5992 "frip %0,%1"
5993 [(set_attr "type" "fp")])
5995 (define_insn "floordf2"
5996 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5997 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5998 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5999 "frim %0,%1"
6000 [(set_attr "type" "fp")])
6002 (define_insn "floorsf2"
6003 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6004 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6005 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6006 "frim %0,%1"
6007 [(set_attr "type" "fp")])
6009 (define_insn "rounddf2"
6010 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6011 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6012 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6013 "frin %0,%1"
6014 [(set_attr "type" "fp")])
6016 (define_insn "roundsf2"
6017 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6018 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6019 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6020 "frin %0,%1"
6021 [(set_attr "type" "fp")])
6023 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6024 (define_insn "stfiwx"
6025 [(set (match_operand:SI 0 "memory_operand" "=Z")
6026 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6027 UNSPEC_STFIWX))]
6028 "TARGET_PPC_GFXOPT"
6029 "stfiwx %1,%y0"
6030 [(set_attr "type" "fpstore")])
6032 (define_expand "floatsisf2"
6033 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6034 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6035 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6036 "")
6038 (define_insn "floatdidf2"
6039 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6040 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
6041 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6042 "fcfid %0,%1"
6043 [(set_attr "type" "fp")])
6045 (define_insn_and_split "floatsidf_ppc64_mfpgpr"
6046 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6047 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6048 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6049 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6050 "#"
6051 "&& 1"
6052 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6053 (set (match_dup 0) (float:DF (match_dup 2)))]
6054 "")
6056 (define_insn_and_split "floatsidf_ppc64"
6057 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6058 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6059 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6060 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6061 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6062 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6063 "#"
6064 "&& 1"
6065 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6066 (set (match_dup 2) (match_dup 3))
6067 (set (match_dup 4) (match_dup 2))
6068 (set (match_dup 0) (float:DF (match_dup 4)))]
6069 "")
6071 (define_insn_and_split "floatunssidf_ppc64"
6072 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6073 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6074 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6075 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6076 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6077 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6078 "#"
6079 "&& 1"
6080 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6081 (set (match_dup 2) (match_dup 3))
6082 (set (match_dup 4) (match_dup 2))
6083 (set (match_dup 0) (float:DF (match_dup 4)))]
6084 "")
6086 (define_insn "fix_truncdfdi2"
6087 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
6088 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6089 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6090 "fctidz %0,%1"
6091 [(set_attr "type" "fp")])
6093 (define_expand "floatdisf2"
6094 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6095 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6096 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6097 "
6098 {
6099 rtx val = operands[1];
6100 if (!flag_unsafe_math_optimizations)
6101 {
6102 rtx label = gen_label_rtx ();
6103 val = gen_reg_rtx (DImode);
6104 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6105 emit_label (label);
6106 }
6107 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6108 DONE;
6109 }")
6111 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6112 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6113 ;; from double rounding.
6114 (define_insn_and_split "floatdisf2_internal1"
6115 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6116 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
6117 (clobber (match_scratch:DF 2 "=f"))]
6118 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6119 "#"
6120 "&& reload_completed"
6121 [(set (match_dup 2)
6122 (float:DF (match_dup 1)))
6123 (set (match_dup 0)
6124 (float_truncate:SF (match_dup 2)))]
6125 "")
6127 ;; Twiddles bits to avoid double rounding.
6128 ;; Bits that might be truncated when converting to DFmode are replaced
6129 ;; by a bit that won't be lost at that stage, but is below the SFmode
6130 ;; rounding position.
6131 (define_expand "floatdisf2_internal2"
6132 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6133 (const_int 53)))
6134 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6135 (const_int 2047)))
6136 (clobber (scratch:CC))])
6137 (set (match_dup 3) (plus:DI (match_dup 3)
6138 (const_int 1)))
6139 (set (match_dup 0) (plus:DI (match_dup 0)
6140 (const_int 2047)))
6141 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6142 (const_int 2)))
6143 (set (match_dup 0) (ior:DI (match_dup 0)
6144 (match_dup 1)))
6145 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6146 (const_int -2048)))
6147 (clobber (scratch:CC))])
6148 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6149 (label_ref (match_operand:DI 2 "" ""))
6150 (pc)))
6151 (set (match_dup 0) (match_dup 1))]
6152 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6153 "
6154 {
6155 operands[3] = gen_reg_rtx (DImode);
6156 operands[4] = gen_reg_rtx (CCUNSmode);
6157 }")
6158 \f
6159 ;; Define the DImode operations that can be done in a small number
6160 ;; of instructions. The & constraints are to prevent the register
6161 ;; allocator from allocating registers that overlap with the inputs
6162 ;; (for example, having an input in 7,8 and an output in 6,7). We
6163 ;; also allow for the output being the same as one of the inputs.
6165 (define_insn "*adddi3_noppc64"
6166 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6167 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6168 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6169 "! TARGET_POWERPC64"
6170 "*
6171 {
6172 if (WORDS_BIG_ENDIAN)
6173 return (GET_CODE (operands[2])) != CONST_INT
6174 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6175 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6176 else
6177 return (GET_CODE (operands[2])) != CONST_INT
6178 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6179 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6180 }"
6181 [(set_attr "type" "two")
6182 (set_attr "length" "8")])
6184 (define_insn "*subdi3_noppc64"
6185 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6186 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6187 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6188 "! TARGET_POWERPC64"
6189 "*
6190 {
6191 if (WORDS_BIG_ENDIAN)
6192 return (GET_CODE (operands[1]) != CONST_INT)
6193 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6194 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6195 else
6196 return (GET_CODE (operands[1]) != CONST_INT)
6197 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6198 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6199 }"
6200 [(set_attr "type" "two")
6201 (set_attr "length" "8")])
6203 (define_insn "*negdi2_noppc64"
6204 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6205 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6206 "! TARGET_POWERPC64"
6207 "*
6208 {
6209 return (WORDS_BIG_ENDIAN)
6210 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6211 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6212 }"
6213 [(set_attr "type" "two")
6214 (set_attr "length" "8")])
6216 (define_expand "mulsidi3"
6217 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6218 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6219 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6220 "! TARGET_POWERPC64"
6221 "
6222 {
6223 if (! TARGET_POWER && ! TARGET_POWERPC)
6224 {
6225 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6226 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6227 emit_insn (gen_mull_call ());
6228 if (WORDS_BIG_ENDIAN)
6229 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6230 else
6231 {
6232 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6233 gen_rtx_REG (SImode, 3));
6234 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6235 gen_rtx_REG (SImode, 4));
6236 }
6237 DONE;
6238 }
6239 else if (TARGET_POWER)
6240 {
6241 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6242 DONE;
6243 }
6244 }")
6246 (define_insn "mulsidi3_mq"
6247 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6248 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6249 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6250 (clobber (match_scratch:SI 3 "=q"))]
6251 "TARGET_POWER"
6252 "mul %0,%1,%2\;mfmq %L0"
6253 [(set_attr "type" "imul")
6254 (set_attr "length" "8")])
6256 (define_insn "*mulsidi3_no_mq"
6257 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6258 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6259 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6260 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6261 "*
6262 {
6263 return (WORDS_BIG_ENDIAN)
6264 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6265 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6266 }"
6267 [(set_attr "type" "imul")
6268 (set_attr "length" "8")])
6270 (define_split
6271 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6272 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6273 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6274 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6275 [(set (match_dup 3)
6276 (truncate:SI
6277 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6278 (sign_extend:DI (match_dup 2)))
6279 (const_int 32))))
6280 (set (match_dup 4)
6281 (mult:SI (match_dup 1)
6282 (match_dup 2)))]
6283 "
6284 {
6285 int endian = (WORDS_BIG_ENDIAN == 0);
6286 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6287 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6288 }")
6290 (define_expand "umulsidi3"
6291 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6292 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6293 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6294 "TARGET_POWERPC && ! TARGET_POWERPC64"
6295 "
6296 {
6297 if (TARGET_POWER)
6298 {
6299 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6300 DONE;
6301 }
6302 }")
6304 (define_insn "umulsidi3_mq"
6305 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6306 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6307 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6308 (clobber (match_scratch:SI 3 "=q"))]
6309 "TARGET_POWERPC && TARGET_POWER"
6310 "*
6311 {
6312 return (WORDS_BIG_ENDIAN)
6313 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6314 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6315 }"
6316 [(set_attr "type" "imul")
6317 (set_attr "length" "8")])
6319 (define_insn "*umulsidi3_no_mq"
6320 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6321 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6322 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6323 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6324 "*
6325 {
6326 return (WORDS_BIG_ENDIAN)
6327 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6328 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6329 }"
6330 [(set_attr "type" "imul")
6331 (set_attr "length" "8")])
6333 (define_split
6334 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6335 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6336 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6337 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6338 [(set (match_dup 3)
6339 (truncate:SI
6340 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6341 (zero_extend:DI (match_dup 2)))
6342 (const_int 32))))
6343 (set (match_dup 4)
6344 (mult:SI (match_dup 1)
6345 (match_dup 2)))]
6346 "
6347 {
6348 int endian = (WORDS_BIG_ENDIAN == 0);
6349 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6350 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6351 }")
6353 (define_expand "smulsi3_highpart"
6354 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6355 (truncate:SI
6356 (lshiftrt:DI (mult:DI (sign_extend:DI
6357 (match_operand:SI 1 "gpc_reg_operand" ""))
6358 (sign_extend:DI
6359 (match_operand:SI 2 "gpc_reg_operand" "")))
6360 (const_int 32))))]
6361 ""
6362 "
6363 {
6364 if (! TARGET_POWER && ! TARGET_POWERPC)
6365 {
6366 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6367 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6368 emit_insn (gen_mulh_call ());
6369 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6370 DONE;
6371 }
6372 else if (TARGET_POWER)
6373 {
6374 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6375 DONE;
6376 }
6377 }")
6379 (define_insn "smulsi3_highpart_mq"
6380 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6381 (truncate:SI
6382 (lshiftrt:DI (mult:DI (sign_extend:DI
6383 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6384 (sign_extend:DI
6385 (match_operand:SI 2 "gpc_reg_operand" "r")))
6386 (const_int 32))))
6387 (clobber (match_scratch:SI 3 "=q"))]
6388 "TARGET_POWER"
6389 "mul %0,%1,%2"
6390 [(set_attr "type" "imul")])
6392 (define_insn "*smulsi3_highpart_no_mq"
6393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6394 (truncate:SI
6395 (lshiftrt:DI (mult:DI (sign_extend:DI
6396 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6397 (sign_extend:DI
6398 (match_operand:SI 2 "gpc_reg_operand" "r")))
6399 (const_int 32))))]
6400 "TARGET_POWERPC && ! TARGET_POWER"
6401 "mulhw %0,%1,%2"
6402 [(set_attr "type" "imul")])
6404 (define_expand "umulsi3_highpart"
6405 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6406 (truncate:SI
6407 (lshiftrt:DI (mult:DI (zero_extend:DI
6408 (match_operand:SI 1 "gpc_reg_operand" ""))
6409 (zero_extend:DI
6410 (match_operand:SI 2 "gpc_reg_operand" "")))
6411 (const_int 32))))]
6412 "TARGET_POWERPC"
6413 "
6414 {
6415 if (TARGET_POWER)
6416 {
6417 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6418 DONE;
6419 }
6420 }")
6422 (define_insn "umulsi3_highpart_mq"
6423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6424 (truncate:SI
6425 (lshiftrt:DI (mult:DI (zero_extend:DI
6426 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6427 (zero_extend:DI
6428 (match_operand:SI 2 "gpc_reg_operand" "r")))
6429 (const_int 32))))
6430 (clobber (match_scratch:SI 3 "=q"))]
6431 "TARGET_POWERPC && TARGET_POWER"
6432 "mulhwu %0,%1,%2"
6433 [(set_attr "type" "imul")])
6435 (define_insn "*umulsi3_highpart_no_mq"
6436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6437 (truncate:SI
6438 (lshiftrt:DI (mult:DI (zero_extend:DI
6439 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6440 (zero_extend:DI
6441 (match_operand:SI 2 "gpc_reg_operand" "r")))
6442 (const_int 32))))]
6443 "TARGET_POWERPC && ! TARGET_POWER"
6444 "mulhwu %0,%1,%2"
6445 [(set_attr "type" "imul")])
6447 ;; If operands 0 and 2 are in the same register, we have a problem. But
6448 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6449 ;; why we have the strange constraints below.
6450 (define_insn "ashldi3_power"
6451 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6452 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6453 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6454 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6455 "TARGET_POWER"
6456 "@
6457 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6458 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6459 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6460 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6461 [(set_attr "length" "8")])
6463 (define_insn "lshrdi3_power"
6464 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6465 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6466 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6467 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6468 "TARGET_POWER"
6469 "@
6470 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6471 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6472 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6473 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6474 [(set_attr "length" "8")])
6476 ;; Shift by a variable amount is too complex to be worth open-coding. We
6477 ;; just handle shifts by constants.
6478 (define_insn "ashrdi3_power"
6479 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6480 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6481 (match_operand:SI 2 "const_int_operand" "M,i")))
6482 (clobber (match_scratch:SI 3 "=X,q"))]
6483 "TARGET_POWER"
6484 "@
6485 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6486 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6487 [(set_attr "type" "shift")
6488 (set_attr "length" "8")])
6490 (define_insn "ashrdi3_no_power"
6491 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6492 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6493 (match_operand:SI 2 "const_int_operand" "M,i")))]
6494 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6495 "@
6496 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6497 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6498 [(set_attr "type" "two,three")
6499 (set_attr "length" "8,12")])
6501 (define_insn "*ashrdisi3_noppc64"
6502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6503 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6504 (const_int 32)) 4))]
6505 "TARGET_32BIT && !TARGET_POWERPC64"
6506 "*
6507 {
6508 if (REGNO (operands[0]) == REGNO (operands[1]))
6509 return \"\";
6510 else
6511 return \"mr %0,%1\";
6512 }"
6513 [(set_attr "length" "4")])
6515 \f
6516 ;; PowerPC64 DImode operations.
6518 (define_insn_and_split "absdi2"
6519 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6520 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6521 (clobber (match_scratch:DI 2 "=&r,&r"))]
6522 "TARGET_POWERPC64"
6523 "#"
6524 "&& reload_completed"
6525 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6526 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6527 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6528 "")
6530 (define_insn_and_split "*nabsdi2"
6531 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6532 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6533 (clobber (match_scratch:DI 2 "=&r,&r"))]
6534 "TARGET_POWERPC64"
6535 "#"
6536 "&& reload_completed"
6537 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6538 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6539 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6540 "")
6542 (define_insn "muldi3"
6543 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6544 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6545 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6546 "TARGET_POWERPC64"
6547 "@
6548 mulld %0,%1,%2
6549 mulli %0,%1,%2"
6550 [(set (attr "type")
6551 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6552 (const_string "imul3")
6553 (match_operand:SI 2 "short_cint_operand" "")
6554 (const_string "imul2")]
6555 (const_string "lmul")))])
6557 (define_insn "*muldi3_internal1"
6558 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6559 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6560 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6561 (const_int 0)))
6562 (clobber (match_scratch:DI 3 "=r,r"))]
6563 "TARGET_POWERPC64"
6564 "@
6565 mulld. %3,%1,%2
6566 #"
6567 [(set_attr "type" "lmul_compare")
6568 (set_attr "length" "4,8")])
6570 (define_split
6571 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6572 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6573 (match_operand:DI 2 "gpc_reg_operand" ""))
6574 (const_int 0)))
6575 (clobber (match_scratch:DI 3 ""))]
6576 "TARGET_POWERPC64 && reload_completed"
6577 [(set (match_dup 3)
6578 (mult:DI (match_dup 1) (match_dup 2)))
6579 (set (match_dup 0)
6580 (compare:CC (match_dup 3)
6581 (const_int 0)))]
6582 "")
6584 (define_insn "*muldi3_internal2"
6585 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6586 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6587 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6588 (const_int 0)))
6589 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6590 (mult:DI (match_dup 1) (match_dup 2)))]
6591 "TARGET_POWERPC64"
6592 "@
6593 mulld. %0,%1,%2
6594 #"
6595 [(set_attr "type" "lmul_compare")
6596 (set_attr "length" "4,8")])
6598 (define_split
6599 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6600 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6601 (match_operand:DI 2 "gpc_reg_operand" ""))
6602 (const_int 0)))
6603 (set (match_operand:DI 0 "gpc_reg_operand" "")
6604 (mult:DI (match_dup 1) (match_dup 2)))]
6605 "TARGET_POWERPC64 && reload_completed"
6606 [(set (match_dup 0)
6607 (mult:DI (match_dup 1) (match_dup 2)))
6608 (set (match_dup 3)
6609 (compare:CC (match_dup 0)
6610 (const_int 0)))]
6611 "")
6613 (define_insn "smuldi3_highpart"
6614 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6615 (truncate:DI
6616 (lshiftrt:TI (mult:TI (sign_extend:TI
6617 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6618 (sign_extend:TI
6619 (match_operand:DI 2 "gpc_reg_operand" "r")))
6620 (const_int 64))))]
6621 "TARGET_POWERPC64"
6622 "mulhd %0,%1,%2"
6623 [(set_attr "type" "lmul")])
6625 (define_insn "umuldi3_highpart"
6626 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6627 (truncate:DI
6628 (lshiftrt:TI (mult:TI (zero_extend:TI
6629 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6630 (zero_extend:TI
6631 (match_operand:DI 2 "gpc_reg_operand" "r")))
6632 (const_int 64))))]
6633 "TARGET_POWERPC64"
6634 "mulhdu %0,%1,%2"
6635 [(set_attr "type" "lmul")])
6637 (define_insn "rotldi3"
6638 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6639 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6640 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6641 "TARGET_POWERPC64"
6642 "@
6643 rldcl %0,%1,%2,0
6644 rldicl %0,%1,%H2,0"
6645 [(set_attr "type" "var_shift_rotate,integer")])
6647 (define_insn "*rotldi3_internal2"
6648 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6649 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6650 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6651 (const_int 0)))
6652 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6653 "TARGET_64BIT"
6654 "@
6655 rldcl. %3,%1,%2,0
6656 rldicl. %3,%1,%H2,0
6657 #
6658 #"
6659 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6660 (set_attr "length" "4,4,8,8")])
6662 (define_split
6663 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6664 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6665 (match_operand:DI 2 "reg_or_cint_operand" ""))
6666 (const_int 0)))
6667 (clobber (match_scratch:DI 3 ""))]
6668 "TARGET_POWERPC64 && reload_completed"
6669 [(set (match_dup 3)
6670 (rotate:DI (match_dup 1) (match_dup 2)))
6671 (set (match_dup 0)
6672 (compare:CC (match_dup 3)
6673 (const_int 0)))]
6674 "")
6676 (define_insn "*rotldi3_internal3"
6677 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6678 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6679 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6680 (const_int 0)))
6681 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6682 (rotate:DI (match_dup 1) (match_dup 2)))]
6683 "TARGET_64BIT"
6684 "@
6685 rldcl. %0,%1,%2,0
6686 rldicl. %0,%1,%H2,0
6687 #
6688 #"
6689 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6690 (set_attr "length" "4,4,8,8")])
6692 (define_split
6693 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6694 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6695 (match_operand:DI 2 "reg_or_cint_operand" ""))
6696 (const_int 0)))
6697 (set (match_operand:DI 0 "gpc_reg_operand" "")
6698 (rotate:DI (match_dup 1) (match_dup 2)))]
6699 "TARGET_POWERPC64 && reload_completed"
6700 [(set (match_dup 0)
6701 (rotate:DI (match_dup 1) (match_dup 2)))
6702 (set (match_dup 3)
6703 (compare:CC (match_dup 0)
6704 (const_int 0)))]
6705 "")
6707 (define_insn "*rotldi3_internal4"
6708 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6709 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6710 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6711 (match_operand:DI 3 "mask64_operand" "n,n")))]
6712 "TARGET_POWERPC64"
6713 "@
6714 rldc%B3 %0,%1,%2,%S3
6715 rldic%B3 %0,%1,%H2,%S3"
6716 [(set_attr "type" "var_shift_rotate,integer")])
6718 (define_insn "*rotldi3_internal5"
6719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6720 (compare:CC (and:DI
6721 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6722 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6723 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6724 (const_int 0)))
6725 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6726 "TARGET_64BIT"
6727 "@
6728 rldc%B3. %4,%1,%2,%S3
6729 rldic%B3. %4,%1,%H2,%S3
6730 #
6731 #"
6732 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6733 (set_attr "length" "4,4,8,8")])
6735 (define_split
6736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6737 (compare:CC (and:DI
6738 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6739 (match_operand:DI 2 "reg_or_cint_operand" ""))
6740 (match_operand:DI 3 "mask64_operand" ""))
6741 (const_int 0)))
6742 (clobber (match_scratch:DI 4 ""))]
6743 "TARGET_POWERPC64 && reload_completed"
6744 [(set (match_dup 4)
6745 (and:DI (rotate:DI (match_dup 1)
6746 (match_dup 2))
6747 (match_dup 3)))
6748 (set (match_dup 0)
6749 (compare:CC (match_dup 4)
6750 (const_int 0)))]
6751 "")
6753 (define_insn "*rotldi3_internal6"
6754 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6755 (compare:CC (and:DI
6756 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6757 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6758 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6759 (const_int 0)))
6760 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6761 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6762 "TARGET_64BIT"
6763 "@
6764 rldc%B3. %0,%1,%2,%S3
6765 rldic%B3. %0,%1,%H2,%S3
6766 #
6767 #"
6768 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6769 (set_attr "length" "4,4,8,8")])
6771 (define_split
6772 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6773 (compare:CC (and:DI
6774 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6775 (match_operand:DI 2 "reg_or_cint_operand" ""))
6776 (match_operand:DI 3 "mask64_operand" ""))
6777 (const_int 0)))
6778 (set (match_operand:DI 0 "gpc_reg_operand" "")
6779 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6780 "TARGET_POWERPC64 && reload_completed"
6781 [(set (match_dup 0)
6782 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6783 (set (match_dup 4)
6784 (compare:CC (match_dup 0)
6785 (const_int 0)))]
6786 "")
6788 (define_insn "*rotldi3_internal7"
6789 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6790 (zero_extend:DI
6791 (subreg:QI
6792 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6793 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6794 "TARGET_POWERPC64"
6795 "@
6796 rldcl %0,%1,%2,56
6797 rldicl %0,%1,%H2,56"
6798 [(set_attr "type" "var_shift_rotate,integer")])
6800 (define_insn "*rotldi3_internal8"
6801 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6802 (compare:CC (zero_extend:DI
6803 (subreg:QI
6804 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6805 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6806 (const_int 0)))
6807 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6808 "TARGET_64BIT"
6809 "@
6810 rldcl. %3,%1,%2,56
6811 rldicl. %3,%1,%H2,56
6812 #
6813 #"
6814 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6815 (set_attr "length" "4,4,8,8")])
6817 (define_split
6818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6819 (compare:CC (zero_extend:DI
6820 (subreg:QI
6821 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6822 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6823 (const_int 0)))
6824 (clobber (match_scratch:DI 3 ""))]
6825 "TARGET_POWERPC64 && reload_completed"
6826 [(set (match_dup 3)
6827 (zero_extend:DI (subreg:QI
6828 (rotate:DI (match_dup 1)
6829 (match_dup 2)) 0)))
6830 (set (match_dup 0)
6831 (compare:CC (match_dup 3)
6832 (const_int 0)))]
6833 "")
6835 (define_insn "*rotldi3_internal9"
6836 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6837 (compare:CC (zero_extend:DI
6838 (subreg:QI
6839 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6840 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6841 (const_int 0)))
6842 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6843 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6844 "TARGET_64BIT"
6845 "@
6846 rldcl. %0,%1,%2,56
6847 rldicl. %0,%1,%H2,56
6848 #
6849 #"
6850 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6851 (set_attr "length" "4,4,8,8")])
6853 (define_split
6854 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6855 (compare:CC (zero_extend:DI
6856 (subreg:QI
6857 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6858 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6859 (const_int 0)))
6860 (set (match_operand:DI 0 "gpc_reg_operand" "")
6861 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6862 "TARGET_POWERPC64 && reload_completed"
6863 [(set (match_dup 0)
6864 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6865 (set (match_dup 3)
6866 (compare:CC (match_dup 0)
6867 (const_int 0)))]
6868 "")
6870 (define_insn "*rotldi3_internal10"
6871 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6872 (zero_extend:DI
6873 (subreg:HI
6874 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6875 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6876 "TARGET_POWERPC64"
6877 "@
6878 rldcl %0,%1,%2,48
6879 rldicl %0,%1,%H2,48"
6880 [(set_attr "type" "var_shift_rotate,integer")])
6882 (define_insn "*rotldi3_internal11"
6883 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6884 (compare:CC (zero_extend:DI
6885 (subreg:HI
6886 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6887 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6888 (const_int 0)))
6889 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6890 "TARGET_64BIT"
6891 "@
6892 rldcl. %3,%1,%2,48
6893 rldicl. %3,%1,%H2,48
6894 #
6895 #"
6896 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6897 (set_attr "length" "4,4,8,8")])
6899 (define_split
6900 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6901 (compare:CC (zero_extend:DI
6902 (subreg:HI
6903 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6904 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6905 (const_int 0)))
6906 (clobber (match_scratch:DI 3 ""))]
6907 "TARGET_POWERPC64 && reload_completed"
6908 [(set (match_dup 3)
6909 (zero_extend:DI (subreg:HI
6910 (rotate:DI (match_dup 1)
6911 (match_dup 2)) 0)))
6912 (set (match_dup 0)
6913 (compare:CC (match_dup 3)
6914 (const_int 0)))]
6915 "")
6917 (define_insn "*rotldi3_internal12"
6918 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6919 (compare:CC (zero_extend:DI
6920 (subreg:HI
6921 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6922 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6923 (const_int 0)))
6924 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6925 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6926 "TARGET_64BIT"
6927 "@
6928 rldcl. %0,%1,%2,48
6929 rldicl. %0,%1,%H2,48
6930 #
6931 #"
6932 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6933 (set_attr "length" "4,4,8,8")])
6935 (define_split
6936 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6937 (compare:CC (zero_extend:DI
6938 (subreg:HI
6939 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6940 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6941 (const_int 0)))
6942 (set (match_operand:DI 0 "gpc_reg_operand" "")
6943 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6944 "TARGET_POWERPC64 && reload_completed"
6945 [(set (match_dup 0)
6946 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6947 (set (match_dup 3)
6948 (compare:CC (match_dup 0)
6949 (const_int 0)))]
6950 "")
6952 (define_insn "*rotldi3_internal13"
6953 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6954 (zero_extend:DI
6955 (subreg:SI
6956 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6957 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6958 "TARGET_POWERPC64"
6959 "@
6960 rldcl %0,%1,%2,32
6961 rldicl %0,%1,%H2,32"
6962 [(set_attr "type" "var_shift_rotate,integer")])
6964 (define_insn "*rotldi3_internal14"
6965 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6966 (compare:CC (zero_extend:DI
6967 (subreg:SI
6968 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6969 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6970 (const_int 0)))
6971 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6972 "TARGET_64BIT"
6973 "@
6974 rldcl. %3,%1,%2,32
6975 rldicl. %3,%1,%H2,32
6976 #
6977 #"
6978 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6979 (set_attr "length" "4,4,8,8")])
6981 (define_split
6982 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6983 (compare:CC (zero_extend:DI
6984 (subreg:SI
6985 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6986 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6987 (const_int 0)))
6988 (clobber (match_scratch:DI 3 ""))]
6989 "TARGET_POWERPC64 && reload_completed"
6990 [(set (match_dup 3)
6991 (zero_extend:DI (subreg:SI
6992 (rotate:DI (match_dup 1)
6993 (match_dup 2)) 0)))
6994 (set (match_dup 0)
6995 (compare:CC (match_dup 3)
6996 (const_int 0)))]
6997 "")
6999 (define_insn "*rotldi3_internal15"
7000 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7001 (compare:CC (zero_extend:DI
7002 (subreg:SI
7003 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7004 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7005 (const_int 0)))
7006 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7007 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7008 "TARGET_64BIT"
7009 "@
7010 rldcl. %0,%1,%2,32
7011 rldicl. %0,%1,%H2,32
7012 #
7013 #"
7014 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7015 (set_attr "length" "4,4,8,8")])
7017 (define_split
7018 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7019 (compare:CC (zero_extend:DI
7020 (subreg:SI
7021 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7022 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7023 (const_int 0)))
7024 (set (match_operand:DI 0 "gpc_reg_operand" "")
7025 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7026 "TARGET_POWERPC64 && reload_completed"
7027 [(set (match_dup 0)
7028 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7029 (set (match_dup 3)
7030 (compare:CC (match_dup 0)
7031 (const_int 0)))]
7032 "")
7034 (define_expand "ashldi3"
7035 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7036 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7037 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7038 "TARGET_POWERPC64 || TARGET_POWER"
7039 "
7040 {
7041 if (TARGET_POWERPC64)
7042 ;
7043 else if (TARGET_POWER)
7044 {
7045 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7046 DONE;
7047 }
7048 else
7049 FAIL;
7050 }")
7052 (define_insn "*ashldi3_internal1"
7053 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7054 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7055 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7056 "TARGET_POWERPC64"
7057 "@
7058 sld %0,%1,%2
7059 sldi %0,%1,%H2"
7060 [(set_attr "type" "var_shift_rotate,shift")])
7062 (define_insn "*ashldi3_internal2"
7063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7064 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7065 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7066 (const_int 0)))
7067 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7068 "TARGET_64BIT"
7069 "@
7070 sld. %3,%1,%2
7071 sldi. %3,%1,%H2
7072 #
7073 #"
7074 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7075 (set_attr "length" "4,4,8,8")])
7077 (define_split
7078 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7079 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7080 (match_operand:SI 2 "reg_or_cint_operand" ""))
7081 (const_int 0)))
7082 (clobber (match_scratch:DI 3 ""))]
7083 "TARGET_POWERPC64 && reload_completed"
7084 [(set (match_dup 3)
7085 (ashift:DI (match_dup 1) (match_dup 2)))
7086 (set (match_dup 0)
7087 (compare:CC (match_dup 3)
7088 (const_int 0)))]
7089 "")
7091 (define_insn "*ashldi3_internal3"
7092 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7093 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7094 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7095 (const_int 0)))
7096 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7097 (ashift:DI (match_dup 1) (match_dup 2)))]
7098 "TARGET_64BIT"
7099 "@
7100 sld. %0,%1,%2
7101 sldi. %0,%1,%H2
7102 #
7103 #"
7104 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7105 (set_attr "length" "4,4,8,8")])
7107 (define_split
7108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7109 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7110 (match_operand:SI 2 "reg_or_cint_operand" ""))
7111 (const_int 0)))
7112 (set (match_operand:DI 0 "gpc_reg_operand" "")
7113 (ashift:DI (match_dup 1) (match_dup 2)))]
7114 "TARGET_POWERPC64 && reload_completed"
7115 [(set (match_dup 0)
7116 (ashift:DI (match_dup 1) (match_dup 2)))
7117 (set (match_dup 3)
7118 (compare:CC (match_dup 0)
7119 (const_int 0)))]
7120 "")
7122 (define_insn "*ashldi3_internal4"
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7124 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7125 (match_operand:SI 2 "const_int_operand" "i"))
7126 (match_operand:DI 3 "const_int_operand" "n")))]
7127 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7128 "rldic %0,%1,%H2,%W3")
7130 (define_insn "ashldi3_internal5"
7131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7132 (compare:CC
7133 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7134 (match_operand:SI 2 "const_int_operand" "i,i"))
7135 (match_operand:DI 3 "const_int_operand" "n,n"))
7136 (const_int 0)))
7137 (clobber (match_scratch:DI 4 "=r,r"))]
7138 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7139 "@
7140 rldic. %4,%1,%H2,%W3
7141 #"
7142 [(set_attr "type" "compare")
7143 (set_attr "length" "4,8")])
7145 (define_split
7146 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7147 (compare:CC
7148 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7149 (match_operand:SI 2 "const_int_operand" ""))
7150 (match_operand:DI 3 "const_int_operand" ""))
7151 (const_int 0)))
7152 (clobber (match_scratch:DI 4 ""))]
7153 "TARGET_POWERPC64 && reload_completed
7154 && includes_rldic_lshift_p (operands[2], operands[3])"
7155 [(set (match_dup 4)
7156 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7157 (match_dup 3)))
7158 (set (match_dup 0)
7159 (compare:CC (match_dup 4)
7160 (const_int 0)))]
7161 "")
7163 (define_insn "*ashldi3_internal6"
7164 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7165 (compare:CC
7166 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7167 (match_operand:SI 2 "const_int_operand" "i,i"))
7168 (match_operand:DI 3 "const_int_operand" "n,n"))
7169 (const_int 0)))
7170 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7171 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7172 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7173 "@
7174 rldic. %0,%1,%H2,%W3
7175 #"
7176 [(set_attr "type" "compare")
7177 (set_attr "length" "4,8")])
7179 (define_split
7180 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7181 (compare:CC
7182 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7183 (match_operand:SI 2 "const_int_operand" ""))
7184 (match_operand:DI 3 "const_int_operand" ""))
7185 (const_int 0)))
7186 (set (match_operand:DI 0 "gpc_reg_operand" "")
7187 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7188 "TARGET_POWERPC64 && reload_completed
7189 && includes_rldic_lshift_p (operands[2], operands[3])"
7190 [(set (match_dup 0)
7191 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7192 (match_dup 3)))
7193 (set (match_dup 4)
7194 (compare:CC (match_dup 0)
7195 (const_int 0)))]
7196 "")
7198 (define_insn "*ashldi3_internal7"
7199 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7200 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7201 (match_operand:SI 2 "const_int_operand" "i"))
7202 (match_operand:DI 3 "mask64_operand" "n")))]
7203 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7204 "rldicr %0,%1,%H2,%S3")
7206 (define_insn "ashldi3_internal8"
7207 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7208 (compare:CC
7209 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7210 (match_operand:SI 2 "const_int_operand" "i,i"))
7211 (match_operand:DI 3 "mask64_operand" "n,n"))
7212 (const_int 0)))
7213 (clobber (match_scratch:DI 4 "=r,r"))]
7214 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7215 "@
7216 rldicr. %4,%1,%H2,%S3
7217 #"
7218 [(set_attr "type" "compare")
7219 (set_attr "length" "4,8")])
7221 (define_split
7222 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7223 (compare:CC
7224 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7225 (match_operand:SI 2 "const_int_operand" ""))
7226 (match_operand:DI 3 "mask64_operand" ""))
7227 (const_int 0)))
7228 (clobber (match_scratch:DI 4 ""))]
7229 "TARGET_POWERPC64 && reload_completed
7230 && includes_rldicr_lshift_p (operands[2], operands[3])"
7231 [(set (match_dup 4)
7232 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7233 (match_dup 3)))
7234 (set (match_dup 0)
7235 (compare:CC (match_dup 4)
7236 (const_int 0)))]
7237 "")
7239 (define_insn "*ashldi3_internal9"
7240 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7241 (compare:CC
7242 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7243 (match_operand:SI 2 "const_int_operand" "i,i"))
7244 (match_operand:DI 3 "mask64_operand" "n,n"))
7245 (const_int 0)))
7246 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7247 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7248 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7249 "@
7250 rldicr. %0,%1,%H2,%S3
7251 #"
7252 [(set_attr "type" "compare")
7253 (set_attr "length" "4,8")])
7255 (define_split
7256 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7257 (compare:CC
7258 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7259 (match_operand:SI 2 "const_int_operand" ""))
7260 (match_operand:DI 3 "mask64_operand" ""))
7261 (const_int 0)))
7262 (set (match_operand:DI 0 "gpc_reg_operand" "")
7263 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7264 "TARGET_POWERPC64 && reload_completed
7265 && includes_rldicr_lshift_p (operands[2], operands[3])"
7266 [(set (match_dup 0)
7267 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7268 (match_dup 3)))
7269 (set (match_dup 4)
7270 (compare:CC (match_dup 0)
7271 (const_int 0)))]
7272 "")
7274 (define_expand "lshrdi3"
7275 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7276 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7277 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7278 "TARGET_POWERPC64 || TARGET_POWER"
7279 "
7280 {
7281 if (TARGET_POWERPC64)
7282 ;
7283 else if (TARGET_POWER)
7284 {
7285 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7286 DONE;
7287 }
7288 else
7289 FAIL;
7290 }")
7292 (define_insn "*lshrdi3_internal1"
7293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7294 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7295 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7296 "TARGET_POWERPC64"
7297 "@
7298 srd %0,%1,%2
7299 srdi %0,%1,%H2"
7300 [(set_attr "type" "var_shift_rotate,shift")])
7302 (define_insn "*lshrdi3_internal2"
7303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7304 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7305 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7306 (const_int 0)))
7307 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7308 "TARGET_64BIT "
7309 "@
7310 srd. %3,%1,%2
7311 srdi. %3,%1,%H2
7312 #
7313 #"
7314 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7315 (set_attr "length" "4,4,8,8")])
7317 (define_split
7318 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7319 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7320 (match_operand:SI 2 "reg_or_cint_operand" ""))
7321 (const_int 0)))
7322 (clobber (match_scratch:DI 3 ""))]
7323 "TARGET_POWERPC64 && reload_completed"
7324 [(set (match_dup 3)
7325 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7326 (set (match_dup 0)
7327 (compare:CC (match_dup 3)
7328 (const_int 0)))]
7329 "")
7331 (define_insn "*lshrdi3_internal3"
7332 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7333 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7334 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7335 (const_int 0)))
7336 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7337 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7338 "TARGET_64BIT"
7339 "@
7340 srd. %0,%1,%2
7341 srdi. %0,%1,%H2
7342 #
7343 #"
7344 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7345 (set_attr "length" "4,4,8,8")])
7347 (define_split
7348 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7349 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7350 (match_operand:SI 2 "reg_or_cint_operand" ""))
7351 (const_int 0)))
7352 (set (match_operand:DI 0 "gpc_reg_operand" "")
7353 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7354 "TARGET_POWERPC64 && reload_completed"
7355 [(set (match_dup 0)
7356 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7357 (set (match_dup 3)
7358 (compare:CC (match_dup 0)
7359 (const_int 0)))]
7360 "")
7362 (define_expand "ashrdi3"
7363 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7364 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7365 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7366 "WORDS_BIG_ENDIAN"
7367 "
7368 {
7369 if (TARGET_POWERPC64)
7370 ;
7371 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7372 {
7373 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7374 DONE;
7375 }
7376 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7377 && WORDS_BIG_ENDIAN)
7378 {
7379 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7380 DONE;
7381 }
7382 else
7383 FAIL;
7384 }")
7386 (define_insn "*ashrdi3_internal1"
7387 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7388 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7389 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7390 "TARGET_POWERPC64"
7391 "@
7392 srad %0,%1,%2
7393 sradi %0,%1,%H2"
7394 [(set_attr "type" "var_shift_rotate,shift")])
7396 (define_insn "*ashrdi3_internal2"
7397 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7398 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7399 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7400 (const_int 0)))
7401 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7402 "TARGET_64BIT"
7403 "@
7404 srad. %3,%1,%2
7405 sradi. %3,%1,%H2
7406 #
7407 #"
7408 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7409 (set_attr "length" "4,4,8,8")])
7411 (define_split
7412 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7413 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7414 (match_operand:SI 2 "reg_or_cint_operand" ""))
7415 (const_int 0)))
7416 (clobber (match_scratch:DI 3 ""))]
7417 "TARGET_POWERPC64 && reload_completed"
7418 [(set (match_dup 3)
7419 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7420 (set (match_dup 0)
7421 (compare:CC (match_dup 3)
7422 (const_int 0)))]
7423 "")
7425 (define_insn "*ashrdi3_internal3"
7426 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7427 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7428 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7429 (const_int 0)))
7430 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7431 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7432 "TARGET_64BIT"
7433 "@
7434 srad. %0,%1,%2
7435 sradi. %0,%1,%H2
7436 #
7437 #"
7438 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7439 (set_attr "length" "4,4,8,8")])
7441 (define_split
7442 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7443 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7444 (match_operand:SI 2 "reg_or_cint_operand" ""))
7445 (const_int 0)))
7446 (set (match_operand:DI 0 "gpc_reg_operand" "")
7447 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7448 "TARGET_POWERPC64 && reload_completed"
7449 [(set (match_dup 0)
7450 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7451 (set (match_dup 3)
7452 (compare:CC (match_dup 0)
7453 (const_int 0)))]
7454 "")
7456 (define_insn "anddi3"
7457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7458 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7459 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7460 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7461 "TARGET_POWERPC64"
7462 "@
7463 and %0,%1,%2
7464 rldic%B2 %0,%1,0,%S2
7465 rlwinm %0,%1,0,%m2,%M2
7466 andi. %0,%1,%b2
7467 andis. %0,%1,%u2
7468 #"
7469 [(set_attr "type" "*,*,*,compare,compare,*")
7470 (set_attr "length" "4,4,4,4,4,8")])
7472 (define_split
7473 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7474 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7475 (match_operand:DI 2 "mask64_2_operand" "")))
7476 (clobber (match_scratch:CC 3 ""))]
7477 "TARGET_POWERPC64
7478 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7479 && !mask_operand (operands[2], DImode)
7480 && !mask64_operand (operands[2], DImode)"
7481 [(set (match_dup 0)
7482 (and:DI (rotate:DI (match_dup 1)
7483 (match_dup 4))
7484 (match_dup 5)))
7485 (set (match_dup 0)
7486 (and:DI (rotate:DI (match_dup 0)
7487 (match_dup 6))
7488 (match_dup 7)))]
7489 {
7490 build_mask64_2_operands (operands[2], &operands[4]);
7491 })
7493 (define_insn "*anddi3_internal2"
7494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7495 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7496 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7497 (const_int 0)))
7498 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7499 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7500 "TARGET_64BIT"
7501 "@
7502 and. %3,%1,%2
7503 rldic%B2. %3,%1,0,%S2
7504 rlwinm. %3,%1,0,%m2,%M2
7505 andi. %3,%1,%b2
7506 andis. %3,%1,%u2
7507 #
7508 #
7509 #
7510 #
7511 #
7512 #
7513 #"
7514 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7515 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7517 (define_split
7518 [(set (match_operand:CC 0 "cc_reg_operand" "")
7519 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7520 (match_operand:DI 2 "mask64_2_operand" ""))
7521 (const_int 0)))
7522 (clobber (match_scratch:DI 3 ""))
7523 (clobber (match_scratch:CC 4 ""))]
7524 "TARGET_64BIT && reload_completed
7525 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7526 && !mask_operand (operands[2], DImode)
7527 && !mask64_operand (operands[2], DImode)"
7528 [(set (match_dup 3)
7529 (and:DI (rotate:DI (match_dup 1)
7530 (match_dup 5))
7531 (match_dup 6)))
7532 (parallel [(set (match_dup 0)
7533 (compare:CC (and:DI (rotate:DI (match_dup 3)
7534 (match_dup 7))
7535 (match_dup 8))
7536 (const_int 0)))
7537 (clobber (match_dup 3))])]
7538 "
7539 {
7540 build_mask64_2_operands (operands[2], &operands[5]);
7541 }")
7543 (define_insn "*anddi3_internal3"
7544 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7545 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7546 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7547 (const_int 0)))
7548 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7549 (and:DI (match_dup 1) (match_dup 2)))
7550 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7551 "TARGET_64BIT"
7552 "@
7553 and. %0,%1,%2
7554 rldic%B2. %0,%1,0,%S2
7555 rlwinm. %0,%1,0,%m2,%M2
7556 andi. %0,%1,%b2
7557 andis. %0,%1,%u2
7558 #
7559 #
7560 #
7561 #
7562 #
7563 #
7564 #"
7565 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7566 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7568 (define_split
7569 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7570 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7571 (match_operand:DI 2 "and64_2_operand" ""))
7572 (const_int 0)))
7573 (set (match_operand:DI 0 "gpc_reg_operand" "")
7574 (and:DI (match_dup 1) (match_dup 2)))
7575 (clobber (match_scratch:CC 4 ""))]
7576 "TARGET_64BIT && reload_completed"
7577 [(parallel [(set (match_dup 0)
7578 (and:DI (match_dup 1) (match_dup 2)))
7579 (clobber (match_dup 4))])
7580 (set (match_dup 3)
7581 (compare:CC (match_dup 0)
7582 (const_int 0)))]
7583 "")
7585 (define_split
7586 [(set (match_operand:CC 3 "cc_reg_operand" "")
7587 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7588 (match_operand:DI 2 "mask64_2_operand" ""))
7589 (const_int 0)))
7590 (set (match_operand:DI 0 "gpc_reg_operand" "")
7591 (and:DI (match_dup 1) (match_dup 2)))
7592 (clobber (match_scratch:CC 4 ""))]
7593 "TARGET_64BIT && reload_completed
7594 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7595 && !mask_operand (operands[2], DImode)
7596 && !mask64_operand (operands[2], DImode)"
7597 [(set (match_dup 0)
7598 (and:DI (rotate:DI (match_dup 1)
7599 (match_dup 5))
7600 (match_dup 6)))
7601 (parallel [(set (match_dup 3)
7602 (compare:CC (and:DI (rotate:DI (match_dup 0)
7603 (match_dup 7))
7604 (match_dup 8))
7605 (const_int 0)))
7606 (set (match_dup 0)
7607 (and:DI (rotate:DI (match_dup 0)
7608 (match_dup 7))
7609 (match_dup 8)))])]
7610 "
7611 {
7612 build_mask64_2_operands (operands[2], &operands[5]);
7613 }")
7615 (define_expand "iordi3"
7616 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7617 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7618 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7619 "TARGET_POWERPC64"
7620 "
7621 {
7622 if (non_logical_cint_operand (operands[2], DImode))
7623 {
7624 HOST_WIDE_INT value;
7625 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7626 ? operands[0] : gen_reg_rtx (DImode));
7628 if (GET_CODE (operands[2]) == CONST_INT)
7629 {
7630 value = INTVAL (operands[2]);
7631 emit_insn (gen_iordi3 (tmp, operands[1],
7632 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7633 }
7634 else
7635 {
7636 value = CONST_DOUBLE_LOW (operands[2]);
7637 emit_insn (gen_iordi3 (tmp, operands[1],
7638 immed_double_const (value
7639 & (~ (HOST_WIDE_INT) 0xffff),
7640 0, DImode)));
7641 }
7643 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7644 DONE;
7645 }
7646 }")
7648 (define_expand "xordi3"
7649 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7650 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7651 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7652 "TARGET_POWERPC64"
7653 "
7654 {
7655 if (non_logical_cint_operand (operands[2], DImode))
7656 {
7657 HOST_WIDE_INT value;
7658 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7659 ? operands[0] : gen_reg_rtx (DImode));
7661 if (GET_CODE (operands[2]) == CONST_INT)
7662 {
7663 value = INTVAL (operands[2]);
7664 emit_insn (gen_xordi3 (tmp, operands[1],
7665 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7666 }
7667 else
7668 {
7669 value = CONST_DOUBLE_LOW (operands[2]);
7670 emit_insn (gen_xordi3 (tmp, operands[1],
7671 immed_double_const (value
7672 & (~ (HOST_WIDE_INT) 0xffff),
7673 0, DImode)));
7674 }
7676 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7677 DONE;
7678 }
7679 }")
7681 (define_insn "*booldi3_internal1"
7682 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7683 (match_operator:DI 3 "boolean_or_operator"
7684 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7685 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7686 "TARGET_POWERPC64"
7687 "@
7688 %q3 %0,%1,%2
7689 %q3i %0,%1,%b2
7690 %q3is %0,%1,%u2")
7692 (define_insn "*booldi3_internal2"
7693 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7694 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7695 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7696 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7697 (const_int 0)))
7698 (clobber (match_scratch:DI 3 "=r,r"))]
7699 "TARGET_64BIT"
7700 "@
7701 %q4. %3,%1,%2
7702 #"
7703 [(set_attr "type" "compare")
7704 (set_attr "length" "4,8")])
7706 (define_split
7707 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7708 (compare:CC (match_operator:DI 4 "boolean_operator"
7709 [(match_operand:DI 1 "gpc_reg_operand" "")
7710 (match_operand:DI 2 "gpc_reg_operand" "")])
7711 (const_int 0)))
7712 (clobber (match_scratch:DI 3 ""))]
7713 "TARGET_POWERPC64 && reload_completed"
7714 [(set (match_dup 3) (match_dup 4))
7715 (set (match_dup 0)
7716 (compare:CC (match_dup 3)
7717 (const_int 0)))]
7718 "")
7720 (define_insn "*booldi3_internal3"
7721 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7722 (compare:CC (match_operator:DI 4 "boolean_operator"
7723 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7724 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7725 (const_int 0)))
7726 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7727 (match_dup 4))]
7728 "TARGET_64BIT"
7729 "@
7730 %q4. %0,%1,%2
7731 #"
7732 [(set_attr "type" "compare")
7733 (set_attr "length" "4,8")])
7735 (define_split
7736 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7737 (compare:CC (match_operator:DI 4 "boolean_operator"
7738 [(match_operand:DI 1 "gpc_reg_operand" "")
7739 (match_operand:DI 2 "gpc_reg_operand" "")])
7740 (const_int 0)))
7741 (set (match_operand:DI 0 "gpc_reg_operand" "")
7742 (match_dup 4))]
7743 "TARGET_POWERPC64 && reload_completed"
7744 [(set (match_dup 0) (match_dup 4))
7745 (set (match_dup 3)
7746 (compare:CC (match_dup 0)
7747 (const_int 0)))]
7748 "")
7750 ;; Split a logical operation that we can't do in one insn into two insns,
7751 ;; each of which does one 16-bit part. This is used by combine.
7753 (define_split
7754 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7755 (match_operator:DI 3 "boolean_or_operator"
7756 [(match_operand:DI 1 "gpc_reg_operand" "")
7757 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7758 "TARGET_POWERPC64"
7759 [(set (match_dup 0) (match_dup 4))
7760 (set (match_dup 0) (match_dup 5))]
7761 "
7762 {
7763 rtx i3,i4;
7765 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7766 {
7767 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7768 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7769 0, DImode);
7770 i4 = GEN_INT (value & 0xffff);
7771 }
7772 else
7773 {
7774 i3 = GEN_INT (INTVAL (operands[2])
7775 & (~ (HOST_WIDE_INT) 0xffff));
7776 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7777 }
7778 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7779 operands[1], i3);
7780 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7781 operands[0], i4);
7782 }")
7784 (define_insn "*boolcdi3_internal1"
7785 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7786 (match_operator:DI 3 "boolean_operator"
7787 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7788 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7789 "TARGET_POWERPC64"
7790 "%q3 %0,%2,%1")
7792 (define_insn "*boolcdi3_internal2"
7793 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7794 (compare:CC (match_operator:DI 4 "boolean_operator"
7795 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7796 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7797 (const_int 0)))
7798 (clobber (match_scratch:DI 3 "=r,r"))]
7799 "TARGET_64BIT"
7800 "@
7801 %q4. %3,%2,%1
7802 #"
7803 [(set_attr "type" "compare")
7804 (set_attr "length" "4,8")])
7806 (define_split
7807 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7808 (compare:CC (match_operator:DI 4 "boolean_operator"
7809 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7810 (match_operand:DI 2 "gpc_reg_operand" "")])
7811 (const_int 0)))
7812 (clobber (match_scratch:DI 3 ""))]
7813 "TARGET_POWERPC64 && reload_completed"
7814 [(set (match_dup 3) (match_dup 4))
7815 (set (match_dup 0)
7816 (compare:CC (match_dup 3)
7817 (const_int 0)))]
7818 "")
7820 (define_insn "*boolcdi3_internal3"
7821 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7822 (compare:CC (match_operator:DI 4 "boolean_operator"
7823 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7824 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7825 (const_int 0)))
7826 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7827 (match_dup 4))]
7828 "TARGET_64BIT"
7829 "@
7830 %q4. %0,%2,%1
7831 #"
7832 [(set_attr "type" "compare")
7833 (set_attr "length" "4,8")])
7835 (define_split
7836 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7837 (compare:CC (match_operator:DI 4 "boolean_operator"
7838 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7839 (match_operand:DI 2 "gpc_reg_operand" "")])
7840 (const_int 0)))
7841 (set (match_operand:DI 0 "gpc_reg_operand" "")
7842 (match_dup 4))]
7843 "TARGET_POWERPC64 && reload_completed"
7844 [(set (match_dup 0) (match_dup 4))
7845 (set (match_dup 3)
7846 (compare:CC (match_dup 0)
7847 (const_int 0)))]
7848 "")
7850 (define_insn "*boolccdi3_internal1"
7851 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7852 (match_operator:DI 3 "boolean_operator"
7853 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7854 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7855 "TARGET_POWERPC64"
7856 "%q3 %0,%1,%2")
7858 (define_insn "*boolccdi3_internal2"
7859 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7860 (compare:CC (match_operator:DI 4 "boolean_operator"
7861 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7862 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7863 (const_int 0)))
7864 (clobber (match_scratch:DI 3 "=r,r"))]
7865 "TARGET_64BIT"
7866 "@
7867 %q4. %3,%1,%2
7868 #"
7869 [(set_attr "type" "compare")
7870 (set_attr "length" "4,8")])
7872 (define_split
7873 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7874 (compare:CC (match_operator:DI 4 "boolean_operator"
7875 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7876 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7877 (const_int 0)))
7878 (clobber (match_scratch:DI 3 ""))]
7879 "TARGET_POWERPC64 && reload_completed"
7880 [(set (match_dup 3) (match_dup 4))
7881 (set (match_dup 0)
7882 (compare:CC (match_dup 3)
7883 (const_int 0)))]
7884 "")
7886 (define_insn "*boolccdi3_internal3"
7887 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7888 (compare:CC (match_operator:DI 4 "boolean_operator"
7889 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7890 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7891 (const_int 0)))
7892 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7893 (match_dup 4))]
7894 "TARGET_64BIT"
7895 "@
7896 %q4. %0,%1,%2
7897 #"
7898 [(set_attr "type" "compare")
7899 (set_attr "length" "4,8")])
7901 (define_split
7902 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7903 (compare:CC (match_operator:DI 4 "boolean_operator"
7904 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7905 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7906 (const_int 0)))
7907 (set (match_operand:DI 0 "gpc_reg_operand" "")
7908 (match_dup 4))]
7909 "TARGET_POWERPC64 && reload_completed"
7910 [(set (match_dup 0) (match_dup 4))
7911 (set (match_dup 3)
7912 (compare:CC (match_dup 0)
7913 (const_int 0)))]
7914 "")
7915 \f
7916 ;; Now define ways of moving data around.
7918 ;; Set up a register with a value from the GOT table
7920 (define_expand "movsi_got"
7921 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7922 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7923 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7924 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7925 "
7926 {
7927 if (GET_CODE (operands[1]) == CONST)
7928 {
7929 rtx offset = const0_rtx;
7930 HOST_WIDE_INT value;
7932 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7933 value = INTVAL (offset);
7934 if (value != 0)
7935 {
7936 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7937 emit_insn (gen_movsi_got (tmp, operands[1]));
7938 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7939 DONE;
7940 }
7941 }
7943 operands[2] = rs6000_got_register (operands[1]);
7944 }")
7946 (define_insn "*movsi_got_internal"
7947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7948 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7949 (match_operand:SI 2 "gpc_reg_operand" "b")]
7950 UNSPEC_MOVSI_GOT))]
7951 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7952 "{l|lwz} %0,%a1@got(%2)"
7953 [(set_attr "type" "load")])
7955 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7956 ;; didn't get allocated to a hard register.
7957 (define_split
7958 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7959 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7960 (match_operand:SI 2 "memory_operand" "")]
7961 UNSPEC_MOVSI_GOT))]
7962 "DEFAULT_ABI == ABI_V4
7963 && flag_pic == 1
7964 && (reload_in_progress || reload_completed)"
7965 [(set (match_dup 0) (match_dup 2))
7966 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7967 UNSPEC_MOVSI_GOT))]
7968 "")
7970 ;; For SI, we special-case integers that can't be loaded in one insn. We
7971 ;; do the load 16-bits at a time. We could do this by loading from memory,
7972 ;; and this is even supposed to be faster, but it is simpler not to get
7973 ;; integers in the TOC.
7974 (define_insn "movsi_low"
7975 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7976 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7977 (match_operand 2 "" ""))))]
7978 "TARGET_MACHO && ! TARGET_64BIT"
7979 "{l|lwz} %0,lo16(%2)(%1)"
7980 [(set_attr "type" "load")
7981 (set_attr "length" "4")])
7983 (define_insn "*movsi_internal1"
7984 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7985 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7986 "gpc_reg_operand (operands[0], SImode)
7987 || gpc_reg_operand (operands[1], SImode)"
7988 "@
7989 mr %0,%1
7990 {cal|la} %0,%a1
7991 {l%U1%X1|lwz%U1%X1} %0,%1
7992 {st%U0%X0|stw%U0%X0} %1,%0
7993 {lil|li} %0,%1
7994 {liu|lis} %0,%v1
7995 #
7996 {cal|la} %0,%a1
7997 mf%1 %0
7998 mt%0 %1
7999 mt%0 %1
8000 mt%0 %1
8001 {cror 0,0,0|nop}"
8002 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8003 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8005 ;; Split a load of a large constant into the appropriate two-insn
8006 ;; sequence.
8008 (define_split
8009 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8010 (match_operand:SI 1 "const_int_operand" ""))]
8011 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8012 && (INTVAL (operands[1]) & 0xffff) != 0"
8013 [(set (match_dup 0)
8014 (match_dup 2))
8015 (set (match_dup 0)
8016 (ior:SI (match_dup 0)
8017 (match_dup 3)))]
8018 "
8019 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8021 if (tem == operands[0])
8022 DONE;
8023 else
8024 FAIL;
8025 }")
8027 (define_insn "*mov<mode>_internal2"
8028 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8029 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8030 (const_int 0)))
8031 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8032 ""
8033 "@
8034 {cmpi|cmp<wd>i} %2,%0,0
8035 mr. %0,%1
8036 #"
8037 [(set_attr "type" "cmp,compare,cmp")
8038 (set_attr "length" "4,4,8")])
8040 (define_split
8041 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8042 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8043 (const_int 0)))
8044 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8045 "reload_completed"
8046 [(set (match_dup 0) (match_dup 1))
8047 (set (match_dup 2)
8048 (compare:CC (match_dup 0)
8049 (const_int 0)))]
8050 "")
8051 \f
8052 (define_insn "*movhi_internal"
8053 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8054 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8055 "gpc_reg_operand (operands[0], HImode)
8056 || gpc_reg_operand (operands[1], HImode)"
8057 "@
8058 mr %0,%1
8059 lhz%U1%X1 %0,%1
8060 sth%U0%X0 %1,%0
8061 {lil|li} %0,%w1
8062 mf%1 %0
8063 mt%0 %1
8064 mt%0 %1
8065 {cror 0,0,0|nop}"
8066 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8068 (define_expand "mov<mode>"
8069 [(set (match_operand:INT 0 "general_operand" "")
8070 (match_operand:INT 1 "any_operand" ""))]
8071 ""
8072 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8074 (define_insn "*movqi_internal"
8075 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8076 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8077 "gpc_reg_operand (operands[0], QImode)
8078 || gpc_reg_operand (operands[1], QImode)"
8079 "@
8080 mr %0,%1
8081 lbz%U1%X1 %0,%1
8082 stb%U0%X0 %1,%0
8083 {lil|li} %0,%1
8084 mf%1 %0
8085 mt%0 %1
8086 mt%0 %1
8087 {cror 0,0,0|nop}"
8088 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8089 \f
8090 ;; Here is how to move condition codes around. When we store CC data in
8091 ;; an integer register or memory, we store just the high-order 4 bits.
8092 ;; This lets us not shift in the most common case of CR0.
8093 (define_expand "movcc"
8094 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8095 (match_operand:CC 1 "nonimmediate_operand" ""))]
8096 ""
8097 "")
8099 (define_insn "*movcc_internal1"
8100 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8101 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8102 "register_operand (operands[0], CCmode)
8103 || register_operand (operands[1], CCmode)"
8104 "@
8105 mcrf %0,%1
8106 mtcrf 128,%1
8107 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8108 crxor %0,%0,%0
8109 mfcr %0%Q1
8110 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8111 mr %0,%1
8112 {lil|li} %0,%1
8113 mf%1 %0
8114 mt%0 %1
8115 mt%0 %1
8116 {l%U1%X1|lwz%U1%X1} %0,%1
8117 {st%U0%U1|stw%U0%U1} %1,%0"
8118 [(set (attr "type")
8119 (cond [(eq_attr "alternative" "0,3")
8120 (const_string "cr_logical")
8121 (eq_attr "alternative" "1,2")
8122 (const_string "mtcr")
8123 (eq_attr "alternative" "6,7,9")
8124 (const_string "integer")
8125 (eq_attr "alternative" "8")
8126 (const_string "mfjmpr")
8127 (eq_attr "alternative" "10")
8128 (const_string "mtjmpr")
8129 (eq_attr "alternative" "11")
8130 (const_string "load")
8131 (eq_attr "alternative" "12")
8132 (const_string "store")
8133 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8134 (const_string "mfcrf")
8135 ]
8136 (const_string "mfcr")))
8137 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8138 \f
8139 ;; For floating-point, we normally deal with the floating-point registers
8140 ;; unless -msoft-float is used. The sole exception is that parameter passing
8141 ;; can produce floating-point values in fixed-point registers. Unless the
8142 ;; value is a simple constant or already in memory, we deal with this by
8143 ;; allocating memory and copying the value explicitly via that memory location.
8144 (define_expand "movsf"
8145 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8146 (match_operand:SF 1 "any_operand" ""))]
8147 ""
8148 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8150 (define_split
8151 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8152 (match_operand:SF 1 "const_double_operand" ""))]
8153 "reload_completed
8154 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8155 || (GET_CODE (operands[0]) == SUBREG
8156 && GET_CODE (SUBREG_REG (operands[0])) == REG
8157 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8158 [(set (match_dup 2) (match_dup 3))]
8159 "
8160 {
8161 long l;
8162 REAL_VALUE_TYPE rv;
8164 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8165 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8167 if (! TARGET_POWERPC64)
8168 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8169 else
8170 operands[2] = gen_lowpart (SImode, operands[0]);
8172 operands[3] = gen_int_mode (l, SImode);
8173 }")
8175 (define_insn "*movsf_hardfloat"
8176 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8177 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8178 "(gpc_reg_operand (operands[0], SFmode)
8179 || gpc_reg_operand (operands[1], SFmode))
8180 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8181 "@
8182 mr %0,%1
8183 {l%U1%X1|lwz%U1%X1} %0,%1
8184 {st%U0%X0|stw%U0%X0} %1,%0
8185 fmr %0,%1
8186 lfs%U1%X1 %0,%1
8187 stfs%U0%X0 %1,%0
8188 mt%0 %1
8189 mt%0 %1
8190 mf%1 %0
8191 {cror 0,0,0|nop}
8192 #
8193 #"
8194 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8195 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8197 (define_insn "*movsf_softfloat"
8198 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8199 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8200 "(gpc_reg_operand (operands[0], SFmode)
8201 || gpc_reg_operand (operands[1], SFmode))
8202 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8203 "@
8204 mr %0,%1
8205 mt%0 %1
8206 mt%0 %1
8207 mf%1 %0
8208 {l%U1%X1|lwz%U1%X1} %0,%1
8209 {st%U0%X0|stw%U0%X0} %1,%0
8210 {lil|li} %0,%1
8211 {liu|lis} %0,%v1
8212 {cal|la} %0,%a1
8213 #
8214 #
8215 {cror 0,0,0|nop}"
8216 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8217 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8219 \f
8220 (define_expand "movdf"
8221 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8222 (match_operand:DF 1 "any_operand" ""))]
8223 ""
8224 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8226 (define_split
8227 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8228 (match_operand:DF 1 "const_int_operand" ""))]
8229 "! TARGET_POWERPC64 && reload_completed
8230 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8231 || (GET_CODE (operands[0]) == SUBREG
8232 && GET_CODE (SUBREG_REG (operands[0])) == REG
8233 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8234 [(set (match_dup 2) (match_dup 4))
8235 (set (match_dup 3) (match_dup 1))]
8236 "
8237 {
8238 int endian = (WORDS_BIG_ENDIAN == 0);
8239 HOST_WIDE_INT value = INTVAL (operands[1]);
8241 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8242 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8243 #if HOST_BITS_PER_WIDE_INT == 32
8244 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8245 #else
8246 operands[4] = GEN_INT (value >> 32);
8247 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8248 #endif
8249 }")
8251 (define_split
8252 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8253 (match_operand:DF 1 "const_double_operand" ""))]
8254 "! TARGET_POWERPC64 && reload_completed
8255 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8256 || (GET_CODE (operands[0]) == SUBREG
8257 && GET_CODE (SUBREG_REG (operands[0])) == REG
8258 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8259 [(set (match_dup 2) (match_dup 4))
8260 (set (match_dup 3) (match_dup 5))]
8261 "
8262 {
8263 int endian = (WORDS_BIG_ENDIAN == 0);
8264 long l[2];
8265 REAL_VALUE_TYPE rv;
8267 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8268 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8270 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8271 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8272 operands[4] = gen_int_mode (l[endian], SImode);
8273 operands[5] = gen_int_mode (l[1 - endian], SImode);
8274 }")
8276 (define_split
8277 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8278 (match_operand:DF 1 "const_double_operand" ""))]
8279 "TARGET_POWERPC64 && reload_completed
8280 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8281 || (GET_CODE (operands[0]) == SUBREG
8282 && GET_CODE (SUBREG_REG (operands[0])) == REG
8283 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8284 [(set (match_dup 2) (match_dup 3))]
8285 "
8286 {
8287 int endian = (WORDS_BIG_ENDIAN == 0);
8288 long l[2];
8289 REAL_VALUE_TYPE rv;
8290 #if HOST_BITS_PER_WIDE_INT >= 64
8291 HOST_WIDE_INT val;
8292 #endif
8294 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8295 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8297 operands[2] = gen_lowpart (DImode, operands[0]);
8298 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8299 #if HOST_BITS_PER_WIDE_INT >= 64
8300 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8301 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8303 operands[3] = gen_int_mode (val, DImode);
8304 #else
8305 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8306 #endif
8307 }")
8309 ;; Don't have reload use general registers to load a constant. First,
8310 ;; it might not work if the output operand is the equivalent of
8311 ;; a non-offsettable memref, but also it is less efficient than loading
8312 ;; the constant into an FP register, since it will probably be used there.
8313 ;; The "??" is a kludge until we can figure out a more reasonable way
8314 ;; of handling these non-offsettable values.
8315 (define_insn "*movdf_hardfloat32"
8316 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8317 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8318 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8319 && (gpc_reg_operand (operands[0], DFmode)
8320 || gpc_reg_operand (operands[1], DFmode))"
8321 "*
8322 {
8323 switch (which_alternative)
8324 {
8325 default:
8326 gcc_unreachable ();
8327 case 0:
8328 /* We normally copy the low-numbered register first. However, if
8329 the first register operand 0 is the same as the second register
8330 of operand 1, we must copy in the opposite order. */
8331 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8332 return \"mr %L0,%L1\;mr %0,%1\";
8333 else
8334 return \"mr %0,%1\;mr %L0,%L1\";
8335 case 1:
8336 if (rs6000_offsettable_memref_p (operands[1])
8337 || (GET_CODE (operands[1]) == MEM
8338 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8339 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8340 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8341 {
8342 /* If the low-address word is used in the address, we must load
8343 it last. Otherwise, load it first. Note that we cannot have
8344 auto-increment in that case since the address register is
8345 known to be dead. */
8346 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8347 operands[1], 0))
8348 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8349 else
8350 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8351 }
8352 else
8353 {
8354 rtx addreg;
8356 addreg = find_addr_reg (XEXP (operands[1], 0));
8357 if (refers_to_regno_p (REGNO (operands[0]),
8358 REGNO (operands[0]) + 1,
8359 operands[1], 0))
8360 {
8361 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8362 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8363 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8364 return \"{l%X1|lwz%X1} %0,%1\";
8365 }
8366 else
8367 {
8368 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8369 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8370 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8371 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8372 return \"\";
8373 }
8374 }
8375 case 2:
8376 if (rs6000_offsettable_memref_p (operands[0])
8377 || (GET_CODE (operands[0]) == MEM
8378 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8379 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8380 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8381 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8382 else
8383 {
8384 rtx addreg;
8386 addreg = find_addr_reg (XEXP (operands[0], 0));
8387 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8388 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8389 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8390 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8391 return \"\";
8392 }
8393 case 3:
8394 return \"fmr %0,%1\";
8395 case 4:
8396 return \"lfd%U1%X1 %0,%1\";
8397 case 5:
8398 return \"stfd%U0%X0 %1,%0\";
8399 case 6:
8400 case 7:
8401 case 8:
8402 return \"#\";
8403 }
8404 }"
8405 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8406 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8408 (define_insn "*movdf_softfloat32"
8409 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8410 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8411 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8412 && (gpc_reg_operand (operands[0], DFmode)
8413 || gpc_reg_operand (operands[1], DFmode))"
8414 "*
8415 {
8416 switch (which_alternative)
8417 {
8418 default:
8419 gcc_unreachable ();
8420 case 0:
8421 /* We normally copy the low-numbered register first. However, if
8422 the first register operand 0 is the same as the second register of
8423 operand 1, we must copy in the opposite order. */
8424 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8425 return \"mr %L0,%L1\;mr %0,%1\";
8426 else
8427 return \"mr %0,%1\;mr %L0,%L1\";
8428 case 1:
8429 /* If the low-address word is used in the address, we must load
8430 it last. Otherwise, load it first. Note that we cannot have
8431 auto-increment in that case since the address register is
8432 known to be dead. */
8433 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8434 operands[1], 0))
8435 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8436 else
8437 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8438 case 2:
8439 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8440 case 3:
8441 case 4:
8442 case 5:
8443 return \"#\";
8444 }
8445 }"
8446 [(set_attr "type" "two,load,store,*,*,*")
8447 (set_attr "length" "8,8,8,8,12,16")])
8449 ; ld/std require word-aligned displacements -> 'Y' constraint.
8450 ; List Y->r and r->Y before r->r for reload.
8451 (define_insn "*movdf_hardfloat64_mfpgpr"
8452 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8453 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8454 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8455 && (gpc_reg_operand (operands[0], DFmode)
8456 || gpc_reg_operand (operands[1], DFmode))"
8457 "@
8458 std%U0%X0 %1,%0
8459 ld%U1%X1 %0,%1
8460 mr %0,%1
8461 fmr %0,%1
8462 lfd%U1%X1 %0,%1
8463 stfd%U0%X0 %1,%0
8464 mt%0 %1
8465 mf%1 %0
8466 {cror 0,0,0|nop}
8467 #
8468 #
8469 #
8470 mftgpr %0,%1
8471 mffgpr %0,%1"
8472 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8473 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8475 ; ld/std require word-aligned displacements -> 'Y' constraint.
8476 ; List Y->r and r->Y before r->r for reload.
8477 (define_insn "*movdf_hardfloat64"
8478 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8479 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8480 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8481 && (gpc_reg_operand (operands[0], DFmode)
8482 || gpc_reg_operand (operands[1], DFmode))"
8483 "@
8484 std%U0%X0 %1,%0
8485 ld%U1%X1 %0,%1
8486 mr %0,%1
8487 fmr %0,%1
8488 lfd%U1%X1 %0,%1
8489 stfd%U0%X0 %1,%0
8490 mt%0 %1
8491 mf%1 %0
8492 {cror 0,0,0|nop}
8493 #
8494 #
8495 #"
8496 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8497 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8499 (define_insn "*movdf_softfloat64"
8500 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8501 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8502 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8503 && (gpc_reg_operand (operands[0], DFmode)
8504 || gpc_reg_operand (operands[1], DFmode))"
8505 "@
8506 ld%U1%X1 %0,%1
8507 std%U0%X0 %1,%0
8508 mr %0,%1
8509 mt%0 %1
8510 mf%1 %0
8511 #
8512 #
8513 #
8514 {cror 0,0,0|nop}"
8515 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8516 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8517 \f
8518 (define_expand "movtf"
8519 [(set (match_operand:TF 0 "general_operand" "")
8520 (match_operand:TF 1 "any_operand" ""))]
8521 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8522 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8524 ; It's important to list the o->f and f->o moves before f->f because
8525 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8526 ; which doesn't make progress. Likewise r->Y must be before r->r.
8527 (define_insn_and_split "*movtf_internal"
8528 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8529 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8530 "!TARGET_IEEEQUAD
8531 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8532 && (gpc_reg_operand (operands[0], TFmode)
8533 || gpc_reg_operand (operands[1], TFmode))"
8534 "#"
8535 "&& reload_completed"
8536 [(pc)]
8537 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8538 [(set_attr "length" "8,8,8,20,20,16")])
8540 (define_insn_and_split "*movtf_softfloat"
8541 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8542 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8543 "!TARGET_IEEEQUAD
8544 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8545 && (gpc_reg_operand (operands[0], TFmode)
8546 || gpc_reg_operand (operands[1], TFmode))"
8547 "#"
8548 "&& reload_completed"
8549 [(pc)]
8550 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8551 [(set_attr "length" "20,20,16")])
8553 (define_expand "extenddftf2"
8554 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8555 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8556 "!TARGET_IEEEQUAD
8557 && TARGET_HARD_FLOAT
8558 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8559 && TARGET_LONG_DOUBLE_128"
8560 {
8561 if (TARGET_E500_DOUBLE)
8562 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8563 else
8564 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8565 DONE;
8566 })
8568 (define_expand "extenddftf2_fprs"
8569 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8570 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8571 (use (match_dup 2))])]
8572 "!TARGET_IEEEQUAD
8573 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8574 {
8575 operands[2] = CONST0_RTX (DFmode);
8576 /* Generate GOT reference early for SVR4 PIC. */
8577 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8578 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8579 })
8581 (define_insn_and_split "*extenddftf2_internal"
8582 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8583 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8584 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8585 "!TARGET_IEEEQUAD
8586 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8587 "#"
8588 "&& reload_completed"
8589 [(pc)]
8590 {
8591 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8592 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8593 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8594 operands[1]);
8595 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8596 operands[2]);
8597 DONE;
8598 })
8600 (define_expand "extendsftf2"
8601 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8602 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8603 "!TARGET_IEEEQUAD
8604 && TARGET_HARD_FLOAT
8605 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8606 && TARGET_LONG_DOUBLE_128"
8607 {
8608 rtx tmp = gen_reg_rtx (DFmode);
8609 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8610 emit_insn (gen_extenddftf2 (operands[0], tmp));
8611 DONE;
8612 })
8614 (define_expand "trunctfdf2"
8615 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8616 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8617 "!TARGET_IEEEQUAD
8618 && TARGET_HARD_FLOAT
8619 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8620 && TARGET_LONG_DOUBLE_128"
8621 "")
8623 (define_insn_and_split "trunctfdf2_internal1"
8624 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8625 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8626 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8627 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8628 "@
8629 #
8630 fmr %0,%1"
8631 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8632 [(const_int 0)]
8633 {
8634 emit_note (NOTE_INSN_DELETED);
8635 DONE;
8636 }
8637 [(set_attr "type" "fp")])
8639 (define_insn "trunctfdf2_internal2"
8640 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8641 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8642 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8643 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8644 "fadd %0,%1,%L1"
8645 [(set_attr "type" "fp")])
8647 (define_expand "trunctfsf2"
8648 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8649 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8650 "!TARGET_IEEEQUAD
8651 && TARGET_HARD_FLOAT
8652 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8653 && TARGET_LONG_DOUBLE_128"
8654 {
8655 if (TARGET_E500_DOUBLE)
8656 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8657 else
8658 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8659 DONE;
8660 })
8662 (define_insn_and_split "trunctfsf2_fprs"
8663 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8664 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8665 (clobber (match_scratch:DF 2 "=f"))]
8666 "!TARGET_IEEEQUAD
8667 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8668 "#"
8669 "&& reload_completed"
8670 [(set (match_dup 2)
8671 (float_truncate:DF (match_dup 1)))
8672 (set (match_dup 0)
8673 (float_truncate:SF (match_dup 2)))]
8674 "")
8676 (define_expand "floatsitf2"
8677 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8678 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8679 "!TARGET_IEEEQUAD
8680 && TARGET_HARD_FLOAT
8681 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8682 && TARGET_LONG_DOUBLE_128"
8683 {
8684 rtx tmp = gen_reg_rtx (DFmode);
8685 expand_float (tmp, operands[1], false);
8686 emit_insn (gen_extenddftf2 (operands[0], tmp));
8687 DONE;
8688 })
8690 ; fadd, but rounding towards zero.
8691 ; This is probably not the optimal code sequence.
8692 (define_insn "fix_trunc_helper"
8693 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8694 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8695 UNSPEC_FIX_TRUNC_TF))
8696 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8697 "TARGET_HARD_FLOAT && TARGET_FPRS"
8698 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8699 [(set_attr "type" "fp")
8700 (set_attr "length" "20")])
8702 (define_expand "fix_trunctfsi2"
8703 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8704 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8705 "!TARGET_IEEEQUAD
8706 && (TARGET_POWER2 || TARGET_POWERPC)
8707 && TARGET_HARD_FLOAT
8708 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8709 && TARGET_LONG_DOUBLE_128"
8710 {
8711 if (TARGET_E500_DOUBLE)
8712 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8713 else
8714 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8715 DONE;
8716 })
8718 (define_expand "fix_trunctfsi2_fprs"
8719 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8720 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8721 (clobber (match_dup 2))
8722 (clobber (match_dup 3))
8723 (clobber (match_dup 4))
8724 (clobber (match_dup 5))])]
8725 "!TARGET_IEEEQUAD
8726 && (TARGET_POWER2 || TARGET_POWERPC)
8727 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8728 {
8729 operands[2] = gen_reg_rtx (DFmode);
8730 operands[3] = gen_reg_rtx (DFmode);
8731 operands[4] = gen_reg_rtx (DImode);
8732 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8733 })
8735 (define_insn_and_split "*fix_trunctfsi2_internal"
8736 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8737 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8738 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8739 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8740 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8741 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8742 "!TARGET_IEEEQUAD
8743 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8744 "#"
8745 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8746 [(pc)]
8747 {
8748 rtx lowword;
8749 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8751 gcc_assert (MEM_P (operands[5]));
8752 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8754 emit_insn (gen_fctiwz (operands[4], operands[2]));
8755 emit_move_insn (operands[5], operands[4]);
8756 emit_move_insn (operands[0], lowword);
8757 DONE;
8758 })
8760 (define_expand "negtf2"
8761 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8762 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8763 "!TARGET_IEEEQUAD
8764 && TARGET_HARD_FLOAT
8765 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8766 && TARGET_LONG_DOUBLE_128"
8767 "")
8769 (define_insn "negtf2_internal"
8770 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8771 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8772 "!TARGET_IEEEQUAD
8773 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8774 "*
8775 {
8776 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8777 return \"fneg %L0,%L1\;fneg %0,%1\";
8778 else
8779 return \"fneg %0,%1\;fneg %L0,%L1\";
8780 }"
8781 [(set_attr "type" "fp")
8782 (set_attr "length" "8")])
8784 (define_expand "abstf2"
8785 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8786 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8787 "!TARGET_IEEEQUAD
8788 && TARGET_HARD_FLOAT
8789 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8790 && TARGET_LONG_DOUBLE_128"
8791 "
8792 {
8793 rtx label = gen_label_rtx ();
8794 if (TARGET_E500_DOUBLE)
8795 {
8796 if (flag_unsafe_math_optimizations)
8797 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8798 else
8799 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8800 }
8801 else
8802 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8803 emit_label (label);
8804 DONE;
8805 }")
8807 (define_expand "abstf2_internal"
8808 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8809 (match_operand:TF 1 "gpc_reg_operand" ""))
8810 (set (match_dup 3) (match_dup 5))
8811 (set (match_dup 5) (abs:DF (match_dup 5)))
8812 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8813 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8814 (label_ref (match_operand 2 "" ""))
8815 (pc)))
8816 (set (match_dup 6) (neg:DF (match_dup 6)))]
8817 "!TARGET_IEEEQUAD
8818 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8819 "
8820 {
8821 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8822 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8823 operands[3] = gen_reg_rtx (DFmode);
8824 operands[4] = gen_reg_rtx (CCFPmode);
8825 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8826 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8827 }")
8828 \f
8829 ;; Next come the multi-word integer load and store and the load and store
8830 ;; multiple insns.
8832 ; List r->r after r->"o<>", otherwise reload will try to reload a
8833 ; non-offsettable address by using r->r which won't make progress.
8834 (define_insn "*movdi_internal32"
8835 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8836 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8837 "! TARGET_POWERPC64
8838 && (gpc_reg_operand (operands[0], DImode)
8839 || gpc_reg_operand (operands[1], DImode))"
8840 "@
8841 #
8842 #
8843 #
8844 fmr %0,%1
8845 lfd%U1%X1 %0,%1
8846 stfd%U0%X0 %1,%0
8847 #"
8848 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8850 (define_split
8851 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8852 (match_operand:DI 1 "const_int_operand" ""))]
8853 "! TARGET_POWERPC64 && reload_completed"
8854 [(set (match_dup 2) (match_dup 4))
8855 (set (match_dup 3) (match_dup 1))]
8856 "
8857 {
8858 HOST_WIDE_INT value = INTVAL (operands[1]);
8859 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8860 DImode);
8861 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8862 DImode);
8863 #if HOST_BITS_PER_WIDE_INT == 32
8864 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8865 #else
8866 operands[4] = GEN_INT (value >> 32);
8867 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8868 #endif
8869 }")
8871 (define_split
8872 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
8873 (match_operand:DI 1 "input_operand" ""))]
8874 "reload_completed && !TARGET_POWERPC64
8875 && gpr_or_gpr_p (operands[0], operands[1])"
8876 [(pc)]
8877 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8879 (define_insn "*movdi_mfpgpr"
8880 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8881 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8882 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8883 && (gpc_reg_operand (operands[0], DImode)
8884 || gpc_reg_operand (operands[1], DImode))"
8885 "@
8886 mr %0,%1
8887 ld%U1%X1 %0,%1
8888 std%U0%X0 %1,%0
8889 li %0,%1
8890 lis %0,%v1
8891 #
8892 {cal|la} %0,%a1
8893 fmr %0,%1
8894 lfd%U1%X1 %0,%1
8895 stfd%U0%X0 %1,%0
8896 mf%1 %0
8897 mt%0 %1
8898 {cror 0,0,0|nop}
8899 mftgpr %0,%1
8900 mffgpr %0,%1"
8901 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8902 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8904 (define_insn "*movdi_internal64"
8905 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8906 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8907 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8908 && (gpc_reg_operand (operands[0], DImode)
8909 || gpc_reg_operand (operands[1], DImode))"
8910 "@
8911 mr %0,%1
8912 ld%U1%X1 %0,%1
8913 std%U0%X0 %1,%0
8914 li %0,%1
8915 lis %0,%v1
8916 #
8917 {cal|la} %0,%a1
8918 fmr %0,%1
8919 lfd%U1%X1 %0,%1
8920 stfd%U0%X0 %1,%0
8921 mf%1 %0
8922 mt%0 %1
8923 {cror 0,0,0|nop}"
8924 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8925 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8927 ;; immediate value valid for a single instruction hiding in a const_double
8928 (define_insn ""
8929 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8930 (match_operand:DI 1 "const_double_operand" "F"))]
8931 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8932 && GET_CODE (operands[1]) == CONST_DOUBLE
8933 && num_insns_constant (operands[1], DImode) == 1"
8934 "*
8935 {
8936 return ((unsigned HOST_WIDE_INT)
8937 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8938 ? \"li %0,%1\" : \"lis %0,%v1\";
8939 }")
8941 ;; Generate all one-bits and clear left or right.
8942 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8943 (define_split
8944 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8945 (match_operand:DI 1 "mask64_operand" ""))]
8946 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8947 [(set (match_dup 0) (const_int -1))
8948 (set (match_dup 0)
8949 (and:DI (rotate:DI (match_dup 0)
8950 (const_int 0))
8951 (match_dup 1)))]
8952 "")
8954 ;; Split a load of a large constant into the appropriate five-instruction
8955 ;; sequence. Handle anything in a constant number of insns.
8956 ;; When non-easy constants can go in the TOC, this should use
8957 ;; easy_fp_constant predicate.
8958 (define_split
8959 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8960 (match_operand:DI 1 "const_int_operand" ""))]
8961 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8962 [(set (match_dup 0) (match_dup 2))
8963 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8964 "
8965 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8967 if (tem == operands[0])
8968 DONE;
8969 else
8970 FAIL;
8971 }")
8973 (define_split
8974 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8975 (match_operand:DI 1 "const_double_operand" ""))]
8976 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8977 [(set (match_dup 0) (match_dup 2))
8978 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8979 "
8980 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8982 if (tem == operands[0])
8983 DONE;
8984 else
8985 FAIL;
8986 }")
8987 \f
8988 ;; TImode is similar, except that we usually want to compute the address into
8989 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8990 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8992 ;; We say that MQ is clobbered in the last alternative because the first
8993 ;; alternative would never get used otherwise since it would need a reload
8994 ;; while the 2nd alternative would not. We put memory cases first so they
8995 ;; are preferred. Otherwise, we'd try to reload the output instead of
8996 ;; giving the SCRATCH mq.
8998 (define_insn "*movti_power"
8999 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9000 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9001 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9002 "TARGET_POWER && ! TARGET_POWERPC64
9003 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9004 "*
9005 {
9006 switch (which_alternative)
9007 {
9008 default:
9009 gcc_unreachable ();
9011 case 0:
9012 if (TARGET_STRING)
9013 return \"{stsi|stswi} %1,%P0,16\";
9014 case 1:
9015 case 2:
9016 return \"#\";
9017 case 3:
9018 /* If the address is not used in the output, we can use lsi. Otherwise,
9019 fall through to generating four loads. */
9020 if (TARGET_STRING
9021 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9022 return \"{lsi|lswi} %0,%P1,16\";
9023 /* ... fall through ... */
9024 case 4:
9025 case 5:
9026 return \"#\";
9027 }
9028 }"
9029 [(set_attr "type" "store,store,*,load,load,*")])
9031 (define_insn "*movti_string"
9032 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9033 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9034 "! TARGET_POWER && ! TARGET_POWERPC64
9035 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9036 "*
9037 {
9038 switch (which_alternative)
9039 {
9040 default:
9041 gcc_unreachable ();
9042 case 0:
9043 if (TARGET_STRING)
9044 return \"{stsi|stswi} %1,%P0,16\";
9045 case 1:
9046 case 2:
9047 return \"#\";
9048 case 3:
9049 /* If the address is not used in the output, we can use lsi. Otherwise,
9050 fall through to generating four loads. */
9051 if (TARGET_STRING
9052 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9053 return \"{lsi|lswi} %0,%P1,16\";
9054 /* ... fall through ... */
9055 case 4:
9056 case 5:
9057 return \"#\";
9058 }
9059 }"
9060 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
9062 (define_insn "*movti_ppc64"
9063 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9064 (match_operand:TI 1 "input_operand" "r,r,m"))]
9065 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9066 || gpc_reg_operand (operands[1], TImode))"
9067 "#"
9068 [(set_attr "type" "*,load,store")])
9070 (define_split
9071 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9072 (match_operand:TI 1 "const_double_operand" ""))]
9073 "TARGET_POWERPC64"
9074 [(set (match_dup 2) (match_dup 4))
9075 (set (match_dup 3) (match_dup 5))]
9076 "
9077 {
9078 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9079 TImode);
9080 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9081 TImode);
9082 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9083 {
9084 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9085 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9086 }
9087 else if (GET_CODE (operands[1]) == CONST_INT)
9088 {
9089 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9090 operands[5] = operands[1];
9091 }
9092 else
9093 FAIL;
9094 }")
9096 (define_split
9097 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9098 (match_operand:TI 1 "input_operand" ""))]
9099 "reload_completed
9100 && gpr_or_gpr_p (operands[0], operands[1])"
9101 [(pc)]
9102 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9103 \f
9104 (define_expand "load_multiple"
9105 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9106 (match_operand:SI 1 "" ""))
9107 (use (match_operand:SI 2 "" ""))])]
9108 "TARGET_STRING && !TARGET_POWERPC64"
9109 "
9110 {
9111 int regno;
9112 int count;
9113 rtx op1;
9114 int i;
9116 /* Support only loading a constant number of fixed-point registers from
9117 memory and only bother with this if more than two; the machine
9118 doesn't support more than eight. */
9119 if (GET_CODE (operands[2]) != CONST_INT
9120 || INTVAL (operands[2]) <= 2
9121 || INTVAL (operands[2]) > 8
9122 || GET_CODE (operands[1]) != MEM
9123 || GET_CODE (operands[0]) != REG
9124 || REGNO (operands[0]) >= 32)
9125 FAIL;
9127 count = INTVAL (operands[2]);
9128 regno = REGNO (operands[0]);
9130 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9131 op1 = replace_equiv_address (operands[1],
9132 force_reg (SImode, XEXP (operands[1], 0)));
9134 for (i = 0; i < count; i++)
9135 XVECEXP (operands[3], 0, i)
9136 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9137 adjust_address_nv (op1, SImode, i * 4));
9138 }")
9140 (define_insn "*ldmsi8"
9141 [(match_parallel 0 "load_multiple_operation"
9142 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9143 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9144 (set (match_operand:SI 3 "gpc_reg_operand" "")
9145 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9146 (set (match_operand:SI 4 "gpc_reg_operand" "")
9147 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9148 (set (match_operand:SI 5 "gpc_reg_operand" "")
9149 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9150 (set (match_operand:SI 6 "gpc_reg_operand" "")
9151 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9152 (set (match_operand:SI 7 "gpc_reg_operand" "")
9153 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9154 (set (match_operand:SI 8 "gpc_reg_operand" "")
9155 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9156 (set (match_operand:SI 9 "gpc_reg_operand" "")
9157 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9158 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9159 "*
9160 { return rs6000_output_load_multiple (operands); }"
9161 [(set_attr "type" "load_ux")
9162 (set_attr "length" "32")])
9164 (define_insn "*ldmsi7"
9165 [(match_parallel 0 "load_multiple_operation"
9166 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9167 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9168 (set (match_operand:SI 3 "gpc_reg_operand" "")
9169 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9170 (set (match_operand:SI 4 "gpc_reg_operand" "")
9171 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9172 (set (match_operand:SI 5 "gpc_reg_operand" "")
9173 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9174 (set (match_operand:SI 6 "gpc_reg_operand" "")
9175 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9176 (set (match_operand:SI 7 "gpc_reg_operand" "")
9177 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9178 (set (match_operand:SI 8 "gpc_reg_operand" "")
9179 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9180 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9181 "*
9182 { return rs6000_output_load_multiple (operands); }"
9183 [(set_attr "type" "load_ux")
9184 (set_attr "length" "32")])
9186 (define_insn "*ldmsi6"
9187 [(match_parallel 0 "load_multiple_operation"
9188 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9189 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9190 (set (match_operand:SI 3 "gpc_reg_operand" "")
9191 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9192 (set (match_operand:SI 4 "gpc_reg_operand" "")
9193 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9194 (set (match_operand:SI 5 "gpc_reg_operand" "")
9195 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9196 (set (match_operand:SI 6 "gpc_reg_operand" "")
9197 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9198 (set (match_operand:SI 7 "gpc_reg_operand" "")
9199 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9200 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9201 "*
9202 { return rs6000_output_load_multiple (operands); }"
9203 [(set_attr "type" "load_ux")
9204 (set_attr "length" "32")])
9206 (define_insn "*ldmsi5"
9207 [(match_parallel 0 "load_multiple_operation"
9208 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9209 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9210 (set (match_operand:SI 3 "gpc_reg_operand" "")
9211 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9212 (set (match_operand:SI 4 "gpc_reg_operand" "")
9213 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9214 (set (match_operand:SI 5 "gpc_reg_operand" "")
9215 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9216 (set (match_operand:SI 6 "gpc_reg_operand" "")
9217 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9218 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9219 "*
9220 { return rs6000_output_load_multiple (operands); }"
9221 [(set_attr "type" "load_ux")
9222 (set_attr "length" "32")])
9224 (define_insn "*ldmsi4"
9225 [(match_parallel 0 "load_multiple_operation"
9226 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9227 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9228 (set (match_operand:SI 3 "gpc_reg_operand" "")
9229 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9230 (set (match_operand:SI 4 "gpc_reg_operand" "")
9231 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9232 (set (match_operand:SI 5 "gpc_reg_operand" "")
9233 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9234 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9235 "*
9236 { return rs6000_output_load_multiple (operands); }"
9237 [(set_attr "type" "load_ux")
9238 (set_attr "length" "32")])
9240 (define_insn "*ldmsi3"
9241 [(match_parallel 0 "load_multiple_operation"
9242 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9243 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9244 (set (match_operand:SI 3 "gpc_reg_operand" "")
9245 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9246 (set (match_operand:SI 4 "gpc_reg_operand" "")
9247 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9248 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9249 "*
9250 { return rs6000_output_load_multiple (operands); }"
9251 [(set_attr "type" "load_ux")
9252 (set_attr "length" "32")])
9254 (define_expand "store_multiple"
9255 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9256 (match_operand:SI 1 "" ""))
9257 (clobber (scratch:SI))
9258 (use (match_operand:SI 2 "" ""))])]
9259 "TARGET_STRING && !TARGET_POWERPC64"
9260 "
9261 {
9262 int regno;
9263 int count;
9264 rtx to;
9265 rtx op0;
9266 int i;
9268 /* Support only storing a constant number of fixed-point registers to
9269 memory and only bother with this if more than two; the machine
9270 doesn't support more than eight. */
9271 if (GET_CODE (operands[2]) != CONST_INT
9272 || INTVAL (operands[2]) <= 2
9273 || INTVAL (operands[2]) > 8
9274 || GET_CODE (operands[0]) != MEM
9275 || GET_CODE (operands[1]) != REG
9276 || REGNO (operands[1]) >= 32)
9277 FAIL;
9279 count = INTVAL (operands[2]);
9280 regno = REGNO (operands[1]);
9282 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9283 to = force_reg (SImode, XEXP (operands[0], 0));
9284 op0 = replace_equiv_address (operands[0], to);
9286 XVECEXP (operands[3], 0, 0)
9287 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9288 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9289 gen_rtx_SCRATCH (SImode));
9291 for (i = 1; i < count; i++)
9292 XVECEXP (operands[3], 0, i + 1)
9293 = gen_rtx_SET (VOIDmode,
9294 adjust_address_nv (op0, SImode, i * 4),
9295 gen_rtx_REG (SImode, regno + i));
9296 }")
9298 (define_insn "*stmsi8"
9299 [(match_parallel 0 "store_multiple_operation"
9300 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9301 (match_operand:SI 2 "gpc_reg_operand" "r"))
9302 (clobber (match_scratch:SI 3 "=X"))
9303 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9304 (match_operand:SI 4 "gpc_reg_operand" "r"))
9305 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9306 (match_operand:SI 5 "gpc_reg_operand" "r"))
9307 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9308 (match_operand:SI 6 "gpc_reg_operand" "r"))
9309 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9310 (match_operand:SI 7 "gpc_reg_operand" "r"))
9311 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9312 (match_operand:SI 8 "gpc_reg_operand" "r"))
9313 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9314 (match_operand:SI 9 "gpc_reg_operand" "r"))
9315 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9316 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9317 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9318 "{stsi|stswi} %2,%1,%O0"
9319 [(set_attr "type" "store_ux")])
9321 (define_insn "*stmsi7"
9322 [(match_parallel 0 "store_multiple_operation"
9323 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9324 (match_operand:SI 2 "gpc_reg_operand" "r"))
9325 (clobber (match_scratch:SI 3 "=X"))
9326 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9327 (match_operand:SI 4 "gpc_reg_operand" "r"))
9328 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9329 (match_operand:SI 5 "gpc_reg_operand" "r"))
9330 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9331 (match_operand:SI 6 "gpc_reg_operand" "r"))
9332 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9333 (match_operand:SI 7 "gpc_reg_operand" "r"))
9334 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9335 (match_operand:SI 8 "gpc_reg_operand" "r"))
9336 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9337 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9338 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9339 "{stsi|stswi} %2,%1,%O0"
9340 [(set_attr "type" "store_ux")])
9342 (define_insn "*stmsi6"
9343 [(match_parallel 0 "store_multiple_operation"
9344 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9345 (match_operand:SI 2 "gpc_reg_operand" "r"))
9346 (clobber (match_scratch:SI 3 "=X"))
9347 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9348 (match_operand:SI 4 "gpc_reg_operand" "r"))
9349 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9350 (match_operand:SI 5 "gpc_reg_operand" "r"))
9351 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9352 (match_operand:SI 6 "gpc_reg_operand" "r"))
9353 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9354 (match_operand:SI 7 "gpc_reg_operand" "r"))
9355 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9356 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9357 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9358 "{stsi|stswi} %2,%1,%O0"
9359 [(set_attr "type" "store_ux")])
9361 (define_insn "*stmsi5"
9362 [(match_parallel 0 "store_multiple_operation"
9363 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9364 (match_operand:SI 2 "gpc_reg_operand" "r"))
9365 (clobber (match_scratch:SI 3 "=X"))
9366 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9367 (match_operand:SI 4 "gpc_reg_operand" "r"))
9368 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9369 (match_operand:SI 5 "gpc_reg_operand" "r"))
9370 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9371 (match_operand:SI 6 "gpc_reg_operand" "r"))
9372 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9373 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9374 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9375 "{stsi|stswi} %2,%1,%O0"
9376 [(set_attr "type" "store_ux")])
9378 (define_insn "*stmsi4"
9379 [(match_parallel 0 "store_multiple_operation"
9380 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9381 (match_operand:SI 2 "gpc_reg_operand" "r"))
9382 (clobber (match_scratch:SI 3 "=X"))
9383 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9384 (match_operand:SI 4 "gpc_reg_operand" "r"))
9385 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9386 (match_operand:SI 5 "gpc_reg_operand" "r"))
9387 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9388 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9389 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9390 "{stsi|stswi} %2,%1,%O0"
9391 [(set_attr "type" "store_ux")])
9393 (define_insn "*stmsi3"
9394 [(match_parallel 0 "store_multiple_operation"
9395 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9396 (match_operand:SI 2 "gpc_reg_operand" "r"))
9397 (clobber (match_scratch:SI 3 "=X"))
9398 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9399 (match_operand:SI 4 "gpc_reg_operand" "r"))
9400 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9401 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9402 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9403 "{stsi|stswi} %2,%1,%O0"
9404 [(set_attr "type" "store_ux")])
9406 (define_insn "*stmsi8_power"
9407 [(match_parallel 0 "store_multiple_operation"
9408 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9409 (match_operand:SI 2 "gpc_reg_operand" "r"))
9410 (clobber (match_scratch:SI 3 "=q"))
9411 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9412 (match_operand:SI 4 "gpc_reg_operand" "r"))
9413 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9414 (match_operand:SI 5 "gpc_reg_operand" "r"))
9415 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9416 (match_operand:SI 6 "gpc_reg_operand" "r"))
9417 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9418 (match_operand:SI 7 "gpc_reg_operand" "r"))
9419 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9420 (match_operand:SI 8 "gpc_reg_operand" "r"))
9421 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9422 (match_operand:SI 9 "gpc_reg_operand" "r"))
9423 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9424 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9425 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9426 "{stsi|stswi} %2,%1,%O0"
9427 [(set_attr "type" "store_ux")])
9429 (define_insn "*stmsi7_power"
9430 [(match_parallel 0 "store_multiple_operation"
9431 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9432 (match_operand:SI 2 "gpc_reg_operand" "r"))
9433 (clobber (match_scratch:SI 3 "=q"))
9434 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9435 (match_operand:SI 4 "gpc_reg_operand" "r"))
9436 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9437 (match_operand:SI 5 "gpc_reg_operand" "r"))
9438 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9439 (match_operand:SI 6 "gpc_reg_operand" "r"))
9440 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9441 (match_operand:SI 7 "gpc_reg_operand" "r"))
9442 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9443 (match_operand:SI 8 "gpc_reg_operand" "r"))
9444 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9445 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9446 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9447 "{stsi|stswi} %2,%1,%O0"
9448 [(set_attr "type" "store_ux")])
9450 (define_insn "*stmsi6_power"
9451 [(match_parallel 0 "store_multiple_operation"
9452 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9453 (match_operand:SI 2 "gpc_reg_operand" "r"))
9454 (clobber (match_scratch:SI 3 "=q"))
9455 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9456 (match_operand:SI 4 "gpc_reg_operand" "r"))
9457 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9458 (match_operand:SI 5 "gpc_reg_operand" "r"))
9459 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9460 (match_operand:SI 6 "gpc_reg_operand" "r"))
9461 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9462 (match_operand:SI 7 "gpc_reg_operand" "r"))
9463 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9464 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9465 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9466 "{stsi|stswi} %2,%1,%O0"
9467 [(set_attr "type" "store_ux")])
9469 (define_insn "*stmsi5_power"
9470 [(match_parallel 0 "store_multiple_operation"
9471 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9472 (match_operand:SI 2 "gpc_reg_operand" "r"))
9473 (clobber (match_scratch:SI 3 "=q"))
9474 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9475 (match_operand:SI 4 "gpc_reg_operand" "r"))
9476 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9477 (match_operand:SI 5 "gpc_reg_operand" "r"))
9478 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9479 (match_operand:SI 6 "gpc_reg_operand" "r"))
9480 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9481 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9482 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9483 "{stsi|stswi} %2,%1,%O0"
9484 [(set_attr "type" "store_ux")])
9486 (define_insn "*stmsi4_power"
9487 [(match_parallel 0 "store_multiple_operation"
9488 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9489 (match_operand:SI 2 "gpc_reg_operand" "r"))
9490 (clobber (match_scratch:SI 3 "=q"))
9491 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9492 (match_operand:SI 4 "gpc_reg_operand" "r"))
9493 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9494 (match_operand:SI 5 "gpc_reg_operand" "r"))
9495 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9496 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9497 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9498 "{stsi|stswi} %2,%1,%O0"
9499 [(set_attr "type" "store_ux")])
9501 (define_insn "*stmsi3_power"
9502 [(match_parallel 0 "store_multiple_operation"
9503 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9504 (match_operand:SI 2 "gpc_reg_operand" "r"))
9505 (clobber (match_scratch:SI 3 "=q"))
9506 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9507 (match_operand:SI 4 "gpc_reg_operand" "r"))
9508 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9509 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9510 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9511 "{stsi|stswi} %2,%1,%O0"
9512 [(set_attr "type" "store_ux")])
9513 \f
9514 (define_expand "setmemsi"
9515 [(parallel [(set (match_operand:BLK 0 "" "")
9516 (match_operand 2 "const_int_operand" ""))
9517 (use (match_operand:SI 1 "" ""))
9518 (use (match_operand:SI 3 "" ""))])]
9519 ""
9520 "
9521 {
9522 /* If value to set is not zero, use the library routine. */
9523 if (operands[2] != const0_rtx)
9524 FAIL;
9526 if (expand_block_clear (operands))
9527 DONE;
9528 else
9529 FAIL;
9530 }")
9532 ;; String/block move insn.
9533 ;; Argument 0 is the destination
9534 ;; Argument 1 is the source
9535 ;; Argument 2 is the length
9536 ;; Argument 3 is the alignment
9538 (define_expand "movmemsi"
9539 [(parallel [(set (match_operand:BLK 0 "" "")
9540 (match_operand:BLK 1 "" ""))
9541 (use (match_operand:SI 2 "" ""))
9542 (use (match_operand:SI 3 "" ""))])]
9543 ""
9544 "
9545 {
9546 if (expand_block_move (operands))
9547 DONE;
9548 else
9549 FAIL;
9550 }")
9552 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9553 ;; register allocator doesn't have a clue about allocating 8 word registers.
9554 ;; rD/rS = r5 is preferred, efficient form.
9555 (define_expand "movmemsi_8reg"
9556 [(parallel [(set (match_operand 0 "" "")
9557 (match_operand 1 "" ""))
9558 (use (match_operand 2 "" ""))
9559 (use (match_operand 3 "" ""))
9560 (clobber (reg:SI 5))
9561 (clobber (reg:SI 6))
9562 (clobber (reg:SI 7))
9563 (clobber (reg:SI 8))
9564 (clobber (reg:SI 9))
9565 (clobber (reg:SI 10))
9566 (clobber (reg:SI 11))
9567 (clobber (reg:SI 12))
9568 (clobber (match_scratch:SI 4 ""))])]
9569 "TARGET_STRING"
9570 "")
9572 (define_insn ""
9573 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9574 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9575 (use (match_operand:SI 2 "immediate_operand" "i"))
9576 (use (match_operand:SI 3 "immediate_operand" "i"))
9577 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9578 (clobber (reg:SI 6))
9579 (clobber (reg:SI 7))
9580 (clobber (reg:SI 8))
9581 (clobber (reg:SI 9))
9582 (clobber (reg:SI 10))
9583 (clobber (reg:SI 11))
9584 (clobber (reg:SI 12))
9585 (clobber (match_scratch:SI 5 "=q"))]
9586 "TARGET_STRING && TARGET_POWER
9587 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9588 || INTVAL (operands[2]) == 0)
9589 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9590 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9591 && REGNO (operands[4]) == 5"
9592 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9593 [(set_attr "type" "store_ux")
9594 (set_attr "length" "8")])
9596 (define_insn ""
9597 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9598 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9599 (use (match_operand:SI 2 "immediate_operand" "i"))
9600 (use (match_operand:SI 3 "immediate_operand" "i"))
9601 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9602 (clobber (reg:SI 6))
9603 (clobber (reg:SI 7))
9604 (clobber (reg:SI 8))
9605 (clobber (reg:SI 9))
9606 (clobber (reg:SI 10))
9607 (clobber (reg:SI 11))
9608 (clobber (reg:SI 12))
9609 (clobber (match_scratch:SI 5 "=X"))]
9610 "TARGET_STRING && ! TARGET_POWER
9611 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9612 || INTVAL (operands[2]) == 0)
9613 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9614 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9615 && REGNO (operands[4]) == 5"
9616 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9617 [(set_attr "type" "store_ux")
9618 (set_attr "length" "8")])
9620 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9621 ;; register allocator doesn't have a clue about allocating 6 word registers.
9622 ;; rD/rS = r5 is preferred, efficient form.
9623 (define_expand "movmemsi_6reg"
9624 [(parallel [(set (match_operand 0 "" "")
9625 (match_operand 1 "" ""))
9626 (use (match_operand 2 "" ""))
9627 (use (match_operand 3 "" ""))
9628 (clobber (reg:SI 5))
9629 (clobber (reg:SI 6))
9630 (clobber (reg:SI 7))
9631 (clobber (reg:SI 8))
9632 (clobber (reg:SI 9))
9633 (clobber (reg:SI 10))
9634 (clobber (match_scratch:SI 4 ""))])]
9635 "TARGET_STRING"
9636 "")
9638 (define_insn ""
9639 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9640 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9641 (use (match_operand:SI 2 "immediate_operand" "i"))
9642 (use (match_operand:SI 3 "immediate_operand" "i"))
9643 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9644 (clobber (reg:SI 6))
9645 (clobber (reg:SI 7))
9646 (clobber (reg:SI 8))
9647 (clobber (reg:SI 9))
9648 (clobber (reg:SI 10))
9649 (clobber (match_scratch:SI 5 "=q"))]
9650 "TARGET_STRING && TARGET_POWER
9651 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9652 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9653 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9654 && REGNO (operands[4]) == 5"
9655 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9656 [(set_attr "type" "store_ux")
9657 (set_attr "length" "8")])
9659 (define_insn ""
9660 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9661 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9662 (use (match_operand:SI 2 "immediate_operand" "i"))
9663 (use (match_operand:SI 3 "immediate_operand" "i"))
9664 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9665 (clobber (reg:SI 6))
9666 (clobber (reg:SI 7))
9667 (clobber (reg:SI 8))
9668 (clobber (reg:SI 9))
9669 (clobber (reg:SI 10))
9670 (clobber (match_scratch:SI 5 "=X"))]
9671 "TARGET_STRING && ! TARGET_POWER
9672 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9673 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9674 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9675 && REGNO (operands[4]) == 5"
9676 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9677 [(set_attr "type" "store_ux")
9678 (set_attr "length" "8")])
9680 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9681 ;; problems with TImode.
9682 ;; rD/rS = r5 is preferred, efficient form.
9683 (define_expand "movmemsi_4reg"
9684 [(parallel [(set (match_operand 0 "" "")
9685 (match_operand 1 "" ""))
9686 (use (match_operand 2 "" ""))
9687 (use (match_operand 3 "" ""))
9688 (clobber (reg:SI 5))
9689 (clobber (reg:SI 6))
9690 (clobber (reg:SI 7))
9691 (clobber (reg:SI 8))
9692 (clobber (match_scratch:SI 4 ""))])]
9693 "TARGET_STRING"
9694 "")
9696 (define_insn ""
9697 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9698 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9699 (use (match_operand:SI 2 "immediate_operand" "i"))
9700 (use (match_operand:SI 3 "immediate_operand" "i"))
9701 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9702 (clobber (reg:SI 6))
9703 (clobber (reg:SI 7))
9704 (clobber (reg:SI 8))
9705 (clobber (match_scratch:SI 5 "=q"))]
9706 "TARGET_STRING && TARGET_POWER
9707 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9708 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9709 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9710 && REGNO (operands[4]) == 5"
9711 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9712 [(set_attr "type" "store_ux")
9713 (set_attr "length" "8")])
9715 (define_insn ""
9716 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9717 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9718 (use (match_operand:SI 2 "immediate_operand" "i"))
9719 (use (match_operand:SI 3 "immediate_operand" "i"))
9720 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9721 (clobber (reg:SI 6))
9722 (clobber (reg:SI 7))
9723 (clobber (reg:SI 8))
9724 (clobber (match_scratch:SI 5 "=X"))]
9725 "TARGET_STRING && ! TARGET_POWER
9726 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9727 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9728 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9729 && REGNO (operands[4]) == 5"
9730 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9731 [(set_attr "type" "store_ux")
9732 (set_attr "length" "8")])
9734 ;; Move up to 8 bytes at a time.
9735 (define_expand "movmemsi_2reg"
9736 [(parallel [(set (match_operand 0 "" "")
9737 (match_operand 1 "" ""))
9738 (use (match_operand 2 "" ""))
9739 (use (match_operand 3 "" ""))
9740 (clobber (match_scratch:DI 4 ""))
9741 (clobber (match_scratch:SI 5 ""))])]
9742 "TARGET_STRING && ! TARGET_POWERPC64"
9743 "")
9745 (define_insn ""
9746 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9747 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9748 (use (match_operand:SI 2 "immediate_operand" "i"))
9749 (use (match_operand:SI 3 "immediate_operand" "i"))
9750 (clobber (match_scratch:DI 4 "=&r"))
9751 (clobber (match_scratch:SI 5 "=q"))]
9752 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9753 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9754 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9755 [(set_attr "type" "store_ux")
9756 (set_attr "length" "8")])
9758 (define_insn ""
9759 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9760 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9761 (use (match_operand:SI 2 "immediate_operand" "i"))
9762 (use (match_operand:SI 3 "immediate_operand" "i"))
9763 (clobber (match_scratch:DI 4 "=&r"))
9764 (clobber (match_scratch:SI 5 "=X"))]
9765 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9766 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9767 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9768 [(set_attr "type" "store_ux")
9769 (set_attr "length" "8")])
9771 ;; Move up to 4 bytes at a time.
9772 (define_expand "movmemsi_1reg"
9773 [(parallel [(set (match_operand 0 "" "")
9774 (match_operand 1 "" ""))
9775 (use (match_operand 2 "" ""))
9776 (use (match_operand 3 "" ""))
9777 (clobber (match_scratch:SI 4 ""))
9778 (clobber (match_scratch:SI 5 ""))])]
9779 "TARGET_STRING"
9780 "")
9782 (define_insn ""
9783 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9784 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9785 (use (match_operand:SI 2 "immediate_operand" "i"))
9786 (use (match_operand:SI 3 "immediate_operand" "i"))
9787 (clobber (match_scratch:SI 4 "=&r"))
9788 (clobber (match_scratch:SI 5 "=q"))]
9789 "TARGET_STRING && TARGET_POWER
9790 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9791 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9792 [(set_attr "type" "store_ux")
9793 (set_attr "length" "8")])
9795 (define_insn ""
9796 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9797 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9798 (use (match_operand:SI 2 "immediate_operand" "i"))
9799 (use (match_operand:SI 3 "immediate_operand" "i"))
9800 (clobber (match_scratch:SI 4 "=&r"))
9801 (clobber (match_scratch:SI 5 "=X"))]
9802 "TARGET_STRING && ! TARGET_POWER
9803 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9804 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9805 [(set_attr "type" "store_ux")
9806 (set_attr "length" "8")])
9807 \f
9808 ;; Define insns that do load or store with update. Some of these we can
9809 ;; get by using pre-decrement or pre-increment, but the hardware can also
9810 ;; do cases where the increment is not the size of the object.
9811 ;;
9812 ;; In all these cases, we use operands 0 and 1 for the register being
9813 ;; incremented because those are the operands that local-alloc will
9814 ;; tie and these are the pair most likely to be tieable (and the ones
9815 ;; that will benefit the most).
9817 (define_insn "*movdi_update1"
9818 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9819 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9820 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9821 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9822 (plus:DI (match_dup 1) (match_dup 2)))]
9823 "TARGET_POWERPC64 && TARGET_UPDATE"
9824 "@
9825 ldux %3,%0,%2
9826 ldu %3,%2(%0)"
9827 [(set_attr "type" "load_ux,load_u")])
9829 (define_insn "movdi_<mode>_update"
9830 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9831 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9832 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9833 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9834 (plus:P (match_dup 1) (match_dup 2)))]
9835 "TARGET_POWERPC64 && TARGET_UPDATE"
9836 "@
9837 stdux %3,%0,%2
9838 stdu %3,%2(%0)"
9839 [(set_attr "type" "store_ux,store_u")])
9841 (define_insn "*movsi_update1"
9842 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9843 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9844 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9845 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9846 (plus:SI (match_dup 1) (match_dup 2)))]
9847 "TARGET_UPDATE"
9848 "@
9849 {lux|lwzux} %3,%0,%2
9850 {lu|lwzu} %3,%2(%0)"
9851 [(set_attr "type" "load_ux,load_u")])
9853 (define_insn "*movsi_update2"
9854 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9855 (sign_extend:DI
9856 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9857 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9858 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9859 (plus:DI (match_dup 1) (match_dup 2)))]
9860 "TARGET_POWERPC64"
9861 "lwaux %3,%0,%2"
9862 [(set_attr "type" "load_ext_ux")])
9864 (define_insn "movsi_update"
9865 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9866 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9867 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9868 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9869 (plus:SI (match_dup 1) (match_dup 2)))]
9870 "TARGET_UPDATE"
9871 "@
9872 {stux|stwux} %3,%0,%2
9873 {stu|stwu} %3,%2(%0)"
9874 [(set_attr "type" "store_ux,store_u")])
9876 (define_insn "*movhi_update1"
9877 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9878 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9879 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9880 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9881 (plus:SI (match_dup 1) (match_dup 2)))]
9882 "TARGET_UPDATE"
9883 "@
9884 lhzux %3,%0,%2
9885 lhzu %3,%2(%0)"
9886 [(set_attr "type" "load_ux,load_u")])
9888 (define_insn "*movhi_update2"
9889 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9890 (zero_extend:SI
9891 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9892 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9893 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9894 (plus:SI (match_dup 1) (match_dup 2)))]
9895 "TARGET_UPDATE"
9896 "@
9897 lhzux %3,%0,%2
9898 lhzu %3,%2(%0)"
9899 [(set_attr "type" "load_ux,load_u")])
9901 (define_insn "*movhi_update3"
9902 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9903 (sign_extend:SI
9904 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9905 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9906 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9907 (plus:SI (match_dup 1) (match_dup 2)))]
9908 "TARGET_UPDATE"
9909 "@
9910 lhaux %3,%0,%2
9911 lhau %3,%2(%0)"
9912 [(set_attr "type" "load_ext_ux,load_ext_u")])
9914 (define_insn "*movhi_update4"
9915 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9916 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9917 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9918 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9919 (plus:SI (match_dup 1) (match_dup 2)))]
9920 "TARGET_UPDATE"
9921 "@
9922 sthux %3,%0,%2
9923 sthu %3,%2(%0)"
9924 [(set_attr "type" "store_ux,store_u")])
9926 (define_insn "*movqi_update1"
9927 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9928 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9929 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9930 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9931 (plus:SI (match_dup 1) (match_dup 2)))]
9932 "TARGET_UPDATE"
9933 "@
9934 lbzux %3,%0,%2
9935 lbzu %3,%2(%0)"
9936 [(set_attr "type" "load_ux,load_u")])
9938 (define_insn "*movqi_update2"
9939 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9940 (zero_extend:SI
9941 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9942 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9943 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9944 (plus:SI (match_dup 1) (match_dup 2)))]
9945 "TARGET_UPDATE"
9946 "@
9947 lbzux %3,%0,%2
9948 lbzu %3,%2(%0)"
9949 [(set_attr "type" "load_ux,load_u")])
9951 (define_insn "*movqi_update3"
9952 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9953 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9954 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9955 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9956 (plus:SI (match_dup 1) (match_dup 2)))]
9957 "TARGET_UPDATE"
9958 "@
9959 stbux %3,%0,%2
9960 stbu %3,%2(%0)"
9961 [(set_attr "type" "store_ux,store_u")])
9963 (define_insn "*movsf_update1"
9964 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9965 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9966 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9967 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9968 (plus:SI (match_dup 1) (match_dup 2)))]
9969 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9970 "@
9971 lfsux %3,%0,%2
9972 lfsu %3,%2(%0)"
9973 [(set_attr "type" "fpload_ux,fpload_u")])
9975 (define_insn "*movsf_update2"
9976 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9977 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9978 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9979 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9980 (plus:SI (match_dup 1) (match_dup 2)))]
9981 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9982 "@
9983 stfsux %3,%0,%2
9984 stfsu %3,%2(%0)"
9985 [(set_attr "type" "fpstore_ux,fpstore_u")])
9987 (define_insn "*movsf_update3"
9988 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9989 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9990 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9991 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9992 (plus:SI (match_dup 1) (match_dup 2)))]
9993 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9994 "@
9995 {lux|lwzux} %3,%0,%2
9996 {lu|lwzu} %3,%2(%0)"
9997 [(set_attr "type" "load_ux,load_u")])
9999 (define_insn "*movsf_update4"
10000 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10001 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10002 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10003 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10004 (plus:SI (match_dup 1) (match_dup 2)))]
10005 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10006 "@
10007 {stux|stwux} %3,%0,%2
10008 {stu|stwu} %3,%2(%0)"
10009 [(set_attr "type" "store_ux,store_u")])
10011 (define_insn "*movdf_update1"
10012 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10013 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10014 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10015 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10016 (plus:SI (match_dup 1) (match_dup 2)))]
10017 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10018 "@
10019 lfdux %3,%0,%2
10020 lfdu %3,%2(%0)"
10021 [(set_attr "type" "fpload_ux,fpload_u")])
10023 (define_insn "*movdf_update2"
10024 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10025 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10026 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10027 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10028 (plus:SI (match_dup 1) (match_dup 2)))]
10029 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10030 "@
10031 stfdux %3,%0,%2
10032 stfdu %3,%2(%0)"
10033 [(set_attr "type" "fpstore_ux,fpstore_u")])
10035 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10037 (define_insn "*lfq_power2"
10038 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10039 (match_operand:V2DF 1 "memory_operand" ""))]
10040 "TARGET_POWER2
10041 && TARGET_HARD_FLOAT && TARGET_FPRS"
10042 "lfq%U1%X1 %0,%1")
10044 (define_peephole2
10045 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10046 (match_operand:DF 1 "memory_operand" ""))
10047 (set (match_operand:DF 2 "gpc_reg_operand" "")
10048 (match_operand:DF 3 "memory_operand" ""))]
10049 "TARGET_POWER2
10050 && TARGET_HARD_FLOAT && TARGET_FPRS
10051 && registers_ok_for_quad_peep (operands[0], operands[2])
10052 && mems_ok_for_quad_peep (operands[1], operands[3])"
10053 [(set (match_dup 0)
10054 (match_dup 1))]
10055 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10056 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10058 (define_insn "*stfq_power2"
10059 [(set (match_operand:V2DF 0 "memory_operand" "")
10060 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10061 "TARGET_POWER2
10062 && TARGET_HARD_FLOAT && TARGET_FPRS"
10063 "stfq%U0%X0 %1,%0")
10066 (define_peephole2
10067 [(set (match_operand:DF 0 "memory_operand" "")
10068 (match_operand:DF 1 "gpc_reg_operand" ""))
10069 (set (match_operand:DF 2 "memory_operand" "")
10070 (match_operand:DF 3 "gpc_reg_operand" ""))]
10071 "TARGET_POWER2
10072 && TARGET_HARD_FLOAT && TARGET_FPRS
10073 && registers_ok_for_quad_peep (operands[1], operands[3])
10074 && mems_ok_for_quad_peep (operands[0], operands[2])"
10075 [(set (match_dup 0)
10076 (match_dup 1))]
10077 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10078 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10080 ;; After inserting conditional returns we can sometimes have
10081 ;; unnecessary register moves. Unfortunately we cannot have a
10082 ;; modeless peephole here, because some single SImode sets have early
10083 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10084 ;; sequences, using get_attr_length here will smash the operands
10085 ;; array. Neither is there an early_cobbler_p predicate.
10086 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10087 (define_peephole2
10088 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10089 (match_operand:DF 1 "any_operand" ""))
10090 (set (match_operand:DF 2 "gpc_reg_operand" "")
10091 (match_dup 0))]
10092 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10093 && peep2_reg_dead_p (2, operands[0])"
10094 [(set (match_dup 2) (match_dup 1))])
10096 (define_peephole2
10097 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10098 (match_operand:SF 1 "any_operand" ""))
10099 (set (match_operand:SF 2 "gpc_reg_operand" "")
10100 (match_dup 0))]
10101 "peep2_reg_dead_p (2, operands[0])"
10102 [(set (match_dup 2) (match_dup 1))])
10104 \f
10105 ;; TLS support.
10107 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
10108 (define_insn "tls_gd_32"
10109 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10110 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10111 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10112 UNSPEC_TLSGD))]
10113 "HAVE_AS_TLS && !TARGET_64BIT"
10114 "addi %0,%1,%2@got@tlsgd")
10116 (define_insn "tls_gd_64"
10117 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10118 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10119 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10120 UNSPEC_TLSGD))]
10121 "HAVE_AS_TLS && TARGET_64BIT"
10122 "addi %0,%1,%2@got@tlsgd")
10124 (define_insn "tls_ld_32"
10125 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10126 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
10127 UNSPEC_TLSLD))]
10128 "HAVE_AS_TLS && !TARGET_64BIT"
10129 "addi %0,%1,%&@got@tlsld")
10131 (define_insn "tls_ld_64"
10132 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10133 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
10134 UNSPEC_TLSLD))]
10135 "HAVE_AS_TLS && TARGET_64BIT"
10136 "addi %0,%1,%&@got@tlsld")
10138 (define_insn "tls_dtprel_32"
10139 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10140 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10141 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10142 UNSPEC_TLSDTPREL))]
10143 "HAVE_AS_TLS && !TARGET_64BIT"
10144 "addi %0,%1,%2@dtprel")
10146 (define_insn "tls_dtprel_64"
10147 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10148 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10149 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10150 UNSPEC_TLSDTPREL))]
10151 "HAVE_AS_TLS && TARGET_64BIT"
10152 "addi %0,%1,%2@dtprel")
10154 (define_insn "tls_dtprel_ha_32"
10155 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10156 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10157 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10158 UNSPEC_TLSDTPRELHA))]
10159 "HAVE_AS_TLS && !TARGET_64BIT"
10160 "addis %0,%1,%2@dtprel@ha")
10162 (define_insn "tls_dtprel_ha_64"
10163 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10164 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10165 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10166 UNSPEC_TLSDTPRELHA))]
10167 "HAVE_AS_TLS && TARGET_64BIT"
10168 "addis %0,%1,%2@dtprel@ha")
10170 (define_insn "tls_dtprel_lo_32"
10171 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10172 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10173 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10174 UNSPEC_TLSDTPRELLO))]
10175 "HAVE_AS_TLS && !TARGET_64BIT"
10176 "addi %0,%1,%2@dtprel@l")
10178 (define_insn "tls_dtprel_lo_64"
10179 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10180 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10181 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10182 UNSPEC_TLSDTPRELLO))]
10183 "HAVE_AS_TLS && TARGET_64BIT"
10184 "addi %0,%1,%2@dtprel@l")
10186 (define_insn "tls_got_dtprel_32"
10187 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10188 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10189 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10190 UNSPEC_TLSGOTDTPREL))]
10191 "HAVE_AS_TLS && !TARGET_64BIT"
10192 "lwz %0,%2@got@dtprel(%1)")
10194 (define_insn "tls_got_dtprel_64"
10195 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10196 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10197 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10198 UNSPEC_TLSGOTDTPREL))]
10199 "HAVE_AS_TLS && TARGET_64BIT"
10200 "ld %0,%2@got@dtprel(%1)")
10202 (define_insn "tls_tprel_32"
10203 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10204 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10205 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10206 UNSPEC_TLSTPREL))]
10207 "HAVE_AS_TLS && !TARGET_64BIT"
10208 "addi %0,%1,%2@tprel")
10210 (define_insn "tls_tprel_64"
10211 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10212 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10213 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10214 UNSPEC_TLSTPREL))]
10215 "HAVE_AS_TLS && TARGET_64BIT"
10216 "addi %0,%1,%2@tprel")
10218 (define_insn "tls_tprel_ha_32"
10219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10220 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10221 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10222 UNSPEC_TLSTPRELHA))]
10223 "HAVE_AS_TLS && !TARGET_64BIT"
10224 "addis %0,%1,%2@tprel@ha")
10226 (define_insn "tls_tprel_ha_64"
10227 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10228 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10229 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10230 UNSPEC_TLSTPRELHA))]
10231 "HAVE_AS_TLS && TARGET_64BIT"
10232 "addis %0,%1,%2@tprel@ha")
10234 (define_insn "tls_tprel_lo_32"
10235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10236 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10237 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10238 UNSPEC_TLSTPRELLO))]
10239 "HAVE_AS_TLS && !TARGET_64BIT"
10240 "addi %0,%1,%2@tprel@l")
10242 (define_insn "tls_tprel_lo_64"
10243 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10244 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10245 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10246 UNSPEC_TLSTPRELLO))]
10247 "HAVE_AS_TLS && TARGET_64BIT"
10248 "addi %0,%1,%2@tprel@l")
10250 ;; "b" output constraint here and on tls_tls input to support linker tls
10251 ;; optimization. The linker may edit the instructions emitted by a
10252 ;; tls_got_tprel/tls_tls pair to addis,addi.
10253 (define_insn "tls_got_tprel_32"
10254 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10255 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10256 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10257 UNSPEC_TLSGOTTPREL))]
10258 "HAVE_AS_TLS && !TARGET_64BIT"
10259 "lwz %0,%2@got@tprel(%1)")
10261 (define_insn "tls_got_tprel_64"
10262 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10263 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10264 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10265 UNSPEC_TLSGOTTPREL))]
10266 "HAVE_AS_TLS && TARGET_64BIT"
10267 "ld %0,%2@got@tprel(%1)")
10269 (define_insn "tls_tls_32"
10270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10271 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10272 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10273 UNSPEC_TLSTLS))]
10274 "HAVE_AS_TLS && !TARGET_64BIT"
10275 "add %0,%1,%2@tls")
10277 (define_insn "tls_tls_64"
10278 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10279 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10280 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10281 UNSPEC_TLSTLS))]
10282 "HAVE_AS_TLS && TARGET_64BIT"
10283 "add %0,%1,%2@tls")
10284 \f
10285 ;; Next come insns related to the calling sequence.
10286 ;;
10287 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10288 ;; We move the back-chain and decrement the stack pointer.
10290 (define_expand "allocate_stack"
10291 [(set (match_operand 0 "gpc_reg_operand" "")
10292 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10293 (set (reg 1)
10294 (minus (reg 1) (match_dup 1)))]
10295 ""
10296 "
10297 { rtx chain = gen_reg_rtx (Pmode);
10298 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10299 rtx neg_op0;
10301 emit_move_insn (chain, stack_bot);
10303 /* Check stack bounds if necessary. */
10304 if (current_function_limit_stack)
10305 {
10306 rtx available;
10307 available = expand_binop (Pmode, sub_optab,
10308 stack_pointer_rtx, stack_limit_rtx,
10309 NULL_RTX, 1, OPTAB_WIDEN);
10310 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10311 }
10313 if (GET_CODE (operands[1]) != CONST_INT
10314 || INTVAL (operands[1]) < -32767
10315 || INTVAL (operands[1]) > 32768)
10316 {
10317 neg_op0 = gen_reg_rtx (Pmode);
10318 if (TARGET_32BIT)
10319 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10320 else
10321 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10322 }
10323 else
10324 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10326 if (TARGET_UPDATE)
10327 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10328 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10330 else
10331 {
10332 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10333 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10334 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10335 }
10337 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10338 DONE;
10339 }")
10341 ;; These patterns say how to save and restore the stack pointer. We need not
10342 ;; save the stack pointer at function level since we are careful to
10343 ;; preserve the backchain. At block level, we have to restore the backchain
10344 ;; when we restore the stack pointer.
10345 ;;
10346 ;; For nonlocal gotos, we must save both the stack pointer and its
10347 ;; backchain and restore both. Note that in the nonlocal case, the
10348 ;; save area is a memory location.
10350 (define_expand "save_stack_function"
10351 [(match_operand 0 "any_operand" "")
10352 (match_operand 1 "any_operand" "")]
10353 ""
10354 "DONE;")
10356 (define_expand "restore_stack_function"
10357 [(match_operand 0 "any_operand" "")
10358 (match_operand 1 "any_operand" "")]
10359 ""
10360 "DONE;")
10362 ;; Adjust stack pointer (op0) to a new value (op1).
10363 ;; First copy old stack backchain to new location, and ensure that the
10364 ;; scheduler won't reorder the sp assignment before the backchain write.
10365 (define_expand "restore_stack_block"
10366 [(set (match_dup 2) (match_dup 3))
10367 (set (match_dup 4) (match_dup 2))
10368 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10369 (set (match_operand 0 "register_operand" "")
10370 (match_operand 1 "register_operand" ""))]
10371 ""
10372 "
10373 {
10374 operands[2] = gen_reg_rtx (Pmode);
10375 operands[3] = gen_frame_mem (Pmode, operands[0]);
10376 operands[4] = gen_frame_mem (Pmode, operands[1]);
10377 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10378 }")
10380 (define_expand "save_stack_nonlocal"
10381 [(set (match_dup 3) (match_dup 4))
10382 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10383 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10384 ""
10385 "
10386 {
10387 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10389 /* Copy the backchain to the first word, sp to the second. */
10390 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10391 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10392 operands[3] = gen_reg_rtx (Pmode);
10393 operands[4] = gen_frame_mem (Pmode, operands[1]);
10394 }")
10396 (define_expand "restore_stack_nonlocal"
10397 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10398 (set (match_dup 3) (match_dup 4))
10399 (set (match_dup 5) (match_dup 2))
10400 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10401 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10402 ""
10403 "
10404 {
10405 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10407 /* Restore the backchain from the first word, sp from the second. */
10408 operands[2] = gen_reg_rtx (Pmode);
10409 operands[3] = gen_reg_rtx (Pmode);
10410 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10411 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10412 operands[5] = gen_frame_mem (Pmode, operands[3]);
10413 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10414 }")
10415 \f
10416 ;; TOC register handling.
10418 ;; Code to initialize the TOC register...
10420 (define_insn "load_toc_aix_si"
10421 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10422 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10423 (use (reg:SI 2))])]
10424 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10425 "*
10426 {
10427 char buf[30];
10428 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10429 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10430 operands[2] = gen_rtx_REG (Pmode, 2);
10431 return \"{l|lwz} %0,%1(%2)\";
10432 }"
10433 [(set_attr "type" "load")])
10435 (define_insn "load_toc_aix_di"
10436 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10437 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10438 (use (reg:DI 2))])]
10439 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10440 "*
10441 {
10442 char buf[30];
10443 #ifdef TARGET_RELOCATABLE
10444 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10445 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10446 #else
10447 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10448 #endif
10449 if (TARGET_ELF)
10450 strcat (buf, \"@toc\");
10451 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10452 operands[2] = gen_rtx_REG (Pmode, 2);
10453 return \"ld %0,%1(%2)\";
10454 }"
10455 [(set_attr "type" "load")])
10457 (define_insn "load_toc_v4_pic_si"
10458 [(set (match_operand:SI 0 "register_operand" "=l")
10459 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10460 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10461 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10462 [(set_attr "type" "branch")
10463 (set_attr "length" "4")])
10465 (define_insn "load_toc_v4_PIC_1"
10466 [(set (match_operand:SI 0 "register_operand" "=l")
10467 (match_operand:SI 1 "immediate_operand" "s"))
10468 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10469 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10470 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10471 "bcl 20,31,%1\\n%1:"
10472 [(set_attr "type" "branch")
10473 (set_attr "length" "4")])
10475 (define_insn "load_toc_v4_PIC_1b"
10476 [(set (match_operand:SI 0 "register_operand" "=l")
10477 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10478 UNSPEC_TOCPTR))]
10479 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10480 "bcl 20,31,$+8\\n\\t.long %1-$"
10481 [(set_attr "type" "branch")
10482 (set_attr "length" "8")])
10484 (define_insn "load_toc_v4_PIC_2"
10485 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10486 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10487 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10488 (match_operand:SI 3 "immediate_operand" "s")))))]
10489 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10490 "{l|lwz} %0,%2-%3(%1)"
10491 [(set_attr "type" "load")])
10493 (define_insn "load_toc_v4_PIC_3b"
10494 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10495 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10496 (high:SI
10497 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10498 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10499 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10500 "{cau|addis} %0,%1,%2-%3@ha")
10502 (define_insn "load_toc_v4_PIC_3c"
10503 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10504 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10505 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10506 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10507 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10508 "{cal|addi} %0,%1,%2-%3@l")
10510 ;; If the TOC is shared over a translation unit, as happens with all
10511 ;; the kinds of PIC that we support, we need to restore the TOC
10512 ;; pointer only when jumping over units of translation.
10513 ;; On Darwin, we need to reload the picbase.
10515 (define_expand "builtin_setjmp_receiver"
10516 [(use (label_ref (match_operand 0 "" "")))]
10517 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10518 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10519 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10520 "
10521 {
10522 #if TARGET_MACHO
10523 if (DEFAULT_ABI == ABI_DARWIN)
10524 {
10525 const char *picbase = machopic_function_base_name ();
10526 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10527 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10528 rtx tmplabrtx;
10529 char tmplab[20];
10531 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10532 CODE_LABEL_NUMBER (operands[0]));
10533 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10535 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10536 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10537 }
10538 else
10539 #endif
10540 rs6000_emit_load_toc_table (FALSE);
10541 DONE;
10542 }")
10544 ;; Elf specific ways of loading addresses for non-PIC code.
10545 ;; The output of this could be r0, but we make a very strong
10546 ;; preference for a base register because it will usually
10547 ;; be needed there.
10548 (define_insn "elf_high"
10549 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10550 (high:SI (match_operand 1 "" "")))]
10551 "TARGET_ELF && ! TARGET_64BIT"
10552 "{liu|lis} %0,%1@ha")
10554 (define_insn "elf_low"
10555 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10556 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10557 (match_operand 2 "" "")))]
10558 "TARGET_ELF && ! TARGET_64BIT"
10559 "@
10560 {cal|la} %0,%2@l(%1)
10561 {ai|addic} %0,%1,%K2")
10562 \f
10563 ;; A function pointer under AIX is a pointer to a data area whose first word
10564 ;; contains the actual address of the function, whose second word contains a
10565 ;; pointer to its TOC, and whose third word contains a value to place in the
10566 ;; static chain register (r11). Note that if we load the static chain, our
10567 ;; "trampoline" need not have any executable code.
10569 (define_expand "call_indirect_aix32"
10570 [(set (match_dup 2)
10571 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10572 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10573 (reg:SI 2))
10574 (set (reg:SI 2)
10575 (mem:SI (plus:SI (match_dup 0)
10576 (const_int 4))))
10577 (set (reg:SI 11)
10578 (mem:SI (plus:SI (match_dup 0)
10579 (const_int 8))))
10580 (parallel [(call (mem:SI (match_dup 2))
10581 (match_operand 1 "" ""))
10582 (use (reg:SI 2))
10583 (use (reg:SI 11))
10584 (set (reg:SI 2)
10585 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10586 (clobber (scratch:SI))])]
10587 "TARGET_32BIT"
10588 "
10589 { operands[2] = gen_reg_rtx (SImode); }")
10591 (define_expand "call_indirect_aix64"
10592 [(set (match_dup 2)
10593 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10594 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10595 (reg:DI 2))
10596 (set (reg:DI 2)
10597 (mem:DI (plus:DI (match_dup 0)
10598 (const_int 8))))
10599 (set (reg:DI 11)
10600 (mem:DI (plus:DI (match_dup 0)
10601 (const_int 16))))
10602 (parallel [(call (mem:SI (match_dup 2))
10603 (match_operand 1 "" ""))
10604 (use (reg:DI 2))
10605 (use (reg:DI 11))
10606 (set (reg:DI 2)
10607 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10608 (clobber (scratch:SI))])]
10609 "TARGET_64BIT"
10610 "
10611 { operands[2] = gen_reg_rtx (DImode); }")
10613 (define_expand "call_value_indirect_aix32"
10614 [(set (match_dup 3)
10615 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10616 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10617 (reg:SI 2))
10618 (set (reg:SI 2)
10619 (mem:SI (plus:SI (match_dup 1)
10620 (const_int 4))))
10621 (set (reg:SI 11)
10622 (mem:SI (plus:SI (match_dup 1)
10623 (const_int 8))))
10624 (parallel [(set (match_operand 0 "" "")
10625 (call (mem:SI (match_dup 3))
10626 (match_operand 2 "" "")))
10627 (use (reg:SI 2))
10628 (use (reg:SI 11))
10629 (set (reg:SI 2)
10630 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10631 (clobber (scratch:SI))])]
10632 "TARGET_32BIT"
10633 "
10634 { operands[3] = gen_reg_rtx (SImode); }")
10636 (define_expand "call_value_indirect_aix64"
10637 [(set (match_dup 3)
10638 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10639 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10640 (reg:DI 2))
10641 (set (reg:DI 2)
10642 (mem:DI (plus:DI (match_dup 1)
10643 (const_int 8))))
10644 (set (reg:DI 11)
10645 (mem:DI (plus:DI (match_dup 1)
10646 (const_int 16))))
10647 (parallel [(set (match_operand 0 "" "")
10648 (call (mem:SI (match_dup 3))
10649 (match_operand 2 "" "")))
10650 (use (reg:DI 2))
10651 (use (reg:DI 11))
10652 (set (reg:DI 2)
10653 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10654 (clobber (scratch:SI))])]
10655 "TARGET_64BIT"
10656 "
10657 { operands[3] = gen_reg_rtx (DImode); }")
10659 ;; Now the definitions for the call and call_value insns
10660 (define_expand "call"
10661 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10662 (match_operand 1 "" ""))
10663 (use (match_operand 2 "" ""))
10664 (clobber (scratch:SI))])]
10665 ""
10666 "
10667 {
10668 #if TARGET_MACHO
10669 if (MACHOPIC_INDIRECT)
10670 operands[0] = machopic_indirect_call_target (operands[0]);
10671 #endif
10673 gcc_assert (GET_CODE (operands[0]) == MEM);
10674 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10676 operands[0] = XEXP (operands[0], 0);
10678 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10679 && flag_pic
10680 && GET_CODE (operands[0]) == SYMBOL_REF
10681 && !SYMBOL_REF_LOCAL_P (operands[0]))
10682 {
10683 rtx call;
10684 rtvec tmp;
10686 tmp = gen_rtvec (3,
10687 gen_rtx_CALL (VOIDmode,
10688 gen_rtx_MEM (SImode, operands[0]),
10689 operands[1]),
10690 gen_rtx_USE (VOIDmode, operands[2]),
10691 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10692 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10693 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10694 DONE;
10695 }
10697 if (GET_CODE (operands[0]) != SYMBOL_REF
10698 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10699 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10700 {
10701 if (INTVAL (operands[2]) & CALL_LONG)
10702 operands[0] = rs6000_longcall_ref (operands[0]);
10704 switch (DEFAULT_ABI)
10705 {
10706 case ABI_V4:
10707 case ABI_DARWIN:
10708 operands[0] = force_reg (Pmode, operands[0]);
10709 break;
10711 case ABI_AIX:
10712 /* AIX function pointers are really pointers to a three word
10713 area. */
10714 emit_call_insn (TARGET_32BIT
10715 ? gen_call_indirect_aix32 (force_reg (SImode,
10716 operands[0]),
10717 operands[1])
10718 : gen_call_indirect_aix64 (force_reg (DImode,
10719 operands[0]),
10720 operands[1]));
10721 DONE;
10723 default:
10724 gcc_unreachable ();
10725 }
10726 }
10727 }")
10729 (define_expand "call_value"
10730 [(parallel [(set (match_operand 0 "" "")
10731 (call (mem:SI (match_operand 1 "address_operand" ""))
10732 (match_operand 2 "" "")))
10733 (use (match_operand 3 "" ""))
10734 (clobber (scratch:SI))])]
10735 ""
10736 "
10737 {
10738 #if TARGET_MACHO
10739 if (MACHOPIC_INDIRECT)
10740 operands[1] = machopic_indirect_call_target (operands[1]);
10741 #endif
10743 gcc_assert (GET_CODE (operands[1]) == MEM);
10744 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10746 operands[1] = XEXP (operands[1], 0);
10748 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10749 && flag_pic
10750 && GET_CODE (operands[1]) == SYMBOL_REF
10751 && !SYMBOL_REF_LOCAL_P (operands[1]))
10752 {
10753 rtx call;
10754 rtvec tmp;
10756 tmp = gen_rtvec (3,
10757 gen_rtx_SET (VOIDmode,
10758 operands[0],
10759 gen_rtx_CALL (VOIDmode,
10760 gen_rtx_MEM (SImode,
10761 operands[1]),
10762 operands[2])),
10763 gen_rtx_USE (VOIDmode, operands[3]),
10764 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10765 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10766 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10767 DONE;
10768 }
10770 if (GET_CODE (operands[1]) != SYMBOL_REF
10771 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10772 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10773 {
10774 if (INTVAL (operands[3]) & CALL_LONG)
10775 operands[1] = rs6000_longcall_ref (operands[1]);
10777 switch (DEFAULT_ABI)
10778 {
10779 case ABI_V4:
10780 case ABI_DARWIN:
10781 operands[1] = force_reg (Pmode, operands[1]);
10782 break;
10784 case ABI_AIX:
10785 /* AIX function pointers are really pointers to a three word
10786 area. */
10787 emit_call_insn (TARGET_32BIT
10788 ? gen_call_value_indirect_aix32 (operands[0],
10789 force_reg (SImode,
10790 operands[1]),
10791 operands[2])
10792 : gen_call_value_indirect_aix64 (operands[0],
10793 force_reg (DImode,
10794 operands[1]),
10795 operands[2]));
10796 DONE;
10798 default:
10799 gcc_unreachable ();
10800 }
10801 }
10802 }")
10804 ;; Call to function in current module. No TOC pointer reload needed.
10805 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10806 ;; either the function was not prototyped, or it was prototyped as a
10807 ;; variable argument function. It is > 0 if FP registers were passed
10808 ;; and < 0 if they were not.
10810 (define_insn "*call_local32"
10811 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10812 (match_operand 1 "" "g,g"))
10813 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10814 (clobber (match_scratch:SI 3 "=l,l"))]
10815 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10816 "*
10817 {
10818 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10819 output_asm_insn (\"crxor 6,6,6\", operands);
10821 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10822 output_asm_insn (\"creqv 6,6,6\", operands);
10824 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10825 }"
10826 [(set_attr "type" "branch")
10827 (set_attr "length" "4,8")])
10829 (define_insn "*call_local64"
10830 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10831 (match_operand 1 "" "g,g"))
10832 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10833 (clobber (match_scratch:SI 3 "=l,l"))]
10834 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10835 "*
10836 {
10837 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10838 output_asm_insn (\"crxor 6,6,6\", operands);
10840 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10841 output_asm_insn (\"creqv 6,6,6\", operands);
10843 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10844 }"
10845 [(set_attr "type" "branch")
10846 (set_attr "length" "4,8")])
10848 (define_insn "*call_value_local32"
10849 [(set (match_operand 0 "" "")
10850 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10851 (match_operand 2 "" "g,g")))
10852 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10853 (clobber (match_scratch:SI 4 "=l,l"))]
10854 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10855 "*
10856 {
10857 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10858 output_asm_insn (\"crxor 6,6,6\", operands);
10860 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10861 output_asm_insn (\"creqv 6,6,6\", operands);
10863 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10864 }"
10865 [(set_attr "type" "branch")
10866 (set_attr "length" "4,8")])
10869 (define_insn "*call_value_local64"
10870 [(set (match_operand 0 "" "")
10871 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10872 (match_operand 2 "" "g,g")))
10873 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10874 (clobber (match_scratch:SI 4 "=l,l"))]
10875 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10876 "*
10877 {
10878 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10879 output_asm_insn (\"crxor 6,6,6\", operands);
10881 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10882 output_asm_insn (\"creqv 6,6,6\", operands);
10884 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10885 }"
10886 [(set_attr "type" "branch")
10887 (set_attr "length" "4,8")])
10889 ;; Call to function which may be in another module. Restore the TOC
10890 ;; pointer (r2) after the call unless this is System V.
10891 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10892 ;; either the function was not prototyped, or it was prototyped as a
10893 ;; variable argument function. It is > 0 if FP registers were passed
10894 ;; and < 0 if they were not.
10896 (define_insn "*call_indirect_nonlocal_aix32"
10897 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10898 (match_operand 1 "" "g,g"))
10899 (use (reg:SI 2))
10900 (use (reg:SI 11))
10901 (set (reg:SI 2)
10902 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10903 (clobber (match_scratch:SI 2 "=l,l"))]
10904 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10905 "b%T0l\;{l|lwz} 2,20(1)"
10906 [(set_attr "type" "jmpreg")
10907 (set_attr "length" "8")])
10909 (define_insn "*call_nonlocal_aix32"
10910 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10911 (match_operand 1 "" "g"))
10912 (use (match_operand:SI 2 "immediate_operand" "O"))
10913 (clobber (match_scratch:SI 3 "=l"))]
10914 "TARGET_32BIT
10915 && DEFAULT_ABI == ABI_AIX
10916 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10917 "bl %z0\;%."
10918 [(set_attr "type" "branch")
10919 (set_attr "length" "8")])
10921 (define_insn "*call_indirect_nonlocal_aix64"
10922 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10923 (match_operand 1 "" "g,g"))
10924 (use (reg:DI 2))
10925 (use (reg:DI 11))
10926 (set (reg:DI 2)
10927 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10928 (clobber (match_scratch:SI 2 "=l,l"))]
10929 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10930 "b%T0l\;ld 2,40(1)"
10931 [(set_attr "type" "jmpreg")
10932 (set_attr "length" "8")])
10934 (define_insn "*call_nonlocal_aix64"
10935 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10936 (match_operand 1 "" "g"))
10937 (use (match_operand:SI 2 "immediate_operand" "O"))
10938 (clobber (match_scratch:SI 3 "=l"))]
10939 "TARGET_64BIT
10940 && DEFAULT_ABI == ABI_AIX
10941 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10942 "bl %z0\;%."
10943 [(set_attr "type" "branch")
10944 (set_attr "length" "8")])
10946 (define_insn "*call_value_indirect_nonlocal_aix32"
10947 [(set (match_operand 0 "" "")
10948 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10949 (match_operand 2 "" "g,g")))
10950 (use (reg:SI 2))
10951 (use (reg:SI 11))
10952 (set (reg:SI 2)
10953 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10954 (clobber (match_scratch:SI 3 "=l,l"))]
10955 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10956 "b%T1l\;{l|lwz} 2,20(1)"
10957 [(set_attr "type" "jmpreg")
10958 (set_attr "length" "8")])
10960 (define_insn "*call_value_nonlocal_aix32"
10961 [(set (match_operand 0 "" "")
10962 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10963 (match_operand 2 "" "g")))
10964 (use (match_operand:SI 3 "immediate_operand" "O"))
10965 (clobber (match_scratch:SI 4 "=l"))]
10966 "TARGET_32BIT
10967 && DEFAULT_ABI == ABI_AIX
10968 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10969 "bl %z1\;%."
10970 [(set_attr "type" "branch")
10971 (set_attr "length" "8")])
10973 (define_insn "*call_value_indirect_nonlocal_aix64"
10974 [(set (match_operand 0 "" "")
10975 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10976 (match_operand 2 "" "g,g")))
10977 (use (reg:DI 2))
10978 (use (reg:DI 11))
10979 (set (reg:DI 2)
10980 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10981 (clobber (match_scratch:SI 3 "=l,l"))]
10982 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10983 "b%T1l\;ld 2,40(1)"
10984 [(set_attr "type" "jmpreg")
10985 (set_attr "length" "8")])
10987 (define_insn "*call_value_nonlocal_aix64"
10988 [(set (match_operand 0 "" "")
10989 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10990 (match_operand 2 "" "g")))
10991 (use (match_operand:SI 3 "immediate_operand" "O"))
10992 (clobber (match_scratch:SI 4 "=l"))]
10993 "TARGET_64BIT
10994 && DEFAULT_ABI == ABI_AIX
10995 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10996 "bl %z1\;%."
10997 [(set_attr "type" "branch")
10998 (set_attr "length" "8")])
11000 ;; A function pointer under System V is just a normal pointer
11001 ;; operands[0] is the function pointer
11002 ;; operands[1] is the stack size to clean up
11003 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11004 ;; which indicates how to set cr1
11006 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11007 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11008 (match_operand 1 "" "g,g,g,g"))
11009 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11010 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
11011 "DEFAULT_ABI == ABI_V4
11012 || DEFAULT_ABI == ABI_DARWIN"
11013 {
11014 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11015 output_asm_insn ("crxor 6,6,6", operands);
11017 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11018 output_asm_insn ("creqv 6,6,6", operands);
11020 return "b%T0l";
11021 }
11022 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11023 (set_attr "length" "4,4,8,8")])
11025 (define_insn "*call_nonlocal_sysv<mode>"
11026 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11027 (match_operand 1 "" "g,g"))
11028 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11029 (clobber (match_scratch:SI 3 "=l,l"))]
11030 "(DEFAULT_ABI == ABI_DARWIN
11031 || (DEFAULT_ABI == ABI_V4
11032 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11033 {
11034 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11035 output_asm_insn ("crxor 6,6,6", operands);
11037 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11038 output_asm_insn ("creqv 6,6,6", operands);
11040 #if TARGET_MACHO
11041 return output_call(insn, operands, 0, 2);
11042 #else
11043 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11044 {
11045 if (TARGET_SECURE_PLT && flag_pic == 2)
11046 /* The magic 32768 offset here and in the other sysv call insns
11047 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11048 See sysv4.h:toc_section. */
11049 return "bl %z0+32768@plt";
11050 else
11051 return "bl %z0@plt";
11052 }
11053 else
11054 return "bl %z0";
11055 #endif
11056 }
11057 [(set_attr "type" "branch,branch")
11058 (set_attr "length" "4,8")])
11060 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11061 [(set (match_operand 0 "" "")
11062 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11063 (match_operand 2 "" "g,g,g,g")))
11064 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11065 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
11066 "DEFAULT_ABI == ABI_V4
11067 || DEFAULT_ABI == ABI_DARWIN"
11068 {
11069 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11070 output_asm_insn ("crxor 6,6,6", operands);
11072 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11073 output_asm_insn ("creqv 6,6,6", operands);
11075 return "b%T1l";
11076 }
11077 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11078 (set_attr "length" "4,4,8,8")])
11080 (define_insn "*call_value_nonlocal_sysv<mode>"
11081 [(set (match_operand 0 "" "")
11082 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11083 (match_operand 2 "" "g,g")))
11084 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11085 (clobber (match_scratch:SI 4 "=l,l"))]
11086 "(DEFAULT_ABI == ABI_DARWIN
11087 || (DEFAULT_ABI == ABI_V4
11088 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11089 {
11090 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11091 output_asm_insn ("crxor 6,6,6", operands);
11093 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11094 output_asm_insn ("creqv 6,6,6", operands);
11096 #if TARGET_MACHO
11097 return output_call(insn, operands, 1, 3);
11098 #else
11099 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11100 {
11101 if (TARGET_SECURE_PLT && flag_pic == 2)
11102 return "bl %z1+32768@plt";
11103 else
11104 return "bl %z1@plt";
11105 }
11106 else
11107 return "bl %z1";
11108 #endif
11109 }
11110 [(set_attr "type" "branch,branch")
11111 (set_attr "length" "4,8")])
11113 ;; Call subroutine returning any type.
11114 (define_expand "untyped_call"
11115 [(parallel [(call (match_operand 0 "" "")
11116 (const_int 0))
11117 (match_operand 1 "" "")
11118 (match_operand 2 "" "")])]
11119 ""
11120 "
11121 {
11122 int i;
11124 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11126 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11127 {
11128 rtx set = XVECEXP (operands[2], 0, i);
11129 emit_move_insn (SET_DEST (set), SET_SRC (set));
11130 }
11132 /* The optimizer does not know that the call sets the function value
11133 registers we stored in the result block. We avoid problems by
11134 claiming that all hard registers are used and clobbered at this
11135 point. */
11136 emit_insn (gen_blockage ());
11138 DONE;
11139 }")
11141 ;; sibling call patterns
11142 (define_expand "sibcall"
11143 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11144 (match_operand 1 "" ""))
11145 (use (match_operand 2 "" ""))
11146 (use (match_operand 3 "" ""))
11147 (return)])]
11148 ""
11149 "
11150 {
11151 #if TARGET_MACHO
11152 if (MACHOPIC_INDIRECT)
11153 operands[0] = machopic_indirect_call_target (operands[0]);
11154 #endif
11156 gcc_assert (GET_CODE (operands[0]) == MEM);
11157 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11159 operands[0] = XEXP (operands[0], 0);
11160 operands[3] = gen_reg_rtx (SImode);
11162 }")
11164 ;; this and similar patterns must be marked as using LR, otherwise
11165 ;; dataflow will try to delete the store into it. This is true
11166 ;; even when the actual reg to jump to is in CTR, when LR was
11167 ;; saved and restored around the PIC-setting BCL.
11168 (define_insn "*sibcall_local32"
11169 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11170 (match_operand 1 "" "g,g"))
11171 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11172 (use (match_operand:SI 3 "register_operand" "l,l"))
11173 (return)]
11174 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11175 "*
11176 {
11177 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11178 output_asm_insn (\"crxor 6,6,6\", operands);
11180 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11181 output_asm_insn (\"creqv 6,6,6\", operands);
11183 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11184 }"
11185 [(set_attr "type" "branch")
11186 (set_attr "length" "4,8")])
11188 (define_insn "*sibcall_local64"
11189 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11190 (match_operand 1 "" "g,g"))
11191 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11192 (use (match_operand:SI 3 "register_operand" "l,l"))
11193 (return)]
11194 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11195 "*
11196 {
11197 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11198 output_asm_insn (\"crxor 6,6,6\", operands);
11200 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11201 output_asm_insn (\"creqv 6,6,6\", operands);
11203 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11204 }"
11205 [(set_attr "type" "branch")
11206 (set_attr "length" "4,8")])
11208 (define_insn "*sibcall_value_local32"
11209 [(set (match_operand 0 "" "")
11210 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11211 (match_operand 2 "" "g,g")))
11212 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11213 (use (match_operand:SI 4 "register_operand" "l,l"))
11214 (return)]
11215 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11216 "*
11217 {
11218 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11219 output_asm_insn (\"crxor 6,6,6\", operands);
11221 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11222 output_asm_insn (\"creqv 6,6,6\", operands);
11224 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11225 }"
11226 [(set_attr "type" "branch")
11227 (set_attr "length" "4,8")])
11230 (define_insn "*sibcall_value_local64"
11231 [(set (match_operand 0 "" "")
11232 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11233 (match_operand 2 "" "g,g")))
11234 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11235 (use (match_operand:SI 4 "register_operand" "l,l"))
11236 (return)]
11237 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11238 "*
11239 {
11240 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11241 output_asm_insn (\"crxor 6,6,6\", operands);
11243 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11244 output_asm_insn (\"creqv 6,6,6\", operands);
11246 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11247 }"
11248 [(set_attr "type" "branch")
11249 (set_attr "length" "4,8")])
11251 (define_insn "*sibcall_nonlocal_aix32"
11252 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11253 (match_operand 1 "" "g"))
11254 (use (match_operand:SI 2 "immediate_operand" "O"))
11255 (use (match_operand:SI 3 "register_operand" "l"))
11256 (return)]
11257 "TARGET_32BIT
11258 && DEFAULT_ABI == ABI_AIX
11259 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11260 "b %z0"
11261 [(set_attr "type" "branch")
11262 (set_attr "length" "4")])
11264 (define_insn "*sibcall_nonlocal_aix64"
11265 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11266 (match_operand 1 "" "g"))
11267 (use (match_operand:SI 2 "immediate_operand" "O"))
11268 (use (match_operand:SI 3 "register_operand" "l"))
11269 (return)]
11270 "TARGET_64BIT
11271 && DEFAULT_ABI == ABI_AIX
11272 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11273 "b %z0"
11274 [(set_attr "type" "branch")
11275 (set_attr "length" "4")])
11277 (define_insn "*sibcall_value_nonlocal_aix32"
11278 [(set (match_operand 0 "" "")
11279 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11280 (match_operand 2 "" "g")))
11281 (use (match_operand:SI 3 "immediate_operand" "O"))
11282 (use (match_operand:SI 4 "register_operand" "l"))
11283 (return)]
11284 "TARGET_32BIT
11285 && DEFAULT_ABI == ABI_AIX
11286 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11287 "b %z1"
11288 [(set_attr "type" "branch")
11289 (set_attr "length" "4")])
11291 (define_insn "*sibcall_value_nonlocal_aix64"
11292 [(set (match_operand 0 "" "")
11293 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11294 (match_operand 2 "" "g")))
11295 (use (match_operand:SI 3 "immediate_operand" "O"))
11296 (use (match_operand:SI 4 "register_operand" "l"))
11297 (return)]
11298 "TARGET_64BIT
11299 && DEFAULT_ABI == ABI_AIX
11300 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11301 "b %z1"
11302 [(set_attr "type" "branch")
11303 (set_attr "length" "4")])
11305 (define_insn "*sibcall_nonlocal_sysv<mode>"
11306 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11307 (match_operand 1 "" ""))
11308 (use (match_operand 2 "immediate_operand" "O,n"))
11309 (use (match_operand:SI 3 "register_operand" "l,l"))
11310 (return)]
11311 "(DEFAULT_ABI == ABI_DARWIN
11312 || DEFAULT_ABI == ABI_V4)
11313 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11314 "*
11315 {
11316 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11317 output_asm_insn (\"crxor 6,6,6\", operands);
11319 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11320 output_asm_insn (\"creqv 6,6,6\", operands);
11322 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11323 {
11324 if (TARGET_SECURE_PLT && flag_pic == 2)
11325 return \"b %z0+32768@plt\";
11326 else
11327 return \"b %z0@plt\";
11328 }
11329 else
11330 return \"b %z0\";
11331 }"
11332 [(set_attr "type" "branch,branch")
11333 (set_attr "length" "4,8")])
11335 (define_expand "sibcall_value"
11336 [(parallel [(set (match_operand 0 "register_operand" "")
11337 (call (mem:SI (match_operand 1 "address_operand" ""))
11338 (match_operand 2 "" "")))
11339 (use (match_operand 3 "" ""))
11340 (use (match_operand 4 "" ""))
11341 (return)])]
11342 ""
11343 "
11344 {
11345 #if TARGET_MACHO
11346 if (MACHOPIC_INDIRECT)
11347 operands[1] = machopic_indirect_call_target (operands[1]);
11348 #endif
11350 gcc_assert (GET_CODE (operands[1]) == MEM);
11351 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11353 operands[1] = XEXP (operands[1], 0);
11354 operands[4] = gen_reg_rtx (SImode);
11356 }")
11358 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11359 [(set (match_operand 0 "" "")
11360 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11361 (match_operand 2 "" "")))
11362 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11363 (use (match_operand:SI 4 "register_operand" "l,l"))
11364 (return)]
11365 "(DEFAULT_ABI == ABI_DARWIN
11366 || DEFAULT_ABI == ABI_V4)
11367 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11368 "*
11369 {
11370 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11371 output_asm_insn (\"crxor 6,6,6\", operands);
11373 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11374 output_asm_insn (\"creqv 6,6,6\", operands);
11376 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11377 {
11378 if (TARGET_SECURE_PLT && flag_pic == 2)
11379 return \"b %z1+32768@plt\";
11380 else
11381 return \"b %z1@plt\";
11382 }
11383 else
11384 return \"b %z1\";
11385 }"
11386 [(set_attr "type" "branch,branch")
11387 (set_attr "length" "4,8")])
11389 (define_expand "sibcall_epilogue"
11390 [(use (const_int 0))]
11391 "TARGET_SCHED_PROLOG"
11392 "
11393 {
11394 rs6000_emit_epilogue (TRUE);
11395 DONE;
11396 }")
11398 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11399 ;; all of memory. This blocks insns from being moved across this point.
11401 (define_insn "blockage"
11402 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11403 ""
11404 "")
11405 \f
11406 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11407 ;; signed & unsigned, and one type of branch.
11408 ;;
11409 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11410 ;; insns, and branches. We store the operands of compares until we see
11411 ;; how it is used.
11412 (define_expand "cmp<mode>"
11413 [(set (cc0)
11414 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11415 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11416 ""
11417 "
11418 {
11419 /* Take care of the possibility that operands[1] might be negative but
11420 this might be a logical operation. That insn doesn't exist. */
11421 if (GET_CODE (operands[1]) == CONST_INT
11422 && INTVAL (operands[1]) < 0)
11423 operands[1] = force_reg (<MODE>mode, operands[1]);
11425 rs6000_compare_op0 = operands[0];
11426 rs6000_compare_op1 = operands[1];
11427 rs6000_compare_fp_p = 0;
11428 DONE;
11429 }")
11431 (define_expand "cmp<mode>"
11432 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11433 (match_operand:FP 1 "gpc_reg_operand" "")))]
11434 ""
11435 "
11436 {
11437 rs6000_compare_op0 = operands[0];
11438 rs6000_compare_op1 = operands[1];
11439 rs6000_compare_fp_p = 1;
11440 DONE;
11441 }")
11443 (define_expand "beq"
11444 [(use (match_operand 0 "" ""))]
11445 ""
11446 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11448 (define_expand "bne"
11449 [(use (match_operand 0 "" ""))]
11450 ""
11451 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11453 (define_expand "bge"
11454 [(use (match_operand 0 "" ""))]
11455 ""
11456 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11458 (define_expand "bgt"
11459 [(use (match_operand 0 "" ""))]
11460 ""
11461 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11463 (define_expand "ble"
11464 [(use (match_operand 0 "" ""))]
11465 ""
11466 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11468 (define_expand "blt"
11469 [(use (match_operand 0 "" ""))]
11470 ""
11471 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11473 (define_expand "bgeu"
11474 [(use (match_operand 0 "" ""))]
11475 ""
11476 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11478 (define_expand "bgtu"
11479 [(use (match_operand 0 "" ""))]
11480 ""
11481 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11483 (define_expand "bleu"
11484 [(use (match_operand 0 "" ""))]
11485 ""
11486 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11488 (define_expand "bltu"
11489 [(use (match_operand 0 "" ""))]
11490 ""
11491 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11493 (define_expand "bunordered"
11494 [(use (match_operand 0 "" ""))]
11495 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11496 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11498 (define_expand "bordered"
11499 [(use (match_operand 0 "" ""))]
11500 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11501 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11503 (define_expand "buneq"
11504 [(use (match_operand 0 "" ""))]
11505 ""
11506 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11508 (define_expand "bunge"
11509 [(use (match_operand 0 "" ""))]
11510 ""
11511 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11513 (define_expand "bungt"
11514 [(use (match_operand 0 "" ""))]
11515 ""
11516 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11518 (define_expand "bunle"
11519 [(use (match_operand 0 "" ""))]
11520 ""
11521 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11523 (define_expand "bunlt"
11524 [(use (match_operand 0 "" ""))]
11525 ""
11526 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11528 (define_expand "bltgt"
11529 [(use (match_operand 0 "" ""))]
11530 ""
11531 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11533 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11534 ;; For SEQ, likewise, except that comparisons with zero should be done
11535 ;; with an scc insns. However, due to the order that combine see the
11536 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11537 ;; the cases we don't want to handle.
11538 (define_expand "seq"
11539 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11540 ""
11541 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11543 (define_expand "sne"
11544 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11545 ""
11546 "
11547 {
11548 if (! rs6000_compare_fp_p)
11549 FAIL;
11551 rs6000_emit_sCOND (NE, operands[0]);
11552 DONE;
11553 }")
11555 ;; A >= 0 is best done the portable way for A an integer.
11556 (define_expand "sge"
11557 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11558 ""
11559 "
11560 {
11561 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11562 FAIL;
11564 rs6000_emit_sCOND (GE, operands[0]);
11565 DONE;
11566 }")
11568 ;; A > 0 is best done using the portable sequence, so fail in that case.
11569 (define_expand "sgt"
11570 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11571 ""
11572 "
11573 {
11574 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11575 FAIL;
11577 rs6000_emit_sCOND (GT, operands[0]);
11578 DONE;
11579 }")
11581 ;; A <= 0 is best done the portable way for A an integer.
11582 (define_expand "sle"
11583 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11584 ""
11585 "
11586 {
11587 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11588 FAIL;
11590 rs6000_emit_sCOND (LE, operands[0]);
11591 DONE;
11592 }")
11594 ;; A < 0 is best done in the portable way for A an integer.
11595 (define_expand "slt"
11596 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11597 ""
11598 "
11599 {
11600 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11601 FAIL;
11603 rs6000_emit_sCOND (LT, operands[0]);
11604 DONE;
11605 }")
11607 (define_expand "sgeu"
11608 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11609 ""
11610 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11612 (define_expand "sgtu"
11613 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11614 ""
11615 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11617 (define_expand "sleu"
11618 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11619 ""
11620 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11622 (define_expand "sltu"
11623 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11624 ""
11625 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11627 (define_expand "sunordered"
11628 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11629 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11630 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11632 (define_expand "sordered"
11633 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11634 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11635 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11637 (define_expand "suneq"
11638 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11639 ""
11640 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11642 (define_expand "sunge"
11643 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11644 ""
11645 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11647 (define_expand "sungt"
11648 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11649 ""
11650 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11652 (define_expand "sunle"
11653 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11654 ""
11655 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11657 (define_expand "sunlt"
11658 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11659 ""
11660 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11662 (define_expand "sltgt"
11663 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11664 ""
11665 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11667 (define_expand "stack_protect_set"
11668 [(match_operand 0 "memory_operand" "")
11669 (match_operand 1 "memory_operand" "")]
11670 ""
11671 {
11672 #ifdef TARGET_THREAD_SSP_OFFSET
11673 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11674 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11675 operands[1] = gen_rtx_MEM (Pmode, addr);
11676 #endif
11677 if (TARGET_64BIT)
11678 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11679 else
11680 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11681 DONE;
11682 })
11684 (define_insn "stack_protect_setsi"
11685 [(set (match_operand:SI 0 "memory_operand" "=m")
11686 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11687 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11688 "TARGET_32BIT"
11689 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11690 [(set_attr "type" "three")
11691 (set_attr "length" "12")])
11693 (define_insn "stack_protect_setdi"
11694 [(set (match_operand:DI 0 "memory_operand" "=m")
11695 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11696 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11697 "TARGET_64BIT"
11698 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11699 [(set_attr "type" "three")
11700 (set_attr "length" "12")])
11702 (define_expand "stack_protect_test"
11703 [(match_operand 0 "memory_operand" "")
11704 (match_operand 1 "memory_operand" "")
11705 (match_operand 2 "" "")]
11706 ""
11707 {
11708 #ifdef TARGET_THREAD_SSP_OFFSET
11709 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11710 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11711 operands[1] = gen_rtx_MEM (Pmode, addr);
11712 #endif
11713 rs6000_compare_op0 = operands[0];
11714 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11715 UNSPEC_SP_TEST);
11716 rs6000_compare_fp_p = 0;
11717 emit_jump_insn (gen_beq (operands[2]));
11718 DONE;
11719 })
11721 (define_insn "stack_protect_testsi"
11722 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11723 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11724 (match_operand:SI 2 "memory_operand" "m,m")]
11725 UNSPEC_SP_TEST))
11726 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11727 (clobber (match_scratch:SI 3 "=&r,&r"))]
11728 "TARGET_32BIT"
11729 "@
11730 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11731 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11732 [(set_attr "length" "16,20")])
11734 (define_insn "stack_protect_testdi"
11735 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11736 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11737 (match_operand:DI 2 "memory_operand" "m,m")]
11738 UNSPEC_SP_TEST))
11739 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11740 (clobber (match_scratch:DI 3 "=&r,&r"))]
11741 "TARGET_64BIT"
11742 "@
11743 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11744 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11745 [(set_attr "length" "16,20")])
11747 \f
11748 ;; Here are the actual compare insns.
11749 (define_insn "*cmp<mode>_internal1"
11750 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11751 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11752 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11753 ""
11754 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11755 [(set_attr "type" "cmp")])
11757 ;; If we are comparing a register for equality with a large constant,
11758 ;; we can do this with an XOR followed by a compare. But this is profitable
11759 ;; only if the large constant is only used for the comparison (and in this
11760 ;; case we already have a register to reuse as scratch).
11761 ;;
11762 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11763 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11765 (define_peephole2
11766 [(set (match_operand:SI 0 "register_operand")
11767 (match_operand:SI 1 "logical_const_operand" ""))
11768 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11769 [(match_dup 0)
11770 (match_operand:SI 2 "logical_const_operand" "")]))
11771 (set (match_operand:CC 4 "cc_reg_operand" "")
11772 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11773 (match_dup 0)))
11774 (set (pc)
11775 (if_then_else (match_operator 6 "equality_operator"
11776 [(match_dup 4) (const_int 0)])
11777 (match_operand 7 "" "")
11778 (match_operand 8 "" "")))]
11779 "peep2_reg_dead_p (3, operands[0])
11780 && peep2_reg_dead_p (4, operands[4])"
11781 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11782 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11783 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11785 {
11786 /* Get the constant we are comparing against, and see what it looks like
11787 when sign-extended from 16 to 32 bits. Then see what constant we could
11788 XOR with SEXTC to get the sign-extended value. */
11789 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11790 SImode,
11791 operands[1], operands[2]);
11792 HOST_WIDE_INT c = INTVAL (cnst);
11793 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11794 HOST_WIDE_INT xorv = c ^ sextc;
11796 operands[9] = GEN_INT (xorv);
11797 operands[10] = GEN_INT (sextc);
11798 })
11800 (define_insn "*cmpsi_internal2"
11801 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11802 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11803 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11804 ""
11805 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11806 [(set_attr "type" "cmp")])
11808 (define_insn "*cmpdi_internal2"
11809 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11810 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11811 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11812 ""
11813 "cmpld%I2 %0,%1,%b2"
11814 [(set_attr "type" "cmp")])
11816 ;; The following two insns don't exist as single insns, but if we provide
11817 ;; them, we can swap an add and compare, which will enable us to overlap more
11818 ;; of the required delay between a compare and branch. We generate code for
11819 ;; them by splitting.
11821 (define_insn ""
11822 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11823 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11824 (match_operand:SI 2 "short_cint_operand" "i")))
11825 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11826 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11827 ""
11828 "#"
11829 [(set_attr "length" "8")])
11831 (define_insn ""
11832 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11833 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11834 (match_operand:SI 2 "u_short_cint_operand" "i")))
11835 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11836 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11837 ""
11838 "#"
11839 [(set_attr "length" "8")])
11841 (define_split
11842 [(set (match_operand:CC 3 "cc_reg_operand" "")
11843 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11844 (match_operand:SI 2 "short_cint_operand" "")))
11845 (set (match_operand:SI 0 "gpc_reg_operand" "")
11846 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11847 ""
11848 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11849 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11851 (define_split
11852 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11853 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11854 (match_operand:SI 2 "u_short_cint_operand" "")))
11855 (set (match_operand:SI 0 "gpc_reg_operand" "")
11856 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11857 ""
11858 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11859 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11861 (define_insn "*cmpsf_internal1"
11862 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11863 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11864 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11865 "TARGET_HARD_FLOAT && TARGET_FPRS"
11866 "fcmpu %0,%1,%2"
11867 [(set_attr "type" "fpcompare")])
11869 (define_insn "*cmpdf_internal1"
11870 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11871 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11872 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11873 "TARGET_HARD_FLOAT && TARGET_FPRS"
11874 "fcmpu %0,%1,%2"
11875 [(set_attr "type" "fpcompare")])
11877 ;; Only need to compare second words if first words equal
11878 (define_insn "*cmptf_internal1"
11879 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11880 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11881 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11882 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11883 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11884 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11885 [(set_attr "type" "fpcompare")
11886 (set_attr "length" "12")])
11888 (define_insn_and_split "*cmptf_internal2"
11889 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11890 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11891 (match_operand:TF 2 "gpc_reg_operand" "f")))
11892 (clobber (match_scratch:DF 3 "=f"))
11893 (clobber (match_scratch:DF 4 "=f"))
11894 (clobber (match_scratch:DF 5 "=f"))
11895 (clobber (match_scratch:DF 6 "=f"))
11896 (clobber (match_scratch:DF 7 "=f"))
11897 (clobber (match_scratch:DF 8 "=f"))
11898 (clobber (match_scratch:DF 9 "=f"))
11899 (clobber (match_scratch:DF 10 "=f"))]
11900 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11901 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11902 "#"
11903 "&& reload_completed"
11904 [(set (match_dup 3) (match_dup 13))
11905 (set (match_dup 4) (match_dup 14))
11906 (set (match_dup 9) (abs:DF (match_dup 5)))
11907 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11908 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11909 (label_ref (match_dup 11))
11910 (pc)))
11911 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11912 (set (pc) (label_ref (match_dup 12)))
11913 (match_dup 11)
11914 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11915 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11916 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11917 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11918 (match_dup 12)]
11919 {
11920 REAL_VALUE_TYPE rv;
11921 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11922 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11924 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11925 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11926 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11927 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11928 operands[11] = gen_label_rtx ();
11929 operands[12] = gen_label_rtx ();
11930 real_inf (&rv);
11931 operands[13] = force_const_mem (DFmode,
11932 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11933 operands[14] = force_const_mem (DFmode,
11934 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11935 DFmode));
11936 if (TARGET_TOC)
11937 {
11938 operands[13] = gen_const_mem (DFmode,
11939 create_TOC_reference (XEXP (operands[13], 0)));
11940 operands[14] = gen_const_mem (DFmode,
11941 create_TOC_reference (XEXP (operands[14], 0)));
11942 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11943 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11944 }
11945 })
11946 \f
11947 ;; Now we have the scc insns. We can do some combinations because of the
11948 ;; way the machine works.
11949 ;;
11950 ;; Note that this is probably faster if we can put an insn between the
11951 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11952 ;; cases the insns below which don't use an intermediate CR field will
11953 ;; be used instead.
11954 (define_insn ""
11955 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11956 (match_operator:SI 1 "scc_comparison_operator"
11957 [(match_operand 2 "cc_reg_operand" "y")
11958 (const_int 0)]))]
11959 ""
11960 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11961 [(set (attr "type")
11962 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11963 (const_string "mfcrf")
11964 ]
11965 (const_string "mfcr")))
11966 (set_attr "length" "8")])
11968 ;; Same as above, but get the GT bit.
11969 (define_insn "move_from_CR_gt_bit"
11970 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11971 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11972 "TARGET_E500"
11973 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11974 [(set_attr "type" "mfcr")
11975 (set_attr "length" "8")])
11977 ;; Same as above, but get the OV/ORDERED bit.
11978 (define_insn "move_from_CR_ov_bit"
11979 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11980 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11981 "TARGET_ISEL"
11982 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11983 [(set_attr "type" "mfcr")
11984 (set_attr "length" "8")])
11986 (define_insn ""
11987 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11988 (match_operator:DI 1 "scc_comparison_operator"
11989 [(match_operand 2 "cc_reg_operand" "y")
11990 (const_int 0)]))]
11991 "TARGET_POWERPC64"
11992 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11993 [(set (attr "type")
11994 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11995 (const_string "mfcrf")
11996 ]
11997 (const_string "mfcr")))
11998 (set_attr "length" "8")])
12000 (define_insn ""
12001 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12002 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12003 [(match_operand 2 "cc_reg_operand" "y,y")
12004 (const_int 0)])
12005 (const_int 0)))
12006 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12007 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12008 "TARGET_32BIT"
12009 "@
12010 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12011 #"
12012 [(set_attr "type" "delayed_compare")
12013 (set_attr "length" "8,16")])
12015 (define_split
12016 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12017 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12018 [(match_operand 2 "cc_reg_operand" "")
12019 (const_int 0)])
12020 (const_int 0)))
12021 (set (match_operand:SI 3 "gpc_reg_operand" "")
12022 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12023 "TARGET_32BIT && reload_completed"
12024 [(set (match_dup 3)
12025 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12026 (set (match_dup 0)
12027 (compare:CC (match_dup 3)
12028 (const_int 0)))]
12029 "")
12031 (define_insn ""
12032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12033 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12034 [(match_operand 2 "cc_reg_operand" "y")
12035 (const_int 0)])
12036 (match_operand:SI 3 "const_int_operand" "n")))]
12037 ""
12038 "*
12039 {
12040 int is_bit = ccr_bit (operands[1], 1);
12041 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12042 int count;
12044 if (is_bit >= put_bit)
12045 count = is_bit - put_bit;
12046 else
12047 count = 32 - (put_bit - is_bit);
12049 operands[4] = GEN_INT (count);
12050 operands[5] = GEN_INT (put_bit);
12052 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12053 }"
12054 [(set (attr "type")
12055 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12056 (const_string "mfcrf")
12057 ]
12058 (const_string "mfcr")))
12059 (set_attr "length" "8")])
12061 (define_insn ""
12062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12063 (compare:CC
12064 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12065 [(match_operand 2 "cc_reg_operand" "y,y")
12066 (const_int 0)])
12067 (match_operand:SI 3 "const_int_operand" "n,n"))
12068 (const_int 0)))
12069 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12070 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12071 (match_dup 3)))]
12072 ""
12073 "*
12074 {
12075 int is_bit = ccr_bit (operands[1], 1);
12076 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12077 int count;
12079 /* Force split for non-cc0 compare. */
12080 if (which_alternative == 1)
12081 return \"#\";
12083 if (is_bit >= put_bit)
12084 count = is_bit - put_bit;
12085 else
12086 count = 32 - (put_bit - is_bit);
12088 operands[5] = GEN_INT (count);
12089 operands[6] = GEN_INT (put_bit);
12091 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12092 }"
12093 [(set_attr "type" "delayed_compare")
12094 (set_attr "length" "8,16")])
12096 (define_split
12097 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12098 (compare:CC
12099 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12100 [(match_operand 2 "cc_reg_operand" "")
12101 (const_int 0)])
12102 (match_operand:SI 3 "const_int_operand" ""))
12103 (const_int 0)))
12104 (set (match_operand:SI 4 "gpc_reg_operand" "")
12105 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12106 (match_dup 3)))]
12107 "reload_completed"
12108 [(set (match_dup 4)
12109 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12110 (match_dup 3)))
12111 (set (match_dup 0)
12112 (compare:CC (match_dup 4)
12113 (const_int 0)))]
12114 "")
12116 ;; There is a 3 cycle delay between consecutive mfcr instructions
12117 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12119 (define_peephole
12120 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12121 (match_operator:SI 1 "scc_comparison_operator"
12122 [(match_operand 2 "cc_reg_operand" "y")
12123 (const_int 0)]))
12124 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12125 (match_operator:SI 4 "scc_comparison_operator"
12126 [(match_operand 5 "cc_reg_operand" "y")
12127 (const_int 0)]))]
12128 "REGNO (operands[2]) != REGNO (operands[5])"
12129 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12130 [(set_attr "type" "mfcr")
12131 (set_attr "length" "12")])
12133 (define_peephole
12134 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12135 (match_operator:DI 1 "scc_comparison_operator"
12136 [(match_operand 2 "cc_reg_operand" "y")
12137 (const_int 0)]))
12138 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12139 (match_operator:DI 4 "scc_comparison_operator"
12140 [(match_operand 5 "cc_reg_operand" "y")
12141 (const_int 0)]))]
12142 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12143 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12144 [(set_attr "type" "mfcr")
12145 (set_attr "length" "12")])
12147 ;; There are some scc insns that can be done directly, without a compare.
12148 ;; These are faster because they don't involve the communications between
12149 ;; the FXU and branch units. In fact, we will be replacing all of the
12150 ;; integer scc insns here or in the portable methods in emit_store_flag.
12151 ;;
12152 ;; Also support (neg (scc ..)) since that construct is used to replace
12153 ;; branches, (plus (scc ..) ..) since that construct is common and
12154 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12155 ;; cases where it is no more expensive than (neg (scc ..)).
12157 ;; Have reload force a constant into a register for the simple insns that
12158 ;; otherwise won't accept constants. We do this because it is faster than
12159 ;; the cmp/mfcr sequence we would otherwise generate.
12161 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12162 (DI "rKJI")])
12164 (define_insn_and_split "*eq<mode>"
12165 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12166 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12167 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12168 "!TARGET_POWER"
12169 "#"
12170 "!TARGET_POWER"
12171 [(set (match_dup 0)
12172 (clz:GPR (match_dup 3)))
12173 (set (match_dup 0)
12174 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12175 {
12176 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12177 {
12178 /* Use output operand as intermediate. */
12179 operands[3] = operands[0];
12181 if (logical_operand (operands[2], <MODE>mode))
12182 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12183 gen_rtx_XOR (<MODE>mode,
12184 operands[1], operands[2])));
12185 else
12186 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12187 gen_rtx_PLUS (<MODE>mode, operands[1],
12188 negate_rtx (<MODE>mode,
12189 operands[2]))));
12190 }
12191 else
12192 operands[3] = operands[1];
12194 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12195 })
12197 (define_insn_and_split "*eq<mode>_compare"
12198 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12199 (compare:CC
12200 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12201 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12202 (const_int 0)))
12203 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12204 (eq:P (match_dup 1) (match_dup 2)))]
12205 "!TARGET_POWER && optimize_size"
12206 "#"
12207 "!TARGET_POWER && optimize_size"
12208 [(set (match_dup 0)
12209 (clz:P (match_dup 4)))
12210 (parallel [(set (match_dup 3)
12211 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12212 (const_int 0)))
12213 (set (match_dup 0)
12214 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12215 {
12216 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12217 {
12218 /* Use output operand as intermediate. */
12219 operands[4] = operands[0];
12221 if (logical_operand (operands[2], <MODE>mode))
12222 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12223 gen_rtx_XOR (<MODE>mode,
12224 operands[1], operands[2])));
12225 else
12226 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12227 gen_rtx_PLUS (<MODE>mode, operands[1],
12228 negate_rtx (<MODE>mode,
12229 operands[2]))));
12230 }
12231 else
12232 operands[4] = operands[1];
12234 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12235 })
12237 (define_insn "*eqsi_power"
12238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12239 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12240 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12241 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12242 "TARGET_POWER"
12243 "@
12244 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12245 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12246 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12247 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12248 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12249 [(set_attr "type" "three,two,three,three,three")
12250 (set_attr "length" "12,8,12,12,12")])
12252 ;; We have insns of the form shown by the first define_insn below. If
12253 ;; there is something inside the comparison operation, we must split it.
12254 (define_split
12255 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12256 (plus:SI (match_operator 1 "comparison_operator"
12257 [(match_operand:SI 2 "" "")
12258 (match_operand:SI 3
12259 "reg_or_cint_operand" "")])
12260 (match_operand:SI 4 "gpc_reg_operand" "")))
12261 (clobber (match_operand:SI 5 "register_operand" ""))]
12262 "! gpc_reg_operand (operands[2], SImode)"
12263 [(set (match_dup 5) (match_dup 2))
12264 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12265 (match_dup 4)))])
12267 (define_insn "*plus_eqsi"
12268 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12269 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12270 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12271 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12272 "TARGET_32BIT"
12273 "@
12274 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12275 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12276 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12277 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12278 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12279 [(set_attr "type" "three,two,three,three,three")
12280 (set_attr "length" "12,8,12,12,12")])
12282 (define_insn "*compare_plus_eqsi"
12283 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12284 (compare:CC
12285 (plus:SI
12286 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12287 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12288 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12289 (const_int 0)))
12290 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12291 "TARGET_32BIT && optimize_size"
12292 "@
12293 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12294 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12295 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12296 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12297 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12298 #
12299 #
12300 #
12301 #
12302 #"
12303 [(set_attr "type" "compare")
12304 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12306 (define_split
12307 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12308 (compare:CC
12309 (plus:SI
12310 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12311 (match_operand:SI 2 "scc_eq_operand" ""))
12312 (match_operand:SI 3 "gpc_reg_operand" ""))
12313 (const_int 0)))
12314 (clobber (match_scratch:SI 4 ""))]
12315 "TARGET_32BIT && optimize_size && reload_completed"
12316 [(set (match_dup 4)
12317 (plus:SI (eq:SI (match_dup 1)
12318 (match_dup 2))
12319 (match_dup 3)))
12320 (set (match_dup 0)
12321 (compare:CC (match_dup 4)
12322 (const_int 0)))]
12323 "")
12325 (define_insn "*plus_eqsi_compare"
12326 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12327 (compare:CC
12328 (plus:SI
12329 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12330 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12331 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12332 (const_int 0)))
12333 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12334 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12335 "TARGET_32BIT && optimize_size"
12336 "@
12337 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12338 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12339 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12340 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12341 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12342 #
12343 #
12344 #
12345 #
12346 #"
12347 [(set_attr "type" "compare")
12348 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12350 (define_split
12351 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12352 (compare:CC
12353 (plus:SI
12354 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12355 (match_operand:SI 2 "scc_eq_operand" ""))
12356 (match_operand:SI 3 "gpc_reg_operand" ""))
12357 (const_int 0)))
12358 (set (match_operand:SI 0 "gpc_reg_operand" "")
12359 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12360 "TARGET_32BIT && optimize_size && reload_completed"
12361 [(set (match_dup 0)
12362 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12363 (set (match_dup 4)
12364 (compare:CC (match_dup 0)
12365 (const_int 0)))]
12366 "")
12368 (define_insn "*neg_eq0<mode>"
12369 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12370 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12371 (const_int 0))))]
12372 ""
12373 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12374 [(set_attr "type" "two")
12375 (set_attr "length" "8")])
12377 (define_insn_and_split "*neg_eq<mode>"
12378 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12379 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12380 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12381 ""
12382 "#"
12383 ""
12384 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12385 {
12386 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12387 {
12388 /* Use output operand as intermediate. */
12389 operands[3] = operands[0];
12391 if (logical_operand (operands[2], <MODE>mode))
12392 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12393 gen_rtx_XOR (<MODE>mode,
12394 operands[1], operands[2])));
12395 else
12396 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12397 gen_rtx_PLUS (<MODE>mode, operands[1],
12398 negate_rtx (<MODE>mode,
12399 operands[2]))));
12400 }
12401 else
12402 operands[3] = operands[1];
12403 })
12405 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12406 ;; since it nabs/sr is just as fast.
12407 (define_insn "*ne0si"
12408 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12409 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12410 (const_int 31)))
12411 (clobber (match_scratch:SI 2 "=&r"))]
12412 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12413 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12414 [(set_attr "type" "two")
12415 (set_attr "length" "8")])
12417 (define_insn "*ne0di"
12418 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12419 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12420 (const_int 63)))
12421 (clobber (match_scratch:DI 2 "=&r"))]
12422 "TARGET_64BIT"
12423 "addic %2,%1,-1\;subfe %0,%2,%1"
12424 [(set_attr "type" "two")
12425 (set_attr "length" "8")])
12427 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12428 (define_insn "*plus_ne0si"
12429 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12430 (plus:SI (lshiftrt:SI
12431 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12432 (const_int 31))
12433 (match_operand:SI 2 "gpc_reg_operand" "r")))
12434 (clobber (match_scratch:SI 3 "=&r"))]
12435 "TARGET_32BIT"
12436 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12437 [(set_attr "type" "two")
12438 (set_attr "length" "8")])
12440 (define_insn "*plus_ne0di"
12441 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12442 (plus:DI (lshiftrt:DI
12443 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12444 (const_int 63))
12445 (match_operand:DI 2 "gpc_reg_operand" "r")))
12446 (clobber (match_scratch:DI 3 "=&r"))]
12447 "TARGET_64BIT"
12448 "addic %3,%1,-1\;addze %0,%2"
12449 [(set_attr "type" "two")
12450 (set_attr "length" "8")])
12452 (define_insn "*compare_plus_ne0si"
12453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12454 (compare:CC
12455 (plus:SI (lshiftrt:SI
12456 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12457 (const_int 31))
12458 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12459 (const_int 0)))
12460 (clobber (match_scratch:SI 3 "=&r,&r"))
12461 (clobber (match_scratch:SI 4 "=X,&r"))]
12462 "TARGET_32BIT"
12463 "@
12464 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12465 #"
12466 [(set_attr "type" "compare")
12467 (set_attr "length" "8,12")])
12469 (define_split
12470 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12471 (compare:CC
12472 (plus:SI (lshiftrt:SI
12473 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12474 (const_int 31))
12475 (match_operand:SI 2 "gpc_reg_operand" ""))
12476 (const_int 0)))
12477 (clobber (match_scratch:SI 3 ""))
12478 (clobber (match_scratch:SI 4 ""))]
12479 "TARGET_32BIT && reload_completed"
12480 [(parallel [(set (match_dup 3)
12481 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12482 (const_int 31))
12483 (match_dup 2)))
12484 (clobber (match_dup 4))])
12485 (set (match_dup 0)
12486 (compare:CC (match_dup 3)
12487 (const_int 0)))]
12488 "")
12490 (define_insn "*compare_plus_ne0di"
12491 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12492 (compare:CC
12493 (plus:DI (lshiftrt:DI
12494 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12495 (const_int 63))
12496 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12497 (const_int 0)))
12498 (clobber (match_scratch:DI 3 "=&r,&r"))]
12499 "TARGET_64BIT"
12500 "@
12501 addic %3,%1,-1\;addze. %3,%2
12502 #"
12503 [(set_attr "type" "compare")
12504 (set_attr "length" "8,12")])
12506 (define_split
12507 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12508 (compare:CC
12509 (plus:DI (lshiftrt:DI
12510 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12511 (const_int 63))
12512 (match_operand:DI 2 "gpc_reg_operand" ""))
12513 (const_int 0)))
12514 (clobber (match_scratch:DI 3 ""))]
12515 "TARGET_64BIT && reload_completed"
12516 [(set (match_dup 3)
12517 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12518 (const_int 63))
12519 (match_dup 2)))
12520 (set (match_dup 0)
12521 (compare:CC (match_dup 3)
12522 (const_int 0)))]
12523 "")
12525 (define_insn "*plus_ne0si_compare"
12526 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12527 (compare:CC
12528 (plus:SI (lshiftrt:SI
12529 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12530 (const_int 31))
12531 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12532 (const_int 0)))
12533 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12534 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12535 (match_dup 2)))
12536 (clobber (match_scratch:SI 3 "=&r,&r"))]
12537 "TARGET_32BIT"
12538 "@
12539 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12540 #"
12541 [(set_attr "type" "compare")
12542 (set_attr "length" "8,12")])
12544 (define_split
12545 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12546 (compare:CC
12547 (plus:SI (lshiftrt:SI
12548 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12549 (const_int 31))
12550 (match_operand:SI 2 "gpc_reg_operand" ""))
12551 (const_int 0)))
12552 (set (match_operand:SI 0 "gpc_reg_operand" "")
12553 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12554 (match_dup 2)))
12555 (clobber (match_scratch:SI 3 ""))]
12556 "TARGET_32BIT && reload_completed"
12557 [(parallel [(set (match_dup 0)
12558 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12559 (match_dup 2)))
12560 (clobber (match_dup 3))])
12561 (set (match_dup 4)
12562 (compare:CC (match_dup 0)
12563 (const_int 0)))]
12564 "")
12566 (define_insn "*plus_ne0di_compare"
12567 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12568 (compare:CC
12569 (plus:DI (lshiftrt:DI
12570 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12571 (const_int 63))
12572 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12573 (const_int 0)))
12574 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12575 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12576 (match_dup 2)))
12577 (clobber (match_scratch:DI 3 "=&r,&r"))]
12578 "TARGET_64BIT"
12579 "@
12580 addic %3,%1,-1\;addze. %0,%2
12581 #"
12582 [(set_attr "type" "compare")
12583 (set_attr "length" "8,12")])
12585 (define_split
12586 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12587 (compare:CC
12588 (plus:DI (lshiftrt:DI
12589 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12590 (const_int 63))
12591 (match_operand:DI 2 "gpc_reg_operand" ""))
12592 (const_int 0)))
12593 (set (match_operand:DI 0 "gpc_reg_operand" "")
12594 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12595 (match_dup 2)))
12596 (clobber (match_scratch:DI 3 ""))]
12597 "TARGET_64BIT && reload_completed"
12598 [(parallel [(set (match_dup 0)
12599 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12600 (match_dup 2)))
12601 (clobber (match_dup 3))])
12602 (set (match_dup 4)
12603 (compare:CC (match_dup 0)
12604 (const_int 0)))]
12605 "")
12607 (define_insn ""
12608 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12609 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12610 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12611 (clobber (match_scratch:SI 3 "=r,X"))]
12612 "TARGET_POWER"
12613 "@
12614 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12615 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12616 [(set_attr "length" "12")])
12618 (define_insn ""
12619 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12620 (compare:CC
12621 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12622 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12623 (const_int 0)))
12624 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12625 (le:SI (match_dup 1) (match_dup 2)))
12626 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12627 "TARGET_POWER"
12628 "@
12629 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12630 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12631 #
12632 #"
12633 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12634 (set_attr "length" "12,12,16,16")])
12636 (define_split
12637 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12638 (compare:CC
12639 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12640 (match_operand:SI 2 "reg_or_short_operand" ""))
12641 (const_int 0)))
12642 (set (match_operand:SI 0 "gpc_reg_operand" "")
12643 (le:SI (match_dup 1) (match_dup 2)))
12644 (clobber (match_scratch:SI 3 ""))]
12645 "TARGET_POWER && reload_completed"
12646 [(parallel [(set (match_dup 0)
12647 (le:SI (match_dup 1) (match_dup 2)))
12648 (clobber (match_dup 3))])
12649 (set (match_dup 4)
12650 (compare:CC (match_dup 0)
12651 (const_int 0)))]
12652 "")
12654 (define_insn ""
12655 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12656 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12657 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12658 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12659 "TARGET_POWER"
12660 "@
12661 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12662 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12663 [(set_attr "length" "12")])
12665 (define_insn ""
12666 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12667 (compare:CC
12668 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12669 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12670 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12671 (const_int 0)))
12672 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12673 "TARGET_POWER"
12674 "@
12675 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12676 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12677 #
12678 #"
12679 [(set_attr "type" "compare")
12680 (set_attr "length" "12,12,16,16")])
12682 (define_split
12683 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12684 (compare:CC
12685 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12686 (match_operand:SI 2 "reg_or_short_operand" ""))
12687 (match_operand:SI 3 "gpc_reg_operand" ""))
12688 (const_int 0)))
12689 (clobber (match_scratch:SI 4 ""))]
12690 "TARGET_POWER && reload_completed"
12691 [(set (match_dup 4)
12692 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12693 (match_dup 3)))
12694 (set (match_dup 0)
12695 (compare:CC (match_dup 4)
12696 (const_int 0)))]
12697 "")
12699 (define_insn ""
12700 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12701 (compare:CC
12702 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12703 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12704 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12705 (const_int 0)))
12706 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12707 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12708 "TARGET_POWER"
12709 "@
12710 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12711 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12712 #
12713 #"
12714 [(set_attr "type" "compare")
12715 (set_attr "length" "12,12,16,16")])
12717 (define_split
12718 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12719 (compare:CC
12720 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12721 (match_operand:SI 2 "reg_or_short_operand" ""))
12722 (match_operand:SI 3 "gpc_reg_operand" ""))
12723 (const_int 0)))
12724 (set (match_operand:SI 0 "gpc_reg_operand" "")
12725 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12726 "TARGET_POWER && reload_completed"
12727 [(set (match_dup 0)
12728 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12729 (set (match_dup 4)
12730 (compare:CC (match_dup 0)
12731 (const_int 0)))]
12732 "")
12734 (define_insn ""
12735 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12736 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12737 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12738 "TARGET_POWER"
12739 "@
12740 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12741 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12742 [(set_attr "length" "12")])
12744 (define_insn "*leu<mode>"
12745 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12746 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12747 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12748 ""
12749 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12750 [(set_attr "type" "three")
12751 (set_attr "length" "12")])
12753 (define_insn "*leu<mode>_compare"
12754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12755 (compare:CC
12756 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12757 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12758 (const_int 0)))
12759 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12760 (leu:P (match_dup 1) (match_dup 2)))]
12761 ""
12762 "@
12763 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12764 #"
12765 [(set_attr "type" "compare")
12766 (set_attr "length" "12,16")])
12768 (define_split
12769 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12770 (compare:CC
12771 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12772 (match_operand:P 2 "reg_or_short_operand" ""))
12773 (const_int 0)))
12774 (set (match_operand:P 0 "gpc_reg_operand" "")
12775 (leu:P (match_dup 1) (match_dup 2)))]
12776 "reload_completed"
12777 [(set (match_dup 0)
12778 (leu:P (match_dup 1) (match_dup 2)))
12779 (set (match_dup 3)
12780 (compare:CC (match_dup 0)
12781 (const_int 0)))]
12782 "")
12784 (define_insn "*plus_leu<mode>"
12785 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12786 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12787 (match_operand:P 2 "reg_or_short_operand" "rI"))
12788 (match_operand:P 3 "gpc_reg_operand" "r")))]
12789 ""
12790 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12791 [(set_attr "type" "two")
12792 (set_attr "length" "8")])
12794 (define_insn ""
12795 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12796 (compare:CC
12797 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12798 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12799 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12800 (const_int 0)))
12801 (clobber (match_scratch:SI 4 "=&r,&r"))]
12802 "TARGET_32BIT"
12803 "@
12804 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12805 #"
12806 [(set_attr "type" "compare")
12807 (set_attr "length" "8,12")])
12809 (define_split
12810 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12811 (compare:CC
12812 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12813 (match_operand:SI 2 "reg_or_short_operand" ""))
12814 (match_operand:SI 3 "gpc_reg_operand" ""))
12815 (const_int 0)))
12816 (clobber (match_scratch:SI 4 ""))]
12817 "TARGET_32BIT && reload_completed"
12818 [(set (match_dup 4)
12819 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12820 (match_dup 3)))
12821 (set (match_dup 0)
12822 (compare:CC (match_dup 4)
12823 (const_int 0)))]
12824 "")
12826 (define_insn ""
12827 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12828 (compare:CC
12829 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12830 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12831 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12832 (const_int 0)))
12833 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12834 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12835 "TARGET_32BIT"
12836 "@
12837 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12838 #"
12839 [(set_attr "type" "compare")
12840 (set_attr "length" "8,12")])
12842 (define_split
12843 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12844 (compare:CC
12845 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12846 (match_operand:SI 2 "reg_or_short_operand" ""))
12847 (match_operand:SI 3 "gpc_reg_operand" ""))
12848 (const_int 0)))
12849 (set (match_operand:SI 0 "gpc_reg_operand" "")
12850 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12851 "TARGET_32BIT && reload_completed"
12852 [(set (match_dup 0)
12853 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12854 (set (match_dup 4)
12855 (compare:CC (match_dup 0)
12856 (const_int 0)))]
12857 "")
12859 (define_insn "*neg_leu<mode>"
12860 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12861 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12862 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12863 ""
12864 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12865 [(set_attr "type" "three")
12866 (set_attr "length" "12")])
12868 (define_insn "*and_neg_leu<mode>"
12869 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12870 (and:P (neg:P
12871 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12872 (match_operand:P 2 "reg_or_short_operand" "rI")))
12873 (match_operand:P 3 "gpc_reg_operand" "r")))]
12874 ""
12875 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12876 [(set_attr "type" "three")
12877 (set_attr "length" "12")])
12879 (define_insn ""
12880 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12881 (compare:CC
12882 (and:SI (neg:SI
12883 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12884 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12885 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12886 (const_int 0)))
12887 (clobber (match_scratch:SI 4 "=&r,&r"))]
12888 "TARGET_32BIT"
12889 "@
12890 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12891 #"
12892 [(set_attr "type" "compare")
12893 (set_attr "length" "12,16")])
12895 (define_split
12896 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12897 (compare:CC
12898 (and:SI (neg:SI
12899 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12900 (match_operand:SI 2 "reg_or_short_operand" "")))
12901 (match_operand:SI 3 "gpc_reg_operand" ""))
12902 (const_int 0)))
12903 (clobber (match_scratch:SI 4 ""))]
12904 "TARGET_32BIT && reload_completed"
12905 [(set (match_dup 4)
12906 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12907 (match_dup 3)))
12908 (set (match_dup 0)
12909 (compare:CC (match_dup 4)
12910 (const_int 0)))]
12911 "")
12913 (define_insn ""
12914 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12915 (compare:CC
12916 (and:SI (neg:SI
12917 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12918 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12919 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12920 (const_int 0)))
12921 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12922 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12923 "TARGET_32BIT"
12924 "@
12925 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12926 #"
12927 [(set_attr "type" "compare")
12928 (set_attr "length" "12,16")])
12930 (define_split
12931 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12932 (compare:CC
12933 (and:SI (neg:SI
12934 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12935 (match_operand:SI 2 "reg_or_short_operand" "")))
12936 (match_operand:SI 3 "gpc_reg_operand" ""))
12937 (const_int 0)))
12938 (set (match_operand:SI 0 "gpc_reg_operand" "")
12939 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12940 "TARGET_32BIT && reload_completed"
12941 [(set (match_dup 0)
12942 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12943 (match_dup 3)))
12944 (set (match_dup 4)
12945 (compare:CC (match_dup 0)
12946 (const_int 0)))]
12947 "")
12949 (define_insn ""
12950 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12951 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12952 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12953 "TARGET_POWER"
12954 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12955 [(set_attr "length" "12")])
12957 (define_insn ""
12958 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12959 (compare:CC
12960 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12961 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12962 (const_int 0)))
12963 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12964 (lt:SI (match_dup 1) (match_dup 2)))]
12965 "TARGET_POWER"
12966 "@
12967 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12968 #"
12969 [(set_attr "type" "delayed_compare")
12970 (set_attr "length" "12,16")])
12972 (define_split
12973 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12974 (compare:CC
12975 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12976 (match_operand:SI 2 "reg_or_short_operand" ""))
12977 (const_int 0)))
12978 (set (match_operand:SI 0 "gpc_reg_operand" "")
12979 (lt:SI (match_dup 1) (match_dup 2)))]
12980 "TARGET_POWER && reload_completed"
12981 [(set (match_dup 0)
12982 (lt:SI (match_dup 1) (match_dup 2)))
12983 (set (match_dup 3)
12984 (compare:CC (match_dup 0)
12985 (const_int 0)))]
12986 "")
12988 (define_insn ""
12989 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12990 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12991 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12992 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12993 "TARGET_POWER"
12994 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12995 [(set_attr "length" "12")])
12997 (define_insn ""
12998 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12999 (compare:CC
13000 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13001 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13002 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13003 (const_int 0)))
13004 (clobber (match_scratch:SI 4 "=&r,&r"))]
13005 "TARGET_POWER"
13006 "@
13007 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13008 #"
13009 [(set_attr "type" "compare")
13010 (set_attr "length" "12,16")])
13012 (define_split
13013 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13014 (compare:CC
13015 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13016 (match_operand:SI 2 "reg_or_short_operand" ""))
13017 (match_operand:SI 3 "gpc_reg_operand" ""))
13018 (const_int 0)))
13019 (clobber (match_scratch:SI 4 ""))]
13020 "TARGET_POWER && reload_completed"
13021 [(set (match_dup 4)
13022 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13023 (match_dup 3)))
13024 (set (match_dup 0)
13025 (compare:CC (match_dup 4)
13026 (const_int 0)))]
13027 "")
13029 (define_insn ""
13030 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13031 (compare:CC
13032 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13033 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13034 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13035 (const_int 0)))
13036 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13037 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13038 "TARGET_POWER"
13039 "@
13040 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13041 #"
13042 [(set_attr "type" "compare")
13043 (set_attr "length" "12,16")])
13045 (define_split
13046 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13047 (compare:CC
13048 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13049 (match_operand:SI 2 "reg_or_short_operand" ""))
13050 (match_operand:SI 3 "gpc_reg_operand" ""))
13051 (const_int 0)))
13052 (set (match_operand:SI 0 "gpc_reg_operand" "")
13053 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13054 "TARGET_POWER && reload_completed"
13055 [(set (match_dup 0)
13056 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13057 (set (match_dup 4)
13058 (compare:CC (match_dup 0)
13059 (const_int 0)))]
13060 "")
13062 (define_insn ""
13063 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13064 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13065 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13066 "TARGET_POWER"
13067 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13068 [(set_attr "length" "12")])
13070 (define_insn_and_split "*ltu<mode>"
13071 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13072 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13073 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13074 ""
13075 "#"
13076 ""
13077 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13078 (set (match_dup 0) (neg:P (match_dup 0)))]
13079 "")
13081 (define_insn_and_split "*ltu<mode>_compare"
13082 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13083 (compare:CC
13084 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13085 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13086 (const_int 0)))
13087 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13088 (ltu:P (match_dup 1) (match_dup 2)))]
13089 ""
13090 "#"
13091 ""
13092 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13093 (parallel [(set (match_dup 3)
13094 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13095 (set (match_dup 0) (neg:P (match_dup 0)))])]
13096 "")
13098 (define_insn_and_split "*plus_ltu<mode>"
13099 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13100 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13101 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13102 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13103 ""
13104 "#"
13105 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13106 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13107 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13108 "")
13110 (define_insn_and_split "*plus_ltu<mode>_compare"
13111 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13112 (compare:CC
13113 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13114 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13115 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13116 (const_int 0)))
13117 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13118 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13119 ""
13120 "#"
13121 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13122 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13123 (parallel [(set (match_dup 4)
13124 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13125 (const_int 0)))
13126 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13127 "")
13129 (define_insn "*neg_ltu<mode>"
13130 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13131 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13132 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13133 ""
13134 "@
13135 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13136 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13137 [(set_attr "type" "two")
13138 (set_attr "length" "8")])
13140 (define_insn ""
13141 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13142 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13143 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13144 (clobber (match_scratch:SI 3 "=r"))]
13145 "TARGET_POWER"
13146 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13147 [(set_attr "length" "12")])
13149 (define_insn ""
13150 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13151 (compare:CC
13152 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13153 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13154 (const_int 0)))
13155 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13156 (ge:SI (match_dup 1) (match_dup 2)))
13157 (clobber (match_scratch:SI 3 "=r,r"))]
13158 "TARGET_POWER"
13159 "@
13160 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13161 #"
13162 [(set_attr "type" "compare")
13163 (set_attr "length" "12,16")])
13165 (define_split
13166 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13167 (compare:CC
13168 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13169 (match_operand:SI 2 "reg_or_short_operand" ""))
13170 (const_int 0)))
13171 (set (match_operand:SI 0 "gpc_reg_operand" "")
13172 (ge:SI (match_dup 1) (match_dup 2)))
13173 (clobber (match_scratch:SI 3 ""))]
13174 "TARGET_POWER && reload_completed"
13175 [(parallel [(set (match_dup 0)
13176 (ge:SI (match_dup 1) (match_dup 2)))
13177 (clobber (match_dup 3))])
13178 (set (match_dup 4)
13179 (compare:CC (match_dup 0)
13180 (const_int 0)))]
13181 "")
13183 (define_insn ""
13184 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13185 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13186 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13187 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13188 "TARGET_POWER"
13189 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13190 [(set_attr "length" "12")])
13192 (define_insn ""
13193 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13194 (compare:CC
13195 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13196 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13197 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13198 (const_int 0)))
13199 (clobber (match_scratch:SI 4 "=&r,&r"))]
13200 "TARGET_POWER"
13201 "@
13202 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13203 #"
13204 [(set_attr "type" "compare")
13205 (set_attr "length" "12,16")])
13207 (define_split
13208 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13209 (compare:CC
13210 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13211 (match_operand:SI 2 "reg_or_short_operand" ""))
13212 (match_operand:SI 3 "gpc_reg_operand" ""))
13213 (const_int 0)))
13214 (clobber (match_scratch:SI 4 ""))]
13215 "TARGET_POWER && reload_completed"
13216 [(set (match_dup 4)
13217 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13218 (match_dup 3)))
13219 (set (match_dup 0)
13220 (compare:CC (match_dup 4)
13221 (const_int 0)))]
13222 "")
13224 (define_insn ""
13225 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13226 (compare:CC
13227 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13228 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13229 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13230 (const_int 0)))
13231 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13232 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13233 "TARGET_POWER"
13234 "@
13235 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13236 #"
13237 [(set_attr "type" "compare")
13238 (set_attr "length" "12,16")])
13240 (define_split
13241 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13242 (compare:CC
13243 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13244 (match_operand:SI 2 "reg_or_short_operand" ""))
13245 (match_operand:SI 3 "gpc_reg_operand" ""))
13246 (const_int 0)))
13247 (set (match_operand:SI 0 "gpc_reg_operand" "")
13248 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13249 "TARGET_POWER && reload_completed"
13250 [(set (match_dup 0)
13251 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13252 (set (match_dup 4)
13253 (compare:CC (match_dup 0)
13254 (const_int 0)))]
13255 "")
13257 (define_insn ""
13258 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13259 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13260 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13261 "TARGET_POWER"
13262 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13263 [(set_attr "length" "12")])
13265 (define_insn "*geu<mode>"
13266 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13267 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13268 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13269 ""
13270 "@
13271 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13272 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13273 [(set_attr "type" "three")
13274 (set_attr "length" "12")])
13276 (define_insn "*geu<mode>_compare"
13277 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13278 (compare:CC
13279 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13280 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13281 (const_int 0)))
13282 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13283 (geu:P (match_dup 1) (match_dup 2)))]
13284 ""
13285 "@
13286 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13287 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13288 #
13289 #"
13290 [(set_attr "type" "compare")
13291 (set_attr "length" "12,12,16,16")])
13293 (define_split
13294 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13295 (compare:CC
13296 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13297 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13298 (const_int 0)))
13299 (set (match_operand:P 0 "gpc_reg_operand" "")
13300 (geu:P (match_dup 1) (match_dup 2)))]
13301 "reload_completed"
13302 [(set (match_dup 0)
13303 (geu:P (match_dup 1) (match_dup 2)))
13304 (set (match_dup 3)
13305 (compare:CC (match_dup 0)
13306 (const_int 0)))]
13307 "")
13309 (define_insn "*plus_geu<mode>"
13310 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13311 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13312 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13313 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13314 ""
13315 "@
13316 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13317 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13318 [(set_attr "type" "two")
13319 (set_attr "length" "8")])
13321 (define_insn ""
13322 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13323 (compare:CC
13324 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13325 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13326 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13327 (const_int 0)))
13328 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13329 "TARGET_32BIT"
13330 "@
13331 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13332 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13333 #
13334 #"
13335 [(set_attr "type" "compare")
13336 (set_attr "length" "8,8,12,12")])
13338 (define_split
13339 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13340 (compare:CC
13341 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13342 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13343 (match_operand:SI 3 "gpc_reg_operand" ""))
13344 (const_int 0)))
13345 (clobber (match_scratch:SI 4 ""))]
13346 "TARGET_32BIT && reload_completed"
13347 [(set (match_dup 4)
13348 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13349 (match_dup 3)))
13350 (set (match_dup 0)
13351 (compare:CC (match_dup 4)
13352 (const_int 0)))]
13353 "")
13355 (define_insn ""
13356 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13357 (compare:CC
13358 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13359 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13360 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13361 (const_int 0)))
13362 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13363 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13364 "TARGET_32BIT"
13365 "@
13366 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13367 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13368 #
13369 #"
13370 [(set_attr "type" "compare")
13371 (set_attr "length" "8,8,12,12")])
13373 (define_split
13374 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13375 (compare:CC
13376 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13377 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13378 (match_operand:SI 3 "gpc_reg_operand" ""))
13379 (const_int 0)))
13380 (set (match_operand:SI 0 "gpc_reg_operand" "")
13381 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13382 "TARGET_32BIT && reload_completed"
13383 [(set (match_dup 0)
13384 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13385 (set (match_dup 4)
13386 (compare:CC (match_dup 0)
13387 (const_int 0)))]
13388 "")
13390 (define_insn "*neg_geu<mode>"
13391 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13392 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13393 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13394 ""
13395 "@
13396 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13397 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13398 [(set_attr "type" "three")
13399 (set_attr "length" "12")])
13401 (define_insn "*and_neg_geu<mode>"
13402 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13403 (and:P (neg:P
13404 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13405 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13406 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13407 ""
13408 "@
13409 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13410 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13411 [(set_attr "type" "three")
13412 (set_attr "length" "12")])
13414 (define_insn ""
13415 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13416 (compare:CC
13417 (and:SI (neg:SI
13418 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13419 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13420 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13421 (const_int 0)))
13422 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13423 "TARGET_32BIT"
13424 "@
13425 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13426 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13427 #
13428 #"
13429 [(set_attr "type" "compare")
13430 (set_attr "length" "12,12,16,16")])
13432 (define_split
13433 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13434 (compare:CC
13435 (and:SI (neg:SI
13436 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13437 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13438 (match_operand:SI 3 "gpc_reg_operand" ""))
13439 (const_int 0)))
13440 (clobber (match_scratch:SI 4 ""))]
13441 "TARGET_32BIT && reload_completed"
13442 [(set (match_dup 4)
13443 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13444 (match_dup 3)))
13445 (set (match_dup 0)
13446 (compare:CC (match_dup 4)
13447 (const_int 0)))]
13448 "")
13450 (define_insn ""
13451 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13452 (compare:CC
13453 (and:SI (neg:SI
13454 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13455 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13456 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13457 (const_int 0)))
13458 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13459 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13460 "TARGET_32BIT"
13461 "@
13462 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13463 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13464 #
13465 #"
13466 [(set_attr "type" "compare")
13467 (set_attr "length" "12,12,16,16")])
13469 (define_split
13470 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13471 (compare:CC
13472 (and:SI (neg:SI
13473 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13474 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13475 (match_operand:SI 3 "gpc_reg_operand" ""))
13476 (const_int 0)))
13477 (set (match_operand:SI 0 "gpc_reg_operand" "")
13478 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13479 "TARGET_32BIT && reload_completed"
13480 [(set (match_dup 0)
13481 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13482 (set (match_dup 4)
13483 (compare:CC (match_dup 0)
13484 (const_int 0)))]
13485 "")
13487 (define_insn ""
13488 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13489 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13490 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13491 "TARGET_POWER"
13492 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13493 [(set_attr "length" "12")])
13495 (define_insn ""
13496 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13497 (compare:CC
13498 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13499 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13500 (const_int 0)))
13501 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13502 (gt:SI (match_dup 1) (match_dup 2)))]
13503 "TARGET_POWER"
13504 "@
13505 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13506 #"
13507 [(set_attr "type" "delayed_compare")
13508 (set_attr "length" "12,16")])
13510 (define_split
13511 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13512 (compare:CC
13513 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13514 (match_operand:SI 2 "reg_or_short_operand" ""))
13515 (const_int 0)))
13516 (set (match_operand:SI 0 "gpc_reg_operand" "")
13517 (gt:SI (match_dup 1) (match_dup 2)))]
13518 "TARGET_POWER && reload_completed"
13519 [(set (match_dup 0)
13520 (gt:SI (match_dup 1) (match_dup 2)))
13521 (set (match_dup 3)
13522 (compare:CC (match_dup 0)
13523 (const_int 0)))]
13524 "")
13526 (define_insn "*plus_gt0<mode>"
13527 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13528 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13529 (const_int 0))
13530 (match_operand:P 2 "gpc_reg_operand" "r")))]
13531 ""
13532 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13533 [(set_attr "type" "three")
13534 (set_attr "length" "12")])
13536 (define_insn ""
13537 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13538 (compare:CC
13539 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13540 (const_int 0))
13541 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13542 (const_int 0)))
13543 (clobber (match_scratch:SI 3 "=&r,&r"))]
13544 "TARGET_32BIT"
13545 "@
13546 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13547 #"
13548 [(set_attr "type" "compare")
13549 (set_attr "length" "12,16")])
13551 (define_split
13552 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13553 (compare:CC
13554 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13555 (const_int 0))
13556 (match_operand:SI 2 "gpc_reg_operand" ""))
13557 (const_int 0)))
13558 (clobber (match_scratch:SI 3 ""))]
13559 "TARGET_32BIT && reload_completed"
13560 [(set (match_dup 3)
13561 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13562 (match_dup 2)))
13563 (set (match_dup 0)
13564 (compare:CC (match_dup 3)
13565 (const_int 0)))]
13566 "")
13568 (define_insn ""
13569 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13570 (compare:CC
13571 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13572 (const_int 0))
13573 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13574 (const_int 0)))
13575 (clobber (match_scratch:DI 3 "=&r,&r"))]
13576 "TARGET_64BIT"
13577 "@
13578 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13579 #"
13580 [(set_attr "type" "compare")
13581 (set_attr "length" "12,16")])
13583 (define_split
13584 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13585 (compare:CC
13586 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13587 (const_int 0))
13588 (match_operand:DI 2 "gpc_reg_operand" ""))
13589 (const_int 0)))
13590 (clobber (match_scratch:DI 3 ""))]
13591 "TARGET_64BIT && reload_completed"
13592 [(set (match_dup 3)
13593 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13594 (match_dup 2)))
13595 (set (match_dup 0)
13596 (compare:CC (match_dup 3)
13597 (const_int 0)))]
13598 "")
13600 (define_insn ""
13601 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13602 (compare:CC
13603 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13604 (const_int 0))
13605 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13606 (const_int 0)))
13607 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13608 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13609 "TARGET_32BIT"
13610 "@
13611 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13612 #"
13613 [(set_attr "type" "compare")
13614 (set_attr "length" "12,16")])
13616 (define_split
13617 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13618 (compare:CC
13619 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13620 (const_int 0))
13621 (match_operand:SI 2 "gpc_reg_operand" ""))
13622 (const_int 0)))
13623 (set (match_operand:SI 0 "gpc_reg_operand" "")
13624 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13625 "TARGET_32BIT && reload_completed"
13626 [(set (match_dup 0)
13627 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13628 (set (match_dup 3)
13629 (compare:CC (match_dup 0)
13630 (const_int 0)))]
13631 "")
13633 (define_insn ""
13634 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13635 (compare:CC
13636 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13637 (const_int 0))
13638 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13639 (const_int 0)))
13640 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13641 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13642 "TARGET_64BIT"
13643 "@
13644 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13645 #"
13646 [(set_attr "type" "compare")
13647 (set_attr "length" "12,16")])
13649 (define_split
13650 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13651 (compare:CC
13652 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13653 (const_int 0))
13654 (match_operand:DI 2 "gpc_reg_operand" ""))
13655 (const_int 0)))
13656 (set (match_operand:DI 0 "gpc_reg_operand" "")
13657 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13658 "TARGET_64BIT && reload_completed"
13659 [(set (match_dup 0)
13660 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13661 (set (match_dup 3)
13662 (compare:CC (match_dup 0)
13663 (const_int 0)))]
13664 "")
13666 (define_insn ""
13667 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13668 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13669 (match_operand:SI 2 "reg_or_short_operand" "r"))
13670 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13671 "TARGET_POWER"
13672 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13673 [(set_attr "length" "12")])
13675 (define_insn ""
13676 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13677 (compare:CC
13678 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13679 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13680 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13681 (const_int 0)))
13682 (clobber (match_scratch:SI 4 "=&r,&r"))]
13683 "TARGET_POWER"
13684 "@
13685 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13686 #"
13687 [(set_attr "type" "compare")
13688 (set_attr "length" "12,16")])
13690 (define_split
13691 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13692 (compare:CC
13693 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13694 (match_operand:SI 2 "reg_or_short_operand" ""))
13695 (match_operand:SI 3 "gpc_reg_operand" ""))
13696 (const_int 0)))
13697 (clobber (match_scratch:SI 4 ""))]
13698 "TARGET_POWER && reload_completed"
13699 [(set (match_dup 4)
13700 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13701 (set (match_dup 0)
13702 (compare:CC (match_dup 4)
13703 (const_int 0)))]
13704 "")
13706 (define_insn ""
13707 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13708 (compare:CC
13709 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13710 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13711 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13712 (const_int 0)))
13713 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13714 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13715 "TARGET_POWER"
13716 "@
13717 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13718 #"
13719 [(set_attr "type" "compare")
13720 (set_attr "length" "12,16")])
13722 (define_split
13723 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13724 (compare:CC
13725 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13726 (match_operand:SI 2 "reg_or_short_operand" ""))
13727 (match_operand:SI 3 "gpc_reg_operand" ""))
13728 (const_int 0)))
13729 (set (match_operand:SI 0 "gpc_reg_operand" "")
13730 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13731 "TARGET_POWER && reload_completed"
13732 [(set (match_dup 0)
13733 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13734 (set (match_dup 4)
13735 (compare:CC (match_dup 0)
13736 (const_int 0)))]
13737 "")
13739 (define_insn ""
13740 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13741 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13742 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13743 "TARGET_POWER"
13744 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13745 [(set_attr "length" "12")])
13747 (define_insn_and_split "*gtu<mode>"
13748 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13749 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13750 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13751 ""
13752 "#"
13753 ""
13754 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13755 (set (match_dup 0) (neg:P (match_dup 0)))]
13756 "")
13758 (define_insn_and_split "*gtu<mode>_compare"
13759 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13760 (compare:CC
13761 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13762 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13763 (const_int 0)))
13764 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13765 (gtu:P (match_dup 1) (match_dup 2)))]
13766 ""
13767 "#"
13768 ""
13769 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13770 (parallel [(set (match_dup 3)
13771 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13772 (set (match_dup 0) (neg:P (match_dup 0)))])]
13773 "")
13775 (define_insn_and_split "*plus_gtu<mode>"
13776 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13777 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13778 (match_operand:P 2 "reg_or_short_operand" "rI"))
13779 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13780 ""
13781 "#"
13782 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13783 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13784 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13785 "")
13787 (define_insn_and_split "*plus_gtu<mode>_compare"
13788 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13789 (compare:CC
13790 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13791 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13792 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13793 (const_int 0)))
13794 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13795 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13796 ""
13797 "#"
13798 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13799 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13800 (parallel [(set (match_dup 4)
13801 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13802 (const_int 0)))
13803 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13804 "")
13806 (define_insn "*neg_gtu<mode>"
13807 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13808 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13809 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13810 ""
13811 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13812 [(set_attr "type" "two")
13813 (set_attr "length" "8")])
13815 \f
13816 ;; Define both directions of branch and return. If we need a reload
13817 ;; register, we'd rather use CR0 since it is much easier to copy a
13818 ;; register CC value to there.
13820 (define_insn ""
13821 [(set (pc)
13822 (if_then_else (match_operator 1 "branch_comparison_operator"
13823 [(match_operand 2
13824 "cc_reg_operand" "y")
13825 (const_int 0)])
13826 (label_ref (match_operand 0 "" ""))
13827 (pc)))]
13828 ""
13829 "*
13830 {
13831 return output_cbranch (operands[1], \"%l0\", 0, insn);
13832 }"
13833 [(set_attr "type" "branch")])
13835 (define_insn ""
13836 [(set (pc)
13837 (if_then_else (match_operator 0 "branch_comparison_operator"
13838 [(match_operand 1
13839 "cc_reg_operand" "y")
13840 (const_int 0)])
13841 (return)
13842 (pc)))]
13843 "direct_return ()"
13844 "*
13845 {
13846 return output_cbranch (operands[0], NULL, 0, insn);
13847 }"
13848 [(set_attr "type" "jmpreg")
13849 (set_attr "length" "4")])
13851 (define_insn ""
13852 [(set (pc)
13853 (if_then_else (match_operator 1 "branch_comparison_operator"
13854 [(match_operand 2
13855 "cc_reg_operand" "y")
13856 (const_int 0)])
13857 (pc)
13858 (label_ref (match_operand 0 "" ""))))]
13859 ""
13860 "*
13861 {
13862 return output_cbranch (operands[1], \"%l0\", 1, insn);
13863 }"
13864 [(set_attr "type" "branch")])
13866 (define_insn ""
13867 [(set (pc)
13868 (if_then_else (match_operator 0 "branch_comparison_operator"
13869 [(match_operand 1
13870 "cc_reg_operand" "y")
13871 (const_int 0)])
13872 (pc)
13873 (return)))]
13874 "direct_return ()"
13875 "*
13876 {
13877 return output_cbranch (operands[0], NULL, 1, insn);
13878 }"
13879 [(set_attr "type" "jmpreg")
13880 (set_attr "length" "4")])
13882 ;; Logic on condition register values.
13884 ; This pattern matches things like
13885 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13886 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13887 ; (const_int 1)))
13888 ; which are generated by the branch logic.
13889 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13891 (define_insn "*cceq_ior_compare"
13892 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13893 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13894 [(match_operator:SI 2
13895 "branch_positive_comparison_operator"
13896 [(match_operand 3
13897 "cc_reg_operand" "y,y")
13898 (const_int 0)])
13899 (match_operator:SI 4
13900 "branch_positive_comparison_operator"
13901 [(match_operand 5
13902 "cc_reg_operand" "0,y")
13903 (const_int 0)])])
13904 (const_int 1)))]
13905 ""
13906 "cr%q1 %E0,%j2,%j4"
13907 [(set_attr "type" "cr_logical,delayed_cr")])
13909 ; Why is the constant -1 here, but 1 in the previous pattern?
13910 ; Because ~1 has all but the low bit set.
13911 (define_insn ""
13912 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13913 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13914 [(not:SI (match_operator:SI 2
13915 "branch_positive_comparison_operator"
13916 [(match_operand 3
13917 "cc_reg_operand" "y,y")
13918 (const_int 0)]))
13919 (match_operator:SI 4
13920 "branch_positive_comparison_operator"
13921 [(match_operand 5
13922 "cc_reg_operand" "0,y")
13923 (const_int 0)])])
13924 (const_int -1)))]
13925 ""
13926 "cr%q1 %E0,%j2,%j4"
13927 [(set_attr "type" "cr_logical,delayed_cr")])
13929 (define_insn "*cceq_rev_compare"
13930 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13931 (compare:CCEQ (match_operator:SI 1
13932 "branch_positive_comparison_operator"
13933 [(match_operand 2
13934 "cc_reg_operand" "0,y")
13935 (const_int 0)])
13936 (const_int 0)))]
13937 ""
13938 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13939 [(set_attr "type" "cr_logical,delayed_cr")])
13941 ;; If we are comparing the result of two comparisons, this can be done
13942 ;; using creqv or crxor.
13944 (define_insn_and_split ""
13945 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13946 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13947 [(match_operand 2 "cc_reg_operand" "y")
13948 (const_int 0)])
13949 (match_operator 3 "branch_comparison_operator"
13950 [(match_operand 4 "cc_reg_operand" "y")
13951 (const_int 0)])))]
13952 ""
13953 "#"
13954 ""
13955 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13956 (match_dup 5)))]
13957 "
13958 {
13959 int positive_1, positive_2;
13961 positive_1 = branch_positive_comparison_operator (operands[1],
13962 GET_MODE (operands[1]));
13963 positive_2 = branch_positive_comparison_operator (operands[3],
13964 GET_MODE (operands[3]));
13966 if (! positive_1)
13967 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13968 GET_CODE (operands[1])),
13969 SImode,
13970 operands[2], const0_rtx);
13971 else if (GET_MODE (operands[1]) != SImode)
13972 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13973 operands[2], const0_rtx);
13975 if (! positive_2)
13976 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13977 GET_CODE (operands[3])),
13978 SImode,
13979 operands[4], const0_rtx);
13980 else if (GET_MODE (operands[3]) != SImode)
13981 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13982 operands[4], const0_rtx);
13984 if (positive_1 == positive_2)
13985 {
13986 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13987 operands[5] = constm1_rtx;
13988 }
13989 else
13990 {
13991 operands[5] = const1_rtx;
13992 }
13993 }")
13995 ;; Unconditional branch and return.
13997 (define_insn "jump"
13998 [(set (pc)
13999 (label_ref (match_operand 0 "" "")))]
14000 ""
14001 "b %l0"
14002 [(set_attr "type" "branch")])
14004 (define_insn "return"
14005 [(return)]
14006 "direct_return ()"
14007 "{br|blr}"
14008 [(set_attr "type" "jmpreg")])
14010 (define_expand "indirect_jump"
14011 [(set (pc) (match_operand 0 "register_operand" ""))])
14013 (define_insn "*indirect_jump<mode>"
14014 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14015 ""
14016 "@
14017 bctr
14018 {br|blr}"
14019 [(set_attr "type" "jmpreg")])
14021 ;; Table jump for switch statements:
14022 (define_expand "tablejump"
14023 [(use (match_operand 0 "" ""))
14024 (use (label_ref (match_operand 1 "" "")))]
14025 ""
14026 "
14027 {
14028 if (TARGET_32BIT)
14029 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14030 else
14031 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14032 DONE;
14033 }")
14035 (define_expand "tablejumpsi"
14036 [(set (match_dup 3)
14037 (plus:SI (match_operand:SI 0 "" "")
14038 (match_dup 2)))
14039 (parallel [(set (pc) (match_dup 3))
14040 (use (label_ref (match_operand 1 "" "")))])]
14041 "TARGET_32BIT"
14042 "
14043 { operands[0] = force_reg (SImode, operands[0]);
14044 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14045 operands[3] = gen_reg_rtx (SImode);
14046 }")
14048 (define_expand "tablejumpdi"
14049 [(set (match_dup 4)
14050 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14051 (set (match_dup 3)
14052 (plus:DI (match_dup 4)
14053 (match_dup 2)))
14054 (parallel [(set (pc) (match_dup 3))
14055 (use (label_ref (match_operand 1 "" "")))])]
14056 "TARGET_64BIT"
14057 "
14058 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14059 operands[3] = gen_reg_rtx (DImode);
14060 operands[4] = gen_reg_rtx (DImode);
14061 }")
14063 (define_insn "*tablejump<mode>_internal1"
14064 [(set (pc)
14065 (match_operand:P 0 "register_operand" "c,*l"))
14066 (use (label_ref (match_operand 1 "" "")))]
14067 ""
14068 "@
14069 bctr
14070 {br|blr}"
14071 [(set_attr "type" "jmpreg")])
14073 (define_insn "nop"
14074 [(const_int 0)]
14075 ""
14076 "{cror 0,0,0|nop}")
14077 \f
14078 ;; Define the subtract-one-and-jump insns, starting with the template
14079 ;; so loop.c knows what to generate.
14081 (define_expand "doloop_end"
14082 [(use (match_operand 0 "" "")) ; loop pseudo
14083 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14084 (use (match_operand 2 "" "")) ; max iterations
14085 (use (match_operand 3 "" "")) ; loop level
14086 (use (match_operand 4 "" ""))] ; label
14087 ""
14088 "
14089 {
14090 /* Only use this on innermost loops. */
14091 if (INTVAL (operands[3]) > 1)
14092 FAIL;
14093 if (TARGET_64BIT)
14094 {
14095 if (GET_MODE (operands[0]) != DImode)
14096 FAIL;
14097 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14098 }
14099 else
14100 {
14101 if (GET_MODE (operands[0]) != SImode)
14102 FAIL;
14103 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14104 }
14105 DONE;
14106 }")
14108 (define_expand "ctr<mode>"
14109 [(parallel [(set (pc)
14110 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14111 (const_int 1))
14112 (label_ref (match_operand 1 "" ""))
14113 (pc)))
14114 (set (match_dup 0)
14115 (plus:P (match_dup 0)
14116 (const_int -1)))
14117 (clobber (match_scratch:CC 2 ""))
14118 (clobber (match_scratch:P 3 ""))])]
14119 ""
14120 "")
14122 ;; We need to be able to do this for any operand, including MEM, or we
14123 ;; will cause reload to blow up since we don't allow output reloads on
14124 ;; JUMP_INSNs.
14125 ;; For the length attribute to be calculated correctly, the
14126 ;; label MUST be operand 0.
14128 (define_insn "*ctr<mode>_internal1"
14129 [(set (pc)
14130 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14131 (const_int 1))
14132 (label_ref (match_operand 0 "" ""))
14133 (pc)))
14134 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14135 (plus:P (match_dup 1)
14136 (const_int -1)))
14137 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14138 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14139 ""
14140 "*
14141 {
14142 if (which_alternative != 0)
14143 return \"#\";
14144 else if (get_attr_length (insn) == 4)
14145 return \"{bdn|bdnz} %l0\";
14146 else
14147 return \"bdz $+8\;b %l0\";
14148 }"
14149 [(set_attr "type" "branch")
14150 (set_attr "length" "*,12,16,16")])
14152 (define_insn "*ctr<mode>_internal2"
14153 [(set (pc)
14154 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14155 (const_int 1))
14156 (pc)
14157 (label_ref (match_operand 0 "" ""))))
14158 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14159 (plus:P (match_dup 1)
14160 (const_int -1)))
14161 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14162 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14163 ""
14164 "*
14165 {
14166 if (which_alternative != 0)
14167 return \"#\";
14168 else if (get_attr_length (insn) == 4)
14169 return \"bdz %l0\";
14170 else
14171 return \"{bdn|bdnz} $+8\;b %l0\";
14172 }"
14173 [(set_attr "type" "branch")
14174 (set_attr "length" "*,12,16,16")])
14176 ;; Similar but use EQ
14178 (define_insn "*ctr<mode>_internal5"
14179 [(set (pc)
14180 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14181 (const_int 1))
14182 (label_ref (match_operand 0 "" ""))
14183 (pc)))
14184 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14185 (plus:P (match_dup 1)
14186 (const_int -1)))
14187 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14188 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14189 ""
14190 "*
14191 {
14192 if (which_alternative != 0)
14193 return \"#\";
14194 else if (get_attr_length (insn) == 4)
14195 return \"bdz %l0\";
14196 else
14197 return \"{bdn|bdnz} $+8\;b %l0\";
14198 }"
14199 [(set_attr "type" "branch")
14200 (set_attr "length" "*,12,16,16")])
14202 (define_insn "*ctr<mode>_internal6"
14203 [(set (pc)
14204 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14205 (const_int 1))
14206 (pc)
14207 (label_ref (match_operand 0 "" ""))))
14208 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14209 (plus:P (match_dup 1)
14210 (const_int -1)))
14211 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14212 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14213 ""
14214 "*
14215 {
14216 if (which_alternative != 0)
14217 return \"#\";
14218 else if (get_attr_length (insn) == 4)
14219 return \"{bdn|bdnz} %l0\";
14220 else
14221 return \"bdz $+8\;b %l0\";
14222 }"
14223 [(set_attr "type" "branch")
14224 (set_attr "length" "*,12,16,16")])
14226 ;; Now the splitters if we could not allocate the CTR register
14228 (define_split
14229 [(set (pc)
14230 (if_then_else (match_operator 2 "comparison_operator"
14231 [(match_operand:P 1 "gpc_reg_operand" "")
14232 (const_int 1)])
14233 (match_operand 5 "" "")
14234 (match_operand 6 "" "")))
14235 (set (match_operand:P 0 "gpc_reg_operand" "")
14236 (plus:P (match_dup 1) (const_int -1)))
14237 (clobber (match_scratch:CC 3 ""))
14238 (clobber (match_scratch:P 4 ""))]
14239 "reload_completed"
14240 [(parallel [(set (match_dup 3)
14241 (compare:CC (plus:P (match_dup 1)
14242 (const_int -1))
14243 (const_int 0)))
14244 (set (match_dup 0)
14245 (plus:P (match_dup 1)
14246 (const_int -1)))])
14247 (set (pc) (if_then_else (match_dup 7)
14248 (match_dup 5)
14249 (match_dup 6)))]
14250 "
14251 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14252 operands[3], const0_rtx); }")
14254 (define_split
14255 [(set (pc)
14256 (if_then_else (match_operator 2 "comparison_operator"
14257 [(match_operand:P 1 "gpc_reg_operand" "")
14258 (const_int 1)])
14259 (match_operand 5 "" "")
14260 (match_operand 6 "" "")))
14261 (set (match_operand:P 0 "nonimmediate_operand" "")
14262 (plus:P (match_dup 1) (const_int -1)))
14263 (clobber (match_scratch:CC 3 ""))
14264 (clobber (match_scratch:P 4 ""))]
14265 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14266 [(parallel [(set (match_dup 3)
14267 (compare:CC (plus:P (match_dup 1)
14268 (const_int -1))
14269 (const_int 0)))
14270 (set (match_dup 4)
14271 (plus:P (match_dup 1)
14272 (const_int -1)))])
14273 (set (match_dup 0)
14274 (match_dup 4))
14275 (set (pc) (if_then_else (match_dup 7)
14276 (match_dup 5)
14277 (match_dup 6)))]
14278 "
14279 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14280 operands[3], const0_rtx); }")
14281 \f
14282 (define_insn "trap"
14283 [(trap_if (const_int 1) (const_int 0))]
14284 ""
14285 "{t 31,0,0|trap}"
14286 [(set_attr "type" "trap")])
14288 (define_expand "conditional_trap"
14289 [(trap_if (match_operator 0 "trap_comparison_operator"
14290 [(match_dup 2) (match_dup 3)])
14291 (match_operand 1 "const_int_operand" ""))]
14292 ""
14293 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14294 operands[2] = rs6000_compare_op0;
14295 operands[3] = rs6000_compare_op1;")
14297 (define_insn ""
14298 [(trap_if (match_operator 0 "trap_comparison_operator"
14299 [(match_operand:GPR 1 "register_operand" "r")
14300 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14301 (const_int 0))]
14302 ""
14303 "{t|t<wd>}%V0%I2 %1,%2"
14304 [(set_attr "type" "trap")])
14305 \f
14306 ;; Insns related to generating the function prologue and epilogue.
14308 (define_expand "prologue"
14309 [(use (const_int 0))]
14310 "TARGET_SCHED_PROLOG"
14311 "
14312 {
14313 rs6000_emit_prologue ();
14314 DONE;
14315 }")
14317 (define_insn "*movesi_from_cr_one"
14318 [(match_parallel 0 "mfcr_operation"
14319 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14320 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14321 (match_operand 3 "immediate_operand" "n")]
14322 UNSPEC_MOVESI_FROM_CR))])]
14323 "TARGET_MFCRF"
14324 "*
14325 {
14326 int mask = 0;
14327 int i;
14328 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14329 {
14330 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14331 operands[4] = GEN_INT (mask);
14332 output_asm_insn (\"mfcr %1,%4\", operands);
14333 }
14334 return \"\";
14335 }"
14336 [(set_attr "type" "mfcrf")])
14338 (define_insn "movesi_from_cr"
14339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14340 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14341 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14342 UNSPEC_MOVESI_FROM_CR))]
14343 ""
14344 "mfcr %0"
14345 [(set_attr "type" "mfcr")])
14347 (define_insn "*stmw"
14348 [(match_parallel 0 "stmw_operation"
14349 [(set (match_operand:SI 1 "memory_operand" "=m")
14350 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14351 "TARGET_MULTIPLE"
14352 "{stm|stmw} %2,%1"
14353 [(set_attr "type" "store_ux")])
14355 (define_insn "*save_fpregs_<mode>"
14356 [(match_parallel 0 "any_parallel_operand"
14357 [(clobber (match_operand:P 1 "register_operand" "=l"))
14358 (use (match_operand:P 2 "call_operand" "s"))
14359 (set (match_operand:DF 3 "memory_operand" "=m")
14360 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14361 ""
14362 "bl %z2"
14363 [(set_attr "type" "branch")
14364 (set_attr "length" "4")])
14366 ; These are to explain that changes to the stack pointer should
14367 ; not be moved over stores to stack memory.
14368 (define_insn "stack_tie"
14369 [(set (match_operand:BLK 0 "memory_operand" "+m")
14370 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14371 ""
14372 ""
14373 [(set_attr "length" "0")])
14376 (define_expand "epilogue"
14377 [(use (const_int 0))]
14378 "TARGET_SCHED_PROLOG"
14379 "
14380 {
14381 rs6000_emit_epilogue (FALSE);
14382 DONE;
14383 }")
14385 ; On some processors, doing the mtcrf one CC register at a time is
14386 ; faster (like on the 604e). On others, doing them all at once is
14387 ; faster; for instance, on the 601 and 750.
14389 (define_expand "movsi_to_cr_one"
14390 [(set (match_operand:CC 0 "cc_reg_operand" "")
14391 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14392 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14393 ""
14394 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14396 (define_insn "*movsi_to_cr"
14397 [(match_parallel 0 "mtcrf_operation"
14398 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14399 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14400 (match_operand 3 "immediate_operand" "n")]
14401 UNSPEC_MOVESI_TO_CR))])]
14402 ""
14403 "*
14404 {
14405 int mask = 0;
14406 int i;
14407 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14408 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14409 operands[4] = GEN_INT (mask);
14410 return \"mtcrf %4,%2\";
14411 }"
14412 [(set_attr "type" "mtcr")])
14414 (define_insn "*mtcrfsi"
14415 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14416 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14417 (match_operand 2 "immediate_operand" "n")]
14418 UNSPEC_MOVESI_TO_CR))]
14419 "GET_CODE (operands[0]) == REG
14420 && CR_REGNO_P (REGNO (operands[0]))
14421 && GET_CODE (operands[2]) == CONST_INT
14422 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14423 "mtcrf %R0,%1"
14424 [(set_attr "type" "mtcr")])
14426 ; The load-multiple instructions have similar properties.
14427 ; Note that "load_multiple" is a name known to the machine-independent
14428 ; code that actually corresponds to the PowerPC load-string.
14430 (define_insn "*lmw"
14431 [(match_parallel 0 "lmw_operation"
14432 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14433 (match_operand:SI 2 "memory_operand" "m"))])]
14434 "TARGET_MULTIPLE"
14435 "{lm|lmw} %1,%2"
14436 [(set_attr "type" "load_ux")])
14438 (define_insn "*return_internal_<mode>"
14439 [(return)
14440 (use (match_operand:P 0 "register_operand" "lc"))]
14441 ""
14442 "b%T0"
14443 [(set_attr "type" "jmpreg")])
14445 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14446 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14448 (define_insn "*return_and_restore_fpregs_<mode>"
14449 [(match_parallel 0 "any_parallel_operand"
14450 [(return)
14451 (use (match_operand:P 1 "register_operand" "l"))
14452 (use (match_operand:P 2 "call_operand" "s"))
14453 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14454 (match_operand:DF 4 "memory_operand" "m"))])]
14455 ""
14456 "b %z2")
14458 ; This is used in compiling the unwind routines.
14459 (define_expand "eh_return"
14460 [(use (match_operand 0 "general_operand" ""))]
14461 ""
14462 "
14463 {
14464 if (TARGET_32BIT)
14465 emit_insn (gen_eh_set_lr_si (operands[0]));
14466 else
14467 emit_insn (gen_eh_set_lr_di (operands[0]));
14468 DONE;
14469 }")
14471 ; We can't expand this before we know where the link register is stored.
14472 (define_insn "eh_set_lr_<mode>"
14473 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14474 UNSPECV_EH_RR)
14475 (clobber (match_scratch:P 1 "=&b"))]
14476 ""
14477 "#")
14479 (define_split
14480 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14481 (clobber (match_scratch 1 ""))]
14482 "reload_completed"
14483 [(const_int 0)]
14484 "
14485 {
14486 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14487 DONE;
14488 }")
14490 (define_insn "prefetch"
14491 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14492 (match_operand:SI 1 "const_int_operand" "n")
14493 (match_operand:SI 2 "const_int_operand" "n"))]
14494 "TARGET_POWERPC"
14495 "*
14496 {
14497 if (GET_CODE (operands[0]) == REG)
14498 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14499 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14500 }"
14501 [(set_attr "type" "load")])
14502 \f
14504 (include "sync.md")
14505 (include "altivec.md")
14506 (include "spe.md")