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Allow netbsd target to also set structure size boundary
[official-gcc.git] / gcc / config / arm / arm.h
blob0c8c697bfbb3b0a28b70123f80a1edc0bff96987
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #ifndef __ARM_H__
26 #define __ARM_H__
27
28 #define TARGET_CPU_arm2 0x0000
29 #define TARGET_CPU_arm250 0x0000
30 #define TARGET_CPU_arm3 0x0000
31 #define TARGET_CPU_arm6 0x0001
32 #define TARGET_CPU_arm600 0x0001
33 #define TARGET_CPU_arm610 0x0002
34 #define TARGET_CPU_arm7 0x0001
35 #define TARGET_CPU_arm7m 0x0004
36 #define TARGET_CPU_arm7dm 0x0004
37 #define TARGET_CPU_arm7dmi 0x0004
38 #define TARGET_CPU_arm700 0x0001
39 #define TARGET_CPU_arm710 0x0002
40 #define TARGET_CPU_arm7100 0x0002
41 #define TARGET_CPU_arm7500 0x0002
42 #define TARGET_CPU_arm7500fe 0x1001
43 #define TARGET_CPU_arm7tdmi 0x0008
44 #define TARGET_CPU_arm8 0x0010
45 #define TARGET_CPU_arm810 0x0020
46 #define TARGET_CPU_strongarm 0x0040
47 #define TARGET_CPU_strongarm110 0x0040
48 #define TARGET_CPU_strongarm1100 0x0040
49 #define TARGET_CPU_arm9 0x0080
50 #define TARGET_CPU_arm9tdmi 0x0080
51 /* Configure didn't specify */
52 #define TARGET_CPU_generic 0x8000
53
54 enum arm_cond_code
55 {
56 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
57 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
58 };
59
60 extern enum arm_cond_code arm_current_cc;
61 extern char * arm_condition_codes[];
62
63 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
64
65 extern int arm_target_label;
66 extern int arm_ccfsm_state;
67 extern struct rtx_def * arm_target_insn;
68 extern int lr_save_eliminated;
69 /* This is needed by the tail-calling peepholes */
70 extern int frame_pointer_needed;
71 /* Run-time compilation parameters selecting different hardware subsets. */
72 extern int target_flags;
73 /* The floating point instruction architecture, can be 2 or 3 */
74 extern const char * target_fp_name;
75
76 \f
77 /* Just in case configure has failed to define anything. */
78 #ifndef TARGET_CPU_DEFAULT
79 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
80 #endif
81
82 /* If the configuration file doesn't specify the cpu, the subtarget may
83 override it. If it doesn't, then default to an ARM6. */
84 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
85 #undef TARGET_CPU_DEFAULT
86 #ifdef SUBTARGET_CPU_DEFAULT
87 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
88 #else
89 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
90 #endif
91 #endif
92
93 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
94 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
95 #else
96 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
97 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
98 #else
99 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
100 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
101 #else
102 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9
103 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
104 #else
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
107 #else
108 Unrecognized value in TARGET_CPU_DEFAULT.
109 #endif
110 #endif
111 #endif
112 #endif
113 #endif
114
115 #ifndef CPP_PREDEFINES
116 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
117 #endif
118
119 #define CPP_SPEC "\
120 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
121 %(cpp_endian) %(subtarget_cpp_spec)"
122
123 /* Set the architecture define -- if -march= is set, then it overrides
124 the -mcpu= setting. */
125 #define CPP_CPU_ARCH_SPEC "\
126 %{march=arm2:-D__ARM_ARCH_2__} \
127 %{march=arm250:-D__ARM_ARCH_2__} \
128 %{march=arm3:-D__ARM_ARCH_2__} \
129 %{march=arm6:-D__ARM_ARCH_3__} \
130 %{march=arm600:-D__ARM_ARCH_3__} \
131 %{march=arm610:-D__ARM_ARCH_3__} \
132 %{march=arm7:-D__ARM_ARCH_3__} \
133 %{march=arm700:-D__ARM_ARCH_3__} \
134 %{march=arm710:-D__ARM_ARCH_3__} \
135 %{march=arm7100:-D__ARM_ARCH_3__} \
136 %{march=arm7500:-D__ARM_ARCH_3__} \
137 %{march=arm7500fe:-D__ARM_ARCH_3__} \
138 %{march=arm7m:-D__ARM_ARCH_3M__} \
139 %{march=arm7dm:-D__ARM_ARCH_3M__} \
140 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
141 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
142 %{march=arm8:-D__ARM_ARCH_4__} \
143 %{march=arm810:-D__ARM_ARCH_4__} \
144 %{march=arm9:-D__ARM_ARCH_4T__} \
145 %{march=arm920:-D__ARM_ARCH_4__} \
146 %{march=arm920t:-D__ARM_ARCH_4T__} \
147 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
148 %{march=strongarm:-D__ARM_ARCH_4__} \
149 %{march=strongarm110:-D__ARM_ARCH_4__} \
150 %{march=strongarm1100:-D__ARM_ARCH_4__} \
151 %{march=armv2:-D__ARM_ARCH_2__} \
152 %{march=armv2a:-D__ARM_ARCH_2__} \
153 %{march=armv3:-D__ARM_ARCH_3__} \
154 %{march=armv3m:-D__ARM_ARCH_3M__} \
155 %{march=armv4:-D__ARM_ARCH_4__} \
156 %{march=armv4t:-D__ARM_ARCH_4T__} \
157 %{march=armv5:-D__ARM_ARCH_5__} \
158 %{!march=*: \
159 %{mcpu=arm2:-D__ARM_ARCH_2__} \
160 %{mcpu=arm250:-D__ARM_ARCH_2__} \
161 %{mcpu=arm3:-D__ARM_ARCH_2__} \
162 %{mcpu=arm6:-D__ARM_ARCH_3__} \
163 %{mcpu=arm600:-D__ARM_ARCH_3__} \
164 %{mcpu=arm610:-D__ARM_ARCH_3__} \
165 %{mcpu=arm7:-D__ARM_ARCH_3__} \
166 %{mcpu=arm700:-D__ARM_ARCH_3__} \
167 %{mcpu=arm710:-D__ARM_ARCH_3__} \
168 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
169 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
170 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
171 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
172 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
173 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
174 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
175 %{mcpu=arm8:-D__ARM_ARCH_4__} \
176 %{mcpu=arm810:-D__ARM_ARCH_4__} \
177 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
178 %{mcpu=arm920:-D__ARM_ARCH_4__} \
179 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
180 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
181 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
182 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
183 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
184 %{!mcpu*:%(cpp_cpu_arch_default)}} \
185 "
186
187 /* Define __APCS_26__ if the PC also contains the PSR */
188 #define CPP_APCS_PC_SPEC "\
189 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
190 -D__APCS_32__} \
191 %{mapcs-26:-D__APCS_26__} \
192 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
193 "
194
195 #ifndef CPP_APCS_PC_DEFAULT_SPEC
196 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
197 #endif
198
199 #define CPP_FLOAT_SPEC "\
200 %{msoft-float:\
201 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
202 -D__SOFTFP__} \
203 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
204 "
205
206 /* Default is hard float, which doesn't define anything */
207 #define CPP_FLOAT_DEFAULT_SPEC ""
208
209 #define CPP_ENDIAN_SPEC "\
210 %{mbig-endian: \
211 %{mlittle-endian: \
212 %e-mbig-endian and -mlittle-endian may not be used together} \
213 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
214 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
215 "
216
217 /* Default is little endian, which doesn't define anything. */
218 #define CPP_ENDIAN_DEFAULT_SPEC ""
219
220 #define CC1_SPEC ""
221
222 /* This macro defines names of additional specifications to put in the specs
223 that can be used in various specifications like CC1_SPEC. Its definition
224 is an initializer with a subgrouping for each command option.
225
226 Each subgrouping contains a string constant, that defines the
227 specification name, and a string constant that used by the GNU CC driver
228 program.
229
230 Do not define this macro if it does not need to do anything. */
231 #define EXTRA_SPECS \
232 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
233 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
234 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
235 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
236 { "cpp_float", CPP_FLOAT_SPEC }, \
237 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
238 { "cpp_endian", CPP_ENDIAN_SPEC }, \
239 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
240 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
241 SUBTARGET_EXTRA_SPECS
242
243 #define SUBTARGET_EXTRA_SPECS
244 #ifndef SUBTARGET_CPP_SPEC
245 #define SUBTARGET_CPP_SPEC ""
246 #endif
247
248 \f
249 /* Run-time Target Specification. */
250 #ifndef TARGET_VERSION
251 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
252 #endif
253
254 /* Nonzero if the function prologue (and epilogue) should obey
255 the ARM Procedure Call Standard. */
256 #define ARM_FLAG_APCS_FRAME (1 << 0)
257
258 /* Nonzero if the function prologue should output the function name to enable
259 the post mortem debugger to print a backtrace (very useful on RISCOS,
260 unused on RISCiX). Specifying this flag also enables
261 -fno-omit-frame-pointer.
262 XXX Must still be implemented in the prologue. */
263 #define ARM_FLAG_POKE (1 << 1)
264
265 /* Nonzero if floating point instructions are emulated by the FPE, in which
266 case instruction scheduling becomes very uninteresting. */
267 #define ARM_FLAG_FPE (1 << 2)
268
269 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
270 that assume restoration of the condition flags when returning from a
271 branch and link (ie a function). */
272 #define ARM_FLAG_APCS_32 (1 << 3)
273
274 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
275
276 /* Nonzero if stack checking should be performed on entry to each function
277 which allocates temporary variables on the stack. */
278 #define ARM_FLAG_APCS_STACK (1 << 4)
279
280 /* Nonzero if floating point parameters should be passed to functions in
281 floating point registers. */
282 #define ARM_FLAG_APCS_FLOAT (1 << 5)
283
284 /* Nonzero if re-entrant, position independent code should be generated.
285 This is equivalent to -fpic. */
286 #define ARM_FLAG_APCS_REENT (1 << 6)
287
288 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
289 loaded byte-at-a-time. */
290 #define ARM_FLAG_SHORT_BYTE (1 << 7)
291
292 /* Nonzero if all floating point instructions are missing (and there is no
293 emulator either). Generate function calls for all ops in this case. */
294 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
295
296 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
297 #define ARM_FLAG_BIG_END (1 << 9)
298
299 /* Nonzero if we should compile for Thumb interworking. */
300 #define ARM_FLAG_INTERWORK (1 << 10)
301
302 /* Nonzero if we should have little-endian words even when compiling for
303 big-endian (for backwards compatibility with older versions of GCC). */
304 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
305
306 /* Nonzero if we need to protect the prolog from scheduling */
307 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
308
309 /* Nonzero if a call to abort should be generated if a noreturn
310 function tries to return. */
311 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
312
313 /* Nonzero if function prologues should not load the PIC register. */
314 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
315
316 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
317 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
318 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
319 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
320 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
321 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
322 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
323 /* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
324 that short values should not be accessed using word load instructions
325 as there is a possibility that they may not be word aligned and this
326 would generate an MMU fault. On processors which do not have a 16 bit
327 load instruction therefore, short values must be loaded by individual
328 byte accesses rather than loading a word and then shifting the desired
329 value into place. */
330 #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
331 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
332 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
333 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
334 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
335 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
336 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
337 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
338 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
339
340 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
341 Bit 31 is reserved. See riscix.h. */
342 #ifndef SUBTARGET_SWITCHES
343 #define SUBTARGET_SWITCHES
344 #endif
345
346 #define TARGET_SWITCHES \
347 { \
348 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
349 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
350 "Generate APCS conformant stack frames" }, \
351 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
352 {"poke-function-name", ARM_FLAG_POKE, \
353 "Store function names in object code" }, \
354 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
355 {"fpe", ARM_FLAG_FPE, "" }, \
356 {"apcs-32", ARM_FLAG_APCS_32, \
357 "Use the 32bit version of the APCS" }, \
358 {"apcs-26", -ARM_FLAG_APCS_32, \
359 "Use the 26bit version of the APCS" }, \
360 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
361 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
362 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
363 "Pass FP arguments in FP registers" }, \
364 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
365 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
366 "Generate re-entrant, PIC code" }, \
367 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
368 {"short-load-bytes", ARM_FLAG_SHORT_BYTE, \
369 "Load shorts a byte at a time" }, \
370 {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \
371 {"short-load-words", -ARM_FLAG_SHORT_BYTE, \
372 "Load words a byte at a time" }, \
373 {"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \
374 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
375 "Use library calls to perform FP operations" }, \
376 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
377 "Use hardware floating point instructions" }, \
378 {"big-endian", ARM_FLAG_BIG_END, \
379 "Assume target CPU is configured as big endian" }, \
380 {"little-endian", -ARM_FLAG_BIG_END, \
381 "Assume target CPU is configured as little endian" }, \
382 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
383 "Assume big endian bytes, little endian words" }, \
384 {"thumb-interwork", ARM_FLAG_INTERWORK, \
385 "Support calls between THUMB and ARM instructions sets" }, \
386 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
387 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
388 "Generate a call to abort if a noreturn function returns"}, \
389 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
390 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
391 "Do not move instructions into a function's prologue" }, \
392 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
393 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
394 "Do not load the PIC register in function prologues" }, \
395 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
396 SUBTARGET_SWITCHES \
397 {"", TARGET_DEFAULT, "" } \
398 }
399
400 #define TARGET_OPTIONS \
401 { \
402 {"cpu=", & arm_select[0].string, \
403 "Specify the name of the target CPU" }, \
404 {"arch=", & arm_select[1].string, \
405 "Specify the name of the target architecture" }, \
406 {"tune=", & arm_select[2].string, "" }, \
407 {"fpe=", & target_fp_name, "" }, \
408 {"fp=", & target_fp_name, \
409 "Specify the version of the floating point emulator" }, \
410 { "structure-size-boundary=", & structure_size_string, \
411 "Specify the minumum bit alignment of structures" }, \
412 { "pic-register=", & arm_pic_register_string, \
413 "Specify the register to be used for PIC addressing" } \
414 }
415
416 struct arm_cpu_select
417 {
418 const char * string;
419 const char * name;
420 const struct processors * processors;
421 };
422
423 /* This is a magic array. If the user specifies a command line switch
424 which matches one of the entries in TARGET_OPTIONS then the corresponding
425 string pointer will be set to the value specified by the user. */
426 extern struct arm_cpu_select arm_select[];
427
428 enum prog_mode_type
429 {
430 prog_mode26,
431 prog_mode32
432 };
433
434 /* Recast the program mode class to be the prog_mode attribute */
435 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
436
437 extern enum prog_mode_type arm_prgmode;
438
439 /* What sort of floating point unit do we have? Hardware or software.
440 If software, is it issue 2 or issue 3? */
441 enum floating_point_type
442 {
443 FP_HARD,
444 FP_SOFT2,
445 FP_SOFT3
446 };
447
448 /* Recast the floating point class to be the floating point attribute. */
449 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
450
451 /* What type of floating point to tune for */
452 extern enum floating_point_type arm_fpu;
453
454 /* What type of floating point instructions are available */
455 extern enum floating_point_type arm_fpu_arch;
456
457 /* Default floating point architecture. Override in sub-target if
458 necessary. */
459 #define FP_DEFAULT FP_SOFT2
460
461 /* Nonzero if the processor has a fast multiply insn, and one that does
462 a 64-bit multiply of two 32-bit values. */
463 extern int arm_fast_multiply;
464
465 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
466 extern int arm_arch4;
467
468 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
469 extern int arm_arch5;
470
471 /* Nonzero if this chip can benefit from load scheduling. */
472 extern int arm_ld_sched;
473
474 /* Nonzero if this chip is a StrongARM. */
475 extern int arm_is_strong;
476
477 /* Nonzero if this chip is a an ARM6 or an ARM7. */
478 extern int arm_is_6_or_7;
479
480 #ifndef TARGET_DEFAULT
481 #define TARGET_DEFAULT 0
482 #endif
483
484 /* The frame pointer register used in gcc has nothing to do with debugging;
485 that is controlled by the APCS-FRAME option. */
486 /* Not fully implemented yet */
487 /* #define CAN_DEBUG_WITHOUT_FP 1 */
488
489 #define TARGET_MEM_FUNCTIONS 1
490
491 #define OVERRIDE_OPTIONS arm_override_options ()
492
493 /* Nonzero if PIC code requires explicit qualifiers to generate
494 PLT and GOT relocs rather than the assembler doing so implicitly.
495 Subtargets can override these if required. */
496 #ifndef NEED_GOT_RELOC
497 #define NEED_GOT_RELOC 0
498 #endif
499 #ifndef NEED_PLT_RELOC
500 #define NEED_PLT_RELOC 0
501 #endif
502
503 /* Nonzero if we need to refer to the GOT with a PC-relative
504 offset. In other words, generate
505
506 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
507
508 rather than
509
510 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
511
512 The default is true, which matches NetBSD. Subtargets can
513 override this if required. */
514 #ifndef GOT_PCREL
515 #define GOT_PCREL 1
516 #endif
517 \f
518 /* Target machine storage Layout. */
519
520
521 /* Define this macro if it is advisable to hold scalars in registers
522 in a wider mode than that declared by the program. In such cases,
523 the value is constrained to be within the bounds of the declared
524 type, but kept valid in the wider mode. The signedness of the
525 extension may differ from that of the type. */
526
527 /* It is far faster to zero extend chars than to sign extend them */
528
529 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
530 if (GET_MODE_CLASS (MODE) == MODE_INT \
531 && GET_MODE_SIZE (MODE) < 4) \
532 { \
533 if (MODE == QImode) \
534 UNSIGNEDP = 1; \
535 else if (MODE == HImode) \
536 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
537 (MODE) = SImode; \
538 }
539
540 /* Define this macro if the promotion described by `PROMOTE_MODE'
541 should also be done for outgoing function arguments. */
542 /* This is required to ensure that push insns always push a word. */
543 #define PROMOTE_FUNCTION_ARGS
544
545 /* Define for XFmode extended real floating point support.
546 This will automatically cause REAL_ARITHMETIC to be defined. */
547 /* For the ARM:
548 I think I have added all the code to make this work. Unfortunately,
549 early releases of the floating point emulation code on RISCiX used a
550 different format for extended precision numbers. On my RISCiX box there
551 is a bug somewhere which causes the machine to lock up when running enquire
552 with long doubles. There is the additional aspect that Norcroft C
553 treats long doubles as doubles and we ought to remain compatible.
554 Perhaps someone with an FPA coprocessor and not running RISCiX would like
555 to try this someday. */
556 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
557
558 /* Disable XFmode patterns in md file */
559 #define ENABLE_XF_PATTERNS 0
560
561 /* Define if you don't want extended real, but do want to use the
562 software floating point emulator for REAL_ARITHMETIC and
563 decimal <-> binary conversion. */
564 /* See comment above */
565 #define REAL_ARITHMETIC
566
567 /* Define this if most significant bit is lowest numbered
568 in instructions that operate on numbered bit-fields. */
569 #define BITS_BIG_ENDIAN 0
570
571 /* Define this if most significant byte of a word is the lowest numbered.
572 Most ARM processors are run in little endian mode, so that is the default.
573 If you want to have it run-time selectable, change the definition in a
574 cover file to be TARGET_BIG_ENDIAN. */
575 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
576
577 /* Define this if most significant word of a multiword number is the lowest
578 numbered.
579 This is always false, even when in big-endian mode. */
580 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
581
582 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
583 on processor pre-defineds when compiling libgcc2.c. */
584 #if defined(__ARMEB__) && !defined(__ARMWEL__)
585 #define LIBGCC2_WORDS_BIG_ENDIAN 1
586 #else
587 #define LIBGCC2_WORDS_BIG_ENDIAN 0
588 #endif
589
590 /* Define this if most significant word of doubles is the lowest numbered.
591 This is always true, even when in little-endian mode. */
592 #define FLOAT_WORDS_BIG_ENDIAN 1
593
594 /* Number of bits in an addressable storage unit */
595 #define BITS_PER_UNIT 8
596
597 #define BITS_PER_WORD 32
598
599 #define UNITS_PER_WORD 4
600
601 #define POINTER_SIZE 32
602
603 #define PARM_BOUNDARY 32
604
605 #define STACK_BOUNDARY 32
606
607 #define FUNCTION_BOUNDARY 32
608
609 #define EMPTY_FIELD_BOUNDARY 32
610
611 #define BIGGEST_ALIGNMENT 32
612
613 /* Make strings word-aligned so strcpy from constants will be faster. */
614 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
615 (TREE_CODE (EXP) == STRING_CST \
616 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
617
618 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
619 value set in previous versions of this toolchain was 8, which produces more
620 compact structures. The command line option -mstructure_size_boundary=<n>
621 can be used to change this value. For compatability with the ARM SDK
622 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
623 0020D) page 2-20 says "Structures are aligned on word boundaries". */
624 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
625 extern int arm_structure_size_boundary;
626
627 /* This is the value used to initialise arm_structure_size_boundary. If a
628 particular arm target wants to change the default value it should change
629 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
630 for an example of this. */
631 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
632 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
633 #endif
634
635 /* Used when parsing command line option -mstructure_size_boundary. */
636 extern const char * structure_size_string;
637
638 /* Non-zero if move instructions will actually fail to work
639 when given unaligned data. */
640 #define STRICT_ALIGNMENT 1
641
642 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
643
644 \f
645 /* Standard register usage. */
646
647 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
648 (S - saved over call).
649
650 r0 * argument word/integer result
651 r1-r3 argument word
652
653 r4-r8 S register variable
654 r9 S (rfp) register variable (real frame pointer)
655
656 r10 F S (sl) stack limit (used by -mapcs-stack-check)
657 r11 F S (fp) argument pointer
658 r12 (ip) temp workspace
659 r13 F S (sp) lower end of current stack frame
660 r14 (lr) link address/workspace
661 r15 F (pc) program counter
662
663 f0 floating point result
664 f1-f3 floating point scratch
665
666 f4-f7 S floating point variable
667
668 cc This is NOT a real register, but is used internally
669 to represent things that use or set the condition
670 codes.
671 sfp This isn't either. It is used during rtl generation
672 since the offset between the frame pointer and the
673 auto's isn't known until after register allocation.
674 afp Nor this, we only need this because of non-local
675 goto. Without it fp appears to be used and the
676 elimination code won't get rid of sfp. It tracks
677 fp exactly at all times.
678
679 *: See CONDITIONAL_REGISTER_USAGE */
680
681 /* The stack backtrace structure is as follows:
682 fp points to here: | save code pointer | [fp]
683 | return link value | [fp, #-4]
684 | return sp value | [fp, #-8]
685 | return fp value | [fp, #-12]
686 [| saved r10 value |]
687 [| saved r9 value |]
688 [| saved r8 value |]
689 [| saved r7 value |]
690 [| saved r6 value |]
691 [| saved r5 value |]
692 [| saved r4 value |]
693 [| saved r3 value |]
694 [| saved r2 value |]
695 [| saved r1 value |]
696 [| saved r0 value |]
697 [| saved f7 value |] three words
698 [| saved f6 value |] three words
699 [| saved f5 value |] three words
700 [| saved f4 value |] three words
701 r0-r3 are not normally saved in a C function. */
702
703 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
704 #define FIRST_PSEUDO_REGISTER 27
705
706 /* 1 for registers that have pervasive standard uses
707 and are not available for the register allocator. */
708 #define FIXED_REGISTERS \
709 { \
710 0,0,0,0,0,0,0,0, \
711 0,0,0,1,0,1,0,1, \
712 0,0,0,0,0,0,0,0, \
713 1,1,1 \
714 }
715
716 /* 1 for registers not available across function calls.
717 These must include the FIXED_REGISTERS and also any
718 registers that can be used without being saved.
719 The latter must include the registers where values are returned
720 and the register where structure-value addresses are passed.
721 Aside from that, you can include as many other registers as you like.
722 The CC is not preserved over function calls on the ARM 6, so it is
723 easier to assume this for all. SFP is preserved, since FP is. */
724 #define CALL_USED_REGISTERS \
725 { \
726 1,1,1,1,0,0,0,0, \
727 0,0,0,1,1,1,1,1, \
728 1,1,1,1,0,0,0,0, \
729 1,1,1 \
730 }
731
732 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
733 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
734 #endif
735
736 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
737 trampled. This effectively reduces the number of available registers by 1.
738 XXX It is a hack, I know.
739 XXX Is this still needed? */
740 #define CONDITIONAL_REGISTER_USAGE \
741 { \
742 if (obey_regdecls) \
743 fixed_regs[0] = 1; \
744 if (TARGET_SOFT_FLOAT) \
745 { \
746 int regno; \
747 for (regno = 16; regno < 24; ++regno) \
748 fixed_regs[regno] = call_used_regs[regno] = 1; \
749 } \
750 if (flag_pic) \
751 { \
752 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
753 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
754 } \
755 else if (TARGET_APCS_STACK) \
756 { \
757 fixed_regs[10] = 1; \
758 call_used_regs[10] = 1; \
759 } \
760 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
761 }
762
763 /* These are a couple of extensions to the formats accecpted
764 by asm_fprintf:
765 %@ prints out ASM_COMMENT_START
766 %r prints out REGISTER_PREFIX reg_names[arg] */
767 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
768 case '@': \
769 fputs (ASM_COMMENT_START, FILE); \
770 break; \
771 \
772 case 'r': \
773 fputs (REGISTER_PREFIX, FILE); \
774 fputs (reg_names [va_arg (ARGS, int)], FILE); \
775 break;
776
777 /* Convert fron bytes to ints. */
778 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
779
780 /* The number of (integer) registers required to hold a quantity of type MODE. */
781 #define NUM_REGS(MODE) \
782 NUM_INTS (GET_MODE_SIZE (MODE))
783
784 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
785 #define NUM_REGS2(MODE, TYPE) \
786 NUM_INTS ((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
787
788 /* The number of (integer) argument register available. */
789 #define NUM_ARG_REGS 4
790
791 /* Return the regiser number of the N'th (integer) argument. */
792 #define ARG_REGISTER(N) (N - 1)
793
794 /* The number of the last argument register. */
795 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
796
797 /* Return number of consecutive hard regs needed starting at reg REGNO
798 to hold something of mode MODE.
799 This is ordinarily the length in words of a value of mode MODE
800 but can be less for certain modes in special long registers.
801
802 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
803 mode. */
804 #define HARD_REGNO_NREGS(REGNO, MODE) \
805 (( REGNO >= 16 \
806 && REGNO != FRAME_POINTER_REGNUM \
807 && REGNO != ARG_POINTER_REGNUM) \
808 ? 1 : NUM_REGS (MODE))
809
810 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
811 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
812 regs holding FP. */
813 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
814 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
815 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
816 || REGNO == ARG_POINTER_REGNUM \
817 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
818
819 /* Value is 1 if it is a good idea to tie two pseudo registers
820 when one has mode MODE1 and one has mode MODE2.
821 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
822 for any hard reg, then this must be 0 for correct output. */
823 #define MODES_TIEABLE_P(MODE1, MODE2) \
824 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
825
826 /* Specify the registers used for certain standard purposes.
827 The values of these macros are register numbers. */
828
829 /* Define this if the program counter is overloaded on a register. */
830 #define PC_REGNUM 15
831
832 /* Register to use for pushing function arguments. */
833 #define STACK_POINTER_REGNUM 13
834 #define SP_REGNUM STACK_POINTER_REGNUM
835
836 /* Base register for access to local variables of the function. */
837 #define FRAME_POINTER_REGNUM 25
838
839 /* Define this to be where the real frame pointer is if it is not possible to
840 work out the offset between the frame pointer and the automatic variables
841 until after register allocation has taken place. FRAME_POINTER_REGNUM
842 should point to a special register that we will make sure is eliminated. */
843 #define HARD_FRAME_POINTER_REGNUM 11
844 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
845
846 /* Register which holds return address from a subroutine call. */
847 #define LR_REGNUM 14
848
849 /* Scratch register - used in all kinds of places, eg trampolines. */
850 #define IP_REGNUM 12
851
852 /* Value should be nonzero if functions must have frame pointers.
853 Zero means the frame pointer need not be set up (and parms may be accessed
854 via the stack pointer) in functions that seem suitable.
855 If we have to have a frame pointer we might as well make use of it.
856 APCS says that the frame pointer does not need to be pushed in leaf
857 functions, or simple tail call functions. */
858 #define FRAME_POINTER_REQUIRED \
859 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
860
861 /* Base register for access to arguments of the function. */
862 #define ARG_POINTER_REGNUM 26
863
864 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
865 as an invisible last argument (possible since varargs don't exist in
866 Pascal), so the following is not true. */
867 #define STATIC_CHAIN_REGNUM 8
868
869 /* Register in which address to store a structure value
870 is passed to a function. */
871 #define STRUCT_VALUE_REGNUM 0
872
873 /* Internal, so that we don't need to refer to a raw number */
874 #define CC_REGNUM 24
875
876 /* The order in which register should be allocated. It is good to use ip
877 since no saving is required (though calls clobber it) and it never contains
878 function parameters. It is quite good to use lr since other calls may
879 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
880 least likely to contain a function parameter; in addition results are
881 returned in r0.
882 */
883 #define REG_ALLOC_ORDER \
884 { \
885 3, 2, 1, 0, 12, 14, 4, 5, \
886 6, 7, 8, 10, 9, 11, 13, 15, \
887 16, 17, 18, 19, 20, 21, 22, 23, \
888 24, 25, 26 \
889 }
890 \f
891 /* Register and constant classes. */
892
893 /* Register classes: all ARM regs or all FPU regs---simple! */
894 enum reg_class
895 {
896 NO_REGS,
897 FPU_REGS,
898 GENERAL_REGS,
899 ALL_REGS,
900 LIM_REG_CLASSES
901 };
902
903 #define N_REG_CLASSES (int) LIM_REG_CLASSES
904
905 /* Give names of register classes as strings for dump file. */
906 #define REG_CLASS_NAMES \
907 { \
908 "NO_REGS", \
909 "FPU_REGS", \
910 "GENERAL_REGS", \
911 "ALL_REGS", \
912 }
913
914 /* Define which registers fit in which classes.
915 This is an initializer for a vector of HARD_REG_SET
916 of length N_REG_CLASSES. */
917 #define REG_CLASS_CONTENTS \
918 { \
919 { 0x0000000 }, /* NO_REGS */ \
920 { 0x0FF0000 }, /* FPU_REGS */ \
921 { 0x200FFFF }, /* GENERAL_REGS */ \
922 { 0x2FFFFFF } /* ALL_REGS */ \
923 }
924
925 /* The same information, inverted:
926 Return the class number of the smallest class containing
927 reg number REGNO. This could be a conditional expression
928 or could index an array. */
929 #define REGNO_REG_CLASS(REGNO) \
930 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
931 || REGNO == ARG_POINTER_REGNUM) \
932 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
933 ? NO_REGS : FPU_REGS)
934
935 /* The class value for index registers, and the one for base regs. */
936 #define INDEX_REG_CLASS GENERAL_REGS
937 #define BASE_REG_CLASS GENERAL_REGS
938
939 /* Get reg_class from a letter such as appears in the machine description.
940 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
941 #define REG_CLASS_FROM_LETTER(C) \
942 ((C)=='f' ? FPU_REGS : NO_REGS)
943
944 /* The letters I, J, K, L and M in a register constraint string
945 can be used to stand for particular ranges of immediate operands.
946 This macro defines what the ranges are.
947 C is the letter, and VALUE is a constant value.
948 Return 1 if VALUE is in the range specified by C.
949 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
950 J: valid indexing constants.
951 K: ~value ok in rhs argument of data operand.
952 L: -value ok in rhs argument of data operand.
953 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
954 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
955 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
956 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
957 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
958 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
959 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
960 || (((VALUE) & ((VALUE) - 1)) == 0)) \
961 : 0)
962
963 /* For the ARM, `Q' means that this is a memory operand that is just
964 an offset from a register.
965 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
966 address. This means that the symbol is in the text segment and can be
967 accessed without using a load. */
968
969 #define EXTRA_CONSTRAINT(OP, C) \
970 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
971 : (C) == 'R' ? (GET_CODE (OP) == MEM \
972 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
973 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
974 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
975 : 0)
976
977 /* Constant letter 'G' for the FPU immediate constants.
978 'H' means the same constant negated. */
979 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
980 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
981 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
982
983 /* Given an rtx X being reloaded into a reg required to be
984 in class CLASS, return the class of reg to actually use.
985 In general this is just CLASS; but on some machines
986 in some cases it is preferable to use a more restrictive class. */
987 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
988
989 /* Return the register class of a scratch register needed to copy IN into
990 or out of a register in CLASS in MODE. If it can be done directly,
991 NO_REGS is returned. */
992 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
993 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
994 ? GENERAL_REGS : NO_REGS)
995
996 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
997 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
998 (((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \
999 && (GET_CODE (X) == MEM \
1000 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1001 && true_regnum (X) == -1))) \
1002 ? GENERAL_REGS : NO_REGS)
1003
1004 /* Try a machine-dependent way of reloading an illegitimate address
1005 operand. If we find one, push the reload and jump to WIN. This
1006 macro is used in only one place: `find_reloads_address' in reload.c.
1007
1008 For the ARM, we wish to handle large displacements off a base
1009 register by splitting the addend across a MOV and the mem insn.
1010 This can cut the number of reloads needed. */
1011 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1012 do \
1013 { \
1014 if (GET_CODE (X) == PLUS \
1015 && GET_CODE (XEXP (X, 0)) == REG \
1016 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1017 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1018 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1019 { \
1020 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1021 HOST_WIDE_INT low, high; \
1022 \
1023 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1024 low = ((val & 0xf) ^ 0x8) - 0x8; \
1025 else if (MODE == SImode || MODE == QImode \
1026 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1027 || (MODE == HImode && ! arm_arch4)) \
1028 /* Need to be careful, -4096 is not a valid offset */ \
1029 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1030 else if (MODE == HImode && arm_arch4) \
1031 /* Need to be careful, -256 is not a valid offset */ \
1032 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1033 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1034 && TARGET_HARD_FLOAT) \
1035 /* Need to be careful, -1024 is not a valid offset */ \
1036 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1037 else \
1038 break; \
1039 \
1040 high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \
1041 /* Check for overflow or zero */ \
1042 if (low == 0 || high == 0 || (high + low != val)) \
1043 break; \
1044 \
1045 /* Reload the high part into a base reg; leave the low part \
1046 in the mem. */ \
1047 X = gen_rtx_PLUS (GET_MODE (X), \
1048 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1049 GEN_INT (high)), \
1050 GEN_INT (low)); \
1051 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1052 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1053 OPNUM, TYPE); \
1054 goto WIN; \
1055 } \
1056 } \
1057 while (0)
1058
1059 /* Return the maximum number of consecutive registers
1060 needed to represent mode MODE in a register of class CLASS.
1061 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1062 #define CLASS_MAX_NREGS(CLASS, MODE) \
1063 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1064
1065 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1066 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1067 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
1068 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
1069 ? 20 : 2)
1070 \f
1071 /* Stack layout; function entry, exit and calling. */
1072
1073 /* Define this if pushing a word on the stack
1074 makes the stack pointer a smaller address. */
1075 #define STACK_GROWS_DOWNWARD 1
1076
1077 /* Define this if the nominal address of the stack frame
1078 is at the high-address end of the local variables;
1079 that is, each additional local variable allocated
1080 goes at a more negative offset in the frame. */
1081 #define FRAME_GROWS_DOWNWARD 1
1082
1083 /* Offset within stack frame to start allocating local variables at.
1084 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1085 first local allocated. Otherwise, it is the offset to the BEGINNING
1086 of the first local allocated. */
1087 #define STARTING_FRAME_OFFSET 0
1088
1089 /* If we generate an insn to push BYTES bytes,
1090 this says how many the stack pointer really advances by. */
1091 /* The push insns do not do this rounding implicitly. So don't define this. */
1092 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1093
1094 /* Define this if the maximum size of all the outgoing args is to be
1095 accumulated and pushed during the prologue. The amount can be
1096 found in the variable current_function_outgoing_args_size. */
1097 #define ACCUMULATE_OUTGOING_ARGS 1
1098
1099 /* Offset of first parameter from the argument pointer register value. */
1100 #define FIRST_PARM_OFFSET(FNDECL) 4
1101
1102 /* Value is the number of byte of arguments automatically
1103 popped when returning from a subroutine call.
1104 FUNDECL is the declaration node of the function (as a tree),
1105 FUNTYPE is the data type of the function (as a tree),
1106 or for a library call it is an identifier node for the subroutine name.
1107 SIZE is the number of bytes of arguments passed on the stack.
1108
1109 On the ARM, the caller does not pop any of its arguments that were passed
1110 on the stack. */
1111 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1112
1113 /* Define how to find the value returned by a library function
1114 assuming the value has mode MODE. */
1115 #define LIBCALL_VALUE(MODE) \
1116 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1117 ? gen_rtx_REG (MODE, 16) \
1118 : gen_rtx_REG (MODE, 0))
1119
1120 /* Define how to find the value returned by a function.
1121 VALTYPE is the data type of the value (as a tree).
1122 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1123 otherwise, FUNC is 0. */
1124 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1125 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1126
1127 /* 1 if N is a possible register number for a function value.
1128 On the ARM, only r0 and f0 can return results. */
1129 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1130 ((REGNO) == 0 || (((REGNO) == 16) && TARGET_HARD_FLOAT))
1131
1132 /* How large values are returned */
1133 /* A C expression which can inhibit the returning of certain function values
1134 in registers, based on the type of value. */
1135 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1136
1137 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1138 values must be in memory. On the ARM, they need only do so if larger
1139 than a word, or if they contain elements offset from zero in the struct. */
1140 #define DEFAULT_PCC_STRUCT_RETURN 0
1141
1142 /* Define where to put the arguments to a function.
1143 Value is zero to push the argument on the stack,
1144 or a hard register in which to store the argument.
1145
1146 MODE is the argument's machine mode.
1147 TYPE is the data type of the argument (as a tree).
1148 This is null for libcalls where that information may
1149 not be available.
1150 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1151 the preceding args and about the function being called.
1152 NAMED is nonzero if this argument is a named parameter
1153 (otherwise it is an extra parameter matching an ellipsis).
1154
1155 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1156 other arguments are passed on the stack. If (NAMED == 0) (which happens
1157 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1158 passed in the stack (function_prologue will indeed make it pass in the
1159 stack if necessary). */
1160 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1161 ((NAMED) \
1162 ? ((CUM) >= NUM_ARG_REGS ? 0 : gen_rtx_REG (MODE, CUM))\
1163 : 0)
1164
1165 /* For an arg passed partly in registers and partly in memory,
1166 this is the number of registers used.
1167 For args passed entirely in registers or entirely in memory, zero. */
1168 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1169 ( NUM_ARG_REGS > (CUM) \
1170 && (NUM_ARG_REGS < ((CUM) + NUM_REGS2 (MODE, TYPE))) \
1171 ? NUM_ARG_REGS - (CUM) : 0)
1172
1173 /* A C type for declaring a variable that is used as the first argument of
1174 `FUNCTION_ARG' and other related values. For some target machines, the
1175 type `int' suffices and can hold the number of bytes of argument so far.
1176
1177 On the ARM, this is the number of bytes of arguments scanned so far. */
1178 #define CUMULATIVE_ARGS int
1179
1180 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1181 for a call to a function whose data type is FNTYPE.
1182 For a library call, FNTYPE is 0.
1183 On the ARM, the offset starts at 0. */
1184 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1185 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 1 : 0))
1186
1187 /* Update the data in CUM to advance over an argument
1188 of mode MODE and data type TYPE.
1189 (TYPE is null for libcalls where that information may not be available.) */
1190 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1191 (CUM) += NUM_REGS2 (MODE, TYPE)
1192
1193 /* 1 if N is a possible register number for function argument passing.
1194 On the ARM, r0-r3 are used to pass args. */
1195 #define FUNCTION_ARG_REGNO_P(REGNO) \
1196 ((REGNO) >= 0 && (REGNO) <= 3)
1197
1198 /* Perform any actions needed for a function that is receiving a variable
1199 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1200 of the current parameter. PRETEND_SIZE is a variable that should be set to
1201 the amount of stack that must be pushed by the prolog to pretend that our
1202 caller pushed it.
1203
1204 Normally, this macro will push all remaining incoming registers on the
1205 stack and set PRETEND_SIZE to the length of the registers pushed.
1206
1207 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1208 named arg and all anonymous args onto the stack.
1209 XXX I know the prologue shouldn't be pushing registers, but it is faster
1210 that way. */
1211 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1212 { \
1213 extern int current_function_anonymous_args; \
1214 current_function_anonymous_args = 1; \
1215 if ((CUM) < NUM_ARG_REGS) \
1216 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM)) * UNITS_PER_WORD; \
1217 }
1218
1219 /* Generate assembly output for the start of a function. */
1220 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1221 output_func_prologue ((STREAM), (SIZE))
1222
1223 /* If your target environment doesn't prefix user functions with an
1224 underscore, you may wish to re-define this to prevent any conflicts.
1225 e.g. AOF may prefix mcount with an underscore. */
1226 #ifndef ARM_MCOUNT_NAME
1227 #define ARM_MCOUNT_NAME "*mcount"
1228 #endif
1229
1230 /* Call the function profiler with a given profile label. The Acorn
1231 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1232 On the ARM the full profile code will look like:
1233 .data
1234 LP1
1235 .word 0
1236 .text
1237 mov ip, lr
1238 bl mcount
1239 .word LP1
1240
1241 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1242 will output the .text section.
1243
1244 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1245 ``prof'' doesn't seem to mind about this! */
1246 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1247 { \
1248 char temp[20]; \
1249 rtx sym; \
1250 \
1251 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1252 IP_REGNUM, LR_REGNUM); \
1253 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1254 fputc ('\n', STREAM); \
1255 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1256 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1257 ASM_OUTPUT_INT (STREAM, sym); \
1258 }
1259
1260 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1261 the stack pointer does not matter. The value is tested only in
1262 functions that have frame pointers.
1263 No definition is equivalent to always zero.
1264
1265 On the ARM, the function epilogue recovers the stack pointer from the
1266 frame. */
1267 #define EXIT_IGNORE_STACK 1
1268
1269 /* Generate the assembly code for function exit. */
1270 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1271 output_func_epilogue (STREAM, SIZE)
1272
1273 /* Determine if the epilogue should be output as RTL.
1274 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1275 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1276
1277 /* Definitions for register eliminations.
1278
1279 This is an array of structures. Each structure initializes one pair
1280 of eliminable registers. The "from" register number is given first,
1281 followed by "to". Eliminations of the same "from" register are listed
1282 in order of preference.
1283
1284 We have two registers that can be eliminated on the ARM. First, the
1285 arg pointer register can often be eliminated in favor of the stack
1286 pointer register. Secondly, the pseudo frame pointer register can always
1287 be eliminated; it is replaced with either the stack or the real frame
1288 pointer. */
1289
1290 #define ELIMINABLE_REGS \
1291 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1292 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
1293 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1294 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
1295
1296 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1297 Frame pointer elimination is automatically handled.
1298
1299 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1300 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1301 pointer, we must eliminate FRAME_POINTER_REGNUM into
1302 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1303 #define CAN_ELIMINATE(FROM, TO) \
1304 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1305
1306 /* Define the offset between two registers, one to be eliminated, and the other
1307 its replacement, at the start of a routine. */
1308 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1309 { \
1310 int volatile_func = arm_volatile_func (); \
1311 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1312 (OFFSET) = 0; \
1313 else if ((FROM) == FRAME_POINTER_REGNUM \
1314 && (TO) == STACK_POINTER_REGNUM) \
1315 (OFFSET) = current_function_outgoing_args_size \
1316 + ((get_frame_size () + 3) & ~3); \
1317 else \
1318 { \
1319 int regno; \
1320 int offset = 12; \
1321 int saved_hard_reg = 0; \
1322 \
1323 if (! volatile_func) \
1324 { \
1325 for (regno = 0; regno <= 10; regno++) \
1326 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1327 saved_hard_reg = 1, offset += 4; \
1328 /* PIC register is a fixed reg, so call_used_regs set. */ \
1329 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1330 saved_hard_reg = 1, offset += 4; \
1331 for (regno = 16; regno <=23; regno++) \
1332 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1333 offset += 12; \
1334 } \
1335 if ((FROM) == FRAME_POINTER_REGNUM) \
1336 (OFFSET) = -offset; \
1337 else \
1338 { \
1339 if (! frame_pointer_needed) \
1340 offset -= 16; \
1341 if (! volatile_func \
1342 && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \
1343 offset += 4; \
1344 offset += current_function_outgoing_args_size; \
1345 (OFFSET) = ((get_frame_size () + 3) & ~3) + offset; \
1346 } \
1347 } \
1348 }
1349
1350 /* Output assembler code for a block containing the constant parts
1351 of a trampoline, leaving space for the variable parts.
1352
1353 On the ARM, (if r8 is the static chain regnum, and remembering that
1354 referencing pc adds an offset of 8) the trampoline looks like:
1355 ldr r8, [pc, #0]
1356 ldr pc, [pc]
1357 .word static chain value
1358 .word function's address
1359 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1360 #define TRAMPOLINE_TEMPLATE(FILE) \
1361 { \
1362 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1363 REGISTER_PREFIX, reg_names[STATIC_CHAIN_REGNUM], \
1364 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1365 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1366 REGISTER_PREFIX, reg_names[PC_REGNUM], \
1367 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1368 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1369 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1370 }
1371
1372 /* Length in units of the trampoline for entering a nested function. */
1373 #define TRAMPOLINE_SIZE 16
1374
1375 /* Alignment required for a trampoline in units. */
1376 #define TRAMPOLINE_ALIGN 4
1377
1378 /* Emit RTL insns to initialize the variable parts of a trampoline.
1379 FNADDR is an RTX for the address of the function's pure code.
1380 CXT is an RTX for the static chain value for the function. */
1381 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1382 { \
1383 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1384 (CXT)); \
1385 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1386 (FNADDR)); \
1387 }
1388
1389 \f
1390 /* Addressing modes, and classification of registers for them. */
1391
1392 #define HAVE_POST_INCREMENT 1
1393 #define HAVE_PRE_INCREMENT 1
1394 #define HAVE_POST_DECREMENT 1
1395 #define HAVE_PRE_DECREMENT 1
1396
1397 /* Macros to check register numbers against specific register classes. */
1398
1399 /* These assume that REGNO is a hard or pseudo reg number.
1400 They give nonzero only if REGNO is a hard reg of the suitable class
1401 or a pseudo reg currently allocated to a suitable hard reg.
1402 Since they use reg_renumber, they are safe only once reg_renumber
1403 has been allocated, which happens in local-alloc.c.
1404
1405 On the ARM, don't allow the pc to be used. */
1406 #define REGNO_OK_FOR_BASE_P(REGNO) \
1407 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1408 || (REGNO) == ARG_POINTER_REGNUM \
1409 || (unsigned) reg_renumber[(REGNO)] < 15 \
1410 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1411 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1412 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1413 REGNO_OK_FOR_BASE_P(REGNO)
1414
1415 /* Maximum number of registers that can appear in a valid memory address.
1416 Shifts in addresses can't be by a register. */
1417
1418 #define MAX_REGS_PER_ADDRESS 2
1419
1420 /* Recognize any constant value that is a valid address. */
1421 /* XXX We can address any constant, eventually... */
1422
1423 #ifdef AOF_ASSEMBLER
1424
1425 #define CONSTANT_ADDRESS_P(X) \
1426 (GET_CODE (X) == SYMBOL_REF \
1427 && CONSTANT_POOL_ADDRESS_P (X))
1428
1429 #else
1430
1431 #define CONSTANT_ADDRESS_P(X) \
1432 (GET_CODE (X) == SYMBOL_REF \
1433 && (CONSTANT_POOL_ADDRESS_P (X) \
1434 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1435
1436 #endif /* AOF_ASSEMBLER */
1437
1438 /* Nonzero if the constant value X is a legitimate general operand.
1439 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1440
1441 On the ARM, allow any integer (invalid ones are removed later by insn
1442 patterns), nice doubles and symbol_refs which refer to the function's
1443 constant pool XXX. */
1444 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1445
1446 /* Symbols in the text segment can be accessed without indirecting via the
1447 constant pool; it may take an extra binary operation, but this is still
1448 faster than indirecting via memory. Don't do this when not optimizing,
1449 since we won't be calculating al of the offsets necessary to do this
1450 simplification. */
1451 /* This doesn't work with AOF syntax, since the string table may be in
1452 a different AREA. */
1453 #ifndef AOF_ASSEMBLER
1454 #define ENCODE_SECTION_INFO(decl) \
1455 { \
1456 if (optimize > 0 && TREE_CONSTANT (decl) \
1457 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1458 { \
1459 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1460 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1461 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1462 } \
1463 }
1464 #endif
1465
1466 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1467 and check its validity for a certain class.
1468 We have two alternate definitions for each of them.
1469 The usual definition accepts all pseudo regs; the other rejects
1470 them unless they have been allocated suitable hard regs.
1471 The symbol REG_OK_STRICT causes the latter definition to be used. */
1472 #ifndef REG_OK_STRICT
1473
1474 /* Nonzero if X is a hard reg that can be used as a base reg
1475 or if it is a pseudo reg. */
1476 #define REG_OK_FOR_BASE_P(X) \
1477 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1478 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1479
1480 /* Nonzero if X is a hard reg that can be used as an index
1481 or if it is a pseudo reg. */
1482 #define REG_OK_FOR_INDEX_P(X) \
1483 REG_OK_FOR_BASE_P(X)
1484
1485 #define REG_OK_FOR_PRE_POST_P(X) \
1486 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1487 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1488
1489 #else
1490
1491 /* Nonzero if X is a hard reg that can be used as a base reg. */
1492 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1493
1494 /* Nonzero if X is a hard reg that can be used as an index. */
1495 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1496
1497 #define REG_OK_FOR_PRE_POST_P(X) \
1498 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1499 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1500 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1501 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1502
1503 #endif
1504 \f
1505 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1506 that is a valid memory address for an instruction.
1507 The MODE argument is the machine mode for the MEM expression
1508 that wants to use this address.
1509
1510 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1511 #define BASE_REGISTER_RTX_P(X) \
1512 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1513
1514 #define INDEX_REGISTER_RTX_P(X) \
1515 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1516
1517 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1518 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1519 only be small constants. */
1520 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1521 do \
1522 { \
1523 HOST_WIDE_INT range; \
1524 enum rtx_code code = GET_CODE (INDEX); \
1525 \
1526 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1527 { \
1528 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1529 && INTVAL (INDEX) > -1024 \
1530 && (INTVAL (INDEX) & 3) == 0) \
1531 goto LABEL; \
1532 } \
1533 else \
1534 { \
1535 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1536 goto LABEL; \
1537 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1538 && (! arm_arch4 || (MODE) != HImode)) \
1539 { \
1540 rtx xiop0 = XEXP (INDEX, 0); \
1541 rtx xiop1 = XEXP (INDEX, 1); \
1542 if (INDEX_REGISTER_RTX_P (xiop0) \
1543 && power_of_two_operand (xiop1, SImode)) \
1544 goto LABEL; \
1545 if (INDEX_REGISTER_RTX_P (xiop1) \
1546 && power_of_two_operand (xiop0, SImode)) \
1547 goto LABEL; \
1548 } \
1549 if (GET_MODE_SIZE (MODE) <= 4 \
1550 && (code == LSHIFTRT || code == ASHIFTRT \
1551 || code == ASHIFT || code == ROTATERT) \
1552 && (! arm_arch4 || (MODE) != HImode)) \
1553 { \
1554 rtx op = XEXP (INDEX, 1); \
1555 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1556 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1557 && INTVAL (op) <= 31) \
1558 goto LABEL; \
1559 } \
1560 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1561 range = ((MODE) == HImode || (MODE) == QImode) \
1562 ? (arm_arch4 ? 256 : 4095) : 4096; \
1563 if (code == CONST_INT && INTVAL (INDEX) < range \
1564 && INTVAL (INDEX) > -range) \
1565 goto LABEL; \
1566 } \
1567 } \
1568 while (0)
1569
1570 /* Jump to LABEL if X is a valid address RTX. This must also take
1571 REG_OK_STRICT into account when deciding about valid registers, but it uses
1572 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1573 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1574 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1575 refs must be forced though a static cell to ensure addressability. */
1576 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1577 { \
1578 if (BASE_REGISTER_RTX_P (X)) \
1579 goto LABEL; \
1580 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1581 && GET_CODE (XEXP (X, 0)) == REG \
1582 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1583 goto LABEL; \
1584 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1585 && (GET_CODE (X) == LABEL_REF \
1586 || (GET_CODE (X) == CONST \
1587 && GET_CODE (XEXP ((X), 0)) == PLUS \
1588 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1589 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1590 goto LABEL; \
1591 else if ((MODE) == TImode) \
1592 ; \
1593 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1594 { \
1595 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1596 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1597 { \
1598 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1599 if (val == 4 || val == -4 || val == -8) \
1600 goto LABEL; \
1601 } \
1602 } \
1603 else if (GET_CODE (X) == PLUS) \
1604 { \
1605 rtx xop0 = XEXP(X,0); \
1606 rtx xop1 = XEXP(X,1); \
1607 \
1608 if (BASE_REGISTER_RTX_P (xop0)) \
1609 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1610 else if (BASE_REGISTER_RTX_P (xop1)) \
1611 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1612 } \
1613 /* Reload currently can't handle MINUS, so disable this for now */ \
1614 /* else if (GET_CODE (X) == MINUS) \
1615 { \
1616 rtx xop0 = XEXP (X,0); \
1617 rtx xop1 = XEXP (X,1); \
1618 \
1619 if (BASE_REGISTER_RTX_P (xop0)) \
1620 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1621 } */ \
1622 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1623 && GET_CODE (X) == SYMBOL_REF \
1624 && CONSTANT_POOL_ADDRESS_P (X) \
1625 && ! (flag_pic \
1626 && symbol_mentioned_p (get_pool_constant (X)))) \
1627 goto LABEL; \
1628 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1629 && (GET_MODE_SIZE (MODE) <= 4) \
1630 && GET_CODE (XEXP (X, 0)) == REG \
1631 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1632 goto LABEL; \
1633 }
1634 \f
1635 /* Try machine-dependent ways of modifying an illegitimate address
1636 to be legitimate. If we find one, return the new, valid address.
1637 This macro is used in only one place: `memory_address' in explow.c.
1638
1639 OLDX is the address as it was before break_out_memory_refs was called.
1640 In some cases it is useful to look at this to decide what needs to be done.
1641
1642 MODE and WIN are passed so that this macro can use
1643 GO_IF_LEGITIMATE_ADDRESS.
1644
1645 It is always safe for this macro to do nothing. It exists to recognize
1646 opportunities to optimize the output.
1647
1648 On the ARM, try to convert [REG, #BIGCONST]
1649 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1650 where VALIDCONST == 0 in case of TImode. */
1651 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1652 { \
1653 if (GET_CODE (X) == PLUS) \
1654 { \
1655 rtx xop0 = XEXP (X, 0); \
1656 rtx xop1 = XEXP (X, 1); \
1657 \
1658 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1659 xop0 = force_reg (SImode, xop0); \
1660 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1661 xop1 = force_reg (SImode, xop1); \
1662 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1663 { \
1664 HOST_WIDE_INT n, low_n; \
1665 rtx base_reg, val; \
1666 n = INTVAL (xop1); \
1667 \
1668 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1669 { \
1670 low_n = n & 0x0f; \
1671 n &= ~0x0f; \
1672 if (low_n > 4) \
1673 { \
1674 n += 16; \
1675 low_n -= 16; \
1676 } \
1677 } \
1678 else \
1679 { \
1680 low_n = ((MODE) == TImode ? 0 \
1681 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1682 n -= low_n; \
1683 } \
1684 base_reg = gen_reg_rtx (SImode); \
1685 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1686 GEN_INT (n)), NULL_RTX); \
1687 emit_move_insn (base_reg, val); \
1688 (X) = (low_n == 0 ? base_reg \
1689 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1690 } \
1691 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1692 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1693 } \
1694 else if (GET_CODE (X) == MINUS) \
1695 { \
1696 rtx xop0 = XEXP (X, 0); \
1697 rtx xop1 = XEXP (X, 1); \
1698 \
1699 if (CONSTANT_P (xop0)) \
1700 xop0 = force_reg (SImode, xop0); \
1701 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1702 xop1 = force_reg (SImode, xop1); \
1703 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1704 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1705 } \
1706 if (flag_pic) \
1707 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1708 if (memory_address_p (MODE, X)) \
1709 goto WIN; \
1710 }
1711
1712 /* Go to LABEL if ADDR (a legitimate address expression)
1713 has an effect that depends on the machine mode it is used for. */
1714 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1715 { \
1716 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1717 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1718 goto LABEL; \
1719 }
1720 \f
1721 /* Specify the machine mode that this machine uses
1722 for the index in the tablejump instruction. */
1723 #define CASE_VECTOR_MODE SImode
1724
1725 /* Define as C expression which evaluates to nonzero if the tablejump
1726 instruction expects the table to contain offsets from the address of the
1727 table.
1728 Do not define this if the table should contain absolute addresses. */
1729 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1730
1731 /* Specify the tree operation to be used to convert reals to integers. */
1732 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1733
1734 /* This is the kind of divide that is easiest to do in the general case. */
1735 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1736
1737 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1738 unsigned is probably best, but may break some code. */
1739 #ifndef DEFAULT_SIGNED_CHAR
1740 #define DEFAULT_SIGNED_CHAR 0
1741 #endif
1742
1743 /* Don't cse the address of the function being compiled. */
1744 #define NO_RECURSIVE_FUNCTION_CSE 1
1745
1746 /* Max number of bytes we can move from memory to memory
1747 in one reasonably fast instruction. */
1748 #define MOVE_MAX 4
1749
1750 /* Define if operations between registers always perform the operation
1751 on the full register even if a narrower mode is specified. */
1752 #define WORD_REGISTER_OPERATIONS
1753
1754 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1755 will either zero-extend or sign-extend. The value of this macro should
1756 be the code that says which one of the two operations is implicitly
1757 done, NIL if none. */
1758 #define LOAD_EXTEND_OP(MODE) \
1759 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1760 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1761
1762 /* Define this if zero-extension is slow (more than one real instruction).
1763 On the ARM, it is more than one instruction only if not fetching from
1764 memory. */
1765 /* #define SLOW_ZERO_EXTEND */
1766
1767 /* Nonzero if access to memory by bytes is slow and undesirable. */
1768 #define SLOW_BYTE_ACCESS 0
1769
1770 /* Immediate shift counts are truncated by the output routines (or was it
1771 the assembler?). Shift counts in a register are truncated by ARM. Note
1772 that the native compiler puts too large (> 32) immediate shift counts
1773 into a register and shifts by the register, letting the ARM decide what
1774 to do instead of doing that itself. */
1775 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1776 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1777 On the arm, Y in a register is used modulo 256 for the shift. Only for
1778 rotates is modulo 32 used. */
1779 /* #define SHIFT_COUNT_TRUNCATED 1 */
1780
1781 /* All integers have the same format so truncation is easy. */
1782 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1783
1784 /* Calling from registers is a massive pain. */
1785 #define NO_FUNCTION_CSE 1
1786
1787 /* Chars and shorts should be passed as ints. */
1788 #define PROMOTE_PROTOTYPES 1
1789
1790 /* The machine modes of pointers and functions */
1791 #define Pmode SImode
1792 #define FUNCTION_MODE Pmode
1793
1794 /* The structure type of the machine dependent info field of insns
1795 No uses for this yet. */
1796 /* #define INSN_MACHINE_INFO struct machine_info */
1797
1798 /* The relative costs of various types of constants. Note that cse.c defines
1799 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1800 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1801 case CONST_INT: \
1802 if (const_ok_for_arm (INTVAL (RTX))) \
1803 return (OUTER_CODE) == SET ? 2 : -1; \
1804 else if (OUTER_CODE == AND \
1805 && const_ok_for_arm (~INTVAL (RTX))) \
1806 return -1; \
1807 else if ((OUTER_CODE == COMPARE \
1808 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1809 && const_ok_for_arm (-INTVAL (RTX))) \
1810 return -1; \
1811 else \
1812 return 5; \
1813 case CONST: \
1814 case LABEL_REF: \
1815 case SYMBOL_REF: \
1816 return 6; \
1817 case CONST_DOUBLE: \
1818 if (const_double_rtx_ok_for_fpu (RTX)) \
1819 return (OUTER_CODE) == SET ? 2 : -1; \
1820 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1821 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1822 return -1; \
1823 return(7);
1824
1825 #define ARM_FRAME_RTX(X) \
1826 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1827 || (X) == arg_pointer_rtx)
1828
1829 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
1830 return arm_rtx_costs (X, CODE);
1831
1832 /* Moves to and from memory are quite expensive */
1833 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1834
1835 /* All address computations that can be done are free, but rtx cost returns
1836 the same for practically all of them. So we weight the different types
1837 of address here in the order (most pref first):
1838 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1839 #define ADDRESS_COST(X) \
1840 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1841 || GET_CODE (X) == SYMBOL_REF) \
1842 ? 0 \
1843 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1844 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1845 ? 10 \
1846 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1847 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1848 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1849 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1850 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1851 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1852 ? 1 : 0)) \
1853 : 4)))))
1854
1855 /* Try to generate sequences that don't involve branches, we can then use
1856 conditional instructions */
1857 #define BRANCH_COST 4
1858
1859 /* A C statement to update the variable COST based on the relationship
1860 between INSN that is dependent on DEP through dependence LINK. */
1861 #define ADJUST_COST(INSN, LINK, DEP, COST) \
1862 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
1863 \f
1864 /* Position Independent Code. */
1865 /* We decide which register to use based on the compilation options and
1866 the assembler in use; this is more general than the APCS restriction of
1867 using sb (r9) all the time. */
1868 extern int arm_pic_register;
1869
1870 /* Used when parsing command line option -mpic-register=. */
1871 extern const char * arm_pic_register_string;
1872
1873 /* The register number of the register used to address a table of static
1874 data addresses in memory. */
1875 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1876
1877 #define FINALIZE_PIC arm_finalize_pic ()
1878
1879 /* We can't directly access anything that contains a symbol,
1880 nor can we indirect via the constant pool. */
1881 #define LEGITIMATE_PIC_OPERAND_P(X) \
1882 (! symbol_mentioned_p (X) \
1883 && (! CONSTANT_POOL_ADDRESS_P (X) \
1884 || ! symbol_mentioned_p (get_pool_constant (X))))
1885
1886 /* We need to know when we are making a constant pool; this determines
1887 whether data needs to be in the GOT or can be referenced via a GOT
1888 offset. */
1889 extern int making_const_table;
1890
1891 \f
1892 /* Condition code information. */
1893 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1894 return the mode to be used for the comparison.
1895 CCFPEmode should be used with floating inequalities,
1896 CCFPmode should be used with floating equalities.
1897 CC_NOOVmode should be used with SImode integer equalities.
1898 CC_Zmode should be used if only the Z flag is set correctly
1899 CCmode should be used otherwise. */
1900
1901 #define EXTRA_CC_MODES \
1902 CC(CC_NOOVmode, "CC_NOOV") \
1903 CC(CC_Zmode, "CC_Z") \
1904 CC(CC_SWPmode, "CC_SWP") \
1905 CC(CCFPmode, "CCFP") \
1906 CC(CCFPEmode, "CCFPE") \
1907 CC(CC_DNEmode, "CC_DNE") \
1908 CC(CC_DEQmode, "CC_DEQ") \
1909 CC(CC_DLEmode, "CC_DLE") \
1910 CC(CC_DLTmode, "CC_DLT") \
1911 CC(CC_DGEmode, "CC_DGE") \
1912 CC(CC_DGTmode, "CC_DGT") \
1913 CC(CC_DLEUmode, "CC_DLEU") \
1914 CC(CC_DLTUmode, "CC_DLTU") \
1915 CC(CC_DGEUmode, "CC_DGEU") \
1916 CC(CC_DGTUmode, "CC_DGTU") \
1917 CC(CC_Cmode, "CC_C")
1918
1919 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1920
1921 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1922
1923 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1924 do \
1925 { \
1926 if (GET_CODE (OP1) == CONST_INT \
1927 && ! (const_ok_for_arm (INTVAL (OP1)) \
1928 || (const_ok_for_arm (- INTVAL (OP1))))) \
1929 { \
1930 rtx const_op = OP1; \
1931 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1932 OP1 = const_op; \
1933 } \
1934 } \
1935 while (0)
1936
1937 #define STORE_FLAG_VALUE 1
1938
1939 /* Define the information needed to generate branch insns. This is
1940 stored from the compare operation. Note that we can't use "rtx" here
1941 since it hasn't been defined! */
1942
1943 extern struct rtx_def * arm_compare_op0;
1944 extern struct rtx_def * arm_compare_op1;
1945
1946 /* Define the codes that are matched by predicates in arm.c */
1947 #define PREDICATE_CODES \
1948 {"s_register_operand", {SUBREG, REG}}, \
1949 {"f_register_operand", {SUBREG, REG}}, \
1950 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1951 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1952 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1953 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1954 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1955 {"offsettable_memory_operand", {MEM}}, \
1956 {"bad_signed_byte_operand", {MEM}}, \
1957 {"alignable_memory_operand", {MEM}}, \
1958 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1959 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1960 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1961 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1962 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
1963 {"load_multiple_operation", {PARALLEL}}, \
1964 {"store_multiple_operation", {PARALLEL}}, \
1965 {"equality_operator", {EQ, NE}}, \
1966 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1967 {"const_shift_operand", {CONST_INT}}, \
1968 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1969 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1970 {"multi_register_push", {PARALLEL}}, \
1971 {"cc_register", {REG}}, \
1972 {"logical_binary_operator", {AND, IOR, XOR}}, \
1973 {"dominant_cc_register", {REG}},
1974
1975 \f
1976
1977 /* Gcc puts the pool in the wrong place for ARM, since we can only
1978 load addresses a limited distance around the pc. We do some
1979 special munging to move the constant pool values to the correct
1980 point in the code. */
1981 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1982
1983 /* Output an internal label definition. */
1984 #ifndef ASM_OUTPUT_INTERNAL_LABEL
1985 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1986 do \
1987 { \
1988 char * s = (char *) alloca (40 + strlen (PREFIX)); \
1989 \
1990 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1991 && !strcmp (PREFIX, "L")) \
1992 { \
1993 arm_ccfsm_state = 0; \
1994 arm_target_insn = NULL; \
1995 } \
1996 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1997 ASM_OUTPUT_LABEL (STREAM, s); \
1998 } \
1999 while (0)
2000 #endif
2001
2002 /* Output a push or a pop instruction (only used when profiling). */
2003 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2004 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
2005
2006 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2007 asm_fprintf (STREAM,"\tldmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
2008
2009 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2010 do \
2011 { \
2012 if (TARGET_POKE_FUNCTION_NAME) \
2013 arm_poke_function_name (STREAM, NAME); \
2014 } \
2015 while (0)
2016
2017 /* Target characters. */
2018 #define TARGET_BELL 007
2019 #define TARGET_BS 010
2020 #define TARGET_TAB 011
2021 #define TARGET_NEWLINE 012
2022 #define TARGET_VT 013
2023 #define TARGET_FF 014
2024 #define TARGET_CR 015
2025 \f
2026 /* Only perform branch elimination (by making instructions conditional) if
2027 we're optimising. Otherwise it's of no use anyway. */
2028 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2029 if (optimize) \
2030 arm_final_prescan_insn (INSN)
2031
2032 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2033 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
2034
2035 /* Output an operand of an instruction. */
2036 #define PRINT_OPERAND(STREAM, X, CODE) \
2037 arm_print_operand (STREAM, X, CODE)
2038
2039 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2040 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2041 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
2042 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
2043 ? ((~ (HOST_WIDE_INT) 0) \
2044 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2045 : 0))))
2046
2047 /* Output the address of an operand. */
2048 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
2049 { \
2050 int is_minus = GET_CODE (X) == MINUS; \
2051 \
2052 if (GET_CODE (X) == REG) \
2053 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2054 else if (GET_CODE (X) == PLUS || is_minus) \
2055 { \
2056 rtx base = XEXP (X, 0); \
2057 rtx index = XEXP (X, 1); \
2058 int base_reg; \
2059 HOST_WIDE_INT offset = 0; \
2060 if (GET_CODE (base) != REG) \
2061 { \
2062 /* Ensure that BASE is a register (one of them must be). */ \
2063 rtx temp = base; \
2064 base = index; \
2065 index = temp; \
2066 } \
2067 base_reg = REGNO (base); \
2068 switch (GET_CODE (index)) \
2069 { \
2070 case CONST_INT: \
2071 offset = INTVAL (index); \
2072 if (is_minus) \
2073 offset = -offset; \
2074 asm_fprintf (STREAM, "[%r, #%d]", base_reg, offset); \
2075 break; \
2076 \
2077 case REG: \
2078 asm_fprintf (STREAM, "[%r, %s%r]", base_reg, \
2079 is_minus ? "-" : "", REGNO (index)); \
2080 break; \
2081 \
2082 case MULT: \
2083 case ASHIFTRT: \
2084 case LSHIFTRT: \
2085 case ASHIFT: \
2086 case ROTATERT: \
2087 { \
2088 asm_fprintf (STREAM, "[%r, %s%r", base_reg, \
2089 is_minus ? "-" : "", REGNO (XEXP (index, 0))); \
2090 arm_print_operand (STREAM, index, 'S'); \
2091 fputs ("]", STREAM); \
2092 break; \
2093 } \
2094 \
2095 default: \
2096 abort(); \
2097 } \
2098 } \
2099 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2100 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2101 { \
2102 extern int output_memory_reference_mode; \
2103 \
2104 if (GET_CODE (XEXP (X, 0)) != REG) \
2105 abort (); \
2106 \
2107 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2108 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2109 REGNO (XEXP (X, 0)), \
2110 GET_CODE (X) == PRE_DEC ? "-" : "", \
2111 GET_MODE_SIZE (output_memory_reference_mode)); \
2112 else \
2113 asm_fprintf (STREAM, "[%r], #%s%d", \
2114 REGNO (XEXP (X, 0)), \
2115 GET_CODE (X) == POST_DEC ? "-" : "", \
2116 GET_MODE_SIZE (output_memory_reference_mode)); \
2117 } \
2118 else output_addr_const (STREAM, X); \
2119 }
2120
2121 /* Handles PIC addr specially */
2122 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
2123 { \
2124 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2125 { \
2126 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2127 fputs (" - (", STREAM); \
2128 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2129 fputs (")", STREAM); \
2130 } \
2131 else output_addr_const (STREAM, X); \
2132 \
2133 /* Mark symbols as position independent. We only do this in the \
2134 .text segment, not in the .data segment. */ \
2135 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2136 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2137 { \
2138 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2139 fprintf (STREAM, "(GOTOFF)"); \
2140 else if (GET_CODE (X) == LABEL_REF) \
2141 fprintf (STREAM, "(GOTOFF)"); \
2142 else \
2143 fprintf (STREAM, "(GOT)"); \
2144 } \
2145 }
2146
2147 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2148 Used for C++ multiple inheritance. */
2149 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2150 do \
2151 { \
2152 int mi_delta = (DELTA); \
2153 char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2154 int shift = 0; \
2155 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2156 ? 1 : 0); \
2157 if (mi_delta < 0) mi_delta = -mi_delta; \
2158 while (mi_delta != 0) \
2159 { \
2160 if (mi_delta & (3 << shift) == 0) \
2161 shift += 2; \
2162 else \
2163 { \
2164 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2165 mi_op, this_regno, this_regno, \
2166 mi_delta & (0xff << shift)); \
2167 mi_delta &= ~(0xff << shift); \
2168 shift += 8; \
2169 } \
2170 } \
2171 fputs ("\tb\t", FILE); \
2172 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2173 if (NEED_PLT_RELOC) \
2174 fputs ("(PLT)", FILE); \
2175 fputc ('\n', FILE); \
2176 } \
2177 while (0)
2178
2179 /* A C expression whose value is RTL representing the value of the return
2180 address for the frame COUNT steps up from the current frame. */
2181
2182 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2183 ((COUNT == 0) \
2184 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2185 : NULL_RTX)
2186
2187 /* Used to mask out junk bits from the return address, such as
2188 processor state, interrupt status, condition codes and the like. */
2189 #define MASK_RETURN_ADDR \
2190 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2191 in 26 bit mode, the condition codes must be masked out of the \
2192 return address. This does not apply to ARM6 and later processors \
2193 when running in 32 bit mode. */ \
2194 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2195
2196 /* The remainder of this file is only needed for building the compiler
2197 itself, not for the collateral. */
2198 #ifdef HAVE_CONFIG_H
2199
2200 /* Prototypes for functions in arm.c */
2201
2202 #ifdef BUFSIZ /* stdio.h has been included, ok to use FILE * */
2203 #define STDIO_PROTO(ARGS) PROTO (ARGS)
2204 #else
2205 #define STDIO_PROTO(ARGS) ()
2206 #endif
2207
2208 #ifndef TREE_CODE
2209 union tree_node;
2210 #define Tree union tree_node *
2211 #else
2212 #define Tree tree
2213 #endif
2214
2215 #ifndef RTX_CODE
2216 struct rtx_def;
2217 #define Rtx struct rtx_def *
2218 #else
2219 #define Rtx rtx
2220 #endif
2221
2222 #ifndef HOST_WIDE_INT
2223 #include "hwint.h"
2224 #endif
2225
2226
2227 #ifndef HAVE_MACHINE_MODES
2228 #include "machmode.h"
2229 #endif
2230
2231 #define Mmode enum machine_mode
2232
2233 #ifdef RTX_CODE
2234 #define RTX_CODE_PROTO(ARGS) PROTO (ARGS)
2235 #else
2236 #define RTX_CODE_PROTO(ARGS) ()
2237 #endif
2238
2239 #define Rcode enum rtx_code
2240
2241 void arm_override_options PROTO ((void));
2242 int use_return_insn PROTO ((int));
2243 int const_ok_for_arm PROTO ((HOST_WIDE_INT));
2244 int arm_split_constant RTX_CODE_PROTO ((Rcode, Mmode, HOST_WIDE_INT, Rtx,
2245 Rtx, int));
2246 Rcode arm_canonicalize_comparison RTX_CODE_PROTO ((Rcode, Rtx *));
2247 int arm_return_in_memory PROTO ((Tree));
2248 int legitimate_pic_operand_p PROTO ((Rtx));
2249 Rtx legitimize_pic_address PROTO ((Rtx, Mmode, Rtx));
2250 int is_pic PROTO ((Rtx));
2251 void arm_finalize_pic PROTO ((void));
2252 int arm_rtx_costs RTX_CODE_PROTO ((Rtx, Rcode));
2253 int arm_adjust_cost PROTO ((Rtx, Rtx, Rtx, int));
2254 int const_double_rtx_ok_for_fpu PROTO ((Rtx));
2255 int neg_const_double_rtx_ok_for_fpu PROTO ((Rtx));
2256 int s_register_operand PROTO ((Rtx, Mmode));
2257 int f_register_operand PROTO ((Rtx, Mmode));
2258 int reg_or_int_operand PROTO ((Rtx, Mmode));
2259 int reload_memory_operand PROTO ((Rtx, Mmode));
2260 int arm_rhs_operand PROTO ((Rtx, Mmode));
2261 int arm_rhsm_operand PROTO ((Rtx, Mmode));
2262 int arm_add_operand PROTO ((Rtx, Mmode));
2263 int arm_not_operand PROTO ((Rtx, Mmode));
2264 int offsettable_memory_operand PROTO ((Rtx, Mmode));
2265 int alignable_memory_operand PROTO ((Rtx, Mmode));
2266 int bad_signed_byte_operand PROTO ((Rtx, Mmode));
2267 int fpu_rhs_operand PROTO ((Rtx, Mmode));
2268 int fpu_add_operand PROTO ((Rtx, Mmode));
2269 int power_of_two_operand PROTO ((Rtx, Mmode));
2270 int di_operand PROTO ((Rtx, Mmode));
2271 int soft_df_operand PROTO ((Rtx, Mmode));
2272 int index_operand PROTO ((Rtx, Mmode));
2273 int const_shift_operand PROTO ((Rtx, Mmode));
2274 int shiftable_operator PROTO ((Rtx, Mmode));
2275 int logical_binary_operator PROTO ((Rtx, Mmode));
2276 int shift_operator PROTO ((Rtx, Mmode));
2277 int equality_operator PROTO ((Rtx, Mmode));
2278 int minmax_operator PROTO ((Rtx, Mmode));
2279 int cc_register PROTO ((Rtx, Mmode));
2280 int dominant_cc_register PROTO ((Rtx, Mmode));
2281 int symbol_mentioned_p PROTO ((Rtx));
2282 int label_mentioned_p PROTO ((Rtx));
2283 Rcode minmax_code PROTO ((Rtx));
2284 int adjacent_mem_locations PROTO ((Rtx, Rtx));
2285 int load_multiple_operation PROTO ((Rtx, Mmode));
2286 int store_multiple_operation PROTO ((Rtx, Mmode));
2287 int load_multiple_sequence PROTO ((Rtx *, int, int *, int *,
2288 HOST_WIDE_INT *));
2289 char * emit_ldm_seq PROTO ((Rtx *, int));
2290 int store_multiple_sequence PROTO ((Rtx *, int, int *, int *,
2291 HOST_WIDE_INT *));
2292 char * emit_stm_seq PROTO ((Rtx *, int));
2293 int arm_valid_machine_decl_attribute PROTO ((Tree, Tree, Tree));
2294 Rtx arm_gen_load_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
2295 Rtx arm_gen_store_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
2296 int arm_gen_movstrqi PROTO ((Rtx *));
2297 Rtx gen_rotated_half_load PROTO ((Rtx));
2298 Mmode arm_select_cc_mode RTX_CODE_PROTO ((Rcode, Rtx, Rtx));
2299 Rtx gen_compare_reg RTX_CODE_PROTO ((Rcode, Rtx, Rtx, int));
2300 void arm_reload_in_hi PROTO ((Rtx *));
2301 void arm_reload_out_hi PROTO ((Rtx *));
2302 void arm_reorg PROTO ((Rtx));
2303 char * fp_immediate_constant PROTO ((Rtx));
2304 void print_multi_reg STDIO_PROTO ((FILE *, char *, int, int));
2305 char * output_call PROTO ((Rtx *));
2306 char * output_call_mem PROTO ((Rtx *));
2307 char * output_mov_long_double_fpu_from_arm PROTO ((Rtx *));
2308 char * output_mov_long_double_arm_from_fpu PROTO ((Rtx *));
2309 char * output_mov_long_double_arm_from_arm PROTO ((Rtx *));
2310 char * output_mov_double_fpu_from_arm PROTO ((Rtx *));
2311 char * output_mov_double_arm_from_fpu PROTO ((Rtx *));
2312 char * output_move_double PROTO ((Rtx *));
2313 char * output_mov_immediate PROTO ((Rtx *));
2314 char * output_add_immediate PROTO ((Rtx *));
2315 char * arithmetic_instr PROTO ((Rtx, int));
2316 void output_ascii_pseudo_op STDIO_PROTO ((FILE *, unsigned char *, int));
2317 char * output_return_instruction PROTO ((Rtx, int, int));
2318 int arm_volatile_func PROTO ((void));
2319 void arm_poke_function_name STDIO_PROTO ((FILE *, char *));
2320 void output_func_prologue STDIO_PROTO ((FILE *, int));
2321 void output_func_epilogue STDIO_PROTO ((FILE *, int));
2322 void arm_expand_prologue PROTO ((void));
2323 char * arm_output_epilogue PROTO ((void));
2324 void arm_print_operand STDIO_PROTO ((FILE *, Rtx, int));
2325 void arm_final_prescan_insn PROTO ((Rtx));
2326 int short_branch PROTO ((int, int));
2327 void assemble_align PROTO((int)); /* Used in arm.md, but defined in output.c */
2328 int multi_register_push PROTO ((Rtx, Mmode));
2329 #ifdef AOF_ASSEMBLER
2330 Rtx aof_pic_entry PROTO ((Rtx));
2331 void aof_dump_pic_table STDIO_PROTO ((FILE *));
2332 char * aof_text_section PROTO ((void));
2333 char * aof_data_section PROTO ((void));
2334 void aof_add_import PROTO ((char *));
2335 void aof_delete_import PROTO ((char *));
2336 void aof_dump_imports STDIO_PROTO ((FILE *));
2337 #endif
2338 #endif /* HAVE_CONFIG_H */
2339
2340 #endif /* __ARM_H__ */
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